US Pat. No. 10,170,636

GATE-TO-BULK SUBSTRATE ISOLATION IN GATE-ALL-AROUND DEVICES

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a fin including a first semiconductor material on a substrate, wherein the first semiconductor material includes silicon germanium having a first concentration of germanium in the silicon germanium;
a nanowire over the fin, the nanowire including a second semiconductor material, wherein the second semiconductor material includes silicon germanium having a second concentration of germanium in the silicon germanium; and
wherein the first concentration is at least 10% less than the second concentration;
a first layer of oxide material on exposed portions of the nanowire and a second layer of oxide material on the fin, the first layer of oxide material having a first thickness and the second layer of oxide material having a second thickness, where the first thickness is less than the second thickness; and
a gate stack over a channel region of the nanowire, the gate stack including a gate dielectric layer on the nanowire and directly on the second layer of oxide material, a workfunction metal on the gate dielectric layer, and a gate conductor on the workfunction metal.

US Pat. No. 10,170,635

SEMICONDUCTOR DEVICE, DISPLAY DEVICE, DISPLAY APPARATUS, AND SYSTEM

RICOH COMPANY, LTD., Tok...

1. A semiconductor device comprising:a base;
a gate electrode to which a gate voltage is applied;
a source electrode and a drain electrode through which an electric current is generated according to the gate voltage being applied to the gate electrode;
a semiconductor layer made of an oxide semiconductor;
a gate insulating layer inserted between the gate electrode and the semiconductor layer, wherein
the semiconductor layer includes a channel-forming region and a non-channel-forming region, each having
an insulating-layer-facing face facing the gate insulating layer, and
a base-facing face facing the base layer and opposite to the insulating-layer-facing face,
the channel-forming region is in contact with the source electrode and the drain electrode, and
the non-channel-forming region is in contact with the source electrode and the drain electrode.

US Pat. No. 10,170,634

WIRE-LAST GATE-ALL-AROUND NANOWIRE FET

INTERNATIONAL BUSINESS MA...

1. A nanowire field effect transistor (FET) device comprising:a first source/drain region and a second source/drain region, each on an upper surface of a bulk semiconductor substrate, the bulk semiconductor substrate including a single layer of semiconductor material extending from a base to the upper surface, the single layer excluding an insulator layer between the base and the upper surface;
a gate region interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate;
a plurality of nanowires only in the gate region, the nanowires suspended above the semiconductor substrate and defining gate channels of the nanowire FET device; and
a gate structure including a gate electrode in the gate region and sidewalls spacers on sidewalls of the gate electrode that directly contact the upper surface of the bulk semiconductor substrate, the gate electrode formed directly on the upper surface of the bulk semiconductor substrate and contacting an entire surface of each nanowire.

US Pat. No. 10,170,633

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:forming an oxide semiconductor film over a substrate;
forming a conductive film over the oxide semiconductor film;
heating the conductive film formed over the oxide semiconductor film;
forming a first resist mask over the conductive film;
etching the conductive film using the first resist mask to form a source electrode and a drain electrode;
forming a second resist mask over the oxide semiconductor film after etching the conductive film;
etching the oxide semiconductor film using the second resist mask,
forming a gate insulating film over the oxide semiconductor film; and
forming a gate electrode over the gate insulating film.

US Pat. No. 10,170,632

SEMICONDUCTOR DEVICE INCLUDING OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor including a first oxide semiconductor layer; and
a second transistor including a second oxide semiconductor layer,
wherein the second transistor includes a first gate electrode below the second oxide semiconductor layer and a second gate electrode above the second oxide semiconductor layer,
wherein the second oxide semiconductor layer includes a first region and a second region,
wherein the second region overlaps with a source or a drain electrode of the second transistor,
wherein a thickness of the first region is smaller than a thickness of the second region, and
wherein the first transistor is electrically connected to a pixel electrode, and the pixel electrode is formed using the same material as the second gate electrode.

US Pat. No. 10,170,631

MANUFACTURING METHODS OF OXIDE THIN FILM TRANSISTORS

Wuhan China Star Optoelec...

1. A manufacturing method of oxide thin film transistors (TFTs), comprising:providing a substrate and forming an oxide semiconductor active layer on the substrate;
depositing an insulation dielectric layer on the active layer;
applying an annealing process to components formed after the insulation dielectric layer is deposited;
wherein the insulation dielectric layer comprises at least SiOx thin layer directly connected to the active layer; and
wherein the insulation dielectric layer further comprises a SiNX thin layer deposited on the SiOx thin layer.

US Pat. No. 10,170,630

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device comprising:forming a transistor comprises a gate electrode;
forming a cylindrical semiconductor consisting of an oxide semiconductor on and in contact with the gate electrode;
forming a gate insulating film covering a side surface and a top surface of the cylindrical semiconductor; and
forming a first conductor covering the side surface of the cylindrical semiconductor with the gate insulating film therebetween.

US Pat. No. 10,170,629

FIELD-EFFECT TRANSISTOR AND THE MANUFACTURING METHOD

Shenzhen China Star Optoe...

1. A method for manufacturing a field-effect transistor, comprising:depositing a first insulating layer on a substrate;
forming a source electrode and a drain electrode on the first insulating layer;
forming a carbon quantum dots active layer covering the source electrode and the drain electrode; and
forming a second insulating layer and a gate electrode on the carbon quantum dots active layer sequentially;
wherein forming the carbon quantum dots active layer covering the source electrode and the drain electrode comprises:
dissolving the carbon quantum dots in octane to form a first mixed solution;
coating the first mixed solution on the first insulating layer, the source electrode and the drain electrode by a spin coating technology to form the carbon quantum dots film layer; and
vacuum baking the carbon quantum dots film to form the carbon quantum dots active layer covering the source electrode and the drain electrode;
wherein the first insulating layer depositing on a substrate further comprises:
forming a first material layer on the substrate by a chemical vapor deposition method, the first material layer is a silicon oxide layer, an alumina layer, a silicon nitride layer, or a mixed layer of silicon oxide, aluminum oxide and silicon nitride;
soaking and rinsing the first material layer with a second mixed solution; and
drying the first material layer after soaking and rinsing to form the first insulating layer.

US Pat. No. 10,170,628

METHOD FOR FORMING AN EXTREMELY THIN SILICON-ON-INSULATOR (ETSOI) DEVICE HAVING REDUCED PARASITIC CAPACITANCE AND CONTACT RESISTANCE DUE TO WRAP-AROUND STRUCTURE OF SOURCE/DRAIN REGIONS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, comprising:forming first spacers on sides of a gate structure and second spacers on the first spacers;
etching a semiconductor layer below the gate structure using the second spacers as a mask to protect portions of the semiconductor layer that extend beyond the gate structure;
forming undercuts in a buried dielectric layer below the semiconductor layer; and
epitaxially growing source and drain regions wrapped around the semiconductor layer from a top of the semiconductor layer and into the undercuts on an opposite side of the semiconductor layer.

US Pat. No. 10,170,627

NANOWIRE TRANSISTOR WITH SOURCE AND DRAIN INDUCED BY ELECTRICAL CONTACTS WITH NEGATIVE SCHOTTKY BARRIER HEIGHT

Acorn Technologies, Inc.,...

1. A nanowire transistor, comprising:a gate circumferentially surrounding and displaced from a semiconductor nanowire channel by an electrically insulating gate oxide, the semiconductor nanowire channel having no intentional doping;
a source at a first end of the nanowire channel, and a drain at a second end of the nanowire channel, the source and drain each comprising undoped semiconductor material; and
a first metal contact circumferentially surrounding the source and providing an electrically conductive path to the source, and a second metal contact circumferentially surrounding the drain and providing an electrically conductive path to the drain,
wherein the first metal contact electrostatically induces free charge carriers in the source, the first metal contact is separated from the gate by an insulating material layer or a gap, and the second metal contact is separated from the gate by an insulating material layer or a gap.

US Pat. No. 10,170,626

TRANSISTOR PANEL HAVING A GOOD INSULATION PROPERTY AND A MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A transistor panel, comprising:a channel region including a first oxide of a first metal;
a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source region and the drain region, and wherein the channel region is connected to the source region and the drain region;
an insulation layer disposed on the channel region;
an upper electrode disposed on the insulation layer;
an interlayer insulation layer disposed on the upper electrode, the source region and the drain region; and
a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source region and the drain region, wherein the first portion of the barrier layer contacts each of the source region and the drain region,
wherein the upper electrode and the barrier layer each comprise a second metal, and
the barrier layer does not overlap the upper electrode in a direction perpendicular to a top surface of the upper electrode.

US Pat. No. 10,170,625

METHOD FOR MANUFACTURING A COMPACT OTP/MTP TECHNOLOGY

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:providing a substrate having a buried oxide (BOX) layer formed over the substrate;
forming first and second fins on the BOX layer, wherein the second fin is arranged opposite the first fin on the BOX layer such that an end of the second fin is aligned to an end of the first fin with a gap in between;
forming first and second gates, laterally separated, over and perpendicular to the first and second fins, respectively;
forming at least one third gate between the first and second gates and contacting the BOX layer through the gap, each third gate overlapping an end of the first fin, the second fin, or both fins;
forming at least one additional pair of separated first and second fins parallel to and vertically spaced from the first and second fins;
extending the first and second gates over one or more of the additional first and second fins, respectively;
forming a source/drain (S/D) region in each of the first and second fins adjacent to the first and second gates, respectively, remote from the at least one third gate;
utilizing each of the first and second gates as a word line (WL);
utilizing each at least one third gate as a source line (SL) or connecting a SL to the S/D region; and
connecting a bit line (BL) to the S/D region or the at least one third gate.

US Pat. No. 10,170,624

NON-PLANAR TRANSISTOR

UNITED MICROELECTRONICS C...

1. A non-planar transistor, comprising:a fin structure disposed on a substrate, wherein the fin structure comprises an upper portion, a concave portion and a lower portion, and the concave portion is disposed between the upper portion and the lower portion;
a gate structure disposed on the fin structure;
a first spacer structure disposed on a sidewall of the gate structure, wherein the first spacer structure comprises a first spacer and a second spacer, the first spacer is disposed between the gate structure and the second spacer, and a height of the first spacer is different from a height of the second spacer;
a source/drain region disposed in a semiconductor layer at a side of the first spacer structure, wherein the material of the semiconductor layer is different from the material of the fin structure;
a shallow trench isolation (STI) surrounding the fin structure; and
a second spacer structure disposed on the shallow trench isolation, wherein a part of the semiconductor layer is disposed on the fin structure, and the second spacer structure comprises a third spacer and a fourth spacer, wherein the third spacer is disposed between the fourth spacer and the semiconductor layer on the fin structure, and the third spacer is disposed between the semiconductor layer and the shallow trench isolation, wherein a height of the third spacer is different from a height of the fourth spacer, and the semiconductor layer covers an outer sidewall of the third spacer in a cross-section.

US Pat. No. 10,170,623

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor device, comprising:providing a plurality of mandrels on a substrate, each of the mandrels spaced from each other on a planar surface of the substrate;
removing a portion of the mandrels and a portion of the substrate to form a trench across the mandrels, the trench having a bottom surface lower than the planar surface;
forming a plurality of spacers not sealing the whole trench formed on the planar surface of the substrate, the spacers only covering sidewalls of the mandrels and the trench;
after completely removing the mandrels, using the spacers as a mask to form a plurality of fin shaped structures on the substrate and a plurality of shallow trenches surrounding the fin shaped structures; and
removing a portion of the spacers to form a spacing layer on the sidewalls of the trench, wherein the spacing layer has a top surface being lower than a top surface of the fin shaped structures.

US Pat. No. 10,170,622

SEMICONDUCTOR DEVICE INCLUDING MOS TRANSISTOR HAVING SILICIDED SOURCE/DRAIN REGION AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit structure comprising:a semiconductor substrate;
a gate structure over the semiconductor substrate;
a spacer on a sidewall of the gate structure;
a silicon germanium region including a first silicon germanium region and a second silicon germanium region;
the first silicon germanium region being located in the substrate, and the first silicon germanium region having a first germanium percentage,
the second silicon germanium region lying over the first silicon germanium region, and the second silicon germanium region having a second germanium percentage higher than the first germanium percentage; and
a metal silicide region over the second silicon germanium region,
wherein the spacer has a side surface and bottom surface extending from a lower end of the side surface, the bottom surface of the spacer facing the substrate,
the silicon germanium region has an inclined surface,
one part of the inclined surface of the silicon germanium region intersects the side surface of the spacer at a level above the lower end of the side surface, and
another part of the inclined surface of the silicon germanium region intersects the bottom surface of the spacer at a second location spaced from the lower end of the side surface of the spacer in a direction towards the gate structure, such that the silicon germanium region contacts the spacer along both the side surface and the bottom surface of the spacer.

US Pat. No. 10,170,621

METHOD OF MAKING A TRANSISTOR HAVING A SOURCE AND A DRAIN OBTAINED BY RECRYSTALLIZATION OF SEMICONDUCTOR

1. Method of making a transistor, comprising:forming a gate and a first dielectric spacer in contact with the side walls of the gate, on a first region of a first layer that will form the transistor channel, the first layer being a crystalline semiconducting layer;
forming first portions of crystalline semiconductor on second regions of the first layer that will form part of the transistor source and drain;
making at least the second regions of the first layer amorphous and doping them;
recrystallizing at least the semiconductor in the second regions of the first layer and activating the dopants present at least in the semiconductor of the second regions of the first layer;
removing the first portions;
forming a second dielectric spacer in contact with the lateral walls of the gate such that the thickness of the second dielectric spacer is more than the thickness of the first dielectric spacer;
forming second portions of doped crystalline semiconductor on the second regions of the first layer such that at least said second portions and the second regions of the first layer together form the source and drain of the transistor.

US Pat. No. 10,170,620

SUBSTANTIALLY DEFECT FREE RELAXED HETEROGENEOUS SEMICONDUCTOR FINS ON BULK SUBSTRATES

International Business Ma...

1. A semiconductor structure comprising:a bulk semiconductor substrate of a first semiconductor material;
a plurality of spaced apart fin pedestal structures of a second semiconductor material located on said bulk semiconductor substrate of said first semiconductor material, wherein said second semiconductor material is different from said first semiconductor material;
a pair of spaced apart semiconductor fins of said second semiconductor material located on each fin pedestal structure, wherein one of said semiconductor fins of said pair of spaced apart semiconductor fins has a sidewall surface that is vertically aligned with a sidewall surface of a first end of each of said fin pedestal structures and another of said semiconductor fins of said pair of spaced apart semiconductor has a sidewall surface that is vertically aligned with a sidewall surface of a second end of each of said fin pedestal structures;
a first dielectric material structure located between each semiconductor fin of said pair of semiconductor fins, said first dielectric material structure is located on an exposed topmost surface of each of said fin pedestal structures; and
a second dielectric material structure located between each fin pedestal structure and present on said bulk semiconductor substrate, wherein said first and second dielectric material structures comprise a dielectric material having an upper undoped region and a lower doped region, and wherein said lower doped region of the first dielectric material structure has a topmost surface that is coplanar with a topmost surface of said lower doped region of said second dielectric material structure, and wherein said upper doped region of the first dielectric material structure has a topmost surface that is coplanar with a topmost surface of said upper doped region of said second dielectric material structure.

US Pat. No. 10,170,619

VERTICAL SCHOTTKY CONTACT FET

International Business Ma...

1. A semiconductor structure comprising:a vertical field effect transistor located above a substrate, said vertical field effect transistor comprising:
a bottom Schottky contact source/drain structure located directly on a surface of said substrate, said bottom Schottky contact source/drain structure comprises a base portion and a vertically extending portion;
a semiconductor channel region extending vertically upwards from a surface of said base portion of said bottom Schottky contact source/drain structure;
a top Schottky contact source/drain structure located on a topmost surface of said semiconductor channel region; and
a gate structure located on each side of said semiconductor channel region, wherein said vertically extending portion of said bottom Schottky contact source/drain structure has a topmost surface that is coplanar with a topmost surface of said top Schottky contact source/drain structure.

US Pat. No. 10,170,618

VERTICAL TRANSISTOR WITH REDUCED GATE-INDUCED-DRAIN-LEAKAGE CURRENT

International Business Ma...

14. A vertical transport fin field effect transistor, comprising:a bottom source/drain layer at the surface of the substrate;
one or more channels on the bottom source/drain layer, where the channels extend away from the bottom source/drain layer;
an extension region between each of the one or more channels and the bottom source/drain layer;
a gate structure on each of the one or more channels; and
a top source/drain segment on the top surface of each of the one or more channels, wherein either each of the top source/drain segments or the bottom source/drain layer has a bandgap in the range of about 1.0 eV to about 1.2 eV, and the other of the bottom source/drain layer or each of the top source/drain segments has a bandgap in the range of about 0.7 eV to about 0.9 eV.

US Pat. No. 10,170,617

VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

GLOBALFOUNDRIES, Grand C...

1. A structure, comprising:a vertical fin structure composed of semiconductor material and having a lower dopant region at a lower portion of the vertical fin structure, an upper dopant region at an upper portion of the vertical fin structure and a channel region between the lower dopant region and the upper dopant region;
a recessed portion in the semiconductor material adjacent to the lower dopant region at a lower portion of the vertical fin structure;
shallow trench isolation structures formed in the semiconductor material, adjacent to the recessed portion; and
doped semiconductor material in the recessed portion in the semiconductor material on sides of the vertical fin structure at the lower portion and adjacent to the shallow trench isolation structures, the lower dopant region being composed of the doped semiconductor material at the lower portion,
wherein the doped semiconductor material comprises a tri-layer of material within the recessed portion, with a higher doped semiconductor material in a lower portion and upper portion of the recessed portion, and a lower doped semiconductor material sandwiched therebetween.

US Pat. No. 10,170,616

METHODS OF FORMING A VERTICAL TRANSISTOR DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming a vertical transistor device, the method comprising:forming a plurality of layers of material above a bottom source/drain (S/D) layer of semiconductor material that is positioned above a semiconductor substrate, said plurality of layers including a bottom spacer layer of dielectric material positioned on said bottom source/drain (S/D) layer of semiconductor material, a sacrificial gate material layer positioned on said bottom spacer layer of dielectric material, a top spacer layer of dielectric material positioned on said sacrificial gate material layer, and a sacrificial layer of material positioned on said top spacer layer of material;
performing at least one etching process to define a cavity in said plurality of layers of material, wherein a portion of said bottom source/drain (S/D) layer of semiconductor material is exposed at a bottom of said cavity;
performing at least one epi deposition process to form a vertically oriented channel semiconductor structure on said bottom source/drain (S/D) layer of semiconductor material and in said cavity and a top source/drain (S/D) layer of semiconductor material above said vertically oriented channel semiconductor structure;
after performing said at least one epi deposition process, removing at least one of said plurality of layers of material to thereby expose an outer perimeter surface of said vertically oriented channel semiconductor structure; and
forming a gate structure around said exposed outer perimeter surface of said vertically oriented channel semiconductor structure.

US Pat. No. 10,170,615

SEMICONDUCTOR DEVICE INCLUDING A LATERAL TRANSISTOR

Infineon Technologies Aus...

1. A semiconductor device, comprising:a drift contact region;
a drain region of a first conductivity type, the drift contact region and the drain region being arranged in a first direction parallel to a first main surface of a semiconductor substrate;
a layer stack comprising a drift layer of the first conductivity type and a compensation layer of a second conductivity type, the drain region being electrically connected with the drift layer;
a body region of the second conductivity type;
a connection region of the second conductivity type extending from the first main surface of the semiconductor substrate and into the layer stack, the connection region being electrically connected with the compensation layer; and
a buried semiconductor portion beneath the layer stack and in electrical contact with the connection region,
wherein the buried semiconductor portion does not fully overlap with the drift layer,
wherein in the first direction, the layer stack is interposed between the drain region and the drift contact region and the drift contact region is interposed between the layer stack and the body region.

US Pat. No. 10,170,613

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first transistor disposed on the semiconductor substrate, the first transistor including:
a first semiconductor layer;
an active region in the first semiconductor layer; and
a first conductive layer underlying the first semiconductor layer; and
a second transistor disposed on the semiconductor substrate, the second transistor including:
a second semiconductor layer;
another active region in the second semiconductor layer; and
a second conductive layer underlying the second semiconductor layer and electrically isolated from the first conductive layer.

US Pat. No. 10,170,612

EPITAXIAL BUFFER LAYERS FOR GROUP III-N TRANSISTORS ON SILICON SUBSTRATES

Intel Corporation, Santa...

1. A semiconductor material stack, comprising:a silicon substrate having a first lattice constant;
a group III-N device layer disposed over the silicon substrate, the group III-N device layer having a second lattice constant different than the first lattice constant;
a buffer disposed between the silicon substrate and the group III-N device layer, wherein the buffer includes an AlxIn1-xN layer, with x being less than unity; a top barrier layer formed above the group III-N device layer;
N-type group III-N source and drain regions disposed on the top barrier layer;
a gate electrode disposed between the N-type group III-N source and drain regions, wherein the top barrier layer has a first thickness between the gate electrode and the group III-N device layer and a second, greater, thickness between the N-type group III-N source and drain regions and the group III-N device layer, and
a third thickness between a spacer region disposed between the gate electrode and each of the group III-N source and drain regions and the group III-N device layer, wherein the third thickness is intermediate to the first thickness and the second thickness and a gate dielectric disposed below the gate electrode and adjacent to sidewalls of the gate electrode.

US Pat. No. 10,170,611

T-GATE FIELD EFFECT TRANSISTOR WITH NON-LINEAR CHANNEL LAYER AND/OR GATE FOOT FACE

HRL Laboratories, LLC, M...

1. A high electron mobility transistor (HEMT) comprising:a source contact spaced apart from a drain contact by a distance in a first direction;
a gate disposed between the source and drain contacts extending in a second direction perpendicular to the first direction comprising a gate head and a gate foot;
a first surface and a second surface of a channel;
a top barrier layer forming a 2DEG in the channel, wherein a surface of the source contact contacts a first surface of the channel and a first surface of the top barrier layer, and a surface of the drain contact contacts a second surface of the channel and a second surface of the top barrier layer, the first surface and the second surface of the channel facing away from one another;
wherein the gate foot comprises a curved section, and a contour width of the gate foot is greater than a superficial width of the gate head,
the first and second surfaces of the channel having sections with curved shapes related to the shape of the curved section of the gate foot, and
the curved section of the gate foot does not include a straight section.

US Pat. No. 10,170,610

PSEUDOMORPHIC HIGH ELECTRON MOBILITY TRANSISTOR WITH LOW CONTACT RESISTANCE

QUALCOMM Incorporated, S...

1. A pseudomorphic high electron mobility transistor (pHEMT), comprising:a substrate layer;
a bottom barrier layer on the substrate layer;
a channel layer on the bottom barrier layer;
an upper barrier layer on the channel layer;
a source and a drain on the upper barrier layer, each having a cap layer, an Ohmic contact layer on the cap layer, and a metal contact layer on the Ohmic contact layer, wherein the Ohmic contact layer has a smaller bandgap than the cap layer and comprises InxGa1-xAs, wherein the value of x increases from the bottom of the Ohmic contact layer to the top of the Ohmic contact layer; and
a gate metal stack on the upper barrier layer.

US Pat. No. 10,170,609

INTERNAL SPACER FORMATION FROM SELECTIVE OXIDATION FOR FIN-FIRST WIRE-LAST REPLACEMENT GATE-ALL-AROUND NANOWIRE FET

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a nanowire field-effect transistor (FET) device, the method comprising:forming at least one stacked multi-semiconductor layer fin on an upper surface of a wafer, the at least one stacked multi-semiconductor layer fin including at least one semiconductor fin portion interposed between an opposing pair of sacrificial fin portions;
forming at least one dummy gate stack including a dummy gate on an upper surface of the at least one stacked multi-semiconductor layer fin;
etching the stacked multi-semiconductor layer fin while using the at least one dummy gate stack as a mask to preserve an underlying semiconductor fin portion and an underlying sacrificial fin portion and to expose sidewalls of the underlying sacrificial fin portions;
forming oxidized spacers on the sidewalls of the underlying sacrificial fin portions that are beneath the dummy gate;
after forming the oxidized spacers, epitaxially growing a semiconductor material laterally from exposed sidewalls of at least one of the underlying semiconductor fin portions to form replacement source/drain regions on opposing sides of the at least one stacked multi-semiconductor layer fin such that the oxidized spacers are interposed between the underlying sacrificial fin portions and the replacement source/drain regions;
removing the dummy gate after forming the oxidized spacers to form trenches that expose non-oxidized portions of the sacrificial fin portions and selectively etching the exposed non-oxidized portions of the sacrificial fin portions with respect to the oxidized spacers to form voids that define at least one nanowire of a nanowire FET device; and
utilizing the oxidized spacers to prohibit the voids from extending laterally beyond the oxidized spacers and into the replacement source/drain regions.

US Pat. No. 10,170,608

INTERNAL SPACER FORMATION FROM SELECTIVE OXIDATION FOR FIN-FIRST WIRE-LAST REPLACEMENT GATE-ALL-AROUND NANOWIRE FET

INTERNATIONAL BUSINESS MA...

1. A semiconductor device extending along a first direction to define a length, a second direction to define a width, and a third direction opposite the first and second directions to define a height, comprising:a first source/drain region and a second source/drain region, each on an upper surface of a wafer;
a gate region interposed between the first and second source/drain regions;
a plurality of nanowires, each nanowire having a first end anchored to the first source/drain region and an opposing second end anchored to the second source/drain region such that the at least one nanowire is suspended above the wafer in the gate region, the nanowire extending along the first direction to define a wire length and the second direction to define a wire width, the plurality of nanowires defining a stacked nanowire mesh including a first layer of nanowires interposed between the wafer and a second layer of nanowires;
at least one gate electrode in the gate region, the gate electrode extending along the second direction and contacting an entire surface of the at least one nanowire to define a gate-all-around configuration;
gate spacers on the sidewalls of the gate electrode, the gate spacers having a first thickness and extending along the second direction; and
at least one pair of oxidized spacers having a second thickness and surrounding the at least one gate electrode to electrically isolate the at least one gate electrode from the first and second source/drain regions, the at least one pair of oxidized spacers extending along the second direction parallel with the gate spacers and on sidewalls of the gate electrode beneath the gate spacers, the second thickness of the at least one pair of oxidized spacers being equal to the first thickness of the gate spacers,
wherein the first source/drain region and the second source/drain region are a single layer epitaxial material, and
wherein the first source/drain region includes a first raised replacement source/drain and the second source/drain region includes a second raised replacement source/drain, the first and second raised replacement source/drain regions formed directly against the first end of every nanowire among the plurality of nanowires and the at least one pair of oxidized spacers.

US Pat. No. 10,170,607

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprisinga semiconductor substrate including:
a first conductivity-type drift layer;
a second conductivity-type base layer disposed in a surface layer portion of the drift layer; and
a second conductivity-type collector layer and a first conductivity-type cathode layer disposed opposite to the base layer with respect to the drift layer, wherein
in the semiconductor substrate, a region operating as an IGBT element is referred to as an IGBT region, and a region operating as a diode element is referred to as a diode region, and the IGBT region and the diode region are alternately and repetitively arranged,
the IGBT region and the diode region are divided from each other by a boundary between the collector layer and the cathode layer,
the collector layer and the cathode layer extend in a direction along a surface of the semiconductor substrate, and the collector layer and the cathode layer are alternately and repetitively arranged in a direction orthogonal to the direction in which the collector layer and the cathode layer extend,
the collector layer is referred to as a first collector layer,
the semiconductor substrate further includes a second collector layer having a second conductivity-type impurity concentration higher than that of the first collector layer, at the surface of the semiconductor substrate along which the first collector layer and the cathode layer are disposed, and
the second collector layer is disposed between the first collector layer and the cathode layer, the second collector layer is located only at a position corresponding to a boundary between the IGBT region and the diode region, and the second collector layer is in contact with the cathode layer.

US Pat. No. 10,170,606

INSULATED GATE BIPOLAR TRANSISTOR AND DIODE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor layer having a first principal surface on one side thereof and a second principal surface on the other side thereof;
a channel region of a first conductivity type formed at a surface layer portion of the first principal surface of the semiconductor layer;
an emitter region of a second conductivity type formed at a surface layer portion of the channel region in the semiconductor layer;
a drift region of the second conductivity type formed in a region of the second principal surface side with respect to the channel region in the semiconductor layer so as to be electrically connected to the channel region;
a collector region of the first conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region;
a cathode region of the second conductivity type formed at a surface layer portion of the second principal surface of the semiconductor layer so as to be electrically connected to the drift region and including a line-shaped pattern continuously laid around, the line-shaped pattern including a pattern extending in a meandering form as viewed in plan; and
a gate electrode formed at the first principal surface side of the semiconductor layer so as to face the channel region across an insulating film.

US Pat. No. 10,170,605

MOS-BIPOLAR DEVICE

ECO SEMICONDUCTORS LIMITE...

1. A semiconductor device comprising a cluster of cells, wherein at least a portion of the cells comprise a base region of a first conductivity type having disposed therein at least one cathode region of a first and second conductivity type, the cathode regions being connected together through conductive contacts such that the cells are operative, and wherein at least a portion of the remaining cells comprise a base region of a first conductivity type and no cathode regions so that the remaining cathode regions are configured to be inoperative and designated as dummy cells; a first well region of a second conductivity type; a second well region of a first conductivity type; a drift region of a second conductivity type; an anode region of a first conductivity type; and an anode contact; in which each cell is disposed within the first well region and the first well region is disposed within the second well region; wherein the device comprises an elongate trench that longitudinally intersects the second well region and the drift region and laterally intersects the base region and the first and second well regions, the trench partially extending through a thickness of the second well region, wherein an insulating film is provided to substantially cover the inner surface of the trench and wherein a first gate is formed on the insulating film so as to substantially fill the trench; and in which the device is configured such that during operation of the device a depletion region at a junction between the base region and the first well region extends to a junction between the first well region and the second well region with increasing anode potential until the anode potential reaches a predetermined threshold potential so that the potential of the first well region is isolated from an increase in the potential of the anode contacts above the predetermined threshold.

US Pat. No. 10,170,604

METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS

ATOMERA INCORPORATED, Lo...

1. A method for making a semiconductor device comprising:forming at least one double-barrier resonant tunneling diode (DBRTD) by
forming a first doped semiconductor layer,
forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
forming a first intrinsic semiconductor layer on the first barrier layer,
forming a second barrier layer on the first intrinsic semiconductor layer and comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
forming a second intrinsic semiconductor layer on the second barrier layer,
forming a third barrier layer on the second intrinsic semiconductor layer and comprising a third superlattice, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
forming a third intrinsic semiconductor layer on the third barrier layer,
forming a fourth barrier layer on the third intrinsic semiconductor layer, and
forming a second doped semiconductor layer on the fourth barrier layer.

US Pat. No. 10,170,603

SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE WITH ELECTRON MEAN FREE PATH CONTROL LAYERS

ATOMERA INCORPORATED, Lo...

1. A semiconductor device comprising:at least one double-barrier resonant tunneling diode (DBRTD) comprising
a first doped semiconductor layer,
a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
a first intrinsic semiconductor layer on the first barrier layer,
a second barrier layer on the first intrinsic semiconductor layer and comprising a second superlattice, the second superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
a second intrinsic semiconductor layer on the second barrier layer,
a third barrier layer on the second intrinsic semiconductor layer and comprising a third superlattice, the third superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
a third intrinsic semiconductor layer on the third barrier layer,
a fourth barrier layer on the third intrinsic semiconductor layer, and
a second doped semiconductor layer on the fourth barrier layer.

US Pat. No. 10,170,602

SEMICONDUCTOR DEVICE WITH MULTIPLE HBTS HAVING DIFFERENT EMITTER BALLAST RESISTANCES

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a first no-contact HBT and a second no-contact HBT formed over a substrate, wherein the first no-contact HBT comprises a first lower cap over a first emitter, a first middle cap over the first lower cap, a first ballast resistor layer over the first middle cap, and a first upper cap over the first ballast resistor layer at a top portion of the first no-contact HBT, and the second no-contact HBT comprises a second lower cap over a second emitter, a second middle cap over the second lower cap, a second ballast resistor layer over the second middle cap, and a second upper cap over the second ballast resistor layer at a top portion of the second no-contact HBT;
removing the second upper cap and the second ballast resistor layer from the second no-contact HBT to form a second etched HBT; and
providing a first emitter contact to the first no-contact HBT to form a first HBT, wherein the first emitter contact is formed over the first upper cap, and providing a second emitter contact to the second etched HBT to form a second HBT, wherein the second emitter contact is formed over the second middle cap.

US Pat. No. 10,170,601

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE WITH BIPOLAR JUNCTION TRANSISTOR

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:a collector element formed in or over a semiconductor substrate;
a semiconductor element over the collector element, wherein the semiconductor element has a top surface, a bottom surface, and a side surface;
an emitter element over the top surface of the semiconductor element; and
a base element over the collector element and in direct contact with the side surface of the semiconductor element.

US Pat. No. 10,170,600

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A manufacturing method of a semiconductor device, comprising the steps of:forming a silicon layer over a substrate;
forming a resin layer over the silicon layer;
forming a transistor over the resin layer;
forming a conductive layer over the silicon layer and the resin layer; and
separating the substrate and the transistor from each other,
wherein the resin layer comprises an opening over the silicon layer,
wherein the conductive layer is in contact with the silicon layer through the opening of the resin layer, and
wherein in the step of separating the substrate and the transistor from each other, silicon contained in the silicon layer and metal contained in the conductive layer react with each other by irradiation of the silicon layer with light to form a metal silicide layer.

US Pat. No. 10,170,599

SEMICONDUCTOR DEVICE INCLUDING INSULATING FILMS WITH DIFFERENT THICKNESSES AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film over a substrate;
forming a first oxide insulating film over and in contact with the oxide semiconductor film, in an apparatus and by chemical vapor deposition in a first atmosphere, and with a first radio-frequency power supplied to an electrode of the apparatus; and
forming a second oxide insulating film over and in contact with the first oxide insulating film, in the apparatus and by chemical vapor deposition in a second atmosphere, and with a second radio-frequency power supplied to the electrode of the apparatus,
wherein the first radio-frequency power is lower than the second radio-frequency power,
wherein the first oxide insulating film is formed thinner than the second oxide insulating film, and a thickness of the first oxide insulating film is less than or equal to 50 nm, and
wherein spin densities of the first oxide insulating film measured by electron spin resonance are less than or equal to a lower limit of detection at a g-factor of 2.001.

US Pat. No. 10,170,598

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming an oxynitride semiconductor layer over an oxide insulating layer formed over an insulating surface;
forming a gate insulating layer over the oxynitride semiconductor layer; and
forming a gate electrode over the gate insulating layer,
wherein the oxynitride semiconductor layer includes a channel region, a source region, and a drain region,
wherein an amount of oxygen released by the oxide insulating layer in thermal desorption spectroscopy is greater than or equal to 1.0×1020 atoms/cm3, and
wherein the oxynitride semiconductor layer is an n-type semiconductor layer.

US Pat. No. 10,170,597

METHOD FOR FORMING FLASH MEMORY UNIT

Integrated Silicon Soluti...

1. A method for forming flash memory units, each of the flash memory units comprising a select gate PMOS transistor and a control gate PMOS transistor, the method comprising the steps of:providing a P-type substrate and forming an N-type well in the P-type substrate, wherein the N-type well comprises a plurality of flash memory unit areas each comprising a select gate PMOS transistor area and a control gate PMOS transistor area;
forming a channel area, a gate oxide layer, an N-type floating gate and an insulating layer sequentially for the select gate PMOS transistor and the control gate PMOS transistor in the flash memory unit area;
etching a part or all of the insulating layer in the select gate PMOS transistor area, and forming a logic gate on the etched insulating layer in the flash memory unit area;
implanting P-type impurities into the logic gate in the flash memory unit area, wherein a doping concentration of the logic gate is larger than a doping concentration of the N-type floating gate;
separating the logic gate in the select gate PMOS transistor area from the logic gate in the control gate PMOS transistor area by etching;
diffusing the P-type impurities in the logic gate in the select gate PMOS transistor area to the N-type floating gate in the select gate PMOS transistor area using a heating process, such that the N-type floating gate in the select gate PMOS transistor area changes to a P-type floating gate; and
forming electrodes for the select gate PMOS transistor and the control gate PMOS transistor.

US Pat. No. 10,170,596

FABRICATION OF AN ISOLATED DUMMY FIN BETWEEN ACTIVE VERTICAL FINS WITH TIGHT FIN PITCH

International Business Ma...

1. An arrangement of active and inactive fins on a substrate, comprising:a substrate;
a pair of vertical fins on the substrate;
an inactive vertical fin on the substrate between the pair of vertical fins, wherein the inactive vertical fin includes a lower portion made of a semiconductor material and an upper portion made of an insulating material;
a protective liner on a lower portion of each of the pair of vertical fins and the lower portion of the inactive vertical fin; and
a filler layer on the protective liner and the substrate, wherein a top surface of the filler layer is above the protective liner and the lower portion of the inactive vertical fin made of the semiconductor material.

US Pat. No. 10,170,594

PUNCH THROUGH STOPPER IN BULK FINFET DEVICE

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device comprising:forming a gate structure on a channel region portion of a fin structure after forming an isolation region;
forming a spacer on the gate structure;
exposing a lower portion of a sidewall of the fin structure;
forming a doped material on the lower portion of the fin structure, wherein said forming the doped material on the exposed lower portion of the sidewall of the fin structure comprises epitaxial deposition of a semiconductor material that is in situ doped with an n-type or p-type dopant; and
diffusing dopant from the doped material to a base portion of the fin structure.

US Pat. No. 10,170,593

THRESHOLD VOLTAGE MODULATION THROUGH CHANNEL LENGTH ADJUSTMENT

International Business Ma...

1. A method of forming an arrangement of long fin and short fin devices on a substrate, comprising:forming a plurality of long fins on the substrate;
forming a plurality of short fins on the substrate, wherein the short fins are shorter than the long fins;
forming a first active gate across the plurality of long fins;
forming a second active gate across the plurality of short fins, wherein at least one of the plurality of long fins is adjacent to at least one of the plurality of short fins; and
forming at least two dummy gates across the plurality of long fins.

US Pat. No. 10,170,592

INTEGRATED CIRCUIT STRUCTURE WITH SUBSTRATE ISOLATION AND UN-DOPED CHANNEL

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a circuit device, the method comprising:receiving a substrate having a first semiconductor layer of a first semiconductor material and a second semiconductor layer of a second semiconductor material on the first semiconductor layer, wherein the second semiconductor material is different from the first semiconductor material in composition;
patterning the first semiconductor layer, the second semiconductor layer, and the substrate to form a fin structure that includes the first semiconductor layer, the second semiconductor layer, and a patterned portion of the substrate; and
performing a selective oxidization process to the first semiconductor layer, such that a bottom portion of the first semiconductor layer is fully oxidized while a top portion of the first semiconductor layer directly above the oxidized bottom portion and the patterned portion of the substrate directly below the oxidized bottom portion remain un-oxidized.

US Pat. No. 10,170,591

SELF-ALIGNED FINFET FORMATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, the method comprising:forming a first hardmask on a semiconductor substrate;
forming a planarizing layer on the first hardmask;
forming a second hardmask on the planarizing layer;
removing portions of the second hardmask;
forming alternating blocks of a first material and a second material over the second hardmask;
removing the blocks of the second material to expose portions of the planarizing layer;
removing exposed portions of the planarizing layer to expose portions of the first hardmask and removing portions of the first hardmask to expose portions of the semiconductor substrate;
removing exposed portions of the semiconductor substrate to form a first fin and a second fin, wherein the first fin is arranged under a portion of the planarizing layer;
further removing exposed portions of the semiconductor substrate to further increase the height of the first fin and substantially remove the second fin; and
forming a gate stack over a channel region of the first fin;
wherein the planarizing layer includes an organic planarizing material;
wherein the second hardmask includes a first layer arranged on the planarizing layer, a second layer arranged on the first layer, and a third layer arranged on the second layer; and
wherein a layer of the first material is deposited over portions of the first layer of the second hardmask prior to forming the alternating blocks of the first material and the second material.

US Pat. No. 10,170,590

VERTICAL FIELD EFFECT TRANSISTORS WITH UNIFORM THRESHOLD VOLTAGE

INTERNATIONAL BUSINESS MA...

9. A semiconductor structure, comprising:semiconductor fins on a substrate, the semiconductor fins being arranged in a direction;
a spacer layer between the semiconductor fins, the spacer layer being on a surface of the substrate upon which the semiconductor fins are formed;
a high dielectric constant layer, wherein a first portion of the high dielectric constant layer is on sidewalls of the semiconductor fins, and a second portion of the high dielectric constant layer is over the spacer layer;
a work function metal layer on sidewalls of the semiconductor fins and on the high dielectric constant layer, a thickness of the work function metal layer in the direction being uniform; and
a top spacer layer, wherein the top spacer layer is on a portion of the low resistance metal layer, a portion of the work function metal layer, and a portion of the high-dielectric constant layer.

US Pat. No. 10,170,589

VERTICAL POWER MOSFET AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor region;
a gate dielectric over the semiconductor region;
a gate electrode over the gate dielectric;
a drain region and a source region at a top surface of the semiconductor region and adjacent to the gate electrode;
a gate spacer on a sidewall of the gate electrode;
a dielectric layer over the gate electrode and the gate spacer, wherein the dielectric layer comprises a portion, with the portion comprising a first sidewall contacting the gate spacer, and a second sidewall opposite to the first sidewall;
a deep metal via in the semiconductor region, wherein an edge of the deep metal via is aligned to the second sidewall of the portion of the dielectric layer;
a source electrode underlying the semiconductor region, wherein the source electrode is electrically shorted to the source region through the deep metal via; and
a Metal-Oxide-Semiconductor (MOS) device selected from the group consisting essentially of a low-voltage MOSFET and a high-side MOSFET formed at a top surface of the semiconductor region, wherein the MOSFET comprises an additional source region and an additional drain region at the top surface of the semiconductor region, and the source electrode extends directly underlying, and is electrically decoupled from, the additional source region and the additional drain region.

US Pat. No. 10,170,588

METHOD OF FORMING VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTOR WITH HIGH-K DIELECTRIC FEATURE UNIFORMITY

International Business Ma...

1. A method of forming a vertical transport fin field effect transistor, comprising:forming a doped layer on a substrate;
forming a multilayer fin on the doped layer, wherein the multilayer fin includes a lower trim layer portion, an upper trim layer portion, and a fin channel portion between the lower trim layer portion and the upper trim layer portion;
removing a portion of the lower trim layer portion to form a lower trim layer post;
removing a portion of the upper trim layer portion to form an upper trim layer post;
forming an upper recess filler adjacent to the upper trim layer post, and a lower recess filler adjacent to the lower trim layer post; and
removing a portion of the fin channel portion to form a fin channel post between the upper trim layer post and lower trim layer post.

US Pat. No. 10,170,587

HETEROGENEOUS SOURCE DRAIN REGION AND EXTENSION REGION

International Business Ma...

1. A semiconductor device fabrication process comprising:forming a sacrificial portion upon a substrate;
forming a sacrificial gate stack upon the sacrificial portion;
forming a sacrificial gate spacer upon the sacrificial portion against the sacrificial gate;
forming a source drain region of a first doped material upon the substrate against the gate spacer;
removing the sacrificial gate stack forming a replacement gate trench;
forming an extension trench between the sacrificial gate spacer and the substrate by removing the sacrificial portion accessible via the replacement gate trench;
forming an extension region of a second doped material that has a higher mobility relative to the first doped material within the extension trench against the sacrificial gate spacer and against the substrate;
removing the sacrificial gate spacer; and
forming a replacement gate spacer upon the extension region.

US Pat. No. 10,170,586

UNIPOLAR SPACER FORMATION FOR FINFETS

International Business Ma...

1. A method for forming a spacer for a semiconductor device, comprising:depositing a dummy spacer layer over surfaces of gate structures and fins, the gate structures being transversely orientated relative to the fins;
planarizing a dielectric fill formed over the gate structures and the fins to remove a portion of the dummy spacer layer formed on tops of the gate structures and expose the dummy spacer layer at tops of sidewalls of the gate structures;
forming channels by removing the dummy spacer layer along the sidewalls of the gate structures, the fins being protected by the dielectric fill;
forming a spacer by filling the channels with a spacer material; and
removing the dielectric fill and the dummy spacer layer to expose the tins.

US Pat. No. 10,170,585

SEMICONDUCTOR DEVICES HAVING EQUAL THICKNESS GATE SPACERS

International Business Ma...

1. A method of forming equal thickness gate spacers for PFET (p-type field effect transistor) and NFET (n-type field effect transistor) devices, the method comprising:depositing at least a first dielectric layer to pinch-off space between gates;
recessing the first dielectric layer such that a first gate hard mask is exposed;
depositing a first conformal atomic layer deposition (ALD) layer or depositing a first directed self-assembly (DSA) layer adjacent gate masks of the PFET and NFET devices;
masking the NFET device and etching the first dielectric layer in a PFET region using the first ALD layer or the first DSA layer as a mask to form a PFET spacer;
forming PFET epi growth regions;
depositing a first nitride liner and a first inter-level dielectric (ILD) over the PFET and NFET devices;
recessing the ILD and the nitride liner to reveal a second gate hard mask;
depositing a second conformal ALD layer or depositing a second DSA layer adjacent the gate masks of the PFET and NFET devices;
masking the PFET device and etching the first dielectric layer in NFET region using the second ALD layer or the second DSA layer as a mask to form an NFET spacer;
forming NFET epi growth regions;
depositing a second nitride liner and a second inter-level dielectric (ILD) over the PFET and NFET devices; and
removing the gate masks of the PFET and NFET devices to form high-k metal gates (HKMGs) between the PFET and NFET epi growth regions.

US Pat. No. 10,170,584

NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS

International Business Ma...

1. A method of forming a nanosheet device, comprising:forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer;
forming a stack cover layer on at least a portion of the channel stack, wherein the stack cover layer is formed on at least a portion of exposed sides of the at least one nanosheet channel layer and the at least one sacrificial release layer;
forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate;
removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib; and
forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.

US Pat. No. 10,170,583

FORMING A GATE CONTACT IN THE ACTIVE AREA

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:patterning a fin in a substrate;
forming a gate between source/drain regions over the substrate, the gate having a dielectric spacer along a sidewall;
removing a portion of the dielectric spacer and filling with a metal oxide to form a spacer, the spacer having a first spacer portion and a second spacer portion;
recessing the gate and depositing a dielectric cap over the gate;
forming a source/drain contact over at least one of the source/drain regions, the source/drain contact contacting the spacer and the dielectric spacer;
forming a via contact over the source/drain contact; and
removing the dielectric cap and forming a gate contact over the gate, the gate contact having a first gate contact portion contacting the gate and a second gate contact portion positioned over the first gate contact portion, the second gate contact portion being wider than the first gate contact portion;
wherein the first spacer portion and the second spacer portion comprise different materials, the first spacer portion lines sidewalls of the gate and extends to a height that is over the gate, and directly contacts the first gate contact portion and the source/drain contact, and the second spacer portion is arranged directly on top of the first spacer portion, directly beneath an overhanging portion of the second gate contact portion, and directly in contact with the source/drain contact.

US Pat. No. 10,170,582

UNIFORM BOTTOM SPACER FOR VERTICAL FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:forming a protective liner above and in direct contact with a semiconductor substrate, a fin extending upward from the semiconductor substrate and a nitride-oxide-nitride hardmask positioned on top of the fin, wherein the protective liner comprises a metal oxide material;
removing the protective liner from a top surface of the semiconductor substrate and a top surface of the nitride-oxide-nitride hardmask, wherein the protective liner remains on sidewalls of the fin and the nitride-oxide-nitride hardmask;
forming a first dielectric layer above and in direct contact with the semiconductor substrate, the protective liner and the top surface of the nitride-oxide-nitride hardmask;
simultaneously removing top portions of the first dielectric layer and the nitride-oxide-nitride hardmask, wherein the first dielectric layer remains in direct contact with a bottom portion of the protective liner and the semiconductor substrate;
removing the protective liner from the semiconductor structure, wherein removing the protective liner creates an opening between the first dielectric layer and the bottom portion of the fin; and
forming a second dielectric layer, the second dielectric layer fills the opening between the first dielectric layer and the bottom portion of the fin.

US Pat. No. 10,170,581

FINFET WITH REDUCED PARASITIC CAPACITANCE

International Business Ma...

1. A method of fabricating a finFET semiconductor device, the method comprising:forming a dummy gate above and perpendicular to semiconductor fins;
forming sidewall spacers on opposite sides of the dummy gate;
covering exposed portions of the semiconductor fins not covered by the dummy gate or the sidewall spacers with a dummy dielectric material;
forming an isolation region adjacent to and in direct contact with the dummy dielectric material, an upper surface of the isolation region is substantially flush with an upper surface of the dummy dielectric material;
replacing the dummy gate with a metal gate electrode covered by a dielectric gate cap;
replacing the dummy dielectric material with a self-aligned silicide contact, the self-aligned silicide contact being adjacent to and in direct contact with the sidewall spacers which separates it from the metal gate electrode, wherein the dummy dielectric material is removed selective to the isolation region, the sidewall spacers, and the dielectric gate cap;
forming a blanket metal layer on top of both the metal gate electrode and the self-aligned silicide contact, the blanket metal layer being in direct contact with the self-aligned silicide contact but physically isolated from the metal gate electrode by the dielectric gate cap;
patterning the blanket metal layer to form a source-drain contact;
removing excess material from the self-aligned silicide contact by recessing all of the self-aligned silicide contact except for a portion directly beneath the source-drain contact, wherein after recessing the self-aligned silicide contact has a stepped profile, the stepped profile comprising at least a first upper surface and a second upper surface, the first upper surface being in direct contact with the source-drain contact and above the second upper surface;
depositing an interlevel dielectric layer directly on top of the isolation region, the gate cap, and the second upper surface of the self-aligned silicide contact;
forming an opening in the interlevel dielectric and the gate cap to expose an upper surface of the metal gate electrode; and
forming a gate contact within the opening above and in direct contact with the metal gate electrode.

US Pat. No. 10,170,580

STRUCTURE OF GAN-BASED TRANSISTOR AND METHOD OF FABRICATING THE SAME

INDUSTRIAL TECHNOLOGY RES...

1. A GaN-based transistor device, comprising:a substrate;
a buffer layer, disposed on the substrate;
a channel layer, disposed on the buffer layer;
a barrier layer, disposed on a part of the channel layer;
a passivation layer, disposed on the barrier layer, wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall, and the first side wall and the second side wall are corresponding to each other;
a barrier metal layer, disposed on the passivation layer, wherein the barrier metal layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening to expose a part of the barrier layer;
a gate electrode, disposed on the exposed part of the barrier layer;
a source electrode, disposed on the channel layer, wherein the source electrode covers the first side wall and a part of the barrier metal layer adjacent to the first side wall; and
a drain electrode, disposed on the channel layer, wherein the drain electrode covers the second side wall and another part of the barrier metal layer adjacent to the second side wall;
wherein the gate electrode is disposed between the source electrode and the drain electrode; wherein an interface between the source electrode and the channel layer is an Ohmic contact; wherein an interface between the drain electrode and the channel layer is another Ohmic contact; wherein an interface between the gate electrode and the barrier layer is a Schottky contact.

US Pat. No. 10,170,579

SURFACE TREATMENT AND PASSIVATION FOR HIGH ELECTRON MOBILITY TRANSISTORS

TAIWAN SEMICONDUCTOR MANU...

1. A High Electron Mobility Transistor (HEMT), comprising:a first III-V compound layer having a first band gap;
a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap;
a first oxide layer over the second III-V compound layer;
a first interfacial layer over the first oxide layer, wherein the first interfacial layer comprises a crystalline semiconductor material; and
a passivation layer over the first interfacial layer.

US Pat. No. 10,170,578

THROUGH-SUBSTRATE VIA POWER GATING AND DELIVERY BIPOLAR TRANSISTOR

International Business Ma...

1. A semiconductor substrate, comprising:a through-substrate via (TSV) comprising:
a sidewall insulator defining an outer boundary of the TSV, and
a bipolar junction transistor disposed within the sidewall insulator, the bipolar junction transistor comprising:
a first semiconductor layer doped with a first-type of dopant, wherein the first semiconductor layer comprises a collector,
a second semiconductor layer doped with a second-type of dopant, wherein the second semiconductor layer comprises a base, and
a third semiconductor layer doped with the first-type of dopant, wherein the third semiconductor layer comprises an emitter, and wherein the first, second, and third semiconductor layers are arranged in the TSV to form one of: a PNP junction and an NPN junction, wherein the base is disposed between the collector and the emitter in the TSV, wherein a material of the collector forms an annular shape, wherein a base contact is disposed in a central opening of the annular shape, wherein the base contact comprises a conductive material that directly contacts the base in the second semiconductor layer.

US Pat. No. 10,170,577

VERTICAL TRANSPORT FETS HAVING A GRADIENT THRESHOLD VOLTAGE

International Business Ma...

1. A semiconductor structure comprising:at least one semiconductor fin present in a device region and extending upwards from a surface of a base semiconductor substrate;
a bottom source/drain structure located on the base semiconductor substrate and contacting sidewall surfaces of a lower portion of the at least one semiconductor fin, wherein the bottom source/drain structure serves as a drain region;
a gate dielectric layer located above the bottom source/drain structure and contacting another portion of the sidewall surfaces of the at least one semiconductor fin;
a gate structure located laterally adjacent a sidewall of the gate dielectric layer, the gate structure comprising a TiN liner having a first threshold voltage and a TiN portion having a second threshold voltage that is greater than the first threshold voltage; and
a top source/drain structure located on an upper portion of the at least one semiconductor fin, wherein the top source/drain structure serves as a source region.

US Pat. No. 10,170,576

STABLE WORK FUNCTION FOR NARROW-PITCH DEVICES

International Business Ma...

1. A method for forming a gate structure for a field effect transistor, comprising:forming a gate dielectric layer over and between a plurality of fins;
depositing a single diffusion prevention layer on the gate dielectric layer over and between the plurality of fins; and
depositing an oxygen affinity layer on the diffusion prevention layer by pinching off portions of the oxygen affinity layer within the diffusion prevention layer to merge the portions without intervening layers between the portions.

US Pat. No. 10,170,575

VERTICAL TRANSISTORS WITH BURIED METAL SILICIDE BOTTOM CONTACT

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a material stack including a surface semiconductor layer present on a metal semiconductor alloy layer;
a first of a source region or a drain region present in the surface semiconductor layer, the surface semiconductor layer including the first of the source or the drain region having a first portion that extends continuously across an entirety of a width of the semiconductor device, and a second portion that has a pedestal geometry that does not extend the entirety of the width of the semiconductor device;
a vertically orientated channel having a first end contacting and aligned with the second portion of the surface semiconductor layer that has the pedestal geometry;
a gate structure in direct contact with the vertically orientated channel;
a second of the source region or the drain region present at a second end of the vertically oriented channel that is opposite said first end of the vertically orientated channel; and
a via contact in electrical communication with the metal semiconductor alloy layer providing a contact to said first of said source region or said drain region of the semiconductor device, wherein the metal semiconductor alloy layer extends continuously across the entirety of the width of the semiconductor device including being present directly underlying a portion of the surface semiconductor layer that is present directly underlying an entirety of the vertically , orientated channel.

US Pat. No. 10,170,574

HYBRID SOURCE AND DRAIN CONTACT FORMATION USING METAL LINER AND METAL INSULATOR SEMICONDUCTOR CONTACTS

INTERNATIONAL BUSINESS MA...

1. A method of forming contacts to an electrical device comprising:providing a first via to a first semiconductor device comprising at least one of a silicon and germanium containing source and drain region and providing a second via to a second semiconductor device comprising at least one of a silicon containing source and drain region;
forming a material stack in the first and second via, the first material stack comprising a first metal layer and a second metal layer;
converting the second metal layer of the first material stack within the second via to a second metal oxide;
removing the second metal oxide with an etch that is selective to the first metal layer; and
converting the first metal layer present in the second via to first metal oxide with an oxidation anneal, wherein during said oxidation anneal the second metal layer in the first via alloys with the first metal layer and silicon from the silicon and germanium containing source and drain region to provide a binary metal semiconductor alloy.

US Pat. No. 10,170,573

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate;
a metal gate on the substrate, wherein the metal gate comprises a tungsten layer protruding from the top surface of the metal gate;
a first inter-layer dielectric (ILD) layer around the metal gate, wherein a top surface of the metal gate is lower than a top surface of the ILD layer thereby forming a recessed region atop the metal gate, wherein the recessed region is separated by the tungsten layer into a first sub-region and a second sub-region;
a mask layer in the recessed region;
a first void in the mask layer within the first sub-region of the recessed region;
a second void in the mask layer within the second sub-region of the recessed region;
a second inter-layer dielectric (ILD) layer on the mask layer and the first ILD layer;
a contact hole extending into the second ILD layer and the mask layer, wherein the contact hole exposes the top surface of the metal gate and communicates with the first and second voids; and
a conductive layer disposed in the contact hole and the first and second voids.

US Pat. No. 10,170,571

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a composite gate structure formed over a semiconductor substrate, wherein the composite gate structure comprises:
a gate dielectric layer;
a metal layer disposed on the gate dielectric layer; and
a semiconductor layer disposed on the gate dielectric layer, wherein the metal layer and the semiconductor layer are stacked on the gate dielectric layer side by side.

US Pat. No. 10,170,570

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a plurality of electrodes, extending in a first direction and a second direction orthogonal to the first direction, and stacked one over the other with an insulating layer disposed between each adjacent electrode;
the plurality of electrodes including a first side, and a second side, each extending in the second direction and spaced from each other in the first direction;
a plurality of protrusion portions extending from the first side of at least two of the electrodes, the protrusion portions spaced from one another in the second direction;
an extraction portion extending from the second side of the electrode on the at least two electrodes having protrusion portions extending from the first side thereof; and
first and second contact plugs extending in a third direction, orthogonal to the first and second directions, one of each contacting the extraction portions connected to one of the two electrodes having protrusion portions extending from the first side thereof,
wherein the extraction portion extending from the uppermost of the two electrodes having protrusion portions extending from the first side thereof is located closer to the center of the second side in the second direction, than the location of the extraction portion extending from the lowermost of the two electrodes having protrusion portions extending from the first side thereof.

US Pat. No. 10,170,569

THIN FILM TRANSISTOR FABRICATION UTLIZING AN INTERFACE LAYER ON A METAL ELECTRODE LAYER

APPLIED MATERIALS, INC., ...

1. A thin film transistor structure, comprising:a metal electrode layer disposed on a barrier layer formed above a gate insulating material;
an interface layer disposed on and in direct contact with the metal electrode layer, wherein the interface layer is an oxygen free dielectric material sized to be formed on and to have the same width as the metal electrode layer; and
an inorganic insulating material layer disposed on and in direct contact with the interface layer, wherein the inorganic insulating material layer is an oxygen containing dielectric layer.

US Pat. No. 10,170,568

HIGH VOLTAGE LATERALLY DIFFUSED MOSFET WITH BURIED FIELD SHIELD AND METHOD TO FABRICATE SAME

International Business Ma...

1. A method to fabricate laterally diffused MOSFETs comprising:providing a semiconductor substrate having disposed over a top surface thereof a bottom surface of an n-type layer;
forming a recess in a top surface of the n-type layer;
forming in the recess an electrically conductive field shield member covered completely with a dielectric material;
epitaxially growing in vertical and lateral directions from the top surface of the n-type layer additional n-type semiconductor material so as to completely bury the electrically conductive field shield member and dielectric material, where the n-type layer and the additional n-type semiconductor material are doped for forming an n-type drift region;
forming, in the n-type drift region, a p-type body region overlying the buried electrically conductive field shield member and dielectric material and forming first and second n+ drain regions;
forming, in the p-type body region, first and second n+ source regions and a p+ body contact region overlying the buried electrically conductive field shield member and dielectric material;
depositing first and second gate dielectrics and gate electrodes so as to overly a portion of the p-type body region and the n-type drift region, where a first gate electrode is disposed on the first gate dielectric associated with a first laterally diffused MOSFET and where a second gate electrode is disposed on the second gate dielectric associated with a second laterally diffused MOSFET; and
providing a plurality of additional field shields, where one of the additional field shields is disposed on the first gate dielectric in proximity to the first gate electrode and a first portion of the n-type drift region, and where another one of the additional field shields is disposed on the second gate dielectric in proximity to the second gate electrode and overlying a second portion of the n-type drift region;
where the p+ body contact region is formed by implanting p-type dopant atoms into a region of the n-type drift region where two growth fronts, formed during the step of epitaxially growing in the lateral direction the additional n-type semiconductor material, meet and grow together.

US Pat. No. 10,170,566

SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD FOR MANUFACTURING THE SAME, MEMORY CELL HAVING THE SAME AND ELECTRONIC DEVICE HAVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a semiconductor substrate having a plurality of active regions and a device isolation region for isolating the plurality of active regions from each other;
a buried bit line and a buried gate electrode which are formed in the semiconductor substrate;
a gate trench having a bottom surface, a first side surface and a second side surface opposite to the first side surface, wherein the buried gate electrode is embedded in the gate trench,
wherein the device isolation region includes a first device isolation region extending in a first direction and a second device isolation region extending in a second direction crossing with the first direction and having a conductive shield pillar,
wherein the conductive shield pillar has a height that overlaps a portion of the buried gate electrode and the buried bit line,
wherein a top surface of the conductive shield pillar being at a higher level than a bottom surface of the buried gate electrode, and
wherein a bottom surface of the conductive shield pillar being at lower level than a bottom surface of the buried bit line.

US Pat. No. 10,170,565

IMAGING DEVICE, METHOD FOR DRIVING IMAGING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. An imaging device comprising:a photoelectric conversion element;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor; and
a first capacitor,
wherein one terminal of the photoelectric conversion element is directly connected to one of a source electrode and a drain electrode of the first transistor,
wherein the other terminal of the photoelectric conversion element is directly connected to a first power supply line,
wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the sixth transistor,
wherein the other of the source electrode and the drain electrode of the first transistor is directly connected to one terminal of the first capacitor,
wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to the other terminal of the first capacitor,
wherein the one of the source electrode and the drain electrode of the third transistor is electrically connected to a gate electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is electrically connected to one of a source electrode and a drain electrode of the fourth transistor,
wherein the other of the source electrode and the drain electrode of the third transistor is directly connected to one of a source electrode and a drain electrode of the fifth transistor,
wherein the gate electrode of the fourth transistor is directly connected to the other terminal of the first capacitor,
wherein the other of the source electrode and the drain electrode of the fifth transistor is directly connected to a second power supply line, and
wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor.

US Pat. No. 10,170,564

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A manufacturing method of a semiconductor device including a vertical MOSFET having a planar gate, the manufacturing method of a semiconductor device comprising:forming an n-type gallium nitride layer on a gallium nitride monocrystalline substrate having a threading dislocation density of less than 1E+7 cm?2; and
forming an impurity-implanted region that contains impurities at a uniform concentration in a direction parallel to a main surface of the gallium nitride monocrystalline substrate, by ion-implanting the impurities into the n-type gallium nitride layer, the impurities including at least one element selected from among magnesium, beryllium, calcium and zinc, wherein
at least part of the impurity-implanted region serves as a channel forming region of the vertical MOSFET.

US Pat. No. 10,170,563

GALLIUM NITRIDE SEMICONDUCTOR DEVICE WITH IMPROVED TERMINATION SCHEME

Alpha and Omega Semicondu...

1. A gallium nitride based semiconductor power device comprising:a top gallium nitride layer comprises a plurality of guard rings disposed in a peripheral area of the top gallium nitride layer wherein the guard rings comprise a plurality of trenches having substantially a same depth opened in an upper portion of the top gallium nitride layer filled with a P-doped gallium-based epitaxial layer therein and wherein the guard rings surrounding a first electrode of the semiconductor power device comprises a metal layer covering over a middle portion of a top surface of the top gallium nitride layer; and
a heavily doped bottom gallium nitride epitaxial layer extending beyond an outer edge of the top gallium nitride layer wherein an extended portion of the bottom gallium nitride epitaxial layer having an exposed top surface not covered by the top gallium nitride layer and wherein a second electrode of the semiconductor power device is disposed directly on the exposed top surface of the extended portion of the bottom gallium nitride layer.

US Pat. No. 10,170,562

SEMICONDUCTOR DEVICE HAVING A JUNCTION PORTION CONTACTING A SCHOTTKY METAL

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a first conductive-type SiC semiconductor layer having a front surface and a rear surface;
an anode electrode having a multi-layered structure being in contact with the front surface of the SiC semiconductor layer; and
a cathode electrode formed on the rear surface of the SiC semiconductor layer, wherein
a Schottky junction is formed between the anode electrode and the front surface of the SiC semiconductor layer,
fine recesses are formed only in a SiC semiconductor layer side of a Schottky junction portion between the anode electrode and the front surface of the SiC semiconductor layer,
a part of the anode electrode is embedded in the fine recesses, and
the fine recesses have a depth not greater than 20 nm and are irregularly arranged on the SiC semiconductor layer.

US Pat. No. 10,170,561

DIAMOND SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A diamond semiconductor device comprising:a first diamond semiconductor layer of a first conductivity type having a main surface;
a second diamond semiconductor layer of an i-type or a second conductivity type provided on the main surface of the first diamond semiconductor layer, and having a first side surface with a plane orientation of a {111};
a third diamond semiconductor layer of the first conductivity type provided on the first side surface; and
a fourth diamond semiconductor layer of the second conductivity type provided on the main surface of the first diamond semiconductor layer and on a side surface of the second diamond semiconductor layer, at a side opposite to a side of the third diamond semiconductor layer.

US Pat. No. 10,170,560

SEMICONDUCTOR DEVICES WITH ENHANCED DETERMINISTIC DOPING AND RELATED METHODS

ATOMERA INCORPORATED, Lo...

1. A semiconductor device comprising:a semiconductor substrate;
a plurality of stacked groups of layers on the semiconductor substrate, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions; and
a dopant in the semiconductor substrate beneath the plurality of stacked groups of layers in at least one localized region with the plurality of stacked groups of layers vertically and horizontally constraining the dopant in the at least one localized region, the dopant having a fall-off steeper than 3.3 nm/decade.

US Pat. No. 10,170,558

LOCALIZED AND SELF-ALIGNED PUNCH THROUGH STOPPER DOPING FOR FINFET

International Business Ma...

1. A method for doping punch through stoppers (PTSs), comprising:recessing a dielectric layer to form gaps between a top portion of the dielectric layer and a spacer formed on sidewalls of fins to expose the fins in the gaps; and
doping the fins through the gaps to form PTSs in the fins, wherein a doped region extends from a bottom surface of the PTSs into a substrate, wherein each fin is formed of a material compound that is different from the substrate.

US Pat. No. 10,170,557

THYRISTOR WITH IMPROVED PLASMA SPREADING

ABB Schweiz AG, Baden (C...

1. A thyristor device comprising:a semiconductor wafer having a first main side and a second main side opposite to the first main side;
a first electrode layer, which is arranged on the first main side;
a second electrode layer, which is arranged on the first main side and which is electrically separated from the first electrode layer;
a third electrode layer, which is arranged on the second main side;
wherein the semiconductor wafer includes the following layers;
a first emitter layer of a first conductivity type, the first emitter layer being in electrical contact with the first electrode layer;
a first base layer of a second conductivity type different from the first conductivity type, wherein the first base layer is in electrical contact with the second electrode layer, and wherein the first base layer and the first emitter layer form a first, p-n junction;
a second base layer of the first conductivity type, the second base layer and the fist base layer forming a second p-n junction;
a second emitter layer of the second conductivity type, wherein the second emitter layer is in electrical contact with the third electrode layer, and
wherein the second emitter layer and the second base layer form a third p-n junction.
wherein the thyristor device comprises a plurality of discrete emitter shorts, each emitter short penetrating through the first emitter layer to electrically connect the first base layer with the first electrode layer,
wherein in an orthogonal projection onto a plane parallel to the first main side, a contact area covered by an electrical contact of the first electrode layer with the first emitter layer and the emitter shorts includes areas in the shape of lanes in which no emitter shorts are arranged,
wherein the width of the lanes is at least two times the average distance between centers of emitter shorts next to each other in the contact area,
the lanes are curved, and in the orthogonal projection onto the plane parallel to the first main side, the lanes extend from an edge of the contact area adjacent to the second electrode layer in a direction away from the second electrode layer.

US Pat. No. 10,170,556

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device manufacturing method, comprising:preparing a semiconductor substrate of a first conductivity type;
forming a semiconductor layer of the first conductivity type over a main surface of the semiconductor substrate;
forming a plurality of first ditches in an upper surface portion of the semiconductor layer such that the first ditches are arranged in a first direction extending along an upper surface of the semiconductor substrate;
forming a plurality of second ditches in bottom surface portions of each of the first ditches such that the second ditches are arranged in a second direction perpendicular to the first direction;
covering a side wall of each of the first ditches with a first insulating film and a side wall and a bottom surface of each of the second ditches with a second insulating film thicker than the first insulating film;
after the covering the side wall of each of the first ditches, forming gate electrodes inside the first ditches and the second ditches;
forming a first semiconductor region of a second conductivity type different from the first conductivity type over a side wall of each of the first ditches; and
forming a source region of the first conductivity type in an upper surface portion of the semiconductor layer,
wherein, in the first ditches adjacently arranged in the first direction, distances between an upper surface of the grate electrodes and a bottom surface of the second insulating film are different.

US Pat. No. 10,170,555

INTERMETALLIC DOPING FILM WITH DIFFUSION IN SOURCE/DRAIN

Taiwan Semiconductor Manu...

1. A method comprising:etching a substrate to form a first semiconductor strip;
forming a first dummy gate structure over a first channel region of the first semiconductor strip, the first dummy gate structure being perpendicular to the first semiconductor strip;
etching a first recess in the first semiconductor strip on a first side of the first dummy gate structure;
etching a second recess in the first semiconductor strip on a second side of the first dummy gate structure;
forming a first intermetallic doping film in the first recess and the second recess;
diffusing a first dopant of the first intermetallic doping film into the first semiconductor strip proximate the first recess and into the first semiconductor strip proximate the second recess;
epitaxially growing a source/drain region in the first recess; and
epitaxially growing a source/drain region in the second recess.

US Pat. No. 10,170,554

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a gate structure on a substrate, the gate structure comprising:
a gate dielectric layer, disposed on the substrate;
a raised source/drain region adjacent to the gate structure, the raised source/drain region comprising a tip region under the gate structure;
a channel region under gate dielectric layer of the gate structure; and
a protection layer, wherein:
the protection layer is interposed between the substrate and the raised source/drain region, and
an atom stacking arrangement of the protection layer is different from the substrate and the raised source/drain region, and the atom stacking arrangement of the protection layer is an amorphous state having a higher degree of lattice disorder than that of the substrate and the raised source/drain region, and the protection layer has a first end portion with the amorphous state formed between the tip region under the gate structure and the channel region under the gate dielectric layer.

US Pat. No. 10,170,553

SHAPED TERMINALS FOR A BIPOLAR JUNCTION TRANSISTOR

GLOBALFOUNDRIES Inc., Gr...

1. A method of fabricating a device structure, the method comprising:epitaxially growing a base layer;
epitaxially growing an emitter layer with a thickness on the base layer;
forming a hardmask layer over a section of the emitter layer; and
etching, by a plurality of etching processes with the hardmask layer over the section of the emitter layer, a plurality of trenches extending through the emitter layer to define an emitter of the device structure,
wherein the emitter layer has a concentration of an element that varies as a function of the thickness of the emitter layer, the section of the emitter layer is laterally etched by the etching processes such that the section of the emitter layer is undercut relative to the hardmask layer, and the emitter has a variable width over the thickness of the emitter layer due to a lateral etch rate that varies as a function of the concentration of the element during the plurality of etching processes.

US Pat. No. 10,170,552

CO-INTEGRATION OF SILICON AND SILICON-GERMANIUM CHANNELS FOR NANOSHEET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming nanosheet semiconductor devices, comprising:forming a first stack in a first device region comprising layers of a first channel material and layers of a sacrificial material;
forming a second stack in a second device region comprising layers of a second channel material, layers of the sacrificial material, and a liner formed around the layers of the second channel material; and
etching away the sacrificial material using a wet etch that is selective to the sacrificial material and the second channel material and does not affect the first channel material or the liner, wherein the liner protects the second channel material from the wet etch.

US Pat. No. 10,170,551

SIDEWALL IMAGE TRANSFER NANOSHEET

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a nanosheet stack on a substrate, the nanosheet stack comprising:
a sacrificial nanosheet layer on the substrate; and
a nanosheet layer on the sacrificial nanosheet layer;
an etch stop layer on the nanosheet stack;
a mandrel on the etch stop layer;
sidewalls adjacent to sidewalls of the mandrel; and
a fill layer on exposed portions of the etch stop layer.

US Pat. No. 10,170,550

STRESSED NANOWIRE STACK FOR FIELD EFFECT TRANSISTOR

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming an alternating stack of disposable material portions and semiconductor material portions on a substrate;
forming a disposable gate structure straddling, and contacting sidewalls of, said alternating stack;
removing said disposable material portions selective to said semiconductor material portions and said disposable gate structure;
forming a first gate structure between each vertically neighboring pair among said semiconductor material portions, said first gate structure including a first gate dielectric and a first gate electrode;
forming a planarization dielectric layer around said disposable gate structure;
forming a gate cavity by removing said disposable gate structure selective to said planarization dielectric layer; and
forming a second gate structure within said gate cavity, said second gate structure including a second gate dielectric and a second gate electrode, wherein said forming the first gate structure comprises forming, after removing said disposable material portions, a first gate dielectric layer on surfaces of said semiconductor material portions, forming a first gate conductor layer on said first gate dielectric layer, anisotropically etching said first gate conductor layer and said first gate dielectric layer employing a combination of said disposable gate structure and said semiconductor material portions as an etch mask, and isotropically etching remaining portions of said first gate conductor layer and said first gate dielectric layer between said vertically neighboring pair among said semiconductor material portions.

US Pat. No. 10,170,549

STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET

Samsung Electronics Co., ...

1. A method for fabricating a nanosheet stack structure having one or more sub-stacks, the method comprising:growing an epitaxial crystalline initial stack of the one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are each kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing such that the non-sacrificial layers B and C remain metastable and without relaxation during processing, and wherein the sacrificial layer A is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A;
proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that hold the nanosheets in place after selective etch of the sacrificial layers; and
selectively removing sacrificial layers A from all non-sacrificial layers B and C, while the remaining layers B and C in the stack are held in place by the pillar structures, so that after removal of the sacrificial layers A, each of the sub-stacks contains the non-sacrificial layers B and C, the sacrificial layer A differing from the non-sacrificial layers B and C such that removal of the sacrificial layer A leaves the non-sacrificial layer B and the non-sacrificial layer C in all of the plurality of sub-stacks and such that no sub-stack includes the non-sacrificial layer B in the absence of the non-sacrificial layer C and no sub-stack includes the non-sacrificial layer C in the absence of the non-sacrificial layer B, the sacrificial layer A being at least three times as thick as the non-sacrificial layer B and as the non-sacrificial layer C.

US Pat. No. 10,170,548

INTEGRATED CAPACITORS WITH NANOSHEET TRANSISTORS

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor device, the method comprising:depositing alternating nanosheet layers and sacrificial layers onto a substrate;
simultaneously forming fins in a capacitor region and fins in a device region, wherein the fins in the capacitor region have a greater width than the fins in the device region;
selectively etching the sacrificial layers to form an undercut in the capacitor region and complete removal in the device region;
doping the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region;
depositing a high k dielectric layer onto the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region, and on the nanosheet layers in the device region; and
forming top and bottom electrodes in the capacitor region.

US Pat. No. 10,170,547

NANODEVICE

JAPAN SCIENCE AND TECHNOL...

1. A nanodevice comprising:nanogap electrodes comprising a first electrode and a second electrode so as to have a nanosized gap in between;
a nanoparticle disposed between the nanogap electrodes;
one or more gate electrodes, each of the one or more gate electrodes connected to a wire so as to apply an input voltage;
a floating gate electrode;
a control gate electrode to control a state of electric charge of the floating gate electrode;
a first insulating layer on which the nanogap electrodes and the floating gate electrode are disposed; and
a second insulating layer disposed on the first insulating layer, the nanogap electrodes, the floating gate electrode, and the nanoparticle,
wherein the control gate electrode is disposed on the first insulating layer, and
the control gate electrode is disposed on an opposite side to the nanoparticle with the floating gate electrode interposed therebetween, or
wherein the control gate electrode is disposed on the second insulating layer and above the floating gate electrode, and
wherein the one or more gate electrodes do not include the floating gate electrode and the control gate electrode.

US Pat. No. 10,170,546

FULLY SUBSTRATE-ISOLATED FINFET TRANSISTOR

STMicroelectronics, Inc.,...

1. A device, comprising:a substrate;
a fin suspended over the substrate, the fin including a channel region, the fin having a first surface that faces the substrate;
a source region;
a drain region;
an insulating layer between the substrate and the fin, the source region, and the drain region, the insulating layer extending between and in contact with the substrate and the channel region of the fin, the first surface of the fin being between a surface of the insulating layer and the substrate; and
a gate overlying the channel region of the fin.

US Pat. No. 10,170,545

MEMORY ARRAYS

Micron Technology, Inc., ...

1. A memory array, comprising:a semiconductor substrate;
a trench extending into the substrate and proximate a transistor, the trench comprising an upper portion over a lower portion;
a liner along an interior wall of the lower and upper portions of the trench, the liner comprising a transition configuration between the lower and upper portions of the trench, the transition configuration comprising a curved configuration and the liner comprising the only transition configuration for the lower and upper portions of the trench; and
an electrically insulative material in the lower and upper portions of the trench.

US Pat. No. 10,170,544

INTEGRATED CIRCUIT PRODUCTS THAT INCLUDE FINFET DEVICES AND A PROTECTION LAYER FORMED ON AN ISOLATION REGION

GLOBALFOUNDRIES Inc., Gr...

1. An integrated circuit product, comprising:a FinFET device comprising at least one fin, a gate structure, and a sidewall spacer;
a device isolation region comprising a first insulating material positioned around a perimeter of said FinFET device; and
an isolation protection layer positioned above said device isolation region, said isolation protection layer comprising a material that is different from said first insulating material, wherein a first portion of said isolation protection layer is positioned under a portion of said gate structure and under a portion of said sidewall spacer, and wherein a second portion of said isolation protection layer is not positioned under said gate structure and is not positioned under said sidewall spacer, said first portion of said isolation protection layer having a thickness that is greater than a thickness of said second portion.

US Pat. No. 10,170,543

VERTICAL FIN FIELD EFFECT TRANSISTOR WITH AIR GAP SPACERS

International Business Ma...

1. A method of forming a fin field effect transistor device with air gaps, comprising:forming a vertical fin on a substrate;
forming an inner protective cap on the vertical fin;
forming an outer protective cap on the inner protective cap;
forming a source/drain layer in contact with the vertical fin;
forming a sacrificial bottom spacer on each side of the vertical fin, and on the source/drain layer; and
forming a spacer cap layer on the sacrificial bottom spacer.

US Pat. No. 10,170,542

SEMICONDUCTOR DEVICE

Nuvoton Technology Corpor...

1. A semiconductor device, comprising:a substrate of a first conductivity type;
a metal-oxide-semiconductor-field-effect transistor (MOSFET), located on the substrate, wherein the MOSFET comprises:
a first epitaxial layer of a second conductivity type;
at least two body regions of the first conductivity type, respectively located in the first epitaxial layer;
at least two first doped regions of the second conductivity type, respectively located in the body regions; and
a gate structure, located on the first epitaxial layer between the first doped regions;
a first junction gate field-effect transistor (JFET), located on the substrate, the first JFET having a second epitaxial layer of the second conductivity type;
an isolation structure, located between the MOSFET and the first JFET to separate the first epitaxial layer from the second epitaxial layer; and
a buried layer of the second conductivity type, located between the MOSFET and the substrate, wherein the buried layer extends from below the MOSFET to below the isolation structure and below the first JFET, so as to electrically connect the MOSFET to the first JFET.

US Pat. No. 10,170,541

SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF ELECTRODES AND SUPPORTERS

Samsung Electronics Co., ...

1. A semiconductor device comprising:a plurality of electrode structures on a substrate, the plurality of electrode structures having side surfaces; and
an upper supporter group and a lower supporter between upper ends and lower ends of the plurality of electrode structures, respectively, the upper supporter group including a plurality of upper supporters, at least some of the plurality of upper supporters each having an upper surface and a lower surface, the at least some of the plurality of upper supporters having a thickness between the upper surface and the lower surface, respectively,
wherein a first one of the upper surface and the lower surface has a curved profile, and a second one of the upper surface and lower surface has a flat profile, and
at least some of the plurality of upper supporters have the thickness that decreases towards the plurality of electrode structures.

US Pat. No. 10,170,540

CAPACITORS

INTERNATIONAL BUSINESS MA...

1. A method comprising:forming separate wiring lines on a substrate, with spacing between adjacent separate wiring lines;
forming air gaps within the spacing by depositing capping material on the separate wiring lines and the spacing between the adjacent separate wiring lines;
forming a dielectric material over the capping material;
forming a trench in the dielectric material and over plural ones of the adjacent separate wiring lines, wherein the forming the trench opens the air gaps by removing a surface of the capping material; and
depositing conductive material within the opened air gaps through the trench.

US Pat. No. 10,170,539

STACKED CAPACITOR WITH ENHANCED CAPACITANCE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first conductive layer over the semiconductor substrate;
a second conductive layer over the first conductive layer;
a dielectric layer between the first conductive layer and the second conductive layer;
a cap layer over the second conductive layer;
a first contact via through the cap layer, the second conductive layer and the dielectric layer, and electrically connected to the first conductive layer, wherein a bottom of the first contact via stops at an upper surface of the first conductive layer; and
a second contact via through the cap layer, and electrically connected to the second conductive layer, wherein a bottom of the second contact via stops at an upper surface of the second conductive layer.

US Pat. No. 10,170,538

MIS CAPACITOR

Korea Electronics Technol...

1. An MIS capacitor, comprising:a lower electrode formed of a semiconductor substrate having electrical conductivity and through which an electrical signal passes at a lower surface thereof, wherein the lower electrode has the lower surface, an upper surface substantially parallel to the lower surface, and a side surface formed between the lower surface and the upper surface and connecting an edge of the lower surface and an edge of the upper surface;
an insulating layer formed on the lower electrode;
an upper electrode formed on the insulating layer and through which the electrical signal passes at an upper surface thereof; and
a first conductive layer formed on the side surface of the lower electrode so that the electrical signal passing the lower surface and the upper surface of the lower electrode passes along the side surface of the lower electrode,
wherein the first conductive layer has electro conductivity higher than the electro conductivity of the lower electrode.

US Pat. No. 10,170,537

CAPACITOR STRUCTURE COMPATIBLE WITH NANOWIRE CMOS

International Business Ma...

1. A method of forming an electrical device comprising:forming a stacked structure of at least a first semiconductor material layer and a second semiconductor material layer, wherein a material of the first and second semiconductor material layers have different oxidation rates;
oxidizing a sidewall of the stacked structure to form an oxide layer, wherein a first thickness of a first portion of the oxide layer that is present on the first semiconductor material layer is different from a second thickness of a second portion of the oxide layer that is present on the second semiconductor material layer;
removing the first or second portion of the oxide layer having a lesser thickness to provide an exposed surface of the stacked structure;
forming a replacement structure on a first portion of the stacked structure;
forming an epitaxial semiconductor material on the exposed surface of the stacked structure, wherein portions of the stacked structure having the epitaxial semiconductor material has a greater width than portions of the stacked structure not including the epitaxial semiconductor material;
forming an epitaxial crystalline semiconductor material on end portions of the stacked structure on opposing sides of the replacement structure;
forming a dielectric layer on exposed portions of the stacked structure having the epitaxial semiconductor material; and
forming a conductive material on the dielectric layer.

US Pat. No. 10,170,536

MAGNETIC MEMORY WITH METAL OXIDE ETCH STOP LAYER AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a substrate;
a first passivation layer over the substrate;
a second passivation layer over the first passivation layer;
a magnetic layer in the second passivation layer; and
an etch stop layer between the magnetic layer and the first passivation layer, wherein the etch stop layer is in contact with the magnetic layer, and the etch stop layer includes at least one acid resistant layer, and the acid resistant layer includes a metal oxide.

US Pat. No. 10,170,535

ACTIVE-MATRIX TOUCHSCREEN

X-Celeprint Limited, Cor...

1. An active-matrix touchscreen having a touch area in which the active-matrix touchscreen is responsive to touches, the touchscreen comprising:a substrate;
a system controller;
a plurality of spatially separated independent touch elements disposed in a two-dimensional array within the touch area on and in contact with the substrate, each touch element comprising:
a mutual-capacitive touch sensor comprising at least two electrical conductors in a common layer on and in contact with the substrate, the two electrical conductors forming a capacitor; and
a touch controller circuit on and in contact with the substrate for providing one or more sensor-control signals to the touch sensor and for receiving a sense signal responsive to the one or more sensor-control signals from the touch sensor, wherein each touch sensor operates independently of any other touch sensor of the plurality of touch elements, wherein the two electrical conductors of each touch element are electrically separate from the two electrical conductors of any other touch element,
wherein the touch controller circuit of one or more of the plurality of spatially separated independent touch elements is disposed between the respective touch sensors of two or more of the plurality of spatially separated independent touch elements over the substrate.

US Pat. No. 10,170,534

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate;
a plurality of display elements in a display area of the substrate, wherein each of the plurality of display elements includes a pixel electrode, an opposite electrode, and an intermediate layer between the pixel electrode and the opposite electrode;
a drive circuit on an outer side of the display area and including a thin film transistor;
a first insulating layer on the drive circuit;
a first power supply line layer on the first insulating layer and overlapping the drive circuit;
a second insulating layer on the first power supply line layer; and
a connection electrode layer on the second insulating layer, wherein the connection electrode layer electrically connects the first power supply line layer to the opposite electrode.

US Pat. No. 10,170,533

DISPLAY DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. A display device comprising:a pixel array unit having pixels arranged in a matrix, at least one of the pixels having an electro-optical element, a first capacitor, a second capacitor, a first transistor configured to supply a data signal from a data line to the first capacitor, and a second transistor configured to flow a drive current to the electro-optical element;
a data signal line extending in a first direction; and
a scan line extending in a second direction perpendicular to the first direction,
wherein,
the first capacitor has a first electrode and a second electrode overlapped with the first electrode partly,
the second capacitor has a third electrode and a fourth electrode overlapped with the third electrode partly,
the first electrode is disposed in a first layer,
the fourth electrode is disposed in a second layer which is different from the first layer, and the second layer is disposed over the first layer,
the first electrode is electrically connected to a control terminal of the second transistor,
the second electrode is electrically connected to a first current terminal of the second transistor,
the third electrode is electrically connected to an anode electrode of the electro-optical element, and
the second electrode and the third electrode are electrically connected.

US Pat. No. 10,170,532

EL DISPLAY PANEL, POWER SUPPLY LINE DRIVE APPARATUS, AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An electroluminescence display device comprising:a plurality of pixel circuits arranged in a matrix form having a column and a row; and
a peripheral circuit configured to drive the pixel circuits,
wherein the pixel circuits includes:
a first pixel circuit configured to drive a first electroluminescence element, and
a second pixel circuit adjacent to the first pixel circuit along a column direction and configured to drive a second electroluminescence element,
wherein the peripheral circuits includes:
a first buffer circuit including a first transistor and a second transistor serially connected between a first node and a second node, and configured to alternatively output a high potential and a low potential, to the first pixel circuit via a first extraction wire,
a second buffer circuit including a third transistor and a fourth transistor serially connected between a third node and a fourth node, and configured to alternatively output a high potential and a low potential, to the second pixel circuit via a second extraction wire,
a first line connected to the first node of the first buffer circuit and the third node the second buffer circuit, and
a second line connected to the second node of the first buffer circuit and the fourth node the second buffer circuit,
wherein the first line and the second line is disposed on an input side of first buffer circuit.

US Pat. No. 10,170,531

ORGANIC LIGHT EMITTING DIODE DISPLAY INCLUDING REACTION BLOCKING MEMBER ON COMMON VOLTAGE LINE

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display comprising:a substrate divided into a pixel area, and a peripheral area enclosing the pixel area;
an organic light emitting diode which is in the pixel area, and comprises a first electrode, an organic emission layer and a second electrode;
a switching element which is in the pixel area, and controls the organic light emitting diode;
a protective layer covering the switching element;
a pixel defining layer which defines the pixel area in which the organic light emitting diode is disposed;
a common voltage line which is in the peripheral area, and transmits a common voltage to the second electrode; and
a reaction blocking part which is in the peripheral area and overlaps the common voltage line, the reaction blocking part comprising a same material as the first electrode,
wherein in the peripheral area:
a side surface of the common voltage line which is furthest from the pixel area is exposed by each of the protective layer and the pixel defining layer, and
the reaction blocking part which comprises the same material as the first electrode overlaps an entirety of the exposed side surface of the common voltage line which is furthest from the pixel area.

US Pat. No. 10,170,530

DISPLAY DEVICE INCLUDING FIRST AND SECOND SUBSTRATES, ONE INCLUDING A PAD ELECTRODE

Japan Display Inc., Mina...

1. A display device comprising:a first substrate including an insulating substrate with a first through hole, a pad electrode positioned above the insulating substrate, and a signal line electrically connected to the pad electrode;
a second substrate opposed to the first substrate;
a sealant which adheres the first substrate and the second substrate;
a line substrate including a connection line and disposed below the insulating substrate; and
a conductive material which electrically connects the pad electrode and the connection line, wherein
the pad electrode and the first through hole overlap the sealant,
a first part of the first through hole does not overlap the pad electrode and overlaps the sealant, and a second part of the first through hole overlaps both of the pad electrode and the sealant, and
the sealant is less absorptive than is the insulating substrate as to a wavelength less than 350 nm.

US Pat. No. 10,170,529

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:preparing a processed member, the processed member comprising:
an organic resin layer over a substrate; and
an element layer comprising a transistor over the organic resin layer;
irradiating the organic resin layer with a linear beam through the substrate by using a first apparatus, the first apparatus comprising:
a laser oscillator configured to emit a laser light;
an optical device configured to extend the laser light; and
a lens configured to condense the laser light into the linear beam; and
separating the organic resin layer from the substrate by using a separation apparatus after irradiating the organic resin layer with the linear beam,
wherein the separation apparatus comprises a roller, and
wherein the organic resin layer and the element layer are rolled up by the roller at the step of separating the organic resin layer from the substrate.

US Pat. No. 10,170,528

DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display panel comprising:a driver circuit;
a signal line electrically connected to the driver circuit; and
a pixel electrically connected to the signal line, the pixel comprising:
a first display element comprising a first conductive film;
a second conductive film comprising a region overlapping with the first conductive film;
an insulating film comprising a region between the first conductive film and the second conductive film;
a pixel circuit electrically connected to the second conductive film and the signal line, the pixel circuit comprising a first transistor comprising silicon in a channel formation region; and
a second display element electrically connected to the pixel circuit,
wherein the insulating film comprises a first opening,
wherein the first conductive film comprises a second opening,
wherein the second opening overlaps the second display element, and
wherein the second conductive film is electrically connected to the first conductive film in the first opening.

US Pat. No. 10,170,527

ORGANIC LIGHT EMITTING DIODE DISPLAY

SAMSUNG DISPLAY CO., LTD....

1. An organic light emitting diode display, comprising:a substrate including a pixel region and a peripheral region enclosing the pixel region;
a scan line on the substrate and transferring a scan signal;
a data line crossing the scan line and transferring a data voltage;
a switching transistor disposed in the pixel region and electrically connected to the scan line and the data line;
a driving transistor disposed in the pixel region and electrically connected to the switching transistor;
a pixel-area passivation layer disposed on the switching transistor and the driving transistor;
a pixel electrode disposed on the pixel-area passivation layer;
a pixel partition wall layer disposed on the pixel-area passivation layer and having a pixel opening overlapping the pixel electrode;
an organic light emission layer disposed in the pixel opening and disposed on the pixel electrode;
a common electrode disposed on the organic light emission layer and the pixel partition wall layer;
a common voltage line disposed in the peripheral region and electrically connected to the common electrode;
a peripheral passivation layer disposed in the peripheral region and contacting a side wall of the common voltage line;
a peripheral driving voltage line disposed in the peripheral region and which transfers a driving voltage ELVDD;
a driving voltage pad to which the driving voltage ELVDD is applied from the outside;
a driving voltage connecting part connecting the driving voltage pad and the peripheral driving voltage line,
wherein the driving voltage pad is disposed at the same layer as the common voltage line.

US Pat. No. 10,170,526

ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL AND METHOD FOR MANUFACTURING SAME

WUHAN CHINA STAR OPTOELEC...

1. An organic light emitting diode (OLED) display panel, comprising:a thin film transistor layer;
an anode layer formed on the thin film transistor layer, the anode layer comprising at least two arrays of anodes arranged in an array;
a pixel definition layer formed on the thin film transistor layer, the pixel definition layer comprising a plurality of sub-pixel openings, wherein the sub-pixel openings and the anodes are aligned with each other; and
a barrier layer disposed on the pixel definition layer between any two of the anodes adjacent to each other, wherein the barrier layer is configured to block an electrical charge released by one of the two adjacent anodes from entering into a region in a cathode layer corresponding to the other of the two adjacent anodes;
wherein a height of the barrier layer in a direction perpendicular to a plane of the OLED display panel is greater than a height of a sum of a first common layer, a second common layer, and the cathode layer.

US Pat. No. 10,170,525

ORGANIC LIGHT EMITTING DISPLAY DEVICE

Samsung Display Co., Ltd....

1. An organic light emitting display (OLED) device, comprising:a substrate including a sub-pixel region and a transparent region;
a gate insulation layer on the substrate;
a planarization layer in the sub-pixel region on the gate insulation layer, the planarization layer exposing-the transparent region;
a boundary pattern which covers a boundary of the sub-pixel region and the transparent region, the boundary pattern including:
a first boundary extension extending in a direction from the boundary of the sub-pixel region and the transparent region into the sub-pixel region, the first boundary extension extending onto the sidewall of the planarization layer, and
a second boundary extension extending in a direction from the boundary of the sub-pixel region and the transparent region into the transparent region, the second boundary extension extending onto an upper surface of the gate insulation layer that is located in transparent region on the substrate;
a pixel defining layer on the planarization layer, the pixel defining layer exposing the transparent region and exposing at least a portion of an upper surface of the boundary pattern in the transparent region; and
a sub-pixel structure on the planarization layer.

US Pat. No. 10,170,524

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an input/output device comprising a display portion and a touch sensor, the input/output device having a first region, a second region adjacent to the first region, and a third region adjacent to the second region;
a member over the input/output device, the member having a first part and a second part;
a first fixing portion configured to fix an end of the first region of the input/output device and an end of the first part of the member;
a second fixing portion configured to fix an end of the third region of the input/output device; and
a roll-up portion connected to an end of the second part of the member and the second fixing portion,
wherein the second part of the member is located over the second region and the third region of the input/output device in an unfolded state,
wherein the roll-up portion is configured to roll up the second part of the member in a folded state, and
wherein the input/output device reversibly exists in the folded state and the unfolded state.

US Pat. No. 10,170,523

TOUCH SENSITIVE DISPLAY AND METHOD FOR MANUFACTURING THE SAME

TPK Touch Solutions Inc.,...

1. A touch sensitive display, comprising:an upper substrate;
a lower substrate that has a top surface facing a bottom surface of the upper substrate;
a touch sensing layer disposed on the bottom surface of the upper substrate wherein the touch sensing layer comprises a plurality of sensing electrodes and a plurality of signal transmission lines connected to the plurality of sensing electrodes;
a mask layer disposed in a peripheral area on the bottom surface of the upper substrate, wherein:
the plurality of sensing electrodes is surrounded by the mask layer, and
the plurality of sensing electrodes and the mask layer intersect a plane parallel to a plane in which the top surface of the lower substrate lies;
an organic light-emitting assembly disposed on the top surface of the lower substrate; and
a sealing layer disposed between the mask layer and the lower substrate and sealing together the upper substrate and the lower substrate.

US Pat. No. 10,170,522

HIGH PIXEL DENSITY ARRAY ARCHITECTURE

Ignis Innovations Inc., ...

1. A display device comprising a matrix of subpixels grouped into pixels, the matrix of subpixels arranged in a substantially rectilinear matrix oriented at substantially a 45 degree angle relative to a major axis of the display, each pixel forming a right angle shape oriented in one of a first direction and a second direction opposite from the first direction.

US Pat. No. 10,170,521

ORGANIC LIGHT-EMITTING DIODE DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light-emitting diode display device comprising:a substrate on which red, green and blue sub-pixel regions are defined;
a first electrode in the red, green and blue sub-pixel regions, respectively;
first, second and third light-emitting layers on the first electrode in the red, green and blue sub-pixel regions, respectively;
a second electrode on the first, second and third light-emitting layers; and
red, green and blue color filters on the second electrode and corresponding to the red, green and blue sub-pixel regions, respectively,
wherein a thickness of the first light-emitting layer is smaller than a thickness of the second light emitting layer, and
wherein a thickness of the third light-emitting layer is smaller than the thickness of the first light-emitting layer.

US Pat. No. 10,170,520

NEGATIVE-CAPACITANCE STEEP-SWITCH FIELD EFFECT TRANSISTOR WITH INTEGRATED BI-STABLE RESISTIVE SYSTEM

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a negative capacitance steep-switch transistor comprising:receiving a semiconductor structure including a substrate, a fin disposed on the substrate, a source/drain disposed on the substrate adjacent to the fin, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, a shallow trench isolation (STI) layer disposed upon the substrate, and an inter-layer dielectric disposed on the trench contact and the cap;
forming a source/drain recess in the inter-layer dielectric extending to the trench contact;
forming a gate recess in the inter-layer dielectric extending to the gate;
depositing a ferroelectric material within the gate recess;
forming a source/drain contact within the source/drain recess in contact with the trench contact;
forming a gate contact within the gate recess in contact with the ferroelectric material;
forming a contact recess in a portion of the source/drain contact;
depositing a bi-stable resistive system (BRS) material in the contact recess in contact with the portion of the source/drain contact; and
forming a metallization layer contact upon the BRS material, a portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forming a reversible switch.

US Pat. No. 10,170,519

MAGNETORESISTIVE ELEMENT AND MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive element comprising:a first metal layer having a body-centered cubic structure;
a second metal layer having a hexagonal close-packed structure on the first metal layer;
a metal nitride layer on the second metal layer;
a first magnetic layer on the metal nitride layer;
an insulating layer on the first magnetic layer; and
a second magnetic layer on the insulating layer.

US Pat. No. 10,170,518

SELF-ASSEMBLED PATTERN PROCESS FOR FABRICATING MAGNETIC JUNCTIONS USABLE IN SPIN TRANSFER TORQUE APPLICATIONS

Samsung Electronics Co., ...

1. A method for providing a plurality of magnetic junctions on a substrate and usable in a magnetic device, the method comprising:providing a patterned seed layer, the patterned seed layer including a plurality of magnetic seed islands interspersed with an insulating matrix;
providing at least a portion of a magnetoresistive stack after the step of providing the patterned seed layer, the magnetoresistive stack including at least one magnetic segregating layer, the at least one magnetic segregating layer including at least one magnetic material and at least one insulator;
annealing the at least the portion of the magnetoresistive stack such that the at least one magnetic segregating layer segregates such that a plurality of portions of at least one magnetic material align with the plurality of magnetic seed islands and such that a plurality of portions of the at least one insulator align with the insulating matrix.

US Pat. No. 10,170,517

METHOD FOR FORMING IMAGE SENSOR DEVICE

Taiwan Semiconductor Manu...

1. A method for forming an image sensor device on a substrate, comprising:(a) recessing a portion of the substrate thereby forming a first shallow trench;
(b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench;
(c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as an intact mask thereby shrinking a width of the first deep trench;
(d) removing the spacer layer;
(e) forming a second oxide layer over the sidewall of the first shallow trench;
(f) forming a second liner layer in the substrate surrounding the first shallow trench; and
(g) filling the first shallow trench with a first isolation material thereby forming a first shallow trench isolation (STI) feature in the substrate.

US Pat. No. 10,170,516

IMAGE SENSING DEVICE AND METHOD FOR FABRICATING THE SAME

VISERA TECHNOLOGIES COMPA...

1. An image sensing device, comprising:a substrate, comprising a pixel array having a plurality of pixels;
a light guide structure, disposed over the substrate, forming a plurality of light pipes and a plurality of reflecting portions defining the light pipes, wherein the light pipes are aligned with the pixels of the pixel array;
a microlens array, disposed between the substrate and the light guide structure; the microlens array including a plurality of microlenses; and
a color filter array, disposed between the substrate and the microlens array,
wherein the substrate, the light guide structure, the microlens array and the color filter array are formed on a single die, and
wherein each light reflecting portion extends to and contacts an outer edge of at least one of the plurality of microlenses.

US Pat. No. 10,170,515

IMPLANTATION PROCESS FOR SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:providing a substrate, wherein the substrate has a first surface and a second surface opposite to each other;
performing a first implantation process on the substrate from the first surface to form a first shallow implantation region in the substrate adjacent to the first surface;
forming a device on the first surface adjacent to the first shallow implantation region;
performing a thinning process on the second surface of the substrate; and
performing a second implantation process on the substrate from the second surface to form a first deep implantation region and a second deep implantation region in the substrate adjacent to the second surface, wherein the first deep implantation region is formed to adjoin the first shallow implantation region, the second implantation process is performed such that at least a portion of the second deep implantation region is separated from the first deep implantation region, and the second deep implantation region is formed to peripherally surround the first deep implantation region.

US Pat. No. 10,170,514

IMAGE SENSOR

CMOSIS BVBA, Antwerp (BE...

1. An image sensor comprising an array of pixels and control logic which is arranged to control operation of the pixels, each of the pixels comprising:a pinned photodiode;
a first sense node;
a second sense node;
a transfer gate connected between the pinned photodiode and the first sense node;
a first reset transistor connected between a voltage reference line and the second sense node;
a second reset transistor connected between the first sense node and the second sense node; and
a buffer amplifier having an input connected to the first sense node;the image sensor further comprising:a first reset control line connected between the control logic and the first reset transistor in each of a plurality of pixels of the array;
a second reset control line connected between the control logic and the second reset transistor in each of the plurality of pixels of the array;
wherein the control logic is arranged to selectively operate the pixels in a low conversion gain mode and in a high conversion gain mode and in each of the conversion gain modes the control logic is arranged to operate one of the first reset control line and the second reset control line to continuously switch on one of the first reset transistor and the second reset transistor during a readout period of an operational cycle of the pixels and;wherein, in each of the conversion gain modes the control logic is arranged to operate the first reset control line and the second reset control line such that the first reset transistor and the second reset transistor are switched on during a non-readout period of the operational cycle of the pixels;wherein for the low conversion gain mode;
the second reset transistor is switched on during a readout period, and the first reset control line is operated to switch on the first reset transistor to reset the first sense node and
for the high conversion pain mode;
the first reset transistor is switched on during a readout period, and the second reset control line is operated to switch on the second reset transistor to reset the first sense node.

US Pat. No. 10,170,513

IMAGE SENSOR WITH VERTICAL ELECTRODES

STMICROELECTRONICS (CROLL...

1. An image sensor arranged inside and on top of a semiconductor substrate having a front surface and a rear surface, the sensor comprising a plurality of pixels, each comprising:a photosensitive area, a reading area, and a storage area extending between the photosensitive area and the reading area;
a first vertical insulated electrode extending from the front surface of the substrate between the photosensitive area and the storage area, comprising at least one opening extending from the front surface of the substrate and defining an area of charge transfer between the photosensitive area and the storage area; and
an insulation element comprising an insulating wall extending vertically inside of or opposite a lower portion of said opening, or under said opening, so that the depth of the charge transfer area is smaller than the depth of said first vertical insulated electrode, wherein, in each pixel, the photosensitive area comprises a first well of a conductivity type opposite to that of the substrate, and the storage area comprises a second well of the conductivity type opposite to that of the substrate and having a depth greater than that of the first well; the first vertical insulated electrode extends down to a depth greater than or equal to that of the second well; and the vertical insulating wall extends between the rear surface plane of the first vertical insulated electrode, and a plane located under the rear surface plane of the first well.

US Pat. No. 10,170,512

UNIFORM-SIZE BONDING PATTERNS

Taiwan Semiconductor Manu...

15. A method comprising:forming an image sensor comprising:
depositing a first passivation layer over a first substrate, the first substrate having a plurality of photosensitive elements therein;
forming a first plurality of bonding pads in the first passivation layer, the first plurality of bonding pads having a first width and a first pitch; and
forming a second plurality of bonding pads in the first passivation layer, the second plurality of bonding pads having the first width, the second plurality of bonding pads being grouped into clusters, the second plurality of bonding pads having a second pitch between neighboring clusters and the first pitch between adjacent bonding pads in a first cluster, the first pitch being smaller than the second pitch;
forming a second substrate comprising:
forming a second passivation layer over a second substrate; and
forming a third plurality of hybrid bonding pads in the second passivation layer; and
bonding the second substrate is to the image sensor such that the first plurality of bonding pads and the second plurality of bonding pads are coupled with respective ones of the third plurality of bonding pads.

US Pat. No. 10,170,511

SOLID-STATE IMAGING DEVICES HAVING A MICROLENS LAYER WITH DUMMY STRUCTURES

VISERA TECHNOLOGIES COMPA...

1. A solid-state imaging device, having a sensing region, a pad region and a peripheral region located between the sensing region and the pad region, comprising:a semiconductor substrate;
a plurality of photoelectric conversion elements disposed in the semiconductor substrate and in the sensing region;
a bond pad disposed on the semiconductor substrate and in the pad region;
a microlens layer, including a microlens array and a first dummy structure, disposed above the semiconductor substrate, wherein the microlens array is disposed in the sensing region, the first dummy structure is disposed in the pad region, and the first dummy structure includes a plurality of first microlens elements disposed to surround an area of the bond pad; and
a passivation film conformally formed on a top surface of the microlens layer.

US Pat. No. 10,170,510

COLOR SEPARATION ELEMENT ARRAY, IMAGE SENSOR INCLUDING THE SAME, AND ELECTRONIC DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A color separation element array comprising:a transparent layer; and
a plurality of color separation elements provided in the transparent layer and configured to separate an incident light into a color light according to wavelength bands,
wherein the plurality of color separation elements comprise a first element having a first refractive index and a second element arranged in one side of the first element in a horizontal direction and having a second refractive index.

US Pat. No. 10,170,509

OPTICAL FILTER ARRAY

VIAVI Solutions Inc., Sa...

1. A device, comprising:a first mirror disposed on a substrate;
a plurality of spacers disposed on the first mirror,
a first spacer, of the plurality of spacers, being associated with a first thickness,
a second spacer, of the plurality of spacers, being associated with a second thickness that is different from the first thickness;
a first sensor element corresponding to the first spacer; and
a second sensor element corresponding to the second spacer,
a separation width between the first sensor element and the second sensor element being less than approximately 10 micrometers (?m); and
a second mirror disposed on the plurality of spacers,
the second mirror including a first slanted side and a second slanted side, and
the second slanted side being on an opposite side of the second mirror from the first slanted side.

US Pat. No. 10,170,508

OPTICAL PACKAGE STRUCTURE

KINGPAK TECHNOLOGY INC., ...

1. An optical package structure comprising:a substrate having a first surface and a second surface opposite to the first surface;
a frame layer formed on the first surface of the substrate and surrounding a cavity on the substrate, the frame layer having a first surface and a second surface opposite to each other, wherein the first surface of the frame layer faces toward the cavity and the second surface of the frame layer faces away from the cavity;
an optical unit disposed on the first surface of the substrate and located inside the cavity;
a bonding layer formed on a portion of an upper edge of the frame layer and exposing the other portion of the upper edge of the frame layer;
a transparent plate mounted on the bonding layer and extending across the optical unit, the transparent plate extending beyond an outer edge of the bonding layer, the transparent plate having a first surface and a second surface opposite to the first surface and facing toward the optical unit; and
an encapsulation layer covering a lateral edge of the transparent plate and the outer edge of the bonding layer, the encapsulation layer being in contact with a portion of the second surface of the transparent plate and a portion of the upper edge of the frame layer, an external lateral surface of the encapsulation layer which faces away from the cavity being aligned with the second surface of the frame layer.

US Pat. No. 10,170,507

SOLID-STATE IMAGING DEVICE

OLYMPUS CORPORATION, Tok...

1. A solid-state imaging device, comprising:a plurality of micro lenses;
a first substrate which has a plurality of first photoelectric conversion units, in which each of the plurality of first photoelectric conversion units corresponds to any one of the plurality of micro lenses, in which first light transmitted through the plurality of micro lenses is incident on the plurality of first photoelectric conversion units corresponding to the plurality of micro lenses, and in which the plurality of first photoelectric conversion units generate first signals according to the first light;
a second substrate which has a plurality of second photoelectric conversion units and a plurality of third photoelectric conversion units, in which a plurality of pairs of photoelectric conversion units are disposed, in which each of the plurality of pairs of photoelectric conversion units includes one of the second photoelectric conversion units and one of the third photoelectric conversion units, in which each of the plurality of pairs of photoelectric conversion units corresponds to at least one of the plurality of first photoelectric conversion units, in which second light transmitted through the plurality of first photoelectric conversion units is incident on the plurality of pairs of photoelectric conversion units corresponding to the plurality of first photoelectric conversion units, in which the plurality of second photoelectric conversion units generate second signals according to third light, in which the third light is the second light corresponding to light passing through a first lens region, in which the plurality of third photoelectric conversion units generate third signals according to fourth light, and in which the fourth light is the second light corresponding to light passing through a second lens region,
wherein an imaging lens is disposed optically forward of the plurality of micro lenses and the imaging lens has the first lens region and the second lens region,
the second substrate further includes charge isolation regions disposed between the second photoelectric conversion units and the third photoelectric conversion units and the charge isolation regions are configured to prevent movement of charge between the second photoelectric conversion units and the third photoelectric conversion units, and
the first substrate further includes pillar-shaped separating layers formed so as to extend in the direction from the charge isolation regions to the first photoelectric conversion units, the separating layers configured to separate the second light into the third light and the fourth light and to cause the third light and the fourth light to be incident on the second photoelectric conversion units and the third photoelectric conversion units respectively.

US Pat. No. 10,170,506

LTPS ARRAY SUBSTRATE AND METHOD FOR PRODUCING THE SAME

Shenzhen China Star Optoe...

1. A method for producing a low temperature poly-silicon (LTPS) array substrate, comprising:forming a gate of a thin-film transistor (TFT) on a substrate;
forming an insulating layer, a semiconductor layer, and a first positive photoresist layer on the substrate one by one in which an upper surface of the insulating layer is a plane;
exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer;
forming a source and a drain of the TFT on the polycrystalline silicon layer;
forming a pixel electrode on the insulating layer and a part of the drain;
forming a plain passivation layer on a source-drain electrode layer, which is fabricated from the source and the drain, and forming contact vias in the plain passivation layer for exposing surfaces of the gate and the drain, and the contact vias being disposed outside the polycrystalline silicon layer; and
forming a transparent electrode layer on the plain passivation layer so that the transparent electrode layer is electrically connected to the gate via the contact via;
wherein before the insulating layer is formed on the substrate, a pre-operation is carried out to form a buffer layer on a portion of the substrate that is not covered by the gate such that an upper surface of the buffer layer and an upper surface of the gate collectively form a plane, and the pre-operation comprises the following steps:
forming the buffer layer and a negative photoresist layer on the substrate in sequence;
exposing one side of the substrate on the opposite side of the gate for removing a portion of the negative photoresist layer disposed right above the gate; and
removing the buffer layer disposed right above the gate such that a portion of the buffer layer is preserved on the portion of the substrate that is not covered by the gate; and
wherein the step of “exposing one side of the substrate on the opposite side of the gate for forming a polycrystalline silicon layer” comprises the following sub-steps:
exposing one side of the substrate on the opposite side of the gate for only preserving the first positive photoresist layer disposed on a first section disposed right above the gate;
injecting P-type impurity ions into the semiconductor layer outside the first section;
exposing one side of the substrate on the opposite side of the gate for forming the first positive photoresist layer disposed on a second section disposed right above the gate, and the second section being smaller than the first section; and
removing the first positive photoresist layer disposed on the second section.

US Pat. No. 10,170,505

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display apparatus comprising:a substrate comprising a display area and a peripheral area outside the display area;
a display unit over an upper surface of the substrate to correspond to the display area; and
a protective film comprising a protective film base and an adhesive layer, the protective film being attached to a lower surface of the substrate by the adhesive layer,
wherein the protective film base comprises a first protective film base corresponding at least to the display area, and a second protective film base having a physical property that is different from a physical property of the first protective film base and corresponding to at least a part of the peripheral area, and
wherein the second protective film base has a light transmittance that is greater than a light transmittance of the first protective film base.

US Pat. No. 10,170,504

MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE, TFT ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A TFT array substrate, comprising a thin film transistor and a pixel electrode formed on a base substrate, the pixel electrode being electrically connected with a drain electrode of the thin film transistor,wherein
the array substrate further comprises a light-shielding pattern provided above the thin film transistor;
the array substrate further comprises: a passivation layer provided between the thin film transistor and the pixel electrode, and a passivation layer via hole penetrating the passivation layer;
the array substrate further comprises a light-shielding conductive metal layer formed of a same material as the light-shielding pattern, and an entirety of the light-shielding conductive metal layer is provided in the passivation layer via hole; and
the pixel electrode is electrically connected with the drain electrode of the thin film transistor through the light-shielding conductive metal layer.

US Pat. No. 10,170,503

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL PANEL

Wuhan China Star Optoelec...

1. A thin film transistor array substrate, comprising: a substrate, a silicon thin film transistor formed on the substrate, an oxide semiconductor transistor, and a capacitor; the silicon thin film transistor and the oxide semiconductor transistor having a top gate structure; the capacitor and the silicon thin film transistor or the capacitor and the oxide semiconductor transistor being overlapping arrangement;wherein, the thin film transistor array substrate comprises:
a polysilicon layer and a semiconductor oxide layer provided and spaced on the substrate;
a gate insulating layer covering the polysilicon layer and the semiconductor oxide layer;
a first gate, a first metal layer, and a second gate provided and spaced on the gate insulating layer, the first gate being provided on the polysilicon layer, the second gate being provided on the semiconductor oxide layer;
an etch stop layer covering the first gate, the first metal layer, and the second gate, the etch stop layer comprising a first insulating layer and a second insulating layer provided by stacking;
a source-drain metal layer provided on the etch stop layer, the source-drain metal layer comprising a first source, a first drain, a second source, and a second drain, the first source and the first drain being respectively contacted with the polysilicon layer, the second source and the second drain being respectively contacted with the semiconductor oxide layer;
wherein, the polysilicon layer, the gate insulating layer, the first gate, the etch stop layer, the first source, and the first drain form the silicon thin film transistor; the semiconductor oxide layer, the gate insulating layer, the second gate, the etch stop layer, the second source, and the second drain form the oxide semiconductor transistor;
wherein, the silicon thin film transistor further comprises a floating gate;
wherein, the floating gate is provided between the first insulating layer and the second insulating layer, the floating gate is located on the first gate;
wherein, the first gate and the second gate are formed using the same mask process.

US Pat. No. 10,170,502

TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. A transistor array panel comprising:a substrate;
a buffer layer positioned on the substrate;
a semiconductor layer positioned on the buffer layer;
an intermediate insulating layer positioned on the semiconductor layer;
an upper conductive layer positioned on the intermediate insulating layer;
a lower conductive layer positioned between the substrate and the buffer layer,
wherein the semiconductor layer includes a first contact hole,
wherein the intermediate insulating layer includes a second contact hole positioned in an overlapping relationship with the first contact hole,
wherein the upper conductive layer is in contact with a side surface of the semiconductor layer in the first contact hole,
wherein the buffer layer comprises a third contact hole positioned over and exposing the lower conductive layer,
wherein the intermediate insulating layer comprises a fourth contact hole positioned in an overlapping relationship with the third contact hole,
wherein the lower conductive layer comprises a different material from a material of the semiconductor layer, and
wherein the upper conductive layer is in contact with an upper surface of the buffer layer in the fourth contact hole, and is in contact with an upper surface of the lower conductive layer in the third contact hole.

US Pat. No. 10,170,501

DISPLAY PANEL

INNOLUX CORPORATION, Mia...

1. A display panel, comprising:a substrate comprising a display region and a non-display region adjacent to the display region; and
a thin film transistor disposed on the non-display region of the substrate, wherein the thin film transistor comprises:
a semiconductor layer disposed over the substrate;
a first insulating layer disposed over the semiconductor layer;
a first metal layer disposed over the first insulating layer, and the first metal layer comprises a first branch portion and a second branch portion, wherein the first branch portion and the second branch portion are electrically connected to each other;
a second insulating layer disposed over the first insulating layer;
a plurality of first via holes and a plurality of second via holes penetrating through the first insulating layer and the second insulating layer, wherein the first branch portion and the second branch portion are disposed between the plurality of first via holes and the second via holes; and
a second metal layer disposed over the second insulating layer, wherein the second metal layer comprises a first portion electrically connected to the semiconductor layer through the plurality of first via holes and a second portion electrically connected to the semiconductor layer through the plurality of second via holes,
wherein a minimum distance between one of the first via holes and the first branch portion is a first distance, and a minimum distance between one of the second via holes and the second branch portion is a second distance, and the second distance is different from the first distance,
wherein the first metal layer serves as a gate electrode of the thin film transistor and the second metal layer serves as a source/drain electrode of the thin film transistor.

US Pat. No. 10,170,500

TRANSISTOR, LIQUID CRYSTAL DISPLAY DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:a transistor comprising a gate electrode, a source electrode, a drain electrode, and a semiconductor layer;
a first wiring electrically connected to the gate electrode, the first wiring extending in a first direction;
a second wiring electrically connected to the source electrode, the second wiring extending in a second direction and intersecting the first wiring;
a pixel electrode electrically connected to the drain electrode; and
a capacitor wiring having a first part extending in parallel with the first direction, and second and third parts each extending in parallel with the second direction,
wherein the pixel electrode has a first edge portion overlapping with the first part of the capacitor wiring, a second edge portion overlapping with the second part of the capacitor wiring, and a third edge portion overlapping with the third part of the capacitor wiring,
wherein the semiconductor layer overlaps with the first wiring, the second wiring, the pixel electrode, and the capacitor wiring, and
wherein the semiconductor layer overlaps with an entirety of the pixel electrode.

US Pat. No. 10,170,499

FINFET DEVICE WITH ABRUPT JUNCTIONS

International Business Ma...

1. A method of forming a FinFET device comprising:providing a plurality of semiconductor fins on a surface of an insulator layer;
forming a plurality of gate structures orientated perpendicular to and straddling each semiconductor fin of said plurality of semiconductor fins;
providing a dielectric spacer on vertical sidewalls of each gate structure;
removing, entirely by an anisotropic etch, an entirety of each semiconductor fin and a portion of said insulator layer, not protected by said gate structures and said dielectric spacers, wherein said removing provides semiconductor fin portions located on pedestal insulator portions of said insulator layer;
forming a source-side doped semiconductor material portion on one exposed vertical sidewall of each semiconductor fin portion and a drain-side doped semiconductor portion on another exposed vertical sidewall of each semiconductor fin portion; and
diffusing, by annealing, a dopant from said source-side doped semiconductor material portion into each semiconductor fin portion to form a source region along an entirety of said one exposed vertical sidewall of each semiconductor fin portion, and a dopant from said drain-side doped semiconductor material portion into each semiconductor fin portion to form a drain region along an entirety of said another exposed vertical sidewall of each semiconductor fin portion, said source region and said drain region are laterally separated from each other by a channel region of said semiconductor fin portion, and wherein a first junction between the source region and the channel region has a first dopant concentration gradient of less than 6 nm per decade, and a second junction between the drain region and the channel region has a second dopant concentration gradient of less than 6 nm per decade.

US Pat. No. 10,170,498

STRAINED CMOS ON STRAIN RELAXATION BUFFER SUBSTRATE

International Business Ma...

1. A method for fabricating a FinFET device comprising:providing a first long silicon fin for n-type FinFET devices and a first long silicon germanium fin for p-type FinFET devices on a strain relaxation buffer (SRB) substrate;
cutting the first long silicon fin forming a first and a second cut silicon fin, each of the first and second cut silicon fins having a vertical face at a fin end of the respective cut silicon fin, wherein the vertical faces of the first and second cut silicon fins are oriented facing each other;
cutting the first long silicon germanium fin forming a first and a second cut silicon germanium fins, each of the first and the second cut silicon germanium cut fin having a vertical face at a fin end of the respective cut silicon germanium fin, wherein the vertical faces of the first and second cut silicon germanium fins are oriented facing each other;
forming a tensile dielectric structure which bridges the vertical faces of the first and second cut silicon fins to maintain tensile strain in the first and second cut silicon fins; and
forming a compressive dielectric structure which bridges the vertical faces of the first and second cut silicon germanium fins to maintain compressive strain in the first and second cut silicon germanium fins.

US Pat. No. 10,170,497

METHOD FOR MANUFACTURING AN ELECTRONIC DEVICE AND METHOD FOR OPERATING AN ELECTRONIC DEVICE

1. A method for manufacturing an electronic device, the method comprising:providing a carrier comprising a hollow chamber structure within the carrier;
forming a first trench structure extending from a surface of the carrier to the hollow chamber structure such that an electrically isolated region is formed over the hollow chamber structure; and
forming at least one second trench structure extending from the surface of the carrier into a second region of the carrier, the second region of the carrier being laterally adjacent to the electrically isolated region, the second trench structure being at least a part of an electronic component provided in the second region of the carrier.

US Pat. No. 10,170,496

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a cell structure comprising alternately stacked first conductive patterns and first interlayer insulating layers enclosing a channel layer;
a source coupling structure physically separated from the cell structure by a slit and comprising alternately stacked second conductive patterns and second interlayer insulating layers; and
a source discharge transistor coupled to the source coupling structure.

US Pat. No. 10,170,495

STACKED MEMORY DEVICE, OPTICAL PROXIMITY CORRECTION (OPC) VERIFYING METHOD, METHOD OF DESIGNING LAYOUT OF STACKED MEMORY DEVICE, AND METHOD OF MANUFACTURING STACKED MEMORY DEVICE

Samsung Electronics Co., ...

1. A method of manufacturing a stacked memory device, the method comprising:designing a layout of the stacked memory device, the layout including a first pattern;
calculating value of shift of the first pattern according to a first location of the first pattern in the layout;
obtaining a difference value between the first location of the first pattern and a second location of a second pattern formed through a first optical proximity correction (OPC) with respect to the first pattern;
determining, by a processor that executes software instructions, whether a second OPC is to be performed, based on the value of shift and the difference value;
when the processor determines that the second OPC is to be performed, forming a third pattern through the second OPC;
forming a mask, based on the second pattern or third pattern formed through the second OPC; and
forming the stacked memory device through a lithographic process using the mask.

US Pat. No. 10,170,494

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A stacked semiconductor memory device comprising:a stacked body comprising:
a plurality of underlying metal films comprising:
a tantalum-aluminum film having an aluminum content of more than 50 atomic % and less than 85 atomic %,
a tungsten-zirconium film having a zirconium content of less than 40 atomic %, a tungsten-titanium film having a titanium content of less than 80 atomic %, or
a tungsten film;
a plurality of metal films provided on the underlying metal films and in contact with the underlying metal films, the metal films containing at least one of tungsten and molybdenum, and having a main orientation of (100) or (111); and
a plurality of insulator films,
wherein
the underlying metal films are provided between a lower surface of the metal films and the insulator films, and the underlying metal films are not provided on an upper surface of the metal-films, and
at least one of the plurality of insulator films contacts at least one of the plurality of underlying metal films and at least one the plurality of metal films.

US Pat. No. 10,170,493

ASSEMBLIES HAVING VERTICALLY-STACKED CONDUCTIVE STRUCTURES

Micron Technology, Inc., ...

1. An assembly, comprising:a stack of alternating first and second levels; the first levels comprising insulative material, and the second levels comprising conductive material; the assembly including channel material structures extending through the stack, and including insulative panel structures extending through the stack; the conductive material within the second levels having outer edges; the outer edges having proximal regions near the insulative panel structures and distal regions spaced from the insulative panel structures by the proximal regions; and
interface material along the outer edges of the conductive material, the interface material having a first composition along the proximal regions of the outer edges, and having a second composition along the distal regions of the outer edges; the first composition being different than the second composition.

US Pat. No. 10,170,492

MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A memory device, comprising:a semiconductor substrate;
a first conductive layer, disposed on the semiconductor substrate;
a plurality insulating layers, disposed on the first conductive layer;
a plurality of second conductive layers, alternatively stacked with the insulating layers and insulated from the first conductive layer;
at least one contact plug comprising a first conductive material, passing through the insulating layers and the second conductive layers, insulated from the second conductive layers and electrically contacting to the first conductive layer; and
at least one dummy plug, formed in an opening passing through a bottommost layer of the insulating layers and the second conductive layers, corresponding to the at least one contact plug, wherein the at least one dummy plug comprises a dielectric isolation layer formed on a sidewall and a bottom of the opening and a second conductive material fully filling the opening and insulated from the second conductive layers and the first conductive layer.

US Pat. No. 10,170,491

MEMORY INCLUDING BLOCKING DIELECTRIC IN ETCH STOP TIER

Micron Technology, Inc., ...

1. A memory comprising:a vertical pillar coupled to a source; and
a dielectric etch stop tier over the source, the dielectric etch stop tier comprising a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the dielectric etch stop tier and separating the dielectric etch stop tier into multiple dielectric tiers.

US Pat. No. 10,170,490

MEMORY DEVICE INCLUDING PASS TRANSISTORS IN MEMORY TIERS

Micron Technology, Inc., ...

1. An apparatus comprising:a piece of semiconductor material formed over a substrate;
a pillar extending through the piece of semiconductor material;
a select gate located along a first portion of the pillar;
memory cells located along a second portion of the pillar; and
transistors coupled to the select gate through a portion of the piece of semiconductor material, the transistors including sources and drains, the transistors including gates electrically uncoupled to each other, and at least a portion of the piece of semiconductor material forms the sources and drains of the transistors, and a portion of the select gate.

US Pat. No. 10,170,489

HIGH-VOLTAGE TRANSISTOR HAVING SHIELDING GATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:first, second, third, and fourth high-voltage transistors arranged on a main surface of a semiconductor substrate, the first and second high-voltage transistors being adjacent each other in a gate-width direction, the third and fourth high-voltage transistors being adjacent each other in the gate-width direction, the first and third high-voltage transistors being adjacent each other in a gate-length direction, the second and fourth high-voltage transistors being adjacent each other in the gate-length direction, and each of the transistors having a gate electrode, and a gate electrode contact formed on the gate electrode; and
a conductive line provided on a portion of an element isolation region, the conductive line positioned between the first and third transistors and between the second and fourth transistors,
wherein the gate electrode contact is formed on a fringe portion formed by extending an end portion of the gate electrode onto the element isolation region in the gate-width direction.

US Pat. No. 10,170,488

NON-VOLATILE MEMORY OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANF...

1. A semiconductor device, comprising:a substrate having a surface;
a plurality of isolation structures disposed in the substrate to at least define a first region, a second region, and a third region on the substrate;
a floating gate memory cell disposed in the first region, wherein the floating gate memory cell comprises:
an erase gate structure disposed on the surface of the substrate;
a first floating gate structure and a second floating gate structure recessed in the substrate and located at two opposite sides of the erase gate structure;
a first word line disposed on the surface of the substrate, wherein the first word line is adjacent to the first floating gate structure opposite to the erase gate structure;
a common source disposed in the substrate between the first floating gate structure and the second floating gate structure;
a second word line disposed on the surface of the substrate, wherein the second word line is adjacent to the second floating gate structure opposite to the erase gate structure;
a first spacer disposed between the first floating gate structure and the first word line; and
a second spacer disposed between the second floating gate structure and the second word line;
a first device disposed in the second region; and
a second device disposed in the third region.

US Pat. No. 10,170,487

DEVICE HAVING AN INTER-LAYER VIA (ILV), AND METHOD OF MAKING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A three-dimensional integrated circuit comprising:a first transistor on a first level;
a word line coupled to the first transistor;
a first via coupled to the first transistor;
a second transistor on a second level different from the first level;
another word line coupled to the second transistor; and
a second via coupled between the first transistor and the second transistor.

US Pat. No. 10,170,486

SEMICONDUCTOR STORAGE DEVICE COMPRISING PERIPHERAL CIRCUIT, SHIELDING LAYER, AND MEMORY CELL ARRAY

Semiconductor Energy Labo...

1. A semiconductor storage device comprising:a first transistor;
a conductive film over the first transistor; and
a plurality of second transistors each comprising a channel region,
wherein a channel region of the first transistor comprises silicon,
wherein each of the plurality of channel regions of second transistors comprises an oxide semiconductor, and
wherein entirety of the plurality of second transistors overlaps with the conductive film.

US Pat. No. 10,170,485

THREE-DIMENSIONAL STACKED JUNCTIONLESS CHANNELS FOR DENSE SRAM

International Business Ma...

1. A method, comprising:forming a heteroepitaxial stack of layers of a p-doped material, an n-doped material, and a sacrificial material;
patterning the heteroepitaxial stack;
forming a dummy gate on the patterned heteroepitaxial stack;
forming sidewall spacers on the dummy gate;
removing the sacrificial material from between the layers of p-doped material and n-doped material;
depositing a dielectric isolation material adjacent the sidewall spacers and between the layers of p-doped material and n-doped material;
removing the dummy gate to form a gate opening;
removing the dielectric isolation material from between the layers of p-doped material and n-doped material;
depositing a gate dielectric on surfaces in the gate opening and on the layers of p-doped material and n-doped material under the gate opening;
depositing a workfunction metal on the gate dielectric;
filling the gate opening with a fill metal; and
forming contacts to the layers of p-doped material and n-doped material;
wherein the deposited gate dielectric on the layers of p-doped material and n-doped material and the deposited workfunction metal define junctionless field effect transistor devices.

US Pat. No. 10,170,484

INTEGRATED CIRCUIT STRUCTURE INCORPORATING MULTIPLE GATE-ALL-AROUND FIELD EFFECT TRANSISTORS HAVING DIFFERENT DRIVE CURRENTS AND METHOD

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming, on a substrate that comprises a first semiconductor material, a multi-layer stack comprising alternating layers of a second semiconductor material and the first semiconductor material;
forming a recess in the multi-layer stack such that a first area of the multi-layer stack has more layers of the first semiconductor material than a second area of the multi-layer stack;
filling the recess with a sacrificial material;
after the filling of the recess with the sacrificial material, patterning the multi-layer stack into multi-layer fins comprising at least a first fin in the first area and a second fin in the second area, wherein the first fin comprises the alternating layers and wherein the second fin comprises the sacrificial material above at least one layer of the first semiconductor material; and
forming transistors comprising: a first transistor comprising multiple first nanoshapes for multiple first channel regions formed using multiple layers of the first semiconductor material in the first fin; and a second transistor comprising at least one second nanoshape for at least one second channel region formed using the at least one layer of the first semiconductor material in the second fin,
wherein the first transistor is formed so as to have a first number of the first nanoshapes and the second transistor is formed so as to have a second number of the second nanoshapes that is less than the first number, and
wherein each second nanoshape is essentially co-planar with one of the first nanoshapes.

US Pat. No. 10,170,483

SEMICONDUCTOR DEVICE, STATIC RANDOM ACCESS MEMORY CELL AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) cell comprising:two pull-up (PU) transistors, two pass-gate (PG) transistors, and two pull-down (PD) transistors, wherein the PU transistors and the PD transistors are configured to form two cross-coupled inverters, the PG transistors are electrically connected to the cross-coupled inverters, and at least one of the PU transistors, the PG transistors, and the PD transistors comprises:
a semiconductor fin comprising at least one channel portion;
an epitaxy structure over the semiconductor fin;
at least one isolation structure adjacent to the semiconductor fin; and
a plurality of dielectric fin sidewall structures on opposite sides of the epitaxy structure and over the isolation structure.

US Pat. No. 10,170,481

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor memory device comprising:a substrate, wherein the substrate comprises a memory cell region and a periphery region;
a plurality of bit lines, disposed on the substrate, within the memory cell region;
a gate, disposed on the substrate, within the periphery region;
a spacer layer covering the bit lines and a sidewall of the gate; and
a first spacer disposed on the sidewall and an opposite sidewall of the gate and covering the spacer layer.

US Pat. No. 10,170,480

METHODS FOR MANUFACTURING A FIN-BASED SEMICONDUCTOR DEVICE INCLUDING A METAL GATE DIFFUSION BREAK STRUCTURE WITH A CONFORMAL DIELECTRIC LAYER

TAIWAN SEMICONDUCTOR MANU...

16. A method of forming a fin-like field-effect transistor (FinFET) device, the method comprising:forming a first active region and a second active region on a substrate, such that the first active region and the second active region are spaced apart from each other in a first direction;
forming a first group of fins in the first active region and a second group of fins in the second active region, such that each fin of the first and second groups of fins extends along a second direction substantially perpendicular to the first direction;
forming one or more gates over the first active region and the second active region along the first direction, the one or more gates including a first isolation gate and a functional gate;
forming a first sidewall spacer along the first isolation gate; and
forming a source/drain feature on a side of the first sidewall spacer and extending into the substrate to a first depth,
wherein the first isolation gate includes a dielectric layer and a metal gate layer, the first isolation gate formed in a trench in the substrate, the dielectric layer conformed to a side surface of the first sidewall spacer and extending along the first sidewall spacer and into the substrate such that the dielectric layer physically contacts the first sidewall spacer, the source/drain feature, and the substrate at a bottom of the trench, the metal gate layer extending into the substrate to a second depth that is greater than the first depth.

US Pat. No. 10,170,479

FABRICATION OF VERTICAL DOPED FINS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTORS

International Business Ma...

1. A complementary metal oxide semiconductor (CMOS) device with punch-through stops/wells, comprising:one or more vertical fin(s) on a substrate in a first region and one or more vertical fin(s) on the substrate in a second region, wherein the first region is adjacent to the second region;
a first dopant source on the one or more vertical fin(s) in the first region, wherein the first dopant source extends along a portion of the length of each of the one or more vertical fins in the first region;
a second dopant source on the one or more vertical fin(s) in the second region, wherein the second dopant source extends along a portion of the length of each of the one or more vertical fins in the second region;
a first doped region in the substrate forming a first punch-through stop/well below the first dopant source, wherein the first punch-through stop/well includes a first dopant at a concentration in the range of about 1×1017/cm3 to about 1×1019/cm3;
a second doped region in the substrate forming a second punch-through stop/well below the second dopant source, wherein the second punch-through stop/well includes a second dopant at a concentration in the range of about 1×1017/cm3 to about 1×1019/cm3;
an isolation spacer on the first dopant source and the second dopant source, wherein the thickness of the first dopant source and second dopant source are in the range of about 50 nm to about 150 nm; and
a gate dielectric layer on at least a portion of the isolation spacer, at least a portion of the one or more vertical fins) in the first region, and at least a portion of the one or more vertical fin(s) in the second region.

US Pat. No. 10,170,478

SPACER FOR DUAL EPI CMOS DEVICES

INTERNATIONAL BUSINESS MA...

1. A method of making a semiconductor comprising:forming a first semiconductor device comprising two or more first gate stacks formed on a first substrate, and forming a second semiconductor device comprising two or more second gate stacks formed on the first substrate, the first semiconductor device including a first fin region having first source-drain areas and the second semiconductor device including a second fin region having second source-drain areas, the first source-drain area and the second source drain area each comprising a horizontal surface on an upper surface of the respective source-drain area:
depositing a wet-etch resistant spacer material on the first and second semiconductor devices;
removing a portion of the wet-etch resistant spacer material from the first fin region and the second fin region with anisotropic spacer reactive ion etch such that remaining portions of the wet-etch resistant spacer material form first wet-etch resistant spacers having a first thickness on the first semiconductor device and second wet-etch resistant spacers having a second thickness equal to the first thickness on the second semiconductor device;
depositing a first nitride liner on the first and second semiconductor devices;
depositing a dielectric layer on the first nitride liner;
planarizing the dielectric layer;
selectively removing the dielectric layer from between the first wet-etch resistant spacer material in the first fin region and the second wet-etch resistant spacer in the second fin region;
depositing a second nitride liner on the first and second semiconductor devices and selectively removing the second nitride liner from the first semiconductor device;
growing a first epitaxial layer on the first source-drain area by an epitaxial growth process such that the first epitaxial layer extends the length of the first source-drain area and covers the horizontal surface of the first source-drain area except areas covered by the first gate stack and the first wet-etch resistant spacer material;
depositing a third nitride liner on the first and second semiconductor devices and selectively removing the third nitride liner from the second semiconductor device; and
growing a second epitaxial layer on the second source-drain area by a second epitaxial growth process.

US Pat. No. 10,170,477

FORMING MOSFET STRUCTURES WITH WORK FUNCTION MODIFICATION

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising:a first transistor of a first type comprising a first channel region material and a first gate electrode, the first gate electrode comprising gate materials including a work function material and a work function modifying material; and a second transistor of a second type comprising a second channel region material and a second gate electrode, the second gate electrode comprising gate materials including the work function material; wherein the work function modifying material is lanthanum oxide; the work function modifying material is applied to a dielectric layer; the work function material for the first and second gate electrodes are identical; and the work function modifying material is configured to change the threshold voltage of the first transistor; and an insulator layer between the first transistor and the second transistor, wherein a first portion of the insulator layer includes the work function material and a second portion of the insulator layer includes the work function material and the work function modifying material, wherein the first channel region and the second channel region extends through a horizontal insulator layer.

US Pat. No. 10,170,476

STRUCTURE AND METHOD OF LATCHUP ROBUSTNESS WITH PLACEMENT OF THROUGH WAFER VIA WITHIN CMOS CIRCUITRY

INTERNATIONAL BUSINESS MA...

1. A method of manufacturing a semiconductor structure, comprising:forming an N-well in a p-type substrate;
forming a P-well in the substrate;
forming a PFET device on the N-well at a front side of the substrate;
forming an NFET device on the P-well at the front side of the substrate;
forming an isolation region at the front side of the substrate and contacting both the N-well and the P-well; and
forming a through wafer via (TWV) extending from a back side of the substrate to a bottom surface of the isolation region,
wherein the P-well is devoid of a substrate contact at the front side of the substrate; and
the N-well comprises an N-well contact at the front side of the substrate.

US Pat. No. 10,170,475

SILICON-ON-NOTHING TRANSISTOR SEMICONDUCTOR STRUCTURE WITH CHANNEL EPITAXIAL SILICON REGION

INTERNATIONAL BUSINESS MA...

1. A method of forming a transistor on a silicon substrate, the method comprising:forming a gate stack structure on an epitaxial silicon region disposed on a silicon substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and
growing a raised epitaxial source and drain from the silicon substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure.

US Pat. No. 10,170,474

TWO DIMENSION MATERIAL FIN SIDEWALL

International Business Ma...

1. A semiconductor structure fabrication method comprising:forming neighboring fins associated with a semiconductor substrate, the neighboring fins separated by a fin well;
forming a fin cap upon each neighboring fin;
forming a well-plug within a bottom portion of the fin well such that sidewall portions of the neighboring fins are exposed to an upper portion of the fin well; and
forming a 2D material upon the sidewall portions of the neighboring fins.

US Pat. No. 10,170,473

FORMING LONG CHANNEL FINFET WITH SHORT CHANNEL VERTICAL FINFET AND RELATED INTEGRATED CIRCUIT

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit (IC), comprising:a first transistor structure including:
a semiconductor substrate;
a semiconductor fin extending from the semiconductor substrate;
a doped first source/drain region in the semiconductor substrate under a first end of the semiconductor fin;
a doped second source/drain region in the semiconductor substrate under a second, opposing end of the semiconductor fin, the second source/drain region separated from the first source/drain region by a portion of the semiconductor substrate having an opposite doping from that of the first and second source/drain region; and
a surrounding gate extending about the semiconductor fin above the semiconductor substrate, a lower surface of the surrounding gate isolated from the semiconductor substrate by a first spacer.

US Pat. No. 10,170,472

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

16. An integrated circuit device, comprising:a substrate comprising adjacent first and second substrate regions;
active fins protruding from the substrate in the first and second substrate regions and extending parallel to one another in a first direction;
first and second gate electrodes extending co-linearly in a second direction that intersects the first direction, wherein the first and second gate electrodes are electrically isolated and extend on first and second active fins of the active fins in the first substrate region to define first and second transistors, respectively;
first and second wordlines extending in parallel on the first and second substrate regions; and
first and second wordline contacts connecting the first and second gate electrodes to the first and second wordlines, respectively,
wherein the first and second transistors in the first substrate region are between the first and second wordline contacts.

US Pat. No. 10,170,471

BULK FIN FORMATION WITH VERTICAL FIN SIDEWALL PROFILE

International Business Ma...

1. A semiconductor device, comprising:a base layer; and
a plurality of fins atop the base layer, wherein:
each fin comprises:
an undoped silicon oxide fin layer atop the base layer;
a doped silicon oxide fin layer atop the undoped silicon oxide fin layer;
a silicon fin layer atop the doped silicon oxide fin layer; and
a hard mask cap atop the silicon fin layer;
each fin has a uniform width along a height of the respective fin along a first direction;
the height spans from an upper surface of the base layer to an upper surface of the hard mask cap; and
the first direction is a direction that intersects a first fin and a second fin of the plurality of fins.

US Pat. No. 10,170,470

SWITCHING DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A switching device, comprising:a semiconductor substrate;
a plurality of gate trenches provided in an upper surface of the semiconductor substrate;
bottom insulating layers covering bottom surfaces of the gate trenches;
gate insulating layers covering side surfaces of the gate trenches; and
gate electrodes arranged in the gate trenches and insulated from the semiconductor substrate by the bottom insulating layers and the gate insulating layers,
wherein
a device region is a region in the upper surface in which the plurality of gate trenches is provided,
the device region includes a peripheral portion provided at a periphery of the device region and a center portion surrounded by the peripheral portion, the gate insulating layers being located in the peripheral portion and the center portion,
the gate insulating layers in the center portion have a first thickness and a first dielectric constant,
one or more of the gate insulating layers in the peripheral portion has, within at least a part of the peripheral portion, a second thickness thicker than the first thickness and a second dielectric constant greater than the first dielectric constant, and
the semiconductor substrate comprises:
a first region being of a first conductivity type and in contact with the gate insulating layers in the center portion and the peripheral portion;
a body region being of a second conductivity type and in contact with the gate insulating layers under the first region in the center portion and the peripheral portion; and
a second region being of the first conductivity type and in contact with the gate insulating layers under the body region in the center portion and the peripheral portion.

US Pat. No. 10,170,469

VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

International Business Ma...

1. A semiconductor structure comprising:a first vertical field-effect transistor comprising a first threshold voltage; and
at least a second vertical field-effect transistor comprising a second threshold voltage that is different from the first threshold voltage,
wherein each of the first vertical field-effect transistor and the second vertical field-effect transistor comprises
a source layer and a drain layer, wherein each drain layer is formed in a region of the first vertical field-effect transistor and second vertical field-effect transistor, respectively, above the source layer,
substrate in contact with the source layer,
a first spacer layer on the source layer,
a second spacer layer, where a portion of the drain layer extends over the second spacer, and
metal gate in contact with sidewalls of the epitaxially grown channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer.

US Pat. No. 10,170,468

SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURING THE SAME

VANGUARD INTERNATIONAL SE...

11. A method for manufacturing a semiconductor structure, comprising:providing a semiconductor substrate with a first conductivity type;
forming a first well in the semiconductor substrate, wherein the first well has a second conductivity type;
forming a first region in the first well, wherein the first region has the first conductivity type;
forming a second region in the first well, wherein the second region has the first conductivity type, and a dopant concentration of the first region is higher than a dopant concentration of the second region;
forming a second well in the first region, wherein the second well has the first conductivity type;
forming a first doped region in the first region, wherein the first doped region has the second conductivity type that is different than the first conductivity type;
forming a second doped region in the second well, wherein the second doped region has the first conductivity type;
forming a third doped region in the second region, wherein the third doped region has the first conductivity type; and
forming a fourth doped region in the first region, wherein the fourth doped region has the second conductivity type.

US Pat. No. 10,170,467

THREE DIMENSIONAL MEMORY DEVICE AND METHOD FOR FABRICATING THE SAME

MACRONIX INTERNATIONAL CO...

1. A three dimensional (3D) semiconductor memory device, comprising:a semiconductor substrate, having a first protruding portion;
a first transistor formed in the semiconductor substrate, comprising:
a first source line, disposed in the semiconductor substrate and partially extending below the first protruding portion;
a first gate line configured to surround and cover the first protruding portion and electrically separated from the first source line and the first protruding portion; and
a first drain electrode formed on and connecting to the first protruding portion;
a plurality of conductive planes stacked on the semiconductor substrate and electrically separated from each other;
a first conductive pillar passing through the conductive planes and connecting to the first drain electrode;
a first memory layer disposed between the conductive planes and the first conductive pillar; and
a plurality of memory cells formed at a plurality points of intersection correspondingly formed between the conductive planes, the first conductive pillar and the memory layer; and connected in series by the first conductive pillar.

US Pat. No. 10,170,466

DEVICE HAVING AN ACTIVE CHANNEL REGION

HEWLETT-PACKARD DEVELOPME...

1. A transistor comprising:a substrate;
a drain in the substrate;
a source in the substrate;
a channel between the drain and the source, the channel surrounding the drain and having a channel length to width ratio; and
a gate over the channel to provide an active channel region that has an active channel region length to width ratio that is greater than the channel length to width ratio.

US Pat. No. 10,170,465

CO-FABRICATION OF VERTICAL DIODES AND FIN FIELD EFFECT TRANSISTORS ON THE SAME SUBSTRATE

International Business Ma...

9. A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:forming a bottom spacer layer on a substrate;
forming a dummy gate layer on the bottom spacer layer;
forming a top spacer layer on the dummy gate layer;
forming one or more fin trenches, where at least one of the one or more fin trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a vertical fin in at least one of the one or more fin trenches;
forming one or more diode trenches, where at least one of the one or more diode trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches; and
forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, wherein the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

US Pat. No. 10,170,464

COMPOUND SEMICONDUCTOR DEVICES HAVING BURIED RESISTORS FORMED IN BUFFER LAYER

International Business Ma...

1. A semiconductor device, comprising:a semiconductor substrate;
a buffer layer disposed on the semiconductor substrate, wherein the buffer layer comprises a first buffer layer and a second buffer layer, wherein the first buffer layer comprises a first layer of epitaxial compound semiconductor material that is epitaxially grown on the semiconductor substrate, wherein the second buffer layer comprises a second layer of epitaxial compound semiconductor material that is epitaxially grown on the first buffer layer, wherein the first and second layers of epitaxial compound semiconductor material are formed of different compositions of compound semiconductor material;
an active device layer disposed on the buffer layer, wherein the active device layer comprises a layer of epitaxial semiconductor material that is epitaxially grown on the buffer layer;
a contact plug disposed within a contact opening formed in the second buffer layer; and
a buried resistor disposed within a cavity formed within the first buffer layer below the second buffer layer and the active device layer, wherein a portion of the cavity within the first buffer layer comprises an undercut region which undercuts a portion of the second buffer layer surrounding the contact plug within the contact opening formed in the second buffer layer such that a portion of the buried resistor within the undercut region of the cavity is disposed underneath a bottom surface of the second buffer layer;
wherein the contact plug is connected to the buried resistor;
wherein the buffer layer serves to match a lattice constant of the semiconductor substrate to a lattice constant of the layer of epitaxial semiconductor material of the active device layer.

US Pat. No. 10,170,463

BIPOLAR TRANSISTOR COMPATIBLE WITH VERTICAL FET FABRICATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating two transistors, comprising:forming a first semiconductor fin and a second semiconductor fin, where each of the first and second semiconductor fins comprises a doped lower portion;
forming lower spacers around the first and second semiconductor fins, the lower spacer around the first semiconductor fin having a height lower than a height of the lower spacer around the second semiconductor fin;
forming a gate stack around the first semiconductor fin and the second semiconductor fin;
wherein the height of the lower spacer around the first semiconductor fin rises below a level of the doped lower portion of the first semiconductor fin and wherein the height of the lower spacer around the second semiconductor fin rises above a level of the doped lower portion of the second semiconductor fin;
forming an upper spacer around the first and second semiconductor fin and over the gate stacks;
etching away the gate stack around the second semiconductor fin; and
forming an extrinsic base around the second semiconductor fin and under the upper spacer in a region exposed by etching away the gate stack.

US Pat. No. 10,170,462

DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising a display panel including an active area where an image is displayed and a pad area corresponding to a non-display area, the display device comprising:a first substrate and a second substrate, which face each other;
an organic light emitting diode arranged on the first substrate in the active area;
a signal pad arranged on the first substrate in the pad area;
a connection electrode connected with one side of the signal pad; and
a flexible circuit film connected with the connection electrode,
wherein the signal pad includes a plurality of lines arranged by interposing an insulating film therebetween, and the plurality of lines are electrically connected with each other, and
wherein the signal pad includes at least two lines of a first line arranged on the same layer as a gate line arranged in the active area, a second line arranged on the same layer as a data line arranged in the active area, and a third line arranged on the same layer as a pixel electrode arranged in the active area.

US Pat. No. 10,170,461

ESD HARD BACKEND STRUCTURES IN NANOMETER DIMENSION

Taiwan Semiconductor Manu...

1. A method of testing a semiconductor device, the semiconductor device comprising:a semiconductor substrate;
a interconnect structure disposed over the semiconductor substrate;
a first conductive pad disposed over the interconnect structure;
a second conductive pad disposed over the interconnect structure and spaced apart from the first conductive pad;
a third conductive pad disposed over the interconnect structure and spaced apart from the first and second conductive pads;
a fourth conductive pad disposed over the interconnect structure and spaced apart from the first, second, and third conductive pads;
a first ESD protection element, including a first fuse, electrically coupled between the first and second conductive pads;
a second ESD protection element, including a second fuse, electrically coupled between the third and fourth conductive pads;
a first device under test (DUT) electrically coupled between the first and third conductive pads; and
a second DUT electrically coupled between the second and fourth conductive pads;
the method comprising:
subjecting the semiconductor device to an electrostatic discharge (ESD) prone environment during manufacturing or testing of the semiconductor device;
after subjecting the semiconductor device to the ESD prone environment, blowing away the first fuse and blowing away the second fuse; and
after blowing away the first and second fuses, conducting an electro-migration test by applying electrical stress to the first DUT or to the second DUT.

US Pat. No. 10,170,460

VOLTAGE BALANCED STACKED CLAMP

International Business Ma...

1. An apparatus for balancing voltages, comprising:a voltage supply pin operatively connected to a voltage divider, wherein the voltage supply pin supplies a total voltage to the voltage divider;
a stacked circuit operatively connected to the voltage divider, wherein the stacked circuit comprises a first layer and a second layer, wherein the first layer is not coupled to the second layer, and the voltage divider distributes the total voltage as to the stacked circuit;
a voltage grounder operatively connected to the voltage divider and wherein the first layer and the second layer comprise:
a group of inverters within the first layer operatively connected to a first n-type channel field effect transistor (NFET), wherein the group of inverters within the first layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the first n-type channel field effect transistor (NFET); and
a group of inverters within the second layer operatively connected to a second n-type channel field effect transistor (NFET), wherein the group of inverters within the second layer comprise:
a first inverter, a second inverter, and a third inverter, wherein
the first inverter connects the voltage divider to the second inverter, the second inverter connects to the third inverter, and wherein the third inverter connects to the second n-type channel field effect transistor (NFET); and
a third node, wherein the third node is point (principal nodes or junctions) coupled to a first p-type field effect transistor (PFET) at a gate terminal of the first PFET, the second inverter, and the third inverter of the first layer.

US Pat. No. 10,170,459

METHODS FOR AN ESD PROTECTION CIRCUIT INCLUDING A FLOATING ESD NODE

GLOBALFOUNDRIES SINGAPORE...

1. A method comprising:providing a substrate including a first-type well area in an electrostatic discharge (ESD) region;
forming a base junction of the first-type along the perimeter of the ESD region;
forming a shallow trench isolation (STI) region adjacent the base junction;
forming alternate emitter and collector junctions of a second-type adjacent the STI region, parallel to and spaced from each other by parallel additional STI regions;
forming at least one gate perpendicular to and over a collector junction;
epitaxially forming a floating ESD node of the first-type in the collector junction adjacent one side of the at least one gate; and
determining a gate-length based on a target ESD event trigger-voltage, wherein a shorter gate-length reduces the trigger-voltage such that the ESD region is activated at a lower voltage.

US Pat. No. 10,170,458

MANUFACTURING METHOD OF PACKAGE-ON-PACKAGE STRUCTURE

Powertech Technology Inc....

1. A manufacturing method of a package-on-package (POP) structure, comprising:forming a first package structure, wherein the first package structure comprises a circuit carrier and a die disposed on the circuit carrier, forming the first package structure comprising:
providing a conductive interposer on the circuit carrier, wherein the conductive interposer comprises a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die, the conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier, wherein the plate of the conductive interposer comprises a central region and a peripheral region connected to the central region, the conductive protrusion is formed in the central region and the conductive pillars are formed in the peripheral region;
encapsulating the conductive interposer by an encapsulant; and
removing a portion of the encapsulant and the plate of the conductive interposer; and
forming a second package structure on the first package structure, wherein the second package structure is electrically connected to the first package structure through the conductive interposer.

US Pat. No. 10,170,457

COWOS STRUCTURES AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:attaching a first die and a second die to an interposer;
attaching a first substrate to a first surface of the first die and a first surface of the second die, the first substrate comprising silicon, the first surface of the first die being opposite to a second surface of the first die that is attached to the interposer, and the first surface of the second die being opposite to a second surface of the second die that is attached to the interposer;
forming a plurality of electrical connectors over the interposer, each electrical connector of the plurality of electrical connectors being electrically connected to a respective through via of a plurality of through vias comprised in the interposer, wherein the first substrate physically supports the interposer during the forming of the plurality of electrical connectors;
bonding the interposer to a second substrate using the plurality of electrical connectors; and
attaching a heat dissipation lid to the second substrate, the interposer being disposed in an inner cavity of the heat dissipation lid.

US Pat. No. 10,170,456

SEMICONDUCTOR PACKAGES INCLUDING HEAT TRANSFERRING BLOCKS AND METHODS OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip and a second semiconductor chip disposed on an interconnection layer and laterally spaced apart from each other;
a heat transferring block disposed between the first and second semiconductor chips to be mounted on the interconnection layer;
an encapsulant filling spaces between the heat transferring block and the first and second semiconductor chips and covering sidewalls of the first and second semiconductor chips; and
a heat dissipation layer connected to a top surface of the heat transferring block opposite to the interconnection layer and extending to cover a top surface of the encapsulant,
wherein the heat transferring block emits heat trapped in a region of the encapsulant between the first and second semiconductor chips,
wherein the heat transferring block comprises a through via to emit the heat, and
the through via is electrically isolated from the interconnection layer and the first and second semiconductor chips.