US Pat. No. 10,141,520

COATING LIQUID FOR FORMING LIGHT EMITTING LAYER, ORGANIC ELECTROLUMINESCENT ELEMENT, METHOD FOR MANUFACTURING ORGANIC ELECTROLUMINESCENT ELEMENT, AND LIGHTING/DISPLAY DEVICE

Konica Minolta, Inc., To...

1. A coating solution for forming a luminous layer included in one or more organic layers disposed between an anode and a cathode, the coating solution comprising:a thermally-activated delayed fluorescent, compound, and
a heavy atom compound having an external heavy-atom effect to promote intersystem crossing of the thermally-activated delayed fluorescent compound from a triplet excited state to a singlet excited state to increase a fluorescent intensity,
wherein the heavy atom compound is a phosphorescent metal complex,
a lowest excited triplet energy level (T1(TADF)) of the thermally-activated delayed fluorescent compound and a lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex are within ranges allowing transfer of energy electrons therebetween,
a difference in energy between a lowest excited singlet energy level (S1(TADF)) of the thermally-activated delayed fluorescent compound and the lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex is within a range represented by Expression (1):
?0.2 eV?[S1(TADF)-T1(P)]?1.0 eV  (1), and
a difference in energy between the lowest excited triplet energy level (T1(TADF)) of the thermally-activated delayed fluorescent compound and the lowest excited triplet energy level (T1(P)) of the phosphorescent metal complex is within a range represented by Expression (3):
?0.2 eV?[T1(TADF)?T1(P)]?0.5 eV  (3)

US Pat. No. 10,141,519

COMPOUND, LIGHT EMITTING DEVICE COMPRISING SAME, AND ELECTRONIC DEVICE

LMS CO., LTD., Gyeonggi-...

1. A compound represented by the following Formula 3:
in Formula 3,
La represents a single bond, an arylene group having 6 to 30 carbon atoms, or a heteroarylene group having 2 to 30 carbon atoms,
Ra and Rb each independently represent an aryl group having 6 to 30 carbon atoms,
Rc, and Rd each independently represent hydrogen,
R1, R2, R5, R6, R7, R8, R11, and R12 each independently represent an alkyl group having 1 to 6 carbon atoms.

US Pat. No. 10,141,518

COMPOUNDS FOR ELECTRONIC DEVICES

Merck Patent GmbH, Darms...

1. A compound of a formula (I)
wherein A is, identically or differently on each occurrence, a group of the following formula (II) or (III)

wherein the dashed line emanating from the nitrogen atom represents the bond from the group A to the central benzene ring;
wherein the group HetAr including the nitrogen atom shown is, identically or differently on each occurrence, a heteroaryl group having 5 to 30 aromatic ring atoms, optionally substituted by one or more radicals R2;
wherein the group Ar1 is, identically or differently on each occurrence, an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, optionally substituted by one or more radicals R2, and wherein the two groups Ar1 may be connected via a group Y so that a ring is formed with the nitrogen atom of the group A, wherein
Y is selected from a single bond, BR2, C(R2)2, Si(R2)2, NR2, PR2, P(?O)R2, P(?S)R2, O, S, S?O, and S(?O)2; and
R1 is, identically or differently on each occurrence, CN, C(?O)R3, C(?O)OR3, C(?O)N(R3)2, P(?O)(R3)2, OSO2R3, S(?O)R3, S(?O)2R3, or a heteroaryl group selected from pyridyl, pyrazinyl, pyridazinyl, pyrimidyl and triazinyl, each of which optionally substituted by one or more radicals R3;
R2 is, identically or differently on each occurrence, H, D, F, Cl, Br, I, B(OR3)2, CHO, C(?O)R3, CR3?C(R3)2, CN, C(?O)OR3, C(?O)N(R3)2, Si(R3)3, N(R3)2, NO2, P(?O)(R3)2, OSO2R3, OR3, S(?O)R3, S(?O)2R3, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 20 C atoms, a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 20 C atoms, or an alkenyl or alkynyl group having 2 to 20 C atoms, wherein the above-mentioned groups are optionally substituted by one or more radicals R3 and wherein one or more CH2 groups in the above-mentioned groups are optionally replaced by —R3C?CR3—, Si(R3)2, C?O, C?S, C?NR3, —C(?O)O—, —C(?O)NR3—, NR3, P(?O)(R3), —O—, —S—, SO, or SO2, and wherein one or more H atoms in the above-mentioned groups are optionally replaced by D, F, Cl, Br, I, CN, or NO2, or an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R3, or an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R3, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R3, wherein two or more radicals R2 are optionally linked to one another and optionally form a ring;
R3 is, identically or differently on each occurrence, H, D, F, Cl, Br, I, B(OR4)2, CHO, C(?O)R4, CR4?C(R4)2, CN, C(?O)OR4, C(?O)N(R4)2, Si(R4)3, N(R4)2, NO2, P(?O)(R4)2, OSO2R4, OR4, S(?O)R4, S(?O)2R4, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 20 C atoms, or a branched or cyclic alkyl, alkoxy or
thioalkyl group having 3 to 20 C atoms, or an alkenyl or alkynyl group having 2 to 20 C atoms, wherein the above-mentioned groups are optionally substituted by one or more radicals R4 and wherein one or more CH2 groups in the above-mentioned groups are optionally replaced by —R4C?CR4—, —C?C—, Si(R4)2, C?O, C?S, C?NR4, —C(?O)O—, —C(?O)NR4—, NR4, P(?O)(R4), —O—, —S—, SO, or SO2, and wherein one or more H atoms in the above-mentioned groups are optionally replaced by D, F, Cl, Br, I, CN, or NO2, or an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R4, or an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R4, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, optionally substituted by one or more radicals R4, wherein two or more radicals R3 are optionally linked to one another and optionally form a ring; and
R4 is, identically or differently on each occurrence, H, D, F, or an aliphatic, aromatic or heteroaromatic organic radical having 1 to 20 C atoms, in which, in addition, one or more H atoms are optionally replaced by D or F; two or more substituents R4 are optionally linked to one another and optionally form a ring.

US Pat. No. 10,141,516

COMPOUND FOR ORGANIC ELECTRIC ELEMENT, ORGANIC ELECTRIC ELEMENT COMPRISING THE SAME AND ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound represented by Formula 1 below:
wherein,
m is an integer from 1 to 4,
n is an integer from 1 to 3,
R1 is selected from the group consisting of hydrogen, deuterium, tritium, a C6-C60 aryl group, and a fluorenyl group, and R2 is selected from the group consisting of hydrogen, deuterium, tritium, a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the aryl group, heterocyclic group, and fluorenyl group may be substituted by one or more substituents selected from the group consisting of halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group,
Ar1 is selected from the group consisting of a fluorenyl group, a C6-C60 aryl group, a C2-C20 alkenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, and a C1-C50 alkyl group, wherein the aryl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group; and the heterocyclic group, fluorenyl group, alkyl group, and alkenyl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group,
L1 is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, and a C2-C60 bivalent heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the arylene group, fluorenylene group, and heterocyclic group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group, and
Ar2 and Ar3 are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, wherein the aryl group, heterocyclic group, and fluorenyl group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, -L?-N(R?)(R?), a C1-C20 alkyl group, a C2-C20 alkenyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, and a C2-C20 heterocyclic group, wherein L? is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; and R? and R? are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, and a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P.

US Pat. No. 10,141,515

SPACE-THROUGH CHARGE TRANSFER COMPOUND, AND ORGANIC LIGHT EMITTING DIODE AND DISPLAY DEVICE USING THE SAME

LG Display Co., Ltd., Se...

1. A space-through charge transfer compound, comprising:a naphthalene core;
an electron donor moiety selected from the group consisting of carbazole and phenylcarbazole; and
an electron acceptor moiety selected from the group consisting of pyridine, diazine, triazole, and phenyl benzodiazole,
wherein the electron donor moiety and the electron acceptor moiety are combined to first and eighth positions of the naphthalene core with a benzene linker, respectively.

US Pat. No. 10,141,514

COMPOSITION AND LIGHT EMITTING DEVICE USING THE SAME

Sumitomo Chemical Company...

1. A composition comprisinga phosphorescent compound (B) having an emission spectrum whose maximum peak wavelength is from 380 nm to less than 495 nm and having no dendron represented by the formula (D-A) or (D-B), wherein the emission spectrum is obtained by measuring the PL spectrum of a dilute solution comprising the phosphorescent compound (B) and an organic solvent at room temperature,
two or more phosphorescent compounds (DGR) having an emission spectrum whose maximum peak wavelength is from 495 nm to less than 750 nm and having a dendron represented by the formula (D-A) or (D-B?), wherein the emission spectrum is obtained by measuring the PL spectrum of a dilute solution comprising the phosphorescent compound (DGR) and an organic solvent at room temperature, and
a compound represented by the formula (H-1), wherein
the phosphorescent compound (B) is a phosphorescent compound represented by the formula (1?),
each of the two or more phosphorescent compounds (DGR) is a phosphorescent compound represented by the formula (2), and at least one of the two or more phosphorescent compounds (DGR) is a phosphorescent further compound represented by the formula (2-A1), (2-A2), (2-A3), or (2-A4), and
a ratio of the content of the two or more phosphorescent compounds (DGR) to the content of the phosphorescent compound (B) is 0.1 to 10 parts by weight to 100 parts by weight:
whereinmDA1, mDA2 and mDA3 each independently represent an integer of 0 or more,
GDA represents a nitrogen atom, an aromatic hydrocarbon group or a heterocyclic group and these groups each optionally have a substituent,
ArDA1, ArDA2 and ArDA3 each independently represent an arylene group or a divalent heterocyclic group and these groups each optionally have a substituent, and when a plurality of ArDA1, ArDA2 and ArDA3 are present, they may be the same or different at each occurrence, and
TDA represents an aryl group or a monovalent heterocyclic group and these groups each optionally have a substituent, and the plurality of TDA may be the same or different:
whereinmDA4, mDA5, mDA6 and mDA7 each independently represent an integer of 0 or more, the plurality of GDA may be the same or different,
ArDA1, ArDA2, ArDA3, ArDA4, ArDA5, ArDA6 and ArDA7 each independently represent an arylene group or a divalent heterocyclic group and these groups each optionally have a substituent, and when a plurality of ArDA1, ArDA2, ArDA3, ArDA4, ArDA5, ArDA6 and ArDA7 are present, they may be the same or different at each occurrence;
whereinGDA1, GDA2 and GDA3 each independently represent a nitrogen atom,anaromatic hydrocarbon group or a heterocyclic group and these groups each optionally have a substituent, and mDA2 is an integer of 1 or more when GDA1 and GDA2 are each a nitrogen atom, mDA3 is an integer of 1 or more when GDA1 and GDA3 are each a nitrogen atom;
whereinArH1 and ArH2 each independently represent an aryl group or a monovalent heterocyclic group and these groups each optionally have a substituent,
nH1 represents 1, nH2 represents 0 or 1, and a plurality of nH2 may be the same or different,
nH3 represents 1,
LH1 represents a divalent heterocyclic group represented by the formula (AA-10), (AA-11), (AA-12), (AA-13), (AA-14), (AA-15), (AA-33) or (AA-34),
LH2 represents a group represented by -N(-LH21- RH21)-, and when a plurality of LH2 are present, they may be the same or different, and
LH21 represents a single bond, an arylene group or a divalent heterocyclic group and these groups each optionally have a substituent, and RH21 represents a hydrogen atom, an alkyl group, a cycloalkyl group, an aryl group or a monovalent heterocyclic group and these groups each optionally have a substituent:
wherein R represents a hydrogen atom, an alkyl group, a cycloalkyl group, an aryl group or a monovalent heterocyclic group, and a plurality of R may be the same or different:whereinM represents a ruthenium atom, a rhodium atom, a palladium atom, an iridium atom or a platinum atom,
n1 represents an integer of 1 or more, n2 represents an integer of 0 or more, and n1+n2 is 2 or 3, and n1+n2 is 3 when M is a ruthenium atom, a rhodium atom or an iridium atom, while n1+n2 is 2 when M is a palladium atom or a platinum atom,
E1 and E2 each independently represent a carbon atom or a nitrogen atom, and at least one of E1 and E2 is a carbon atom,
the ring R1? represents a diazole ring and this diazole ring optionally has a substituent, and when a plurality of substituents are present, they may be the same or different and may form a ring together with atoms to which they are attached, and when a plurality of the rings R1? are present, they may be the same or different,
the ring R2 represents a 5-membered or 6-membered aromatic hydrocarbon ring or a 5-membered or 6-membered aromatic heterocyclic ring and these rings each optionally have a substituent, and when a plurality of substituents are present, they may be the same or different and may form a ring together with atoms to which they are attached, and when a plurality of the rings R2 are present, they may be the same or different, and E2 is a carbon atom when the ring R2 is a 6-membered aromatic heterocyclic ring,
the substituent which the ring R1? optionally has and the substituent which the ring R2 optionally has may form a ring together with atoms to which they are attached, and
A1-G1-A2 represents an anionic bidentate ligand, A1 and A2 each independently represent a carbon atom, an oxygen atom or a nitrogen atom and together may constitute a ring, G1 represents a single bond or an atomic group constituting the bidentate ligand together with A1 and A2, and when a plurality of A1-G1-A2 are present, they may be the same or different:
whereinM represents a ruthenium atom, a rhodium atom, a palladium atom, an iridium atom or a platinum atom,
n3 represents an integer of 1 or more, n4 represents an integer of 0 or more, and n3+n4 is 2 or 3, and n3+n4 is 3 when M is a ruthenium atom, a rhodium atom or an iridium atom, while n3+n4 is 2 when M is a palladium atom or a platinum atom,
E4 represents a carbon atom or a nitrogen atom,
the ring R3 represents a 6-membered aromatic heterocyclic ring and this ring optionally has a substituent, and when a plurality of substituents are present, they may be the same or different and may form a ring together with atoms to which they are attached, and when a plurality of the rings R3 are present, they may be the same or different,
the ring R4 represents a 5-membered or 6-membered aromatic hydrocarbon ring or a 5-membered or 6-membered aromatic heterocyclic ring and these rings each optionally have a substituent and when a plurality of substituents are present, they may be the same or different and may form a ring together with atoms to which they are attached, and when a plurality of the rings R4 are present, they may be the same or different, and E4 is a carbon atom when the ring R4 is a 6-membered aromatic heterocyclic ring,
the substituent which the ring R3 optionally has and the substituent which the ring R4 optionally has may form a ring together with atoms to which they are attached,
at least one ring selected from the group consisting of the ring R3 and the ring R4 has a dendron represented by the formula (D-A) or (D-B?), and
A1-G1-A2 represents an anionic bidentate ligand, A1 and A2 each independently represent a carbon atom, an oxygen atom or a nitrogen atom and together may constitute a ring, G1 represents a single bond or an atomic group constituting the bidentate ligand together with A1 and A2, and when a plurality of A1-G1-A2 are present, they may be the same or different:
whereinM1 represents an iridium atom or a platinum atom,
A1-G1-A2, n3 and n4 represent the same meaning as described above,
R1C, R2C, R3C, R4C, R5C, R6C, R7C R8C each independently represent a hydrogen atom, an alkyl group, a cycloalkyl group, an alkoxy group, a cycloalkoxy group, an aryl group, an aryloxy group, a monovalent heterocyclic group, a halogen atom or a dendron represented by the formula (D-A) or (D-B?) and these groups each optionally have a substituent, and when a plurality of R1C, R2C, R3C, R4C, R5C, R6C, R7C and R8C are present they may be the same or different at each occurrence, and R1C, and R2C, R2C and R3C, R3C and R4C, R4C and R5C and R6C, R6C and R7C, and R7C and R8C each may be combined together to form a ring together with the carbon atoms to which they are attached, and
at least one selected from the group consisting of R1C, R2C, R3CR4C, R5C, R6C, R7C and R8C is a dendron represented by the formula (D-A) wherein GDA is a group represented by the formula (GDA-14) or a dendron represented by the formula (D-B?) wherein GDA1 is a group represented by the formula (GDA-14):
wherein * represents a linkage to ArDA1, ** represents a linkage to ArDA2, and *** represents a linkage to ArDA3:whereinM1,A1-G1-A2, n3 and n4 represent the same meaning as described above,
R9C, R10C, R 11C, R12C, R13C, R14C, R15C, R16C, R17C and R18C each independently represent a hydrogen atom, an alkyl group, a cycloalkyl group, an alkoxy group, a cycloalkoxy group, an aryl group, an aryloxy group, a monovalent heterocyclic group, a halogen atom or a dendron represented by the formula (D-A) or (D-B?) and these groups each optionally have a substituent, and when a plurality of R9C, R10C, R11C, R12C, R13C, R14C, R15C, R16C, R17C and R18C are present, they may be the same or different at each occurrence, and R9C and R10C, R11C, and R11C and R12C, R12C and R13C, R13C and R14C, R14C and R15C, R15C and R16C, R16C and R17C and R18C each may be combined together to form a ring together with the carbon atoms to which they are attached, and
at least one selected from the group consisting of R9C, R10C, R11C R12C, R13C, R14C, R15C, R16C, R17C and R18C is a dendron represented by the formula (D- A) or (D-B?):
wherein M1, A1-G1-A2, n3, n4, R9C, R10C, R11CR12C, R13C, R14C, R15C, R16C, R17C and R18C represent the same meaning as described above:wherein M1, A1-G1-A2, n3, n4, R9C, R10C, R11C, R12C, R13C, R14C, R15C, R16C, R17C and R18C represent the same meaning as described above .

US Pat. No. 10,141,513

POLYMERIC LIGHT EMITTING SUBSTANCE AND POLYMER LIGHT EMITTING DEVICE USING THE SAME

SUMITOMO CHEMICAL COMPANY...

1. A polymer light emitting substance having a polystyrene reduced number-average molecular weight of from 103 to 108,wherein the polymer light emitting substance comprises one or more repeating units of the general formula (1), and one or more repeating units having in a side chain a metal complex structure showing light emission from the triplet excited state, and
the metal complex structure showing light emission from the triplet excited state is represented by the below formula (6):

wherein Ar1 represents an arylene group or a divalent heterocyclic compound group; R1 and R2 each independently represent a hydrogen atom, an alkyl group, an aryl group, a monovalent heterocyclic compound group or a cyano group; and n represents 0 or 1,

wherein M represents a rhenium atom, an osmium atom, an iridium atom, a platinum atom, or a gold atom; Ar represents a ligand bonded to M via one or more of a nitrogen atom, an oxygen atom, a carbon atom, a sulfur atom and a phosphorus atom, with bonding to a main chain of the polymer light emitting substance at an arbitrary position via an atom, a direct bond or a divalent group; L represents a hydrogen atom, a hydrocarbon group having 1 to 10 carbon atoms, a carboxylate group having 1 to 10 carbon atoms, a diketonate group having 1 to 10 carbon atoms, a halogen atom, an amide group, an imide group, an alkoxide group, an alkylmercapto group, a carbonyl ligand, an arylene ligand, an alkene ligand, an alkyne ligand, an amine ligand, an imine ligand, a nitrile ligand, an isonitrile ligand, a phosphine ligand, a phosphine oxide ligand, a phosphate ligand, an ether ligand, a sulfone ligand, a sulfoxide ligand or a sulfide ligand; m represents an integer of 1 to 5; and o represents an integer of 0 to 5.

US Pat. No. 10,141,512

CONDUCTING AND SEMI-CONDUCTING ALIGNMENT MATERIALS

ROLIC AG, Zug (CH)

1. Compound of formula (I)
wherein
A, B, E and F independently from each other represents an unsaturated conjugated aliphatic group;
or A, B, E and F independently from each other represent an unsubstituted or substituted carbocyclic or heterocyclic aromatic group, wherein the carbocyclic or heterocyclic aromatic group is selected from
thiophene, fluorene, silafluorene, carbazole, pyridine, pyridazine, pyrimidine, furan, pyrrol and their derivatives,
L1, L2, L3, L4 and L5 independently from each other represent a bridging group, which is selected from the group consisting of single bond, —NH—, —PH—, —CH?CH—,—CR5?CH—, —C?C— or a metallic system,
a, b, e and f are independently from each other of 1 to 0, with the proviso that the sum of a+b=1 and e+f=1,
a?, b?, e? and f? are independently from each other equal to a, b, e and f, respectively,
g is 0 or 1,
n and m are independently from each other 0 to 10000,
Y1, Y2, Y3, Y4, Y5, Y6, Y7 and Y8 are independently from each other a spacer, which is a single bond or a cyclic, straight-chain or branched, substituted or unsubstituted C1-C24 alkylene, wherein one or more CH2, C, CH groups may independently from each other be replaced by a linking group and/or a non-aromatic, aromatic, unsubstituted or substituted carbocyclic or heterocyclic group connected via bridging groups and
D1, D2, D3, D4, D5, D6, D7 and D8 are independently from each other a hydrogen, —R1, a halogen or a photoalignment group, selected from the group consisting of cinnamate group, cyanostilbene group, quinoline group and chalcone group;
wherein R1 is a cyclic, straight-chain or branched, substituted or unsubstituted C1-C24alkyl, wherein one or more CH2, C, CH groups, may independently from each other be replaced by a linking group and/or a non-aromatic, aromatic, unsubstituted or substituted carbocyclic or heterocyclic group connected via bridging groups, selected from —CH?CH—, —CR5??CR5—, —C?C—, —CR5?N—, —C(CH3)=N—, —N?N—, —NR6—, —PR6— or a single bond,
wherein R5 , R5?, R6 are independently from each other hydrogen or C1-C6alkyl; or a cyclic, straight-chain or branched, substituted or unsubstituted C1-C24alkylen, wherein one or more CH2 groups may independently from each other be replaced by a linking group;
and wherein the linking group is selected from —O—, —CO—, —CO—O—, —O—CO—, NR6-, —NR6-CO—, —CO—NR6-, —NR6-CO—O—, —O—CO—NR6-, —NR6CO—NR6-, —CH?CH—, —C?C—, —O—CO—O—, and —Si(CH3)2—O—Si(CH3)2—, and wherein:
R6 represents a hydrogen atom or C1-C6alkyl;
with the proviso that oxygen atoms of linking groups are not directly linked to each other,
with the proviso that n, g, and m are not 0 at the same time,
with the proviso that at least one of D1, D2, D3, D4, D5, D6, D7 and D8 is a photoalignment group.

US Pat. No. 10,141,511

DEPOSITION MASK, APPARATUS FOR MANUFACTURING DISPLAY APPARATUS, AND METHOD OF MANUFACTURING DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A deposition mask extending in a first direction, the deposition mask comprising:a pattern portion comprising a plurality of pattern holes; and
a clamping portion comprising a protrusion portion to be attached to a clamp and an indentation portion formed in a direction toward the pattern portion,
wherein the pattern portion comprises a blocking portion that at least partially overlaps the protrusion portion in the first direction and has an area gradually decreasing in a second direction from the protrusion portion toward the indentation portion, the second direction crossing the first direction.

US Pat. No. 10,141,510

OLED DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

6. A manufacturing method of an organic light emitting diode display panel, comprising manufacturing an anode layer, a light emitting layer and a cathode layer on a base substrate, wherein the method further comprises:manufacturing by an entire-surface coating process a hole transport layer having a first preset thickness between the anode layer and the light emitting layer; and
manufacturing by an inkjet printing process a hole transport layer having a second preset thickness in a first preset region of the hole transport layer having the first preset thickness,
wherein the organic light emitting diode display panel comprises an R pixel region, a G pixel region and a B pixel region, the thickness of the hole transport layer corresponding to the R pixel region being an eighth preset thickness, the thickness of the hole transport layer corresponding to the G pixel region being a ninth preset thickness, and the thickness of the hole transport layer corresponding to the B pixel region being a tenth preset thickness, wherein the eighth preset thickness is smaller than the ninth preset thickness, and the ninth preset thickness is smaller than the tenth preset thickness.

US Pat. No. 10,141,509

CROSSBAR RESISTIVE MEMORY ARRAY WITH HIGHLY CONDUCTIVE COPPER/COPPER ALLOY ELECTRODES AND SILVER/SILVER ALLOYS ELECTRODES

International Business Ma...

1. A method comprising:depositing a first electrode, a first metal cap, a first metal film, and a first hardmask (HM) on a silicon surface, wherein the deposited first metal film contains one or more crystal grains, wherein the one or more crystal grains in the first metal film contain a plurality of respective grain boundaries;
increasing respective sizes of the plurality of respective grain boundaries in the one or more crystal grains in the first metal film by subtractive etching;
forming a resistive random access memory (RRAM) cell, wherein the RRAM cell contains a critical dimension that is inversely proportional to a diameter of each respective crystal grains in the first metal film;
depositing the RRAM cell over the deposited first electrode;
depositing a second electrode, a second metal cap, a second metal film, and a second hardmask (HM) over the deposited RRAM cell, wherein the second metal film contains one or more crystal grains, wherein a diameter of each of the one or more crystal grains of the second film corresponds inversely to the critical dimension of the RRAM cell; and
depositing a spacer over the second HM.

US Pat. No. 10,141,508

CLAMP ELEMENTS FOR PHASE CHANGE MEMORY ARRAYS

Micron Technology, Inc., ...

1. A method for forming cell structures, comprising:forming a mask material having a mask hole, the mask hole formed non-orthogonally relative to a row of contacts;
forming a conductive material and a spacer material over the mask material and in a portion of the mask hole;
removing portions of the conductive material and the spacer material to expose contacts from the row of contacts underlying the mask hole and to form a plurality of conductive elements and a plurality of spacer elements; and
forming a plurality of bit lines over the plurality of conductive elements and spacer elements.

US Pat. No. 10,141,507

BIASED PLASMA OXIDATION METHOD FOR ROUNDING STRUCTURE

MACRONIX INTERNATIONAL CO...

1. A method of making a memory cell, comprising:forming an interlayer conductor extending from an upper surface to a lower surface of an insulation layer, wherein a first end of the interlayer conductor is coupled to a terminal of an access device, and a second end of the interlayer conductor has a top surface coplanar with the upper surface of the insulation layer; and
forming a memory element from the second end of the interlayer conductor including:
a bombardment step which smooths and rounds edges of a top portion of the memory element, and rounds edges of the insulation layer proximate to the memory element, and
an oxidation step creating metal oxide in the memory element.

US Pat. No. 10,141,506

RESISTIVE SWITCHING CO-SPUTTERED PT—(NIO—AL2O3)—PT DEVICES

National University of Si...

1. A capacitor-like structure, comprising:a first electrode constructed of a first metal,
a co-sputtered transition metal oxide (TMO) layer on the first electrode, wherein the co-sputtered TMO layer is a nickel oxide (NiO)-aluminum oxide (Al2O3) layer having a composition of substantially 84% NiO and 16% Al2O3, wherein substantially refers to a percentage within ±10%;
a second electrode constructed of a second metal in contact with the co-sputtered TMO layer,
wherein the capacitor-like structure is resistively switchable due to formation and rupture of conducting nano-filaments (CFs) through the co-sputtered TMO layer in response to application of a voltage between the first electrode and the second electrode.

US Pat. No. 10,141,505

BROMINE CONTAINING SILICON PRECURSORS FOR ENCAPSULATION LAYERS

Lam Research Corporation,...

16. An apparatus comprisingat least one process chamber comprising a pedestal for holding a substrate;
at least one outlet for coupling to a vacuum;
one or more process gas inlets coupled to process gas sources; and
a controller for controlling operations, comprising machine-readable instructions for:
causing introduction of diiodosilane or hexaiodosilane to the at least one process chamber; and
causing introduction of a second reactant to the at least one process chamber.

US Pat. No. 10,141,504

METHODS AND PROCESSES FOR FORMING DEVICES FROM CORRELATED ELECTRON MATERIAL (CEM)

ARM Ltd., Cambridge (GB)...

1. A wafer, comprising:one or more first CEM devices to operate at a first layer of the wafer; and
one or more second CEM devices to operate at a second layer positioned over the first layer of the wafer, wherein the one or more second CEM devices to operate at the second layer of the wafer comprises a through-substrate via, and wherein
the one or more first CEM devices to operate at the first layer exhibit a performance profile different from the performance profile exhibited by the one or more second CEM devices to operate at the second layer positioned over the first layer of the wafer.

US Pat. No. 10,141,503

SELECTIVE PHASE CHANGE MATERIAL GROWTH IN HIGH ASPECT RATIO DIELECTRIC PORES FOR SEMICONDUCTOR DEVICE FABRICATION

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a phase change memory (PCM) device comprising:depositing a first dielectric material;
forming an opening in the first dielectric material;
depositing a bottom metal electrode within the opening and polishing the bottom metal electrode;
depositing a second dielectric material on a surface of the bottom metal electrode and the first dielectric material;
depositing a metal nitride conformally to a pore within the second dielectric material of the phase change memory (PCM) device, the pore extending through the second dielectric material and exposing a portion of a top surface of the bottom metal electrode;
etching the metal nitride such that the metal nitride only and directly remains on an entire sidewalls of the pore, exposing the portion of the top surface of the bottom metal electrode after the etching of the metal nitride; and
selectively depositing a phase change material only within the pore of the second dielectric layer to completely fill an entire of the pore with the phase change material, the selective deposition of the phase change material producing a growth rate of phase change material on the metal nitride at a substantially greater rate than a growth rate of the phase change material on exposed surfaces of the second dielectric material;
applying a vacuum during the depositing of the metal nitride, etching of the metal nitride, and the selective depositing of the phase change material;
depositing a top metal electrode in contact with a top surface of the phase change material and in contact with portions of a top surface of second dielectric material; and
depositing a third dielectric material, the third dielectric material is in contact with sidewalls of the top metal electrode.

US Pat. No. 10,141,502

SEMICONDUCTOR MEMORY DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor memory device comprising:a plurality of first conductive metal lines each extending in a first direction and having a plurality of recesses formed on a top surface thereof to form a plurality of protrusions such that the protrusions and the recesses are alternately arranged in the first direction;
a plurality of second conductive metal lines each extending in a second direction and disposed over the first conductive metal lines to cross over the first conductive metal lines at corresponding ones of the protrusions of the first conductive metal lines;
a plurality of memory cells each disposed on a corresponding one of the plurality of protrusions of said first conductive metal lines and extending in a third direction to contact a corresponding one of the second conductive metal lines; and
a plurality of thermal insulating plugs, each disposed in a corresponding one of said recesses of the first conductive metal lines.

US Pat. No. 10,141,501

MAGNETORESISTIVE ELEMENT

TDK CORPORATION, Tokyo (...

1. A magnetoresistive element comprising:a channel layer;
a first ferromagnetic layer;
a second ferromagnetic layer; and
a reference electrode, wherein:
the first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode are apart from each other and are electrically connected to each other through the channel layer;
the first ferromagnetic layer, the second ferromagnetic layer, and the reference electrode do not overlap each other and are apart from each other when viewed in a thickness direction of the channel layer;
the channel layer includes a first region that overlaps the first ferromagnetic layer when viewed in the thickness direction, a second region that overlaps the second ferromagnetic layer when viewed in the thickness direction, a third region that overlaps the reference electrode when viewed in the thickness direction, a fourth region located between the first region and the second region, and a fifth region located between the second region and the third region;
the second region is located between the first region and the third region in the channel layer;
the first region, the second region, and the fourth region form a sixth region;
the second region, the third region, and the fifth region form a seventh region; and
an average cross-sectional area of the sixth region according to a first plane which perpendicularly intersects a shortest path in the channel layer between an end surface of the first region that is opposite to a surface of the first region that is in contact with the fourth region and an end surface of the second region that is opposite to a surface of the second region that is in contact with the fourth region is smaller than an average cross-sectional area of the seventh region according to a second plane which perpendicularly intersects a shortest path in the channel layer between an end surface of the second region that is opposite to a surface of the second region that is in contact with the fifth region and an end surface of the third region that is opposite to a surface of the third region that is in contact with the fifth region.

US Pat. No. 10,141,500

MAGNETOELECTRIC CONVERTING ELEMENT AND MODULE UTILIZING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A magnetoelectric converting element comprising:a substrate;
a magnetosensitive layer formed on/over the substrate;
a first insulating layer having a first opening exposing a part of the magnetosensitive layer;
an underlying conductive layer formed on/over the part of the magnetosensitive layer;
a second insulating layer having a second opening exposing a part of the underlying conductive layer; and
a terminal conductor formed on/over the part of the underlying conductive layer,
wherein the second opening is located inside the first opening in plan view, and
wherein an entirety of the terminal conductor is contained within the first opening when viewed in plan.

US Pat. No. 10,141,499

PERPENDICULAR MAGNETIC TUNNEL JUNCTION DEVICE WITH OFFSET PRECESSIONAL SPIN CURRENT LAYER

Spin Transfer Technologie...

1. A magnetic device, comprising:a first synthetic antiferromagnetic structure in a first plane having a magnetization vector that is perpendicular to the first plane and having a fixed magnetization direction;
an antiferromagnetic coupling layer in a second plane and disposed above the first synthetic antiferromagnetic structure;
a second synthetic antiferromagnetic structure in a third plane and disposed over the antiferromagnetic coupling layer;
a magnetic reference layer in a fourth plane and disposed over the second synthetic antiferromagnetic structure, the magnetic reference layer having a magnetization vector that is perpendicular to the fourth plane and having a fixed magnetization direction;
a non-magnetic tunnel barrier layer in a fifth plane and disposed over the magnetic reference layer;
a free magnetic layer having a first diameter and disposed in a sixth plane over the non-magnetic tunnel barrier layer, the free magnetic layer having a magnetization vector that is perpendicular to the sixth plane and having a magnetization direction that can switch between a first magnetization direction to a second magnetization direction, the magnetic reference layer, the non-magnetic tunnel barrier layer and the free magnetic layer forming a magnetic tunnel junction; and
a precessional spin current magnetic layer having a second diameter that is less than the first diameter and a center that is offset relative to a center of the free magnetic layer, the precessional spin current magnetic layer disposed in a seventh plane that is physically separated from the free magnetic layer and coupled to the free magnetic layer by a filter coupling layer that may induce ferromagnetic or antiferromagnetic coupling between the free magnetic layer and the filter layer.

US Pat. No. 10,141,498

MAGNETORESISTIVE STACK, SEED REGION THEREOF AND METHOD OF MANUFACTURING SAME

Everspin Technologies, In...

1. A method of manufacturing a magnetoresistive stack comprising:depositing a seed region on an electrically conductive material, wherein depositing the seed region includes:
depositing an alloy including nickel and chromium having a thickness greater than or equal to 40 Angstroms and a material composition of chromium in the range of 25-60% by atomic percent;
depositing a fixed magnetic region on and in direct contact with the seed region, wherein depositing the fixed magnetic region includes:
depositing a multilayer unpinned, fixed synthetic antiferromagnetic structure including (i) depositing a first ferromagnetic structure on and in direct contact with the seed region, (ii) depositing a coupling material on and in direct contact with the first ferromagnetic structure, and (iii) depositing a second ferromagnetic structure on and in direct contact with the coupling material,
depositing a transition layer on and in direct contact with the second ferromagnetic structure, wherein the transition layer includes a non-ferromagnetic transition metal, and
forming a high-iron alloy interface region over the transition layer, wherein the high-iron alloy interface region has at least 50% iron by atomic composition;
depositing one or more dielectric layers wherein, after annealing, the one or more dielectric layers are on and in direct contact with the high-iron alloy interface region of the fixed magnetic region; and
depositing a free magnetic region over the one or more dielectric layers.

US Pat. No. 10,141,497

THIN FILM STACK

HEWLETT-PACKARD DEVELOPME...

1. A thin film stack, comprising a substrate, a metal layer, and an adhesive layer, wherein the adhesive layer comprises a blend of zinc oxide and tin oxide, wherein the adhesive layer is adhered to the substrate and the metal layer, and wherein the blend of zinc oxide and tin oxide comprises from 90 at % to 100 at % of the adhesive layer, and is present at a zinc oxide to tin oxide atomic ratio of 1:20 to 20:1.

US Pat. No. 10,141,496

DEVICE HOUSING WITH VIBRATOR COMPONENT

Microsoft Technology Lice...

1. An electronic device, comprising:a housing in which an internal recess is defined, wherein the housing comprises a first antenna region for accommodating a first antenna of the electronic device and a second antenna region for accommodating a second antenna of the electronic device, wherein the first and second antenna regions extend generally parallel to a shorter side of the device;
a piezo beam positioned in the internal recess and mounted to an internal structure of the electronic device defining a wall of the recess, the piezo beam being mounted to the internal structure in a mounting direction generally perpendicular to a thinnest dimension of the electronic device; and
an elongate mass coupled to a center area of the piezo beam and having opposing free ends that are free to vibrate at selected frequencies to produce haptic feedback, wherein the piezo beam and the elongate mass are positioned between and spaced apart from the first and second antenna regions.

US Pat. No. 10,141,495

MICROSYSTEMS-BASED METHOD AND APPARATUS FOR PASSIVE DETECTION AND PROCESSING OF RADIO-FREQUENCY SIGNALS

1. A radiofrequency device, comprising:a passive impedance transforming voltage amplifier receivingly connected to an antenna for receiving radiofrequency (RF) signals, the impedance transforming voltage amplifier adapted to produce an RF actuation signal; and
a MEMS switch having a radiofrequency (RF) actuation electrode receivingly connected to the impedance transforming voltage amplifier;
wherein:
the MEMS switch further comprises a DC bias electrode positioned to latch the MEMS switch in a closed position by electrostatic attraction when energized by a suitable voltage;
the MEMS switch further comprises a bridge that physically and electrically contacts at least the DC bias electrode when the MEMS switch is in the closed position; and
the bridge is configured with a mechanical mode of vibration that, when subjected to the RF actuation signal having a fundamental frequency that matches at least one frequency of the said mechanical mode of vibration, allows the MEMS switch to be periodically urged toward the closed position.

US Pat. No. 10,141,494

HEADSET AND HEADPHONE

1. A headset comprising:at least one microphone configured to detect ambient noises;
at least one electroacoustic reproduction transducer configured to output an audio signal to be reproduced;
a control unit configured to control the headset;
a digital active noise reduction unit having an adjustable functionality and having a digital hardware; and
a data interface configured to:
couple the headset, via a bi-directional data communication, with an external media player; and
receive at least one functionality adjustment for the digital active noise reduction unit from a user via the external media player, wherein the functionality adjustment comprises adjustable parameters of the digital active noise reduction unit;
wherein the control unit is connected with the digital active noise reduction unit and the data interface;
wherein the control unit is further configured to adjust the functionality of the digital active noise reduction unit according to the received functionality adjustment, the control unit selecting a mode of digital active noise reduction of the digital active noise reduction unit according to the received functionality adjustment;
wherein the digital active noise reduction unit is configured to perform active noise reduction based at least on the ambient noises recorded by the microphone and the received functionality adjustment.

US Pat. No. 10,141,493

THERMAL MANAGEMENT FOR SUPERCONDUCTING INTERCONNECTS

Microsoft Technology Lice...

1. An interconnect for coupling a superconducting system and a non-superconducting system, the interconnect comprising:a first end configured for coupling to the superconducting system, wherein the interconnect comprises a superconducting element having a critical temperature; and
a second end configured for coupling to the non-superconducting system, such that during operation of the superconducting system and the non-superconducting system, a first portion of the interconnect near the first end having a first temperature equal to or below the critical temperature of the superconducting element, a second portion of the interconnect near the second end having a second temperature above the critical temperature of the superconducting element, and wherein the interconnect is further configured to reduce a length of the second portion such that temperature substantially over an entire length of the interconnect is maintained at a temperature equal to or below the critical temperature of the superconducting element.

US Pat. No. 10,141,492

ENERGY HARVESTING FOR WEARABLE TECHNOLOGY THROUGH A THIN FLEXIBLE THERMOELECTRIC DEVICE

NIMBUS MATERIALS INC., F...

1. A flexible thermoelectric device, comprising:a lower dielectric layer comprising flexible material to provide structure to the flexible thermoelectric device;
a lower conduction layer comprising a plurality of electrically conductive pads disposed directly on and across a surface of the lower dielectric layer, the plurality of electrically conductive pads comprising a plurality of N-designated conductive pads and a plurality of P-designated conductive pads, where the plurality of electrically conductive pads are arranged in pairs such that each pair comprises one N-designated conductive pad of the plurality of N-designated conductive pads and one P-designated conductive pad of the plurality of P-designated conductive pads that are adjacent to one another across the surface of the lower dielectric layer, where the N-designated conductive pad and the P-designated conductive pad in each pair are electrically coupled to one another through an electrically conductive lead extending between the N-designated conductive pad and the P-designated conductive pad adjacent to one another in the pair, the electrically conductive lead extending across the surface of the lower dielectric layer, being parallel to lengths of the N-designated conductive pad and the P-designated conductive pad in the pair, and being narrower in width compared to widths of the N-designated conductive pad and the P-designated conductive pad in the pair, where the widths of the N-designated conductive pad and the P-designated conductive pad are a dimension perpendicular to the length thereof;
a plurality of N-type thin film thermoelectric conduits, each N-type thin film thermoelectric conduit on top of a respective N-designated conductive pad of the plurality of N-designated conductive pads, each N-type thin film thermoelectric conduit having a top surface and a bottom surface, where the bottom surface directly contacts the respective N-designated conductive pad, and the top surface is opposite to the bottom surface;
a plurality of P-type thin film thermoelectric conduits, each P-type thin film thermoelectric conduit on top of a respective P-designated conductive pad of the plurality of P-designated conductive pads, each P-type thin film thermoelectric conduit having a top surface and a bottom surface, where the bottom surface directly contacts the respective P-designated conductive pad, and the top surface is opposite to the bottom surface;
an internal dielectric layer comprising a flexible dielectric material extending across the top surfaces of all the N-type thin film thermoelectric conduits and all the P-type thin film thermoelectric conduits, the internal dielectric layer being electrically insulating, and a surface of the internal dielectric layer being parallel to the top surfaces of each N-type thin film thermoelectric conduit and each P-type thin film thermoelectric conduit;
a thermal insulator to fill a space around each N-type thin film thermoelectric conduit and each P-type thin film thermoelectric conduit, the thermal insulator and the internal dielectric layer being laminated on top of the N-type thin film thermoelectric conduits and the P-type thin film thermoelectric conduits;
a plurality of contact holes extending through the internal dielectric layer and the thermal insulator such that each contact hole extends through a thickness of the internal dielectric layer directly into a thickness of the thermal insulator, and ends on the top surface of the respective N-type thin film thermoelectric conduit or the respective P-type thin film thermoelectric conduit;
a plurality of electrically conductive contacts, each electrically conductive contact fills a respective contact hole of the plurality of contact holes such that each electrically conductive contact extends perpendicularly through the respective contact hole from the top surface of the respective N-type thin film thermoelectric conduit or the respective P-type thin film thermoelectric conduit, through the thermal insulator, and through the thickness of the internal dielectric layer, where each electrically conductive contact includes an outward extension that emerges outward from the respective contact hole above the internal dielectric layer;
a plurality of another electrically conductive leads, each of which bridges between the outward extension of a first respective electrically conductive contact of the plurality of electrically conductive contacts outwardly extending from the N-type thin film thermoelectric conduit on the N-designated conductive pad of a first pair of the pairs and the outward extension of a second respective electrically conductive contact of the plurality of electrically conductive contacts outwardly extending from the P-type thin film thermoelectric conduit on the P-designated conductive pad in a second pair of the pairs, where the first pair and the second pair are adjacent to each other, such that all N-type and P-type thin film thermoelectric conduits of the flexible thermoelectric device are connected in series by the electrically conductive lead in each pair and the another electrically conductive leads, each another electrically conductive lead being disposed directly on the top surface of the internal dielectric layer between the outward extension of the first respective electrically conductive contact and the outward extension of the second respective electrically conductive contact; and
an upper dielectric layer comprising flexible material on top of the plurality of another electrically conductive leads to provide structure to the flexible thermoelectric device,
wherein each N-type thin film thermoelectric conduit and each P-type thin film thermoelectric conduit comprises thermoelectric material no thicker than 50 microns, and
wherein the flexible thermoelectric device is bendable to fit a shape of a target platform in which the flexible thermoelectric device is used to harvest thermal energy.

US Pat. No. 10,141,491

METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device comprising:providing an undivided base having a first main surface and a second main surface on the opposite side from the first main surface, the undivided base having conductive patterns disposed on the first main surface and conductive patterns disposed on the second main surface;
mounting a plurality of light emitting elements on the conductive patterns on the first main surface;
forming a light reflecting member that integrally covers side surfaces of the light emitting elements and the first main surface of the undivided base; and
after the forming of the light reflecting member, forming at least one groove on the second main surface of the undivided base at a position corresponding to a space between the light emitting elements so that the groove reaches the first main surface and the undivided base is divided into a plurality of base members without a further step of separating the light reflecting member.

US Pat. No. 10,141,490

COMPOSITE BASE AND METHOD OF MANUFACTURING LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A method of manufacturing a light emitting device, comprising:providing a light emitting device set that includes
a lead frame including a plurality of pairs of supporting leads each of which pairs consists of a first supporting lead and a second supporting lead,
a plurality of packages respectively supported by the plurality of pairs of supporting leads, and
a plurality of light emitting elements respectively mounted on the plurality of packages; and
removing the plurality of packages from the lead frame,
wherein the packages each include a resin molded body,
the resin molded body includes
a first outer surface supported by the first supporting lead,
a second outer surface positioned opposite to the first outer surface and supported by the second supporting lead,
a third outer surface positioned between the first outer surface and the second outer surface,
a fourth outer surface positioned opposite to the third outer surface,
a first recess that is open at the first outer surface and the third outer surface, and
a second recess that is open at the second outer surface and the third outer surface,
wherein the first supporting lead fits into the first recess, and the second supporting lead fits into the second recess, and
wherein the packages are each removed from the lead frame by the third outer surface being pushed.

US Pat. No. 10,141,489

LED ILLUMINATION APPARATUS

Shoichi Nakamura, Higash...

1. An LED illumination apparatus comprising:a tubular lens casing that has a first end face at which illuminating lenses are provided and a second end face;
an LED holding part on which LED elements are mounted;
a base part provided on the second end face side of the lens casing;
a concave part formed in the base part so as to house the LED holding part;
a coupling part that holds a coupling state between the lens casing and the base part by fitting the lens casing to the concave part at the second end face to hermetically seal the internal space of the lens casing;
support columns formed so as to protrude from the base part to a space outside the LED illumination apparatus;anda fan device having a frame supported by the support columns, wherein
the fan device makes taken-in air collide with the end face of the base part that faces away from the concave part and exhausts the air through the window parts each formed by adjacent support columns as a pair of side frames thereof and the sides of the respective frame and base part that face each other as upper and lower frames thereof.

US Pat. No. 10,141,488

LIGHTING DEVICE

NICHIA CORPORATION, Anan...

1. A lighting device comprising:a lightguide panel having an end face that is a light-receiving surface; and
a light-emitting device that emits light toward the end face of the lightguide panel, the light-emitting device including:
a light-emitting element; and
a first light-transmissive member located between the end face of the lightguide panel and the light-emitting element, the first light-transmissive member having a plurality of protrusions on a surface thereof, wherein
at least one of the plurality of protrusions is in direct contact with the end face of the lightguide panel.

US Pat. No. 10,141,487

COVER FOR LIGHT EMITTER

SHINKO ELECTRIC INDUSTRIE...

1. A cover for a light emitter having one or more light emitting devices, comprising:a glass plate having an upper face, a lower face, and a peripheral side surface;
a frame made of metal having an opening smaller than the glass plate; and
a low melting glass having a lower melting point than the glass plate, the glass plate being sealed to the frame with the low melting glass to close the opening,
wherein the frame has an encircling step formed on a side thereof to which the glass plate is sealed,
wherein the encircling step includes:
a placement face situated at a recessed position relative to an upper surface of the frame, the placement face being in contact with a perimeter of the lower face of the glass plate to have the glass plate placed thereon; and
a wall face connecting the upper surface of the frame and the placement face,
wherein the wall face includes first wall faces situated at opposite ends of each inner side of the encircling step and a second wall face situated between the first wall faces, and
the second wall face includes a face extending at a smaller inclination angle than the first wall faces with respect to the placement face, and
wherein gaps between the first wall faces and the peripheral side surface of the glass plate and a gap between the second wall face and the peripheral side surface of the glass plate are filled with the low melting glass.

US Pat. No. 10,141,486

PROCESS METHOD USING ORGANIC SILICONE RESIN PHOTOCONVERTER TO BOND-PACKAGE LED BY TANDEM ROLLING

Jiangsu Cherrity Optronic...

1. A process method for bond-packaging an LED using an organic silicone resin photoconverter by tandem rolling, comprising the following continuous process flow: preparation of a semi-cured photoconversion sheet, pseudo-curing of the semi-cured photoconversion sheet, preparation of a flip chip LED array sheet, forming of LED package elements by dual-roller roll-bonding, curing of the LED package elements, and cutting of the LED package elements, wherein the process comprises the following basic steps:step 1: preparation of a semi-cured photoconversion sheet: obtaining the semi-cured photoconversion sheet formed of a first protective film, a semi-cured photoconversion film, and a second protective film, wherein the semi-cured photoconversion film comprises semi-cured organic silicone resin and a photoconversion material;
step 2: pseudo-curing of the semi-cured photoconversion sheet: in a vacuum condition, by means of low-temperature freezing, pseudo-curing the semi-cured photoconversion sheet obtained in step 1, to obtain a pseudo-cured photoconversion sheet;
step 3: preparation of a flip chip LED array sheet: obtaining the flip chip LED array sheet, flip chip LEDs in the flip chip LED array sheet being arranged on a carrier film in an array manner, wherein the flip chip LEDs being arranged in an array manner means arrangement in an array by using an individual flip chip LED as a unit or arrangement in an array by using a flip chip LED assembly as a unit, and the flip chip LED assembly is formed of two or more individual flip chip LEDs;
step 4: forming of LED package elements by dual-roller roll-bonding: in a vacuum condition, removing the second protective film of the pseudo-cured photoconversion sheet in step 2, to obtain the pseudo-cured photoconversion sheet containing no protective film on a single side, then enabling the pseudo-cured photoconversion sheet to turn from a pseudo-cured state to a semi-cured state by means of heating or/and illumination, and subsequently performing dual-roller roll-bonding on the semi-cured photoconversion sheet and the flip chip LED array sheet, such that the flip chip LEDs in the flip chip LED array are bonded to and inserted in the semi-cured photoconversion sheet, to obtain the LED package elements;
step 5: curing of the LED package elements: in a vacuum condition, curing the LED package elements by means or heat curing or/and photocuring, to obtain the cured LED package elements; and
step 6: cutting of the LED package elements: removing the first protective film of the cured LED package elements in step 5, and cutting the cured LED package elements, to obtain finished LED package elements having slits for splitting into single LED package elements.

US Pat. No. 10,141,485

VEHICLE LAMP USING SEMICONDUCTOR LIGHT EMITTING DEVICE

LG Electronics Inc., Seo...

1. A lamp for a vehicle, comprising:a light source unit configured to emit light, the light source unit comprising:
a substrate that includes a wiring electrode,
a plurality of semiconductor light emitting devices electrically connected to the wiring electrode,
a plurality of phosphor layers that respectively cover the plurality of semiconductor light emitting devices and that are configured to convert wavelengths of light, and
barrier ribs disposed on the substrate and configured to reflect light, the barrier ribs being interposed between the plurality of semiconductor light emitting devices,
wherein a height of each of the barrier ribs exceeds a height of each of the plurality of semiconductor light emitting devices in a thickness direction of the plurality of semiconductor light emitting devices.

US Pat. No. 10,141,484

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device composing:a light emitting element having a peak emission wavelength in a range of 410 nm to 440 nm; and
a phosphor member, the phosphor member containing a phosphor comprising:
a first phosphor having a peak emission wavelength in a range of 430 nm to 500 nm and containing an alkaline-earth phosphate, which includes Cl and is activated with Eu;
a second phosphor having a peak emission wavelength in a range of 440 nm to 550 nm and containing at least one of an alkaline-earth aluminate, which is activated with Eu, and a silicate, which includes Ca, Mg, and Cl and is activated with Eu;
a third phosphor having a peak emission wavelength in a range of 500 nm to 600 nm and containing a rare-earth aluminate, which is activated with Ce;
a fourth phosphor having a peak emission wavelength in a range of 610 nm to 650 nm and containing a silicon nitride, which includes Al and at least one of Sr and Ca and is activated with Eu; and
a fifth phosphor having a peak emission wavelength in a range of 650 nm to 670 nm and containing a fluorogermanate, which is activated with Mn,
wherein a percentage content of the first phosphor to a total content of the phosphor is in a range of 20 mass % to 80 mass %,
wherein a content ratio of the first phosphor to the third phosphor is 0.3 to 7,
wherein a half value width of the emission spectrum of the third phosphor is 95 nm to 115 nm; and
wherein the light emitting device is configured to emit light of correlated color temperature in a range of 4,500 K to 5,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.6 to 1.5, and a special color rendering Index R12 of the light emitting device is 90 or greater and a sum of special color rendering Indices R9 to R15 of the light emitting device is 660 or greater.

US Pat. No. 10,141,483

SEMICONDUCTOR ILLUMINATING DEVICE

OSRAM Opto Semiconductors...

1. A semiconductor illuminating device for emitting illumination light comprising:an LED configured for emitting blue primary radiation; and
an LED phosphor arranged and configured such that it emits secondary light that forms at least one component of the illumination light,
wherein the LED phosphor comprises a red phosphor for emitting red light as a component of the secondary light and a green phosphor for emitting green light as a component of the secondary light, wherein the green light has a color point located above a first straight line having a slope m1 and a y-intercept n1 in a CIE standard chromaticity diagram, with the slope m1=1.189 and the y-intercept n1=0.226, and
wherein the components of the illumination light are at such a ratio to one another that the illumination light has a color temperature of at most 5500 K.

US Pat. No. 10,141,482

SEMICONDUCTOR LIGHT EMITTING DEVICE

ALPAD CORPORATION, Tokyo...

1. A semiconductor light emitting device, comprising:a light emitting chip having a semiconductor layer at a first surface of the light emitting chip;
a transparent film on the first surface and forming an interface with the semiconductor layer;
a phosphor resin layer including a resin and a phosphor, on the transparent film;
a first electrode having an upper surface on which the light emitting chip is disposed;
a second electrode having an upper surface and being spaced from the first electrode in a direction parallel to the upper surface of the first electrode; and
a reflection layer provided on the upper surfaces of the first and second electrodes, wherein
a refractive index of the transparent film is greater than a refractive index of the semiconductor layer.

US Pat. No. 10,141,480

LIGHT EMITTING DIODE CHIP HAVING DISTRIBUTED BRAGG REFLECTOR AND METHOD OF FABRICATING THE SAME

Seoul Viosys Co., Ltd., ...

1. A method of fabricating a light emitting diode chip, the method comprising:forming a light emitting structure on a first surface of a substrate, the light emitting structure comprising:
a first conductive-type semiconductor layer;
a second conductive-type semiconductor layer; and
an active layer disposed between the first conductive-type semiconductor layer and the second conductive-type semiconductor layer;
removing a portion of the substrate by grinding a second surface of the substrate;
after the grinding, reducing the surface roughness of the second surface of the substrate by lapping the substrate; and
forming a distributed Bragg reflector on the second surface of the substrate,
wherein the distributed Bragg reflector comprises a first material layer comprising TiO2, a second material layer comprising SiO2, a third material layer comprising TiO2, and a fourth material layer comprising SiO2, and
wherein the first material layer has an optical thickness that is different from an optical thickness of the third material layer.

US Pat. No. 10,141,479

LIGHT-EMITTING PACKAGE STRUCTURE PROVIDED WITH PREDETERMINED VIEW ANGLE

LITE-ON OPTO TECHNOLOGY (...

1. A light-emitting package structure, comprising:a carrier substrate having a circuit structure;
a thin film chip disposed on the carrier substrate and having an epitaxial structure and at least two electrodes disposed on a bottom surface of the epitaxial structure, the at least two electrodes contacting the circuit structure;
an underfill material disposed in a gap between the at least two electrodes of the thin film chip for supporting the thin film chip;
a wavelength converting layer at least covering the epitaxial structure of the thin film chip; and
a reflecting wall surrounding the wavelength converting layer and the thin film chip, wherein a reflectivity of the reflecting wall is larger than 70%, and a ratio between a total luminous intensity of light emitted by the light-emitting package structure in an illumination angle of ±40 degrees and a luminous intensity area within a view angle of light emitted by the light-emitting package structure is larger than 0.7.

US Pat. No. 10,141,478

STRUCTURE OF A REFLECTIVE ELECTRODE AND AN OHMIC LAYER OF A LIGHT EMITTING DEVICE

LG INNOTEK CO., LTD., Se...

1. A light emitting device comprising:a substrate;
a first conductive layer on the substrate;
a second conductive layer on the first conductive layer;
a metal layer on the second conductive layer;
a light emitting structure on the metal layer and the second conductive layer, the light emitting structure including a first semiconductor layer containing AlGaN, an active layer, and a second semiconductor layer containing AlGaN;
a first electrode on the light emitting structure; and
a passivation layer disposed on a side surface of the light emitting structure,
wherein a first region of the metal layer directly contacts with the light emitting structure, a second region of the second conductive layer directly contacts with the light emitting structure, and a third region of the first conductive layer directly contacts with the light emitting structure,
wherein the second region of the second conductive layer is disposed at a periphery of the first region of the metal layer,
wherein a portion of the passivation layer including a first roughness is disposed on a top surface of the light emitting structure,
wherein a first portion of the top surface of the light emitting structure includes a second roughness,
wherein the second region of the second conductive layer and the first portion of the top surface of the light emitting structure are vertically overlapped,
wherein a width of the second conductive layer is greater than a width of the metal layer, and
wherein a thickness from a top surface of the substrate to a bottom surface of the metal layer at a center portion of the metal layer is less than a thickness from the top surface of the substrate to the bottom surface of the metal layer at an edge portion of the metal layer.

US Pat. No. 10,141,477

STRAINED ALGAINP LAYERS FOR EFFICIENT ELECTRON AND HOLE BLOCKING IN LIGHT EMITTING DEVICES

Lumileds LLC, San Jose, ...

1. A light-emitting device, comprising:an electron blocking layer, wherein at least a portion of the electron blocking layer is arranged to have a tensile strain;
a hole blocking layer, wherein at least a portion of the hole blocking layer is arranged to have a compressive strain; and
an active layer disposed between the hole blocking layer and the electron blocking layer.

US Pat. No. 10,141,476

LIGHT EMITTING DIODE CHIP SCALE PACKAGING STRUCTURE

LEXTAR ELECTRONICS CORPOR...

1. A light emitting diode chip scale packaging structure, comprising:a light emitting unit comprising a light emitting diode chip; and
a lens covering the light emitting diode chip, wherein a curve of an outer surface of the lens in a cross-section view substantially complies with a polynomial of:
z=?0.0005y6?0.0059y5+0.0871y4?0.3718y3+0.5658y2?0.0709y+2.5046,
z is a variable of vertical axis of the curve, y is a variable of horizontal axis of the curve, a center point of the curve corresponding to the light emitting diode chip is a coordinate where y is 0 and z is 2.5046, wherein a correlation coefficient calculated from fitting the curve to the polynomial is larger than or equal to 0.995, the outer surface has a concave structure, the center point of the curve is the lowest point of the concave structure, the lens is in contact with the light emitting unit, and no air gap is between the lens and the light emitting unit.

US Pat. No. 10,141,475

METHOD FOR BINDING MICRO DEVICE TO CONDUCTIVE PAD

MIKRO MESA TECHNOLOGY CO....

1. A method for binding a micro device to a conductive pad of an array substrate, the method comprising:lowering a temperature of the conductive pad in an environment comprising a vapor such that at least a portion of the vapor is condensed to form a liquid layer on the conductive pad;
disposing the micro device over the conductive pad such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the conductive pad, wherein the micro device comprises an electrode facing the conductive pad; and
evaporating the liquid layer such that the electrode is bound to and is in electrical contact with the conductive pad.

US Pat. No. 10,141,474

PASSIVATION METHOD

Taiwan Semiconductor Manu...

1. A method of passivating an absorber layer of a solar cell module, comprising the steps of:providing an absorber layer formed over a substrate, the absorber layer having a planar upper surface; and
forming a porous alumina passivation layer on the upper surface of the absorber layer, wherein the porous alumina passivation layer has a passivating region directly over and in contact with the upper surface of the absorber layer operating to passivate the absorber layer and wherein in the passivating region the passivation layer has pore dimensions sufficient to provide a non-planar, textured upper surface;
conformably forming a buffer layer over the passivating region of the passivation layer; and
conformably forming a transparent conducting oxide layer over the buffer layer, thereby providing the buffer layer and transparent conducting oxide layer each with a non-planar, textured upper surface over the passivating region of the passivation layer,
wherein the non-planar, textured upper surfaces of the porous alumina passivation layer, buffer layer and transparent conducting oxide layer provide the solar cell with increased light scattering effect, as compared to planar, non-textured upper surfaces, as light passes through the textured upper surfaces to an area of the upper surface of the absorber layer in contact with and passivated by the passivating region of the porous alumina passivation layer.

US Pat. No. 10,141,473

PHOTOVOLTAIC DEVICES AND METHOD OF MAKING

First Solar, Inc., Tempe...

1. A photovoltaic device, comprising:a layer stack; and
an absorber layer disposed on the layer stack, wherein:
the absorber layer comprises a compound comprising cadmium, selenium, and tellurium,
the compound comprising cadmium, selenium, and tellurium has a first region and a second region,
an atomic concentration of selenium varies across the absorber layer; the first region of the compound comprising cadmium, selenium, and tellurium has a thickness between 100 nanometers to 3000 nanometers,
the second region of the compound comprising cadmium, selenium, and tellurium has a thickness between 100 nanometers to 3000 nanometers,
a ratio of an average atomic concentration of selenium in the first region of the compound comprising cadmium, selenium, and tellurium to an average atomic concentration of selenium in the second region of the compound comprising cadmium, selenium, and tellurium is greater than 10, and
the compound comprising cadmium, selenium, and tellurium further comprises mercury in an amount of that varies across a thickness of the absorber layer.

US Pat. No. 10,141,472

PHOTODIODE STRUCTURES

INTERNATIONAL BUSINESS MA...

1. A method, comprising:forming a waveguide structure in a dielectric layer;
forming an amorphous Ge material over an upper surface of the waveguide structure in a back end of the line (BEOL) metal layer; and
crystallizing the amorphous Ge material into a crystalline Ge structure by an annealing process with a metal layer in contact with the Ge material,
wherein the forming of the Ge material adjacent to the waveguide structure in a back end of the line (BEOL) metal layer comprises:
depositing a barrier layer of nitride directly on the upper surface of the waveguide structure, followed by a patterning of the barrier layer;
depositing the amorphous Ge material directly on the barrier layer, followed by a patterning of the amorphous Ge material;
opening a via to expose portions of the amorphous Ge material;
depositing the metal layer on the amorphous Ge material through the opening of the via; and
crystallizing of the amorphous Ge material through the annealing process to form the crystalline Ge structure aligned with the via.

US Pat. No. 10,141,471

PROXIMITY DETECTOR DEVICE WITH INTERCONNECT LAYERS AND RELATED METHODS

1. A device, comprising:a first interconnect layer comprising a first dielectric layer and a plurality of first electrically conductive traces;
an integrated circuit (IC) layer overlying the first interconnect layer and comprising an image sensor IC and a light source IC laterally spaced from the image sensor IC;
a second interconnect layer overlying the IC layer and comprising a second dielectric layer and a plurality of second electrically conductive traces, the second interconnect layer having first and second openings respectively aligned with the image sensor IC and the light source IC, the image sensor IC and the light source IC being electrically coupled to the plurality of first electrically conductive traces and the plurality of second electrically conductive traces;
a transparent adhesive material filling the first and second openings and contacting surfaces of the image sensor IC and the light source IC;
a lens assembly overlying the second interconnect layer and comprising first and second lenses respectively aligned with the first and second openings, the first and second lenses being adhered to the transparent adhesive material; and
a plurality of contacts coupled respectively to the plurality of first electrically conductive traces.

US Pat. No. 10,141,470

PHOTODIODE TYPE STRUCTURE, COMPONENT AND METHOD FOR MANUFACTURING SUCH A STRUCTURE

1. A photodiode type structure intended to receive electromagnetic radiation in a given wavelength range, the photodiode type structure comprising:a support including at least one semiconductor layer, the semiconductor layer including of a first semiconductor zone of a first type of conductivity, the first semiconductor zone being made of a first semiconductor material having a forbidden band gap such that the first semiconductor zone is transparent in the given wavelength range;
a mesa in contact with the semiconductor layer, the mesa including a second semiconductor zone, known as absorption zone, the second semiconductor zone being of a second type of conductivity opposite to the first type of conductivity so as to form a semiconductor junction having a space charge zone, the second semiconductor zone being made of a second semiconductor material having a forbidden band gap suited to favoring the absorption of electromagnetic radiation, the second semiconductor zone having a concentration of majority carriers such that the second semiconductor zone is included within the space charge zone, and is thus depleted, in the absence of polarization of the structure; and
a third semiconductor zone of the second type of conductivity made of a third semiconductor material having a forbidden band gap such that the third semiconductor zone is transparent in the given wavelength range, the third semiconductor zone being interposed between the first and the second semiconductor zones while being at least partially arranged in the semiconductor layer and while forming the semiconductor junction with the first semiconductor zone in the semiconductor layer, wherein the third semiconductor zone also forming with the second semiconductor zone a potential barrier for minority carriers of the second semiconductor zone.

US Pat. No. 10,141,469

RADIALLY STACKED SOLAR CELLS BASED ON 2D ATOMIC CRYSTALS AND METHODS FOR THEIR PRODUCTION

STC.UNM, Albuquerque, NM...

1. A method for fabricating a solar cell, comprising:forming a sacrificial layer;
forming a barrier layer having a gradient strain on the sacrificial layer;
attaching a heterostructure comprising a first light absorbing layer and at least a second light absorbing layer to the barrier layer, wherein the second light absorbing layer is attached to the first light absorbing layer and thereby forms a heterojunction at an interface between the first light absorbing layer and the second light absorbing layer; and
removing the sacrificial layer subsequent to the attaching of the first light absorbing layer and the second light absorbing layer to the barrier layer,
wherein the barrier layer, the first light absorbing layer, and the second light absorbing layer form a spiral structure having a spiral shape resulting from the gradient strain of the barrier layer.

US Pat. No. 10,141,468

METHOD AND APPARATUS FOR A THERMOPHOTOVOLTAIC CELL

Atrius Energy, Inc., Hun...

1. A thermophotovoltaic cell, comprising:a PN junction comprising a p-type semiconductor layer, wherein said p-type semiconductor layer further comprises chromium oxide;
a passivation layer; and
a pair of opposing conductive current collectors;
wherein said PN junction and said passivation layer are positioned between said pair of opposing conductive current collectors.

US Pat. No. 10,141,467

SOLAR CELL AND METHOD FOR MANUFACTURING THE SAME

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a semiconductor substrate with a front surface, a back surface, and an edge connecting the front surface and the back surface;
a first conductive type region formed on substantially the entirety of the front surface of the semiconductor substrate;
a second conductive type region formed on the back surface of the semiconductor substrate, the second conductive type region being spaced from an edge of the semiconductor substrate and having a conductive type different from that of the first conductive type region;
an isolation portion formed at a perimeter of the second conductive type region on the back surface of the semiconductor substrate, wherein the isolation portion has a lower dopant concentration than the second conductive type region;
an anti-reflective film formed over substantially the entirety of the first conductive type region;
a passivation film formed over substantially the entirety of the second conductive type region and the isolation portion;
a first electrode connected to the first conductive type region through the anti-reflective film; and
a second electrode connected to the second conductive type region through the passivation film; wherein the semiconductor substrate comprises a base region in which the first and second conductive type regions are not disposed;
wherein the second conductive type region has a boundary portion in direct contact with the isolation portion, and in which a doping concentration of the boundary portion is changed linearly in relation to a distance from the edge of the semiconductor substrate at a predetermined slope,
wherein the second conductive type region comprises an effective area in direct contact with the boundary portion; wherein a doping concentration of the base region is a first concentration and a doping concentration of the effective area is a second concentration, the doping concentration of the boundary portion changes from a third concentration less than the second concentration and greater than the first concentration to the first concentration, and the third concentration is 1×1015/cm2 or more;
wherein a width of the isolation portion is smaller than a distance between the edge of the semiconductor substrate and an end of the second electrode that is closest to the edge of the semiconductor substrate,
wherein the second electrode is connected to the effective area of the second conductive type region,
wherein the second electrode includes:
a plurality of finger electrodes extended in a first direction; and
a plurality of bus bar electrodes extended in a second direction crossing the first direction, and
wherein the second conductive type region includes a first portion corresponding to the plurality of finger electrodes.

US Pat. No. 10,141,466

SUBSTRATE FOR SOLAR CELL, AND SOLAR CELL

SHIN-ETSU CHEMICAL CO., L...

1. A method for manufacturing a solar cell using a silicon substrate of square shape with corners as viewed in plan view, having a first corner and a second corner not diagonal to the first corner, which is provided with a chamfer at the first corner or a notch at or near the first corner and with a notch at or near the second corner or a chamfer at the second corner, the notch or chamfer at the second corner is selected to be different from the chamfer or notch at the first corner,wherein the first and second corners are used to identify the direction of the substrate and discriminate the front and back surfaces of the substrate during manufacturing.

US Pat. No. 10,141,465

EPITAXIAL LIFT-OFF PROCESSED GAAS THIN-FILM SOLAR CELLS INTEGRATED WITH NON-TRACKING MINI-COMPOUND PARABOLIC CONCENTRATORS

The Regents of the Univer...

1. A method for integrating a thin-film solar cell with non-tracking miniconcentrators, said method comprising:providing a growth substrate;
depositing at least one protection layer on the growth substrate;
depositing at least one sacrificial layer on the at least one protection layer;
depositing a photoactive cell on the sacrificial layer, wherein the photoactive cell is inverted;
forming a patterned metal layer comprising an array of mesas on the photoactive cell by a photolithography method, wherein the mesas are separated by one or more trenches that extend through the patterned metal layer and the photoactive cell to the sacrificial layer;
bonding the patterned metal layer to a metallized surface of a plastic sheet;
etching the sacrificial layer with one or more etch steps that remove the photoactive cell from the growth substrate to form thin film solar cells bonded to the plastic sheet;
dicing the thin film solar cells bonded to the plastic sheet along the one or more trenches;
fabricating compound parabolic concentrators from a plastic material; and
transferring the thin film solar cells onto the compound parabolic concentrators by an adhesive-free bonding step to form an integrated thin film solar cell and compound parabolic concentrator.

US Pat. No. 10,141,464

SOLAR CELL MODULE

LG ELECTRONICS INC., Seo...

1. A solar cell module comprising:a plurality of bi-facial solar cells having a front surface and a back surface, respectively, wherein light is incident to both of the front surface and the back surface of each of the plurality of bi-facial solar cells;
a light transmission protection part positioned on the front surfaces of the plurality of bi-facial solar cells;
a front protection part positioned between the light transmission protection part and the front surfaces of the plurality of bi-facial solar cells;
a back sheet positioned on the back surfaces of the plurality of bi-facial solar cells, wherein the back sheet includes a first area overlapping the plurality of bi-facial solar cells and having a first transmittance, and a second area being a remaining portion except the first area and having a second transmittance different from the first transmittance; and
a back protection part positioned between the back sheet and the back surfaces of the plurality of bi-facial solar cells,
wherein the back sheet includes:
a base layer,
a first sheet layer positioned between a first surface of the base layer and the back protection part,
a second sheet layer selectively positioned on a second surface of the base layer to correspond to the second area, and
a third sheet layer positioned on the second surface of the base layer and on the second sheet layer.

US Pat. No. 10,141,463

PHOTOVOLTAIC DEVICES AND METHODS FOR MAKING THE SAME

First Solar Malaysia SDN....

1. A photovoltaic device, comprising:a support layer;
a cadmium and tellurium layer comprising cadmium and tellurium, and being of p-type; and
a transparent conductive oxide layer;
wherein the photovoltaic device is free of a CdS layer,
wherein the cadmium and tellurium layer comprises zinc, selenium, mercury, lead, or any combination thereof,
wherein a concentration of the zinc, selenium, mercury, lead, or any combination thereof within the cadmium and tellurium layer is compositionally graded, and
wherein a total atomic percentage of the zinc, selenium, mercury, lead, or any combination thereof of the cadmium and tellurium layer is up to about 10 atomic %.

US Pat. No. 10,141,462

SOLAR CELLS HAVING DIFFERENTIATED P-TYPE AND N-TYPE ARCHITECTURES

SunPower Corporation, Sa...

1. A solar cell, comprising:an N-type semiconductor substrate having a light-receiving surface and a back surface;
a plurality of N-type polycrystalline silicon regions disposed on a first thin dielectric layer disposed on the back surface of the N-type semiconductor substrate; and
a plurality of P-type polycrystalline silicon regions disposed on a second thin dielectric layer disposed in a corresponding one of a plurality of trenches interleaving the plurality of N-type polycrystalline silicon regions in the back surface of the N-type semiconductor substrate, wherein a total area of the plurality of N-type polycrystalline silicon regions is greater than a total area of the plurality of P-type polycrystalline silicon regions in the plurality of corresponding trenches.

US Pat. No. 10,141,461

TEXTURED MULTI-JUNCTION SOLAR CELL AND FABRICATION METHOD

INTERNATIONAL BUSINESS MA...

1. A multi junction photovoltaic device, comprising:a semiconductor layer having substantially symmetrical pyramidal shapes with (111) facets exposed to form a textured surface;
a first p-n junction formed directly on the textured surface; and
at least one other p-n junction formed over the first p-n junction and following the textured surface.

US Pat. No. 10,141,460

PHOTOVOLTAIC STRUCTURE FOR A ROADWAY

COLAS, Boulogne Billanco...

1. A roadway comprising:(i) a road having a surface made of bituminous mixes or made of cement concrete, and
(ii) a photovoltaic structure comprising:
(a) at least one photovoltaic module adhesively bonded directly to the surface of the road, and
(b) a non-opaque surfacing comprising:
(1) a non-opaque matrix covering the at least one photovoltaic module, and
(2) non-opaque texturing elements embedded in the non-opaque matrix,
wherein the non-opaque texturing elements form reliefs of different shapes and different sizes on an outer surface of the non-opaque surfacing, the reliefs giving an irregular macrotexture and an irregular microtexture to the outer surface, with a mean texture depth measured according to the NF EN 13036-1 standard of between 0.2 mm and 3 mm and a polished stone value (PSV) of resistance to polishing according to the NF EN 13043 standard of at least PSV44.

US Pat. No. 10,141,459

BINARY GLASS FRITS USED IN N-TYPE SOLAR CELL PRODUCTION

1. A solar cell precursor comprising as precursor partsi. a wafer with a back face and a front face, wherein the front face comprises a p-doped layer;
ii. a first paste comprising
Ag particles;
Al particles in a range from about 0.01 to about 5 wt. %, based on the total weight of the paste;
a vehicle;
a glass frit in a range from about 0.1 to about 5 wt. %, based on the total weight of the paste, wherein the glass frit comprises a first glass frit with a glass transition temperature Tgl and a further glass frit with a glass transition temperature Tgf, wherein both Tgl and Tgf are in a range from 320 to 500° C., and wherein Tgf differs from Tgl by at least 50° C.; and
an additive, wherein the first paste is superimposed on a first area on said p-doped layer.

US Pat. No. 10,141,458

VERTICAL GATE GUARD RING FOR SINGLE PHOTON AVALANCHE DIODE PITCH MINIMIZATION

OmniVision Technologies, ...

1. A photon detection device, comprising:a single photon avalanche diode (SPAD) disposed in a first region of a first semiconductor layer, wherein the SPAD includes a multiplication junction defined at an interface between an n doped layer and a p doped layer of the SPAD in the first region of the first semiconductor layer;
a vertical gate structure disposed in the first semiconductor layer proximate to the SPAD, wherein the vertical gate structure surrounds the SPAD to isolate the SPAD in the first region of the first semiconductor layer from a second region of the first semiconductor layer on an opposite side of the vertical gate structure, wherein the n doped layer and the p doped layer of the SPAD laterally extend within the first region of the first semiconductor layer to contact the vertical gate structure; and
a depletion layer generated around a perimeter of the SPAD at an interface of the vertical gate structure and the p doped layer in response to a gate bias voltage coupled to the vertical gate structure, wherein the depletion layer isolates the SPAD from the second region of the first semiconductor layer on the opposite side of the vertical gate structure.

US Pat. No. 10,141,457

SOLAR CELL

LG ELECTRONICS INC., Seo...

1. A solar cell comprising:a crystalline silicon semiconductor substrate of a first conductive type;
an emitter region having a second conductive type different from the first conductive type and at a first surface of the crystalline silicon semiconductor substrate, wherein the emitter region forms a p-n junction along with the crystalline silicon semiconductor substrate;
a silicon carbide layer directly on a second surface opposite the first surface of the crystalline silicon semiconductor substrate configured to form a first charge accumulation layer in the second surface of the crystalline silicon semiconductor substrate, and having a first impurity doping concentration of the first conductive type, the first charge accumulation layer to accumulate charge caused by a difference in band gap between the crystalline silicon semiconductor substrate and the silicon carbide layer;
a first electrode on the first surface of the crystalline silicon semiconductor substrate and coupled to the emitter region;
a heavily doped region under the first electrode and containing impurities of a second conductive type at a doping concentration higher than the crystalline semiconductor substrate and a second charge accumulation layer;
a second electrode on the second surface of the crystalline silicon semiconductor substrate and coupled to the crystalline silicon semiconductor substrate;
a surface field region partially in the second surface of the crystalline silicon semiconductor substrate and having a second impurity doping concentration of the first conductive type higher than the first impurity doping concentration of the silicon carbide layer; and
an anti-reflection part on the emitter region,
wherein the silicon carbide layer has a plurality of openings and the second electrode contacts the surface field region through the plurality of openings of the silicon carbide layer,
wherein a conduction band average energy level of the crystalline silicon semiconductor substrate is higher than a conduction band average energy level of the silicon carbide layer, and
wherein an amount of impurities contained of the silicon carbide layer is 1×1018/cm3 to 5×1020/cm3, and
wherein the emitter region is formed of a silicon carbide to form the second charge accumulation layer in the first surface of the crystalline silicon semiconductor substrate to accumulate charge caused by a difference in band gap between the crystalline silicon semiconductor substrate and the emitter region.

US Pat. No. 10,141,456

SCHOTTKY DIODE AND METHOD FOR ITS MANUFACTURING

Fraunhofer Gesellschaft Z...

1. A Schottky diode comprising:a drift region comprising diamond having a first conductivity type;
a plurality of junction barrier Schottky regions comprising diamond having a second conductivity type opposite the first conductivity type and being arranged on a top of the drift region and separated by spaces;
at least one Schottky contact being applied to the top of the drift region, thereby covering the junction barrier Schottky regions and filling the spaces between the junction barrier Schottky regions; and
at least one Ohmic contact on the drift region.

US Pat. No. 10,141,455

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode;
a second electrode, the first electrode and the second electrode being aligned with respect to a first direction;
an insulating region, the insulating region and the second electrode being aligned with respect to a second direction crossing the first direction, wherein the first direction and the second direction are orthogonal;
a first semiconductor region of a first conductivity type provided between the first electrode and the second electrode and between the first electrode and the insulating region, the first semiconductor region being in contact with the first electrode;
a second semiconductor region of a second conductivity type provided between the first semiconductor region and the second electrode and between the first semiconductor region and the insulating region, the second semiconductor region being in contact with the second electrode; and
a third semiconductor region of the first conductivity type provided between the second semiconductor region and the insulating region, the third semiconductor region being in contact with the first semiconductor region.

US Pat. No. 10,141,454

FIELD-EFFECT TRANSISTORS HAVING BLACK PHOSPHORUS CHANNEL AND METHODS OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a phosphorene-containing layer over a substrate, wherein a channel region, a source region, and a drain region are defined in the phosphorene-containing layer, and further wherein the channel region is disposed between a source region and a drain region; and
forming a passivation layer over the source region and the drain region defined in the phosphorene-containing layer.

US Pat. No. 10,141,453

SEMICONDUCTOR DEVICE

SHARP KABUSHIKI KAISHA, ...

1. A semiconductor device comprising:a substrate; and
a thin film transistor supported on the substrate, the thin film transistor including a gate electrode, an oxide semiconductor layer, a gate insulating layer provided between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode electrically connected to the oxide semiconductor layer,
a signal line connected to the source electrode and a scanning line connected to the gate electrode, the scanning line extending along a first direction and the signal line extending along a second direction crossing the first direction,wherein:the drain electrode, the source electrode and the oxide semiconductor layer are arranged in line along either the first direction or the second direction;
the source electrode is shaped so as to project along the second direction, and the drain electrode is arranged so as to oppose the source electrode with the oxide semiconductor layer interposed therebetween;
the drain electrode is shaped so as to project toward the oxide semiconductor layer;
a width W1 and a width W2 satisfy a relationship |W1?W2|?1 ?m, where the width W1 is a width of the oxide semiconductor layer in a channel width direction of the thin film transistor, and the width W2 is a width of the drain electrode in a direction perpendicular to a direction in which the drain electrode projects;
the width W1 and the width W2 are 3 ?m or more and 6 ?m or less;
the oxide semiconductor layer and the drain electrode are misaligned from each other in the first direction; and
a width W3 is 1 ?m or more and is less than the width W1, where the width W3 is a width in the first direction of an overlapping portion between the oxide semiconductor layer and the drain electrode.

US Pat. No. 10,141,452

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising the steps of:forming an insulating layer over an oxide semiconductor layer;
forming a groove in the insulating layer;
forming a conductive film over the insulating layer such that a part of the conductive film is provided in the groove;
forming a gate electrode layer by removing the conductive film partially such that the part of the conductive film remains in the groove;
etching the insulating layer such that at least part of the insulating layer which overlaps the oxide semiconductor layer is removed after forming the gate electrode layer; and
forming a source region and a drain region by adding an ion to the oxide semiconductor layer using the gate electrode layer as a mask after etching the insulating layer.

US Pat. No. 10,141,451

ELECTRODE LAYER, THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising an active layer, and a source electrode and a drain electrode on the active layer;wherein each of the source electrode and the drain electrode comprises a combination of a metal electrode sub-layer that is substantially non-transparent, and a diffusion barrier sub-layer between the metal electrode sub-layer and the active layer;
wherein the diffusion barrier sub-layer is made of a material comprising M1OaNb doped with one or more metal element, one or more non-metal element, or a combination thereof, wherein M1 is a single metal or a combination of metals, a?0, and b>0.

US Pat. No. 10,141,449

OXIDE THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An oxide thin film transistor, comprising:a gate oxide layer; and
an oxide channel layer comprising a front channel oxide layer and a back channel oxide layer, the front channel oxide layer located between the back channel oxide layer and the gate oxide layer and in contact with the gate oxide layer, a conduction band bottom of the back channel oxide layer higher than a conduction band bottom of the front channel oxide layer, and a band gap of the back channel oxide layer larger than a band gap of the front channel oxide layer;
wherein a material of the back channel oxide layer is the same as a material of the front channel oxide layer, the material of the back channel oxide layer includes ion-doping, and the material of the front channel oxide layer includes no ion-doping or includes ion-doping different from that of the material of the back channel oxide layer.

US Pat. No. 10,141,448

VERTICAL FETS WITH DIFFERENT GATE LENGTHS AND SPACER THICKNESSES

International Business Ma...

1. A method of forming a vertical field effect transistor (VFET) device, the method comprising the steps of:patterning fins having a uniform fin height in a substrate, wherein at least a first one of the fins comprises a vertical fin channel of a first VFET and wherein at least a second one of the fins comprises a vertical fin channel of a second VFET;
forming bottom source and drains at a base of the fins, wherein the bottom source and drains are doped;
forming first bottom spacers on the bottom source and drains at the base of the fins;
selectively forming second bottom spacers on the first bottom spacers at the base of the at least one second fin, wherein the second bottom spacers are configured to serve as a dopant source;
annealing the substrate under conditions sufficient to drive dopants i) from the bottom source and drains into the at least one first fin and ii) from the bottom source and drains and from the second bottom spacers into the at least one second fin, forming bottom junctions at the base of the at least one first fin having a height H1 and bottom junctions at the base of the at least one second fin having a height H2, wherein H2>H1;
forming gates along sidewalls of the fins above the bottom source and drains, wherein the gates along the sidewalls of the at least one first fin have a gate length Lg1 and the gates along the sidewalls of the at least one second fin have a gate length Lg2, wherein Lg1>Lg2 based on H2>H1;
forming top spacers above the gates at tops of the fins; and
forming top source and drains above the top spacers at the tops of the fins.

US Pat. No. 10,141,447

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A semiconductor device, comprising:an active fin extended in a first direction on a substrate;
a gate structure extended in a second direction, wherein the gate structure intersects the active fin, and covers an upper portion of the active fin;
a source/drain region on the active fin adjacent to the gate structure;
a silicide layer on the source/drain region;
a contact plug connected to the source/drain region; and
a void between the silicide layer and the contact plug.

US Pat. No. 10,141,446

FORMATION OF BOTTOM JUNCTION IN VERTICAL FET DEVICES

GLOBALFOUNDRIES Inc., Gr...

1. A vertical FinFET device comprising:a semiconductor substrate;
a fin disposed on said semiconductor substrate, said fin having a top surface and substantially vertical sides;
an epitaxially grown semiconductor material defining a bottom junction disposed below at least one of said vertical sides of said fin;
a gate structure disposed adjacent to at least said vertical sides of said fin;
a top junction disposed adjacent said top surface of said fin; and
wherein said epitaxially grown semiconductor material extends under a portion of said fin and comprises tapering surfaces juxtaposed under said fin.

US Pat. No. 10,141,445

VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS

International Business Ma...

1. A semiconductor structure comprising at least:a substrate;
at least one alternating stack of semiconductor material layers and metal gate material layers disposed on the substrate;
a metal gate disposed on and in contact with the alternating stack of semiconductor material layers and metal gate material layers;
a source region;
a drain region;
a first plurality of epitaxially grown interconnects formed on and in contact with outer sidewalls of the alternating stack and outer sidewalls of the source region; and
a second plurality of epitaxially grown interconnects formed on and in contact with outer sidewalls of the alternating stack and outer sidewalls of the drain region,
wherein the source and drain regions are absent from direct contact with the at least one alternating stack.

US Pat. No. 10,141,444

OXIDE THIN-FILM TRANSISTOR WITH ILLUMINATED OHMIC CONTACT LAYERS, ARRAY SUBSTRATE AND METHODS FOR MANUFACTURING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing an oxide thin-film transistor, comprising:forming a pattern of a light shielding layer on a base substrate that is made of a light-transmissive material, wherein the light shielding layer is made of an organic material;
forming a pattern of an oxide semi-conductor layer above the base substrate, wherein an orthographic projection of the pattern of the light shielding layer onto the base substrate is completely located within and is smaller than an orthographic projection of the pattern of the oxide semi-conductor layer onto the base substrate;
providing the ultraviolet light source at a side of the base substrate away from the light shielding layer;
illuminating, by the ultraviolet light source, two opposite boundary regions of the pattern of the oxide semi-conductor layer that are not shielded by the light shielding layer, wherein the illuminated two opposite boundary regions of the pattern of the oxide semi-conductor layer form ohmic contact layers and a region of the pattern of the oxide semi-conductor layer that is not illuminated forms a semi-conductor active layer;
forming a gate insulator on the semi-conductor active layer and forming a gate electrode on the gate insulator; and
forming a source electrode and a drain electrode, wherein the source electrode and the drain electrode are connected to the semi-conductor active layer via the ohmic contact layers respectively,
wherein the oxide thin-film transistor is of a top-gate structure, and the gate electrode is arranged between the semi-conductor active layer and the source electrode and the drain electrode in a direction in which the semi-conductor active layer, the gate insulator, and the gate electrode are stacked, and the light shielding layer is sandwiched between the oxide semi-conductor layer and the base substrate.

US Pat. No. 10,141,443

SEMICONDUCTOR DEVICES FINFET DEVICES WITH OPTIMIZED STRAINED-SOURECE-DRAIN RECESS PROFILES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate;
a gate stack over the substrate; and
a strained layer in a recess of the substrate and aside the gate stack,
wherein a ratio of a depth at the greatest width of the recess to a width of the gate stack ranges from about 0.5 to 0.7,
wherein the semiconductor device further comprises a spacer on a sidewall of the gate stack, a top edge of the recess is covered by and spaced apart from an outer edge of the spacer, a sidewall of the recess connecting the top edge and a bottom edge of the recess is a curved surface without a sharp turning point, and an included angle between an upper portion of the sidewall of the recess and a surface of the substrate is from about 50 degrees to 90 degrees, and
wherein the substrate is a substrate with at least one fin extending in a first direction, and the gate stack extends in a second direction different from the first direction and is across the at least one fin.

US Pat. No. 10,141,442

SEMICONDUCTOR DEVICE HAVING TIPLESS EPITAXIAL SOURCE/DRAIN REGIONS

INTEL CORPORATION, Santa...

1. A semiconductor device, comprising:a gate stack on a substrate, wherein the gate stack is comprised of a metallic gate electrode above a portion of the substrate, and a gate dielectric layer between the metallic gate electrode and the portion of the substrate, the gate dielectric layer also along sidewalls of the metallic gate electrode, the gate dielectric layer comprising a top high-k dielectric portion and a bottom portion having a dielectric constant less than or equal to a dielectric constant of silicon dioxide;
a pair of source/drain regions in the substrate, the portion of the substrate between the pair of source/drain regions, wherein a lattice constant of the pair of source/drain regions is different than a lattice constant of the portion of the substrate, and wherein at least a portion of the pair of source/drain regions is under a portion of the gate dielectric layer and under a portion of the metallic gate electrode;
a shallow trench isolation structure laterally adjacent to one of the pair of source/drain regions; and
an inter-layer dielectric layer directly laterally adjacent to and in contact with a portion of the gate dielectric layer along the sidewalls of the metallic gate electrode, the inter-layer dielectric layer over the pair of source/drain regions, the inter-layer dielectric layer also over the shallow trench isolation structure;
wherein the pair of source/drain regions have an undercut profile of approximately 55 degrees with respect to an uppermost surface of the substrate, the undercut profile extending from the gate dielectric layer into the substrate, such that the undercut profile commences from and is in contact with a bottommost surface of the bottom portion of the gate dielectric layer; and
wherein a top surface of the one of the pair of source/drain regions that is laterally adjacent to the shallow trench isolation structure is higher than a top surface of the shallow trench isolation structure.

US Pat. No. 10,141,441

VERTICAL TRANSISTOR WITH BACK BIAS AND REDUCED PARASITIC CAPACITANCE

INTERNATIONAL BUSINESS MA...

1. A method of making a vertical transistor device, the method comprising:forming a front gate and a back gate opposite a major surface of a substrate, the front gate and the back gate being symmetric and arranged on opposing sides of a channel between the front gate and the back gate, the channel extending from a drain to a source;
forming a mask to cover the front gate;
removing the back gate; and
replacing the back gate with a layer of insulator and another back gate stack, the another back gate stack only covering a junction between the channel and the source, and remaining portions of the back gate being the layer of insulator.

US Pat. No. 10,141,440

DRIFT-REGION FIELD CONTROL OF AN LDMOS TRANSISTOR USING BIASED SHALLOW-TRENCH FIELD PLATES

Polar Semiconductor, LLC,...

1. A Laterally-Diffused Metal-Oxide-Semiconductor (LDMOS) transistor comprising:a substrate layer;
an active device layer vertically adjacent to and separated from the substrate layer by a metallurgical junction, the active device layer comprising:
a source;
a body having a body contact region and a channel region; and
a drain having a drain contact region and a drift region, the drift region laterally extending from a drift-region/body metallurgical junction and a drift-region/drain-contact-region interface; and
an interconnect layer vertically adjacent to and separated from the active device layer by an interface surface, the interconnect layer comprising:
a gate extending from a first end located above the source, over the channel region, and to a second end located above the drift region; and
one or more contacts providing electrical connection between one or more nets in the interconnect layer and each of the source, the body contact region and the drain contact region in the active device layer; and
a pair of adjacent trenches vertically extending from the interface surface to a dielectric trench bottom, the trenches laterally separated from one another by the drift region, each of the trenches having first and second conductive field plates longitudinally separated from one another by an intervening dielectric, the first and second conductive field plates electrically connected to one or more biasing circuit nets in the interconnection layer, the first and second conductive field plates separated from the drift region by a dielectric material.

US Pat. No. 10,141,439

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a first GaN based semiconductor layer of a first conductive type;
a second GaN based semiconductor layer of the first conductive type provided above the first GaN based semiconductor layer, the second GaN based semiconductor layer having an impurity concentration of the first conductive type lower than that of the first GaN based semiconductor layer;
a third GaN based semiconductor layer of a second conductive type provided above a part of the second GaN based semiconductor layer;
a fourth GaN based semiconductor layer of the first conductive type provided above the third GaN based semiconductor layer, the fourth GaN based semiconductor layer having the impurity concentration of the first conductive type higher than that of the second GaN based semiconductor layer;
a gate insulating film provided on the second GaN based semiconductor layer, the third GaN based semiconductor layer, and the fourth GaN based semiconductor layer;
a gate electrode provided on the gate insulating film;
a first electrode provided on the fourth GaN based semiconductor layer;
a second electrode provided at a side of the first GaN based semiconductor layer opposite to the second GaN based semiconductor layer;
a third electrode provided on the second GaN based semiconductor layer; and
a plurality of fifth GaN based semiconductor layers of the second conductive type provided above a part of the second GaN based semiconductor layer, the plurality of fifth GaN based semiconductor layers surrounding the first electrode and the third electrode, the plurality of fifth GaN based semiconductor layers being provided to be separated from each other, the plurality of fifth GaN based semiconductor layers having substantially the same impurity concentration of the second conductive type as the third GaN based semiconductor layer;
wherein the first electrode is provided in a groove having a bottom-face and side-faces, the third GaN based semiconductor layer is exposed to the bottom-face, the fourth GaN based semiconductor layer is exposed to the side-faces, and the first electrode is in contact with the third GaN based semiconductor layer.

US Pat. No. 10,141,438

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate;
a first III-V compound layer over the substrate;
a first passivation layer on the first III-V compound layer;
a source electrode penetrating the first passivation layer to electrically contact the first III-V compound layer; and
a drain electrode penetrating the first passivation layer to electrically contact the first III-V compound layer,
wherein a lower portion of the source electrode directly surrounded by the first passivation layer, the lower portion comprising:
an upper part having a first width; and
a lower part having a second width, the first width being greater than the second width; and
wherein an upper portion of the source electrode further comprises a third width measured from one side to an opposite side of an outer circumference of the upper portion, the third width being smaller than the first width.

US Pat. No. 10,141,437

EXTREME HIGH MOBILITY CMOS LOGIC

Intel Corporation, Santa...

1. A transistor, comprising:a doped silicon semi-insulating substrate;
a buffer layer disposed above the doped silicon semi-insulating substrate;
a bottom barrier layer disposed above the buffer layer wherein the bottom barrier layer comprises a material different than the buffer layer;
a group III-V material quantum well layer disposed above the bottom barrier layer;
a top barrier layer disposed above the group III-V material quantum well layer;
a gate stack disposed above the top barrier layer, the gate stack comprising:
a high-k gate dielectric layer disposed above the top barrier layer; and
a metal gate electrode disposed above the high-k gate dielectric layer; and
a semiconductor cap layer on an etch stop layer on the top barrier layer, wherein the gate stack is in an opening through the semiconductor cap layer.

US Pat. No. 10,141,436

TUNNEL FIELD EFFECT TRANSISTOR HAVING ANISOTROPIC EFFECTIVE MASS CHANNEL

Purdue Research Foundatio...

1. A tunnel field effect transistor (TFET) device, comprising:a substrate;
heavily doped source and drain regions disposed at opposite ends of the substrate separated by a channel region, where the channel region is intrinsic or lightly doped with doping of less than 1018/cm3 and the source and drain regions doped with doping of between about 1018/cm3 to about 1021/cm3, collectively forming a structure wherein the structure is PiN or NiP;
a gate terminal separated from the channel region by a dielectric layer;
a source and drain terminal coupled to the source and drain regions, respectively,
the channel region comprising a channel material having a first effective mass along a longitudinal axis extending from the source region to the drain region and a second effective mass along a lateral axis perpendicular to the longitudinal axis, wherein a ratio of the first effective mass to the second effective mass is between 1 and 50, the channel region comprising a first substantially parallelogram portion having a first length defined along a longitudinal axis extending from the source region to the drain region and a second substantially parallelogram portion connected to the first substantially parallelogram portion having a second length defined along the longitudinal axis and larger than the first length, the TFET device having an effective channel length defined along the longitudinal axis that is an average of the first and second lengths.

US Pat. No. 10,141,434

COMPLEMENTARY TUNNELING FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

Huawei Technologies Co., ...

1. A complementary tunneling field effect transistor, comprising:a first drain region and a first source region disposed on a substrate, wherein the first drain region and the first source region comprise a first dopant;
a first channel disposed on the first drain region and a second channel disposed on the first source region;
a second source region disposed on the first channel and a second drain region disposed on the second channel, wherein the second source region and the second drain region comprise a second dopant;
a first epitaxial layer disposed on the first drain region and the second source region, and a second epitaxial layer disposed on the second drain region and the first source region, wherein the first epitaxial layer covers a side wall of the first channel and the second source region, and the second epitaxial layer covers a side wall of the second channel and the second drain region;
a first gate stack layer disposed on the first epitaxial layer, and a second gate stack layer disposed on the second epitaxial layer;
a first isolator disposed on the second source region and the first drain region, and a second isolator disposed on the first source region and the second drain region, wherein the first isolator is in contact with the first epitaxial layer and the first gate stack layer, and the second isolator is in contact with the second epitaxial layer and the second gate stack layer; and
wherein the first drain region, the first channel, the second source region, the first epitaxial layer, and the first gate stack layer form a first tunneling field effect transistor, and the second drain region, the second channel, the first source region, the second epitaxial layer, and the second gate stack layer form a second tunneling field effect transistor.

US Pat. No. 10,141,433

METHOD OF MANUFACTURING THIN FILM TRANSISTOR

Wuhan China Star Optoelec...

1. A method of manufacturing a thin film transistor, comprising the steps of:depositing a first metal layer on the top surface of the substrate, and patterning the first metal layer to form a gate electrode;
depositing a gate insulating layer, a semiconductor material and an etching stop layer sequentially on the gate electrode;
patterning the etching stop layer by a first mask to form a stopper directly above gate electrode;
depositing a second metal layer covering the stopper and the semiconductor material;
using a second mask and a photoresist to form a source electrode region, a drain electrode region and a channel region on the surface of the second metal layer;
etching the periphery region of the source electrode region, the drain electrode region and the channel region to expose the gate insulating layer;
removing the photoresist and etching the second metal layer within the channel, and forming a source electrode and a drain electrode by the remaining second metal layer; and
irradiating the bottom of the substrate by UV light to enhance the conductivity of the region of the semiconductor material contacted with the source electrode and the drain electrode.

US Pat. No. 10,141,432

SEMICONDUCTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate;
a first gate structure comprising a first distal end;
a second gate structure being spaced apart from the first gate structure and aligned with the first gate structure, the second gate structure comprising a second distal end facing the first distal end, wherein the first gate structure and the second gate structure are extended in a straight line and superimposed along a cross-sectional view;
a first cut slot between the first distal end and the second distal end, wherein the first cut slot is disposed between two separate gate structures directly above a first isolation structure, the two separate gate structures are the first and second gate structures extending in the same straight line;
a liner layer on interior surface of the first cut slot; and
a dielectric layer on the liner layer, wherein the first cut slot is completely filled with the liner layer and the dielectric layer.

US Pat. No. 10,141,431

EPITAXY SOURCE/DRAIN REGIONS OF FINFETS AND METHOD FORMING SAME

Taiwan Semiconductor Manu...

1. A method comprising:forming isolation regions extending into a semiconductor substrate, wherein the forming the isolation regions comprises:
in a common etching process, etching the semiconductor substrate to form two first trenches and a second trench between the two first trenches;
forming a hard mask layer comprising first bottom portions extending to bottoms of the two first trenches, and a second bottom portion extending to a bottom of the second trench;
performing an etching step, wherein both the two first bottom portions and the second bottom portion are exposed to an etchant used in the etching step, and the first bottom portions and portions of the semiconductor substrate directly underlying the first bottom portions are etched to extend the two first trenches down, and the second bottom portion protects a portion of the semiconductor substrate directly underlying the second bottom portion; and
filling the two first trenches and the second trench with a dielectric material to form isolation regions;
recessing the isolation regions, so that portions of semiconductor strips between the isolation regions protrude higher than the isolation regions to form semiconductor fins;
recessing the semiconductor fins to form recesses;
epitaxially growing a first semiconductor material from the recesses;
etching the first semiconductor material; and
epitaxially growing a second semiconductor material from the first semiconductor material that has been etched back.

US Pat. No. 10,141,430

FIN STRUCTURES WITH UNIFORM THRESHOLD VOLTAGE DISTRIBUTION AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device structure, comprising:determining a threshold voltage distribution profile along a height of a silicon germanium (SiGe) fin structure over a semiconductor substrate;
determining a germanium (Ge) concentration profile to counteract the threshold voltage distribution profile according to a correlation between Ge concentration and threshold voltage in the SiGe fin structure;
forming a SiGe epitaxial layer with the Ge concentration profile along a thickness of the SiGe epitaxial layer;
etching the SiGe epitaxial layer to form the SiGe fin structure; and
forming, on the SiGe fin structure, a field-effect transistor having a uniform threshold voltage along the height of the SiGe fin structure.

US Pat. No. 10,141,429

FINFET HAVING ISOLATION STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of making a transistor, comprising:forming a fin structure protruding from an upper surface of a substrate, the fin structure extending along a first direction and comprising a lower portion and an upper portion;
forming a first isolation structure over the upper surface of the substrate and surrounding the lower portion of the fin structure;
patterning a recess in the fin structure;
depositing a second isolation structure in the recess;
forming a gate structure over the fin structure and extending along a second direction different from the first direction, the gate structure and the fin structure defining a non-overlapping region in the upper portion of the fin structure, wherein the patterning the recess in the fin structure comprises patterning the recess in the non-overlapping region of the fin structure; and
forming a drain contact region in the non-overlapping region of the fin structure, the second isolation structure being between the drain contact region and the gate structure.

US Pat. No. 10,141,428

FIN FORMATION IN FIN FIELD EFFECT TRANSISTORS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a plurality of fins from a first material, the plurality of fins formed over a substrate and defining troughs therebetween;
depositing a semiconductor layer formed from a second material over the plurality of fins, the second material being different than the first material;
depositing dielectric material covering the plurality of fins and the semiconductor layer, the dielectric material defining dielectric regions;
diffusing the second material from the semiconductor layer into an entirety of each fin of the plurality of fins;
removing the dielectric regions; and
planarizing an upper surface of the dielectric regions to be planar with an upper surface of the plurality of fins.

US Pat. No. 10,141,427

METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES INCLUDING GATE PATTERN, MULTI-CHANNEL ACTIVE PATTERN AND DIFFUSION LAYER

Samsung Electronics Co., ...

1. A method for fabricating a semiconductor device comprising:forming a multi-channel active pattern protruding from an isolation layer;
forming a dummy gate pattern on the multi-channel active pattern, the dummy gate pattern overlapping a portion of the multi-channel active pattern;
after forming the dummy gate pattern on the multi-channel active pattern, forming a pre-liner layer on a top surface of the multi-channel active pattern not overlapping the dummy gate pattern;
forming an impurity supply layer on a top surface of the pre-liner layer that is on the multi-channel active pattern not overlapping the dummy gate pattern;
forming a first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern by performing a first thermal process on the impurity supply layer at a first temperature; and
after forming the first diffusion layer in the multi-channel active pattern not overlapping the dummy gate pattern, forming a second diffusion layer in the multi-channel active pattern along an outer periphery of the multi-channel active pattern not overlapping the dummy gate pattern by performing a second thermal process on the impurity supply layer at a second temperature.

US Pat. No. 10,141,426

VERTICAL TRANSISTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A vertical transistor device comprising:a semiconductor substrate including a substrate material;
a first semiconductor fin forming a vertical channel region comprising a semiconductor material arranged on the semiconductor substrate;
a first source/drain region comprising a first portion directly vertically beneath the semiconductor material of the first semiconductor fin and a second portion, the first portion comprising a doped portion of the semiconductor substrate arranged below and in contact with the second portion, the second portion comprising a doped epitaxially grown semiconductor material, the doped epitaxially grown semiconductor material being a dissimilar material from the substrate material, and the first source/drain region comprising a graduated doping concentration profile that extends from the doped epitaxially grown semiconductor material to the vertical channel region;
a first spacer layer arranged directly on the second portion of the first source/drain region;
a first gate stack arranged directly on the first spacer layer, the first gate stack comprising gate dielectric material, a work function metal, and a conductive metal; a sidewall of the first gate stack directly contacting a sidewall of the first semiconductor fin, and a top surface of the first semiconductor fin arranged above a top surface of the first gate stack; and
a second spacer layer arranged directly on the first gate stack and extending higher than the first semiconductor fin;
wherein the first gate stack of the vertical transistor device wraps around horizontal sides of the vertical channel region, and the conductive metal of the first gate stack is arranged in contact the second spacer layer.

US Pat. No. 10,141,425

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming a first oxide semiconductor layer over and in contact with an insulating surface;
forming a second oxide semiconductor layer over the first oxide semiconductor layer;
performing first heat treatment in a first atmosphere after the step of forming the second oxide semiconductor layer;
forming a third oxide semiconductor layer over the second oxide semiconductor layer;
forming an insulating film over and in contact with the third oxide semiconductor layer; and
performing second heat treatment after the step of forming the insulating film,
wherein the first atmosphere is any one of a nitrogen atmosphere, an oxygen atmosphere, and a dry-air atmosphere.

US Pat. No. 10,141,424

METHOD OF PRODUCING A CHANNEL STRUCTURE FORMED FROM A PLURALITY OF STRAINED SEMICONDUCTOR BARS

IBM CORPORATION, Yorktow...

1. A Method for fabricating a structure with semiconducting bars suitable for forming at least one transistor channel, including:providing at least a semiconducting structure on a substrate, composed of an alternation of first bars based on at least a first material and second bars based on at least a second material, the second material being a semiconducting material, the first bars and the second bars being stacked, then
forming a sacrificial gate and first insulating spacers on each side of the sacrificial gate, then
removing regions of the stack located on each side of the insulating spacers, then
removing end portions from the first bars by selective etching of the first material relative to the second material so as to expose spaces around the ends of the second bars,
forming of internal spacers in said spaces around said ends of the second bars, then
forming of semiconducting source and drain blocks by growth of at least one semiconducting material on each side of the insulating spacers and the internal spacers,
then,
removing exposed portions of the structure based on the first material through an opening in a mask formed on the structure, the removal being made by selective etching in the opening of the first material relative to the second material, so as to expose a space around a central portion of the second bars, then
growing or depositing a layer of a semiconducting material around the second bars in the opening such that the semiconducting material is in contact with the second bars, the semiconducting material having a mesh parameter different from the mesh parameter of the second material so as to induce a strain on the layer of the semiconducting material.

US Pat. No. 10,141,423

THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A fabrication method of a thin film transistor (TFT), comprising steps of:forming a protection layer in an area above an active layer between a source electrode and a drain electrode to be formed;
forming a source-drain metal layer above the active layer having the protection layer formed thereabove;
coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area and a photoresist non-reserved area, wherein the photoresist reserved area corresponds to areas of the source electrode and the drain electrode to be formed, and the photoresist non-reserved area corresponds to the other area;
etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source electrode and the drain electrode and expose the protection layer above the active layer; and
removing the photoresist above the source electrode and the drain electrode and the protection layer.

US Pat. No. 10,141,422

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INTEGRATING A VERTICAL CONDUCTION TRANSISTOR, AND SEMICONDUCTOR DEVICE

STMICROELECTRONICS S.R.L....

1. A vertical conduction device, comprising:a semiconductor body;
a first conduction terminal which extends at a first side of the semiconductor body;
a second conduction terminal which extends at a second side opposite to the first side of the semiconductor body;
a control terminal configured to be biased to generate a conductive channel between the first and second conduction terminals;
a silicon oxide seed layer within the semiconductor body;
a polycrystalline silicon region of the semiconductor body, the polycrystalline silicon region extending in contact with, and over the seed layer;
a monocrystalline silicon region of the semiconductor body, which surrounds the seed layer; and
an implanted region, which extends in the semiconductor body in said polycrystalline silicon region and forms a conductive path between the first side of the semiconductor body and the second conduction terminal.

US Pat. No. 10,141,421

VERTICAL POWER MOSFET AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor layer of a first conductivity type;
a first and a second body region over the semiconductor layer, wherein the first and the second body regions are of a second conductivity type opposite to the first conductivity type;
a doped semiconductor region of the first conductivity type between and contacting the first and the second body regions, wherein the doped semiconductor region has a bottom portion extending into the semiconductor layer to separate a top surface layer of the semiconductor layer into a first region and a second region;
a gate dielectric layer over the first and the second body regions and the doped semiconductor region; and
a first gate electrode and a second gate electrode over the gate dielectric layer, and overlapping the first and the second body regions, respectively, wherein the first and the second gate electrodes are physically separated from each, and are electrically interconnected, and wherein the doped semiconductor region is overlapped by a region between the first and the second gate electrodes.

US Pat. No. 10,141,420

TRANSISTORS WITH DIELECTRIC-ISOLATED SOURCE AND DRAIN REGIONS

International Business Ma...

1. A method of forming a semiconductor device, comprising:forming a sacrificial layer on source/drain regions of a semiconductor layer;
forming a reactant layer on the sacrificial layer;
annealing the reactant layer and the sacrificial layer to convert the reactant layer to a dielectric layer; and
forming source and drain regions on the dielectric layer.

US Pat. No. 10,141,419

TWO-STEP DUMMY GATE FORMATION

Taiwan Semiconductor Manu...

1. A device comprising:a semiconductor substrate;
isolation regions extending into the semiconductor substrate;
a semiconductor fin between opposite portions of the isolation regions, wherein the semiconductor fin is higher than top surfaces of the isolation regions;
a gate stack on a top surface and opposite sides of the semiconductor fin; and
a gate spacer contacting a sidewall of the gate stack, wherein the gate spacer comprises:
a lower portion having a first inner edge contacting a sidewall of the gate stack; and
an upper portion over the lower portion, the upper portion having a second inner edge contacting the sidewall of the gate stack, wherein the first inner edge and the second inner edge are in different vertical planes.

US Pat. No. 10,141,418

DEVICE WITH HETEROEPITAXIAL STRUCTURE MADE USING A GROWTH MASK

STC.UNM, Albuquerque, NM...

5. A device comprising:a semiconductor substrate;
a seed area delineated with a selective growth mask on the semiconductor substrate, the seed area comprising a first material and having a linear surface dimension of less than 100 nm; and
a heteroepitaxial layer grown on the seed area, the heteroepitaxial layer comprising a second material that is different from the first material,
wherein the heteroepitaxial layer is a vertical nanowire, the vertical nanowire being doped to provide a source region, a drain region and a gate region, the device forming a vertical transistor.

US Pat. No. 10,141,417

GATE STRUCTURE, SEMICONDUCTOR DEVICE AND THE METHOD OF FORMING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A gate structure comprising:a gate stack comprising:
a doped work function metal (WFM) stack; and
a metal gate electrode overlying the doped WFM stack;
a doped oxide layer in physical contact with a first portion of a sidewall of the gate stack, wherein a surface of the doped oxide layer that extends away from the gate stack and is facing away from a semiconductor substrate is planar; and
a doped spacer over and contacting the doped oxide layer, wherein the doped spacer is in physical contact with a second portion of the sidewall of the gate stack, wherein the doped WFM stack has a dopant concentration lower than a dopant concentration of the doped spacer.

US Pat. No. 10,141,416

SEMICONDUCTOR STRUCTURE WITH ENLARGED GATE ELECTRODE STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

8. A method for manufacturing a semiconductor structure, comprising:forming a trench over a substrate;
forming a gate dielectric layer on sidewalls and a bottom of the trench;
forming a plurality of conductive layers over the gate dielectric layer on the sidewalls and the bottom of the trench;
forming a blocking structure in a lower portion of the trench over the plurality of conductive layers;
etching a portion of each of the plurality of conductive layers not covered by the blocking structure, wherein the etching forms a sloped top surface of each of the plurality of conductive layers, wherein the sloped top surface extends from a termination point level with and interfacing a top surface of the blocking structure upwards towards another termination point closer a nearest sidewall of the trench;
after the etching, removing the blocking structure; and
after removing the blocking structure, depositing at least one additional conductive gate layer over the etched plurality of conductive layers.

US Pat. No. 10,141,415

COMBINED GATE AND SOURCE TRENCH FORMATION AND RELATED STRUCTURE

Infineon Technologies Ame...

1. A method of forming a semiconductor device, said method comprising:forming a semiconductor substrate including a drain region, a drift region above said drain region, a base region above said drift region, and a source region above said base region, said drain region, said drift region and said source region having a first conductivity type and said base region having a second conductivity type opposite said first conductivity type;
forming a gate trench and a first portion of a source trench in said semiconductor substrate and both extending into said drift region to a same first depth in said semiconductor substrate, said first portion of said source trench being wider than said gate trench;
forming a gate electrode in said gate trench;
after forming said gate trench and said first portion of said source trench, forming a second portion of said source trench under said first portion and extending deeper into said drift region than said first portion, said second portion being narrower than said first portion and extending to a second depth in said semiconductor substrate greater than said first depth;
lining sidewalls of said first portion, sidewalls of said second portion and a bottom of said second portion with a dielectric material; and
forming a conductive filler in said source trench, said conductive filler insulated from the surrounding semiconductor substrate by said dielectric material.

US Pat. No. 10,141,414

NEGATIVE CAPACITANCE MATCHING IN GATE ELECTRODE STRUCTURES

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:forming a negative capacitor portion of a gate electrode structure of a transistor element adjacent and capacitively coupled to a floating electrode portion of said gate electrode structure; and
adjusting a negative capacitance of said negative capacitor portion by independently adjusting an effective capacitive area of a dielectric material of said negative capacitor portion and a thickness of said dielectric material.

US Pat. No. 10,141,413

WAFER STRENGTH BY CONTROL OF UNIFORMITY OF EDGE BULK MICRO DEFECTS

Taiwan Semiconductor Manu...

1. A method for processing a disk-shaped semiconductor wafer, the method comprising:receiving a disk-shaped semiconductor wafer;
providing the disk-shaped semiconductor wafer to a semiconductor manufacturing system, wherein the semiconductor manufacturing system comprises a plurality of successive semiconductor processing steps configured to form an integrated circuit (IC), and wherein one of the successive semiconductor processing steps comprises a thermal process;
initiating a scanning electron microscope to measure an oxygen concentration or a density of bulk micro defects (BMDs) at a plurality of locations in a peripheral region of the disk-shaped semiconductor wafer extending about ten millimeters inwardly from an outermost edge of the disk-shaped semiconductor wafer;
subtracting a minimum measured oxygen concentration or minimum measured BMD from a maximum measured oxygen concentration or maximum measured BMD, respectively, to determine a max/min difference;
dividing the max/min difference by an average of the measured oxygen concentrations or average of the measured BMDs, respectively, to determine a threshold value of the disk-shaped semiconductor wafer;
if the threshold value of the disk-shaped semiconductor wafer is outside a predetermined range comprising a statistical profile of oxygen concentration ranging between approximately 9.5 parts per million atomic and approximately 11.5 parts per million atomic, removing the disk-shaped semiconductor wafer from the semiconductor manufacturing system such that the disk-shaped semiconductor wafer is prevented from undergoing the thermal process; and
if the threshold value of the disk-shaped semiconductor wafer is inside the predetermined range comprising the statistical profile of oxygen concentration, forming the IC on the disk-shaped semiconductor wafer in the semiconductor manufacturing system, wherein forming the IC comprises the disk-shaped semiconductor wafer undergoing the thermal process.

US Pat. No. 10,141,412

FIELD EFFECT TRANSISTOR USING TRANSITION METAL DICHALCOGENIDE AND A METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A field effect transistor (FET), comprising:a gate dielectric layer;
a channel layer formed on the gate dielectric layer; and
a gate electrode, wherein:
the channel layer includes a body region having a first side and a second side opposite to the first side, the body region being a channel of the FET,
the channel layer further includes first finger regions each protruding from the first side of the body region and second finger regions each protruding from the second side of the body region,
a source electrode covers the first finger regions, and a drain electrode covers the second finger regions,
the channel layer is a single layer or multiple layers of MoS2,
each of the first finger regions and each of the second finger regions extend along a first direction, and
the first direction corresponds to a zigzag edge structure of the MoS2 layer, which extends perpendicular to atomic bonds located at the edge.

US Pat. No. 10,141,411

TEMPERATURE SENSING SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate of silicon carbide, wherein the semiconductor substrate includes a portion in which an n-type drift region and a p-type body region are laminated through an epitaxial growth technique by depositing the n-type drift region on the semiconductor substrate and then by depositing the p-type body region on the n-type drift region; and
a temperature sensor portion disposed in the semiconductor substrate and separated from the drift region by the body region,
wherein the body region extends from the temperature sensor portion through the areas having a plurality of trench gates, and
wherein the temperature sensor portion comprises:
an n-type cathode region being in contact with the body region; and
a p-type anode region separated from the body region by the cathode region.

US Pat. No. 10,141,410

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE AND ELEVATOR

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:an n-type SiC region;
an electrode in contact with the n-type SiC region; and
a region including oxygen, the region provided in the n-type SiC region, the region being provided adjacent to the electrode, the region being SiC.

US Pat. No. 10,141,409

THIN FILM TRANSISTOR AND ARRAY SUBSTRATE THEREOF EACH HAVING DOPED OXIDIZED OR DOPED GRAPHENE ACTIVE REGION AND OXIDIZED GRAPHENE GATE INSULATING LAYER AND PRODUCING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A thin film transistor, comprising: a source electrode, a drain electrode, a gate electrode; an active region and a gate insulating layer, wherein, the source electrode, the drain electrode and the gate electrode are composed of graphene, the active region is composed of doped oxidized graphene, the gate insulating layer is composed of oxidized graphene,and wherein, the graphene composing the source electrode, the drain electrode and the gate electrode is formed by reducing oxidized graphene, and the doped oxidized graphene composing the active region is formed by treating oxidized graphene.

US Pat. No. 10,141,408

METHOD AND ARRANGEMENT FOR REDUCING CONTACT RESISTANCE OF TWO-DIMENSIONAL CRYSTAL MATERIAL

INSTITUTE OF MICROELECTRO...

1. A method, comprising:forming a contact material layer on a two-dimensional crystal material layer, the contact material layer forming an electrical contact to the two-dimensional crystal material layer;
performing ion implantation on at least the two-dimensional crystal material layer, to bombard the two-dimensional crystal material layer so as to create vacancies therein; and
performing thermal annealing of the contact material layer and the two-dimensional crystal material layer for interaction of the vacancies with the contact material layer and implanted ions, so that they form bonds to modify a contact interface between the contact material layer and the two-dimensional crystal material layer.

US Pat. No. 10,141,407

GRAPHENE DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

8. A graphene device comprising:a first electrode;
a graphene layer on the first electrode;
a second electrode and a third electrode spaced apart from each other on the graphene layer, the third electrode being directly formed on the graphene layer;
an insulation layer between the graphene layer and the second electrode, the second electrode being configured to adjust a work function of the graphene layer; and
an information storage layer between the graphene layer and the first electrode, the information storage layer configured to store an electric charge,
wherein the insulation layer and the third electrode are directly formed on a same surface of the graphene layer, the third electrode and the insulation layer are spaced apart from each other on top of a same surface of the graphene layer, and
wherein the information storage layer includes a high-k dielectric material layer.

US Pat. No. 10,141,406

TENSILE STRAINED NFET AND COMPRESSIVELY STRAINED PFET FORMED ON STRAIN RELAXED BUFFER

International Business Ma...

1. A fabrication method, comprising:obtaining a structure including a substrate and a strain relaxed silicon germanium buffer layer on the substrate;
forming an epitaxial silicon germanium layer on a first region of the strain relaxed buffer layer, the epitaxial silicon germanium layer being doped with dopants of a first conductivity type;
forming a tensile strained layer comprising silicon directly on the epitaxial silicon germanium layer;
forming an epitaxial relaxed layer comprising silicon on a second region of the strain relaxed buffer layer, the epitaxial relaxed layer being doped with dopants of a second conductivity type that is opposite in polarity to the first conductivity type;
forming a compressively strained silicon germanium layer directly on the epitaxial relaxed layer;
electrically isolating the first and second regions;
forming first and second recesses extending respectively within the first and second regions of the strain relaxed silicon germanium buffer layer; and
forming the epitaxial silicon germanium layer within the first recess and forming the epitaxial relaxed layer within the second recess;
wherein the strain relaxed buffer layer has at least a top region having the composition Si1-xGex where x is between 0.2 and 0.3, the epitaxial silicon germanium layer has the composition Si1-yGey where y is equal to or exceeds x by 0.02 or less, and the compressively strained silicon germanium layer has the composition Si1-zGez where z is between 0.2 and 0.3.

US Pat. No. 10,141,405

LATERAL BIPOLAR JUNCTION TRANSISTOR WITH ABRUPT JUNCTION AND COMPOUND BURIED OXIDE

International Business Ma...

1. A method of forming a lateral bipolar junction transistor (LBJT) comprising:providing a germanium containing material on a nucleation dielectric layer with a bonding method;
patterning the germanium containing material selectively to the nucleation dielectric layer to form a base region present overlying a pedestal of the passivating layer;
forming emitter and collector extension regions on opposing sides of the base region; and
forming an emitter region and collector region on exposed portions of the nucleation dielectric layer extending into contact with the emitter and collector extension regions.

US Pat. No. 10,141,404

POWER SEMICONDUCTOR DEVICE HAVING FULLY DEPLETED CHANNEL REGION

Infineon Technologies AG,...

1. A power semiconductor device, comprising:a semiconductor body coupled to a first load terminal structure and a second load terminal structure and configured to conduct a load current;
a first cell and a second cell, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first mesa included in the first cell, the first mesa including a first port region having the first conductivity type and being electrically connected to the first load terminal structure, and a first channel region being coupled to the drift region;
a second mesa included in the second cell, the second mesa including a second port region having a second conductivity type and being electrically connected to the first load terminal structure, and a second channel region being coupled to the drift region;
each of the first mesa and the second mesa being spatially confined, in a direction perpendicular to a direction of the load current within the respective mesa, by an insulation structure and having a total extension of less than 100 nm in the direction, wherein the insulation structure houses:
a control electrode structure for controlling the load current within the first mesa and the second mesa, the control electrode structure being electrically insulated from the first load terminal structure; and
a guidance electrode electrically insulated from the control electrode structure and arranged in between the first mesa and the second mesa,
wherein the control electrode structure is configured to induce an inversion channel within the first channel region and an accumulation channel within the second channel region.

US Pat. No. 10,141,403

INTEGRATING THIN AND THICK GATE DIELECTRIC NANOSHEET TRANSISTORS ON SAME CHIP

International Business Ma...

13. A semiconductor structure, comprising:a single nanosheet stack formed over a substrate;
a thin gate dielectric nanosheet transistor formed by fabricating a first portion of the single nanosheet stack, the thin gate dielectric nanosheet transistor including a plurality of nanosheets separated from each other by a first distance; and
a thick gate dielectric nanosheet transistor formed by fabricating a second portion of the single nanosheet stack, the thick gate dielectric nanosheet transistor including a plurality of nanosheets separated from each other by a second distance, the second distance being greater than the first distance.

US Pat. No. 10,141,402

FINFET DEVICES

INTERNATIONAL BUSINESS MA...

1. A structure comprising a plurality of fin structures which are supported by lined insulator material, wherein the lined insulator material is provided on an in-situ doped material.

US Pat. No. 10,141,401

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:performing a first plasma etching process on a substrate to form a first trench in the substrate, wherein the first plasma etching process uses a first etching gas and a first deposition gas, the first trench surrounds a first portion of the substrate, the first portion has a top surface and a first inclined surface, the first inclined surface connects the top surface to a bottom surface of the first trench, and the first inclined surface is inclined relative to the top surface at a first angle;
removing a second portion of the substrate under the bottom surface to form a second trench under and connected to the first trench, wherein the second trench surrounds a third portion of the substrate under the first portion, the third portion has a first sidewall, the first sidewall is inclined relative to the top surface at a second angle, and the first angle is greater than the second angle;
forming an isolation structure in the first trench and the second trench, wherein the isolation structure has a second inclined surface, and the first inclined surface and the second inclined surface form second sidewalls of a recess;
forming a gate insulating layer over the top surface and the first inclined surface, wherein the gate insulating layer extends into the recess and partially covers the second inclined surface, the recess is filled with the gate and the gate insulating layer, and the gate is over the isolation structure partially; and
forming a gate over the gate insulating layer and the isolation structure, wherein the gate crosses the first portion, and the gate extends into the recess.

US Pat. No. 10,141,400

SEMICONDUCTOR DEVICES INCLUDING FIELD EFFECT TRANSISTORS WITH DUMMY GATES ON ISOLATION

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a device isolation layer on a substrate to define an active region;
a first gate electrode on the active region extending in a first direction parallel to a top surface of the substrate;
a second gate electrode on the device isolation layer and spaced apart from the first gate electrode in the first direction;
a gate spacer between the first gate electrode and the second gate electrode; and
source/drain regions in the active region at opposite sides of the first gate electrode,
wherein the source/drain regions are spaced apart from each other in a second direction that is parallel to the top surface of the substrate and crossing the first direction, and
wherein, when viewed in a plan view, an entirety of the first gate electrode is spaced apart from a boundary between the active region and the device isolation layer.

US Pat. No. 10,141,399

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a second semiconductor region of the first conductivity type provided on a portion of the first semiconductor region, an impurity concentration of the first conductivity type of the second semiconductor region being lower than an impurity concentration of the first conductivity type of the first semiconductor region;
a third semiconductor region of a second conductivity type provided on the second semiconductor region; and
a first insulating layer provided on another portion of the first semiconductor region, the first insulating layer being provided around the portion of the first semiconductor region, the second semiconductor region, and at least a portion of the third semiconductor region, the first insulating layer contacting the third semiconductor region,
a length in a second direction of the first semiconductor region being longer than a length in the second direction of the second semiconductor region and being longer than a distance from one end portion in the second direction of the first insulating layer to one other end portion in the second direction of the first insulating layer,
the second direction being orthogonal to a first direction from the second semiconductor region toward the third semiconductor region,
any semiconductor region which opposes to the second semiconductor region with the first insulating layer interposed being not provided.

US Pat. No. 10,141,398

HIGH VOLTAGE MOS STRUCTURE AND ITS MANUFACTURING METHOD

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a high-voltage (HV) NMOS structure, comprising:
a source region and a drain region separated from each other;
a channel region disposed between the source region and the drain region, the channel region having a channel direction from the source region toward the drain region;
a gate dielectric disposed on the channel region and on portions of the source region and the drain region; and
a gate electrode disposed on the gate dielectric, the gate electrode comprising:
a first portion of n-type doping; and
two second portions of p-type doping disposed at two sides of the first portion, the two second portions having an extending direction perpendicular to the channel direction;
wherein the HV NMOS structure further comprises:
a substrate;
a first n-type doped region and a second n-type doped region disposed in the substrate and separated from each other;
an isolation structure disposed in the substrate, the isolation structure having a first through opening and a second through opening in the first n-type doped region and the second n-type doped region, respectively;
a first n-type heavily doped region and a second n-type heavily doped region disposed in the first through opening and the second through opening, respectively;
wherein the first n-type doped region and the first n-type heavily doped region are disposed in the source region, and the second n-type doped region and the second n-type heavily doped region are disposed in the drain region.

US Pat. No. 10,141,397

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) forming a first epitaxial layer of a first conductivity type over a semiconductor substrate;
(b) forming a first trench in the first epitaxial layer;
(c) filling the first trench with a semiconductor material of a second conductivity type opposite to the first conductivity type;
(d) after the step (c), forming a second epitaxial layer of the first conductivity type over the first epitaxial layer including the first trench filled with the semiconductor material;
(e) forming a second trench in the second epitaxial layer, the second trench being planarly superposed on the first trench and connected with the first trench;
(f) filling the second trench with the semiconductor material of the second conductivity type; and
(g) after the step (f), forming an element section over the second epitaxial layer.

US Pat. No. 10,141,396

PROTECTED ELECTRONIC CHIP

STMicroelectronics (Rouss...

1. An electronic chip, comprising:a doped semiconductor substrate of a first conductivity type;
a doped buried layer of a second conductivity type overlying the doped semiconductor substrate;
a first doped well of the first conductivity type overlying the doped buried layer;
a first wall of the second conductivity type in contact with the doped buried layer and surrounding the first doped well;
circuit components formed at a top surface of the first doped well and separated from the doped buried layer; and
a current detector coupled to the doped buried layer and connected between a node configured to carry a voltage potential and the first wall, the current detector configured to detect a bias current flowing into or out of the doped buried layer, wherein the current detector comprises:
a resistor coupled between the node configured to carry the voltage potential and the first wall;
an inverter with an input coupled to the node configured to carry the voltage potential;
a comparator coupled across the resistor, the comparator having a positive input coupled to the first wall and a negative input coupled to the node configured to carry the voltage potential; and
an OR gate with a first input coupled to an output of the inverter and a second input coupled to an output of the comparator.

US Pat. No. 10,141,395

HIGH-K METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

INTERNATIONAL BUSINESS MA...

1. A metal-insulator-metal (MIM) capacitor, comprising, in a cross-sectional view:a first metal plate;
a second metal plate;
a third metal plate; and
a layer of high-k material contacting the first metal plate, the second metal plate, and the third metal plate.

US Pat. No. 10,141,394

INTEGRATED CIRCUIT COMPRISING A METAL-INSULATOR-METAL CAPACITOR AND FABRICATION METHOD THEREOF

IMEC vzw, Leuven (BE)

1. An integrated circuit (IC) comprising:a semiconductor substrate; and
a plurality of metallization levels, each metallization level comprising a layer of intermetal dielectric having metal areas embedded therein,
a metal-insulator-metal capacitor (MIMCAP) comprising a bottom electrode, a top electrode and a metal-insulator-metal (MIM) stack comprising a lower conductive layer, an upper conductive layer and an insulator layer sandwiched between the lower and upper conductive layers,
wherein the bottom electrode comprises a planar metal area of a lower metallization level, the planar metal area having perforations formed therethrough,
wherein the IC comprises cavities, each cavity extending through one of the perforations and into the semiconductor substrate, each cavity being separated from edges of a corresponding perforation by a first intermetal dielectric material of the lower metallization level,
wherein the MIM stack comprises a planar portion of the MIM stack on at least a part of an upper surface of the bottom electrode and a plurality of non-planar portions of the MIM stack extending into the cavities, the MIM stack lining the sidewalls and bottoms of the cavities, and
wherein the top electrode comprises:
a planar portion of the top electrode formed by a planar metal area of an upper metallization level adjacent to the lower metallization level, wherein the planar portion of the top electrode is formed on at least a part of an upper surface of the planar portion of the MIM stack, and wherein the planar portion of the top electrode has sidewalls lined by portions of the MIM stack, and
non-planar portions of the top electrode extending from the planar portion of the top electrode into the cavities.

US Pat. No. 10,141,393

THREE DIMENSIONAL CAPACITOR

Cypress Semiconductor Cor...

1. A device, comprising:a first conductor disposed directly on a substrate, wherein a bottom surface of the first conductor is in contact with a semiconducting portion of the substrate and the first conductor further includes a top surface, first and second sidewalls;
a dielectric structure disposed at least partly over the first conductor; and
a second conductor disposed over and covering the dielectric structure partly, wherein the second conductor is not disposed over the top surface of the first conductor.

US Pat. No. 10,141,392

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR STRUCTURE WITH AN EMBEDDED CAPACITOR

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic capacitor plate structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic capacitor plate structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a high-k dielectric material on a surface of the first metallic capacitor plate structure or the second metallic capacitor plate structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the high-k dielectric material and the first metallic capacitor plate structure or the second metallic capacitor plate structure.

US Pat. No. 10,141,391

MICROSTRUCTURE MODULATION FOR 3D BONDED SEMICONDUCTOR CONTAINING AN EMBEDDED RESISTOR STRUCTURE

International Business Ma...

11. A method of forming a three-dimensional (3D) bonded semiconductor structure, the method comprising:providing a first semiconductor structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and a first metallic pad structure having a columnar grain microstructure embedded in the first bonding oxide layer, and a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and a second metallic pad structure having a columnar grain microstructure embedded in the second bonding oxide layer;
forming a metal resistor structure on a recessed surface of the first metallic pad structure or the second metallic pad structure; and
bonding the first semiconductor structure to the second semiconductor structure, wherein the bonding provides a bonding interface between the first and second bonding oxide layers and another bonding interface between the metal resistor structure and the first metallic pad structure or the second metallic pad structure.

US Pat. No. 10,141,390

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting apparatus, comprising:a substrate comprising an active area, a dead area surrounding the active area, and a pad area in an outer region of the dead area;
at least one thin-film transistor disposed in the active area, the at least one thin-film transistor comprising an active pattern, a gate electrode, a source electrode, and drain electrode;
at least one pixel electrode disposed in the active area and electrically connected to one of the source electrode and the drain electrode;
a common electrode facing the substrate and comprising a protrusion, the protrusion being disposed at an end portion of the common electrode adjacent to the pad area and extending towards the pad area;
a first voltage supply unit disposed on the dead area and the pad area and contacting the protrusion of the common electrode, the first voltage supply unit being configured to apply a first voltage to the common electrode;
a second voltage supply unit overlapping the common electrode, and spaced apart and electrically insulated therefrom; and
an insulating layer disposed over the active area and the dead area, and between the common electrode and the second voltage supply unit,
wherein:
the common electrode is disposed on the at least one thin-film transistor and the at least one pixel electrode; and
an end portion of the insulating layer adjacent to the first voltage supply unit contacts an end portion of the first voltage supply unit adjacent to the active area.

US Pat. No. 10,141,389

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:a first flexible substrate which has a first side, a second side, a third side, and a fourth side in a plan view, the first flexible substrate including a display region and a peripheral region surrounding the display region in the plan view, each of a first length of the first side and a third length of the third side being smaller than each of a second length of the second side and a fourth length of the fourth side;
pixels arranged on the display region;
a first wiring which is arranged inside the first flexible substrate, the first wiring including a first extending portion extending in a first direction and a first turn back portion extending in a second direction opposite to the first direction, the first extending portion including a first portion and a second portion, the first turn back portion including a third portion and a fourth portion, one end of the first portion connected to one end of the second portion, another end of the second portion connected to one end of the third portion, another end of the third portion connected to one end of the fourth portion, each of the second and third portions exhibiting a first shape-memory-effect; and
a second wiring which is arranged inside the first flexible substrate, the second wiring including a second extending portion extending in the first direction and a second turn back portion extending in the second direction, one end of the second extending portion connected to one end of the second turn back portion, each of the second extending portion and the second turn back portion exhibiting a second shape-memory-effect, wherein
each of the first side and the third side extends in a third direction perpendicular to the first direction and the second direction,
each of the second side and the fourth side extends in the first direction,
a part of each of the second and third portions overlaps with a part of each of the second extending portion and the second turn back portion as seen from the third direction, and
another part of each of the second and third portions overlaps with no part of each of the second extending portion and the second turn back portion as seen from the third direction.

US Pat. No. 10,141,388

DISPLAY DEVICE WITH TRANSISTOR SAMPLING FOR IMPROVED PERFORMANCE

SONY CORPORATION, Tokyo ...

1. An apparatus comprising:a plurality of pixels arranged in a matrix form, each of the pixels including a capacitor, a first transistor, a second transistor, and a light emitting element;
a plurality of first lines that extend along a first direction and connected to the pixels;
a plurality of second line that extend along a second direction and connected to the pixels, the second direction being perpendicular to the first direction;
wherein,
(a) each of the first lines includes a first lower wiring portion, a second lower wiring portion, and an upper wiring portion, and
(b) in each of the first lines:
(i) the upper wiring portion is connected to the first lower wiring portion via a first plurality of contact holes formed in an insulating film, and connected to the second lower wiring portion via a second plurality of contact holes formed in the insulating film,
(ii) the upper wiring portion is on the insulating film,
(iii) the insulating film is on the lower wiring portion,
(iv) the power supply line crosses the first lower wiring portion, and
(v) the second lower wiring portion crosses a corresponding one of the second lines.

US Pat. No. 10,141,387

DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising: a substrate; a light emitting diode disposed above the substrate; a first transistor disposed above the substrate and comprising: a first semiconductor layer; a first top gate electrode disposed above the first semiconductor layer; a first bottom gate electrode disposed under the first semiconductor layer; a first source electrode electrically connected to the first semiconductor layer; and a first drain electrode electrically connected to the first semiconductor layer, wherein the first drain electrode is electrically connected to the light emitting diode; and a second transistor disposed above the substrate and comprising a second semiconductor layer; wherein one of the first semiconductor layer and the second semiconductor layer comprises a first silicon semiconductor layer, and the other comprises a first oxide semiconductor layer, wherein the second transistor further comprises a first gate electrode and a second gate electrode, the first gate electrode is disposed above the second semiconductor layer, and the second gate electrode is disposed under the second semiconductor layer, wherein the second transistor further comprises a second drain electrode electrically connected to the second semiconductor layer, and the second drain electrode is electrically connected to the first source electrode through a conductive line or by direct contact, wherein the second transistor further comprises a second source electrode electrically connected to the second semiconductor layer, and the second source electrode is electrically connected to the first drain electrode through a conductive line or by direct.

US Pat. No. 10,141,386

ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising: a base substrate, a plurality of pixel units disposed on a side of the base substrate, a chip for providing signal to the plurality of pixel units, and signal lines corresponding to each of the plurality of the pixel units,wherein the chip is disposed on an opposed side of the base substrate having the plurality of pixel units disposed thereon,
wherein via holes penetrating at least the base substrate are disposed on the array substrate,
wherein the signal lines electrically connect each of the plurality of the pixel units to the chip through the via holes,
wherein the signal lines comprise wires that comprise first wires and second wires, the first wires at least comprise gate lines, and the second wires at least comprise data lines, and
wherein the chip at least comprises a gate driving chip connected to the gate lines and a source driving chip connected to the data lines.

US Pat. No. 10,141,385

THIN FILM TRANSISTOR SUBSTRATE AND DISPLAY PANEL USING SAME

HON HAI PRECISION INDUSTR...

1. A thin film transistor (TFT) substrate, the TFT substrate defining a display area and a non-display area surrounding the display area, the TFT substrate comprising:a substrate;
a plurality of first scanning lines on the substrate and in the display area, each of the plurality of first scanning lines extending along a first direction;
a plurality of data lines on the substrate and in the display area, each of the plurality of data lines extending along a second direction that is different from the first direction, each of the plurality of data lines electrically insulated from the plurality of first scanning lines;
a conductive layer on the substrate and above the plurality of first scanning lines;
at least one electrically insulating layer on the substrate and between the plurality of first scanning lines and the conductive layer;
a touch sensing layer on the substrate and above the conductive layer;
wherein the conductive layer forms a plurality of second scanning lines in the display area and a plurality of touch traces; each of the plurality of touch traces is electrically coupled to the touch sensing layer; each of the plurality of second scanning lines is electrically coupled to one of the plurality of first scanning lines by extending through the at least one electrically insulating layer.

US Pat. No. 10,141,384

ORGANIC ELECTROLUMINESCENT PANEL AND LUMINESCENT UNIT

Joled Inc., Tokyo (JP)

1. An organic electroluminescent panel comprising:a plurality of pixels each including a plurality of subpixels, the subpixels each including an organic electroluminescent element, the organic electroluminescent element including a first electrode, a second electrode, and an organic material layer that is provided between the first electrode and the second electrode; and
a plurality of banks that define each of the subpixels in each of the pixels,
the organic electroluminescent element in each of the subpixels being provided in a gap between adjacent two of the plurality of banks, and
the following relational expression being satisfied:
y?0.0001714x2+0.0151429x+0.2914286
where y denotes a height, from a bottom surface of the gap, of a pinning position at which a surface of the organic material layer and one of the banks are in contact with each other, and x denotes a width of the bottom surface of the gap.

US Pat. No. 10,141,383

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:a lower substrate and an upper substrate;
a bank layer on the lower substrate to define a plurality of sub-pixel areas;
a cathode provided on the lower substrate, the cathode covering the plurality of sub-pixel areas and the bank layer;
an auxiliary electrode provided on the upper substrate, the entire auxiliary electrode being positioned between two immediately adjacent sub-pixel areas among the plurality of pixel areas defined by the bank layer;
a connection assistance unit provided on at least one of the lower substrate and the upper substrate, wherein the connection assistance unit is positioned to make the auxiliary electrode on the upper substrate be in contact with the cathode on the lower substrate,
wherein the auxiliary electrode has a hydrophobic property.

US Pat. No. 10,141,382

METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DIODE DISPLAY PANEL HAVING POLYMER NETWORK LIQUID CRYSTAL

Samsung Display Co., Ltd....

1. A method of manufacturing an organic light emitting diode display panel, comprising:forming a lower substrate, the lower substrate comprising a first area and a second area;
forming an organic light emitting device on the lower substrate;
disposing a polymer network liquid crystal on the organic light emitting device;
forming a second optical layer in the second area, the second optical layer comprising the polymer network liquid crystal; and
varying an optical property of the polymer network liquid crystal so as to form a first optical layer in the first area in which the first optical layer has a first refractive index different than a second refractive index of the second optical layer.

US Pat. No. 10,141,381

ORGANIC LIGHT-EMITTING DIODE (OLED) ARRAY SUBSTRATE, METHOD OF MANUFACTERING THE SAME, AND RELATED DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An Organic Light Emitting Diode (OLED) array substrate, comprising:a plurality of pixels arranged in an array on a base substrate, wherein:
each pixel comprises a first sub-pixel and a second sub-pixel displaying different colors;
each sub-pixel comprises a light emitting unit and a control circuit; and
an orthogonal projection of the control circuit of the second sub-pixel on the base substrate completely covers an orthogonal projection of the light emitting unit of the first sub-pixel on the base substrate.

US Pat. No. 10,141,380

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device, comprising:a plurality of pixels, each of the plurality of pixels having a plurality of first sub pixels, at least one second sub pixel, and at least one third sub pixel,
wherein the plurality of first sub pixels of one pixel of the plurality of pixels are disposed along a first line extended in a first direction,
wherein the at least one second sub pixel of the one pixel is disposed on one side of the first line and the at least one third sub pixel of the one pixel is disposed on the other side of the first line,
wherein the at least one second sub pixel and the at least one third sub pixel of the one pixel are disposed along a second line extended in a second direction different from the first direction, and
wherein a reference pixel among the plurality of pixels and an adjacent pixel adjacent to the reference pixel in the second direction are symmetric with respect to a boundary line between the reference pixel and the adjacent pixel.

US Pat. No. 10,141,379

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE WITH REDUCED REFLECTANCE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode display device comprising:a display panel including a plurality of pixels, at least one pixel among the plurality of pixels including a first sub-pixel, a second sub-pixel, a third sub-pixel and a fourth sub-pixel defined at intersection regions between a plurality of gate lines and a plurality of data lines; and
a first color filter layer, a second color filter layer and a third color filter layer corresponding to the first sub-pixel, the third sub-pixel and the fourth sub-pixel, respectively,
wherein the second sub-pixel includes:
an emission area,
a first color filter pattern disposed in the second sub-pixel for absorbing light incident from an outside of the organic light emitting diode display device, extending beyond opposite outer edges of the emission area, and disposed in parallel with the gate line, the first color filter pattern and the second sub-pixel corresponding to different colors, and
a second color filter pattern disposed in the second sub-pixel for absorbing light incident from an outside of the organic light emitting diode display device, having an outer perimeter fully within the emission area, separated from the first color filter pattern, and disposed in parallel with the gate line, and
wherein the first color filter pattern has a different color than the second color filter pattern.

US Pat. No. 10,141,378

LIGHT EMITTING DEVICE FREE OF TFT AND CHIPLET

INDUSTRIAL TECHNOLOGY RES...

1. A light emitting device, comprising:a first electrode layer;
an organic light emitting layer formed on the first electrode layer; and
a second electrode layer formed on the organic light emitting layer,
wherein the organic light emitting layer is sandwiched between the first electrode layer and the second electrode layer, the second electrode layer includes a plurality of electrode patterns separated from one another, the electrode patterns of the second electrode correspond to a plurality of monochromatic blocks and have different sizes or numbers to form different density, and the electrode patterns are divided into a plurality of electrode pattern groups that are arranged in an alternate manner, wherein each of the electrode patterns is free from being connected to a thin film transistor (TFT) and a chiplet.

US Pat. No. 10,141,377

ELECTROLUMINESCENT DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An electroluminescent display device comprising:a substrate on which first and second pixel regions are defined;
a passivation layer over the substrate;
a first electrode in each of the first and second pixel regions on the passivation layer;
a bank layer exposing the first electrode;
a light emitting layer on the first electrode exposed by the bank layer; and
a second electrode on the light emitting layer,
wherein the bank layer includes first and second openings exposing the first electrodes corresponding to the first and second pixel regions, respectively,
wherein the bank layer further includes a third opening exposing the first electrode corresponding to a third pixel region,
wherein a depth of the first opening is larger than a depth of the third opening,
wherein a height of the bank layer of the third pixel region is smaller than a height of the bank layer of the first pixel region, and
wherein the passivation layer has a groove in the second opening of the second pixel region, and each of the bank layer of the first and second pixel regions has a same height.

US Pat. No. 10,141,376

ORGANIC PHOTOELECTRONIC DEVICE AND IMAGE SENSOR

Samsung Electronics Co., ...

1. An organic photoelectronic device, comprising:a first electrode and a second electrode facing each other;
a light-absorption layer between the first electrode and the second electrode, the light-absorption layer including a first p-type light-absorption material and a first n-type light-absorption material, the first p-type light-absorption material and the first n-type light-absorption material forming a heterojunction, and
a light-absorption auxiliary layer on one side of the light-absorption layer, the light-absorption auxiliary layer including a second p-type light-absorption material or a second n-type light-absorption material, the light-absorption auxiliary layer having a smaller full width at half maximum (FWHM) than the light-absorption layer.

US Pat. No. 10,141,375

DISPLAY DEVICE HAVING A SOLAR CELL LAYER

LG Display Co., Ltd., Se...

1. A display device comprising:a first light-emitting area provided on a lower substrate;
a second light-emitting area provided on the lower substrate;
a third light-emitting area provided on the lower substrate;
a solar cell layer provided on an upper substrate facing the lower substrate, the solar cell layer producing power by absorbing light, the solar cell layer including first, second and third organic solar cell layers which are disposed in areas corresponding to the respective first, second and third light-emitting areas,
wherein the solar cell layer includes:
a first electrode provided on the upper substrate;
a hole transporting layer provided between the first electrode and each of the first, second and third organic solar cell lavers,
an electron transporting layer provided the first, second and third organic solar cell layers, and
a second electrode provided on the electron transporting layer and disposed in areas corresponding to the respective first, second and third organic solar cell layers.

US Pat. No. 10,141,374

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a plurality of first interconnects provided along a first direction, respectively;
a plurality of second interconnects provided along a second direction different from the first direction, respectively;
a plurality of third interconnects provided along a third direction different from the first and second directions, respectively;
a plurality of memory cells including variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects and coupled with the mutually different second interconnects; and
a plurality of selectors which couple the third interconnects with the first interconnects,
wherein one of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects,
a plurality of gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween, and
wherein in each of the selectors, gates provided on the side surfaces of the semiconductor layer are coupled with each other in common along a second direction, and
the gates are separated between the selectors.

US Pat. No. 10,141,373

MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A memory device, comprising;a plurality of first conductive patterns on a substrate, each of the plurality of first conductive patterns extending in a first direction;
a first selection pattern on each of the plurality of first conductive patterns;
a first barrier portion surrounding the first selection pattern;
a first electrode and a first variable resistance pattern on the first selection pattern; and
a plurality of second conductive patterns on the first variable resistance pattern, each of the plurality of second conductive patterns extending in a second direction crossing the first direction,
wherein the first selection pattern has a conductivity of an n type or a p type, and wherein the first barrier portion is a p type doped region adjacent to a sidewall of the first selection pattern.

US Pat. No. 10,141,372

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

8. A three-dimensional semiconductor device, comprising:a substrate including a cell array region, a dummy region, a contact region, and an overlapped region,
the contact region being adjacent to the cell array region in a first direction, the dummy region being adjacent to the cell array region in a second direction, the overlapped region being adjacent to the contact region in the second direction and adjacent to the dummy region in the first direction, the second direction being perpendicular to the first direction;
a first stack structure including a plurality of first electrodes vertically stacked on the substrate, the first stack structure extending along the first direction on the cell array region and the contact region; and
a second stack structure including a plurality of second electrodes vertically stacked on the substrate, the second stack structure spaced apart from the first stack structure in the second direction and provided on the dummy region and the overlapped region,
wherein the second stack structure has a first staircase structure extending in the first direction and a second staircase structure extending in the second direction,
the first staircase structure has a first slope with respect to the top surface of the substrate and the second staircase structure has a second slope with respect to the top surface of the substrate, and
the second slope is greater than the first slope.

US Pat. No. 10,141,371

WIDE BAND GAP DEVICE INTEGRATED CIRCUIT DEVICE

Qromis, Inc., Santa Clar...

1. A device comprising:a plurality of groups of gallium nitride (GaN) epitaxial layers, a combined thickness of the plurality of groups of GaN epitaxial layers greater than ten microns;
mesas etched within at least some groups of the plurality of groups of GaN epitaxial layers;
internal interconnects formed within the mesas;
electrodes formed on at least one of the internal interconnects or the GaN epitaxial layers, the electrodes configuring each group of GaN epitaxial layers of the plurality of groups of GaN epitaxial layers into a GaN device of a plurality of GaN devices; and
external interconnects formed over at least some of the electrodes for connecting the plurality of GaN devices into an integrated circuit.

US Pat. No. 10,141,370

OPTOELECTRONIC DEVICE AND METHOD FOR MANUFACTURING SAME

1. An optoelectronic device comprising:a plurality of light-emitting diodes comprising semiconductor elements; and
current-limiting components, each said component being series-connected with a corresponding one of the plurality of semiconductor elements and having a resistance which increases along with current intensity flowing through the corresponding series-connected current-limiting component and semiconductor element.

US Pat. No. 10,141,369

PHOTO-DETECTOR

DB HITEK CO., LTD., Seou...

1. A photo-detector comprising:a substrate having a light-receiving region;
a first field generating region disposed on one side of the light-receiving region;
a second field generating region disposed on another side of the light-receiving region;
a detection region disposed adjacent to the first field generating region to collect minority carriers generated in the light-receiving region;
a controller for applying first and second voltages to the first and second field generating regions, respectively, to generate a majority carrier current for moving the minority carriers towards the detection region;
a first field contact region disposed on the first field generating region;
a second field contact region disposed on the second field generating region;
isolation regions disposed on side surfaces of the first and second field contact regions and the detection contact region;
a guard region spaced apart from the detection region and connected to a ground potential; and
a blocking region disposed between the detection region and the guard region to block a leakage current between the detection region and the guard region.

US Pat. No. 10,141,368

SEMICONDUCTOR DEVICE

HAMAMATSU PHOTONICS K.K.,...

1. A semiconductor device comprising: a semiconductor substrate that has a first surface and a second surface opposite to each other and in which a through hole to extend from the first surface to the second surface is formed;a first wiring that is provided on the first surface and has a portion located above a first opening of the through hole on the a first surface side;
an insulating layer that is provided on an inner surface of the through hole and the second surface and is continuous through a second opening of the through hole on the a second surface side; and
a second wiring that is provided on a surface of the insulating layer and is electrically connected to the first wiring in an opening of the insulating layer on the first surface side, wherein the through hole is a vertical hole, and on both sides of a center line of the through hole in a plane including the center line of the through hole, a segment that connects a first point corresponding to an edge of the opening of the insulating layer and a second point corresponding to an edge of the second opening is a first segment, a segment that connects the second point and a third point corresponding to an intersection point between the second opening and the surface of the insulating layer is a second segment, and a segment that connects the third point and the first point is a third segment, a first area of the insulating layer that is located on an inner surface side of the through hole with respect to the first segment is larger than the sum of a second area of the insulating layer that is surrounded by the first segment, the second segment, and the third segment and a third area of the insulating layer that is located on a side opposite the inner surface side of the through hole with respect to the third segment.

US Pat. No. 10,141,367

PHOTOELECTRIC CONVERSION APPARATUS AND PHOTOELECTRIC CONVERSION SYSTEM

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion apparatus comprising:a plurality of pixels, each pixel including
a pixel electrode having a first electrode and a second electrode on an upper part of a substrate,
an upper electrode arranged on an upper part of the pixel electrode,
a photoelectric conversion layer arranged between the pixel electrode and the upper electrode,
a first signal output circuit including a first amplification unit having an input node directly connected to the first electrode, and
a second signal output circuit including a second amplification unit having an input node directly connected to the second electrode; and
a control unit configured to supply an electric potential to the second electrode that a potential of the second electrode with respect to signal charges decreases as compared with a potential of the first electrode with respect to signal charges in an electric potential supplied to the first electrode during a first period in which the first signal output circuit outputs a signal.

US Pat. No. 10,141,366

STACKED SEMICONDUCTOR CHIP RGBZ SENSOR

Google Inc., Mountain Vi...

1. A method comprising:forming a backside illumination pixel array including (i) pixels of a first type, and, (ii) for each pixel, a light guide structure between the pixel and a front side surface of the backside illumination pixel array;
forming a front side illumination pixel array including (i) pixels of a second type, and, (ii) for each pixel, a light guide structure between the pixel and a front side surface of the front side pixel array; and
stacking the backside illumination pixel array on the front side illumination pixel array.

US Pat. No. 10,141,365

SOLID-STATE IMAGING DEVICE HAVING IMPROVED LIGHT-COLLECTION, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device, comprising:a substrate having a first side as a light-incident side and a second side opposite to the first side;
a first photoelectric conversion region disposed in the substrate;
a second photoelectric conversion region disposed adjacent to the first photoelectric conversion region in the substrate;
a third photoelectric conversion region disposed adjacent to the second photoelectric conversion region in the substrate;
a silicon oxide film disposed over the first side of the substrate;
a hafnium oxide film disposed over the silicon oxide film;
a first light-shielding film disposed over the hafnium oxide film, the first light-shielding film disposed between the first photoelectric conversion region and the second photoelectric conversion region;
a second light-shielding film disposed over the hafnium oxide film, the second light-shielding film disposed between the second photoelectric conversion region and the third photoelectric conversion region;
a titanium nitride film disposed between the hafnium oxide film and the first light-shielding film;
a trench including a first trench portion and a second trench portion;
a plurality of photoelectric conversion portions, wherein a photoelectric conversion portion of the plurality of photoelectric conversion portions is disposed between the first trench portion and the second trench portion; and
a metallic oxide film including a first portion, a second portion and a third portion,
wherein,
the first portion is disposed in the first trench portion,
the second portion is disposed in the second trench portion, and
the third portion is overlapping with the photoelectric conversion portion.

US Pat. No. 10,141,364

IMAGING DEVICE INCLUDING UNIT PIXEL CELL

Panasonic Intellectual Pr...

1. An imaging device comprising:a unit pixel cell comprising:
a photoelectric converter that generates an electric signal through photoelectric conversion of incident light; and
a signal detection circuit that detects the electric signal, the signal detection circuit comprising:
a first transistor that amplifies the electric signal,
a second transistor that selectively transmits an output of the first transistor to outside of the unit pixel cell, and
a feedback circuit that forms a feedback loop through which the electric signal is negatively fed back, the feedback loop passing through the first transistor, the feedback circuit comprising a third transistor provided on the feedback loop, a gate of the third transistor being connected to a voltage control circuit that outputs at least three voltages different from each other, wherein
the feedback circuit comprises a first capacitor and a second capacitor connected in a series to the first capacitor,
the photoelectric converter is connected to a first reference voltage via the first capacitor and the second capacitor,
one end of the first capacitor is connected to the photoelectric converter without passing through any one of the first to third transistors,
the other end of the first capacitor is connected to one end of the second capacitor,
the other end of the second capacitor is connected to the first reference voltage without passing through any one of the first to third transistors, and
the first capacitor has a first capacitance value, and the second capacitor has a second capacitance value larger than the first capacitance value.

US Pat. No. 10,141,363

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device that has a solid-state imaging element of a back side illumination type, comprising the steps of:(a) providing a semiconductor substrate that comprises a main surface and a back surface on the opposite side of the main surface;
(b) forming an element separation region at a part of the main surface of a second region that surrounds a first region of the semiconductor substrate in plan view;
(c) forming an insulation film that covers the main surface of the semiconductor substrate exposed from the element separation region in the second region;
(d) after the step (c), forming a silicide layer that is in contact with the main surface of the semiconductor substrate of the first region;
(e) after the step (d), forming a wiring layer over the main surface of the semiconductor substrate and joining a support substrate above the wiring layer;
(f) after the step (e), exposing the insulation film by removing the semiconductor substrate of the second region; and
(g) after the step (f), cutting the wiring layer and the support substrate of the second region, and thereby obtaining the solid-state imaging element that includes the semiconductor substrate of the first region.

US Pat. No. 10,141,362

SEMICONDUCTOR DEVICE HAVING PROTECTION LAYER WRAPPING AROUND CONDUCTIVE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising: an image sensor device layer; a first bonding layer over the image sensor device layer; a second bonding layer bonded with the first bonding layer; a substrate over the second bonding layer; and a conductive via passing through the substrate, the second bonding layer, and the first bonding layer, wherein the conductive via comprises: a protection layer peripherally enclosed by the substrate, the second bonding layer, and the first bonding layer, wherein the protection layer covers a sidewall cut formed at an interface between the second bonding layer and the first bonding layer; and a conductive material peripherally enclosed by the protection layer, wherein the protection layer has a protrusion protruding from an outer sidewall of the protection layer and in contact with the first bonding layer and the second bonding layer.

US Pat. No. 10,141,361

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An image sensor comprising:a first semiconductor section including a first semiconductor substrate and a first multi-wiring layer, the first semiconductor substrate including a photodiode, and the first multi-wiring layer including a first insulating interlayer and first and second wirings; and
a second semiconductor section including a second semiconductor substrate and a second multi-wiring layer, the second semiconductor section including at least a part of a signal processing circuit, and the second multi-wiring layer including a second insulating interlayer and third and fourth wirings,
wherein,
the first semiconductor section and the second semiconductor section are bonded together such that the first multi-wiring layer and the second multi-wiring layer face each other,
the first wiring of the first multi-wiring layer directly contacts the third wiring of the second multi-wiring layer in a pixel region including the photodiode, and
the second wiring of the first multi-wiring layer directly contacts the fourth wiring of the second multi-wiring layer in a peripheral region other than the pixel region.

US Pat. No. 10,141,360

ISOLATED GLOBAL SHUTTER PIXEL STORAGE STRUCTURE

OmniVision Technologies, ...

1. An imaging system, comprising:a pixel array of pixel cells, wherein each one of the pixel cells includes:
a photodiode disposed in a semiconductor material to accumulate image charge in response to incident light directed to the photodiode;
a global shutter gate transistor, wherein a portion of the global shutter gate transistor is disposed in the semiconductor material and coupled to the photodiode to selectively deplete the image charge from the photodiode;
a storage transistor, wherein a portion of the storage transistor is disposed in the semiconductor material to store the image charge; and
an optical isolation structure disposed in the semiconductor material proximate to the storage transistor to isolate a sidewall of the storage transistor from stray light and stray charge in the semiconductor material outside of the storage transistor, wherein the optical isolation structure includes a deep trench isolation structure formed in the semiconductor material, wherein the deep trench isolation structure is filled with tungsten, wherein the optical isolation structure further includes a P+ passivation formed over an interior sidewall of the deep trench optical isolation structure between the tungsten and the semiconductor material;
control circuitry coupled to the pixel array to control operation of the pixel array; and
readout circuitry coupled to the pixel array to readout image data from the plurality of pixels.

US Pat. No. 10,141,359

IMAGE SENSOR

HIMAX TECHNOLOGIES LIMITE...

1. An image sensor, comprising:an infrared receiving portion configured to receive infrared, and
a visible light receiving portion configured to receive a visible light, wherein the visible light receiving portion comprises an infrared cutoff filter grid and a color filter;
wherein the infrared cutoff filter grid has a grid structure;
wherein the infrared cutoff filter grid is configured to block the transmission of the infrared laterally passing the color filter;
wherein when viewed in cross section, the infrared cutoff filter grid comprises a base portion having an upper surface, and a plurality of pillar portions extending upwardly from the upper surface of the base portion, each adjacent pair of the pillar portions forming a space therebetween to thereby form a plurality of spaces;
wherein the color filter comprises a red color filter unit, a blue color filter unit, and a green color filter unit, and each of the red color filter unit, the blue color filter unit, and the green color filter unit is filled in one of the spaces;
wherein the visible light receiving portion further comprises a visible light photodiode and an infrared cutoff filter disposed on the visible light photodiode;
wherein the infrared cutoff filter and infrared cutoff filter grid are formed in one-piece.

US Pat. No. 10,141,358

SEMICONDUCTOR SWITCHING DEVICE SEPARATED BY DEVICE ISOLATION

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus comprising:a device isolation structure disposed within a substrate;
a photo-sensitive device isolated by the device isolation structure;
a first gate structure disposed over the substrate and having a first portion disposed over the device isolation structure; and
a second gate structure disposed over the substrate and over the device isolation structure;
a first source/drain feature disposed within the substrate and at least partially enclosed by the device isolation structure and the first gate structure, and
wherein a thickness of the first portion of the first gate structure is such that electric current flowing through the first source/drain feature is prevented from flowing into the photo-sensitive device.

US Pat. No. 10,141,357

PHOTOSENSOR SUBSTRATE

SHARP KABUSHIKI KAISHA, ...

1. A photosensor substrate comprising:a substrate;
a plurality of photoelectric transducers disposed on the substrate; and
transistors connected to the photoelectric transducers, respectively; wherein
the transistors each include
a semiconductor layer supported by the substrate,
a drain electrode and a source electrode facing each other in a direction parallel to a plane of the substrate, with the semiconductor layer interposed therebetween,
a gate insulating film covering the semiconductor layer, the drain electrode, and the source electrode, and
a gate electrode facing the semiconductor layer with the gate insulating film interposed therebetween, and
the photoelectric transducers each include
a lower electrode connected to the drain electrode or the source electrode via a contact hole provided in the gate insulating film,
a semiconductor film in contact with the lower electrode, and
an upper electrode facing the lower electrode with the semiconductor film interposed therebetween,
wherein the gate electrode of the transistor and the lower electrode of the photoelectric transducer are disposed at an identical layer level and made of an identical material.

US Pat. No. 10,141,356

IMAGE SENSOR PIXELS HAVING DUAL GATE CHARGE TRANSFERRING TRANSISTORS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor pixel, comprising:a photodiode that generates charge in response to image light;
a floating diffusion node; and
a charge transferring transistor having a first gate and a second gate, wherein the first gate and the second gate are controlled by respective first and second control lines, wherein the charge transferring transistor is configured to transfer the generated charge from the photodiode to the floating diffusion node, wherein the second control line is configured to modulate a bias applied to the second gate between at least three different voltages, wherein the at least three different voltages include a reset voltage, a transfer voltage, and an intermediate voltage, and wherein the intermediate voltage is dynamically adjusted while the generated charge is transferred from the photodiode to the floating diffusion node to change a conversion gain of the image sensor pixel.

US Pat. No. 10,141,355

SOLID-STATE IMAGING DEVICE, PRODUCTION METHOD OF THE SAME, AND IMAGING APPARATUS

Sony Corporation, Tokyo ...

1. An imaging apparatus, comprising:an imaging optical unit;
a solid-state imaging device;
a signal processing unit;
a storage unit;
a display device;
an operation unit; and
a power source unit,
wherein the solid-state imaging device comprises,
a semiconductor substrate having a first side and a second side, opposite the first side, as a light incident side;
a plurality of transistors disposed at the first side of the semiconductor substrate;
a plurality of photoelectric conversion regions disposed in the semiconductor substrate, the plurality of photoelectric conversion regions including a first photoelectric conversion region and a second photoelectric conversion region adjacent to the first photoelectric conversion region;wherein:the first and second photoelectric conversion regions are each selectively coupled to a first amplification transistor from the plurality of transistors;
each of the first and second photoelectric conversion regions comprises a respective impurity region;
the plurality of transistors further comprises a first transfer transistor and a second transfer transistor coupled to the first photoelectric conversion region and the second photoelectric conversion region, respectively;
the first transfer transistor and the second transfer transistor are each coupled to a first floating diffusion;
the first floating diffusion is coupled to the first amplification transistor; and
the impurity regions of the first and second photoelectric conversion regions are greater than or equal to one micrometer thick and less than or equal to five micrometers thick in a depth direction between the first and second sides of the semiconductor substrate.

US Pat. No. 10,141,354

IMAGING DEVICE AND IMAGE ACQUISITION DEVICE

Panasonic Intellectual Pr...

1. An imaging device, comprising:unit pixel cells; and
a voltage application circuit that generates at least two different voltages,
each of the unit pixel cells comprising:
a photoelectric conversion layer having a first surface and a second surface being on a side opposite to the first surface,
a pixel electrode located on the first surface,
an auxiliary electrode located on the first surface, the auxiliary electrode being spaced from the pixel electrode and electrically connected to the voltage application circuit,
an upper electrode located on the second surface, the upper electrode opposing to the pixel electrode and the auxiliary electrode,
a charge storage node electrically connected to the pixel electrode, and
a charge detection circuit electrically connected to the charge storage node, wherein
the unit pixel cells include a first unit pixel cell and a second unit pixel cell adjacent to the first unit pixel cell,
the auxiliary electrode of the first unit pixel cell is located between the pixel electrode of the first unit pixel cell and the pixel electrode of the second unit pixel cell,
the voltage application circuit generates a first voltage and a second voltage higher than the first voltage,
the voltage application circuit selectively applies either one of the first voltage and the second voltage to the auxiliary electrode, and
the charge detection circuit comprises a reset transistor that sets the pixel electrode at a reset voltage at predetermined timing, the reset voltage being higher than the first voltage and lower than the second voltage.

US Pat. No. 10,141,353

PASSIVE COMPONENTS IMPLEMENTED ON A PLURALITY OF STACKED INSULATORS

QUALCOMM Incorporated, S...

1. An integrated circuit apparatus, comprising:a first insulator, the first insulator being substantially planar and having a first top surface and a first bottom surface opposite the first top surface;
a first conductor disposed on the first insulator;
a second insulator, the second insulator being substantially planar and having a second top surface and a second bottom surface opposite the second top surface;
a second conductor disposed on the second insulator; and
a dielectric layer disposed between the first conductor of the first insulator and the second conductor of the second insulator;
wherein:
a capacitor is formed by the first conductor disposed on the first insulator, the dielectric layer, and the second conductor disposed on the second insulator; and
an inductor is formed on the first insulator and the second insulator.

US Pat. No. 10,141,352

MANUFACTURING METHOD OF ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of an array substrate, comprising:sequentially depositing a first electrode layer and a gate metal layer on a base substrate, the first electrode layer including at least two conductive layers, formation materials of the at least two conductive layers having different etching rates;
forming a photoresist layer on the gate metal layer;
exposing and developing the photoresist layer using a halftone mask plate;
performing a first etching process on the gate metal layer;
etching the first electrode layer;
ashing the developed photoresist layer; and
performing a second etching process only on the gate metal layer by using remaining photoresist layer as a mask, and stripping the remaining photoresist layer.

US Pat. No. 10,141,350

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a substrate; and
a plurality of data lines and a plurality of gate lines disposed on the substrate, the data lines and the gate lines being configured to define a plurality of pixel units,
wherein each pixel units comprises:
a pixel electrode;
a thin film transistor electrically connected to the data line and the gate line and configured to drive the pixel electrode; and
a resin layer disposed on the data line and/or the gate line and provided with at least one gas discharging structure each having an opening facing away from the substrate.

US Pat. No. 10,141,349

THIN-FILM TRANSISTOR ARRAY, FABRICATION METHOD THEREFOR, IMAGE DISPLAY DEVICE AND DISPLAY METHOD

TOPPAN PRINTING CO., LTD....

1. A thin-film transistor array, comprising:a plurality of thin-film transistors each having a configuration in which a gate electrode, a gate wiring connected to the gate electrode, capacitor electrode, and a capacitor wiring connected to the capacitor electrode are provided on an insulating substrate, with a source electrode and a drain electrode having a gap therebetween and including a semiconductor pattern being formed, in a region overlapping with the gate electrode via a gate insulator film, the semiconductor pattern being covered with a protective layer, two thin-film transistors of the plurality of thin-film transistors being independently formed for each pixel, two source electrodes in each pixel being separately connected to two respective source wirings, two drain electrodes each being directly connected to an electrode of the pixel via respective drain-connecting electrodes,
wherein the thin-film transistor array includes source-connecting electrodes each connecting between the source electrodes of the two thin-film transistors formed for each pixel,
wherein the protective layer is in a stripe pattern and formed along the gate wirings such that the protective layer covers the semiconductor patterns and the source wirings,
wherein the protective layer does not cover a portion of the source-connecting electrodes, and
wherein the thin-film transistor array includes an insulating film that covers the source wirings and the portion of the source-connecting electrodes not covered by the protective layer.

US Pat. No. 10,141,348

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a first base;
a first thin-film transistor (TFT) and a second TFT which are disposed on the first base to be adjacent to each other along a first direction;
an organic layer which covers the first TFT and the second TFT and comprises a first opening overlapping a first drain electrode of the first TFT and a second opening overlapping a second drain electrode of the second TFT;
a common electrode which is located on the organic layer and comprises a first common electrode opening overlapping the first opening and a second common electrode opening overlapping the second opening;
a bump spacer which is located on the common electrode;
an insulating layer which is located on the common electrode and the bump spacer;
a first pixel electrode which is disposed on the insulating layer to overlap the common electrode and is electrically connected to the first TFT; and
a second pixel electrode which is disposed on the insulating layer to overlap the common electrode and is electrically connected to the second TFT,
wherein a minimum distance between the bump spacer and the first common electrode opening is equal to a minimum distance between the bump spacer and the second common electrode opening in a plan view,
wherein the bump spacer and the insulating layer are formed of different materials.

US Pat. No. 10,141,347

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising:a plurality of gate lines;
a plurality of first data lines, parallel to a short side of the array substrate;
a plurality of second data lines, parallel to a long side of the array substrate;
a first integrated circuit, arranged in a short-side frame;
wherein the plurality of the second data lines are configured for connecting the first integrated circuit with the plurality of the first data lines; the first integrated circuit transmits data signal to the plurality of first data lines through the plurality of second data lines;
wherein an amount of the plurality of gate lines is same as an amount of the plurality of second data lines and both of them are m, and an amount of the plurality of first data lines is n;
wherein m>n, n second data lines of the m second data lines are connected to the n first data lines in one-to-one correspondence, and remaining second data lines are suspended.

US Pat. No. 10,141,346

THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF AND LIQUID CRYSTAL DISPLAY

Shenzhen China Star Optoe...

1. A thin-film transistor, comprising:a substrate;
a gate electrode formed on the surface of the substrate;
a gate insulting layer covered on the gate electrode;
a semiconductor layer disposed on the surface of the gate insulating layer away from the gate electrode and corresponding to the gate electrode;
an etching stop layer covered the semiconductor layer, and the etching stop layer having a first through hole and a second through hole, wherein the first through hole and the second through hole are set corresponding to the semiconductor layer to expose partial of the semiconductor layer, and the first through hole and the second through hole are set in intervals;
a passivation layer covered the etching stop layer, the passivation layer having a third through hole and a fourth through hole wherein the third through hole is corresponding to the first through hole and is in communication with the first through hole; the fourth through hole is corresponding to the second through hole and is in communication with the second through hole;
a source electrode disposed on the passivation layer and connected to one terminal of the semiconductor layer via the first through hole and the third through hole; and
a drain electrode disposed on the passivation layer and in intervals with the source electrode and connected to the other terminal of the semiconductor layer via the second through hole and the fourth through hole;
wherein a data line is formed between the etching stop layer and the passivation layer;
the passivation layer further comprises a fifth through hole formed therein and corresponding to the data line to expose a part of the data line; and
the part of the data line is electrically connected to the source electrode via the fifth through hole.

US Pat. No. 10,141,345

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:common electrodes;
pixel electrodes overlapped with the common electrodes in a direction perpendicular to the array substrate;
common electrode lines;
at least one auxiliary common electrode line formed in a same layer as the pixel electrodes;
a passivation layer and an insulation layer provided between the common electrode lines and the at least one auxiliary common electrode line; and
data lines provided between the insulation layer and the passivation layer,
wherein the at least one auxiliary common electrode line is arranged to intersect with the common electrode lines and be electrically connected to the common electrode lines through via holes formed in the insulation layer and the passivation layer, and
wherein the at least one auxiliary common electrode line is disposed overlapped with the data lines in the direction perpendicular to the array substrate, the at least one auxiliary common electrode line is arranged parallel to the data lines, and the insulation layer is provided between the at least one auxiliary common electrode line and the data lines.

US Pat. No. 10,141,343

OXIDE SEMICONDUCTOR, THIN FILM TRANSISTOR, AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductive layer;
a second conductive layer;
a first insulating layer over the first conductive layer and the second conductive layer;
an oxide semiconductor layer over the first insulating layer;
a third conductive layer electrically connected to the oxide semiconductor layer;
a fourth conductive layer electrically connected to the oxide semiconductor layer; and
a fifth conductive layer over the first insulating layer,
wherein the first conductive layer includes a region functioning as a gate electrode of a transistor,
wherein the second conductive layer includes a region functioning as a first electrode of a capacitor,
wherein the oxide semiconductor layer includes a region functioning as a channel formation region of the transistor,
wherein the third conductive layer includes a region functioning as one of a source electrode and a drain electrode of the transistor,
wherein the fourth conductive layer includes a region functioning as the other one of the source electrode and the drain electrode of the transistor,
wherein the fourth conductive layer is electrically connected to the second conductive layer,
wherein the fifth conductive layer includes a region functioning as a second electrode of the capacitor,
wherein the oxide semiconductor layer includes In, Ga, and Zn, and
wherein a concentration of Zn is lower than a concentration of In or a concentration of Ga.

US Pat. No. 10,141,342

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first circuit comprising an integrator circuit comprising an operational amplifier;
a second circuit;
a first transistor; and
a second transistor,
wherein one of a source and a drain of the first transistor is directly connected to an inverting input terminal of the operational amplifier,
wherein one of a source and a drain of the second transistor is directly connected to the inverting input terminal of the operational amplifier,
wherein a first analog signal is input to an input terminal of the integrator circuit via the first transistor,
wherein a second analog signal is input to the input terminal of the integrator circuit via the second transistor,
wherein the integrator circuit is configured to change capacitance between the inverting input terminal of the operational amplifier and an output terminal of the operational amplifier,
wherein the first circuit is configured to convert the first analog signal into a first digital signal,
wherein the second circuit is configured to generate a second digital signal based on the first digital signal,
wherein the first circuit is configured to convert the second analog signal into a third digital signal based on the second digital signal, and
wherein at least one of the first transistor and the second transistor comprises an oxide semiconductor in a channel formation region.

US Pat. No. 10,141,341

THIN-FILM-TRANSISTOR (TFT) ARRAY PANEL WITH STRESS ELIMINATION LAYER AND METHOD OF MANUFACTURING THE SAME

Shenzhen China Star Optoe...

1. A method for manufacturing a TFT array panel, the TFT array panel comprising:a flexible baseplate;
a buffer layer, disposed on the flexible baseplate, on which a stress-elimination portion for eliminating a stress of the flexible baseplate is disposed;
a display-element layer, disposed on the buffer layer;
wherein the method comprises steps:
A. disposing the buffer layer on the flexible baseplate;
B. disposing the stress-elimination portion on the buffer layer, wherein the stress-elimination portion is used to eliminate a stress of the flexible baseplate;
C. disposing the display-element layer on the buffer layer;
wherein the step B comprises:
b1. Performing a photo-mask process and/or an etching process on the buffer layer, to form the stress-elimination portion;
the stress-elimination portion is disposed on a plane of the buffer layer, and the plane is positioned closer to the display-element layer than a position of one other plane of the buffer layer;
wherein the stress-elimination portion comprises at least one recess and at least one protrusion portion, wherein the at least one recess and the at least one protrusion portion are lined up as a one dimensional array or a two dimensional array.

US Pat. No. 10,141,340

THIN-FILM-TRANSISTOR, THIN-FILM-TRANSISTOR ARRAY SUBSTRATE, FABRICATING METHODS THEREOF, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a thin-film-transistor (TFT), the method comprising:forming an initial conductive layer on a base substrate;
forming an oxidation preventing layer on a portion of the initial conductive layer to be removed;
performing an oxidization process to partially oxidize the initial conductive layer to form an oxidized insulating sub-layer and a non-oxidized conductive sub-layer, a portion of the non-oxidized conductive sub-layer being exposed through the oxidized insulating sub-layer;
removing the oxidation preventing layer after forming the oxidized insulating sub-layer;
removing, after the oxidation preventing layer is removed, the portion of the initial conductive layer to be removed to expose a portion of the base substrate; and
forming an active layer, a source electrode and a drain electrode over a portion of the oxidized insulating sub-layer that is separated by the exposed portion of the base substrate from the portion of the non-oxidized conductive sub-layer exposed through the oxidized insulating sub-layer.