US Pat. No. 11,114,599

ELECTRONIC DEVICES INCLUDING SOLID SEMICONDUCTOR DIES

3M INNOVATIVE PROPERTIES ...


1. A method comprising:providing an array of solid semiconductor dies each extending between a first end and an opposite, second end thereof;
sinking the first ends of the dies into a major surface of a first liner;
filling a flowable polymeric material onto the major surface of the first liner;
solidifying the polymeric material to form a layer of polymeric matrix material, wherein the array of solid semiconductor dies is at least partially embedded in the layer of polymeric matrix material;
delaminating the first liner from the first ends of the dies; and
electrically connecting the first ends of the dies,
wherein solidifying the polymeric material comprises thermal or radiation curing, and
wherein the polymeric material is cured from the side of the first ends, and an uncured material at the second ends is removed after curing.

US Pat. No. 11,114,598

LAMP USING SEMICONDUCTOR LIGHT-EMITTING ELEMENTS

LG ELECTRONICS INC., Seo...


1. A lamp, comprising:a wiring substrate;
a bus electrode provided on the wiring substrate;
a plurality of electrode lines provided on the wiring substrate, and extending from the bus electrode, each electrode line having one end and a central portion located between the one end and the bus electrode;
a plurality of semiconductor light-emitting elements aligned along an extending direction of the plurality of electrode lines, and disposed to be spaced apart from adjacent electrode lines of the plurality of electrode lines by varying distances, respectively; and
a plurality of transparent electrodes that respectively provide an electrical connection between the plurality of electrode lines and the plurality of semiconductor light-emitting elements,
wherein the respective varying distances between the plurality of semiconductor light-emitting elements and each of the adjacent electrode lines decrease toward the central portion of the each electrode line.

US Pat. No. 11,114,597

DISPLAY DEVICE HAVING AN ELECTRONIC DEVICE DISPOSED ON A FIRST PAD AND A SECOND PAD

INNOLUX CORPORATION, Mia...


1. A display device, comprising:a substrate;
a first metal line and a second metal line disposed on the substrate;
a first pad and a second pad disposed on the substrate and electrically connected to the first metal line and the second metal line respectively; and
an electronic device disposed on the first pad and the second pad, and the electronic device comprising a first connecting post and a second connecting post;
wherein a portion of the first connecting post is embedded in the first pad and a portion of the second connecting post is embedded in the second pad, and a topmost height of the first pad from the substrate is higher than a topmost height of the first metal line from the substrate along a normal direction of the substrate;
wherein the first connecting post does not overlap the first metal line in the normal direction of the substrate, wherein the first pad overlaps only one edge of the first metal line in a cross-sectional view, and the second pad overlaps only one edge of the second metal line in the cross-sectional view.

US Pat. No. 11,114,596

LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...


1. A light emitting device comprising:a light-emitting element having a first surface and a second surface opposite each other, the light-emitting element comprising a pair of external connecting electrodes on the first surface, each of the external connecting electrodes comprising an electrode formed on the first surface and a metal layer formed on the electrode,
a wavelength conversion member covering the second surface of the light-emitting element, and
a coating member covering the first surface except for the external connecting electrodes,
wherein the coating member comprises a light reflective material and resin, and
wherein a laser irradiation mark is formed on a surface of the coating member.

US Pat. No. 11,114,595

OPTICAL COMPONENT AND TRANSPARENT BODY

NGK Insulators, Ltd., Na...


1. An optical component including:at least one optical element configured to emit ultraviolet light; and
a package in which the optical element is housed, the package including:
a mounting substrate on which the optical element is mounted; and
a transparent body that is joined onto the mounting substrate via an organic-based adhesive layer, the transparent body defining a lens body including a raised pedestal provided on the adhesive layer, and the package having a structure in which the ultraviolet light is not guided to the adhesive layer through the transparent body, and the ultraviolet light does not directly strike the adhesive layer,
wherein an angle ? defined between an upper surface of the pedestal and a lower section of the lens body is greater than or equal to 80 degrees and less than 90 degrees.

US Pat. No. 11,114,594

LIGHT EMITTING DEVICE PACKAGES USING LIGHT SCATTERING PARTICLES OF DIFFERENT SIZE

CreeLED, Inc., Durham, N...


1. An emitting device, comprising:multiple emitters spaced apart on a common flat surface, wherein each of said multiple emitters emit a spectrum of radiation and at least two of said emitters emit spectrums having different wavelength ranges;
an encapsulant over said multiple emitters and on said common flat surface, each of said emitters disposed off-center on said common flat surface with respect to said encapsulant;
a first plurality of scattering particles comprising a diameter greater than 1 micrometer at least partially surrounding at least one emitter of said multiple emitters, wherein said first plurality of scattering particles scatters light at wavelengths within a first sub-spectrum of said spectrums; and
a second plurality of scattering particles comprising a diameter less than 1 micrometer at least partially surrounding at least one emitter of said multiple emitters, wherein said second plurality of scattering particles scatters light at wavelengths within a second sub-spectrum of said spectrums;
wherein said first plurality of scattering particles interacts with said wavelengths within said first sub-spectrum more than said wavelengths within said second sub-spectrum, and said second plurality of scattering particles interacts with said wavelengths within said second sub-spectrum more than said wavelengths within said first sub-spectrum;
wherein said first and second pluralities of scattering particles are mixed together in and are dispersed throughout a common medium and said first and second pluralities of scattering particles contain indices of refraction different than the index of refraction of said common medium;
wherein radiation emitted from said multiple emitters interacts with said first and second pluralities of scattering particles, such that said diameters of said first and second pluralities of scattering particles and the index of refraction differential between said common medium and said first and second pluralities of scattering particles create a substantially forward or sideways scattering effect over said first sub-spectrum and said second sub-spectrum.

US Pat. No. 11,114,593

OPTOELECTRONIC MODULES AND OPTOELECTRONIC MOLDING TOOLS AND PROCESSES FOR MANUFACTURING THE SAME

ams Sensors Singapore Pte...


1. A method for manufacturing a plurality of discrete optoelectronic modules from a wafer assembly, the method comprising:adding a substrate wafer to the wafer assembly, the substrate wafer including a plurality of optoelectronic components mounted to a first side of the substrate wafer;
coating the first side of the substrate wafer and the plurality of optoelectronic components with a photosensitive material, the plurality of optoelectronic components being sensitive to and/or operable to emit electromagnetic radiation of a particular wavelength;
exposing a first side of the photosensitive material to electromagnetic radiation such that a plurality of defining portions is formed within the photosensitive material, each defining portion at least partially delineating dimensions of at least one optical channel associated with at least one of the optoelectronic components;
developing the photosensitive material such that the photosensitive material that is not the plurality of defining portions is removed from the wafer assembly;
mounting a back-fill wafer to the plurality of defining portions, the backfill wafer including a plurality of channels and defining, at least partially, a plurality of cavities adjacent to the plurality of defining portions;
introducing a formable material into the back-fill wafer via the plurality of channels such that the formable material at least partially fills the plurality of cavities;
curing the formable material such that the formable material within the plurality of cavities is substantially solid; and
dicing the wafer assembly into the plurality of discrete optoelectronic modules.

US Pat. No. 11,114,592

LIGHT EMITTING DIODE


1. A microelectronic device, comprising:at least one of a light emitting diode with a p-n junction operable to emit radiation when coupled with a power source;
a plurality of optically transmissive enclosures; and
at least one outer optically-transmissive enclosure the boundaries of which contain an inner space within which is a plurality of innermost, second optically-transmissive enclosure, the wall of which form the boundaries of an interior space in each second enclosure;
wherein said interior space has within each at least one said light-emitting diode; and
wherein a heat exchanger is disposed adjacent to the wall of the second optically-transmissive enclosure.

US Pat. No. 11,114,590

WAVELENGTH CONVERSION MODULE, METHOD OF FORMING THE SAME AND PROJECTION APPARATUS

Coretronic Corporation, ...


1. A wavelength conversion module, comprising:a substrate, having a rough surface comprising two first regions and a second region, wherein the second region is located between the two first regions in a radial direction on the substrate; and
a wavelength conversion layer, located on the substrate and comprising a wavelength conversion material, a bonding material and a plurality of diffuse reflection particles,
wherein the wavelength conversion material is distributed in the bonding material, the plurality of diffuse reflection particles are located on the rough surface of the substrate, and the plurality of diffuse reflection particles are located between the wavelength conversion material and the substrate, and
wherein a second density of the plurality of diffuse reflection particles in the second region is greater than a first density of the plurality of diffuse reflection particles in one of the two first regions.

US Pat. No. 11,114,589

FLUORIDE PHOSPHOR AND LIGHT-EMITTING DEVICE USING SAME

Denka Company Limited, T...


1. A fluoride phosphor having a composition represented by a following general formula (1) and a repose angle of 30° or more and 60° or less:A2M(1-n)F6:Mn4+n??formula (1)
wherein 0 wherein a bulk density of the fluoride phosphor is 1.00 g/cm3 or more and 1.40 g/cm3 or less, and
wherein a mass median diameter (D50) of the fluoride phosphor is 29 ?m or less.

US Pat. No. 11,114,588

SEMICONDUCTOR LIGHT EMITTING ELEMENT

Ushio Denki Kabushiki Kai...


1. A semiconductor light emitting element comprising an n-type or p-type first semiconductor layer on a substrate, an active layer on the upper side of the first semiconductor layer, and a second semiconductor layer on the upper side of the active layer having a conductivity type different from the conductivity type of the first semiconductor layer, the semiconductor light emitting element comprising:a first insulating layer formed in a position closer to the substrate than the first semiconductor layer in a first direction orthogonal to a surface of the substrate and formed so as to protrude outward from a first surface of the first semiconductor layer, the first surface of the first semiconductor layer facing the substrate in the first direction;
a bonding layer including a solder material formed on the upper side of the substrate;
a first electrode made of a high reflective material located inside the first insulating layer as seen in the first direction and formed so as to be in contact with the first surface directly or via a thin film; and
a second electrode formed so as to be in contact with a surface of the second semiconductor layer opposite to a side of the second semiconductor layer that faces the substrate, wherein
a first region, where the first surface and the first insulating layer face each other, and a second region, where the first surface and the first electrode face each other, are spaced apart in a second direction parallel to the surface of the substrate,
a first conductive layer in contact with the first surface in a third region is interposed between the first region and the second region in the second direction, the first conductive layer being formed of a material having higher contact resistance to the first surface as compared to the first electrode, and the first conductive layer being formed to connect a surface of the first electrode that faces the substrate, a side surface of the first electrode, and the third region to one another,
a second conductive layer formed of a material different from the material of the first conductive layer, and formed so as to be in contact with a surface of the bonding layer opposite to a surface of the bonding layer that faces the substrate, a surface of the first conductive layer that faces the substrate, and a surface of the first insulating layer that faces the substrate, and
a second insulating layer is formed so as to be spaced apart from the first insulating layer in the second direction, the second insulating layer in contact with another surface of the first conductive layer facing the substrate, the second insulating layer in a position facing the second electrode in the first direction.

US Pat. No. 11,114,587

STREAMLINED GAN-BASED FABRICATION OF LIGHT EMITTING DIODE STRUCTURES

Odyssey Semiconductor, In...


1. A method for fabricating a microLED array, the method comprising:providing a sapphire substrate member comprising a surface region;
forming an n-type gallium nitride material overlying the surface region;
forming an active layer overlying the n-type gallium nitride material, the active layer having a thickness ranging from about 50 to about 100 nanometers and characterized by three to fifteen quantum well regions;
forming a p-type gallium nitride material overlying the active layer to form a stack including the n-type gallium nitride material, the active layer, and the p-type gallium nitride material;
forming a plurality of p-type contact regions overlying the p-type gallium and nitride material, each of the p-type contact regions having an ohmic contact region and an overlying capping metal layer, the plurality of p-type contact regions being configured as an N by M array, where N is 10 to 5000 and M is 10 to 5000, such that each of the p-type contact regions has a size of a pixel element;
forming an n-type contact frame using a photolithography lift off and a metal deposition process;
performing an etching process to remove material in a plurality of exposed regions while the n-type contact frame and the plurality of p-type contact regions mask underlying regions; causing formation of a plurality of the pixel elements, each of which has been separated from each other, and a trench region to expose a portion of the n-type gallium nitride material during the etching process; and
forming an n-type contact region comprising a metal fill material overlying an exposed portion of the n-type gallium nitride material wherein the method further comprising forming a conformal passivation layer overlying a surface region of a plurality of exposed regions of the plurality of pixel elements, forming a planarizing layer overlying a topography of the conformal passivation layer; removing a thickness of the planarizing layer to expose an upper region of the n-type contact region and a portion of each of the p-type contact regions, the upper region of the n-type contact region having a portion of the conformal passivation layer and the portion of each of the p-type contact regions having a portion of the conformal passivation layer, and removing the portion of the conformal passivation layer overlying each of the p-type contact regions and the portion of the conformal passivation layer overlying the upper region of the n-type contact region to expose each of the p-type contact regions and expose the n-type contact region.

US Pat. No. 11,114,586

SEMICONDUCTOR LIGHT EMITTING DEVICE

KABUSHIKI KAISHA TOSHIBA,...


1. A semiconductor light emitting device, comprising:a substrate; and
a multi quantum well layer provided on the substrate,
the multi quantum well layer including a plurality of InGaAs well layers and a plurality of barrier layers, the plurality of barrier layers each being made of AlGaAsP mixed crystal represented by a formula AlzGa1-zAs1-yPy(0?z<1, 0 wherein the first barrier layers have first thicknesses in the first direction, respectively, and the second barrier layers have second thicknesses in the first direction, respectively, the second thicknesses being larger than the first thicknesses.


US Pat. No. 11,114,585

ADVANCED ELECTRONIC DEVICE STRUCTURES USING SEMICONDUCTOR STRUCTURES AND SUPERLATTICES

Silanna UV Technologies P...


1. A semiconductor structure comprising:a p-type superlattice region;
an i-type superlattice region; and
an n-type superlattice region;
wherein:
at least one of the p-type superlattice region, the i-type superlattice region and the n-type superlattice region comprises a plurality of unit cells exhibiting a monotonic change in average composition along a growth axis from a first average composition corresponding to a first wider band gap (WBG) material to a second average composition corresponding to a first narrower band gap (NBG) material, or from a third average composition corresponding to a second NBG material to a fourth average composition corresponding to a second WBG material, with no abrupt changes in polarization at interfaces between each region.

US Pat. No. 11,114,584

OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...


1. An optoelectronic component comprising an active layer having a multiple quantum well structure, wherein the multiple quantum well structure comprises quantum well layers, comprising Alx1Iny1Ga1-x1-y1N with 0?x1<0.03, 0?y1?0.1 and x1+y1?1, and barrier layers comprising Alx2Iny2Ga1-x2-y2N with 0?x2?1, 0?y2?0.02 and x2+y2?1, the barrier layers have a spatially varying aluminium content x2, a maximum value of the aluminium content in the barrier layers is x2,max?0.05, a minimum value of the aluminium content in the barrier layers is x2,min<0.05, the multiple quantum well structure is arranged between an n-type semiconductor region and a p-type semiconductor region, an intermediate layer is arranged between a barrier layer and a subsequent quantum well layer in a direction pointing from the n-type semiconductor region to the p-type semiconductor region, the intermediate layer is directly adjacent to the subsequent quantum well layer, and the intermediate layer comprises Alx3Iny3Ga1-x3-y3N with 0?x3<0.03, 0?y3?0.02 and x3+y3?1.

US Pat. No. 11,114,583

LIGHT EMITTING DEVICE ENCAPSULATED ABOVE ELECTRODES

NICHIA CORPORATION, Anan...


1. A light emitting device comprising:a light emitting element having a first face on which a first electrode and a second electrode are provided;
a wavelength converting member covering a whole of the light emitting element except for the first face such that a first surface of the wavelength converting member and the first face constitute a substantially flat plane;
a first electrically conductive material having a first conductive material surface connected to the first face and the first surface of the wavelength converting member to be electrically connected to the first electrode and a second conductive material surface opposite to the first conductive material surface in a thickness direction perpendicular to the substantially flat plane;
a second electrically conductive material having a third conductive material surface connected to the first face and the first surface of the wavelength converting member to be electrically connected to the second electrode and a fourth conductive material surface opposite to the third conductive material surface in the thickness direction; and
an insulating member comprising:a first part disposed on the first electrically conductive material such that the first electrically conductive material is provided between the first part and the first face and is provided between the first part and the wavelength converting member, the first part having a first insulating member surface connected to a part of the second conductive material surface and a second insulating member surface opposite to the first insulating member surface in the thickness direction, the second insulating member surface being separated in the thickness direction from a remaining part of the second conductive material surface other than the part of the second conductive material surface;
a second part disposed on the second electrically conductive material such that the second electrically conductive material is provided between the second part and the first face and is provided between the second part and the wavelength converting member, the second part having a third insulating member surface connected to a part of the fourth conductive material surface and a fourth insulating member surface opposite to the third insulating member surface in the thickness direction, the fourth insulating member surface being separated in the thickness direction from a remaining part of the fourth conductive material surface other than the part of the fourth conductive material surface; and
a third part integrated with the first part and the second part to contact the first face between the first electrode and the second electrode.


US Pat. No. 11,114,582

DISPLAY APPARATUS WITH INCREASED SELF-ALIGNMENT EFFICIENCY

Samsung Display Co., Ltd....


1. A display apparatus comprising:a substrate;
a first electrode on the substrate;
a second electrode on the substrate and being opposite the first electrode;
a plurality of light-emitting devices on the first electrode and the second electrode;
a third electrode on the first electrode and contacting the first electrode; and
a fourth electrode on the second electrode and contacting the second electrode,
wherein each of the light-emitting devices is between the first and second electrodes and the third and fourth electrodes, and
wherein one end of each of the light-emitting devices is between the first electrode and the third electrode.

US Pat. No. 11,114,581

METHOD FOR PRODUCING SOLAR CELL MODULE

SHARESUN CO., LTD.


1. A method for producing a crystalline silicon solar cell module, wherein crystalline silicon solar cells required by a crystalline silicon solar cell module and corresponding connecting strips are first positioned according to design arrangement of the crystalline silicon solar cell module, and subsequently the crystalline silicon solar cells are soldered and connected via a non-contact soldering and connecting method, comprising the steps of:(1) positioning the crystalline silicon solar cells and the corresponding connecting strips on a bottom layer;
(2) placing a top layer on the crystalline silicon solar cells and the corresponding connecting strips;
(3) utilizing weight of the top layer or external pressure to enable the connecting strips to be attached to metal grid lines of the crystalline silicon solar cells; and
(4) soldering and connecting all of the crystalline silicon solar cells via a non-contact soldering and connecting method.

US Pat. No. 11,114,580

PHOTOVOLTAIC DEVICES AND METHOD OF MAKING

First Solar, Inc., Tempe...


1. A photovoltaic device, comprising:a layer stack comprising a transparent conductive layer; and
an absorber layer disposed on the layer stack, wherein:the absorber layer comprises cadmium, selenium, tellurium, and zinc,
the absorber layer comprises a first region disposed proximate to the layer stack relative to a second region,
the first region of the absorber layer is disposed at a front interface of the absorber layer,
the second region of the absorber layer is disposed at a back interface of the absorber layer,
the first region of the absorber layer has a thickness between 200 nanometers to 1500 nanometers,
the second region of the absorber layer has a thickness between 200 nanometers to 1500 nanometers, and
a ratio of an average atomic concentration of selenium in the first region of the absorber layer to an average atomic concentration of selenium in the second region of the absorber layer is greater than 2.


US Pat. No. 11,114,579

METHOD FOR PREPARING ULTRATHIN TWO-DIMENSIONAL NANOSHEETS AND APPLICATIONS THEREOF

UNIVERSITY OF ELECTRONIC ...


1. A method, comprising:placing BiX3 powder where X=I, Br, or Cl in a crucible, and putting the crucible on a first heating zone of a furnace disposed at a gas inlet of a quartz tube; placing substrates covered with metal sheets on a second heating zone of the furnace disposed at a gas outlet of the quartz tube;
vacuumizing the quartz tube by a mechanical pump; pumping Ar gas into the quartz tube until a gas pressure is equal to 101.325 kPa; pumping a carrier gas into the quartz tube and adjusting and maintaining a steady flow rate of the carrier gas; and
heating and maintaining the second heating zone; heating the first heating zone to evaporate BiX3 until the ultrathin 2D nanosheets are formed on the substrate; and cooling the substrate naturally to 15-30° C.

US Pat. No. 11,114,578

IMAGE SENSORS WITH SILVER-NANOPARTICLE ELECTRODES

SHENZHEN XPECTVISION TECH...


1. An apparatus comprising:an array of avalanche photodiodes (APDs), each of the APDs comprising an absorption region, an electrode and a first amplification region;
wherein the absorption region is configured to generate charge carriers from a photon absorbed by the absorption region;
wherein the electrode comprises silver nanoparticles and is electrically connected to the absorption region;
wherein the first amplification region comprises a junction with an electric field in the junction;
wherein the electric field is at a value sufficient to cause an avalanche of charge carriers entering the first amplification region, but not sufficient to make the avalanche self-sustaining;
wherein the junctions of the APDs are discrete;
wherein the silver nanoparticles comprise silver nanowires.

US Pat. No. 11,114,577

PHOTOVOLTAIC POWER GENERATION DEVICE

PANASONIC INTELLECTUAL PR...


1. A photovoltaic power generation device comprising:a first solar cell module including a first solar cell panel and a first frame installed at an edge portion of the panel;
a second solar cell module including a second solar cell panel and a second frame installed at an edge portion of the panel, the second solar cell module being disposed next to and on a ridge-side of the first solar cell module with a space therebetween;
a mounting bracket to be fixed to a roof, the mounting bracket allowing a part of the first frame that is installed at a ridge-side edge portion of the first solar cell module, and a part of the second frame that is installed at an eave-side edge portion of the second solar cell module, to be mounted thereon; and
a fixing bracket disposed at the space to straddle between the first frame and the second frame, the fixing bracket being fixed to the mounting bracket to press the frames from above,
wherein the photovoltaic power generation device further comprises a base bracket to which a bolt for fixing the fixing bracket is fastened,
the mounting bracket includes a guide rail portion that slidably supports the base bracket such that the base bracket is slidable along a eave-ridge direction of the roof,
the fixing bracket is fixed to the mounting bracket via the base bracket inserted into the guide rail portion, and
wherein the first frame includes a first inner flange portion extending to an inner side of the first solar cell module, and
the base bracket includes an engaging portion that protrudes higher than the top of the mounting bracket and engages with the first inner flange portion.

US Pat. No. 11,114,576

SOLAR CELL MODULE

LG ELECTRONICS INC., Seo...


1. A solar cell module comprising:a plurality of first conductive lines connected to a first electrode of a first solar cell and extended in a first direction;
a plurality of second conductive lines connected to a second electrode of a second solar cell adjacent with the first solar cell and extended in the first direction; and
an intercell connector spaced apart from the first solar cell and the second solar cell and extended in a second direction crossing the first direction, the intercell connector including a first connection portion connected with the plurality of first conductive lines and a second connection portion connected with the plurality of second conductive lines;
wherein a separation distance between the first solar cell and the first connection portion is closer than a separation distance between the second solar cell and a part of the intercell connector positioned on the same line as the first connection portion, and
a separation distance between the second solar cell and the second connection portion is closer than a separation distance between the first solar cell and an another part of the intercell connector positioned on the same line as the second connection portion.

US Pat. No. 11,114,575

SOLAR CELL

ZHEJIANG JINKO SOLAR CO.,...


1. A solar cell, comprising:a substrate;
an emitter, a first passivation film, an antireflection film and a first electrode that are sequentially disposed on an upper surface of the substrate;
a tunneling layer, a retardation layer, a field passivation layer, a second passivation film and a second electrode that are sequentially disposed on a lower surface of the substrate;
wherein the retardation layer is configured to retard a migration of a doped ion in the field passivation layer to the substrate, and the retardation layer comprises:a first retardation sub-layer overlapping with a projection of the second electrode, and
a second retardation sub-layer misaligning with a projection of the second electrode, and at least the second retardation sub-layer being configured as an intrinsic semiconductor layer;

wherein a thickness of the first retardation sub-layer is smaller than a thickness of the second retardation sub-layer in a direction perpendicular to the upper surface of the substrate, and a surface of the first retardation sub-layer away from the substrate is flush with a surface of the second retardation sub-layer away from the substrate.

US Pat. No. 11,114,574

SEMICONDUCTOR SENSOR

OSRAM Opto Semiconductors...


1. A semiconductor sensor comprising:a detector chip that detects radiation of a first wavelength range or green light,
an interference filter that optically precedes the detector chip and is permeable to the radiation of the first wavelength range or the green light, and impermeable and reflective to radiation of a second wavelength range or red or near-infrared light,
a color filter that optically precedes the interference filter,
wherein
the color filter has a transparency of at least 60% for the first wavelength range or green light, and absorbs radiation of the second wavelength range or red or near-infrared light, and
the semiconductor sensor appears gray or black to an observer in a region of the interference filter independently of the angle,
the interference filter comprises at least one refractive index matching layer that delimits the interference filter toward the color filter, and
a cast body in which the interference filter and the detector chip are embedded,
wherein the cast body contains least one plastic to which at least one filter material is added, and
the cast body extends across the interference filter so that the color filter is formed by the part of the cast body extending across the interference filter.

US Pat. No. 11,114,573

OPTOELECTRONIC MODULE ASSEMBLY AND MANUFACTURING METHOD

ams Sensors Singapore Pte...


1. An optoelectronic module comprising:an active optoelectronic component in or on a mounting substrate, the mounting substrate having a first surface and having a second surface on an opposite side from the first surface;
an optical sub-assembly;
a spacer disposed between the mounting substrate and the optical sub-assembly so as to establish a particular distance between the active optoelectronic component and the optical sub-assembly;
first electrical contacts disposed on the first surface of the mounting substrate; and
second electrical contacts disposed on the second surface of the mounting substrate;
wherein the first and second electrical contacts are configured to permit active alignment of the active optoelectronic component and the optical sub-assembly.

US Pat. No. 11,114,572

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...


1. A semiconductor device comprising:a semiconductor layer of a first conductivity type having a first surface and a second surface on an opposite side to the first surface;
a second semiconductor layer of a second conductivity type embedded in the semiconductor layer;
a first trench and a second trench formed in the semiconductor layer such that the first trench and the second trench extend from the first surface in a thickness direction of the semiconductor layer and penetrate the second semiconductor layer in a sectional view in a direction intersecting the first surface;
a first insulating film formed on at least a side surface of the first trench;
a second insulating film formed on at least a side surface of the second trench;
a first sinker layer of the second conductivity type formed in a first portion of the semiconductor layer defined by the second semiconductor layer, the first trench and second trench such that the first sinker layer extends in a depth direction of the first trench and is in contact with the second semiconductor layer and the first insulating film;
a second sinker layer of the second conductivity type formed in the first portion of the semiconductor layer such that the second sinker layer extends in a depth direction of the second trench and is in contact with the second semiconductor layer and the second insulating film;
a diode impurity region of the first conductivity type which is formed on the first surface of the semiconductor layer and forms a Zener diode by pn junction between the first sinker layer and the diode impurity region;
a first wiring electrically connected to the diode impurity region; and
a second wiring electrically connected to the second sinker layer.

US Pat. No. 11,114,571

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

DENSO CORPORATION, Kariy...


10. The semiconductor device according to claim 1,wherein the maximum point indicates the maximum concentration in the impurity concentration profile of the lower diffusion region in the depth direction and a radial direction of the diode formation region.

US Pat. No. 11,114,570

MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF

E Ink Holdings Inc., Hsi...


1. A memory structure, comprising:a substrate;
a gate electrode located on the substrate;
a first isolation layer located on the gate electrode;
a thin metal layer located on the first isolation layer and having a plurality of metal particles;
a plurality of indium gallium zinc oxide (IGZO) particles located on the metal particles;
a second isolation layer located on the IGZO particles;
an IGZO channel layer located on the second isolation layer; and
a source/drain electrode located on the IGZO channel layer.

US Pat. No. 11,114,569

SEMICONDUCTOR DEVICE WITH AN OXIDIZED INTERVENTION AND METHOD FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device, comprising:a substrate;
a memory unit comprising a memory unit conductive layer positioned above the substrate, a lateral oxidized intervention layer positioned below the memory unit conductive layer and comprising a sidewall portion and a center portion, and a plurality of memory unit spacers attached to the sidewall portion of the lateral oxidized intervention layer; and
a well region doped with a dopant and disposed in the substrate, wherein a portion of the well region is defined as a control unit positioned in the substrate and below the lateral oxidized intervention layer;
wherein the sidewall portion of the lateral oxidized intervention layer has a greater concentration of oxygen than the center portion of the lateral oxidized intervention layer.

US Pat. No. 11,114,568

SEMICONDUCTOR DEVICE

Japan Display Inc., Mina...


1. A semiconductor device having a thin film transistor (TFT) comprising an oxide semiconductor layer, a drain electrode, a source electrode, a gate insulating film, a gate electrode, and a channel, which is formed in the oxide semiconductor layer between the drain electrode and the source electrode,a channel length direction is defined by a direction the drain electrode and the source electrode oppose to each other,
a channel width direction is defined by an orthogonal direction to the channel length direction,
wherein a width of the oxide semiconductor layer in the channel width direction is wider than a width of the gate electrode in the channel width direction,
a width of the drain electrode and a width of the source electrode in the channel width direction are wider than the width of the oxide semiconductor layer in the channel width direction, and
wherein the gate insulating film is formed between the gate electrode and the oxide semiconductor layer,
the oxide semiconductor layer that is not covered by the gate electrode is covered by a silicon oxide film in addition to the gate insulating film.

US Pat. No. 11,114,567

MANUFACTURING METHOD OF TFT SUBSTRATE AND TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...


1. A manufacturing method of thin film transistor (TFT) substrate, which comprises:Step 1: providing a base substrate, and forming a data line and a source connected to the data line on the base substrate;
Step 2: forming an active layer, the active layer being at least partially above the source;
Step 3: forming a gate insulating layer on top of the active layer, the source, the data line and the base substrate such that a portion of the gate insulating layer is directly formed on the top of the active layer to completely cover and directly contact entirety of the top of the active layer, and patternizing the gate insulating layer to form a first via corresponding to the active layer;
Step 4: forming a first gate, a second gate and a drain, the first gate and the second gate being on the gate insulating layer and corresponding respectively to two lateral sides of the active layer, the drain being at least partially inside the first via and connected to the active layer through the first via;
Step 5: forming a passivation layer on the drain, the first gate, the second gate and the gate insulating layer, patternizing the passivation layer to form a second via corresponding to the drain; and
Step 6: forming a pixel electrode, the pixel electrode being at least partially inside the second via and connected to the drain through the second via,
wherein the drain is formed after the formation of the gate insulating layer and is filled in the first via of the gate insulating layer such that the connection between drain and the active layer is formed after the formation of the gate insulating layer; and
wherein the second via is located above and corresponding, in position, to the first via such that the second via is communication with the first via and a part of the pixel electrode that is located in the second via is in direct, electrical contact with a part of the drain that is located in the first via and an orthographic projection that is cast by the part of the pixel electrode located in the second via on the base substrate completely covers orthographic projections that are respectively cast by the part of drain located in the first via and the active layer on the base substrate.

US Pat. No. 11,114,566

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device comprising:a first fin, a second fin and a dummy fin arranged on a substrate along a first direction, wherein the dummy fin is disposed between the first fin and the second fin;
a first epitaxial source/drain region over the first fin;
a first metal gate over the first fin and a second metal gate over the second fin;
an isolation structure on the dummy fin, wherein the dummy fin and the isolation structure separate the first and the second metal gate; and
a metal wire in direct contact with a top surface and opposite sidewalls of the dummy fin and extending over the first epitaxial source/drain region along the first direction.

US Pat. No. 11,114,565

SEMICONDUCTOR DEVICE

National Institute of Adv...


1. A semiconductor device comprising:a semiconductor layer having a thickness of 20 nm or less;
a gate electrode formed over the semiconductor layer via a gate insulating film;
a pair of source/drain regions in which an impurity of a first conductivity type is introduced into the semiconductor layer next to the gate electrode;
a first plug electrically connected to the gate electrode;
a ferroelectric film connected to an upper surface of the first plug; and
a second plug connected to an upper surface of the ferroelectric film,
wherein the gate electrode and the source/drain regions constitute a first field effect transistor, and
a first area where a contact surface between the first plug and the ferroelectric film and a contact surface between the ferroelectric film and the second plug overlap in a plan view is smaller than a second area where the gate electrode and the semiconductor layer overlap.

US Pat. No. 11,114,564

FERROELECTRIC MFM INDUCTOR AND RELATED CIRCUITS

TAIWAN SEMICONDUCTOR MANU...


1. A structure, comprising:a substrate;
a fin-shaped raised semiconductor body region over the substrate;
a dielectric layer between the substrate and the fin-shaped raised semiconductor body region;
an insulator bump region between the fin-shaped raised semiconductor body region and the dielectric layer;
a gate structure at least partially over the fin-shaped raised semiconductor body region, the gate structure including a gate dielectric layer and a metal-ferroelectric-metal gate stack over the gate dielectric layer, the metal-ferroelectric-metal gate stack having a first metal layer, a second metal layer and a ferroelectric ZrO2 layer sandwiched between the first metal layer and the second metal layer; and
a source/drain structure adjacent to the semiconductor body region.

US Pat. No. 11,114,563

SEMICONDUCTOR DEVICES WITH LOW JUNCTION CAPACITANCES AND METHODS OF FABRICATION THEREOF

Taiwan Semiconductor Manu...


1. A semiconductor device comprising:a substrate;
an active area in the substrate, the active area, when viewed in cross section, havinga lower portion with a first width laterally bounded on a first side and a second side by a first dielectric layer and a second dielectric layer, respectively,
a mid portion, above the lower portion, the mid portion having a second width laterally bounded by a third dielectric layer and a fourth dielectric layer, respectively, the second width being less than the first width and the third and fourth dielectric layers at least partially disposed over the first and second dielectric layers, the third and fourth dielectric layers being distinct layers from the first and second dielectric layers, and
a channel portion, the channel portion having a third width bounded by a first source/drain region and a second source/drain region, respectively, the third width being less than the second width, wherein the lower portion, the mid portion, and the channel portion are a continuous semiconductor region;

a gate structure formed, at least in part, above the channel portion; and
spacers on opposing sides of the channel portion, the spacers being separated from the active area by the third dielectric layer and the fourth dielectric layer.

US Pat. No. 11,114,562

SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...


1. A semiconductor device, comprising:a first gate structure extending along a first direction on a substrate;
a first drain region extending along the first direction on one side of the first gate structure;
a first source region and a second source region adjacent to another side of the first gate structure;
a second gate structure on the substrate and extending along the first direction, wherein the first source region and the second source region are between the first gate structure and the second gate structure, and an edge of the first source region and an edge of the second source region between the first gate structure and the second gate structure are bordered and directly contacted by a shallow trench isolation under a top view;
a first body contact region disposed between the first source region and the second source region; and
a first body implant region extending along the first direction and overlapping part of the first gate structure, wherein a long side of the first body implant region is less than a long side of the first gate structure, wherein bottom surfaces of the first drain region, the first source region, the second source region, the first body contact region and the first body implant region are coplanar, a concentration of the first body contact region is greater than a concentration of the first body implant region, and an edge of the first body contact region is aligned with an edge of the first body implant region under the first gate structure.

US Pat. No. 11,114,561

LDMOS DEVICE AND METHOD FOR MANUFACTURING SAME

Shanghai Huahong Grace Se...


1. A LDMOS device, comprising:a first epitaxial layer of a second conduction type, wherein a drift region of a first conduction type and a body region of a second conduction type are formed in selected areas of the first epitaxial layer, and the drift region horizontally makes contact with the body region or is spaced from the body region by a certain distance, the first epitaxial layer is a silicon epitaxial layer;
a gate structure which is formed on a surface of the body region by stacking a gate dielectric layer and a polysilicon gate, wherein channels are formed on the surface, covered by the polysilicon gate, of the body region, and a second side of the gate dielectric layer and a second side of the polysilicon gate extend onto a surface of the drift region;
a source region which is formed on the surface of the body region and has a second side self-aligned with a first side of the polysilicon gate;
a drain region which is formed in a selected area of the drift region and has a first side spaced from the second side of the polysilicon gate by a certain distance; and
a common dielectric layer, wherein the common dielectric layer covers a portion, between the second side of the polysilicon gate and the drain region, of the surface of drift region, extends onto a surface of the polysilicon gate and also covers part of a surface of the drain region, a self-aligned metal silicide is formed on portions, not covered by the common dielectric layer, of the surfaces of the polysilicon gate, the source region and the drain region, and the common dielectric layer serves a growth barrier layer of the self-aligned metal silicide; and
a drain terminal field plate is formed on a portion, between the second side of the polysilicon gate and the drain region, of a surface of the common dielectric layer, and a portion, located at a bottom of the drain terminal field plate, of the common dielectric layer serves as a field plate dielectric layer;
the drain terminal field plate comprises a second polysilicon layer or a self-aligned metal silicide formed through self-aligned metal silicification on a surface of the second polysilicon layer;
the polysilicon gate is connected to a gate electrode formed by a front metal layer via the contact hole at the top of the polysilicon gate, and the drain terminal field plate is also connected to the gate electrode formed by the front metal layer via the contact hole at the top of the drain terminal field plate.

US Pat. No. 11,114,560

SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...


1. A silicon carbide semiconductor device, comprising:a silicon carbide semiconductor substrate of a first conductivity type, having a front surface and a back surface opposite to the front surface;
a first semiconductor layer of the first conductivity type, provided on the front surface of the silicon carbide semiconductor substrate, and containing silicon carbide, the first semiconductor layer having an impurity concentration lower than an impurity concentration of the silicon carbide semiconductor substrate, and further having a first side, and a second side opposite to the first side and facing the front surface of the silicon carbide semiconductor substrate;
a first base region of a second conductivity type, selectively provided in the first semiconductor layer, the first base having a first surface, and a second surface opposite to the first surface and facing the front surface of the silicon carbide semiconductor substrate;
a second semiconductor layer of the second conductivity type, provided on the first side of the first semiconductor layer, and containing silicon carbide;
a first semiconductor region of the first conductivity type, selectively provided in a surface layer of the second semiconductor layer;
a second semiconductor region of the second conductivity type, selectively provided in the surface layer of the second semiconductor layer, and being in contact with the first semiconductor region, the second semiconductor region having a first surface, and a second surface opposite to the first surface and facing the front surface of the silicon carbide semiconductor substrate;
a first electrode in contact with the first semiconductor region and the second semiconductor region; and
a second electrode provided on the back surface of the silicon carbide semiconductor substrate, wherein
the first base region is provided so as to overlap the second semiconductor region in a depth direction,
in the second semiconductor region, a distribution of point defects in the depth direction from the first surface of the second semiconductor region has first and second peaks at positions deeper than a position of an interface between the first semiconductor layer and the second surface of the first base region, and
the first peak has a deeper position than does the first peak and has a greater quantity of the point defects than does the second peak.

US Pat. No. 11,114,559

SEMICONDUCTOR DEVICE HAVING REDUCED GATE CHARGES AND SUPERIOR FIGURE OF MERIT

Vishay-Siliconix, LLC, S...


1. A semiconductor device comprising:a planar first epitaxial layer; and
a plurality of trench-like structures that extend into a second epitaxial layer coupled to the first epitaxial layer, said plurality of trench-like structures comprising:a first plurality of said plurality of trench-like structures, said first plurality comprising first trench-like structures, each trench-like structure in said first plurality comprising a gate electrode contacted to gate metal and insulated from source metal by an intervening oxide layer, each trench-like structure in said first plurality further comprising a source electrode of polysilicon material contacted to said source metal, wherein said gate electrode is separated from said second epitaxial layer by a gate oxide, and wherein said source electrode is separated from said second epitaxial layer by a shield oxide; and

a second plurality of said plurality of trench-like structures, said second plurality comprising second trench-like structures, said second trench-like structures interleaved with said first trench-like structures in alternating fashion such that every other of said plurality of trench-like structures is one of said second trench-like structures, wherein each of said second trench-like structures is adjacent to both a respective first source region and a respective second source region, wherein each trench-like structure of said second trench-like structures is filled with said polysilicon material to form only one polysilicon region within said each trench-like structure of said second trench-like structures, wherein each said only one polysilicon region is electrically and physically contacted to said source metal via a source contact and is separated from said second epitaxial layer by said shield oxide, wherein each said only one polysilicon region is also electrically and physically contacted to said gate metal via a gate contact, and wherein a bottom surface of said only one polysilicon region and a bottom surface of said source electrode are aligned with each other substantially in a same plane that is parallel to said planar first epitaxial layer.

US Pat. No. 11,114,558

SHIELDED GATE TRENCH MOSFET INTEGRATED WITH SUPER BARRIER RECTIFIER

NAMI MOS CO., LTD., New ...


1. An integrated circuit comprising a shielded gate trench metal oxide semiconductor transistor (SGT MOSFET) and a super barrier rectifier (SBR) horizontally disposed in two different areas on a single chip, further comprising:an epitaxial layer of a first conductivity type extending over a substrate of said first conductivity type, said substrate having a higher doping concentration than said epitaxial layer;
said SGT MOSFET further comprising:
a plurality of first type trenches formed in said epitaxial layer, each of said first type trenches being filled with a first shielded electrode and a first gate electrode, said shielded electrode being insulated from said epitaxial layer by a first insulating film, said first gate electrode being insulated from said epitaxial layer by a first gate oxide film, said first shielded electrode and said first gate electrode being insulated from each other;
a first body region of a second conductivity type having a first source region of said first conductivity type thereon and surrounding said first gate electrode padded by said first gate oxide film;
said SBR further comprising:
at least one second type trench formed in parallel with said first type trenches, said second type trench being filled with said a second shielded electrode and a second gate electrode, said second shielded electrode being insulated from said epitaxial layer by a second insulating film, said second gate electrode being insulated from said epitaxial layer by a second gate oxide film, said second shielded electrode and said second gate electrode being insulated from each other;
said second gate oxide film having a thickness less than said first gate oxide film; a second body region of said second conductivity type having a second source region thereon and surrounding said second gate electrode padded by said second gate oxide film;
said first body region, said second body region, said first and second source regions and said second gate electrode being shorted to a source metal through a plurality of trenched contacts; and
said second body region has a shallower junction depth and a lower doping concentration than said first body region.

US Pat. No. 11,114,556

GATE STACK DESIGN FOR GAN E-MODE TRANSISTOR PERFORMANCE

Intel Corporation, Santa...


1. An integrated circuit structure, comprising:a first layer including a group III-V semiconductor material;
a gate stack over the first layer, and including a second layer between third and fourth layers, the second layer comprising aluminum, gallium, and nitrogen, and the third and fourth layers each comprising aluminum and nitrogen; and
a first region and a second region each including a group III-V semiconductor material and separated from at least a portion of the gate stack by respective third regions, the third regions including a group III-V semiconductor material.

US Pat. No. 11,114,555

HIGH ELECTRON MOBILITY TRANSISTOR DEVICE AND METHODS FOR FORMING THE SAME

Vanguard International Se...


1. A high electron mobility transistor device, comprising:a substrate;
a buffer layer disposed over the substrate, wherein the buffer layer comprises a gradient buffer layer disposed over a superlattice buffer layer, and wherein the superlattice buffer layer comprises a plurality of pairs of AlN layers and AlGaN layers, the gradient buffer layer comprises a plurality of AlGaN layers with different concentrations, and one of the plurality of AlGaN layers of the gradient buffer layer is in contact with one of the AlN layers of the superlattice buffer layer;
a plurality of pairs of alternating layers disposed over the substrate buffer layer, wherein each pair of alternating layers comprises a carbon-doped gallium nitride layer and an undoped gallium nitride layer, and a topmost layer of the pairs of alternating layers is a topmost undoped gallium nitride layer;
a stress-relief layer disposed over the topmost undoped gallium nitride layer;
a gallium nitride layer disposed over the stress-relief layer, wherein the stress-relief layer is in contact with the gallium nitride layer and the topmost undoped gallium nitride layer; and
a barrier layer disposed over the gallium nitride layer, wherein a 2DEG is created at the interface between the gallium nitride layer and the barrier layer.

US Pat. No. 11,114,554

HIGH-ELECTRON-MOBILITY TRANSISTOR HAVING A BURIED FIELD PLATE

Infineon Technologies Aus...


1. A high-electron-mobility semiconductor device, the device comprising:a buffer region comprising first, second and third cross-sections forming a stepped lateral profile, the first cross-section being thicker than the third cross-section and comprising a first buried field plate disposed therein, the second cross-section interposed between the first and third cross-sections and forming oblique angles with the first and third cross-sections;
a barrier region of uniform thickness extending along the stepped lateral profile of the buffer region, the barrier region separated from the first buried field plate by a portion of the buffer region;
a source electrode on the first cross-section and in ohmic contact with the channel;
a gate electrode on the first cross-section, the gate electrode being spaced apart from the channel by the barrier region; and
a drain electrode disposed outside of the first and second cross-sections and in ohmic contact with the channel,
wherein the buffer region comprises a first semiconductor material and the barrier region comprises a second semiconductor material, the first and second semiconductor materials having different band-gaps such that an electrically conductive channel comprising a two-dimensional charge carrier gas arises at an interface between the buffer and barrier regions due to piezoelectric effects,
wherein, in the absence of external bias to the channel, the channel extends completely across the second cross-section from the first cross-section to the third cross section.

US Pat. No. 11,114,553

LATERAL INSULATED GATE TURN-OFF DEVICE WITH INDUCED EMITTER

Pakal Technologies, Inc.,...


1. A lateral insulated gate turn-off (IGTO) device formed as a die comprising:a first semiconductor layer of a first conductivity type;
a well of a second conductivity type formed in the first semiconductor layer;
a first region of the first conductivity type formed in the well and shallower than the well;
a first electrode electrically contacting the first region;
at least one trenched first gate extending along the first region and into the well, the first gate not extending outside of the well, the at least one trenched first gate being connected to a first gate electrode;
a second region of the second conductivity type formed in the first semiconductor layer and laterally spaced from the well;
a second electrode electrically contacting the second region; and
at least one trenched second gate extending along the second region and into the first semiconductor layer, the at least one trenched second gate being connected to a second gate electrode;
wherein a lateral structure of npn and pnp transistors is formed, and wherein the well forms a first base of one of the transistors,
the well having dimensions and a dopant concentration such that, when a forward biasing voltage is applied between the first electrode and the second electrode and when a first turn-on voltage is applied to the first gate electrode, the at least one trenched first gate creates a first inversion layer in the well to turn on the IGTO device to conduct a lateral current between the first electrode and the second electrode, and
wherein the at least one trenched second gate is configured so that when a second turn-on voltage, different from the first turn-on voltage, is applied to the second gate electrode, the at least one trenched second gate creates a second inversion layer in the first semiconductor layer that extends between the second region and the first semiconductor layer.

US Pat. No. 11,114,552

INSULATED GATE TURN-OFF DEVICE WITH DESIGNATED BREAKDOWN AREAS BETWEEN GATE TRENCHES

Pakal Technologies, Inc.,...


1. A vertical insulated gate turn-off (IGTO) device comprising:a first semiconductor layer of a first conductivity type;
a second semiconductor layer of a second conductivity type overlying the first semiconductor layer; and
an array of cells comprising:a plurality of first insulated gates within trenches in the second semiconductor layer, the first insulated gates being electrically connected together, the first insulated gates having a gate oxide layer along sidewalls of the trenches; and
first regions of the second conductivity type within the second semiconductor layer between at least some of the trenches, the first regions having a dopant concentration higher than a dopant concentration in the second semiconductor layer, wherein the first regions do not extend to the trenches,
wherein a first portion of the second semiconductor layer is located above the first regions, and a second portion of the second semiconductor layer is located below the first regions,
wherein the cells conduct a current when the first insulated gates are biased beyond a threshold voltage.


US Pat. No. 11,114,551

FIN FIELD-EFFECT TRANSISTOR HAVING COUNTER-DOPED REGIONS BETWEEN LIGHTLY DOPED REGIONS AND DOPED SOURCE/DRAIN REGIONS

Semiconductor Manufacturi...


1. A fin field-effect transistor, comprising:a semiconductor substrate;
a plurality of fins on the semiconductor substrate;
a gate structure crossing the fins by covering portions of top and side surfaces of the fins, wherein portions of the fins under the gate structure are channel regions;
lightly doped regions in the fins at both sides of the gate structure;
doped source/drain regions in the fins at both sides of the gate structure; and
counter doped regions in the fins and between the lightly doped regions and the doped source/drain regions, wherein:
the counter doped regions are between the lightly doped regions and the doped source/drain regions along a length direction of the fins and a direction perpendicular to the semiconductor substrate.

US Pat. No. 11,114,550

RECESSING STI TO INCREASE FIN HEIGHT IN FIN-FIRST PROCESS

Taiwan Semiconductor Manu...


1. A method comprising:forming a dummy gate stack over a semiconductor substrate and isolation regions, wherein the isolation regions extend into the semiconductor substrate;
epitaxially growing a source/drain region between the isolation regions and on a side of the dummy gate stack, wherein the source/drain region comprises opposite sidewalls;
recessing first portions of the isolation regions on opposite sides of the source/drain region so that top portions of the source/drain region protrude higher than the recessed first portions of the isolation regions, wherein the opposite sidewalls are exposed after the first portions of the isolation regions are recessed;
removing the dummy gate stack to reveal second portions of the isolation regions; and
recessing the second portions of the isolation regions, wherein a portion of the semiconductor substrate between and contacting the recessed first portions of the isolation regions forms a semiconductor fin.

US Pat. No. 11,114,549

SEMICONDUCTOR STRUCTURE CUTTING PROCESS AND STRUCTURES FORMED THEREBY

Taiwan Semiconductor Manu...


1. A method comprising:trimming a fin on a substrate, wherein trimming the fin comprises etching the fin to a level above top surfaces of neighboring isolation regions on the substrate, the fin protruding from between the neighboring isolation regions;
forming a liner along respective first sidewalls of a first section and a second section of the fin, the first sidewalls of the first section and the second section of the fin being formed by trimming the fin;
cutting the fin through the liner; and
forming a fill material along the liner and where the fin was cut.

US Pat. No. 11,114,548

SEMICONDUCTOR DEVICE HAVING SOURCE AND DRAIN IN ACTIVE REGION AND MANUFACTURING METHOD FOR SAME

Semiconductor Manufacturi...


1. A semiconductor device, comprising:a substrate;
a first active region on the substrate;
a first gate structure on the first active region, where the first gate structure comprises a first gate dielectric layer positioned on the first active region, a first gate positioned on the first gate dielectric layer, and a first buffer layer positioned on the first gate;
a first source and a first drain positioned in the first active region, where the first source and the first drain are respectively on two sides of the first gate structure, the first gate structure is not positioned directly above any portion of the first source nor the first drain, and a top surface of the first source is level with and directly next to a bottom surface of the first gate dielectric layer without an intervening structure between the top surface of the first source and the bottom surface of the first gate dielectric layer, where a top surface of the first drain is level with and directly next to the bottom surface of the first gate dielectric layer without an intervening structure between the top surface of the first drain and the bottom surface of the first gate dielectric layer; and
two spacers respectively positioned on side surfaces on two sides of the first gate without contacting surfaces of the first buffer layer, positioned directly above the first gate dielectric layer, and abutting against a top surface of the first gate dielectric layer without covering end top surfaces of the first gate dielectric layer at both ends of the first gate dielectric layer, side surfaces of the two spacers only contacting the first gate;
wherein a size of the first drain is larger than a size of the first source, the size of the first drain comprises a horizontal size of a portion of the first drain exposed on a top surface of the first active region along a channel direction and the size of the first source comprises a horizontal size of a portion of the first source exposed on the top surface of the first active region along the channel direction.

US Pat. No. 11,114,547

FIELD EFFECT TRANSISTOR WITH NEGATIVE CAPACITANCE DIELETRIC STRUCTURES

Taiwan Semiconductor Manu...


16. A method of fabricating a semiconductor device, the method comprising:forming a fin structure with a fin base portion and a fin top portion on a substrate;
forming a spacer structure in a first region of the fin top portion, wherein the spacer structure comprises a negative capacitance (NC) dielectric layer comprising an NC dielectric material, a non-NC dielectric structure, and an air gap;
forming a source/drain region on the fin base portion and in contact with the fin top portion, wherein the source/drain region, the NC dielectric layer, and the non-NC dielectric structure enclose the air gap; and
forming a gate structure on a second region of the fin top portion, wherein the gate structure comprises a gate dielectric layer having the NC dielectric material.

US Pat. No. 11,114,546

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device, comprising:a fin over a substrate;
a gate over a top surface of a channel portion of the fin;
a dielectric layer; and
a contact, wherein:a first portion of the fin, different than the channel portion of the fin, is in contact with the substrate,
the channel portion of the fin is spaced apart from the substrate,
a first sidewall of the dielectric layer faces the gate,
a second sidewall of the dielectric layer faces the fin,
a first portion of the second sidewall of the dielectric layer is in contact with the fin, and
a second portion of the second sidewall of the dielectric layer is spaced apart from the fin by the contact.


US Pat. No. 11,114,545

CAP LAYER AND ANNEAL FOR GAPFILL IMPROVEMENT

Taiwan Semiconductor Manu...


1. A method for semiconductor processing, the method comprising:forming a first fin and a second fin protruding from a substrate, the first fin and the second fin forming a trench between the first fin and the second fin;
forming a first film over a bottom surface and sidewalls of the trench;
performing a cyclic etch-dep process to form a second film over the first film, wherein a combined thickness of the first film and the second film is greater than half of a distance between the first fin and the second fin;
forming a dielectric cap layer on the second film;
after forming the dielectric cap layer, performing an anneal process on the second film; and
removing the dielectric cap layer, thereby exposing the second film.

US Pat. No. 11,114,544

INTEGRATED CIRCUIT DEVICE HAVING FIN-TYPE ACTIVE

Samsung Electronics Co., ...


1. An integrated circuit device comprising:a fin-type active region protruding from a top surface of a substrate and extending in a first direction that is parallel to the top surface of the substrate;
a gate structure on a top surface of the fin-type active region and extending on the substrate in a second direction that is perpendicular to the first direction;
a source/drain region on a first side of the gate structure and adjacent a side surface of the fin-type active region that protrudes from the top surface of the substrate;
a first contact structure on the source/drain region;
a contact capping layer on the first contact structure; and
a second contact structure on the gate structure,
wherein a top surface of the first contact structure has a first width in the first direction,
wherein a bottom surface of the contact capping layer has a second width that is greater than the first width of the top surface of the first contact structure in the first direction, and
wherein the contact capping layer comprises a protruding portion extending outward from a sidewall of the first contact structure, and
wherein a portion of a sidewall of the second contact structure is around the contact capping layer.

US Pat. No. 11,114,543

GROUP III-V DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...


1. A group III-V device structure, comprising:a channel layer formed over a substrate;
an active layer formed over the channel layer;
a doped structure formed over the active layer;
a first dielectric layer formed over the active layer and extends over the doped structure;
a gate electrode formed over the doped structure, wherein the gate electrode has an extending portion over the first dielectric layer, and the first dielectric layer is between the extending portion of the gate electrode and the doped structure;
a source electrode and a drain electrode formed over the active layer, wherein the source electrode and the drain electrode are formed on opposite sides of the gate electrode, and the doped structure is isolated from the source electrode by the first dielectric layer, wherein a bottom surface of the extending portion of the gate electrode is level with a top surface of the source electrode;
a through via structure formed through the channel layer, the active layer and a portion of the substrate, wherein the source electrode horizontally extends over and in direct contact with the through via structure, and the first dielectric layer is between the active layer and the source electrode, and the through via structure is through the first dielectric layer; and
a doped well region formed in a portion of the substrate and below the through via structure, wherein the doped well region surrounds a bottom portion of the through via structure.

US Pat. No. 11,114,542

SEMICONDUCTOR DEVICE WITH REDUCED GATE HEIGHT BUDGET

GLOBALFOUNDRIES U.S. INC....


1. A structure comprising:a plurality of recessed gate structures each of which include gate material and sidewall material formed on sidewalls of the gate material, the plurality of recessed gate structures separated from one another by a cut within the gate material;
at least one trench structure extending to within an insulator material and a poly material underneath the insulator material, the at least one trench structure being located on sides of the sidewall material which oppose the recessed gate structures; and
a capping material over the plurality of recessed gate structures, between the sidewall material, within the cut and within the at least one trench structure between the poly material and the insulator material on sides of the sidewall material opposing the recessed gate structures.

US Pat. No. 11,114,541

SEMICONDUCTOR DEVICE INCLUDING CAPACITOR

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device, comprising a capacitor including a bottom electrode, a dielectric layer, and a top electrode that are sequentially disposed on a substrate,wherein the dielectric layer comprises a hafnium oxide layer including hafnium oxide having a tetragonal crystal structure,
wherein the capacitor further includes two seed layers respectively disposed between the hafnium oxide layer and one selected from the bottom electrode and the top electrode,
wherein a first one of the two seed layers is an oxidation seed layer, and
wherein a second one of the two seed layers is a conductive seed layer including at least one selected from the group consisting of cobalt, nickel, copper, and cobalt nitride.

US Pat. No. 11,114,540

SEMICONDUCTOR DEVICE INCLUDING STANDARD CELLS WITH HEADER/FOOTER SWITCH INCLUDING NEGATIVE CAPACITANCE

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device, comprising:a first potential supply line for supplying a first potential;
a second potential supply line for supplying a second potential lower than the first potential;
a functional circuit including a PMOS transistor and a NMOS transistor; and
a switch disposed between the first potential supply line and one of the PMOS transistor and the NMOS transistor of the functional circuit, wherein:
a voltage potential of the first potential supply line is supplied to the functional circuit via the switch,
the switch includes a negative capacitance (NC) MOS FET showing a negative capacitance, and a drain or a source of the NC MOS FET is directly connected to the first potential supply line without interposing any electronic devices,
the NMOS and PMOS transistors are normal MOS FETs, where in an NC MOS FET, a gate voltage is applied to a gate dielectric layer through a negative capacitor, and in a normal MOS FET, a gate voltage is applied to a gate dielectric layer without a negative capacitor,
a gate dielectric layer of the NC MOS FET includes a first dielectric layer and a second dielectric layer disposed on and in direct contact with the first dielectric layer, and
the second dielectric layer includes a ferroelectric material.

US Pat. No. 11,114,539

GATE STACK FOR HETEROSTRUCTURE DEVICE

POWER INTEGRATIONS, INC.,...


1. A heterostructure semiconductor device comprising:a first active layer;
a second active layer disposed on the first active layer, a two-dimensional electron gas layer formed between the first and second active layers;
a sandwich gate dielectric layer structure disposed on the second active layer, wherein at least one layer of the sandwich gate dielectric layer structure is an ex-situ deposited layer formed through atomic layer deposition (ALD) with O2 plasma as compared to the first active layer and the second active layer and at least another layer of the sandwich gate dielectric layer structure is an in-situ deposited layer formed through metal-organic chemical vapor deposition (MOCVD) as compared to the first active layer and the second active layer, wherein the in-situ deposited layer has a thickness between 30-60 nanometers such that a critical voltage of the heterostructure semiconductor device is between approximately 100-170 volts;
a passivation layer disposed over the sandwich gate dielectric layer structure;
a gate that extends through the passivation layer to the top of the sandwich gate dielectric layer structure, wherein the gate is vertically separated from the second active layer by the sandwich gate dielectric layer structure and the sandwich gate dielectric layer structure is beneath a bottommost surface of the gate; and
first and second ohmic contacts disposed on the second active layer, the first and second ohmic contacts being laterally spaced-apart, the gate being disposed between the first and second ohmic contacts, wherein the two-dimensional electron gas layer is formed between the first and second active layers beneath the first and second ohmic contacts and the gate, wherein the heterostructure semiconductor device is a high-voltage FET.

US Pat. No. 11,114,538

TRANSISTOR WITH AN AIRGAP SPACER ADJACENT TO A TRANSISTOR GATE

Intel Corporation, Santa...


1. A microelectronic transistor, comprising:a microelectronic substrate;
a source region and a drain region formed in the microelectronic substrate;
a single layer of interlayer dielectric disposed over the microelectronic substrate;
a source contact extending through the interlayer dielectric and electrically contacting the source region;
a drain contact extending through the interlayer dielectric and electrically contacting the drain region;
a gate positioned between the source contact and the drain contact, wherein the gate comprises a gate dielectric layer and a gate electrode; and
an airgap spacer positioned between the gate and at least one of the source contact and the drain contact, wherein the airgap spacer is defined by only an exposed portion of the microelectronic substrate, an exposed portion of the single layer of interlayer dielectric, and an exposed portion of the gate, wherein the single layer of interlayer dielectric contacts the gate dielectric layer of the gate.

US Pat. No. 11,114,537

ENHANCEMENT-MODE HIGH ELECTRON MOBILITY TRANSISTOR

IMEC VZW, Leuven (BE)


1. A method for manufacturing an enhancement-mode high electron mobility transistor, wherein the method comprises:providing a stack of layers comprising:a substrate;
a III-V channel layer over the substrate;
a III-V barrier layer on the III-V channel layer;
a p-doped III-V layer on the III-V barrier layer, wherein the p-doped III-V layer has a first surface area; and
a Schottky contact interlayer on the p-doped III-V layer, wherein the Schottky contact interlayer has a surface that is in contact with the p-doped III-V layer and that has a second surface area, wherein the second surface area is less than the first surface area, and wherein the second surface area leaves a peripheral part of a top surface of the p-doped III-V layer uncovered by the Schottky contact interlayer; and

depositing a metal gate on the Schottky contact interlayer, thereby forming an interface between the metal gate and the Schottky contact interlayer such that entire interface has a third surface area, wherein the third surface area is less than the second surface area.

US Pat. No. 11,114,536

SEMICONDUCTOR DEVICE HAVING MULTIPLE DIMENSIONS OF GATE STRUCTURES AND METHOD FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device, comprising:a substrate comprising an array area and a peripheral area adjacent to the array area;
a first gate structure positioned in the array area; and
a second gate structure positioned in the peripheral area;
wherein a width of the first gate structure is less than a width of the second gate structure, and a depth of the first gate structure is less than a depth of the second gate structure;
wherein the first gate structure comprises a first gate insulating layer inwardly positioned in the array area, a first gate conductive layer positioned on the first gate insulating layer, and a first bottom capping layer positioned on the first gate conductive layer, wherein a top surface of the first bottom capping layer is at a same vertical level as a top surface of the substrate.

US Pat. No. 11,114,535

INTEGRATED CIRCUIT DEVICES AND METHODS OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. An integrated circuit device comprising:a substrate including a fin active region extending in a first direction;
a gate structure crossing the fin active region and extending in a second direction crossing the first direction;
source/drain regions on the fin active region at opposite sides of the gate structure;
a first contact structure electrically connected to one of the source/drain regions, the first contact structure comprising first and second sidewalls opposite each other in the second direction and a third sidewall adjacent the gate structure;
a pair of first contact block structures on the first and second sidewalls, respectively, of the first contact structure; and
an interlayer insulation layer on the gate structure, the interlayer insulation layer adjacent to the third sidewall of the first contact structure and adjacent to a fourth sidewall of each of the pair of first contact block structures in the first direction,
wherein at least one of the first contact block structures, in the pair of first contact block structures, has a width in the first direction that is greater than a width of the first contact structure in the first direction.

US Pat. No. 11,114,534

THREE-DIMENSIONAL NOR ARRAY INCLUDING VERTICAL WORD LINES AND DISCRETE CHANNELS AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...


1. A three-dimensional memory device, comprising:an alternating stack of source layers and drain layers located over a substrate;
memory openings vertically extending through the alternating stack;
vertical word lines located in each one of the memory openings and vertically extending through each of the source layers and the drain layers of the alternating stack;
vertical stacks of discrete semiconductor channels located in each one of the memory openings and contacting horizontal surfaces of a respective vertically neighboring pair of a source layer of the source layers and a drain layer of the drain layers; and
vertical stacks of discrete memory material portions located in each one of the memory openings and laterally surrounding a respective one of the vertical word lines, wherein each memory material portion is laterally spaced from a respective one of the semiconductor channels by a respective gate dielectric layer.

US Pat. No. 11,114,533

SEMICONDUCTOR DEVICE INCLUDING CONTACTS HAVING DIFFERENT HEIGHTS AND DIFFERENT WIDTHS

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device, comprising:a substrate including a first region and a second region;
a first gate stack on the first region of the substrate;
a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate;
a second gate stack on the second region of the substrate; and
a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate,
wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and
wherein a width of the second source/drain contact is greater than a width of the first source/drain contact,
wherein the first gate stack includes a first gate electrode and a first gate dielectric pattern, wherein the first gate electrode is on the substrate, and the first gate dielectric pattern is between the substrate and the first gate electrode,
wherein the second gate stack includes a second gate electrode and a second gate dielectric pattern, wherein the second gate electrode is on the substrate, and the second gate dielectric pattern is between the substrate and the second gate electrode, and
wherein a thickness of the second gate dielectric pattern is greater than a thickness of the first gate dielectric pattern.

US Pat. No. 11,114,532

SEMICONDUCTOR STRUCTURES AND METHODS OF FORMING THE SAME

Vanguard International Se...


1. A semiconductor structure, comprising:a substrate;
a source structure and a drain structure disposed on the substrate;
a gate structure disposed on the substrate and between the source structure and the drain structure;
a first field plate disposed on the substrate;
a first oxide layer disposed between the substrate and the first field plate;
a second field plate disposed on the first field plate, wherein the second field plate is closer to the drain structure than the first field plate;
a planarized second oxide layer disposed between the first oxide layer and the second field plate; and
a third field plate disposed on the second field plate, wherein the third field plate is closer to the drain structure than the second field plate, wherein an end of the third field plate close to the source structure is closer to the drain structure than an end of the second field plate close to the source structure, and the end of the second field plate close to the source structure is closer to the drain structure than an end of the first field plate close to the source structure.

US Pat. No. 11,114,531

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

Kabushiki Kaisha Toshiba,...


1. A semiconductor device comprising:a first electrode;
a second electrode;
a gate electrode;
an n-type first silicon carbide region positioned between the first electrode and the second electrode and between the gate electrode and the second electrode;
a p-type second silicon carbide region positioned between the first electrode and the first silicon carbide region;
a third silicon carbide region positioned between the first electrode and the p-type second silicon carbide region and spaced apart from the n-type first silicon carbide region, the third silicon carbide region being metallized silicon carbide containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and the third silicon carbide region having a crystal structure of silicon carbide; and
a gate insulating layer positioned between the gate electrode and the p-type second silicon carbide region, wherein
the at least one element is present at the carbon site of the crystal structure of silicon carbide, and
a concentration of the at least one element in the third silicon carbide region is 1×1019 cm?3 to 5×1022 cm?3.

US Pat. No. 11,114,530

QUANTUM WELL STACKS FOR QUANTUM DOT DEVICES

Intel Corporation, Santa...


1. A quantum dot device, comprising:a quantum well stack including a quantum well layer, wherein the quantum well layer includes an isotopically purified material; and
a gate above the quantum well stack,
wherein the isotopically purified material includes silicon and germanium.

US Pat. No. 11,114,529

GATE-ALL-AROUND FIELD-EFFECT TRANSISTOR DEVICE

Taiwan Semiconductor Manu...


1. A method of forming a semiconductor device, the method comprising:forming semiconductor fins over a substrate and a patterned mask layer over the semiconductor fins, wherein the semiconductor fins comprise epitaxial layers over semiconductor strips, wherein the epitaxial layers comprise alternating layers of a first semiconductor material and a second semiconductor material;
forming hybrid fins over isolation regions on opposing sides of the semiconductor fins, wherein each of the hybrid fins comprises a dielectric fin and a dielectric structure over the dielectric fin;
forming a gate structure over the semiconductor fins and over the hybrid fins;
removing first portions of the patterned mask layer, first portions of the epitaxial layers, and first portions of the dielectric structures that are disposed beyond sidewalls of the gate structure without substantially removing the dielectric fins;
forming an interlayer dielectric (ILD) layer over the dielectric fins and around the gate structure;
removing a gate electrode of the gate structure to form an opening in the gate structure, the opening exposing second portions of the patterned mask layer and second portions of the dielectric structure that are disposed under the gate structure;
removing a first dielectric structure of the dielectric structures while keeping a second dielectric structure of the dielectric structures; and
selectively removing the first semiconductor material, wherein after the selectively removing, the second semiconductor material forms nanowires, wherein the second dielectric structure extends further from the substrate than an uppermost surface of the nanowires.

US Pat. No. 11,114,528

POWER TRANSISTOR WITH DV/DT CONTROLLABILITY AND TAPERED MESAS

Infineon Technologies Aus...


1. A power semiconductor transistor, comprising:a semiconductor body coupled to a first load terminal and a second load terminal of the transistor and comprising a drift region of a first conductivity type configured to conduct a load current between the first and second load terminals;
at least one power unit cell comprising:at least one control trench having a control trench electrode;
at least one further trench having a further trench electrode;
at least one active mesa comprising a source region of the first conductivity type and electrically connected to the first load terminal and a channel region of a second conductivity type and separating the source region and the drift region, wherein, in the at least one active mesa, at least a respective section of each of the source region, the channel region and the drift region are arranged adjacent to a sidewall of the at least one control trench, and wherein the control trench electrode is configured to receive a control signal from a control terminal of the power semiconductor transistor and to control the load current in the at least one active mesa;
a semiconductor barrier region of the second conductivity type formed in the semiconductor body and overlapping with at least 50% of a first width of the at least one active mesa and with a bottom of the at least one further trench,
wherein the at least one active mesa has the first width at the channel region and a second width at an opening portion of the at least one active mesa, the second width being smaller than 75% of the first width,
wherein a p-n junction between the channel region and the drift region is disposed in an upper region of the at least one active mesa which has the first width,
wherein the semiconductor barrier region comprises one or more openings, wherein one or more sections of the drift region extend through the one or more openings, and wherein the one or more openings laterally overlap with the at least one active mesa.


US Pat. No. 11,114,527

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Renesas Electronics Corpo...


1. A semiconductor device comprising:a semiconductor substrate;
a semiconductor layer formed on the semiconductor substrate and including an active region, the active region including:a source region; and
a drain region formed away from the source region with a channel length;

a first device isolation portion formed in the semiconductor layer, the first device isolation portion surrounding the active region of the semiconductor layer in a plan view;
a first terrace insulating film formed between the source region and the drain region, the first terrace insulating film being formed on the semiconductor layer;
a gate insulating film formed on the semiconductor layer;
a gate electrode formed on the gate insulating film, the gate electrode being partially formed on the first terrace insulating film;
a first buried layer of a second conductivity type different from a first conductivity type of the semiconductor substrate, the first buried layer formed in the semiconductor layer; and
a second buried layer of the first conductivity type formed on the first buried layer; and
a junction isolating part of the first conductivity type surrounding the first device isolation portion in the plan view, the junction isolating part reaching the second buried layer,
wherein a thickness of the first terrace insulating film is smaller than a thickness of the first device isolation portion,
wherein a cell pitch which is a distance between a center part of the source region and a center part of the drain region is shorter than 5 ?m in a channel length direction,
wherein, in the plan view, the source region, the drain region, the first device isolation portion, the gate electrode and the junction isolating part overlap with the first buried layer, and
wherein, in the plan view, the source region, the drain region, the first device isolation portion, and the gate electrode overlap with the second buried region.

US Pat. No. 11,114,526

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...


1. A semiconductor device, comprising:a semiconductor substrate of a first conductivity type having a first surface and a second surface opposite to the first surface;
an emitter region of the first conductivity type provided in the semiconductor substrate at the first surface;
a base region of a second conductivity type provided in the semiconductor substrate below and adjacent to the emitter region;
a gate electrode provided in the semiconductor substrate at the first surface and surrounding the emitter region and the base region;
a gate insulating film insulating the gate electrode;
a ballast resistance region of the second conductivity type provided in the semiconductor substrate at the first surface and surrounding the gate electrode;
a variation of lateral doping (VLD) region of the second conductivity type provided in the semiconductor substrate at the first surface and surrounding the ballast resistance region;
a semiconductor region of the second conductivity type provided in the ballast resistance region at the first surface, the semiconductor region having a concentration of a second conductivity type impurity higher than that of the ballast resistance region;
a first insulating film provided on a part of the first surface that surrounds the emitter region and corresponds to the ballast resistance region, the first insulating film having a hole at the top of the semiconductor region;
a first-conductivity-type surface semiconductor region provided in the semiconductor substrate at the first surface and surrounding the ballast resistance region, the first-conductivity-type surface semiconductor region having a concentration of a first conductivity type impurity higher than that of the semiconductor substrate; and
a stopper layer of the first conductivity type provided in the semiconductor substrate at the first surface and surrounding the first-conductivity-type surface semiconductor region, a thickness of the stopper layer being greater than a thickness of the first-conductivity-type surface semiconductor region;
a collector region of the first conductivity type provided in the semiconductor substrate at the second surface;
a first electrode provided on the first insulating film and electrically connected to the semiconductor region via the hole;
a second electrode electrically connected to the emitter region, and spaced apart from the first electrode; and
a third electrode electrically connected to the collector region, wherein
the VLD region comprises a plurality of sub-regions, the plurality of sub-regions including a first sub-region surrounding the ballast resistance region, a second sub-region adjacent to and surrounding the first sub-region, and a third sub-region adjacent to and surrounding the second sub-region, the third sub-region positioned at an outer edge of the VLD region, and
a width of the second sub-region in a first direction along the first surface is smaller than a width of the first sub-region in the first direction, and greater than a width of the third sub-region in the first direction.

US Pat. No. 11,114,525

OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT

OSRAM OLED GMBH, Regensb...


1. A method for producing an optoelectronic component, the method comprising:providing a semiconductor layer sequence having an active region for emitting radiation;
applying a dielectric layer to the semiconductor layer sequence;
applying a seed layer to the dielectric layer, wherein the seed layer comprises a first metal and a second metal, wherein the second metal is less noble than the first metal, wherein an amount of the second metal in the seed layer is between 0.5 wt % and 10 wt %, or a ratio of the first metal to the second metal in the seed layer is between 95:5 and 99:1; and
applying a solder layer comprising the first metal to the seed layer.

US Pat. No. 11,114,524

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device, comprising:a first electrode on a substrate;
a second electrode on the first electrode;
a first dielectric layer between the first electrode and the second electrode;
a third electrode on the second electrode;
a second dielectric layer between the second electrode and the third electrode;
a first contact plug penetrating the third electrode and contacting the first electrode; and
a buffer dielectric layer on a top surface of the third electrode,
wherein the first contact plug contacts the top surface of the third electrode and a side surface of the third electrode, the buffer dielectric layer does not cover a first portion of the top surface of the third electrode, and the first portion of the top surface of the third electrode is in contact with the first contact plug.

US Pat. No. 11,114,523

DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....


1. An electronic device comprising:a display panel comprising:a first panel region comprising:a first pixel;
a second pixel disposed in a same pixel row as the first pixel;
a third pixel disposed in a pixel row different from the pixel row of the first pixel and the second pixel; and
a fourth pixel disposed in a same pixel row as the third pixel; and

a second panel region having greater light transmittance than the first panel region; and
a third panel region having greater light transmittance than the first panel region, wherein the first pixel, the second pixel, the third pixel, and the fourth pixel are disposed outside the second panel region, and the third panel region, the first pixel opposite to the second pixel with respect to the second panel region and the third panel region, and the third pixel is opposite to the fourth pixel with respect to the second panel region and the third panel region; and

an optical film disposed on the display panel,
wherein the display panel comprises:a circuit element layer comprising a signal line;
pixel driving circuits configured to drive a corresponding pixel of the first pixel, the second pixel, the third pixel, and the fourth pixel; and
a display element layer disposed on the circuit element layer, the display element layer comprising a display element and a dummy display element,

wherein the circuit element layer comprises:a first region in which the signal line and the pixel driving circuits are disposed;
a second region corresponding to the second panel region and the third panel region, the signal line and the pixel driving circuits being disposed outside the second region;
a third region disposed along a periphery of the second region, the signal line being disposed in the third region; and
a dummy region disposed between the second panel region and the third panel region,

wherein the signal line comprises:a first scan line connected to the first pixel;
a second scan line connected to the second pixel;
a first reset line connected to the third pixel;
a second reset line connected to the fourth pixel; and
a connection line disposed in the third region and the dummy region, the connection line being electrically connected to the first scan line, the second scan line,

the first reset line, and the second reset line;
wherein the dummy display element is disposed in the dummy region, andlaminated structures of the display element and the dummy display element are different from each other.


US Pat. No. 11,114,522

DISPLAY DEVICE, MANUFACTURING METHOD OF DISPLAY DEVICE, AND EXPOSURE DEVICE

SHARP KABUSHIKI KAISHA, ...


1. A display device comprising:a plurality of picture elements,
wherein a first electrode is formed in each of the plurality of picture elements,
a second electrode opposite to the first electrode,
a light-emitting layer is formed between the first electrode and the second electrode,
a cover layer is formed such that an opening of the first electrode is formed,
a spacer is provided between two of the first electrodes, the spacer and the cover layer are formed of a same material through a same process,
wherein a width of the spacer is from 8 ?m to 12 ?m,
the spacer is formed with a height greater than a height of the cover layer, the spacer is provided in a display portion,
wherein the height of the cover layer is from 1 ?m to 3 ?m,
an outer edge portion of the spacer is spaced from an outer edge portion of the cover layer, and
wherein the outer edge portion of the cover layer and the outer edge portion of the spacer are formed at an interval of 2 ?m to 5 ?m.

US Pat. No. 11,114,521

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....


1. A display device comprisinga substrate;
a first insulating layer disposed on the substrate;
a second insulating layer disposed on the first insulating layer;
a third insulating layer disposed on the second insulating layer; and
a pixel disposed on the substrate and comprising:
a first transistor;
a second transistor electrically connected to the first transistor;
a third transistor electrically connected to the first transistor; and
a light-emitting diode element electrically connected to at least one of the first transistor and the third transistor,
wherein the first transistor includes a first semiconductor member and a first gate electrode,
wherein the first gate electrode is disposed between the first semiconductor member and the substrate,
wherein the second transistor includes a second semiconductor member and a second gate electrode,
wherein the second semiconductor member is disposed between the second gate electrode and the substrate, directly contacts the third insulating layer, and is spaced from the second insulating layer,
wherein an oxide semiconductor material of the second semiconductor member is identical to an oxide semiconductor material of the first semiconductor member,
wherein the third transistor includes a third semiconductor member and a third gate electrode, and
wherein the second insulating layer is disposed between the third gate electrode and the third insulating layer.

US Pat. No. 11,114,520

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....


1. A display device comprising:a display panel comprising a display area and a non-display area;
signal wires disposed in the display area;
connection wires disposed in the display area and electrically connected to the signal wires; and
touch electrodes disposed on the connection wires, wherein the connection wires comprise:diagonal portions extending in a diagonal direction; and first protrusion patterns protruding from the diagonal portions of the connection wires,

wherein parts of the first protrusion patterns overlap the touch electrodes.

US Pat. No. 11,114,519

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

LG Display Co., Ltd., Se...


9. An organic light-emitting display device comprising:an organic emission layer disposed on a substrate;
an upper electrode disposed on the organic emission layer;
a plurality of lower electrodes disposed below the upper electrode;
a plurality of lower insulation layers disposed between the plurality of lower electrodes and the substrate;
a trench located between the plurality of lower electrodes, in a plan view, in a lower insulation layer among the plurality of lower insulation layers;
an auxiliary line connected to one lower electrode of the plurality of lower electrodes and disposed below the one lower electrode;
an auxiliary cover line disposed to cover an upper surface and a side surface of the auxiliary line;
a connection line configured to interconnect other lower electrode of the plurality of lower electrodes and a thin-film transistor and disposed in the same layer as the auxiliary line; and
a connection cover line disposed on the connection line to cover an upper surface and a side surface of the connection line and spaced apart from the auxiliary cover line with the trench interposed therebetween,
wherein any one of the plurality of lower insulating layers is disposed on the auxiliary cover line to expose a side surface of the auxiliary cover line.

US Pat. No. 11,114,518

WIRING STRUCTURE, DISPLAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...


1. A wiring structure, comprising a plurality of hollowed pattern strings, each hollowed pattern string comprising a plurality of hollowed patterns arranged sequentially in a length extension direction of the wiring structure, each hollowed pattern comprising a hollowed region and a non-hollowed region,wherein the non-hollowed region of any hollowed pattern in a hollowed pattern string and the non-hollowed region of a further hollowed pattern string adjacent to the hollowed pattern string at least partially overlap in a direction perpendicular to an upper surface of the wiring structure, and hollowed regions of hollowed patterns in the plurality of hollowed pattern strings do not overlap each other.

US Pat. No. 11,114,517

ORGANIC EL DISPLAY APPARATUS AND METHOD OF MANUFACTURING ORGANIC EL DISPLAY APPARATUS

SAKAI DISPLAY PRODUCTS CO...


1. An organic electro luminescent (EL) display apparatus comprising:a substrate having a surface on which a drive circuit comprising a thin film transistor is formed,
a planarizing layer including a first inorganic insulating layer and an organic insulating layer to planarize the surface of the substrate by covering the drive circuit, and
an organic light emitting element, the organic light emitting element comprising a first electrode being formed on a surface of the planarizing layer and connected, via a contact formed in the planarizing layer, to the drive circuit, an organic light emitting layer being formed on the first electrode, and a second electrode being formed on the organic light emitting layer,
wherein a surface of the organic insulating layer is formed such that a planarity thereof is brought to be greater than or equal to 20 nm and less than or equal to 50 nm in arithmetic average roughness Ra, and
wherein the first electrode is formed on only a region of the surface of the planarizing layer, in which the contact is not formed, and the organic light emitting layer is formed on only the first electrode, and the first electrode and the organic light emitting layer have substantially the same degree of surface roughness as a surface roughness of the planarizing layer, thereby, even in a microscopically planar state, a surface of the organic light emitting layer having no unevenness.

US Pat. No. 11,114,516

DISPLAY DEVICE

Japan Display Inc., Toky...


1. A display deice comprising:a substrate having a display region and a peripheral region surrounding the display region;
a pixel over the display region;
a passivation film over the pixel, the passivation film including:a first layer containing an inorganic compound;
a second layer over the first layer, the second layer containing an organic compound; and
a third layer over the second layer, the third layer containing an inorganic compound;

a resin layer over the passivation film; and
a first dam over the peripheral region and surrounding the display region,
wherein the second layer is selectively arranged in a region surrounded by the first dam,
an edge of the first layer, an edge of the third layer, and an edge of the resin layer are aligned directly above the first dam, and
the resin layer does not continuously extend outside the edge of the first layer or the edge of the third layer.

US Pat. No. 11,114,515

ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...


1. An organic light-emitting diode (OLED) display panel, comprising:a substrate;
a pixel defining layer disposed on the substrate, wherein the pixel defining layer comprises a plurality of recessed regions and a plurality of grooves, wherein the recessed regions communicate with each other through the grooves, the recessed regions and the grooves form a mesh structure, the mesh structure defines a plurality of pixel regions, and widths of the recessed regions is greater than widths of the grooves, a depth of the grooves from the substrate is lower than a depth of the recessed regions from the substrate, such that a height difference between a bottom of the recessed regions and a bottom of the grooves is formed;
an organic light-emitting layer disposed on the pixel defining layer, wherein the organic light-emitting layer defines the grooves; and
an organic encapsulation layer disposed on the organic light-emitting layer;
wherein the widths and the depths of the grooves are configured, such that a plurality of organic encapsulation droplets are spread via capillary force, and the organic encapsulation droplets are used for manufacturing the organic encapsulation layer.

US Pat. No. 11,114,514

ORGANIC ELECTROLUMINESCENT DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

HEFEI BOE OPTOELECTRONICS...


1. An organic electroluminescent display panel, comprising:a pixel defining layer disposed on a substrate, the pixel defining layer comprising a plurality of openings and a bank surrounding each of the openings and defining a plurality of pixel areas, wherein:
the bank is composed of a hydrophilic material pattern layer and a conductive hydrophobic pattern layer which are stacked from bottom to top over the substrate;
the conductive hydrophobic pattern layer comprises a hydrophobic resin, a photosensitizer, and a conductive material,
the conductive material comprises at least one of carbon nanotubes and graphene, and the mass percentage content of the conductive material is 5% to 20% of the conductive hydrophobic pattern layer by mass.

US Pat. No. 11,114,513

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...


1. A display substrate comprising:a base substrate; and
a pixel defining layer on the base substrate,
wherein the pixel defining layer comprises a first defining layer and a second defining layer on the first defining layer,
wherein the first defining layer defines a plurality of lower openings,
wherein the second defining layer defines a plurality of upper openings corresponding to the plurality of lower openings,
wherein respective orthographic projections of respective bottom surfaces of ones of the plurality of the upper openings adjacent the first defining layer on the base substrate overlap respective orthographic projections of corresponding lower openings on the base substrate,
wherein the respective orthographic projections of the respective bottom surfaces of the ones of the plurality of upper openings have equal respective areas,
wherein the plurality of lower openings comprise a first lower opening, a second lower opening and a third lower opening, and of the display substrate comprise a first pixel, a second pixel and a third pixel,
wherein the first lower opening, the second lower opening and the third lower opening form a first cavity, a second cavity and a third cavity respectively together with a corresponding upper opening of the plurality of upper openings for accommodating respective light emitting structures of the first pixel, the second pixel and the third pixel, and
wherein an area of an orthographic projection of the third lower opening on the base substrate is different from an area of an orthographic projection of the first lower opening on the base substrate or an orthographic projection of the second lower opening on the base substrate,
wherein respective lower openings and respective upper openings of each of the first cavity, the second cavity and the third cavity define a step formed by a material of the first defining layer, and
wherein the respective lower openings transition to the respective upper openings via the step,
wherein the respective light emitting structures of the first pixel, the second pixel and the third pixel comprise respective hole injection layers,
wherein the respective hole injection layers cover an upper surface of the first defining layer within a corresponding first cavity, second cavity, or third cavity, and
wherein respective hole injection layers in the first cavity, the second cavity and the third cavity have a substantially equal thickness.

US Pat. No. 11,114,512

ORGANIC LIGHT EMITTING DIODE DISPLAY

LG Display Co., Ltd., Se...


1. An organic light emitting diode display comprising:a first substrate on which an organic light emitting diode having an anode, an organic compound layer, and a cathode is disposed;
a second substrate on which a power line supplied with a power voltage is disposed, the second substrate facing the first substrate;
an auxiliary electrode;
a barrier on the auxiliary electrode;
a bank layer covering an edge of the auxiliary electrode and a portion of the barrier, wherein the bank layer has a first opening exposing at least a portion of the anode and a second opening simultaneously exposing at least a portion of the auxiliary electrode and at least a portion of the barrier;
a protective layer on the cathode; and
a contact electrode disposed on the protective layer, one end of the contact electrode directly contacting the auxiliary electrode or the cathode; and
wherein the contact electrode and the power line directly contact each other,
wherein the cathode of the organic light emitting diode is on the barrier and the bank layer,
wherein one end of the cathode is configured to directly contact the auxiliary electrode.

US Pat. No. 11,114,511

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....


1. A display device comprising:a display panel comprising two pixels spaced apart from each other and a transmission area between the two pixels;
an input sensing section disposed on the display panel and comprising sensing electrodes and trace lines electrically connected to the sensing electrodes;
a metal layer on the display panel, the metal layer disposed between the two pixels and surrounding the transmission area, the metal layer does not overlap the two pixels the metal layer comprising a first hole located in the transmission area, the first hole having a first width; and
an optical functional section on the metal layer, the optical functional section comprising a second hole that overlaps the first hole, the second hole having a second width that is greater than the first width.

US Pat. No. 11,114,510

ORGANIC LIGHT-EMITTING DISPLAY DEVICE HAVING TOUCH SENSOR

LG DISPLAY CO., LTD., Se...


1. An organic light-emitting display device comprising:a light-emitting element disposed on a substrate;
an encapsulation unit disposed on the light-emitting element, the encapsulation unit including a first inorganic encapsulation film on the light-emitting element, a second inorganic encapsulation film on the first inorganic film, and an organic encapsulation film between the first inorganic encapsulation film and the second inorganic encapsulation film;
a touch insulating film disposed on the second inorganic encapsulation film of the encapsulation unit;
a touch sensor disposed on the touch insulating film;
a routing line connected to the touch sensor;
a touch pad connected to the routing line;
a plurality of connection electrodes disposed between the routing line and the substrate to connect the routing line and the touch pad to each other;
a crack prevention layer disposed on the plurality of connection electrodes, the crack prevention layer overlapping the plurality of connection electrodes; and
a trench penetrating the second inorganic encapsulation film and the touch insulating film to expose the crack prevention layer,
wherein the touch sensor comprises:first touch electrodes arranged on the touch insulating film in a first direction, the first touch electrodes being connected to each other via first bridges; and
second touch electrodes arranged on the touch insulating film in a second direction, the second touch electrodes being connected to each other via second bridges,

wherein the first and second bridges and the first and second touch electrodes are formed of a same material as each other in a same plane, and the first and second bridges and the first and second touch electrodes are disposed on the touch insulating film, and
wherein the touch insulating film is disposed on the second inorganic encapsulation film in a non-active area where the touch pad is disposed.

US Pat. No. 11,114,509

OLED DISPLAY DEVICE WITH FINGERPRINT ON DISPLAY


1. An organic light emitting diode (OLED) display device with fingerprint on display (FOD) comprising:an OLED display panel comprising:a substrate; and
a plurality of sub-pixels arranged in an array on the substrate; and

a fingerprint recognition module disposed under the OLED display panel;
wherein the substrate comprises an effective display area, the sub-pixels are located in the effective display area, a fingerprint recognition block is disposed in the effective display area, and the fingerprint recognition module is disposed corresponding to the fingerprint recognition block;
a number of thin film transistors (TFTs) in each of the sub-pixels located in the fingerprint recognition block is less than a number of TFTs in each of the sub-pixels outside the fingerprint recognition block,
wherein the substrate further comprises a frame area surrounding the effective display area, a first scan driving circuit and a second scan driving circuit are disposed in the frame area, the first scan driving circuit is configured to drive the sub-pixels in the fingerprint recognition block to emit light, and the second scan driving circuit is configured to drive the sub-pixels outside the fingerprint recognition block to emit light,
wherein each of the sub-pixels outside the fingerprint recognition block comprises a third TFT, a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a ninth TFT, a second storage capacitor and a second OLED;
a gate of the third TFT receives a first scan signal, a source of the third TFT is electrically connected to a second node, a drain of the third TFT is electrically connected to a third node;
a gate of the fourth TFT receives a second scan signal, a source of the fourth TFT is electrically connected to the second node, a drain of the fourth TFT is electrically connected to a source of the seventh TFT;
a gate of the fifth TFT receives a light emitting control signal, a source of the fifth TFT receives the power supply voltage, a drain of the fifth TFT is electrically connected to a source of the ninth TFT;
a gate of the sixth TFT receives the light emitting control signal, a source of the sixth TFT is electrically connected to the third node, a drain of the sixth TFT is electrically connected to an anode of the second OLED;
a gate of the seventh TFT receives a third scan signal, the source of the seventh TFT receives an initialization voltage, a drain of the seventh TFT is electrically connected to the anode of the second OLED;
a gate of the eighth TFT receives the first scan signal, a source of the eighth TFT receives the data signal, a drain of the eighth TFT is electrically connected to the source of the ninth TFT;
a gate of the ninth TFT is electrically connected to the second node, a drain of the ninth TFT is electrically connected to the third node;
a first terminal of the second storage capacitor is electrically connected to the second node, a second terminal of the second storage capacitor is electrically connected to the source of the fifth TFT;
a cathode of the second OLED is grounded;
the first scan signal, the second scan signal, the third scan signal and the light emitting control signal are all provided by the second scan driving circuit.

US Pat. No. 11,114,508

DISPLAY PANEL INCLUDING IMAGE POINTS ARRANGED IN RECTANGULAR GRID AND DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...


1. A display panel, comprising:first pixel units, second pixel units and third pixel units, disposed close to each other, representing a first color, a second color, and a third color respectively, wherein the first pixel units, each comprises six first sub-pixels dividing an anode on said first pixel unit;wherein the second pixel units, each comprises six second sub-pixels dividing an anode on said second pixel unit;
wherein the third pixel units, each comprises six third sub-pixels dividing an anode on said third pixel unit;
wherein all sub-pixels are insulated from each other;
wherein a main pixel comprises one of the first, one of the second, and one of the third sub-pixels; and

a display source image comprising a plurality of image points, arranged in a rectangular grid, wherein four of the plurality of image points form a smallest square in the grid;
wherein one of the plurality of image points is in one-to-one association with a center point of the main pixel, and said image point falls within 10% proximity of the associated center point of the main pixel, wherein the proximity is defined as:
L1/L2?10%,
wherein L1 is a distance between said image point and the center of the main pixel, and L2 is a distance between display positions of two closest image points.

US Pat. No. 11,114,507

PIXEL ARRANGEMENT, MANUFACTURING METHOD THEREOF, DISPLAY PANEL, DISPLAY DEVICE AND MASK

CHENGDU BOE OPTOELECTRONI...


1. A pixel arrangement, comprising:a plurality of first groups of sub-pixels arranged in a first direction, each of the plurality of first groups comprising a first plurality of first sub-pixels and a first plurality of third sub-pixels arranged alternately; and
a plurality of second groups of sub-pixels arranged in the first direction, each of the plurality of second groups comprising a second plurality of third sub-pixels and a first plurality of second sub-pixels arranged alternately,
wherein the plurality of first groups and the plurality of second groups are alternately arranged in a second direction perpendicular to the first direction, and
wherein the plurality of first groups and the plurality of second groups are arranged to form a plurality of third groups of sub-pixels arranged in the second direction and a plurality of fourth groups of sub-pixels arranged in the second direction,
wherein the plurality of third groups and the plurality of fourth groups are alternately arranged in the first direction, and
wherein each of the plurality of third groups comprises a second plurality of first sub-pixels and a third plurality of third sub-pixels arranged alternately, and each of the plurality of fourth groups comprises a fourth plurality of third sub-pixels and a second plurality of second sub-pixels arranged alternately,
wherein ones of the first plurality of third sub-pixels in each of the first groups different from ones of the second plurality of third sub-pixels in each of the second groups.

US Pat. No. 11,114,506

ORGANIC LIGHT EMITTING DISPLAY PANEL, DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

BOE Technology Group Co.,...


1. An organic light emitting display panel, comprising: a substrate, a reflecting layer, a blocking layer and a plurality of pixel units, wherein the reflecting layer is disposed on a substrate;the blocking layer is disposed on the reflecting layer, and the blocking layer comprises retaining walls configured to separate the plurality of pixel unit; and
each of the plurality of pixel units defined by retaining walls comprises a transparent conducting layer, a first electrode, a light emitting layer and a second electrode arranged in that order on a side of the reflecting layer facing away from the substrate, wherein the second electrode is semi-transparent and semi-reflective;
wherein light emitted by each of the plurality of pixel units is transmitted between the reflecting layer and the second electrode in such a way that light propagation satisfies the strong microcavity effect, and in a direction vertical to the substrate, thicknesses of transparent conducting layers in the plurality of pixel units with different emitting colors are different.

US Pat. No. 11,114,505

IMAGING DEVICE

PANASONIC INTELLECTUAL PR...


1. An imaging device comprising:a semiconductor substrate including a pixel region in which pixels are arranged and a peripheral region adjacent to the pixel region;
an insulating layer that covers the pixel region and the peripheral region;
first electrodes located on the insulating layer above the pixel region and arranged two-dimensionally in a column direction and a row direction;
a photoelectric conversion layer that covers the first electrodes;
a second electrode that covers the photoelectric conversion layer;
detection circuitry located in the pixel region and configured to be electrically connected to the first electrodes;
peripheral circuitry located in the peripheral region, configured to be electrically connected to the detection circuitry, and including analog circuitry and digital circuitry; and
a third electrode located on the insulating layer above the peripheral region, wherein
the second electrode extends above the peripheral region,
the second electrode includes a connection region in which the second electrode is connected to third electrode,
the connection region overlaps the analog circuitry in a plan view, and
in all cross-sections perpendicular to a surface of the semiconductor substrate, parallel to the column direction or the row direction, intersecting at least one of the first electrodes, and intersecting the connection region, no transistor of the digital circuitry is located directly below the connection region.

US Pat. No. 11,114,504

SEMICONDUCTOR DEVICE INCLUDING VARIABLE RESISTANCE LAYER

SK hynix Inc., Icheon-si...


1. A semiconductor device comprising:a substrate;
a gate structure disposed on the substrate, the gate structure comprising at least one gate electrode layer and at least one interlayer insulation layer that are alternately stacked;
a hole pattern penetrating the gate structure on substrate; and
a first variable resistance layer, a second variable resistance layer, and a channel layer sequentially disposed on a sidewall surface of the gate electrode layer in the hole pattern,
wherein the first and second variable resistance layers comprise ions exchangeable with each other.

US Pat. No. 11,114,503

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...


1. A memory device, comprising:a first electrically conductive portion;
a second electrically conductive portion, a direction from the first electrically conductive portion toward the second electrically conductive portion being aligned with a first direction;
a first variable resistance portion provided between the first electrically conductive portion and the second electrically conductive portion; and
a first region, a second direction from the first variable resistance portion toward the first region crossing the first direction,
the first region includinga first layer portion, and
a second layer portion provided between the first layer portion and the first variable resistance portion in the second direction,

a first distance along the second direction between the first layer portion and the second layer portion being longer than at least one of a first lattice length or a second lattice length, the first lattice length being a lattice length of the first layer portion along a first axis direction crossing the second direction, the second lattice length being a lattice length of the second layer portion along a second axis direction crossing the second direction.

US Pat. No. 11,114,502

RESISTIVE MEMORY CELL HAVING AN OVONIC THRESHOLD SWITCH

STMICROELECTRONICS (ROUSS...


1. A resistive memory cell, comprising:a phase change layer of phase-change material;
a resistive element in contact with the phase change material; and
an ovonic threshold switch having no physical contact with the phase-change material, the resistive element being positioned between the ovonic threshold switch and the phase change layer.

US Pat. No. 11,114,501

SOI SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING AN SOI SEMICONDUCTOR STRUCTURE

TDK-Micronas GmbH, Freib...


1. An SOI semiconductor structure comprising:a second semiconductor wafer formed as a substrate layer on a back side and a semiconductor layer formed on a front side of a first semiconductor wafer;
an insulating layer disposed between the substrate layer and the semiconductor layer;
a three-dimensional Hall sensor structure having a sensor region made up of a monolithic semiconductor body and having an integrated circuit formed in the semiconductor layer, he semiconductor body having a second conductivity type and extends from a buried lower surface towards the front side;
at least three first metallic terminal contacts spaced a distance apart, being formed on the front side;
at least three second terminal contacts spaced a distance apart, being formed on the lower surface, each of the at least three second terminal contacts comprising a highly doped polysilicon of a second conductivity type or a metal;
wherein, each of the at least three first terminal contacts and each of the at least three second terminal contacts being formed on a highly doped semiconductor contact region of a second conductivity type,
wherein at least a portion of the at least three first terminal contacts being formed on the highly doped connecting regions being offset with respect to at least a portion of the at least three second terminal contacts formed on the highly doped connecting region in a projection substantially perpendicular to the front side,
wherein the at least three first terminal contacts and the at least three second terminal contacts each have a multiple rotational symmetry with respect to an axis of symmetry viewed perpendicularly on the front side and on the lower surface of the semiconductor body, and
wherein the lower surface of the semiconductor body being formed on the insulating layer.

US Pat. No. 11,114,500

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....


1. A display device comprising:a substrate comprising a display area having a plurality of pixel areas and a non-display area located around the display area;
a circuit element layer comprising a circuit element in each of the pixel areas and a reference voltage wiring in the non-display area, the reference voltage wiring being electrically coupled to the circuit element; and
a display element layer comprising a first pixel electrode on the circuit element layer in each of the pixel areas, a second pixel electrode located opposite to the first pixel electrode, a plurality of light emitting elements between the first pixel electrode and the second pixel electrode, and a first wiring on the circuit element layer in the non-display area,
wherein the first wiring is directly coupled to the reference voltage wiring in the non-display area,
wherein the first wiring comprises:
a body portion that extends in a first direction; and
a protruding portion that protrudes from the body portion in a second direction intersecting the first direction, and
wherein the protruding portion overlaps the reference voltage wiring, and the first wiring is coupled to the reference voltage wiring by the protruding portion.

US Pat. No. 11,114,499

DISPLAY DEVICE HAVING LIGHT EMITTING STACKED STRUCTURE

SEOUL VIOSYS CO., LTD.


1. A display device comprising:a plurality of pixel tiles spaced apart from each other, each of the pixel tiles including:
a substrate; and
a plurality of light emitting stacked structures disposed on the substrate, each of the light emitting stacked structures comprising a plurality of epitaxial sub-units sequentially disposed one over another to have overlapping light emitting areas, and each of the plurality of epitaxial sub-units being configured to emit different colored light,
wherein a distance between two adjacent light emitting stacked structures in the same pixel tile is substantially equal to a shortest distance between two adjacent light emitting stacked structures of different pixel tiles.

US Pat. No. 11,114,498

IMAGE SENSOR AND IMAGING APPARATUS

SONY CORPORATION, Tokyo ...


1. A light detecting device, comprising:a pixel configured to output a pixel signal, wherein the pixel includes:a photoelectric conversion region;
a floating diffusion region coupled to the photoelectric conversion region; and
a select transistor;

a vertical signal line coupled to one of a source of the select transistor or a drain of the select transistor;
switch circuitry that includes a first switch coupled to a gate of the select transistor; and
a negative voltage power source coupled to the switch circuitry, whereinthe negative voltage power source is configured to generate a negative potential, and
the gate of the select transistor is configured to selectively couple to one of the negative potential or a power potential via the first switch.


US Pat. No. 11,114,497

SENSOR, ARRAY SUBSTRATE CONTAINING SENSOR, DISPLAY PANEL CONTAINING ARRAY SUBSTRATE

BOE TECHNOLOGY GROUP CO.,...


1. A sensor, comprising:a base substrate;
a voltage dividing photodiode on the base substrate;
a detecting photodiode on the base substrate;
a first power terminal; and
a second power terminal,
wherein:
the voltage dividing photodiode comprises a first electrode, a first P-type semiconductor layer, a first I-type semiconductor layer, a first N-type semiconductor layer, and a second electrode arranged in a stack,
the detecting photodiode comprises a third electrode, a second P-type semiconductor layer, a second I-type semiconductor layer, a second N-type semiconductor layer, and a fourth electrode arranged in a stack,
the second power terminal comprises at least one metal layer,
the first electrode is electrically connected to the first power terminal,
the second electrode and the third electrode form a unitary structure,
the fourth electrode is electrically connected to the second power terminal,
the detecting photodiode is configured to operate with a reverse bias applied by the first power terminal and the second power terminal, so as to detect a light intensity, and
the unitary structure formed by the second electrode and the third electrode is opaque and covers an entirety of the first electrode, the first P-type semiconductor layer, the first I-type semiconductor layer, and the first N-type semiconductor layer of the voltage dividing photodiode, so that the voltage dividing photodiode is configured to operate substantially permanently in a dark state.

US Pat. No. 11,114,496

ACTIVE MATRIX SUBSTRATE, X-RAY IMAGING PANEL WITH THE SAME, AND METHOD FOR PRODUCING THE SAME

SHARP KABUSHIKI KAISHA, ...


1. An active matrix substrate comprising:a photoelectric conversion element;
an electrode provided with a first opening, the electrode being disposed on one surface of the photoelectric conversion element;
an organic insulating film provided with a second opening, the organic insulating film covering the photoelectric conversion element and the electrode; and
a conductive film for supplying a bias voltage to the electrode,
wherein the first opening and the second opening overlap each other when viewed in plan view, and
the conductive film is provided inside the first opening and the second opening so as to be in contact with the electrode.

US Pat. No. 11,114,495

ARRAY SUBSTRATE AND METHOD FOR MANUFACTURING AN ARRAY SUNSTRATE

HKC CORPORATION LIMITED, ...


1. An array substrate, comprising:a substrate;
a switch assembly disposed on the substrate;
a plurality of photosensors;
a color photoresist layer; and
a pixel electrode formed on the color photoresist layer and coupled with the switch assembly;
wherein the photosensor is correspondingly disposed on a side of the switch assembly; the color photoresist layer is formed on the switch assembly and the photosensor; the switch assembly comprises a first metal layer; the photosensor comprises a first electrode layer formed directly on the substrate and a first amorphous silicon layer disposed above the first electrode layer; the first electrode layer and the first metal layer are disposed on a same layer.

US Pat. No. 11,114,494

IMAGE SENSOR BASED ON AVALANCHE PHOTODIODES

SHENZHEN XPECTVISION TECH...


1. An apparatus comprising:an array of avalanche photodiodes (APDs), each of the APDs comprising an absorption region and an amplification region;
wherein the absorption region is configured to generate charge carriers from a photon absorbed by the absorption region;
wherein the absorption region comprises a silicon epitaxial layer;
wherein the amplification region comprises a junction with an electric field in the junction;
wherein the electric field is at a value sufficient to cause an avalanche of charge carriers entering the amplification region, but not sufficient to make the avalanche self-sustaining;
wherein the junctions of the APDs are discrete.

US Pat. No. 11,114,493

IMAGE SENSORS WITH VERTICALLY STACKED PHOTODIODES AND VERTICAL TRANSFER GATES

SEMICONDUCTOR COMPONENTS ...


1. An image sensor comprising:a first layer of a first doping type;
a second layer of a second doping type different from the first doping type, wherein the second layer is formed adjacent to the first layer;
a floating diffusion region of the first doping type that is formed in the second layer; and
a transfer gate comprising conductive gate material and a region of the second doping type around the conductive gate material, wherein the region of the second doping type is in contact with the first layer and the second layer and wherein the conductive gate material extends vertically between a front surface of the image sensor and a back surface of the image sensor; and
a residual substrate at the back surface, wherein the transfer gate extends at least partially into the residual substrate.

US Pat. No. 11,114,492

IMAGE SENSOR

SK hynix Inc., Icheon-si...


1. An image sensor comprising:a photoelectric conversion element structured to receive incident light and convert the received light into electric charges;
a monochromatic color separation element overlapping with the photoelectric conversion element;
a plurality of light focusing elements formed over the color separation element;
a plurality of transfer transistors electrically coupled to the photoelectric conversion element to respond to a transfer signal to selectively transfer the electric charges out of the photoelectric conversion element; and
a lag prevention structure formed at a center of the photoelectric conversion element and structured to receive the transfer signal to operate together with the plurality of transfer transistors to facilitate transfer the electric charges out of the photoelectric conversion element,
wherein the lag prevention structure includes an impurity region and an ohmic contact layer, and
wherein the impurity region is formed in the photoelectric conversion element, and the ohmic contact layer is formed over the impurity region, and
wherein the number of the plurality of light focusing elements is the same as the number of the plurality of transfer transistors.

US Pat. No. 11,114,491

BACK-ILLUMINATED SENSOR AND A METHOD OF MANUFACTURING A SENSOR

KLA Corporation, Milpita...


1. A method of fabricating an image sensor, the method comprising:forming a first epitaxial layer on a substrate;
forming a circuit element on a first surface of the first epitaxial layer;
thinning the substrate to generate a thinned substrate, the thinned substrate exposing at least a surface portion of a second surface of the first epitaxial layer, said second surface being opposed to the first surface on which said circuit element is disposed;
forming a second epitaxial layer on the exposed portion of the first epitaxial layer; and
forming a pure boron layer on the second epitaxial layer,
wherein forming the second epitaxial layer includes generating a p-type dopant concentration gradient in the second epitaxial layer by gradually increasing a concentration of a p-type dopant used during formation of the second epitaxial layer such that a first layer portion of the second epitaxial layer has a lower p-type dopant concentration than a subsequently formed second layer portion of the second epitaxial layer, and a highest p-type dopant concentration of the second epitaxial layer is adjacent to the pure boron layer.

US Pat. No. 11,114,490

LIGHT RECEIVING ELEMENT, RANGING MODULE, AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...


1. A light receiving element comprising:an on-chip lens;
a wiring layer; and
a semiconductor layer disposed between the on-chip lens and the wiring layer,
wherein the semiconductor layer includes:a photodiode;
a first transfer transistor that transfers electric charge from the photodiode to a first charge storage portion;
a second transfer transistor that transfers electric charge from the photodiode to a second charge storage portion; and
an interpixel separation portion that separates the semiconductor layer from semiconductor layers of adjacent pixels, for at least part of the semiconductor layer in a depth direction,

wherein the wiring layer has at least one layer including a light blocking member, and
wherein the light blocking member is disposed to overlap with the photodiode in a plan view.

US Pat. No. 11,114,489

BACK-ILLUMINATED SENSOR AND A METHOD OF MANUFACTURING A SENSOR

KLA-Tencor Corporation, ...


1. An image sensor for sensing at least one of deep ultraviolet (DUV) radiation, vacuum ultraviolet (VUV) radiation, extreme ultraviolet (EUV) radiation and charged particles, the image sensor comprising:a semiconductor membrane including circuit elements formed on a first surface of the semiconductor membrane and first metal interconnects formed over the circuit elements;
a pure boron layer formed on a second surface of the semiconductor membrane; and
a protection layer formed over the circuit elements such that the first metal interconnects are entirely disposed between the semiconductor membrane and said protection layer,
wherein the semiconductor membrane includes a boron-doped region extending from second surface into the semiconductor membrane such that the boron-doped region is disposed immediately adjacent to the pure boron layer,
wherein the first metal interconnects comprise a refractory metal,
wherein the protection layer comprises one or more of monocrystalline silicon and glass.

US Pat. No. 11,114,488

IMAGE SENSING DEVICES WITH REFLECTOR ARRAYS

Shenzhen Adaps Photonics ...


1. An image sensor module comprising:a control circuit;
a SPAD pixel array configured to generate imaging data based on detected photons, the SPAD pixel array comprising a first pixel and a second pixel, the first pixel comprising a first isolation structure and a second isolation structure, the second pixel comprising the second isolation structure and a third isolation structure, the first pixel comprising an oxide region and an absorption region overlaying the oxide region, the oxide region comprising a first reflector array and a second reflector array, the first reflector array being positioned between the absorption region and the second reflector array; and
a memory for storing the imaging data.

US Pat. No. 11,114,487

PHOTOELECTRIC CONVERSION APPARATUS AND IMAGING SYSTEM USING THE SAME

CANON KABUSHIKI KAISHA, ...


1. A photoelectric conversion apparatus comprising:a first photoelectric conversion portion including a first semiconductor region of a first conductive type;
a second photoelectric conversion portion including a second semiconductor region of the first conductive type;
a first region where a first storage portion configured to hold a signal based on a charge generated by the first photoelectric conversion portion is arranged;
a second region where a second storage portion configured to hold a signal based on a charge generated by the second photoelectric conversion portion is arranged;
a first floating diffusion portion arranged at different location from the first storage portion and configured to hold a signal based on a charge generated by the first photoelectric conversion portion;
a first electrode arranged in the first region in a plan view;
a second electrode arranged in the second region in the plan view; and
a first transistor connected to the first floating diffusion portion, the first transistor being one of a reset transistor, an amplification transistor, and a selection transistor,
wherein a first element isolation portion using an insulator is arranged between the first transistor and the first photoelectric conversion portion, and
wherein the first electrode and the second electrode are arranged on a same active region.

US Pat. No. 11,114,486

IMPLANT ISOLATED DEVICES AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...


1. A device comprising:a semiconductor substrate having an active region;
an implant isolation region surrounding the active region and extending from a top surface of the semiconductor substrate into the semiconductor substrate;
a gate dielectric layer overlying the active region and at least partially overlying the implant isolation region;
a gate electrode layer over a portion of the gate dielectric layer;
an end cap dielectric layer overlying the gate dielectric layer and overlying the implant isolation region, the end cap dielectric layer forming a first end cap dielectric structure and a second end cap dielectric structure; and
a second gate electrode layer on the gate electrode layer, the second gate electrode layer extending a least partially over the first end cap dielectric structure and the second end cap dielectric structure, the gate electrode layer and second gate electrode layer together forming a gate electrode.

US Pat. No. 11,114,485

METAL MIRROR BASED MULTISPECTRAL FILTER ARRAY

VIAVI Solutions Inc., Sa...


1. A method comprising:providing a substrate that includes a set of sensor elements;
depositing multiple layers of a multispectral filter array onto the substrate,wherein the multiple layers include:a first spacer layer disposed over all sensor elements in the set of sensor elements,
a second spacer layer disposed over less than all sensor elements in the set of sensor elements, and
a metal mirror,


depositing one or more other layers associated with the multispectral filter array onto the multiple layers; and
attaching a lens that alters a characteristic of light that is directed toward a corresponding sensor element of the sensor elements.

US Pat. No. 11,114,484

PHOTOELECTRIC CONVERSION APPARATUS, PHOTOELECTRIC CONVERSION SYSTEM, MOVING BODY, AND MANUFACTURING METHOD FOR PHOTOELECTRIC CONVERSION APPARATUS

CANON KABUSHIKI KAISHA, ...


1. A photoelectric conversion apparatus comprising:a semiconductor substrate having a first surface on which light is incident and a second surface facing the first surface, and having one or a plurality of photoelectric conversion units performing photoelectric conversion on the incident light and accumulating first electric charges of a first polarity, one or a plurality of first transistors having a first gate formed on the second surface, and one or a plurality of second transistors having a second gate formed on the second surface, the second gate having a gate length shorter than a gate length of the first gate;
a first fixed charge film continuously provided on the first surface directly or with an insulating film in between in an area overlapping the one or a plurality of photoelectric conversion units, the one or a plurality of first transistors, and the one or a plurality of second transistors in a plan view viewed from a direction perpendicular to the first surface of the semiconductor substrate, the first fixed charge film having fixed charges of the first polarity; and
a second fixed charge film provided on a side of the first fixed charge film opposite to a side of the semiconductor substrate provided directly or with an insulating film in between in an area overlapping the one or a plurality of second transistors and the first fixed charge film in the plan view, the second fixed charge film having fixed charges of a second polarity,
wherein, at a position overlapping with the one or the plurality of photoelectric conversion portions in the plan view, the second fixed charge film is not provided or a thickness of the second fixed charge film is less than a thickness of the first fixed charge film.

US Pat. No. 11,114,483

CAVITYLESS CHIP-SCALE IMAGE-SENSOR PACKAGE

OmniVision Technologies, ...


1. A cavityless chip-scale image-sensor package comprising:a substrate that includes a plurality of pixels forming a pixel array;
a microlens array that includes a plurality of microlenses each (i) having a lens refractive index, (ii) being aligned to a respective one of the plurality of pixels, and (iii) having a non-planar microlens surface facing away from the respective one of the plurality of pixels;
a low-index layer formed of either nanoporous silicon dioxide or nanoporous aluminum oxyhydroxide, and having (i) a first refractive index less than the lens refractive index, (ii) a bottom surface, at least part of which is conformal to each non-planar microlens surface, and (iii) a non-planar top surface that is conformal to the bottom surface and opposite the bottom surface, the microlens array being between the pixel array and the low-index layer; and
a bonding layer adjoining the low-index layer such that the low-index layer is between the microlens array and the bonding layer; and
a cover glass disposed on the bonding layer opposite the low-index layer,
the bonding layer and the cover glass having a second refractive index and a third refractive index respectively, each exceeding the first refractive index.

US Pat. No. 11,114,482

SCALABLE-PIXEL-SIZE IMAGE SENSOR

Gigajot Technology, Inc.,...


1. An integrated-circuit pixel comprising:four sets of photodetection elements, each of the sets disposed in a respective one of four sub-pixel quadrants defined by first and second orthogonal axes that traverse the integrated-circuit pixel;
four readout circuits each coupled to a respective one of the four sets of photodetection elements, each of the readout circuits having:a floating diffusion node;
a first transfer gate coupled between the floating diffusion node and a constituent photodetection element of the respective one of the four sets of photodetection elements; and
an amplifier transistor having a gate terminal coupled to the floating diffusion node;

a shared reset node;
a reset transistor coupled between the shared reset node and a reset-voltage supply; and
a plurality of binning transistors each coupled between the shared reset node and the floating diffusion node of a respective one of the readout circuits.

US Pat. No. 11,114,481

CAPACITOR INCLUDING FIRST ELECTRODE, DIELECTRIC LAYER, AND SECOND ELECTRODE, IMAGE SENSOR, AND METHOD FOR PRODUCING CAPACITOR

PANASONIC INTELLECTUAL PR...


1. A capacitor comprising:a first electrode;
a second electrode facing the first electrode; and
a dielectric layer disposed between the first and second electrodes and being in contact with each of the first and second electrodes, wherein:
the dielectric layer has a thickness of 16 nm or more,
the first electrode contains carbon,
the dielectric layer contains carbon, and
in a middle portion of the first electrode between an uppermost surface of the first electrode facing the dielectric layer and a lowermost surface of the first electrode opposed to the uppermost surface, an elemental percentage of carbon is 30 atomic % or less.

US Pat. No. 11,114,480

PHOTODETECTOR

ACTLIGHT SA, Lausanne (C...


1. A photodetector device comprising:first and second light absorbing regions composed of semiconductor material, doped respectively n-type and p-type, wherein the first and second light absorbing regions are formed as respective epitaxial layers arranged on top of one another in relation to a substrate, wherein the light absorbing regions are configured to generate pairs of electrons and holes in response to absorption of photons when light is incident on the device;
first and second contact regions composed of semiconductor material and doped respectively p-type and n-type, wherein the contact regions have higher doping concentrations than the light absorbing regions, and are labelled as p+ and n+ respectively; and
first and second contacts connected to the first and second contact regions respectively,
wherein the n-type and p-type light absorbing regions and the n+ and p+ contact regions are arranged in a sequence n+p n p+ so that, after a voltage applied between the n+ and p+ contacts is switched from a reverse bias to a forward bias, electrons and holes which are generated in the light absorbing regions in response to photon absorption drift towards the p+ and n+ contact regions respectively, which causes current to start to flow between the contacts after a time delay which is inversely proportional to the incident light intensity.

US Pat. No. 11,114,479

OPTOELECTRONICS AND CMOS INTEGRATION ON GOI SUBSTRATE

International Business Ma...


1. A structure comprising:a germanium layer above a semiconductor substrate in a first region of the semiconductor substrate;
an optoelectronic device on the germanium layer in the first region, the optoelectronic device has a bottom cladding layer, an active region adjacent to and contacting a waveguide, and a top cladding layer, wherein the bottom cladding layer is on the germanium layer, the active region is on the bottom cladding layer, and the top cladding layer is on the active region; and
a silicon device on a silicon layer in a second region of the semiconductor substrate,
wherein an upper surface of the silicon layer in the second region is above an upper surface of the germanium layer in the first region.

US Pat. No. 11,114,478

THIN FILM TRANSISTOR AND MANUFACTURE METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURE METHOD THEREOF

Hefei Xinsheng Optoelectr...


1. A manufacture method of a thin film transistor, comprising:providing a base substrate; and
forming a gate electrode, a first electrode, a second electrode, and a semiconductor layer of the thin film transistor on the base substrate, wherein at least one of a group consisting of the gate electrode, the first electrode, and the second electrode comprises N portions that are stacked in a direction perpendicular to the base substrate, adjacent two portions of the N portions are in direct contact with each other, and N is a positive integer more than or equal to 2,
wherein the method comprises: performing N patterning processes to respectively form the N portions;
wherein the gate electrode comprises N1 portions that are stacked in the direction perpendicular to the base substrate, the first electrode comprises N2 portions that are stacked in the direction perpendicular to the base substrate, and the second electrode comprises N3 portions that are stacked in the direction perpendicular to the base substrate; N1, N2, and N3 are all positive integers more than or equal to 2;
in a direction from a position close to the base substrate to a position away from the base substrate, the N1 portions are sequentially a first portion, a second portion . . . , and a N1-th portion, the N2 portions are sequentially a first portion, a second portion . . . , and a N2-th portion, and the N3 portions are sequentially a first portion, a second portion . . . , and a N3-th portion; and
a M1-th portion of the gate electrode, a M2-th portion of the first electrode, and a M3-th portion of the second electrode are simultaneously formed by one patterning process using a same mask, wherein M1 is a positive integer less than or equal to N1, M2 is a positive integer less than or equal to N2, and M3 is a positive integer less than or equal to N3.

US Pat. No. 11,114,477

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...


1. A method for manufacturing an array substrate, comprising:forming a buffer layer on a substrate, the substrate comprising a display region and a non-display region;
forming a first photoresist pattern on the buffer layer of the non-display region and removing a part of the buffer layer to form a first via hole in the non-display region;
forming an insulating layer on the buffer layer of the non-display region and the first via hole; and
forming a second photoresist pattern on the insulating layer of the non-display region and removing a part of the insulating layer to form a second via hole in the non-display region, the second photoresist pattern corresponding to the first via hole and the second via hole connected to the first via hole,
wherein the insulating layer at least partially covers the first via hole and a cross-sectional area of the second via hole is less than or equal to a cross-sectional area of the first via hole, and
wherein a thickness of the first via hole is between 0.7 micrometer and 0.9 micrometer and a thickness of the second via hole is between 0.6 micrometer and 0.8 micrometer.

US Pat. No. 11,114,476

MANUFACTURING METHOD OF TFT ARRAY SUBSTRATE, TFT ARRAY SUBSTRATE AND DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...


1. A manufacturing method of a TFT array substrate comprises:providing a rigid substrate, depositing a first metal layer on the rigid substrate, and patterning the first metal layer to form a gate electrode and a gate scanning line;
depositing sequentially a gate insulating layer, an active layer and a second metal layer on the gate and the gate scanning line;
coating photoresist on the second metal layer and patterning the photoresist to form a first photoresist layer and a second photoresist layer; wherein the first photoresist layer comprises a first-stage photoresist layer, a second-stage photoresist layer and a third-stage photoresist layer; the thickness of the second-stage photoresist layer is larger than that of the first-stage photoresist layer, and the thickness of the third-stage photoresist layer is larger than that of the second-stage photoresist layer;
the first-stage photoresist layer is disposed in the middle of the first photoresist layer and a channel is formed; and the thickness of the second photoresist layer is larger than that of the second-stage photoresist layer;
etching a region of the second metal layer, a region of the active layer and a region of the gate insulating layer, which are outside the channel and uncovered by the first photoresist layer and the second photoresist layer to expose the rigid substrate;
performing ashing treatment on the first photoresist layer and the second photoresist layer to remove the first-stage photoresist layer, and forming a source electrode, and a drain electrode by etching;
performing ashing treatment on the second-stage photoresist layer, the third-stage photoresist layer and the second photoresist layer to remove the second-stage photoresist layer, and then depositing a passivation layer as a whole;
stripping the third-stage photoresist layer and the second photoresist layer, and depositing a transparent conductive layer and patterning the transparent conductive layer to form a pixel electrode and a common electrode.

US Pat. No. 11,114,475

IPS THIN-FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...


1. A method for manufacturing an in-plane switching (IPS) thin-film transistor (TFT) array substrate, comprising the following steps:S1: providing a backing plate and forming a gate electrode, a scan line, a pixel electrode, and a common electrode on the backing plate with a first mask-involved operation, wherein the scan line and the gate electrode are connected to each other;
S2: depositing a gate insulation layer on the gate electrode, the scan line, the pixel electrode, the common electrode, and the backing plate, depositing a semiconductor layer on the gate insulation layer, and subjecting the gate insulation layer and the semiconductor layer to patterning treatment with a second mask-involved operation to form a first through hole and a second through hole in the gate insulation layer and an active layer located above and corresponding to the gate electrode, wherein the first through hole and the second through hole are respectively corresponding to and located above the pixel electrode and the common electrode; and
S3: depositing a source-drain metal layer on the active layer and the gate insulation layer and subjecting the source-drain metal layer to patterning treatment with a third mask-involved operation so as to form a source electrode, a drain electrode, a data line, and a common electrode line, wherein the source electrode and the drain electrode are respectively in contact engagement with two sides of the active layer; the data line and the source electrode are connected to each other; the drain electrode is connected through the first through hole of the gate insulation layer to the pixel electrode; and the common electrode line is connected through the second through hole of the gate insulation layer to the common electrode;
wherein Step S1 comprises:
S11: depositing a first metal layer on the backing plate with physical vapor deposition;
S12: subjecting the first metal layer to patterning treatment with the first mask-involved operation to form a predetermined gate electrode pattern and a predetermined scan line pattern, and the pixel electrode and the common electrode; and
S13: carrying out an operation of coating a second metal layer on the predetermined gate electrode pattern and the predetermined scan line pattern to form the gate electrode and the scan line, wherein the second metal layer has electrical conductance greater than electrical conductance of the first metal layer; and
wherein the first metal layer is subjected to the patterning treatment of Step S12 to form a first metal pattern that includes a first part and a second part different from the first part, the first part including the predetermined gate electrode pattern and the predetermined scan line pattern, the second part including the pixel electrode and the common electrode, wherein the operation of coating is carried out after the formation of the first metal pattern such that the second metal layer is coated on the first part of the first metal pattern to cover the first part of the first metal pattern, while the second part of the first metal pattern does not include the second metal layer coated thereon and is completely exposed outside from the second metal layer.

US Pat. No. 11,114,474

THIN FILM TRANSISTOR, MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...


1. A manufacturing method of a thin film transistor (TFT), comprising:providing a base substrate;
forming a first electrode, an isolating layer, an active layer and a gate insulating layer on the base substrate;
simultaneously forming a second electrode and a gate electrode,
wherein the second electrode is connected to the active layer.

US Pat. No. 11,114,473

METHOD FOR TRANSFERRING LIGHT EMITTING ELEMENTS, DISPLAY PANEL, METHOD FOR MAKING DISPLAY PANEL, AND SUBSTRATE

Century Technology (Shenz...


1. A method for transferring light emitting elements, comprising:providing a plurality of light emitting elements, wherein a first magnetic material layer is on an end of each of the plurality of light emitting elements;
providing a first electromagnetic plate, wherein the first electromagnetic plate defines a plurality of adsorption positions, each of the plurality of adsorption positions is capable of magnetically attracting one light emitting element on being energized;
providing a receiving substrate, wherein providing the receiving substrate comprises providing a base layer, forming a second magnetic material layer on a side of the base layer, and forming a bonding layer on a side of the second magnetic material layer away from the base layer, wherein the bonding layer defines a plurality of receiving areas, each of the plurality of receiving areas is configured for receiving one of the plurality of light emitting elements;
energizing the first electromagnetic plate to magnetically adsorb one of the plurality of light emitting elements at each of the plurality of adsorption positions, wherein a surface of the first electromagnetic plate on which the plurality of light emitting elements are magnetically adsorbed is opposite to a surface of the receiving substrate defining the plurality of receiving areas, and the plurality of the light emitting elements are aligned one-to-one with the plurality of the receiving areas;
providing a second electromagnetic plate on a side of the base layer away from the second magnetic material layer; wherein the second electromagnetic plate has magnetic properties after being energized; and
powering on the second electromagnetic plate to form a magnetic field between the first magnetic material layer of each of the plurality of light emitting elements and the second magnetic material layer, and powering off the first electromagnetic plate so that each of the plurality of light emitting elements is detached from the first electromagnetic plate by the magnetic field and transferred to one corresponding receiving area of the receiving substrate.

US Pat. No. 11,114,472

THIN FILM TRANSISTOR PANEL, DISPLAY DEVICE, AND METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR PANEL

Samsung Display Co., Ltd....


1. A transistor panel comprising:a substrate;
a transistor overlapping the substrate and comprising a semiconductor layer;
a first inorganic buffer layer disposed between the substrate and the semiconductor layer;
an inorganic fluorine-containing buffer layer disposed between the first inorganic buffer layer and the semiconductor layer, directly contacting the semiconductor layer, and containing fluorine in a range of 0.5 at % to 2 at %; and
a second inorganic buffer layer interposed between the first inorganic buffer layer and the inorganic fluorine-containing buffer layer,
wherein at least one of the first inorganic buffer layer and the second inorganic buffer layer contains fluorine, and
wherein each of a content of fluorine contained in the first inorganic buffer layer and a content of fluorine contained in the second inorganic buffer layer is less than a content of fluorine contained in the inorganic fluorine-containing buffer layer.

US Pat. No. 11,114,471

THIN FILM TRANSISTORS HAVING RELATIVELY INCREASED WIDTH AND SHARED BITLINES

Intel Corporation, Santa...


1. An integrated circuit structure, comprising:a plurality of transistors formed in an insulator structure above a substrate, each comprising a lateral arrangement of:a gate in the insulating structure, a source laterally adjacent to a first side of the gate, and a drain laterally adjacent to an opposite a second side of the gate, the plurality of transistors arranged in a column such that the respective lateral arrangement of the source, the gate, and the drain of each of the transistors aligns with an adjacent thin film transistor, wherein the plurality transistors extend vertically through the insulator structure at least two interconnect levels to provide increased relative width; and a first conductive contact formed between one of sources and drains of at least two of the plurality of transistors in the column, and the conductive contact extends through the insulator structure at least two interconnect levels.


US Pat. No. 11,114,470

SEMICONDUCTOR DEVICE, ELECTRONIC COMPONENT, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...


1. A semiconductor device comprising:a cell array comprising a first memory cell and a second memory cell;
a first driver circuit configured to supply a selection signal; and
a second driver circuit configured to write or read out data,
wherein:
the first memory cell comprises a first transistor and a first capacitor electrically connected to each other,
the second memory cell comprises a second transistor and a second capacitor electrically connected to each other,
the first driver circuit comprises a third transistor,
the second driver circuit comprises a fourth transistor,
the first to fourth transistors each include a metal oxide in a channel thereof,
the first to fourth transistors have the same polarity, and
the channels of the first and second transistors are formed in a first semiconductor layer.

US Pat. No. 11,114,469

ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...


1. A system, comprising:an array substrate, comprising:an indium gallium zinc oxide (IGZO) film layer;
a gate layer with a disconnected portion at a position thereof overlapping the IGZO film layer to form a first gate line and a second gate line, the first gate line and the second gate line being configured to detect conductorization of indium gallium zinc oxide; and
a gate insulating layer disposed between the IGZO film layer and the gate layer, and provided with at least two through holes thereon, wherein the disconnected portion is between the at least two through holes, the first gate line is connected with the IGZO film layer through at least one through hole, and the second gate line is connected with the IGZO film layer through another at least one through hole such that the IGZO film layer is connected in series with the gate layer.


US Pat. No. 11,114,468

THIN FILM TRANSISTOR ARRAY SUBSTRATE


1. A thin film transistor (TFT) array substrate, comprising:a display device plate; and
a semiconductor layer disposed on the display device plate, wherein a thickness of the semiconductor layer is less than or equal to 35 nm, and the semiconductor layer is generally “n” shaped;
wherein the semiconductor layer comprises an active island and semiconductor lines connected to the active island and perpendicularly disposed to the active island, a width of the active island is less than or equal to 1.8 ?m; and
wherein the semiconductor lines comprise ion lightly doped areas and channel connecting areas, and a width of the ion lightly doped area is less than the width of the active island.

US Pat. No. 11,114,467

DISPLAY DEVICE

LG Display Co., Ltd., Se...


1. A display device, comprising:a substrate including a first sub pixel and a second sub pixel;
a first electrode patterned in each of the first sub pixel and the second sub pixel on the substrate;
a first emission layer provided in each of the first sub pixel and the second sub pixel on the first electrode, and configured to emit first colored light;
a second electrode provided in each of the first sub pixel and the second sub pixel on the first emission layer;
a second emission layer provided on the second electrode, and configured to emit second colored light; and
a third electrode provided on the second emission layer,
wherein the first electrode of the first sub pixel is relatively larger than the first electrode of the second sub pixel,
wherein the first electrode of the first sub pixel is electrically connected with the second electrode of the first sub pixel, and the first electrode of the second sub pixel is insulated from the second electrode of the second sub pixel,
wherein the substrate includes a first sub pixel area provided with the plurality of first sub pixels arranged in a first direction, and a second sub pixel area provided with the plurality of second sub pixels arranged in the first direction and disposed adjacent to the first sub pixel area in a second direction, and
wherein the second electrode disposed in the second sub pixel area extends along the plurality of second sub pixels, and one end of the second electrode disposed in the second sub pixel area is in contact with the third electrode.

US Pat. No. 11,114,466

IC PRODUCTS FORMED ON A SUBSTRATE HAVING LOCALIZED REGIONS OF HIGH RESISTIVITY AND METHODS OF MAKING SUCH IC PRODUCTS

GLOBALFOUNDRIES U.S. INC....


1. An integrated circuit (IC) product, comprising:a semiconductor-on-insulator (SOI) substrate comprising a base semiconductor layer, a buried insulation layer positioned above the base semiconductor layer and an active semiconductor layer positioned above the buried insulation layer;
a first region of localized high resistivity formed in the base semiconductor layer, the first region of localized high resistivity having an electrical resistivity that is greater than an electrical resistivity of a material of the base semiconductor layer; and
a first region comprising integrated circuits formed above the active semiconductor layer, wherein the first region comprising integrated circuits is positioned vertically above the first region of localized high resistivity in the base semiconductor layer.

US Pat. No. 11,114,465

MEMORY DEVICE, SEMICONDUCTOR DEVICE AND ASSOCIATED METHOD

TAIWAN SEMICONDUCTOR MANU...


1. A memory device, comprising:a plurality of memory cells arranged in an array, wherein each memory cell includes a transistor and a capacitor connected to a gate terminal of the transistor in series;
a plurality of first conductive lines, extending in a first direction, wherein each first conductive line connects to gate terminals of transistors arranged in same column in the array;
a plurality of second conductive lines, extending in the first direction, wherein each second conductive line connects to source terminals of transistors arranged in same column in the array;
a plurality of third conductive lines, extending in the first direction, wherein each third conductive line connects to drain terminals of transistors arranged in same column in the array; and
a plurality of fourth conductive line, extending in a second direction, wherein each fourth conductive line couples to the capacitor arranged in same row in the array.

US Pat. No. 11,114,464

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MONOLITHIC 3D INC., Klam...


1. A 3D device, the device comprising:a first level comprising logic circuits;
a second level comprising a plurality of volatile memory cells; and
a third level comprising a plurality of non-volatile memory cells,wherein said first level is bonded to said second level.


US Pat. No. 11,114,463

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...


13. A semiconductor device, comprising:a substrate having a first region and a second region;
gate electrodes stacked perpendicularly to an upper surface of the substrate in the first region, and extending to different lengths in a first direction in the second region;
first isolation regions extended in the first direction while passing through the gate electrodes in the first region and the second region, the first isolation regions being spaced apart from each other in a second direction perpendicular to the first direction;
second isolation regions passing through the gate electrodes between the first isolation regions, the second isolation regions being spaced apart from each other in the first direction;
channels extending perpendicularly to the upper surface of the substrate through the gate electrodes in the first region;
dummy channels extending perpendicularly to the upper surface of the substrate through the gate electrodes in the second region, the dummy channels including first dummy channels arranged in rows and columns and second dummy channels on both sides of a separation region in the second direction, the separation region being a region in which adjacent ones of the second isolation regions are spaced apart from each other in the first direction;
upper isolation regions extending in the first direction, and passing through at least one gate electrode including a gate electrode in an uppermost portion among the gate electrodes, between the second isolation regions and the first isolation regions; and
a lower isolation region passing only through some of the gate electrodes, the lower isolation region passing at least through one gate electrode including a gate electrode in a lowermost portion among the gate electrodes, in a region vertically overlapping the separation region.

US Pat. No. 11,114,462

THREE-DIMENSIONAL MEMORY DEVICE WITH COMPOSITE CHARGE STORAGE STRUCTURES AND METHODS FOR FORMING THE SAME

SANDISK TECHNOLOGIES LLC,...


1. A memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
a memory stack structure extending through the alternating stack, wherein the memory stack structure comprises a vertical stack of discrete charge storage elements that are vertically spaced apart from each other located at levels of the electrically conductive layers, a tunneling dielectric layer located on inner sidewalls of the discrete charge storage elements, and a vertical semiconductor channel contacting an inner sidewall of the tunneling dielectric layer,
wherein each of the discrete charge storage elements comprises:
a silicon nitride portion including an inner sidewall that contacts an outer sidewall of the tunneling dielectric layer; and
a silicon carbide nitride liner in contact with the silicon nitride portion;
further comprising silicon oxide blocking dielectric portions located at each level of the discrete charge storage elements, wherein each of the discrete charge storage elements is laterally spaced from a respective one of the electrically conductive layers by a respective one of the silicon oxide blocking dielectric portions;
wherein each of the discrete charge storage elements further comprises a silicon nitride liner contacting the silicon carbide nitride liner and the outer sidewall of the tunneling dielectric layer;
wherein the silicon nitride liner of each of the discrete charge storage elements contacts a respective overlying one of the insulating layers, and contacts a respective underlying one of the insulating layers; and
wherein the silicon nitride liner of each of the discrete charge storage elements is thinner than the silicon nitride portion.

US Pat. No. 11,114,461

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES HAVING SOURCE STRUCTURE OVERLAPS BURIED INSULATING LAYER

SAMSUNG ELECTRONICS CO., ...


1. A three-dimensional (3D) semiconductor memory device, comprising:first and second semiconductor layers horizontally spaced apart from each other;
a buried insulating layer between the first and second semiconductor layers;
a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and
an isolation structure disposed on the buried insulating layer between the first and second cell array structures,
wherein the first cell array structure comprises:an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and
a first source structure disposed between the first semiconductor layer and the electrode structure,

the first source structure is extended onto the buried insulating layer, and
the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structure.

US Pat. No. 11,114,460

SEMICONDUCTOR MEMORY DEVICES

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor memory device comprising:a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer between the first and second semiconductor layers;
a plurality of gate electrodes on the second semiconductor layer and spaced apart from each other in a first direction perpendicular to an upper surface of the second semiconductor layer; and
a plurality of channel structures penetrating the first, second and third semiconductor layers and the plurality of gate electrodes, each respective channel structure of the plurality of channel structures including a gate insulating film, a channel layer, and a buried insulating film, the gate insulating film including a tunnel insulating film adjacent to the channel layer, a charge blocking film adjacent to the plurality of gate electrodes, and a charge storage film between the tunnel insulating film and the charge blocking film, the charge storage film including an upper cover protruding in a second direction toward the outside of the respective channel structure, and the second direction being perpendicular to the first direction.

US Pat. No. 11,114,459

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING WIDTH-MODULATED CONNECTION STRIPS AND METHODS OF FORMING THE SAME

SANDISK TECHNOLOGIES LLC,...


1. A three-dimensional memory device, comprising:alternating stacks of insulating layers and electrically conductive layers located over a substrate, wherein the alternating stacks are laterally spaced apart from each other by line trenches, each including at least one segment that laterally extends along a first horizontal direction; and
a first memory array region and a second memory array region that are laterally spaced apart along the first horizontal direction by an inter-array region therebetween, wherein each of the alternating stacks continuously extends through the first memory array region, the inter-array region, and the second memory array region, and memory stack structures extend through a respective one of the alternating stacks in the first memory array region or in the second memory array region;
wherein:
each of the alternating stacks includes a respective terrace region in which layers of a respective alternating stack have variable lateral extents that decrease with a vertical distance from the substrate within an area of the inter-array region, and a respective array interconnection region laterally offset from the respective terrace region and which continuously extends from the first memory array region to the second memory array region;
each of the alternating stacks has a width modulation along a second horizontal direction that is perpendicular to the first horizontal direction within the area of the inter-array region and
each of the memory stack structures comprises a vertical semiconductor channel and a memory film.

US Pat. No. 11,114,458

THREE-DIMENSIONAL MEMORY DEVICE WITH SUPPORT STRUCTURES IN GATE LINE SLITS AND METHODS FOR FORMING THE SAME

YANGTZE MEMORY TECHNOLOGI...


1. A three-dimensional (3D) memory device, comprising:a memory stack comprising interleaved a plurality of conductor layers and a plurality of insulating layers extending laterally in the memory stack;
a plurality of channel structures extending vertically through the memory stack into a substrate, the plurality of channel structures and the plurality of conductor layers intersecting with one another and forming a plurality of memory cells;
at least one slit structure extending vertically and laterally in the memory stack and dividing the plurality of memory cells into at least one memory block, the at least one slit structure each comprising a plurality of slit openings and a support structure between adjacent slit openings, the support structure being in contact with adjacent memory blocks and contacting the substrate and comprising a dividing structure over interleaved a plurality of conductor portions and a plurality of insulating portions; and
a source structure comprising an insulating spacer in each of the plurality of slit openings and a source contact in a respective insulating spacer, adjacent source contacts in the source structure being disconnected from each other.

US Pat. No. 11,114,457

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...


1. A semiconductor device, comprising:a stacked structure including at least one source select line, a plurality of word lines and at least one drain select line; and
a channel layer passing through the stacked structure,
wherein the channel layer is a single layer, the single layer including a first region corresponding to the source select line, a cell region corresponding to the word lines, and a second region corresponding to the drain select line, and the first region has a greater thickness than the cell region.

US Pat. No. 11,114,456

MEMORY STACKS HAVING SILICON OXYNITRIDE GATE-TO-GATE DIELECTRIC LAYERS AND METHODS FOR FORMING THE SAME

YANGTZE MEMORY TECHNOLOGI...


1. A three-dimensional (3D) memory device, comprising:a substrate;
a memory stack comprising a first memory deck above the substrate, a second memory deck above the first memory deck, and an inter-deck dielectric layer right above the first memory deck and right below the second memory deck, each of the first memory deck and the second memory deck comprising a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate, wherein the inter-deck dielectric layer is in direct contact with and between the first memory deck and the second memory deck, wherein the inter-deck dielectric layer is a single layer including a first silicon oxynitride layer and an inter-deck plug extending into the inter-deck dielectric layer between the first memory deck and the second memory deck and surrounded and electrically isolated by silicon oxynitride in the inter-deck dielectric layer, and each of the gate-to-gate dielectric layers comprises a second silicon oxynitride layer stacked between two silicon oxide layers, wherein one of the two silicon oxide layers is in direct contact with one of the gate conductive layers and the second silicon oxynitride layer, and another one of the two silicon oxide layers is in direct contact with another one of the gate conductive layers and the second silicon oxynitride layer; and
a NAND memory string extending vertically through the plurality of interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack, the NAND memory string comprising a first channel structure extending vertically through the first memory deck and a second channel structure extending vertically through the second memory deck, wherein each of the first channel structure and the second channel structure further comprises a first channel plug and a second channel plug in an upper portion of the first channel structure and the second channel structure respectively, and the inter-deck plug is vertically between and in direct contact with a lower portion of the second channel structure and the first channel plug of the first channel structure.

US Pat. No. 11,114,455

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SK hynix inc., Icheon-si...


1. A method of manufacturing a semiconductor device, the method comprising:forming a stacked structure, the stacked structure comprising first material layers and second material layers that are alternately stacked in a vertical direction;
forming channel structures passing through the stacked structure;
forming isolation insulating layers extending in a first horizontal direction in the stacked structure, the first horizontal direction crossing the vertical direction, each of the isolation insulating layers passing through at least one of the first material layers and at least one of the second material layers;
forming slits and holes passing through the stacked structure; and
forming material patterns through the slits and the holes, which replace the second material layers,
wherein the slits extend in the first horizontal direction,
wherein the material patterns surround the channel structures, and
wherein the channel structures comprise first channel structures abutting each of the isolation insulating layers and arranged next to each other in the first horizontal direction.

US Pat. No. 11,114,454

SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...


1. A semiconductor device, comprising:a source structure penetrated by a first penetrating portion;
a first stack structure disposed on the source structure and penetrated by a second penetrating portion overlapping the first penetrating portion;
a second stack structure disposed on the first stack structure and extending to overlap the first penetrating portion and the second penetrating portion; and
channel pillars passing through the second stack structure and the first stack structure,
wherein the first stack structure includes a first region penetrated by the channel pillars and second regions extending from the first region to be disposed at opposite sides of the second penetrating portion, and
wherein the second stack structure includes a dummy stack structure overlapping the second penetrating portion and a gate stack structure extending to overlap the first region and the second region.

US Pat. No. 11,114,453

BONDED MEMORY DEVICE AND FABRICATION METHODS THEREOF

YANGTZE MEMORY TECHNOLOGI...


1. A method for forming a bonded semiconductor device, comprising:forming a first wafer and a second wafer, the first wafer having a functional layer over a substrate, wherein the functional layer comprises a plurality of memory arrays, and the substrate does not include single-crystalline silicon, wherein forming the first wafer comprises:forming an insulating material layer over the substrate,
patterning the insulating material layer to form an isolation structure and a plurality of trenches in the isolation structure, and
depositing a semiconductor material to fill up the plurality of trenches to form a plurality of array-base regions in the isolation structure, the isolation structure insulating the plurality of array-base regions from one another;

flipping the first wafer to bond onto the second wafer to form the bonded semiconductor device so that the substrate is on top of the functional layer;
removing at least a portion of the substrate to form a top surface of the bonded semiconductor device; and
forming bonding pads over the top surface.

US Pat. No. 11,114,452

SEAL METHOD TO INTEGRATE NON-VOLATILE MEMORY (NVM) INTO LOGIC OR BIPOLAR CMOS DMOS (BCD) TECHNOLOGY

Taiwan Semiconductor Manu...


1. A method for forming an integrated circuit, the method comprising:forming a trench isolation structure extending into a substrate and delineating a first substrate region and a second substrate region;
depositing a seal layer covering the substrate;
performing a first removal process to remove the seal layer from the first substrate region of the substrate, but not the second substrate region of the substrate;
forming a first gate dielectric layer and a first gate electrode stacked on the first substrate region after the first removal process;
performing a second removal process to remove the seal layer from the second substrate region while the first gate electrode is covered by a mask, wherein a continuous portion of the seal layer remains overlying the trench isolation structure upon completion of the second removal process and has a first seal sidewall facing away from the first gate electrode;
depositing a multilayer film covering the first and second substrate regions and the continuous portion of the seal layer, and further lining the first seal sidewall; and
performing a first etch into the multilayer film to form a second gate dielectric layer and a second gate electrode stacked on the second substrate region, wherein the second gate dielectric layer and the second gate electrode are formed from individual layers of the multilayer film that are distinct from the seal layer.

US Pat. No. 11,114,451

METHOD OF FORMING A DEVICE WITH FINFET SPLIT GATE NON-VOLATILE MEMORY CELLS AND FINFET LOGIC DEVICES

Silicon Storage Technolog...


1. A method of forming a device, comprising:providing a silicon substrate with an upper surface and having first and second areas;
removing portions of the silicon substrate in the first area of the silicon substrate to form an upwardly extending first silicon fin having a pair of side surfaces extending up and terminating at a top surface, and in the second area of the silicon substrate to form an upwardly extending second silicon fin having a pair of side surfaces extending up and terminating at a top surface;
performing a first implantation to form a first source region in the first silicon fin;
performing a second implantation to form a first drain region in the first silicon fin and to form a second source region and a second drain region in the second silicon fin, wherein the first source region and the first drain region define a first channel region of the first silicon fin extending there between, and wherein the second source region and the second drain region define a second channel region of the second silicon fin extending there between;
forming a floating gate disposed over and insulated from a first portion of the first channel region using a first polysilicon deposition, wherein the floating gate wraps around the top and side surfaces of the first silicon fin;
forming an erase gate disposed over and insulated from the first source region, and a word line gate disposed over and insulated from a second portion of the first channel region, and a dummy gate disposed over and insulated from the second channel region, using a second polysilicon deposition, wherein:the erase gate wraps around the top and side surfaces of the first silicon fin,
the word line gate wraps around the top and side surfaces of the first silicon fin,
the dummy gate wraps around the top and side surfaces of the second silicon fin;

and
replacing the dummy gate with a metal gate that is disposed over and insulated from the second channel region, wherein the metal gate wraps around the top and side surfaces of the second silicon fin.

US Pat. No. 11,114,450

ONE-TIME PROGRAMABLE MEMORY DEVICE HAVING ENHANCED PROGRAM EFFICIENCY AND METHOD FOR FABRICATING THE SAME

SK hynix system ic Inc., ...


1. A one-time programmable (OTP) memory device including a plurality of unit cells which are respectively located at cross points of word lines respectively disposed in a plurality of rows and bit lines respectively disposed in a plurality of columns, wherein each of the plurality of unit cells comprising:a selection transistor comprising a drain region separated from a common junction region by a first channel region, and a selection gate structure disposed over the first channel region; and
a storage transistor comprising a source region separated from the common junction region by a second channel region, and a floating gate structure disposed over the second channel region,
wherein the drain region is coupled to any one of the bit lines,
wherein the source region is coupled to a common source line,
wherein a length of an overlapping region between the source region and the floating gate structure in a channel length direction of the storage transistor is less than a length of an overlapping region between the common junction region and the floating gate structure in the channel length direction of the storage transistor, and
wherein the source region and the common junction region are formed after the floating gate structure and the selection gate structure are formed.

US Pat. No. 11,114,449

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...


1. A semiconductor device comprising:a memory cell including first to cth sub memory cells (c is a natural number greater than or equal to 2),
wherein a jth sub memory cell includes a transistor and a capacitor (j is a natural number of 1 to c),
wherein a semiconductor layer in the transistor includes an oxide semiconductor,
wherein the oxide semiconductor includes at least one of indium, gallium, and zinc,
wherein, when j?2, the jth sub memory cell is arranged over a j?1th sub memory cell, and
wherein a bit line is electrically connected to the jth sub memory cell and the j?1th sub memory cell.

US Pat. No. 11,114,448

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device; comprising:a substrate comprising a first region and a second region;
a first semiconductor element positioned in the first region of the substrate;
a second semiconductor element positioned in the first region of the substrate;
a bridge conductive unit electrically connected to the first semiconductor element and the second semiconductor element; and
a programmable unit positioned in the second region and electrically connected to the bridge conductive unit;
wherein the programmable unit comprises a first programmable conductive layer, a programmable insulating layer, and a second programmable conductive layer, the first programmable conductive layer is electrically connected to the bridge conductive unit, the programmable insulating layer is positioned above the first programmable conductive layer, and the second programmable conductive layer is positioned above the programmable insulating layer,
wherein the bridge conductive unit is interposed between the first and second semiconductor elements.

US Pat. No. 11,114,447

SRAM DEVICE PROVIDED WITH A PLURALITY OF SHEETS SERVING AS A CHANNEL REGION

SAMSUNG ELECTRONICS CO., ...


1. An SRAM device comprising:a substrate including a first NMOS region, a second NMOS region and a PMOS region;
a first pull-down transistor disposed in the first NMOS region, the first pull-down transistor including a first gate structure, a first source/drain disposed on a first side of the first gate structure, a second source/drain disposed on a second side of the first gate structure and a first channel disposed below the first gate structure and connecting the first source/drain and the second source/drain;
a second pull-down transistor disposed in the second NMOS region, the second pull-down transistor including a second gate structure, a third source/drain disposed on a first side of the second gate structure, a fourth source/drain disposed on a second side of the second gate structure and a second channel disposed below the second gate structure and connecting the third source/drain and the fourth source/drain;
a first pull-up transistor disposed in the PMOS region, the first pull-up transistor including a third gate structure, a fifth source/drain disposed on a first side of the third gate structure, a sixth source/drain disposed on a second side of the third gate structure and a third channel disposed below the third gate structure and connecting the fifth source/drain and the sixth source/drain;
a second pull-up transistor disposed in the PMOS region, the second pull-up transistor including a fourth gate structure, a seventh source/drain disposed on a first side of the fourth gate structure, an eighth source/drain disposed on a second side of the fourth gate structure and a fourth channel disposed below the fourth gate structure and connecting the seventh source/drain and the eighth source/drain;
a first pass gate transistor disposed in the first NMOS region, the first pass gate transistor including a fifth gate structure, a ninth source/drain disposed on a first side of the fifth gate structure, a tenth source/drain disposed on a second side of the fifth gate structure and a fifth channel disposed below the fifth gate structure and connecting the ninth source/drain and the tenth source/drain; and
a second pass gate transistor disposed in the second NMOS region, the second pass gate transistor including a sixth gate structure, an eleventh source/drain disposed on a first side of the sixth gate structure, a twelfth source/drain disposed on a second side of the sixth gate structure and a sixth channel disposed below the sixth gate structure and connecting the eleventh source/drain and the twelfth source/drain,
wherein the first pull-down transistor and the first pull-up transistor form a first inverter,
the second pull-down transistor and the second pull-up transistor form a second inverter,
the first channel includes a first semiconductor sheet and a second semiconductor sheet that is stacked on and spaced apart from the first semiconductor sheet,
the second channel includes a third semiconductor sheet and a fourth semiconductor sheet that is stacked on and spaced apart from the third semiconductor sheet,
the third channel includes a fifth semiconductor sheet and a sixth semiconductor sheet that is stacked on and spaced apart from the fifth semiconductor sheet,
the fourth channel includes a seventh semiconductor sheet and an eighth semiconductor sheet that is stacked on and spaced apart from the seventh semiconductor sheet,
the fifth channel includes a ninth semiconductor sheet and a tenth semiconductor sheet that is stacked on and spaced apart from the ninth semiconductor sheet,
the sixth channel includes an eleventh semiconductor sheet and a twelfth semiconductor sheet that is stacked on and spaced apart from the eleventh semiconductor sheet,
a width of the first semiconductor sheet is greater than a width of the fifth semiconductor sheet, and
a width of the ninth semiconductor sheet is greater than the width of the fifth semiconductor sheet,
a ratio of the width of the first semiconductor sheet to the width of the fifth semiconductor sheet is 1.4 to 1.9 or 2.1 to 10, and
a ratio of the width of the ninth semiconductor sheet to the width of the fifth semiconductor sheet is 1.4 to 1.9 or 2.1 to 10.

US Pat. No. 11,114,446

SRAM WITH HIERARCHICAL BIT LINES IN MONOLITHIC 3D INTEGRATED CHIPS

Intel Corporation, Santa...


1. A memory device, comprising:a first plurality of memory cells extending laterally on a first level;
a second plurality of memory cells extending laterally on the first level;
a local sense amplifier on the first level between the first plurality of memory cells and the second plurality of memory cells;
a local bit line extending laterally on a second level, the second level vertically separated by one or more first inter-level dielectric layers from the first level in a first direction, the local bit line electrically coupled to each memory cell of the first plurality of memory cells, each memory cell of the second plurality of memory cells, and the local sense amplifier; and
a global bit line extending laterally on a third level vertically separated by one or more second inter-level dielectric layers from the first level in a second direction opposite the first direction, the global bit line electrically coupled to the local sense amplifier.

US Pat. No. 11,114,445

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...


1. A semiconductor device, comprising:a substrate comprising an active pattern;
a cell region on the substrate, the cell region comprising a cell circuit; and
a core region on the substrate, the core region comprising a peripheral circuit,
wherein, in plan view, the active pattern on the core region comprises a plurality of corners,
wherein each of the corners has a rounding index that is equal to or less than about 15 nm, wherein the rounding index indicates a distance between a respective tip of the each of the corners and a right-angled corner.

US Pat. No. 11,114,444

SEMICONDUCTOR DEVICE WITH CONDUCTIVE CAP LAYER OVER CONDUCTIVE PLUG AND METHOD FOR FORMING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device, comprising:a semiconductor substrate;
a first word line and a second word line disposed over the semiconductor substrate;
a conductive plug disposed between the first word line and the second word line;
a conductive cap layer directly disposed over the conductive plug, wherein a top surface and a portion of a sidewall surface of the conductive plug are completely covered by and directly contacted with the conductive cap layer;
a dielectric layer disposed over the first word line and the second word line, wherein the portion of the sidewall surface of the conductive plug protrudes from the dielectric layer, wherein the top surface of the conductive plug is higher than a topmost surface of the dielectric layer; and
a bit line disposed over the conductive cap layer, wherein the bit line is electrically connected to the conductive plug.

US Pat. No. 11,114,443

SEMICONDUCTOR STRUCTURE FORMATION

Micron Technology, Inc., ...


1. A method for semiconductor structure formation, comprising:patterning a working surface of a semiconductor wafer;
performing a vapor etch selective to a first oxide material at the working surface to recess the first oxide material to a first intended depth of an opening relative to the working surface and to expose a second oxide material on a sidewall of the opening; and
subsequent to performing the vapor etch, performing a wet etch selective to the second oxide material to recess the second oxide material to the first intended depth.

US Pat. No. 11,114,442

SEMICONDUCTOR MEMORY DEVICE WITH SHALLOW BURIED CAPACITOR AND FABRICATION METHOD THEREOF

HeFeChip Corporation Limi...


1. A semiconductor device, comprising:a substrate comprising a semiconductor substrate, a buried oxide layer on said semiconductor substrate, and a silicon device layer on said buried layer;
at least one bottle-shaped capacitor cavity extending through said silicon device layer and said buried oxide layer, wherein said at least one bottle-shaped capacitor cavity is comprised of an upper portion disposed in said silicon device layer and a widened bottom burrow disposed in said buried oxide layer and underneath the silicon device layer, wherein said widened bottom burrow is wider than said upper portion;
at least one buried capacitor located in said at least one bottle-shaped capacitor cavity, said at least one buried capacitor comprising an inner electrode and an outer electrode with a capacitor dielectric layer therebetween;
at least one transistor disposed on said substrate, wherein said at least one transistor comprises a source region and a drain region disposed in said silicon device layer, a channel region between said source region and said drain region, and a gate over said channel region, and wherein said source region is electrically connected to said inner electrode of said at least one buried capacitor; and
a conductive material layer embedded within said upper portion, wherein said inner electrode is in direct contact with said conductive material layer.

US Pat. No. 11,114,441

SEMICONDUCTOR MEMORY DEVICE

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor memory device, comprising:a substrate having an active area, wherein the active area has a first area, a second area and a third area, the third area surrounds the first area, the second area surrounds the first area and the third area;
a plurality of landing pads disposed on the first area;
a first conducting layer disposed on the second area;
a plurality of first capacitors disposed on the landing pads respectively;
a plurality of second capacitors disposed on the first conducting layer;
a second conducting layer disposed on the second capacitors; and
a plurality of third capacitors disposed in the third area, wherein the second conducting layer is not electrically connected to the third capacitors.

US Pat. No. 11,114,440

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...


1. A method of fabricating a semiconductor memory device, the method comprising:forming on a semiconductor substrate a bit line and a bit line capping pattern on the bit line;
forming a first spacer that covers a sidewall of the bit line capping pattern and a sidewall of the bit line;
forming a lower buried dielectric pattern covering a lower sidewall of the first spacer;
forming a sacrificial spacer and a second spacer that sequentially cover middle and upper sidewalls of the first spacer;
partially removing upper portions of the sacrificial spacer and the second spacer to expose the upper sidewall of the first spacer;
forming a storage node contact adjacent to the second spacer;
forming a conductive layer that covers the bit line capping pattern, the first spacer, the sacrificial spacer, the second spacer, and the storage node contact;
etching the conductive layer to form a recess region exposing the sacrificial spacer and to form a landing pad electrically connected to the storage node contact;
removing the sacrificial spacer to form an air gap region; and
forming an upper buried dielectric pattern that fills the recess region and defines a top end of the air gap region.

US Pat. No. 11,114,439

MULTI-DIVISION 3D NAND MEMORY DEVICE

Yangtze Memory Technologi...


1. A semiconductor structure, comprising:a substrate; and
a plurality of layer stacks disposed over the substrate, wherein the plurality of layer stacks comprises first and second staircase structures abutting each other, wherein:a bottommost step of the second staircase structure is separated from and higher than a topmost step of the first staircase structure;
each of the first and the second staircase structures comprises P steps in a first direction;
each of the P steps comprises N steps, wherein P and N are natural numbers greater than or equal to 1; and
each of the N steps of the first staircase structure extends towards a second direction, wherein each of the N steps of the second staircase structure extends towards another direction opposite to the second direction.


US Pat. No. 11,114,438

THYRISTOR VOLATILE RANDOM ACCESS MEMORY AND METHODS OF MANUFACTURE

TC Lab, Inc., Gilroy, CA...


1. A method of making a volatile memory array having row lines, column lines, and an array of thyristors having anodes coupled to one of the row and column lines and having cathodes coupled to the other of the row and column lines, the method comprising:implanting opposite conductivity type dopant into a first conductivity type semiconductor substrate to thereby provide a buried layer and the cathode for each of the thyristors;
forming a first conductivity type epitaxial layer on the buried layer;
removing all of the epitaxial layer and the buried layer to expose portions of the substrate from a first plurality of parallel regions extending in a first direction of the memory array to thereby form a first plurality of deep trenches;
filling the first plurality of deep trenches with insulating material;
removing all of the epitaxial layer to expose portions of the buried layer from a second plurality of parallel regions extending in a second direction of the memory array to thereby form a second plurality of shallow trenches;
filling the second plurality of shallow trenches with insulating material;
forming a further epitaxial layer on an upper surface of the epitaxial layer;
implanting opposite conductivity type dopant into an upper portion of the further epitaxial layer to form upper opposite conductivity type regions separated from the buried layer by the epitaxial layer;
implanting first conductivity type dopant into a top portion of the further epitaxial layer to form the anode for each of the thyristors; and
providing electrical connections to the further epitaxial layer to provide connections to the anodes of the thyristors.

US Pat. No. 11,114,437

SEMICONDUCTOR DEVICE COMPRISING FIRST AND SECOND STANDARD CELLS ARRANGED ADJACENT TO EACH OTHER

SOCIONEXT INC., Kanagawa...


1. A semiconductor device comprising first and second standard cells which are arranged adjacent to each other in a first direction, wherein:the first standard cell includes a plurality of first fins which extend in the first direction, and which are arranged along a boundary between the first and second standard cells in a second direction that is perpendicular to the first direction,
the second standard cell includes a plurality of second fins which extend in the first direction, and which are arranged in the second direction along the boundary between the first and second standard cells such that each of the plurality of second fins is aligned with an associated one of the plurality of first fins, wherein the plurality of second fins include at least one dummy fin and at least one first active fin,
the second standard cell further includes at least one second active fin different from the plurality of first fins and the plurality of second fins, wherein the at least one second active fin, the at least one dummy fin and one of the plurality of first fins are aligned with each other in the first direction, and
the first and second standard cells include a first power supply line and a second power supply line having a different potential than the first power supply line, both extending in the first direction.

US Pat. No. 11,114,436

METAL GATE STRUCTURE AND METHODS THEREOF

Taiwan Semiconductor Manu...


1. A method of semiconductor device fabrication, comprising:forming a first fin and a second fin on a substrate;
forming a gate structure over the first and second fins, wherein the gate structure extends from the first fin to the second fin; and
performing a line-cut process to separate the gate structure into a first metal gate structure and a second metal gate structure with an interposing space, wherein the line-cut process includes:performing a first anisotropic etch to remove a first portion of a plurality of metal layers of the gate structure, wherein the first anisotropic etch has a first etchant gas;
after the first anisotropic etch, performing a second isotropic etch to remove a second portion of the gate structure, the second portion including a region of at least one metal layer of the plurality of metal layers, wherein the second isotropic etch has a second etchant gas different than the first etchant gas; and
after the second isotropic etch, performing a third wet etch to remove a third portion of the gate structure, the third portion including a residual portion of a gate dielectric layer.


US Pat. No. 11,114,435

FINFET HAVING LOCALLY HIGHER FIN-TO-FIN PITCH

IMEC vzw, Leuven (BE) Ka...


1. A semiconductor fin device comprising:at least three fins including first to third fins protruding from a substrate and arranged to extend in parallel in a first direction and further arranged to laterally alternate in a second direction with a plurality of shallow trench isolation structures, wherein each of the at least three fins is separated from an immediately adjacent one of the at least three fins by a first fin spacing and by one of the shallow trench isolation structures, and wherein immediately adjacent ones of the shallow trench isolation structures are discretely separated from each other in the second direction by one of the at least three fins,
wherein at least a portion of each of the first fin and the second fin of the at least three fins vertically protrudes to substantially the same vertical level higher than upper surfaces of the shallow trench isolation structures immediately adjacent to a respective one of the each of the first fin and the second fin, and
wherein the third fin is formed laterally between the first fin and the second fin in the second direction, the third fin having a non-protruding region which extends vertically to a level below or equal to upper surfaces of the shallow trench isolation structures immediately adjacent to the third fin; and
a first gate dielectric that is conformal with respect to topmost surfaces and upper sidewall portions of the first and second fins,
wherein the first gate dielectric has the same composition at portions contacting each of the first, second and third fins,
wherein the first gate dielectric overlaps and contacts a topmost portion of the third fin in the non-protruding region and immediately adjacent ones of the shallow trench isolation structures with respect to the third fin, and wherein the first gate dielectric contacting sidewalls of the first fin and sidewalls of the second fin has a thickness measured in the second direction that is at least half of the first fin spacing.

US Pat. No. 11,114,434

COMPUTATION-IN-MEMORY IN THREE-DIMENSIONAL MEMORY DEVICE

YANGTZE MEMORY TECHNOLOGI...


1. A three-dimensional (3D) memory device, comprising:a first semiconductor structure comprising a peripheral circuit, a data processing circuit, and a first bonding layer comprising a plurality of first bonding contacts;
a second semiconductor structure comprising an array of 3D NAND memory strings and a second bonding layer comprising a plurality of second bonding contacts; and
a bonding interface between the first bonding layer and the second bonding layer, whereinthe first bonding contacts are in contact with the second bonding contacts at the bonding interface,
the first semiconductor structure is above the second semiconductor structure, and
the first semiconductor structure further comprises a semiconductor layer above the first bonding layer, and a pad-out interconnect layer above the semiconductor layer.


US Pat. No. 11,114,433

3DIC STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...


1. A three dimensional integrated circuit (3DIC) structure, comprising:a first die having a first interconnect structure and a first pad electrically connected to the first interconnect structure;
a second die having a second interconnect structure and a second pad electrically connected to the second interconnect structure; and
a hybrid bonding structure bonding the first die and the second die, and disposed between the first interconnect structure and the second interconnect structure, wherein the hybrid bonding structure comprises a first bonding structure covering the first pad and a second bonding structure covering the second pad, the first bonding structure comprises:a first bonding dielectric layer; and
a first bonding metal layer, disposed in the first bonding dielectric layer, wherein the first bonding metal layer comprises a first via plug and a first metal feature disposed over and in direct contact with the first via plug, a height of the first metal feature is greater than a height of the first via plug,
wherein the first pad is laterally aside the first bonding metal layer, and separated from the second pad by the first bonding dielectric layer therebetween, and a bottom surface of the first metal feature contacting the first via plug is lower than a top surface of the first pad of the first die.


US Pat. No. 11,114,432

PROTECTION CIRCUIT WITH A FET DEVICE COUPLED FROM A PROTECTED BUS TO GROUND

Semtech Corporation, Cam...


1. A semiconductor device, comprising:a voltage input circuit node;
a ground voltage node;
a first transistor coupled between the voltage input circuit node and the ground voltage node, wherein the first transistor is a field-effect transistor (FET);
a first resistor coupled between a source or drain terminal of the first transistor and the voltage input circuit node, wherein the first resistor and first transistor are coupled between the voltage input circuit node and ground voltage node in series;
a second transistor coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor, wherein the second transistor is a FET, and wherein a source or drain terminal of the second transistor is coupled to a gate terminal of the first transistor;
a voltage-limiting circuit coupled between the source or drain terminal of the second transistor and the gate terminal of the first transistor, wherein the voltage-limiting circuit includes a fourth transistor comprising a first source, drain, emitter, or collector terminal coupled to the source or drain terminal of the second transistor and a second source, drain, emitter, or collector terminal of the fourth transistor is coupled to the gate terminal of the first transistor; and
a triggering circuit coupled between the voltage input circuit node and the ground voltage node in parallel with the first transistor, wherein a first circuit node of the triggering circuit is coupled to a gate terminal of the second transistor, and wherein the triggering circuit includes,a second resistor coupled between the first circuit node and the voltage input circuit node,
a third transistor comprising a first emitter or collector terminal coupled to the first circuit node and a second emitter or collector terminal coupled to the ground voltage node, wherein the third transistor is a bipolar junction transistor (BJT), and
a triggering diode comprising a cathode coupled to the first circuit node and an anode coupled to a base terminal of the third transistor.


US Pat. No. 11,114,431

ELECTROSTATIC DISCHARGE PROTECTION DEVICE

Semiconductor Manufacturi...


1. An electrostatic discharge (ESD) protection device, comprising:a substrate having an input region;
a plurality of fins on the substrate in the input region;
a well region, doped with first-type ions, in the plurality of fins and in the substrate;
an epitaxial layer on each fin in the input region;
a drain region, doped with second-type ions, in a top portion of each fin and in the epitaxial layer;
an extended drain region, doped with the second-type ions, in a bottom portion of each fin to connect to the drain region and in a portion of the substrate, in the input region; and
a counter-doped region, doped with the first-type ions, in a portion of the substrate between two adjacent fins to insulate adjacent extended drain regions, wherein a PN junction is formed between the counter-doped region and the extended drain region.

US Pat. No. 11,114,430

LEAKAGE CURRENT DETECTION AND PROTECTION DEVICE AND POWER CONNECTOR EMPLOYING THE SAME

Chengli Li, Suzhou (CN)


1. A leakage current detection and protection device coupled between an input end and an output end of power lines, the device comprising:a first switching module and a second switching module, wherein each of the first and second switching modules is coupled on the power lines between the input end and the output end, wherein the first and second switching modules are operable to connect or disconnect an electrical connection between the input and output ends such that the input end is electrically connected to the output end when both the first and second switching modules are in their connected state, and the input end is electrically disconnected from the output end when either of the first and second switching modules is in its disconnected state;
a leakage current detection module configured to detect a leakage current signal on the power lines and to generate a leakage fault signal in response to detecting the leakage current signal;
a self-test module configured to detect a fault of the leakage current detection module and to output a self-test fault signal when the fault in the leakage current detection module is detected;
a first drive module, coupled to the self-test module and the first switching module, and configured, in response to the self-test fault signal, to control the first switching module to disconnect the electrical connection between the input and output ends; and
a second drive module, coupled to the leakage current detection module and the second switching module, and configured, in response to the leakage fault signal, to control the second switching module to disconnect the electrical connection between the input and output ends, wherein the first and second drive modules are separate from each other and configured to separately control the first and second switching modules, respectively.

US Pat. No. 11,114,429

INTEGRATED CIRCUIT DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

XILINX, INC., San Jose, ...


1. An integrated circuit device comprising:a first die having a first body, the first body comprising a passive region and an active region;
a first contact pad exposed to a surface of the first body, the first contact pad configured to connect to a first supply voltage;
a second contact pad exposed to the surface of the first body, the second contact pad configured to connect to a second supply voltage or ground;
a first charge-sensitive circuitry formed in the first body and coupled between the first contact pad and the second contact pad;
a first RC clamp formed in the first body and coupled between the first contact pad and the second contact pad, the first RC clamp comprising:at least two BigFETs coupled between the first contact pad and the second contact pad; and
a trigger circuitry coupled in parallel to gate terminals of the at least two BigFETs;

a plurality of FEOL layers including an oxide layer, the oxide layer forming a gate oxide layer of a first BigFET of the at least two BigFETs; and
a second die having another BigFET in an RC clamp, the another BigFET of the RC clamp of the second die having an oxide gate layer thicker than the gate oxide layer of the first BigFET of the first die.

US Pat. No. 11,114,428

INTEGRATED CIRCUIT DEVICE

SAMSUNG ELECTRONICS CO., ...


1. An integrated circuit device comprising:a memory comprisinga memory stack,
a memory cell interconnection comprising a plurality of upper conductive patterns configured to be electrically connectable to the memory stack, and
a memory cell insulation surrounding the memory stack and the memory cell interconnection;

a peripheral circuit comprisinga peripheral circuit board,
a peripheral circuit region on the peripheral circuit board, and
a peripheral circuit interconnection comprising a plurality of lower conductive patterns between the peripheral circuit region and the memory and bonded to the memory cell interconnection;

a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, the plurality of conductive bonding structures being bonded plurality of first upper conductive patterns selected from among the plurality of upper conductive patterns and a respective plurality of first lower conductive patterns selected from among the plurality of lower conductive patterns; and
a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a second lower conductive pattern selected from among the plurality of lower conductive patterns in the vertical direction, in a second region, the second region overlapping the memory cell insulation in the vertical direction.

US Pat. No. 11,114,427

3D SEMICONDUCTOR PROCESSOR AND MEMORY DEVICE AND STRUCTURE

Monolithic 3D Inc., Klam...


1. A 3D semiconductor device, the device comprising:a first level comprising first single crystal transistors; and
a second level comprising second single crystal transistors,wherein said first level is overlaid by said second level,
wherein a vertical distance from said first single crystal transistors to said second single crystal transistors is less than four microns,
wherein said first level comprises a plurality of processors, and
wherein said second level comprises a plurality of memory cells.


US Pat. No. 11,114,426

BENDABLE PANEL AND METHOD OF FABRICATING SAME


1. A bendable panel, comprising:a flexible display panel comprising a flexible substrate as a base, wherein the flexible substrate comprises an active display area and a binding end positioned on a side of the active display area;
a driving chip disposed on the binding end, wherein the binding end is bent toward a direction away from a light emitting side of the flexible display panel, such that the driving chip is positioned on a back surface of the flexible substrate;
a back film layer disposed on the back surface of the flexible substrate, wherein the back film layer is configured to support and protect the flexible substrate;
a foam layer disposed on the back surface of the back film layer, wherein the foam layer is configured to protect the flexible substrate; and
a support plate;
wherein the binding end comprises a first terminal portion adjacent to the active display area, a second terminal portion adjacent to the driving chip, and a bent portion connected to the first terminal portion and the second terminal portion and having a bent shape; and
wherein a bent region disposed on an inner surface of the bent portion is provided with a glue;
wherein the support plate is attached to a back surface of the second terminal portion, the support plate covers at least the back surface of the second terminal portion on which the driving chip is disposed, a configuration of the support plate, the back surface of the second terminal portion, and the driving chip fills a height difference between the foam layer and the second terminal portion.

US Pat. No. 11,114,425

PACKAGING OF RADIATION DETECTORS IN AN IMAGE SENSOR

SHENZHEN XPECTVISION TECH...


1. An image sensor comprising:a first package comprising a plurality of radiation detectors mounted on a printed circuit board (PCB);
wherein a dead zone of the first package does not extend between neighboring radiation detectors among the plurality of radiation detectors;
wherein the radiation detectors have no guard rings or sidewall doping;
wherein each of the radiation detectors comprises an array of pixels;
wherein pixels on peripheries of the radiation detectors are configured to deduct a contribution of a dark current from energy of a radiation particle incident thereon.

US Pat. No. 11,114,424

DISPLAY SUBSTRATE AND METHOD FOR PREPARING THE SAME, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...


1. A display substrate, comprising:a base substrate;
a display function layer located on a first surface of the base substrate, a first groove arranged in the first surface and recessed from the first surface toward the base substrate, and a first connection sub-line located in the first groove and covering a bottom and each side wall of the first groove, wherein the first connection sub-line is connected to a signal input terminal of the display function layer; and
an integrated circuit located on a second surface of the base substrate opposite to the first surface, a second groove arranged in the second surface and recessed from the second surface toward the base substrate to the first connection sub-line, and a second connection sub-line located in the second groove, wherein the second connection sub-line is connected to the first connection sub-line and a signal output terminal of the integrated circuit,
wherein an orthogonal projection of the first groove on the base substrate at least partially overlaps an orthogonal projection of the second groove on the base substrate, and the first groove and the second groove communicate with each other and together penetrate the base substrate.

US Pat. No. 11,114,423

IMAGE-FORMING ELEMENT

SHARP KABUSHIKI KAISHA, ...


1. An image-forming element that includes a plurality of pixels and projects and displays light emitted from the pixels, the element comprising:a light emitting element which includes a light source emitting the light; and
a mounting substrate on which a plurality of light emitting elements are provided on a mounting surface,
wherein a plurality of light sources which are segmented and included in at least one pixel are provided,
wherein each of the light sources includes one or a plurality of power supply electrodes provided on the same surface,
wherein the mounting substrate includes a drive circuit which drives the light source and electrodes which are provided on the mounting surface and are electrically connected to the power supply electrodes of the light source, and
wherein the drive circuit includes at least one non-volatile memory transistor to reduce a variation of light emission intensity between the light emitting elements.