US Pat. No. 11,069,696

DEVICE STRUCTURE FOR A 3-DIMENSIONAL NOR MEMORY ARRAY AND METHODS FOR IMPROVED ERASE OPERATIONS APPLIED THERETO

SUNRISE MEMORY CORPORATIO...


1. A thin-film storage transistor in a memory string, comprising:first and second semiconductor layers of a first conductivity, serving as a drain terminal and a source terminal of the thin-film storage transistor, respectively;
a third semiconductor layer of a second conductivity adjacent the first and second semiconductor layers, serving as a channel region of the thin-film storage transistor;
a conductor serving as a gate terminal of the thin-film storage transistor;
a charge-trapping region between the conductor and third semiconductor layer;
a fourth semiconductor layer of the second conductivity provided in close proximity to the third semiconductor layer and having a dopant concentration substantially equal to or great than the dopant concentration of the third semiconductor layer and
a diffusion barrier layer that prevents dopant diffusion between the third and fourth semiconductor layer.

US Pat. No. 11,069,695

FLOATING GATE TEST STRUCTURE FOR EMBEDDED MEMORY DEVICE

Taiwan Semiconductor Manu...


1. An integrated circuit (IC) comprising:a memory region and a logic region integrated in a substrate;
a plurality of logic devices disposed in the logic region, wherein a logic device of the plurality of logic devices comprises a logic gate electrode separated from the substrate by a logic gate dielectric;
a plurality of memory cell structures disposed in a memory cell region of the memory region, wherein a memory cell structure of the plurality of memory cell structures comprises a pair of control gates respectively separated from the substrate by a pair of floating gates and a pair of select gate electrodes disposed on opposite sides of the pair of control gates; and
a plurality of memory test structures disposed in a memory test region at a periphery of the memory region surrounding the plurality of memory cell structures, wherein a memory test structure of the plurality of memory test structures comprises a pair of dummy control gates respectively separated from the substrate by a pair of dummy floating gates and a pair of dummy select gate electrodes disposed on opposite sides of the pair of dummy control gates;
wherein the memory test structure further comprises a pair of conductive floating gate test contact vias respectively extending through the pair of dummy control gates and reaching on the dummy floating gates.

US Pat. No. 11,069,694

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...


1. A method for forming a semiconductor structure, comprising:providing a substrate comprising:
a unit memory area, and
a plurality of discrete first gate laminated structures that are formed on the substrate of the unit memory area;
forming a unit dielectric layer on a portion of the substrate exposed from a first gate laminated structure of the plurality of discrete first gate laminated structures, where a portion of a side wall of the first gate laminated structure is exposed from the unit dielectric layer, and the first gate laminated structure and the unit dielectric layer enclose a unit groove;
forming an isolation spacer layer on a side wall of the unit groove, where a bottom of the isolation spacer layer is in contact with the unit dielectric layer, and a top of the isolation spacer layer is lower than a top of the first gate laminated structure;
forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and
annealing the metal layer to form a metal silicide layer.

US Pat. No. 11,069,693

METHOD FOR IMPROVING CONTROL GATE UNIFORMITY DURING MANUFACTURE OF PROCESSORS WITH EMBEDDED FLASH MEMORY

Taiwan Semiconductor Manu...


1. A method, comprising:forming a recessed region in a semiconductor substrate;
forming gate materials for a plurality of floating gates and control gates of a memory array in layers over the recessed region;
forming a protective layer over the gate materials in the recessed region;
planarizing the protective layer by:depositing a sacrificial layer over the protective layer;
planarizing the sacrificial layer; and
after planarizing the sacrificial layer, etching the planarized surface of the sacrificial layer at an even rate across the recessed region, to a depth sufficient to leave a planarized surface on the protective layer:,

forming an etch mask layer over the planarized protective layer; and
forming a plurality of gate stacks in the recessed region by etching the gate materials.

US Pat. No. 11,069,692

FINFET SRAM CELLS WITH DIELECTRIC FINS

TAIWAN SEMICONDUCTOR MANU...


1. An integrated circuit (IC), comprising:a first static random access memory (SRAM) cell oriented lengthwise along a first direction and widthwise along a second direction generally perpendicular to the first direction, wherein the first SRAM cell is disposed over a substrate, and wherein the first SRAM cell includes:first, second, third, and fourth dielectric fins disposed in this order along the first direction and oriented lengthwise along the second direction, wherein the first and the fourth dielectric fins define two edges of the first SRAM cell, and wherein bottom portions of the first, second, third, and fourth dielectric fins are disposed in isolation features over the substrate;
a first p-type semiconductor fin disposed between the first and the second dielectric fins;
a second p-type semiconductor fin disposed between the third and the fourth dielectric fins;
a first n-type semiconductor fin and a second n-type semiconductor fin disposed between the second and the third dielectric fins,
wherein the first and the second p-type semiconductor fins and the first and the second n-type semiconductor fins are oriented lengthwise along the second direction, and
wherein the isolation features separate each of the first and the second p-type semiconductor fins and the first and the second n-type semiconductor fins from each of the first, second, third, and fourth dielectric fins; and
gate structures oriented lengthwise along the first direction and spaced from each other along the second direction, wherein the gate structures engage one or more of the first, the second, the third, and the fourth dielectric fin, the first and the second n-type semiconductor fins, and the first and the second p-type semiconductor fins.


US Pat. No. 11,069,691

MEMORY CELL ARRAY WITH LARGE GATE WIDTHS

GLOBALFOUNDRIES U.S. Inc....


1. An integrated circuit with a memory cell array, comprising:a plurality of conductive lines exhibiting a serpentine shape;
a plurality of semiconductor lines extending in a first direction; and
a plurality of transistor devices, wherein gates of said transistor devices are formed in portions of said conductive lines and channels of said transistor devices are formed in said semiconductor lines;
wherein at least one portion of at least one of said conductive lines runs across a first one of said semiconductor lines in a second direction inclined to a direction perpendicular to said first direction at a first inclination angle of more than 5° as measured clockwise from said direction perpendicular to said first direction, and said at least one of said conductive lines run across a second one of said semiconductor lines in a third direction at a second inclination angle of more than 5° as measured counterclockwise from said direction perpendicular to said first direction,
wherein said first inclination angle is between 10° and 40° as measured clockwise from said direction perpendicular to said first direction and said second inclination angle is between 10° and 40° as measured counterclockwise from said direction perpendicular to said first direction, and
wherein a portion of said at least one of said conductive lines that overlaps a third one of said semiconductor lines is perpendicular to said first direction, wherein a width of said first one of said semiconductor lines in said direction perpendicular to said first direction is different from a width of said third one of said semiconductor lines in said direction perpendicular to said first direction.

US Pat. No. 11,069,690

DRAM AND FLASH STRUCTURE AND METHOD OF FABRICATING THE SAME

UNITED MICROELECTRONICS C...


1. A method of fabricating a DRAM and a flash, comprising:providing a substrate comprising a first region and a second region, wherein the first region is for disposing a DRAM, and the second region is for disposing a flash;
forming a plurality of trenches in the first region and the second region to define a first active region in the first region and a second active region in the second region;
forming a silicon oxide/silicon nitride/silicon oxide composite layer filling in the trenches to form a plurality of shallow trench isolations;
forming a first buried gate crossing the first active region and a second buried gate crossing the second active region, wherein the second buried gate only consists of a control gate and a gate dielectric layer, the gate dielectric layer is formed by a single material;
forming a capacitor plug contacting the first active region and disposed at one side of the first buried gate; and
forming a capacitor electrically connecting the capacitor plug.

US Pat. No. 11,069,689

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

UNITED MICROELECTRONICS C...


1. A manufacturing method of a semiconductor memory device, comprising:providing a semiconductor substrate, wherein a memory cell region and a peripheral region are defined on the semiconductor substrate;
forming a contact hole on the memory cell region, wherein the contact hole exposes a part of the semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming a first trench on the memory cell region, wherein the first trench penetrates the dielectric layer;
forming a second trench on the peripheral region, wherein the second trench penetrates the dielectric layer;
forming a metal conductive layer, wherein the first trench and the second trench are filled with the metal conductive layer for forming a bit line metal structure in the first trench and a first metal gate structure in the second trench; and
forming a contact structure in the contact hole, wherein the contact structure is located between the bit line metal structure and the semiconductor substrate.

US Pat. No. 11,069,688

VERTICAL TRANSISTOR WITH EDRAM

International Business Ma...


1. A method comprising:providing a substrate with a first doped layer thereon;
forming a trench through the substrate and the first doped layer;
filling the trench with a first polysilicon material;
after filling the trench with the first polysilicon material, i) growing a second polysilicon material over the first polysilicon material and ii) epitaxially growing a second doped layer over the first doped layer, wherein the grown second polysilicon material and the epitaxially grown second doped layer form a basis for a strap merging the second doped layer and the second polysilicon material; and
performing a planarization process on an excess portion of the grown second polysilicon material that grows over the second doped layer.

US Pat. No. 11,069,687

INTEGRATED ASSEMBLIES HAVING SHIELD LINES BETWEEN DIGIT LINES, AND METHODS OF FORMING INTEGRATED ASSEMBLIES

Micron Technology, Inc., ...


1. An integrated assembly, comprising:digit lines extending along a first direction; the digit lines being spaced from one another by intervening regions; each of the digit lines having a first width along a cross-section orthogonal to the first direction; each of the intervening regions also having the first width along the cross-section; each of the digit lines having a top surface at a first height;
vertically-extending pillars over the digit lines; each of the vertically-extending pillars comprising a transistor channel region and an upper source/drain region; lower source/drain regions being under the channel regions and being coupled with the digit lines; the transistor channel regions extending vertically between the lower source/drain regions and the upper source/drain regions; each of the vertically-extending pillars having the first width along the cross-section; the intervening regions extending upwardly to between the vertically-extending pillars and comprising the first width from top surfaces of the upper source/drain regions to bottom surfaces of the digit lines;
storage elements coupled with the upper source/drain regions;
wordlines extending along a second direction which crosses the first direction; the wordlines including gate regions adjacent the channel regions; and
shield lines within the intervening regions and extending along the first direction; each of the shield lines having a top surface at a second height which is greater than or equal to the first height.

US Pat. No. 11,069,686

TECHNIQUES FOR ENHANCING VERTICAL GATE-ALL-AROUND FET PERFORMANCE

International Business Ma...


1. A vertical field effect transistor (VFET) device, comprising:at least one fin patterned in a substrate;
bottom source and drains at a base of the at least one fin;
bottom spacers on the bottom source and drains;
a gate along sidewalls of the at least one fin;
an oxide layer formed along the sidewalls of a top portion of the at least one fin;
a charged layer disposed over the at least one fin in direct contact with the oxide layer, wherein the charged layer induces an opposite charge in the top portion of the at least one fin forming a dipole;
top spacers above the gate; and
top source and drains above the top spacers.

US Pat. No. 11,069,685

SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...


1. A semiconductor device comprising:a substrate including a first region and a second region, and having a silicon-on-insulator (SOI) structure;
a first gate on the first region of the substrate;
a second gate on the second region of the substrate;
a first source/drain on the first region of the substrate;
a second source/drain on the second region of the substrate;
a plurality of first insulating spacers on sidewalls of the first gate;
a plurality of second insulating spacers on sidewalls of the second gate; and
a plurality of air spacers between the plurality of first insulating spacers and the first source/drain,
wherein no air spacer is between the plurality of second insulating spacers and the second source/drain.

US Pat. No. 11,069,684

STACKED FIELD EFFECT TRANSISTORS WITH REDUCED COUPLING EFFECT

International Business Ma...


1. A method for forming a semiconductor structure, comprising:forming a first set of nanosheet layers and a second set of nanosheet layers on a substrate, wherein each of the first set of nanosheet layers and the second set of nanosheet layers comprises alternating silicon layers and silicon-germanium layers, and wherein the first set of nanosheet layers and the second set of nanosheet layers are separated by a first sacrificial isolation layer;
forming a bottom source/drain region on the substrate and in contact with the first set of nanosheet layers;
forming a second sacrificial isolation layer on at least the bottom source/drain region;
forming a top source/drain region on at least a portion of the second sacrificial isolation layer;
depositing an interlevel dielectric layer on the top source/drain region and the second sacrificial isolation layer;
forming one or more trenches in the interlevel dielectric layer and exposing a top surface of the second sacrificial isolation layer; and
removing the second sacrificial isolation layer to form an air gap positioned between the bottom source/drain region and the top source/drain region.

US Pat. No. 11,069,683

SELF RESTORING LOGIC STRUCTURES

ICs LLC, McCall, ID (US)...


1. A Self Restoring Logic (SRL) latch formed of three NMOS and PMOS structures having a first latch with a first NMOS structure adjacent a first PMOS structure to form a first logic section, a second latch with a second NMOS structure adjacent a second PMOS structure to form a second logic section wherein the first and second NMOS structures are adjacent one another, and a third latch with a third NMOS structure adjacent a third PMOS structure to form a third logic section wherein the second and third PMOS structures are adjacent one another, wherein the latch is adapted to have alternating logic with a state assignment of 010 and 101, further wherein outputs of the first and third logic sections are the same and an output of the second logic section is the logical complement of the outputs of the first and third logic sections.

US Pat. No. 11,069,682

MULTI-FIN FINFET DEVICE INCLUDING EPITAXIAL GROWTH BARRIER ON OUTSIDE SURFACES OF OUTERMOST FINS AND RELATED METHODS

STMICROELECTRONICS, INC.,...


1. A device, comprising:a substrate;
a plurality of fins over the substrate, the plurality of fins including a first fin and a second fin, the first fin including a first sidewall surface and a second sidewall surface opposite to the first sidewall surface, the second fin including a third sidewall surface and a fourth sidewall surface opposite to the third sidewall surface, the second sidewall surface of the first fin facing the third sidewall surface of the second fin;
a gate over the plurality of fins;
a plurality of epitaxial source and drain structures positioned between the plurality of fins, ones of the plurality of epitaxy source and drain structures contacting the third sidewall surface and the second sidewall surface; and
an epitaxial growth barrier layer over the first sidewall surface of the first fin and on an upper portion only of the second sidewall of the first fin.

US Pat. No. 11,069,681

INTEGRATED CIRCUIT DEVICE

Samsung Electronics Co., ...


1. An integrated circuit device comprising:a fin-type active region extending lengthwise in a first direction;
a plurality of nanosheets overlapping each other in a second direction on a fin top surface of the fin-type active region; and
a source/drain region on the fin-type active region and facing the plurality of nanosheets in the first direction,
wherein the plurality of nanosheets comprises a first nanosheet, which is closest to the fin top surface of the fin-type active region and has a shortest length in the first direction, from among the plurality of nanosheets, and
wherein the source/drain region comprises a source/drain main region and a first source/drain protruding region protruding from the source/drain main region, wherein the first source/drain protruding region protrudes from the source/drain main region toward the first nanosheet to overlap portions of the plurality of nanosheets in the second direction,
wherein the source/drain region comprises a first semiconductor layer doped with a first dopant of a first conductivity type,
wherein the first nanosheet comprises a second semiconductor layer doped with a second dopant of the first conductivity type, and
wherein nanosheets other than the first nanosheet, from among the plurality of nanosheets, comprise an undoped third semiconductor layer.

US Pat. No. 11,069,680

FINFET-BASED INTEGRATED CIRCUITS WITH REDUCED PARASITIC CAPACITANCE

International Business Ma...


1. An integrated circuit comprising:a first set of fins protruding upward from a substrate;
a second set of fins protruding upward from the substrate, discrete from the first set of fins;
a gate passing above the first set of fins and the second set of fins; and
a dielectric plug surrounded by the gate on two sides where the gate passes between the first set of fins and the second set of fins,
wherein the gate protrudes in a first portion and a second portion on opposite sides of the dielectric plug, and the first portion is closer to the substrate than is the second portion.

US Pat. No. 11,069,679

REDUCING GATE RESISTANCE IN STACKED VERTICAL TRANSPORT FIELD EFFECT TRANSISTORS

International Business Ma...


1. A method for forming a stacked semiconductor device structure, the method comprising at least:forming, on a substrate, a first vertical transport field effect transistor (VTFET) comprising at least a first gate structure having a first gate length;
forming an insulating layer on the first VTFET; and
forming a second VTFET stacked on the first VTFET and comprising at least a second gate structure having a second gate length that is less than the first gate length,
wherein the insulating layer insulates a first semiconductor fin of the first VTFET from a second semiconductor fin of the second VTFET.

US Pat. No. 11,069,678

LOGIC GATE CELL STRUCTURE

Qorvo US, Inc., Greensbo...


1. A logic gate cell structure comprising:a substrate;
a channel layer disposed over the substrate;
a field-effect transistor (FET) contact layer disposed over the channel layer and divided by an isolation region into a first portion within a single contact region and a second portion within a combined contact region, wherein a gate contact is disposed within the isolation region over the channel layer, and the channel layer and the FET contact layer form part of a FET device;
a first etch stop layer disposed over the second portion of the FET contact layer within the combined contact region, wherein the first etch stop layer has a dopant atom concentration that is in the range from 4×1018 cm?3 to 5×1018 cm?3;
a sub-collector layer disposed within the combined contact region and directly onto the first etch stop layer to provide a shorted current path between the gate contact and a combined collector/source contact disposed over the sub-collector layer;
a collector layer disposed over the sub-collector layer, wherein the collector layer has the same type of doping as the first etch stop layer;
a base layer disposed over the collector layer; and
an emitter layer disposed over the base layer, wherein the sub-collector, the collector layer, the base layer, and the emitter layer form part of a bipolar junction transistor.

US Pat. No. 11,069,676

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

NANYA TECHNOLOGY CORPORAT...


1. A semiconductor device, comprising:a first gate structure comprising a first gate bottom insulating layer inwardly positioned, a first gate top insulating layer positioned on the first gate bottom insulating layer, a first gate top conductive layer positioned on the first gate top insulating layer, and a first gate filler layer positioned on the first gate top conductive layer; and
a capacitor structure comprising a capacitor bottom insulating layer inwardly positioned, a capacitor bottom conductive layer positioned on the capacitor bottom insulating layer, a capacitor top insulating layer positioned on the capacitor bottom conductive layer, a capacitor top conductive layer positioned on the capacitor top insulating layer, and a capacitor filler layer positioned on the capacitor top conductive layer;
wherein the first gate bottom insulating layer is formed of a same material as the capacitor bottom insulating layer.

US Pat. No. 11,069,675

ESD PROTECTION DEVICE WITH BIDIRECTIONAL DIODE STRING-TRIGGERING SCR STRUCTURE

JIANGNAN UNIVERSITY, Wux...


1. An ESD protection device for bidirectional diode string triggering SCR structure, comprising:a diode string formed by a well splitting technique,
a bidirectional SCR structure; and
a metal wire,
wherein the bidirectional SCR structure and the diode string comprise a P substrate, a deep N well, a first P well, a first N well, a second P well, a second N well, a first P+ implantation region, a first N+ implantation region, a second P+ implantation region, a second N+ implantation region, a third P+ implantation region, a third N+ implantation region, a fourth P+ implantation region and a fourth N+ implantation region, wherein the deep N well is arranged on the P substrate, and the first P well, the first N well, the second P well and the second N well are successively arranged from left to right on a surface region of the deep N well; the left edge of the first P well is connected with the left edge of the deep N well; the right side of the first P well is connected with the left side of the first N well; the right side of the first N well is connected with the left side of the second P well; the right edge of the second P well is connected with the left side of the second N well; the right edge of the second N well is connected with the right edge of the deep N well; the first P+ implantation region and the first N+ implantation region are successively arranged from left to right on the surface region of the first P well; the second P+ implantation region and the second N+ implantation region are successively arranged from left to right on the surface region of the first N well; the third P+ implantation region and the third N+ implantation region are successively arranged from left to right on the surface region of the second P well; the fourth P+ implantation region and the fourth N+ implantation region are successively arranged from left to right on the surface region of the second N well,
wherein, in the second N well region, a mask preparing plate is used to insert a plurality of P wells at intervals; the circumference of each P well is isolated by the N well; different quantities of diodes are prepared to form a diode string which assists a departure path to effectively suppress the Darlington effect; the surface region of each P well is respectively provided with a pair of P+ implantation region and N+ implantation region; trigger voltage is controlled by increasing or decreasing the number of diodes formed by well splitting,
wherein the metal wire is used to connect the implantation region, and lead out two electrodes from the metal wire respectively as the forward conduction and reverse conduction of the ESD protection device, to ensure that a diode formed by well splitting assists a trigger path in conducting, thereby reducing the trigger voltage and turn-on time of the ESD protection device,
wherein when the ESD protection device is a bidirectional three-diode triggering SCR structure, in the second N well region, along the Z-axis direction of the ESD protection device, the third P well, the third N well, the fourth P well, the fourth N well, the fifth P well, the fifth N well and the sixth N well are successively inserted on the right side; the fifth P+ implantation region, the fifth N+ implantation region, the sixth P+ implantation region, the sixth N+ implantation region, the seventh P+ implantation region and the seventh N+ implantation region are respectively inserted into the P well,
wherein the lower side of the second N well is connected with the lower side of the deep N well; the upper side of the second N well is connected with the lower side of the third P well; the upper side of the third P well is connected with the lower side of the third N well; the upper side of the third N well is connected with the lower side of the fourth P well; the upper side of the fourth P well is connected with the lower side of the fourth N well; the upper side of the fourth N well is connected with the lower side of the fifth P well; the upper side of the fifth P well is connected with the lower side of the fifth N well; the upper side of the fifth N well is connected with the upper side of the deep N well; the fifth P+ implantation region and the fifth N+ implantation region are successively arranged from bottom to top on the surface region of the third P well; the sixth P+ implantation region and the sixth N+ implantation region are successively arranged from bottom to top on the surface region of the fourth P well; the seventh P+ implantation region and the seventh N+ implantation region are successively arranged from bottom to top on the surface region of the fifth P well,
wherein the first N+ implantation region is connected with first metal; the second P+ implantation region is connected with second metal; the second N+ implantation region is connected with third metal; the third N+ implantation region is connected with fourth metal; the fourth P+ implantation region is connected with fifth metal; the fourth N+ implantation region is connected with sixth metal; the first P+ implantation region is connected with seventh metal; the third P+ implantation region is connected with eighth metal; the fifth P+ implantation region is connected with ninth metal; the fifth N+ implantation region is connected with tenth metal; the sixth P+ implantation region is connected with eleventh metal; the sixth N+ implantation region is connected with twelfth metal; the seventh P+ implantation region is connected with thirteenth metal; the seventh N+ implantation region is connected with fourteenth metal,
wherein the third metal, the sixth metal and the ninth metal are connected with the seventeenth metal; the seventh metal, the eighth metal and the fourteenth metal are connected with the twentieth metal; the tenth metal and the eleventh metal are connected with the eighteenth metal; the twelfth metal and the thirteenth metal are connected with the nineteenth metal,
wherein the first metal and the second metal are connected with the fifteenth metal, and a first electrode is led out from the fifteenth metal, and used as a metal anode of the ESD protection device—conducted forward or a metal cathode—conducted reversely,
wherein the fourth metal and the fifth metal are connected with the sixteenth metal; a second electrode is led out from the sixteenth metal, and used as a metal cathode of the ESD protection device—conducted forward or a metal anode—conducted reversely,
wherein when the first electrode is used as the metal anode of the ESD protection device and the second electrode is used as the metal cathode of the ESD protection device, the first N+ implantation region and the first P well, the first N well and the second P well, the second N well and the fourth P+ implantation region respectively form reverse bias PN junctions,
wherein the reverse bias PN junction formed by the first N well and the second P well is an avalanche breakdown junction of the SCR, and the diode formed by the well splitting assists the trigger path in conducting, thereby reducing the trigger voltage and turn-on time of the ESD protection device,
wherein when the first electrode is used as the metal cathode of the ESD protection device and the second electrode is used as the metal anode of the ESD protection device, the third N+ implantation region and the second P well, the first N well and the second P+ implantation region, the first N well and the first P+ well respectively form reverse bias PN junctions, and
wherein the reverse bias PN junction formed by the first N well and the first P well is an avalanche breakdown junction of the SCR, and the diode formed by the well splitting assists the trigger path in conducting, thereby reducing the trigger voltage and turn-on time of the ESD protection device.

US Pat. No. 11,069,674

SEMICONDUCTOR DEVICE

INFINEON TECHNOLOGIES AG,...


1. A semiconductor device comprising:“n” pairs of pn-junction structures, with n is an integer?2, wherein the i-th pair, with i?{1, . . . , n}, comprises two pn-junction structures of the i-th type, wherein the two pn-junction structures of the i-th type are anti-serially connected,
wherein the pn-junction structure of the i-th type comprises an i-th junction grading coefficient mi,
wherein at least a first pair of the n pairs of pn-junction structures comprises a first junction grading coefficient with m1?0.48 and a second pair of the n pairs of pn-junction structures comprises a second junction grading coefficient m2?0.52, and
wherein the junction grading coefficients m1, m2 of the first and second pair of the n pairs of pn-junction structures result in generation of a spurious third harmonic signal of the semiconductor device with a signal power level, which is at least 10 dB lower than a reference signal power level of the spurious third harmonic signal obtained for a reference case in which the first and second junction grading coefficients m1, m2 are 0.25.

US Pat. No. 11,069,673

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...


1. A package comprising:at least one semiconductor die encapsulated by a molding compound;
a redistribution layer, disposed on the molding compound and over a front-side of the at least one semiconductor die and electrically connected with the at least one semiconductor die; and
a backside film, disposed on the molding compound and over a backside of the at least one semiconductor die, wherein the backside film that is located on the at least one semiconductor die includes trenches, and bottoms of the trenches are free of a conductor.

US Pat. No. 11,069,672

LAMINATED ELEMENT MANUFACTURING METHOD

HAMAMATSU PHOTONICS K.K.,...


1. A laminated element manufacturing method comprising:a first forming step of preparing a first wafer as a semiconductor wafer including a semiconductor substrate having a front surface and a back surface, and a circuit layer including a plurality of functional elements two-dimensionally arranged along the front surface, and forming a first gettering region for each of the functional elements by irradiating the semiconductor substrate of the first wafer with a laser light so as to correspond to each of the functional elements;
a first grinding step of grinding the semiconductor substrate of the first wafer and removing a portion of the first gettering region, after the first forming step;
a bonding step of preparing a second wafer as the semiconductor wafer and bonding the circuit layer of the second wafer to the semiconductor substrate of the first wafer such that each of the functional elements of the first wafer correspond to each of the functional elements of the second wafer, after the first grinding step;
a second forming step of forming a second gettering region for each of the functional elements by irradiating the semiconductor substrate of the second wafer with a laser light so as to correspond to each of the functional elements, after the bonding step; and
a second grinding step of grinding the semiconductor substrate of the second wafer and removing a portion of the second gettering region, after the second forming step.

US Pat. No. 11,069,671

SEMICONDUCTOR PACKAGE AND METHOD

Taiwan Semiconductor Manu...


1. A method comprising:aligning a first package component with a second package component, the first package component having a first region and a second region, the first region comprising a first conductive connector, the second region comprising a second conductive connector;
performing a first laser shot on a first portion of a top surface of the first package component, the first laser shot reflowing the first conductive connector of the first region, the first portion of the top surface of the first package component completely overlapping the first region, wherein performing the first laser shot comprises:directing a laser beam at the first portion of the top surface of the first package component until the first conductive connector reflows; and
after the first conductive connector reflows, turning off the laser beam until the first conductive connector solidifies; and

after performing the first laser shot, performing a second laser shot on a second portion of the top surface of the first package component, the second laser shot reflowing the second conductive connector of the second region, the second portion of the top surface of the first package component completely overlapping the second region.

US Pat. No. 11,069,670

CAMERA ASSEMBLY AND PACKAGING METHOD THEREOF, LENS MODULE, AND ELECTRONIC DEVICE

Ningbo Semiconductor Inte...


1. A method for packaging a camera assembly, comprising:providing a photosensitive chip;
mounting an optical filter on the photosensitive chip;
temporarily bonding the photosensitive chip and functional components on a carrier substrate, wherein the photosensitive chip has soldering pads facing away from the carrier substrate and the functional components have soldering pads facing toward the carrier substrate;
forming an encapsulation layer covering the carrier substrate, the photosensitive chip, and the functional components, and exposing the optical filter;
after the encapsulation layer is formed, removing the carrier substrate; and
after the carrier substrate is removed, forming a redistribution layer structure on a side of the encapsulation layer facing away from the optical filter to electrically connect the soldering pads of the photosensitive chip with the soldering pads of the functional components,
wherein after bonding the photosensitive chip and the functional components on the carrier substrate, forming a stress buffering layer on sidewall of the optical filter between the sidewall of the optical filter and the soldering pads of the photosensitive chip, wherein:
the stress buffering layer is formed on the sidewall of the optical filter before the optical filter is mounted on the photosensitive chip; or
the stress buffering layer is formed on the sidewall of the optical filter after the photosensitive chip is temporarily bonded on the carrier substrate and before the encapsulation layer is formed.

US Pat. No. 11,069,669

MICRO LED DISPLAY PANEL AND METHOD FOR MAKING SAME

HON HAI PRECISION INDUSTR...


1. A micro LED display panel, comprising:a blue LED layer, the blue LED layer comprising a plurality of blue micro LEDs spaced apart from each other, each of the plurality of blue micro LEDs defining a blue sub-pixel;
a green LED layer, the green LED layer comprising a plurality of green micro LEDs spaced apart from each other, each of the plurality of green micro LEDs defining a green sub-pixel; and
a red LED layer, the red LED layer comprising a plurality of red micro LEDs spaced apart from each other, each of the plurality of red micro LEDs defining a red sub-pixel;
wherein the blue LED layer, the green LED layer, and the red LED layer are stacked one by one along a depth direction of the micro LED display panel; and
each of the plurality of blue micro LEDs, each of the plurality of green micro LEDs, and each of the plurality of red micro LEDs are staggered from each other;
wherein the blue LED layer comprises a first transparent conductive layer, a first light emitting layer, and a first electrode layer stacked one by one along the depth direction; the first light emitting layer is provided between the first transparent conductive layer and the first electrode layer; the first light emitting layer comprises an N-type doped inorganic light emitting layer, an active layer, and a P-type doped inorganic light emitting layer stacked one by one along the depth direction; the active layer is provided between the P-type doped inorganic light emitting layer and the N-type doped inorganic light emitting layer; the N-type doped inorganic light emitting layer comprises a plurality of N-type doped units spaced apart from each other; the first electrode layer comprises a plurality of electrodes spaced apart from each other; each of the plurality of N-type doped units is coupled to the first transparent conductive layer; the P-type doped inorganic light emitting layer is coupled to each of the plurality of electrodes; a projection of each of the plurality of N-type doped units on the first electrode layer overlaps with one of the plurality of electrodes; a portion of the blue LED layer corresponding to one of the plurality of N-type doped units defines one blue sub-pixel.

US Pat. No. 11,069,668

ELECTRONIC DEVICE FOR REDUCING A BORDER EDGE OF THE NON-DISPLAY AREAS

INNOLUX CORPORATION, Mia...


1. An electronic device, comprising:a display area;
a non-display area adjacent to the display area;
a plurality of first signal lines, and each of the plurality of first signal lines comprising:
a first section extending in a first direction; and
a second section extending in a second direction different from the first direction; wherein from a top view of the electronic device, the second section crosses the first section;
a plurality of second signal lines extending in the second direction and sequentially arranged in the first direction;
wherein the plurality of first signal lines are scan lines and the plurality of second signal lines are data lines, or the plurality of first signal lines are data lines and the plurality of second signal lines are scan lines; and
wherein each of the second sections of the plurality of first signal lines is disposed between any two of the plurality of second signal lines, and all of the second sections of the plurality of first signal lines are disposed between part of the plurality of second signal lines.

US Pat. No. 11,069,667

WAFER LEVEL PROXIMITY SENSOR

STMICROELECTRONICS PTE LT...


16. A wafer level proximity micro-sensor module, comprising:a back-grinded silicon substrate having a first surface opposite a second surface;
a light sensor at the first surface of the back-grinded silicon substrate, the light sensor including a surface substantially co-planar with the first surface of the back-grinded silicon substrate;
a first contact pad at the first surface of the silicon substrate;
a light emitter coupled to the first contact pad;
a cap coupled to the first surface of the silicon substrate, the cap including a third surface opposite to the first surface of the silicon substrate, a first opening aligned with the light emitter and a second opening aligned with the light sensor, the first opening having a width proximate the light emitter that is greater than a width of the light emitter; and
a first transparent portion fills the first opening and covers the light emitter, a second transparent portion fills the second opening and covers the light sensor, the first transparent portion has a fourth surface, the second transparent portion has a fifth surface, and the fourth surface and the fifth surface are substantially flush with the third surface of cap, the first transparent portion is in direct physical contact with a surface of the first contact pad, and the second transparent portion is in direct physical contact with the light sensor;
wherein the back-grinded substrate and the cap are singulated to yield the wafer level proximity micro-sensor module, and a thickness of the wafer level proximity micro-sensor module extends between the second surface of the back-grinded silicon substrate and the third surface of the cap, the thickness is in the range of 0.4 and 0.6 millimeters.

US Pat. No. 11,069,666

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...


1. A semiconductor package, comprising:a frame having a through-hole;
a first semiconductor chip disposed in the through-hole of the frame, and having an active surface on which a connection pad is disposed, an inactive surface opposing the active surface, and a side surface connecting the active and inactive surfaces;
a first encapsulant covering at least a portion of each of the inactive surface and the side surface of the first semiconductor chip;
a connection structure having a first surface having disposed thereon the active surface of the first semiconductor chip and a first surface of the frame, and including an insulating layer, a redistribution layer disposed on the insulating layer, and at least one via extending from the redistribution layer through the insulating layer to directly contact and electrically connect to the connection pad of the first semiconductor chip;
a first passive component disposed on a second surface of the connection structure opposing the first surface of the connection structure, the first passive component being electrically connected to the redistribution layer;
a second passive component disposed on the first surface of the connection structure and electrically connected to the redistribution layer; and
a plurality of metal pads protruding from a second surface of the frame opposing the first surface of the frame, each metal pad having a respective electrical connection metal thereon,
wherein the connection structure has a first thickness, measured between the first and second surfaces thereof, in a first region having the first semiconductor chip thereon, and a second thickness, measured between the first and second surfaces thereof, different from the first thickness, in a second region having the second passive component thereon, the second passive component including at least one of a Multilayer Ceramic Capacitor (MLCC), a capacitor, an inductor, or a bead,
wherein the frame has an additional through-hole spaced apart from the through-hole in which the first semiconductor chip is disposed,
the second passive component is disposed in the additional through-hole of the frame, the second passive component having a thickness smaller than a thickness of the first semiconductor chip, and
the connection structure has the first thickness throughout a region facing the through-hole of the frame, and has the second thickness higher than the first thickness throughout a region facing the additional through-hole of the frame.

US Pat. No. 11,069,664

MICRO-LED MODULE AND METHOD FOR FABRICATING THE SAME

LUMENS CO., LTD., Yongin...


1. A micro-LED module comprising:a micro-LED comprising:a plurality of LED cells arrayed in a matrix, each of the plurality of LED cells comprising an n-type semiconductor layer, an active layer, and a p-type semiconductor layer;
a plurality of p-type electrode pads on the p-type semiconductor layers of the plurality of LED cells; and
an n-type electrode pad formed in an exposed area of the n-type semiconductor layer, the exposed area being formed along a peripheral edge of the micro-LED;

an active matrix substrate comprising:a plurality of individual electrode pads corresponding to the plurality of p-type electrode pads of the micro-LED;
a common electrode pad corresponding to the n-type electrode pad of the micro-LED;
a plurality of first pillars corresponding to the plurality of individual electrode pads; and
a second pillar corresponding to the common electrode pad;

a plurality of first solder bonding portions bonding each of the plurality of first pillars of the active matrix substrate to the corresponding p-type electrode pad of the micro-LED; and
a second solder bonding portion bonding the second pillar of the active matrix substrate to the n-type electrode pad of the micro-LED,
wherein a maximum cross-sectional diameter of each of the plurality of first solder bonding portions is larger than a diameter of the corresponding first pillar, and a minimum cross-sectional diameter of each of the plurality of first solder bonding portions is larger than 80% and smaller than 100% of the diameter of the corresponding first pillar.

US Pat. No. 11,069,663

METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND OPTOELECTRONIC SEMICONDUCTOR COMPONENT

OSRAM OLED GmbH, Regensb...


1. A method of producing an optoelectronic semiconductor component comprising:A) providing at least three source substrates, wherein each of the source substrates is equipped with a specific type of radiation-emitting semiconductor chips,
B) providing a target substrate having a mounting plane configured to mount the semiconductor chips thereto,
C) forming platforms on the target substrate, and
D) transferring at least some of the semiconductor chips with a wafer-to-wafer process from the source substrates onto the target substrate so that the semiconductor chips transferred to the target substrate maintain their relative position with respect to one another, within the types of semiconductor chips, wherein
on the target substrate the semiconductor chips of each type of semiconductor chips have a specific height above the mounting plane due to the platforms so that the semiconductor chips of different types of semiconductor chips have different heights,
only after the transfer of the semiconductor chips of a first to a penultimate type of semiconductor chips and before the semiconductor chips of the respective next type of semiconductor chips are transferred, one of each type of platform is produced, and
at least the semiconductor chips of one of the types of semiconductor chips are detached from the respective source substrate by a laser lift-off method so that a laser radiation is irradiated through the associated source substrate.

US Pat. No. 11,069,662

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...


1. A semiconductor package, comprising:a first chip package, comprising:a plurality of first semiconductor dies, electrically connected to each other; and
a first insulating encapsulant, encapsulating the plurality of first semiconductor dies;

a second semiconductor die and a third semiconductor die, electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die;
a second insulating encapsulant, encapsulating the second semiconductor die and the third semiconductor die; and
through vias, penetrating the second insulating encapsulant and arranged aside of the second semiconductor die and the third semiconductor die, wherein the through vias are overlapped with the second semiconductor die and the third semiconductor die along a direction perpendicular to a stacking direction of the first chip package and the second semiconductor die.

US Pat. No. 11,069,661

ELECTRONIC PACKAGE

SILICONWARE PRECISION IND...


1. An electronic package, comprising:a carrier;
a first package module disposed on the carrier and including at least one first electronic component, with a first layout area being defined by a lower surface of the first electronic component and provided with one of a first encapsulating portion and a second encapsulating portion, the material of the second encapsulating portion being different from that of the first encapsulating portion; and
a second package module stacked on top of the first package module and including a plurality of second electronic components stacked to each other, with a second layout area being defined by a lower surface of each of the second electronic components, at least one of the plurality of second layout areas being provided with the other one of the first encapsulating portion and the second encapsulating portion relative to the first layout area, wherein a stress balance line is defined between the first package module and the second package module, and the first encapsulating portion and the second encapsulating portion are arranged in a way such that a strain of the first package module and a strain of the second package module are complementary to each other, and a stress of the first package module and a stress of the second package module cancel each other out.

US Pat. No. 11,069,660

DISPLAY DEVICE

Au Optronics Corporation,...


1. A display device, comprising:a first substrate;
a first active element layer, disposed on the first substrate;
a first light-emitting element, a second light-emitting element and a third light-emitting element, electrically connected with the first active element layer, wherein the first light-emitting element includes a first electrode, a first light-emitting layer and a second electrode stacked in sequence, wherein the second light-emitting element includes a first electrode, a second light-emitting layer and a second electrode stacked in sequence, and wherein the third light-emitting element includes a first electrode, a third light-emitting layer and a second electrode stacked in sequence, wherein the second electrodes of the first light-emitting element, the second light-emitting element and the third light-emitting element are electrically connected with each other;
a first pixel defining layer, disposed on the first active element layer and having a first opening, a second opening and a third opening, wherein the first light-emitting layer, the second light-emitting layer and the third light-emitting layer are disposed in the first opening, the second opening and the third opening respectively;
a fourth light-emitting element, a fifth light-emitting element and a sixth light-emitting element, disposed on the first pixel defining layer, wherein the fourth light-emitting element, the fifth light-emitting element and the sixth light-emitting element have a fourth light-emitting layer, a fifth light-emitting layer and a sixth light-emitting layer respectively, the second light-emitting element is disposed between the fourth light-emitting element and the fifth light-emitting element, and the third light-emitting element is disposed between the fifth light-emitting element and the sixth light-emitting element, wherein a vertical distance between the first light-emitting element and the fourth light-emitting element is greater than 0 micrometers and less than or equal to 5 micrometers; and
a plurality of spacers disposed on the first pixel defining layer, and disposed between the first substrate and a second substrate, wherein the spacers space apart from and do not contact the second electrodes of the first light-emitting element, the second light-emitting element, and the third light-emitting element, wherein the second electrode of the first light-emitting element and the second electrode of the fourth light-emitting element with identical polarity are disposed between the first light-emitting layer and the fourth light-emitting layer, the second electrode of the second light-emitting element and the second electrode of the fifth light-emitting element with identical polarity are disposed between the second light-emitting layer and the fifth light-emitting layer, and the second electrode of the third light-emitting element and the second electrode of the sixth light-emitting element with identical polarity are disposed between the third light-emitting layer and the sixth light-emitting layer.

US Pat. No. 11,069,658

SYSTEM ON INTEGRATED CHIPS AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...


1. A package comprising:a first semiconductor die;
a first isolation material around the first semiconductor die;
a second semiconductor die over the first semiconductor die, the first semiconductor die and the second semiconductor die share a first insulator-to-insulator interface and a first metal-to-metal interface, the second semiconductor die and the first isolation material share a second insulator-to-insulator interface;
a second isolation material around the second semiconductor die; and
redistribution layers over the second semiconductor die, the redistribution layers are electrically connected to the first semiconductor die and the second semiconductor die.

US Pat. No. 11,069,657

CHIP PACKAGE HAVING DIE STRUCTURES OF DIFFERENT HEIGHTS AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...


1. A package comprising:a substrate;
a first chip stack attached to the substrate;
a second chip stack attached to the substrate, the first chip stack and the second chip stack being attached to a same side of the substrate; and
a molding compound layer surrounding the first chip stack and the second chip stack, the molding compound layer covering a topmost surface of the first chip stack, a topmost surface of the molding compound layer being substantially level with a topmost surface of the second chip stack.

US Pat. No. 11,069,656

THREE-LAYER PACKAGE-ON-PACKAGE STRUCTURE AND METHOD FORMING SAME

Taiwan Semiconductor Manu...


1. A method comprising:disposing a first package component;
disposing a second package component, wherein at a time after both of the first package component and the second package component are disposed, the first package component and the second package component are on opposite sides of a layer of a first molding compound, wherein the first package component and the second package component are disposed back-to-back, with a first front side of the first package component comprising a first bond pad, and a second front side of the second package component comprising a second bond pad, and wherein the first front side faces away from the second front side, and the second front side faces away from the first front side;
encapsulating the second package component in a second molding compound;
planarizing the second molding compound; and
forming a first plurality of redistribution lines to electrically connect to the second package component, wherein the second package component is between the first plurality of redistribution lines and the first package component.

US Pat. No. 11,069,655

SEMICONDUCTOR DEVICE INCLUDING TWO OR MORE CHIPS MOUNTED OVER WIRING SUBSTRATE

Micron Technology, Inc., ...


1. A semiconductor device comprising:a wiring substrate having first connection pads and second connection pads thereon; and
a composite chip mounted over the wiring substrate, the composite chip including—a first area having a first memory circuit and a plurality of first electrode pads coupled to the first memory circuit, wherein the first electrode pads are coupled to the first connection pads,
a second area having a second memory circuit and a plurality of second electrode pads coupled to the second memory circuit, wherein the second electrode pads are coupled to the second connection pads,
a permanent third area having a first material between the first area and the second area, wherein the first area is spaced apart from the second area by the first material,
a passivation film over the first and second areas so as to expose the first and second electrode pads,
a rewiring pad formed on the passivation film in the first area,
a redistribution wiring formed on the passivation film and coupled between an associated one of the first electrode pads and the rewiring pad, and
an insulating layer over the passivation film and the redistribution wiring so as to expose the rewiring pad,

wherein the first memory circuit and the second memory circuit are substantially free from electrically connecting to each other via the third area; and
wherein the third area has a width in a range of 20 ?m to 80 ?m.

US Pat. No. 11,069,654

METAL FRAME, DUMMY WAFER, SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SONY CORPORATION, Tokyo ...


1. A metal frame, comprising:a plurality of openings, wherein each opening of the plurality of openings includes a plurality of chip-like semiconductor elements; and
a lattice structure including a plurality of frames, whereineach frame of the plurality of frames is between adjacent openings of the plurality of openings,
the plurality of frames includes a set of frames in a dicing area of a dummy wafer, and
frames of the set of frames are in a discontinuous arrangement on a dicing length of the dicing area.


US Pat. No. 11,069,653

METHODS AND STRUCTURES FOR PACKAGING SEMICONDUCTOR DIES

Taiwan Semiconductor Manu...


1. A method of packaging semiconductor dies, the method comprising:attaching a die to a carrier wafer, the die having conductive contact pads on an upper surface thereof;
forming a molding compound layer over the upper surface of the die;
removing an upper portion of the molding compound layer disposed over the conductive contact pads using a first process;
removing a middle portion of the molding compound layer using a second process different from the first process, wherein there is no intervening process to remove the molding compound layer between the first process and the second process, wherein removing the middle portion of the molding compound layer exposes the upper surface of the die, and wherein after removing the middle portion of the molding compound layer, an uppermost surface of a remaining bottom portion of the molding compound layer facing away from the carrier wafer is closer to the carrier wafer than the upper surface of the die, the remaining bottom portion of the molding compound layer surrounding the die; and
forming a redistribution layer (RDL) over the upper surface of the die.

US Pat. No. 11,069,652

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...


1. A method of manufacturing a semiconductor structure, comprising:providing a first substrate including a plurality of conductive bumps disposed over the first substrate;
providing a second substrate;
disposing a patterned adhesive over the first substrate;
bonding the first substrate with the second substrate, wherein at least a portion of the plurality of conductive bumps is exposed through the patterned adhesive; and
singulating a chip from the first substrate.

US Pat. No. 11,069,649

LASER ASSISTED SOLDER BONDING OF DIRECT CONVERSION COMPOUND SEMICONDUCTOR DETECTOR

Detection Technology Oy, ...


1. A method, comprising:configuring a direct conversion compound semiconductor sensor over a first surface of a readout integrated circuit (IC) comprising two surfaces, the first surface of the readout IC and a second surface of the readout IC, the first surface of the readout IC comprising a solder material on the first surface of the readout IC, and the second surface of the readout IC comprising a solder material on the second surface of the readout IC, wherein the direct conversion compound semiconductor sensor is configured over the first surface of the readout IC by bonding, wherein the bonding comprises placing the direct conversion compound semiconductor sensor over the readout IC so that electrical contact points configured on a bottom surface of the direct conversion compound semiconductor sensor match with the solder material on the first surface of the readout IC and applying a physical force on the direct conversion compound semiconductor sensor, and
wherein the physical force applied on the direct conversion compound semiconductor sensor is such that a temporary physical adhesion between the solder material on the first surface of the readout IC and the direct conversion compound semiconductor sensor is configured;
illuminating the solder material on the first surface of the readout IC with an infra-red laser such that the solder material on the first surface of the readout IC melts and forms solder joints between the readout IC and the direct conversion compound semiconductor sensor;
configuring a substrate over the second surface of the readout IC;
and illuminating the solder material on the second surface of the readout IC with the infra-red laser such that the solder material on the second surface of the readout IC melts and electrically connects the readout IC with the substrate; and
wherein the solder material on the first surface of the readout IC and the solder material on the second surface of the readout IC comprises an electronic industry standard high temperature solder alloy.

US Pat. No. 11,069,648

SEMICONDUCTOR STRUCTURE AND METHOD FOR OBTAINING LIGHT EMITTING DIODES RECONSTITUTED OVER A CARRIER SUBSTRATE

IMEC VZW, Leuven (BE)


1. A method for obtaining one or more Light Emitting Diode (LED) devices, reconstituted over a carrier substrate, the method comprising:providing a silicon-based semiconductor substrate as the carrier substrate;
providing a compound semiconductor stack including an LED layer per each of the one or more LED devices;
applying a silicon carbon nitride (SiCN) layer to the stack and the substrate, respectively;
bonding the stack to the substrate by contacting the SiCN layer applied to the stack and the SiCN layer applied to the substrate to form a bonded stack and substrate; and
annealing the bonded stack and substrate at an annealing temperature equal to or higher than a processing temperature for completing the LED device from the stack, wherein the annealing and processing temperatures are at least 400° C.

US Pat. No. 11,069,647

SEMICONDUCTOR WAFER, BONDING STRUCTURE AND WAFER BONDING METHOD

Wuhan Xinxin Semiconducto...


1. A semiconductor wafer, comprising:a semiconductor substrate;
a device structure on the semiconductor substrate, and an interconnection structure for the device structure;
a top cover layer covering the interconnection structure;
a bonding pad disposed in the top cover layer, wherein the bonding pad is arranged in contact with and is connected to the interconnection structure; and
a bonding alignment mark disposed in the top cover layer;
wherein a pattern of the bonding alignment mark comprises a plurality of sub-patterns, each of the plurality of sub-patterns comprises an array of dots, and a smallest distance among the plurality of sub-patterns is greater than a distance between centers of adjacent dots in the array of one of the plurality of sub-patterns.

US Pat. No. 11,069,646

PRINTED CIRCUIT BOARD STRUCTURE HAVING PADS AND CONDUCTIVE WIRE

NANYA TECHNOLOGY CORPORAT...


1. A printed circuit board structure, comprising:a printed circuit board;
a semiconductor chip disposed on the printed circuit board;
a first pad disposed on and electrically connected to the semiconductor chip;
a second pad disposed on the printed circuit board;
a conductive wire electrically connecting the first pad and the second pad; and
a third pad disposed between the first pad and the second pad, wherein the conductive wire has a portion located on the third pad, and wherein the third pad is electrically isolated from the semiconductor chip.

US Pat. No. 11,069,645

ELECTRONIC COMPONENT MODULE

MURATA MANUFACTURING CO.,...


1. An electronic component module, comprising:an electronic component;
a resin structure that covers at least a portion of the electronic component;
a through wire that extends through the resin structure in a predetermined direction;
a wiring layer that electrically connects the electronic component to the through wire and includes a portion located between the electronic component and the through wire in plan view in the predetermined direction; and
a resin layer between the wiring layer and the electronic component, and between the wiring layer and the resin structure; wherein
the wiring layer includes a protruding portion that protrudes in the predetermined direction between the electronic component and the through wire; and
the resin layer covers at least a portion of a surface of the resin structure and at least a portion of a first principal surface of the electronic component.

US Pat. No. 11,069,644

SEMICONDUCTOR DEVICE INCLUDING A SOLDER COMPOUND CONTAINING A COMPOUND SN/SB

Infineon Technologies AG,...


1. A semiconductor device, comprising:a semiconductor die comprising a first surface and a second surface opposite to the first surface;
a first metallization layer disposed on the first surface of the semiconductor die;
a first solder layer disposed on the first metallization layer, wherein the first solder layer contains the compound Sn/Sb, wherein the material composition of the compound Sn/Sb is such that the ratio of Sb in the compound is in a range from 17% to 90%; and
a first contact member comprising a Cu-based base body and a Ni-based layer disposed on a main surface of the Cu-based base body;
wherein the first contact member is connected with the Ni-based layer to the first solder layer.

US Pat. No. 11,069,643

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

FUJI ELECTRIC CO., LTD., ...


1. A semiconductor device manufacturing method, comprising:preparing a conductive plate having a front surface at a front side and a rear surface at a rear side opposite to the front side, the front surface including a first front surface on which a first arrangement region is disposed and a second front surface on which a second arrangement region is disposed, the first front surface having a height measured from the rear surface that is lower than a height of the second front surface measured from the rear surface;
applying an uncured first bonding material to the first arrangement region and an uncured second bonding material different from the uncured first bonding material to the second arrangement region;
disposing a first part on the first arrangement region via the uncured first bonding material and a second part on the second arrangement region via the uncured second bonding material; and
bonding, by heating to cure the uncured first bonding material and the uncured second bonding material, the first part to the first arrangement region via a first bonding material and the second part to the second arrangement region via a second bonding material, wherein
the applying includes:applying, by using a first mask in which a first opening having a shape corresponding to a shape of the first arrangement region is formed to cover a part of the front surface including the second arrangement region, the uncured first bonding material to the first arrangement region via the first opening; and
before curing the uncured first bonding material, applying, by using a second mask in which a second opening having a shape corresponding to a shape of the second arrangement region is formed to cover a part of the front surface including the first arrangement region on which the uncured first bonding material has been applied, the uncured second bonding material to the second arrangement region via the second opening.


US Pat. No. 11,069,642

PACKAGE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...


1. A package structure, comprising:a semiconductor die;
a redistribution circuit structure, located on and electrically connected to the semiconductor die, the redistribution circuit structure comprising a first contact pad having a first width and a second contact pad having a second width;
conductive pads, located on and electrically connected to the redistribution circuit structure through connecting to the first contact pad and the second contact pad, the redistribution circuit structure being located between the conductive pads and the semiconductor die;
an insulating encapsulation, encapsulating the semiconductor die and located on the redistribution circuit structure; and
conductive pillars, penetrating through the insulating encapsulation and electrically connected to the redistribution circuit structure,
wherein in a projection on the redistribution circuit structure along a stacking direction of the semiconductor die and the redistribution circuit structure, a positioning location of the first contact pad is aside of a positioning location of the semiconductor die and overlapped with a positioning location of the insulating encapsulation and a positioning location of the conductive pillars, and a positioning location of the second contact pad is overlapped with the positioning location of the semiconductor die,
wherein the first width of the first contact pad is less than a width of the conductive pads, and the second width of the second contact pad is substantially equal to or greater than the width of the conductive pads.

US Pat. No. 11,069,641

INTEGRATED CIRCUIT PACKAGE AND DISPLAY DEVICE USING THE SAME

LG DISPLAY CO., LTD., Se...


1. An integrated circuit package comprising:an integrated circuit,
wherein a bottom surface of the integrated circuit package includes:an input bump area in which a plurality of input bumps are arranged;
an output bump area in which a plurality of output bumps are arranged, the output bump area being separated from the input bump area;
a first barrier bump area in which a plurality of input barrier bumps are arranged, the first barrier bump area disposed between the input bump area and the output bump area;
a second barrier bump area in which a plurality of output barrier bumps are arranged, disposed between the first barrier bump area and the output bump area; and
a side barrier bump area in which a plurality of side barrier bumps are arranged without the input bumps and the output bumps, and respectively disposed in a region defined by both ends of the input bump area and both ends of the output bump area,

wherein the first barrier bump area is closer to the input bump area than the second barrier bump area, and the second barrier bump area is closer to the output bump area than the first barrier bump area, and
wherein each the input barrier bumps has a first width wider than that of each the input bumps, and each the output barrier bumps has a second width wider than that of each the output bumps.

US Pat. No. 11,069,640

PACKAGE FOR POWER ELECTRONICS

Cree Fayetteville, Inc., ...


1. A package for power electronics comprising:a power substrate;
at least two power semiconductor die on the power substrate, each one of the at least two power semiconductor die comprising:a first power switching pad and a second power switching pad;
a control pad;
a semiconductor structure between the first power switching pad, the second power switching pad, and the control pad, the semiconductor structure configured such that a resistance of a power switching path between the first power switching pad and the second power switching pad is based on a control signal provided at the control pad; and
a Kelvin connection pad coupled to the second power switching pad on the power semiconductor die;

a Kelvin conductive trace on the power substrate;
a Kelvin connection contact coupled to the Kelvin connection pad of each one of the at least two power semiconductor die via the Kelvin conductive trace; and
a control conductive trace coupled to the control pad, wherein the control conductive trace is arranged on the power substrate and between the first power switching pad and the Kelvin conductive trace.

US Pat. No. 11,069,639

SEMICONDUCTOR MODULE, ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING A SEMICONDUCTOR MODULE

Infineon Technologies Aus...


1. A method, comprising:forming at least one trench in separation regions of a first surface of a semiconductor wafer;
forming at least one trench in non-device regions of the first surface of the semiconductor wafer, the separation regions being arranged between component positions of the semiconductor wafer, the component positions comprising at least two electronic devices for forming a circuit, a non-device region arranged between a first device region comprising a first electronic device and a second device region comprising a second electronic device, and a first metallization structure arranged on the first surface in the first device region and in the second device region;
applying a first epoxy layer to the first surface of the semiconductor wafer such that the at least one trench in separation regions, the at least one trench in non-device regions, edge regions of the component positions, edge regions of the first device region and edge regions of the second device region are covered with the first epoxy layer;
removing portions of a second surface of the semiconductor wafer, the second surface opposing the first surface, to reveal portions of the first epoxy layer in the separation regions and in the non-device regions and to produce a worked second surface;
applying a second metallization layer to the worked second surface and operably coupling the first electronic device to the second electronic device to form the circuit;
inserting a separation line through the first epoxy layer in the separation regions to form a plurality of separate semiconductor modules comprising the circuit;
inserting conductive material into the at least one trench formed in the non-device regions; and
electrically coupling the conductive material to the first electronic device and to the second electronic device.

US Pat. No. 11,069,638

METHOD FOR FABRICATING THE ELECTRONIC COMPONENT, AND METHOD FOR TRANSPOSING A MICRO-ELEMENT

AU OPTRONICS CORPORATION,...


1. A method for fabricating an electronic component, comprising:providing a circuit substrate; and
forming a connecting electrode with a plurality of micro-protrusions on the circuit substrate, comprising:forming a first transparent conductive film on the circuit substrate;
patterning the first transparent conductive film to form a first transparent conductive pattern;
performing subcritical annealing on the first transparent conductive pattern; and
etching the first transparent conductive pattern to form a first transparent conductive layer with a plurality of micrometers or nanometer particles.


US Pat. No. 11,069,636

PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...


1. A package structure, comprising:a die;
an encapsulant encapsulating sidewalls of the die;
a first polymer material layer on the encapsulant and the die;
a second polymer material layer on the first polymer material layer; and
a first redistribution layer embedded in the first polymer material layer and the second polymer material layer and electrically connected to the die,
wherein the first redistribution layer has a top surface substantially coplanar with a top surface of the second polymer material layer, and a portion of a top surface of the first polymer material layer is in contact with the first redistribution layer.

US Pat. No. 11,069,635

RADIO FREQUENCY TRANSISTOR AMPLIFIERS AND OTHER MULTI-CELL TRANSISTORS HAVING ISOLATION STRUCTURES

Cree, Inc., Durham, NC (...


1. A multi-cell transistor, comprising:a semiconductor structure;
a plurality of unit cell transistors that are electrically connected in parallel, each unit cell transistor including a gate finger that extends in a first direction on a top surface of the semiconductor structure;
a gate runner that is electrically connected to a first gate finger of the gate fingers, the gate runner configured to be coupled to a gate signal at an interior position of the gate runner; and
an isolation structure on the top surface of the semiconductor structure between adjacent ones of the unit cell transistors, the isolation structure having a height from the top surface of the semiconductor structure that exceeds a height of the gate runner from the top surface of the semiconductor structure,
wherein the gate fingers of the unit cell transistors are spaced apart from each other along a second direction and arranged on the top surface of the semiconductor structure in a plurality of groups.

US Pat. No. 11,069,634

AMPLIFIER AND AMPLIFICATION APPARATUS

FUJITSU LIMITED, Kawasak...


1. An amplifier comprising:an amplifier circuit configured to include a transistor that amplifies a signal;
an insulating film provided over the amplifier circuit;
an input pad provided over the insulating film and coupled to the transistor through a wiring in the insulating film;
an output pad provided over the insulating film and coupled to the transistor through the wiring in the insulating film; and
a metal layer provided over the insulating film to be grounded, and configured to include an opening that extends in a second direction intersecting with a first direction in a plane direction, the signal propagating from the input pad to the output pad in the first direction, and the opening being at a position overlapping the transistor.

US Pat. No. 11,069,633

ELECTRONIC PACKAGE

Siliconware Precision Ind...


1. An electronic package, comprising:a carrier;
at least one electronic component disposed on the carrier;
an antenna structure disposed on and electrically connected with the carrier, wherein the antenna structure includes a metal frame provided upright on the carrier and a wire provided on the carrier and electrically connected with the metal frame;
a buffer covering the wire and free from being electrically connected with the antenna structure, wherein the buffer is an insulator to slow an emission wave speed of the wire, and the buffer is free from covering the electronic component; and
an encapsulant formed on the carrier and covering the electronic component, the buffer, and the antenna structure.

US Pat. No. 11,069,632

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...


1. An array substrate, comprising:a plurality of shielding layers disposed on a substrate and arranged at intervals;
a dielectric layer spread on the substrate and covering the shielding layers, the dielectric layer comprising a plurality of dielectric patterns, the dielectric patterns comprising main dielectric patterns and auxiliary dielectric patterns disposed on at least one side of the main dielectric patterns; and
a gate insulating layer disposed on the dielectric layer;
wherein the main dielectric patterns partially overlap the shielding layer to form overlapping areas and non-overlapping areas, the auxiliary dielectric patterns do not overlap the shielding layer, and the auxiliary dielectric patterns are disposed among adjacent main dielectric patterns;
wherein the dielectric layer is used to absorb static electricity in the gate insulating layer, and cross-sectional areas of the auxiliary dielectric patterns are greater than cross-sectional areas of the main dielectric patterns.

US Pat. No. 11,069,631

THREE-DIMENSIONAL MEMORY DIE CONTAINING STRESS-COMPENSATING SLIT TRENCH STRUCTURES AND METHODS FOR MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...


1. A semiconductor die comprising:a plurality of alternating stacks of insulating layers and electrically conductive layers that are located over a substrate and that laterally extend along a first horizontal direction and that are laterally spaced apart along a second horizontal direction which is perpendicular to the first horizontal direction;
a plurality of sets of memory stack structures extending through the plurality of alternating stacks; and
a plurality of nested seal ring structures comprising:a first seal ring structure comprising having a first seal ring width between an inner sidewall and an outer sidewall thereof; and
a second seal ring structure having a second seal ring width between an inner sidewall and an outer sidewall thereof, wherein the first seal ring width is less than the second seal ring width;

wherein:each of the plurality of nested seal ring structures comprises a respective pair of first sidewall segments that are parallel to first sidewalls of the semiconductor die, and a respective pair of second sidewall segments that are perpendicular to the first sidewalls of the semiconductor die;
a first void extends inside at least one of the first sidewall segments of the first seal ring structure;
the first sidewall segments of the first seal ring structure have the first seal ring width;
the second sidewall segments of the first seal ring structure have an additional seal ring width that is greater than the first seal ring width;
the first void has a first void width; and
each of the second sidewall segments includes a second void that has a second void width that is less than the first void width.


US Pat. No. 11,069,630

STRUCTURES AND METHODS FOR REDUCING THERMAL EXPANSION MISMATCH DURING INTEGRATED CIRCUIT PACKAGING

Taiwan Semiconductor Manu...


1. A semiconductor structure, comprising:a first metal layer comprising a first device metal structure over a substrate;
a dielectric region formed over the first metal layer, wherein the dielectric region comprises:a plurality of metal layers each of which comprises a dummy metal structure over the first device metal structure, wherein the dummy metal structures in each pair of two adjacent metal layers in the plurality of metal layers shield respectively two non-overlapping portions of the first device metal structure from a top view of the semiconductor structure, and
an inter-metal dielectric layer comprising dielectric material between each pair of two adjacent metal layers in the plurality of metal layers; and

a polymer region formed over the dielectric region, wherein:the dielectric region comprises fluorine ions, and
embedding of the dummy metal structures decreases a density of the fluorine ions in the dielectric region.


US Pat. No. 11,069,628

INTEGRATED CIRCUIT PROVIDED WITH DECOYS AGAINST REVERSE ENGINEERING AND CORRESPONDING FABRICATION PROCESS

STMicroelectronics (Rouss...


1. An integrated circuit, comprising:a first domain configured to be supplied with power at a first supply voltage and including at least one first transistor comprising a first gate region and a first gate dielectric region; and
a second domain configured to be supplied with power at a second supply voltage greater than the first supply voltage and including at least one second transistor comprising a floating gate region, a second gate region and a second gate dielectric region located between the floating gate region and the second gate region, wherein the second gate region is configured to be biased at a voltage that is higher than the first supply voltage;
wherein said first and second gate dielectric regions have a same composition and are configured such that said at least one first transistor is turned off for any biasing of said first gate region at a voltage that is lower than or equal to the first supply voltage.

US Pat. No. 11,069,627

SCRIBE SEALS AND METHODS OF MAKING

Texas Instruments Incorpo...


1. A semiconductor die, comprising:a plurality of layers including a first layer, the first layer having a top surface;
a scribe seal formed in at least one layer of the plurality of layers, the scribe seal including a metal stack having a first metal layer, located proximate the top surface of the first layer; and
a trench that is entirely filled with a sealant formed in at least one layer of the plurality of layers, the trench extending below a plane corresponding to a top surface of the first metal layer and the trench laterally separated from the first metal layer.

US Pat. No. 11,069,626

MOLDING COMPOUND AND SEMICONDUCTOR PACKAGE WITH A MOLDING COMPOUND

Infineon Technologies AG,...


1. A molding compound, comprising:a matrix; and
a filler comprising filler particles,
wherein the filler particles each comprise a core comprising a semiconducting material and an electrically insulating cover,
wherein the core comprises one of: a doped monocrystalline silicon particle, and a silicon carbide particle.

US Pat. No. 11,069,625

METHOD FOR FORMING PACKAGE STRUCTURE

Taiwan Semiconductor Manu...


1. A method for forming a package structure, comprising:forming a package layer over a substrate;
forming a first dielectric layer over the package layer;
forming a first alignment mark and a second alignment mark over the first dielectric layer;
forming a second dielectric layer over the first dielectric layer; and
removing a portion of the second dielectric layer to form a first trench to expose a top surface of the first dielectric layer and the first alignment mark, and to form a first opening to expose the second alignment.

US Pat. No. 11,069,624

ELECTRICAL DEVICES AND METHODS OF MANUFACTURE

Faraday Semi, Inc., Irvi...


1. A method of making an electrical device comprising:coupling a first frontside conductive layer to a front side of an integrated circuit die, wherein the front side of the integrated circuit die includes one or more frontside contacts;
forming one or more holes through the first frontside conductive layer at one or more locations over the one or more frontside contacts;
applying a conductive material into the one or more holes through the first frontside conductive layer to electrically couple the first frontside conductive layer to the frontside contacts of the integrated circuit die;
forming a circuit pattern in the first frontside conductive layer;
forming one or more conductive raised portions on the frontside conductive layer;
applying a second frontside conductive layer over the first frontside conductive layer, with an insulating material between at least portions of the first frontside conductive layer and the second frontside conductive layer;
forming one or more holes through the second frontside conductive layer at one or more locations over the one or more conductive raised portions;
applying a conductive material into the one or more holes through the second frontside conductive layer to electrically couple the second frontside conductive layer to the one or more raised formations; and
forming a circuit pattern in the second frontside conductive layer.

US Pat. No. 11,069,623

SEMICONDUCTOR PACKAGE

Samsung Electronics Co., ...


1. A semiconductor package comprising:a substrate;
a first semiconductor chip and a second semiconductor chip on the substrate, the first semiconductor chip including one or more logic circuits, the second semiconductor chip being spaced apart from the first semiconductor chip, and the second semiconductor chip including one or more power management integrated circuits;
a passive element on the substrate, the passive element being spaced apart from the first semiconductor chip and the second semiconductor chip, the passive element being between the first semiconductor chip and the second semiconductor chip,
a height of the passive element being greater than a height of the first semiconductor chip and a height of the second semiconductor chip;
a conductive structure on the substrate;
an interposer substrate on the first semiconductor chip, the passive element, and the conductive structure,
the interposer substrate being electrically connected to the conductive structure; and
an upper passive element on the interposer substrate,
wherein a height of the upper passive element is greater than a gap between the substrate and the interposer substrate,
wherein the conductive structure includes signal structures and power supply structures,
wherein the signal structures are more adjacent to the first semiconductor chip than the power supply structures; and
wherein the power supply structures are more adjacent to the second semiconductor chip than the signal structures.

US Pat. No. 11,069,622

INTERPOSER-TYPE COMPONENT CARRIER AND METHOD OF MANUFACTURING THE SAME


1. An interposer component carrier, comprising:a stack comprising at least one electrically conductive layer structure and at least one electrically insulating layer structure:
a cavity formed in an upper portion of the stack;
an active component embedded in the cavity and having terminals lacing upwards; and
a redistribution structure comprising:exactly one further electrically insulating layer structure above the active component, the further electrically insulating layer structure having an upper surface and a lower surface;
vias connecting the terminals of the active component and passing through the further electrically insulating layer from the upper surface to the lower surface, the vias having a first distance between each other; and
trenches arranged at the upper surface of the further electrically insulating layer structure above the active component and being filled by metal, the trenches having a second distance between each other, the second distance being smaller than the first distance.


US Pat. No. 11,069,621

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...


1. A semiconductor device comprising:an input terminal including a P terminal and an N terminal;
a laminated circuit substrate connected to the input terminal;
a power substrate provided above the laminated circuit substrate, the input terminal extending through the power substrate and the laminated circuit substrate electrically connected to the power substrate;
a capacitor provided in a conduction path between the P terminal and the N terminal; and
a resistor provided in series with the capacitor in the conduction path between the P terminal and the N terminal.

US Pat. No. 11,069,620

DIE INTERCONNECT SUBSTRATE, AN ELECTRICAL DEVICE AND A METHOD FOR FORMING A DIE INTERCONNECT SUBSTRATE

Intel Corporation, Santa...


1. A die interconnect substrate, comprising:a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die; and
a multilayer substrate structure comprising a substrate interconnect, wherein the bridge die is embedded in the multilayer substrate structure, and wherein the substrate interconnect extends from a level above the bridge die to a level below the bridge die,
wherein the multilayer substrate structure further comprises an electrically insulating layer comprising a first electrically insulating material; and
wherein the multilayer substrate structure further comprises an electrically insulating filler structure located laterally between the bridge die and the electrically insulating layer, wherein the electrically insulating filler structure comprises a second electrically insulating material different from the first electrically insulating material.

US Pat. No. 11,069,619

INTERCONNECT STRUCTURE AND ELECTRONIC DEVICE EMPLOYING THE SAME

Samsung Electronics Co., ...


1. An interconnect structure comprising:a dielectric layer;
a metal interconnect having a bottom surface, a first side, a second side opposite the first side, and a top surface,
the bottom surface, the first side, and the second side of the metal interconnect being surrounded by the dielectric layer;
a graphene layer on at least the top surface of the metal interconnect; and
a metal bonding layer providing interfacial bonding between the metal interconnect and the graphene layer, the metal bonding layer including a metal material,
wherein the graphene layer includes a first graphene layer on the top surface of the metal interconnect, second graphene layers on the first side and the second side of the metal interconnect, and a third graphene layer on the bottom surface of the metal interconnect, and
wherein the metal bonding layer is between the third graphene layer and the bottom surface of the metal interconnect.

US Pat. No. 11,069,618

LINE STRUCTURE AND A METHOD FOR PRODUCING THE SAME

DAI NIPPON PRINTING CO., ...


1. A multi-layer line structure comprising:a first line layer;
a second line layer located on a first organic resin film located on the first line layer;
a first insulating layer including an inorganic layer located on the second line layer and a second organic resin film located on the inorganic layer, the inorganic layer being insulating a third line layer located under the first line layer;
a third organic resin film located between the third line layer and the first line layer; and
a first via connection part located in a first via connection hole running in an up-down direction through the first organic resin film in an area where the first line layer and the second line layer overlap each other,
wherein:
the inorganic layer wholly covers and is in contact with a side surface of the second line layer and at least the part of the top surface of the second line layers;
the first organic resin film wholly covers and is in contact with a side surface of the first line layer and at least the part of the top surface of the first line layer; and
the third organic resin film wholly covers and is in contact with a side surface of the third line layer and at least the part of the top surface of the third line layer.

US Pat. No. 11,069,617

SEMICONDUCTOR DEVICE AND NONVOLATILE MEMORY

TOSHIBA MEMORY CORPORATIO...


1. A semiconductor device comprising:a transistor havinga diffusion layer arranged in a substrate and exposed on a surface of the substrate, elongated in a first direction along the surface of the substrate, and
a gate electrode arranged above the diffusion layer; and

contacts arranged in the first direction on both sides of the gate electrode and each connected to the diffusion layer, the contacts having elongated bottom surfaces,
wherein elongated dimensions of any neighboring pair of the bottom surfaces across the gate electrode are not mutually aligned in a straight line or along a cleavage direction of a crystal of the substrate,
wherein none of the elongated dimensions is perpendicular to the first direction.

US Pat. No. 11,069,616

HORIZONTAL PROGRAMMABLE CONDUCTING BRIDGES BETWEEN CONDUCTIVE LINES

Tokyo Electron Limited, ...


1. A semiconductor device comprising:a first level having a plurality of transistor devices over a substrate; and
a first wiring level positioned over the first level, the first wiring level including a plurality of conductive lines extending parallel to the first level, and one or more programmable horizontal bridges extending parallel to the first level, each of the one or more programmable horizontal bridges electrically connecting two respective conductive lines of the plurality of conductive lines in the first wiring level, wherein:
the one or more programmable horizontal bridges include a programmable material having a modifiable resistivity in that the one or more programmable horizontal bridges change between being conductive and being non-conductive,
a first programmable horizontal bridge of the one or more programmable horizontal bridges is positioned between a first conductive line and a second conductive line of the plurality of conductive lines in the first wiring level along a first direction that is parallel to the substrate,
the first programmable horizontal bridge further extends between the first conductive line and the second conductive line along a second direction that is parallel to substrate and perpendicular to the first direction,
a first sidewall of the first programmable horizontal bridge is positioned at a first side of the first conductive line and extends away from a first sidewall of the first conductive line along the second direction, and
a second sidewall of the first programmable horizontal bridge is positioned at a second side of the first conductive line and extends away from a second sidewall of the first conductive line along the second direction.

US Pat. No. 11,069,615

INDUCTOR, FILTER, AND MULTIPLEXER

TAIYO YUDEN CO., LTD., T...


1. An inductor comprising:a substrate;
a first wiring line located on the substrate;
a second wiring line located above the first wiring line and spaced from the first wiring line through an air gap, at least a part of the second wiring line overlapping with at least a part of the first wiring line in plan view;
a first supporting post connecting an end of the first wiring line and an end of the second wiring line such that a direct current conducts between the first wiring line and the second wiring line through the first supporting post; and
a second supporting post which overlaps with the second wiring line in plan view, and is surrounded by the first wiring line in plan view, the second supporting post being insulated from the first wiring line, the second supporting post supporting the second wiring line,
wherein
the second supporting post does not overlap with the first wiring line in plan view, and is located in an opening, and
the first wiring line has the opening and the opening is a closed area completely surrounded by the first wiring line.

US Pat. No. 11,069,614

SEMICONDUCTOR PACKAGE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor structure, comprising:a die, wherein the die further comprise:a die substrate;
a die pad over the die substrate;
a conductive via over the die pad; and
a dielectric material surrounding the conductive via;

a molding surrounding the die;
a first dielectric layer disposed over the die and the molding; and
a second dielectric layer disposed between the first dielectric layer and the die, and between the first dielectric layer and the molding,
wherein the dielectric material of the die is surrounded by the molding, a top surface of the dielectric material is aligned with a top surface of the conductive via and aligned with a top surface of the molding, a material content ratio in the first dielectric layer is substantially greater than that in the second dielectric layer, and the material content ratio substantially inversely affects a mechanical strength of the first dielectric layer and the second dielectric layer.

US Pat. No. 11,069,613

INTEGRATED CIRCUIT DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...


1. An integrated circuit device comprising:a first insulation layer on a substrate;
a lower wiring structure in the first insulation layer and comprising a metal layer and a conductive barrier layer, wherein the metal layer is on the conductive barrier layer;
an etch stop layer overlapping an upper surface of the first insulation layer and an upper surface of the conductive barrier layer and having a first thickness;
a capping layer overlapping a first portion of the upper surface of the metal layer and having a second thickness which is less than the first thickness;
a second insulation layer overlapping the etch stop layer and the capping layer; and
an upper wiring structure connected to a second portion of the upper surface of the metal layer not overlapped by the capping layer,
wherein the upper wiring structure is in the second insulation layer, and
wherein the upper wiring structure comprises a concave-convex structure contacting a portion of an upper surface of the etch stop layer, a sidewall of the etch stop layer, and the second portion of the upper surface of the metal layer.

US Pat. No. 11,069,612

SEMICONDUCTOR DEVICES HAVING ELECTRICALLY AND OPTICALLY CONDUCTIVE VIAS, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...


1. A semiconductor device, comprising:a first semiconductor die having a first optical component and a first via;
a second semiconductor die having a second optical component and a second via; and
an optically and electrically conductive material in the first via and in the second via, wherein the optically and electrically conductive material forms a continuous optical path extending between the first and second semiconductor dies, and wherein the optical path optically couples the first and second optical components.

US Pat. No. 11,069,611

LINER-FREE AND PARTIAL LINER-FREE CONTACT/VIA STRUCTURES

International Business Ma...


1. A semiconductor structure comprising:a lower portion of a volume expanded electrically conductive structure embedded in a first dielectric material layer;
a dielectric capping layer located on the first dielectric material layer, wherein the dielectric capping layer has a contact/via opening comprising a lower portion and an upper portion, wherein the lower portion of the contact/via opening has a same width as the upper portion of the contact/via opening and contains an upper portion of the volume expanded electrically conductive structure which is in direct physical contact with a sidewall of the dielectric capping layer;
a contact/via diffusion barrier liner and a contact/via structure present in the upper portion of the contact/via opening, wherein the contact/via diffusion barrier liner and the contact/via structure both have a topmost surface that is coplanar with a topmost surface of the dielectric capping layer; and
a contact structure located above the dielectric capping layer, the contact/via diffusion barrier liner, and the contact/via structure, wherein the contact structure is embedded in a second dielectric material layer.

US Pat. No. 11,069,610

METHODS FOR FORMING MICROELECTRONIC DEVICES WITH SELF-ALIGNED INTERCONNECTS, AND RELATED DEVICES AND SYSTEMS

Micron Technology, Inc., ...


1. A method of forming a microelectronic device structure, the method comprising:patterning a first conductive material and a first sacrificial material to form at least one first feature comprising a first conductive structure;
forming a dielectric material adjacent the at least one first feature;
forming another dielectric material on the first sacrificial material and the dielectric material;
forming at least one opening through the other dielectric material to expose at least one portion of the first sacrificial material;
forming a second sacrificial material on the other dielectric material and on the at least one portion of the first sacrificial material exposed by the at least one opening;
patterning the second sacrificial material to form at least one second feature;
forming an additional dielectric material adjacent the at least one second feature;
removing the second sacrificial material and the at least one portion of the first sacrificial material to form extended openings exposing therein at least one portion of the first conductive material; and
filling the extended openings with a second conductive material to form at least one interconnect in each of the extended openings.

US Pat. No. 11,069,609

TECHNIQUES FOR FORMING VIAS AND OTHER INTERCONNECTS FOR INTEGRATED CIRCUIT STRUCTURES

Intel Corporation, Santa...


1. An integrated circuit structure comprising:a via contact layer, the via contact layer including a first via and a second via, wherein the first via comprises a first conductive material, and wherein the second via comprises a second conductive material, wherein the first conductive material is different than the second conductive material; and
wherein a width of a grain size of the first conductive material of the first via is greater than or equal to a width of the first via, and wherein a width of a grain size of the second conductive material of the second via is greater than or equal to a width of the second via.

US Pat. No. 11,069,608

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...


1. A semiconductor structure, comprising:a first semiconductor die comprising:a first semiconductor substrate;
a first interconnect structure disposed below the first semiconductor substrate; and
a first bonding conductor disposed below the first interconnect structure and electrically coupled to the first semiconductor substrate through the first interconnect structure; and

a second semiconductor die bonded to the first semiconductor die and comprising:a second semiconductor substrate and a second interconnect structure disposed below and electrically coupled to the second semiconductor substrate; and
a through semiconductor via penetrating through the second semiconductor substrate and extending into the second interconnect structure to be electrically coupled to the second interconnect structure, wherein the first bonding conductor of the first semiconductor die extends from the first interconnect structure of the first semiconductor die towards the through semiconductor via of the second semiconductor die to electrically connect the first semiconductor die to the second semiconductor die, and the first bonding conductor of the first semiconductor die corresponding to the through semiconductor via of the second semiconductor die is smaller than the through semiconductor via.


US Pat. No. 11,069,607

METAL OPTION STRUCTURE OF SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...


1. A metal option structure of a semiconductor device, comprising:a plurality of vias connecting first metal lines provided in a first metal layer to second metal lines provided in a second metal layer disposed over the first metal layer, and configured to constitute a plurality of nodes of an option circuit; and
an identification pattern extending from the first metal layer to the second metal layers and having a different layout structure from the vias.

US Pat. No. 11,069,606

FABRICATION PROCESS AND STRUCTURE OF FINE PITCH TRACES FOR A SOLID STATE DIFFUSION BOND ON FLIP CHIP INTERCONNECT

Compass Technology Compan...


1. A semiconductor package comprising:a flexible substrate;
a plurality of traces formed on said flexible substrate, each respective trace comprising at least four different conductive materials having different melting points and plastic deformation properties constructed in four layers, which are optimized for both diffusion bonding and soldering of passive components wherein a topmost layer of each said trace comprises tin; and
at least one die mounted on said substrate wherein there is a diffusion bond between at least one of said plurality of traces and said at least one die.

US Pat. No. 11,069,605

WIRING STRUCTURE HAVING LOW AND HIGH DENSITY STACKED STRUCTURES


1. A wiring structure, comprising:a plurality of upper conductive structures each including a plurality of upper dielectric layers, a plurality of upper circuit layers in contact with the upper dielectric layers at least one bonding portion electrically connected to one of the upper circuit layers, and at least one inner via disposed between two adjacent ones of the upper circuit layers for electrically connecting the two adjacent ones of the upper circuit layers, wherein a tapering direction of the inner via is different from a tapering direction of the bonding portion;
a lower conductive structure including at least one lower dielectric layer and at least one lower circuit layer in contact with the lower dielectric layer; and
an intermediate layer disposed between the upper conductive structures and the lower conductive structure and bonding the upper conductive structures and the lower conductive structure together, wherein the upper conductive structures are electrically connected to the lower conductive structure,
wherein the plurality of upper conductive structures are stacked on one another, the wiring structure further comprises at least one intervening layer disposed between two adjacent ones of the upper conductive structures and bonds the two adjacent ones of the upper conductive structures together.

US Pat. No. 11,069,604

SEMICONDUCTOR PACKAGE AND METHOD OF MAKING THE SAME

ALPHA AND OMEGA SEMICONDU...


1. A method for fabricating semiconductor packages, the method comprising the steps of:providing a removable carrier;
forming a plurality of pillars on a top surface of the removable carrier;
attaching a plurality of semiconductor devices to the top surface of the removable carrier;
forming a first molding encapsulation enclosing a majority portion of the plurality of pillars and a majority portion of the plurality of semiconductor devices so that top surfaces of the plurality of pillars and top surface electrodes of the plurality of semiconductor devices are exposed from a top surface of the first molding encapsulation;
applying a first photo resist layer over the top surface of the first molding encapsulation;
developing a first photo resist pattern using a first patterned mask under a first exposure process;
applying a first redistribution layer (RDL) over an exposed top surface of the first molding encapsulation and the top surface electrodes of the plurality of semiconductor devices forming a first plurality of electrical interconnections;
removing the first photo resist pattern;
forming a second molding encapsulation enclosing the first plurality of electrical interconnections;
removing the removable carrier;
applying a second photo resist layer over a bottom surface of the first molding encapsulation and the plurality of semiconductor devices;
developing a second photo resist pattern using a second patterned mask under a second exposure process;
applying a second RDL over an exposed bottom surface of the first molding encapsulation and the plurality of semiconductor devices forming a second plurality of electrical interconnections;
removing the second photo resist pattern; and
applying a singulation process forming the semiconductor packages;
wherein a bottom surface of the second molding encapsulation is directly attached to the top surface of the first molding encapsulation in a region directly between one pillar of the plurality of pillars and one semiconductor device of the plurality of semiconductor devices; and
wherein the one pillar of the plurality of pillars and the one semiconductor device of the plurality of semiconductor devices are contained in a same semiconductor package of the semiconductor packages.

US Pat. No. 11,069,603

SEMICONDUCTOR DEVICE

SUMITOMO ELECTRIC INDUSTR...


1. A semiconductor device comprising:a first electrode terminal of a die pad;
a second electrode terminal of a lead;
a semiconductor element having an electrode on one surface connected to one surface of the first electrode terminal;
a wire that connects an electrode on another surface of the semiconductor element and the second electrode terminal;
a resin portion formed of an insulator covering the semiconductor element, a part of the second electrode terminal, and the one surface of the first electrode terminal,
wherein a height position of the die pad differs from a height position of the lead,
wherein one side of the first electrode terminal and one side of the second electrode terminal face each other, where a spatial distance between the first electrode terminal and the second electrode terminal is shortest, and
wherein the one side of the first electrode terminal and the one side of the second electrode terminal are chamfered into a C-surface or a R-surface to increase the spatial distance.

US Pat. No. 11,069,602

PACKAGE AND TERMINAL ARRANGEMENT FOR SEMICONDUCTOR MODULE

Mitsubishi Electric Corpo...


1. A semiconductor module comprising:at least one pair of first and second switching devices that are inserted in series between a first potential and a second potential lower than the first potential, and operate complementarily;
a first drive circuit that performs drive control of the first switching device; and
a second drive circuit that performs drive control of the second switching device, wherein
the at least one pair of first and second switching devices and the first and second drive circuits are sealed in a package having a rectangular shape in plan view, the semiconductor module further comprising:
a control terminal provided to protrude from a side surface of a first long side out of first and second long sides of the package, and to which a control signal of the first and second drive circuits is inputted;
an output terminal provided to protrude from a side surface of the second long side and supplied with an output of the first and second switching devices;
a first main terminal provided to protrude from a side surface of a first short side out of first and second short sides of the package, and to which the first potential is applied; and
a second main terminal provided to protrude from a side surface of the second short side, and to which the second potential is applied.

US Pat. No. 11,069,601

LEADLESS SEMICONDUCTOR PACKAGE WITH WETTABLE FLANKS

STMicroelectronics, Inc.,...


1. A package, comprising:encapsulation material including a first surface facing a first direction, a second surface facing a second direction opposite to the first direction, and a plurality of side surfaces;
a die pad including a plurality of side surfaces;
a plurality of conductive leads positioned laterally to the plurality of side surfaces of the die pad, each of the plurality of conductive leads including:a first portion including a first surface facing the first direction, a second surface facing the second direction, and a side surface, the first surface of the first portion being coplanar with the first surface of the encapsulation material, the first portion extending in a third direction transverse to the first and second directions; and
a second portion including a surface that is coplanar with the second surface of the encapsulation material, the second portion extending from the second surface of the first portion toward the second surface of the encapsulation material, the second portion being spaced from one of the plurality of side surfaces of the encapsulation material by a portion of the encapsulation material, the portion of the encapsulation material extending away from the die pad and past the side surface of the first portion in the third direction; and

a conductive layer on the first surface and the side surface of the first portion of each of the plurality of conductive leads.

US Pat. No. 11,069,600

SEMICONDUCTOR PACKAGE WITH SPACE EFFICIENT LEAD AND DIE PAD DESIGN

Infineon Technologies AG,...


1. A semiconductor package, comprising:a die pad comprising a die attach surface, a rear surface opposite the die attach surface, and an outer edge side extending between the die attach surface and the rear surface, the outer edge side having a step-shaped profile wherein an upper section of the die pad laterally overhangs past a lower section of the die pad;
a semiconductor die mounted on the die attach surface and comprising a first electrical terminal on an upper surface of the semiconductor die that faces away from the die attach surface; and
a first conductive clip that directly electrically contacts the first electrical terminal and wraps around the outer edge side of the die pad such that a section of the first conductive clip is at least partially within an area that is directly below the upper section of the die pad and directly laterally adjacent to the lower section.

US Pat. No. 11,069,599

RECESSED LEAD LEADFRAME PACKAGES

SEMICONDUCTOR COMPONENTS ...


1. A chip-on-lead package comprising:a leadframe coupled to a semiconductor chip, the leadframe comprising a plurality of leads extending inwardly into an opening in the leadframe surrounded by the plurality of leads;
wherein at least one of the plurality of leads comprises a thinned portion adjacent to the semiconductor chip and is an at least one thinned lead; and
wherein the plurality of leads, except for the at least one thinned lead, mechanically couple to the semiconductor chip through a die bonding material.

US Pat. No. 11,069,598

MEMORY ARRAYS AND METHODS USED IN FORMING A MEMORY ARRAY AND CONDUCTIVE THROUGH-ARRAY-VIAS (TAVS)

Micron Technology, Inc., ...


1. A method used in forming a memory array and conductive through-array-vias (TAVs), comprising:forming a stack comprising vertically-alternating insulative tiers and wordline tiers;
forming a mask comprising horizontally-elongated trench openings and operative TAV openings above the stack;
etching unmasked portions of the stack through the trench and operative TAV openings in the mask to form horizontally-elongated trench openings in the stack and to form operative TAV openings in the stack;
forming conductive material in the operative TAV openings in the stack to form individual operative TAVs in individual of the operative TAV openings in the stack; and
forming a wordline-intervening structure in individual of the trench openings in the stack.

US Pat. No. 11,069,597

SEMICONDUCTOR CHIPS AND METHODS OF MANUFACTURING THE SAME

Samsung Electronics Co., ...


1. A semiconductor chip, comprising:a substrate;
an interlayer insulation layer includinga bottom interlayer insulation layer on an upper surface of the substrate, and
a top interlayer insulation layer on the bottom interlayer insulation layer;

an etch stop layer between the bottom interlayer insulation layer and the top interlayer insulation layer;
a landing pad on the interlayer insulation layer, the landing pad including a landing pad metal layer and a landing pad barrier layer, the landing pad barrier layer surrounding an upper surface of the landing pad metal layer and a side surface of the landing pad metal layer, the landing pad barrier layer being at least partially between the landing pad metal layer and the top interlayer insulation layer; and
a through via connected to the landing pad through the substrate, the interlayer insulation layer, and the etch stop layer,
wherein the etch stop layer is isolated from direct contact with the landing pad,
wherein the through via extends through a through via hole that exposes the landing pad barrier layer, the upper surface of the landing pad metal layer, and an inner sidewall of the landing pad metal layer, the through via extends through the landing pad barrier layer and directly contacts the landing pad metal layer, and a sidewall of the through via directly contacts the inner sidewall of the landing pad metal layer.

US Pat. No. 11,069,596

THROUGH SILICON CONTACT STRUCTURE AND METHOD OF FORMING THE SAME

YANGTZE MEMORY TECHNOLOGI...


1. An integrated structure comprising:a first dielectric layer formed over a first main surface of a substrate, the substrate further including an opposing second main surface;
a through silicon contact (TSC) formed in the first dielectric layer and the substrate so that the TSC extends through the first dielectric layer and extends into the substrate;
a conductive plate formed over the first dielectric layer, the conductive plate being electrically coupled with the TSC;
an isolation trench formed in the substrate that surrounds the conductive plate, the isolation trench and the conductive plate being spaced apart from each other;
a second dielectric layer formed on the second main surface of the substrate; and
a first plurality of vias formed in the second dielectric layer that extend through the second main surface into the substrate, wherein a first via of the first plurality of vias is coupled to the TSC.

US Pat. No. 11,069,595

WATER COOLING MODULE

ASIA VITAL COMPONENTS CO....


1. A water cooling module, comprising:a flow-guiding main body being provided with a first inlet, a first outlet, a second inlet, a second outlet, a third outlet, a flow-guiding passage set and a cavity portion;the flow-guiding passage set including a plurality of flow-guiding passages, and the first inlet, the second inlet and the first outlet being respectively communicable with one of the flow-guiding passages, the cavity portion being formed on one side of the flow-guiding main body opposite to the flow-guiding passage set to have a downward open side and being communicable with the first outlet, the second outlet and the third outlet;

a pump set including a first pump and a second pump; the first pump having a first water inlet and a first water outlet, and the second pump having a second water inlet and a second water outlet;
the first water inlet and the first water outlet being respectively communicable with one of the flow-guiding passages; and
the second water inlet and the second water outlet being respectively communicable with one of the flow-guiding passages; and
a plurality of water cooling radiators vertically stacked, the plurality of water cooling radiators including a first water-receiving chamber, a first connecting portion, and a second connecting portion, respectively, the first water-receiving chamber internally defines a first water-receiving space communicable with the first and the second connecting portion, the first and the second connecting portion of the plurality of water cooling radiators being respectively communicable with the first inlet, the second outlet and the third outlet.

US Pat. No. 11,069,594

METHODS OF FORMING ELECTRONIC ASSEMBLIES WITH INVERSE OPAL STRUCTURES USING VARIABLE CURRENT DENSITY ELECTROPLATING

The Board of Trustees of ...


1. A method of forming an inverse opal structure along a metal substrate comprising:depositing a plurality of polymer spheres along the metal substrate;
electroplating the metal substrate and the plurality of polymer spheres at a first current density to form a first solid metal layer between the metal substrate and the plurality of polymer spheres such that the plurality of polymer spheres is raised from the metal substrate;
electroplating the metal substrate and the plurality of polymer spheres at a second current density to diffuse metals from the metal substrate and deposit the metals about the plurality of polymer spheres, wherein the second current density is greater than the first current density;
electroplating the metal substrate and the plurality of polymer spheres to form a second solid metal layer disposed over the plurality of polymer spheres; and
removing the plurality of polymer spheres to form the inverse opal structure disposed between the first solid metal layer and the second solid metal layer and having a porous structure, wherein the first solid metal layer and the second solid metal layer define planar interface surfaces disposed over the porous structure of the inverse opal structure.

US Pat. No. 11,069,593

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...


1. A semiconductor device comprising:a first cooling plate comprising a circuit pattern disposed on an insulator;
a second cooling plate facing the first cooling plate and comprising a circuit pattern disposed on an insulator;
a semiconductor chip joined between the circuit pattern of the first cooling plate and the circuit pattern of the second cooling plate with a joining material; and
a case having an opening at a center portion, the case holding outer peripheries of the first cooling plate and the second cooling plate, and the opening containing part of the first cooling plate, part of the second cooling plate, and the semiconductor chip,
wherein the semiconductor chip is directly mounted to a semiconductor-chip mounting part positioned at the center portion of the case and between the first cooling plate and the second cooling plate,
wherein the case comprises a plurality of sidewalls extending entirely around the opening, each of the plurality of sidewalls including a portion covering the semiconductor-chip mounting part and positioned at the center portion of the each of the plurality of sidewalls of the case, each sidewall portion having a width along a direction parallel to a center axis of the opening greater than widths along the direction of remaining portions of the sidewall of the case,
wherein the widths continuously vary, and
wherein an upper end of each of the plurality of sidewalls is upwardly protuberant as the upper end approaches the semiconductor-chip mounting part from an edge of the case in its lateral direction, and a lower end of each of the plurality of sidewalls is downwardly protuberant as the lower end approaches the semiconductor-chip mounting part from the edge of the case in its lateral direction.

US Pat. No. 11,069,592

SEMICONDUCTOR PACKAGES INCLUDING A LOWER STRUCTURE, AN UPPER STRUCTURE ON THE LOWER STRUCTURE, AND A CONNECTION PATTERN BETWEEN THE LOWER STRUCTURE AND THE UPPER STRUCTURE

Samsung Electronics Co., ...


1. A semiconductor package, comprising:a lower structure, the lower structure including a lower base and a first lower chip on the lower base, the first lower chip including a chip bonding pad, a pad structure, and a heat sink structure, the pad structure having a thickness greater than a thickness of the chip bonding pad, wherein at least a portion of the heat sink structure is at a same height level as at least a portion of the pad structure;
an upper structure on the lower structure; and
a connection pattern between the lower structure and the upper structure, the connection pattern configured to electrically connect the lower structure and the upper structure to each other, the connection pattern connected to the upper structure, the connection pattern extending away from the upper structure to be connected to the pad structure,
wherein the chip bonding pad does not overlap the pad structure and the connection pattern in a vertical direction perpendicular to an upper surface of the lower base.

US Pat. No. 11,069,591

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...


1. A semiconductor device comprising:a semiconductor substrate:
a groove formed at an edge of the semiconductor substrate so that part of the groove is exposed at an outer edge of the semiconductor substrate;
a passivation film formed over the semiconductor substrate;
an external insulating layer formed over the passivation film, part of the external insulating layer intruding into the groove;
a ball terminal formed at the surface of the semiconductor device;
an opening formed through the passivation film at a location thereon; and
a wiring formed through the opening to connect the semiconductor substrate and the ball terminal,
wherein the passivation film formed next to the groove has a lateral surface and a vertical surface, the external insulating layer intrudes into the groove and is disposed in contact with both of the lateral surface and the vertical surface of the passivation film formed next to the groove.

US Pat. No. 11,069,590

WAFER-LEVEL FAN-OUT PACKAGE WITH ENHANCED PERFORMANCE

Qorvo US, Inc., Greensbo...


1. An apparatus comprising:a first thinned die comprising a first device layer, a first dielectric layer over the first device layer, and a plurality of first die bumps underneath the first device layer;
a second die comprising a second device layer, a silicon substrate over the second device layer, and a plurality of second die bumps underneath the second device layer;
a multilayer redistribution structure formed underneath the first thinned die and the second die;
a first mold compound residing over the silicon substrate of the second die;
a second mold compound residing over the multilayer redistribution structure, around and underneath the first thinned die, and around and underneath the second die; wherein:the second mold compound extends beyond a top surface of the first thinned die to define an opening within the second mold compound and over the first thinned die, such that the top surface of the first thinned die is at a bottom of the opening; and
a top surface of the first mold compound and a top surface of the second mold compound are coplanar; and

a third mold compound filling the opening and in contact with the top surface of the first thinned die, wherein the first mold compound, the second mold compound, and the third mold compound are formed from different materials.

US Pat. No. 11,069,589

CIRCUIT BOARD AND CIRCUIT MODULE

TAIYO YUDEN CO., LTD., T...


1. A circuit board, comprising:a core base material including a metal core layer having a first main surface capable of supporting a mounting component and a second main surface which is opposite to the first main surface;
a first exterior coating base material which is arranged facing the first main surface; and
a second exterior coating base material which is arranged facing the second main surface and includes a heat dissipation layer having a via which is connected to the second main surface,
wherein the first exterior coating base material includes:a recess storing the mounting component; and
a first wiring layer that includes:a first connection terminal that is electrically connected to the mounting component stored in the recess, and
a second connection terminal that has an area larger than an area of the first connection terminal and that is connected to at least one electrode of a temperature measurement element mounted in the first exterior coating base material,


wherein the second connection terminal is configured as a heat collecting terminal that receives heat from the core layer, and
wherein the temperature measurement element measures an amount of heat generated by driving of the mounting component.

US Pat. No. 11,069,588

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...


1. A semiconductor package comprising:a package substrate;
at least one semiconductor chip mounted on the package substrate; and
a molding member that surrounds the at least one semiconductor chip,
the molding member including fillers,each of the fillers including a core and a coating layer that surrounds the core,
the core including a non-electromagnetic material,

the coating layer including an electromagnetic material, andthe molding member including regions that respectively have different distributions of the fillers, at least some of the fillers in the molding member being adjacent to the semiconductor chip, wherein

the molding member includes a first region and a second region,
the first region has a first concentration of the fillers,
the second region has a second concentration of the fillers that is less than the first concentration,
the second region is over the first region and extends over the at least one semiconductor chip, and
the at least one semiconductor chip is on the first region.

US Pat. No. 11,069,587

INTEGRATED SEMICONDUCTOR DEVICE AND PROCESS FOR MANUFACTURING AN INTEGRATED SEMICONDUCTOR DEVICE

STMICROELECTRONICS S.R.L....


1. An integrated semiconductor device comprising:a supporting substrate having a first substrate face and a second substrate face opposite to the first substrate face;
a semiconductor die having a first die face coupled to the first substrate face of the supporting substrate, the first die face comprising first die contact pads in a central portion of the semiconductor die,
wherein the supporting substrate has at least one through opening,
wherein the first die contact pads are arranged facing the through opening, and
wherein the supporting substrate comprises first substrate contact pads connected by first bonding wires to the respective first die contact pads through the through opening; and
an array of first electric connection structures arranged on the second substrate face in a central portion of the supporting substrate, wherein each of the array of first electric connection structures is coupled to a respective one of the first die contact pads.

US Pat. No. 11,069,586

CHIP-ON-FILM PACKAGE

Novatek Microelectronics ...


1. A chip-on-film package, comprising:a flexible substrate, comprising at least one segment, wherein the at least one segment comprises a central portion, a first side portion, and a second side portion, and the first side portion and the second side portion are located at two opposite sides of the central portion respectively;
a chip, disposed on the central portion, comprising a first side close to the first side portion and a second side close to the second side portion, and comprising a plurality of first connecting pads and a plurality of second connecting pads for bonding to the flexible substrate, wherein the first connecting pads and the second connecting pads are disposed along the second side of the chip;
a plurality of first test pads and a plurality of second test pads, disposed on the first side portion;
a plurality of first connecting wires, wherein two ends of each of the first connecting wires are respectively connected to the corresponding first connecting pad and the corresponding first test pad;
a plurality of second connecting wires, wherein each of the second connecting wires comprises a first section, a second section and a third section, wherein the first section is located at the second side portion, the second section is located at the central portion and connects the corresponding second connecting pad and one end of the first section,
the third section is located at the central portion and connects to the other end of the first section and the corresponding second test pad, and two ends of each of the second connecting wires are respectively connected to the corresponding second connecting pad and the corresponding second test pad, and
wherein each of the plurality of first connecting pads is connected to one of the plurality of first test pads on the first side portion, and each of the plurality of second connecting pads is connected to one of the plurality of second test pads on the first side portion.

US Pat. No. 11,069,585

SEMICONDUCTOR SUBSTRATE CRACK MITIGATION SYSTEMS AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...


1. A method for healing a crack in a semiconductor substrate, the method comprising: identifying a crack in a semiconductor substrate; heating an area of the semiconductor substrate comprising the crack until the crack is healed; electronically identifying the heated area of the semiconductor substrate, the semiconductor substrate comprising one or more semiconductor die; and excluding the one or more semiconductor die formed in the heated area of the semiconductor substrate from further functional use.

US Pat. No. 11,069,584

INSPECTION METHOD FOR MICRO LED

POINT ENGINEERING CO., LT...


1. An inspection method for a micro LED, the method comprising:sequentially inspecting first to m-th rows of micro LEDs;
sequentially inspecting first to n-th columns of the micro LEDs; and
determining positional coordinates of a defective micro LED through the inspecting of the first to m-th rows and the first to n-th columns of the micro LEDs.

US Pat. No. 11,069,583

APPARATUS AND METHOD FOR THE MINIMIZATION OF UNDERCUT DURING A UBM ETCH PROCESS

VEECO INSTRUMENTS INC., ...


1. A method for endpoint detection in a wet etching process of a substrate, the method comprising:emitting, by a light source, light onto a plurality of sample locations on a surface of a first substrate during the wet etching process of the first substrate;
detecting, by a light detector, reflection of the light that is emitted onto each of the plurality of sample locations of the first substrate during the wet etching process of the first substrate;
analyzing, by at least one processor configured to execute instructions stored on processor readable media, first light information associated with the light reflected from each of the plurality of sample locations of the first substrate to represent the first light information in a first color model, wherein the at least one processor represents the first light information in the first color model by assigning a red color value, a green color value and a blue color value for each of the plurality of sample locations;
converting, by the at least one processor, the representation of the first light information from the first color model to a second color model as a function of a non-linear transformation, by assigning respective values for hue, saturation, and brightness;
determining, by the at least one processor, an end point of the wet etching of the first substrate using the light information represented by the second color model associated with at least one of the sample locations of the first substrate;
generating, by the at least one processor, etch parameters for a wet etching process for a second substrate based on the analyzed first light information represented by the second color model;
emitting, by a light source, light onto at least a plurality of sample locations on the surface of the second substrate during the wet etching process of the second substrate;
detecting, by the light detector, a reflection of light off the plurality of sample locations on the surface of the second substrate during the wet etching process of the second substrate;
analyzing, by the at least one processor, second light information associated with the light reflected from each of the plurality of sample locations of the second substrate, to represent the second light information in the first color model for each of the plurality of sample locations of the second substrate;
converting, by the at least one processor, the representation of the second light information from the first color model to the second color model as a function of a non-linear transformation, by assigning respective values for hue, saturation, and brightness;
applying, by the at least one processor, the representation of at least some of the second light information represented by the second color model and the generated etch parameters to determine an end point of the etching of the second substrate; and
modifying, by the at least one processor during the wet etching process of the second substrate, the generated etch parameters based on the representation of the at least some of the second light information represented by the second color model and the generated etch parameters to determine an end point of the etching of the second substrate.

US Pat. No. 11,069,582

SEMICONDUCTOR MANUFACTURING EQUIPMENT AND SEMICONDUCTOR MANUFACTURING METHOD

Mitsubishi Electric Corpo...


1. A semiconductor manufacturing method configured to perform processing for manufacturing a semiconductor on a wafer, the semiconductor manufacturing method comprising a step ofcalculating a thickness,
the step of calculating a thickness including the steps of(a) acquiring a plurality of measurement values at different measurement positions of the wafer from a thickness measurement function configured to measure a thickness of the wafer or a thickness measurement object deposited on the wafer,
(b) creating histogram data based on the plurality of measurement values, and
(c) extracting a grade group from the histogram data

the grade group including sequential grades having frequencies equal to or greater than a predetermined frequency,the step of calculating a thickness including a step of (d) calculating a representative value of a thickness of a measurement region based on the grades included in the extracted grade group.


US Pat. No. 11,069,581

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...


1. A method of manufacturing a semiconductor device, comprising:(a) preparing a substrate including a semiconductor base material, an insulating layer formed on the semiconductor base material, and a semiconductor layer formed on the insulating layer;
(b) after the (a), removing the semiconductor layer located in a bulk region of the substrate and the insulating layer located in the bulk region;
(c) after the (b), performing an epitaxial growth treatment on a surface of the semiconductor base material located in a first region of the bulk region;
(d) after the (c), forming a first gate electrode on the semiconductor layer located in a SOI region of the substrate via a first gate insulating film, a second gate electrode on the semiconductor base material located in the first region of the bulk region and on which the epitaxial growth treatment is performed via a second gate insulating film, and a third gate electrode on the semiconductor base material located in a second region of the bulk region and on which the epitaxial growth treatment is not performed via a third gate insulating film, respectively,
wherein a thickness of the third gate insulating film is larger than a thickness of each of the first gate insulating film and the second gate insulating film, and
wherein each of the first gate electrode, the second gate electrode and the third gate electrode is made of a first material;
(e) after the (d), forming an interlayer insulating film on the substrate so as to cover each of the first gate electrode, the second gate electrode and the third gate electrode;
(f) after the (e), polishing the interlayer insulating film, and exposing each of the first gate electrode, the second gate electrode and the third gate electrode from the interlayer insulating film; and
(g) after the (f), displacing the first material, that comprises each of the first gate electrode, the second gate electrode and the third gate electrode, to a second material, which is different from the first material.

US Pat. No. 11,069,580

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF CHANNEL PATTERNS

SAMSUNG ELECTRONICS CO., ...


1. A semiconductor device manufacturing method comprising:forming first semiconductor patterns extending in a first direction on a substrate, the first semiconductor patterns being spaced vertically from each other;
forming second semiconductor patterns positioned adjacent to the first semiconductor patterns in a second direction perpendicular to the first direction on the substrate and extending in the first direction parallel to the first semiconductor patterns;
forming a gate dielectric layer surrounding the first semiconductor patterns and the second semiconductor patterns;
forming a first organic pattern covering the second semiconductor patterns;
forming a sacrificial pattern interposed between the first semiconductor patterns and both side surfaces of the sacrificial pattern are exposed;
forming a conductive pattern surrounding the second semiconductor patterns and disposed between the first organic pattern and the second semiconductor patterns;
forming a second organic pattern covering the first semiconductor patterns, the gate dielectric layer, the sacrificial pattern, and the first organic pattern;
forming a cross-linking layer interposed between the first organic pattern and the second organic pattern;
removing the second organic pattern on the cross-linking layer and exposing the sacrificial pattern; and
removing the sacrificial pattern.

US Pat. No. 11,069,579

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...


1. A method comprising:forming a first fin extending from a substrate;
forming a gate stack on the first fin;
depositing a first gate spacer along a side of the gate stack, the first gate spacer comprising a first dielectric material;
depositing a second gate spacer along a side of the first gate spacer, the second gate spacer comprising a second dielectric material, the second dielectric material being different from the first dielectric material;
forming a source/drain region in the first fin adjacent the second gate spacer;
depositing a contact etch stop layer (CESL) along a side of the second gate spacer and over the source/drain region, the CESL comprising a third dielectric material, the second dielectric material being different from the third dielectric material;
removing at least a portion of the second gate spacer to form a void between the first gate spacer and the CESL; and
forming a source/drain contact through the CESL to couple the source/drain region, the void physically separating the source/drain contact from the gate stack.

US Pat. No. 11,069,578

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...


1. A method comprising:etching a semiconductor fin to form a first recess and a second semiconductor fin to form a second recess, the semiconductor fin defining sidewalls and a bottom surface of the first recess, the semiconductor fin extending in a first direction;
forming a source/drain region in the first recess, the source/drain region comprising a single continuous material extending from a bottom surface of the first recess to above a top surface of the semiconductor fin, a precursor gas for forming the source/drain region comprising phosphine (PH3) and at least one of arsine (AsH3) or monomethylsilane (CH6Si), a local maximum width of the source/drain region above a top surface of the semiconductor fin being less than a local maximum width of the source/drain region below the top surface of the semiconductor fin, the single continuous material comprising SiP:C:As;
forming a second source/drain region in the second recess, the second source/drain region comprising the single continuous material, wherein the single continuous material of the second source/drain region merges with the single continuous material of the source/drain region; and
forming a gate over the semiconductor fin adjacent the source/drain region, the gate extending in a second direction perpendicular the first direction.

US Pat. No. 11,069,577

NANOSHEET TRANSISTORS WITH DIFFERENT GATE DIELECTRICS AND WORKFUNCTION METALS

INTERNATIONAL BUSINESS MA...


1. A method for forming a semiconductor device, comprising:patterning a stack of layers that includes channel layers, n-type doped first sacrificial layers having a first thickness between the channel layers, and carbon-doped second sacrificial layers having a second thickness between the channel layers and the first sacrificial layers, to form one or more device regions, wherein the second thickness is less than a dislocation thickness to cause dislocations between the second sacrificial layers and the channel layers, and wherein a combination of the first thickness and the second thickness is greater than the dislocation thickness;
recessing the first sacrificial layers and the second sacrificial layers relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the first sacrificial layers and respective second sacrificial layers;
forming inner spacers in recesses formed by the recessing of the first sacrificial layers and the second sacrificial layers; and
etching away the first sacrificial layers and the second sacrificial layers to leave the channel layers suspended.

US Pat. No. 11,069,576

METHOD OF FORMING MULTI-THRESHOLD VOLTAGE DEVICES USING DIPOLE-HIGH DIELECTRIC CONSTANT COMBINATIONS AND DEVICES SO FORMED

Samsung Electronics Co., ...


1. A semiconductor device comprising:a substrate; and
a plurality of components on the substrate, each of the plurality of components including a source, a drain, a channel and a gate structure, the channel being between the source and drain, the gate structure adjacent to the channel region, the gate structure for a first portion of the plurality of components including a first dipole combination, the gate structure for a second portion of the plurality of components including a second dipole combination different from the first dipole combination, the first dipole combination including a first dipole layer and a first high dielectric constant layer on the first dipole layer, the second dipole combination including a second dipole layer and a second high dielectric constant layer on the second dipole layer, the gate structure further including a work function metal layer and a contact metal layer, the second dipole combination being different from the first dipole combination, the first dipole layer and the second dipole layer being selected from lanthanum oxide, lanthanum silicon oxide, aluminum oxide and yttrium oxide, and the first high dielectric constant layer and the second high dielectric constant layer including hafnium oxide, wherein the gate structure for a third portion of the plurality of components includes a third dipole combination different from the first and second dipole combinations, the third dipole combination including a third dipole layer and a third high dielectric constant layer on the third dipole layer, the third dipole combination being different from the first dipole combination and the second dipole combination.

US Pat. No. 11,069,575

SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF

Semiconductor Manufacturi...


1. A semiconductor device manufacturing method, comprising:providing a substrate structure that comprises a substrate, a source region on the substrate, and a gate structure on the source region;
forming cavities on two opposing sides of the gate structure;
forming electrodes that are at least partially positioned in the cavities, with forming each of the electrodes comprising: forming an electrode body that has an outer surface and subsequently forming an amorphous layer on the outer surface of the electrode body;
forming a dielectric layer covering the electrodes and the gate structure on the substrate structure;
after the amorphous layer has been formed, etching the dielectric layer to form a contact hole exposing the amorphous layer;
forming a conductive adhesive layer on a side of the contact hole, wherein the conductive adhesive layer exposes a face of the amorphous layer; and
forming a contact component in the contact hole and on the conductive adhesive layer, wherein the contact component directly contacts the face of the amorphous layer.

US Pat. No. 11,069,574

WAFER PROCESSING METHOD INCLUDING APPLYING A POLYESTER SHEET TO A WAFER

DISCO CORPORATION, Tokyo...


1. A wafer processing method for dividing a wafer along a plurality of division lines to obtain a plurality of individual device chips, the division lines being formed on a front side of the wafer, the wafer processing method comprising:a preparing step of preparing a ring frame having an inside opening for accommodating the wafer;
a providing step of positioning the wafer in the inside opening of the ring frame and providing a polyester sheet having no adhesive layer on a back side of the wafer and on a back side of the ring frame, such that the polyester sheet is in direct contact with the back side of the wafer and the back side of the ring frame;
a uniting step of heating the polyester sheet while applying a pressure to the polyester sheet after performing the polyester sheet providing step, thereby uniting the wafer and the ring frame through the polyester sheet by thermocompression bonding to form a frame unit in a condition where the wafer and the ring frame are exposed;
a dividing step of cutting the wafer along each division line by using a cutting apparatus including a rotatable cutting blade after performing the uniting step, thereby dividing the wafer into the individual device chips; and
a pickup step of applying an ultrasonic wave to the polyester sheet in each of the plurality of separate regions corresponding to each device chip, pushing up each device chip through the polyester sheet, then picking up each device chip from the polyester sheet after performing the dividing step.

US Pat. No. 11,069,573

WAFER LEVEL PACKAGE STRUCTURE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...


1. A method comprising:forming a first package comprising:attaching a first die to a first interconnect structure;
forming a first set of electrical connectors on an active surface of the first die;
providing a release film over the first set of electrical connectors;
forming a plurality of through vias adjacent the first die, each of the plurality of through vias having a first end adjoining the first interconnect structure and a second end extending in a direction away from the first interconnect structure;
encapsulating the first die and the plurality of through vias with a molding material;
planarizing the molding material to expose top surfaces of the release film and second ends of the plurality of through vias;
forming a second interconnect structure over the molding material, the first set of electrical connectors, and the plurality of through vias, the second interconnect structure being coupled to the first set of electrical connectors and the plurality of through vias; and

attaching a second die to the second interconnect structure using a second set of electrical connectors.

US Pat. No. 11,069,572

SEMICONDUCTOR DEVICE AND FORMING METHOD THEREOF

Semiconductor Manufacturi...


15. A semiconductor device, comprising:a substrate, a first fin and a second fin adjacent to each other and arranged in parallel on the substrate, an isolation structure covering a portion of sidewalls of the first second fins, a gate structure across the first fin or the second fin, the gate structure covering a portion of the isolation structure, a first doped source/drain region disposed in the first fin on both sides of the gate structure, and a second doped source/drain region disposed in the second fin on both sides of the gate structure, and an interlayer dielectric layer on the isolation structure, covering tops and sidewalls of the first and second fins, and top and sidewalls of the gate structure,
a first through hole in the interlayer dielectric layer, exposing the first doped source/drain region or the second doped source/drain region, and a first plug in the first through hole, and
a second through hole in the interlayer dielectric layer on the isolation structure, and a second plug in the second through hole, wherein the second plug is connected to the first plug.

US Pat. No. 11,069,571

HIGH SPEED, HIGH DENSITY, LOW POWER DIE INTERCONNECT SYSTEM

GULA CONSULTING LIMITED L...


1. A system comprising:a first die including a plurality of conducting layers and a downwardly-facing surface;
a first inductive coupling portion arranged along the downwardly-facing surface of the first die;
a second die having one or more conducting layers and an upwardly-facing surface;
a second inductive coupling portion arranged along the upwardly-facing surface of the second die;
a third die including a plurality of conducting layers and a downwardly-facing surface, wherein the downwardly-facing surface of the third die is non-conductive;
wherein:the first die and the third die are conductively coupled in a flip-chip orientation;
the first inductive coupling portion and the second inductive coupling portion are configured to inductively couple the first die with the second die; and
the downwardly-facing surface of the first die and the upwardly-facing surface of the second die are separated by an interface material comprising at least one of a heat conductor or an interposer.


US Pat. No. 11,069,570

METHOD FOR FORMING AN INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...


1. A method of forming an interconnect structure, comprising:providing a semiconductor substrate;
depositing a photoresist and a bottom anti-reflective coating (BARC) layer on the semiconductor substrate;
forming an opening in the photoresist and the BARC layer and a portion of the semiconductor substrate;
depositing a conductive material in the opening at a first speed and over the photoresist and the BARC layer at a second speed, wherein the first speed is greater than the second speed; and
planarizing the conductive material and the semiconductor substrate.

US Pat. No. 11,069,569

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...


1. A semiconductor device comprising:a substrate;
a plurality of lower electrodes disposed on the substrate, and including a plurality of first lower electrodes and a plurality of second lower electrodes that are respectively arranged in a first direction and alternately arranged in a second direction perpendicular to the first direction, each of the plurality of second lower electrodes being offset from each of the plurality of first lower electrodes with respect to the second direction;
a support structure pattern contacting the plurality of lower electrodes;
a plurality of openings disposed in the support structure pattern, arranged in the first direction and in the second direction, one of the plurality of openings exposes only two of the plurality of first lower electrodes and exposes only two of the plurality of second lower electrodes among the plurality of lower electrodes;
a dielectric layer disposed on the plurality of lower electrodes and the support structure pattern; and
an upper electrode disposed on the dielectric layer, whereina first width of the one of the plurality of openings in the first direction is less than a second width of the one of the plurality of openings in the second direction,
an area of a top surface of at least one of the two of the plurality of first lower electrodes is smaller than an area of a top surface of at least one of the two of the plurality of second lower electrodes,
and

the plurality of openings are offset from one another with respect to the first direction and with respect to the second direction.

US Pat. No. 11,069,568

ULTRA-THIN DIFFUSION BARRIERS

Applied Materials, Inc., ...


1. A method of forming a semiconductor device, comprising:positioning a device intermediate in a process chamber, the device intermediate including a dielectric layer disposed on a substrate and conductive features in contact with the substrate and extending through the dielectric layer;
depositing a silicon nitride barrier layer having a thickness of less than 70 angstroms on exposed surfaces of the dielectric layer and the conductive features via atomic layer deposition, the substrate maintained at a temperature of about 250° C. to about 550° C. during deposition of the barrier layer, wherein the barrier layer is formed of at least two portions, each portion formed by a separate deposition process; and
annealing the device intermediate having the barrier layer thereon at a temperature of about 350° C. to about 550° C. and a pressure of about 6.5 torr to about 760 torr.

US Pat. No. 11,069,567

MODULATING METAL INTERCONNECT SURFACE TOPOGRAPHY

International Business Ma...


1. An integrated circuit (IC) including a metal interconnect structure within a dielectric layer of the IC, the IC comprising:a recess, having at least one side and a bottom, in a top surface of the dielectric layer;
a surface modulation liner including at least two different metallic elements deposited onto the at least one side and onto the bottom of the recess, a first element of the at least two different metallic elements having a first standard electrode potential greater than a standard electrode potential of an interconnect metal, a second element of the at least two different metallic elements having a second standard electrode potential less than the standard electrode potential of the interconnect metal, wherein a difference between the standard electrode potential of the surface modulation liner and the standard electrode potential of the interconnect metal is less than a difference between the standard electrode potential of an element of the at least two different metallic elements and the standard electrode potential of the interconnect metal; and
the interconnect metal, wherein the interconnect metal is physically separated from the dielectric layer by the surface modulation liner, the interconnect metal filling a portion of the recess not filled by the surface modulation liner, the interconnect metal having a surface topography that is modulated.

US Pat. No. 11,069,566

HYBRID SIDEWALL BARRIER FACILITATING LOW RESISTANCE INTERCONNECTION

INTERNATIONAL BUSINESS MA...


1. A device, comprising:an interconnect material layer having an opening forming a first side of the interconnect material layer and a second side of the interconnect material layer and comprising a barrier liner that is discontinuous and coupled to sidewalls of the opening and wherein the barrier liner covers a bottom surface of the opening,
wherein, on the sidewalls, which are substantially parallel to one another, the barrier liner is discontinuous and formed as a plurality of semi-spherical portions spaced apart from one another such that one or more sections along the sidewalls fail to include the barrier liner, and wherein, across the bottom surface of the opening, between the two sidewalls, the barrier liner is continuous and formed as substantially flat portions;
a second barrier layer that provides a continuous coating over a first portion of the barrier liner that is discontinuous over the sidewalls, and a second portion of the barrier liner that is continuous across the bottom surface of the opening,
a seed enhancement liner coupled to and covering a first portion of the second electrical conductivity of the seed enhancement liner,
wherein the barrier liner is directly connected to and between the seed enhancement liner and the interconnect material layer, and wherein the seed enhancement liner is directly connected to and between an interconnect metallic material and the barrier liner; and
a cap layer formed as a continuous substantially flat layer across a top of:
the first side of the interconnect material layer, the second side of the interconnect material layer, the first portion of the barrier liner, the seed enhancement liner, the interconnect metallic material and the opening.

US Pat. No. 11,069,565

SEMICONDUCTOR INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF

Semiconductor Manufacturi...


1. A semiconductor interconnect structure, comprising:a substrate;
a first metal layer overlapping the substrate and having a cavity;
a dielectric layer overlapping the substrate, partially covering the first metal layer, having an undercut, and having a hole;
a second metal layer positioned inside the cavity and completely filling the undercut; and
a third metal layer overlapping the second metal layer and positioned inside the hole.

US Pat. No. 11,069,564

DOUBLE METAL PATTERNING

INTERNATIONAL BUSINESS MA...


1. A method of forming a semiconductor device, the method comprising:forming mandrels on a substrate, the mandrels comprising a first metal layer; and
disposing spacer material and fill material on the mandrels so as to form a pattern having a trench between portions of the first metal layer by entirely removing the fill material between two adjacent mandrels, the trench exposing a dielectric layer in direct contact with the substrate, the spacer material covering a top surface and sidewalls of the first metal layer; and
forming a second metal layer on the dielectric layer in direct contact with the substrate in the pattern so as to fill the trench between the portions of the first metal layer, the second metal layer being adjacent to the first metal layer, the first and second metal layers being separated by the spacer material.

US Pat. No. 11,069,563

METHOD FOR PROCESSING SUBSTRATE AND SUBSTRATE PROCESSING APPARATUS

EBARA CORPORATION, Toyko...


1. A method for processing a substrate, whereinthe substrate includes an insulating film layer where a groove is formed, a barrier metal layer, and a wiring metal layer in order from a bottom in at least a part of a region, and the method comprises:
(1) while the wiring metal layer is exposed to a surface of the substrate, a step of removing the surface of the substrate,
(2) while the wiring metal layer and the barrier metal layer are exposed to the surface of the substrate, a step of removing the surface of the substrate, and
(3) while the wiring metal layer, the barrier metal layer, and the insulating film layer are exposed to the surface of the substrate:a step of bringing the surface of the substrate into contact with a catalyst;
a step of supplying a process liquid between the catalyst and the surface of the substrate; and
a step of applying a voltage or flowing a current between the catalyst and the surface of the substrate.


US Pat. No. 11,069,562

PASSIVATION LAYER FOR INTEGRATED CIRCUIT STRUCTURE AND FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...


10. A method, comprising:forming metal lines over an interconnect structure that is formed above transistors;
depositing a liner oxide layer in contact with the metal lines;
forming a passivation oxide structure in contact with a top surface of the liner layer, wherein the liner layer is more porous than any position in the passivation oxide structure; and
forming a protection nitride layer in contact with a top surface of the passivation oxide structure.

US Pat. No. 11,069,561

METHODS OF FORMING ELECTRONIC DEVICES, AND RELATED ELECTRONIC DEVICES AND ELECTRONIC SYSTEMS

Micron Technology, Inc., ...


1. An electronic device, comprising:a dielectric structure;
interconnect structures extending into the dielectric structure and having uppermost vertical boundaries above uppermost vertical boundaries of the dielectric structure, each of the interconnect structures comprising:a conductive material; and
a barrier material intervening between the conductive material and the dielectric structure;

an additional barrier material covering surfaces of the interconnect structures above the uppermost vertical boundaries of the dielectric structure;
an isolation material overlying the additional barrier material; and
at least one air gap laterally intervening between at least two of the interconnect structures laterally-neighboring one another, the at least one air gap vertically extending from a lower portion of the isolation material, through the additional barrier material, and into the dielectric structure.

US Pat. No. 11,069,560

METHOD OF TRANSFERRING DEVICE LAYER TO TRANSFER SUBSTRATE AND HIGHLY THERMAL CONDUCTIVE SUBSTRATE

SHIN-ETSU CHEMICAL CO., L...


1. A method of transferring a device layer in a silicon on insulator (SOI) wafer obtained by stacking a silicon (Si) layer, an insulator layer, and the device layer to a transfer substrate, the method comprising:temporarily bonding a surface on which the device layer is formed of the SOI wafer to a supporting substrate using an adhesive for temporary bonding;
removing the Si layer of the SOI wafer until the insulator layer is exposed and obtaining a thinned device wafer;
coating only the transfer substrate with an adhesive for transfer and then bonding the insulator layer in the thinned device wafer to the transfer substrate via the adhesive for transfer;
thermally curing the adhesive for transfer under a load at the same time as or after bonding;
peeling off the supporting substrate; and
removing the adhesive for temporary bonding remaining on a surface of the device layer after peeling off;
whereinthe removing the Si layer includes:grinding and thinning the Si layer,
edge trimming a SOI wafer temporarily bonded to the supporting substrate and an adhesive for temporary bonding, and
removing the remaining Si layer by etching using an acid.



US Pat. No. 11,069,559

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING SAME

NEXCHIP SEMICONDUCTOR COR...


1. A method for forming a semiconductor structure, comprising:providing a pre-processed substrate with a first trench;
forming an auxiliary layer over the pre-processed substrate, wherein the auxiliary layer covers an inner surface of the first trench and a top surface of the pre-processed substrate;
forming a first filling dielectric over the pre-processed substrate, wherein the first filling dielectric covers the auxiliary layer and completely fills the first trench;
performing a first planarization process to remove a portion of the first filling dielectric until the auxiliary layer is exposed, wherein a remaining portion of the first filling dielectric is located in the first trench and surrounded by the auxiliary layer;
etching back the auxiliary layer so that a top surface of the auxiliary layer is lower than a top surface of the first filling dielectric;
forming a second filling dielectric over the pre-processed substrate, wherein the second filling dielectric covers the first filling dielectric, the auxiliary layer and the pre-processed substrate, and has a top surface higher than the top surface of the pre-processed substrate; and
performing a second planarization process until the top surface of the pre-processed substrate is exposed.

US Pat. No. 11,069,558

DUMMY FIN STRUCTURES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...


1. A device comprising:a first semiconductor fin extending upwards from a semiconductor substrate;
an isolation region around the first semiconductor fin;
an insulating fin extending from above a topmost surface of the isolation region to below the topmost surface of the isolation region, wherein the insulating fin has a different material composition than the isolation region; and
a gate stack disposed over and extending along sidewalls of the first semiconductor fin and over and along sidewalls of the insulating fin.

US Pat. No. 11,069,557

METHOD FOR PRODUCING THIN WAFER

SHIN-ETSU CHEMICAL CO., L...


1. A method for producing a thin wafer, comprising:separating a support body from a wafer laminate by irradiating the wafer laminate with light from the side of the support body of the wafer laminate; and
after the separating, removing a resin layer remaining on the wafer from the wafer by peeling;
wherein the wafer laminate includes a support body, an adhesive layer formed on the support body, and a wafer stacked with a surface thereof including a circuit plane facing the adhesive layer; and
the adhesive layer includes only a resin layer A with a light-blocking property, and a resin layer B including a thermosetting silicone resin or a non-silicone thermoplastic resin in this order from the side of the support body,
wherein the resin layer A with a light-blocking property has a transmissivity of 20% or less at a wavelength of 355 nm and an absorption maximum wavelength of 300 to 500 nm.

US Pat. No. 11,069,556

MICRO COMPONENT STRUCTURE

PlayNitride Display Co., ...


1. A micro component structure, comprising:a substrate;
at least one micro component disposed on the substrate, having a spacing from the substrate, and having at least one top surface; and
a fixing structure disposed on the substrate and comprising at least one covering portion and at least one connecting portion, wherein the at least one covering portion is disposed on a portion of the at least one top surface of the at least one micro component, the at least one connecting portion is connected to an edge of the at least one covering portion and extends onto the substrate, and at least one of the at least one covering portion and the at least one connecting portion comprises at least one patterned structure,
wherein the at least one patterned structure is at least one groove, and the at least one connecting portion comprises the at least one groove,
wherein from a top view, a width ratio of the at least one groove to the connecting portion along a cutting line is greater than or equal to 0.2 and less than or equal to 0.8, and a ratio of an area of the at least one connecting portion occupied by the at least one groove to an area of the at least one connecting portion is greater than or equal to 0.2 and less than or equal to 0.8.

US Pat. No. 11,069,555

DIE ATTACH SYSTEMS, AND METHODS OF ATTACHING A DIE TO A SUBSTRATE

ASSEMBLEON B.V., Eindhov...


1. A die attach system comprising:a support structure for supporting a substrate;
a die supply source including a plurality of die for attaching to the substrate;
a bond head for bonding a die from the die supply source to the substrate, the bond head including a bond tool for contacting the die supply source during transfer of the die from the die supply source to the substrate;
a first motion system for moving the bond head including the bond tool along a first axis; and
a second motion system, independent of the first motion system, for moving the bond tool along the first axis.

US Pat. No. 11,069,554

CARBON NANOTUBE ELECTROSTATIC CHUCK

Applied Materials, Inc., ...


1. A platen comprising:a dielectric layer having openings on a top surface, wherein all openings are used for lift pins and/or ground pins;
a base;
one or more electrodes disposed between the dielectric layer and a top surface of the base or embedded in the base; and
a plurality of vertically aligned carbon nanotubes disposed on the top surface of the dielectric layer, wherein a height of the plurality of vertically aligned carbon nanotubes is between 1 and 500 ?m and wherein the vertically aligned carbon nanotubes transfer heat between the platen and a workpiece disposed on the platen.

US Pat. No. 11,069,553

ELECTROSTATIC CHUCK WITH FEATURES FOR PREVENTING ELECTRICAL ARCING AND LIGHT-UP AND IMPROVING PROCESS UNIFORMITY

Lam Research Corporation,...


1. A substrate support for a substrate processing system, the substrate support comprising:a baseplate;
a bond layer provided on the baseplate; and
a ceramic layer arranged on the bond layer, whereinthe ceramic layer includes a first region and a second region located radially outward of the first region,
the first region has a first thickness,
the second region has a second thickness such that a lower surface of the ceramic layer steps upward from the first region to the second region, and
the first thickness is greater than the second thickness,

wherein the baseplate includes heat transfer gas supply holes arranged to supply heat transfer gas to an underside of the ceramic layer, and wherein the heat transfer gas supply holes are configured for fluid communication with a heat transfer gas source, and
wherein the heat transfer gas supply holes are arranged directly under an outer edge of the second region but not under the first region.

US Pat. No. 11,069,552

MEASUREMENT SYSTEM, SUBSTRATE PROCESSING SYSTEM, AND DEVICE MANUFACTURING METHOD

NIKON CORPORATION, Tokyo...


1. A measurement system used in a manufacturing line for micro-devices, the measurement system comprising:a plurality of measurement devices in which each device performs measurement processing on substrates; and
a carrying system to perform delivery of the substrates to and from the plurality of measurement devices, wherein
the plurality of measurement devices includes a first measurement device that acquires position information on a plurality of marks formed on the substrates, and a second measurement device that acquires position information on the plurality of marks formed on the substrates, and
the position information on the plurality of marks formed on one of the substrates can be acquired under a setting of a first predetermined condition in the first measurement device, and the position information on the plurality of marks formed on another one of the substrates can be acquired under a setting of a second predetermined condition different from the first predetermined condition in the second measurement device, the position information is utilized in an exposure processing on the substrates by an exposure apparatus that is provided separately from the measurement devices in the manufacturing line.

US Pat. No. 11,069,551

METHOD OF DAMPENING A FORCE APPLIED TO AN ELECTRICALLY-ACTUATABLE ELEMENT


1. A method of dampening a force applied to an electrically-actuatable element during a transfer of the electrically-actuatable element from a first side of a first substrate to a second substrate, the method comprising:positioning a needle adjacent a second side of the first substrate opposite the first side of the first substrate;
moving the needle, via a needle actuator, to a position at which the needle presses on the second side of the first substrate to press the electrically-actuatable element into contact with the second substrate disposed adjacent the first side of the first substrate; and
dampening the force applied to the electrically-actuatable element when the needle presses the electrically-actuatable element into contact with the second substrate.

US Pat. No. 11,069,550

LOAD PORT

HIRATA CORPORATION, Kuma...


1. A load port comprising:a port plate including an opening portion capable of taking in and out a substrate; and
a placing table on which a container that stores the substrate is placed,
wherein the placing table comprises:
a base portion;
a dock plate on which the container is placed;
a support unit provided between the base portion and the dock plate and configured to support the dock plate such that the dock plate can move between a first position on a side of the port plate and a second position apart from the port plate; and
a cam mechanism configured to move the dock plate between the first position and the second position with respect to the base portion,
the support unit includes a slider on which the dock plate is placed and which is configured to move together with the dock plate,
the cam mechanism includes:
a driving mechanism provided on the base portion; and
a cam plate which is connected to the slider and in which a cam groove is formed,
the driving mechanism includes:
a rotation driving unit;
a rotation shaft rotated by the rotation driving unit;
a long piece-shaped rotation member fixed to the rotation shaft and configured to rotate about the rotation shaft as a rotation center; and
a first cam follower and a second cam follower, which are provided in the rotation member, and
the cam groove includes:
a first cam groove engaging with the first cam follower; and
a second cam groove formed at a position different from the first cam groove in a moving direction of the dock plate and engaging with the second cam follower.

US Pat. No. 11,069,549

OVERHEAD TRANSPORT VEHICLE, OVERHEAD TRANSPORT SYSTEM, AND CONTROL METHOD FOR OVERHEAD TRANSPORT VEHICLE

Murata Machinery, Ltd., ...


1. A transport system includinga track provided on a ceiling or in a vicinity of the ceiling, and an overhead transport vehicle comprising:
a traveler that travels on a track provided on a ceiling or in a vicinity of the ceiling;
a main body mounted on the traveler;
a transferer including a holder to hold an article, a mover to move the holder between a storing position at which the article held by the holder is stored within the main body and an exiting position at which the article exits the main body, and a rotator to rotate the holder about a vertical rotation axis, the transferer receiving or delivering the article from or to a transfer destination where the article is to be placed in a prescribed orientation; and
a controller to control operations of the traveler and the transferer, wherein
the main body has an inner wall at a position at which the article held by the holder comes in contact therewith when the holder set at the storing position is rotated by a predetermined angle by the rotator,
the controller causes the traveler to travel in a state where the holder is set at the storing position by the mover, and when the article is received from or delivered to the transfer destination by means of the transferer, causes the rotator to rotate the holder by the predetermined angle or more in a state where the holder is positioned at the exiting position by the mover to align the article held by the holder with the prescribed orientation of the transfer destination, and the mover includes a lift driver that causes the holder to ascend or descend between the storing position and the exiting position at which the article held by the holder exits downward from the main body, wherein
the overhead transport vehicle includes a lateral extender that advances or retracts the holder laterally with respect to the track;
the track has a straight section and a curved section connected to the straight section;
the transfer destination is provided on a lower and lateral side of the curved section; and
when the article is received from or delivered to the transfer destination by the transferer, the controller performs control to
cause the traveler to stop in the curved section of the track,
cause the lift driver to lower the holder to the exiting position,
cause the rotator to rotate the holder to align the article held by the holder with the prescribed orientation of the transfer destination,
cause the lateral extender to advance the lift driver to a position at which the holder or the article is directly above the transfer destination, and
cause the lift driver to lower the holder.

US Pat. No. 11,069,548

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING SYSTEM

Tokyo Electron Limited, ...


1. A substrate processing method comprising:placing a substrate storage container storing a substrate on a load port;
automatically determining a type of the substrate stored in the placed substrate storage container;
by referring to a storage unit that stores a parameter data set related to a transport condition for each substrate type, controlling transport of the substrate stored in the substrate storage container based on the parameter data set corresponding to the automatically determined type of the substrate to process the substrate, and
after automatically determining the type of the substrate, and before transporting the substrate stored in the substrate storage container, performing mapping based on conditions set in the parameter data set to detect an abnormality of the substrate stored in the substrate storage container.

US Pat. No. 11,069,547

IN-SITU TEMPERATURE MEASUREMENT FOR INSIDE OF PROCESS CHAMBER

Applied Materials, Inc., ...


1. A process chamber comprising:a chamber body of a semiconductor process chamber having sidewalls;
a lid; and
a temperature measurement kit further comprising:a view port disposed through at least one sidewall of the semiconductor process chamber, the view port having a window transmissive to IR radiation;
a mounting bracket coupled to a first intermediate bracket by a first actuator;
a second intermediate bracket coupled to the first intermediate bracket by a second actuator;
an IR sensor mounting bracket coupled to the second intermediate bracket by a third actuator, the first actuator configured to provide rotational movement along an X axis, the second actuator configured to provide rotational movement along a Y axis, and the third actuator configured to provide rotational movement along a Z axis;
an IR sensor mounted to the IR sensor mounting bracket, the IR sensor mounting bracket configured to reposition the IR sensor to measure an emitted wavelength through the view port of two or more regions of the processing chamber; and
a mounting plate attached to the mounting bracket and the mounting plate is coupled to the chamber body using one or more fasteners.


US Pat. No. 11,069,546

SUBSTRATE PROCESSING SYSTEM

TOKYO ELECTRON LIMITED, ...


1. A substrate processing system, comprising:a first processing block comprising a first processing unit configured to perform a process on a substrate with a first surface of the substrate facing upward, and a first transfer device configured to carry the substrate into/from the first processing unit;
a second processing block comprising a second processing unit configured to perform a process on the substrate with a second surface of the substrate, which is opposite to the first surface, facing upward, and a second transfer device configured to carry the substrate into/from the second processing unit; and
a reversing device provided on a transfer path of the substrate from the first processing block to the second processing block, and configured to reverse the substrate; and
a delivery block comprising a first transit unit provided at a position allowed to be accessed by the first transfer device and configured to accommodate therein the substrate with the first surface facing upward; a second transit unit provided at a position allowed to be accessed by the second transfer device and configured to accommodate therein the substrate with the second surface facing upward; and a delivery device configured to carry the substrate into/from the first transit unit and the second transit unit,
wherein the reversing device is disposed within the delivery block,
the first processing block and the second processing block are arranged in a height direction thereof,
the first transit unit and the second transit unit corresponding to the first processing block and the second processing block respectively are arranged in a height direction thereof,
the delivery device is different from the first transfer device and the second transfer device, and configured to transfer the substrate into/from the reversing device, and
the reversing device being located at a position that is inaccessible by the first and second transfer devices such that the first and second transfer devices do not access the reversing device.

US Pat. No. 11,069,545

SUBSTRATE PROCESSING APPARATUS, TEMPERATURE CONTROL METHOD, AND TEMPERATURE CONTROL PROGRAM

TOKYO ELECTRON LIMITED, ...


1. A substrate processing apparatus comprising:a placing table having a placement surface on which one or both of a substrate and a ring member arranged to surround the substrate are placed, the placement surface being divided into a plurality of regions in each of which a heater is provided so as to adjust a temperature therein;
a calculator configured to calculate a target temperature of the heater in each divided region in which a critical dimension at a predetermined measurement point of the substrate satisfies a predetermined condition when a predetermined substrate processing is performed on the substrate placed on the placement surface, using a prediction model to predict the critical dimension at the measurement point based on a temperature of the heater in each divided region as a parameter and by taking into consideration an influence of a temperature of a heater in another divided region other than a divided region including the measurement point, according to a distance between the measurement point in the divided region and the another divided region; and
a heater controller configured to control the heater in each divided region to reach the target temperature calculated by the calculator when the substrate processing is performed on the substrate placed on the placement surface.

US Pat. No. 11,069,544

RAPID THERMAL PROCESSING METHOD AND APPARATUS FOR PROGRAMMING THE PINNED LAYER OF SPINTRONIC DEVICES

MultiDimension Technology...


1. A rapid thermal processing apparatus for programming a pinned layer of spintronic devices, the apparatus comprising:a rapid thermal annealing light source,
a reflective cover,
a magnet configured to produce a constant magnetic field, and
a wafer,
wherein the reflective cover at least comprises a transparent insulating layer and a reflective layer,
the transparent insulating layer and the reflective layer being sequentially coated on the wafer such that the transparent insulating layer is on and in direct contact with the wafer and the reflective layer is on and in direct contact with the transparent insulating layer, the reflective layer further being patterned with an opening in the reflective layer corresponding to a heating area of the wafer,
wherein the light source is configured to send light through the opening of the reflective layer and through the transparent insulating layer to the heating area of the wafer, and
wherein the rapid thermal processing apparatus is configured to locally program an antiferromagnetic layer on the wafer by controlling exposure time of the light source-for heating the heating area on the wafer to a temperature above a blocking temperature of the antiferromagnetic layer, and in the presence of the magnetic field.

US Pat. No. 11,069,543

LAMINATE PROCESSING METHOD

DISCO CORPORATION, Tokyo...


1. A laminate processing method of dividing a laminate into individual image sensor chips, the laminate in which a glass substrate is disposed through a transparent adhesive layer on a front surface of a wafer where a plurality of image sensors are formed in a plurality of respective regions demarcated by a plurality of crossing division lines, the method comprising:a cut groove forming step of positioning a cutting blade from a side of the glass substrate constituting the laminate and cutting a region of the glass substrate corresponding to each of the division lines, thereby forming a cut groove in each of the division lines that reaches the adhesive layer in the glass substrate;
a division start point forming step of positioning a focal point of a laser beam having a transmission wavelength to the wafer inside a region of the wafer corresponding to each of the division lines from a back surface of the wafer, applying the laser beam thereto, continuously forming a modified layer inside the wafer, and forming a crack reaching from the modified layer to the adhesive layer, thereby forming a division start point;
a laminate supporting step of supporting the glass substrate side of the laminate through an expandable tape to an annular frame having an inside opening with a size large enough to accommodate the laminate therein, at least after the cut groove forming step is carried out;
a modified layer removing step of positioning a cutting blade to the region of the wafer corresponding to each of the division lines and cutting while supplying cutting water into which a water-soluble resin is mixed from the wafer side of the laminate, thereby removing the modified layer formed inside the wafer;
a dividing step of, after the modified layer removing step is carried out, expanding the expandable tape, and dividing the laminate into individual image sensor chips; and
a cleaning step of supplying cleaning water from the back surface of the wafer with a state in which the expandable tape is expanded being maintained, thereby cleaning the laminate.

US Pat. No. 11,069,542

CLEANING WATER SUPPLY DEVICE

KURITA WATER INDUSTRIES L...


1. A cleaning water supply device, comprising:a cleaning water production unit that produces cleaning water at a certain concentration by adding a pH adjuster and/or an oxidation-reduction potential adjuster to ultrapure water;
a storage tank that stores the cleaning water from the cleaning water production unit therein; and
a plurality of supply means for supplying the cleaning water in the storage tank to cleaning machines, each supply means including a branching piping directly connected to the storage tank, a pump attached to the branching piping, a pipe connecting the branching piping to one of the cleaning machines through the pump, and a return piping extending from the pipe to the storage tank to return part of the cleaning water to the storage tank.

US Pat. No. 11,069,541

SEMICONDUCTOR DEVICE PACKAGE FOR DEBONDING SUBSTRATE ASSEMBLY FROM CARRIER SUBSTRATE USING LIGHT AND METHOD OF MANUFACTURING SAME

Samsung Electronics Co., ...


1. A method for manufacturing a semiconductor device package, the method comprising:accommodating a substrate, with a semiconductor chip mounted thereon, in a cavity located in a center of a carrier substrate, the carrier substrate having a support portion in contact with a side wall of the cavity to form an upper surface of the side wall, the support portion surrounding the cavity, and the carrier substrate formed of a transparent material;
defining a molding portion of the substrate by pressing the support portion and an edge region of the substrate; and
molding the molding portion to cover the semiconductor chip.

US Pat. No. 11,069,540

PACKAGE ON PACKAGE AND A METHOD OF FABRICATING THE SAME

PHOENIX PIONEER TECHNOLOG...


1. A package on package, comprising:an interposer substrate including:an insulating layer having a first surface and a second surface opposing the first surface and made of a molding compound, a primer or epoxy;
a wiring layer formed on the first surface of the insulating layer and being in communication with the second surface of the insulating layer;
a wiring build-up layer structure formed on the second surface of the insulating layer and electrically connected to the wiring layer, wherein the wiring build-up layer structure comprises a plurality of conductive pillars;
an insulating protection layer formed on the second surface of the insulating layer and the wiring layer and encapsulating the wiring build-up layer structure, wherein the wiring build-up layer structure is exposed from the insulating protection layer; and
a plurality of external connection pillars disposed on, protruding from and electrically connected to the wiring build-up layer structure, wherein each of the external connection pillars comprises a connection portion connected to and being in direct contact with each of the conductive pillars and a main portion disposed on the connection portion, protruding from the insulating protection layer and having a circumference surface exposed from the insulating protection layer;

at least one integrated circuit (IC) or IC packaging member stacked on the wiring layer of the interposer substrate; and
an IC packaging member stacked below and electrically connected to the external connection pillars of the interposer substrate, wherein the IC packaging member is in an elevated space of the external connection pillars.

US Pat. No. 11,069,539

3D PACKAGES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...


1. An interposer comprising:a first underbump metallization (UBM) extending from a topmost surface of a first layer of the interposer to a bottommost surface of the first layer of the interposer, wherein a first solder ball directly contacts the first UBM;
a second UBM extending completely through a second layer of the interposer, wherein a second solder ball directly contacts the second UBM;
an interconnecting structure between the first layer and the second layer, the interconnecting structure comprising:a plurality of insulating films; and
a plurality of conductive lines in the plurality of insulating films, the plurality of conductive lines electrically connecting the second UBM to the first UBM, wherein the interposer is free of any active devices.


US Pat. No. 11,069,538

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

SHINDENGEN ELECTRIC MANUF...


1. A semiconductor device comprising:a substrate provided with a first conductive layer and a second conductive layer on an upper surface of the substrate;
a semiconductor element disposed on the upper surface of the substrate, the semiconductor element having: a first terminal provided on a lower surface of the semiconductor element and electrically connected to the first conductive layer, and a second terminal provided on an upper surface of the semiconductor element and the second terminal receiving a control signal;
a sealing portion that seals the substrate and the semiconductor element;
a lead frame that has one end in contact with a upper surface of the second conductive layer provided at an end of the upper surface of the substrate in the sealing portion, and that has the other end exposed from the sealing portion;
a first control conductive bonding material bonds between the second conductive layer and the one end of the lead frame at the end of the substrate, and has electrical conductivity;
a connector has a one end portion contacting the upper surface of the second terminal of the semiconductor element in the sealing portion, and the other end in contact with the second conductive layer, the connector electrically connecting the second conductive layer and the second terminal on the upper surface of the semiconductor element;
a second control conductive bonding material bonds between the upper surface of the second terminal of the semiconductor element and the one end of the connector, and has electrical conductivity; and
a third control conductive bonding material bonds the second conductive layer of the substrate and the other end of the connector, and has electrical conductivity,
wherein the one end portion of the connector comprising:a horizontal portion;
a first inclined portion that is connected to the horizontal portion and is located closer to the tip end side of the one end than the horizontal portion, and the first inclined portion having a shape inclined downward from the horizontal portion; and
a control bending portion that is connected to the first inclined portion and positioned at the tip of the one end portion, and the control bending portion bent downwardly along the bending axis direction, and

wherein a lower surface of the control bending portion is in contact with an upper surface of the second terminal.

US Pat. No. 11,069,537

METHOD FOR DELIDDING A HERMETICALLY SEALED CIRCUIT PACKAGE

Hamilton Sundstrand Corpo...


1. A method of delidding an integrated circuit (IC) package, comprising:directing a laser beam along a cut line of an integrated circuit package, wherein the integrated circuit package includes a body and a lid, the lid defining a cavity therein, and wherein the lid includes a side wall extending from the body to a top surface, the top surface opposed from the body, the cut line defining a removable portion, wherein the removable portion includes the top surface of the lid;
cutting along the cut line; and
removing the removable portion after the directing.

US Pat. No. 11,069,536

DEVICE MANUFACTURING METHOD

TOKYO ELECTRON LIMITED, ...


1. A method of manufacturing a device, the method comprising:a preparation step of preparing a workpiece having a recess formed therein;
a burying step of burying a sacrificial material composed of a thermally decomposable organic material in the recess;
a lamination step of laminating a preliminary sealing film on the sacrificial material buried in the recess;
a first removal step of removing the sacrificial material in the recess through the preliminary sealing film, by annealing the workpiece at a first temperature and thermally decomposing the sacrificial material,
a processing step of performing a predetermined process on a portion other than the recess in the workpiece, in a state in which the recess is covered with the preliminary sealing film; and
a second removal step of removing the preliminary sealing film.

US Pat. No. 11,069,535

ATOMIC LAYER ETCH OF TUNGSTEN FOR ENHANCED TUNGSTEN DEPOSITION FILL

Lam Research Corporation,...


1. A method comprising:preferentially etching a first amount of a metal in a feature on a substrate at or near an opening of the feature relative to an interior region of the feature by(i) exposing the feature to a halogen-containing gas to form a modified surface of the first amount of the metal;
(ii) exposing the modified surface to an activation gas; and
(iii) applying a bias to the substrate during at least one of (i) and (ii) using a bias power.


US Pat. No. 11,069,534

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES

TAIWAN SEMICONDUCTOR MANU...


1. A method of manufacturing a semiconductor device including a field effect transistor, comprising:forming a gate dielectric layer over a channel region;
forming a first conductive layer over the gate dielectric layer;
forming a protective layer at a surface region of the first conductive layer;
forming a metallic layer by applying a metal containing gas on the protective layer;
removing the metallic layer by a wet etching operation using a solution,
wherein the protective layer protects the first conductive layer from the solution of the wet etching operation so that the protective layer remains at an end of the wet etching operation.

US Pat. No. 11,069,533

CMP SYSTEM AND METHOD OF USE

Taiwan Semiconductor Manu...


1. An apparatus comprising:a planarization device comprising a high-rate platen, a buffing platen, and a first nozzle;
a cleaning device comprising a second nozzle and one or more wafer holders; and
a capacitive deionization device comprising a first electrode and a second electrode, the capacitive deionization device being disposed on a surface of a polishing pad of the high-rate platen or the buffing platen.

US Pat. No. 11,069,532

METHOD FOR MANUFACTURING NICKEL SILICIDE

Shanghai Huali Integrated...


1. A method for manufacturing nickel silicide, comprising:Step 1: providing a semiconductor substrate, wherein the semiconductor substrate has an exposed silicon surface which is a formation region of nickel silicide, wherein the semiconductor substrate is formed with a source region and a drain region of a MOSFET, the formation region of the nickel silicide includes the source region and the drain region of the MOSFET, and an embedded epitaxial layer is formed in the source region or the drain region of the MOSFET to provide a stress for a channel region of the MOSFET to improve carrier mobility;
Step 2: carrying out pre-amorphization ion implantation to form an amorphous layer in the formation region of the nickel silicide, wherein an implantation source of the pre-amorphization ion implantation is xenon which is a non-radioactive inert gas with the maximum mass, so that uniformity of an interface layer between the amorphous layer and the exposed silicon surface is optimized, wherein a xenon source of the pre-amorphization ion implantation is gaseous, implantation energy is 0.5KeV-10KeV, an implantation dose is 1*1013 cm?2-1*1014 cm?2, a temperature is ?100° C.-25° C., and an implantation angle is 0-30°; and
Step 3: forming the nickel silicide in the formation region of the nickel silicide by self-alignment.

US Pat. No. 11,069,531

REPLACEMENT GATE METHODS THAT INCLUDE TREATING SPACERS TO WIDEN GATE

Taiwan Semiconductor Manu...


1. A method, comprising:forming a dummy dielectric layer over a substrate;
forming a dummy gate over the dummy dielectric layer;
forming a first spacer adjacent the dummy gate;
removing the dummy gate to form a cavity, wherein the cavity is defined at least in part by the first spacer;
performing a plasma treatment on portions of the first spacer, wherein the plasma treatment causes a material composition of the portions of the first spacer to change from a first material composition to a second material composition;
etching the portions of the first spacer having the second material composition to remove the portions of the first spacer having the second material composition; and
filling the cavity with a plurality of conductive materials to form a gate structure.

US Pat. No. 11,069,530

ETCHING PLATINUM-CONTAINING THIN FILM USING PROTECTIVE CAP LAYER

TEXAS INSTRUMENTS INCORPO...


1. A method of forming a microelectronic device, comprising:providing a substrate;
forming a platinum-containing layer over the substrate;
forming a cap layer comprising one selected from a group consisting essentially of a cap layer that is primarily aluminum and a cap layer that is primarily copper over the platinum-containing layer, wherein an interface between the cap layer and the platinum-containing layer is free of platinum oxide; and
removing the cap layer and at least a portion of the platinum-containing layer by a wet etch process, a same wet etchant of the wet etch process removing both the cap layer and at least the portion of the platinum containing layer, the cap layer having an etch rate at least twice the etch rate of the platinum containing layer in the same wet etchant.

US Pat. No. 11,069,529

SEMICONDUCTOR DEVICE WITH AT LEAST ONE LOWER-SURFACE SIDE LIFETIME CONTROL REGION

FUJI ELECTRIC CO., LTD., ...


1. A semiconductor device comprising:a semiconductor substrate having a drift region of a first-conductivity type;
a transistor portion provided in the semiconductor substrate; and
a diode portion that is provided in the semiconductor substrate, and is provided next to the transistor portion in a predetermined array direction,
wherein
each of the transistor portion and the diode portion has:a base region of a second-conductivity type provided above the drift region;
a plurality of trench portions that penetrate the base region, lie from an upper surface of the semiconductor substrate to the drift region, and extend in a direction of extension perpendicular to the array direction;
an at least one lower-surface side lifetime control region that includes a lifetime killer extending across a boundary between the transistor portion and the diode portion entirely within a lower-surface side relative to a middle in a depth direction between the upper surface and lower surface of the semiconductor substrate; and
an upper-surface side lifetime control region that includes a lifetime killer extending across a boundary between the transistor portion and the diode portion entirely within an upper-surface side in the semiconductor substrate relative to the lower-surface side lifetime control region, and

in the array direction, the transistor portion has a portion provided with the lower-surface side lifetime control region, and a portion not provided with the lower-surface side lifetime control region.

US Pat. No. 11,069,528

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...


1. A method for manufacturing an integrated circuit comprising:forming an opening within a mask over a hard mask material;
depositing a first gap-filling material along sidewalls of the opening;
depositing a second gap-filling material within the opening, the second gap-filling material being different from the first gap-filling material, the second gap-filling material comprising a metal oxide or a metal nitride;
removing the mask;
etching the first gap-filling material; and
patterning the hard mask material using the second gap-filling material as a mask, wherein a width of the second gap-filling material at one-half of a height of the second gap-filling material is less than a width of the second gap-filling material at a full height of the second gap-filling material.

US Pat. No. 11,069,527

LASER ASSISTED SIC GROWTH ON SILICON

Board of Trustees of Mich...


1. A heterojunction device comprising:a Si substrate; and
a photothermal film of SiC formed on a surface of the Si substrate,
the photothermal film of SiC having a Si:C ratio that increases or decreases from a SiC surface in contact with the Si substrate to an opposing SiC surface that is not in contact with the Si substrate,
wherein the photothermal film of SiC is a melt comprising Si derived from the Si substrate and C derived from a carbon source, and
wherein the photothermal film of SiC has a surface comprising at least one of a pyramidal or Gaussian texture.

US Pat. No. 11,069,526

USING A SELF-ASSEMBLY LAYER TO FACILITATE SELECTIVE FORMATION OF AN ETCHING STOP LAYER

TAIWAN SEMICONDUCTOR MANU...


1. A semiconductor device, comprising:a first conductive component;
a first interlayer dielectric (ILD) that surrounds the first conductive component;
a first dielectric layer disposed over the first ILD, wherein the first dielectric layer has a greater dielectric constant than the first ILD;
a second conductive component disposed over, and at least partially aligned with, the first conductive component, wherein at least a portion of the first dielectric layer is disposed between the first ILD and the second conductive component;
a second ILD that surrounds the second conductive component, and wherein the first dielectric layer has a lower etching rate than the second ILD;
an etching stop layer that is disposed between the first dielectric layer and the second ILD; and
at least a portion of a self-assembly layer disposed between the first conductive component and the etching stop layer but not between the first conductive component and the second conductive component.

US Pat. No. 11,069,525

METHODS FOR USING REMOTE PLASMA CHEMICAL VAPOR DEPOSITION (RP-CVD) AND SPUTTERING DEPOSITION TO GROW LAYERS IN LIGHT EMITTING DEVICES

LUMILEDS LLC, San Jose, ...


1. A method for growing a light emitting device, the method comprising:growing a p-type region over a growth substrate by at least one of RP-CVD and sputtering deposition in at least a reduced hydrogen environment that does not cause inoperability of at least the p-type region; and
growing an n-type region over the p-type region using a non-RP-CVD and non-sputtering deposition process, the p-type region and the n-type region comprising III-nitride materials.

US Pat. No. 11,069,524

METHODS FOR USING REMOTE PLASMA CHEMICAL VAPOR DEPOSITION (RP-CVD) AND SPUTTERING DEPOSITION TO GROW LAYERS IN LIGHT EMITTING DEVICES

LUMILEDS LLC, San Jose, ...


1. A method for growing a light emitting device, the method comprising:growing a device structure on a growth substrate using a non-RP-CVD and non-sputtering deposition process, the device structure including a n-type region and a p-type region stacked together; and
growing at least a portion of a layer of a tunnel junction on the device structure by using at least one of remote plasma chemical vapor deposition (RP-CVD) and sputtering deposition in a gaseous environment comprising one or more of a nitrogen-containing gas and a hydrogen-containing gas.

US Pat. No. 11,069,523

METHOD OF MATERIAL DEPOSITION

FEI Company, Hillsboro, ...


1. A method of charged particle beam induced material deposition onto a sample comprising:loading a substrate into a charged particle beam system, the substrate containing a region of interest;
providing a first precursor gas including a first gas species and a second gas species towards the substrate;
directing a charged particle beam toward the substrate to induce deposition from the first precursor gas of a first protective layer above the region of interest,
wherein the first protective layer is a composite mix of at least two materials, the at lease two materials including a first material having a first sputter rate and a second material having a second, different, sputter rate, and wherein the first gas species yields the first material of the composite mix and the second gas species yields the second material of the composite mix;
after depositing the first protective layer, providing a second precursor gas towards the substrate; and
directing a second charged particle beam toward the substrate to induce deposition from the second precursor gas of a second protective layer above the first protective layer.

US Pat. No. 11,069,522

SI PRECURSORS FOR DEPOSITION OF SIN AT LOW TEMPERATURES

ASM IP HOLDING B.V., Alm...


1. A method of depositing a silicon nitride thin film on a substrate in a reaction space comprising a susceptor and a showerhead plate by plasma enhanced atomic layer deposition (PEALD), the method comprising:carrying out a plurality of deposition cycles, at least one of the deposition cycles comprising:
(a) introducing a vapor-phase silicon reactant consisting of silicon, iodine and hydrogen into the reaction space;
(b) removing excess silicon reactant and reaction byproducts from the reaction space with the aid of a purge gas;
(c) contacting the substrate with a plasma generated from a reactant gas comprising nitrogen above the substrate and between the susceptor and the showerhead plate; and
(d) removing excess plasma and reaction byproducts from the reaction space with the aid of the purge gas;
wherein there is a gap of 0.5 to 5 cm between the susceptor and the showerhead plate;
wherein the plasma is produced by applying RF power with a density of from 0.02 W/cm2 to 2.0 W/cm2 to the reactant gas between the susceptor and the showerhead plate; and
wherein the reactant gas is flowed continuously to the reaction space throughout the deposition cycle.

US Pat. No. 11,069,521

SUBNANOMETER-LEVEL LIGHT-BASED SUBSTRATE CLEANING MECHANISM

Planar Semiconductor, Inc...


1. A substrate cleaning apparatus comprising:a substrate holder configured to hold and rotate a vertically-oriented substrate at various speeds;
an inner shield and an outer shield configured to at least partially surround the substrate holder during operation of the apparatus, each of the inner shield and the outer shield being configured to operate independently from each other in at least one of rotational speed and direction from the other shield; and
a front-side light source and a back-side light source, each of the front-side light source and the back-side light source being configured to emit and impinge at least one wavelength of light onto at least one face of the substrate to remove particles and organic contaminants from the at least one face of the substrate, each of the front-side light source and the back-side light source having an energy level selected for the substrate to remove the particles and the organic contaminants from the substrate and not cause damage to any surface of the substrate.

US Pat. No. 11,069,520

SUBSTRATE PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...


1. A substrate processing method, comprising:supplying a treatment liquid to a substrate held in a horizontal position;
substituting the treatment liquid supplied to the substrate with a solvent having a lower surface tension than the treatment liquid; and
drying the substrate by shaking off the solvent on the substrate at a preset rotation number so that an intermediate portion of the substrate located between a central portion and a peripheral portion of the substrate is last dried,
wherein the solvent, which has a temperature higher than a room temperature, is discharged toward a rear surface of the peripheral portion of the substrate, and
wherein an air flow flowing toward the peripheral portion of the substrate along an upper end portion of a recovery cup is generated and blown to the peripheral portion by machining the upper end portion to have an arc shape.

US Pat. No. 11,069,519

AMPLIFIER AMPLITUDE CONTROL FOR A MASS SPECTROMETER

Thermo Finnigan LLC, San...


1. A mass spectrometer, comprising:a quadrupole mass analyzer;
a resonant circuit configured to generate a first radio frequency (RF) signal applied to a first pair of rods of the quadrupole mass analyzer, the resonant circuit having a first resonant inductor used to store energy for generating the first RF signal at a first amplitude;
an amplitude control circuit having a first amplitude control inductor that is inductively coupled with the first resonant inductor, and having a first diode that is coupled with the first amplitude control inductor; and
a controller circuit configured to transfer energy from the first resonant inductor to the first amplitude control inductor to adjust the first RF signal from the first amplitude to a second amplitude by changing an operational state of the first diode.

US Pat. No. 11,069,517

PHYSICAL ISOLATION OF ADDUCTS AND OTHER COMPLICATING FACTORS IN PRECURSOR ION SELECTION FOR IDA

DH Technologies Developme...


1. A system for identifying precursor ions originating from an ion source device using a scanning sequential windowed precursor ion selection and mass analysis survey scan, comprising:an ion source device that ionizes and transforms a sample into an ion beam;
a mass filter receives the ion beam;
a mass analyzer; and
a processor in communication with the mass filter and the mass analyzer that
(a) instructs the mass filter to filter the ion beam by scanning a precursor ion mass selection window with a width smaller than a precursor ion mass range of interest across a precursor ion mass range of interest in overlapping steps, producing a series of overlapping precursor ion mass selection windows across the precursor ion mass range, and instructs the mass filter to transmit precursor ions from each precursor ion mass selection window of the series of overlapping precursor ion mass selection windows to the mass analyzer,
(b) instructs the mass analyzer to analyze the precursor ions of each precursor ion mass selection window of the series of overlapping precursor ion mass selection windows, producing a precursor ion spectrum for each overlapping precursor ion mass selection window and a plurality of precursor ion spectra for the precursor ion mass range,
(c) receives the plurality of precursor ion spectra from the mass analyzer,
(d) selects a precursor ion from the plurality of precursor ion spectra that has an intensity above a predetermined threshold,
(e) for the selected precursor ion, retrieves the intensities of the selected precursor ion from the plurality of precursor ion spectra for at least one scan of the precursor ion mass selection window across the precursor ion mass range and produces a trace that describes how the intensity of the selected precursor ion varies with the location of the precursor ion mass selection window expressed as the precursor ion mass-to-charge ratio (m/z) of the precursor ion mass selection window as the precursor ion mass selection window is scanned across the precursor ion mass range, and
(f) identifies the selected precursor ion as a precursor ion originating from the ion source device if the trace includes a nonzero intensity for the m/z value of the selected precursor ion.

US Pat. No. 11,069,516

ELECTRO STATIC LINEAR ION TRAP MASS SPECTROMETER

DH Technologies Developme...


1. An electrostatic linear ion trap for measuring induced current of one or more ions and reducing higher order frequency harmonics of the induced current by combining the induced current with measurements from reflecting reflectron plates, comprising:a first set of reflectron plates with holes in the center that are coaxially aligned along a central axis, wherein the first set of plates includes a first inlet plate followed by a first plurality of reflection plates followed by a first plurality of trapping plates;
a cylindrical pickup electrode positioned so that a first end of the pickup electrode is adjacent to the first inlet plate of the first set of plates and the pickup electrode is coaxially aligned with the first set of plates along the central axis;
a second set of reflectron plates with holes in the center that are coaxially aligned with the pickup electrode along the central axis, wherein the second set of plates includes a second inlet plate followed by a second plurality of reflection plates followed by a second plurality of trapping plates and wherein the second set of plates is positioned so that the second inlet plate is adjacent to a second end of the cylindrical pickup electrode;
a voltage power supply for applying separate voltages to one or more plates of the first set of reflectron plates and to one or more plates of the second set of reflectron plates in order to trap and oscillate one or more ions that have been received along the central axis through the holes of the first set of plates between the first set of plates and the second set of plates; and
measurement circuitry to measure a first induced current from the cylindrical pickup electrode, a second induced current from one or more plates of the first set of reflectron plates, and a third induced current from one or more plates of the second set of reflectron plates and to combine the first measured induced current with the second measured induced current and the third measured induced current to determine an induced current of the one or more ions and reduce higher order frequency harmonics of the induced current.

US Pat. No. 11,069,515

PULSED POWER MODULE WITH PULSE AND ION FLUX CONTROL FOR MAGNETRON SPUTTERING

Starfire Industries LLC, ...


1. An electrical power pulse generator system comprising:a main energy storage capacitor configured to supply a negative direct current (DC) power;
a kick energy storage capacitor configured to supply a positive DC power;
an output pulse rail;
a main pulse power transistor interposed between the main energy storage capacitor and the output pulse rail, wherein the main pulse power transistor includes a main power transmission control input for controlling power transmission from the main energy storage capacitor to the output pulse rail, through the main pulse power transistor;
a main pulse power transistor control line connected to the main power transmission control input of the main pulse power transistor;
a positive kick pulse power transistor interposed between the kick energy storage capacitor and the output pulse rail, wherein the positive kick pulse power transistor includes a kick power transmission control input for controlling power transmission from the kick energy storage capacitor to the output pulse rail, through the positive kick pulse power transistor; and
a positive kick pulse power transistor control line connected to the kick power transmission control input of the positive kick pulse transistor.

US Pat. No. 11,069,514

REMOTE CAPACITIVELY COUPLED PLASMA SOURCE WITH IMPROVED ION BLOCKER

APPLIED MATERIALS, INC., ...


1. A gas distribution apparatus comprising:a remote plasma source having a faceplate;
an ion blocker having a back surface facing the faceplate and a front surface defining a thickness, the back surface of the ion blocker spaced a distance from the faceplate to form a gap, the ion blocker comprising a plurality of openings extending through the thickness;
a showerhead having a back surface and a front surface, the back surface of the showerhead facing and spaced from the front surface of the ion blocker, the showerhead comprising a plurality of apertures to allow radicals from the remote plasma source to flow through the showerhead; and
a voltage regulator connected to the ion blocker and the showerhead to polarize the ion blocker relative to the showerhead;
wherein the ion blocker is polarized relative to the showerhead so that there are substantially no plasma gas ions passing through the showerhead.