US Pat. No. 11,031,390

BIDIRECTIONAL SWITCH HAVING BACK TO BACK FIELD EFFECT TRANSISTORS

Alpha and Omega Semicondu...

1. A method for forming a bi-directional semiconductor switching device, comprising:forming first and second vertical field effect transistors (FETs) in tandem from a semiconductor substrate, wherein a source for the first FET is on a first side of the substrate and a source for the second FET is on a second side of the substrate opposite the first side, wherein gates for both the first and second FETs are disposed in tandem in a common set of trenches formed in a drift region of the semiconductor substrate that is sandwiched between the source for the first FET and the source for the second FET, wherein the drift region forms a common drain for both the first FET and the second FET wherein the drift region is of a same conductivity type as the source for the first FET and the source for the second FET but at a lower carrier concentration than that of the source for the first FET and the source for the second FET.

US Pat. No. 11,031,389

SEMICONDUCTOR STRUCTURES OVER ACTIVE REGION AND METHODS OF FORMING THE STRUCTURES

GLOBALFOUNDRIES U.S. INC....

1. A semiconductor device comprising:an active region and a shallow trench isolation layer disposed above a substrate;
a plurality of source or drain regions disposed in the active region;
a plurality of gate stacks having a first and second gate stacks, wherein each gate stack is disposed in between the source or drain regions;
a plurality of trench contact structures having a first and second trench contact structures, wherein each trench contact structure is disposed on a corresponding source or drain region;
gate spacers with top surfaces, wherein the gate spacers are adjacent to the trench contact structures;
a gate cut region having a plurality of gate isolation structures disposed on the shallow trench isolation layer, wherein the first trench contact structure is also disposed on the shallow trench isolation and in between the gate isolation structures;
a gate cap dielectric layer disposed on the first or the second gate stack;
a trench cap dielectric layer disposed on a top surface of the first or the second trench contact structure and the top surfaces of the gate spacers, wherein the trench cap dielectric layer has a top surface that is coplanar with a top surface of the gate cap dielectric layer; and
a dielectric fill layer disposed on the gate isolation structures and adjacent to the trench cap dielectric layer.

US Pat. No. 11,031,388

SEMICONDUCTOR STRUCTURE AND DRIVING CHIP

Silergy Semiconductor Tec...

1. A semiconductor structure, comprising:a) a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first and second regions;
b) an isolation structure located in the isolation region, wherein the isolation structure comprises a first isolation ring having a first doping type, and a second isolation ring having a second doping type, wherein the first isolation ring is configured to absorb first carriers flowing from the first region to the second region, the second isolation ring is configured to absorb second carriers flowing from the second region to the first region, the first isolation ring comprises a first portion adjacent to the first region, and a second portion adjacent to the second region, and the second isolation ring is located between the first and second portions of the first isolation ring; and
c) a lateral blocking component formed between the first isolation ring and the second isolation ring in the isolation structure, wherein the lateral blocking component comprises a trench configured to block a lateral flow of the first and second carriers, in order to increase a flow path of the first and second carriers in the semiconductor substrate.

US Pat. No. 11,031,387

PN DIODES AND CONNECTED GROUP III-N DEVICES AND THEIR METHODS OF FABRICATION

Intel Corporation, Santa...

1. A semiconductor structure comprising:a silicon substrate;
a group III-N semiconductor material disposed on the silicon substrate;
a group III-N transistor structure disposed on the group III-N semiconductor material;
a well disposed in the silicon substrate, the well having a first conductivity type;
a doped region disposed in the well, the doped region having a second conductivity type opposite the first conductivity type;
a first electrode connected to the well of the first conductivity type; and
a second electrode connected to the doped region having the second conductivity type, wherein the well and the doped region form a PN diode.

US Pat. No. 11,031,386

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a first conductivity type semiconductor layer;
a second conductivity type region selectively formed in the semiconductor layer;
a second conductivity type peripheral impurity region formed around the second conductivity type region in the semiconductor layer, the peripheral impurity region being spaced apart from the second conductivity type region;
a Schottky electrode that is formed on the semiconductor layer and that forms a Schottky junction portion between a first conductivity type part of the semiconductor layer and the Schottky electrode, the Schottky electrode being in contact with the first conductivity type part of the semiconductor layer, the second conductivity type region and the peripheral impurity region;
a first diode region including a first pn junction portion between the peripheral impurity region and the first conductivity type part of the semiconductor layer; and
a second diode region including a Zener diode made of a second pn junction portion between the second conductivity type region and the first conductivity type part of the semiconductor layer, the second diode region formed at more inner side of the semiconductor device than the first diode region,
wherein the first pn junction portion has a higher withstand voltage than a Zener voltage VZ of the Zener diode, and
a first withstand voltage of the first diode region is higher than a second withstand voltage of the second diode region.

US Pat. No. 11,031,385

STANDARD CELL FOR REMOVING ROUTING INTERFERENCE BETWEEN ADJACENT PINS AND DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit comprising:a first standard cell associated with a first layer and a second layer of the integrated circuit, the first standard cell including,
first transistors, the first transistors being first FinFETs (fin field-effect transistors),
a first metal pin, a second metal pin, and a third metal pin successively side by side on the first layer, the first metal pin, the second metal pin and the third metal pin extending in a first direction, the first metal pin and the second metal pin having a first minimum metal center-to-metal center pitch therebetween, the first minimum metal center-to-metal center pitch being less than or equal to 80 nm,
a fourth metal pin and a fifth metal pin at the second layer, the fourth metal pin and the fifth metal pin extending in a second direction, the second direction being perpendicular to the first direction,
a first via between the first metal pin and the fourth metal pin, and
a second via between the third metal pin and the fifth metal pin such that a first via center-to-via center space between the first via and the second via is greater than double the first minimum metal center-to-metal center pitch; and
a second standard cell associated with the first layer and the second layer of the integrated circuit, the second standard cell including,
second transistors, the second transistors being second FinFETs,
a sixth metal pin, a seventh metal pin, and an eighth metal pin successively side by side on the first layer, the sixth metal pin, the seventh metal pin, and the eighth metal pin extending in the first direction, the sixth metal pin and the seventh metal pin having a second minimum metal center-to-metal center pitch therebetween, the second minimum metal center-to-metal center pitch being less than or equal to 80 nm,
a ninth metal pin and a tenth metal pin on the second layer, the ninth metal pin and the tenth metal pin extending in the second direction,
a third via between the sixth metal pin and the ninth metal pin, and
a fourth via between the eighth metal pin and the tenth metal pin such that a second via center-to-via center space between the third via and the fourth via is greater than double the second minimum metal center-to-metal center pitch and is greater than the first via center-to-via center space such that the integrated circuit includes vias with different via center-to-via center spaces to reduce routing congestion while the first minimum metal center-to-metal center pitch associated with the first standard cell is equal to the second minimum metal center-to-metal center pitch associated with the second standard cell.

US Pat. No. 11,031,384

INTEGRATED CIRCUITS AND METHODS OF MANUFACTURING AND DESIGNING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. An integrated circuit comprising:a semiconductor substrate;
a plurality of gate lines formed in a gate layer above the semiconductor substrate, the plurality of gate lines arranged in a first direction and extending in a second direction perpendicular to the second direction; and
a plurality of metal lines formed in a conduction layer above the gate layer, the plurality of metal lines arranged in the first direction and extending in the second direction, wherein the plurality of metal lines comprise 6N metal lines, the plurality of gate lines comprise 4N gate lines, the 6N metal lines and the 4N gate lines form a unit wiring structure, N is a positive integer, and a plurality of unit wiring structures are arranged in the first direction,
wherein two metal pitches between every three metal lines sequentially adjacent in the first direction among the plurality of metal lines are different from each other.

US Pat. No. 11,031,383

SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:at least one memory cell;
at least one strap cell abutting the at least one memory cell, the at least one strap cell comprising:
an active region;
a first gate arranged across the active region;
a second gate arranged across the active region and disposed at an end of the active region; and
at least one conductive segment disposed over the first gate and the second gate; and
at least one logic cell, wherein the at least one strap cell is disposed between the at least one memory cell and the at least one logic cell, and the at least one logic cell comprises a third gate;
wherein the at least one conductive segment of the at least one strap cell is spaced apart from the third gate of the at least one logic cell, and a length of the at least one conductive segment of the at least one strap cell is smaller than five times of a gate pitch between the first gate and the second gate of the at least one strap cell.

US Pat. No. 11,031,382

PASSIVE ELEMENT, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. An electronic device, comprising:a first insulation layer having a first surface and a second surface opposite to the first surface; and
a first conductive pillar comprising a first portion and a second portion,
wherein the first portion of the first conductive pillar is surrounded by the first insulation layer, the second portion of the first conductive pillar is disposed on the first surface of the first insulation layer, a height of the second portion of the first conductive pillar is equal to or greater than 10% of a height of the first portion of the first conductive pillar, wherein the second portion of the first conductive pillar has a curved surface, and the curved surface surrounds the second portion of the first conductive pillar,
wherein a width of the first portion of the first conductive pillar and a width of the second portion of the first conductive pillar has a first difference, and a ratio of the height of the second portion of the first conductive pillar to the first difference ranges from 1:1.1 to 1:1.3.

US Pat. No. 11,031,381

OPTICAL TRANSCEIVER AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. An optical transceiver, comprising:a photonic integrated circuit component comprising at least one optical input/output portion, wherein the photonic integrated circuit component has at least one groove located in proximity of the at least one optical input/output portion;
an electric integrated circuit component stacked over and electrically connected to the photonic integrated circuit component; and
an insulating encapsulant disposed on the photonic integrated circuit component and laterally encapsulating the electric integrated circuit component, wherein the insulating encapsulant and the at least one groove of the photonic integrated circuit component are adapted for insertion of a photonic device.

US Pat. No. 11,031,380

MANUFACTURING METHOD OF MICRO LED DISPLAY MODULE

SYNDIANT INC., Dallas, T...

1. A manufacturing method of micro light emitting diode (LED) display module, the method comprising the following steps:initially, preparing a LED wafer and a driver circuit wafer, wherein a portion of the LED wafer is defined as a LED block, the LED block has a first semiconductor layer, a light emitting layer and a second semiconductor layer, the light emitting layer is disposed between the first semiconductor layer and the second semiconductor layer, the first semiconductor layer connects with a substrate, the first semiconductor layer is a N-type semiconductor layer and the second semiconductor layer is a P-type semiconductor layer, and a chip size portion of the driver circuit wafer is defined as a driver chip block;
next, etching the LED block to form a plurality of trenches arranged crisscrossingly, wherein the trenches define a plurality of micro LED pixels arranged in an array, each of the trenches at least penetrates through the second semiconductor layer and the light emitting layer, and the first semiconductor layer is not penetrated through by each of the trenches;
next, bonding the LED block and the driver chip block to each other, wherein the second semiconductor layer is electrically connected to a plurality of pixel electrodes of the driver chip block, and each of the micro LED pixels corresponds to one of the pixel electrodes; and
next, removing the substrate;
next, disposing a light transmissive conductive layer on the first semiconductor layer, wherein the light transmissive conductive layer has a common electrode corresponding to the micro LED pixels; and
next, disposing a color layer on the light transmissive conductive layer, wherein the color layer is a red, green and blue color layer.

US Pat. No. 11,031,379

STRAY INDUCTANCE REDUCTION IN PACKAGED SEMICONDUCTOR DEVICES

SEMICONDUCTOR COMPONENTS ...

18. A semiconductor device package comprising:a substrate;
a positive power supply terminal electrically coupled with the substrate, the positive power supply terminal being arranged in a first plane;
a first negative power supply terminal that is laterally disposed from the positive power supply terminal, the first negative power supply terminal being arranged in the first plane;
a second negative power supply terminal that is laterally disposed from the positive power supply terminal, the second negative power supply terminal being arranged in the first plane, the positive power supply terminal being disposed between the first negative power supply terminal and the second negative power supply terminal;
a first semiconductor die disposed on the substrate, the first semiconductor die including a low-side transistor of a power transistor pair;
a second semiconductor die disposed on the substrate, the second semiconductor die including a high-side transistor of the power transistor pair;
a first conductive clip electrically coupling the first negative power supply terminal and the second negative power supply terminal with the low-side transistor;
a second conductive clip electrically coupling the high-side transistor with the substrate, the second conductive clip being arranged parallel to the first conductive clip;
a third conductive clip electrically coupling the first negative power supply terminal with the second negative power supply terminal via a conductive bridge, a portion of the conductive bridge being arranged in a second plane that is parallel to, and non-coplanar with the first plane, the third conductive clip, the first negative power supply terminal and the second negative power supply terminal being electrically coupled with the first conductive clip; and
an output terminal electrically coupled with the substrate.

US Pat. No. 11,031,378

SEMICONDUCTOR DEVICE INCLUDING HIGH SPEED HETEROGENEOUS INTEGRATED CONTROLLER AND CACHE

Western Digital Technolog...

1. A semiconductor device configured to operate with a host device, comprising:a first semiconductor die comprising:
an ASIC logic circuit configured to interface with the host device,
a memory array logic circuit configured to interface with a memory array, and
a cache structure configured to provide storage within the first semiconductor die; and
a group of one or more second semiconductor dies coupled to the first semiconductor die, the group of one or more second semiconductor dies comprising the memory array configured to interface with the memory array logic circuit of the first semiconductor die.

US Pat. No. 11,031,377

INTEGRATION OF THREE-DIMENSIONAL NAND MEMORY DEVICES WITH MULTIPLE FUNCTIONAL CHIPS

Yangtze Memory Technologi...

1. A method for forming a three-dimensional semiconductor device, comprising:forming a microprocessor chip, comprising:
forming at least one microprocessor device on a first substrate; and
forming a first interconnect layer on the at least one microprocessor device, the first interconnect layer comprising at least one first interconnect structure;
forming a memory chip, comprising:
forming at least one memory cell on a second substrate; and
forming a second interconnect layer on the at least one memory cell, the second interconnect layer comprising at least one second interconnect structure; and
bonding the first interconnect layer of the microprocessor chip with the second interconnect layer of the memory chip, such that the at least one microprocessor device of the microprocessor chip is electrically connected with the at least one memory cell of the memory chip through the at least one first interconnect structure or the at least one second interconnect structure.

US Pat. No. 11,031,376

CHIP PACKAGE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A chip package, comprising:a first semiconductor die comprising a top surface having a first region and a second region; conductive pillars disposed over the second region of the first semiconductor die;
a dielectric structure comprising a first support portion and a second support portion, the first support portion being disposed on the first region of the first semiconductor die, and the second support portion being physically separated from the first semiconductor die;
a second semiconductor die stacked over the first support portion and the second support portion, and the second semiconductor die being electrically connected to the first semiconductor die through the conductive pillars; and
an insulating encapsulant encapsulating the first semiconductor die, the second semiconductor die, the dielectric structure and the conductive pillars.

US Pat. No. 11,031,375

SEMICONDUCTOR DEVICES HAVING A CONDUCTIVE PILLAR AND METHODS OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing a semiconductor package, the method comprising:forming a first redistribution structure on a first carrier;
forming a plurality of conductive pillars on the first redistribution structure by using a mask pattern;
mounting a first semiconductor chip on the first redistribution structure to be adjacent to the plurality of conductive pillars;
forming an encapsulant configured to cover an upper surface of the first redistribution structure, the plurality of conductive pillars, and the first semiconductor chip;
planarizing the encapsulant such that an upper surface of the first semiconductor chip is exposed;
exposing the plurality of conductive pillars by forming an opening in the planarized encapsulant; and
forming a second redistribution structure on the first semiconductor chip and the planarized encapsulant, the second redistribution structure being connected to the plurality of conductive pillars,
wherein upper surfaces of the plurality of conductive pillars are located at a lower level than the upper surface of the first semiconductor chip,
the second redistribution structure comprises a first interconnection pattern, a second interconnection pattern on the first interconnection pattern, a connection via configured to connect the first interconnection pattern to the plurality of conductive pillars, and a via connecting the first interconnection pattern and the second interconnection pattern,
an upper surface of the connection via has a width greater than a width of a lower surface of the connection via,
a height of the connection via is greater than a height of the via, and
a side surface of a conductive pillar and at least a portion of the connection via are surrounded by the encapsulant.

US Pat. No. 11,031,374

METHODS OF COMPENSATING FOR MISALIGNMENT OF BONDED SEMICONDUCTOR WAFERS

Micron Technology, Inc., ...

1. A method comprising:bonding a first semiconductor wafer and a second semiconductor wafer with each other, the first semiconductor wafer comprising a memory cell array and the second semiconductor wafer comprising a circuit to access the memory cell array; and
forming, after the bonding, a plurality of contacts on the first semiconductor wafer; the plurality of contacts being for electrical connections between the first and second semiconductor wafers; the plurality of contacts being linked to a plurality of reference positions, respectively; wherein each of the contacts of the plurality of contacts is shifted from an associated one of the plurality of the reference positions to absorb a bonding alignment error between the first and second semiconductor wafers.

US Pat. No. 11,031,373

SPACER FOR DIE-TO-DIE COMMUNICATION IN AN INTEGRATED CIRCUIT

INTERNATIONAL BUSINESS MA...

1. A multi-die integrated circuit device, comprising:a substrate;
two or more dice comprising components that implement functionality of the multi-die integrated circuit, wherein the components include logic gates; and
a spacer disposed between the substrate and each of the two or more dice, wherein each of the two or more dice makes direct electrical contact with the substrate through holes in the spacer, each of the two or more dice does not make direct electrical contact with the spacer, and the spacer is in direct contact with the substrate, wherein the spacer includes a second set of holes and a polymeric substance is dispensed into the second set of holes.

US Pat. No. 11,031,372

SEMICONDUCTOR DEVICE INCLUDING DUMMY PULL-DOWN WIRE BONDS

Western Digital Technolog...

1. A semiconductor device, comprising:a substrate including a set of contact pads;
one or more semiconductor die mounted on the substrate and electrically coupled to the substrate, at least one semiconductor die of the one or more semiconductor die comprising a set of bond pads; and
a set of wire bonds connected between the set of bond pads on the at least one semiconductor die and the set of contact pads on the substrate, the set of wire bonds configured to exert a force on the one or more semiconductor die to hold the one or more semiconductor die down on the substrate.

US Pat. No. 11,031,371

SEMICONDUCTOR PACKAGE AND METHOD OF FABRICATING SEMICONDUCTOR PACKAGE

SanDisk Information Techn...

1. A semiconductor package, comprising:a first component comprising a plurality of first dies stacked on top of each other, each of the first dies comprising at least one side surface and an electrical contact exposed on the side surface and terminating at the side surface, and the plurality of first dies aligned so that the corresponding side surfaces of all first dies are substantially coplanar with respect to each other to form a common sidewall;
a first conductive pattern formed over the sidewall, the first conductive pattern comprising:
a first portion comprised of two or more sections in contact with the sidewall and electrically coupled to the electrical contacts of the plurality of first dies, and
a second portion comprised of one or more second sections between each of the two or more sections of the first portion, the one or more second sections spaced away from the sidewall;
at least one second component; and
a second conductive pattern formed on a surface of the second component, the second conductive pattern affixed and electrically connected to the first conductive pattern.

US Pat. No. 11,031,370

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Amkor Technology Singapor...

1. A method of manufacturing a semiconductor device, the method comprising:receiving a structure comprising:
a substrate;
an interposer on the substrate, where the interposer comprises a first interposer side facing away from the substrate and a second interposer side facing toward and coupled to the substrate; and
a plurality of contact structures coupled to the first interposer side;
coupling a carrier to the first interposer side utilizing an adhesive, where the adhesive laterally surrounds the contact structures;
removing the substrate; and
coupling a semiconductor die to the second interposer side.

US Pat. No. 11,031,369

APPARATUS FOR BOND WAVE PROPAGATION CONTROL

Taiwan Semiconductor Manu...

1. A workpiece bonding apparatus for controlling a propagation of a bond wave between a first workpiece and a second workpiece, the workpiece bonding apparatus comprising:a first chuck configured to selectively secure the first workpiece;
a second chuck configured to selectively secure the second workpiece at a predetermined position proximate to the first workpiece; and
a vacuum apparatus positioned between the first chuck and second chuck proximate to respective peripheries of the first workpiece and second workpiece, wherein the vacuum apparatus is configured to selectively induce a vacuum between opposing surfaces of the first workpiece and second workpiece, therein selectively attracting the first workpiece and second workpiece toward one another.

US Pat. No. 11,031,368

BONDING APPARATUS

PANASONIC INTELLECTUAL PR...

1. A bonding apparatus in which a bonding tool holds a chip and the bonding tool is lowered in a direction of a stage on which a board is placed so as to oppose the chip to bond the chip to a bonding position of the board, the bonding apparatus comprising:a movable light guide configured to
receive an image of the chip incident from a first incident port that opposes the chip and emits the image of the chip upward from a first emission port separated from the first incident port in a horizontal direction, and
receive an image of the bonding position of the board incident from a second incident port that opposes the bonding position and emits the image of the bonding position upward from a second emission port separated from the second incident port in the horizontal direction, when being positioned between the chip positioned above the bonding position and the board;
a first capture which images the image of the chip emitted from the first emission port;
a second capture which images the image of the bonding position emitted from the second emission port;
a detector which detects a relative positional deviation of the chip and the bonding position based on the image of the chip imaged by the first capture and the image of the bonding position imaged by the second capture;
an aligner which relatively moves the bonding tool and the stage based on the relative positional deviation detected by the detector; and
a mover which advances and retreats the movable light guide to a space between the chip positioned above the bonding position and the board,
wherein the first emission port of the movable light guide reflects the image of the chip upward, and the second emission port of the movable light guide reflects the image of the bonding position of the board upward.

US Pat. No. 11,031,367

BOND HEAD ASSEMBLIES INCLUDING REFLECTIVE OPTICAL ELEMENTS, RELATED BONDING MACHINES, AND RELATED METHODS

Kulicke and Soffa Industr...

1. A bond head assembly for a bonding machine, the bond head assembly comprising:a body portion;
a bonding tool for bonding a semiconductor element to a substrate, the bonding tool being secured to the body portion; and
at least one reflective optical element carried by and secured to the bond head assembly, the at least one reflective optical element being configured to be positioned along an optical path of the bonding machine such that a vision system of the bonding machine is configured to view a portion of the semiconductor element while being carried by the bonding tool prior to bonding of the semiconductor element to the substrate.

US Pat. No. 11,031,366

SHIELDED ELECTRONIC COMPONENT PACKAGE

Amkor Technology Singapor...

1. An electronic component package comprising:an electronic component comprising a component upper side, a component lower side, and a component first lateral side;
a substrate comprising:
a substrate upper side coupled to the component lower side;
a substrate lower side;
a substrate first lateral side; and
a shield trace at the substrate upper side;
a wire coupled to the shield trace;
an encapsulating material in contact with and encapsulating at least a portion of the substrate upper side, at least a portion of the component first lateral side, and at least a portion of the wire, the encapsulating material comprising an encapsulant upper side, an encapsulant lower side coupled to the substrate upper side, and an encapsulant first lateral side; and
a conformal shield layer on the encapsulating material and coupled to the wire at the encapsulant upper side, wherein:
the conformal shield layer vertically covers at least a portion of the electronic component;
the conformal shield layer laterally covers at least a portion of the electronic component; and
the conformal shield layer laterally covers at least a portion of the substrate.

US Pat. No. 11,031,365

SEMICONDUCTOR DEVICE HAVING A SOLDER BLOCKING METAL LAYER

SUMITOMO ELECTRIC DEVICE ...

1. A semiconductor device comprising:a mounting substrate;
a semiconductor chip mounted on the mounting substrate, the semiconductor chip including a rear surface facing the mounting substrate, a front surface opposite to the rear surface, and at least one heat generating element formed on the front surface;
a rear-surface metal layer formed on the rear surface of the semiconductor chip, the rear-surface metal layer including gold (Au);
an AuSn solder layer located between the mounting substrate and the rear surface of the semiconductor chip to fix the semiconductor chip to the mounting substrate through the rear-surface metal layer; and
a solder blocking metal layer located between the rear surface of the semiconductor chip and the mounting substrate, and in a non-heating region that excludes a heating region in which the at least one heat generating element is formed, the solder blocking metal layer including at least one of nickel-chrome (NiCr), nickel (Ni) and titanium (Ti) and extending to a first edge of the semiconductor chip, wherein a void is provided between the solder blocking metal layer and the AuSn solder layer.

US Pat. No. 11,031,364

NANOPARTICLE BACKSIDE DIE ADHESION LAYER

TEXAS INSTRUMENTS INCORPO...

1. A microelectronic device, comprising:a microelectronic die having a die attach surface;
a nanoparticle layer coupled to and covering a plurality of areas of the die attach surface, the nanoparticle layer including nanoparticles wherein adjacent nanoparticles are adhered to each other;
a package substrate having a substrate interface surface coupled to the nanoparticle layer; and
a layer of a die attach material connecting the nanoparticle layer to the package substrate at the substrate interface surface, wherein the die attach material extends into the nanoparticle layer and contacts at least a portion of the nanoparticles in an interlocking configuration, and configured to increase a mechanical adhesion between the die attach surface and the package substrate;
a gap in and extending through the nanoparticle layer and the die attach material layer, the gap extending from the die attach surface to the substrate interface surface.

US Pat. No. 11,031,363

INTERCONNECT STRUCTURES, PACKAGED SEMICONDUCTOR DEVICES, AND METHODS OF PACKAGING SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

8. A method of forming a semiconductor device, the method comprising:encapsulating a plurality of dies and a plurality of through-vias by depositing a molding material over the plurality of dies and the plurality of through-vias;
forming an interconnect on the plurality of dies, the plurality of through-vias, and the molding material, comprising:
depositing a conductive layer having a plurality of first contact pads and a plurality of second contact pads;
depositing a first dielectric layer on the conductive layer;
forming a plurality of ground-up underbump metallization (UBM) pads directly on the first dielectric layer in respective first regions of the interconnect, a plurality of respective lower surfaces of the plurality of ground-up UBM pads physically contacting an upper surface of the first dielectric layer, the respective first regions of the interconnect having a respective first amount of reliability risk over a threshold amount of reliability risk, a plurality of respective first portions of the plurality of ground-up UBM pads extending through the first dielectric layer to contact respective first contact pads of the plurality of first contact pads in the conductive layer, each of the respective first portions of the plurality of ground-up UBM pads having a respective recessed top surface; and
forming a plurality of post-passivation interconnects (PPIs) directly on the first dielectric layer, each of the plurality of PPIs being a single continuous conductive material in respective second regions of the interconnect, the respective second regions of the interconnect having a second amount of reliability risk under the threshold amount of reliability risk, each of the plurality of PPIs comprising a respective PPI pad and a respective conductive segment, the respective conductive segments extending through the first dielectric layer to contact respective second contact pads of the plurality of second contact pads in the conductive layer, each respective PPI pad having a flat top surface, a respective lower surface of each respective PPI pad physically contacting the upper surface of the first dielectric layer;
coupling a plurality of first connectors to respective ground-up UBM pads, each of the plurality of first connectors contacting respective sidewalls and respective recessed top surfaces of the respective ground-up UBM pads;
coupling a plurality of second connectors to respective PPI pads, each of the plurality of second connectors physically contacting respective flat top surface of respective PPI pads; and
depositing a second dielectric layer on the interconnect, the second dielectric layer covering respective portions of respective spherical surfaces of first connectors of the plurality of first connectors, the second dielectric layer covering at least respective first portions of respective lower halves of respective spherical surfaces of second connectors of the plurality of second connectors, respective second portions of the respective lower halves of the respective spherical surfaces of the second connectors being directly adjacent to an ambient, the second dielectric layer covering respective sidewalls of respective PPI pads of the plurality of PPIs.

US Pat. No. 11,031,362

3D-INTERCONNECT

Invensas Corporation, Sa...

1. A method of making a microelectronic package, comprising:bonding a conductive structure to a carrier so that the conductive structure overlies a rear surface of a microelectronic element disposed on the carrier and an exposed top surface of the carrier, the conductive structure being a monolithic structure having a base and a plurality of interconnections extending continuously away from the base toward the carrier, the plurality of interconnections having free ends overlying the carrier, wherein the microelectronic element is positioned between at least two adjacent interconnections of the plurality of interconnections;
encapsulating the plurality of interconnections and the microelectronic element with an encapsulant;
removing the carrier to expose the free ends of the interconnections and bond pads of the microelectronic element;
conductively connecting the free ends of the interconnections and bond pads of the microelectronic element with terminals of the microelectronic package; and
patterning the conductive structure to form external contacts, at least some of the external contacts overlying the microelectronic element.

US Pat. No. 11,031,361

SEMICONDUCTOR BONDING STRUCTURE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor bonding structure, comprising:a first semiconductor element having a first element top surface and a first element bottom surface opposite to the first element top surface;
a first bonding structure disposed adjacent to the first element top surface of the first semiconductor element, comprising:
a first electrical connector;
a first insulation layer surrounding the first electrical connector; and
a first metal layer surrounding the first insulation layer; and
a second electrical connector disposed in the first semiconductor element, wherein the second electrical connector electrically connects to the first bonding structure.

US Pat. No. 11,031,360

TECHNIQUES FOR AN INDUCTOR AT A SECOND LEVEL INTERFACE

Intel Corporation, Santa...

1. A method comprising:fabricating a first portion of an inductor coil at a first substrate of an integrated circuit package;
fabricating a second portion of the inductor coil in a second substrate, wherein the second substrate is a non-semiconductor substrate, and wherein the second substrate is a printed circuit board; and
electrically and mechanically coupling the integrated circuit package and the first portion of the inductor coil with the second substrate and the second portion of inductor coil.

US Pat. No. 11,031,359

CAPACITOR LOOP STRUCTURE

Intel Corporation, Santa...

1. An apparatus comprising:an integrated circuit package substrate;
a capacitor substrate at least partially disposed on package substrate, wherein the capacitor substrate comprises a loop with an external perimeter that defines an external edge of the capacitor substrate, and an inner perimeter that defines a hole in the capacitor substrate, wherein the hole comprises an opening provided through the capacitor substrate, wherein the capacitor substrate partially overhangs the package substrate, forming a first area that is directly disposed on the package substrate, and a second area that extends from the first area and that overhangs the package substrate;
at least one capacitor disposed on the capacitor substrate in a space formed between the external and inner perimeters, wherein a first portion of the capacitor is disposed on the first area that is directly disposed on the package substrate, and a second portion of the capacitor is disposed on the second area that overhangs the package substrate;
a first electrical interconnect provided through the first area of the capacitor substrate that is directly disposed on the package substrate to electrically couple the first portion of the capacitor with the package substrate; and
a second electrical interconnect provided through the second area of the capacitor substrate that overhangs the package substrate, to electrically couple the second portion of the capacitor with the package substrate or other electric components.

US Pat. No. 11,031,358

OVERHANG MODEL FOR REDUCING PASSIVATION STRESS AND METHOD FOR PRODUCING THE SAME

MARVELL ASIA PTE, LTD., ...

1. A device comprising:a first top metal layer within a logic region of a sensor;
a second top metal layer within an array region of the sensor;
a dielectric layer over the logic region and the array region, height of the dielectric layer over the first and second top metal layers greater than the height of the dielectric layer in-between the first and second top metal layers;
a first passivation layer over the dielectric layer, the first passivation layer being in-between the first and second top metal layers, and a height of the first passivation layer being level with the height of the dielectric layer over the first and second top metal layers;
a pad opening in the logic region of the sensor with dimensions based on a predetermined overhang value, the pad opening exposing the first op metal layer;
a pad opening in the array region of the sensor with dimensions based on the predetermined overhang value; and
a second passivation layer over the dielectric layer, the first passivation layer and the pad opening in the array region of the sensor.

US Pat. No. 11,031,357

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a substrate having a main surface and an end surface extending in a direction transverse to the main surface, the main surface including a peripheral region and a device region surrounded by the peripheral region;
a first insulating film provided on the device region and the peripheral region; and
a first amorphous insulating film provided on the first insulating film,
the first amorphous insulating film being disposed on the peripheral region, the first amorphous insulating film being separated from the device region,
the first amorphous insulating film extending in a form of a stripe along the direction in which the end surface extends,
the first amorphous insulating film being flush with the end surface.

US Pat. No. 11,031,356

SEMICONDUCTOR PACKAGE STRUCTURE FOR IMPROVING DIE WARPAGE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY SINGAPOR...

1. A semiconductor device, comprising:a substrate comprising a substrate top side;
a semiconductor die comprising a die top side, a die bottom side opposite the die top side, and a die lateral side joining the die top side to the die bottom side;
conductive elements on the die bottom side that:
bond the die bottom side to the substrate top side; and
electrically interconnect circuitry of the semiconductor die to the substrate;
an adhesive layer covering the die top side, wherein the adhesive layer comprises an adhesive top side, an adhesive bottom side opposite the adhesive top side, and an adhesive lateral side joining the adhesive top side to the adhesive bottom side;
interconnects on the substrate top side, wherein each interconnect has a horizontal line of symmetry; and
a mold compound comprising a mold top side and a mold bottom side opposite the mold top side;
wherein the mold bottom side directly contacts the substrate top side; and
wherein the mold compound:
directly contacts and covers the adhesive lateral side; and
encompasses the interconnects such that a top side of each interconnect does not extend beyond the mold top side and is exposed through the mold top side.

US Pat. No. 11,031,355

SEMICONDUCTOR DEVICE

MITSUBISHI ELECTRIC CORPO...

1. A semiconductor device comprising:an insulating substrate having a main surface;
a semiconductor element disposed on the main surface of the insulating substrate;
a case member surrounding the semiconductor element and connected to the insulating substrate;
a sealing material that is disposed in an internal region surrounded by the case member and the insulating substrate, and that surrounds the semiconductor element; and
an electrode terminal that is connected to the semiconductor element, and that is formed integrally with the case member,
the case member including a recess that is continuous with a connection portion of the case member connected to the insulating substrate, and that faces the internal region,
the recess including an inner wall portion facing the main surface of the insulating substrate,
the inner wall portion having an end on an outer peripheral side to an end on an inner peripheral side of the case member,
the electrode terminal having a first portion extending in a direction along the main surface of the insulating substrate and a second portion extending in a vertical direction intersecting the first portion,
a distance from the main surface of the insulating substrate to the end on the inner peripheral side of the inner wall portion being greater than a distance from the main surface to an upper surface of the semiconductor element, and
the inner wall portion being disposed between the first portion and the main surface.

US Pat. No. 11,031,354

MIXING ORGANIC MATERIALS INTO HYBRID PACKAGES

Taiwan Semiconductor Manu...

9. A package comprising:a supporting substrate, wherein the supporting substrate is free from conductive features therein;
a silicon oxide layer over and physically contacting the supporting substrate;
a device die over the silicon oxide layer, wherein the device die comprises a silicon substrate, and the silicon substrate is bonded to, and is in physical contact with, the silicon oxide layer, wherein Si—O—Si bonds are formed between the silicon substrate and the silicon oxide layer;
a first encapsulant encapsulating the device die therein; and
an interposer over and bonded with the device die.

US Pat. No. 11,031,353

WARPAGE CONTROL IN MICROELECTRONIC PACKAGES, AND RELATED ASSEMBLIES AND METHODS

Micron Technology, Inc., ...

1. A microelectronic device package, comprising:a substrate;
one or more microelectronic devices positioned over the substrate;
an encapsulant material surrounding and extending over the one or more microelectronic devices; and
at least one warpage control layer positioned over and secured to a surface of the encapsulant material, the at least one warpage control layer having a first region having a first thickness and a second region having a second thickness greater than the first thickness of the first region.

US Pat. No. 11,031,352

ROUTING DESIGN OF DUMMY METAL CAP AND REDISTRIBUTION LINE

Taiwan Semiconductor Manu...

1. A package comprising:a first dielectric layer;
a device die over the first dielectric layer;
an encapsulant encapsulating the device die;
a second dielectric layer over the encapsulant;
an active metal cap in the second dielectric layer;
a dummy metal cap in the second dielectric layer, wherein in a plane view of the package, the dummy metal cap is separated into a first portion and a second portion, and a contour of the dummy metal cap has a same shape as the active metal cap; and
a first redistribution line passing between, and physically separated from, the first portion and the second portion of the dummy metal cap.

US Pat. No. 11,031,351

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:forming an insulating film over a semiconductor structure, wherein the semiconductor structure comprises:
a semiconductor chip; and
a molding compound disposed around the semiconductor chip;
forming a sealing ring over a sidewall of the insulating film, wherein a sidewall of the sealing ring facing away from the sidewall of the insulating film and a top surface of the molding compound are exposed, wherein forming the seal ring is performed such that the exposed sidewall of the seal ring has a stair-shaped surface; and
forming a protective layer in contact with the exposed sidewall of the sealing ring, wherein forming the protective layer is performed such that the protective layer has an inclined and substantially smooth surface that covers the stair-shaped surface of the seal ring.

US Pat. No. 11,031,350

LEADFRAME WITH PAD ANCHORING MEMBERS AND METHOD OF FORMING THE SAME

STMICROELECTRONICS, INC.,...

1. A device, comprising:a leadframe including:
a plurality of leads;
a die pad having a first surface opposite a second surface, the second surface having a first portion substantially parallel with the first surface and a second portion, the second portion being at a first angle to the first portion;
a first flange extending from a first outermost edge of the die pad and away from the first surface of the die pad, the first flange having a first portion coupled to the first outermost edge of the die pad and a second portion having a third surface, a plane of the third surface being at a first angle with respect to the first surface, the third surface being substantially parallel to the second portion of the second surface; and
a cavity between an edge of the first portion of the first flange and a plane of the second surface of the die pad.

US Pat. No. 11,031,349

METHOD OF FORMING A SEMICONDUCTOR DEVICE AND CURRENT SENSING CIRCUIT THEREFOR

SEMICONDUCTOR COMPONENTS ...

10. A semiconductor device comprising:a semiconductor substrate having a first doped region of a first conductivity type;
a second doped region of a second conductivity type on the first doped region, the second doped region having a surface opposite to the semiconductor substrate;
a first isolation structure surrounding a first perimeter of a first portion of the first doped region and the second doped region and forming a first active region within the first portion including forming the first isolation structure extending from the surface through the second doped region, through the first doped region, and into the semiconductor substrate;
a first P-N junction within the first active region, the first P-N junction formed at an interface between the first doped region and the second doped region, the first P-N junction having a first depletion region;
active circuits on the second doped region within the first active region, the active circuits having a second P-N junction, the second P-N junction having a second depletion region overlying at least a portion of the first P-N junction;
a sensing circuit formed on the second doped region, the sensing circuit configured to apply a voltage to the first doped region that expands the first depletion region toward the second depletion region wherein the first depletion region substantially does not intersect the second depletion region; and
the sensing circuit configured to detect electrons formed within the first doped region and to responsively assert a detection signal representing detection of the electrons wherein the sensing circuit detects the electrons while applying the voltage to the first doped region.

US Pat. No. 11,031,348

SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A semiconductor structure, comprising:a substrate having a front surface and a back surface opposite to the front surface;
at least one semiconductor device disposed in a device region of the substrate;
a first through-substrate via (TSV) disposed in the substrate, wherein two ends of the first TSV are exposed on the front surface and the back surface of the substrate;
an insulating layer surrounding the first TSV, wherein the insulating layer comprises an electrically insulating material;
a shielding layer surrounding the insulating layer, wherein the shielding layer comprises an electrically conductive material directly coupled to a ground layer in the substrate to be connected to ground, and the shielding layer is electrically isolated from the first TSV by the insulating layer; and
a second TSV disposed in the substrate and in parallel to the first TSV, wherein two ends of the second TSV are exposed on the front surface and the back surface of the substrate.

US Pat. No. 11,031,347

SEMICONDUCTOR PACKAGES

Samsung Electronics Co., ...

1. A semiconductor package comprising:a redistribution structure;
a first semiconductor chip on the redistribution structure;
a copper clad laminate on the first semiconductor chip;
a first mold layer between the copper clad laminate and the redistribution structure;
a shielding wall surrounding the first semiconductor chip;
a plurality of first conductive pillars around the shielding wall;
a plurality of inter-package connections on the plurality of first conductive pillars;
a substrate on the plurality of inter-package connections;
at least one second semiconductor chip on the substrate; and
a second mold layer covering the at least one second semiconductor chip.

US Pat. No. 11,031,346

ADVANCED WAFER SECURITY METHOD INCLUDING PATTERN AND WAFER VERIFICATIONS

International Business Ma...

1. A method comprising:first verifying that a pattern printed on a processed wafer matches a pattern of a trusted reference;
measuring, after the first verifying, a peak and valley profile present at a specific location on a backside surface of the processed wafer containing the patterned pattern; and
second verify that the measured peak and valley profile of the processed wafer matches an original peak and valley profile measured at the same location on the backside surface of a trusted wafer, wherein when the measured peak and valley profiles of the processed wafer and the trusted wafer match, the processed wafer is the trusted wafer.

US Pat. No. 11,031,345

INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME

Medtronic, Inc., Minneap...

1. An integrated circuit package, comprising:a substrate comprising a core layer disposed between a first dielectric layer and a second dielectric layer;
a die disposed in a cavity of the core layer;
an encapsulant disposed in the cavity between the die and a sidewall of the cavity;
a first patterned conductive layer disposed within the first dielectric layer;
a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, wherein the device is electrically connected to the die;
a second patterned conductive layer disposed within the second dielectric layer; and
a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer, wherein the conductive pad is electrically connected to the die; and
a field plate disposed within the first dielectric layer, wherein the field plate is spaced apart from the die.

US Pat. No. 11,031,344

PACKAGE HAVING REDISTRIBUTION LAYER STRUCTURE WITH PROTECTIVE LAYER AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

10. A method of fabricating a package, comprising:forming a redistribution layer (RDL) structure on a die, comprising:
forming a first dielectric material on the die;
forming a second dielectric material over the first dielectric material;
patterning the second dielectric material to form a first opening in the second dielectric material, wherein the second dielectric material has a plurality of comb portions in the first opening to separate the first opening into a plurality of sub-openings;
patterning the first and second dielectric materials to form a second opening in the first and second dielectric materials;
forming a protective layer on the die to cover the first and second openings;
removing a portion of the protective layer on a bottom surface of the second opening to expose the contact of the die;
filling the first opening and the second opening with a conductive material; and
performing a planarization process until exposing the plurality of comb portions, so as to form a plurality of first conductive patterns in the plurality of sub-openings and form a second conductive pattern in the second opening, wherein the protective layer has a first portion and a second portion, the first portion continuously covers bottom surfaces and sidewalls of the plurality of first conductive patterns and is in contact with a top surface of the first dielectric material, and the second portion continuously covers a sidewall of the second conductive pattern.

US Pat. No. 11,031,343

FINS FOR ENHANCED DIE COMMUNICATION

International Business Ma...

8. A semiconductor structure comprising:a first chip on a substrate and having at least one first protruding section, the first protruding section comprising first interconnect locations, wherein the first protruding section comprises a first protruding section upper surface opposite to a first protruding section lower surface, and wherein the first protruding section lower surface is on the substrate;
a second chip on the substrate and having at least one second protruding section, the second protruding section comprising second interconnect locations, wherein the second protruding section comprises a second protruding section upper surface opposite to a second protruding section lower surface, and wherein the second protruding section lower surface is on the substrate; and
a bridge connected to the first chip and connected to the second chip through a connection selected from the group consisting of solder balls and copper to copper connections, wherein the bridge is aligned to the orientation of the first chip and the second chip,
wherein the first chip and the second chip are arranged such that the first protruding section is interdigitated with the second protruding section, and wherein the bridge substantially covers the interdigitated first protruding section upper surface of the at least one first protruding section and the second protruding section upper surface of the at least one second protruding section.

US Pat. No. 11,031,342

SEMICONDUCTOR PACKAGE AND METHOD

Taiwan Semiconductor Manu...

13. A method comprising:encapsulating an integrated circuit die and a through via with a molding compound, the integrated circuit die having a die connector;
forming a first conductive via on the die connector of the integrated circuit die;
forming a second conductive via on the through via;
depositing a first dielectric layer having a first portion, a second portion, and a third portion, the first portion disposed on first sidewalls and a first top surface of the first conductive via, the second portion disposed on second sidewalls and a second top surface of the second conductive via, the third portion disposed between the first conductive via and the second conductive via, the third portion being recessed beneath the first top surface and the second top surface;
removing the first portion and the second portion of the first dielectric layer; and
after the removing, forming a conductive line on the first sidewalls and the first top surface of the first conductive via, the second sidewalls and the second top surface of the second conductive via, and the third portion of the first dielectric layer.

US Pat. No. 11,031,341

SIDE MOUNTED INTERCONNECT BRIDGES

Intel Corporation, Santa...

1. A semiconductor device, comprising:a substrate;
a motherboard attached to the substrate;
a first semiconductor die attached to the substrate, wherein the substrate includes multi-layer break out pads;
a silicon interconnect bridge attached to a side surface of the substrate and wherein the silicon interconnect bridge is electrically coupled to the first semiconductor die via the multi-layer break out pads;
a second semiconductor die electrically coupled to a second end of the silicon interconnect bridge, wherein the second semiconductor die is attached to the motherboard and wherein the motherboard includes a cavity;
wherein the second end of the interconnect bridge extends into the cavity of the motherboard;
wherein the silicon interconnect bridge is attached to the motherboard within the cavity of the motherboard; and
wherein the silicon interconnect bridge is electrically coupled to the second semiconductor die via the motherboard.

US Pat. No. 11,031,340

SEMICONDUCTOR DEVICE INCLUDING A MULTILAYER ETCH STOP LAYER

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a semiconductor substrate including a first region and a second region;
a plurality of field effect transistors on the first region and the second region of the semiconductor substrate;
a plurality of metal contact patterns in a gap-fill insulation layer covering the field effect transistors, the plurality of metal contact patterns being connected to the field effect transistors;
an etch stop layer covering top surfaces of the plurality of metal contact patterns and including a sequentially stacked first insulation layer, second insulation layer, and third insulation layer;
a resistance structure on the etch stop layer on the second region;
an interlayer dielectric layer covering the resistance structure and the etch stop layer;
a first contact plug penetrating the interlayer dielectric layer and the etch stop layer and connected to at least one metal contact pattern of the plurality of metal contact patterns on the first region; and
a second contact plug penetrating the interlayer dielectric layer and connected to the resistance structure on the second region,
wherein:
the first insulation layer, second insulation layer, and third insulation layer include different insulating materials from each other,
a thickness of the third insulation layer is greater than a thickness of the second insulation layer,
the third insulation layer includes a first portion on the first region and a second portion on the second region,
the first portion has a first thickness and the second portion has a second thickness greater than the first thickness, and
the first thickness is greater than the thickness of the second insulation layer.

US Pat. No. 11,031,339

METAL INTERCONNECTS

INTERNATIONAL BUSINESS MA...

1. A process for forming a metal interconnect layer, the process comprising:lithographically patterning and etching an interlayer dielectric to form one or more openings;
conformally depositing a liner layer into the one or more openings;
following deposition of the liner layer, depositing a metal into the one or more openings and on the liner layer;
planarizing a surface to remove an excess of the metal such that the uppermost surfaces of the metal and the interlayer dielectric are coplanar to each other;
removing a portion of the metal to form a recess, wherein the uppermost surface of the metal is below the uppermost surface of the interlayer dielectric;
removing a portion of the liner layer within the recess subsequent to removing the portion of the metal to form the recess;
depositing a capping layer thereon to fill the recess, wherein a portion of sidewalls of the capping layer directly contacts the interlayer dielectric; and
planarizing a surface to remove excess capping layer such that the uppermost surfaces of the capping layer and the interlayer dielectric are coplanar to each other and the uppermost surface of the metal is below the uppermost surfaces of the capping layer and the interlayer dielectric,
wherein the capping layer comprises silicon carbide, silicon (nitrogen, hydrogen, carbon), silicon oxycarbide, hydrogenated silicon carbide, silicon dioxide, or an organosilicate glass.

US Pat. No. 11,031,338

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first interlayer insulating film on a substrate;
a via which penetrates the first interlayer insulating film;
a first etching stop film which extends along an upper surface of the first interlayer insulating film;
a second interlayer insulating film on the first etching stop film, the second interlayer insulating film including a plurality of air gaps arranged periodically;
a first wiring pattern in the second interlayer insulating film, the first wiring pattern penetrating the first etching stop film and is connected to the via; and
a capping film which covers an upper surface of the second interlayer insulating film and an upper surface of the first wiring pattern, each of the plurality of air gaps in the second interlayer insulating film extending from the first etching stop film to the capping film.

US Pat. No. 11,031,337

FORMING DUAL METALLIZATION INTERCONNECT STRUCTURES IN SINGLE METALLIZATION LEVEL

International Business Ma...

1. A method, comprising:forming an insulating layer on a substrate;
patterning the insulating layer to form a plurality of trench openings in the insulating layer, wherein the plurality of trench openings comprises a first trench opening having a first width, and a second trench opening having a second width, which is greater than the first width;
depositing a first layer of liner material to form a first liner layer on sidewall and bottom surfaces of the first and second trench openings;
performing a first metal deposition process for depositing a layer of a first metallic material to fill the first trench opening with the first metallic material, wherein the first metallic material within the first trench opening comprises a first metallic line;
terminating the first metal deposition process at a point in time after the first trench opening is completely filled with the first metallic material and before the second trench opening is completely filled with the first metallic material such that the second trench is partially filled with the first metallic material at the point in time when the first metal deposition process is terminated;
forming a patterned etch protection layer which is disposed over an entirety of an upper surface of the first metallic material within the first trench opening and an entirety of an upper surface of the insulating layer, wherein the patterned etch protection layer comprises a patterned opening which exposes the first metallic material within the second trench opening without exposing any portion of the upper surface of the insulating layer, wherein forming the patterned etch protection layer, comprises:
depositing a conformal layer of etch protection material over the layer of the first metallic material; and
patterning the conformal layer of etch protection material to remove a portion of the conformal layer of etch protection material which covers the second trench opening and expose the first metallic material within the second trench opening without exposing any portion of the first metallic material and the upper surface of the insulating layer outside the second trench opening;
performing an etch process to remove the exposed first metallic material from the second trench opening, while the patterned etch protection layer protects the first metallic material within the first trench opening and the upper surface of the insulating layer from being etched during the etch process;
performing a second metal deposition process for depositing a layer of a second metallic material to fill the second trench opening with the second metallic material, wherein the second metallic material within the second trench opening comprises a second metallic line, wherein the second metallic material is different from the first metallic material; and
performing a planarization process to remove the patterned etch protection layer and overburden portions of the layers of the first and second metallic material disposed over the upper surface of the insulating layer.

US Pat. No. 11,031,336

SEMICONDUCTOR MEMORY DEVICE HAVING CONTACT ELEMENT OF RECTANGULAR SHAPE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a static random-access memory (SRAM) device including a pass gate (PG) transistor, a pull-down (PD) transistor, and a pull-up (PU) transistor;
a first gate line of the PG transistor, a second gate line of the PD transistor and the PU transistor, wherein the first gate line and the second gate line extend in a first direction;
a common source/drain region of the PG transistor, PD transistor, and PU transistor interposing the first gate line and the second gate line;
another source/drain region of the PG transistor;
a first contact extending from the common source/drain region and a second contact extending from the another source/drain region;
a third contact disposed above the second contact, the third contact having a shape with a first width in the first direction and a first length in a second direction, the second direction being perpendicular to the first direction and the first length being greater than the first width; and
a fourth contact disposed above the first contact, the fourth contact having a substantially rectangular shape in a plan view and a via extending from the fourth contact to a third gate line of the SRAM device.

US Pat. No. 11,031,335

SEMICONDUCTOR DEVICES INCLUDING REDISTRIBUTION LAYERS

Micron Technology, Inc., ...

1. A semiconductor device, comprising:a substrate comprising a semiconductor material;
a redistribution layer supported on the substrate, the redistribution layer comprising electrically conductive material located on a side of a dielectric material opposite the substrate; and
vias extending from the electrically conductive material through the dielectric material toward the substrate;
wherein a first region of the electrically conductive material comprises a first width proximate to a first set of the vias and a second, greater width proximate to a second, laterally adjacent set of the vias, as measured in a direction at least substantially perpendicular to a line forming a shortest distance between the first set of the vias and the second set of the vias; and
wherein a second region of the electrically conductive material comprises a third width proximate to the first set of the vias and a fourth, smaller width proximate to the second set of the vias.

US Pat. No. 11,031,334

SEMICONDUCTOR DEVICE INCLUDING A CONDUCTIVE FEATURE OVER AN ACTIVE REGION

Taiwan Semiconductor Manu...

1. A method comprising:forming an active region in a substrate;
forming a first gate structure and a second gate structure on the substrate, wherein the second gate structure is adjacent to the first gate structure;
forming an insulating layer on the first gate structure and the second gate structure;
forming a pair of first spacers on each sidewall of the first gate structure;
forming a pair of second spacers on sidewalls of the second gate structure;
etching a portion of the insulating layer over the first gate structure;
etching a portion of the first gate structure;
forming a first conductive feature over the active region, the first conductive feature physically contacting a first spacer of the pair of first spacers: and
depositing a second conductive feature over the first gate structure, wherein a portion of a top surface of the second conductive feature is coplanar with a top surface of the insulating layer remaining over the first gate structure;
forming a dielectric layer over the second conductive feature, the insulating layer over the first gate structure, the first conductive feature, and a second spacer of the first pair of spacers.

US Pat. No. 11,031,333

THREE-DIMENSIONAL MEMORY DEVICES HAVING A PLURALITY OF NAND STRINGS

Yangtze Memory Technologi...

1. A NAND memory device, comprising:a substrate comprising a doped region embedded in the substrate;
a plurality of NAND strings comprising a first end and a second end opposing the first end;
a plurality of epitaxial plugs in direct contact with the first end of the plurality of NAND strings and in direct contact with the doped region of the substrate;
a first interconnect layer above and in direct contact with the second end of the plurality of NAND strings;
one or more peripheral devices above and in direct contact with the first interconnect layer;
a single crystalline silicon layer disposed above and in direct contact with the one or more peripheral devices, wherein the plurality of NAND strings are located between the substrate and the single crystalline silicon layer; and
a back-end-of-line (BEOL) interconnect layer disposed above and in direct contact with the single crystalline silicon layer.

US Pat. No. 11,031,332

PACKAGE PANEL PROCESSING WITH INTEGRATED CERAMIC ISOLATION

TEXAS INSTRUMENTS INCORPO...

1. A packaged electronic device, comprising:a semiconductor die, including an electronic component, and a contact structure connected to the electronic component;
an organic panel frame;
a lamination structure that partially embeds the semiconductor die in an opening of the organic panel frame; and
a ceramic substrate mounted to a first side of the semiconductor die.

US Pat. No. 11,031,331

PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHES WITH TRENCH METAL PLUGS FOR RF TERMINALS

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) switch comprising:a phase-change material (PCM) and a heating element approximately underlying an active segment of said PCM and extending outward and transverse to said PCM;
RF terminals comprising a trench metal liner separated from a trench metal plug by a dielectric liner;
said trench metal liner of said RF terminals being ohmically connected to passive segments of said PCM;
said trench metal plug of at least one of said RF terminals being ohmically separated from and capacitively coupled to said trench metal liner of said RF terminals by said dielectric liner.

US Pat. No. 11,031,330

ELECTROCONDUCTIVE SUBSTRATE, ELECTRONIC DEVICE AND DISPLAY DEVICE

TDK CORPORATION, Tokyo (...

1. An electroconductive substrate comprising:a base material;
a foundation layer which is disposed on the base material and contains a catalyst and a resin;
a trench formation layer disposed on the foundation layer; and
an electroconductive pattern layer including metal plating, wherein:
the trench formation layer includes a trench having (1) a bottom surface that exposes the foundation layer and (2) a lateral surface which includes a surface of the trench formation layer;
the trench is at least partially filled with the electroconductive pattern layer;
the catalyst is dispersed in the resin, as catalyst particles;
the foundation layer includes a mixed region (1) which extends from the electroconductive pattern layer towards the base material and (2) in which metal particles of a metal of the electroconductive pattern layer are in the foundation layer such that the mixed region includes a mixture of the metal particles, the catalyst and the resin; and
the mixed region has a thickness that is less than a thickness of the foundation layer such that a portion of the foundation layer containing the catalyst and the resin but not the metal particles is between the mixed region and the base material.

US Pat. No. 11,031,329

METHOD OF FABRICATING PACKAGING SUBSTRATE

PHOENIX PIONEER TECHNOLOG...

1. A method for fabricating a packaging substrate, comprising:forming on a carrier a conductor layer having a plurality of openings;
disposing a plurality of conductive bumps on the conductor layer, wherein each of the conductive bumps has a post body formed in a corresponding one of the openings and a conductive pad disposed on the conductor layer, the post body being integrally formed with and less in width than the conductive pad;
disposing a plurality of conductive posts on the conductive pads;
forming on the carrier a first insulating layer encapsulating the conductive bumps and the conductive posts;
removing the carrier; and
removing entirety of the conductor layer to expose the post bodies from a first surface of the first insulating layer.

US Pat. No. 11,031,328

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:an interposer substrate including a core substrate and a connection structure, the core substrate having at least one cavity and having through-vias connecting upper and lower surfaces thereof to each other, and the connection structure including an insulating member disposed on the upper surface of the core substrate and a redistribution layer disposed on the insulating member;
at least one semiconductor chip disposed on an upper surface of the connection structure and including connection pads connected to the redistribution layer;
a passive component accommodated in the at least one cavity;
a first insulating layer disposed between the core substrate and the connection structure and encapsulating the passive component in the at least one cavity;
a first wiring layer disposed on the first insulating layer and connecting the through-vias and the passive component to the redistribution layer;
a second insulating layer disposed on the lower surface of the core substrate; and
a second wiring layer disposed on a lower surface of the second insulating layer and connected to the through-vias.

US Pat. No. 11,031,327

THROUGH VIAS AND METHODS OF FORMATION THEREOF

INFINEON TECHNOLOGIES AG,...

1. A semiconductor chip comprising:a device region disposed in or over a semiconductor substrate;
a conductive layer disposed over the semiconductor substrate;
a first doped region disposed in the device region; and
an opening disposed in the semiconductor substrate, the opening extending completely through the conductive layer, the first doped region, and the semiconductor substrate, wherein the opening comprises a top portion, a central portion, and a bottom portion, wherein the top portion extends through the conductive layer into the first doped region, wherein the bottom portion extends to a major surface of the semiconductor substrate, wherein the central portion is disposed between the top and the bottom portions, wherein the opening comprises sidewalls extending from the top portion to the bottom portion, wherein a conductive fill material partially fills the opening including the bottom portion, wherein the conductive fill material is disposed along the sidewalls of the opening so as to have a void in the central portion, wherein the top portion is partially filled with a dummy fill material, and wherein the opening with the conductive fill material, the void, and the dummy fill material define a first through via that extends completely through the conductive layer, the first doped region, and the semiconductor substrate, wherein the sidewalls of the opening are substantially vertical, and wherein the dummy fill material in the top portion has a continuously linear tapered shape, wherein the continuously linear tapered shape is only formed along the entirety of the top portion of the opening.

US Pat. No. 11,031,326

WIRING STRUCTURE, ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A wiring structure, comprising:a metal layer, wherein the metal layer is a seed layer, and the seed layer includes a titanium layer and a copper layer; and
a conductive structure disposed on the metal layer and including a redistribution layer, a first barrier layer and a wetting layer, wherein the first barrier layer is disposed between the redistribution layer and the wetting layer, a first portion of the wetting layer is exposed from the metal layer to form a ball pad, and a second portion of the wetting layer is disposed on the metal layer.

US Pat. No. 11,031,325

LOW-STRESS PASSIVATION LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:receiving an integrated circuit (IC) workpiece comprising a redistribution layer disposed over and electrically coupled to an interconnect structure;
patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer;
depositing a first dielectric layer over the redistribution layer and the recess using a first deposition technique;
depositing a second dielectric layer over the first dielectric layer using a second deposition technique different from the first deposition technique;
depositing a third dielectric layer over the second dielectric layer using a third deposition technique different from the second deposition technique;
planarizing the second dielectric layer and the third dielectric layer to provide a level surface; and
depositing a fourth dielectric layer over the level surface,
wherein a composition of the fourth dielectric layer is different from a composition of first dielectric layer, the second dielectric layer, or the third dielectric layer.

US Pat. No. 11,031,324

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a substrate;
a plurality of solders disposed on the substrate; including a first solder, a second solder, and a third solder; and located adjacent to each other, at least one of composition and concentration of the plurality of solders being different from each other; and
a semiconductor chip including a joining surface to be joined to the substrate with the plurality of solders, wherein
the joining surface of the semiconductor chip includes a plurality of joining areas in which heat generation of the semiconductor chip or a stress on an object to be joined is different from each other,
the plurality of solders are disposed to correspond to the plurality of joining areas, respectively,
the first solder has a central space in which the first solder is absent in plan view, and surrounds the space in plan view except an opening communicating to the space,
the second solder is disposed in the opening, and
the third solder is disposed in the space to directly contact each of the first solder and the second solder.

US Pat. No. 11,031,323

INTERCONNECTING MEMBER FOR POWER MODULE

ABB Power Grids Switzerla...

1. A housing of a power module, the housing comprising:an encasing for encasing semiconductor elements inside the housing;
a power terminal area on the encasing, on which a power terminal plate is provided;
an auxiliary terminal area on the encasing at a lower level than the power terminal area;
an interconnecting member with a power terminal connector part and an auxiliary terminal connector part interconnected by a spring part, wherein the spring part is aligned besides the power terminal plate;
wherein the spring part is formed, such that it at least partially runs on a higher level than the power terminal connector part;
wherein the interconnecting member is inserted with the power terminal connector part through an opening in the encasing below the power terminal plate, such that the spring part engages the power terminal area besides the power terminal plate and runs to the auxiliary terminal area and the auxiliary terminal connector part is disposed on the auxiliary terminal area.

US Pat. No. 11,031,322

SEMICONDUCTOR DEVICE MOUNTED ON CIRCUIT BOARD OF ELECTRONIC DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device, comprising:a semiconductor element which includes an element main surface and an element rear surface that face opposite sides in a thickness direction and in which a first electrode and a second electrode are formed on the element main surface;
a first conductive member electrically connected to the first electrode;
a second conductive member electrically connected to the second electrode;
a third conductive member on which the semiconductor element is mounted; and
a sealing resin configured to cover part of the first conductive member, part of the second conductive member, and the semiconductor element, the sealing resin including a resin rear surface facing the same direction as the element rear surface,
wherein the first conductive member comprises:
a first pad part overlapping with the semiconductor element as viewed in the thickness direction;
a first exposure part protruding from the sealing resin as viewed in the thickness direction; and
a first connection part which is covered with the sealing resin and is connected to the first pad part and the first exposure part,
wherein the first pad part comprises:
a bonding surface bonded to the first electrode;
a first pad main surface facing a direction opposite to the bonding surface in the thickness direction; and
a non-bonding portion which includes an inner surface extending from the bonding surface toward the first pad main surface and is not bonded to the first electrode,
wherein the first exposure part comprises:
a first bent part which is connected to the first connection part and is bent in the thickness direction; and
a first terminal part connected to the first bent part,
wherein a third electrode is formed on the element rear surface of the semiconductor element,
wherein the third conductive member is electrically connected to the third electrode, and includes a mounting surface facing the same direction as the element rear surface and exposed from the resin rear surface, and
wherein the first terminal part is configured to overlap with the third conductive member as viewed in a first direction orthogonal to the thickness direction.

US Pat. No. 11,031,321

SEMICONDUCTOR DEVICE HAVING A DIE PAD WITH A DAM-LIKE CONFIGURATION

Infineon Technologies AG,...

1. A semiconductor device, comprising:a semiconductor substrate;
a power transistor formed in the semiconductor substrate, the power transistor including an active area in which one or more power transistor cells are formed;
a first metal pad formed above the semiconductor substrate and covering substantially all of the active area of the power transistor, the first metal pad being electrically connected to a source or emitter region in the active area of the power transistor, the first metal pad comprising an interior region laterally surrounded by a peripheral region, the peripheral region being thicker than the interior region; and
a first interconnect plate or a semiconductor die attached to the interior region of the first metal pad by a die attach material at a side of the interior region facing away from the semiconductor substrate.

US Pat. No. 11,031,320

STRUCTURES AND METHODS FOR REDUCING PROCESS CHARGING DAMAGES

Taiwan Semiconductor Manu...

1. A silicon-on-insulator (SOI) structure, comprising:a substrate that includes:
a handle layer,
an insulation layer arranged over the handle layer, and
a buried layer arranged over the insulation layer;
a polysilicon region extending downward through the buried layer and the insulation layer, and terminating in the handle layer; and
an etch stop layer located on the substrate, wherein the etch stop layer is in contact with both the substrate and the polysilicon region;
at least one contact located on the etch stop layer;
at least one dielectric layer on the etch stop layer; and
a metal layer over the at least one dielectric layer, wherein the at least one contact connects the metal layer and the etch stop layer.

US Pat. No. 11,031,319

THERMAL INTERFACE MATERIALS WITH ADHESIVE SELANT FOR ELECTRONIC COMPONENTS

Hewlett-Packard Developme...

1. A method of forming an electronic assembly, comprising:depositing a thermal interface material on a surface of an electronic component, wherein the thermal interface material comprises a liquid metal;
bonding the electronic component and a heat sink by disposing the thermal interface material between the electronic component and the heat sink;
applying an adhesive sealant to seal the thermal interface material between the electronic component and the heat sink, wherein the adhesive sealant is in contact with the thermal interface material and is configured to provide dimensional stability to the thermal interface material, and
prior to depositing the thermal interface material on the surface of at least one of the electronic component or the heat sink, drying the electronic component and the heat sink with heat.

US Pat. No. 11,031,318

ENCAPSULATED PHASE CHANGE POROUS LAYER

TOYOTA JIDOSHA KABUSHIKI ...

1. A heat transfer system, comprising:an encapsulated phase change porous layer, comprising:
a porous layer defined by a structure through which fluids are flowable;
a phase change material formed over the structure of the porous layer, the phase change material comprising tin, indium, or paraffin wax; and
an encapsulation material formed over the phase change material such that the encapsulation material encapsulates the phase change material between the encapsulation material and the structure of the porous layer and retains the phase change material between the encapsulation material and the structure of the porous layer when a fluid is flowed through the porous layer.

US Pat. No. 11,031,317

DIRECT BONDED METAL SUBSTRATES WITH ENCAPSULATED PHASE CHANGE MATERIALS AND ELECTRONIC ASSEMBLIES INCORPORATING THE SAME

1. A direct-bonded metal substrate comprising:a ceramic substrate;
a first conductive layer bonded to a first surface of the ceramic substrate and comprising a first core and a first encapsulating layer, wherein:
the first core comprises a phase change material (PCM) having a first melting temperature and comprising one of tin, indium, paraffin wax, and bismuth;
the first encapsulating layer comprises an encapsulating material having a second melting temperature;
the second melting temperature is greater than the first melting temperature; and
the first core is entirely encapsulated by the first encapsulating layer or the first encapsulating layer and the first surface of the ceramic substrate; and
a second conductive layer bonded to a second surface of the ceramic substrate and comprising a second core and a second encapsulating layer encapsulating the second core, which comprises a PCM.

US Pat. No. 11,031,315

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A semiconductor structure, comprising:a substrate;
a plurality of fins formed on a surface of the substrate, wherein, along an extending direction of the fins, the fins include first regions, second regions, and gate structures across the second regions; and the first regions are located at both sides of the second regions;
an isolation structure formed on the surface of the substrate and between the adjacent fins;
first openings formed at the first regions located at both sides of the gate structures, wherein the bottoms of the first openings expose the surface of the substrate;
thermal conductive layers formed in the first openings; and
doped layers formed on top surfaces of the thermal conductive layers,
wherein a top surface of the thermal conductive layers is coplanar with the top surface of the isolation structure, a material of the fins has a first thermal conductivity, a material of the thermal conductive layers have a second thermal conductivity, a width of the thermal conductive layers is greater than a distance between adjacent fins in a direction perpendicular to an extension direction of the plurality of fins, and the second thermal conductivity is larger than the first thermal conductivity.

US Pat. No. 11,031,314

SPACER STRUCTURE FOR DOUBLE-SIDED-COOLED POWER MODULE AND METHOD OF MANUFACTURING THE SAME

Hyundai Motor Company, S...

1. A spacer structure which connects an insulating substrate and a semiconductor chip of a double-sided-cooled power module, the spacer structure comprising:a conductive material layer composed of a composite material;
an underlying plating layer disposed on the conductive material layer; and
a copper plating layer disposed on the underlying plating layer,
wherein the copper plating layer is in contact with a joining material that joins the spacer to the semiconductor chip and the insulating substrate.

US Pat. No. 11,031,313

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor module including a module main body having first and second main surfaces which are opposite to each other, and a terminal protruding from a side surface of the module main body and bent toward the first main surface side;
a mounting board placed on the first main surface side and connected to the terminal;
a heat radiation fin placed on the second main surface side; and
a screw fitting a fitting portion of the module main body from the first main surface side to the heat radiation fin,
wherein the mounting board is provided with an opening at a portion facing the fitting portion, and
a type of a product is printed on the first main surface and exposed from the opening of the mounting board.

US Pat. No. 11,031,312

MULTI-FRACTAL HEATSINK SYSTEM AND METHOD

Fractal Heatsink Technolo...

1. A heat sink comprising:a heat transmissive body;
a base of the heat transmissive body, configured to receive a heat load;
an external surface of the heat transmissive body, comprising a plurality of elongated sections separated from each other by regions of an external heat transfer fluid in a first pattern, configured to transfer a heat load from the base to the external heat transfer fluid; and
a physical multiscale portion having a physical multiscale pattern distinct from the first pattern of the plurality of elongated sections, the physical multiscale pattern being defined by an iterated function system and comprising a plurality of successive levels of differently scaled self-similar features, the physical multiscale portion being configured to interact with a flow of the external heat transfer fluid around the external surface of the heat transmissive body to disrupt a pattern of the flow.

US Pat. No. 11,031,311

PACKAGED SEMICONDUCTOR DEVICE WITH MULTILAYER STRESS BUFFER

TEXAS INSTRUMENTS INCORPO...

1. A method for forming a packaged semiconductor device, comprising:dispensing a first polymer layer having a first modulus less than 1 GPa and the first polymer layer covering a component proximate a surface of a semiconductor die and covering at least a portion of the surface of the semiconductor die surrounding the component;
dispensing a second polymer layer having a second modulus greater than 1 GPa and the second polymer layer covering at least a portion of the first polymer layer;
mounting the semiconductor die on a substrate; and
covering at least the surface of the semiconductor die and a portion of the substrate with mold compound.

US Pat. No. 11,031,310

CHIP PACKAGE

QUALCOMM Incorporated, S...

1. A chip package comprising:a first polymer layer;
a first semiconductor chip, the first polymer layer on the first semiconductor chip, in which the first semiconductor chip comprises:
a first semiconductor device,
a first semiconductor substrate to support the first semiconductor device, and
a first contact pad coupled to the first semiconductor device;
a first conductive interconnect coupled to the first contact pad, a top surface of the first conductive interconnect substantially coplanar with a top surface of the first polymer layer to enclose the first conductive interconnect in the first polymer layer below the top surface of the first conductive interconnect;
a passivation layer on a surface of the first semiconductor chip and sidewalls of the first contact pad, in which at least one intervening layer is coupled between the passivation layer and the first conductive interconnect;
a second polymer layer over the first polymer layer and extending across an edge of the first semiconductor chip; and
a first redistribution layer comprising a first conductive layer on the top surface of the first conductive interconnect and a second conductive layer in contact with the first conductive layer, the first redistribution layer extending across the edge of the first semiconductor chip, at least a portion of the first conductive layer in contact with the second polymer layer, and a width of the first conductive layer equal to a width of the second conductive layer.

US Pat. No. 11,031,309

COVER LID WITH SELECTIVE AND EDGE METALLIZATION

MATERION CORPORATION, Ma...

1. A cover lid, comprising:a plate comprising a top surface, a bottom surface, and a sidewall joining the top surface and bottom surface together;
wherein the sidewall has a plurality of faces; and
a seal ring applied continuously from on a peripheral area of the top surface and extending along an entirety of the sidewall of the plate; and
a solder preform connected only to the seal ring on the peripheral area, wherein the solder preform does not extend to the sidewall of the plate.

US Pat. No. 11,031,308

CONNECTIVITY DETECTION FOR WAFER-TO-WAFER ALIGNMENT AND BONDING

SanDisk Technologies LLC,...

1. An apparatus, comprising:a first workpiece including first active pads, a first test pad, and a second test pad on a primary surface of the first workpiece, the first test pad electrically connected to the second test pad by a conductive path in the first workpiece;
a second workpiece including second active pads, a third test pad, and a fourth test pad on a primary surface of the second workpiece, the first and second workpieces bonded along an interface between the primary surface of the first workpiece and the primary surface of the second workpiece to bond the first active pads with the second active pads, bond the first test pad with the third test pad, and bond the second test pad with the fourth test pad; and
connectivity detection circuits in the second workpiece, the connectivity detection circuits configured to test electrical connectivity between the third test pad and the fourth test pad, the connectivity detection circuits include an exclusive OR (XOR) circuit coupled to the fourth test pad and the third test pad to compare the voltage at the fourth test pad with the voltage at the third test pad.

US Pat. No. 11,031,307

SEMICONDUCTOR PACKAGE, BUFFER WAFER FOR SEMICONDUCTOR PACKAGE, AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

18. A buffer wafer for a semiconductor package comprising:a first surface comprising a plurality of package regions defined by a plurality of scribe lines, a plurality of stacked structures being stacked in the plurality of package regions, respectively;
a second surface formed opposite to the first surface and on which a plurality of bumps respectively connected to the plurality of stacked structures are formed; and
a first detection line formed on the first surface and surrounding four sides of each of the plurality of stacked structures, the first detection line comprising a single line.

US Pat. No. 11,031,306

QUALITY CONTROL METHOD OF POSITION MEASUREMENT LIGHT SOURCE, SEMICONDUCTOR MANUFACTURING APPARATUS, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus, comprising:a position measurement light source; and
a controller irradiating light of the position measurement light source on a plurality of marks having different heights, measuring a relationship between the height of the mark and an intensity of light reflected by the mark, and identifying a wavelength of the position measurement light source by comparing measurement data acquired by the measuring to reference data of a relationship between the height of the mark and an intensity of reflected light for each of a plurality of wavelengths.

US Pat. No. 11,031,305

LATERALLY ADJACENT AND DIVERSE GROUP III-N TRANSISTORS

Intel Corporation, Santa...

1. An integrated circuit comprising:an n-type transistor including
a first layer comprising nitrogen and at least one of gallium and indium, and
a second layer over the first layer, the second layer distinct from the first layer and comprising nitrogen and at least one of aluminum, gallium, and indium; and
a p-type transistor laterally adjacent to the n-type transistor, and including
a third layer comprising nitrogen and at least one of gallium and indium,
a fourth layer over the third layer, the fourth layer distinct from the third layer and comprising nitrogen and at least one of aluminum, gallium, and indium, and
a fifth layer over the fourth layer, the fifth layer distinct from the fourth layer and comprising nitrogen and at least one of gallium and indium.

US Pat. No. 11,031,304

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) providing a SOI substrate including:
a semiconductor substrate,
an insulating layer formed on the semiconductor substrate, and
a semiconductor layer formed on the insulating layer;
(b) forming a first active region, a second active region and a first power feeding region in the SOI substrate, the first active region, the second active region and the first power feeding region being partitioned by forming an element isolation portion, the element isolation portion penetrating through the semiconductor layer and the insulating layer, and having a bottom portion located in the semiconductor substrate;
(c) forming a first well region in the semiconductor substrate located in each of the first active region, the second active region and the first power feeding region;
(d) removing the semiconductor layer located in the first power feeding region and the insulating layer located in the first power feeding region;
(e) forming a first plug on the semiconductor layer located in the first active region, forming a second plug on the semiconductor layer located in the second active region, forming a third plug on the semiconductor substrate located in the first power feeding region, the third plug being to be coupled with the first well region;
(f) above the first plug, the second plug and the third plug, forming a first pad electrode coupled with the first plug, forming a second pad electrode coupled with the second plug, forming a third pad electrode coupled with the third plug; and
(g) supplying voltages different from one another to the first through third pad electrodes, respectively, and performing a first judging process for determining if a conduction between the first or second pad electrodes and the third pad electrode is confirmed,
wherein, in plan view, each of the first active region and the second active region is extended in a first direction, and
wherein, in plan view, the first active region and the second active region are arranged next to each other in a second direction perpendicular to the first direction.

US Pat. No. 11,031,303

DEEP TRENCH ISOLATION STRUCTURE AND METHOD OF MAKING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure comprising:at least a first semiconductor device located on a first semiconductor substrate material portion located in a high voltage region;
at least a second semiconductor device located on a second semiconductor substrate material portion located outside the high voltage region;
a first moat trench isolation structure electrically insulating the first semiconductor substrate material portion from the second semiconductor substrate material portion; and
a second moat trench isolation structure electrically insulating the first semiconductor substrate material portion from the second semiconductor substrate material portion and laterally surrounding the first semiconductor substrate material portion and laterally surrounded by the first moat trench isolation structure.

US Pat. No. 11,031,302

HIGH-K METAL GATE AND METHOD FOR FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a substrate; and
a first gate structure over the substrate, wherein the first gate structure comprises:
a first gate dielectric layer over the substrate;
a first barrier layer over the first gate dielectric layer;
an oxide layer over the first barrier layer;
a self-assembled monolayer on the oxide layer, the self-assembled monolayer comprising a metal; and
a first metal gate material over the self-assembled monolayer.

US Pat. No. 11,031,301

GATE FORMATION SCHEME FOR N-TYPE AND P-TYPE TRANSISTORS HAVING SEPARATELY TUNED THRESHOLD VOLTAGES

INTERNATIONAL BUSINESS MA...

1. A semiconductor wafer structure comprising a configuration of gate stacks over channel fins, the wafer structure comprising:a first channel fin in a substrate;
a second channel fin in the substrate;
a gate dielectric over the substrate and the first and second channel fins;
a first work function metal stack over the gate dielectric; and the first channel fin;
a second work function metal stack over the gate dielectric and the second channel fin;
wherein the first work function metal stack comprises a first oxygen scavenger layer positioned between a first cap layer and a barrier layer;
wherein the second work function metal stack comprises a thinned region of the first oxygen scavenger layer positioned over the barrier layer;
a third work function metal stack over the first channel fin and the second channel fin to form an updated first work function metal stack over the first channel fin and an updated second work function metal stack over the second channel fin;
wherein the updated first work function metal stack comprises, the barrier layer, the first oxygen scavenger layer, the first cap layer and the third work function metal stack; and
wherein the updated second work function metal stack comprises the barrier layer, the thinned region of the first oxygen scavenger layer, and the third work function stack.

US Pat. No. 11,031,300

SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, comprising:receiving a substrate having a first epitaxy region in a first transistor and a second epitaxy region in a second transistor, wherein the first epitaxy region has a first germanium concentration greater than 50%;
introducing a hydroxyl-sensitive agent directly onto the first epitaxy region and the second epitaxy region, wherein the hydroxyl-sensitive agent is selectively bonded to the second epitaxy region;
selectively depositing a first metal layer on the first epitaxy region; and
depositing a second metal layer on the first epitaxy region and the second epitaxy region;
wherein the hydroxyl-sensitive agent is bonded to hydroxyl groups on a surface of the second epitaxy region; and
wherein the second epitaxy region comprises silicon phosphorus.

US Pat. No. 11,031,299

FINFET DEVICE WITH DIFFERENT LINERS FOR PFET AND NFET AND METHOD OF FABRICATING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a semiconductor device, the method comprising:forming a first fin structure over an N-well and forming a second fin structure over a P-well, wherein the second fin structure includes a first type of semiconductor material, and wherein the first fin structure includes the first type of semiconductor material and a second type of semiconductor material;
forming a first liner layer over the first fin structure and over the second fin structure;
forming a mask layer over a first portion of the first liner layer that is disposed over the first fin structure;
removing a second portion of the first liner layer that is disposed over the second fin structure;
removing the mask layer after the removing of the second portion of the first liner layer;
forming a second liner layer over the first portion of the first liner layer, the second fin structure, and the P-well, wherein the second liner layer contains a different material than the first liner layer;
forming an isolation structure around the first fin structure and the second fin structure; and
partially etching the isolation structure to partially expose side surfaces of the first fin structure and the second fin structure, wherein the partially etching includes etching away portions of the first liner layer disposed on sidewalls of the first fin structure such that the second type of semiconductor material is exposed but the first type of semiconductor material is not exposed.

US Pat. No. 11,031,298

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:forming a first recess and a second recess in a substrate;
growing a first epitaxial material stack in the first recess, the first epitaxial material stack comprising alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped;
growing a second epitaxial material stack in the second recess, the second epitaxial material stack comprising alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped;
patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and
forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

US Pat. No. 11,031,297

MULTIPLE GATE LENGTH VERTICAL FIELD-EFFECT-TRANSISTORS

International Business Ma...

1. A semiconductor structure comprising:a first vertical field-effect transistor formed on a substrate, the first vertical field-effect transistor comprising a first gate having a first vertical gate length;
at least a second vertical field-effect transistor formed on the substrate, the second vertical field-effect transistor comprising a second gate having a second vertical gate length that is different from the first vertical gate length of the first gate of the first vertical field-effect transistor; and
a doped contact layer formed above the substrate and in contact with a bottom-most surface of a respective channel of each of the first and second vertical field-effect transistors,
wherein each of the first and second vertical field-effect transistors comprises at least:
a substrate;
a first spacer layer on the doped contact layer;
a second spacer layer; and
a metal gate in contact with sidewalls of a vertical channel layer, a top surface of the first spacer layer, and a bottom surface of the second spacer layer,
wherein the vertical channel layer of each of the first and second vertical field-effect transistors comprises a narrowed portion above a bottom surface of the second spacer layer that extends above a top surface of the second spacer layer.

US Pat. No. 11,031,296

3D VERTICAL FET WITH TOP AND BOTTOM GATE CONTACTS

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, comprising:flipping a vertical transport field effect transistor including a fin with a bottom side having at least one connection to at least one bottom side metallization structure; and
after flipping the vertical transport field effect transistor, forming at least one top side metallization structure having at least one connection to a top side of the vertical transport field effect transistor.

US Pat. No. 11,031,295

GATE CAP LAST FOR SELF-ALIGNED CONTACT

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor device, the method comprising:forming a gate over a channel region of a fin, the gate comprising a gate spacer;
forming a sacrificial contact on a top surface of a source or drain (S/D) region of a substrate, the sacrificial contact directly adjacent to a sidewall of the gate spacer;
recessing an exposed surface of the gate to form a recessed gate surface;
forming a self-aligned contact (SAC) cap on the recessed gate surface;
polishing to a surface of the SAC cap to expose a surface of the sacrificial contact; and
replacing the sacrificial contact with a S/D contact.

US Pat. No. 11,031,294

SEMICONDUCTOR DEVICE AND A METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a semiconductor fin including an active region in which a channel, a source, and a drain are formed;
a gate dielectric layer disposed over the channel;
a gate electrode disposed over the channel; and
first and second sidewall spacers disposed on sidewalls of the gate electrode and the gate dielectric layer, wherein:
a thickness of the gate dielectric layer decreases in a direction from a center portion of the gate dielectric layer towards the source and decreases in a direction from the center portion of the gate dielectric layer towards the drain region,
the first sidewall spacer has a step structure and the second sidewall spacer has a step structure.

US Pat. No. 11,031,293

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method for reducing the dielectric constant of gate sidewall spacers of a semiconductor device, comprising:forming a sacrificial gate electrode structure extending along a first direction over a fin extending along a second direction substantially perpendicular to the first direction on a semiconductor substrate,
wherein the sacrificial gate electrode structure comprises a sacrificial gate dielectric layer and a sacrificial gate electrode layer disposed over the sacrificial gate dielectric layer;
forming opposing gate sidewall spacers, extending along the second direction, on opposing sides of the sacrificial gate electrode layer;
removing the sacrificial gate electrode layer to form a gate space;
implanting fluorine into the gate sidewall spacers and a channel region of the semiconductor device after removing the gate electrode layer by performing a first fluorine implantation;
removing the sacrificial gate dielectric layer;
forming a metal nitride layer in the gate space; and
implanting fluorine into the gate sidewall spacers and the channel region of the semiconductor device after forming the metal nitride layer by performing a second fluorine implantation.

US Pat. No. 11,031,292

MULTI-GATE DEVICE AND RELATED METHODS

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, comprising:providing a first fin in a first device type region and a second fin in a second device type region, wherein each of the first and second fins include a plurality of semiconductor channel layers;
performing a two-step recess of a shallow trench isolation (STI) region on opposing sides of each of the first and second fins to expose a first number of semiconductor channel layers of the plurality of semiconductor channel layers of the first fin in the first device type region and a second number of semiconductor channel layers of the plurality of semiconductor channel layers of the second fin in the second device type region;
after performing the two-step recess of the STI region, forming a bi-layer dielectric over the STI region adjacent to each of the first and second fins; and
after forming the bi-layer dielectric, forming a first gate structure in the first device type region and a second gate structure in the second device type region, wherein the first gate structure is formed over the first fin having the first number of exposed semiconductor channel layers, and wherein the second gate structure is formed over the second fin having the second number of exposed semiconductor channel layers.

US Pat. No. 11,031,291

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a dielectric layer, comprising:receiving a substrate comprising a semiconductor layer including germanium (Ge) compound;
forming a dielectric layer on the semiconductor layer;
forming a first sacrificial cap including silicon (Si) on the dielectric layer;
annealing the substrate to transform the first sacrificial cap into a second sacrificial cap including SiGe; and
removing the second sacrificial cap to expose the dielectric layer.

US Pat. No. 11,031,290

SEMICONDUCTOR STRUCTURE WITH CUTTING DEPTH CONTROL AND METHOD FOR FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a semiconductor device, wherein the method comprises:forming a first fin and a second fin respectively protruding from a substrate;
forming a pair of spacers each across the first and second fins;
growing source/drain devices on both ends of the first fin and both ends of the second fin;
depositing an inter-layer dielectric layer crossing the first fin and the second fin and enclosing the source/drain devices;
forming a metal gate structure that is laterally between the pair of spacers, crosses the first fin and the second fin, and is enclosed by the inter-layer dielectric layer, wherein the metal gate structure is formed between the source/drain devices;
performing a replacement operation to replace a portion of the inter-layer dielectric layer with an isolation material, thereby forming an isolation portion contacting each of both sides of the metal gate structure between the first fin and the second fin, wherein a bottommost end of the isolation material is lower than a widest position of one of the source/drain devices and higher than a bottommost position of said one of the source/drain devices;
performing a metal gate cut operation on a cut region extending through the metal gate structure to the isolation portion, thereby forming a first opening in the metal gate structure and a second opening in the isolation portion, wherein an etchant of the metal gate cut operation has a lower etching selectivity with respect to the isolation portion than to the metal gate structure, such that a first depth of the first opening is greater than a second depth of the second opening and a bottommost position of the second opening is lower than top surfaces of the pair of spacers and higher than a topmost position of one of the source/drain devices; and
filling the first opening and the second opening with an insulating material.

US Pat. No. 11,031,289

SEMICONDUCTOR PACKAGE AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, the method comprising:forming a first dielectric layer over a passivation layer of a die and over a die connector of the die, the die connector extending through the passivation layer;
curing the first dielectric layer, wherein after curing the first dielectric layer, the first dielectric layer has a curved upper surface distal to the passivation layer, wherein the curved upper surface comprises:
a first region over and contacting the die connector; and
a second region laterally adjacent to the die connector, wherein the first region extends further from the passivation layer than the second region, wherein a first distance between the first region and the second region is larger than a first pre-determined threshold of distance;
forming a second dielectric layer over the cured first dielectric layer; and
curing the second dielectric layer, wherein after curing the second dielectric layer, the first dielectric layer extends along and contacts an upper surface of the die connector and sidewalls of the die connector, and an upper surface of the second dielectric layer distal to the passivation layer comprises:
a third region over and contacting the first region; and
a fourth region over the second region, wherein a second distance between the third region and the fourth region is smaller than the first pre-determined threshold of distance.

US Pat. No. 11,031,288

PASSIVE COMPONENTS IN VIAS IN A STACKED INTEGRATED CIRCUIT PACKAGE

Intel Corporation, Santa...

1. A method comprising:forming a plurality of vias in a silicon wafer;
forming passive devices in a portion of the plurality of vias, wherein forming passive devices in the portion of the plurality of vias comprises forming a capacitor in one of the plurality of vias;
forming power supply circuits on the silicon wafer from the passive devices after forming the passive devices;
dicing the silicon wafer to produce a plurality of uncore dies each having a power supply circuit;
attaching one of the plurality of uncore dies to a substrate; and
attaching a cores die having a processing core to the uncore die, the cores die over the uncore die, the cores die being coupled to the power supply circuit through the passive devices of the uncore die to power the processing core.

US Pat. No. 11,031,287

FULLY SELF-ALIGNED VIA WITH SELECTIVE BILAYER DIELECTRIC REGROWTH

Tokyo Electron Limited, ...

1. A method for processing a substrate, the method comprising:providing a substrate, the substrate including a first dielectric layer, a plurality of conductive structures formed in the first dielectric layer, a top surface of the first dielectric layer being level with top surfaces of the conductive structures;
forming a conductive cap layer over the conductive structures and the first dielectric layer, the conductive cap layer being selectively positioned over the conductive structures with a top surface and sidewalls;
forming a second dielectric layer over the first dielectric layer, the second dielectric layer being selectively positioned over the first dielectric layer so that the top surface of the conductive cap layer is uncovered, and the sidewalls of the conductive cap layer are surrounded by the second dielectric layer;
forming a third dielectric layer over the second dielectric layer, the third dielectric layer being selectively positioned over the second dielectric layer so that the top surface of the conductive cap layer is uncovered, and is lower than a top surface of the third dielectric layer;
forming a fourth dielectric layer over the plurality of conductive structures and the third dielectric layer so as to cover the third dielectric layer and the conductive cap layer; and
forming an interconnect structure within the fourth dielectric layer, the interconnect structure including a trench structure and a via structure that is positioned below the trench structure and connected to the trench structure, the via structure including a first portion positioned over the conductive cap layer and sidewalls of the first portion being surrounded by the third dielectric layer, and a second portion disposed over the first portion and the third dielectric layer.

US Pat. No. 11,031,286

CONDUCTIVE FEATURE FORMATION AND STRUCTURE

Taiwan Semiconductor Manu...

1. A method of semiconductor processing, the method comprising:depositing a metal layer in an opening through one or more dielectric layers to a source/drain region on a substrate, the metal layer being along the source/drain region and along a sidewall of the one or more dielectric layers that at least partially defines the opening;
nitriding the metal layer comprising performing a multiple plasma process that includes at least one directional-dependent plasma process to cause nitridation of a first portion of the metal layer along the sidewall of the one or more dielectric layers and partial nitridation of a second portion of the metal layer along the source/drain region, wherein an un-nitridated portion of the metal layer remains un-nitrided by the multiple plasma process;
forming a silicide region comprising reacting the un-nitrided portion of the metal layer with a portion of the source/drain region; and
disposing a conductive material in the opening on the nitrided first portion of the metal layer and the nitrided second portion of the metal layer.

US Pat. No. 11,031,285

DIFFUSION BARRIER COLLAR FOR INTERCONNECTS

Invensas Bonding Technolo...

1. A microelectronic assembly, comprising:a first substrate having a first substantially planar surface, the first substrate comprising an insulating material;
a second substrate having a first substantially planar surface, the second substrate comprising an insulating material, the first surface of the second substrate directly bonded to the first surface of the first substrate without an adhesive;
a first conductive interconnect structure embedded in the first substrate, a surface of the first conductive interconnect structure being exposed through the first surface of the first substrate to form a first interconnect pad;
a second conductive interconnect structure embedded in the second substrate, a surface of the second conductive interconnect structure being exposed through the first surface of the second substrate to form a second interconnect pad; and
a first barrier interface disposed at the first substantially planar surface of the first substrate and at least partially surrounding a perimeter of the first interconnect pad thereby separating the first conductive interconnect structure from the insulating material at the first substantially planar surface, the first barrier interface comprising a first portion of the first barrier interface at least partially surrounding the first conductive interconnect and contacting the second conductive interconnect, and a second portion of the first barrier interface at least partially surrounding the first conductive interconnect without contacting the second conductive interconnect, the first barrier interface comprising a material different from the insulating material of the first substrate, at least a portion of the first barrier interface extending a predetermined depth into the first substrate, the predetermined depth being less than a depth of the first conductive interconnect structure.

US Pat. No. 11,031,284

SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a substrate having a first conductive pattern;
a conductive mask disposed over the first conductive pattern; and
a second conductive pattern, disposed over the conductive mask and electrically connecting with the first conductive pattern through the conductive mask;
wherein a first width of the first conductive pattern and a second width of the second conductive pattern gradually increase toward each other, wherein the conductive mask comprises two corners from a cross-sectional view, and the second conductive pattern covers up at least one corner, and wherein the conductive mask includes a sidewall surface covered with the second conductive pattern.

US Pat. No. 11,031,283

TRENCH ISOLATION INTERFACES

Micron Technology, Inc., ...

1. A semiconductor structure, comprising:an aluminum oxide (Al2O3) dielectric material on vertical and horizontal surfaces, of a shallow trench isolation (STI) structure in a silicon substrate material, that form a trench between the STI structure and a memory device;
an interface in the trench having a fixed negative charge that is formed by interaction of the silicon substrate material with the Al2O3 dielectric and which raises a parasitic threshold of the STI structure; and
a silicon oxide (SiO2) dielectric material in the trench positioned on a surface of the STI structure, wherein the aluminum oxide (Al2O3) dielectric material is positioned on the SiO2 dielectric material to have the interface with a fixed negative charge by interaction of the SiO2 dielectric material with the Al2O3 dielectric material.

US Pat. No. 11,031,282

THREE-DIMENSIONAL MEMORY DEVICES WITH DEEP ISOLATION STRUCTURES

Yangtze Memory Technologi...

1. A method for forming a three-dimensional memory device, comprising:forming, on a first side of a first substrate, a peripheral circuitry comprising first and second peripheral devices, a first interconnect layer, and a shallow trench isolation (STI) structure between the first and second peripheral devices;
forming, on a second substrate, a memory array comprising a plurality of memory cells and a second interconnect layer;
bonding the first and second interconnect layers;
forming an isolation trench through the first substrate and exposing a portion of the STI structure, wherein the isolation trench is formed through a second side of the first substrate that is opposite to the first side;
disposing an isolation material to form an isolation structure in the isolation trench; and
performing a planarization process to remove portions of the isolation material disposed on the second side of the first substrate.

US Pat. No. 11,031,281

SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING A DEEP TRENCH ISOLATION STRUCTURE

GLOBALFOUNDRIES Singapore...

1. A semiconductor device comprising:a semiconductor substrate;
a deep trench extending from a first portion of the semiconductor substrate to a second portion of the semiconductor substrate, wherein the second portion underlies the first portion, wherein the deep trench has a top end in the first portion and an opposite terminating end in the second portion; and
an insulator region at least substantially lining sides of the deep trench;
wherein the insulator region comprises at least one shallow trench in the first portion of the semiconductor substrate;
wherein at least a portion of the at least one shallow trench is arranged horizontally beside at least a portion of the deep trench; and
wherein the deep trench is filled with a conductive material, and the insulator region and the at least one shallow trench are filled with an insulator material,
wherein the at least one shallow trench has a first end and an opposite second end, the first end being wider than the second end;
wherein the first end of the at least one shallow trench is adjacent to the top end of the deep trench, and
wherein the second end of the at least one shallow trench is adjacent to a mid-section of the deep trench between the terminating end and the top end of the deep trench, such that the top end of the deep trench is narrower than the mid-section of the deep trench.

US Pat. No. 11,031,280

ISOLATION REGIONS INCLUDING TWO LAYERS AND METHOD FORMING SAME

Taiwan Semiconductor Manu...

1. A structure comprising:a semiconductor substrate;
a first isolation region extending into the semiconductor substrate, wherein the first isolation region comprises:
a first dielectric liner;
a first dielectric layer over the first dielectric liner and having a first reflective index; and
a second dielectric layer over the first dielectric layer, wherein the second dielectric layer has a second reflective index lower than the first reflective index, wherein the first dielectric layer is a non-conformal layer and having a first portion, and a second portion and a third portion on opposing sides of the first portion; and
a second isolation region extending into the semiconductor substrate, wherein the second isolation region comprises:
a second dielectric liner; and
a third dielectric layer over the second dielectric liner and having the first reflective index, and the second isolation region is free from dielectric materials having the second reflective index; and
a first gate dielectric over and contacting each of the first dielectric layer, the second dielectric layer, and the first dielectric liner; and
a second gate dielectric comprising a first end and a second end over and contacting opposite sidewall portions of the second dielectric liner.

US Pat. No. 11,031,279

SEMICONDUCTOR DEVICE WITH REDUCED TRENCH LOADING EFFECT

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor structure, the method comprising:forming an etch stop layer on a substrate;
forming a dielectric layer on the etch stop layer;
depositing a tetraethyl orthosilicate (TEOS) layer over the dielectric layer;
depositing a metal hard mask layer over the TEOS layer;
patterning the metal hard mask layer and the TEOS layer;
etching the dielectric layer using the patterned metal hard mask layer and the TEOS layer as masks to form first and second pluralities of trenches within the dielectric layer, wherein the first and second pluralities of trenches are respectively etched using first and second etching rates and a portion of the dielectric layer is between the etch stop layer and bottom surfaces of the first or second plurality of trenches, wherein:
the first and second pluralities of trenches have respective first and second pattern densities that are different and
respective first and second depths that are different and within about 5% of each other;
increasing the first etching rate and reducing the second etching rate by releasing oxygen ions from the TEOS layer into the first and second pluralities of trenches, respectively;
removing the TEOS layer and the metal hard mask layer; and
performing a planarization process on the etched dielectric layer.

US Pat. No. 11,031,278

SUCTION MEMBER

KYOCERA Corporation, Kyo...

1. A suction member comprising:a base part comprising a first surface; and
a plurality of protrusions, each of which comprises:
a side surface contiguous to the first surface of the base part, wherein the side surface comprises a plurality of projecting ridges extending in a direction away from the first surface of the base part; and
a top surface contiguous to the side surface, wherein an area of the top surface of each of the plurality of protrusions is smaller than an area of a bottom portion of each of the plurality of protrusions that is contiguous to the first surface of the base part.

US Pat. No. 11,031,277

PROCESSING APPARATUS

DISCO CORPORATION, Tokyo...

1. A processing apparatus comprising:a holding unit holding a circular wafer;
an imaging unit imaging the outer circumference of said wafer held by said holding unit from the upper side of said holding unit; and
a light emitting member provided separately from said holding unit;
said holding unit including a holding table for holding said wafer under suction in a condition where the outer circumference of said wafer projects from the outer circumference of said holding table, a support member for supporting said holding table, and driving means rotating said holding table;
said holding table including a frustoconical portion and a wafer holding portion formed on the upper surface of said frustoconical portion for holding said wafer, said wafer holding portion having a diameter smaller than that of said wafer;
the lower surface of said frustoconical portion having a diameter larger than that of said wafer, wherein
light is applied from said light emitting member to the side surface of said frustoconical portion and next reflected on the side surface of said frustoconical portion, and the light reflected is next applied to the outer circumference of said wafer held on said wafer holding portion of said holding table to thereby image the outer circumference of said wafer in said imaging unit.

US Pat. No. 11,031,276

WAFER EXPANDING METHOD AND WAFER EXPANDING APPARATUS

DISCO CORPORATION, Tokyo...

1. A wafer expanding method for expanding a wafer having a plurality of rectangular devices respectively formed in a plurality of separate regions defined by a plurality of division lines, thereby increasing spacing between any adjacent ones of the devices, each rectangular device having a pair of shorter sides and a pair of longer sides, the wafer expanding method comprising:a wafer preparing step of supporting the wafer through an adhesive tape to a ring frame having an inside opening for accommodating the wafer in a condition where an annular exposed portion of the adhesive tape is defined between an outer circumference of the wafer and an inner circumference of the ring frame, the wafer being divided along each division line or having division start points inside the wafer along each division line;
a jig preparing step of preparing an annular jig having an elliptical opening, the elliptical opening having a shorter portion for restricting a width of the annular exposed portion in a first direction where the shorter sides of the devices extend to a first width and a longer portion for restricting the width of the annular exposed portion in a second direction where the longer sides of the devices extend to a second width larger than the first width;
a fixing step of mounting the ring frame on a cylindrical frame fixing member, next mounting the annular jig on the ring frame, and next fixing the ring frame and the annular jig to the cylindrical frame fixing member; and
an expanding step of operating a cylindrical pushing member having an outer circumference corresponding to the outer circumference of the wafer to push up the annular exposed portion of the adhesive tape and thereby lift the wafer away from the ring frame after performing the fixing step, thereby expanding the annular exposed portion and increasing the spacing between the adjacent devices,
whereby when the wafer is lifted away from the ring frame by operating the cylindrical pushing member in the expanding step, the annular exposed portion in the first direction is attached to the shorter portion of the annular jig to thereby restrict the width of the annular exposed portion to the first width, and at the same time the annular exposed portion in the second direction is attached to the longer portion of the annular jig to thereby restrict the width of the annular exposed portion to the second width.

US Pat. No. 11,031,275

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH MEMORY

Monolithic 3D Inc., Klam...

1. A 3D semiconductor device, the device comprising:a first level comprising logic circuits,
wherein said logic circuits comprise a plurality of first single crystal transistors and a first metal layer;
a second level comprising a plurality of second transistors,
wherein said second level comprises memory cells comprising said plurality of second transistors;
a second metal layer atop said second level,
wherein said plurality of second transistors are junction-less transistors,
wherein at least one of said plurality of second transistors comprises polysilicon,
wherein said memory cells are structured as a plurality of at least sixteen sub-arrays,
wherein each of said sub-arrays is independently controlled,
wherein at least one of said plurality of at least sixteen sub-arrays is at least partially atop at least one of said logic circuits, and
wherein said at least one of said logic circuits is designed to control at least one of said plurality of at least sixteen sub-arrays.

US Pat. No. 11,031,274

SEMICONDUCTOR DEVICE PACKAGES AND METHOD FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier;
a patterned passivation layer disposed on the carrier; and
a first patterned conductive layer disposed on the carrier and surrounded by the patterned passivation layer, the first patterned conductive layer having a first portion and a second portion electrically disconnected from the first portion, the first portion having a first surface adjacent to the carrier and exposed by the patterned passivation layer, and the second portion having a first surface adjacent to the carrier exposed by the patterned passivation layer;
wherein the first surface of the first portion is in direct contact with an insulation medium, wherein the insulation medium comprises an insulation layer, and wherein the insulation layer comprises a pattern of grid.

US Pat. No. 11,031,273

PHYSICAL VAPOR DEPOSITION (PVD) ELECTROSTATIC CHUCK WITH IMPROVED THERMAL COUPLING FOR TEMPERATURE SENSITIVE PROCESSES

APPLIED MATERIALS, INC., ...

1. An electrostatic chuck, comprising:an electrode;
a dielectric body having a disk shape and covering the electrode, the dielectric body including a central region and a peripheral region, and the dielectric body including a lower surface having a central opening and an upper surface having a first opening in the central region and a plurality of second openings in the peripheral region, wherein the upper surface includes a plurality of protrusions and a diameter of each of the plurality of second openings is greater than 25.0 mils;
gas distribution channels that extend from the lower surface to the upper surface to define a plenum within the dielectric body, the gas distribution channels including a first channel that extends from the central opening to the first opening, a plurality of radial channels that extend from the first channel to an annular channel disposed in the peripheral region, and a plurality of second channels that extend from the annular channel to the plurality of second openings; and
a heater disposed in the dielectric body.

US Pat. No. 11,031,272

MICRO DEVICE ELECTROSTATIC CHUCK WITH DIFFUSION BLOCKING LAYER

MIKRO MESA TECHNOLOGY CO....

1. An electrostatic chuck, comprising:a body;
an electrode disposed on the body;
a diffusion blocking layer disposed on the electrode; and
a composite dielectric layer disposed on the diffusion blocking layer, comprising:
a polymer layer; and
a plurality of inorganic dielectric particles distributed within the polymer layer, a permittivity of the inorganic dielectric particles being greater than a permittivity of the polymer layer.

US Pat. No. 11,031,271

HEATER SYSTEM, CERAMIC HEATER, PLASMA TREATMENT SYSTEM, AND ADSORPTION SYSTEM

KYOCERA Corporation, Kyo...

1. A heater system comprising:a heater comprising:
a ceramic substrate comprising a predetermined surface, and
a resistance heating element extending along the predetermined surface in an internal portion of the ceramic substrate, or on a surface of the ceramic substrate; and
a drive device which is configured to supply power to the resistance heating element, the drive device comprising:
a main driving part which is configured to supply a first power to an entirety of a predetermined first region in the resistance heating element so that current flows from one end of the first region to another end of the first region, and
an additional driving part which is configured to supply a second power, superimposed on the first power, to a second region which is a portion of the first region.

US Pat. No. 11,031,270

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE HOLDER AND MOUNTING TOOL

KOKUSAI ELECTRIC CORPORAT...

1. A substrate processing apparatus, comprising:a substrate holder including at least one support column to which a mounting part on which a substrate is mounted is attached and at least one auxiliary support column to which the mounting part is not attached,
wherein the substrate holder is configured such that a diameter of the at least one auxiliary support column is smaller than a diameter of the at least one support column,
wherein the mounting part includes a contact part configured to support the substrate and a main body part extending between the contact part and the at least one support column,
wherein the substrate holder is configured such that when the substrate is held by the mounting part, an end portion of the substrate and the at least one support column are spaced apart from each other by a length of the main body part so as to hold the substrate with the contact part, and
wherein a distance between the end portion of the substrate and the at least one support column is changeable by changing the length of the main body part.

US Pat. No. 11,031,269

SUBSTRATE TRANSPORT ROBOT, SUBSTRATE TRANSPORT SYSTEM, AND SUBSTRATE TRANSPORT METHOD

KAWASAKI JUKOGYO KABUSHIK...

1. A substrate transport robot comprising:a base installed inside a transport chamber;
an arm coupled to the base and including at least three links, each of the at least three links being configured to rotate within a horizontal plane;
a first hand and a second hand, each of the first hand and the second hand being coupled to a distal end portion of the arm such that each of the first hand and the second hand is rotatable about a vertical hand axis, the first hand and the second hand each being configured to support a substrate;
at least five actuators that drive the at least three links, the first hand, and the second hand to rotate, respectively; and
a controller configured to control operations of the at least five actuators, the controller being configured to perform:
a first transfer process of causing the first hand to enter from the transport chamber into a storage chamber that communicates with the transport chamber via an opening, and transferring the substrate between the first hand and a placing portion in the storage chamber, the placing portion being a portion on which the substrate is to be placed;
an exit process of causing the first hand to exit the storage chamber and move into the transport chamber, and controlling operations of the arm and the first hand to move the hand axis away from a center line of the opening, the center line being perpendicular to the opening, such that the hand axis is farther from the center line than a reference position of the first hand; and
a second transfer process of causing the second hand to enter from the transport chamber into the storage chamber, and transferring the substrate between the placing portion and the second hand.

US Pat. No. 11,031,268

DEVICE FOR IN SITU THERMAL CONTROL AND TRANSFER OF A MONOLAYER OR THIN FILM

Purdue Research Foundatio...

1. A device for transferring a monolayer or a thin film comprisinga) a magnetic sample disc; and
b) a heater body encompassing
i. a cartridge heater operatively connected to a temperature controller for heating and temperature control; and
ii. a thermocouple operatively connected to the temperature controller for heating and temperature control; and
c) a magnet positioned at one end of the heater body to provide sufficient force for picking up said magnetic sample disc without physically touching the magnetic sample disc.

US Pat. No. 11,031,267

METHOD AND SYSTEM OF MEASURING AIR-TIGHTNESS AND CONTAINER MEASURED THEREBY

GUDENG PRECISION INDUSTRI...

1. A method of measuring air-tightness, comprising:providing a first cover and a first base for cooperating with each other, wherein the first cover has a first contact surface and the first base has a second contact surface for engaging with the first contact surface to form an air-tight state;
measuring a first contour curve, wherein the first contour curve is a full measurement of the contour of the first contact surface;
measuring a second contour curve, wherein the second contour curve is a full measurement of the contour of the second contact surface;
bringing the first contour curve into contact with the second contour curve after the first contour curve and the second contour curve are measured;
calculating, based on the first and the second contour curves that are matched with each other, to determine a first gap area between the first contour curve and the second contour curve; and
pairing the first cover and the first base as a first combination of acceptable air-tightness when the first gap area is determined to be equal to or smaller than a threshold, thereby forming a first container.

US Pat. No. 11,031,266

WAFER HANDLING EQUIPMENT AND METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

11. A method, comprising:disposing a wafer carrier onto a load port;
detecting, by a first sensor in the wafer carrier, an orientation of a slot in the wafer carrier;
aligning an orientation of a wafer transferring device with the orientation of the slot;
moving, with the aligned orientation of the wafer transferring device, a wafer to the slot by the wafer transferring device;
during moving the wafer to the slot, detecting a radiation from the first sensor by using a second sensor disposed on an end effector of the wafer transferring device;
determining whether an intensity of the radiation is higher than a predetermined threshold intensity; and
in response to determining that the intensity of the detected radiation is higher than the predetermined threshold intensity, terminating the movement of the wafer.

US Pat. No. 11,031,265

LOAD PORT MODULE

Brooks Automation, Inc., ...

1. A substrate loading device comprising:a frame adapted to connect the substrate loading device to a substrate processing apparatus, the frame having a transport opening through which substrates are transported between the substrate loading device and the substrate processing apparatus;
a cassette support connected to the frame for holding at least one substrate cassette container for transfer of substrates to and from the at least one substrate cassette container through the transport opening; and
cassette support purge ports with more than one purge port nozzle locations disposed on the cassette support, each of the more than one purge port nozzle locations being configured so that a purge port nozzle at the purge port nozzle location couples to at least one purge port of the at least one substrate cassette container;
wherein each purge port nozzle location defines an interchangeable purge port nozzle interface so that different interchangeable purge port nozzles, corresponding to different interchangeable purge port nozzle modules each having different predetermined purge nozzle configurations, are removably mounted to respective purge port nozzle interfaces of the more than one purge port nozzle locations that correspond to the different predetermined purge nozzle configurations of the interchangeable purge port nozzle modules, in conformance with and effecting coupling to different ports, of the at least one purge port, of different substrate cassette containers, of the at least one substrate cassette container, having different purge port characteristics.

US Pat. No. 11,031,264

SEMICONDUCTOR DEVICE MANUFACTURING SYSTEM

Taiwan Semoconductor Manu...

1. A semiconductor device manufacturing system, comprising:a processing module comprising:
a processing chamber configured to process a substrate, and
a gate valve configured to provide access to the processing chamber; and
a transfer module comprising:
a transfer chamber coupled to the processing chamber and configured to receive the substrate and transfer the received substrate to the processing module; and
a liner coupled to an inner surface of the transfer chamber and configured to reduce a volume of the transfer chamber while being separated from the substrate.

US Pat. No. 11,031,263

LASER STRIPPING MASS-TRANSFER DEVICE AND METHOD FOR MICRODEVICES BASED ON WINDING PROCESS

HUAZHONG UNIVERSITY OF SC...

1. A laser stripping mass-transfer device for microdevices based on a winding process, the laser stripping mass-transfer device comprising a microdevice stripping transfer module, an auxiliary conveyor module, a transition conveyor module, a transfer conveyor module, a substrate carrier module, a microdevice filling module, a curing module, an encapsulation module, and a substrate transportation module, wherein:the microdevice stripping transfer module is located above a left side of the auxiliary conveyor module and is configured to implement detection and stripping of the microdevices;
the auxiliary conveyor module is configured to adhere the stripped microdevices, and then transfer the stripped microdevices onto the transition conveyor module;
the transition conveyor module is located above a right side of the auxiliary conveyor module and is configured to continuously pick up the microdevices from the auxiliary conveyor module and transfer the microdevices onto the transfer conveyor module;
the transfer conveyor module is located on a right side of the transition conveyor module and is configured to continuously pick up the microdevices from the transition conveyor module and transfer the microdevices onto the substrate carrier module;
the substrate carrier module is located below the transfer conveyor module and is configured to receive the microdevices transferred from the transfer conveyor module and feed the microdevices into the microdevice filling module, the curing module and the encapsulation module in sequence;
the microdevice filling module, the curing module, the encapsulation module, and the substrate transportation module are all disposed on a right side of the transfer conveyor module in sequence from left to right and are respectively configured for filling, curing, encapsulating and loading and unloading; and
wherein the stripped microdevices have an equal-interval spacing on the auxiliary conveyor module, the transition conveyor module, the transfer conveyor module, and the substrate carrier module.

US Pat. No. 11,031,262

LOADLOCK INTEGRATED BEVEL ETCHER SYSTEM

Applied Materials, Inc., ...

1. A chamber, comprising:a substrate support having a substrate support surface positioned in a processing region;
a masking assembly coupled to a gas source, the masking assembly comprising:
a masking plate; and
a baffle connected with the masking plate, the baffle including a standoff portion positioned to contact the substrate support, and wherein, when the substrate support is disposed against the standoff portion, a uniform gap defined by parallel surfaces is formed between a portion of the mask assembly and the peripheral region of the substrate support.

US Pat. No. 11,031,261

LIQUID PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A liquid processing apparatus for horizontally holding a substrate in a substrate holding section having a front side, from and into which the substrate is loaded, and performing liquid processing on the substrate using processing fluid, comprising:a plurality of substrate holding units arranged side by side in a left-right direction, each of the substrate holding units holding the substrate horizontally;
a first nozzle provided in a corresponding relationship with each of the substrate holding units, and supplying a first processing fluid to the substrate held in each of the substrate holding units;
a first arm portion moving the first nozzle forward and backward in a front-rear direction between a first supplying position in which the first processing fluid is supplied to a region including a central portion of the substrate and a first waiting position which is located at a rear side of each of the substrate holding units, so that a discharge portion of the first nozzle moves in a horizontal straight line (L) which passes over the central portion of the substrate;
a second nozzle supplying a second processing fluid to the substrate held in each of the substrate holding units;
a second arm portion moving the second nozzle forward and backward in the front-rear direction between a second supplying position in which the second processing fluid is supplied to the region including the central portion of the substrate and a second waiting position which is located at the rear side of each of the substrate holding units, so that a discharge portion of the second nozzle moves in the horizontal straight line (L); and
a nozzle cleaning unit for cleaning the first nozzle and the second nozzle, and located on the horizontal straight line (L),
wherein the first arm portion and the second arm portion are arranged side by side in the left-right direction.

US Pat. No. 11,031,260

HYDROGEN FLUORIDE VAPOR PHASE CORROSION METHOD

JIANGSU LEUVEN INSTRUMENT...

1. A hydrogen fluoride vapor phase corrosion method, the method comprising:introducing a prescribed vaporized organic liquid into a reaction chamber after a vapor phase hydrogen fluoride containing water reacts, in the reaction chamber, with a wafer;
the prescribed vaporized organic liquid, and the water remaining on a surface of the wafer form an azeotropic mixture; and
evaporating or volatilizing the azeotropic mixture from the surface of the wafer to carry it out.

US Pat. No. 11,031,259

METHOD OF MANUFACTURING AN ELECTRONIC DEVICE AND ELECTRONIC DEVICE MANUFACTURED THEREBY

Amkor Technology Singapor...

1. An electronic device comprising:a substrate comprising an interposer comprising a first interposer side, and a second interposer side opposite the first interposer side;
a semiconductor die comprising a first die side, a second die side opposite the first die side and coupled to the first interposer side, and lateral die sides extending between the first and second die sides;
a first encapsulating material comprising a first encapsulant side facing away from the substrate and a second encapsulating side facing toward the substrate, where the first encapsulating material, laterally surrounds at least the entire lateral die sides, and covers at least the first interposer side;
a second encapsulating material that covers at least the first encapsulant side of the first encapsulating material; and
an interconnection structure on the second interposer side.

US Pat. No. 11,031,258

SEMICONDUCTOR PACKAGES WITH PATTERNS OF DIE-SPECIFIC INFORMATION

Micron Technology, Inc., ...

1. A semiconductor device package, comprising:a first surface and a second surface opposite the first surface;
a semiconductor die positioned between the first and second surfaces; and
a pattern in a designated area of the first surface, the pattern including multiple bit areas, each of the bit areas representing a first bit information or a second bit information, the pattern presenting information for operating the semiconductor die, the pattern being configured to be read by a pattern scanner.

US Pat. No. 11,031,257

METHOD FOR MANUFACTURING POWER DEVICE COOLER

NIPPON LIGHT METAL COMPAN...

1. A method for manufacturing a power device cooler having: first and second aluminum cases joined together to form a refrigerant circulation space therein; and a plurality of aluminum fins arranged inside the refrigerant circulation space and each forming a refrigerant flow passage along with an adjacent portion, the cooler being joined to a heating element equipped with a power device, to cool heat generated from the power device, the method comprising:a braze-joining step of brazing the first and second cases and the fins by means of a non-corrosive flux and a brazing filler material; and
a flux residue removal step of removing flux residues on surfaces of the first and second cases after the brazing,
wherein the flux residue removal step is performed by a wet blasting method in which a mixture of an abrasive formed of polygonal alumina particles having a median particle diameter of 4 to 250 ?m and a liquid is projected, by compressed air, onto a heat receiving surface of the first and second cases that is joined to the heating element.

US Pat. No. 11,031,256

SEMICONDUCTOR DEVICE WITH TIERED PILLAR AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY SINGAPOR...

1. A semiconductor device, comprising:a lower redistribution structure;
a first semiconductor die comprising a die upper side and a die lower side, the die lower side coupled to an upper side of the lower redistribution structure;
an upper redistribution structure comprising a lower side above the die upper side; and
a conductive pillar that couples the lower redistribution structure to the upper redistribution structurel, wherein:
the conductive pillar comprises a lower tier and an upper tier;
the upper tier comprises a lower end coupled to an upper end of the lower tier;
the lower tier comprises a lower end coupled to the upper side of the lower redistribution structure; and
a distance between the upper end of the lower tier and the upper side of the lower redistribution structure is greater than a distance between the die lower side and the upper side of the lower redistribution structure.

US Pat. No. 11,031,255

STACK FRAME FOR ELECTRICAL CONNECTIONS AND THE METHOD TO FABRICATE THEREOF

CYNTEC CO., LTD., Hsinch...

1. A method for forming a conductive structure, the method comprising:forming a lead frame having a plurality of pins, wherein a recess is formed in the lead frame;
disposing an electronic device in the recess;
forming an insulating layer over the lead frame and the electronic device, wherein the insulating layer physically contacts the recess and a top surface of the lead frame that is adjacent to the recess; and
forming at least one conductive pattern layer over the insulating layer, wherein the at least one conductive pattern layer comprises a plurality of electrical connections to connect with the plurality of pins and at least one first I/O terminal of the electronic device.

US Pat. No. 11,031,254

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) preparing a lead frame including a plurality of leads, and a chip mounting portion, each of the plurality of leads having a surface on which a silver plating layer is formed;
(b) mounting a semiconductor chip on the chip mounting portion of the lead frame via a bonding material;
(c) after the step (b), performing an oxygen plasma treatment on the lead frame and the semiconductor chip;
(d) after the step (c), reducing a surface of the silver plating layer; and
(e) after the step (d), electrically connecting a plurality of pad electrodes of the semiconductor chip and the plurality of leads via a plurality of copper wires,
wherein, in the step (e), the plurality of copper wires is connected to the plurality of leads, respectively, via the silver plating layer.

US Pat. No. 11,031,253

ETCHING USING AN ELECTROLYZED CHLORIDE SOLUTION

IMEC VZW, Leuven (BE)

1. A method for etching one or more entities on a semiconductor structure, each entity being made of a material selected from metals and metal nitrides, the method comprising the steps of:(a) oxidizing by electrolysis, at a current of at least 0.1 A, a precursor solution comprising chloride anions at a concentration ranging from 0.01 mol/l to 1.0 mol/l thereby forming an etching solution;
(b) providing a semiconductor structure having the one or more entities thereon; and
(c) etching at least partially the one or more entities by contacting them with the etching solution.

US Pat. No. 11,031,252

HEAT SHIELD FOR CHAMBER DOOR AND DEVICES MANUFACTURED USING SAME

Taiwan Semiconductor Manu...

1. A device comprising:a chamber defined by a chamber wall;
a wafer holding stage within the chamber;
a door in the chamber wall, the door configured to allow access to the chamber, the door comprising a main structure, an attachment structure, and hinges, wherein the attachment structure is connected to the chamber wall, and wherein the main structure is connected to the attachment structure by the hinges, the hinges allowing the main structure to rotate about the attachment structure, the main structure of the door having a first face facing into the chamber and a second face facing away from the chamber;
a heater disposed in the attachment structure of the door, the heater configured to provide heat to the door through thermal conduction of heat from the heater, through the hinges, and to the main structure of the door; and
a heat shield attached to the door, the heat shield being configured to reduce transmission of heat from the door to the wafer holding stage, wherein the heat shield comprises a thermally insulating membrane and a rigid plate affixing the thermally insulating membrane to the door, the thermally insulating membrane disposed between the door and the rigid plate, the thermally insulating membrane having a first center portion and a first outer periphery, the first outer periphery surrounding the first center portion, wherein the rigid plate has a first surface and a second surface, the first surface contacting the first center portion of the thermally insulating membrane, the second surface exposed to the chamber and being free of the thermally insulating membrane, the first outer periphery of the thermally insulating membrane exposed to the chamber and being free of the rigid plate, wherein the first face of the main structure of the door has a second center portion and a second outer periphery, the second outer periphery surrounding the second center portion, wherein the second center portion is covered by the heat shield, wherein the chamber wall, the attachment structure, the hinges, and the second outer periphery are uncovered by the heat shield, and wherein the thermally insulating membrane is a teflon membrane.

US Pat. No. 11,031,251

SELF-ALIGNED PLANARIZATION OF LOW-K DIELECTRICS AND METHOD FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. A device comprising:an interlayer dielectric (ILD) with a first region and a second region;
a pair of copper (Cu) back-end-of-line (BEOL) structures in the ILD in the first region;
a capping layer over the ILD and a portion of the Cu BEOL structures;
an oxide layer over the capping layer;
a metal filled via through the oxide layer and the capping layer to a Cu BEOL structure;
a bottom electrode (BE) over the metal filled via;
a magnetic tunnel junction (MTJ) structure over the BE;
a top electrode (TE) over the MTJ structure;
a nitride layer over and along sidewalls of the MTJ structure, TE, and the oxide layer;
a first low-K layer over the ILD;
a triangular shaped second oxide layer over the first low-K layer in the second region of the ILD; and
a second low-K layer over the ILD.

US Pat. No. 11,031,250

SEMICONDUCTOR STRUCTURES OF MORE UNIFORM THICKNESS

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a first layer of material on top of a first semiconductor structure, the first layer of material having a first composition and a first index of refraction, the first semiconductor structure being located within 5-100 nanometers to a second semiconductor structure relative to a surface of a layer of substrate;
forming a second layer of material on top of first layer of material, the second layer of material having a second composition and a second index of refraction, wherein the first layer of material and the second layer of material are of a same type of material; and
forming an opening to the first semiconductor structure by applying a first etching that etches through at least a first portion of the first layer of material to expose a portion of the first semiconductor structure.

US Pat. No. 11,031,249

ELECTRONIC DEVICE WITH A GATE INSULATING FILM AND A CAP LAYER OF SILICON NITRIDE HAVING CRYSTALLINITY

SUMITOMO CHEMICAL COMPANY...

1. An electronic device comprising:a wafer;
a nitride crystal layer formed of one or more crystal layers of group III nitride; and
a cap layer, wherein
the wafer, the nitride crystal layer and the cap layer are positioned in an order of the wafer, the nitride crystal layer and the cap layer,
the nitride crystal layer comprises an element forming layer that is in contact with the cap layer,
the element forming layer comprises a first crystal layer, a second crystal layer that is formed on the first crystal layer and has a larger band gap than the first crystal layer, a gate structure of a field-effect transistor formed on the second crystal layer and a source/drain region formed in the first crystal layer and the second crystal layer, and a gate insulating film formed by the same material as the cap layer,
a two-dimensional carrier gas is generated near a hetero interface between the first crystal layer and the second crystal layer,
the cap layer is a silicon nitride layer having crystallinity and has a thickness that is larger than a height of the gate structure.

US Pat. No. 11,031,248

ALTERNATING HARDMASKS FOR TIGHT-PITCH LINE FORMATION

Tessera, Inc., San Jose,...

1. A method for forming fins, comprising:forming a three-color hardmask fin pattern on a fin base layer, the three-color hardmask fin pattern comprising hardmask fins of three mutually selectively etchable compositions;
etching away some of the fins of a first color with a selective etch that does not remove fins of a second color or a third color and that leaves at least one fin of the first color behind;
etching away the fins of the second color; and
etching fins into the fin base layer by anisotropically etching around remaining fins of the first color and fins of the third color.

US Pat. No. 11,031,247

METHOD AND APPARATUS FOR DEPOSITING A MONOLAYER ON A THREE DIMENSIONAL STRUCTURE

Varian Semiconductor Equi...

1. A method, comprising:providing a substrate in a first position, the substrate having a surface that defines a substrate plane and a substrate feature that extends from the substrate plane, the substrate feature having at least one surface that extends at a non-zero angle with respect to the substrate plane, the surface feature comprising a set of sidewalls, a trench and a top surface;
directing an ion beam through an extraction plate, arranged adjacent the substrate and parallel to the substrate plane, while the substrate is in the first position, the ion beam comprising angled ions that are incident on the substrate at a nonzero peak angle between 15 degrees and 45 degrees with respect to a perpendicular to the substrate plane, the ion beam effective to form a first sub-monolayer comprising a first species on the substrate feature including the at least one surface, wherein the first sub-monolayer is a uniform sub-monolayer that is formed uniformly on the set of sidewalls, the trench and the top surface;
scanning the substrate from the first position, to a second position, along a path that is parallel to the substrate plane; and
directing a molecular beam to the substrate when the substrate is in the second position when the first sub-monolayer is disposed on the substrate feature, the molecular beam being effective to form a second sub-monolayer of a second species that is configured to react with the first sub-monolayer of the first species to form a uniform monolayer of a product material on the substrate feature including on the set of sidewalls, the trench and the top surface.

US Pat. No. 11,031,245

TIN OXIDE THIN FILM SPACERS IN SEMICONDUCTOR DEVICE MANUFACTURING

Lan Research Corporation,...

1. A method of processing a semiconductor substrate, the method comprising:(a) providing a semiconductor substrate comprising an exposed SnO2 layer and a layer of a silicon-containing material, wherein the layer of the silicon-containing material comprises an exposed portion, and a non-exposed portion, wherein the exposed SnO2 layer is over and in direct contact with the non-exposed portion of the layer of the silicon-containing material, and wherein the silicon-containing material in the exposed portion of the layer of the silicon-containing material is the same as in the non-exposed portion of the layer of the silicon-containing material; and
(b) etching the exposed portion of the layer of the silicon-containing material in a presence of the exposed SnO2 layer using an etch chemistry selected such that a ratio of an etch rate of the silicon-containing material to an etch rate of SnO2 is greater than 1, wherein the etching exposes an underlying layer having a different composition from a composition of the exposed portion of the layer of the silicon-containing material.

US Pat. No. 11,031,244

MODIFICATION OF SNO2 SURFACE FOR EUV LITHOGRAPHY

Lam Research Corporation,...

1. A method, comprising:introducing a hydrophobic surface treatment compound into a processing chamber, the processing chamber contains a substrate with an SnO2 layer for processing, the hydrophobic surface treatment compound forms a modification to a surface of the SnO2 layer that increases more a hydrophobicity of the surface; and
depositing a photoresist layer on the surface of the SnO2 layer via spin coating, said modification of the surface of the SnO2 layer enhances adhesion of contact between the photoresist and the SnO2 layer during spin coating;
wherein the hydrophobic surface treatment compound includes a reactive group and an amino group, the reactive group reacts with Sn atoms of the surface of the SnO2 layer for said modification and the amino group participates in hydrophobic-hydrophobic interactions with the photoresist by increasing the hydrophobicity of the surface.

US Pat. No. 11,031,243

NANOWIRE WITH REDUCED DEFECTS

Microsoft Technology Lice...

1. A nanowire structure comprising:a substrate;
a patterned mask layer on the substrate, the patterned mask layer having an opening through which the substrate is exposed; and
a nanowire on the substrate through the opening in the patterned mask layer, the nanowire comprising:
a buffer layer on the substrate;
a defect filtering layer on the buffer layer, wherein the defect filtering layer is a strained layer; and
an active layer on the defect filtering layer.

US Pat. No. 11,031,242

METHODS FOR DEPOSITING A BORON DOPED SILICON GERMANIUM FILM

ASM IP Holding B.V., Alm...

1. A method for depositing a boron doped silicon germanium (Si1-xGex) film, the method comprising:providing a substrate within a reaction chamber;
heating the substrate to a deposition temperature;
flowing a silicon precursor, a germanium precursor, and a halide gas into the reaction chamber through a first multi-port gas injector (MPI) having a first plurality of individual port injectors for providing a gas mixture into the reaction chamber;
flowing a boron dopant precursor into the reaction chamber through a second multi-port gas injector (MPI) independent from the first gas injector, the second MPI having a second plurality of individual port injectors for providing the boron dopant precursor into the reaction chamber;
individually controlling flow rates of the gas mixture through the first plurality of individual ports;
individually controlling flow rates of the boron dopant precursor through the second plurality of individual ports;
contacting the substrate with the silicon precursor, the germanium precursor, the halide gas, and the boron dopant precursor; and
depositing the boron doped silicon germanium (Si1-xGex) film over a surface of the substrate wherein the boron concentration in the boron doped silicon germanium film varies across the substrate such that a ratio of an edge boron concentration (EBC) and a center boron concentration (CBC), expressed as an EBC/CBC value, differ.

US Pat. No. 11,031,241

METHOD OF GROWING DOPED GROUP IV MATERIALS

Applied Materials, Inc., ...

1. A method of forming a semiconductor film, comprising:introducing at least one dopant precursor comprising a dopant to a process chamber while a substrate is positioned therein;
soaking the substrate in the at least one dopant precursor for a first predetermined period of time to form a dopant layer on the substrate;
purging the at least one dopant precursor from the process chamber to remove the at least one dopant precursor from the process chamber while the dopant layer remains on the substrate; and
introducing a semiconductor film precursor to the process chamber to form a semiconductor film on the substrate, the semiconductor film including a group IV element and having a concentration of the dopant from about 1.0×1019 atoms/cm3 to about 5.0×1021 atoms/cm3.

US Pat. No. 11,031,240

METHOD FOR GROWING GALLIUM NITRIDE BASED ON GRAPHENE AND MAGNETRON SPUTTERED ALUMINUM NITRIDE

14. A gallium nitride film, comprising the following structures in order from bottom to top: a substrate, a graphene layer, an aluminum nitride nucleation layer formed by a magnetron sputtering method, a first gallium nitride layer, and a second gallium nitride layer; wherein V-III ratio of the first gallium nitride layer is different from V-III ratio of the second gallium nitride layer;wherein the gallium nitride film further comprises an aluminum nitride transition layer located between the aluminum nitride nucleation layer and the first gallium nitride layer.

US Pat. No. 11,031,239

GERMANIUM NANOSHEETS AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:receiving a wafer comprising a stack of alternating semiconductor layers on a substrate, the stack of alternating semiconductor layers comprising alternating layers of a group IV semiconductor and layers of germanium, wherein the group IV semiconductor comprises Sn in a concentration ranging from about 20.3% to about 25.5%;
shaping the stack of alternating semiconductor layers to have a first pad, a second pad, and a narrow portion between the first and second pads;
forming a plurality of germanium nanosheets by removing the narrow portion of the layers of the group IV semiconductor, wherein a width of the plurality of germanium nanosheets closer to the substrate is wider than a width of the plurality of germanium nanosheets further from the substrate; and
depositing a dielectric material that surrounds at least a portion of each of the plurality of germanium nanosheets.

US Pat. No. 11,031,238

SILICON CARBIDE STACKED SUBSTRATE AND MANUFACTURING METHOD THEREOF

Hitachi Metals, Ltd., To...

1. A silicon carbide stacked substrate comprising:a first substrate of a first conductivity type which is a hexagonal semiconductor substrate containing silicon carbide;
a first semiconductor layer of the first conductivity type formed on the first substrate and containing silicon carbide;
a second semiconductor layer of the first conductivity type formed on the first semiconductor layer and containing silicon carbide; and
a third semiconductor layer of the first conductivity type formed on the second semiconductor layer and containing silicon carbide,
wherein the first semiconductor layer is in contact with an upper surface of the first substrate,
wherein a first impurity concentration of the first semiconductor layer is lower than any of a second impurity concentration of the second semiconductor layer and a fourth impurity concentration of the upper surface of the first substrate and is higher than a third impurity concentration of the third semiconductor layer, and the second impurity concentration is higher than the third impurity concentration,
wherein the first impurity concentration is 1×1017 cm?3 or lower, and
wherein the fourth impurity concentration is higher than 1×1018 cm?3.

US Pat. No. 11,031,237

AROMATIC AMINO SILOXANE FUNCTIONALIZED MATERIALS FOR USE IN CAPPING POROUS DIELECTRICS

Merck Patent GMbH, Darms...

1. A compound having structure (1a), whereinX1a is a head group which has structure (3); X2a is a tail group selected from the group consisting of structures (4), and (4a);
represents a point of attachment;
Q and Q1 are independently selected from hydrogen or an alkyl group; wherein m is a integer ranging from 2 to 8, wherein, r? is the number of tail groups attached to the head group, and is 1, and m1 and m2 are integers independently ranging from 2 to 8; y and y1 independently are 0, 1 or 2; and further wherein R and R1 are independently selected from a C1 to C6 alkyl group;

US Pat. No. 11,031,236

METHOD FOR IMPROVING SURFACE OF SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor structure, the method comprising:forming a first top electrode (TE) layer over a magnetic tunnel junction (MTJ) layer;
performing a smoothing treatment on the first TE layer, wherein the smoothing treatment is performed in situ with the forming the first TE layer, the smoothing treatment being performed at a temperature in a range of 200° C. to 600° C.; and
forming additional TE layers over the first TE layer.

US Pat. No. 11,031,235

SUBSTRATE PROCESSING APPARATUS

SCREEN Holdings Co., Ltd....

1. A substrate processing apparatus comprising:a substrate rotation holding device including a rotary table that is rotatable around a rotational axis along a vertical direction, and a plurality of support pins to support a substrate horizontally, the plurality of support pins disposed to rotate around the rotational axis together with the rotary table,
wherein the plurality of support pins includes a movable pin that has a support portion disposed movably between a contact position at which the support portion comes into contact with a peripheral edge of the substrate and an open position that is more distant from the rotational axis than the contact position;
the substrate processing apparatus further comprising:
a driving magnet that is coupled to the movable pin and that has a predetermined polar direction with respect to a radial direction of the rotary table;
a pressing magnet that has a magnetic pole and is arranged for applying an attractive magnetic force or a repulsive magnetic force between the driving magnet and the pressing magnet so as to press the support portion against the peripheral edge of the substrate by urging the support portion toward the contact position by means of the attractive magnetic force or the repulsive magnetic force;
a rotating/driving unit that rotates the rotary table together with the plurality of support pins and the driving magnet coupled to the movable pin around the rotational axis; and
a pressing-force changing unit that changes a magnitude of a pressing force against the peripheral edge of the substrate pressed by the support portion in response to rotation of the rotary table around the rotational axis while keeping the magnitude of the pressing force higher than zero; wherein
the pressing-force changing unit comprises
a magnetic-force generating magnet that is a magnet differing from the pressing magnet, and that has a magnetic pole that gives an attractive magnetic force or a repulsive magnetic force between the driving magnet and the magnetic-force generating magnet to urge the support portion toward the open position, the magnetic-force generating magnet being partially disposed on a circumference centered on the rotational axis, the magnetic-force generating magnet and the rotary table relatively rotating with respect to each other when the rotary table is rotating;
a magnet drive unit that drives the magnetic-force generating magnet; and
a pressing-force changing control unit that controls the magnet drive unit so as to place the magnetic-force generating magnet at a first position at which an attractive magnetic force or a repulsive magnetic force is generated between the driving magnet and the magnetic-force generating magnet with a smaller magnitude thereof than an attractive magnetic force or a repulsive magnetic force generated between the driving magnet and the pressing magnet, thereby changing the magnitude of the pressing force applied by the support portion while keeping the magnitude of the pressing force higher than zero when the rotary table together with the plurality of support pins are rotating around the rotational axis so that the driving magnet and the magnetic-force generating magnet placed at the first position are relatively rotating around the rotation axis.

US Pat. No. 11,031,234

WAFER PROCESSING METHOD INCLUDING APPLYING A POLYOLEFIN SHEET TO A WAFER

DISCO CORPORATION, Tokyo...

1. A wafer processing method for dividing a wafer along a plurality of division lines to obtain a plurality of individual device chips, the division lines being formed on a front side of the wafer, the wafer processing method comprising:a ring frame preparing step of preparing a ring frame having an inside opening for accommodating the wafer;
a polyolefin sheet providing step of positioning the wafer in the inside opening of the ring frame and providing a polyolefin sheet having no adhesive layer on a back side of the wafer and on a back side of the ring frame, such that the polyolefin sheet is in direct contact with the back side of the wafer and the back side of the ring frame;
a uniting step of heating the polyolefin sheet as applying a pressure to the polyolefin sheet after performing the polyolefin sheet providing step, thereby uniting the wafer and the ring frame through the polyolefin sheet by thermocompression bonding to form a frame unit in a condition where the wafer and the ring frame are exposed;
a dividing step of applying a laser beam to the wafer along each division line, the laser beam having an absorption wavelength to the wafer, after performing the uniting step, thereby forming a division groove in the wafer along each division line to divide the wafer into the individual device chips; and
a pickup step of blowing air at each device chip through the polyolefin sheet to push up each device chip, thereby picking up each device chip from the polyolefin sheet after performing the dividing step.

US Pat. No. 11,031,233

HIGH LATERAL TO VERTICAL RATIO ETCH PROCESS FOR DEVICE MANUFACTURING

Applied Materials, Inc., ...

1. A system to manufacture an electronic device, comprising:a plasma etch chamber having an inlet to input a gas; and
at least one power source coupled to the plasma etch chamber, a processing unit coupled to the at least one power source to provide a plurality configurations for the at least one power source, the at least one power source having a first configuration to control etching a layer stack over a substrate using a photoresist pattern deposited on the layer stack as a first mask, the at least one power source having a second configuration to control curing the photoresist pattern using a plasma including silicon by-products to form a cured photoresist pattern, the at least one power source having a third configuration to control slimming the cured photoresist pattern, and the at least one power source having a fourth configuration to control etching the layer stack using the slimmed photoresist pattern as a second mask.

US Pat. No. 11,031,232

INJECTION OF IONS INTO AN ION STORAGE DEVICE

Thermo Fisher Scientific ...

1. A method of injecting ions into an ion storage device, comprising:providing an RF trapping field in the ion storage device that defines a trapping volume in the ion storage device by applying one or more RF voltages to one or more trapping electrodes;
providing a gas in the trapping volume;
injecting ions into the trapping volume through an aperture in an end electrode located at a first end of the ion storage device, the end electrode having a DC voltage applied thereto;
reflecting the injected ions at a second end of the ion storage device, opposite to the first end, thereby returning the ions to the first end; and
ramping the DC voltage applied to the end electrode during substantially the whole period between injecting the ions through the aperture and the return of the ions to the first end, such that by the time the ions return to the first end for a first time a potential barrier is established by the ramped DC voltage that prevents returning ions from striking the end electrode.

US Pat. No. 11,031,231

MASS SPECTROMETRY IMAGING WITH AUTOMATIC PARAMETER VARYING IN ION SOURCE TO CONTROL CHARGED DROPLET SPRAYING

Micromass UK Limited, Wi...

1. An apparatus comprising:a first ion source arranged and adapted to emit a spray of charged droplets;
a sensor arranged and adapted to measure one or more spatial properties of said spray of charged droplets throughout an acquisition; and
a control system arranged and adapted to control said one or more spatial properties of said spray of charged droplets in use by automatically varying or adjusting one or more parameters of said first ion source, wherein the control system is configured to determine a suitable value of said one or more spatial properties, and adjust or vary said one or more parameters of said first ion source during the acquisition when a value of said one or more spatial properties measured by said sensor differs from the suitable value by a given amount.

US Pat. No. 11,031,230

DATA DIRECTED DESI-MS IMAGING

Micromass UK Limited, Wi...

1. A method of analysing a sample comprising:(i) surveying a sample in a first mode of operation by directing a spray of charged droplets onto said sample when said spray has a first cross-sectional area or first pixel size at a point of impact with said sample and scanning said spray of charged droplets across said sample at a first speed;
(ii) determining one or more regions of interest in said sample; and
(iii) analysing said one or more regions of interest in a second different mode of operation by directing a spray of charged droplets onto said sample when said spray has a second different cross-sectional area or second different pixel size at a point of impact with said sample and scanning said spray of charged droplets across said one or more regions of interest at a second different speed.

US Pat. No. 11,031,229

SAMPLE DESORPTION IONIZATION DEVICE AND ANALYSIS METHOD FOR A MASS SPECTROMETER

SHIMADZU RESEARCH LABORAT...

1. A sample desorption and ionization device, having a first gas pressure region and a second gas pressure region, wherein the gas pressure in the first gas pressure region is higher than the gas pressure in the second gas pressure region; the device comprises:a heating desorption device, disposed in the first gas pressure region, carrying and heating a sample, wherein an analyte in the sample is desorbed from the sample under a heating action and then enters the first gas pressure region;
a vacuum interface component, connected with the first gas pressure region and the second gas pressure region, and causing the analyte to enter the second gas pressure region from the first gas pressure region, which is driven by a gas flow; and
a soft ionization source, wherein the soft ionization source includes one of a glow discharge ionization source, a radiation ionization source and a dielectric barrier discharge ionization source, the soft ionization source converts gas molecules in the second gas pressure region into activated gas molecules, the analyte entering the second gas pressure region interacts with the activated gas molecules and realizes soft ionization, and the gas pressure in the second gas pressure region is 50-350 Pa.

US Pat. No. 11,031,228

MASS SPECTROMETRY DEVICE AND MASS SPECTROMETRY METHOD

HAMAMATSU PHOTONICS K.K.,...

1. A mass spectrometry device comprising:a sample stage on which a thin film-like sample subjected to imaging mass spectrometry is placed and on which a sample support having a substrate, in which a plurality of through-holes passing from one surface thereof to the other surface thereof are provided, and a conductive layer, which is formed of a conductive material and covers at least a portion of the one surface of the substrate where the through-holes are not disposed, is placed such that the other surface of the substrate faces the sample;
a laser beam application unit configured to control application of a laser beam such that the laser beam is applied to an imaging target region on the one surface, the imaging target region being a portion or all of an effective region of the sample support which functions as a region for moving the sample from the other surface to the one surface due to a capillary phenomenon, and being a region that overlaps the sample when viewed in a thickness direction of the substrate; and
a detection unit configured to detect the sample ionized by the application of the laser beam in a state where a positional relation of the sample in the imaging target region is maintained.

US Pat. No. 11,031,227

DISCHARGE CHAMBERS AND IONIZATION DEVICES, METHODS AND SYSTEMS USING THEM

PerkinElmer Health Scienc...

1. A plasma discharge ionization source comprising a discharge chamber comprising a first electrode configured to couple to a power source, wherein the discharge chamber is configured to sustain a plasma discharge within the discharge chamber and comprises at least one inlet configured to receive a plasma gas and at least one outlet configured to provide ionized analyte from the discharge chamber, wherein the at least one inlet is present in a first region of the discharge chamber and the at least one outlet is outside the first region of the discharge chamber, and wherein the at least one inlet is coupled to the at least one outlet through a bend to remove interfering species from the ionized analyte.

US Pat. No. 11,031,226

MASS SPECTROMETER AND MASS SPECTROMETRY

SHIMADZU CORPORATION, Ky...

1. A mass spectrometric method including steps of transporting ions generated in an ion source to a mass spectrometer section through an ion optical system having a plurality of ion lenses, and detecting the ions after performing mass separation of the ions, the mass spectrometric method further comprising steps of:adjusting a voltage applied to a first ion lens which is one of the plurality of ion lenses so that a detection sensitivity for an ion having a predetermined mass-to-charge ratio satisfies a previously specified requirement; and
applying, to a second ion lens which is one of the plurality of ion lenses except the first ion lens, a voltage at which a change in the ion detection sensitivity with respect to the voltage applied to the second ion lens is within a previously specified range.

US Pat. No. 11,031,225

METHODS AND SYSTEMS FOR CONTROLLING ION CONTAMINATION

DH Technologies Developme...

1. A mass spectrometer system, comprising:an ion source housing defining an ionization chamber, the ionization chamber comprising a curtain plate defining a curtain plate aperture through which ions generated in the ionization chamber from a sample can be transmitted to one or more downstream mass analyzers;
an orifice plate defining a sampling orifice, said orifice plate being separated from the curtain plate so as to define a curtain chamber therebetween through which ions from the curtain plate aperture can be transmitted to the sampling orifice;
a power supply electrically coupled to the curtain plate and the orifice plate for providing electrical signals thereto;
a controller operatively coupled to the power supply, said controller configured to control the electrical signals applied to the curtain plate and orifice plate so as to modulate the electric field within the curtain chamber from a first configuration during a first period in which ions are preferentially transmitted through the sampling orifice and a second configuration during a second period in which ions are substantially prevented from being transmitted through the curtain chamber to the sampling orifice;
wherein in the first configuration, the electric field in the curtain chamber is configured to draw ions of a first polarity through the curtain chamber and into the sampling orifice and
wherein in the second configuration, the orifice plate is maintained at least one of at substantially the same DC potential as the curtain plate and at a repulsive potential relative to the potential of the curtain plate for ions generated by the ion source.

US Pat. No. 11,031,224

ION GUIDING DEVICE AND GUIDING METHOD

SHIMADZU CORPORATION, Ky...

1. An ion guiding device, characterized by comprising:a plurality of ring electrodes with a same size disposed in parallel, wherein a connection line of centers of the plurality of ring electrodes is defined as an axis, a normal of a plane where any of the ring electrodes is located and a tangent line of the axis at a center of the ring electrode form a first included angle, and a range of the first included angle is greater than 0 and less than 90 degrees;
a radio-frequency voltage source, for applying an out-phase radio-frequency voltage on a neighboring ring electrode along the axis, so that ions are confined inside the ring electrode during a transmission process; and
a direct-current voltage source, for applying a direct-current voltage with an amplitude changing along the axis on the ring electrode, so that the ions are transmitted along the axis and focused off-axis to an inner surface of the ring electrode and an ions transmission direction and the axis form a second included angle, and a range of the second included angle is greater than 0 and less than 90 degrees.

US Pat. No. 11,031,223

CAPACITIVELY COUPLED REIMS TECHNIQUE AND OPTICALLY TRANSPARENT COUNTER ELECTRODE

Micromass UK Limited, Wi...

1. A method of analysis comprising:providing a sample on an insulating substrate;
contacting said insulating substrate with a first electrode and contacting said sample with a second electrode; and
applying an AC or RF voltage to said first and second electrodes in order to generate an aerosol from said sample.

US Pat. No. 11,031,222

CHEMICALLY GUIDED AMBIENT IONISATION MASS SPECTROMETRY

Micromass UK Limited, Wi...

1. A method comprising:directing light on to a target;
obtaining or acquiring chemical or other non-mass spectrometric data from one or more regions of a target;
wherein said target comprises native or unmodified target material which is unmodified by the addition of a matrix or reagent;
using said chemical or other non-mass spectrometric data to determine one or more regions of interest of said target;
using a first device to generate aerosol, smoke or vapour from the one or more regions of interest of said target, wherein said step of using said first device to generate aerosol, smoke or vapour from one or more regions of said target further comprises irradiating said target with a laser;
causing said aerosol, smoke or vapour to impact upon a collision surface located within a vacuum chamber of a mass spectrometer and/or ion mobility separator so as to generate a plurality of analyte ions;
mass analysing and/or ion mobility analysing said analyte ions derived in order to obtain mass spectrometric data and/or ion mobility data; and
analysing a profile of said aerosol, smoke or vapour or a profile of ions derived from said aerosol, smoke or vapour.

US Pat. No. 11,031,221

IONISATION OF GASEOUS SAMPLES

Micromass UK Limited, Wi...

1. A method of mass spectrometry and/or ion mobility spectrometry comprising:providing an analyte by using a first device to generate aerosol, smoke or vapour from a target to be analysed;
supplying a matrix compound to said aerosol, smoke or vapour such that said analyte is diluted by, dissolved in, or forms first clusters with said matrix; and
colliding said first clusters or first droplets of said diluted or dissolved analyte with a collision surface located within a vacuum chamber of a mass and/or ion mobility spectrometer so as to generate a plurality of analyte ions;
wherein supplying said matrix compound to said aerosol, smoke or vapour comprises introducing said matrix compound to said aerosol, smoke or vapour within a tube connected to an inlet of said vacuum chamber.

US Pat. No. 11,031,220

ION DETECTION SYSTEM

Micromass UK Limited, Wi...

1. An ion detection system comprising:one or more first devices configured to produce secondary electrons in response to incident ions, the one or more first devices comprising a first ion collection region and a second ion collection region, wherein the one or more first devices are configured to produce first secondary electrons in response to one or more ions incident at the first ion collection region and to produce second secondary electrons in response to one or more ions incident at the second ion collection region;
a first output device configured to output a first signal in response to first secondary electrons produced by the one or more first devices;
a second output device configured to output a second signal in response to second secondary electrons produced by the one or more first devices;
a digitiser configured to digitise the first signal to produce a first digitised signal;
a digitiser configured to digitise the second signal to produce a second digitised signal;
processing circuitry configured to determine first intensity and arrival time, mass or mass to charge ratio data from the first digitised signal;
processing circuitry configured to determine second intensity and arrival time, mass or mass to charge ratio data from the second digitised signal; and
processing circuitry configured to combine the first intensity and arrival time, mass or mass to charge ratio data and the second intensity and arrival time, mass or mass to charge ratio data to form a combined data set.

US Pat. No. 11,031,219

SWATH® TO EXTEND DYNAMIC RANGE

DH Technologies Developme...

1. A system for extending the dynamic range of a quantitation calculation of a known compound of interest by combining two or more product ion extracted ion chromatograms (XICs) for the same product ion produced from two or more different precursor ions of the known compound of interest using a data independent acquisition (DIA) method, comprising:(a) a sample introduction device that introduces a sample that includes one or more compounds of interest over time;
(b) an ion source device that ionizes the sample to transform the sample into an ion beam;
(c) a tandem mass spectrometer that divides a precursor ion mass range of interest into a plurality of precursor ion mass selection windows for a DIA method and performs the DIA method on the ion beam by, at each acquisition time of a plurality of acquisition times, for each precursor mass selection window of the plurality of precursor ion mass selection windows, fragmenting precursor ions in the window producing product ions and mass analyzing the product ions produced, producing a plurality of product ion spectra for each window of the plurality of precursor ion mass selection over the plurality of acquisition times; and
(d) a processor in communication with the tandem mass spectrometer that
(d)(i) receives a plurality of product ion spectra for each window of the plurality of precursor ion mass selection windows from the tandem mass spectrometer,
(d)(ii) selects a mass-to-charge ratio (m/z) value for at least one known product ion of a compound of interest of the one or more compounds of interest;
(d)(iii) calculates an XIC for the m/z value from a plurality of product ion spectra for each of two or more different windows of the plurality of precursor ion mass selection windows, producing two or more XICs,
(d)(iv) combines the two or more XICs into a single XIC that has a larger dynamic range and combines the two or more XICs of the two or more different windows of the plurality of precursor ion mass selection windows without determining if the two or more different windows include a known precursor ion of the compound of interest, and
(d)(v) calculates a quantity for the compound of interest using the single XIC.

US Pat. No. 11,031,218

DATA ACQUISITION METHOD IN A MASS SPECTROMETER

SHIMADZU CORPORATION, Ky...

1. A data acquisition method in a mass spectrometer, comprising:a. providing an ion source to generate precursor ions;
b. feeding the precursor ions into a first mass analyzer, wherein the first mass analyzer selects at least one mass window such that the precursor ions located outside the mass window pass through the first mass analyzer and the precursor ions located within the mass window cannot pass through the first mass analyzer;
c. feeding the precursor ions passing through the first mass analyzer into a collision cell for collisional dissociation, to generate product ions;
d. feeding the product ions into a second mass analyzer for mass analysis and recording a spectrum; and
e. repeating Steps b to d, wherein each time when Step b is repeatedly performed, the selected mass window does not overlap with all the mass windows previously selected; and after all the mass windows in a mass range have been selected, the repetition is stopped.

US Pat. No. 11,031,217

MASS CORRECTION

Micromass UK Limited, Wi...

1. A method of mass spectrometry, the method comprising the steps of:providing a library of matrix data, said matrix data comprising one or more mass, mass to charge ratio or drift time values of one or more matrix components as a function of retention time, the matrix components corresponding to endogenous compounds of the sample that give rise to reproducible chromatographic peaks over the retention time range in which analyte components of the sample elute, and wherein the composition of the matrix components is substantially constant regardless of the origin of the sample;
chromatographically separating a sample in an LC or GC chromatograph, said sample containing at least some of said matrix components and one or more analyte components, wherein said matrix components correspond to components of said sample other than said analyte components;
analysing said sample at a plurality of retention times of the LC or GC chromatograph so as to obtain sample data during one or more analytical runs of said sample, said sample data comprising one or more mass, mass to charge ratio or drift time values of one or more sample components as a function of retention time;
calculating one or more error values as a function of retention time based on a comparison between said sample data and said matrix data, said comparison comprising comparing a mass, mass to charge ratio or drift time value of one or more of said matrix components in the sample data with a corresponding mass, mass to charge ratio or drift time value of one or more of said matrix components in the matrix data;
calculating one or more adjustment or correction values of mass, mass to charge ratio or drift time as a function of retention time based on said one or more error values; and
adjusting a mass calibration as a function of retention time using the one or more adjustment or correction values, and using the adjusted mass calibration to correct for mass to charge ratio drift in said sample data;
wherein said step of using the adjusted mass calibration to correct for mass to charge ratio drift in said sample data is performed during a subsequent experimental run of the sample that uses the LC or GC chromatograph.

US Pat. No. 11,031,216

MASS SPECTROMETRY DATA ACQUISITION METHOD

SHIMADZU CORPORATION, Ky...

1. A mass spectrometry data acquisition method comprising the steps of:a. providing at least one ion source for generating ions;
b. said ions being not fragmented or partially fragmented when a collision cell is in a first working mode;
c. recording a mass spectrum of the ions generated in said first working mode as a first fragmenting spectrum;
d. selecting more than one ion from said ions, the more than one ion being distributed in a plurality of discontinuous mass-to-charge ratio channels;
e. said selected more than one ion being at least partially fragmented when the collision cell is in a second working mode;
f. recording a mass spectrum of the ions generated in said second working mode as a second fragmenting spectrum; and
g. repetitively executing the steps b-f for several times, wherein, when the step d is repetitively executed, the ions, which are distributed in the discontinuous mass-to-charge ratio channels, selected in the previous step d are always selected, until the ion intensity of said selected ions is lower than a set threshold,
wherein the number of said mass-to-charge ratio channels for the selected ions is not greater than a set numerical value.

US Pat. No. 11,031,215

VACUUM PUMP PROTECTION AGAINST DEPOSITION BYPRODUCT BUILDUP

Lam Research Corporation,...

1. An apparatus comprising:a plasma etch chamber;
an etch gas delivery system configured to introduce one or more etch gases into the plasma etch chamber; and
a deposition precursor delivery system configured to introduce one or more deposition precursors into the plasma etch chamber; and
a vacuum pump system in fluid communication with the plasma etch chamber, wherein the vacuum pump system comprises:
a first roughing pump;
a second roughing pump in parallel with the first roughing pump, wherein the vacuum pump system is configured to direct the one or more etch gases through the first roughing pump without directing the etch gases through the second roughing pump when the plasma etch chamber is performing etch operations, wherein the vacuum pump system is configured to direct the one or more deposition precursors through the second roughing pump without directing the deposition precursors through the first roughing pump when the plasma etch chamber is performing deposition operations; and
a turbomolecular pump, the turbomolecular pump being in fluid communication with one or both of the first roughing pump and the second roughing pump.

US Pat. No. 11,031,214

BATCH TYPE SUBSTRATE PROCESSING APPARATUS

EUGENE TECHNOLOGY CO., LT...

1. A batch type substrate processing apparatus comprising:a tube configured to provide a processing space in which a plurality of substrates are accommodated;
a partition wall which is separated from the processing space, provides a discharge space in which plasma is generated, and extends in a longitudinal direction of the tube;
a gas supply pipe configured to supply a process gas required for processing the plurality of substrates to the discharge space; and
a plurality of electrodes extending in the longitudinal direction of the tube and configured to generate plasma in the discharge space,
wherein at least one of the plurality of electrodes is disposed outside the partition wall, and at least one of the plurality of electrodes is disposed inside the partition wall.