US Pat. No. 10,971,583

GATE CUT ISOLATION INCLUDING AIR GAP, INTEGRATED CIRCUIT INCLUDING SAME AND RELATED METHOD

GLOBALFOUNDRIES U.S. INC....

1. An integrated circuit (IC), comprising:a plurality of spaced first and second active regions in a substrate;
a first gate extending over the first active region;
a second gate extending over the second active region; and
a gate cut isolation separating the first gate from the second gate, the gate cut isolation including:
a gate cut isolation opening extending into an interlayer dielectric layer, the gate cut isolation opening between the first gate and the second gate,
a liner extending along a bottom portion and sidewalls of the opening, and
a sealing layer over the gate cut isolation opening, the sealing layer closing an upper end of the opening, creating an air gap in the opening, wherein the sealing layer extends into the gate cut isolation opening and through a surface of the interlayer dielectric layer.

US Pat. No. 10,971,582

METHOD FOR FORMING A SUPERJUNCTION TRANSISTOR DEVICE

1. A method, comprising:forming a plurality of semiconductor layers one on top of the other;
implanting dopant atoms of a first doping type into each of the plurality of semiconductor layers, thereby forming a plurality of first implanted regions in each of the plurality of semiconductor layers; and
implanting dopant atoms of a second doping type into each of the plurality of semiconductor layers, thereby forming a plurality of second implanted regions in each of the plurality of semiconductor layers,
wherein each of implanting the dopant atoms of the first doping type and implanting the dopant atoms of the second doping type into each of the plurality of semiconductor layers comprises forming a respective implantation mask on a respective surface of each of the plurality of semiconductor layers,
wherein at least one of forming the first implanted regions and the second implanted regions in at least one of the plurality of semiconductor layers comprises a tilted implantation process,
wherein the tilted implantation process comprises using an implantation vector that is tilted by a tilt angle relative to a normal of the respective horizontal surface of the respective semiconductor layer.

US Pat. No. 10,971,581

SEMICONDUCTOR DEVICE

SOCIONEXT INC., Kanagawa...

1. A semiconductor device comprising:a substrate which includes first fins and second fins;
a first transistor which includes a first impurity region of a first conductivity type and a second impurity region of the first conductivity type, the first impurity region and the second impurity region being formed in the first fins which extend in a first direction in a plan view;
a first guard ring which includes a third impurity region of a second conductivity type which is different from the first conductivity type, the third impurity region being formed in the second fins which extend in the first direction in a plan view, the first guard ring surrounding the first transistor in a plan view;
a first wiring formed on the first guard ring and electrically connected to the third impurity region; and
a ground wiring formed on the first wiring, the ground wiring being electrically connected to the first wiring and the second impurity region,
wherein
the first transistor includes a first part and a second part,
the first part and the second part are arranged in a second direction which is perpendicular to the first direction in a plan view,
the first part of the first transistor is separated by a first distance from the first guard ring in the first direction in a plan view,
the second part of the first transistor is separated by a second distance from the first guard ring in the first direction in a plan view,
the second distance is shorter than the first distance,
the first part is separated from the ground wiring in a plan view, and the second part is overlapped with the ground wiring in a plan view.

US Pat. No. 10,971,580

SILICON CARBIDE SCHOTTKY DIODES WITH TAPERED NEGATIVE CHARGE DENSITY

GRIFFITH UNIVERSITY, Que...

1. A silicon carbide (SiC) Schottky diode comprising:a layer of N-type SiC;
a layer of P-type SiC in contact with the layer of N-type SiC creating a P-N junction; and
an anode in contact with both the layer of N-type SiC and the layer of P-type SiC creating Schottky contacts between the anode and both the layer of N-type SiC and the layer of P-type SiC, wherein an edge of the layer of P-type SiC is electrically active and comprises a slope that is sloping away from the anode to create a tapered negative charge density at the P-N junction.

US Pat. No. 10,971,579

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

INNOSCIENCE (ZHUHAI) TECH...

1. A GaN-based high electron mobility transistor (HEMT) semiconductor device, comprising:a substrate;
a first group III-V layer disposed over the substrate;
a second group III-V layer disposed over the first group III-V layer, wherein the second group III-V layer has a larger bandgap than that of the first group III-V layer;
a doped group III-V layer disposed on the second group III-V layer;
a metal layer disposed on the doped group III-V layer and covering a first portion of a top surface of the doped group III-V layer to form a first contact area, a second portion of the top surface of the doped III-V layer being not covered by the metal layer, the second portion of the top surface of the doped group III-V layer having a larger surface roughness than the first portion of the top surface of the doped group III-V layer;
a first passivation layer disposed on the second group III-V layer, the doped group III-V layer, and the metal layer and covering the second portion of the top surface of the doped group III-V layer;
a second passivation layer conformally disposed over the first passivation layer;
a third passivation layer disposed over the second passivation layer;
a conductor structure disposed on the doped group III-V layer and penetrating the first, second, and third passivation layers to make contact with the doped group III-V layer;
a source contact and a drain contact laterally separated from the doped group III-V layer, wherein the source contact and the drain contact penetrate at least the first passivation layer to make contact with the second group III-V layer;
a first field plate positioned over the third passivation layer;
a fourth passivation layer positioned over the first field plate and over the third passivation layer;
a second field plate positioned over the fourth passivation layer;
a fifth passivation layer positioned over the second field plate and over the fourth passivation layer;
a third field plate positioned over the fifth passivation layer;
a sixth passivation layer positioned over the third field plate and over the fifth passivation layer; and
at least two interconnect structures penetrating at least the third, fourth, fifth and sixth passivation layers to respectively contact the source contact and drain contact.

US Pat. No. 10,971,578

CAPACITIVE ELECTRONIC CHIP COMPONENT

STMicroelectronics (Rouss...

1. A capacitive component comprising:a semiconductor substrate;
a trench in the semiconductor substrate;
a silicon oxide layer vertically in line with the trench;
first and second conductive layers including polysilicon or amorphous silicon, the silicon oxide layer being between and in contact with the first and second conductive layers;
an insulating layer in the trench, wherein the insulating layer lines walls of the trench; and
a polysilicon wall separated from the substrate by the insulating layer.

US Pat. No. 10,971,577

ADJUSTABLE MULTI-TURN MAGNETIC COUPLING DEVICE

Taiwan Semiconductor Manu...

1. An integrated circuit device, comprising:a transformer comprising a first inductor and a second inductor, wherein the first and second inductors each comprises at least one turn; and
a magnetic coupling ring comprising at least two magnetic coupling turns,
wherein the at least two magnetic coupling turns are each disposed to be either surrounding or surrounded by the transformer in a top view to enable magnetic coupling between the magnetic coupling ring and the transformer, wherein the at least two magnetic coupling turns are in at least two different levels with respect to one another, and
wherein the transformer is configured to conduct a first current in a first direction and the magnetic coupling ring is configured to conduct a second current in a second direction opposite the first direction.

US Pat. No. 10,971,576

HIGH RESISTIVITY SOFT MAGNETIC MATERIAL FOR MINIATURIZED POWER CONVERTER

INTERNATIONAL BUSINESS MA...

1. A method for forming an on-chip magnetic structure, the method comprising:activating a magnetic seed layer with palladium, the magnetic seed layer comprising nickel being arranged directly on an adhesion layer arranged directly on a semiconductor substrate, the adhesion layer being a single layer;
adding a lead salt to a plating solution;
electrolessly plating, with the plating solution, a magnetic alloy onto the palladium to form a Pd/CoWP layer; and
annealing the substrate;
wherein the Pd/CoWP layer comprises cobalt in a range from about 80 to about 90 at. % based on the total number of atoms of the magnetic material, tungsten in a range from about 4 to about 9 at. % based on the total number of atoms of the magnetic material, phosphorous in a range from about 7 to about 15 at. % based on the total number of atoms of the magnetic material, and palladium substantially dispersed throughout the magnetic material.

US Pat. No. 10,971,575

DISPLAY DEVICE HAVING DATA LINES SPACED APART FROM EACH OTHER BY DIFFERENT DISTANCES

Samsung Display Co., Ltd....

1. A display device, comprising:a substrate including a display area and a non-display area;
pixels disposed in the display area;
first and second power lines connected to the pixels and disposed in the non-display area;
first and second wires extending from the pixels to the non-display area and disposed on the substrate, the first and second wires crossing the first and second power lines in the non-display area; and
an insulating layer covering the first and second wires,
wherein:
the first wires are disposed on the non-display area spaced apart from the second wires by a first distance and a second distance that is different from the first distance in a region disposed between the first and second power lines.

US Pat. No. 10,971,574

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate including:
a display area,
a non-display area which is adjacent to the display area, and
a groove in the substrate, in the non-display area thereof,
a light emitting element disposed on the substrate in the display area thereof; and
a common voltage transmitting line through which a common voltage is transmitted to the display area, disposed on the substrate in the non-display area thereof,
wherein the common voltage transmitting line overlaps the groove in the substrate.

US Pat. No. 10,971,573

EL DISPLAY PANEL, POWER SUPPLY LINE DRIVE APPARATUS, AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An electroluminescence display device comprising:a plurality of pixel circuits arranged in a matrix form having a plurality of columns and a plurality of rows, each of the pixel circuits including an organic EL element,
a first circuit device and a second circuit device, each configured to drive the pixel circuits,
a plurality of first output lines connected between the first circuit device and the pixel circuits, and
a plurality of second output lines connected between the second circuit device and the pixel circuits,
wherein:
the first circuit device includes a plurality of buffer circuits,
each of the buffer circuits includes a first transistor and a second transistor serially connected between a first line that provides a high potential and a second line that provides a low potential, and configured to selectively output the high potential and the low potential from an output node electrically connected to the first transistor and the second transistor,
the output node of each of the buffer circuits is connected to a corresponding one of the first output lines so as to selectively provide the high potential and the low potential to the pixel circuits belonging to a corresponding one of the rows,
wherein a layout pattern of wirings of the buffer circuits is configured such that:
(i) the first line extends along a first direction,
(ii) the second line extends along the first direction,
(iii) the first transistor and the second transistor in each of the buffer circuits are arranged along the first direction and are arranged between the first line and the second line,
(iv) the first output lines extend along a second direction perpendicular to the first direction, and
(v) the second line and the first output lines intersect in a plan view perspective.

US Pat. No. 10,971,572

FLEXIBLE OLED PANEL FOR LIGHTING DEVICE AND METHOD OF MANUFACTURING SAME

LG Display Co., Ltd., Se...

1. A flexible OLED panel for a lighting device, the panel comprising:a substrate made of a polymer material and having a first light extracting pattern provided on a lower surface thereof;
an auxiliary wiring pattern disposed on the substrate;
a first electrode disposed on the substrate on which the auxiliary wiring pattern is disposed;
a passivation layer disposed on the first electrode, at least on an area on which the auxiliary wiring pattern is disposed;
an OLED light emitting structure disposed on the first electrode on which the passivation layer is disposed;
a second electrode disposed on the OLED light emitting structure; and
an encapsulation layer disposed on the second electrode,
wherein a barrier layer is provided on an upper surface of the substrate,
wherein a second light extracting pattern is provided between the substrate and the barrier layer, and
wherein the first light extracting pattern is a microlens pattern.

US Pat. No. 10,971,571

DISPLAY DEVICE FOR PREVENTING ARCING AND METHOD OF MANUFACTURING THE SAME

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a first substrate where a display area and a non-display area defined, wherein a plurality of pixels are arranged at the display area and the non-display area surrounds the display area;
a dam surrounding the display area and arranged at the non-display area;
an organic light emitting diode provided in the display area;
an encapsulation film disposed on the organic light emitting diode;
a buffer layer disposed on the encapsulation film;
an insulating film disposed on the buffer layer;
a pad area arranged outside the dam and including a pad electrode, wherein the buffer layer and the insulating film extend from the display area to the pad area;
a link line disposed between the dam and the first substrate; and
a touch line provided on the insulating layer between the display area and the pad area, wherein the touch line contacts the pad electrode through a pad contact hole in the pad area.

US Pat. No. 10,971,570

DISPLAY DEVICE AND BRIGHTNESS DETECTION METHOD THEREFOR

BOE Technology Group Co.,...

1. A display device, comprising:a display layer, comprising a plurality of display units, each of the display units comprising a plurality of sub-pixels;
at least one sensor group, disposed on a light emitting side of the display layer, and each comprising a plurality of sensors, wherein an orthographic projection of one of the sensors on the display layer has an overlapping area with an arranging area of one of the display units on the display layer, respective portions, lying in overlapping areas, of the display units corresponding to different sensors in the same sensor group are the same, and the orthographic projection of the one of the sensors on the display layer is overlapped with a part of an arranging area of each of the plurality of sub-pixels comprised in the one of the display units on the display layer; and
a processor, coupled to each of the sensors,
wherein the plurality of sensors in the same sensor group are configured to, when corresponding display units display same image data, respectively detect actual brightness data of the respective display unit corresponding to each of the sensors, and transmit a plurality of actual brightness data to the processor, and
the processor is configured to receive the actual brightness data transmitted by each of the sensors, and when the actual brightness data does not coincide with target brightness data, determine brightness compensation data of the display unit to which the actual brightness data belongs according to a difference between the actual brightness data and the target brightness data.

US Pat. No. 10,971,569

DISPLAY APPARATUS

Sony Corporation, Tokyo ...

1. A display apparatus comprising:a laminated structure formed on a substrate, the laminated structure including a semiconductor layer, a lower conductive layer, an intermediate conductive layer and an upper conductive layer,
wherein:
a first part of the intermediate conductive layer is connected to a first conductive member via a first contact hole, the first conductive member being a first portion of the semiconductor layer,
a second conductive member is connected to the first part of the intermediate conductive layer via a second contact hole, the second conductive member being a first portion of the upper conductive layer, and the second contact hole at least partially overlapping the first contact hole in a plan view,
a second portion of the semiconductor layer corresponds to a first electrode of a capacitor, the capacitor being configured to store a voltage corresponding to an image signal,
a portion of the lower conductive layer corresponds to a gate electrode of a sampling transistor, the sampling transistor being configured to sample the image signal, and
a second portion of the upper conductive layer corresponds to an anode electrode of a light emitting element.

US Pat. No. 10,971,568

DISPLAY DEVICE

AU OPTRONICS CORPORATION,...

1. A display device, comprising:a first display panel having a first display area, and the first display area having a plurality of first sub-pixel regions;
a second display panel having a second display area, and the second display area having a plurality of second sub-pixel regions, wherein the second display panel is movable to at least partially overlap the first display panel;
at least one detection device disposed on at least one of the first display panel and the second display panel to detect a position of the other one and generate a relative position detection signal correspondingly; and
a control module electrically connected to the detection device, the control module receiving the relative position detection signal and an image display signal from an image signal source, so as to generate a first display signal and a second display signal to respectively output to the first display panel and the second display panel,
wherein the first display panel further comprises a first polarizing layer, and the second display panel further comprises a second polarizing layer, wherein a polarization direction of the first polarizing layer is substantially orthogonal to that of the second polarizing layer,
wherein the first display area comprises:
a first area; and
a first overlap area connected to the first area; and
the second display area comprises:
a second overlap area overlapping the first overlap area,
wherein the first polarizing layer merely located in the first overlap area; and
the second polarizing layer merely located in the second overlap area.

US Pat. No. 10,971,567

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a display area including a plurality of pixels, and a peripheral area positioned outside the display area and including a bending area;
a first conductive layer comprising a first signal wire over the substrate;
a first insulating layer over the first conductive layer;
a second insulating layer in a different layer from the first insulating layer, overlapping the bending area in a plan view, and having a first edge positioned around the bending area; and
a second conductive layer over the second insulating layer, the second conductive layer comprising a second signal wire that comprises a portion in the bending area,
wherein the first signal wire is in the peripheral area, crosses the first edge of the second insulating layer in the plan view, does not overlap the bending area, and comprises a first portion that does not overlap the second insulating layer in the plan view,
wherein the second conductive layer comprises a second portion that overlaps at least a portion of the first portion, and has an edge that is parallel with an edge of the first portion in the plan view, and
wherein a width of the second portion in a first direction is greater than a width of the first portion in the first direction.

US Pat. No. 10,971,566

DISPLAY DEVICE INCLUDING FRAME WIRING IN BENDING SECTION

SHARP KABUSHIKI KAISHA, ...

1. A display device comprising:a resin substrate;
a light-emitting element included in a display region, the light-emitting element being provided over the resin substrate with a TFT layer in between;
a frame region provided around the display region;
a terminal section provided at an end portion of the frame region;
a bending section provided between the display region and the terminal section;
a frame wiring line provided in the frame region, the frame wiring line extending to the terminal section and being electrically connected, via the TFT layer, to the light-emitting element; and
at least one inorganic insulating film provided in the frame region, the at least one inorganic insulating film being overlaid on the resin substrate and being included in the TFT layer, wherein
at the bending section, an opening portion is formed through the at least one inorganic insulating film to expose an upper surface of the resin substrate,
the frame wiring line is provided, on the resin substrate exposed through the opening portion and on an end portion of the inorganic insulating films through which the opening portion is formed, to extend across the opening portion,
among the at least one inorganic insulating film, an inorganic insulating film being in contact with the upper surface of the resin substrate is formed with a silicon oxynitride film,
among the at least one inorganic insulating film, an inorganic insulating film being in contact with the upper surface of the resin substrate is a lowermost layer of a base coat film provided on the resin substrate, and
the base coat film includes a first layer formed with a silicon oxynitride film, a second layer formed with a silicon nitride film, and a third layer formed with a silicon oxide film, which are provided in an order stated over the resin substrate.

US Pat. No. 10,971,565

PIXEL STRUCTURE

Au Optronics Corporation,...

1. A pixel structure, comprising:a substrate;
a thin film transistor, disposed on the substrate and comprising a first end, a second end and a control end;
a first signal line, electrically connected to the first end of the thin film transistor;
a second signal line, electrically connected to the control end of the thin file transistor;
a pixel electrode, electrically connected to the second end of the thin film transistor, wherein the first end of the thin film transistor, the second end of the thin film transistor and the first signal line are formed of a first conductive layer; and
a first light shielding layer, disposed on a top surface of the first conductive layer and a sidewall of the first conductive layer, wherein the first light shielding layer comprises a first photoresist and first particles mixed within the first photoresist,
wherein the first light shielding layer comprises:
a first light shielding pattern, disposed on a top surface of the first end of the thin film transistor and a sidewall of the first end of the thin film transistor; and
a second light shielding pattern, disposed on a top surface of the second end of the thin film transistor and a sidewall of the second end of the thin film transistor,
wherein a first gap is provided between the first light shielding pattern and the second light shielding pattern, a second gap is provided between the first end of the thin film transistor and the second end of the thin film transistor, and the first gap is located within the second gap.

US Pat. No. 10,971,564

DISPLAY PANEL, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

CHENGDU BOE OPTOELECTRONI...

1. A display panel, comprising:a base substrate, comprising a display region and a border region surrounding the display region, the border region comprising a specially-shaped border region;
a first barrier structure configured to be disposed in at least the specially-shaped border region;
at least one second barrier structure configured to be disposed only in the specially-shaped border region; and
a first film layer located in the specially-shaped border region of the base substrate, the first barrier structure being located above the first film layer, the at least one second barrier structure comprising a first raised layer located below the first film layer, the first raised layer being configured such that a portion of the first film layer thereon protrudes in a direction away from the base substrate.

US Pat. No. 10,971,563

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a substrate;
an organic light-emitting device on the substrate;
a sealing member on the organic light-emitting device;
a phase retardation layer on a surface of the organic light emitting device; and
a linear polarization layer on a surface of the sealing member,
wherein the linear polarization layer is located to be closer to a source of external light than the phase retardation layer, and
wherein the linear polarization layer comprises a photochromic material.

US Pat. No. 10,971,562

DISPLAY APPARATUS WITH TOUCH SENSOR HAVING SHIELD LAYER BETWEEN TOUCH SENSOR LINE AND DRIVING LINE

LG Display Co., Ltd., Se...

1. A display apparatus, comprising:a substrate including an active area and a non-active area;
a plurality of data lines and a plurality of gate lines on the substrate;
a driving line in the non-active area configured to transfer a display driving signal to the active area;
a plurality of pixels electrically connected to the plurality of data lines and the plurality of gate lines, each pixel including:
a light emitting diode having an anode, a light emitting layer, and a cathode, and a driving transistor configured to drive the light emitting diode, wherein the driving line is under the cathode in the non-active area;
a shield layer between the cathode and the driving line;
an encapsulation layer on the cathode;
a touch electrode on the encapsulation layer in the active area, the encapsulation layer having a sloped surface;
a first power line in the non-active area electrically connected to the cathode and comprising a same material as the anode;
a second power line disposed in a same material layer as a source/drain electrode of the driving transistor and electrically connected to the first power line;
a third power line disposed in a same material layer as a gate of the driving transistor;
a touch line on the encapsulation layer in the non-active area and configured to supply a touch signal to the touch electrode, and
a plurality of pads in the non-active area,
wherein at least one pad of the plurality of pads is electrically connected to the touch electrode via the touch line,
wherein the driving line is below the touch line in the non-active area,
wherein the touch line is on the sloped surface of the encapsulation layer, thereby having a corresponding slope,
wherein the shield layer is spaced apart from the first power line in a same material layer as the first power line,
wherein the driving line is spaced apart from the third power line in a same material layer as the third power line, and
wherein the plurality of pads have a first pad electrode disposed in a same material layer as the second power line, and a second pad electrode disposed on the first pad electrode and in a same material layer as the touch electrode.

US Pat. No. 10,971,561

OLED DISPLAY PANEL AND DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

10. A display device, comprising a driver unit and an OLED display panel whose driver signals are provided by the driver unit; wherein the OLED display panel comprises an array substrate, an encapsulation cover, and an organic lighting unit sealed between the array substrate and the encapsulation cover by encapsulation adhesive;a chip bonding element is configured on the array substrate;
the encapsulation cover is configured with a touch electrode layer and a plurality of first connection electrodes;
the first connection electrodes are aligned at intervals in two rows;
the organic lighting unit comprises a pixel definition layer;
a plurality of insulating support columns are disposed on the pixel definition layer;
a plurality of second connection electrodes are disposed respectively on the support columns;
each second connection electrode is electrically connected to the chip bonding element;
the support columns contact with the first connection electrodes;
the touch electrode layer comprises a plurality of touch electrodes, each connected to at least a first connection electrode through a touch signal wire;
each first connection electrode is electrically connected to a second connection electrode so that each touch electrode is electrically connected to the chip bonding element; and
a same numbers of support columns and second connection electrodes as that of the first connection electrodes are configured on the pixel definition layer;
wherein each touch electrode is connected through a signal wire to a first connection electrode in a row and another first connection electrode in another row.

US Pat. No. 10,971,560

DISPLAY DEVICE, APPARATUS AND METHOD FOR TESTING DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

11. An apparatus for testing a display device, the apparatus comprising:a test circuit film connected to a first substrate having a display area and a non-display area defined thereon, wherein the non-display area is on an outer side of the display area, and the first substrate includes a first dummy thin-film transistor in the non-display area and a plurality of test pads connected to the first dummy thin-film transistor;
connection pads on a side of the test circuit film and electrically connected to the test pads, respectively; and
a meter connected to the test circuit film, wherein
a bending area is defined that at least partially traverses the display area and the non-display area,
the first dummy thin-film transistor overlaps the bending area, and
the meter checks influence on the first dummy thin-film transistor when the bending area is bent.

US Pat. No. 10,971,559

DISPLAY DEVICE

FUNAI ELECTRIC CO., LTD.,...

1. A display device, comprising:color filters, which comprise red color filters, blue color filters, first green color filters used for a first green, and second green color filters used for a second green having a hue closer to a blue side than the first green; and
a display portion, in which the color filters are disposed,
wherein first groups and second groups are disposed to line up regularly with each other in the display portion,
each of the first groups comprises one red color filter, one blue color filter, one white color filter and one first green color filter,
each of the second groups comprises one red color filter, one blue color filter, one white color filter and one second green color filter, and
the second group is equal to the first group in number of the color filters, and different from the first group in a color filter combination in which the first green color filter and the second color filter are for transmitting different green light.

US Pat. No. 10,971,558

ORGANIC LIGHT EMITTING DIODE DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting diode display device, comprising:a substrate having an emitting area and a non-emitting area;
an overcoating layer on the substrate and including a convex portion and a concave portion, the convex portion including a top surface portion and a side surface portion between the concave portion and the top surface portion, the side surface portion being in a first emission region having a first emission spectrum, the concave portion being in a second emission region having a second emission spectrum different from the first emission spectrum;
a first electrode on the overcoating layer;
a light emitting layer on the first electrode; and
a second electrode on the light emitting layer,
wherein the first emission spectrum includes three peaks corresponding to wavelengths of a red light, a green light, and a blue light, respectively, and the second emission spectrum includes one peak corresponding to one of the wavelengths of the red light, the green light, and the blue light, or two peaks corresponding to two of the wavelengths of the red light, the green light, and the blue light, respectively.

US Pat. No. 10,971,557

DISPLAY DEVICE HAVING COLOR FILTER WITH SCATTERING AGENT

Samsung Display Co., Ltd....

1. A display device comprising:a display panel including an organic electroluminescent element; and
a color filter on the display panel,
wherein the color filter comprises:
a first color filter portion configured to transmit red light; and
a second color filter portion configured to transmit green light,
wherein the first color filter portion and the second color filter portion comprise a scattering agent having an average diameter of 50 nanometers (nm) or more and 500 nm or less,
wherein a first content of the scattering agent included in the first color filter portion is greater than a second content of the scattering agent included in the second color filter portion.

US Pat. No. 10,971,556

ORGANIC LIGHT-EMITTING DISPLAY PANEL AND ORGANIC LIGHT-EMITTING DISPLAY DEVICE

SHANGHAI TIANMA AM-OLED C...

1. An organic light-emitting display panel, the organic light-emitting display panel having a display area, wherein the organic light-emitting display panel comprises:a plurality of pixel rows disposed sequentially along a first direction in the display area, wherein each pixel row of the plurality of pixel rows comprises a plurality of pixel sets arranged along a second direction, wherein the second direction intersects the first direction; wherein each pixel set of the plurality of pixel sets comprises a first pixel and a second pixel arranged along the second direction; and
a plurality of high voltage signal lines extending along the first direction,
wherein the first pixel comprises a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting different colors, and the second pixel comprises a fourth sub-pixel, a fifth sub-pixel, and a sixth sub-pixel emitting different colors;
wherein each of the first to sixth sub-pixels comprises a pixel driving circuit and an organic light-emitting diode;
wherein the plurality of high voltage signal lines is electrically connected to the first to sixth sub-pixels, so as to provide voltage signals to anodes of the organic light-emitting diodes of the first to sixth sub-pixels for driving said first to sixth sub-pixels to emit light, wherein the plurality of high voltage signal lines comprises a third high voltage signal line;
wherein the third sub-pixel and the fourth sub-pixel in a same said pixel set are electrically connected to a same third high voltage signal line and emit a same color.

US Pat. No. 10,971,555

PIXEL STRUCTURE AND DISPLAY APPARATUS

KUNSHAN GO-VISIONOX OPTO-...

1. A pixel structure, comprising:a plurality of repeated units arranged in an array, each repeated unit comprising one sub-pixel of a first color, two sub-pixels of a second color, and two sub-pixels of a third color, wherein all sub-pixels in each repeated unit are arranged along a first direction;
wherein, the first color, the second color, and the third color are different from one another, and each side of the sub-pixel of the first color is arranged with one of the sub-pixels of the second color and one of the sub-pixels of the third color, along the first direction,
wherein a center of a Nth sub-pixel in each repeated unit is arranged in alignment with a center of a N+1th sub-pixel in adjacent repeated unit in a second direction, N being a positive integer,
wherein among the sub-pixel of the first color, sub-pixels of the second color, and sub-pixels of the third color, sub-pixels with a maximum brightness is separated into two secondary sub-pixels along the second direction perpendicular to the first direction, and
wherein the sub-pixel with the maximum brightness is the sub-pixel of the second color, and the sub-pixel of the second color is separated into two secondary sub-pixels, the sub-pixel of the first color is shared by the sub-pixel of the second color and the sub-pixel of the third color on each side of the sub-pixel of the first color to form two pixel unit groups, and in each of the pixel unit groups, the sub-pixel of the first color and the sub-pixels of the third color form one pixel unit with each of the two secondary sub-pixels separated from the sub-pixel of the second color.

US Pat. No. 10,971,554

ORGANIC LIGHT-EMITTING DEVICE

Samsung Display Co., Ltd....

1. An organic light-emitting device, comprising:a first electrode;
a second electrode facing the first electrode;
an emission layer between the first electrode and the second electrode;
a hole control layer between the first electrode and the emission layer;
an electron control layer between the emission layer and the second electrode; and
a capping layer on the second electrode,
wherein the emission layer includes a first sub-emission layer, a second sub-emission layer, and a third sub-emission layer,
wherein at least one of the first to the third sub-emission layers includes a hole-transporting host, an electron-transporting host, and a light-emitting dopant,
wherein the hole-transporting host and the electron-transporting host form an exciplex, and
wherein the light-emitting dopant emits phosphorescent light and thermally activated delayed fluorescence light.

US Pat. No. 10,971,553

OPTICAL STACK FOR IMPROVED COLOR UNIFORMITY IN OLED DISPLAY

3M INNOVATIVE PROPERTIES ...

1. An optical stack comprising first and second layers and a nanostructured interface therebetween, the first layer having a first refractive index, the second layer having a different second refractive index being at least 1.4, the nanostructured interface having a substantially azimuthally symmetric power spectral density (PSD), a wavenumber-PSD product having a maximum for a wavenumber larger than 6 radians/micrometer times the second refractive index, wherein for all wavenumbers less than 6 radians/micrometer times the second refractive index, the wavenumber-PSD product is no more than 0.3 times the maximum, andwherein the optical stack is configured to be disposed on an encapsulated emissive layer of an organic light emitting diode (OLED) display with the second layer disposed between the first layer and the encapsulated emissive layer and with the nanostructured interface proximate to, and outside of, an evanescent zone of the encapsulated emissive layer to reduce a variation in color with view angle of light emitted from the OLED display.

US Pat. No. 10,971,552

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device, comprising:a display module comprising a display panel and a window substrate on the display panel, the display panel comprising a circuit layer comprising a plurality of transistors, a light emitting device layer on the circuit layer and comprising a plurality of light-emitting devices, and an encapsulation layer encapsulating the light emitting device layer; and
a cushion layer below the display module, a pattern comprising a vibration attenuating line extending in a second direction from an edge of the cushion layer to another edge of the cushion layer and an auxiliary vibration attenuating line crossing the vibration attenuating line and extending in a first direction from an edge of the cushion layer to another edge of the cushion layer, the vibration attenuating line and the auxiliary vibration attenuating line being defined by the cushion layer,
wherein the vibration attenuating line is spaced apart from a reference edge of the cushion layer by a first length, and
wherein the first length is a value obtained by dividing a sound speed in the display module by a natural frequency of the display module.

US Pat. No. 10,971,551

ORGANIC LIGHT-EMITTING DIODE DISPLAY PANEL AND MANUFACTURING METHOD THEREFOR, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A manufacturing method of an organic light-emitting diode display panel, comprising:forming patterns of an anode and an auxiliary electrode on a base substrate, wherein the anode and the auxiliary electrode are insulated from each other;
forming a pattern of a pixel definition layer on the anode and the auxiliary electrode, wherein the pixel definition layer includes a pixel opening region exposing the anode and a via exposing a surface of the auxiliary electrode; and
forming a pattern of a luminescent layer and a pattern of a cathode sequentially on the pixel definition layer, wherein the cathode is electrically connected to the auxiliary electrode arranged in the via,
wherein the via comprises a first oblique surface and a second oblique surface facing each other, the first oblique surface forms a first acute angle with respect to the surface of the auxiliary electrode exposed by the via, and the second oblique surface forms a second acute angle with respect to the surface of the auxiliary electrode exposed by the via,
wherein forming a pattern of a pixel definition layer on the anode and the auxiliary electrode is performed by a single-step patterning process, and comprises:
forming the pixel definition layer on the patterns of the anode and the auxiliary electrode;
performing an exposure process on the pixel definition layer by light with a first oblique angle and light with a second oblique angle, respectively, so that the pixel definition layer forms a pattern of the pixel opening region exposing the anode and the via exposing the surface of the auxiliary electrode, wherein the pixel opening region makes an obtuse angle between an edge of the pixel definition layer and anode, the first oblique surface of the via forms the first acute angle with respect to the surface of the auxiliary electrode exposed by the via, and the second oblique surface of the via forms the second acute angle with respect to the surface of the auxiliary electrode exposed by the via.

US Pat. No. 10,971,550

PHOTODIODE ARRAYS

Flexenable Limited, Camb...

1. A method comprising:forming on a support film a first stack of layers defining an array of photodiodes, wherein forming the first stack of layers comprises: i) depositing an organic semiconductor material over a first electrode, and ii) forming pixel electrodes over the organic semiconductor material, wherein forming the pixel electrodes comprises (a) depositing a continuous layer of organic conductor material over the organic semiconductor material, (b) depositing a continuous layer of reflective conductor material over the continuous layer of organic conductor material, (c) patterning the continuous layer of reflective conductor material to produce a reflective conductor material pattern, and (d) thereafter patterning the continuous layer of organic conductor material using the reflective conductor material pattern as a mask to produce an organic conductor material pattern having edges substantially aligned with edges of the reflective conductor pattern in the region of each pixel electrode; and
forming over the first stack of layers in situ on the support film a second stack of layers defining electrical circuitry by which the photoresponse of each photodiode is independently detectable via an array of conductors outside the array of photodiodes, wherein the electrical circuitry comprises transistors including photosensitive semiconductor channels, and the pixel electrodes also function to substantially block the incidence of light on the photosensitive semiconductor channels from the direction of the support film.

US Pat. No. 10,971,549

SEMICONDUCTOR MEMORY DEVICE HAVING A VERTICAL ACTIVE REGION

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor memory device, the method comprising:selectively etching a plurality bottom electrode regions extending in a y-direction relative to a top surface of a substrate;
depositing a bottom electrode in each of the bottom electrode regions;
depositing a cap layer onto a top surface of the bottom electrode;
patterning a plurality of orthogonal mask regions extending in an x-direction relative to the top surface of the substrate, orthogonal to the bottom electrode regions, wherein the plurality of orthogonal mask regions forms a plurality of unprotected areas of the substrate;
selectively etching the plurality of unprotected areas of the substrate to form an etched surface to a depth below a bottom surface of the bottom electrode;
depositing an insulating layer on the etched surface;
depositing a top electrode on the insulating layer to form a metal surface; and
planarizing the metal surface to expose an upper surface of the plurality of the orthogonal mask regions;
wherein an active area between the top electrode and the bottom electrode is located on a vertical side wall extending in a z-direction relative to the top surface of the substrate of the semiconductor memory device;
wherein a bottom surface of the top electrode contacts the insulating layer on the etched surface below the bottom surface of the bottom electrode.

US Pat. No. 10,971,548

VARIABLE RESISTANCE MEMORY DEVICE INCLUDING SYMMETRICAL MEMORY CELL ARRANGEMENTS AND METHOD OF FORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A variable resistance non-volatile memory device comprising:a semiconductor substrate;
a plurality of first conductive lines extending in a first direction perpendicular to the semiconductor substrate and spaced apart in a second direction on the semiconductor substrate;
a second conductive line extending in the second direction parallel to the semiconductor substrate on a first side of the plurality of first conductive lines;
a third conductive line extending in the second direction parallel to the semiconductor substrate on a second side of the plurality of first conductive lines opposite to the first side of the plurality of first conductive lines;
a plurality of first non-volatile memory cells on the first side of the plurality of first conductive lines and each coupled to the second conductive line and to a respective one of the plurality of first conductive lines, wherein each of the plurality of first non-volatile memory cells includes a first variable resistance element, a first electrode, and a first switching element;
a plurality of second non-volatile memory cells on the second side of the plurality of first conductive lines and each coupled to the third conductive line and to the respective one of the plurality of first conductive lines, wherein each of the plurality of second non-volatile memory cells includes a second variable resistance element, a second electrode, and a second switching element; and
a plurality of filling insulation patterns between the plurality of first conductive lines, the plurality of filling insulation patterns extending in the first direction,
wherein the plurality of first conductive lines and the plurality of filling insulation patterns are alternatively arranged in the second direction, and the plurality of filling insulation patterns extend between the plurality of first non-volatile memory cells and between the plurality of second non-volatile memory cells in a third direction that is parallel to the semiconductor substrate and cross the second direction.

US Pat. No. 10,971,547

SWITCH ELEMENT, SWITCHING METHOD AND SEMICONDUCTOR DEVICE

NANOBRIDGE SEMICONDUCTOR,...

1. A switch element, including:a resistance change element including a metal deposition type resistance change film, a first electrode that is connected to one surface of the resistance change film and supplies a metal ion to the resistance change film, and a second electrode that is connected to another surface of the resistance change film;
a first transistor of which a drain or a source is connected to the first electrode; and
a second transistor of which a source or a drain is connected to the second electrode,
wherein, when switching the resistance change element from a low-resistive state to a high-resistive state by the first transistor and the second transistor making a potential of the second electrode higher than a potential of the first electrode,
the switch element switches by having
a first mode in which a gate voltage of the first transistor or the second transistor is defined as a first gate voltage, and a potential difference between the first electrode and the second electrode is defined as a first potential difference, and
a second mode in which a gate voltage of the first transistor or the second transistor is defined as a second gate voltage, and a potential difference between the first electrode and the second electrode is defined as a second potential difference, and
the first gate voltage is set larger than the second gate voltage, and the first potential difference is set smaller than the second potential difference.

US Pat. No. 10,971,546

CROSSPOINT PHASE CHANGE MEMORY WITH CRYSTALLIZED SILICON DIODE ACCESS DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of fabricating an access device in a crosspoint memory array structure during back end of line (BEOL) processing of the crosspoint memory array structure, the method comprising:forming at least a first doped semiconductor layer on an upper surface of a first conductive layer, the first doped semiconductor layer being in electrical connection with the first conductive layer;
exposing at least a portion of the first doped semiconductor layer to a directed energy source, the directed energy source causing localized annealing in the first doped semiconductor layer to activate a dopant of a first conductivity type in the first doped semiconductor layer and to convert at least a portion of the first doped semiconductor layer into a first polycrystalline layer;
subsequent to exposing at least a portion of the first doped semiconductor layer to the directed energy source, forming a second doped semiconductor layer on at least a portion of an upper surface of the first polycrystalline layer;
exposing at least a portion of the second doped semiconductor layer to the directed energy source, the directed energy source causing localized annealing in the second doped semiconductor layer to thereby activate a dopant of a second conductivity type, opposite the first conductivity type, in the second doped semiconductor layer and to convert at least a portion of the second doped semiconductor layer into a second polycrystalline layer;
forming a second conductive layer over a least a portion of the first and second doped semiconductor layers; and
etching the first and second doped semiconductor layers and the first and second conductive layers using a same mask pattern to form an access device that is self-aligned with the first and second conductive layers.

US Pat. No. 10,971,545

MAGNETORESISTIVE STACKS AND METHODS THEREFOR

Everspin Technologies, In...

1. A magnetoresistive device, comprising:multiple magnetic tunnel junction (MTJ) stacks separated from each other by one or more dielectric material layers, wherein each MTJ stack includes multiple MTJ bits arranged one on top of another;
electrically conductive vias extending through the one more dielectric material layers, wherein the electrically conductive vias are configured to (a) access each MTJ bit of the multiple MTJ stacks individually, and (b) access an MTJ bit of the multiple MTJ stacks in series with another MTJ bit of the multiple MTJ stacks;
a first electrically conductive via, of the electrically conductive vias, comprising a section in a horizontal direction that is connected to a first side of a first MTJ bit at a first depth;
a second electrically conductive via, of the electrically conductive vias, comprising a section in a horizontal direction that is connected to a second side of the first MTJ bit at a second depth;
a third electrically conductive via, of the electrically conductive vias, comprising a section in a horizontal direction that is connected to the first side of a second MTJ bit at a third depth; and
a fourth electrically conductive via, of the electrically conductive vias, comprising a section in a horizontal direction that is connected to the second side of the second MTJ bit at a fourth depth,
wherein the first side is opposite to the second side, and
wherein the first depth is higher than the second depth, the second depth is higher than the third depth, and the third depth is higher than the fourth depth.

US Pat. No. 10,971,544

INTEGRATION OF MAGNETO-RESISTIVE RANDOM ACCESS MEMORY AND CAPACITOR

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a magneto-resistive memory device and a capacitor in an interconnect structure, wherein the magneto-resistive memory device is disposed in a first region of the interconnect structure and the capacitor is disposed in a second region of the interconnect structure, the method comprising:forming a first level interconnect metal layer of the interconnect structure;
simultaneously forming a first plurality of layers in the first region of the interconnect structure over the first level interconnect metal layer and a second plurality of layers in the second region of the interconnect structure over the first level interconnect metal layer, wherein the first plurality of layers is a portion of the magneto-resistive memory device and the second plurality of layers is a portion of the capacitor, wherein the forming the first plurality of layers in the first region and the second plurality of layers in the second region includes:
depositing a first dielectric layer on the first level interconnect metal layer in the first region and the second region,
depositing a first metal layer on the first dielectric layer in the first region and the second region,
forming an MTJ stack on the first metal layer in the first region,
depositing a second dielectric layer on the first metal layer in the first region and the second region, wherein the second dielectric layer directly contacts an entire top surface of the first metal layer in the second region,
depositing a second metal layer on the second dielectric layer in the first region and the second region, wherein the second metal layer is disposed directly on and covers an entirety of a top surface of the MTJ stack, an entirety of a top surface of the second dielectric layer in the first region, and an entirety of a top surface of the second dielectric layer in the second region, and
after the depositing the first metal layer, the forming the MTJ stack, the depositing the second dielectric layer, and the depositing the second metal layer, etching the second metal layer, the second dielectric layer, and the first metal layer, such that:
the first plurality of layers includes the MTJ stack disposed between a first etched portion of the second metal layer and a first etched portion of the first metal layer, wherein a first etched portion of the second dielectric layer is disposed between the first etched portion of the second metal layer and the first etched portion of the first metal layer; and
the second plurality of layers includes a second etched portion of the second dielectric layer disposed between a second etched portion of the second metal layer and a second etched portion of the first metal layer; and
forming a second level interconnect metal layer of the interconnect structure over the first plurality of layers and the second plurality of layers.

US Pat. No. 10,971,543

DISPLAY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A display device comprising:a substrate;
an emissive layer provided on the substrate and configured to emit light;
a plurality of color converting layers provided on the emissive layer, each of the plurality of color converting layers being arranged on a portion of the emissive layer and configured to convert the emitted by the emissive layer into different color lights;
at least one barrier arranged on the emissive layer between the plurality of color converting layers to spatially separate the plurality of color converting layers from each other;
a first insulating layer provided between the plurality of color converting layers and the emissive layer, the first insulating layer comprising a plurality of first openings respectively corresponding to the plurality of color converting layers;
a second insulating layer provided between the first insulating layer and the plurality of color converting layers; and
a plurality of first electrodes provided on the emissive layer, each of the plurality of first electrodes respectively in contact with the emissive layer through one of the plurality of first openings,
wherein at least one of the plurality of first electrodes comprises a transparent electrode, and
wherein one of the plurality of first electrodes extends along an upper surface of the first insulating layer.

US Pat. No. 10,971,542

METHOD OF FORMING A SEMICONDUCTOR DEVICE

The Regents of the Univer...

1. A method of forming an electrical circuit structure comprising:providing a first circuit layer including a plurality of first contacts;
constructing a second circuit layer with the steps of:
positioning one or more semiconductor devices on a second substrate;
positioning a plurality of third contacts on the semiconductor devices;
stamping the third contacts to at least one interconnect line;
removing the second substrate; and
positioning a plurality of second contacts on the opposite side of the semiconductor devices from the third contacts;
positioning the second circuit layer on a stamp; and
bonding the plurality of second contacts to the plurality of first contacts via a pressure applied by the stamp.

US Pat. No. 10,971,541

DETECTOR ARCHITECTURE USING PHOTODETECTOR ARRAYS ON THINNED SUBSTRATES

Varex Imaging Corporation...

1. A method, comprising:attaching a carrier substrate to a side of at least one semiconductor substrate, the at least one semiconductor substrate including photodetectors on the side;
thinning the at least one semiconductor substrate while the at least one semiconductor substrate is attached to the carrier substrate;
attaching an optical substrate to the at least one semiconductor substrate while the at least one semiconductor substrate is attached to the carrier substrate;
removing the carrier substrate from the at least one semiconductor substrate; and
attaching at least one semiconductor device to the side of the at least one semiconductor substrate after removing the carrier substrate from the at least one semiconductor substrate.

US Pat. No. 10,971,540

METHOD AND SYSTEMS FOR COUPLING SEMICONDUCTOR SUBSTRATES

FLIR SYSTEMS, INC., Wils...

1. A method, comprising:providing a substrate having a plurality of contacts on a surface of the substrate and a plurality of alignment marks on the surface;
forming, in an evaporative process, a layer of conductive material on the surface;
lifting off parts of the layer of conductive material that are formed over the alignment marks to uncover the alignment marks;
depositing a layer of photoresist over the alignment marks and the layer of conductive material;
patterning, using the alignment marks while the layer of photoresist is present over the alignment marks, the layer of photoresist so that portions of the layer of photoresist remain on corresponding portions of the layer of conductive material that are on the contacts; and
etching, using an inductively coupled plasma (ICP) etch process, uncovered portions of the layer of conductive material so that remaining portions of the layer of conductive material form conductive bumps on the contacts.

US Pat. No. 10,971,539

SOLID-STATE IMAGING DEVICE, METHOD OF DRIVING SOLID-STATE IMAGING DEVICE, IMAGING SYSTEM, AND MOVABLE OBJECT

CANON KABUSHIKI KAISHA, ...

1. A photoelectric conversion device comprising:a photon detector that operates in a Geiger mode and outputs an output signal in accordance with incidence of a photon;
a quench transistor that causes the photon detector to transition to a non- Geiger mode;
a control circuit that supplies a control signal to a gate of the quench transistor and, when the photon detector transitions from a Geiger mode to a non-Geiger mode, switches the quench transistor from a detection mode, in which the quench transistor is in a relatively low resistance state and the photon detector detects a photon, to a hold mode, in which the quench transistor is in a relatively high resistance state and holds the output signal; and
a signal processing circuit that performs a predetermined process on the output signal,
wherein the control circuit determines a period of the hold mode from an exposure condition.

US Pat. No. 10,971,538

PIN DIODE STRUCTURE HAVING SURFACE CHARGE SUPPRESSION

Raytheon Company, Waltha...

1. A method for fabricating an array of photon detectors, comprising:(A) providing a first doped layer on an upper surface of a body, the first doped layer having a first type doped conductivity;
(B) forming a gate structure for the array of photon detectors on a bottom surface of the body, comprising:
(1) forming an insulating layer over the bottom surface of the body;
(2) forming a second doped layer on the insulating layer, the second doped layer having the first type doped conductivity;
(C) providing a mask over the gate structure;
(D) using the provided mask to form a plurality of spaced apertures through the gate structure exposing corresponding spaced portions of the body underlying the plurality of spaced apertures;
(E) introducing a second type doped conductivity material opposite to the first type doped conductivity through the apertures into the exposed spaced portions of the body to form a plurality of doped regions of the second type doped conductivity in the exposed portions of the body.

US Pat. No. 10,971,537

IMAGE SENSORS

Samsung Electronics Co., ...

1. An image sensor comprising:a semiconductor substrate including a pixel region and a pad region;
a plurality of photoelectric conversion regions in the pixel region;
an interconnect structure on a front surface of the semiconductor substrate;
a pad structure in the pad region, the pad structure on a rear surface of the semiconductor substrate;
at least two through via structures in the pad region, each of the at least two through via structures electrically connected to the interconnect structure through the semiconductor substrate; and
an isolation structure at least partially extending into the semiconductor substrate and through the pad region of the semiconductor substrate from the rear surface of the semiconductor substrate, in a direction extending perpendicular to the rear surface of the semiconductor substrate, the isolation structure surrounding all of the pad structure and all of the at least two through via structures in a plane extending parallel to the rear surface of the semiconductor substrate.

US Pat. No. 10,971,536

IMAGE SENSOR AND IMAGE-CAPTURING APPARATUS

NIKON CORPORATION, Tokyo...

1. An image sensor, comprising:a photoelectric conversion unit that photoelectrically converts light to generate an electric charge;
an AD conversion unit having a comparison unit that compares a signal caused by the electric charge generated by the photoelectric conversion unit with a reference signal; a first storage unit provided in a first circuit layer, the first storage unit storing a first signal based on a signal output from the comparison unit; and a second storage unit provided in a second circuit layer that is stacked on the first circuit layer, the second storage unit storing a second signal based on the signal output from the comparison unit; and
a layer having the comparison unit, wherein:
the first circuit layer is located between the layer having the comparison unit and the second circuit layer.

US Pat. No. 10,971,535

IMAGE SENSOR PACKAGE

Samsung Electronics Co., ...

1. An image sensor package, comprising:an image sensor chip on a package substrate, the image sensor chip having a conductive wire attached at a first surface thereof, the conductive wire extending laterally beyond a lateral periphery of the image sensor chip;
a logic chip on the package substrate, the logic chip being disposed to face a second surface of the image sensor chip that is opposite the first surface, the logic chip perpendicularly overlapping the image sensor chip, the logic chip to process a pixel signal output from the image sensor chip; and
a memory chip between the logic chip and the package substrate, perpendicularly overlapping the image sensor chip and the logic chip, wherein:
the package substrate includes an interconnection layer,
the memory chip is mounted on the package substrate by an access terminal that is bonded to and perpendicularly overlaps both the memory chip and the package substrate, the memory chip being electrically connected with the interconnection layer of the package substrate through the access terminal,
the memory chip is electrically connected to the image sensor chip through the conductive wire, the memory chip to store at least one of the pixel signal output from the image sensor chip and a pixel signal processed by the logic chip,
the memory chip is to receive the pixel signal output from the image sensor chip through the conductive wire, and
the memory chip is to receive the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

US Pat. No. 10,971,534

IMAGE SENSOR HAVING IMPROVED FULL WELL CAPACITY AND RELATED METHOD OF FORMATION

Taiwan Semiconductor Manu...

1. An image sensor comprising:a first photodetector disposed in a semiconductor substrate, wherein the first photodetector comprises a first doped region that is disposed in the semiconductor substrate and has a first doping type;
a second photodetector disposed in the semiconductor substrate, wherein the second photodetector comprises a second doped region that is disposed in the semiconductor substrate and has the first doping type;
a back-side trench isolation (BDTI) structure disposed in the semiconductor substrate and between the first doped region and the second doped region, wherein the BDTI structure extends into the semiconductor substrate from a back-side of the semiconductor substrate;
an epitaxial layer lining the BDTI structure, wherein the epitaxial layer separates the BDTI structure from the semiconductor substrate;
a third doped region disposed in the semiconductor substrate, wherein the third doped region has a second doping type opposite the first doping type, and wherein the third doped region is a continuous region that is disposed between the first doped region and the back-side of the semiconductor substrate, between the second doped region and the back-side of the semiconductor substrate, between the BDTI structure and the first doped region, and between the BDTI and the second doped region; and
a well region disposed in the semiconductor substrate, wherein the well region extends into the semiconductor substrate from a front-side of the semiconductor substrate opposite the back-side of the semiconductor substrate, the well region separates both the first doped region and the second doped region from the front-side of the semiconductor substrate, and the first doped region contacts the well region.

US Pat. No. 10,971,533

VERTICAL TRANSFER GATE WITH CHARGE TRANSFER AND CHARGE STORAGE CAPABILITIES

STMICROELECTRONICS (CROLL...

23. An image sensor comprising:a semiconductor region;
a deep trench comprising an insulating material surrounding the semiconductor region;
a first doped region disposed over the semiconductor region, the first doped region having a first doping type, the semiconductor region physically contacting the first doped region to form a p/n junction;
a transfer gate comprising a shallow trench surrounding the first doped region, the shallow trench comprising a conductor surrounded by an insulator;
a ring shaped well disposed over the first doped region and surrounding parts of the first doped region, the ring shaped well having a second doping type opposite to the first doping type, the ring shaped well defined by the deep trench and the shallow trench;
a second doped region within the ring shaped well and disposed over the first doped region, the second doped region being more heavily doped than the first doped region and of the same doping type as the first doped region; and
a third doped region disposed over the second doped region, the third doped region being more heavily doped than the second doped region and of the same doping type as the first doped region, wherein the first doped region, the second doped region, the third doped region, and the transfer gate forming a depletion mode transistor.

US Pat. No. 10,971,532

RADIATION IMAGING APPARATUS, RADIATION IMAGING METHOD, AND STORAGE MEDIUM

CANON KABUSHIKI KAISHA, ...

1. A radiation imaging apparatus in which a pixel for obtaining an image based on radiation and a light shielded pixel which is shielded from light are arranged in an array, comprising:a setting unit configured to set a region including a plurality of pixels for obtaining the image based on the radiation and cause pixel values based on the plurality of pixels in the region to be output; and
a correction unit configured to determine whether the light shielded pixel is included in the region, and correct the pixel values based on the plurality of pixels in the region if the light shielded pixel is included in the region.

US Pat. No. 10,971,531

PIXELS

Sensors Unlimited, Inc., ...

1. A photodiode comprising:an absorption layer;
a cap layer operatively connected to the absorption layer;
a pixel formed in the cap layer and extending into the absorption layer to receive charge generated from photons therefrom, wherein the pixel defines an annular diffused area, wherein the annular diffused area defines an inner diameter, wherein a portion of the cap layer is within the inner diameter of the annular diffused area;
a metal layer operatively connected to the annular diffused area the pixel; and
a dielectric material layer overlaid on the cap layer, wherein the dielectric material layer is positioned between the portion of the cap layer within the inner diameter of the annular diffused area and the metal layer.

US Pat. No. 10,971,530

MANUFACTURING METHOD FOR A TFT ARRAY SUBSTRATE AND TFT ARRAY SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method for a TFT array substrate, comprising steps of:step (S1), providing a substrate, forming a gate electrode and a gate insulation layer covering the gate electrode on the substrate;
step (S2), forming an active layer on the gate insulation layer, wherein the active layer comprises an amorphous silicon material layer and a doped amorphous silicon layer;
step (S3), sequentially depositing an electrode material layer and a metal material layer on the gate insulation layer and the active layer such that the electrode material layer is in contact with the doped amorphous silicon layer; forming a photoresist pattern on the metal material layer, wherein the photoresist pattern includes a first photoresist block and a second photoresist block which are separate from each other; a projection of a portion of the first photoresist block in a vertical direction is overlapped with one end of the active layer, and a projection of a portion of the second photoresist block in the vertical direction is overlapped with an opposite end of the active layer; a thickness of the first photoresist block is greater than a thickness of the second photoresist block; and
step (S4), etching the metal material layer and the electrode material layer using the photoresist pattern as a mask to remove a portion of the metal material layer and a portion of the electrode material layer that are not covered by the photoresist pattern; ashing the photoresist pattern to remove the second photoresist block so as to form an ashed photoresist pattern; etching the metal material layer using the ashed photoresist pattern as a mask to remove a portion of the metal material layer that is not covered by the ashed photoresist pattern in order to form a contact electrode and a pixel electrode respectively connected with the one end and the opposite end of the active layer and a source/drain electrode located on the contact electrode;
wherein the portion of the metal material layer that is not covered by the photoresist pattern is removed with a first removing operation and the portion of the electrode material layer that is not covered by the photoresist pattern is removed with a second removing operation that is different from the first removing operation, and wherein a portion of the doped amorphous silicon layer is not covered by the photoresist pattern and corresponds to the portion of the electrode material layer that is not covered by the photoresist pattern, and the portion of the doped amorphous silicon material layer is removed simultaneously with the portion of the electrode material layer with the second removing operation, and the removal of the portion of the doped amorphous silicon layer is separate from the removal of the portion of the metal material layer that is not covered by the photoresist pattern.

US Pat. No. 10,971,529

ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME

Gio Optoelectronics Corp....

1. A manufacturing method of an electronic device, comprising:providing a substrate, wherein the substrate comprises a first surface and a second surface opposite to each other;
forming a thin film circuit on the first surface of the substrate, wherein the thin film circuit comprises at least one thin film transistor and at least one conductive trace;
forming at least one first connection pad on the first surface of the substrate, wherein the first connection pad is electrically connected with the thin film transistor through the conductive trace;
disposing the second surface of the substrate on a driving circuit board, wherein the driving circuit board comprises at least one second connection pad disposed in an extension direction along the second face of the substrate and adjacently corresponding to the first connection pad; and
after forming the second surface of the substrate on the driving circuit board, forming a conductive member by jet printing or coating to partially cover the second connection pad and partially cover the first connection pad, such that the second connection pad is electrically connected with the first connection pad through the conductive member.

US Pat. No. 10,971,528

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming a first conductor over a first insulator;
forming a resist mask in a pattern over the first conductor;
etching the first conductor with the resist mask to form a second conductor and a third conductor;
performing an impurity removal step on the first insulator after the formation of the second conductor and the third conductor;
removing the resist mask;
forming a second insulator over the first insulator, the second conductor, and the third conductor; and
forming a groove for exposing the first insulator in the second insulator between the second conductor and the third conductor,
wherein the first conductor comprises a metal A, and
wherein the metal A is one kind or a plurality of kinds of aluminum, copper, tungsten, chromium, silver, gold, platinum, tantalum, nickel, molybdenum, magnesium, beryllium, indium, and ruthenium.

US Pat. No. 10,971,527

THIN-FILM TRANSISTOR SUBSTRATE INCLUDING DATA LINE WITH LOWER LAYER DATA LINE AND UPPER LAYER DATA LINE, AND LIQUID CRYSTAL DISPLAY DEVICE AND ORGANIC ELECTROLUMINESCENT DISPLAY DEVICE INCLUDING SAME

SHARP KABUSHIKI KAISHA, ...

1. A thin-film transistor substrate comprising:a gate line;
a data line;
one or more thin-film transistors;
an insulating substrate; and
a stack disposed on the insulating substrate and sequentially including a first line layer, a first insulating film, a semiconductor layer, a second insulating film, a second line layer, a third insulating film, and a third line layer,
at least one of the one or more thin-film transistors being connected to the gate line and the data line,
the at least one of the one or more thin-film transistors including a lower layer gate electrode disposed in the first line layer, the semiconductor layer, and an upper layer gate electrode disposed in the second line layer,
the gate line being disposed in the first line layer,
the data line including a lower layer data line disposed in the second line layer and an upper layer data line disposed in the third line layer,
the gate line intersecting at least one of the lower layer data line or the upper layer data line.

US Pat. No. 10,971,526

PIXEL STRUCTURE WITH ELECTRODE OF TRANSISTOR HAVING U-SHAPED PORTION

Au Optronics Corporation,...

1. A pixel structure, comprising:a scan line;
a data line intersected with the scan line;
a reference voltage line, spaced apart from the data line and intersected with the scan line;
a first transistor, having a first semiconductor pattern, a gate, and a first electrode and a second electrode separated from each other and electrically connected to the first semiconductor pattern;
a second transistor, having a second semiconductor pattern, a gate, a first electrode and a second electrode separated from each other and electrically connected to the second semiconductor pattern;
a third transistor, having a third semiconductor pattern, a gate, a first electrode and a second electrode separated from each other and electrically connected to the third semiconductor pattern;
a first pixel electrode and a second pixel electrode; wherein,
the gate of the first transistor, the gate of the second transistor, and the gate of the third transistor are electrically connected to the scan line, the first electrode of the first transistor and the first electrode of the second transistor are electrically connected to the data line, the second electrode of the second transistor is electrically connected to the first electrode of the third transistor, the second electrode of the third transistor is electrically connected to the reference voltage line, an area of the first pixel electrode is smaller than an area of the second pixel electrode, the second electrode of the first transistor is electrically connected to the first pixel electrode, and the second electrode of the second transistor is electrically connected to the second pixel electrode;
the first electrode of the second transistor, the second electrode of the second transistor, and the first electrode of the third transistor have a plurality of straight line portions, and the straight line portions overlap the second semiconductor pattern and the third semiconductor pattern, and both ends of each of the straight line portions are located outside normal projection regions of the first semiconductor pattern, the second semiconductor pattern, and the third semiconductor pattern;
the first electrode of the first transistor comprises a U-shaped portion overlapping the first semiconductor pattern, and one of the straight line portions of the first electrode of the second transistor comprises a portion of the U-shaped portion of the first electrode;
a curved section of the U-shaped portion is located within the normal projection region of the first semiconductor pattern.

US Pat. No. 10,971,525

TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A thin film transistor (TFT) array substrate manufacturing method, comprisingS10: providing a substrate and forming a TFT on the substrate, comprising
S101: forming patterned data line and source electrode on the substrate, where the data line and the source electrode are connected to each other, and the source electrode has a ring shaped structure,
S102: forming a first insulation layer on the substrate to cover the data line and the source electrode,
S103: forming a ring trough on the first insulation layer by etching, where the source electrode is exposed from the ring trough,
S104: forming in the ring trough a semiconductor active layer that connects the source electrode,
S105: forming a channel on the first insulation layer by etching in an area surrounded by the ring trough, and
S106: forming patterned gate line, gate electrode, and drain electrode on the first insulation layer, where the gate electrode is formed in the channel opposite to the semiconductor active layer and is connected to the gate line, and the drain electrode is connected to the semiconductor active layer;
S20: forming a second insulation layer on the TFT, and forming a pixel via on the second insulation layer to expose the drain electrode; and
S30: forming patterned pixel electrode on the second insulation layer, where the pixel electrode is connected to the drain electrode through the pixel via.

US Pat. No. 10,971,524

DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first gate electrode over a substrate;
a first insulating layer over the first gate electrode;
a first oxide semiconductor layer and a second oxide semiconductor layer over the first insulating layer;
a source or drain electrode over the first oxide semiconductor layer;
a second insulating layer over the first oxide semiconductor layer; and
a second gate electrode over the second insulating layer,
wherein the second gate electrode is overlapped with the first gate electrode with the first insulating layer, the first oxide semiconductor layer, and the second insulating layer interposed between the first gate electrode and the second gate electrode,
wherein a portion of the second oxide semiconductor layer is overlapped with the source or drain electrode and the second insulating layer,
wherein each of the first oxide semiconductor layer and the second oxide semiconductor layer comprises indium, gallium, and zinc, and
wherein a capacitor comprises the second oxide semiconductor layer.

US Pat. No. 10,971,523

PIXEL ARRAY AND FABRICATION METHOD THEREOF

HEFEI XINSHENG OPTOELECTR...

1. A pixel array, comprising:a plurality of gate lines and a plurality of data lines which are arranged intersected and insulated; and
a pixel unit disposed at a position where each of the plurality of gate lines and each of the plurality of data lines are intersected, wherein
the pixel unit comprises a thin film transistor (TFT),
each gate line comprises one end at which a scan signal is supplied, each data line comprises one end at which a data signal is supplied,
wherein for any two pixel units positioned in a same row, a width-to-length ratio of a channel of the TFT in one pixel unit which is positioned closer to the end of a corresponding gate line at which the scan signal is supplied is smaller than a width-to-length ratio of a channel of the TFT in the other pixel unit which is positioned farther from the end of the corresponding gate line at which the scan signal is supplied; and/or
for any two pixel units positioned in a same column, a width-to-length ratio of a channel of the TFT in one pixel unit which is positioned closer to the end of a corresponding data line at which the data signal is supplied is smaller than a width-to-length ratio of a channel of the TFT in the other pixel unit which is positioned farther from the end of the corresponding data line at which the data signal is supplied.

US Pat. No. 10,971,522

HIGH MOBILITY COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR (CMOS) DEVICES WITH FINS ON INSULATOR

INTERNATIONAL BUSINESS MA...

1. A transistor structure, comprising:an insulator layer formed on a silicon substrate and below a plurality of pillars, wherein the plurality of pillars are
formed on the insulator layer and comprising an active layer material with a higher carrier mobility than silicon, wherein the plurality of pillars are physically isolated from one another, and wherein the active layer material of the plurality of pillars is selected from a group consisting of germanium (Ge), semiconductor III-V materials, and semiconductor II-VI materials,
the plurality of pillars having a first portion and a second portion, the first portion having epitaxial growth contacting and extending vertically away from the silicon substrate, and the second portion having fewer epitaxial defects than the first portion and located on and extending vertically away from the first portion.

US Pat. No. 10,971,521

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a peripheral circuit structure disposed on a lower substrate, and including a peripheral pad portion;
an upper substrate disposed on the peripheral circuit structure;
a stack structure disposed on the upper substrate, and including gate horizontal patterns, the gate horizontal patterns being stacked while being spaced apart from each other in a vertical direction perpendicular to an upper surface of the upper substrate;
a vertical channel structure passing through the stack structure in a first region on the upper substrate;
a vertical support structure passing through the stack structure in a second region on the upper substrate;
a separation structure passing through the stack structure in the first and second regions; and
a peripheral contact plug electrically connected to the peripheral pad portion,
wherein the stack structure has a stepped shape in the second region,
wherein the vertical channel structure includes a lower channel portion, an upper channel portion on the lower channel portion, and an intermediate channel portion between the lower channel portion and the upper channel portion,
wherein the lower channel portion includes a lower channel side surface having a first slope,
wherein the upper channel portion includes an upper channel side surface having a second slope,
wherein at least a portion of the intermediate channel portion includes an intermediate channel side surface having a third slope different from the first and second slopes,
wherein the vertical support structure includes:
a lower support portion disposed at the same level as the lower channel portion;
an intermediate support portion disposed at the same level as the intermediate channel portion; and
an upper support portion disposed at the same level as the upper channel portion, and
wherein a side surface of the lower support portion, a side surface of the intermediate support portion and a side surface of the upper support portion are aligned with each other.

US Pat. No. 10,971,520

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SK hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:a stack including interlayer insulating layers and conductive patterns stacked alternately with each other;
a cell pillar passing through the interlayer insulating layers and the conductive patterns in a first region of the stack;
a contact plug contacting one of the conductive patterns in a second region of the stack; and
a first dummy pillar and a second dummy pillar passing through the stack in the second region of the stack,
wherein each of the cell pillar and the first and second dummy pillars includes a tunnel insulating layer formed along a sidewall of a hole passing through the stack, a core insulating layer formed in the hole, and a channel layer formed between the tunnel insulating layer and the core insulating layer in the hole, and
wherein the contact plug is disposed between the first dummy pillar and the second dummy pillar.

US Pat. No. 10,971,519

NON-VOLATILE MEMORY STRUCTURE

Powerchip Semiconductor M...

1. A non-volatile memory structure, comprising:a substrate;
a stacked structure disposed on the substrate and having an opening, wherein the stacked structure comprises first conductive layers and first dielectric layers alternately stacked;
a conductive pillar disposed in the opening;
a channel layer disposed between the stacked structure and the conductive pillar;
a charge storage structure disposed between the stacked structure and the channel layer; and
a second dielectric layer disposed between the channel layer and the conductive pillar.

US Pat. No. 10,971,518

THREE DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional semiconductor memory device, comprising:a substrate including a cell array region and a connection region;
an electrode structure including a plurality of electrodes vertically stacked on the substrate, each of the electrodes having a pad portion on the connection region;
a plurality of electrode separation structures penetrating the electrode structure, the electrode separation structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction; and
a plurality of contact plugs coupled to the pad portions of the electrodes,
wherein the contact plugs comprise:
a plurality of first contact plugs along the first direction; and
a plurality of second contact plugs apart in the second direction from the first contact plugs,
wherein the electrode separation structures comprise:
a first electrode separation structure between the first contact plugs and the second contact plugs;
a second electrode separation structure apart from the first electrode separation structure in the second direction, the first contact plugs between the first and second electrode separation structures; and
a third electrode separation structure apart from the first electrode separation structure in the second direction, the second contact plugs between the first and third electrode separation structures,
wherein the first contact plugs are apart in the second direction at a first distance from the first electrode separation structure, and apart from the second electrode separation structure at a second distance less than the first distance, and
wherein the second contact plugs are apart in the second direction from the first electrode separation structure at a third distance different from the first distance, and apart from the third electrode separation structure at a fourth distance less than the third distance.

US Pat. No. 10,971,517

SOURCE CONTACT STRUCTURE OF THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF

YANGTZE MEMORY TECHNOLOGI...

1. A memory device, comprising:a memory stack comprising a plurality of interleaved conductor layers and insulating layers extending over a substrate;
a plurality of channel structures each extending vertically through the memory stack into the substrate; and
a source contact structure extending vertically through the memory stack and extending in a first lateral direction and separating the memory stack into a first portion and a second portion, wherein the source contact structure comprises:
a dielectric layer between the first portion and the second portion of the memory stack; and
a plurality of source contacts in the dielectric layer and each electrically coupled to a common source of the plurality of channel structures, the plurality of source contacts comprising more than one source contact in each of the first lateral direction and a second lateral direction perpendicular to the first lateral direction.

US Pat. No. 10,971,516

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHODS OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. An integrated circuit device comprising:a substrate comprising a cell region and an extension region arranged along a horizontal direction;
a plurality of conductive layers stacked on the cell region in a vertical direction that is perpendicular to the horizontal direction, wherein the plurality of conductive layers extend onto the extension region and have a stair-step structure on the extension region; and
a plurality of vertical structures on the substrate, wherein each of the plurality of vertical structures extends in the vertical direction, and the plurality of vertical structures comprise a first vertical structure on the cell region and comprise a second vertical structure and a third vertical structure on the extension region,
wherein the first vertical structure extends through the plurality of conductive layers and comprises a first channel layer,
wherein the second vertical structure is in the stair-step structure of the plurality of conductive layers and comprises an upper portion comprising a second channel layer and a lower portion comprising a first insulating layer, and the lower portion of the second vertical structure is between the substrate and the upper portion of the second vertical structure,
wherein the third vertical structure comprises a second insulating layer and is spaced apart from the first insulating layer of the lower portion of the second vertical structure in the horizontal direction,
wherein the second channel layer is spaced apart from the substrate in the vertical direction,
wherein the second channel layer of the upper portion of the second vertical structure directly contacts the first insulating layer of the lower portion of the second vertical structure, and
wherein a vertical length of the second insulating layer of the third vertical structure is different from a vertical length of the first insulating layer of the lower portion of the second vertical structure.

US Pat. No. 10,971,515

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a first conductive layer extending in a first direction;
a first insulating layer extending in the first direction, the first conductive layer and the first insulating layer being arranged in a second direction intersecting the first direction;
a first semiconductor layer opposed to the first conductive layer, and extending in a third direction intersecting the first direction and the second direction;
a second semiconductor layer opposed to the first conductive layer, extending in the third direction, and having a different position in the second direction from the first semiconductor layer;
a first contact electrode connected to the first semiconductor layer; and
a second contact electrode connected to the second semiconductor layer, wherein
in a first cross section extending in the first direction and the second direction:
an entire outer peripheral surface of the first semiconductor layer is surrounded by the first conductive layer; and
an outer peripheral surface of the second semiconductor layer is surrounded by the first conductive layer and the first insulating layer.

US Pat. No. 10,971,514

MULTI-TIER THREE-DIMENSIONAL MEMORY DEVICE WITH DIELECTRIC SUPPORT PILLARS AND METHODS FOR MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional semiconductor device, comprising:a first-tier alternating stack of first insulating layers and first electrically conductive layers located over a substrate;
a second-tier alternating stack of second insulating layers and second electrically conductive layers located over the first-tier alternating stack;
a memory array region including memory stack structures that vertically extend through each layer of the first-tier alternating stack and the second-tier alternating stack;
a staircase region including first stepped surfaces of the first-tier alternating stack and second stepped surfaces of the second-tier alternating stack; and
dielectric support pillar structures consisting essentially of at least one dielectric material and located within the staircase region, wherein one of the dielectric support pillar structures extends through all layers of the first-tier alternating stack and at least a bottommost layer of the second-tier alternating stack, and has a greater lateral extent at a level of a topmost layer of the first-tier alternating stack than at a level of the bottommost layer of the second-tier alternating stack and wherein bottom surfaces of the dielectric support pillar structures are located within a first horizontal plane, and bottom portions of the memory stack structures contact a source contact layer having a top surface that underlies the first horizontal plane.

US Pat. No. 10,971,513

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A three-dimensional (3D) semiconductor memory device comprising:a stack structure extending in a first direction and comprising gate electrodes sequentially stacked on a substrate;
a vertical channel structure penetrating the stack structure and a portion of the substrate;
a conductive pad disposed in an inner space of and surrounded by the vertical channel structure; and
a contact structure extending in the first direction and penetrating the stack structure,
wherein a top surface of the substrate is recessed by the vertical channel structure penetrating the portion of the substrate,
wherein the gate electrodes comprise a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, a first erase gate electrode, and a second erase gate electrode, which are sequentially stacked on the substrate,
wherein the second erase gate electrode is an uppermost one of the gate electrodes,
wherein a top surface of the conductive pad is higher than a top surface of the second erase gate electrode and lower than a top surface of the contact structure, and
wherein a bottom surface of the conductive pad is located at a vertical level between a top surface and a bottom surface of the first erase gate electrode.

US Pat. No. 10,971,512

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:a stacked body provided above a substrate, in which conductive layers are isolated from each other and stacked along a first direction crossing a surface of the substrate;
a source layer provided between the substrate and the stacked body;
memory pillars passing through the stacked body along the first direction and being coupled to the source layer;
a first insulation film provided above the stacked body, the first insulation film being located higher than upper surfaces of the memory pillars in the first direction;
isolation portions passing through the stacked body and the first insulation film along the first direction, extending in a second direction crossing the first direction and isolating the stacked body in a third direction crossing the first direction and the second direction;
a first silicon nitride member provided above the first insulation film;
a second silicon nitride member provided on side walls of the isolation portions; and
through contacts penetrating the first insulation film, the stacked body and the source layer along the first direction, the through contacts including a first through contact and a second through contact both penetrating the stacked body within a region between two isolation portions adjacent in the third direction among the isolation portions, a portion of the stacked body within the region being provided between the first through contact and the second through contact.

US Pat. No. 10,971,511

SEMICONDUCTOR MEMORY

TOSHIBA MEMORY CORPORATIO...

1. A memory comprising:a substrate;
a first region in which a plurality of first word lines are stacked above the substrate and a plurality of first semiconductor pillars extend through the first word lines, wherein first memory cells are formed at intersections of the first semiconductor pillars and the first word lines;
a second region in which a plurality of second word lines are stacked above the substrate and a plurality of second semiconductor pillars extend through the second word lines, wherein second memory cells are formed at intersections of the second semiconductor pillars and the second word lines;
a third region which is disposed between the first region and the second region and includes a plurality of first wires; and
a plurality of bit lines disposed above the first region, second region, and third region and electrically connected to the first memory cells and the second memory cells,
wherein the plurality of first wires are electrically isolated from the first word lines and the second word lines.

US Pat. No. 10,971,510

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a substrate;
a wiring layer including:
a first face;
a second face opposed to the first face in a first direction;
a third face provided between the first face and the second face in the first direction and being different in position from the first face and the second face in a second direction intersecting with the first direction;
a fourth face opposed to the third face in the second direction;
a fifth face continuously connected between the first face and the third face and located in a third direction which is between the first direction and the second direction;
a sixth face opposed to the fifth face in the third direction and continuously connected between the second face and the fourth face;
a seventh face continuously connected between the first face and the fourth face and located in a fourth direction which is between the first direction and the second direction and which is different from the third direction; and
an eighth face opposed to the seventh face in the fourth direction and continuously connected between the second face and the third face;
a first insulating layer provided between the first to eighth faces;
a first signal line provided between the first face and the first insulating layer and extending in a direction perpendicular to the substrate;
a second signal line provided between the second face and the first insulating layer and extending in the direction perpendicular to the substrate;
a third signal line provided between the third face and the first insulating layer and extending in the direction perpendicular to the substrate;
a fourth signal line provided between the fourth face and the first insulating layer and extending in the direction perpendicular to the substrate;
a first memory cell provided between the first signal line and the wiring layer and configured to store first information;
a second memory cell provided between the second signal line and the wiring layer and configured to store second information;
a third memory cell provided between the third signal line and the wiring layer and configured to store third information; and
a fourth memory cell provided between the fourth signal line and the wiring layer and configured to store fourth information,
wherein the first direction, the second direction, the third direction, and the fourth direction are parallel to the substrate.

US Pat. No. 10,971,509

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor memory device comprising:a stack body including a lower conductive pattern and an upper conductive pattern stacked apart from each other in a first direction, and at least one intermediate conductive pattern disposed between the lower conductive pattern and the upper conductive pattern;
a first contact plug connected to the lower conductive pattern and extending in the first direction; and
at least one lower dummy plug overlapping the lower conductive pattern in the first direction and extending in the first direction.

US Pat. No. 10,971,508

INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME

Winbond Electronics Corp....

1. A method of manufacturing an integrated circuit, comprising:providing a substrate having a cell region and a peripheral region;
performing a first process, wherein the first process comprises:
forming a plurality of first gate structures in the cell region, comprising:
forming a tunneling dielectric layer on the substrate;
forming a floating gate on the tunneling dielectric layer;
forming an inter-gate dielectric layer on the floating gate;
forming a control gate on the dielectric layer of the gate; and
forming a top cap layer on the control gate, wherein the control gate is free of metal silicide;
forming a gate dielectric material layer and forming a conductive layer in the peripheral region; and
conformally forming a protective layer on the plurality of first gate structures;
after the first process is performed, a second process is performed, and the second process comprises:
patterning the gate dielectric material layer in the peripheral region and the conductive layer to form a second gate structure; and
forming a source region and a drain region on both sides of the second gate structure, respectively,
wherein a highest temperature of the first process is higher than a highest temperature of the second process.

US Pat. No. 10,971,507

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING THROUGH-MEMORY-LEVEL CONTACT VIA STRUCTURES

SANDISK TECHNOLOGIES LLC,...

1. A device structure comprising:a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate and including first stepped surfaces in a staircase region;
a first retro-stepped dielectric material portion overlying the first stepped surfaces of the first alternating stack;
a second alternating stack of second insulating layers and second electrically conductive layers located over the first alternating stack and including second stepped surfaces in the staircase region;
a second retro-stepped dielectric material portion overlying the second stepped surfaces of the second alternating stack; and
a first laterally-insulated staircase region via structure vertically extending through a first subset of the second electrically conductive layers of the second alternating stack and the first retro-stepped dielectric material portion,
wherein the first laterally-insulated staircase region via structure comprises a first conductive via structure that is electrically connected to one of the first electrically conductive layers, and is electrically isolated from each of the second electrically conductive layers;
wherein the first laterally-insulated staircase region via structure comprises a first dielectric liner that laterally surrounds the first conductive via structure and contacts each of the first subset of the second electrically conductive layers of the second alternating stack; and
wherein a bottommost one of the second electrically conductive layers of the second alternating stack entirely laterally surrounds the first laterally-insulated staircase region via structure as a single continuous structure.

US Pat. No. 10,971,506

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a memory cell including first to cth sub memory cells (c is a natural number greater than or equal to 2),
wherein a jth sub memory cell includes a transistor and a capacitor (j is a natural number of 1 to c),
wherein a semiconductor layer in the transistor includes an oxide semiconductor,
wherein the oxide semiconductor includes at least one of indium, gallium, and zinc,
wherein, when j?2, the jth sub memory cell is arranged over a j?1th sub memory cell, and
wherein a bit line is electrically connected to the jth sub memory cell and the j?1th sub memory cell.

US Pat. No. 10,971,505

MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a plurality of first nanostructures stacked on top of one another;
a plurality of first all-around gate stacks operatively associated with the plurality of first nano structures;
a plurality of second nanostructures stacked on top of one another;
a plurality of second all-around gate stacks operatively associated with the plurality of second nanostructures;
a first drain/source region electrically coupled to a first end of the first nanostructures, the first drain/source region including a first recess with a first depth;
a second drain/source region electrically coupled to a second end of the first nanostructures, the second drain/source region including a second recess with a second depth;
a third drain/source region electrically coupled to a first end of the second nanostructures, the third drain/source region including a third recess with a third depth; and
a fourth drain/source region electrically coupled to a second end of the second nanostructures, the fourth drain/source region including a fourth recess with a fourth depth,
wherein at least one of the first depth, second depth, third depth, or fourth depth is greater than a distance by which a farthest one of the plurality of first nanostructures and the plurality of second nanostructures is spaced apart from a top surface of the first drain/source region, the second drain/source region, the third drain/source region, and the fourth drain/source region.

US Pat. No. 10,971,504

THREE-DIMENSIONAL MONOLITHIC VERTICAL TRANSISTOR MEMORY CELL WITH UNIFIED INTER-TIER CROSS-COUPLE

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, comprising:forming a three-dimensional monolithic vertical transistor memory cell with a unified inter-tier cross-couple, including:
connecting a first tier including a contact disposed on a first inverter gate to a second tier including a second inverter gate by forming a monolithic inter-tier via (MIV) that lands on the contact via the second inverter gate, including forming a ground contact connecting the second tier to a bottom source/drain region of the first tier.

US Pat. No. 10,971,503

STRUCTURE AND METHOD FOR FINFET SRAM

TAIWAN SEMICONDUCTOR MANU...

1. A method for semiconductor fabrication, comprising:forming mandrel patterns over a substrate using a first mask that defines the mandrel patterns, wherein the first mask includes at least four first patterns that are spaced from each other in a first direction, wherein each of the first patterns extends lengthwise in a second direction orthogonal to the first direction;
forming spacers on sidewalls of the mandrel patterns;
removing the mandrel patterns; and
performing a cut process using a second mask that includes at least four cut windows, each cut window in the second mask being an elongated shape extending lengthwise in the second direction and covering a side of one of the first patterns when the first and second masks are superimposed, the side extending in the second direction.

US Pat. No. 10,971,502

SRAM STRUCTURE

UNITED MICROELECTRONICS C...

10. An SRAM structure comprising:a substrate;
a fifth active region, a third active region, a first active region, a second active region, a fourth active region and a sixth active region arranged in a sequence from left to right on the substrate, wherein the first active region, the second active region, the third active region, the fourth active region, the fifth active region and the sixth active region are parallel to each other;
a seventh active region contacting the third active region and the fifth active region, wherein the seventh active region is perpendicular to the fifth active region;
an eighth active region contacting the fourth active region and the sixth active region, wherein the eighth active region is perpendicular to the sixth active region;
a first gate line covering the first active region, the second active region and the fourth active region;
a second gate line covering the fourth active region, wherein the second gate line is parallel to the first gate line;
a third gate line covering the first active region, the second active region and the third active region;
a fourth gate line covering the third active region, wherein the fourth gate line is parallel to the third gate line;
a first metal line electrically connecting to the first gate line and the second gate line, wherein the first metal line is perpendicular to the eighth active region; and
a second metal line electrically connecting to the third gate line and the fourth gate line, wherein the second metal line is perpendicular to the seventh active region.

US Pat. No. 10,971,501

MEMORY STRUCTURE AND MANUFACTURING METHOD THEREOF

Powerchip Semiconductor M...

1. A method of manufacturing a memory structure, comprising:providing a substrate, wherein the substrate comprises a memory cell region and a peripheral circuit region;
forming a memory cell in the memory cell region, wherein a method of forming the memory cell comprises:
forming a buried conductive structure in the substrate;
forming a third contact on the substrate on one side of the buried conductive structure;
forming a conductive line coupled to the third contact; and
forming a fourth contact on the substrate on another side of the buried conductive structure after forming the conductive line;
forming a transistor in the peripheral circuit region, wherein the transistor comprises:
a gate located on the substrate and insulated from the substrate;
a first doped region and a second doped region located in the substrate on two sides of the gate;
a first nickel silicide layer located on the first doped region; and
a second nickel silicide layer located on the second doped region;
forming a dielectric layer covering the first nickel silicide layer and the second nickel silicide layer;
forming a first opening exposing the first nickel silicide layer and a second opening exposing the second nickel silicide layer in the dielectric layer; and
respectively forming a first contact and a second contact in the first opening and the second opening.

US Pat. No. 10,971,500

METHODS USED IN THE FABRICATION OF INTEGRATED CIRCUITRY

Micron Technology, Inc., ...

1. A method used in fabrication of integrated circuitry, comprising:forming a conductive material outwardly of a substrate, the conductive material having a first thickness and comprising a refractory metal nitride other than RuN;
forming metal material outwardly of and in direct physical contact with the conductive material; at least a majority of the metal material containing ruthenium in at least one of elemental-form, metal compound-form, or alloy-form;
forming a masking material outwardly of the ruthenium-containing metal material, the masking material having a second thickness at least twice the first thickness and comprising at least one of:
a refractory metal, other than ruthenium, that is in at least one of elemental-form or alloy-form;
a refractory metal nitride other than RuN;
a refractory metal oxide other than RuO2 and RuO4;
a refractory metal silicide other than Ru2Si, Ru4Si3, RuSi, and Ru2Si3;
a refractory metal carbide other than RuC;
aluminum in at least one of elemental-form or alloy-form;
AlNx;
AlOx; or
AlCx; and
in an absence of additional material over the masking material, using the masking material as a mask while etching an exposed portion of the ruthenium-containing metal material to form a feature of integrated circuitry that comprises the ruthenium-containing metal material, the etching using an etch chemistry comprising an inert gas in combination with at least one feed gas selected from O2 and Cl2.

US Pat. No. 10,971,499

UNIFIED MICRO SYSTEM WITH MEMORY IC AND LOGIC IC

Etron Technology, Inc., ...

1. An unified IC system, comprising:a base memory chip comprising a memory region and a bridge area, the memory region comprising a plurality of memory cells with a plurality of first transistors, and the bridge area comprising a plurality of memory input/output (I/O) pads and a plurality of third transistors;
a plurality of stacked memory chips positioned above the base memory chip; and
a logic chip comprising a logic bridge area and a plurality of second transistors, the logic bridge area comprising a plurality of logic I/O pads;
wherein the plurality of memory I/O pads are electrically coupled to the plurality of logic I/O pads, and a voltage level of an I/O signal of the third transistor is the same or substantially the same as a voltage level of an I/O signal of the second transistor.

US Pat. No. 10,971,498

METHOD OF FORMING A SEMICONDUCTOR MEMORY DEVICE WITH A LATERALLY ETCHED BOTTOM DIELECTRIC LAYER

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor memory device, comprising:providing a substrate having an isolation area to define a plurality of active areas therein;
forming a dielectric layer on the substrate, only a bottom portion of the dielectric layer being laterally etched, wherein the forming of the dielectric layer comprises:
forming a dielectric material layer on the substrate, to cover the isolation area and the active areas, the dielectric material layer comprising a multilayer structure; and
patterning a portion of the multilayer structure;
forming a plurality of bit lines on the dielectric layer, along a direction;
forming at least one bit line contact below one of the bit lines, in the substrate;
forming a spacer structure on sidewalls of each of the bit lines, wherein the forming of the spacer structure comprises:
forming a first material layer covering the bit lines and the multilayer structure;
forming a second material layer covering the first material layer; and
patterning the second material layer and the first material layer while patterning the portion of the multilayer structure, to form the spacer structure and to leave a bottom layer of the multilayer structure being laterally protruded from the spacer structure; and
forming a spacer layer on sidewalls of the spacer structure, the spacer layer directly in contact with the spacer structure and sidewalls of other portions of the dielectric layer.

US Pat. No. 10,971,497

MEMORY CELL

UNITED MICROELECTRONICS C...

1. A memory cell, comprising:a curved gate channel transistor having a first doped region located in a substrate, a second doped region located on the substrate and a third doped region located on the substrate, wherein the second doped region having a curved top surface is directly on the first doped region, the third doped region is right next to the second doped region, and only a sidewall of the third doped region contacts to the second doped region, thereby the first doped region, the second doped region and the third doped region constituting a curved gate channel;
a buried bit line located below the first doped region;
a word line covering the second doped region; and
a capacitor located above the curved gate channel transistor and in electrical contact with the third doped region.

US Pat. No. 10,971,496

SEMICONDUCTOR DEVICE HAVING HYBRID CAPACITORS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a plurality of lower electrode structures disposed on a substrate;
a capacitor dielectric layer disposed on a surface of each of the plurality of lower electrode structures; and
an upper electrode disposed on the capacitor dielectric layer,
wherein the plurality of lower electrode structures comprises a first lower electrode and a second lower electrode disposed on the first lower electrode and having a cylindrical shape, wherein the first lower electrode has a pillar shape,
wherein the first lower electrode comprises an insulating core disposed therein,
wherein a lower surface of the insulating core is positioned closer to an upper surface of the first lower electrode than to a lower surface of the first lower electrode.

US Pat. No. 10,971,495

CAPACITOR CELL AND STRUCTURE THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A capacitor cell, comprising:a first PMOS transistor coupled between a power supply and a first node, having a gate connected to a second node;
a first NMOS transistor coupled between a ground and the second node, having a gate connected to the first node;
a second PMOS transistor coupled between the second node and the first node, having a gate connected to the second node;
a second NMOS transistor, having a drain connected to the first node, a gate connected to the first node, and a source connected to the ground or the second node;
a first N+ doped region in an N-type well region and coupled to the power supply;
a first P+ doped region in a P-type well region and coupled to the ground;
a first isolation region between the gate of the first PMOS transistor and the first N+ doped region in the first well region;
a second isolation region between the gate of the first NMOS transistor and the first P+ doped; and
a third isolation region between the P-type well region and the N-type well region,
wherein the first and second PMOS transistors on the N-type well region and the first and second NMOS transistors on the P-type well region are arranged in the same row,
wherein drains of the first and second PMOS transistors share a P+ doped region over the N-type well region, and the second PMOS transistor is disposed between the first PMOS transistor and the first and second NMOS transistors.

US Pat. No. 10,971,494

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT

SOCIONEXT, INC., Yokoham...

1. A semiconductor device comprising:element isolation insulating regions formed in a substrate and including first and second opposed end portions which are opposed to each other;
a projecting semiconductor region formed on the substrate and extending from the first opposed end portion to the second opposed end portion;
a pair of dummy gate electrodes formed adjacent to the first and second opposed end portions and formed on both side surfaces and a top surface of both end portions of the projecting semiconductor region, the dummy gate electrodes being electrically floating;
a plurality of first gate electrodes each formed on both side surfaces and a top surface of a first portion of the projecting semiconductor region, the plurality of first gate electrodes being formed between the pair of dummy gate electrodes and being component elements of a plurality of first transistors which are configured to be driven according to signals input to the first gate electrodes, each of the plurality of first transistors being a FinFET; and
at least one second gate electrode formed on both side surfaces and a top surface of a second portion of the projecting semiconductor region, the second portion being different from the first portions, the second gate electrode being formed between the first gate electrodes and between the pair of dummy gate electrodes in parallel with the first gate electrodes, in the same layer as a layer where the plurality of first gate electrodes are formed, and being a component element of a second transistor which is applied with a gate voltage such that the second transistor is turned off.

US Pat. No. 10,971,493

INTEGRATED CIRCUIT DEVICE WITH HIGH MOBILITY AND SYSTEM OF FORMING THE INTEGRATED CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit device, comprising:a first fin structure, having a first type dopant, disposed on a substrate and aligned in a first direction;
a second fin structure, having the first type dopant, disposed on the substrate and aligned in the first direction, wherein the second fin structure is successively adjacent to the first fin structure;
a third fin structure, having a second type dopant, disposed on the substrate in the first direction;
a fourth fin structure, having the second type dopant, disposed on the substrate and aligned in the first direction, wherein the fourth fin structure is successively adjacent to the third fin structure;
a first conductive line, aligned in a second direction, arranged to wrap a first portion of the first fin structure, one end of the first conductive line being located between the first fin structure and the second fin structure; and
a second conductive line, aligned with the first conductive line in the second direction, arranged to wrap a second portion, a third portion, and a fourth portion of the second fin structure, the third fin structure, and the fourth fin structure respectively, wherein the second conductive line is physically disconnected from the first conductive line in the second direction, one end of the second conductive line is located between the second fin structure and the first fin structure, and the one end of the first conductive line and the one end of the second conductive face each other in the second direction and are separated from each other;
wherein a first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure.

US Pat. No. 10,971,492

PACKAGE-EMBEDDED THIN-FILM CAPACITORS, PACKAGE-INTEGRAL MAGNETIC INDUCTORS, AND METHODS OF ASSEMBLING SAME

Intel Corporation, Santa...

1. A semiconductor package substrate, comprising:a first build-up film including a first surface;
a second and adjacent build-up film including a recess that abuts the first surface; and
a magnetic inductor, wherein the magnetic inductor includes an inductor trace and a first magnetic-particle body within the recess.

US Pat. No. 10,971,491

METHOD FOR FORMING CAPACITOR, SEMICONDUCTOR DEVICE, MODULE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A method for forming a capacitor, comprising steps of:forming a first conductor;
forming a first insulator over the first conductor;
forming an opening in the first insulator, the opening reaching a top surface of the first conductor;
forming a second conductor over the first insulator and in the opening;
performing a plasma treatment containing oxygen on the second conductor, so that a silicon oxide film is formed on a surface of the second conductor and in the opening;
forming a third conductor over the silicon oxide film to fill the opening; and
performing a polishing treatment so that top surfaces of the second conductor, the silicon oxide film, and the third conductor are substantially level with a top surface of the first insulator,
wherein the second conductor includes tungsten and silicon.

US Pat. No. 10,971,490

THREE-DIMENSIONAL FIELD EFFECT DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of forming stacked fin field effect devices, comprising:forming a layer stack on a surface of a substrate, wherein the layer stack includes a first spacer layer on the substrate, a first protective liner on the first spacer layer, a first gap layer on the first protective liner, a second protective liner on the first gap layer, a second spacer layer on the second protective liner, a sacrificial layer on the second spacer layer, a third spacer layer on the sacrificial layer, a third protective liner on the third spacer layer, a second gap layer on the third protective liner, a fourth protective liner on the second gap layer, and a fourth spacer layer on the fourth protective liner;
forming a plurality of channels through the layer stack to the surface of the substrate;
forming a liner layer on the sidewalls of each of the plurality of channels;
forming a vertical pillar in each of the channels, wherein each of the one or more vertical pillars includes a separate doped region laterally aligned with each of the first spacer layer, second spacer layer, third spacer layer, and a fourth spacer layer;
forming a trench through the layer stack, wherein the trench is laterally offset a distance from the vertical pillar in an adjacent channel;
removing a portion of the sacrificial layer to form a recess between the third spacer layer and the second spacer layer, wherein a portion of the liner layer on the vertical pillar is exposed between the third spacer layer and the second spacer layer;
removing the exposed portion of the liner layer to expose a portion of the vertical pillar between the doped region laterally aligned with the second spacer layer and the doped region laterally aligned with the third spacer layer; and
removing the exposed portion of the vertical pillar to form a space between the doped region laterally aligned with the second spacer layer and the doped region laterally aligned with the third spacer layer.

US Pat. No. 10,971,489

COMPACT PROTECTION DEVICE FOR PROTECTING AN INTEGRATED CIRCUIT AGAINST ELECTROSTATIC DISCHARGE

STMicroelectronics SA, M...

1. An integrated circuit, comprising:a power supply terminal configured to receive a power supply voltage,
a reference terminal configured to receive a reference voltage,
a first signal terminal configured to receive or transmit a first signal,
a second signal terminal configured to receive or transmit a second signal,
a first protection device coupled between the first signal terminal and the power supply terminal,
a second protection device coupled between the first signal terminal and the reference terminal,
a third protection device coupled between the second signal terminal and the power supply terminal,
a fourth protection device coupled between the second signal terminal and the reference terminal, and
a MOS protection transistor having a first electrode coupled to said first signal terminal and a second electrode coupled to said second signal terminal, wherein a gate of the MOS protection transistor is directly connected to the reference terminal and a substrate of the MOS protection transistor is coupled to the reference terminal via a first common resistor.

US Pat. No. 10,971,488

ACTIVE ESD CLAMP DEACTIVATION

Infineon Technologies AG,...

1. A circuit comprising:electrostatic discharge (ESD) protection circuitry coupled between a first rail and a second rail;
triggering circuitry configured to generate an ESD activation signal when a voltage across the first rail and the second rail exceeds a voltage threshold, wherein the triggering circuitry comprises one or more active triggering elements arranged in a series string and wherein the ESD protection circuitry is configured to activate based on the ESD activation signal;
transient detection circuitry configured to generate a deactivation signal when the voltage across the first rail and the second rail comprises a voltage change over time that is less than a transient threshold; and
deactivation circuitry configured to deactivate the triggering circuitry based on the deactivation signal.

US Pat. No. 10,971,487

SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:a cell wafer including first and second planes which are disposed to be adjacent to each other in a first direction and each include a plurality of memory cells, and having, on one surface thereof, a first pad which is coupled in common to the first plane and the second plane; and
a peripheral wafer including a peripheral circuit, and having, on one surface thereof bonded to the one surface of the cell wafer, a second pad which is coupled with the peripheral circuit and is bonded to the first pad,
wherein the peripheral circuit includes a pass transistor circuit which is coupled with the second pad and a block switch circuit which controls the pass transistor circuit,
wherein the block switch circuit is disposed in a first plane region of the peripheral wafer, which overlaps with the first plane in a vertical direction orthogonal to the one surface, and a second plane region of the peripheral wafer, which overlaps with the second plane in the vertical direction, and
wherein the pass transistor circuit is disposed in an interval region of the peripheral wafer between the first plane region and the second plane region.

US Pat. No. 10,971,486

SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package, comprising:a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface;
at least one capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and a plurality of decoupling capacitors formed in an upper region of the semiconductor substrate to be separated from each other, each of the plurality of decoupling capacitors including respective capacitor pads;
a first semiconductor chip arranged on the upper surface of the package substrate, the first semiconductor chip being spaced apart from the at least one capacitor structure;
a plurality of second semiconductor chips mounted on the at least one capacitor structure and the first semiconductor chip using an adhesive film that is in contact with the at least one capacitor structure and the first semiconductor chip; and
conductive connection members including bonding wires that electrically connect at least one of the capacitor pads of the plurality of decoupling capacitors to a corresponding substrate pad of the plurality of substrate pads.

US Pat. No. 10,971,485

SOLENOID INDUCTORS WITHIN A MULTI-CHIP PACKAGE

Taiwan Semiconductor Manu...

1. A multi-chip package, comprising:an enclosed integrated circuit (IC) package comprising:
a first plurality of conductive layers disposed onto a semiconductor substrate, the first plurality of conductive layers including a first portion of a first solenoid inductor and a first portion of a second solenoid inductor,
wherein the semiconductor substrate comprises:
a plurality of through silicon via (TSV) structures to electrically couple the first portion of the first solenoid inductor and a second portion of the first solenoid inductor; and
an enclosing IC package comprising:
a plurality of system on chip (SoC) packages,
a first interposer, situated onto the plurality of SoC packages, having a second plurality of conductive layers, wherein a second portion of the second solenoid inductor and a first portion of a third solenoid inductor are situated within the second plurality of conductive layers,
a second interposer, situated onto the enclosed IC package, having a third plurality of conductive layers, wherein the second portion of the first solenoid inductor and a second portion of the third solenoid inductor are situated within the third plurality of conductive layers,
a plurality of regions of a molding compound situated between the first interposer and the second interposer, wherein the plurality of regions of the molding compound include a plurality of via structures to electrically couple the first portion of the third solenoid inductor and the second portion of the third solenoid inductor, and
a plurality of regions of conductive material situated between the enclosed IC package and the first interposer to electrically couple the first portion of the second solenoid inductor and the second portion of the second solenoid inductor.

US Pat. No. 10,971,484

PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTEM INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A package-on-package (PoP) semiconductor package, comprising:an upper package; and
a lower package including:
a first semiconductor device in a first area,
a second semiconductor device in a second area, and
a command-and-address (CA) vertical interconnection, a data input-output vertical interconnection, and a memory management vertical interconnection, wherein at least one of the CA vertical interconnection, the data input-output vertical interconnection, and the memory management vertical interconnection is between the first semiconductor device and the second semiconductor device.

US Pat. No. 10,971,483

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor package, comprising:an interconnect layer comprising:
first conductive vias and second conductive vias, the first and second conductive vias comprising copper;
first conductive pads comprising tungsten and disposed on the respective first conductive vias, the first conductive pads configured as bond pads;
second conductive pads comprising tungsten and disposed on the respective second conductive vias, the second conductive pads configured as test pads;
a dielectric material laterally surrounding the first and second conductive vias; and
a seed layer comprising titanium and disposed between the dielectric material and each of the first and second conductive vias;
a plurality of conductive pillars over the interconnect layer;
a first semiconductor die bonded to the interconnect layer through the first conductive pads, wherein a first side of the first semiconductor die faces the interconnect layer;
an integrated passive device bonded to the interconnect layer through the first conductive pads, the integrated passive device and the first semiconductor die being disposed on a same side of the interconnect layer;
a second semiconductor die electrically coupled to the conductive pillars; and
an encapsulating material surrounding the first semiconductor die, the integrated passive device and the conductive pillars,
wherein each of the conductive pillars extends though the encapsulating material and comprises an upper surface level with a second side of the first semiconductor die opposite to the first side of the first semiconductor die.

US Pat. No. 10,971,482

LIGHT BLOCKING LOUVER PANEL FOR AN LED LIGHT DISPLAY

Formetco, Inc., Duluth, ...

1. A LED light display comprising:a plurality of LED bulb arrays, each bulb LED array comprises three spaced LED bulbs that are positioned to form a triangle shape that defines an LED bulb centroid that is on a horizontal plane;
a louver panel defining a plurality of hole arrays, wherein each hole array defines a plurality of openings that are sized and spaced to receive at least the distal end portions of the bulbs forming a single LED bulb array, wherein each opening of the one hole array define vertices of a triangle, in which two openings are positioned and define vertices along a substantially vertical plane P1 and the remaining opening is positioned at and defines a vertex that is positioned in a horizontal plane P2 generally perpendicular to the vertical plane, each opening hole array defines a LED opening centroid that is on the horizontal plane and is operationally substantially coincident with the respective LED bulb centroid, wherein the louver panel further comprises a plurality of shaped protrusions in the form of louvers that are configured to extend outwardly and forwardly from a front surface of the louver panel and are arranged in a plurality of columns and in a plurality of rows in regularly repeating patterns related to the pattern of the placement of a plurality of the plurality of hole arrays in the louver panel, each louver comprising an elongate vertical member integrally connected to a compound curve member, wherein the elongate member has a proximal end and a distal end that is positioned in a horizontal plane P3 that is below the horizontal plane P2 bisecting the LED bulb centroid and the LED opening centroid, wherein the compound curve member comprises a first curved member and a second curved member such that the first curve member extends outwardly and upwardly from the proximal end of the vertical member to a first curve distal end and subtends an angle of 90 degrees such that the first curve distal end is positioned in a vertical plane P4 that is parallel to the vertical plane P1 and the second curved member extends outwardly and downwardly to a second curve distal end and subtends an angle of less than 30 degrees such that the second curve distal end is positioned below and at an acute angle with respect to at least a portion of the first curve distal end and wherein each louver is configured to block at least a portion of the emission of light from the LED bulbs in both a horizontal and vertical direction.

US Pat. No. 10,971,481

LIGHT-EMITTING DEVICE AND BACKLIGHT INCLUDING LIGHT-EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light-emitting device, comprising:a first light-emitting element having an emission peak wavelength of 430 nm or more and less than 490 nm;
a second light-emitting element having an emission peak wavelength of 490 nm or more and 570 nm or less;
a support body containing a first lead at which the first light-emitting element is disposed, a second lead at which the second light-emitting element is disposed, and a resin package located in a space between the first lead and the second lead; and
a light-transmissive member containing red phosphor particles and covering the first light-emitting element and the second light-emitting element,
wherein an upper surface of the first lead, an upper surface of the second lead and an upper surface of the resin package are positioned on the same plane, and a lower surface of the first lead, a lower surface of the second lead and a lower surface of the resin package are positioned on the same plane,
wherein one of the red phosphor particles is located in a top end of an interface between the first lead and the resin package, and another of the red phosphor particles is located in a top end of an interface between the second lead and the resin package,
wherein a content density of the red phosphor particles in the light-transmissive member located in a space between the first light-emitting element and the second light-emitting element is higher in a part below an upper surface of the second light-emitting element than in a part above the upper surface thereof, and
the red phosphor particles located in the light-transmissive member in the space between the first light-emitting element and the second light-emitting element settle out so as to be in contact with each other,
wherein the red phosphor particles include at least one of a phosphor with the composition represented by the general formula (I) below and a phosphor with the composition represented by 3.5MgO.0.5MgF2.GeO2:Mn4+,
A2MF6:Mn4+  (I)where, in the general formula (I), A is at least one selected from the group consisting of K, Li, Na, Rb, Cs and NH4+; and M is at least one element selected from the group consisting of Group 4 elements and Group 14 elements.

US Pat. No. 10,971,480

DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A display panel, comprising a thin film transistor, a micro light emitting diode configured above the thin film transistor and electrically coupled to the thin film transistor, wherein the micro light emitting diode comprises a P type semiconductor, a N type semiconductor oppositely configured to the P type semiconductor and a light emitting layer configured between the P type semiconductor and the N type semiconductor, and the N type semiconductor is configured at one side of the P type semiconductor away from the thin film transistor, a thickness of the N type semiconductor being larger than a thickness of the P type semiconductor, one side of the N type semiconductor away from the P type semiconductor being a rough surface,wherein an organic layer is stacked on the thin film transistor and an open groove is configured in the organic layer, the micro light emitting diode being accepted in the open groove and electrically coupled to the thin film transistor; and a passivation layer is stacked on and covers the organic layer and the micro light emitting diode; and
wherein a first electrode is stacked on the thin film transistor and is configured in the open groove of the organic layer, the thin film transistor comprising a source and a drain, one end of the first electrode being coupled to the source and the drain, another end of the first electrode being electrically coupled to the P type semiconductor; and a second electrode is stacked on the passivation layer, one end of the second electrode being electrically coupled to the N type semiconductor by penetrating through the passivation layer to electrically connect with the rough surface of the N type semiconductor.

US Pat. No. 10,971,479

SEMICONDUCTOR PACKAGE INCLUDING STACKED SEMICONDUCTOR CHIPS

SK hynix Inc., Gyeonggi-...

1. A semiconductor package comprising:a substrate;
a first interposer disposed over the substrate;
a first chip stack disposed on the substrate on one side of the first interposer, wherein the first chip stack comprises a plurality of first semiconductor chips stacked with an offset in a first direction;
a second chip stack disposed on the first chip stack, wherein the second chip stack comprises a plurality of second semiconductor chips stacked with an offset in a second direction opposite to the first direction; and
a third chip stack disposed on the substrate on an other side of the first interposer, wherein the third chip stack comprises a plurality of third semiconductor chips stacked with an offset in the second direction,
wherein the first interposer is contacted by a bottom surface of the second chip stack that protrudes beyond the first chip stack in the first direction,
wherein the third chip stack has a thickness larger than the sum of thicknesses of the first and second chip stacks, and
wherein the third chip stack extends over at least a portion of the first interposer so that the at least a portion of the first interposer is located in a space under the third chip stack.

US Pat. No. 10,971,478

INTERPOSER DESIGN IN PACKAGE STRUCTURES FOR WIRE BONDING APPLICATIONS

Intel Corporation, Santa...

1. A microelectronic package structure comprising:a first die on a first side of a printed circuit board;
an interposer on a second side of the first die;
a second die on the second side of the first die, wherein the second die is adjacent the interposer;
a first wire conductive structure, wherein a first end of the first wire is disposed on the second die, and a second end of the first wire conductive structure is disposed on the interposer; and
a second wire conductive structure, wherein a first end of the second wire conductive structure is disposed on the interposer and is adjacent the second end of the first wire, wherein a second end of the second wire conductive structure is directly on the printed circuit board.

US Pat. No. 10,971,477

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:a first redistribution structure comprising a first redistribution line and a second redistribution line;
an integrated circuit die attached to the first redistribution structure;
a first through via coupled to the first redistribution line;
a second through via coupled to the second redistribution line, the second through via having a height greater than a height of the first through via, a first surface of the second through via distal the first redistribution structure being level with a first surface of the first through via distal the first redistribution structure and a first surface of the integrated circuit die distal the first redistribution structure;
an encapsulant surrounding the integrated circuit die, the first through via, and the second through via; and
a second redistribution structure over the encapsulant, the second redistribution structure being coupled to the first through via, the second through via, and the integrated circuit die.

US Pat. No. 10,971,476

BOTTOM PACKAGE WITH METAL POST INTERCONNECTIONS

QUALCOMM Incorporated, S...

1. A package, comprising:a substrate;
a die-side redistribution layer on the substrate;
a dielectric layer on the die-side redistribution layer, wherein the dielectric layer comprises a plurality of openings;
a seed layer on the dielectric layer;
a plurality of die interconnects electrically coupled to the die-side redistribution layer through the seed layer via at least some of the plurality of openings in the dielectric layer; and
a plurality of plated metal posts electrically coupled to the die-side redistribution layer through the seed layer via at least some of the plurality of openings in the dielectric layer, wherein the plurality of metal posts are in situ on the substrate,
wherein the substrate comprises a glass interposer or a semiconductor interposer.

US Pat. No. 10,971,475

SEMICONDUCTOR PACKAGE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor package structure, comprising:a plurality of first dies spaced from each other;
a molding layer between the first dies;
a second die over the plurality of first dies and the molding layer; and
an adhesive layer between the plurality of first dies and the second die, and between the molding layer and the second die,
wherein a first interface between the adhesive layer and the molding layer and a second interface between the adhesive layer and the plurality of first dies are at different levels, wherein the molding layer includes a protrusion portion extending toward the second die, and the first interface is closer to the second die than the second interface.

US Pat. No. 10,971,474

PACKAGE INTEGRATION FOR HIGH BANDWIDTH MEMORY

XILINX, INC., San Jose, ...

1. A chip package comprising:a substrate having circuitry terminating at a plurality of landing pads disposed on a top surface of the substrate, the plurality of landing pads arranged in at least a first plurality of landing pads and a second plurality of landing pads;
a first die having a first plurality of contact pads extending a first distance from a bottom surface of the first die, the first plurality of contact pads electrically and mechanically coupled with the circuitry of the substrate through the first plurality of landing pads;
a second die having a second plurality of contact pads extending a second distance from a bottom surface of the second die, the second plurality of contact pads electrically and mechanically coupled with the circuitry of the substrate through the second plurality of landing pads, the first distance being less than the second distance; and
a first stand-off controlling a spacing from the top surface of the substrate to the bottom surface of the second die.

US Pat. No. 10,971,473

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a substrate including a surface facing in a first direction, and a plurality of electrodes on the surface;
a plurality of first stacked components including a plurality of first chips, the plurality of first stacked components being stacked on the surface;
a plurality of first wires that connects the plurality of first chips and the plurality of electrodes;
a plurality of second stacked components including a plurality of second chips, the plurality of second stacked components being stacked on the surface;
a plurality of second wires that connects the plurality of second chips and the plurality of electrodes; and
a coating resin that covers the surface, the plurality of first stacked components, the plurality of first wires, the plurality of second stacked components, and the plurality of second wires, wherein
the plurality of first stacked components including the plurality of first chips each includes a first top surface facing in the first direction,
the plurality of second stacked components including the plurality of second chips each includes a second top surface facing in the first direction,
a distance between the surface and the second top surface of a farthest one of the plurality of second chips away from the surface is longer than a distance between the surface and the first top surface of a farthest one of the plurality of first chips away from the surface,
the plurality of second stacked components include a first spacer between the surface and a nearest one of the plurality of second chips to the surface,
the first spacer is not connected to the plurality of second wires,
a thickness of the nearest one of the plurality of second chips to the surface is thicker than the farthest one of the plurality of second chips away from the surface, and
a thickness of a nearest one of the plurality of first chips to the surface is thicker than the farthest one of the plurality of first chips away from the surface.

US Pat. No. 10,971,472

METHOD OF LIQUID ASSISTED BONDING

MIKRO MESA TECHNOLOGY CO....

1. A method of liquid assisted bonding, comprising:forming a structure with a liquid layer between an electrode of a device and a contact pad of a substrate and two opposite surfaces of the liquid layer being respectively in contact with the electrode and the contact pad, wherein hydrogen bonds are formed between the liquid layer and at least one of the electrode and the contact pad; and
evaporating the liquid layer to break said hydrogen bonds such that at least one of a surface of the electrode facing the contact pad and a surface of the contact pad facing the electrode is activated so as to assist a formation of a diffusion bonding between the electrode of the device and the contact pad, wherein a contact area between the electrode and the contact pad is smaller than or equal to about 1 square millimeter.

US Pat. No. 10,971,471

METHODS AND SYSTEMS FOR MANUFACTURING SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

1. A semiconductor manufacturing system, comprising:a laser;
a semiconductor assembly including:
a wafer comprising a material that is optically transparent to a beam emitted by the laser, the wafer configured to support a die stack comprising a plurality of semiconductor dies; and
a metal film deposited on the wafer below the die stack and heatable by the beam emitted by the laser; and
a heated bond tip configured to apply heat and pressure to the die stack, wherein the die stack is compressed between the heated bond tip and the metal film, and the plurality of semiconductor dies are thermally bonded by heat emitted by the heated bond tip and the metal film when the metal film is heated by the beam emitted from the laser.

US Pat. No. 10,971,470

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and
a first redistribution portion disposed in a lower portion of the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, at least one first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer,
wherein the first bonding layer and the second bonding layer include first metal pads and second metal pads disposed to correspond to each other and bonded to each other, respectively, and a first bonding insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively,
wherein a top surface and a bottom surface of the first bonding insulating layer are coplanar with top surfaces and bottom surfaces of the first metal pads, respectively, and a top surface and a bottom surface of the second bonding insulating layer are coplanar with top surfaces and bottom surfaces of the second metal pads, respectively.

US Pat. No. 10,971,469

SEMICONDUCTOR DEVICE INCLUDING VARIOUS PERIPHERAL AREAS HAVING DIFFERENT THICKNESSES

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a first semiconductor chip, which has a plurality of first electrodes on a surface of the first semiconductor chip;
a second semiconductor chip, which is disposed to be separated by a gap from the surface of the first semiconductor chip, and which comprises an inner peripheral area that has a plurality of second electrodes connected to each of the plurality of first electrodes on a surface of the second semiconductor chip and an outer peripheral area that surrounds the inner peripheral area and has a thickness thinner than a thickness of the inner peripheral area; and
a sealing resin, which is respectively filled between the surface of the first semiconductor chip and the inner peripheral area, and between the surface of the first semiconductor chip and the outer peripheral area,
wherein the outer peripheral area comprises:
a first outer peripheral area having a thickness thinner than the thickness of the inner peripheral area,
an outermost peripheral area that surrounds the first outer peripheral area and has a thickness thinner than the thickness of the first outer peripheral area, and
a second outer peripheral area, which is located between the inner peripheral area and the first outer peripheral area, and which has a thickness that is thinner than the thickness of the inner peripheral area but is thicker than the thickness of the first outer peripheral area,
the second semiconductor chip has a plurality of wire layers; an uppermost-layer wire, which is disposed as an uppermost layer within the plurality of wire layers disposed on a first insulation layer of the second outer peripheral area, is covered by a second insulation layer formed on the first insulation layer; and a surface of the second insulation layer of the second outer peripheral area is exposed from a third insulation layer formed on the second insulation layer.

US Pat. No. 10,971,468

AUTOMATIC REGISTRATION BETWEEN CIRCUIT DIES AND INTERCONNECTS

3M INNOVATIVE PROPERTIES ...

1. An article comprising:a substrate having a major surface, wherein a pocket and one or more channels are formed on the major surface, and the channels each extend between a first end and a second end thereof, the first end being fluidly connected to the pocket;
a solid circuit die disposed in the pocket, the solid circuit die having one or more contact pads on a surface thereof aligned with the first ends of the channels; and
one or more electrically conductive traces formed in the one or more channels, the electrically conductive traces extending to the first ends of the channels and in direct contact with the contact pads of the solid circuit die,
wherein the one or more electrically conductive traces are layered on a curved meniscus surface of an adhesive layer disposed in the one or more channels.

US Pat. No. 10,971,467

PACKAGING METHOD AND PACKAGE STRUCTURE OF FAN-OUT CHIP

SJ SEMICONDUCTOR (JIANGYI...

1. A packaging method of a fan-out chip, comprising:step 1): providing a first chip with bumps and a second chip without bumps, forming a first dielectric layer on a surface of the second chip, and fabricating through-holes in the first dielectric layer;
step 2): providing a carrier with a bonding layer formed on a surface, and bonding the first chip and the second chip to the bonding layer side by side;
step 3): packing the first chip and the second chip, wherein the bumps of the first chip and the through-holes of the first dielectric layer on the surface of the second chip are exposed after the packing;
step 4): depositing a second dielectric layer covering the first chip and the second chip, patterning a plurality of windows each aligned to one bump of the first chip and one through-hole of the second chip;
step 5): fabricating a metal redistribution layer to fill the plurality of windows, wherein the metal redistribution layer provides electrical connection within the first chip and the second chip, wherein the metal redistribution layer interconnects between the first chip and the second chip; and
step 6): fabricating under-bump metallization layers and a plurality of micro-bumps on the metal redistribution layer.

US Pat. No. 10,971,466

HIGH FREQUENCY MODULE AND COMMUNICATION DEVICE

MURATA MANUFACTURING CO.,...

1. A high frequency module comprising:a high frequency component;
a connection electrode connected to the high frequency component; and
a mounting board on which the high frequency component is mounted, wherein
the mounting board includes
a via conductor having an elongated shape in a plan view of the mounting board,
a first insulating part disposed outside the via conductor, and
one or more second insulating parts disposed inside the via conductor,
the connection electrode and the via conductor are connected while at least partially overlapping one another in the plan view, and
the first insulating part and the one or more second insulating parts are each composed of an insulating material of same kind.

US Pat. No. 10,971,465

DRIVING CHIP, DISPLAY SUBSTRATE, DISPLAY DEVICE AND METHOD FOR MANUFACTURING DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A driving chip, comprising:a substrate comprising a plurality of supporting bumps disposed thereon;
an input area comprising a plurality of input bumps;
an output area comprising a plurality of output bumps; and
an intermediate area;
wherein the plurality of input bumps comprise at least one set of connecting bumps arranged along a first direction, and the plurality of supporting bumps comprise first supporting bumps that are located between adjacent input bumps arranged along the first direction;
wherein the plurality of output bumps comprise at least one set of connecting bumps arranged along the first direction, and the plurality of supporting bumps comprise first supporting bumps that are located between adjacent output bumps arranged along the first direction;
wherein the plurality of supporting bumps further comprise intermediate area supporting bumps that are regularly disposed within the intermediate area;
wherein a distance between one of the first supporting bumps and its adjacent or neighboring input bump or output bump in the first direction is 30 ?m to 40 ?m;
wherein the connecting bumps are higher than the first supporting bumps with respect to the substrate, and a size of each of the first supporting bumps is smaller than a size of a neighboring connecting bump;
wherein the connecting bumps are arranged in rows and connecting wirings are arranged in gaps between the rows; and
wherein for connecting bumps in a same row, a first number of first supporting bumps are arranged between two of the connecting bumps in the same row, a second number of first supporting bumps are arranged between another two of the connecting bumps in the same row, the first number is different from the second number.

US Pat. No. 10,971,464

ELECTRICAL CONNECTION DEVICE AND CHIP MODULE CONNECTION DEVICE

LOTES CO., LTD, Keelung ...

1. An electrical connection device, comprising:an insulating body, provided with a plurality of accommodating holes, wherein each of the accommodating holes is provided with a stopping portion;
a plurality of terminals, correspondingly accommodated in the accommodating holes, wherein each of the terminals has two arm portions and a stopping block located lower than the two arm portions, the two arm portions are located at two opposite sides of the stopping block, an accommodating groove is formed between the two arm portions and is located higher than the stopping block, the stopping portion of a corresponding one of the accommodating holes is located on an upward moving path of the stopping block, a gap is formed between the stopping block and the stopping portion, a top surface of the stopping block has a resisting portion, and the resisting portion is located between the two arm portions; and
a plurality of solder balls, correspondingly accommodated in the accommodating grooves of the terminals respectively, wherein the resisting portion of each of the terminals stops a corresponding one of the solder balls upward.

US Pat. No. 10,971,463

INTERCONNECTION STRUCTURE INCLUDING A METAL POST ENCAPSULATED BY A JOINT MATERIAL HAVING CONCAVE OUTER SURFACE

TAIWAN SEMICONDUCTOR MANU...

15. A semiconductor device, comprising:a first carrier including a first pad and a terminal;
a second carrier including a second pad disposed opposite to the first pad;
a post coupled with and standing on the first pad, wherein the post consists of a metal or a metal alloy;
a joint encapsulating the post and bonding the first pad with the second pad;
a first contact interface between the first pad and the joint, wherein the first contact interface is entirely between the first pad and the joint;
a second contact interface between the first pad and the post, wherein the second contact interface is entirely between the first pad and the post; and
a third contact interface between the joint and the second pad, wherein the third contact interface is entirely between the joint and the second pad,
wherein the first carrier includes a first surface facing the second carrier and a second surface opposite to the first surface, the second contact interface is between the first surface and the second surface, the first pad includes a top surface facing the second carrier and a bottom surface opposite to the top surface, the top surface is entirely between the first surface and the second surface, the first carrier is a silicon substrate, the terminal connects with the first pad through a conductive redistribution layer, and the terminal is offset from the first pad along a direction parallel to the first surface of the first carrier, a wetting angle between an outer surface of the joint and the first pad is less than 90 degree, a wetting angle between the outer surface of the joint and the second pad is less than 90 degree, and the post is separated from the second pad.

US Pat. No. 10,971,462

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Taiwan Semiconductor Manu...

1. A package structure, comprisingan insulating encapsulation;
a first die, a second die and a third die, at least partially covered by the insulating encapsulation and electrically coupled to each other; and
an antenna, located on the insulating encapsulation and electrically coupled to the first die, the second die and the third die, wherein the antenna comprises a first metallic portion and a second metallic portion, the second metallic portion is mechanically separated from the first metallic portion, and the first metallic portion and the second metallic portion work together in a manner of electrical coupling.

US Pat. No. 10,971,461

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A device comprising:a redistribution structure;
a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure;
an antenna structure over the first semiconductor device, wherein the antenna structure comprises a second antenna that is different from the first antenna, wherein the antenna structure comprises an external connection bonded to the first conductive pillar; and
a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.

US Pat. No. 10,971,460

INTEGRATED DEVICES IN SEMICONDUCTOR PACKAGES AND METHODS OF FORMING SAME

Taiwan Semiconductor Manu...

1. A package comprising:an integrated circuit die encapsulated in an encapsulant, wherein the encapsulant is external to the integrated circuit die;
a device over the integrated circuit die, wherein the device overlaps the integrated circuit die in a top-down view, and wherein the device comprises a ground element and a signal line; and
a dielectric feature disposed between the integrated circuit die and the device, wherein a thickness of the dielectric feature is in accordance with an operating bandwidth of the device, wherein the dielectric feature is encapsulated in the encapsulant.

US Pat. No. 10,971,459

HIGH-FREQUENCY MODULE

MURATA MANUFACTURING CO.,...

1. A high-frequency module comprising:a first substrate;
a second substrate facing the first substrate;
a support supporting the first substrate and the second substrate;
a plurality of high-frequency circuit components arranged in an internal space provided by the first substrate, the second substrate and the support, and on both of an uppermost surface of the first substrate and a lowermost surface of the second substrate facing the uppermost surface of the first substrate, the plurality of high-frequency circuit components including a high-frequency amplifier element constituting a high-frequency amplifier circuit; and
a conductor member being arranged between the high-frequency amplifier circuit and a high-frequency circuit component adjacent to the high-frequency amplifier circuit when the first substrate and the second substrate are viewed in a direction perpendicular to the uppermost surface of the first substrate,
wherein the conductor member comprises an upper member, a lower member, a right member, and a left member when viewed in a direction parallel to the uppermost surface of the first substrate, an entire uppermost surface of the upper member of the conductor member is in direct contact with the lowermost surface of the second substrate, an entire lowermost surface of the lower member of the conductor member is co-planer with a lowermost surface the first substrate,
an entire inner surface of the right member of the conductor member is parallel to an entire inner surface of the left member of the conductor member when viewed in the direction parallel to the uppermost surface of the first substrate,
the high-frequency amplifier circuit is completely surrounded by the conductor member when the first substrate and the second substrate are viewed in the direction parallel to the uppermost surface of the first substrate, and
the conductor member is coupled to a ground.

US Pat. No. 10,971,458

COMPENSATION NETWORK FOR HIGH SPEED INTEGRATED CIRCUITS

CREDO TECHNOLOGY GROUP LI...

1. An integrated circuit (IC) that comprises:a pin configured to connect to a substrate pad via a solder bump having a parasitic capacitance;
an inductor that couples the pin to a transmit or receive circuit;
a first electrostatic discharge (ESD) protection device electrically connected to a pin end of the inductor; and
a second ESD protection device electrically connected to a circuit end of the inductor,
wherein the first ESD protection device has a first capacitance that sums with the parasitic capacitance to equal a total capacitance coupled to the circuit end of the inductor.

US Pat. No. 10,971,457

SEMICONDUCTOR DEVICE COMPRISING A COMPOSITE MATERIAL CLIP

Infineon Technologies AG,...

1. A semiconductor device, comprisinga first semiconductor die comprising a first surface, a second surface opposite to the first surface, and a contact pad disposed on the first surface;
a further contact pad spaced apart from the semiconductor die;
a clip comprising a first layer of a first metallic material and a second layer of a second metallic material different from the first metallic material; wherein
the first layer of the clip is connected with the contact pad, and the second layer of the clip is connected with the further contact pad.

US Pat. No. 10,971,456

ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. An electronic component comprising:a multilayer body including a first insulator and a second insulator having a higher resistivity than the first insulator;
a metal conductor positioned between the first insulator and the second insulator and including a predetermined end surface positioned at least near an end surface of the multilayer body;
a plating film provided on the predetermined end surface of the metal conductor in a state extending out in a direction covering an end surface of the first insulator by a larger distance than in a direction covering an end surface of the second insulator; and
an outer conductor provided on an outer side of the plating film and electrically connected to the metal conductor through the plating film.

US Pat. No. 10,971,455

GROUND SHIELD PLANE FOR BALL GRID ARRAY (BGA) PACKAGE

QUALCOMM Incorporated, S...

1. An integrated circuit (IC) package, comprising:a substrate;
an IC disposed above the substrate; and
a shielding layer coupled to a layer of the substrate via a support element configured to support the shielding layer above the substrate such that the shielding layer is disposed at a lateral side of the IC and with a height of an upper surface of the shielding layer above the substrate being lower than a height of an upper surface of the IC above the substrate.

US Pat. No. 10,971,454

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A semiconductor package, comprising:a core structure having a frame having a cavity penetrating first and second surfaces of the frame opposing each other, a wiring structure penetrating the frame to connect the first and second surfaces to each other, a first semiconductor chip disposed in the cavity and having a first surface having a first contact and a second surface opposing the first surface of the first semiconductor chip and having a second contact, a first encapsulant encapsulating the first semiconductor chip and disposed on the first and second surfaces of the frame, and a through-hole penetrating portions of the first encapsulant and the frame, wherein the core structure has first and second surfaces corresponding to the first and second surfaces of the frame, respectively;
a first wiring layer disposed on the first surface of the core structure and penetrating the first encapsulant to connect to the first contact of the first semiconductor chip;
a second wiring layer disposed on the second surface of the core structure and penetrating the first encapsulant to connect to the second contact of the first semiconductor chip;
a chip component disposed in the through-hole of the core structure and having a connection terminal;
a connection structure disposed on the first surface of the core structure and having a redistribution layer connected to the connection terminal of the chip component and to the first wiring layer; and
a second encapsulant disposed on the second surface of the core structure and encapsulating the chip component,
wherein the chip component includes at least one of a chip antenna and a second semiconductor chip.

US Pat. No. 10,971,453

SEMICONDUCTOR PACKAGING WITH HIGH DENSITY INTERCONNECTS

Intel Corporation, Santa...

1. A semiconductor package comprising:a substrate comprising:
a plurality of conducting layers and dielectric layers;
a first active silicon die disposed on an external surface of the substrate;
a second active silicon die at least partially embedded within the substrate;
a first interconnect region formed from a plurality of interconnects between the first active silicon die and the second active silicon die;
a second interconnect region formed from a plurality of interconnects between the first active silicon die and the substrate; and
a third interconnect region formed from a plurality of interconnects between the second active silicon die and the substrate,
wherein a density of the interconnects of the first interconnect region is greater than a density of the interconnects of at least one of the second interconnect region and the third interconnect region.

US Pat. No. 10,971,452

SEMICONDUCTOR PACKAGE INCLUDING ELECTROMAGNETIC INTERFERENCE SHIELDING LAYER

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a base substrate;
first to Nth sub packages sequentially stacked over the base substrate, wherein each of the N sub packages comprises a semiconductor die and a bridge die disposed on at least one side of the semiconductor die and electrically connected to the semiconductor die, where N is a natural number equal to or more than two (2);
a molding layer formed on the base substrate, wherein the molding layer covers the first to Nth sub packages and leaves an Nth conductive post included in the Nth sub package exposed; and
a shielding layer formed on the molding layer, wherein the shielding layer is electrically connected to the exposed Nth conductive post,
wherein the first to (N?1)th sub packages further comprise first to (N?1)th pluralities of conductive posts disposed on the first to (N?1)th bridge dies of the first to (N?1)th sub packages, respectively, wherein the first to (N?1)th pluralities of conductive posts electrically connect each of the first to (N?1)th bridge dies, respectively, to the bridge die of the sub package disposed thereon among the second to Nth sub packages,
wherein the Nth conductive post of the Nth sub package electrically connects the Nth bridge die with the shielding layer and electrically connects with conductive posts among the first to (N?1)th pluralities of conductive posts to provide a ground providing path through the first to Nth bridge dies of the first to Nth sub packages.

US Pat. No. 10,971,451

INTERCONNECT STRUCTURE HAVING NANOCRYSTALLINE GRAPHENE CAP LAYER AND ELECTRONIC DEVICE INCLUDING THE INTERCONNECT STRUCTURE

Samsung Electronics Co., ...

1. An interconnect structure comprising:a dielectric layer including at least one trench;
a conductive wiring filling an inside of the at least one trench; and
a cap layer on at least one surface of the conductive wiring, the cap layer including nanocrystalline graphene, the nanocrystalline graphene including nano-sized crystals,
an upper surface of the dielectric layer being level with an upper surface of the conductive wiring, a lower surface of the cap layer, or both the upper surface of the conductive wiring and the lower surface of the cap layer, wherein
a ratio of carbon having an sp2 bonding structure to total carbon in the nanocrystalline graphene is in a range from about 50% to about 99%,
the nanocrystalline graphene comprises hydrogen of 1 at % to 20 at %, and
a density of the nanocrystalline graphene is 1.6 g/cc to 2.1 g/cc.

US Pat. No. 10,971,450

HEXAGONALLY ARRANGED CONNECTION PATTERNS FOR HIGH-DENSITY DEVICE PACKAGING

Avago Technologies Intern...

1. A connection pattern for a semiconductor package comprising:a plurality of connective elements, arranged in a hexagonal pattern, comprising:
a plurality of power supply elements;
a plurality of ground elements;
one or more pairs of transmit elements; and
one or more pairs of receive elements, each of which is separated from other pairs of receive elements and from all of the one or more pairs of transmit elements by one or more of the ground elements, the power supply elements or both.

US Pat. No. 10,971,449

SEMICONDUCTOR DEVICE WITH METALLIZATION STRUCTURE ON OPPOSITE SIDES OF A SEMICONDUCTOR PORTION

INFINEON TECHNOLOGIES AG,...

1. A method of manufacturing a semiconductor device, the method comprising:forming a semiconductor layer comprising a device region of the semiconductor device, wherein a layer thickness of the semiconductor layer is at most 50 ?m;
forming a first metallization structure on a first surface of the semiconductor layer, the first metallization structure comprising a first copper region with a first thickness;
thinning a second surface of the semiconductor layer to expose a third surface, the second surface being opposite the first surface;
forming a second metallization structure on the third surface of the semiconductor layer, wherein the second metallization structure comprises a second copper region with a second thickness,
wherein a total thickness, which is a sum of the first thickness and the second thickness, deviates from the semiconductor layer thickness by not more than 20% and a difference between the first thickness and the second thickness is not more than 20% of the total thickness;
forming a peripheral device region of the semiconductor device between a central device region of the semiconductor device and a lateral outer surface of the semiconductor layer, wherein a lateral outer surface of the first metallization structure is within the central device region, and wherein a lateral outer surface of the second metallization structure is within the peripheral device region; and
forming an intermediate region between the first metallization structure and the first surface of the semiconductor layer that is absent from the peripheral device region.

US Pat. No. 10,971,448

SWITCHING DEVICE

MURATA MANUFACTURING CO.,...

1. A switching device comprising:a plurality of layers including first to third layers laminated in sequence on or above a principal surface of a substrate;
a plurality of input terminals;
a plurality of output terminals;
a plurality of switching circuits; and
a plurality of channels, each of the channels electrically connecting one of the plurality of input terminals and one of the plurality of output terminals via one of the plurality of switching circuits,
wherein the plurality of channels include a first channel and a second channel intersecting with each other when the principal surface of the substrate is seen in a plan view,
in an intersection area where the first and second channels intersect with each other, the first channel is disposed on the first layer, the second channel is disposed on the third layer, and none of the plurality of channels is disposed on the second layer, and
the first channel is disposed on a layer, which is adjacent to neither a layer on which the second channel is disposed nor a layer which is closest to the substrate, among the plurality of layers.

US Pat. No. 10,971,447

BEOL ELECTRICAL FUSE

International Business Ma...

1. A structure comprising:an interconnect level including at least one electrically conductive structure embedded in an interconnect dielectric material layer;
a dielectric material layer having a via opening located on the interconnect level, wherein the via opening physically exposes a surface of the at least one electrically conductive structure;
an electrode structure present in at least the via opening, wherein a fuse element is located beneath and along sidewalls of the electrode structure that is present in the via opening, and wherein the electrode structure is composed of a material having a higher electromigration (EM) resistance than the fuse element; and
a metal-containing structure located directly on at least the electrode structure.

US Pat. No. 10,971,446

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method comprising:forming a redistribution structure on a carrier;
attaching an integrated passive device on a first side of the redistribution structure;
after attaching the integrated passive device, attaching an interconnect structure to the first side of the redistribution structure, the integrated passive device interposed between the redistribution structure and the interconnect structure;
depositing an underfill material between the interconnect structure and the redistribution structure; and
attaching a semiconductor device on a second side of the redistribution structure that is opposite the first side of the redistribution structure.

US Pat. No. 10,971,445

COMPARISON CIRCUIT INCLUDING INPUT SAMPLING CAPACITOR AND IMAGE SENSOR INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A comparison circuit comprising:an amplifier configured to receive a pixel signal and a ramp signal;
a first pixel capacitor connected to the amplifier through a first floating node and configured to transmit the pixel signal;
a first ramp capacitor connected to the amplifier through a second floating node different from the first floating node and configured to transmit the ramp signal; and
a second pixel capacitor connected in parallel to the first pixel capacitor; and
a second ramp capacitor connected in parallel to the first ramp capacitor,
wherein the second pixel capacitor comprises a first-second pixel capacitor formed between a first shield line in a first metal layer and the first floating node in a second metal layer different from the first metal layer, and
wherein the first shield line is configured to receive the pixel signal,
wherein the second pixel capacitor further comprises a second-second pixel capacitor formed between a second shield line in the second metal layer and the first floating node.

US Pat. No. 10,971,444

VOLTAGE NOISE REDUCTION OF POWER DELIVERY NETWORKS FOR INTEGRATED CIRCUITS

Intel Corporation, Santa...

1. An electronic apparatus, comprising:a first inductor, wherein the first inductor is a segment of a power rail of a first power delivery network (PDN) that has a first capacitance with a first voltage noise; and
a second inductor, wherein the second inductor is a segment of a power rail of a second PDN, the second PDN has a second capacitance with a second voltage noise, wherein the first inductor and the second inductor form a magnetically coupled inductor, and wherein
the first PDN includes an impedance induced by the magnetically coupled inductor to reduce the first voltage noise to a third voltage noise.

US Pat. No. 10,971,443

PACKAGES WITH SI-SUBSTRATE-FREE INTERPOSER AND METHOD FORMING SAME

Taiwan Semiconductor Manu...

9. A package comprising:a first die bonded to a second die, wherein the first die and the second die are encapsulated by a first dielectric material;
a third die encapsulated by the first dielectric material;
a plurality of stacked dies in the first dielectric material and a second dielectric material, wherein bottom surfaces of the second die, the third die, and the plurality of stacked dies are at a same level; and
a blank die bonded to a first substrate of the first die and a second substrate of the third die.

US Pat. No. 10,971,442

SEMICONDUCTOR DEVICE HAVING VIA SIDEWALL ADHESION WITH ENCAPSULANT

Taiwan Semiconductor Manu...

1. A method, comprising:forming a die, the die comprising a pad and a passivation layer over the pad;
forming a first opening through the passivation layer;
depositing a resist layer over the die;
patterning the resist layer to form a second opening aligned to the first opening;
forming a via in the second opening, the via having a first co-efficient of thermal expansion (CTE);
forming a solder cap on the via, wherein a first material of the solder cap flows to a sidewall of the via;
etching the solder cap to remove the first material from an upper surface of the via, and encapsulating the via in a first encapsulant, wherein the first encapsulant has a second CTE and a curing temperature, wherein a ratio of the second CTE and first CTE is less than 2.5:1 or the first curing temperature is less than 250° C.

US Pat. No. 10,971,441

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package comprising:a chip and a molding compound adjacent to each other;
a first polymer layer and a second polymer layer that are stacked on the chip and the molding compound, wherein the second polymer layer overlies the first polymer layer;
a first interconnect structure between the first and second polymer layers;
a capacitor on the second polymer layer and protruding through the second polymer layer to the first interconnect structure, wherein the capacitor comprises a lower electrode, a dielectric layer overlying the lower electrode, and an upper electrode overlying the dielectric layer;
a barrier layer overlying and independent of the upper electrode, wherein the barrier layer is conductive;
a metal layer overlying the barrier layer, wherein the capacitor, the barrier layer, and the metal layer collectively define a first common sidewall and collectively define a second common sidewall on an opposite side of the capacitor as the first common sidewall;
an isolation coating covering the first and second polymer layers and the metal layer, wherein the isolation coating directly contacts a top surface of the metal layer continuously from the first common sidewall to the second common sidewall; and
a conductive bump in an opening defined by the isolation coating and level with the capacitor.

US Pat. No. 10,971,440

SEMICONDUCTOR PACKAGE HAVING AN IMPEDANCE-BOOSTING CHANNEL

Intel Coropration, Santa...

1. A semiconductor package substrate, comprising:a transmitter bump pad disposed along a first vertical axis;
a receiver bump pad disposed along a second vertical axis laterally offset from the first vertical axis; and
an impedance-boosting channel extending between the transmitter bump pad and the receiver bump pad, wherein the impedance-boosting channel includes a first impedance-boosting segment having a first arc segment extending around the first vertical axis, and a second impedance-boosting segment having a second arc segment extending around the second vertical axis, wherein the first impedance-boosting segment and the second impedance-boosting segment are in the semiconductor package substrate, wherein the semiconductor package substrate is a single continuous semiconductor package substrate.

US Pat. No. 10,971,439

BALL GRID ARRAY UNDERFILLING SYSTEMS

HAMILTON SUNDSTRAND CORPO...

1. A ball grid array (BGA) assembly, comprising:a component substrate having at least one underfill channel defined therethrough providing fluidic communication between a first side of the component substrate and a second side of the component substrate;
a plurality of pads or leads exposed on the second side and configured to be soldered to a mating PCB;
a cover mounted to the component substrate defining a reservoir cavity between the first side and the cover; and
an underfill material disposed within the reservoir cavity such that the underfill material can flow through the at least one underfill channel to a gap defined between the second side and the mating PCB when the component substrate is being soldered to the mating PCB.

US Pat. No. 10,971,438

CHIP-ON FILM AND DISPLAY DEVICE INCLUDING THE SAME

LG DISPLAY CO., LTD., Se...

1. A display device comprising:a flexible substrate;
a display portion positioned on the flexible substrate, the display portion including an organic light emitting diode;
a pad portion positioned at one edge of the flexible substrate such that one edge of the pad portion is aligned with the one edge of the flexible substrate; and
a chip-on film connected to the pad portion through an anisotropic conductive film,
wherein the chip-on film includes:
a first base film disposed not to overlap with the flexible substrate;
a second base film positioned on the first base film;
a film pad portion positioned on at least one side of the second base film to overlap with the pad portion and exposed to the outside of the first base film; and
a coating layer positioned on one surface of the first base film near the anisotropic conductive film, the coating layer being made of a material of the same kind as the anisotropic conductive film,
wherein a thickness of the first base film is greater than a thickness of the coating layer,
wherein the coating layer is coated starting from an edge of the first base film adjacent to the film pad portion to enable the anisotropic conductive film to spread out by wettability between the coating layer and the anisotropic conductive film while the anisotropic conductive film is pressed, and cover the coating layer,
wherein the coating layer is disposed not to overlap with the flexible substrate, and
wherein the anisotropic conductive film is attached to lateral side surfaces of the pad portion and the flexible substrate located at the aligned edges of the pad portion and the flexible substrate.

US Pat. No. 10,971,437

CHIP PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Silergy Semiconductor Tec...

1. A chip package structure, comprising:a) a lead frame having a plurality of pins, a first die pad, and a second die pad, wherein said plurality of pins comprises a first set of pins comprising a pin extension on a first side of said lead frame, and a second set of pins on a second side of said lead frame, wherein said first side is opposite to said second side, said first die pad is connected to at least one of said second set of pins, and said second die pad is connected to at least one of said first set of pins;
b) a first die and a second die, wherein a first surface of said first die is installed on said first die pad, and a first surface of said second die is installed on said second die pad;
c) a plurality of pads installed on a second surface of said first die and a second surface of said second die;
d) a plurality of bonding wires comprising a first set of bonding wires with each having one terminal connected to pads of said first die, and a second set of bonding wires with each having one terminal connected to pads of said second die for connectivity between said first die and said second die, and between said plurality of pins and said second die;
e) wherein said plurality of pins of said lead frame and said first die pad are located on a main plane, a plane of said second die pad is lower than said main plane, and at least one bonding wire of said first set of bonding wires spans said second die and connects to said pin extension; and
f) wherein at least a portion of said second die pad extends below said first die pad such that said first die partially overlaps said second die, and said pin extension extends toward the inside of the chip package structure on said main plane and partially exceeds said second die.

US Pat. No. 10,971,436

MULTI-BRANCH TERMINAL FOR INTEGRATED CIRCUIT (IC) PACKAGE

Infineon Technologies AG,...

1. A method of manufacturing an integrated circuit (IC) package, comprising:positioning an IC chip within a package housing of the IC package;
configuring a plurality of terminals to extend from the package housing,
wherein at least one of the plurality of terminals includes a multi-branch terminal, and
wherein branches, of the multi-branch terminal, are included within the package housing; and
bonding a branch, of the multi-branch terminal, to another terminal of the plurality of terminals via a passive bonding.

US Pat. No. 10,971,435

SEMICONDUCTOR DEVICE INCLUDING BONDING PAD AND BOND WIRE OR CLIP

Infineon Technologies AG,...

1. A semiconductor device, comprising:a bonding pad comprising:
a base portion having a base layer, and
a main surface having a bonding region;
a bond wire or clip bonded to the bonding region; and
a supplemental structure in direct contact with the base portion and alongside the bonding region, wherein the supplemental structure directly adjoins the bond wire or clip or is horizontally spaced apart from the bond wire or clip, and wherein a volume-related specific heat capacity of the supplemental structure is higher than a volume-related specific heat capacity of the base layer,
wherein the base layer comprises aluminum or an aluminum alloy.

US Pat. No. 10,971,434

LEAD FRAME PACKAGE HAVING CONDUCTIVE SURFACE WITH INTEGRAL LEAD FINGER

Silanna Asia Pte Ltd, Si...

1. A device comprising:a lead frame having a body with a top surface and a bottom surface and a plurality of lead fingers, each lead finger having a first end and a second end, the first end being attached to the body and the second end being in a different plane than the first end and the body;
a semiconductor die coupled to the bottom surface of the body;
a first flag being a first exposed portion of the top surface of the body of the lead frame and integral with the first end of a first lead finger of the plurality of lead fingers, wherein the first flag and the first lead finger are a continuous material;
a second flag being a second exposed portion of the top surface of the body of the lead frame and integral with the first end of a second lead finger of the plurality of lead fingers, wherein the second flag and the second lead finger are a continuous material; and
an encapsulant covering the semiconductor die, the bottom surface of the body, the first end of the plurality of lead fingers and a portion of the top surface of the body, excluding the first flag and the second flag, wherein the first flag and the second flag are separated and electrically isolated from one another by the encapsulant.

US Pat. No. 10,971,433

SURFACE MOUNTED TYPE LEADFRAME AND PHOTOELECTRIC DEVICE WITH MULTI-CHIPS

KAISTAR LIGHTING (XIAMEN)...

1. A surface mounted type leadframe, comprising:a conductive base, comprising at least three connecting pads, wherein the at least three connecting pads are mutually spaced apart from each other, first surfaces of the at least three connecting pads are configured to form die bonding regions, second surfaces of the at least three connecting pads opposite to the first surfaces are configured to form soldering regions, the connecting pads comprise at least one anode connecting pad and at least two cathode connecting pads; and
an insulating material layer, covering at least a portion of the first surfaces, surrounding the die bonding regions, and being filled in gaps between each two adjacent connecting pads;
wherein the at least three connecting pads comprise even connecting pads, a half of the even connecting pads are anode connecting pads and the other half are cathode connecting pads.

US Pat. No. 10,971,432

SEMICONDUCTOR DEVICE INCLUDING A THROUGH WIRING AREA

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a peripheral circuit area disposed on a first substrate and including one or more circuit devices;
a memory cell area disposed on a second substrate, over the peripheral circuit area, and including a plurality of gate electrodes spaced apart from each other and stacked vertically on the second substrate; and
a through wiring area including a through contact plug and an insulating area surrounding the through contact plug, the through contact plug extended in a first direction through the memory cell area and the second substrate and electrically connecting the memory cell area to the circuit devices,
wherein the insulating area includes:
a first insulating layer penetrating through the second substrate and disposed in parallel to the second substrate,
a plurality of second insulating layers extended in the first direction, over the peripheral circuit area, and
a third insulating layer having a vertical extension portion and a plurality of horizontal extension portions, the vertical extension portion being disposed between the second insulating layers and extended in the first direction, and the plurality of horizontal extension portions being extended in a second direction parallel to a top surface of the second substrate from a side surface of the vertical extension portion to contact the second insulating layers,
wherein the vertical extension portion and the plurality of horizontal extension portions consist of an insulating material,
wherein each of the plurality of horizontal extension portions is positioned on a same level as the plurality of gate electrodes to separate the plurality of gate electrodes horizontally, and
wherein the plurality of horizontal extension portions continuously extend from the vertical extension portion to form a multiple-cross shape.

US Pat. No. 10,971,431

SEMICONDUCTOR DEVICE, COOLING MODULE, POWER CONVERTING DEVICE, AND ELECTRIC VEHICLE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a first cooling device including a plurality of first flow channels through which a fluid is to flow, between a first main surface and a second main surface opposed to each other;
a second cooling device including a plurality of second flow channels through which a fluid is to flow, between a third main surface and a fourth main surface parallel to the first main surface;
a semiconductor element interposed between the first main surface and the third main surface facing each other; and
a control terminal penetrating from the third main surface to the fourth main surface in a terminal-penetrating region provided at a position between adjacent second flow channels among the plurality of second flow channels, and electrically connected to a control electrode of the semiconductor element.

US Pat. No. 10,971,430

SEMICONDUCTOR DEVICE

KYOCERA Corporation, Kyo...

14. A semiconductor device, comprising at least one cooling unit, each of the at least one cooling unit comprising:at least one circuit unit, each of the at least one circuit unit comprising:
a heat sink layer;
a wiring layer; and
a semiconductor element disposed between the heat sink layer and the wiring layer;
a first flow path member comprised of an insulating material; and
a second flow path member comprised of an insulating material, each of the at least one circuit unit being disposed between the first flow path member and the second flow path member,
the wiring layer of a respective at least one circuit unit being directly adhered to only one of the first flow path member and the second flow path member,
the heat sink layer of the respective at least one circuit unit being directly adhered to only the other one of the first flow path member and the second flow path member,
wherein the at least one circuit unit comprises:
a first circuit unit; and
a second circuit unit adjacent to the first circuit unit,
wherein the heat sink layer of the first circuit unit is disposed towards the first flow path member, the wiring layer of the first circuit unit is disposed towards the second flow path member, the heat sink layer of the second circuit unit is disposed towards the second flow path member, and the wiring layer of the second circuit unit is disposed towards the first flow path member.

US Pat. No. 10,971,429

METHOD FOR FORMING A SEMICONDUCTOR PACKAGE

SEMICONDUCTOR COMPONENTS ...

1. A method of forming a semiconductor package comprising:coupling a plurality of die to a non-electrically conductive layer;
coupling the non-electrically conductive layer to a metal sheet;
bonding a plurality of wires to a first side of each die;
bonding the plurality of wires to the metal sheet;
applying a mold compound over each die and the plurality of wires;
exposing an end of each wire of the plurality of wires and the non-electrically conductive layer through removing the metal sheet; and
singulating the mold compound to form a plurality of semiconductor packages;
wherein each semiconductor package of the plurality of semiconductor packages comprises a portion of the non-electrically conductive layer.

US Pat. No. 10,971,428

SEMICONDUCTOR BASEPLATES

SEMICONDUCTOR COMPONENTS ...

16. A baseplate comprising:a planar portion comprising a plurality of recesses therein, the planar portion further comprising a first material; and
a plurality of pegs wherein each peg of the plurality of pegs is configured to fit within each recess of the plurality of recesses, the plurality of pegs further comprising a second material;
wherein each peg of the plurality of pegs is configured to directly contact a bonding material, the bonding material configured to couple to a substrate.

US Pat. No. 10,971,427

HEATSINK FOR INFORMATION HANDLING SYSTEM

Dell Products L.P., Roun...

1. An apparatus, comprising:a heatsink comprising:
an opening configured to receive a movable heatsink insert;
a hole in the heatsink extending from the opening through the heatsink to a first surface on the heatsink opposite from the opening; and
a seal coupled to the heatsink within the opening, wherein the seal is configured to form an enclosed space in the opening at an exit of the hole for containing a fluid between the movable heatsink insert and the heatsink, wherein the enclosed space is defined by the seal, the removable heatsink insert, and a second surface on the heatsink facing the movable heatsink insert.

US Pat. No. 10,971,426

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first package comprising a first substrate and a first semiconductor chip;
a second package arranged on the first package, the second package comprising a second substrate and a second semiconductor chip;
a first solder ball and a supporter layer arranged between the first package and the second package; and
a dam arranged between the first package and the second package, the dam being in contact with sidewalls of the supporter layer,
wherein the dam completely surrounds the supporter layer, when viewed in plan view, and
wherein a bottom surface of the first solder ball is at a higher vertical level than a top surface of the first semiconductor chip.

US Pat. No. 10,971,425

SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

17. A semiconductor device, comprising:a circuit substrate;
a chip package disposed on and electrically connected to the circuit substrate, the chip package comprising a pair of first parallel sides and a pair of second parallel sides shorter than the pair of first parallel sides; and
a stiffener ring disposed on the circuit substrate, the stiffener ring comprising a ring body and a plurality of stiffener ribs surrounded by the ring body, wherein the ring body comprises first stiffener portions extending along a first direction substantially parallel with the pair of first parallel sides and second stiffener portions extending along a second direction substantially parallel with the pair of second parallel sides, and the stiffener ribs extend along the first direction substantially parallel with the pair of first parallel sides.

US Pat. No. 10,971,424

POWER MODULE AND POWER CONVERTOR

Mitsubishi Electric Corpo...

1. A power module comprising:a recessed base plate having a hollow portion, the hollow portion of the base plate has a bottom surface and a side surface, the side surface of the hollow portion is tapered with an upper end side slanted at an angle toward an outer peripheral side, and an outer peripheral portion of the base plate is tapered with a narrowed upper end side;
at least one insulating substrate disposed in the hollow portion of the base plate;
at least one semiconductor chip mounted on the at least one insulating substrate; and
a sealing resin for sealing a surface of the hollow portion side of the base plate, the at least one insulating substrate, and the at least one semiconductor chip, the sealing resin directly contacting and adhering to an inner surface of the recessed based plate defining the hollow portion.

US Pat. No. 10,971,422

SEMICONDUCTOR DIE ASSEMBLY HAVING A HEAT SPREADER THAT EXTENDS THROUGH AN UNDERLYING INTERPOSER AND RELATED TECHNOLOGY

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:an interposer comprising a substrate material having a first side surface, a second side surface, an opening extending from the first side surface to the second side surface defining an annulus through the substrate material, a first die region at one side of the annulus, and a second die region at a second side of the annulus, wherein a portion of the substrate material extends between the first and second die regions;
a first semiconductor die electrically coupled to the first side of the interposer;
a second semiconductor die under the interposer and at least partially aligned with the opening through the interposer; and
a heat spreader having a first portion and a second portion, the first portion extending through the opening of the interposer and being thermally attached to the second semiconductor die, and the second portion extending laterally with respect to the first portion of the heat spreader and being thermally attached to the first semiconductor die.

US Pat. No. 10,971,421

GASKET FOR ELECTRICALLY CONDUCTIVE THERMAL INTERFACE MATERIAL OVER A BARE DIE PACKAGE

Dell Products L.P., Roun...

1. An information handling system, comprising:a substrate including a plurality of exposed electrical components on a top surface of the substrate;
a bare die positioned on the top surface of the substrate;
a gasket positioned on the top surface of the substrate, the gasket is non-electrically conductive; and
an electrically conductive thermal interface material (TIM) positioned on a top surface of the bare die and extending beyond the bare die such that at least a portion of the electrically conductive TIM is in superimposition with the exposed electrical components on the top surface of the substrate, wherein a top surface of the gasket and a top surface of the electrically conductive TIM are substantially flush, wherein the top surface of the electrically conductive TIM and the top surface of the gasket are opposite the top surface of the substrate,
wherein the gasket is in superimposition with the substrate and the portion of the electrically conductive TIM that extends beyond the bare die is in superimposition with the gasket such that the gasket is i) positioned between the electrically conducive TIM that extends beyond the bare die and the exposed electrical components on the top surface of the substrate and ii) is in contact with the bare die such that the gasket inhibits contact between the electrically conductive TIM that extends beyond the bare die and the exposed electrical components that are in superimposition with the electrically conductive TIM.

US Pat. No. 10,971,420

METHOD OF FORMING A THERMAL SHIELD IN A MONOLITHIC 3-D INTEGRATED CIRCUIT

Samsung Electronics Co., ...

1. A monolithic three-dimensional integrated circuit comprising:a first device;
a second device on the first device; and
a thermal shield stack between the first device and the second device, the thermal shield stack comprising a thermal retarder portion having a low thermal conductivity in a vertical direction, and a thermal spreader portion having a high thermal conductivity in a horizontal direction,
wherein the thermal shield stack comprises only dielectric materials.

US Pat. No. 10,971,419

METHOD AND APPARATUS FOR REDUCING NOISE ON INTEGRATED CIRCUIT USING BROKEN DIE SEAL

pSemi Corporation, San D...

1. A die seal formed on an integrated circuit chip, the die seal comprising:(a) a plurality of conductor strips formed on insulating layers of the integrated circuit chip fabricated on a wafer, the conductor strips forming the die seal in proximity to a perimeter of the chip, at least two of the conductor strips broken by at least one angled slot, each such angled slot defining a head of a first of the broken conductor strips on one side of the angled slot and a horizontally adjacent tail of a second of the broken conductor strips on the other side of the angled slot, the angled slots electrically isolating each head from the horizontally adjacent tail;
(b) a plurality of conductive connection vias, each providing electrical and mechanical coupling from a first of the plurality of conductor strips to at least a second of the plurality of conductor strips, the at least a second of the plurality of conductor strips being vertically adjacent to the first of the plurality of conductor strips.

US Pat. No. 10,971,418

PACKAGING STRUCTURES WITH IMPROVED ADHESION AND STRENGTH

SKYWORKS SOLUTIONS, INC.,...

1. A method of packaging an electronic device, the method comprising:depositing a layer of temporary bonding material onto a first substrate;
depositing a layer of photosensitive polymer onto the temporary bonding material;
masking at least a portion of the layer of photosensitive polymer to define an unmasked portion and a masked portion of the photosensitive polymer, the unmasked portion of the photosensitive polymer defining at least a portion of at least one support structure;
performing at least a partial cure of the unmasked portion of the layer of photosensitive polymer;
developing the masked portion of the layer of photosensitive polymer;
attaching a second substrate to the unmasked portion of the photosensitive polymer, the second substrate including an electronic device and an encapsulation structure having a wall surrounding the electronic device, attaching the second substrate to the unmasked portion of the photosensitive polymer including aligning the at least one support structure with the encapsulation structure; and
separating the first substrate from the unmasked portion of the layer of photosensitive polymer.

US Pat. No. 10,971,417

3D STACKED-CHIP PACKAGE

Taiwan Semiconductor Manu...

1. A package, comprising:a first die bonded to a second die with a dielectric-to-dielectric bond;
a first molding compound over the first die and surrounding the second die;
a first via extending through and electrically isolated from a second semiconductor substrate of the second die, the first via extends from a top surface of the first molding compound through a bottom surface of the first molding compound to contact a first conductive pad of the first die; and
a first spacer interposed between the second semiconductor substrate and the first via, the first spacer extends into the first molding compound between the first molding compound and the first via.

US Pat. No. 10,971,416

PACKAGE POWER DELIVERY USING PLANE AND SHAPED VIAS

Intel Corporation, Santa...

1. An electrical package comprising:a first package layer;
a plurality of signal lines with a first thickness formed on the first package layer; and
a power plane with a second thickness formed on the first package layer, wherein the second thickness is greater than the first thickness, and wherein the power plane surrounds one or more of the plurality of signal lines, and wherein a bottom surface of the power plane is substantially coplanar with bottom surfaces of the plurality of signal lines.

US Pat. No. 10,971,415

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE, SEMICONDUCTOR MODULE, AND POWER CONVERSION DEVICE

HITACHI POWER SEMICONDUCT...

1. A semiconductor device comprising:a semiconductor chip including a semiconductor material having a bandgap larger than a bandgap of silicon; and
a sealing member to seal the semiconductor chip;
wherein
the semiconductor chip includes an insulation member formed on a surface of the semiconductor substrate in side view and having a dielectric breakdown field strength higher than the sealing member,
a side surface of the semiconductor chip includes
a first region including a first corner;
a second region including a second corner; and
a third region interposed between the first region and the second region, and
a minimum film thickness of the insulation member in the third region t1 is greater than a maximum film thickness of the insulation member in the first region t2 such that t2

US Pat. No. 10,971,414

SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor chip;
an external connecting terminal having a flat plate shape, the external connecting terminal including a front surface having an exposure region and being electrically connected to the semiconductor chip, and a rear surface opposite to the front surface;
a case including a frame portion and a terminal disposition portion, the frame portion having an inner wall surface surrounding an open area in which the semiconductor chip is disposed, the terminal disposition portion projecting from the inner wall surface toward the open area and having a disposition surface thereof, the external connecting terminal penetrating through the frame portion from an outside of the case toward the inner space, a rear surface side of the external connecting terminal being embedded in the terminal disposition portion from the disposition surface thereof, the exposure region of the front surface of the external connecting terminal being exposed from the disposition surface of the terminal disposition portion; and
a sealing member fixedly encapsulate the semiconductor chip in the open area, wherein
the exposure region of the external connecting terminal has a pair of opposite sides parallel to each other in a direction from the inner wall surface toward the inner space, and
at an area facing at least part of the opposite sides of the exposure region, the disposition surface is located between the front surface and the rear surface of the external connecting terminal in a thickness direction thereof, to have a level difference to the front surface of the external connecting terminal.

US Pat. No. 10,971,413

PLASMA PROCESSING APPARATUS AND CONTROL METHOD

TOKYO ELECTRON LIMITED, ...

1. A plasma processing apparatus comprising:a microwave transmitter configured to radiate microwaves output from a microwave power source into a processing container, wherein the microwave transmitter includes:
an antenna configured to radiate the microwaves;
a microwave transmitting member formed of a dielectric material and facing the processing container configured to transmit the microwaves radiated from the antenna, and form an electric field for generating surface wave plasma by the microwaves;
a sensor provided in the microwave transmitter and configured to monitor electron temperature of the generated plasma; and
a controller configured to determine a plasma ignition state based on the electron temperature of the plasma monitored by the sensor,
wherein a tip of the sensor is embedded in the microwave transmitting member without being exposed to the processing container.

US Pat. No. 10,971,412

MOUNTING SUBSTRATE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A mounting substrate, comprising:a wiring substrate;
a plurality of light-emitting elements arranged in a matrix on a surface of the wiring substrate; and
a plurality of drive ICs that are arranged in a matrix on the surface of the wiring substrate, and control light emission of the light-emitting elements,
wherein the light-emitting elements are mounted in direct contact with a top surface of a seed layer formed on the wiring substrate and the drive ICs are mounted in direct contact with the top surface of the seed layer formed on the wiring substrate, and
the wiring substrate includes a plurality of first wiring lines on the surface where the light-emitting elements and the drive ICs are mounted, the first wiring lines electrically coupling the light-emitting elements to the drive ICs, wherein
the wiring substrate includes
a plurality of selection lines formed in a layer lower than the first wiring lines, and extending in a row direction,
a plurality of signal lines formed in a layer lower than the first wiring lines, and extending in a column direction,
one or a plurality of second wiring lines formed in the same layer as the first wiring lines or in a layer lower than the first wiring lines, and electrically coupled to each of the selection lines, and
one or a plurality of third wiring lines formed in the same layer as the first wiring lines or in a layer lower than the first wiring lines, and electrically coupled to each of the signal lines, and
the drive ICs are electrically coupled to the one or plurality of the second wiring lines and the one or plurality of the third wiring lines and wherein
the wiring substrate includes
a build-up substrate that includes a core substrate and one or more build-up layers formed on each of both sides of the core substrate, and in which interlayer electrical coupling is made by a via, and
a fine L/S (line and space) layer formed in contact with a top surface of the build-up substrate, wherein
an L/S of the fine L/S layer is smaller than an L/S of the build-up substrate,
the selection lines and the signal lines are formed in the build-up layer, and
the first wiring lines, the second wiring lines, and the third wiring lines are formed in the fine L/S layer.

US Pat. No. 10,971,411

HYBRID CORRECTIVE PROCESSING SYSTEM AND METHOD

TEL Epion Inc., Billeric...

1. A system configured to perform corrective processing on a microelectronic workpiece, comprising:a corrective processing system configured to treat a workpiece with a corrective process; and
a controller programmably configured to:
receive a first set of parametric data from a first source that diagnostically relates to at least a first portion of a microelectronic workpiece, wherein the first source is a metrology system;
receive a second set of parametric data from a second source different than the metrology system used as the first source that diagnostically relates to at least a second portion of the microelectronic workpiece;
generate a corrective process; and
process a target region of the microelectronic workpiece by applying the corrective process to the target region using a combination of the first set of parametric data and the second set of parametric data.

US Pat. No. 10,971,410

IMAGE DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An image display device comprising:a plurality of pixel units arranged two-dimensionally;
a base substrate;
a plurality of pixel substrates, arranged over the base substrate, each of the plurality of pixel substrates comprises at least one of the pixel portion; wherein
the base substrate includes a plurality of first wiring layers continuously arranged in a column direction,
each of the plurality of pixel substrates further comprising:
a first light emitting element,
a driving circuit that realizes predetermined light emission by supplying a predetermined current to the first light emitting element, and
the drive circuit receives serial digital data as data indicating light emission intensity of the first light emitting element and drives the first light emitting element based on the serial digital data.

US Pat. No. 10,971,409

METHODS AND SYSTEMS FOR MEASURING SEMICONDUCTOR DEVICES

Micron Technology, Inc., ...

1. A semiconductor die assembly, comprising:a first semiconductor die including:
a first region adjacent to at least one side of the first semiconductor die; and
a plurality of first measurement features on a surface of the first semiconductor die at the first region, wherein the first measurement features comprise a first metal material;
a second semiconductor die stacked over the first semiconductor die and including;
a second region adjacent to at least one side of the second semiconductor die; and
a plurality of second measurement features on a surface of the second semiconductor die at the second region, wherein the second measurement features are vertically aligned with corresponding ones of the first measurement features; and
a plurality of interconnects electrically coupling the first and second semiconductor dies, wherein the interconnects each include a conductive pad on the first semiconductor die, and wherein the conductive pads comprise a second metal material that is the same as the first metal material.

US Pat. No. 10,971,408

CONTACT AIR GAP FORMATION AND STRUCTURES THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, comprising:providing a first transistor including a first gate structure and a source/drain structure adjacent to the first gate structure;
forming a cavity along a sidewall surface of a contact opening disposed over the source/drain structure;
after forming the cavity, depositing a sacrificial layer over a bottom surface and along the sidewall surface of the contact opening including within the cavity, wherein the cavity is filled with the sacrificial layer;
removing a first portion of the sacrificial layer along the bottom surface of the contact opening to expose a portion of the source/drain structure;
forming a contact feature over the portion of the exposed source/drain structure;
removing a remaining portion of the sacrificial layer to form an air gap disposed between the contact feature and the first gate structure; and
depositing a seal layer over the air gap to form an air gap spacer.