US Pat. No. 10,923,331

PLASMA CLEANING DEVICE AND PROCESS

Surfx Technologies LLC, ...

1. An apparatus for treating a mechanical fastener with atmospheric pressure plasma comprising:an atmospheric pressure plasma generator receiving a gas flow and electrical power and directing the gas flow through a gap between a powered electrode and a grounded electrode of the atmospheric pressure plasma generator while applying the electrical power across the powered electrode and the grounded electrode to generate an atmospheric pressure plasma flow in the gap;
wherein the grounded electrode comprises a housing enclosure having a central rectangular opening and the powered electrode comprises a central indexing hole for receiving an extended portion of the mechanical fastener and thereby aligning the mechanical fastener in the central rectangular opening so that a contact surface of the mechanical fastener is uniformly impacted with the atmospheric pressure plasma flow; and
a spacer comprising opposing beveled edges of the central rectangular opening for supporting the edges of the contact surface of the mechanical fastener above the atmospheric pressure plasma flow in order to expose the contact surface of the mechanical fastener to the atmospheric pressure plasma flow and activate the mechanical fastener surface for bonding.

US Pat. No. 10,923,330

SURFACE POLYMER COATINGS

Europlasma NV, Oudenaard...

1. A method for coating a substrate with a polymer layer, which method comprises:locating a first electrode set and a second electrode set within a plasma chamber, wherein each electrode set comprises an inner electrode layer and a pair of outer electrode layers and wherein the inner electrode layer is a radiofrequency electrode layer and the outer electrode layers are ground electrode layers respectively;
placing a substrate between the first and second electrode sets so that an outer electrode layer of each electrode set faces the substrate;
introducing a monomer into the plasma chamber;
actuating each said radiofrequency electrode layer in order to activate a plasma; and
exposing surfaces of the substrate to the plasma such that a polymer layer is deposited on each surface.

US Pat. No. 10,923,328

PLASMA PROCESSING METHOD AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma processing method of forming a protective film comprising:supplying into a chamber a gaseous mixture which contains a compound gas containing a silicon element and a halogen element, an oxygen-containing gas, and an additional gas containing the same halogen element as the halogen element contained in the compound gas, no silicon element, and no carbon element, the gaseous mixture containing no metal element; and
forming the protective film on a surface of a member in the chamber by a plasma of the gaseous mixture supplied into the chamber, wherein the plasma which forms the protective film does not contain a metal.

US Pat. No. 10,923,326

GAS SPRAYING APPARATUS FOR SUBSTRATE PROCESSING APPARATUS AND SUBSTRATE PROCESSING APPARATUS

JUSUNG ENGINEERING CO., L...

1. A substrate processing apparatus comprising:a process chamber;
a substrate supporting unit installed in the process chamber to support a plurality of substrates;
a chamber lid covering an upper portion of the process chamber; and
a process gas distribution unit installed in the chamber lid to distribute a process gas toward the substrate supporting unit,
wherein
the process gas distribution unit comprises a distribution body installed in the chamber lid and a plasma electrode facing the substrate supporting unit, and
the plasma electrode comprises a first plasma electrode and a second plasma electrode, and the second plasma electrode is shorter than the first plasma electrode,
wherein the substrate supporting unit rotates about a rotational shaft,
wherein the process gas distribution unit comprises a plurality of first distribution holes, disposed along a first axis direction and spaced apart from one another, and a plurality of second distribution holes disposed along the first axis direction and spaced apart from one another,
wherein the distribution body comprises a first body, where the first distribution holes are provided, and a second body provided to protrude from the first body with respect to the first axis direction,
wherein the second body comprises a first sub-body provided to have a length, which is reduced in a direction toward the rotational shaft of the substrate supporting unit, in the first axis direction, and
wherein the second distribution holes are provided in the second body, and some second distribution holes, spaced apart from the first distribution holes by a long distance with respect to the first axis direction, of the second distribution holes are provided to have a shorter length in a second axis direction vertical to the first axis direction.

US Pat. No. 10,923,323

PLASMA GENERATING UNIT AND PLASMA PROCESSING APPARATUS

TOKYO ELECTRON LIMITED, ...

1. A plasma generating unit provided in a plasma processing apparatus, comprising:a dielectric window;
a slot plate provided on the dielectric window; and
a coaxial waveguide electrically connected to the slot plate and configured to transmit a microwave, wherein the coaxial waveguide is connected to a microwave generator via a mode converter,
wherein the coaxial waveguide comprises:
an inner conductor; and
an outer conductor configured to surround the inner conductor,
wherein the plasma generating unit further comprises a pressing component configured to elastically press the inner conductor toward the slot plate such that a bottom surface of the inner conductor is in direct contact with a top surface of the slot plate, and
wherein the inner conductor is fixed to a supporting body and the pressing component is provided between the supporting body and the mode converter.

US Pat. No. 10,923,322

ARTICULATED DIRECT-MOUNT INDUCTOR AND ASSOCIATED SYSTEMS AND METHODS

Lam Research Corporation,...

1. An articulated direct-mount inductor, comprising:a coil portion of an electrically conductive material;
a first articulation portion of the electrically conductive material extending from the coil portion, wherein the first articulation portion includes a twist of the electrically conductive material of about ninety degrees, a first bend of the electrically conductive material of about ninety degrees in a first direction, and a second bend of the electrically conductive material of about ninety degrees in a second direction that is opposite of the first direction;
a first mounting structure of the electrically conductive material extending from the first articulation portion, the first mounting structure including a first mounting region having a first mounting surface configured to mount in physical and electrical contact with a terminal of a first electrical component, wherein the first articulation portion orients the first mounting surface of the first mounting region parallel to an x-y plane of a Cartesian coordinate system, with the centerline of the coil portion oriented parallel to a z-axis of the Cartesian coordinate system;
a second articulation portion of the electrically conductive material extending from the coil portion, wherein the second articulation portion includes a twist of the electrically conductive material of about ninety degrees; and
a second mounting structure of the electrically conductive material extending from the second articulation portion, the second mounting structure including a second mounting region having a second mounting surface configured to mount in physical and electrical contact with a terminal of a second electrical component, wherein the second articulation portion orients the second mounting surface of the second mounting structure parallel to the x-y plane of the Cartesian coordinate system,
wherein each of the coil portion, the first articulation portion, the first mounting structure, the second articulation portion, and the second mounting structure is formed from one piece of the electrically conductive material.

US Pat. No. 10,923,320

SYSTEM FOR TUNABLE WORKPIECE BIASING IN A PLASMA REACTOR

APPLIED MATERIALS, INC., ...

1. A method for tunable workpiece biasing in a plasma chamber comprising:generating a first high voltage by a first pulsed voltage source using DC voltages and coupling the first high voltage to a workpiece in the plasma chamber via at least one direct connection, the at least one direct connection enabling ion energy control in the workpiece near the at least one direct connection;
generating one or more of low and medium voltages by a second pulsed voltage source;coupling, capacitively, the one or more of low and medium voltages to the workpiece; andpulsing the first high voltage and the one or more of low and medium voltages by a biasing controller, the biasing controller adjusting the first and second pulsed voltage sources in combination to achieve a configurable ion energy distribution in the workpiece.

US Pat. No. 10,923,319

METHOD FOR PROJECTING A BEAM OF PARTICLES ONTO A SUBSTRATE WITH CORRECTION OF SCATTERING EFFECTS

1. A method for projecting a particle beam onto a substrate, said method comprising:a step of calculating a correction of scattering effects of said particle beam by means of a point spread function modelling forward scattering effects of particles;
a step of modifying a dose profile of said particle beam, implementing the correction thus calculated; and
a step of projecting the particle beam, the dose profile of which has been modified, onto said substrate, and wherein said point spread function comprises one of the following: a two-dimensional double sigmoid function or a linear combination of functions at least one of which comprises a two-dimensional double sigmoid function.

US Pat. No. 10,923,318

OPTICAL ALIGNMENT CORRECTION USING CONVOLUTIONAL NEURAL NETWORK EVALUATION OF A BEAM IMAGE

FEI Company, Hillsboro, ...

1. A method, comprising: exposing a substrate to a charged particle beam (CPB) to obtain a plurality of training images, each of the training images associated with at least one CPB column characteristic; defining a neural network based on the training images so that the neural network is configured to indicate the at least one CPB column characteristic.

US Pat. No. 10,923,315

CHARGED PARTICLE BEAM APPARATUS, AND METHOD OF ADJUSTING CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Tech Corpora...

1. A charged particle beam apparatus comprising:an irradiation optical system including a lens which is configured to converge charged particle beams emitted from a charged particle source;
an imaging optical system which is configured to image charged particles obtained by irradiating a sample with the charged particle beams on an imaging element; and
a control apparatus which is configured to control the lens, wherein
the control apparatus is configured to use a first image obtained by orbital reversal of the charged particle beam on the trajectory thereof in the vicinity of the wafer surface, and a second image obtained by making the charged particle beam reach the wafer, and to evaluate for each lens condition a size of a brightness area in the second image reduced by a certain amount with respect to brightness of the first image, and to select a lens condition under which the size information fulfills a designated condition.

US Pat. No. 10,923,314

METHOD OF IMAGE ACQUISITION AND ELECTRON MICROSCOPE

JEOL Ltd., Tokyo (JP)

1. A method of image acquisition implemented in an electron microscope for generating a differential phase contrast (DPC) image with electrons transmitted through a sample, said method comprising the steps of:obtaining plural DPC images while causing relative variations in the direction of incidence of an electron beam with respect to the sample;
generating one DPC image by accumulating the plural DPC images; and
displaying the one generated DPC image.

US Pat. No. 10,923,313

CHARGED PARTICLE BEAM DEVICE AND METHOD OF OPERATING A CHARGED PARTICLE BEAM DEVICE

1. A method of operating a charged particle beam device, comprising:forming a beam of charged particles;
forming a plurality of beamlets from the beam of charged particles, the beamlets centered on an optical axis, z, of the charged particle beam device, such that a majority of the plurality of the beamlets, after passing a beamlet-forming multiaperture plate, are shifted from the optical axis;
precompensating each of the beamlets by passing each beamlet through a precompensator which reduces aberrations of the beamlets at a target, the precompensator comprising a plurality of multiaperture electrodes, including
at least one “radially variable” multiaperture electrode in which the diameter of each aperture thereof scales with the distance of the aperture from the optical axis, z; and
at least one “cartesianally variable” multiaperture electrode in which the diameter of each aperture thereof scales with an x component of the position of the aperture, x being perpendicular to z;
scanning each of the beamlets along a direction perpendicular to z; and
focusing each of the beamlets with an objective lens onto the target to form a plurality of focal points.

US Pat. No. 10,923,312

MAGNETIC LENS AND EXCITING CURRENT CONTROL METHOD

FOCUS-EBEAM TECHNOLOGY (B...

1. A magnetic lens, comprising: a magnetic yoke, an exciting coil, and a power supply controlling system; wherein,the magnetic yoke is at outside of the exciting coil and surrounds the exciting coil;
the exciting coil is made up of litz wires; and
the power supply controlling system is arranged to supply power to the exciting coil and control flow directions and magnitudes of currents of the exciting coil,
wherein each of the litz wires comprises a first group of wires and a second group of wires, both a number of wires in the first group and a number of wires in the second group being positive integers larger than one;
wherein the power supply controlling system is arranged to:
simultaneously control currents in the wires in the first group to have a same flow direction and adjust magnitudes of the currents in the wires in the first group, to vary a magnetic field intensity of the magnetic lens to achieve a required magnetic field intensity, and adjust magnitudes of currents in the wires in the second group to keep a total thermal power of the first group of wires and the second group of wires unchanged within the litz wire even when the magnetic field intensity of the magnetic lens varies; and
control the currents in the wires in the second group to make a sum of magnitudes of currents with a positive flow direction is equal to a sum of magnitudes of currents with a negative flow direction, such that a magnetic field generated by the second group of wires is zero.

US Pat. No. 10,923,311

CATHODE FOR ION SOURCE COMPRISING A TAPERED SIDEWALL

XIA TAI XIN SEMICONDUCTOR...

1. An apparatus, comprising:an arc chamber having a receiving area in which a plasma comprising ions of a chemical is generated during operation; and
an electron source device protruding into the receiving area of the arc chamber, the electron source device comprising:
a cathode having a body and a cap disposed over the body, the cap having a receiving surface and an emitting surface opposite the receiving surface, the emitting surface having a convex shape facing the receiving area of the arc chamber, the receiving surface having a truncated conical shape where a center area is a flat surface and the center area being surrounded by a tapered sidewall; and
a filament disposed in the body of the cathode.

US Pat. No. 10,923,310

ION BEAM TREATMENT PROCESS FOR PRODUCING A SCRATCH-RESISTANT HIGH-TRANSMITTANCE ANTIREFLECTIVE SAPPHIRE

1. A process for antireflective treatment in the visible region of a material made of sapphire, comprising:a preliminary stage comprising bombarding the material with a preliminary stage beam of a mixture of mono- and multicharged ions of gas and adjusting a rate of displacement VD within a range between 0.025x(P/D) to 0.1x(P/D), where P is a power of the preliminary stage beam expressed in watts (W) and D is a diameter of the preliminary stage beam expressed in centimeters (cm), wherein during the preliminary stage:
the rate of displacement VD is adjusted while keeping an implanted dose and an acceleration voltage constant,
the acceleration voltage is within a range between 10 and 100 kV, and
the implanted dose of ions is within a range between 1016 and 3 ×1017 ions/cm2; and
a treatment stage comprising bombarding the material with a treatment stage beam of a mixture of mono- and multicharged ions of a gas which are produced by an electron cyclotron resonance (ECR) source, wherein during the treatment stage:
an acceleration voltage is within a range of between 10 and 100 kV,
an implanted dose of ions, expressed in ions/cm2, is within a range of between 1016 and 3×1017 ions/cm2, and
a rate of displacement VD, expressed in cm/s, is within a range of between 0.1 cm/s and 5 cm/s.

US Pat. No. 10,923,309

GEH4/AR PLASMA CHEMISTRY FOR ION IMPLANT PRODUCTIVITY ENHANCEMENT

Applied Materials, Inc., ...

1. A method of generating a germanium ion beam, comprising:introducing germane and argon into an ion source, wherein a flow rate of argon is between 0.5 and 2.0 sccm and a flow rate of germane is between 5.46 sccm and 30 sccm and wherein no halogen gasses are introduced into the ion source;
ionizing the germane and argon to form a plasma; and
extracting germanium ions from the ion source to form the germanium ion beam;
wherein the flow rate of argon is selected such that an efficiency of the ion source, defined as a ratio of germanium beam current to total power applied to the ion source, is greater than 4 mA per kW.

US Pat. No. 10,923,308

METHOD AND SYSTEM FOR ENERGY RESOLVED CHROMA IMAGING

FEI Company, Hillsboro, ...

1. A method for imaging a sample, comprising:irradiating a sample with a charged particle beam;
directing scattered charged particles from the sample to form a first image before entering a spectrometer;
dispersing the scattered charged particles based on energies of the scattered charged particles by passing the scattered charged particles through the spectrometer; and
forming a second image with the dispersed particles on a detector, wherein the scattered charged particles at each location of the first image is spread along a corresponding energy spread vector in the second image.

US Pat. No. 10,923,306

ION SOURCE WITH BIASED EXTRACTION PLATE

Applied Materials, Inc., ...

1. An indirectly heated cathode ion source, comprising:an arc chamber, comprising:
a body comprising a plurality of walls connecting a first end and a second end, wherein the body is electrically conductive; and
an extraction plate comprising an extraction aperture through which ions are extracted, which is electrically conductive and electrically isolated from the body using insulators, wherein the body and the extraction plate form a closed volume;
an indirectly heated cathode disposed on the first end of the arc chamber;
an extraction power supply in communication with the extraction plate; and
a controller in communication with the extraction power supply to allow the indirectly heated cathode ion source to operate in a plurality of modes, wherein one of the plurality of modes comprises a cleaning mode, wherein during the cleaning mode, ions from within the arc chamber bombard the extraction plate.

US Pat. No. 10,923,305

NO-VOLTAGE OUTPUT AND VOLTAGE OUTPUT SWITCHING CIRCUIT

Mitsubishi Electric Corpo...

1. A no-voltage output and voltage output switching circuit comprising:an actuator connection terminal block including a plurality of ports each including a first pin, a second pin, and a third pin to which an actuator is connected;
a power connection terminal block including a voltage terminal and a common terminal to which a power supply is connected;
a plurality of first relays;
a plurality of second relays; and
a control circuit to control each of the plurality of first relays and the plurality of second relays,
wherein
the voltage terminal is a terminal to which a voltage different from a voltage applied to the common terminal is applied when the power supply is connected to the power connection terminal block,
the common terminal is connected to the second pin of each of the plurality of ports,
each of the plurality of first relays corresponds to one of the plurality of ports, and each of the plurality of ports corresponds to one of the plurality of first relays,
each of the plurality of second relays corresponds to one of the plurality of ports, and each of the plurality of ports corresponds to one of the plurality of second relays,
one of the plurality of first relays is a first specific relay to enable connection between the first pin of a corresponding port among the plurality of ports and the third pin of the corresponding port,
a second relay corresponding to a port among the plurality of ports corresponding to the first specific relay enables connection between the first pin of the port corresponding to the first specific relay and the voltage terminal, and
at each of the plurality of ports, (i) the control circuit turns a first relay among the plurality of the first relays on to connect the first pin and the third pin and the control circuit turns a second relay among the plurality of the second relays off to isolate the first pin from the voltage terminal in order to create a no-voltage condition at the actuator, and (ii) the control circuit turns the first relay off to isolate the first pin from the third pin and the control circuit turns the second relay on to connect the first pin and the voltage terminal in order to create a voltage condition at the actuator.

US Pat. No. 10,923,304

VACUUM CIRCUIT BREAKER OPERATING MECHANISM

EATON INTELLIGENT POWER L...

1. An operating mechanism for a circuit breaker assembly, said circuit breaker assembly including a first contact and a second contact, wherein at least one of said first contact and said second contact is a movable contact, said at least one movable contact structured to move between an open, first configuration, wherein the contacts are spaced from each other and are not in electrical communication, and a closed, second configuration, wherein the contacts are directly coupled to each other and are in electrical communication, said operating mechanism comprising:an opening, first actuator assembly;
said first actuator assembly structured to operatively engage said at least one movable contact and structured to move said at least one movable contact from said second configuration to said first configuration;
a closing, second actuator assembly;
said second actuator assembly structured to operatively engage said at least one movable contact and structured to move said at least one movable contact from said first configuration to said second configuration;
wherein said first actuator assembly and said second actuator assembly are split cooperative actuators;
wherein said first contact is a movable contact and said second contact is a movable contact, said first contact movable between a withdrawn, first position and an extended, second position, said second contact movable between a withdrawn, first position and an extended, second position, and wherein;
said first actuator assembly includes a first contact opening actuator assembly and a second contact opening actuator assembly;
said first contact opening actuator assembly structured to move said first contact from said second position to said first position;
said second contact opening actuator assembly structured to move said second contact from said second position to said first position;
said second actuator assembly includes a first contact closing actuator assembly and a second contact closing actuator assembly;
said first contact closing actuator assembly structured to move said first contact from said first position to said second position; and
said second contact closing actuator assembly structured to move said second contact from said first position to said second position.

US Pat. No. 10,923,302

SWITCHGEAR

MITSUBISHI ELECTRIC CORPO...

1. A switchgear comprising:a movable part capable of reciprocating movement including movement in a first direction and movement in a second direction opposite to the first direction;
a movable contact coupled to the movable part on a side of the first direction, the movable contact being capable of reciprocating movement including movement in the first direction and movement in the second direction relative to the movable part;
a first biasing member to bias the movable contact in the first direction relative to the movable part;
a latch part capable of switching between a first state in which movement of the movable contact in the first direction is restricted and a second state in which movement of the movable contact in the first direction is permitted; and
a fixed contact provided on a side of the first direction with respect to the movable contact, wherein
the movable part and the movable contact move in the first direction from initial positions at which the movable contact is away from the fixed contact to closed positions at which the movable contact is in contact with the fixed contact,
in a process in which the movable part and the movable contact move from the initial positions to the closed positions, after the movable part and the movable contact have moved a predetermined distance, the movement of the movable contact is restricted by the latch part in the first state, and when the movable part has moved further in the first direction against biasing force of the first biasing member after the movement of the movable contact was restricted, the latch part is switched to the second state in which the movement of the movable contact in the first direction is permitted,
the latch part includes a magnet, and a metallic member, the metallic member being attracted by the magnet from a side of the first direction when the movable part and the movable contact are at the initial positions,
the movable contact includes an abutment portion to come into contact with part of the metallic member avoiding the magnet from a side of the second direction when the movement of the movable contact in the first direction is restricted by the latch part, and
the switchgear further comprises a second biasing member to bias the metallic member in the second direction.

US Pat. No. 10,923,301

DOUBLE THROW SWITCH OPERATING MECHANISM

The Durham Company, Leba...

1. A switching mechanism for actuating a switch, the switching mechanism comprising:an actuator rotatable between an off position and an on position; and
a timing disc assembly comprising an actuator disc, a bias disc, and a switch disc arranged in a stack such that the actuator disc, the bias disc, and the switch disc overlay each other, the actuator disc being rotatably connected to the actuator such that the actuator disc is configured to rotate with the actuator, the actuator disc comprising a first actuator flange and a second actuator flange, the bias disc being connected to at least one biasing mechanism, the bias disc comprising a first bias flange and a second bias flange, the switch disc being connected to the switch, the switch disc comprising a switch flange, the first actuator flange of the actuator disc being configured to engage the first bias flange of the bias disc such that the actuator disc is configured to rotate the bias disc to an overcenter position of the at least one biasing mechanism, wherein the overcenter position of the at least one biasing mechanism is configured to rotate the bias disc such that engagement between the first bias flange of the bias disc and the switch flange of the switch disc is configured to rotate the switch disc from an open position of the switch to a closed position of the switch, the second actuator flange of the actuator disc being configured to engage the second bias flange of the bias disc such that the actuator disc is configured to rotate the bias disc to the overcenter position of the at least one biasing mechanism, wherein the overcenter position of the at least one biasing mechanism is configured to rotate the bias disc such that engagement between the second bias flange of the bias disc and the switch flange of the switch disc is configured to rotate the switch disc from the closed position to the open position of the switch.

US Pat. No. 10,923,300

DISCONNECT SWITCH WITH A DETENT MECHANISM TO PROTECT AGAINST OVER-ROTATION

Leviton Manufacturing Co....

1. An electrical disconnect switch including an over-rotational feature, the electrical disconnect switch comprising:an enclosure having a front surface and an interior portion, the enclosure comprising:
a load switch disposed within the interior portion, the load switch being rotatable between an ON position and an OFF position;
a handle assembly comprising a rotatable handle and a shaft, the shaft being arranged and configured to selectively couple the rotatable handle to the load switch, the rotatable handle being accessible via the front surface;
wherein the shaft includes a detent, the detent being arranged and configured to enable the rotatable handle to be selectively decoupled from the load switch upon application of a predetermined amount of torque and to be recoupled to the load switch when the detent realigns.

US Pat. No. 10,923,299

SWITCH INCLUDING WATERPROOF AND LIGHT LEAK PREVENTION STRUCTURE

ALPS ALPINE CO., LTD., T...

1. A switch including a light emitting member and a push switch on a mount, comprising: a cover plate provided on the mount and configured to cover the light emitting member and the push switch, wherein the cover plate comprises: a rubber dome disposed at a position corresponding to the push switch; a light emitting member cover configured to cover the light emitting member at a predetermined distance from an upper surface of the light emitting member; and a light leak prevention protrusion configured to surround a periphery of the light emitting member and to extend upward up to a predetermined height, the light leak prevention protrusion and the rubber dome being formed into a single piece made of a same material, the light leak prevention protrusion having a height substantially the same as the rubber dome; wherein the light emitting member cover is joined together with an inside of the light leak prevention protrusion.

US Pat. No. 10,923,298

COMPACT POLE UNIT FOR FAST SWITCHES AND CIRCUIT BREAKERS

Eaton Intelligent Power L...

1. A circuit breaker, comprising:a first actuator;
a second actuator; and
a compact pole unit comprising:
an encapsulated body having a first end, a second end, and an outer surface,
one or more rings extending from the encapsulated body on the outer surface,
a first conducting terminal extending from the encapsulated body,
a second conducting terminal extending from the encapsulated body,
a vacuum interrupter positioned within the encapsulated body, the vacuum interrupter comprising:
a vacuum enclosure;
a movable first electrode assembly having a first stem slidably extending from the vacuum enclosure and slidably connected to the first conducting terminal;
a second electrode assembly having a second stem extending from the vacuum enclosure and connected to the second conducting terminal; and
a drive rod interconnecting the first actuator to the first stem at the first end of the compact pole unit; and
a coupler assembly comprising:
a contact spring positioned at the second end of the compact pole unit, and
a plunger interconnecting the second actuator to the contact spring.

US Pat. No. 10,923,296

METHOD FOR MANUFACTURING POSITIVE ELECTRODE INCLUDING CONDUCTIVE POLYMER LAYER SELECTIVELY FORMED ON SURFACE OF CARBON LAYER DISPOSED ON CURRENT COLLECTOR FOR POWER STORAGE DEVICE, AND METHOD FOR MANUFACTURING POWER STORAGE DEVICE

PANASONIC INTELLECTUAL PR...

1. A method for manufacturing a positive electrode for a power storage device, the method comprising:preparing a current collector having a sheet-shape, the current collector having a front surface and a back surface that is opposite to the front surface,
forming a carbon layer on a first region of the front surface while no carbon layer is formed in a second region of the front surface; and
forming a conductive polymer on the carbon layer by immersing the current collector in an electrolytic solution containing a raw material monomer of the conductive polymer and then conducting electrolytic polymerization of the raw material monomer.

US Pat. No. 10,923,295

COMPOSITIONS AND METHODS FOR ENERGY STORAGE DEVICE ELECTRODES

Maxwell Technologies, Inc...

1. A method for fabricating a dry energy storage device electrode film comprising:forming a first dry electrode film mixture comprising dry carbon particles and dry fibrillizable binder particles;
super-fibrillizing the dry fibrillizable binder particles in the dry electrode film mixture to form a super-fibrillized matrix within the electrode film mixture, wherein super-fibrillizing the dry fibrillizable binder particles comprises:
fibrillizing the dry fibrillizable binder particles in the dry electrode film mixture to form a first fibrillized matrix;
destructuring the first fibrillized matrix to form a powdered mixture of carbon particles and fibrillized binder particles; and
fibrillizing the powdered mixture to form a super-fibrillized electrode film mixture comprising a second fibrillized matrix, wherein the second fibrillized matrix comprises the super-fibrillized matrix; and
calendering the super-fibrillized electrode film mixture to form a free-standing super-fibrillized electrode film.

US Pat. No. 10,923,293

HIGH FREQUENCY SUPERCAPACITORS AND METHODS OF MAKING SAME

TEXAS TECH UNIVERSITY SYS...

1. A method of making an AC-supercapacitor comprising the steps of:(a) selecting a material comprising polymer nanofiber network;
(b) employing a plasma to pyrolyze the polymer nanofiber network to create a carbon nanofiber network (CNN) electrode material;
(c) forming a CNN electrode from the CNN electrode material; and
(d) incorporating the CNN electrode in a cell package to form an AC-supercapacitor, wherein the AC-supercapacitor is operable for running at frequencies of at least 0.1 kHz.

US Pat. No. 10,923,292

WIRING MODULE

AUTONETWORKS TECHNOLOGIES...

1. A wiring module configured to be attached to a plurality of power storage elements that are arranged side-by-side, the wiring module comprising:a plurality of electric wires; and
a plurality of coupling units in which the plurality of electric wires are routed,
wherein a first coupling unit of the plurality of coupling units has a first routing portion in which at least one of the plurality of electric wires is routed,
a second coupling unit of the plurality of coupling units has a second routing portion in which at least one of the plurality of electric wires is routed, the second coupling unit being adjacent to the first coupling unit in a direction in which the first routing portion and the second routing portion extend,
an engagement portion is provided on one of the first routing portion and the second routing portion, and an engagement receiving portion that engages with the engagement portion is provided on the other of the first routing portion and the second routing portion,
the plurality of coupling units are coupled in a condition in which the engagement portion and the engagement receiving portion are engaged with each other,
the first routing portion has a groove shape and has a first bottom wall, and one of the engagement portion and the engagement receiving portion is provided on the first bottom wall,
the second routing portion has a groove shape and has a second bottom wall, and the other of the engagement portion and the engagement receiving portion is provided on the second bottom wall,
the engagement portion and the engagement receiving portion overlap in the thickness direction of the first bottom wall and the second bottom wall in a condition in which the first coupling unit and the second coupling unit are coupled,
a hook portion that is provided on the engagement portion and protrudes toward the engagement receiving portion and a hook portion that is provided on the engagement receiving portion and protrudes toward the engagement portion are engaged at a position not exposed to the first routing portion and the second routing portion,
a first cover that covers a first opening portion provided in the first coupling unit is provided on the first coupling unit via a first hinge portion,
a second cover that covers a second opening portion provided in the second coupling unit is provided on the second coupling unit via a second hinge portion,
a unit lock portion is provided on the second cover of the second coupling unit, and
a unit lock receiving portion, which engages with the unit lock portion on the second cover of the second coupling unit in a condition in which the second cover covers the second opening portion, is provided on a portion of the first coupling unit that is different from the first cover and the first hinge portion.

US Pat. No. 10,923,291

OXIDE ON EDGES OF METAL ANODE FOILS

Pacesetter, Inc., Sunnyv...

1. A capacitor, comprising:a housing;
an anode foil within the housing, wherein the anode foil includes a hydration layer on a metal,
the hydration layer being on an edge of the anode foil, and
an oxide being on a face of the anode foil but not being between the edge of the anode foil and the hydration layer;
a cathode foil within the housing; and
a separator between the anode foil and the cathode foil.

US Pat. No. 10,923,290

ELECTROLYTIC CAPACITOR-SPECIFIC ELECTRODE MEMBER AND ELECTROLYTIC CAPACITOR

JAPAN CAPACITOR INDUSTRIA...

1. An electrolytic capacitor-specific electrode member included in an electrolytic capacitor, the electrolytic capacitor-specific electrode member having a wire shape, the electrolytic capacitor-specific electrode member comprising:a core portion; and
a porous layer that is located around the core portion,
in a cross section of the electrolytic capacitor-specific electrode member perpendicular to an axial direction of the electrolytic capacitor-specific electrode member, the porous layer including a plurality of layers that are concentrically arranged from the core portion toward outside and that include at least two layers having different void ratios, wherein:
the core portion and the porous layer are formed from a same base material, and
the porous layer including the at least two layers having different void ratios is formed from a roughened surface of the same base material.

US Pat. No. 10,923,289

STACKED TYPE CAPACITOR PACKAGE STRUCTURE WITHOUT CARBON PASTE LAYER, STACKED TYPE CAPACITOR THEREOF, AND POLYMER COMPOSITE LAYER

ANDAQ TECHNOLOGY CO., LTD...

1. A stacked type capacitor without a carbon paste layer, comprising:a metal foil;
an oxide layer formed on an outer surface of the metal foil to entirely enclose the metal foil;
a polymer composite layer formed on the oxide layer to partially enclose the oxide layer; wherein the polymer composite layer includes 0.1-5% by weight of a poly(3,4-ethylenedioxythiophene):polystyrene sulfonate (PEDOT:PSS) composite, 1-30% by weight of a conductive auxiliary, 0.1-15% by weight of a hydrogen bond type adhesive, 0.01-5% by weight of a silane coupling agent, 0.5-5% by weight of a water-soluble resin, and 0.001-1% by weight of a polyamine compound; wherein the conductive auxiliary is selected from the group consisting of polyol, dimethyl sulfoxide (DMSO), and N-methyl-2-pyrrolidone (NMP); the hydrogen bond type adhesive is selected from the group consisting of sorbitol and polyvinyl alcohol; the water-soluble resin is selected from the group consisting of water-based polyurethane, water-based polyethylene, polyester, and water-based polymethylmethacrylate; and the polyol is selected from the group consisting of ethylene glycol, glycerol, polyethylene glycol, and polyglycefine; and
a silver paste layer formed directly on the polymer composite layer to directly enclose the polymer composite layer,
wherein the oxide layer and the polymer composite layer are connected with each other to form a first connection interface between the oxide layer and the polymer composite layer, and the polymer composite layer and the silver paste layer are connected with each other directly without the carbon paste layer to form a second connection interface between the polymer composite layer and the silver paste layer.

US Pat. No. 10,923,287

VASCULAR COOLED CAPACITOR ASSEMBLY AND METHOD

GM Global Technology Oper...

1. A capacitor assembly configured for use with a cooling fluid system, comprising:a plurality of capacitors, each capacitor having respective first and second leads and a respective central axial passage extending along at least a portion of a respective axial length thereof;
first and second busbars disposed in electrical contact with the first and second leads, respectively;
an encapsulant enveloping the plurality of capacitors and a respective major portion of each of the first and second busbars; and
a network of channels enveloped within the encapsulant and formed by deflagration of a sacrificial material, each channel having a respective inlet end and a respective outlet end, the network having at least one network inlet configured to direct fluid flow into the inlet ends and at least one network outlet configured to direct fluid flow away from the outlet ends, wherein at least one branch of each channel is positioned as being at least one of inside the central axial passage of at least one of the capacitors, around an outer periphery of at least one of the capacitors, and between at least two of the capacitors, and wherein each of the at least one network inlet and the at least one network outlet is configured for sealable engagement with the cooling fluid system.

US Pat. No. 10,923,286

METHOD AND APPARATUS FOR COMPENSATING FOR HIGH THERMAL EXPANSION COEFFICIENT MISMATCH OF A STACKED DEVICE

NXP USA, Inc., Austin, T...

1. A method for compensation for a Thermal Expansion Coefficient (TEC) mismatch for a silicon substrate of a device, the method comprising:providing a first silicon dioxide layer on the silicon substrate;
depositing a modifier layer on the first silicon dioxide layer;
depositing a second silicon dioxide layer on the modifier layer to form a multilayer initial oxide; and
annealing the multilayer initial oxide resulting in an annealed multilayer initial oxide, wherein the annealing causes diffusion of modifier species from the modifier layer into the first and second silicon dioxide layers and results in amorphous polysilicates, the first and second silicon dioxide layers having thicknesses that prevent the diffusion of the modifier species from reaching top and bottom interfaces of the annealed multilayer initial oxide, wherein the annealed multilayer initial oxide compensates for the TEC mismatch for the silicon substrate, thereby mitigating delamination.

US Pat. No. 10,923,284

CAPACITOR COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A capacitor component comprising:a body including dielectric layers and internal electrodes alternately arranged with the dielectric layers; and
external electrodes including electrode layers disposed on the body and connected to the internal electrodes, first conductive resin layers disposed on the electrode layers, and second conductive resin layers disposed on the first conductive resin layers,
wherein the first and second conductive resin layers include a metal powder and a base resin,
the first conductive resin layers have a lower metal powder content than the second conductive resin layers,
the metal powder includes flake-type powder particle and/or spherical-type powder particle, and
a weight ratio of the flake-type powder particle in the metal powder contained in the first conductive resin layers is 60% or more, and a weight ratio of the spherical-type powder particle in the metal powder contained in the second conductive resin layers is 50% or more.

US Pat. No. 10,923,283

MULTILAYER CERAMIC ELECTRONIC COMPONENT HAVING AN EXTERNAL ELECTRODE WHICH INCLUDES A GRAPHENE PLATELET

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including a dielectric layer and an internal electrode;
an electrode layer electrically connected to the internal electrode; and
a conductive resin layer disposed on the electrode layer and including a conductive metal powder, a graphene platelet, and a base resin,
wherein the graphene platelet has a planar shape.

US Pat. No. 10,923,282

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a multilayer ceramic capacitor including a capacitor body, and first and second external electrodes respectively disposed on end surfaces of the capacitor body opposing each other in a length direction of the capacitor body and respectively having first and second band portions extending onto one of side surfaces of the capacitor body connecting the end surfaces of the capacitor body to each other;
an interposer including an interposer body having grooves in surfaces opposing each other in the length direction, and first and second external terminals respectively disposed at ends of the interposer body opposing each other in the length direction; and
conductive adhesive portions disposed between the external electrodes and the external terminals, respectively,
wherein Lc?Li, in which Lc is a distance in the length direction between centers of the first and second band portions of the first and second external electrodes, and Li is a shortest distance in the length direction between connection portions disposed on the grooves in the opposite surfaces of the interposer body, and
each of the grooves includes a single curved surface directly connecting to each other side surfaces of the interposer body opposing each other in a width direction of the capacitor body.

US Pat. No. 10,923,281

CAPACITOR

PANASONIC INTELLECTUAL PR...

1. A capacitor comprising:a capacitor element;
a case that houses the capacitor element; and
a filler resin that fills an interior of the case, wherein:
the case includes a case body and a lid, the case body includes a bottom wall, an inner wall having a tube shape, an outer wall having a tube shape and surrounding the inner wall, and a coupler that couples the inner wall to the outer wall,
the inner wall rises from a peripheral edge of the bottom wall,
the outer wall extends further outward than the bottom wall in a direction from the case body to the lid, the direction being perpendicular to a main surface of the bottom wall,
the coupler forms a first gap between the inner wall and the outer wall,
the bottom wall, the inner wall, the outer wall, and the coupler are integrally formed, and
the lid closes an opening of the outer wall to form a second gap between the lid and the bottom wall, the opening facing the bottom wall.

US Pat. No. 10,923,280

FILM CAPACITOR, COMBINATION TYPE CAPACITOR, INVERTER, AND ELECTRIC VEHICLE

Kyocera Corporation, Kyo...

1. A film capacitor, comprising:a main body portion comprising:
a dielectric film, and
a metal film disposed on one surface of the dielectric film, and having surface roughnesses of S1 and S2 where S1 denotes a surface roughness of the metal film in a first direction, and S2 denotes a surface roughness of the metal film in a second direction, the first direction perpendicular to the second direction, S1 greater than S2; and
the main body portion including a pair of ends in the first direction thereof; and
external electrodes disposed on the pair of ends, respectively,
wherein an average value of fractal dimensions of irregularity boundary lines due to wrinkles of the metal film is 1.08 or more.

US Pat. No. 10,923,278

MULTI-LAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multi-layer ceramic capacitor, comprising:a multi-layer unit that includes
ceramic layers laminated in a first direction,
internal electrodes disposed between the ceramic layers,
a main surface facing the first direction,
a side surface facing a second direction orthogonal to the first direction,
a surface layer portion in a range from the main surface to a predetermined depth, and
a center portion adjacent to the surface layer portion in the first direction; and
a side margin that covers the side surface of the multi-layer unit from the second direction, such that all internal electrodes are covered from the second direction by the side margin,
the ceramic layers having an average dimension in the first direction that is 0.4 ?m or less,
each of the internal electrodes including an oxidized region that is adjacent to the side margin,
the oxidized region in the surface layer portion having a dimension in the second direction that is equal to or more than two times the average dimension of the ceramic layers in the first direction and is equal to or less than four times the average dimension of the ceramic layers in the first direction, and
wherein the oxidized region in the center portion has a diension in the second direction that is smaller than the oxidized region.

US Pat. No. 10,923,276

COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a body comprising:
magnetic particles dispersed in a first insulating material,
a coil portion embedded in the first insulating material;
a first insulating layer along a surface of the coil portion and formed of a second insulating material;
a second insulating layer along a surface of the first insulating layer and formed of a third insulating material; and
external electrodes connected to the coil portion,
wherein a material of the coil portion has a coefficient of thermal expansion (CTE) greater than that of a material of the first insulating layer, and
the material of the first insulating layer has a CTE greater than that of a material of the second insulating layer.

US Pat. No. 10,923,275

STATIONARY INDUCTION APPARATUS

MITSUBISHI ELECTRIC CORPO...

1. A stationary induction apparatus comprising:a core;
a first winding and a second winding each wound in a cylindrical shape with the core as its central axis, the first winding and the second winding having facing surfaces that face with each other; and
an insulating structure arranged between the facing surfaces of the first winding and the second winding,
the insulating structure including
a first insulator located between the facing surfaces of the first winding and the second winding at intervals from the first winding and the second winding, the first insulator having a cylindrical shape with the core as its central axis, and
a plurality of first insulating spacers each arranged between the first winding and the first insulator and between the second winding and the first insulator, the plurality of first insulating spacers extending along an extension direction parallel to the central axis,
the first insulator including a first nonlinear resistive layer containing a nonlinear resistive material having a nonlinear volume resistivity that decreases when an electric field acting on the nonlinear resistive material is higher than a threshold,
the first nonlinear resistive layer being provided in a portion of the first insulator which is at least in contact with a corresponding one of the plurality of first insulating spacers.

US Pat. No. 10,923,273

COIL DESIGN FOR WIRELESS POWER TRANSFER

Integrated Device Technol...

1. A coil configuration for a wireless transmitter, comprising:a plurality of turns coupled between a first tap coupled to an innermost turn and a second tap coupled to an outermost turn;
at least one adjustment tap coupled to at least one turn of the transmitter coil between the innermost turn and the outermost turn; and
a magnetic secured transmission (MST) coil coupled to the second tap.

US Pat. No. 10,923,271

CORE AND TRANSFORMER

FUJI ELECTRIC CO., LTD., ...

1. A core for a transformer, the core comprising:a shaft part having a cylindrical shape; and
a pair of leg parts provided at both sides with respect to the shaft part, each of the leg parts having an inner surface that is curved to face a winding wound on the shaft part,
wherein each of the leg parts has, on both ends of the inner surface, inner corner parts that are chamfered,
wherein each of the leg parts has a flat outer surface and connection surfaces that are orthogonal to the flat outer surface and that connect the flat outer surface and the corner parts to form right-angle outer corner parts,
wherein the inner surface and the inner corner parts of each of the leg parts are curved in different directions,
wherein the winding includes a first winding and a second winding and a voltage of the first winding is higher than a voltage of the second winding, and
wherein the inner corner parts of each of the leg parts are chamfered with a radius of curvature of 2 mm or more so that a partial discharge start voltage between the first winding, the core and the second winding is greater than or equal to 5 kV.

US Pat. No. 10,923,270

COMMON-MODE CHOKE COIL

Murata Manufacturing Co.,...

1. A common-mode choke coil comprising:a ferrite core including a winding core portion and first and second flange portions that are respectively disposed on first and second end portions of the winding core portion that are opposite each other;
first and second wires, each of which is helically wound around the winding core portion and includes a linear central conductor and an insulating coating layer that covers a circumferential surface of the central conductor;
first and second terminal electrodes to which a first end of the first wire and a second end of the first wire, that is opposite the first end, are electrically connected, respectively; and
third and fourth terminal electrodes to which a first end of the second wire and a second end of the second wire, that is opposite the first end, are electrically connected, respectively, and
a common-mode inductance value at 150° C. and 100 kHz is 160 ?H or more, and a return loss at 20° C. and 10 MHz is ?27.1 dB or less.

US Pat. No. 10,923,267

TRANSFORMER

Yaroslav A. Pichkur, Bro...

1. An electrical transformer comprising:a primary circuit extending between two ends, said primary circuit having at least one of the ends thereof connected with a power supply so that a first electrical current from the power source flows through the primary circuit;
a secondary circuit connected with an electrical load;
the primary and secondary circuits each having a respective plurality of wire segments having a length and being connected in series;
said wire segments of the primary and secondary circuits being supported so as to extend in pathways adjacent and parallel to each other over the length thereof in a cross-sectional pattern that is substantially constant over the length of the wire segments so that, when viewed in cross section perpendicular to the direction of extension thereof, the wire segments of the primary and secondary circuits are arranged with the wire segments of the primary circuit alternating with the wire segments of the secondary circuit around points in the cross-sectional pattern, and with the wire segments of the secondary circuit are separated spaced from each other and from the wire segments of the primary circuit; and
wherein the first electrical current in the primary circuit causes formation of a second electrical current in the secondary circuit that is transmitted to the load;
wherein some of the wire segments of the secondary circuit each have a respective set of three or more of the wire segments of the primary circuit arranged rotatively spaced therearound at equal angles, and
wherein the first electrical current creates varying magnetic fields about each of the wire segments of the primary circuit that magnetically induce the second electrical current flowing in said wire segments of the secondary circuit.

US Pat. No. 10,923,265

COIL COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil component comprising:a body portion; and
a coil portion disposed in the body portion,
wherein the coil portion includes a support member and a first coil layer disposed on a first surface of the support member, the first coil layer including a first electrode portion led out to a first end surface of the body portion,
the support member includes first and second insulators each having a composition different from the body portion, and a metal core disposed between the first and second insulators in a thickness direction,
a first end portion of the metal core is led out to the first end surface of the body portion, and
the coil portion further includes a first through-via penetrating through the support member and electrically connecting the first electrode portion of the first coil layer and the first end portion of the metal core to each other.

US Pat. No. 10,923,264

ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a magnetic body; and
a coil pattern embedded in the magnetic body and including an internal coil part and lead parts,
wherein the lead parts extend from respective ends of the internal coil part to a surface of the magnetic body, such that respective thicknesses of the lead parts from the respective ends to the surface are thinner than a thickness of:
(1) at least a part of portions of the internal coil part arranged at a same level as the lead parts, respectively, or
(2) at least the respective ends of the internal coil part, and
wherein the lead parts are spaced apart from inwardly adjacent coil patterns, respectively, of the internal coil part when viewed in a cross-section of a central portion of the magnetic body or electronic component.

US Pat. No. 10,923,262

INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. An inductor comprising:a body having a stack of a plurality of insulating layers, each of which has a coil pattern disposed thereon;
first and second external electrodes disposed on an external surface of the body; and
dummy electrodes formed on portions of the insulating layers corresponding to the first and second external electrodes, the dummy electrodes not being physically connected to the coil pattern disposed on corresponding insulating layers,
wherein the plurality of coil patterns are connected to each other by a coil connection portion and form a coil having both end portions connected to the first and second external electrodes through a coil lead portion,
the dummy electrodes are connected to each other by vias, and
the plurality of coil patterns are composed of coil patterns disposed in outermost positions and coil patterns disposed inwardly of the coil patterns disposed in the outermost positions of the body, a thickness of at least one of the coil patterns disposed inwardly being thicker than that of the coil patterns disposed in the outermost positions.

US Pat. No. 10,923,261

MAGNETIC FASTENING ASSEMBLY

Microsoft Technology Lice...

1. A fastening assembly, comprising:a first permanent magnet of a first magnet grade having a first operating temperature as a first magnet property; and
a second permanent magnet of a second magnet grade having a second operating temperature as a second magnet property, the second operating temperature being lower than the first operating temperature, wherein the first permanent magnet is attachable to the second permanent magnet in a locked state at a first temperature that is lower than the second operating temperature, wherein the first permanent magnet is releasable from the second permanent magnet in an unlocked state at a second temperature that is higher than the second operating temperature.

US Pat. No. 10,923,260

MAGNETORHEOLOGICAL FLUID COMPOSITION AND VIBRATION DAMPING DEVICE USING SAME

Honda Motor Co., Ltd., T...

1. A magnetorheological fluid composition comprising:magnetic particles;
a dispersant having the magnetic particles dispersed in the dispersant; and
a friction modifier,
wherein the friction modifier is an ester-based additive comprising at least one component selected from butyl stearate, butyl oleate, butyl palmitylate, sorbitan monostearate, sorbitan monopalmitate, and glycerol monopalmitate, and
wherein the content of the friction modifier is 0.1 to 5 mass % relative to a total amount of the magnetorheological fluid composition.

US Pat. No. 10,923,259

COIL COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil component comprising:a body;
a coil disposed inside of the body and forming one coil track;
external electrodes disposed on an outer surface of the body,
wherein the coil track includes a corner portion and linear portions extending from the corner portion, and
wherein a radius of a circle tangent to a surface of the corner portion is 0.008 mm to 0.016 mm such that an acute angle is defined between the linear portions.

US Pat. No. 10,923,255

MAGNETIC MATERIAL, PERMANENT MAGNET, ROTARY ELECTRICAL MACHINE, AND VEHICLE

KABUSHIKI KAISHA TOSHIBA,...

1. A magnetic material expressed bya composition formula 1: (R1-xZx)aMbTc
where R is at least one element selected from the group consisting of rare-earth elements, Z is at least one element selected from the group consisting of Y, Zr, and Hf, M is Fe or Fe and Co, T is at least one element selected from the group consisting of Ti, V, Nb, Ta, Mo, and W, x is a number satisfying 0.01?x?0.8, a is a number satisfying 4?a?20 atomic percent, b is a number satisfying b=(100?a?c) atomic percent, and c is a number satisfying 0 the magnetic material comprising
a main phase having a ThMn12 crystal structure,
wherein in the ThMn12 crystal structure, when an amount of the element Z occupying 2a site is Z2a atomic percent, an amount of the element Z occupying 8i site is Z8i atomic percent, an amount of the element Z occupying 8j site is Z8i atomic percent, and an amount of the element Z occupying 8f site is Z8f atomic percent, Z2a, Z8i, Z8j, and Z8f satisfy
(Z8i+Z8j+Z8f)/(Z2a+Z8i+Z8j+Z8f)<0.09.

US Pat. No. 10,923,254

PERMANENT MAGNET, MOTOR, AND GENERATOR

KABUSHIKI KAISHA TOSHIBA,...

1. A permanent magnet expressed by a composition formula:RpFeqMrCutCo100-p-q-r-t
where R represents at least one element selected from the group consisting of rare earth elements, M represents at least one element selected from the group consisting of Zr, Ti, and Hf, p is a number satisfying 10.5?p?12.4 atomic percent, q is a number satisfying 28?q?40 atomic percent, r is a number satisfying 0.88?r?4.3 atomic percent, and t is a number satisfying 3.5?t?13.5 atomic percent,
the magnet comprising:
a metallic structure including crystal grains which constitutes a main phase having a Th2Zn17 crystal phase,
wherein an average value of Fe concentrations in the crystal grains of 20 or more is 28 atomic percent or more and an average value of R element concentrations in the crystal grains of 20 or more is 10 atomic percent or more,
a squareness ratio of the magnet is 92.1% or more and 95.9% or less, and
a magnetization when a magnetic field is ?200 kA/m is 95.5% or more and 98.9% or less of a residual magnetization in an M-H curve of the magnet.

US Pat. No. 10,923,250

WIRING HARNESS PRODUCTION MOUNTING

LASELEC, Toulouse (FR)

1. A method for assisting with the production of wire harnesses comprising the following steps:displaying (601), on a screen, a wiring diagram of said wire harness;
determining (603) at least one cable to be placed on a wire harness production support;
displaying (604), on said wiring diagram, at least one route associated with said at least one determined cable;
determining (607) at least one connector to be placed on said support;
displaying (608) a second list of cables to be connected to said connector;
selecting (609) at least one cable from said second list;
displaying (610) an information window relating to at least one operation to be performed by a user on said at least one selected cable, said window comprising the designation of at least one tool to be used for performing said operation;
determining a first identifier associated with said at least one tool for performing a cable operation;
comparing said first identifier with a second identifier associated with said at least one tool designated in said information window;
based on a non-correspondence between the first and second identifiers, displaying an error message in the case of;
displaying an information window relating to at least one following operation to be performed by a user on said at least one selected cable in the case of correspondence between the first and second identifiers; and
displaying information relating to said operation in the case of correspondence between the first and second identifiers.

US Pat. No. 10,923,247

SUPERCONDUCTING STABILIZATION MATERIAL, SUPERCONDUCTING WIRE, AND SUPERCONDUCTING COIL

MITSUBISHI MATERIALS CORP...

1. A superconducting stabilization material used for a superconducting wire, which is formed of a copper material which comprises:one or more types of additive elements selected from the group consisting of Ca, La, and Ce in a total of 3 ppm by mass to 400 ppm by mass; and
a balance being Cu and inevitable impurities and in which a total concentration of the inevitable impurities excluding O, H, C, N, and S which are gas components is 5 ppm by mass to 100 ppm by mass, wherein
a ratio Y/X of a total amount of additive elements of one or more types selected from the group consisting of Ca, La, and Ce (Y ppm by mass) to a total amount of S, Se, and Te (X ppm by mass) is in a range of 0.5?Y/X?100.

US Pat. No. 10,923,246

FLAME RETARDANT ELECTRICAL CABLE

PRYSMIAN S.P.A., Milan (...

1. A flame-retardant electric cable having a core comprising an electric conductor and an electrically insulating layer comprising a flame-retardant polyolefin-based composition comprising:a) as base polymer, a mixture of at least two polyolefin homopolymers and/or copolymer wherein at least one is a low-density polyethylene copolymer having a density lower than 0.915 g/cm3;
b) calcinated kaolin in an amount greater than 3 phr;
c) a metal hydroxide in an amount greater than 10 phr; and
d) an alkyl or alkenyl alkoxy siloxane,
wherein the alkyl or alkenyl alkoxy siloxane is in an amount ratio of from 1:25 to 1:50 with respect to the sum of the amounts of calcinated kaolin and of the metal hydroxide.

US Pat. No. 10,923,245

TERMINAL MATERIAL FOR CONNECTORS AND METHOD FOR PRODUCING SAME

MITSUBISHI MATERIALS CORP...

1. A terminal material for connectors comprising a substrate made of copper or copper alloy and a nickel or nickel alloy layer, a copper-tin alloy layer and a tin layer layered on the substrate in this order, whereinthe tin layer has an average thickness not less than 0.2 ?m and not more than 1.2 ?m,
the copper-tin alloy layer is a compound alloy layer that is mainly composed of Cu6Sn5, with some of the copper in the Cu6Sn5 being substituted by nickel, the copper-tin alloy layer consists of a Cu3Sn alloy layer arranged on at least a part of the nickel or nickel alloy layer and the Cu6Sn5 alloy layer arranged on at least one of the Cu3Sn alloy layer and the nickel or nickel alloy layer, and has an average crystal grain diameter not less than 0.2 ?m and not more than 1.5 ?m, and a part thereof is exposed from a surface of the tin layer,
an exposure area rate of the copper-tin alloy layer exposed from the surface of the tin layer is not less than 1% and not more than 60%,
the nickel or nickel alloy layer has an average thickness not less than 0.05 ?m and not more than 1.0 ?m and an average crystal grain diameter not less than 0.01 ?m and not more than 0.5 ?m, with (a standard deviation of a crystal grain diameter)/(the average crystal grain diameter) being not more than 1.0, and has an arithmetic average roughness Ra at a surface being in contact with the copper-tin alloy layer not less than 0.005 ?m and not more than 0.5 ?m, and wherein
a coefficient of kinetic friction at a surface thereof is not more than 0.3.

US Pat. No. 10,923,244

PHOSPHOR SCREEN FOR MEMS IMAGE INTENSIFIERS

Elbit Systems of America,...

1. A phosphor screen for a microelectromechanical image intensifier, comprising:a wafer structure with a naturally opaque top layer and an active area defined within the naturally opaque top layer;
a lattice of interior walls formed from the naturally opaque top layer to define a plurality of pixels within the active area;
a thin film phosphor layer that is disposed directly on a bottom of each pixel of the plurality of pixels, between the lattice of interior walls; and
a reflective metal layer that is disposed atop the thin film phosphor layer, wherein the phosphor screen is configured to receive a plurality of electrons from a component spaced apart from the phosphor screen and the interior walls extend above the reflective metal layer so that the interior walls can absorb or reflect one or more electrons, of the plurality of electrons, that backscatter in one of the plurality of pixels, thereby preventing the one or more electrons from traveling laterally into another pixel of the plurality of pixels,
wherein the thin film phosphor layer has a thickness in the range of approximately 200-300 nanometers,
wherein the thin film phosphor layer is annealed at a temperature in a range of 600° C. to 900° C.

US Pat. No. 10,923,243

GRATING STRUCTURE FOR X-RAY IMAGING

KONINKLIJKE PHILIPS N.V.,...

1. A grating for X-ray imaging, comprising:a grating structure including a first plurality of bar members and a second plurality of gaps; and
a fixation structure arranged between the bar members to stabilize the grating bar members;
wherein the bar members are extending in a length direction and in a height direction and are spaced from each other by one of the gaps in a spacing direction transverse to the height direction and to the length direction, wherein the gaps are arranged in a gap direction parallel to the length direction;
wherein the fixation structure comprises at least one bridging web member that is provided between adjacent bar members of the plurality of bar members;
wherein one bridging web member of the at least one bridging web member is longitudinal that extends in the gap direction and that is provided in an inclined manner in relation to the height direction, wherein an inclination is provided in the gap direction; and
wherein the one bridging web member of the at least one bridging web member includes an inclined portion, the inclined portion of the one bridging web member extends along an inclined direction with a constant dimension in the spacing direction and the inclined direction is perpendicular to the spacing direction and is different from the height direction and the length direction.

US Pat. No. 10,923,242

RADIOISOTOPE PRODUCTION TARGET INSERT DESIGN AND TARGET HARVESTING METHODOLOGY FOR LONG TERM IRRADIATION IN COMMERCIAL NUCLEAR REACTORS

Westinghouse Electric Com...

1. A method of irradiating an isotope in a commercial nuclear reactor that has a moveable in-core detector system including detectors that travel in retractable thimbles that extend from a seal table, outside the nuclear reactor, up into a pressure vessel of the nuclear reactor and through instrument thimbles within fuel assemblies supported within a reactor core, the moveable in-core detector system further including a multi-path selector, positioned on an upstream side of the seal table, that selects the retractable thimbles through which the detectors travel, the method comprising the steps of:providing an elongated, hollow, target specimen cable sized to travel in one of the retractable thimbles with the target specimen cable being sealed at a lead end and having a removable plug that is configured to fit into a trailing end, the target specimen cable having a length sufficient to extend out of the seal table when the target specimen is fully inserted in a preselected, substantially fully extended retractable thimble;
loading one or more target specimens through the trailing end into a forward location in the hollow of the target specimen cable;
closing off the trailing end with the removable plug;
identifying the preselected retractable thimble that extends into the instrument thimble into which the target specimen cable is to be loaded;
inserting the lead end of the target specimen cable into the preselected retractable thimble;
driving the target specimen cable through the retractable thimble and into the instrument thimble to an elevation that places the target specimen at a predetermined elevation;
irradiating the target specimen at the predetermined elevation for a preselected period of time; and
withdrawing the target specimen cable from the instrument thimble after the preselected period of time and out of the preselected retractable thimble to a processing area where it can be loaded into a shielded transportation cask.

US Pat. No. 10,923,241

CONCRETE CASK

Hitachi Zosen Corporation...

1. A concrete cask comprising:a metal canister accommodating spent fuel;
a concrete container body for accommodating the canister inside the container body;
a cooling passage provided between an external peripheral surface of the canister and an internal peripheral surface of the container body, and allowing air for cooling the external peripheral surface of the canister to pass; and
a top space provided between a top surface of the canister, and inside of a lid of the container body, wherein
a baffle plate for suppressing introduction of air rising through the cooling passage to the top space is provided,
wherein the baffle plate is mounted on a top external peripheral surface of the canister, and has such a shape that an external periphery around a top end of the canister expands towards a top.

US Pat. No. 10,923,240

METHODS RELATED TO VALVE ACTUATORS HAVING MOTORS WITH PEEK-INSULATED WINDINGS

Flowserve Management Comp...

1. A method of operating a nuclear reactor, comprising:operating a valve actuator to open and close a valve in fluid communication with a nuclear reactor fluid control system; and
driving the valve actuator with an electric motor by rotating an armature of the electric motor with windings of magnet wires of the electric motor, each individual wire of windings of the magnet wires comprising a respective layer of insulating material disposed over and around a conductor of each individual wire, the layer of insulating material comprising polyetheretherketone (PEEK), the layer of insulating material having a thickness between about 0.025 mm and about 0.381 mm and configured to protect functionality of the windings, each of the windings of the magnet wires being directly treated with an impregnating resin after the windings of the magnet wires are formed and wound, the impregnating resin configured to act as a binding agent for structural integrity and provide a barrier to at least one harsh environment in order to at least partially reduce degradation of the layer of insulating material for of the windings of the magnet wires.

US Pat. No. 10,923,239

MOVING AN ENTIRE NUCLEAR REACTOR CORE AS A UNITARY STRUCTURE

SMR INVENTEC, LLC, Camde...

1. A method of fueling a nuclear reactor, the method comprising:a) opening a nuclear reactor vessel;
b) moving a fully assembled nuclear fuel cartridge from a position outside of the nuclear reactor vessel to a position within an interior cavity of the nuclear reactor vessel, the nuclear fuel cartridge comprising a unitary support structure and a plurality of nuclear fuel assemblies preassembled in the unitary support structure and arranged to collectively form a fuel core, the fuel core mounted in the unitary support structure; and
c) closing the nuclear reactor vessel;
wherein the unitary support structure comprises: a bottom core plate, a top core plate, and a plurality of vertically-oriented longitudinal connecting rods interconnecting the top and bottom core plates together;
wherein the nuclear fuel cartridge comprises a reflector cylinder coupled to the unitary, support structure and circumscribing the nuclear fuel core, the reflector cylinder comprising a plurality of arcuately shaped wall segments coupled together, the longitudinal connecting rods extending in a vertical direction through and inside the wall segments at a peripheral portion of the fuel cartridge;
wherein the plurality of connecting rods extend axially between and are fixedly coupled to the top and bottom core plates to sandwich the wall segments of the reflector cylinder therebetween.

US Pat. No. 10,923,238

DIRECT REACTOR AUXILIARY COOLING SYSTEM FOR A MOLTEN SALT NUCLEAR REACTOR

TerraPower, LLC, Bellevu...

1. A molten fuel nuclear reactor comprising:at least one reflector surrounding a reactor core, the reactor core for containing a portion of the nuclear fuel and having an upper region and a lower region;
a heat exchanger circuit separated from the reactor core by a reflector, the heat exchanger circuit connected to the upper region via an upper fuel salt transfer duct and connected to the lower region via a lower fuel salt transfer duct and the heat exchanger circuit including:
a direct reactor auxiliary cooling system (DRACS) heat exchanger wherein the DRACS heat exchanger is a shell and tube heat exchanger having a first shell and a plurality of vertical tubes passing through the first shell configured to remove heat from nuclear fuel flowing through the plurality of vertical tubes and transfer the heat to a DRACS coolant;
a primary heat exchanger that is a shell and tube heat exchanger having a second shell though which the plurality of vertical tubes also passes, the primary heat exchanger configured to remove heat from nuclear fuel flowing through the plurality of vertical tubes and transfer the heat to a primary coolant;
the DRACS heat exchanger located above the primary heat exchanger;
the plurality of vertical tubes fluidicly connected at an upper end to the upper region of the reactor core via the upper fuel salt transfer duct and at the lower end to the lower region of the reactor core via the lower fuel salt transfer duct;
an impeller configured to drive circulation of the nuclear fuel through the plurality of vertical tubes;
wherein the first shell of the DRACS heat exchanger and the second shell of the primary heat exchanger are a continuous shell separated by an internal tubesheet through which the plurality of vertical tubes penetrate, the internal tubesheet configured to separate the DRACS coolant from the primary coolant; and
wherein all nuclear fuel that flows through the plurality of vertical tubes of the heat exchanger circuit flows through both the DRACS heat exchanger and the primary heat exchanger.

US Pat. No. 10,923,237

DEBRIS FILTERS FOR NUCLEAR FUEL ASSEMBLY AND METHOD OF USING THE SAME

1. A debris filter useable in a nuclear reactor, the filter comprising:a lower section including,
a first plate having a plurality of peaks and valleys alternating in a transverse direction, and
a second plate having a plurality of peaks and valleys alternating in the transverse direction, wherein,
the peaks of the first plate touch the valleys of the second plate so as to form a plurality of channels between the first and the second plates, and
at least one of the first plate and the second plate includes cut-out features that permit fluid coolant flow between the channels and entrap debris, wherein the cut-out features include diamond-shaped windows with two acute interior angles and sized to match debris flowing through the channels, wherein the cut-out features further include a plurality of triangle notches each cut out from a lowest terminal edge of the channels, and wherein all of the cut-out features are less than 1 centimeter in a longest dimension and on a lower half of the first plate and the second plate, and wherein the first plate and the second plate are otherwise continuous; and
an upper section joined to the lower section by a plurality of ligaments extending vertically between the upper section and the lower section in a gap section, and wherein each of the plurality of ligaments includes a profile twist to impart swirl to a fluid flowing through the debris filter, wherein the plurality of ligaments do not overlap transversely with any opening of the channels except for corners of the ligaments in the profile twist extending transversely with the openings of the channels.

US Pat. No. 10,923,236

SYSTEM AND METHOD FOR SMALL, CLEAN, STEADY-STATE FUSION REACTORS

THE TRUSTEES OF PRINCETON...

1. A method for widening and densifying a scrape-off layer (SOL) in a field reversed configuration (FRC) fusion reactor, the FRC fusion reactor including a main region having a FRC core surrounded by the SOL, a gas box connected at an end of the main region to the SOL, the gas box including a gas inlet system and an exit orifice, the exit orifice connecting the gas box to the SOL, the method comprising:lowering a temperature of plasma in the gas box by injecting gas into the gas box via the gas inlet system such that the plasma in the gas box is cooler than both core plasma and SOL plasma surrounding the core plasma;
allowing the plasma in the gas box to flow into the SOL of the main region via the exit orifice;
adjusting a radius and length of the exit orifice to set a width and density of the SOL by:
adjusting the radius such that a magnetic flux of plasma in the exit orifice is about equal to a magnetic flux of plasma at an axial midplane of the main region; and
adjusting the length such that gas from the gas box flowing into the main region is minimized; and
populating the SOL with the plasma that has flowed out of the gas box.

US Pat. No. 10,923,235

ORTHOTIC SUPPORT AND STIMULUS SYSTEMS AND METHODS

Articulate Labs, Inc., A...

1. A system comprising:at least one memory;
at least one electrode;
at least one sensor comprising at least one of: at least one additional electrode, at least one accelerometer, at least one positional angular sensor, or combinations thereof;
at least one controller, coupled to the at least one memory, to perform steps comprising:
(a)(i) measure a first movement or position of a limb attached to a user's joint via the at least one sensor;
(a)(ii) measure a second movement or position of the limb attached to the joint via the at least one sensor;
(a)(iii) condition the measurement of the first movement or position of the limb via at least one signal conditioner, the at least one signal conditioner including a frequency filter and an analog-to-digital (A/D) converter;
(a)(iv) condition the measurement of the second movement or position of the limb via the at least one signal conditioner;
(b)(i) model a first internal force applied to the joint based on the conditioned measurement of the first movement or position of the limb attached to the joint at a first point in time;
(b)(ii) model a second internal force applied to the joint based on the conditioned measurement of the second movement or position of the limb attached to the joint at a second point in time;
(c)(1) compare the first and the second modeled internal forces; and
(c)(2) stimulate muscle of the user, via the at least one electrode, based on the comparison.

US Pat. No. 10,923,234

ANALYSIS AND VERIFICATION OF MODELS DERIVED FROM CLINICAL TRIALS DATA EXTRACTED FROM A DATABASE

1. A method comprising:obtaining, from at least one online database, clinical study information, the clinical study information including information corresponding to a number of models that predict a progression of one or more diseases and population summary data that indicates characteristics of groups of individuals involved in a plurality of clinical studies with respect to the one or more diseases;
identifying a first model from among the number of models that predicts the progression of a disease of the one or more diseases, wherein the first model is derived from a first portion of the clinical study information and the progression of the disease includes a plurality of states;
identifying a second model from among the number of models that predicts the progression of the disease, wherein the second model is derived from a second portion of the clinical study information;
generating an aggregate model that includes a first coefficient corresponding to the first model and a second coefficient corresponding to the second model,
generating, based on the population summary data, a virtual population including a number of virtual individuals;
determining, based on data related to virtual individuals included in the virtual population, first simulated outcomes of the aggregate model using a first value of the first coefficient and a second value of the second coefficient, wherein:
individual first simulated outcomes of the first simulated outcomes indicate a first probability of a virtual individual of the virtual population progressing from one state of the disease to another state of the disease over a period of time;
the first value of the first coefficient corresponds to a first amount of contribution of the first model in determining the first simulated outcomes; and
the second value of the second coefficient corresponds to a second amount of contribution of the second model in determining the first simulated outcomes;
analyzing the first simulated outcomes with respect to first observed outcomes obtained from the clinical study information to determine first differences between the first simulated outcomes and the first observed outcomes;
modifying, based on the first differences, at least one of the first coefficient or the second coefficient to determine second simulated outcomes of the aggregate model based on the data related to the virtual individuals included in the virtual population; and
determining a measure of fitness of the aggregate model based on differences between the second simulated outcomes and second observed outcomes obtained from the clinical study information and based on a fitness function corresponding to the aggregate model moving toward a local minimum.

US Pat. No. 10,923,233

COMPUTER NETWORK ARCHITECTURE WITH MACHINE LEARNING AND ARTIFICIAL INTELLIGENCE AND DYNAMIC PATIENT GUIDANCE

CLARIFY HEALTH SOLUTIONS,...

1. A computer network system with artificial intelligence and machine learning, comprising:a prediction module with a prediction generator and an updated database, and
a learning module with a training submodule, in electronic communication with the prediction module,
a dynamic patient guidance web application (DPGWA) in electronic communication with both the prediction module, and a user device,
wherein, the DPGWA is configured to:
a. log a patient into a the dynamic patient guidance web application,
b. receive data from the patient, updating the data in the system, about the patient behavior and/or compliance with a patient care plan,
c. log out the patient,
d. automatically re-score the patient's risk scores by accessing the patient risk scoring web application,
e. based on the new risk scores, update the patient care plan,
f. send an automated message for the patient to the user mobile device requesting that the patient complete a check-in with the DPGWA and receive the updated patient care plan,
g. create a reminder task for a patient clinical care coordinator to contact the patient, if the patient has not responded within a time period,
h. if the patient has a designated caregiver, send a notification to the designated caregiver either (1) to prompt the patient to respond or (2) to respond on behalf of the patient to provide patient check-in information, and receive the updated patient care plan, and
i. if the patient adheres to their patient care plan, reduce the cadence of interventions by a care coordinator for that patient,
wherein, the learning module is configured to:
receive a list of algorithm definitions and datasets for patient risk scoring,
automatically calibrate one or more defined algorithms with the database,
test the calibrated algorithms with a plurality of evaluation metrics,
store the calibrated algorithms and evaluation metrics in a library,
automatically select an algorithm for patient risk scoring based on the evaluation metrics,
update further the database with third party data, and with user episode data, and
re-execute the calibrate, test, store, and select steps after the update of the database step,
wherein, the prediction generator is configured to:
receive a user prediction request for patient risk scoring, including episode data and a client model,
run the currently selected algorithm corresponding to the user of the episode data, and generate patient risk scoring prediction output,
generate a patient risk scoring prediction report based on the algorithm output, and transmit the patient risk scoring prediction report to the user,
wherein, the algorithm definitions are of types that are members of the group comprising:
multi-level models,
random forest regression,
logistical regression,
gamma-distributed regression, and
linear regression;
the third party data is from a party that is a member of the group comprising:
hospitals,
medical practices,
insurance companies,
credit reporting agencies, and
credit rating agencies;
the database includes patient medical data, patient personal data, patient outcome data, and medical treatment data;
the episode data includes individual patient medical data and personal data; and
the user is a member of the group comprising:
hospitals,
medical practices, and
insurance companies,
wherein the user device is remote from the prediction module, and the user device is a member of the group comprising:
a computer,
a desktop PC,
a laptop PC,
a smart phone,
a tablet computer, and
a personal wearable computing device,
wherein the web application communicates with the user device by the Internet, or an extranet, or a VPN, or other network, and the web application is generic for any user, or customized for a specific user, or class of user, and
wherein, the user prediction request requests calibration of the correlation of demographic, social and medical attributes of the patient, to the outcome of a specific patient clinical episode type.

US Pat. No. 10,923,232

SYSTEM AND METHOD FOR IMPROVING THE SPEED OF DETERMINING A HEALTH RISK PROFILE OF A PATIENT

Healthcare Interactive, I...

1. A method for improving the speed of determining a health risk profile associated with a patient, comprising:using a device processor to execute instructions stored on a non-transitory computer readable medium to perform the following steps:
retrieving patient medical information about the patient, wherein the patient medical information is an uncoded natural language expression in a first language;
comparing the patient medical information with records in a first database, the first database including a plurality of records, wherein at least one record in the first database has unique preselected medical information and a first predetermined code associated with the preselected medical information, and wherein the preselected medical information is also an uncoded natural language expression in the first language;
determining if the patient medical information matches one of the records in the first database by comparing the patient medical information with the preselected medical information of the records in the first database;
if the patient medical information matches the preselected medical information, performing a first data conversion procedure in a first location in a first geographic region by immediately assigning the first predetermined code associated with the preselected medical information to the patient medical information; and
if the patient medical information fails to match any record in the first database, performing a second data conversion procedure more slowly than the first data conversion procedure by sending the patient medical information to a translation resource in a second location in a second geographic region remote from the first geographic region, and receiving translated patient medical information from the translation resource, wherein the translated patient medical information is in a second language; sending the translated patient medical information to a coding resource; and receiving, from the coding resource, a second predetermined code associated with the patient medical information; and
determining a health risk profile for the patient using one of the first predetermined code and the second predetermined code;
the method further including making a determination of a level of confidence that the patient medical information matches the preselected medical information;
wherein determining if the patient medical information matches one of the records in the first database is performed by determining whether the level of confidence exceeds a first predetermined threshold; and
wherein, if the level of confidence exceeds a second predetermined threshold that is higher than the first predetermined threshold, the method further includes: performing a third data conversion procedure faster than the first data conversion procedure by immediately assigning a first health risk index associated with the preselected medical information to the patient medical information; and determining a health risk profile for the patient using the first health risk index.

US Pat. No. 10,923,231

DYNAMIC SELECTION AND SEQUENCING OF HEALTHCARE ASSESSMENTS FOR PATIENTS

International Business Ma...

1. A computer program product comprising a computer readable storage medium having a computer readable program stored therein, wherein the computer readable program, when executed on a computing device, causes the data processing system to implement a health assessment system for administering health care assessments to a patient, and further causes the computing device to:analyze, by a patient information analysis engine of the health assessment system, patient information, from a plurality of patient information sources, stored in a patient registry;
determine, by a health assessment guideline selection engine of the health assessment system, a plurality of health care assessments to be administered to the patient based on the patient information and one or more pre-defined health care assessment guidelines specifying conditions for which health care assessments are to be administered to patients and timing for administering the assessments to the patients, wherein the computer readable program to determine the plurality of health care assessments to be administered to the patient further causes the computing device to:
perform, by natural language processing (NLP) logic of the health assessment system, natural language processing on the one or more pre-defined health care assessment guidelines to identify one or more trigger conditions for each of the health care assessments; and
select, by the health assessment guideline selection engine, a health care assessment to include in the sequence of health care assessments to be administered to the patient based on the patient information indicating that a trigger condition in the one or more trigger conditions associated with the health care assessment is present in the patient information, wherein the trigger condition is at least the patient failing to respond to one or more attempts to communicate with the patient in accordance with a selected communication workflow:
generate, by a health assessment personalization engine of the health assessment system, a sequence of health care assessments to be administered to the patient, in the plurality of health care assessments to be administered to the patient, based on the one or more pre-defined health care assessment guidelines and the patient information, wherein the sequence of health care assessments to be administered to the patient comprises an ordering of the health care assessments to be administered to the patient and a timing interval between the health care assessments to be administered to the patient based on the one or more pre-defined health care assessment guidelines and the patient information; and
administer, by assessor system associated with the health assessment system, at least one health care assessment to the patient in accordance with the sequence of health care assessments to be administered to the patient.

US Pat. No. 10,923,230

METHOD AND APPARATUS FOR PREDICTING RESPONSE TO FOOD

Yeda Research and Develop...

1. A method of treating a subject having a disease which is affected by food intake, the method comprising:presenting the subject with a list of foods on a user interface device, and receiving from the user interface device a selected food to which a response of the subject is unknown;
accessing a computer readable medium storing a first database having data describing the subject but not a response of the subject to said selected food;
accessing a computer readable medium storing a second database having data pertaining to responses of other subjects to foods, said responses of said other subjects including responses of at least one other subject to said selected food or a food similar to said selected food;
analyzing said databases based on said selected food to estimate the response of the subject to said selected food; and
displaying on said user interface device a personalized diet, based on said estimate, thereby treating the subject having the disease.

US Pat. No. 10,923,229

DETERMINING NEW KNOWLEDGE FOR CLINICAL DECISION SUPPORT

Cerner Innovation, Inc.

1. One or more computer-readable storage devices having computer-usable instructions embodied thereon that, when executed by a processor, perform a method for discovering and validating latent relationships in a health care dataset, the method comprising:receiving, at a multi-agent system, a target set of clinical information associated with a target population of patients from a first set of records of a first health-records system, the target set of clinical information including a first plurality of codified clinical concepts;
receiving, at the multi-agent system, a reference set of clinical information associated with a reference population of patients from a second set of records of a second health records system, the reference set of clinical information including a second plurality of codified clinical concepts;
based on the reference set of clinical information and one or more reference sensor indications of a reference patient in the reference population, determining, at the multi-agent system, a probable future clinical decision support event that is common after at least a first time period after the one or more reference sensor indications in the second set of records for the reference population of patients and clustering the second set of records for the reference population of patients based on a change in condition;
discovering, at the multi-agent system, frequent item-sets among the second set of patients that are clustered based on the change in condition;
associating, at the multi-agent system, the frequent item-sets with the probable future clinical decision support event;
training a machine learning agent of the multi-agent system to determine a reference predicate vector pattern associated with a decision epoch for the probable future clinical decision support event based on the reference set of clinical information and on the one or more reference sensor indications of a reference patient in the reference population, wherein the decision epoch represents a future time instance that is also occurring prior to the probable future clinical decision support event;
receiving, at the multi-agent system, sensor information from a sensor coupled to at least one target patient;
based on a change in a target vector element associated with the sensor information, determining, utilizing the trained machine learning agent of the multi-agent system, an onset of the decision epoch based on determining a distance metric between the target vector element and a reference predicate vector from the reference predicate vector pattern;
based on the onset of the decision epoch, automatically and dynamically determining, at the multi-agent system, an altered course of care for the at least one target patient from the target population of patients; and
causing for display, by the multi-agent system, within an interface, the altered course of care for the at least one target patient from the target population of patients by:
(1) notifying one of the following of the probable future clinical decision support event: (i) a target patient among the target population of patients, (ii) a health care professional, and (iii) a medical organization; and
(2) providing an indication of one or more alternative clinical recommendations within the decision epoch.

US Pat. No. 10,923,228

DOWNLOADING AND BOOTING METHOD AND SYSTEM FOR A WEARABLE MEDICAL DEVICE

ZOLL Medical Corporation,...

1. A wearable medical monitoring device, comprising:a plurality of ECG electrodes configured to receive an ECG signal of a patient when the wearable medical monitoring device is worn by the patient; and
a monitor coupled to the plurality of ECG electrodes, the monitor configured to detect an impending cardiac event based on the received ECG signal of the patient;
at least one processor disposed in the monitor, the at least one processor configured to execute a plurality of instructions to implement an update manager wherein the update manager is configured to
receive a software update corresponding to the at least one software module for the monitor,
determine an event estimation of risk score for a predetermined period of time;
cause an installation of the software update during the predetermined period of time when the event estimation of risk score indicates a low likelihood of an impending cardiac event during the predetermined period of time; and
cause a delay in the installation of the software update during the predetermined period of time where the event estimation of risk score indicates a high likelihood of impending cardiac event during the predetermined period of time.

US Pat. No. 10,923,227

TRACKING PROGRAM INTERFACE

Episode Solutions, LLC, ...

1. A method for tracking a user device, comprising:at one or more computing devices:
receiving data for a first user including a first identifier associated with the first user;
generating and storing a first tracking program for the first user, the first tracking program including:
the first identifier associated with the first user;
a first indicated area for a first user device associated with the first user; and
a first time period when the first user is scheduled to be located within the first indicated area, wherein the first time period includes a designated start time and a designated stop time;
after generating and storing the first tracking program and at the first time period when the first user is scheduled to be located within the first indicated area, determining, from a position detection system in the first user device, a first determined position of the first user device;
comparing the first determined position of the first user device with the first indicated area; and
in accordance with a determination that the first determined position of the first user device does not correspond to the first indicated area for a duration of the first time period, transmitting, to a first remote management device, a first tracking alert indicating that the first user is not within the first indicated area within the first time period;
determining whether a response is received from the first remote management device; and
in accordance with a determination that the response is not received from the first remote management device, transmitting alert information to a second remote management device that is distinct from the first remote management device.

US Pat. No. 10,923,226

SYSTEMS, METHODS AND ARTICLES FOR MONITORING AND ENHANCING HUMAN WELLNESS

Delos Living LLC, New Yo...

1. A method of operation in a wellness monitoring system which includes at least one processor, a plurality of body worn sensors, and a plurality of ambient environmental sensors, and at least one nontransitory processor-readable medium which stores at least one of processor-executable instructions or data communicatively coupled to the at least one processor, the method comprising: sensing biometric data by at least one body worn sensor integrated into an armband worn by a first individual, wherein the at least one body worn sensor is communicatively coupled to the at least one processor and is configured to transmit the biometric data to the at least one processor; repeatedly determining by the at least one processor a respective value of at least one wellness parameter associated with the first individual from the biometric data; sensing environmental data by at least one ambient environmental sensor located in an environment which the first individual occupies, wherein the at least one ambient environmental sensor is communicatively coupled to the at least one processor and is configured to transmit environmental data to the at least one processor; repeatedly determining by the at least one processor a respective value of at least one wellness parameter associated with the environment which the first individual occupies from the environmental data; autonomously tracking over time the at least one wellness parameter associated with the first individual; assessing a wellness of the first individual by the at least one processor by comparing the determined value of the at least one wellness parameter associated with the first individual to a target range for the at least one wellness parameter defined in a wellness protocol; and upon determining the at least one wellness parameter associated with first individual is outside the target range, identifying at least one wellness parameter associated with the environment corresponding with the at least one wellness parameter associated with the first individual that is outside the target range, and automatically causing by the at least one processor, a transmission of an electronic message to an electronic device associated with the first individual and configured to display the electronic message, the electronic message prompting the first individual to take an action based at least in part on the assessment and the identified at least one wellness parameter associated with the environment; upon determining the at least one wellness parameter associated with first individual is outside the target range, causing at least one actuator to dynamically adjust at least one operational parameter of at least one active subsystem in the wellness monitoring system based at least in part on the assessment and the identified at least one wellness parameter associated with the environment.

US Pat. No. 10,923,225

ATHLETIC PERFORMANCE SENSING AND/OR TRACKING SYSTEMS AND METHODS

NIKE, Inc., Beaverton, O...

1. A method comprising:establishing, by a sensor device, data communication with a piece of workout equipment;
transmitting, by the sensor device and to the piece of workout equipment, a first set of data for operating a first function of the piece of workout equipment; and
transmitting, by the sensor device and to the piece of workout equipment, a first set of activity data corresponding to an activity performed by a user during a first time period, wherein the piece of workout equipment is configured to display the first set of activity data.

US Pat. No. 10,923,224

NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM, SKILL DETERMINATION METHOD, SKILL DETERMINATION DEVICE AND SERVER

FUJITSU LIMITED, Kawasak...

1. A non-transitory computer-readable recording medium having stored therein a skill determination program that causes a computer to execute a process comprising:calculating each degree of similarity between each position information of a feature point of a plurality of first frames and position information of a feature point of a second frame to obtain a plurality of degrees of similarity, where the feature point of each of the first frames corresponds to a predetermined part or a joint of a body of a first user and the feature point of the second frame corresponds to the predetermined part or the joint of the body of a second user;
identifying a selected first frame, among the plurality of first frames, that corresponds to the second frame based on a degree of similarity from the plurality of degrees of similarity;
comparing a first time of the selected first frame with a second time of a previously selected first frame which has already been matched to a previous second frame;
setting a weight of the selected first frame to a first value when the first time is after the second time and a difference between the first time and the second time is within a predetermined range;
setting the weight to a second value lower than the first value when the first time is after the second time and the difference between the first time and the second time is not within the predetermined range;
setting the weight to a third value lower than the second value when the first time is before the second time;
correcting the degree of similarity using the weight;
re-identifying the selected first frame, among the plurality of first frames based on the degree of similarity, when the degree of similarity has been corrected;
specifying a phase type corresponding to the selected first frame as a type of the second frame, where the plurality of first frames have a plurality of phase types;
generating a plurality of modules which determine a feature amount of a motion of the second user from the feature point included in the second frame, where the modules respectively correspond to the phase types;
selecting one of the modules corresponding to the phase type of the second frame;
outputting the second frame to the one of the modules selected.

US Pat. No. 10,923,223

DATA-ENABLED SYRINGE COLLECTION CONTAINER AND SYSTEMS USING SAME

DOSECUE, LLC, Philadelph...

1. A data-enabled syringe collection container, comprising:a) an upper inlet body, comprising: an inlet lid; a first opening; an entry channel; and a receiving assembly, wherein the inlet lid is configured for covering and accessing the first opening and the entry channel is configured to provide a passageway from the first opening to the receiving assembly, and wherein the receiving assembly comprises a dropout door configured to allow passage through a second opening into the container body;
b) a container body coupled to the upper inlet body; and
c) an electronics module configured for sensing and tracking dose events, the electronics module coupled to at least one of the upper inlet body and the container body.

US Pat. No. 10,923,222

SYSTEM FOR ADMINISTERING A PHARMACEUTICAL PRODUCT

NOVARTIS AG, Basel (CH)

1. A system for administering a pharmaceutical product, comprising:a container accommodating a pharmaceutical product, the container comprising a wireless communication unit and a memory which stores an administration scheme specifically adapted to the pharmaceutical product accommodated in the container, the administration scheme specifying at least one administration-related parameter to be adhered to in administering the pharmaceutical product to a patient;
a wireless communication device configured to read the administration scheme from the memory of the container and to replicate the administration scheme, including information about the pharmaceutical product, on a remote server; and
a remote server configured to (i) store patient-related information including medications prescribed to the patient in an electronic patient record, (ii) perform, based on the patient-related information stored in the electronic patient record, an analysis, (iii) generate an alert in response to the pharmaceutical product and one or more of other medications prescribed to the patient being incompatible, and (iv) instruct the wireless communication device to write data into the memory of the container marking the container as unusable so as to prevent further use of the container,
wherein the wireless communication device is configured to communicate with the remote server via wireless communication.

US Pat. No. 10,923,221

SYSTEM AND METHOD FOR ADMINISTERING MEDICATIONS

Allscripts Software, LLC,...

1. A mobile electronic device comprising a display and a computer readable medium storing a computer program for providing a medication administration workflow in a user-interface (UI), the computer program executable by at least one processor, the computer program comprising sets of instructions for facilitating a method comprising:displaying, to a healthcare provider user via the display, an interface of an electronic health record (EHR) software application comprising a listing of patients;
receiving, from the healthcare provider user via the interface, first user input corresponding to a selection of a first patient included in the listing of patients;
receiving, from the healthcare provider user via the interface, second user input corresponding to engagement with a scan button;
displaying, to the healthcare provider user via the display in response to the received second user input corresponding to engagement with the scan button, a scan window that includes an image captured by the mobile electronic device and allows the healthcare provider user to scan a wrist band of a patient by positioning the mobile electronic device to align the barcode of the wrist band within the scan window;
capturing, via the mobile electronic device, the barcode of the wrist band;
determining, based on the captured barcode of the wrist band, that the wrist band matches to the first patient, and based thereon allowing the healthcare provider to scan in medications for the first patient;
while continually displaying, to the healthcare provider user via the display, the scan window that includes an image captured by the mobile electronic device and allows the healthcare provider user to scan a barcode of one or more medications by repeatedly positioning the mobile electronic device to align a barcode of a medication within the scan window,
capturing, via the mobile electronic device, a barcode of a first medication,
determining, based on the captured barcode of the first medication, that the first medication matches to a medication to be taken by the first patient, and based thereon temporarily displaying a pop-up match indication that subsequently dismisses without user intervention,
capturing, via the mobile electronic device, a barcode of a second medication,
determining, based on the captured barcode of the second medication, that there is a first issue with matching the second medication to a medication to be taken by the first patient, and based thereon temporarily displaying a pop-up issue indication that indicates the first issue and that subsequently dismisses without user intervention,
capturing, via the mobile electronic device, a barcode of a third medication,
determining, based on the captured barcode of the third medication, that the third medication matches to a medication to be taken by the first patient, and based thereon temporarily displaying a pop-up match indication that subsequently dismisses without user intervention;
receiving, from the healthcare provider user via the interface, third user input corresponding to closing of the scan window, and based thereon displaying a medication list including at least the scanned first, second, and third medications and a respective status for each, including indications that the first and third medications match to a medication to be taken by the first patient and an indication of the first issue with matching the second medication to a medication to be taken by the first patient;
receiving, from the healthcare provider user via the interface, fourth user input corresponding to selecting of one of the medications in the medication list, the selected medication being the second medication; and
displaying, to the healthcare provider user, one or more interface elements configured to allow the user to address any outstanding action items for resolving the first issue associated with the selected second medication.

US Pat. No. 10,923,220

PROGRAM, DEVICE, SYSTEM AND METHOD FOR PATIENT WHO IS ATTEMPTING TO QUIT SMOKING

CUREAPP, INC., Tokyo (JP...

1. A non-transitory computer-readable medium with instructions stored thereon, that when executed by a processor, perform the steps comprising:prompting a patient-side device to display:
a message that requests a patient to input report information indicating whether the patient has smoked; and
a message that requests the patient to provide a biological sample to a biomarker concentration meter that measures a biomarker concentration indicating an actual smoking state of the patient;
receiving, from the patient-side device, the report information input by the patient;
receiving, from the biomarker concentration meter, a biomarker concentration measurement value measured from the biological sample by the biomarker concentration meter;
comparing the biomarker concentration measurement value with a biomarker concentration reference value to determine consistency between the biomarker concentration measurement value and the report information for determining whether the report information input by the patient is false;
based on a result of the consistency determination and the actual smoking state of the patient, generating smoking cessation therapy information for smoking cessation therapy to be performed for the patient; and
transmitting the smoking cessation therapy information to the patient-side device that presents information for the smoking cessation therapy to the patient based on the smoking cessation therapy information.

US Pat. No. 10,923,219

METHOD TO ASSIGN WORD CLASS INFORMATION

Nuance Communications, In...

1. A method comprising:analyzing text relating to medical treatment of a patient to identify one or more concepts expressed in the text, wherein the analyzing of the text comprises acts of:
mapping at least some words and/or phrases included in the text to a plurality of corresponding classes, one or more of the plurality of corresponding classes each indicating a category of information of a plurality of categories of information to which a corresponding word and/or phrase included in the text relates;
mapping at least some of the plurality of corresponding classes to one or more particular combinations of corresponding classes, wherein the mapping of the at least some of the plurality of corresponding classes to the one or more particular combinations comprises determining whether any of a plurality of combinations of corresponding classes appears in the at least some of the plurality of corresponding classes;
determining a distance between corresponding classes mapped to the one or more particular combinations of corresponding classes; and
identifying one or more concepts expressed in the text based at least in part on the determined distance between corresponding classes mapped to the one or more particular combinations of corresponding classes.

US Pat. No. 10,923,218

DATA SYNCHRONIZATION BETWEEN TWO OR MORE ANALYTE DETECTING DEVICES IN A DATABASE

ABBOTT DIABETES CARE INC....

1. A diabetes management system, comprising:a plurality of analyte measurement devices; and
a centralized server configured for data communication with the plurality of analyte measurement devices;
wherein each of the plurality of analyte measurement devices comprises:
a diabetes management software application; and
one or more processors coupled to a memory, the memory being configured to store instructions that, when executed by the one or more processors, cause the one or more processors to transmit one or more communications to the centralized server, the one or more communications comprising:
a version number associated with the diabetes management software application,
a unique patient ID associated with a user of the analyte measurement device,
data indicative of measured analyte levels associated with the user of the analyte measurement device, and
one or more timestamps associated with the data indicative of measured analyte levels, and
wherein the centralized server includes at least one computer readable medium having instructions executable by at least one processing device that, when executed, cause the at least one processing device to:
store the unique patient ID received from each of the plurality of analyte measurement devices in a database, and
aggregate, based on the stored unique patient ID, the data indicative of measured analyte levels from each of the plurality of analyte measurement devices.

US Pat. No. 10,923,217

CONDITION OR TREATMENT ASSESSMENT METHODS AND PLATFORM APPARATUSES

Physiowave, Inc., Menlo ...

1. An apparatus comprising:a platform in which a plurality of electrodes are integrated and configured and arranged for engaging a user;
processing circuitry, including a CPU and a memory circuit with user-corresponding data stored in the memory circuit, configured and arranged under the platform upon which the user stands, the processing circuitry being electrically integrated with the plurality of electrodes and being configured to collect physiologic parameter data from the user while the user is standing on the platform using signals obtained by the plurality of electrodes and force sensor circuitry and to further:
process the user-corresponding data with physiologic parameter data obtained while the user is standing on the platform and therefrom derive and output derivation data indicative of a physiologic status of the user for assessment of a condition or treatment of the user that corresponds with the physiologic status;
send the output derivation data indicative of the physiologic status to external circuitry, that includes a computer processor, for assessment of a condition or treatment of the user that corresponds with the physiologic status;
receive user-directed data indicative of a new dosage for a prescription drug prescribed for the user and associated with or in response to the output derivation data; and
collect or track, via the platform, further physiologic parameter data obtained while the user is standing on the platform for assessing if the new dosage for a prescription drug controls symptoms or mitigates side effects associated with the condition or treatment.

US Pat. No. 10,923,216

HEALTH STATUS SYSTEM, PLATFORM, AND METHOD

TensorX, Inc., Nashville...

1. A health status method executed by a processor, comprising:receiving from a test system, by the processor:
a representation of biological sample data of a human sample collected from a human user and analyzed by the test system for an indication of a presence of an infectious disease, and
identification information identifying the user, the biological sample data comprising:
the indication of the presence of the infectious disease;
a time and date of sample collection of the biological sample; and
an identification of the test system, and
the information identifying the identity of the user comprising:
an attestation of the identification of the user recorded in conjunction with collecting the biological sample of the user,
registering and storing the biological sample data in a central storage;
associating the attestation of the user with the biological sample of the user;
generating a certificate of association between the attestation of the user and the biological sample of the user, comprising:
analyzing the attestation of the user,
based on the analysis, verifying that the collected biological sample was obtained from the identified user, and
assigning a time to live for the certificate;
receiving from a venue, an access request for the user to access the venue;
determining the access request is for a time within the period of the time to live; and
providing the certificate of association to the venue.

US Pat. No. 10,923,215

SAMPLE TRACKING VIA SAMPLE TRACKING CHAINS, SYSTEMS AND METHODS

NANT HOLDINGS IP, LLC, C...

1. A biological sample tracking system, comprising:a sample database storing sample tracking chains, each sample tracking chain representing a life cycle of a biological sample; and
at least one processor coupled to the sample database and configured to:
obtain a digital image of a target biological sample;
execute an image processing algorithm on the digital image to derive digital sample descriptors from the digital image, the descriptors derived directly from the target biological sample to represent the intrinsic nature of the target biological sample;
retrieve at least a portion of a sample tracking chain from the sample database by submitting the derived digital sample descriptors to the sample database to identify the sample tracking chain according to one or more similarity measures between the derived digital sample descriptors and previously indexed descriptors in the sample database, the sample tracking chain corresponding to the target biological sample;
retrieve a previous sample state object from the sample tracking chain;
generate a current state representation of an observed state of the target biological sample;
instantiate a current sample state object in the memory as a function of the current state representation and the previous sample state object;
link the current sample state object to the previous sample state object in the sample tracking chain; and
update the sample tracking chain in the sample database with the current sample state object.

US Pat. No. 10,923,214

NEURAL NETWORK FOR PREDICTING DRUG PROPERTY

Accutar Biotechnology Inc...

1. A computer-implemented method for predicting molecule properties, the method comprising:determining a plurality of molecular descriptors associated with a first compound;
determining one or more three-dimensional (3D) conformations of the first compound;
training a neural network using a training set comprising:
the plurality of molecular descriptors associated with the first compound, and
the one or more 3D conformations of the first compound,
wherein training the neural network comprises determining a plurality of features that affect energies of the one or more 3D conformations of the first compound;
receiving an input file of a second compound;
implementing the neural network to determine, based on the input file and a plurality of molecular descriptors associated with the second compound, molecular configurations of the second compound docketed in a protein;
generating, using the neural network, one or more 3D models of the second compound based on the determined molecular configurations of the second compound;
determining, using the neural network, energy scores of the one or more 3D models; and
determining, using the neural network, a property of the docked second compound based on the energy scores.

US Pat. No. 10,923,212

MEMORY CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A memory control method, for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, and the memory control method comprises:reading first data from a first physical unit among the physical units;
decoding the first data by a decoding circuit;
updating reliability information corresponding to a first voltage range according to the decoded first data, wherein the first voltage range is one of a plurality of voltage ranges identified by a plurality of voltage levels;
reading second data from a second physical unit among the physical units; and
decoding data comprised in the second data by the decoding circuit according to the updated reliability information, wherein the data decoded according to the updated reliability information is data read from at least one memory cell having a voltage within the first voltage range.

US Pat. No. 10,923,211

EFFICIENT SCRAMBLING AND ENCODING FOR COPYBACK PROCEDURES IN A MEMORY SUBSYSTEM

MICRON TECHNOLOGY, INC., ...

1. A method comprising:determining to move first encoded data from a first location in a memory die to a second location in the memory die;
combining, in response to determining to move the first encoded data from the first location in the memory die to the second location in the memory die, a starting seed, which is associated with the first location, with a destination seed, which is associated with the second location, to produce a combined seed;
generating a pseudorandom sequence based on the combined seed;
combining the first encoded data with the pseudorandom sequence to produce second encoded data, wherein the first encoded data is scrambled based on the starting seed while, based on combining the first encoded data with the pseudorandom sequence, the second encoded data is scrambled based on the destination seed; and
storing the second encoded data in the second location of the memory die.

US Pat. No. 10,923,210

MEMORY DEVICE INCLUDING LOAD GENERATOR AND METHOD OF OPERATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a load generator configured to generate a plurality of memory test loads for a plurality of first memory accesses directed to at least one memory device, the plurality of memory test loads mimicking a plurality of memory access requests for a plurality of second memory accesses from a plurality of master devices of at least two different device types directed to the at least one memory device, each of the plurality of memory test loads being generated based on a respective device type of the corresponding master device of the plurality of master devices; and
a memory controller configured to,
receive the memory test loads from the load generator, and
process the memory test loads, the processing the memory test loads including performing memory operations associated with the plurality of first memory accesses on the at least one memory device,
wherein the memory controller is further configured to process the memory test loads in a manner which is identical to a manner of processing the memory access requests.

US Pat. No. 10,923,209

SEMICONDUCTOR MEMORY DEVICE

WINBOND ELECTRONICS CORP....

1. A semiconductor memory device comprising:a first detection circuit, detecting a supply voltage falling to a constant voltage;
a second detection circuit, having higher detection accuracy than that of the first detection circuit, and detecting the supply voltage falling to the constant voltage;
a selecting device, selecting the second detection circuit while an internal circuit is in a testing state, and selecting the first detection circuit while the internal circuit is not in the testing state; and
a performing device, responding to a detection result from the first detection circuit or the second detection circuit, and performing a power-down operation.

US Pat. No. 10,923,208

SHIFT REGISTER UNIT, SHIFT REGISTER CIRCUIT AND DISPLAY DEVICE

Hefei Xinsheng Optoelectr...

1. A shift register unit, comprising:a detection input circuit coupled to a first clock signal terminal, a second clock signal terminal, a third clock signal terminal, a first input terminal, a first power signal terminal, a pull-up node and a first node, and configured to transmit a signal from the third clock signal terminal to the pull-up node in response to a signal from the first clock signal terminal and a signal from the second clock signal terminal;
a display input circuit coupled to a second input terminal, the pull-up node, and a second power signal terminal, and configured to transmit a signal from the second power signal terminal to the pull-up node in response to a signal from the second input terminal;
an inverter circuit coupled to a third power signal terminal, the pull-up node, a pull-down node, the first node, and the first power signal terminal, and configured to transmit a signal from the third power signal terminal to the pull-down node in response to the signal from the third power signal terminal, transmit a signal from the first power signal terminal to the pull-down node in response to a signal from the pull-up node, and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the pull-down node;
a pull-down circuit coupled to the pull-down node, the first power signal terminal, a fourth power signal terminal, an output terminal, and a first signal output terminal, and configured to, in response to the signal from the pull-down node, transmit the signal from the first power signal terminal to the output terminal and transmit a signal from the fourth power signal terminal to the first signal output terminal;
a reset circuit coupled to the second clock signal terminal, the pull-up node, the first power signal terminal, a third input terminal, and the first node, and configured to transmit the signal from the first power signal terminal to the pull-up node in response to the signal from the second clock signal terminal and transmit the signal from the first power signal terminal to the pull-up node in response to a signal from the third input terminal; and
a first output circuit coupled to a fourth clock signal terminal, the pull-up node, the output terminal, and the first signal output terminal, and configured to transmit a signal from the fourth clock signal terminal to the output terminal and the first signal output terminal in response to the signal from the pull-up node.

US Pat. No. 10,923,207

SHIFT REGISTER UNIT AND METHOD FOR DRIVING THE SAME, GATE DRIVING CIRCUIT AND DISPLAY APPARATUS

ORDOS YUANSHENG OPTOELECT...

1. A shift register unit, comprising:an input sub-circuit connected to a signal input terminal and a signal control terminal, and configured to output an input signal provided at the signal input terminal under control of a control signal provided at the signal control terminal;
a carry signal output sub-circuit connected to a first clock signal terminal and a first enabling signal terminal, and configured to generate a carry signal according to the input signal output by the input sub-circuit, a first clock signal provided at the first clock signal terminal and a first enabling signal provided at the first enabling signal terminal;
an output sub-circuit connected to a second clock signal terminal and configured to generate an output signal according to the carry signal and a second clock signal provided at the second clock signal terminal; and
a latch sub-circuit configured to latch the output signal,
wherein the carry signal output sub-circuit comprises:
a NOR gate having a first input terminal connected to an output terminal of the input sub-circuit;
a sixth transistor and a seventh transistor, wherein a control terminal of the sixth transistor and a control terminal of the seventh transistor are connected to an output terminal of the NOR gate, a first terminal of the sixth transistor is connected to the first clock signal terminal, a second terminal of the sixth transistor is connected to a first terminal of the seventh transistor at a first node, the first node is connected to a second input terminal of the NOR gate, and a second terminal of the seventh transistor is connected to a reference signal terminal;
a fourth inverter having an input terminal connected to the first node;
a fourth transmission gate having an input terminal connected to the first enabling signal terminal, a first gating signal terminal connected to an output terminal of the fourth inverter, and a second gating signal terminal connected to the first node; and
an eighth transistor having a control terminal connected to the first node, a first terminal connected to an output terminal of the fourth transmission gate to act as an output terminal of the carry signal output sub-circuit, and a second terminal connected to a reference signal terminal.

US Pat. No. 10,923,206

SHIFT REGISTER UNIT FOR DISPLAY AND DRIVING METHOD THEREOF, GATE DRIVING DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A shift register unit comprising:a first input circuit, configured to provide a first control signal from a first signal control terminal to a pull-up node according to a first input signal from a first signal input terminal;
a second input circuit, configured to provide a second control signal from a second signal control terminal to the pull-up node according to a second input signal from a second signal input terminal;
a pull-down control circuit, configured to provide a voltage of a first voltage terminal to a pull-down node according to a voltage of the pull-up node, or to control a voltage of the pull-down node according to a first clock signal from a first clock signal input terminal;
an output circuit, configured to provide a second clock signal from a second clock signal input terminal to a signal output terminal as an output signal according to the voltage of the pull-up node;
a pull-down circuit, configured to provide the voltage of the first voltage terminal to the pull-up node and the signal output terminal according to the voltage of the pull-down node; and
a control circuit, configured to provide the first input signal to the pull-up node according to the first control signal and the first clock signal;
wherein the pull-down control circuit comprises a first transistor, a second transistor, a third transistor, and a first capacitor;
wherein a control electrode and a second electrode of the first transistor are coupled to the first clock signal input terminal, and a first electrode of the first transistor is coupled to the pull-down node;
wherein a control electrode of the second transistor is coupled to the pull-up node, a first electrode of the second transistor is coupled to the first voltage terminal, and a second electrode of the second transistor is coupled to the pull-down node;
wherein a control electrode of the third transistor is coupled to the signal output terminal, a first electrode of the third transistor is coupled to the first voltage terminal, and a second electrode of the third transistor is coupled to the pull-down node; and
wherein the first capacitor is coupled between the pull-down node and the first voltage terminal.

US Pat. No. 10,923,205

MEMORY DEVICES COMPRISING MAGNETIC TRACKS INDIVIDUALLY COMPRISING A PLURALITY OF MAGNETIC DOMAINS HAVING DOMAIN WALLS AND METHODS OF FORMING A MEMORY DEVICE COMPRISING MAGNETIC TRACKS INDIVIDUALLY COMPRISING A PLURALITY OF MAGNETIC DOMAINS HAVING DOMAIN W

Micron Technology, Inc., ...

1. A method of forming a memory device comprising magnetic tracks individually comprising a plurality of magnetic domains having domain walls, comprising:forming an elevationally outermost substrate material of uniform chemical composition that has multiple physical differences therein, the multiple physical differences being characterized by one of (a) and (b), where,
(a): amorphous regions and crystalline regions;
(b): crystalline regions of different lattice configurations;
etching only partially elevationally into the material of uniform chemical composition having multiple physical differences therein to form the material of uniform chemical composition having multiple physical differences therein to have alternating regions of elevational depressions and elevational protrusions in a finished construction of the memory device; and
forming a plurality of magnetic tracks over and which angle relative to the alternating regions, interfaces of immediately adjacent of the alternating regions individually comprising a domain wall pinning site in individual of the magnetic tracks.

US Pat. No. 10,923,204

FULLY TESTIBLE OTP MEMORY

Attopsemi Technology Co.,...

1. An OTP memory, comprising:a plurality of OTP cells, at least one of the OTP cells including at least:
an OTP element including at least one electrical fuse as an OTP element having a first terminal coupled to a first supply voltage line, the at least one OTP element having a resistance; and
a selector coupled to the OTP element with at least one enable signal coupled to a second and/or a third supply voltage line;
at least one read circuit to convert the resistance of the OTP element into a logic state; and
test methods to apply low voltages or currents to the first, the second, and/or the third supply voltage lines during testing of the OTP element so as not to program the OTP element into a different logic state but to alter the read data output.

US Pat. No. 10,923,203

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a one-time programmable (OTP) memory comprising a key program area and a plurality of key protection setting areas,
wherein a key is stored in the key program area, and a plurality of setting values that protect the key stored in the key program area are programmed in the key protection setting areas;
a key register configured to load the key stored in the OTP memory, wherein the key is accessible to secure software when the key is loaded into the key register; and
a key protection control logic circuit configured to load the key stored in the OTP memory into the key register based on the setting values programmed in the key protection setting areas of the OTP memory.

US Pat. No. 10,923,202

HOST-RESIDENT TRANSLATION LAYER TRIGGERED HOST REFRESH

Micron Technology, Inc., ...

1. A method comprising:receiving a memory operation request from a host at a non-volatile memory, the memory operation request including a logical block address (LBA) associated with the host and a physical address associated with the non-volatile memory;
determining a correct physical address associated with the LBA using an address mapping stored on the non-volatile memory;
comparing the correct physical address with the physical address received from the host;
when the correct physical address is different than the physical address received from the host, incrementing a first counter at the non-volatile memory;
comparing the first counter to a threshold value; and
when the first counter is at or over the threshold value, providing a refreshed address mapping table to the host.

US Pat. No. 10,923,201

MEMORY DEVICE AND METHOD OF OPERATING THE MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A memory device comprising:a memory block including a plurality of select transistors, a plurality of normal memory cells and a plurality of dummy memory cells disposed between the plurality of select transistors and the plurality of normal memory cells;
a peripheral circuit configured to perform an erase operation and a soft program operation on the memory block; and
control logic configured to control the peripheral circuit to control the erase operation and the soft program operation, wherein during the soft program operation, threshold voltages of first dummy memory cells adjacent to the plurality of select transistors among the plurality of dummy memory cells are controlled to be higher than threshold voltages of second dummy memory cells adjacent to the plurality of normal memory cells among the plurality of dummy memory cells.

US Pat. No. 10,923,200

APPARATUS AND METHODS FOR DETERMINING READ VOLTAGES FOR A READ OPERATION

Micron Technology, Inc., ...

1. A method of operating a memory, comprising:applying an intermediate read voltage to a selected access line for a read operation;
adding noise to a sensing operation while applying the intermediate read voltage;
determining a value indicative of a number of memory cells of a plurality of memory cells connected to the selected access line that are activated in response to applying the intermediate read voltage to the selected access line during the sensing operation; and
determining a plurality of read voltages for the read operation in response to the value indicative of the number of memory cells of the plurality of memory cells that are activated in response to applying the intermediate read voltage to the selected access line.

US Pat. No. 10,923,199

PEAK CURRENT MANAGEMENT IN A MEMORY ARRAY

Micron Technology, Inc., ...

1. An electronic device comprising:a multi-chip package including multiple memory dice that, each include:
a memory array;
charging circuitry configured to perform one or more memory events in a high current, mode using a high current level or in a low current mode using a lower current level;
polling circuitry configured to poll a power status node common to the multiple memory dice to determine availability of the high current mode; and
a control unit configured to:
operate the charging circuitry in the low current mode to perform the one or more memory events when the polling circuitry detects that the common power status node indicates that the high current mode is unavailable and in use by another memory die; and
operate the charging circuitry in the high current mode to perform the same one or more memory events when the polling circuitry detects that the common power status node indicates that the high current mode is released by the other memory die and is available.

US Pat. No. 10,923,198

MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

SK hynix Inc., Gyeonggi-...

1. A memory device comprising:a memory cell array including memory cells;
a voltage generating circuit configured to generate operating voltages during a program operation;
a row decoder configured to transmit the operating voltages to the memory cells array during the program operation;
a page buffer group configured to receive, during the program operation, a plurality of data and control bit lines of the memory cell array;
a logic group configured to generate and output driver control signals based on data received from an external device; and
an internal power supply circuit configured to control current corresponding to an internal power supply voltage in response to the driver control signals,
wherein the internal power supply circuit increases the current corresponding to the internal power supply voltage as the number of first data in the received data increases, and
wherein the voltage generating circuit, the row decoder, the page buffer group and the logic group operate using the internal power supply voltage.

US Pat. No. 10,923,197

MEMORY DEVICE WITH COMPENSATION FOR ERASE SPEED VARIATIONS DUE TO BLOCKING OXIDE LAYER THINNING

SanDisk Technologies LLC,...

1. An apparatus, comprising:a control circuit configured to connect to a plurality of memory cells, the plurality of memory cells are arranged in NAND strings in a plurality of sub-blocks of a block, the plurality of sub-blocks comprise a central sub-block and an edge sub-block, each NAND string comprises a channel, and the control circuit is configured to:
in an erase operation for the block, charge up channels of NAND strings in the central sub-block to a higher voltage than a voltage to which channels of NAND strings in the edge sub-block are charged up.

US Pat. No. 10,923,196

ERASE OPERATION IN 3D NAND

SanDisk Technologies LLC,...

1. An apparatus comprising:NAND strings comprising non-volatile memory cells;
a voltage source configured to output an erase voltage;
a voltage regulator coupled to the voltage source, the voltage regulator configured to regulate the voltage source based on a comparison of a reference voltage and a voltage based on the erase voltage; and
a control circuit in communication with the NAND strings, the voltage source and the voltage regulator, the control circuit configured to:
provide the erase voltage to the NAND strings;
sense a current provided by the voltage source in response to the erase voltage provided to the NAND strings; and
modulate the reference voltage based on the current from the voltage source.

US Pat. No. 10,923,195

NONVOLATILE MEMORY DEVICE, AN OPERATING METHOD THEREOF, AND A STORAGE SYSTEM INCLUDING THE NONVOLATILE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method comprising:programming an erase control transistor of the plurality of cell transistors; and
after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor,
wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and
wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

US Pat. No. 10,923,194

METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE

Conversant Intellectual P...

1. A flash memory device comprising:a plurality of flash memory cells, each flash memory cell comprising a single transistor, said single transistor being a floating gate transistor;
a plurality of main word lines, each main word line of the plurality of main word lines coupled to a corresponding group of local word lines, each local word line coupled to gate terminals of its corresponding floating gate transistors of the plurality of flash memory cells;
a voltage circuit configured to provide a positive well bias voltage, a negative word line voltage, and a positive word line voltage, the voltage circuit coupled to a p-well to apply the positive well bias voltage to the plurality of flash memory cells for an erase operation; and
driver circuit configured to:
pass the negative word line voltage on a selected main word line of the plurality of main word lines to its corresponding group of selected local word lines for the erase operation, the corresponding group of selected local word lines being coupled to gate terminals of corresponding group of selected flash memory cells to be erased, the difference between the positive well bias voltage and the negative word line voltage being sufficient to erase flash memory cells; and
pass the positive word line voltage on unselected main word lines of the plurality of main word lines to their corresponding groups of unselected local word lines, the corresponding group of unselected local word lines being coupled to gate terminals of corresponding groups of unselected flash memory cells, the difference between the positive well bias voltage and the positive word line voltage being insufficient to erase flash memory cells.

US Pat. No. 10,923,193

MEMORY DEVICE INCLUDING VOLTAGE GENERATING CIRCUIT

SK hynix Inc., Gyeonggi-...

1. A memory device, comprising:a memory block including a channel layer formed between junctions included in a well, and a source select line, word lines, and drain select lines that are sequentially stacked on the well while enclosing the channel layer;
a first voltage source configured to generate a first operating voltage to be applied to the well during a program operation or an erase operation; and
a second voltage source configured to generate a second operating voltage to be applied to source lines that are coupled to the junctions during the program operation or the erase operation.

US Pat. No. 10,923,192

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A memory system comprising:a memory device including a plurality of memory blocks each having a plurality of pages; and
a controller suitable for controlling the memory device to perform program operations in the pages,
wherein the memory device checks program voltage distributions of the programmed pages, checks fail bits in the programmed pages, and confirms a partial program success according to the checked fail bits numbers, and
wherein the controller receives a status signal indicating the partial program success from the memory device, confirms the partial program success of the programmed pages in the program operations in correspondence to the status signal, and performs a copy operation for first data stored in the programmed pages corresponding to the partial program success, in the memory blocks.

US Pat. No. 10,923,191

3D SRAM/ROM WITH SEVERAL SUPERIMPOSED LAYERS AND RECONFIGURABLE BY TRANSISTOR REAR BIASING

1. A microelectronic device provided with several superimposed layers of components and comprising:a lower level provided with one or several components formed in at least one first semiconductive layer,
an upper layer comprising transistors having respective channel regions formed in at least one second semiconductor layer arranged above the first semiconductive layer,
a set of memory cells each provided with a first inverter and a second inverter cross-connected, the first inverter and the second inverter being connected to, and arranged between, a supply line and a ground line,
the first inverter and the second inverter respectively comprising at least one first transistor of a first type, N or P, and at least one second transistor of the first type N or P, belonging to said upper layer, each of said first and second transistors having a lower electrode located between the second semiconductor layer and the first semiconductive layer and coupled by capacitive coupling with a channel region located in the second semiconductor layer,
said memory cells of said set of memory cells being further connected to:
a first biasing line of one among the lower electrode of the first transistor and the lower electrode of the second transistor,
a second biasing line of the other among the lower electrode of the at least one first transistor and the lower electrode of the at least one second transistor,
wherein said set of memory cells belong to a row of cells, said row of cells comprising a first cell connected to said first biasing line and to said second biasing line by means of a first pair of vias, a second cell of said row of cells being connected to said first biasing line and to said second biasing line by means of a second pair of vias,
the device further comprising a circuit configured to, during an initialisation sequence:
during a first phase, apply a first potential and a second potential different from the first potential, respectively on said first biasing line and said second biasing line, and apply a voltage between said supply line and the ground line, in such a way as to impose on each cell of said set of memory cells a logical data having a value depending on the first and second biasing lines to which the lower electrode of a first transistor of the respective cell and the lower electrode of a second transistor of the respective cell are respectively connected,
then
during a second phase, apply the same potential on the first biasing line and the second biasing line, and maintain a voltage between said supply line and the ground line, in such a way as to retain the logical data and render the cells of said set of memory cells available for read and write access.

US Pat. No. 10,923,190

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a first interconnect;
a second interconnect;
a memory cell electrically coupled between the first interconnect and the second interconnect and including a memory element;
a first circuit provided in a first power source domain having a range of a first voltage to a second voltage, the second voltage higher than the first voltage, the first circuit controlling a start and a stop of supply of the second voltage to the first interconnect;
a second circuit provided in a second power source domain having a range of a third voltage to the first voltage, the third voltage lower than the first voltage, the second circuit controlling a start and a stop of supply of the third voltage to the second interconnect; and
a third circuit provided in a third power source domain having a range of a fourth voltage to a fifth voltage, the fourth voltage lower than the first voltage and higher than the third voltage, the fifth voltage lower than the second voltage and higher than the first voltage, the third circuit controlling a start and a stop of supply of a sixth voltage to the first and second interconnects, the six voltage between the fourth voltage and the fifth voltage.

US Pat. No. 10,923,189

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a memory cell including a resistance change memory element in which a low resistance state or a high resistance state can be set according to a voltage decreasing speed of a write voltage signal to be applied across both terminals of the resistance change memory element, and a selector element connected in series to the resistance change memory element;
a word line to which a signal for selecting the memory cell is supplied;
a bit line connected to one end of the memory cell;
an operational amplifier including a non-inverting input terminal connected to the bit line, an inverting input terminal, and an output terminal;
an output circuit including a first terminal connected to the output terminal of the operational amplifier, a second terminal connected to the bit line, and a third terminal to which a predetermined potential is applied; and
a charge/discharge circuit which includes a capacitor, a charge circuit section charging the capacitor, and a discharge circuit section discharging the capacitor, and in which one end of the charge circuit section, one end of the discharge circuit section, and one end of the capacitor are connected to the inverting input terminal of the operational amplifier, wherein
at least at the time of decreasing of the write voltage signal for the memory cell, a potential of the other end of the memory cell is set higher than a potential of the other end of the discharge circuit section and a potential of the other end of the capacitor.

US Pat. No. 10,923,188

MACRO STORAGE CELL COMPOSED OF MULTIPLE STORAGE DEVICES EACH CAPABLE OF STORING MORE THAN TWO STATES

Intel Corporation, Santa...

1. An apparatus, comprising:a macro storage cell comprising a first storage device and a second storage device, the first and second storage devices each able to store more than two states, the macro storage cell to store multiple values resulting from a combination of the respectively stored states of the first and second storage devices, wherein, the first storage device is to store N different states and the second storage device is to store M different states, the first and second storage devices coupled in series with a switch residing between the first and second storage devices, the switch being open during a write so that the first and second storage devices are independently written to, the switch being closed during a read so that NM different states are readable from the macro storage cell.

US Pat. No. 10,923,187

STORAGE DEVICE AND CONTROL METHOD FOR CONTROLLING OPERATIONS OF THE STORAGE DEVICE

SONY SEMICONDUCTOR SOLUTI...

1. A storage device, comprising:a first storage section that includes a plurality of first wiring lines, a plurality of second wiring lines, and a plurality of first memory cells, wherein
the plurality of first wiring lines extends in a first direction and includes a plurality of first selection lines and a plurality of second selection lines,
the plurality of second wiring lines extends in a second direction that intersects with the first direction and includes a plurality of third selection lines and a plurality of fourth selection lines, and
each memory cell of the plurality of first memory cells is inserted between a corresponding one of the plurality of first wiring lines and a corresponding one of the plurality of second wiring lines;
a first selection line driver that includes:
a first driver configured to:
apply a first voltage to at least one first selection line of the plurality of first selection lines; and
apply a non-selection voltage to a selection line of the plurality of first selection lines other than the at least one first selection line; and
a second driver configured to:
apply a second voltage to at least one second selection line of the plurality of second selection lines; and
apply the non-selection voltage to a selection line of the plurality of second selection lines other than the at least one second selection line, wherein
the first voltage is one of a first selection voltage or a second selection voltage,
the second voltage is one of the first selection voltage or the second selection voltage, and
the second voltage is different from the first voltage; and
a second selection line driver that includes:
a third driver configured to:
apply a third voltage to at least one third selection line of the plurality of third selection lines; and
apply the non-selection voltage to a selection line of the plurality of third selection lines other than the at least one third selection line; and
a fourth driver configured to:
apply a fourth voltage to at least one fourth selection line of the plurality of fourth selection lines; and
apply the non-selection voltage to a selection line of the plurality of fourth selection lines other than the at least one fourth selection line, wherein
the third voltage is one of the first selection voltage or the second selection voltage,
the fourth voltage is one of the first selection voltage or the second selection voltage, and
the fourth voltage is different from the third voltage.

US Pat. No. 10,923,186

SEMICONDUCTOR MEMORY DEVICE TO HOLD 5-BITS OF DATA PER MEMORY CELL

Toshiba Memory Corporatio...

1. A semiconductor memory device comprisinga memory cell configured to hold 5-bit data according to a threshold;
a word line coupled to the memory cell; and
a row decoder configured to apply first to 31st voltages to the word line,
wherein a first bit of the 5-bit data is established by reading operations using first to sixth voltages,
a second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages, the second bit being different from the first bit,
a third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages, the third bit being different from the first and second bits,
a fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages, the fourth bit being different from the first to third bits, and
a fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages, the fifth bit being different from the first to fourth bits, and
wherein the first to 31st voltages are different voltages,
the row decoder applies the first to 31st voltages to the word line in ascending order, and
a reading operation using a 21st-applied voltage first establishes one of the first to fifth bits.

US Pat. No. 10,923,185

SRAM WITH BURST MODE OPERATION

Qualcomm Incorporated, S...

1. A memory, comprising:a first column including a first bitcell coupled to a first pair of bit lines and including a first sense amplifier configured to sense a first bit from the first bitcell through a first pair of sense nodes to output the first bit at a first output terminal for the first column;
a bit line pre-charge circuit configured to pre-charge the first pair of bit lines to a power supply voltage;
a second column including a second sense amplifier configured to sense a second bit from a second bitcell through a second pair of sense nodes and to output the second bit at a second output terminal for the second column;
a data output latch;
a column multiplexer configured to select between the first bit from the first output terminal and the second bit from the second output terminal to provide a selected bit to the data output latch; and
a sense node pre-charge circuit configured to discharge the first pair of sense nodes and the second pair of sense nodes in a normal read operation and to not discharge the first pair of sense nodes and the second pair of sense nodes in a burst-mode read operation.

US Pat. No. 10,923,184

DUAL RAIL SRAM DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A static random access memory (SRAM) device, comprising:a voltage input terminal configured to receive a first signal at a first voltage level;
a level shifter connected to the voltage input terminal to receive the first signal and an output terminal configured to output a second signal at a second voltage level higher than the first voltage level;
a memory cell including a word line and first and second bit lines, the word line connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level;
a bit line precharge circuit having a control terminal configured to receive the first signal at the first voltage level to selectively precharge the first and second bit lines to the first voltage level in response to the first signal;
a bit line select circuit connected to the first and second bit lines and having a control terminal configured to receive the first signal at the first voltage level and output a bit line read signal at the first voltage level, wherein the bit line read signal is based on a clock signal and a column address signal;
first and second common bit lines connected to an output of the bit line select circuit, wherein the bit line select circuit is configured to selectively connect the first and second bit lines to the respective first and second common bit lines in response to the first signal;
a sense amplifier having a data input connected to the first and second common bit lines and configured to provide an output of the memory cell to a global bit line, the sense amplifier having a sense amplifier control input connected to the output terminal of the level shifter to selectively receive a sense amplifier enable signal at the second voltage level;
a sense amplifier precharge circuit connected to the first and second common bit lines and configured to precharge the first and second common bit lines to the second voltage level such that a discharge rate of the first and second common bit lines is higher than a discharge rate of the first and second bit lines; and
a circuit having a first input connected to the first common bit line and a second input connected to the second common bit line, wherein the circuit is configured to output the output of the memory cell into a latch connected to the global bit line.

US Pat. No. 10,923,183

MEMORY DEVICE COMPRISING ELECTRICALLY FLOATING BODY TRANSISTOR

Zeno Semiconductor, Inc.,...

1. A semiconductor memory instance comprising:an array of semiconductor memory cells, the array comprising at least two memory sub-arrays, each memory sub-array comprising:
a plurality of said semiconductor memory cells arranged in at least one column and at least one row, wherein at least two of said semiconductor memory cells each include:
a first bipolar device having a first floating base region, a first collector, and a first emitter; and
a second bipolar device having a second floating base region, a second collector, and a second emitter;
wherein said first floating base region is common to said second floating base region;
wherein said first collector is common to said second collector;
wherein said first and second collectors are commonly connected to at least two of said memory cells in one of said memory sub-arrays;
a first decoder circuit to select at least one of said at least one column or at least one of said at least one row; and
a second decoder circuit to select at least one of said memory sub-arrays.

US Pat. No. 10,923,182

FIXED-LEVEL CHARGE SHARING TYPE LCV FOR MEMORY COMPILER

TAIWAN SEMICONDUCTOR MANU...

1. A memory device, comprising:an array of memory cells;
a bit line connected to the memory cells;
a power supply voltage input terminal configured to receive a power supply voltage at a first voltage level to operate the memory cells at the first voltage level;
a bit line precharge circuit having an input terminal configured to receive the power supply voltage at the first voltage level, wherein the bit line precharge circuit is configured to select a second voltage level lower than the first voltage level and precharge the bit line to the second voltage level, the bit line precharge circuit including:
a first power header having a first switch and configured to selectively connect the plurality of bit lines directly to the power supply voltage terminal; and
a second power header having a trim device and a second switch and configured to selectively connect the plurality of bit lines to the power supply voltage terminal via the trim device; and
a precharge controller configured to actuate the first switch to selectively connect the plurality of bit lines directly to the power supply voltage terminal for a first predetermined time period, and to actuate the second switch to selectively connect the plurality of bit lines to the power supply voltage terminal via the trim device for a second predetermined time period that is shorter than the first predetermined time period.

US Pat. No. 10,923,181

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM HAVING THE SAME

Samsung Electronics Co., ...

1. A semiconductor memory device comprising:a data strobe signal input buffer configured to receive a data strobe signal and generate an input data strobe signal;
a data input buffer configured to receive data, which is delayed by a first delay time from a first latching edge of the data strobe signal, and generate input data;
a latency control signal generator configured to generate a first on-die termination control signal, which is activated during a first period in which the data strobe signal is applied, in response to receiving a write command;
a first on-die termination control circuit configured to vary a first variable resistance code in response to the first on-die termination control signal;
a data strobe signal termination circuit configured to terminate the data strobe signal, the data strobe signal termination circuit including a first on-die termination resistor, the first on-die termination resistor configured to vary a resistance value thereof in response to the first variable resistance code;
a row decoder configured to decode a row address signal and generate a plurality of word line selection signals;
a column decoder configured to decode a column address signal and generate a plurality of column selection signals; and
a memory cell array including a plurality of memory cells and configured to write the input data to the memory cells selected by the plurality of word line selection signals and the plurality of column selection signals.

US Pat. No. 10,923,180

SENSING TECHNIQUES USING A CHARGE TRANSFER DEVICE

Micron Technology, Inc., ...

1. A method, comprising:transferring, using a first transistor, a charge between a digit line and a node coupled with a first sense component and a second sense component based at least in part on a first voltage on the digit line being less than a second voltage on a gate of the first transistor;
sensing, by the first sense component, a signal on the node at a first time based at least in part on transferring the charge between the digit line and the node and activating a second transistor coupled between the node and the first sense component;
sensing, by the second sense component, the signal on the node at a second time different than the first time based at least in part on transferring the charge between the digit line and the node and activating a third transistor coupled between the node and the second sense component; and
determining a logic state of a multi-level memory cell based at least in part on sensing the signal by the first sense component and sensing the signal by the second sense component.

US Pat. No. 10,923,179

MEMORY DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A memory device comprising:a page including a plurality of memory cells;
a peripheral circuit configured to perform at least one program loop, wherein the at least one program loop includes:
a program voltage applying phase for applying, during a program operation, a program voltage to a word line to which the plurality of memory cells are coupled; and
a program verify phase for determining whether a selected memory cell among the plurality of memory cells has been completely programmed; and
control logic configured to control the peripheral circuit to:
perform, during the program verify phase, an auxiliary verify operation of applying an auxiliary verify voltage to the word line;
perform, during the program verify phase, a main verify operation of applying a main verify voltage larger than the auxiliary verify voltage to the word line; and
determine whether to interrupt the program operation, based on verify data obtained by performing the auxiliary verify operation and the main verify operation.

US Pat. No. 10,923,178

DATA STORAGE WITH IMPROVED WRITE PERFORMANCE FOR PREFERRED USER DATA

WESTERN DIGITAL TECHNOLOG...

1. A data storage device, comprising:a memory device; and
a controller coupled to the memory device, the controller configured to:
receive user write performance preference data for two or more logical block addresses (LBAs) to be written;
receive a first write command for a first LBA of the two or more LBAs;
receive a second write command for a second LBA of the two or more LBAs, wherein a flash translation layer (FLT) maps LBAs to word lines;
determine whether current word line of the memory device is a word line that needs enhanced post write read (EPWR); and
write the second LBA to the current word line, wherein the first LBA remains in a buffer while the second LBA is written.

US Pat. No. 10,923,177

DELAY-LOCKED LOOP, MEMORY DEVICE, AND METHOD FOR OPERATING DELAY-LOCKED LOOP

NANYA TECHNOLOGY CORPORAT...

1. A delay-locked loop circuit, comprising:a delay line, including a plurality of delay units, for delaying an input signal to generate a first delay signal; and
a control unit receiving the input signal, an access start signal and an access end signal, the control unit configured for generating a control signal according to the input signal, the access start signal and the access end signal, wherein the control signal functions to control the delay line to generate the first delay signal during a time interval between two read operations.

US Pat. No. 10,923,176

SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEVICES CONFIGURED FOR STACKED ARRANGEMENTS

III HOLDINGS 2, LLC, Wil...

1. A semiconductor device, comprising:a memory device from a plurality of memory devices aligned in a vertical stack;
a latency determiner configured to determine a signal latency; and
a latency adjustor configured to adjust the signal latency based on a programmed latency and based on a position of the memory device within the vertical stack, using a data strobe on a common vertical connection.

US Pat. No. 10,923,175

MEMORY DEVICE ADJUSTING DUTY CYCLE AND MEMORY SYSTEM HAVING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation;
a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock; and
a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock,
wherein the memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

US Pat. No. 10,923,174

ELECTRONIC DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A reference voltage generating circuit comprising:a first driving unit coupled between a power voltage and a first node;
a second driving unit coupled between a second node and a ground voltage;
a voltage generating unit coupled in series between the first node and the second node and configured to output a plurality of reference voltages; and
an operation setting unit configured to set a control signal input to the first driving unit and the second driving unit according to an operation mode,
wherein the operation mode is determined based on a target voltage level range corresponding to the plurality of reference voltages, among a plurality of voltage level ranges defined under a first protocol condition and a second protocol condition.

US Pat. No. 10,923,173

VOLTAGE GENERATING CIRCUIT, SEMICONDUCTOR MEMORY DEVICE, AND VOLTAGE GENERATING METHOD

LAPIS Semiconductor Co., ...

1. A voltage generating circuit for generating a DC voltage at an output node, comprising:an oscillation signal generating part generating a first clock signal and a second clock signal having different phases from each other, and the first clock signal and the second clock signal alternately repeat a state of a first voltage and a state of a second voltage;
a capacitor having one end receiving the first clock signal and an other end connected to the output node;
a switch element receiving a control voltage and set to an on state or an off state according to the control voltage, and applying the first voltage to the output node when set to the on state; and
a switch control part receiving the second clock signal, and setting the switch element to the on state by supplying the second voltage as the control voltage to the switch element when the first clock signal is in the state of the second voltage, and setting the switch element to the off state by supplying a voltage of the output node as the control voltage to the switch element when the first clock signal is in the state of the first voltage.

US Pat. No. 10,923,172

APPARATUSES AND METHODS FOR MULTI-BANK REFRESH TIMING

Micron Technology, Inc., ...

1. An apparatus comprising:a refresh timer circuit configured to provide a refresh signal, wherein the refresh timer circuit is further configured to:
responsive to a refresh command, set the refresh signal to an active state;
responsive to a counter circuit outputting a count equal to a row active signal time, set the refresh signal to an inactive state;
responsive to the counter circuit outputting a count equal to a row precharge time, increment a pump counter; and
responsive to a pump count based on the pump counter not being met, set the refresh signal to the active state and reset the counter circuit.

US Pat. No. 10,923,171

SEMICONDUCTOR DEVICE PERFORMING REFRESH OPERATION IN DEEP SLEEP MODE

Micron Technology, Inc., ...

1. An apparatus comprising:a memory cell array including a plurality of memory cells;
a first counter circuit configured to periodically update a count value during a first operation mode;
a burst clock generator configured to successively generate a burst pulse predetermined times when the count value indicates a predetermined value; and
a row address control circuit configured to perform a refresh operation on the memory cell array in response to the burst pulse; and
an oscillator circuit configured to periodically activate an oscillator pulse,
wherein the first counter circuit is configured to update the count value in response to the oscillator pulse during the first operation mode, and
wherein the row address control circuit is configured to perform the refresh operation on the memory cell array in response to the oscillator pulse during a second operation mode.

US Pat. No. 10,923,170

DETERMINING BIAS CONFIGURATION FOR WRITE OPERATIONS IN MEMORY TO IMPROVE DEVICE PERFORMANCE DURING NORMAL OPERATION AS WELL AS TO IMPROVE THE EFFECTIVENESS OF TESTING ROUTINES

Everspin Technologies, In...

1. A method for configuring write parameters used during write operations for a spin torque memory device that includes a plurality of memory cells, the method comprising:performing a first series of write operations for memory cells included on the spin torque memory device, wherein a timing parameter associated with a current pulse width of a spin-polarized current through each memory cell is varied during performance of the first series of write operations;
determining a first selected parameter setting for the current pulse width of the spin-polarized current for write operations based on the first series of write operations, wherein determining the first selected parameter setting includes detecting whether or not each write operation in the first series of write operations was successful and identifying at least one of a speed, an error rate, and a power consumption for the first series of write operations;
storing the first selected parameter setting in a register on the spin torque memory device;
performing a second series of write operations for the memory cells included on the spin torque memory device, wherein performing the second series of write operations comprises varying at least one of a bias voltage and a bias current through each memory cell during performance of a series of up-current write operations;
determining a second selected parameter setting for the at least one of a bias voltage and a bias current for write operations based on the second series of write operations, wherein determining the second selected parameter setting includes detecting whether or not each write operation in the second series of write operations was successful; and
storing the second selected parameter setting in the register on the spin torque memory device such that the second selected parameter setting stored in the register corresponds to at least one of an up-current bias voltage and an up-current bias current to be applied during up-current write operations.

US Pat. No. 10,923,169

MAGNETIC RECORDING ARRAY AND MAGNETIC RECORDING DEVICE

TDK CORPORATION, Tokyo (...

1. A magnetic recording array comprising:a plurality of domain wall moving elements;
a first wiring which is electrically connected to a reference potential and is electrically connected to at least one domain wall moving element of the plurality of domain wall moving elements;
a second wiring which is electrically connected to at least two or more domain wall moving elements of the plurality of domain wall moving elements;
a first switching element which is connected between each of the domain wall moving elements and the first wiring; and
a second switching element which is connected between each of the domain wall moving elements and the second wiring,
wherein each of the domain wall moving elements includes a magnetic recording layer which is electrically connected to the first wiring and the second wiring and includes a magnetic domain wall, a first ferromagnetic layer, and a non-magnetic layer which is located between the first ferromagnetic layer and the magnetic recording layer,
wherein an OFF resistance of the first switching element is smaller than an OFF resistance of the second switching element, and
wherein a resistance area product (RA) of the domain wall moving element is 1×104 ??m2 or more.

US Pat. No. 10,923,168

METHOD OF MAKING MAGNETIC TUNNEL JUNCTION MEMORY DEVICE WITH STRESS INDUCING LAYERS

SK hynix Inc., Icheon-si...

1. A method for fabricating an electronic device comprising:forming a first portion of a variable resistance element over a substrate, the first portion including a free layer having a variable magnetization direction and a tunnel barrier layer disposed over the free layer;
forming a first protective layer on a sidewall of the free layer and a sidewall of the tunnel barrier layer by performing a first passivation process, the first protective layer arranged along a direction perpendicular to a surface of the free layer;
forming a second portion of the variable resistance element over the first portion, the second portion including a pinned layer having a fixed magnetization direction; and
forming a second protective layer on a sidewall of the pinned layer by performing a second passivation process, the second protective layer arranged along the direction,
wherein any one layer of the first protective layer and the second protective layer applies a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element,
wherein each of the first protective layer and the second protective layer includes a passivation layer including an oxide, or hydrogen, or a combination of the oxide and the hydrogen.

US Pat. No. 10,923,167

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:an address latch circuit configured to latch an address based on an input control signal generated according to a column control pulse and configured to output the latched address as a pre-column address based on an output control signal generated according to an internal column control pulse; and
a column address generation circuit configured to generate a column address from the pre-column address based on a delayed column control pulse generated by delaying the column control pulse and a delayed internal column control pulse generated by delaying the internal column control pulse.

US Pat. No. 10,923,166

SEMICONDUCTOR DEVICES PERFORMING A WRITE LEVELING TRAINING OPERATION AND SEMICONDUCTOR SYSTEMS INCLUDING THE SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A method of performing a write leveling training operation, the method comprising:performing an external write leveling training operation to generate a feedback signal based on a data strobe signal and an internal write leveling pulse and to control a write latency delay of the data strobe signal based on the feedback signal; and
performing an internal write leveling training operation to generate the feedback signal based on the data strobe signal and the internal write leveling pulse, which is generated by the write latency delay and a phase alignment, to control the phase alignment based on the feedback signal, and to control the write latency delay of the data strobe signal based on the feedback signal.

US Pat. No. 10,923,165

STACKED MEMORY DEVICE, A SYSTEM INCLUDING THE SAME AND AN ASSOCIATED METHOD

SAMSUNG ELECTRONICS CO., ...

1. A method of operating a stacked memory device, the stacked memory device including calculation units in each of a plurality of calculation semiconductor dies stacked in a vertical direction, the method comprising:providing broadcast data, in common, to each of the calculation units through through-silicon vias electrically connecting the calculation semiconductor dies;
providing internal data respectively read from memory integrated circuits of the calculation semiconductor dies to each of calculation units; and
performing a plurality of calculations based on the broadcast data and the internal data simultaneously using the calculation units.

US Pat. No. 10,923,164

DUAL POWER I/O TRANSMITTER

Intel Corporation, Santa...

1. An apparatus comprising:a first power supply rail to provide a first power supply;
second and third power supply rails to provide second and third power supplies, respectively, wherein a voltage level of the first power supply is higher than a voltage level of each of the second and third power supplies, and wherein the voltage level of the first power supply, the voltage level of the second power supply, and the voltage level of the third power supply is greater than zero;
a first driver circuitry coupled to the first power supply rail and the second power supply rail;
a second driver circuitry coupled to the third power supply rail, and coupled to the first driver circuitry; and
a stack of transistors of N conductivity type coupled to the first power supply rail, and to the second driver circuitry.

US Pat. No. 10,923,163

SEQUENTIAL MEMORY OPERATION WITHOUT DEACTIVATING ACCESS LINE SIGNALS

Micron Technology, Inc., ...

1. A memory apparatus comprising:data lines;
an access line;
a first group of memory cells coupled to the access line, each of the data lines coupled to a respective memory cell in the first group of memory cells;
a second group of memory cells coupled to the access line, each of the data lines coupled to a respective memory cell in the second group of memory cells; and
a memory controller operable to apply a signal to the access line during a memory operation of obtaining information from the first group of memory cells and obtaining information from the second memory cells, and to abstain from precharging the data lines during a time interval between obtaining the information from the first group of memory cells and obtaining information from the second memory cells.

US Pat. No. 10,923,162

MEMORY DEVICES

Samsung Electronics Co., ...

1. A memory device comprising:a first word line on a substrate at a first level, the first word line extending in a first direction parallel to a top surface of the substrate, the first word line having a first length in the first direction;
a second word line on the substrate at a second level higher than the first level, the second word line extending in the first direction, the second word line being shifted from the first word line in the first direction by about ½ of the first length;
a third word line on the substrate at a third level higher than the second level, the third word line extending in the first direction, the third word line vertically overlapping the second word line;
a fourth word line on the substrate at a fourth level higher than the third level, the fourth word line extending in the first direction, the fourth word line vertically overlapping the first word line; and
a plurality of memory cells, each of the plurality of memory cells being disposed on the first through fourth word lines.

US Pat. No. 10,923,161

BITCELL WORDLINE STRAPPING CIRCUITRY

Arm Limited, Cambridge (...

1. An integrated circuit, comprising:a bitcell;
a first strap that couples the bitcell to ground;
a second strap that couples the bitcell to a bitline with a second via; and
a third strap that couples the bitcell to a wordline within a boundary of the bitcell,
wherein the third strap couples the bitcell to the wordline with a third via, wherein the second and third vias are different, wherein the second and third vias are positioned within the boundary of the bitcell.

US Pat. No. 10,923,160

TESTING ASSEMBLY FOR SEALED HARD DISK DRIVES

Seagate Technology LLC, ...

1. A hard disk drive comprising:a base deck;
a cover coupled to the base deck to create an internal cavity; and
a testing assembly coupled to the cover and arranged to expose an organic material to the internal cavity, the testing assembly including a housing that comprises aluminum, is partially positioned outside the internal cavity, and partially extends into the internal cavity.

US Pat. No. 10,923,159

EVENT DETECTION THROUGH VARIABLE BITRATE OF A VIDEO

Alarm.com Incorporated, ...

1. A computer-implemented method comprising:receiving, at a server and from a video recorder at a property, bitrate information that describes bitrates for portions of a video without the server receiving the video;
determining bitrate criteria that corresponds to a likely occurrence of an event being shown in the video;
determining that the bitrate indicated by the bitrate information for a particular portion of the video satisfies the bitrate criteria;
in response to determining that the bitrate indicated by the bitrate information for the particular portion of the video satisfies the bitrate criteria, determining that an instance of the event is likely to be shown in the particular portion of the video; and
providing, by the server, a user device an indication that the event is likely to be shown in the particular portion of the video, wherein the user device receives the video from the video recorder based on receipt of the indication from the server.

US Pat. No. 10,923,158

DYNAMIC SEQUENTIAL IMAGE PROCESSING

International Business Ma...

1. A computer-implemented method for sequential image processing comprising:obtaining a first set of parameters corresponding to a first video, the first set of parameters including a first skip number and a first segment length;
obtaining a first set of image feature values corresponding to the first video;
storing the first set of parameters and the first set of image feature values as reference data;
calculating a second set of image feature values corresponding to a second video;
comparing the second set of image feature values to the reference data to generate a first degree of difference;
determining, based on the comparing, that the first degree of difference exceeds a threshold;
calculating, in response to the determining, a variance between the first set of image feature values and the reference data;
generating, based at least in part on the variance, a second set of parameters corresponding to the second video, the second set of parameters including a second skip number and a second segment length; and
assigning the second set of parameters to the second video for performing a video analysis task with the second video.

US Pat. No. 10,923,157

SYSTEM AND METHOD FOR EVENT DATA COLLECTION AND VIDEO ALIGNMENT

ScoreBreak, LLC, Denver,...

1. A method for collecting, processing, and aligning either live or prerecorded digital video data and event data that occur during the course of an event for immediate replay using multiple, decentralized, distributed processing resources the method comprising:receiving and storing digital video data feed and digital video metadata from at least one camera associated with an event in a memory medium in video-based format using a first process or device;
receiving and storing event data and event data metadata associated with the event in a memory medium in linguistic-based format using a second process or device, the event data containing at least one action that occurred in the event;
retrieving the at least one digital video data feed and metadata and event data and metadata associated with the event from the respective memory media in which they are stored;
aligning metadata system times of the two processes or devices used to generate data feeds of an event's at least one digital video data and event data by way of trusted system timestamp alignment or action selection alignment;
determining at least one system time alignment offset value between the processes or devices used for event data recording and digital video data recording;
recording the at least one alignment offset value between the digital video data metadata and event data action metadata, or vice versa, in records of a database stored in a memory, the database including records for containing entries in data fields for at least the system timestamp when the file was created and/or the start of the recording and additional cords for further available metadata, and
providing the digital video and event data to a user in real time for immediate review and analysis.

US Pat. No. 10,923,156

METHOD AND SYSTEM FOR FACILITATING LOW-COST HIGH-THROUGHPUT STORAGE FOR ACCESSING LARGE-SIZE I/O BLOCKS IN A HARD DISK DRIVE

Alibaba Group Holding Lim...

1. A computer-implemented method, comprising:receiving a first request to write data to a hard disk drive (HDD) which comprises a plurality of platters with corresponding heads, wherein a respective platter includes a plurality of tracks;
aligning the heads at a same first position on a first track of each platter;
writing the data to the platters by distributing the data as a plurality of data sectors to track sectors located at the same first position on the first track of each platter;
receiving a second request to read the data from the HDD;
identifying the first track as a location at which the data is stored;
aligning the heads at a same random position on the first track of each platter;
reading, during a single rotation of the platters and beginning from the same random position, all data stored on the first track of each platter;
storing the read data in a data buffer; and
reshuffling the read data in the data buffer to obtain the data requested in the second request.

US Pat. No. 10,923,155

SYNTHESIZING A PRESENTATION FROM MULTIPLE MEDIA CLIPS

Gracenote, Inc., Emeryvi...

1. A method comprising:accessing, by one or more processors of a server computing device, a plurality of media clips including a first video clip and a second video clip;
matching, by the one or more processors, a first fingerprint of at least a part of the first video clip with a second fingerprint of at least a part of the second video clip;
determining, by the one or more processors, a temporal overlap of the first video clip with the second video clip based at least in part on the match of the first fingerprint of at least the part of the first video clip with the second fingerprint of at least the part of the second video clip; and
based on the temporal overlap of the first video clip with the second video clip:
merging, by the one or more processors, the first video clip and the second video clip into a group of temporally-overlapping video clips,
transmitting, by the one or more processors, to a client computing device, data identifying the group of temporally-overlapping video clips and specifying a synchronization of the first video clip with the second video clip, and
generating, by the one or more processors, for display on a display device of the client computing device, a graphical user interface that identifies the group of temporally-overlapping video clips, specifies the synchronization of the first video clip with the second video clip, and allows access to, and manipulation of, the first and second video clips.

US Pat. No. 10,923,154

SYSTEMS AND METHODS FOR DETERMINING HIGHLIGHT SEGMENT SETS

GoPro, Inc., San Mateo, ...

1. A system configured for determining highlight segments, the system comprising: one or more processors configured by machine-readable instructions to:obtain content files that define a content segment set, the content segment set including a first content segment and a second content segment; and
iteratively select multiple content segments from the content segment set for inclusion in a highlight segment set by:
selecting an individual content segment included in the content segment set as a selected content segment for inclusion in the highlight segment set;
determining diversity scores for content segments that are (i) included in the content segment set and (ii) not selected for inclusion in the highlight segment set, the diversity scores indicating similarity between the individual content segments not selected for inclusion in the highlight segment set and the selected content segment; and
disqualifying one or more of the content segments from being selected for inclusion in the highlight segment set in future iterations based on the diversity scores.

US Pat. No. 10,923,153

NON-LINEAR PROGRAM PLANNER, PREPARATION, AND DELIVERY SYSTEM

SCRIPPS NETWORKS INTERACT...

1. A method for program planning, preparation, and delivery of a non-linear video asset, the method comprising:receiving a linear broadcast schedule from a linear schedule service application into a non-linear planning application;
receiving content rights from a content rights application into the non-linear planning application;
receiving a source video asset from a storage device into the non-linear planning application;
generating a partner content avails with the non-linear planning application;
generating a metadata file of the source video asset with the non-linear planning application, wherein the metadata file of the source video asset includes an updated metadata field related to distribution of the source video asset;
adding the source video asset to a playlist created using a planning user interface;
automatically creating a partner avails document based on partner content distribution dates, partner content rights, and the identified source video asset; and
sending the partner avails document to distribution partners.

US Pat. No. 10,923,152

PARTIAL UPDATES FOR SHINGLED MAGNETIC RECORDING DEVICES

Amazon Technologies, Inc....

1. A method, comprising:receiving a command to delete data stored in a shingled magnetic recording (SMR) region of a storage device;
responsive to receiving the command to delete the data, resetting a write pointer for the SMR region;
receiving a command to undo the deletion of the data; and
responsive to receiving the command to undo the deletion of the data, undoing the deletion of the data, wherein undoing the deletion comprises using a partial write pointer update to set the write pointer for the SMR region to a write position after the data stored in the SMR region of the storage device.

US Pat. No. 10,923,151

ILLUMINATION CONTROL DEVICE, ILLUMINATION CONTROL METHOD AND ILLUMINATION CONTROL PROGRAM

ALPHATHETA CORPORATION, ...

1. A lighting controller comprising a device installed with software, the device:obtains music piece information comprising information on a beat position in music piece data;
controls a lighting fixture, based on a lighting control data corresponding to the music piece data to which lighting control information is allocated, with reference to a change point of a lighting effect, whose minimum unit is defined by the beat position;
monitors an operation signal indicating an operation performed on a music piece reproduction apparatus that reproduces the music piece data or a music piece reproduction controller that controls the music piece reproduction apparatus; and
allocates, as the lighting effect, a lighting state of the lighting fixture and a change in the lighting state to at least one operation unit of the music piece reproduction apparatus or the music piece reproduction controller,
wherein, in response to the operation signal the device maintains correspondence between a current reproduction position in the music piece data and a current processing position in the lighting control data, and the device detects an operation content from the operation signal, obtains lighting effect information corresponding to the detected operation content, and changes the control of the lighting fixture.

US Pat. No. 10,923,150

METHOD FOR PRODUCING MAGNETIC RECORDING MEDIUM

FUJI ELECTRIC CO., LTD., ...

1. A method for producing a magnetic recording medium comprising:(1) preparing a substrate;
(2) forming a seed layer comprising (Mg1-xTix)O onto the substrate;
(3) plasma etching the seed layer in an atmosphere comprising inert gas; and
(4) forming a magnetic recording layer comprising an ordered alloy onto the seed layer which has been subjected to the plasma etching in step (3),
wherein x is 0 or more and 0.8 or less,
wherein plasma etching the seed layer in step (3) is performed in an atmosphere comprising the inert gas and oxygen, and
wherein the step (2) is performed before forming any magnetic recording layer, including the magnetic recording layer in the step (4).

US Pat. No. 10,923,149

ALUMINUM ALLOY SUBSTRATE FOR MAGNETIC RECORDING MEDIUM AND METHOD FOR MANUFACTURING THE SAME, SUBSTRATE FOR MAGNETIC RECORDING MEDIUM, MAGNETIC RECORDING MEDIUM, AND HARD DISC DRIVE

SHOWA DENKO K.K., Tokyo ...

1. An aluminum alloy substrate for a magnetic recording medium, havinga metallic structure made of an Al alloy which has a composition including Si in a range of 18.0% by mass to 22.0% by mass, Ni in a range of 5.0% by mass to 8.5% by mass, Cu in a range of 2.5% by mass to 4.0% by mass, and Mg in a range of 0.8% by mass to 1.5% by mass with a remainder being Al,
wherein primary-crystal Si particles which have a maximum diameter of 0.5 ?m or more and an average particle diameter of 2 ?m or less are dispersed in the metallic structure,
a diameter of the substrate is in a range of 53 mm to 97 mm, and a thickness of the substrate is in a range of 0.2 mm to 0.9 mm, and
a value of E/? (E: Young's modulus, ?: density) is 36.0 (GPa)/(gcm?3) or more.

US Pat. No. 10,923,148

MAGNETIC RECORDING MEDIUM

Sony Corporation, Tokyo ...

1. A magnetic recording mediumwhich has a layer structure including a magnetic layer and a base layer, and
of which an average thickness tT is tT?5.6 ?m,
a dimensional change amount ?w in a width direction with respect to a change in tension in a longitudinal direction is 707 ppm/N??w?800 ppm/N,
a servo pattern is recorded on the magnetic layer,
a standard deviation ?PES of a position error signal (PES) value obtained from a servo signal in which the servo pattern is reproduced is 17??PES?23, and
a maximum value ?1M of a friction coefficient ?1 between a surface on a side of the magnetic layer and an LTO3 head in a case where measurement of the friction coefficient ?1 is performed 250 times is 0.04??1M?0.5.

US Pat. No. 10,923,147

MAGNETIC MEDIA DESIGN WITH MULTIPLE NON-MAGNETIC EXCHANGE CONTROL LAYERS

WESTERN DIGITAL TECHNOLOG...

1. A magnetic medium, comprising:a substrate; and
a magnetic recording layer structure on the substrate, the magnetic recording layer structure comprising an alternating pattern of magnetic recording sublayers and non-magnetic exchange control sublayers;
wherein the magnetic recording layer structure comprises at least six of the magnetic recording sublayers and at least six of the non-magnetic exchange control sublayers;
wherein the at least six of the magnetic recording sublayers comprise:
a bottom magnetic recording sublayer that is nearest the substrate;
a top magnetic recording sublayer of the magnetic recording sublayers that is furthest from the substrate; and
at least four middle magnetic recording sublayers positioned between the top and bottom recording sublayers and comprising a first middle magnetic recording sublayer that is furthest among the middle magnetic recording sublayers from the substrate;
wherein the magnetic recording layer structure further comprises a gradient of platinum content across the magnetic recording sublayers such that the bottom magnetic recording sublayer comprises a highest platinum content among the magnetic recording sublayers and the top magnetic recording sublayer comprises a lowest platinum content among the magnetic recording sublayers; and
wherein the first middle magnetic recording sublayer and the top magnetic recording sublayer comprise equal platinum content.

US Pat. No. 10,923,146

DATA STORAGE DEVICE EMPLOYING TRIANGLE-LIKE DITHER TO SPREAD TRACK SQUEEZE

Western Digital Technolog...

1. A data storage device comprising:a disk;
a head actuated over the disk; and
control circuitry configured to:
use the head to read servo information from the disk and generate a position error signal (PES) representing a radially position of the head over the disk;
generate a control signal based on the PES and a triangle-shape dither signal; and
position the head radially over the disk using the control signal,
wherein during an access operation the triangle-shape dither signal causes the head to cross multiple servo tracks on the disk at a substantially constant velocity, thereby spreading out an effect of track squeeze of the servo tracks.

US Pat. No. 10,923,145

MICROWAVE-ASSISTED MAGNETIC RECORDING (MAMR) WRITE HEAD WITH COMPENSATION FOR DC SHUNTING FIELD

WESTERN DIGITAL TECHNOLOG...

1. A magnetic recording write head for magnetizing regions in a magnetic recording layer, the write head comprising:a write pole;
a trailing shield;
a spin torque oscillator (STO) between the write pole and the trailing shield;
an electrically conductive coil coupled to the write pole for generating a magnetic write field between the write pole and the trailing shield;
a ferromagnetic compensation layer for offsetting a shunting field;
a nonmagnetic barrier layer between the compensation layer and the STO; and
a nonmagnetic spacer layer adjacent the compensation layer, the compensation layer being located between the spacer layer and the barrier layer.

US Pat. No. 10,923,144

MAGNETIC DISK DEVICE AND READ PROCESSING METHOD

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk;
a head comprising a write head that writes data to the disk, and a first read head and a second read head that read data from the disk; and
a controller that, in reading a first track of a first region of the disk, positions a middle portion of the first read head and the second read head at a first track center of the first track, and in reading a second track of a second region of the disk different from the first region, positions any one of the first read head and the second read head at a second track center of the second track, wherein
when the middle portion is positioned at the first track center in the first region and read retry is repeatedly performed, the controller positions any one of the first read head and the second read head at the first track center in the first region.

US Pat. No. 10,923,143

MAGNETIC TAPE DEVICE CAPABLE OF DETERMINING THE VERTICAL POSITION OF MAGNETIC HEAD BASED ON PATTERN COMBINATIONS COMPRISING SERVO BAND IDENTIFIERS

Quantum LTO Holdings, LLC...

1. A magnetic tape comprising:a plurality of servo bands comprising corresponding servo band signals to be read by servo elements of a magnetic head, wherein the plurality of servo bands comprises servo band frames that are vertically aligned with respect to one another; and
a plurality of pattern combinations comprising servo band identifiers of the corresponding servo band signals from different servo bands of the plurality of servo bands;
wherein a pattern combination of the plurality of pattern combinations indicates a vertical position that is associated with the servo elements of the magnetic head among the plurality of servo bands when performing at least one of: a write operation or a read operation to the magnetic tape, wherein the pattern combination is formed by a first servo band identifier and a second servo band identifier corresponding to different servo bands, respectively, and matches a stored pattern combination to receive write data of the write operation, or read data of the read operation, at a data band of the magnetic tape.

US Pat. No. 10,923,142

SINGING VOICE SEPARATION WITH DEEP U-NET CONVOLUTIONAL NETWORKS

Spotify AB, Stockholm (S...

1. A method for operating a media player, comprising:playing a plurality of audio tracks;
receiving an instruction specifying that a volume of at least one of the audio tracks be adjusted; and
adjusting the volume of the at least one of the audio tracks in response to the instruction,
wherein at least one of the audio tracks represents an estimate of a provided audio signal, and the estimate is obtained based on application of the provided audio signal to a U-Net neural network having a plurality of skip connections between a plurality of layers of the U-Net neural network.

US Pat. No. 10,923,141

SINGING VOICE SEPARATION WITH DEEP U-NET CONVOLUTIONAL NETWORKS

Spotify AB, Stockholm (S...

1. A method for training a neural network system, comprising: applying an audio signal to a U-Net neural network system, the audio signal including a vocal component and a non-vocal component, wherein applying the audio signal to the U-Net neural network includes converting the audio signal to an image;Converting the image to an output audio signal and comparing the output audio signal of the U-Net neural network system to a target signal;
and adjusting at least one parameter of the U-Net neural network system to reduce a result of the comparing, for training the U-Net neural network system to estimate one of the vocal component and the non-vocal component.

US Pat. No. 10,923,140

DEVICE, ROBOT, METHOD, AND RECORDING MEDIUM

PANASONIC INTELLECTUAL PR...

17. A method for a device that interacts with a plurality of users, the device including a microphone that collects sound in a vicinity of the device, a speaker, a memory, and a processor, the method comprising:determining whether or not the sound includes speech of a first user;
determining, when the sound includes the speech of the first user, whether or not the sound includes a first word, the first word being stored in the memory and associated with the first user, the memory at least linking the plurality of users, words associated with the plurality of users, and times at which the words associated with the plurality of users are last spoken;
determining, when the sound includes the first word, whether or not a difference between a first time and a second time is equal to or less than a predetermined time, the first time being a current time at which the first user spoke the first word, the second time being a time at which a second user last spoke a second word associated with the first word, the second user being different from the first user, the first word and the second word each being stored with an association with a same content in the memory, and
causing, when the difference between the first time and the second time is equal to or less than the predetermined time, the speaker to output speech associated with the same content,
wherein the same content is stored in the memory as a third word,
the second word, which is stored in the memory with the association with the same content, is same as the third word, and
the first word, which is stored in the memory with the association with the same content, is a negative word for at least one of refusing or denying the same content.

US Pat. No. 10,923,139

SYSTEMS AND METHODS FOR PROCESSING MEETING INFORMATION OBTAINED FROM MULTIPLE SOURCES

MELO INC., San Jose, CA ...

1. A system for processing information of a meeting, comprising:a communication interface configured to receive meeting information obtained by a plurality of client devices, wherein the meeting information comprises multiple audio streams, wherein the audio streams comprise a plurality of audio frames;
a memory storing computer-executable instructions; and
a processor in communication with the communication interface and the memory, the processor being configured to execute the computer-executable instructions to perform operations, wherein the operations comprise:
determining signal-to-noise-ratio (SNR) indicators associated with the audio streams;
selecting, from the audio streams, a candidate audio stream based on the SNR indicators, wherein the SNR indicator associated with the candidate audio stream indicates that the candidate audio stream has a higher average SNR than that of a predetermined number of other audio streams;
generating an output data stream including at least a portion of the candidate audio stream; and
determining, for each audio stream, SNR values of a predetermine number of audio frames;
comparing the SNR values of corresponding audio frames across the multiple audio frames;
identifying, based on the comparison, a winning audio stream for an individual audio frame, wherein the winning audio stream has a higher SNR value than other audio streams for that individual audio frame; and
determining the SNR indicators based on a number of times an audio stream being identified as a winning audio stream over the predetermined number of comparisons conducted corresponding to the predetermined number of audio frames.

US Pat. No. 10,923,138

SOUND COLLECTION APPARATUS FOR FAR-FIELD VOICE

ALIBABA GROUP HOLDING LIM...

1. An apparatus comprising:a multi-channel analog sound receiver configured to convert a sound signal into an electrical signal;
a first analog-to-digital converter coupled to the multi-channel analog sound receiver and configured to convert the electrical signal into a first digital signal;
a second analog-to-digital converter coupled to a control device and configured to convert a playback reference signal to a second digital signal, the playback reference signal indicating an additional sound signal generated by the control device; and
an interface controller coupled to the first analog-to-digital converter and the second analog-to-digital converter and configured to de-noise the first digital signal using the second digital signal to remove the additional sound signal and transmit the de-noised first digital signal to the control device via a preset interface.

US Pat. No. 10,923,137

SPEECH ENHANCEMENT AND AUDIO EVENT DETECTION FOR AN ENVIRONMENT WITH NON-STATIONARY NOISE

Robert Bosch GmbH, Stutt...

1. A computer-implemented method comprising:obtaining by at least one computer processor, audio input;
extracting, by the at least one computer processor, audio features of the audio input;
generating, by the at least one computer processor, clean audio features for clean speech via a first machine learning system based on the audio features of the audio input;
generating, by the at least one computer processor, a clean speech signal based on the clean audio features of the audio input such that the clean speech signal is an audio signal in which noise of the audio input is removed or reduced;
extracting, by the at least one computer processor, a noise signal from the audio input by using the clean speech signal to obtain the noise signal from the audio input after the clean speech signal is generated from the clean audio features;
extracting, by the at least one computer processor, audio features of the extracted noise signal that is a result obtained after the clean speech signal is removed from the audio input;
generating, by the at least one computer processor, an audio label via a second machine learning system that receives the audio features of the extracted noise signal as input and selects the audio label that identifies a noise source that is determined to correspond to the audio features of the extracted noise signal based on a likelihood score; and
transmitting, by the at least one computer processor, the audio label to computer assistive technology that provides a response to the clean speech signal while using the audio label as contextual information.

US Pat. No. 10,923,136

SPEECH EXTRACTION METHOD, SYSTEM, AND DEVICE BASED ON SUPERVISED LEARNING AUDITORY ATTENTION

INSTITUTE OF AUTOMATION, ...

1. A speech extraction method based on a supervised learning auditory attention, comprising:step S10, converting an original overlapping speech signal into a two-dimensional time-frequency signal representation by a short-time Fourier transform to obtain a first overlapping speech signal;
step S20, performing a first sparsification on the first overlapping speech signal, mapping intensity information of a time-frequency unit of the first overlapping speech signal to preset D intensity levels, and performing a second sparsification on the first overlapping speech signal based on information of the preset D intensity levels to obtain a second overlapping speech signal;
step S30, converting the second overlapping speech signal into a pulse signal by a time coding method; wherein the time coding method comprises a time-rate coding method or a time-population coding method;
step S40, extracting a target pulse from the pulse signal by a target pulse extraction network;
wherein the target pulse extraction network is trained and constructed based on a spiking neural network; and
step S50, converting the target pulse into a time-frequency representation of a target speech to obtain the target speech by an inverse short-time Fourier transform.

US Pat. No. 10,923,135

MATCHED FILTER TO SELECTIVELY CHOOSE THE OPTIMAL AUDIO COMPRESSION FOR A METADATA FILE

1. A process for selecting an optimal audio codec, comprising:creating a plurality of processed audio clips by compressing and then decompressing an original audio clip with a plurality of different audio codec algorithms;
creating a matched filter utilizing the original audio clip to determine a power spectrum of each of the processed audio clips; and
identifying a selected audio codec algorithm used to create a processed audio clip having a highest power spectrum utilizing the matched filter.

US Pat. No. 10,923,134

METHOD, APPARATUS AND SYSTEM FOR EMBEDDING DATA WITHIN A DATA STREAM

SONIC DATA LIMITED, Lond...

1. A method of placing a code, having a plurality of digits, in original data having media data including audio data, such as a music video, piece of music or music track, to produce coded data, the method comprising:determining an area of original data where a digit of the code can be placed to inhibit detection using a placement criteria, wherein determining includes detecting a rate of change of one or more characteristics of the original data and selecting an area of original data following a start point or detection of a rate of change of one of said detected changing characteristics for placement of a digit of the code;
applying a coding strategy to determine at least one of the format or location of a digit of the code in coded data, wherein the or each digit of the code have a melodic or sympathetic relationship with a characteristic, such as an audio characteristic, of the corresponding original data in the at the location in which it is placed; and
adding a digit to the original data and outputting coded data.

US Pat. No. 10,923,133

METHODS AND APPARATUS TO IDENTIFY SIGNALS USING A LOW POWER WATERMARK

The Nielsen Company (US),...

1. An apparatus for media identification based on watermarks, the apparatus comprising:a first processor to:
determine, in response to receiving a signal, if a first watermark is present in the signal using a first processing technique, the first processing technique including:
compare a filtered watermark signal to a reference watermark signal corresponding to a universal watermark;
output an error value, wherein the error value is a difference between the filtered watermark signal and the reference watermark signal, the error value indicative of whether the first watermark is present in the signal; and
in response to the error value satisfying a threshold, reduce the error value associated with a frequency by adjusting coefficients in a direction opposite of a corresponding amplitude to the error value at the frequency;
provoke, in response to the first watermark being present in the signal, a second processing technique on a signal processor; and
the signal processor to:
extract a second watermark in the signal using the second processing technique.

US Pat. No. 10,923,132

DIFFUSIVITY BASED SOUND PROCESSING METHOD AND APPARATUS

Dolby Laboratories Licens...

1. A sound processing system including:a plurality of input channels for receiving audio signals from an audio scene, the audio scene including at least one target sound in the presence of background noise;
a diffusivity measurement unit operably coupled to the plurality of input channels for receiving the audio signals therefrom and measuring a level of diffusivity of the sounds present therein;
a leveler unit operably coupled to the plurality of input channels for receiving the audio signals therefrom and for applying a gain to the audio signals to minimize variations in the audio signal levels; and
a controller operably coupled to the diffusivity measurement unit and the leveler unit to control the gain applied to the audio signals by the leveler unit based on the level of diffusivity of the sounds present therein,
wherein the controller is configured to determine whether the measured level of diffusivity exceeds a predetermined threshold,
and
wherein the controller is configured to, in response to determining that the measured level of diffusivity exceeds the predetermined threshold, either i) set the gain applied to the audio signals to a value of 1 or ii) cause the audio signals to bypass the leveler unit thereby avoiding the application of any gain to the audio signals.

US Pat. No. 10,923,131

MDCT-DOMAIN ERROR CONCEALMENT

Dolby International AB, ...

1. A method for concealing errors in packets of data that are to be decoded in a modified discrete cosine transform (MDCT) based audio decoder arranged to decode a sequence of packets into a sequence of decoded frames, the method comprising:receiving, from an MDCT based audio encoder arranged to encode an audio signal, a packet comprising N/2 MDCT coefficients associated with N windowed time-domain samples of the audio signal;
identifying the packet to be an erroneous packet in that the packet comprises one or more errors;
estimating a first subset comprising N/4 windowed time-domain aliased samples of a first half of an intermediate frame comprising N windowed time-domain aliased samples associated with the erroneous packet, the estimation being based on relations between windowed time-domain aliased samples of the first subset and windowed time-domain samples of the N windowed time-domain samples of the audio signal;
estimating a second subset comprising remaining N/4 windowed time-domain aliased samples of the first half of the intermediate frame based on symmetry relations between windowed time-domain aliased samples of the second subset and windowed time-domain aliased samples of the first subset; and
synthesizing, from the first subset and the second subset, a decoded frame of the sequence, the synthesizing including performing an overlap add.

US Pat. No. 10,923,130

ELECTRONIC DEVICE AND METHOD OF PERFORMING FUNCTION OF ELECTRONIC DEVICE

Samsung Electronics Co., ...

1. An electronic device comprising:at least one communication circuit;
a speaker;
a microphone;
at least one processor operationally connected to the communication circuit, the speaker, and the microphone; and
a memory storing instructions,
wherein the instructions are executable by the at least one processor to cause the electronic device to:
receive a first voice input through the microphone,
execute first voiceprint authentication on the first voice input including determining whether the first voice input matches voice information corresponding to a user stored in the electronic device,
when the first voice input does not match the voice information, transmit a request message including first data related to the first voice input to at least one external electronic device using the communication circuit for execution of a second voiceprint authentication on the first voice input,
receive a response message from the at least one external electronic device indicating whether the first voice input is authenticated under the second voiceprint authentication,
receive a second voice input through the microphone;
receive access information for accessing an external server from the at least one external electronic device and access an external server based on the received access information; and
transmit second data related to the second voice input to the external server through the communication circuit for execution of at least one of Automatic Speech Recognition (ASR) or Natural Language Understanding (NLU) on the second data related to the second voice input.

US Pat. No. 10,923,129

METHOD FOR PROCESSING SIGNALS, TERMINAL DEVICE, AND NON-TRANSITORY READABLE STORAGE MEDIUM

GUANGDONG OPPO MOBILE TEL...

1. A method for processing signals, comprising:collecting, via an electroacoustic transducer of a headphone, a sound signal of external environment when a user talks through the headphone;
identifying feature audio of the sound signal and determining whether the feature audio matches a preset sound model; and
reminding the user in a preset reminding manner corresponding to the feature audio based on a determination that the feature audio matches the preset sound model;
wherein the electroacoustic transducer comprises at least one speaker configured to play an audio signal; and wherein collecting, via the electroacoustic transducer of the headphone, the sound signal of external environment when the user talks through the headphone comprises: collecting, by the at least one speaker of the headphone, the sound signal of the external environment, when the user talks through the headphone;
wherein the electroacoustic transducer further comprises a second microphone configured to collect a voice signal from the user; and wherein the method further comprises: denoising the voice signal from the user collected by the second microphone according to the sound signal of the external environment;
wherein the at least one speaker comprises a first speaker and a second speaker, and the method further comprises: acquiring the sound signal collected by the second microphone, the first speaker, and the second speaker of the headphone; acquiring location information of the sound signal relative to the headphone according to time delays of receiving the sound signal by the second microphone, the first speaker, and the second speaker; and reminding the user according to the location information;
wherein acquiring the location information of the sound signal relative to the headphone according to the time delays of receiving the sound signal by the second microphone, the first speaker, and the second speaker comprises: acquiring three time delays by using the second microphone, the first speaker, and the second speaker respectively as a reference microphone, wherein a time interval at which the sound signal reaches any two of the second microphone, the first speaker, and the second speaker is called a time delay; acquiring an average time delay according to the three time delays; and estimating the location information of the sound signal according to the average time delay and acquiring the location information of the sound signal relative to the headphone.

US Pat. No. 10,923,128

SPEECH RECOGNITION

Cirrus Logic, Inc., Aust...

1. A method of performing speech recognition, comprising:at a first device:
receiving an audio signal representing speech;
performing a first data integrity check operation on the received audio signal;
performing a speaker recognition process on the received audio signal;
forwarding the received audio signal to a second device, wherein the second device comprises a speech recognition function; and
forwarding an output of the first data integrity check operation to the second device; and
at the second device:
receiving the audio signal forwarded from the first device;
receiving the output of the first data integrity check operation forwarded from the first device;
performing a second data integrity check operation on the audio signal forwarded from the first device;
performing the speech recognition function on the audio signal forwarded from the first device;
determining if an output of the second data integrity check operation matches the output of the first data integrity check operation forwarded from the first device; and
using a result of performing the speech recognition function on the audio signal forwarded from the first device only if an output of the second data integrity check operation matches the output of the first data integrity check operation forwarded from the first device,
wherein the first and second data integrity check operations comprise one or more of generating a checksum value, generating a message authentication code (MAC) based on the received audio signal, and obtaining a predetermined hash function based on the received audio signal.

US Pat. No. 10,923,127

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR AUTOMATICALLY ANALYZING AND CATEGORIZING PHONE CALLS

DIALOGTECH INC.

1. A system for automatically processing call records comprising:a call records server that provides call recordings in real time upon completion of the call for analysis,
a call records analyzer that provides parallel processing of waveform and transcription of the call records;
means for categorizing the calls by processing structured features and unstructured data features through vectorization of the transcription so that the call records are objectively tagged and stored in groups of predetermined call categories, and
a display, wherein selection of a stored call record displays specific data for the call including a visual waveform depicting a breakdown of the call participants, a text transcription of the call, playable audio of the call, category tag of the call, and time and date of the call,
wherein the display further comprises a button that when pressed initiates output of a visual and audio walk-through of the call so that the audio of the call plays while a status indicator bar travels along visual waveform and a highlighter highlights the corresponding word text of the call.