US Pat. No. 10,559,509

INSULATING SUBSTRATE AND SEMICONDUCTOR DEVICE USING SAME

Hitachi Metals, Ltd., To...

1. An insulating substrate comprising:a heat dissipation layer;
a wire layer;
a wire formed within the wire layer that is connected to a first semiconductor and a second semiconductor;
an insulating layer formed between the wire layer and the heat dissipation layer that electrically insulates the wire layer from the heat dissipation layer;
and
a resistance layer that is integrally formed with the wire from a paste including RuO2 and a glass powder, wherein a width and length of the resistance layer are adjusted to provide an equal resistance to an input gate of the first semiconductor and the second semiconductor.

US Pat. No. 10,559,508

METHOD FOR MANUFACTURING SIC SUBSTRATE

Mitsubishi Electric Corpo...

1. A method for manufacturing an SiC substrate comprising:performing a CMP treatment on an SiC substrate;
after the CMP treatment, capturing an image of a surface of the SiC substrate to detect a scratch;
determining the SiC substrate as a good article when a length L of the scratch having a contrast value equal to or larger than a threshold value is not more than ?(D/2)2/A×F/100,
wherein the scratch having the contrast value equal to or larger than the threshold value in the image serves as a starting point of an epitaxial defect,
a diameter of the SiC substrate is represented by D,
a length of a long side of a device chip to be formed on the SiC substrate is represented by A, and
an allowable defective rate caused by scratches is represented by F.

US Pat. No. 10,559,507

DIRECT WAFER MAPPING AND SELECTIVE ELASTOMER DEPOSITION

Facebook Technologies, LL...

1. A method, comprising:applying a voltage difference across electrodes of each of a plurality of light emitting diodes (LEDs);
measuring at least one parameter associated with each of the plurality of LEDs to determine whether each of the plurality of LEDs is operational;
selectively depositing an elastomer coating on a top surface of each of the plurality of LEDs determined to be operational.

US Pat. No. 10,559,506

METHOD OF INSPECTING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method of inspecting a semiconductor device, the method comprising:setting at least one target place on a wafer, the target place including at least one deep trench;
forming a first cut surface by performing first milling on the target place in a first direction;
obtaining first image data of the first cut surface;
forming a second cut surface by performing second milling on the target place in a second direction opposite to the first direction;
obtaining second image data of the second cut surface;
obtaining a plurality of first critical dimension (CD) values for the deep trench from the first image data;
obtaining a plurality of second CD values for the deep trench from the second image data;
analyzing a degree of bending of the deep trench based on the plurality of first CD values and the plurality of second CD values; and
providing the semiconductor device meeting a condition based on results of the analyzing.

US Pat. No. 10,559,505

PROTECTIVE FILM-FORMING FILM, SHEET FOR FORMING PROTECTIVE FILM, COMPLEX SHEET FOR FORMING PROTECTIVE FILM, AND INSPECTION METHOD

Lintec Corporation, Toky...

1. An inspection method comprising: adhering a protective film-forming film to a semiconductor wafer; curing the protective film-forming film to obtain a semiconductor wafer provided with a protective film; and, irradiating infrared rays to the semiconductor wafer provided with the protective film or a semiconductor chip obtained by processing the semiconductor wafer provided with the protective film, to inspect presence of cracks which cannot be detected by visual observation in the semiconductor wafer provided with the protective film or the semiconductor chip provided with the protective film; wherein the light transmittance at a wavelength of 1600 nm of the protective film-forming film is 72% or greater, and the light transmittance at a wavelength of 550 nm of the protective film-forming film is 20% or less.

US Pat. No. 10,559,504

HIGH MOBILITY SEMICONDUCTOR FINS ON INSULATOR

International Business Ma...

1. A method of fabricating a monolithic structure including parallel semiconductor fins, comprising:obtaining a first structure including:
a semiconductor substrate;
a bottom dielectric layer on the substrate;
a top dielectric layer on the bottom dielectric layer;
a first trench extending vertically through the top dielectric layer and the bottom dielectric layer and exposing a top surface portion of the semiconductor substrate; and
an epitaxial semiconductor pillar within the first trench and directly on the exposed top surface portion of the semiconductor substrate;
forming a plurality of parallel second trenches extending vertically through the top dielectric layer and orthogonally with respect to the first trench, the second trenches including bottom ends adjoining the bottom dielectric layer and inner ends adjoining the semiconductor pillar;
epitaxially growing a plurality of semiconductor fins directly on the semiconductor pillar such that the semiconductor fins extend laterally from the semiconductor pillar within the plurality of second trenches, the semiconductor fins adjoining the bottom dielectric layer;
removing the semiconductor pillar from at least a top portion of the first trench extending vertically through the top dielectric layer; and
filling at least the top portion of the first trench with electrically insulating material.

US Pat. No. 10,559,503

METHODS, APPARATUS AND SYSTEM FOR A PASSTHROUGH-BASED ARCHITECTURE

GLOBALFOUNDRIES INC., Gr...

1. A finFET device, comprising:a first gate structure and a second gate structure on a semiconductor substrate;
a first active area contacting a first end of said first gate structure and contacting a first end of said second gate structure;
a second active area contacting a second end of said first gate structure and contacting a second end of said second gate structure; and
a self-aligned trench silicide (TS) structure configured to operatively couple said first active area to said second active area, wherein said TS structure is flush in height with said first gate structure and said second gate structure.

US Pat. No. 10,559,502

FABRICATION OF A PAIR OF VERTICAL FIN FIELD EFFECT TRANSISTORS HAVING A MERGED TOP SOURCE/DRAIN

INTERNATIONAL BUSINESS MA...

1. An adjoined pair of vertical fin devices, comprising:a first bottom source/drain and a second bottom source/drain on a substrate, wherein the first bottom source/drain is separated from the second bottom source/drain by a shallow trench isolation region in the substrate;
at least four vertical fins, wherein at least two of the at least four vertical fins are on the first bottom source/drain and at least two of the at least four vertical fins are on the second bottom source/drain; and
a merged source/drain on one vertical fin on the first bottom source/drain and one adjacent vertical fin on the second bottom source/drain that bridges the shallow trench isolation region to electrically couple the adjacent vertical fins.

US Pat. No. 10,559,501

SELF-ALIGNED QUADRUPLE PATTERNING PROCESS FOR FIN PITCH BELOW 20NM

QUALCOMM Incorporated, S...

1. A method of forming one or more two-fin FinFET devices, comprising:forming one or more mandrels with a lithographic etch process;
forming at least one sidewall spacer on at least one vertical side of each of the one or more mandrels after formation of the one or more mandrels;
removing the one or more mandrels after formation of the at least one sidewall spacer; and
forming two fins, one on each of the opposing vertical sides of the at least one sidewall spacer after formation of the at least one sidewall spacer, to form two fins of the two-fin FinFET device,
wherein fins of each two-fin FinFET device is formed on opposing vertical sides of the at least one sidewall spacer formed on one of the mandrels.

US Pat. No. 10,559,500

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE WITH WIDER SIDEWALL SPACER FOR A HIGH VOLTAGE MISFET

RENESAS ELECTRONICS CORPO...

1. A manufacturing method of a semiconductor device, comprising the steps of:(a) providing a semiconductor substrate;
(b) forming a first gate electrode via a first gate insulating film and a second gate electrode via a second gate insulating film over the semiconductor substrate;
(c) forming first sidewall insulating films selectively formed on side surfaces of the first and second gate electrodes;
(d) forming a first insulating film over the semiconductor substrate to cover upper surfaces of the first and second gate electrodes and side surfaces of the first sidewall insulating films, the first insulating film having first portions on upper surfaces of the first and second gate electrodes and second portions on side surfaces of the first sidewall insulating films on the first and second gate electrode;
(e) forming second sidewall insulating films selectively formed on the second portions at the side surfaces of the second gate electrode;
(f) forming a second insulating film over the first insulating film and the second sidewall insulating film; and
(g) after the step (e), etching back the second insulating film, the second sidewall insulating films and the first insulating film to thereby form third sidewall insulating films having a first width which are formed on the side surfaces of the first gate electrode via the first sidewall insulating films and fourth sidewall insulating films having a second width which are formed on the side surfaces of the second gate electrode via the first sidewall insulating films,wherein the first width is smaller than the second width.

US Pat. No. 10,559,499

SEMICONDUCTOR DEVICE, DISPLAY SYSTEM, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:an image processing portion comprising a correction circuit,
wherein the correction circuit comprises a programmable logic device,
wherein the programmable logic device is configured to be reconfigured so as to be capable of executing first gamma correction by input of first configuration data,
wherein the programmable logic device is configured to be reconfigured so as to be capable of executing second gamma correction by input of second configuration data,
wherein the first gamma correction is performed by a first method and the second gamma correction is performed by a second method,
wherein the first method is table approximation, and
wherein the second method is polygonal line approximation.

US Pat. No. 10,559,498

LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE

INTERNATIONAL BUSINESS MA...

1. A system for completing of annealing metal interconnect overburden layers on semiconductor devices being fabricated on a chip on a semiconductor wafer, comprising:a scanning electron microscope (SEM) equipped with an electron backscatter diffraction (EBSD) capability;
a laser;
a processor; and
a memory, the memory storing instructions to cause the processor to perform:
on a wafer having a metal interconnect overburden layer initially partially annealed, detecting and determining an orientation of early recrystallizing grains at specific locations on a top surface of the metal overburden layer, as implemented and controlled by the processor, using data from the SEM equipped with the EBSD capability;
determining whether the orientations of the early recrystallizing grains at the specific locations is desirable or undesirable, as executed by the processor; and
selectively performing a laser anneal of the metal interconnect overburden layer, as implemented and controlled by the processor, using the laser, in a manner that selectively promotes or inhibits grain orientations from growing at selective locations on the metal interconnect overburden layer.

US Pat. No. 10,559,497

SEAMLESS TUNGSTEN FILL BY TUNGSTEN OXIDATION-REDUCTION

Applied Materials, Inc., ...

1. A method of substrate processing comprising:providing a substrate with a first substrate surface of a first material and a second substrate surface of a second material, the substrate having at least one feature with a sidewall and a bottom, the sidewall formed by the first substrate surface and the bottom formed by the second substrate surface;
forming a tungsten film on the substrate, the tungsten film having a seam formed within the feature and an overburden formed on the first substrate surface outside the feature;
planarizing the substrate to remove the overburden from the first substrate surface so that a top of the tungsten film is about coplanar with the first substrate surface outside the feature;
oxidizing the tungsten film to form a tungsten oxide pillar which extends from the at least one feature without a seam;
reducing the tungsten oxide pillar to tungsten, the tungsten forming a substantially seamless tungsten gapfill within the at least one feature so that a top of the tungsten gapfill is below the first surface outside of the feature; and
selectively depositing additional tungsten on the tungsten gapfill to raise the top of the tungsten gapfill to be substantially coplanar with the first substrate surface outside of the feature, selectively depositing additional tungsten comprises depositing a silicon film on the tungsten gapfill and exposing the silicon film to a tungsten halide to convert the silicon film to tungsten.

US Pat. No. 10,559,496

TECHNIQUES FOR FILLING A STRUCTURE USING SELECTIVE SURFACE MODIFICATION

APPLIED MATERIALS, INC., ...

1. A method of device processing, comprising:providing a cavity in a layer;
directing energetic flux to a bottom surface of the cavity, the cavity having a sidewall oriented perpendicularly to the bottom surface, wherein the energetic flux is oriented parallel to the sidewall and does not strike the sidewall of the cavity;
performing an exposure of the cavity to a moisture-containing ambient; and
introducing a fill material in the cavity using an atomic layer deposition (ALD) process, wherein the fill material forms in layers parallel to the bottom surface, while formation of fill material on the sidewall is suppressed.

US Pat. No. 10,559,495

METHODS FOR PROCESSING SEMICONDUCTOR DICE AND FABRICATING ASSEMBLIES INCORPORATING SAME

Micron Technology, Inc., ...

11. A method for fabricating a reconstituted wafer, the method comprising:forming a film comprising a metal material on a surface of a semiconductor wafer;
securing semiconductor dice to the film in an array of mutually spaced locations;
covering backs and sides of the semiconductor dice with a dielectric molding material; and
removing material from an opposing surface of the semiconductor wafer to expose the film.

US Pat. No. 10,559,494

MICROELECTRONIC ELEMENTS WITH POST-ASSEMBLY PLANARIZATION

Tessera, Inc., San Jose,...

1. A microelectronic unit, comprising:a carrier structure having a front surface, a rear surface opposite the front surface, and a recess having edge surfaces extending below the front surface of the carrier structure;
a microelectronic element having contacts at a top surface thereof, the microelectronic element having edge surfaces adjacent the edge surfaces of the recess;
terminals electrically connected with the contacts of the microelectronic element;
a dielectric region extending between the edge surfaces of the recess and the edge surfaces of the microelectronic element; and
a conductive via extending through the dielectric region between one of the edge surfaces of the recess and one of the edge surfaces of the microelectronic element to the rear surface of the carrier structure, the conductive via being electrically connected with a respective one of the terminals and a respective one of the contacts of the microelectronic element.

US Pat. No. 10,559,493

MULTIFUNCTION SINGLE VIA PATTERNING

International Business Ma...

1. A method for semiconductor device fabrication, comprising:forming storage elements on conductive structures;
depositing a cap layer over the storage elements and the conductive structures;
forming an interlevel dielectric (ILD) layer over the cap layer;
patterning trenches in the ILD layer to expose a top portion of the storage elements;
removing the storage elements where interlevel vias are to be formed to expose the conductive structures therebelow to form via openings; and
depositing a conductive material in the trenches and the via openings to concurrently make contact with the storage elements and form interlevel vias in the via openings.

US Pat. No. 10,559,492

PATTERNING METHODS FOR SEMICONDUCTOR DEVICES AND STRUCTURES RESULTING THEREFROM

Taiwan Semiconductor Manu...

1. A method comprising:forming a first mask layer over a target layer;
forming a plurality of spacers over the first mask layer;
forming a second mask layer over the plurality of spacers and patterning the second mask layer to form a first opening, wherein in a plan view a major axis of the first opening extends in a direction that is perpendicular to a major axis of a spacer of the plurality of spacers;
depositing a sacrificial material in the first opening;
patterning the sacrificial material;
etching the first mask layer using the plurality of spacers and the patterned sacrificial material;
etching the target layer using the etched first mask layer to form second openings in the target layer; and
filling the second openings in the target layer with a conductive material.

US Pat. No. 10,559,491

FABRICATION OF VERTICAL TRANSPORT FIN FIELD EFFECT TRANSISTORS WITH A SELF-ALIGNED SEPARATOR AND AN ISOLATION REGION WITH AN AIR GAP

INTERNATIONAL BUSINESS MA...

1. A method of forming a vertical transport fin field effect transistor with self-aligned dielectric separators, comprising:foil ling two vertical fins on a bottom source/drain region;
forming an isolation channel through the bottom source/drain region into a substrate between the two vertical fins; and
forming an insulating plug in the isolation channel, wherein the insulating plug has a pinch-off void within the isolation channel that does not extend beyond the bottom source/drain region and the substrate, and a section of the insulating plug extends beyond the bottom source/drain region and the substrate.

US Pat. No. 10,559,490

DUAL-DEPTH STI CAVITY EXTENSION AND METHOD OF PRODUCTION THEREOF

GLOBALFOUNDRIES INC., Gr...

1. A device comprising:a multiple depth shallow trench isolation (STI) regions, wherein each of the multiple depth STI regions comprises: a top region having a vertical sidewall profile; and a bottom region having a width greater than or equal to the top region and a sidewall profile;
a first well in a portion of a substrate, the first well electrically isolated from the substrate;
a second well in a portion of the first well, the second well electrically isolated from the first well and the substrate;
a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer above the second well; and
the multiple depth STI regions, laterally separated, through the SOI layer and the BOX layer and in the substrate, wherein at least one of the multiple depth STI regions is deeper than other multiple depth STI regions,
wherein the multiple depth STI regions further comprise:
a first, second and third multiple depth STI regions, wherein the first and third multiple depth STI regions are deeper than the second well;
a silicon nitride (SiN) liner on sidewall portions of the top region of the first and third multiple depth STI regions;
an oxide layer in the bottom region and a portion of the top region of the first and third multiple depth STI regions; and
a high density plasma (HDP) or tetraethyl orthosilicate (TEOS) layer in remaining portion of the top region of the first and third multiple depth STI regions, the upper surface of the HDP or TEOS layer coplanar to the upper surface of the SOI layer.

US Pat. No. 10,559,489

APPARATUS FOR MANUFACTURING A DISPLAY DEVICE AND A MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. An apparatus for manufacturing a display device, comprising:a first jig including a first side, the first side having a concave groove for receiving a cover window, wherein the cover window includes a first planar portion, a first curved portion and a second curved portion, wherein the first and second curved portions are disposed at opposite ends of the first planar portion in a first direction;
a second jig including a planar side for receiving a display panel and provided to horizontally move in a second direction crossing the first direction, wherein when the second jig is moved in the second direction with the display panel on the planar side, the display panel is disposed between the first and second curved portions of the cover window; and
a pair of third jigs for supporting the first and second curved portions of the cover window.

US Pat. No. 10,559,488

TWO-LEVEL TAPE FRAME RINSE ASSEMBLY

VEECO PRECISION SURFACE P...

1. A two-level tape frame rinse assembly for use in processing a wafer comprising:a rotatable chuck assembly,
a plurality of grippers associated with the chuck assembly for selectively grasping the wafer, each gripper having a pivotable gripper finger, each gripper finger being movable between an open position and a closed position; the grippers including a plurality of lifter pins each being movable between an up position and a down position, the plurality of grippers being spaced circumferentially;
a rotatable backside support plate associated with the chuck assembly for supporting the wafer, the backside support plate having a plurality of openings formed therethrough, the backside support plate being disposed internally between the plurality of grippers; and
an annular shaped frame on which the grippers are disposed and fixed, the rotatable backside support plate being disposed internally within the annular shaped frame, each gripper protruding upwardly from the annular shaped frame, wherein the annular shaped frame is connected to a center hub by a plurality of spoke shaped supports;
wherein in a first wafer position, the lifter pins are in the up position for supporting the wafer such that a gap is formed between a backside of the wafer and a top surface of the backside support plate,
wherein in a second wafer position, the lifter pins are in the down position for allowing the wafer to seat against and be supported by the backside support plate;
wherein in a third wafer position, the lifter pins are in the down position and the gripper fingers are in the closed position for grasping the wafer such that the gap is formed between the backside of the wafer and the top surface of the backside support plate to allow for a rinse tool to pass through one opening of the backside support plate and treat the backside of the wafer.

US Pat. No. 10,559,487

WAFER DIVIDING METHOD AND DIVIDING APPARATUS

DISCO CORPORATION, Tokyo...

1. A wafer dividing method using a dividing apparatus, the dividing apparatus including a table adapted to suction hold a wafer through a heat-shrinkable tape of a work set, the work set having the tape attached to a ring frame to close an opening of the ring frame, the wafer being formed with division starting points along division lines and attached to the tape at the opening; a ring frame holding section adapted to hold the ring frame of the work set; a lifting unit adapted to relatively move the table and the ring frame holding section in a vertical direction for bringing them closer to and away from each other; and a heater adapted to heat the tape in a ring shape between an outer periphery of the wafer and an inner periphery of the ring frame of the work set, the table and the ring frame holding section being relatively moved respectively in an upward direction and a downward direction such as to be spaced away from each other by the lifting unit, in a state in which the work set is held by the ring frame holding section, to expand the tape at the opening and thereby to divide the wafer at the division starting points into chips, the water dividing method comprising:a holding step of holding the work set by the ring frame holding section;
a dividing step of relatively moving the table and the ring frame holding section away from each other by the lifting unit to expand the tape, and dividing the wafer at the division starting points to form a predetermined gap between the adjacent chips, after the holding step;
a tape holding step of suction holding that area of the expanded tape to which the wafer is adhered by the table, after the dividing step;
a ring tape expanding step of relatively moving the table and the ring frame holding section further away from each other, to expand the ring-shaped tape between the outer periphery of the wafer and the inner periphery of the ring frame, after the tape holding step; and
a fixing step of relatively moving the table and the ring frame holding section closer to each other by the lifting unit to slacken the ring-shaped tape and heating the ring-shaped tape by the heater, to heat shrink the ring-shaped tape and to fix the work set while maintaining the predetermined gap between the adjacent chips, after the ring tape expanding step.

US Pat. No. 10,559,486

METHOD FOR POLYMER-ASSISTED CHIP TRANSFER

Facebook Technologies, LL...

1. A method comprising:depositing a first adhesive layer on a first substrate, the first adhesive layer comprises a first material;
drying the first adhesive layer;
providing a second substrate with one or more chips attached;
placing the one or more chips on the first substrate through the first adhesive layer, the one or more chips attached to the second substrate;
depositing a second adhesive layer on the first substrate, the second adhesive layer covering edges of the second substrate and an edge portion of at least one of the one or more chips, the second adhesive layer not covering other portions of the one or more chips, the second adhesive layer made of a second material that is different from the first material, at least one of the first and second materials being a polymer material;
performing laser lift-off on an interface of the one or more chips and the second substrate;
removing at least the portions of the second adhesive layer covering the edges of the second substrate after performing the laser lift-off;
removing the second substrate from the one or more chips after performing the laser lift-off;
softening the first adhesive layer after removing the second substrate; and
removing the one or more chips from the first substrate.

US Pat. No. 10,559,485

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, METHOD OF LOADING SUBSTRATE AND NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM

Kokusai Electric Corporat...

1. A method of manufacturing a semiconductor device using a substrate retainer comprising a substrate loading region provided with a plurality of slots and capable of loading and holding a maximum of X substrates in the plurality of slots, where X is a natural number equal to or greater than 3, the method comprising:(a) loading Y, where Y is a natural number less than X, substrate(s) to be processed in the substrate retainer in a dispersed manner by adjusting Z, where Z is a natural number, indicating a maximum number of the substrates to be loaded consecutively in the substrate retainer such that a density distribution of the substrate(s) to be processed in the substrate loading region when Z is adjusted is more flattened compared with the density distribution of the substrate(s) to be processed when Z is equal to Y; and
(b) loading the substrate retainer where the Y substrate(s) to be processed is/are dispersedly loaded into a process chamber and processing the Y substrate(s) to be processed.

US Pat. No. 10,559,484

SUBSTRATE STORAGE CONTAINER

SHIN-ETSU POLYMER CO., LT...

1. A substrate storage container comprising: a container body for storing substrates, wherein at least one side of the container body is open; and a lid removable to open and close an opening of the container body, whereinthe substrate storage container comprises, in the container body, first holding portions with first holding grooves for holding rear parts of the substrates,
the substrate storage container comprises, inside of the lid, second holding portions with second holding grooves for holding front parts of the substrates,
at least the first holding grooves in the first holding portions and at least the second holding grooves in the second holding portions are made of an alloy resin mainly containing a polycarbonate resin and a polybutylene terephthalate resin, and
the alloy resin making at least the first holding grooves contains an amount equal to or more than 25% by mass and equal to or less than 40% by mass of polybutylene terephthalate resin and equal to or more than 60% and equal to or less than 75% of polycarbonate resin with respect to the mass of the resin components of the alloy resin.

US Pat. No. 10,559,483

PLATFORM ARCHITECTURE TO IMPROVE SYSTEM PRODUCTIVITY

LAM RESEARCH CORPORATION,...

1. A loading station for a substrate processing system, the loading station having a vertically-stacked configuration and comprising:a first loading station, the first loading station comprising
a first airlock volume, and
a first valve and a second valve arranged at respective ends of the first loading station, wherein the first valve and the second valve are configured to selectively provide access to the first airlock volume, wherein the first valve and the second valve include a first actuator and a second actuator, respectively, configured to open and close the first valve and the second valve, and wherein the first actuator and the second actuator extend downward from the first loading station; and
a second loading station arranged above and adjacent to the first loading station, the second loading station comprising
a second airlock volume, and
a third valve and a fourth valve arranged at respective ends of the second loading station, wherein the third valve and the fourth valve are configured to selectively provide access to the second airlock volume, wherein the third valve and the fourth valve include a third actuator and a fourth actuator, respectively, configured to open and close the third valve and the fourth valve,
a third loading station arranged above and adjacent to the second loading station, the third loading station comprising
a third airlock volume, and
a fifth valve and a sixth valve arranged at respective ends of the third loading station, wherein the fifth valve and the sixth valve are configured to selectively provide access to the third airlock volume, wherein the fifth valve and the sixth valve include a fifth actuator and a sixth actuator, respectively, configured to open and close the fifth valve and the sixth valve,
wherein a length of the first loading station is less than a length of the second loading station, wherein the length of the first loading station corresponds to a horizontal distance between ends of the first loading station and the length of the second loading station corresponds to a horizontal distance between ends of the second loading station, and wherein the third actuator and the fourth actuator each extend downward from the second loading station to overlap a horizontal plane defined by the first loading station.

US Pat. No. 10,559,482

HEAT TREATMENT METHOD OF LIGHT IRRADIATION TYPE

SCREEN HOLDINGS CO., LTD....

1. A heat treatment method for irradiating a substrate held on a quartz susceptor provided in a chamber with light from a continuous lighting lamp provided outside said chamber to heat the substrate, the heat treatment method comprising the steps of:(a) keeping temperature of a quartz window provided in said chamber by light irradiation from said continuous lighting lamp;
(b) holding an object to be heated that absorbs infrared light to increase in temperature on said susceptor before a substrate to be treated is transferred into said chamber so that said object to be heated is heated by light irradiation from said continuous lighting lamp to preliminary heat said susceptor; and
(c) holding said substrate on said susceptor after said step (b) so that said substrate is heated by light irradiation from said continuous lighting lamp, wherein
when temperature of each of said quartz window and said susceptor increases to be constant by continuously irradiating a plurality of substrates of one lot with light to heat the substrates without heating said quartz window and said susceptor, the temperature of said quartz window and the temperature of the susceptor are indicated as a first stable temperature and a second stable temperature, respectively,
said quartz window is heated so that the temperature of said quartz window is maintained at said first stable temperature in said step (a), and
said susceptor is heated so that the temperature of said susceptor reaches said second stable temperature in said step (b).

US Pat. No. 10,559,481

PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus, comprising:a vacuum chamber in which a sample is plasma processed;
a first radio-frequency power supply supplying a first radio frequency power to generate a plasma;
a sample stage on which the sample is mounted;
a second radio-frequency power supply supplying a second radio-frequency power to the sample stage; and
a control device comprising an input section, a microcomputer, and a D/A converter, wherein the control device is configured to convert a repetition frequency of a pulse for time-modulating the second radio-frequency power to a first analog value corresponding to a first frequency band of the repetition frequency and a second analog value corresponding to a second frequency band of the repetition frequency, the second frequency band being wider than the first frequency band of the repetition frequency;
wherein the second radio-frequency power supply includes:
an A/D converter having a plurality of output ports thereon, the A/D converter configured to receive the first analog value and the second analog value, and to convert the first analog value and the second analog value transmitted by the control device to a first digital signal and a second digital signal, respectively, wherein the A/D converter is further configured to output the first digital signal on the first output port and to output the second digital signal on the second output port;
a signal processor constructed at least in part of hardware configured to select the first output port on which is output the first digital signal converted by the A/D converter or the second output port on which is output the second digital signal converted by the A/D converter based on a channel switching signal received by the signal processor from the control device, wherein said channel switching signal corresponds to the first and second digital signals, and wherein said channel switching signal is based on the second radio-frequency power; and
a pulse generator configured to generate pulses having a repetition frequency corresponding to the first digital signal or the second digital signal selected by the signal processor.

US Pat. No. 10,559,480

SUBSTRATE TREATMENT APPARATUS AND SUBSTRATE TREATMENT METHOD

SCREEN Holdings Co., Ltd....

1. A substrate treatment apparatus comprising:a first tank that stores treatment liquid for treating a substrate;
a first path that returns said treatment liquid spilled over from an upper part of said first tank to a lower part of said first tank;
a second path that branches from said first path;
a measurement tank that is provided with a first region into which said treatment liquid flows from said second path and a second region into which said treatment liquid spilled over from an upper part of said first region flows and stores said treatment liquid flowed in from said second path; and
a pressure sensor that measures a pressure of said treatment liquid at a predetermined depth in said measurement tank in a state in which said treatment liquid is spilling over from an upper part of said second region.

US Pat. No. 10,559,479

SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:a lid member opposed to a surface of a semiconductor substrate;
a support member supporting the lid member;
an oxidation resistant member opposed to a back of the semiconductor substrate; and
an oxidizing system gas introducing member introducing an oxidizing system gas that oxidizes the back of the semiconductor substrate.

US Pat. No. 10,559,478

METHOD FOR MANUFACTURING ELECTRONIC DEVICE AND ELECTRONIC DEVICE

SHINDENGEN ELECTRIC MANUF...

1. A manufacturing method for an electronic device comprising:a step of placing a substrate, which has a metal plate on a back-surface side, on a back-surface-side mold having a mold recessed part;
a step of placing an insertion part for inserting a fastening member on a front surface of the substrate and peripherally inside the mold recessed part;
a step of placing a front-surface-side mold on the back-surface-side mold so as to cover the substrate; and
a step of pouring resin by potting between the front-surface mold and the back-surface-side mold, while the substrate is pressed against the back-surface-side mold,
wherein the metal plate is pressed against the back-surface-side mold by pressing a top part of the insertion part and circumferential part, peripherally outside the insertion part, of the metal plate is in contact with an edge of the mold recessed part, when the substrate is pressed against the back-surface-side mold in the step of pouring resin,
wherein the metal plate has a central metal body part surrounded by a peripheral metal thinned part surrounding the metal body part and which is thinner than the metal body part,
wherein the metal thinned part is located outward of circumference of the mold recessed part and the metal body part is in contact with an edge of the circumference of the mold recessed part, when the metal plate is pressed against the back-surface-side mold in the step of pouring resin.

US Pat. No. 10,559,477

SEMICONDUCTOR PACKAGE WITH REDUCED PARASITIC COUPLING EFFECTS AND PROCESS FOR MAKING THE SAME

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a silicon-on-insulator (SOI) structure including an epitaxial layer, a buried oxide (BOX) layer over the epitaxial layer, and a silicon handle layer over the BOX layer, wherein:
the epitaxial layer has a first sacrificial epitaxial section, a first active epitaxy section and an isolation region; and
the isolation region surrounds the first active epitaxy section and separates the first active epitaxy section from the first sacrificial epitaxial section;
forming at least one first etchable structure that extends through the first sacrificial epitaxial section and the BOX layer to the silicon handle layer;
integrating a first active device in or on the first active epitaxy section, such that the epitaxial layer is formed as a device layer; and
forming a (back-end-of-line) BEOL layer underlying the device layer, wherein:
the BEOL layer has an upper surface including a first surface portion and a second surface portion surrounding the first surface portion;
the first sacrificial epitaxial section is over the first surface portion and not over the second surface portion;
the first epitaxy section and the isolation region are over the second surface portion and not over the first surface portion; and
the BEOL layer comprises a first passive device and a second passive device, which are underlying the first surface portion and not underlying the second surface portion.

US Pat. No. 10,559,476

METHOD AND STRUCTURE FOR A 3D WIRE BLOCK

1. A method for forming an electrical interconnect mechanism, the steps comprising:depositing metal to form a plane having a programmed shape through a process that adds material rather than removes it to form a metal plane by a 3D forming;
extending wires of programmed geometries from said formed metal plane and extending said wires to programmed locations in three dimensional space, and
adding a dielectric to fill on top of said metal plane encompassing all of said metal wires and curing said dielectric to form one or more substrates, removing said metal plane from said one or more substrates by a secondary process thereby producing a finished block having separate isolated paths that provides one or more electrical connections to different spots on said one or more substrates.

US Pat. No. 10,559,475

CONTROL OF DIRECTIONALITY IN ATOMIC LAYER ETCHING

Lam Research Corporation,...

18. A method for performing atomic layer etching (ALE) on a substrate, comprising:performing a surface modification operation on a substrate surface, the surface modification operation including exposing the substrate surface to a halogen-containing plasma that converts at least one monolayer of the substrate surface to a modified layer, wherein a bias voltage is applied during the surface modification operation, the bias voltage being configured to control a depth of the substrate surface that is converted by the surface modification operation, wherein the bias voltage is configured to accelerate ions from the first plasma towards the substrate surface without substantially etching the substrate surface;
performing a removal operation on the substrate surface, the removal operation including removing at least a portion of the modified layer from the substrate surface, wherein removing the portion of the modified layer includes a ligand exchange reaction and applying thermal energy to effect desorption of the portion of the modified layer.

US Pat. No. 10,559,474

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME

SK hynix Inc., Gyeonggi-...

1. A manufacturing method of a semiconductor device, the manufacturing method comprising:forming a pipe gate in which an etch stop pad groove filled with an etch stop pattern is formed;
alternately stacking first material layers and second material layers over the pipe gate;
forming a first slit penetrating the first material layers and the second material layers and overlapping the etch stop pattern;
opening the etch stop pad groove by removing the etch stop pattern through the first slit;
forming a first slit insulating layer filling the first slit and the etch stop pad groove; and
forming a second slit penetrating the first material layers and the second material layers, the second slit crossing the first slit at an overlapping portion of the first slit and the etch stop pad groove.

US Pat. No. 10,559,473

SEMICONDUCTOR PROCESS FOR IMPROVING LOADING EFFECT IN PLANARIZATION

UNITED MICROELECTRONICS C...

1. A semiconductor process for improving loading effects in planarization, comprising:providing a substrate with a first region and a second region;
forming multiple first protruding patterns on said first region and said second region of said substrate, wherein a density of said first protruding pattern in said first region is larger than a density of said first protruding pattern in said second region;
forming a first dielectric layer on said substrate and said first protruding patterns, wherein said first dielectric layer is provided with multiple second protruding patterns corresponding to underlying said first protruding patterns;
forming a second dielectric layer on said first dielectric layer;
performing a first planarization process to remove a portion of said second dielectric layer and expose top surfaces of said second protruding patterns;
performing an etch process to remove said second protruding patterns of said first dielectric layer;
removing remaining said second dielectric layer; and
performing a second planarization process to said first dielectric layer.

US Pat. No. 10,559,472

WORKPIECE PROCESSING METHOD

TOKYO ELECTRON LIMITED, ...

1. A method of processing a workpiece comprising:providing a workpiece which includes a plurality of holes formed on a surface of the workpiece, wherein the plurality of holes include a small diameter hole and a large diameter hole having a diameter larger than the small diameter hole, and wherein the workpiece has an initial size difference which is a difference between the diameters of the large diameter hole and the small diameter hole;
performing a first sequence on the workpiece, the first sequence including:
a first process of forming a film on an inner surface of each of the plurality of holes and wherein the first process includes forming the film with a thickness on the inner surface of the small diameter hole which is smaller than a thickness of the film formed on the inner surface of the large diameter hole; and
a second process of isotropically etching the film, and during the second process the film of the small diameter hole is etched to a small hole film inner diameter and the film of the large diameter hole is etched to a large hole film inner diameter, and wherein the workpiece has a post-etch size difference which is a difference between the large hole film inner diameter and the small hole film inner diameter, and after the isotropically etching the post-etch size difference is smaller than the initial size difference, and
wherein the first process includes a film forming process using a plasma CVD method, and the film contains silicon.

US Pat. No. 10,559,471

METHOD OF MANUFACTURING BONDED WAFER

SUMCO CORPORATION, Tokyo...

1. A method of manufacturing a bonded wafer, comprising:a bonding step of bonding a support substrate wafer and an active layer wafer with an insulating film;
a terrace forming step of forming a terrace surface on the support substrate wafer; and
a strain removing step of removing a strained region generated by the terrace forming step,
wherein the terrace forming step is carried out using a chamfering wheel which comprise a low grit number grinding stone and a high grit number grinding stone having a higher grit number than the low grit number grinding stone, and
wherein the terrace forming step comprises:
a coarse chamfering step of chamfering, after chamfering the active layer wafer, the insulating film from the active layer wafer side and further chamfering the support substrate wafer, using the low grit number grinding stone; and
a finish chamfering step of finish chamfering, after the coarse chamfering step, a machined surface obtained from the coarse chamfering step, using the high grit number grinding stone.

US Pat. No. 10,559,470

CAPPING STRUCTURE

GLOBALFOUNDRIES INC., Gr...

1. A structure, comprising:a plurality of gate structures in a first location with a first density;
a plurality of gate structures in a second location with a second density different than the first density; and
a T-shaped capping structure protecting the plurality of gate structures in the first location and in the second location,
wherein the plurality of gate structures in the first location are short gate structures and the plurality of gate structures in the second location are long gate structure and both the long gate structures and the short gate structure are replacement gate structures.

US Pat. No. 10,559,469

DUAL POCKET APPROACH IN PFETS WITH EMBEDDED SI-GE SOURCE/DRAIN

TEXAS INSTRUMENTS INCORPO...

1. A p-type metal-oxide-semiconductor field effect transistor (PFET), comprising:a p-type silicon substrate;
an n-type well formed in the p-type silicon substrate;
a p-type source formed in the n-type well;
a p-type drain formed in the n-type well;
dual pockets formed in the n-type well laterally between the source and drain, the dual pockets comprising a first pocket with first arsenic n-type dopants and a second pocket with second arsenic n-type dopants;
a first p-type lightly-doped drain (LDD) coupled to the source and on the first and second pockets;
a second p-type LDD coupled to the drain and on the first and second pockets, wherein the first pocket is directly below the first LDD and the second LDD, the second pocket is below the first pocket, the first pocket has a higher arsenic n-type doping concentration than the second pocket, and both the first pocket and the second pocket have a higher n-type doping concentration than the n-type well;
a gate oxide layer formed on the n-type well; and
a gate formed on the gate oxide layer.

US Pat. No. 10,559,468

CAPPED ALD FILMS FOR DOPING FIN-SHAPED CHANNEL REGIONS OF 3-D IC TRANSISTORS

Lam Research Corporation,...

1. A method of doping a channel region of a partially fabricated transistor on a semiconductor substrate, the method comprising:(a) forming a dopant-containing film on the semiconductor substrate, wherein multiple dopant-containing layers of the dopant-containing film are formed by an atomic layer deposition process comprising:
(i) adsorbing a dopant-containing film precursor onto the semiconductor substrate such that the dopant-containing film precursor forms an adsorption-limited layer on the semiconductor substrate;
(ii) removing at least some unadsorbed dopant-containing film precursor from a volume surrounding the adsorbed dopant-containing film precursor;
(iii) reacting the adsorbed dopant-containing film precursor, after removing the at least some unadsorbed dopant-containing film precursor in (ii), to form a dopant-containing layer on the semiconductor substrate;
(iv) removing desorbed dopant-containing film precursor or reaction by-product or desorbed dopant-containing film precursor and reaction by-product from the volume surrounding the dopant-containing layer when present after reacting the adsorbed film precursor; and
(v) repeating (i) through (iv) to form the multiple dopant-containing layers of the dopant-containing film;
(b) forming a capping film at a temperature between about 20° C. and about 450° C. using atomic layer deposition, the capping film comprising a silicon carbide material, the capping film located such that the dopant-containing film formed in (a) is located in between the semiconductor substrate and the capping film, wherein the capping film reduces back diffusion of the dopant out of the channel region relative to silicon dioxide as a capping film; and
(c) driving the dopant from the dopant-containing film into the channel region.

US Pat. No. 10,559,467

SELECTIVE GAS ETCHING FOR SELF-ALIGNED PATTERN TRANSFER

INTERNATIONAL BUSINESS MA...

1. A method for selective gas etching for self-aligned pattern transfer, the method comprising:forming a first block in a common sacrificial layer, the first block comprising a first hardmask material that can be plasma etched using a first gas; and
forming a second block separate from the first block in the common sacrificial layer, the second block comprising a second hardmask material that can be plasma etched using a second gas separate from the first gas;
wherein the first hardmask material is not plasma etched using the second gas, the second hardmask material is not plasma etched using the first gas and the first hard mask and second hardmask cover distinct locations within a given thickness of the common sacrificial layer.

US Pat. No. 10,559,466

METHODS OF FORMING A CHANNEL REGION OF A TRANSISTOR AND METHODS USED IN FORMING A MEMORY ARRAY

Micron Technology, Inc., ...

1. A method of forming a channel region of a transistor, comprising:forming amorphous channel material over a substrate, the amorphous channel material having first and second opposing sides;
forming an insulator material adjacent the second side of the amorphous channel material below a crystallization temperature at and above which the amorphous channel material would become crystalline; and
subjecting the amorphous channel material having the insulator material there-adjacent to a temperature at or above the crystallization temperature to transform the amorphous channel material into crystalline channel material; and
the insulator material being formed directly against the second side of the amorphous channel material.

US Pat. No. 10,559,465

PRE-TREATMENT APPROACH TO IMPROVE CONTINUITY OF ULTRA-THIN AMORPHOUS SILICON FILM ON SILICON OXIDE

APPLIED MATERIALS, INC., ...

1. A method of forming an amorphous silicon layer, comprising:depositing a predetermined thickness of a sacrificial oxide-containing dielectric layer over a substrate positioned in a processing volume;
forming patterned features on the substrate by removing portions of the sacrificial oxide-containing dielectric layer to expose an upper surface of the substrate;
performing a plasma treatment to the patterned features, comprising:
flowing a treatment gas into the processing volume, wherein the treatment gas comprises ammonia, nitrous oxide, or a combination thereof; and
generating a plasma in the processing volume to treat the patterned features of the substrate;
depositing an amorphous silicon layer on the patterned features and the exposed upper surface of the substrate, wherein the amorphous silicon layer has a thickness in a range from about 10 angstroms to about 100 angstroms; and
selectively removing the amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the amorphous silicon layer.

US Pat. No. 10,559,464

METHOD FOR MANUFACTURING PHOTOELECTRIC CONVERSION DEVICE

Canon Kabushiki Kaisha, ...

1. A method for manufacturing a photoelectric conversion device comprising:fixing a first substrate which includes a first semiconductor layer including a photoelectric conversion element, to a second substrate;
thinning the first semiconductor layer after fixing the first substrate to the second substrate;
forming a through hole in the first semiconductor layer after the thinning of the first semiconductor layer;
forming a conductive member in the through hole; and
fixing the first substrate to a third substrate which includes a second semiconductor layer provided with a first transistor such that the first substrate is located between the third substrate and the second substrate after the forming of the conductive member;
wherein, in the step of fixing the first substrate to the second substrate, the first substrate is provided with a second transistor;
wherein the conductive member electrically between the first transistor and the second transistor.

US Pat. No. 10,559,463

MULTI-STATE DEVICE BASED ON ION TRAPPING

International Business Ma...

1. A semiconductor structure comprising:a semiconductor substrate including at least one channel region that is positioned between source/drain regions;
a gate dielectric material located on the channel region of the semiconductor substrate; and
a battery stack located on the gate dielectric material, wherein the battery stack comprises a cathode current collector located on the gate dielectric material, a cathode material located on the cathode current collector, a first ion diffusion barrier material located directly on the cathode material, an electrolyte located directly on the first ion diffusion barrier material, a second ion diffusion barrier material located directly on the electrolyte, an anode region located directly on the second ion diffusion barrier material, and an anode current collector located on the anode region.

US Pat. No. 10,559,462

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM

Kokusai Electric Corporat...

1. A method of manufacturing a semiconductor device, comprising:forming a film containing at least Si, O and N on a substrate in a process chamber by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing:
forming a first layer by supplying a precursor gas containing at least a Si—N bond and a Si—Cl bond and a first catalyst gas to the substrate;
exhausting the precursor gas and the first catalyst gas in the process chamber through an exhaust system;
forming a second layer by supplying an oxidizing gas and a second catalyst gas to the substrate to modify the first layer; and
exhausting the oxidizing gas and the second catalyst gas in the process chamber through the exhaust system.

US Pat. No. 10,559,461

SELECTIVE DEPOSITION WITH ATOMIC LAYER ETCH RESET

LAM RESEARCH CORPORATION,...

1. A method comprising:(a) exposing a substrate housed in a chamber to alternating pulses of a first reactant and a second reactant to deposit a film over the substrate, the substrate having a first substrate material on which deposition of the film is intended and a second substrate material on which deposition of the film is not intended, the second substrate material being different from the first substrate material, and a nucleation delay for the first substrate material being less than a nucleation delay for the second substrate material according to a nucleation delay differential, which degrades upon proceeding with the film deposition; and
(b) exposing the substrate housed in the chamber to alternating pulses of an etching gas and a removal gas to etch a portion of the film deposited in (a) to reset the nucleation delay differential between the first and second substrate materials;
wherein (a) and (b) result in net deposition of the film on the first substrate material.

US Pat. No. 10,559,460

FILM FORMING APPARATUS AND FILM FORMING METHOD

TOKYO ELECTRON LIMITED, ...

1. A film forming apparatus for forming a silicon nitride film on a substrate by having a precursor gas containing silicon to react with a reaction gas containing nitrogen, comprising:a processing container configured to form a vacuum atmosphere;
a substrate mounting part installed in the processing container;
a precursor gas supply part configured to supply a precursor gas containing silicon into the processing container;
a reaction gas supply part configured to supply a reaction gas of a mixture of an ammonia gas and a hydrogen gas into the processing container; and
an ultraviolet irradiating part interposed between the processing container and the reaction gas supply part and configured to excite the reaction gas before the reaction gas reacts with the precursor gas,
wherein the reaction gas is supplied into the processing container via the ultraviolet irradiating part, and
wherein a substrate on the substrate mounting part is not irradiated with an ultraviolet ray emitted from the ultraviolet irradiating part.

US Pat. No. 10,559,459

METHOD FOR PRODUCING SILICON NITRIDE FILM AND SILICON NITRIDE FILM

TAIYO NIPPON SANSO CORPOR...

1. A method for producing a silicon nitride film having the following film properties (a) to (c) on a substrate having a temperature of 250° C. or lower by using an organosilane gas as a raw material gas by a plasma chemical vapor deposition method,wherein a processing gas obtained by adding a hydrogen reducing gas in a range of 200 to 2000 volumetric flow rate to an organosilane gas of 1 volumetric flow rate is used,
a pressure in a process chamber accommodating the substrate is adjusted to be in a range of 35 to 400 Pa, and
a density of high-frequency electric power applied to an electrode installed in the process chamber is adjusted to be in a range of 0.2 to 3.5 W/cm2,
(a) an etching rate by a hydrofluoric acid solution is 10 nm/min or lower,
(b) a formation rate of a silicon oxide while being exposed to a saturated water vapor atmosphere at 208 kPa and 121° C. is 2 nm/hour or lower in terms of a silicon oxide film, and
(c) an internal stress in the film is in the range of ?1000 to 1000 MPa,
wherein the organosilane gas is represented by a formula (R1R2N)nSiH4-n, and wherein R1 and R2 are each independently a hydrocarbon group and n is any one of 2, 3 and 4.

US Pat. No. 10,559,458

METHOD OF FORMING OXYNITRIDE FILM

ASM IP Holding B.V., Alm...

1. A method of forming a nitrogen-incorporated silicon or metal oxide film, comprising steps of:(i) depositing by a plasma a silicon or metal oxide film on a substrate using a precursor containing a silicon or metal and an oxidizing gas, said plasma having a first plasma density; and
(ii) nitriding by a plasma the silicon or metal oxide film using a nitriding gas without using any precursor, said plasma having a second plasma density which is higher than the first plasma density.

US Pat. No. 10,559,457

MASS SPECTROMETER, SYSTEM COMPRISING THE SAME, AND METHODS FOR DETERMINING ISOTOPIC ANATOMY OF COMPOUNDS

CALIFORNIA INSTITUTE OF T...

1. A method for determining the isotopic composition of an analyte in a sample, the method comprising:using a first mass spectrometer comprising a single-collector and having a mass-resolution of about 30,000 or greater to measure ratios of ion beams at each cardinal mass of the analyte to produce first molecular analyte ion data;
using a second mass spectrometer comprising a multi-collector to measure relative abundances of closely-adjacent ions at different cardinal masses of the analyte to produce second molecular analyte ion data;
utilizing the first molecular analyte ion data to identify proportions of isotopologues that contribute to signal intensity at each cardinal mass measured with the second mass spectrometer; and
utilizing the proportions of the isotopologues that contribute to the signal intensity at each cardinal mass to compensate for unresolved detected molecular analyte species and calculate an abundance of one or more isotopic species of interest measured with the second mass spectrometer.

US Pat. No. 10,559,455

MASS SPECTROMETRY PROBES AND SYSTEMS FOR IONIZING A SAMPLE

Purdue Research Foundatio...

1. A method for analyzing a sample, the method comprising:providing a mass spectrometry probe comprising a paper substrate in which a portion of the paper substrate is coated with an electrically conductive material that is not a sample or a solvent, in a manner that a plurality of nanoscale features protrude from the paper substrate, the plurality of nanoscale features configured to act as a plurality of electrodes and upon application of a voltage of 3 volts or less, providing a field strength high enough to cause field emission of microscale solution droplets at the plurality of nanoscale features at a voltage that does not cause fragmentation of the analyte;
connecting the mass spectrometry probe to a voltage source, wherein the voltage source is configured to generate a voltage of 3 volts or less;
contacting the mass spectrometry probe with a sample;
ionizing the sample that has contacted the mass spectrometry probe; and
analyzing the ionized sample in a mass spectrometer.

US Pat. No. 10,559,454

DEVICE FOR MANIPULATING CHARGED PARTICLES

Shimadzu Research Laborat...

1. A device for manipulating charged particles, the device comprising:a series of electrodes arranged so as to form a channel for transportation of the charged particles;
a power supply unit adapted to provide supply voltages to said electrodes so as to create a non-uniform high-frequency electric field within said channel, the pseudopotential of said field having two or more local maxima along the length of said channel for transportation of charged particles, at least within a certain interval of time, wherein transportation of the charged particles along the length of the channel is provided by transposition of the at least two of said maxima of the pseudopotential such that the at least two of said maxima are caused to travel with time along the channel, at least within a certain interval of time and at least within a part of the length of the channel, wherein the supply voltages are high-frequency voltages;
wherein the said channel for transportation of the charged particles contains a gas
wherein the gas pressure defines viscous flow conditions;
wherein the pressure of the gas meets the condition ?/L<0.01, where L is a width of the transport channel and ? is the mean free path of molecules of said viscous gas.

US Pat. No. 10,559,453

TECHNIQUES FOR DETECTING MICRO-ARCING OCCURRING INSIDE A SEMICONDUCTOR PROCESSING CHAMBER

Taiwan Semiconductor Manu...

1. A system for determining micro-arcing in a chamber comprising:a magnetic-field sensor comprising a closed conductive path, wherein the magnetic-field sensor is configured to generate a magnetic-field signal that varies in time commensurate with a time-varying magnetic flux passing through the closed conductive path;
a micro-arc detecting element configured to determine whether a micro-arc has occurred in the chamber based on a magnitude of the magnetic-field signal;
a radio frequency (RF) generator configured to output a RF signal;
a transmission line coupled to the RF generator; and
wherein the transmission line has a central portion that extends laterally along a first plane, and a pair of peripheral portions that extend laterally from the central portion in parallel with a second plane.

US Pat. No. 10,559,452

PLASMA DEVICE DRIVEN BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT

AGC FLAT GLASS NORTH AMER...

1. A plasma source comprising:at least three electrodes, including a first electrode, a second electrode, and a third electrode, the at least three electrodes being arranged linearly such that a first distance between the first electrode and the second electrode is smaller than a second distance between the first electrode and the third electrode; and
a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave, wherein the first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase;
wherein each electrode is electrically connected to the source of power such that the first electrode is electrically connected to the first output wave, the second electrode is electrically connected to the second output wave, and the third electrode is electrically connected to the third output wave;
wherein electrical current flows between the at least three electrodes that are out of electrical phase;
wherein each electrode alternately serves as anode and cathode when powered by the multiple output waves, and
wherein the plasma source is capable of generating a plasma between the electrodes, including a first plasma directly between the first electrode and the second electrode, a second plasma directly between the second electrode and the third electrode, and a third plasma directly between the first electrode and the third electrode.

US Pat. No. 10,559,451

APPARATUS WITH CONCENTRIC PUMPING FOR MULTIPLE PRESSURE REGIMES

Applied Materials, Inc., ...

10. A processing chamber comprising:a chamber body defining a processing region and configured to generate a plasma therein;
a substrate support assembly disposed in the process region; and
an exhaust module comprising:
a body coupled to the chamber body, the body having a first vacuum pump opening and a second vacuum pump opening formed therethrough;
a pumping ring positioned in the body over both the second vacuum pump opening and the vacuum pump opening, the pumping ring comprising:
a substantially ring shaped body, comprising:
a top surface and a bottom surface, the top surface having one or more through holes formed therein, wherein the one or more through holes are arranged in a pattern concentric with the first vacuum pump opening and the bottom surface having a fluid passage formed therein fluidly isolated from the first vacuum pump opening, the fluid passage interconnecting each of the one or more through holes to the second vacuum pump opening; and
an opening formed in the substantially ring shaped body, the opening substantially aligned with the first vacuum pump opening; and
a symmetric flow valve positioned in the body over the pumping ring, the symmetric flow valve movable between a raised position allowing for passage through the opening of the substantially ring shaped body and into the vacuum pump opening and a lowered position substantially sealing the opening of the substantially ring shaped body without sealing the one or more through holes.

US Pat. No. 10,559,450

SCANNING ELECTRON MICROSCOPE

HITACHI HIGH-TECHNOLOGIES...

1. A scanning electron microscope, comprising:an electron source;
a condenser lens and an objective lens respectively for focusing a primary electron beam emitted from the electron source on a specimen;
a plurality of deflectors that deflect the primary electron beam passing the condenser lens;
a detector that detects a signal electron emitted from the specimen by scanning the primary electron beam to the specimen; and
a processor that controls the electron source, the condenser lens, the objective lens and the plurality of deflectors,
wherein the processor is configured to execute a sequence of stored instructions which cause said processor to perform a first deflection field setting operation that sets the plurality of deflectors so as to move a scanning area on the specimen by the primary electron beam to a position deviated from an axis extended from the electron source toward the center of the objective lens and a second deflection field setting operation that sets the plurality of deflectors so as to correct trajectories of signal electrons without changing the scanning area of the primary electron beam set by the first deflection field setting operation; and
the processor controls the plurality of deflectors by adding a setting value set by the second deflection field setting operation to a setting value set by the first deflection field setting operation.

US Pat. No. 10,559,449

STABLE SUPPORT FILMS FOR ELECTRON MICROSCOPY

The Regents of the Univer...

10. A method comprising:(a) providing an electron microscopy grid, the electron microscopy grid comprising a first surface and a second surface, the first surface having a holey carbon film disposed thereon;
(b) providing a plurality of lipid molecules, each lipid molecule of the plurality of lipid molecules having a hydrophilic head and a hydrophobic tail;
(c) contacting the holey carbon film with hydrophobic tails of the plurality of lipid molecules to form a lipid monolayer disposed in a hole in the holey carbon film, the lipid monolayer comprising a portion of the plurality of lipid molecules;
(d) after operation (c), attaching a biotin-binding protein to hydrophilic heads of the lipid monolayer; and
(e) after operation (d), allowing a period of time to elapse to allow the biotin-binding protein to crystalize while being attached to the hydrophilic heads of the lipid monolayer disposed in the hole in the holey carbon film.

US Pat. No. 10,559,448

TRANSMISSION CHARGED PARTICLE MICROSCOPE WITH IMPROVED EELS/EFTEM MODULE

FEI Company, Hillsboro, ...

1. A method of using a Transmission Charged Particle Microscope comprising:n imaging system, for receiving a flux of charged particles transmitted through a specimen and directing the flux of charged particles after passing through the specimen onto a sensing device;
a controller, for controlling at least some operational aspects of the microscope,in which method the sensing device is chosen to be an EELS/EFTEM module comprising:an entrance plane;
an image plane, where in EELS mode an EELS spectrum is formed and in EFTEM mode an EFTEM image is formed;
a slit plane between said entrance plane and said image plane, where in EFTEM mode an energy dispersed focus is formed;
a dispersing device, between said entrance plane and said slit plane, for dispersing an incoming charged particle beam into an energy-dispersed beam with an associated dispersion direction;
a first series of quadrupoles between said dispersing device and slit plane;
a second series of quadrupoles between said slit plane and image plane,which dispersing device and quadrupoles are arranged along an optical axis,whereby, for a Cartesian coordinate system (X,Y,Z) in which said optical axis is disposed along Z, said dispersion direction is defined as being parallel to X,wherein:in said first quadrupole series, exciting one or more quadrupoles so as to deflect an off-axis non-dispersive YZ ray leaving said dispersing device onto a path paraxial to said optical axis from said slit plane to said image plane; and
in said second quadrupole series, exciting either:
(a) a single quadrupole; or
(b) a pair of adjacent quadrupoles,
so as to focus said energy-dispersed beam onto said image plane.

US Pat. No. 10,559,447

CHARGED PARTICLE BEAM DEVICE WITH TRANSIENT SIGNAL CORRECTION DURING BEAM BLANKING

HITACHI HIGH-TECHNOLOGIES...

1. A charged particle beam apparatus comprising:a charged particle source unit that launches a charged particle beam;
a blanking electrode unit that blanks the charged particle beam launched from the charged particle source unit;
a deflecting electrode unit that deflects the charged particle beam launched from the charged particle source unit and passing through the blanking electrode unit;
an objective lens unit that converges the charged particle beam deflected by the deflecting electrode unit and radiates the charged particle beam to a surface of a sample;
a secondary charged particle detection unit that detects a secondary charged particle generated from the sample irradiated with the charged particle beam;
a signal processing unit that processes a signal obtained by detecting the secondary charged particle by the secondary charged particle detection unit;
a control unit that controls the charged particle source unit, the blanking electrode unit, the deflecting electrode unit, the objective lens unit, the secondary charged particle detection unit, and the signal processing unit; and
a storage unit which stores a correction value,
wherein the control unit includes a transient signal correction unit that corrects a transient signal at the time of turning off the blanking of the charged particle beam by the blanking electrode by adding the uncorrected original deflecting signal and a blanking correction signal, based on the correction value at a timing at which the blanking signal output is switched, to the deflecting electrode,
wherein the stored correction value comprises a scanning direction on the sample, a predetermined magnification correction coefficient and a predetermined measurement magnification value,
wherein the transient signal correction unit is a discharge circuit that discharges a charge remaining in the blanking electrode when the blanking of the charged particle beam is turned off by the blanking electrode, and
wherein said discharge circuit comprises a switch electrically coupled between the blanking electrode and an output of an amplifier, said output is electrically connected in parallel with a diode electrically connected to ground, said switch being configured to receive a signal for turning off blanking from the blanking electrode unit to close a contact point and a signal for turning on blanking from the blanking electrode unit to open the contact point.

US Pat. No. 10,559,446

VACUUM CLOSED TUBE AND X-RAY SOURCE INCLUDING THE SAME

Electronics and Telecommu...

1. An X-ray source comprising:a high voltage connection module, a tube module, and a magnetic lens system into which the tube module is inserted, wherein
the tube module includes a vacuum closed tube, and the vacuum closed tube includes:
a cathode electrode provided at one end thereof;
an emitter on the cathode electrode;
an anode electrode provided at the other end;
a first insulation spacer provided between the cathode electrode and the anode electrode;
a first conductive tube and a second conductive tube both provided between the cathode electrode and the anode electrode and separated from each other by the first insulation spacer; and
a first collimator block covering an inner surface of the first insulation spacer and having a first opening.

US Pat. No. 10,559,445

PHOTOELECTRIC SURFACE, PHOTOELECTRIC CONVERSION TUBE, IMAGE INTENSIFIER, AND PHOTOMULTIPLIER TUBE

HAMAMATSU PHOTONICS K.K.,...

1. A photoelectric surface having a laminated structure, the photoelectric surface comprising:a window material that transmits ultraviolet rays;
a conductive film that is formed on the window material and has conductivity;
an intermediate film that is formed on the conductive film and includes a compound of magnesium and fluorine; and
a photoelectric conversion film that is formed on the intermediate film and includes tellurium and an alkali metal, wherein the photoelectric conversion film receives light that has passed through the window material, the conductive film, and the intermediate film, in order, and generates photoelectrons,
wherein the intermediate film has a thickness selected from the range of 0.5 nm to 5.0 nm based on a wavelength of the ultraviolet rays and to cause the photoelectrons generated by the photoelectric conversion film to have a guantum efficiency of 20% or more relative to the ultraviolet rays transmitted by the window material.

US Pat. No. 10,559,444

FUSE DEVICE HAVING PHASE CHANGE MATERIAL

LITTELFUSE, INC., Chicag...

1. A resettable fuse device, comprising:a fuse component;
a first electrode, disposed on a first side of the fuse component;
a second electrode, disposed on a second side of the fuse component; and
a phase change component, disposed in thermal contact with the fuse component,
wherein the fuse component comprises a fuse temperature;
wherein the phase change component exhibits a phase change temperature, the phase change temperature marking a phase transition of the phase change component,
wherein the phase change temperature is less than the fuse temperature, and wherein the phase change component is disposed between the first electrode and the second electrode.

US Pat. No. 10,559,443

LIQUID DIELECTRIC ELECTROSTATIC MEMS SWITCH AND METHOD OF FABRICATION THEREOF

KING ABDULLAH UNIVERSITY ...

1. A microelectromechanical system switch comprising:a cantilevered source switch;
a first actuation gate disposed parallel to the cantilevered source switch;
a first drain disposed parallel to a movable end of the cantilevered source switch; and
a liquid dielectric material disposed within a housing of the microelectromechanical system switch.

US Pat. No. 10,559,442

RELAY

OMRON CORPORATION, Kyoto...

1. A relay comprising:a movable contact terminal;
a contact piece that is attached to the movable contact terminal, and includes a first divided piece and a second divided piece extending in a lengthwise direction and divided from each other;
a first movable contact attached to the first divided piece;
a second movable contact attached to the second divided piece;
a fixed contact terminal disposed at a position facing the contact piece;
a first fixed contact attached to the fixed contact terminal and disposed at a position facing the first movable contact;
a second fixed contact attached to the fixed contact terminal and disposed at a position facing the second movable contact; and
a link member capable of pressing the contact piece, wherein
at a time of contact between the contacts, the first movable contact comes into contact with the first fixed contact before the second movable contact comes into contact with the second fixed contact,
the first movable contact is located on a leading end side of the contact piece with respect to the second movable contact,
the first divided piece includes
a body that extends in the lengthwise direction, and
a projection that projects in a widthwise direction of the first divided piece from the body, and
the projection includes a contact portion pressed by the link member.

US Pat. No. 10,559,441

FORCE SWITCH

Ethicon-Endo Surgery, Inc...

1. A method of creating a switch to be disposed along a longitudinal axis of a device, comprising:providing a hollow body defining an interior cavity;
disposing a switching element movably within the interior cavity to define:
a switch-making position along a switching axis of the switching element; and
a switch-breaking position along the switching axis of the switching element;
disposing a biasing element about the switching element to impart a biasing force to the switching element to place the switching element in one of the switch-making position and the switch-breaking position until an external force imparted to the switching element exceeds the biasing force to thereby cause the switching element to change to the other of the switch-making position and the switch-breaking position;
disposing a biasing force-adjusting element in cooperative engagement with the biasing element such that a magnitude of the biasing force is adjustable using the biasing force-adjusting element; and
coupling an electrically-conductive contact to the switching element to define:
a switch-making state when the switching element is in the switch-making position; and
a switch-breaking state when the switching element is in the switch-breaking position.

US Pat. No. 10,559,440

SWITCH MECHANISM FOR A VEHICLE INTERIOR COMPONENT

Shanghai Yanfeng Jinqiao ...

1. A switch mechanism for a vehicle interior component comprising:(a) a carrier;
(b) a slide configured to slide within the carrier;
(c) at least one pin configured to move within the slide to center the slide in the carrier; and
(d) a spring configured to move the at least one pin within the slide;
wherein the at least one pin comprises a feature configured to guide movement of the at least one pin relative to the slide;
wherein the feature comprises a protrusion configured to move against the slide to guide movement of the at least one pin relative to the slide;
wherein the slide comprises a rib;
wherein the protrusion is configured to slide against the rib to guide movement of the at least one pin relative to the slide;
wherein the carrier comprises a surface;
wherein the at least one pin is configured to slide against the surface of the carrier;
wherein the rib extends from the slide away from the surface of the carrier.

US Pat. No. 10,559,439

ROCKER SWITCH DEVICE

KABUSHIKI KAISHA TOKAI RI...

1. A rocker switch device, comprising:a hollow operation knob;
a body configured such that current is interruptible by the operation knob and a support portion that projects toward an inside of the operation knob and supports the operation knob in a manner allowing for rocking;
a shaft portion that projects toward and engages a shaft bearing portion, the shaft portion projecting from one of the support portion and the operation knob, the shaft bearing portion being formed on the other of the support portion and the operation knob; and
a projection portion that projects from one of a surface of the support portion of the body that is opposite an interior surface of the operation knob and an interior surface of the operation knob that is opposite a surface of the support portion of the body,
wherein the projection portion is formed separate from the shaft portion, and
wherein the projection portion is formed outside the shaft portion in a rocking axis direction of the operation knob and extends in a vertical direction of the support portion.

US Pat. No. 10,559,438

TOGGLE SWITCH ACTUATING MECHANISM

Honeywell International I...

1. A toggle switch comprising:a housing;
a plurality of switches disposed within the housing;
an actuating lever coupled to a pivot pin, wherein the actuating lever extends into the housing; and
an actuator assembly coupled to the actuating lever, the actuator assembly comprising:
an actuation pin coupled to the actuating lever, wherein the actuation pin is configured to actuate one or more of the plurality of switches, and
a spring disposed about an outer surface of the actuating lever, wherein the spring is configured to bias a cam follower into engagement with a cam profile on a bracket, and bias the actuating lever into an actuation position,
wherein the cam follower comprises a roller disposed about a pin, wherein the pin is configured to travel within a longitudinal travel slot disposed in the actuating lever.

US Pat. No. 10,559,437

MEMBRANE SWITCH DEVICE AND KEYBOARD DEVICE

Chicony Electronics Co., ...

1. A membrane switch device, comprising:a first membrane layer comprising a first surface, a first side edge, and a plurality of first conductive wires, wherein the first surface has a first outlet area, the first outlet area has a first no-wire area and a first wire area, the first conductive wires are on the first surface and extending to the first wire area to form a plurality of first contact pads;
a second membrane layer comprising a second surface, a second side edge, and a plurality of second conductive wires, wherein the second surface has a second outlet area, the second outlet area has a second no-wire area and a second wire area, the second conductive wires are on the second surface and extending to the second wire area to form a plurality of second contact pads;
a spacing layer between the first membrane layer and the second membrane layer; and
a flexible printed circuit board comprising a wire-connecting end, a plurality of first electrical lines, a plurality of second electrical lines, a first protection layer, a second protection layer, a first connection surface, and a second connection surface opposite to the first connection surface, wherein the first electrical lines are on the first connection surface and extending to the wire-connecting end to form a plurality of first connecting terminals, the first protection layer covers the first electrical lines to expose the first connecting terminals, the second electrical lines are on the second connection surface and extending to the wire-connecting end to form a plurality of second connecting terminals, the second protection layer covers the second electrical lines to expose the second connecting terminals;
wherein the wire-connecting end of the flexible printed circuit board is between the first outlet area of the first membrane layer and the second outlet area of the second membrane layer, the first connecting terminals are electrically connected to the first contact pads, correspondingly, the second connecting terminals are electrically connected to the second contact pads, correspondingly;
wherein the first protection layer and the first contact pads are not overlapped with each other, and the second protection layer and the second contact pads are not overlapped with each other.

US Pat. No. 10,559,436

KEYFRAME MODULE FOR AN INPUT DEVICE

Logitech Europe S.A., La...

1. An input device comprising:a keyframe having a key opening, wherein the keyframe is configured to receive a key within the key opening, the key having a plurality of tabs that extend laterally from a bottom surface of the key; and
a plate coupled to the keyframe, the plate having a top surface and an opening disposed therein,
wherein a location of the opening within the plate is in alignment with a location of the plurality of tabs of the key such that one or more of the plurality of tabs pass through the opening within the plate and below a top surface of the plate in response to a depression of the key, and
wherein the opening and the location of the plurality of tabs are vertically aligned along a path defined by the depression of the key.

US Pat. No. 10,559,435

SWITCH

Omron Corporation, Kyoto...

1. A switch, comprising:a housing including an internal compartment;
a stationary contact terminal extending from outside the housing to the compartment and fixed to the housing, and including a fixed portion housed in the compartment;
a moving contact terminal extending from outside the housing to the compartment, and being parallel to the stationary contact terminal, the moving contact terminal being fixed to the housing in a manner electrically independent of the stationary contact terminal;
a moving contact unit housed in the compartment, and including a body connected to the moving contact terminal and extending from the moving contact terminal toward the stationary contact terminal, a moving portion included in the body and facing the fixed portion and being movable toward and away from the fixed portion, and an urging member included in the body and being configured to urge the moving portion in an urging direction switchable between a closing direction for moving the moving portion toward the fixed portion and a separating direction for moving the moving portion away from the fixed portion;
an operating unit at least partly exposed outside the housing, and at least partly housed in the compartment to come in contact with and reciprocate with respect to the moving contact unit, the operating unit being configured to switch the urging direction in accordance with reciprocation of the operating unit to move the moving portion toward or away from the fixed portion;
a first elastic unit fixed to the housing, and configured to come in contact with the moving contact unit and elastically deform in the separating direction when the moving portion moves away from the fixed portion under an urging force of the urging member;
a second elastic unit including a contact point located between the moving portion and the fixed portion facing the moving portion in the closing direction and being configured to come in contact with the moving portion, the second elastic unit being fixed to the stationary contact terminal or the moving contact terminal and being configured to elastically deform in the closing direction and electrically connect the stationary contact terminal and the moving contact terminal when the moving portion moves toward the fixed portion under the urging force of the urging member and comes in contact with the contact point, and
a third elastic unit located near the second elastic unit in the compartment, the third elastic unit including an elastic protrusion located between the fixed portion and the contact point in the closing direction and being configured to come in contact with the contact point, and an elastic arm located between the moving portion and the contact point in the closing direction and being configured to come in contact with the moving portion.

US Pat. No. 10,559,434

CONTROL CIRCUIT FOR ELECTRIC LEAKAGE CIRCUIT BREAKER

LSIS CO., LTD., Anyang-s...

1. A control circuit for an electric leakage circuit breaker, comprising:a zero phase current transformer configured to detect a zero phase current on a circuit as a leakage detection signal;
a filter circuit section configured to remove a high frequency noise included in the leakage detection signal;
an input amplifier configured to amplify a voltage formed by a current of the leakage detection signal and an impedance of the filter circuit section, and including a pair of transistors, bases of the transistors connected to both output terminals of the filter circuit section, respectively;
a base current generator commonly connected to the bases of the pair of transistors and configured to supply the same amount of base current to the pair of transistors;
a trip determination circuit section configured to determine whether to output a trip control signal by comparing a voltage value of an amplified leakage detection signal outputted from the input amplifier with a preset reference voltage value, and
a gain adjuster, connected to the base current generator, configured to adjust the gain of a collector current of the pair of transistors over the base current by adjusting the base current supplied to the bases of the pair of transistors.

US Pat. No. 10,559,433

SWITCHING APPARATUS FOR SYNCHRONIZED TOGGLE POSITIONING AND RELATED SENSORY FEEDBACK

SWITCHDOWN LLC, Durham, ...

9. A system of controlling energization of an electrical load using multiple switch devices, said system comprising:a plurality of switch devices, each said switch device including
a toggle element movable between a first position and a second position, said toggle element including a magnetic element affixed thereto;
an electromagnetic element being selectively energized and fixed in position relative to said toggle element;
a sensor creating a signal indicative of said toggle element passing a position midway between said first position and said second position;
a communications wire for distributing said signal among said plurality of switches; and
a microprocessor controlling said electromagnetic element to selectively attract or repel each said magnetic element in each of said plurality of switches simultaneously in response to said signal thereby creating sensory feedback to a user of said system;
wherein said plurality of switches are connected via said communications wire.

US Pat. No. 10,559,432

ELECTROLYTIC CAPACITOR AND MANUFACTURING METHOD THEREFOR

Panasonic Intellectual Pr...

1. An electrolytic capacitor comprising a capacitor element, the capacitor element having:an anode member having a dielectric layer thereon; and
a cathode member including a conductive polymer layer that is in direct contact with the dielectric layer,
wherein the capacitor element is impregnated with a liquid containing at least one of polyalkylene glycol and derivatives selected from a group consisting of polyethylene glycol glyceryl ether, polyethylene glycol diglyceryl ether, polyethylene glycol sorbitol ether, polypropylene glycol glyceryl ether, polypropylene glycol diglyceryl ether, polypropylene glycol sorbitol ether, copolymers of ethylene glycol and propylene glycol, copolymers of ethylene glycol and butylene glycol, and copolymers of propylene glycol and butylene glycol.

US Pat. No. 10,559,431

HIGH VOLTAGE WINDOW ELECTROLYTE FOR SUPERCAPACITORS

UT-BATTELLE, LLC, Oak Ri...

1. A supercapacitor, comprising:a negative electrode comprising carbon black and sodium carboxymethyl cellulose which does not intercalate sodium;
a positive carbon-comprising electrode;
an electrolyte composition comprising sodium hexafluorophosphate and a non-aqueous solvent comprising at least one selected from the group consisting of ethylene glycol dimethyl ether, diethylene glycol dimethyl ether, triethylene glycol dimethyl ether, and tetraethylene glycol dimethyl ether;
wherein the supercapacitor has an electrochemical voltage window of from +0.0 V to 3.5 V (full cell voltage).

US Pat. No. 10,559,430

POWER STORAGE MODULE

AutoNetworks Technologies...

1. An electricity storage module comprising:an electricity storage element group composed of a plurality of electricity storage elements having exhaust ports that discharge gas produced therein, each of the exhaust ports having a constant diameter so as to be continuously open; and
a cover attached to the electricity storage element group,
wherein the electricity storage element group has exhaust surfaces on which the exhaust ports are arranged, and the cover is attached so as to cover the exhaust surfaces,
guide portions that surround the exhaust ports in the form of loops are respectively formed integrally on the exhaust surfaces of the plurality of electricity storage elements,
guided portions that come into close contact with the guide portions are formed integrally on an opposing surface of the cover that opposes the exhaust surfaces, and
the cover is provided with a duct that communicates with the exhaust ports and through which gas discharged from the exhaust ports passes.

US Pat. No. 10,559,429

PHOTOSENSITIVE ORGANIC CAPACITOR

1. A photosensitive organic capacitor comprising: an upper substrate and a lower substrate that are spaced apart by a certain interval; an upper electrode and a lower electrode that are attached to each opposing side of the upper substrate and lower substrate; an active layer that is formed between the upper electrode and the lower electrode; and an upper polarization-inducing layer and a lower polarization-inducing layer that are formed between the upper electrode and the active layer and between the lower electrode and the active layer, and induce polarization of charges within the active layer if light is applied, wherein the upper and lower polarization-inducing layers include poly-3-hexylthiophene (P3HT) and, the active layer includes tris(8-hydroxyquinoline-5-sulfonic acid) aluminum (ALQSA3) and wherein the photosensitive organic capacitor accumulates negative charges near a boundary between the upper polarization-inducing layer and the active layer and positive charges near a boundary between the active layer and the lower polarization-inducing layer, if positive power is applied to the upper electrode and negative power is applied to the lower electrode in a dark condition, where light is not applied to the photosensitive organic capacitor.

US Pat. No. 10,559,428

MULTILAYER CERAMIC ELECTRONIC COMPONENT AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic electronic component comprising:a ceramic body including dielectric layers and internal electrodes stacked to be alternately exposed to a first end surface and a second end surface of the ceramic body with respective dielectric layers interposed therebetween; and
external electrodes disposed on external surfaces of the ceramic body,
wherein the external electrodes include seed layers disposed on at least one surface of the ceramic body in a thickness direction, first electrode layers electrically connected to the internal electrodes and the seed layers, and plating layers disposed on the seed layers and the first electrode layers, respectively,
0.8?T2/T1?1.2, where T1 is a thickness of each of the first electrode layers in a central region of the ceramic body in the thickness direction, and T2 is a thickness of each of the first electrode layers at a point at which an outermost internal electrode, among the internal electrodes, is positioned, and
the first electrode layers are connected to the seed layers in contact portions between the at least one surface of the ceramic body in the thickness direction and the at least one surface of the ceramic body in a length direction,
wherein the first electrode layers and the seed layers directly contact each other without a gap.

US Pat. No. 10,559,427

CERAMIC ELECTRONIC COMPONENT AND MOUNT STRUCTURE THEREFOR

MURATA MANUFACTURING CO.,...

1. A ceramic electronic component comprising:an element body including a first main surface and a second main surface that are opposed to one another;
an electronic component body including a first outer electrode provided on the element body, and a second outer electrode provided on the element body;
a first metal terminal connected to the first outer electrode and defined by a lead wire;
a second metal terminal connected to the second outer electrode and defined by a lead wire; and
an outer resin material that covers the electronic component body, the first and second outer electrodes, a portion of the first metal terminal, and a portion of the second metal terminal; wherein
the second main surface of the element body is located on a side near a mounting surface of a mounting substrate on which the ceramic electronic component is to be mounted;
the first metal terminal includes:
a first terminal joint portion that is connected to the first outer electrode;
a first extension portion that is connected to the first terminal joint portion and that defines a gap between the electronic component body and the mounting surface of the mounting substrate; and
a first mount portion that is connected to the first extension portion and that extends toward a side opposite to the electronic component body;
the second metal terminal includes:
a second terminal joint portion that is connected to the second outer electrode;
a second extension portion that is connected to the second terminal joint portion and that defines a gap between the electronic component body and the mounting surface of the mounting substrate; and
a second mount portion that is connected to the second extension portion and that extends toward a side opposite to the electronic component body;
the outer resin material includes a protruding portion that protrudes toward the mounting surface of the mounting substrate;
the first mount portion includes a first protruding bending portion that protrudes toward the mounting surface of the mounting substrate;
the second mount portion includes a second protruding bending portion that protrudes toward the mounting surface of the mounting substrate; and
vertices of the first protruding bending portion, the second protruding bending portion, and the protruding portion are in contact with the mounting surface of the mounting substrate.

US Pat. No. 10,559,426

ELECTRONIC DEVICE HAVING CERAMIC ELEMENT BODY AND EXTERNAL TERMINAL

TDK CORPORATION, Tokyo (...

1. An electronic device, comprising:a chip component including a terminal electrode formed on an end surface of a ceramic element body containing an internal electrode; and
an external terminal including a first end electrically connected with the terminal electrode and a second end disposed opposite to the first end and connected with a mounting surface,
wherein:
the external terminal comprises:
a first metal; and
a second metal different from the first metal;
the first metal and the second metal are arranged next to each other in a surface direction of the external terminal and alternately exposed on a surface of the external terminal; and
a width of the second metal exposed to the surface of the external terminal is 1/10 to 9/10 of the width of the terminal electrode.

US Pat. No. 10,559,425

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor comprising:a capacitor body having first and second surfaces opposing each other and third and fourth surfaces connected to the first and second surfaces and opposing each other, and including an active region including dielectric layers and pluralities of first and second internal electrodes alternately disposed to overlap each other in a stacking direction with respective dielectric layers interposed therebetween and first and second cover regions disposed on opposite surfaces of the active region, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively;
third and fourth internal electrodes alternately disposed to overlap each other in the stacking direction in the first cover region adjacent to the first surface with respective dielectric layers interposed therebetween;
first and second external electrodes including first and second connected portions respectively formed on the third and fourth surfaces of the capacitor body and respectively connected to the first and second internal electrodes and first and second band portions respectively extending from the first and second connected portions to portions of the first surface of the capacitor body;
a third external electrode disposed on the first surface of the capacitor body to be spaced apart from the first band portion;
a fourth external electrode disposed on the first surface of the capacitor body to be spaced apart from the second band portion;
a first via electrode penetrating through the first cover region to connect the third internal electrode and the third external electrode to each other; and
a second via electrode penetrating through the first cover region to connect the fourth internal electrode and the fourth external electrode to each other,
wherein the first surface is a mounting surface.

US Pat. No. 10,559,424

MULTILAYER CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer capacitor:a capacitor body having first and second surfaces opposing each other and third and fourth surfaces connected to the first and second surfaces and opposing each other, and including an active region including dielectric layers and pluralities of first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween and first and second cover regions disposed on opposite surfaces of the active region, the first and second internal electrodes being exposed through the third and fourth surfaces, respectively;
third and fourth internal electrodes alternately disposed in the first cover region adjacent to the first surface with respective dielectric layers interposed therebetween;
first and second external electrodes including first and second connected portions respectively formed on the third and fourth surfaces of the capacitor body and respectively connected to the first and second internal electrodes, and first and second band portions respectively extending from the first and second connected portions to portions of the first surface of the capacitor body;
a first via electrode penetrating through the first cover region to connect the third internal electrode and the first band portion to each other; and
a second via electrode penetrating through the first cover region to connect the fourth internal electrode and the second band portion to each other,
wherein the first surface is a mounting surface,
the third internal electrode contacts only the first via electrode, from among the first and second via electrodes and first and second external electrodes, and
the fourth internal electrode contacts only the second via electrode, from among the first and second via electrodes and first and second external electrodes.

US Pat. No. 10,559,423

MULTILAYER CERAMIC ELECTRONIC DEVICE

TDK CORPORATION, Tokyo (...

7. A multilayer ceramic electronic device comprising a laminated body having alternately laminated internal electrode layers and dielectric layers, whereineach of the dielectric layers has a thickness of 0.5 ?m or less,
each of the internal electrode layers contains ceramic particles,
a content ratio of the ceramic particles contained in the each of the internal electrode layers is 2 to 15% by representation of cross sectional area, and
the each of the dielectric layers has a thickness standard deviation (?) of 100 nm or less.

US Pat. No. 10,559,422

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME USING TREATMENT WITH NITROGEN AND HYDROGEN

SK hynix Inc., Icheon-si...

1. A method for fabricating an electronic device including a semiconductor memory, comprising:forming a variable resistance element over a substrate, the variable resistance element including a metal-containing layer and an MTJ (Magnetic Tunnel Junction) structure which is located over the metal-containing layer and includes a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer;
forming an initial spacer containing a metal over the variable resistance element;
performing an oxidation process to transform the initial spacer into a middle spacer including an insulating metal oxide; and
performing a treatment using a gas or plasma including nitrogen and hydrogen to transform the middle spacer produced by the oxidation process into a final spacer including an insulating metal nitride or an insulating metal oxynitride.

US Pat. No. 10,559,421

STEP-UP BIPOLAR TRANSFORMER RECTIFIER WITHOUT COMMON MODE RIPPLE

The Boeing Company, Chic...

1. A multi-phase transformer comprising:a single rectifier; and
a plurality of groups of windings connected to the single rectifier, wherein each one of the groups of windings comprises:
a corresponding plurality of primary windings having a first output voltage;
a corresponding plurality of secondary windings joined in series to the corresponding plurality of primary windings and having a second output voltage; and
a corresponding plurality of tertiary windings joined in series to the corresponding plurality of secondary windings and having a third output voltage that is higher than the second output voltage;
wherein each end of a primary winding of the corresponding plurality of primary windings is coupled to an end of another primary winding to form a delta configuration and a junction at each coupling that interconnects at least one secondary winding of the corresponding plurality of secondary windings.

US Pat. No. 10,559,420

TRANSFORMER AND METHOD FOR RETROFITTING A TRANSFORMER

Siemens Aktiengesellschaf...

1. A transformer comprising:a magnetic core including at least one limb having a winding arrangement and a yoke;
a compensation winding arrangement disposed on the yoke, said compensation winding arrangement compensating for a unidirectional flux component flowing in the at least one limb;
wherein the compensation winding arrangement includes at least one compensation winding which is formed from a plurality of conductor loops;
wherein each conductor loop of the plurality of conductor loops includes a plurality of wire sections extending in a direction of the yoke and oriented toward one another; and
wherein a first corresponding wire pair is interconnected and a second corresponding wire pair is extended to terminal contacts which are provided for a connection to an assigned current control device.

US Pat. No. 10,559,419

INDUCTOR ARRANGEMENT

1. An inductor arrangement, comprising:a first inductor structure comprising one or more inductors at least partially on a first layer; and
a second inductor structure comprising one or more inductors at least partially on a second layer; wherein
the inductors are arranged such that currents induced by an external magnetic field are substantially cancelled in at least one of the first inductor structure and the second inductor structure; and
the, or each, inductor of the second inductor structure overlaps, at least partially, the, or each, inductor of the first inductor structure.

US Pat. No. 10,559,418

INVERTER STRUCTURE AND METHOD FOR ASSEMBLING THE SAME

P-DUKE TECHNOLOGY CO., LT...

1. An inverter structure (1), comprising:a bobbin set (10) including a bobbin (11) and a coil set (12) winding around the bobbin (11), the bobbin (11) including a through hole (110);
a first iron core (20) including a first core pillar (21), the first iron core (20) being inserted through one side of the bobbin (11), the first core pillar (21) being received in the through hole (110);
a first insulation body (30), the first insulation body (30) being disposed in the through hole (110) and being in contact with one side of the first core pillar (21);
a single-piece middle iron core (40), the middle iron core (40) being disposed in the through hole (110) and being in contact with the first insulation body (30);
a second insulation body (50), the second insulation body (50) being disposed in the through hole (110) and being in contact with another side of the middle iron core (40) opposite to the first insulation body (30); and
a second iron core (60) including a second core pillar (61), the second iron core (60) being inserted through another side of the bobbin (11) opposite to the first iron core (20), the second core pillar (61) being received in the through hole (110) and being in contact with the second insulation body (50);
wherein lengths of the first core pillar and the second core pillar along an extension direction of the through hole are equal or greater than a length of the middle iron core, such that the first insulation body and the second insulation body are disposed closer to a center of the through hole, and magnetic fields formed by the first core pillar, the middle iron core and the second core pillar do not affect the external bobbin set, thereby avoiding magnetic interference and reducing a magnetic loss.

US Pat. No. 10,559,417

COIL COMPONENT

TDK CORPORATION, Tokyo (...

1. A coil component comprising:a board;
a coil provided on and in direct contact with a main surface of the board and having a seed part disposed on the main surface of the board and a plating part formed by plating growth on the seed part and on the main surface of the board;
a resin body provided on the main surface of the board and having a plurality of resin walls between which winding part of the coil extends;
an insulator layer provided on the resin body to sandwich the resin body between the insulator layer and the main surface of the board;
a junction layer provided between and in contact with the insulator layer and the resin body; and
a covering resin composed of a magnetic powder-containing resin and configured to integrally cover the coil and the resin body of the main surface of the board,
wherein the board, the coil, the resin body, and the covering resin constitute a body section,
wherein the body section has two end faces separated and facing each other in a direction parallel to the board, and two side faces separated and facing each other in a direction parallel to the board; the board extends up to both end faces and both side faces; and the covering resin is provided on the board and in outer peripheral areas of the board beyond both the winding part of the coil and the resin walls of the resin body,
wherein each of a pair of neighboring resin walls and the seed part between the pair of resin walls are separated by a predetermined distance, and the seed part between the pair of resin walls is formed at least at a middle position between the pair of neighboring resin walls,
wherein, among the plurality of resin walls arranged on the main surface of the board, the resin wall located innermost is thicker than the resin wall adjacent thereto, and
wherein the predetermined distance is larger than a thickness, in a direction in which the pair of resin walls are separated by the predetermined distance, of the adjacent resin wall, and larger than a width of the seed part in the direction.

US Pat. No. 10,559,416

ELECTRICAL DEVICE WITH REINFORCED MOLDED PINS

XFMRS, Inc., Camby, IN (...

1. An electronic device comprising:a molded frame including a central winding bobbin and first and second lateral supports extending laterally outward therefrom, each of the first and second lateral supports including a top surface and first and second lower surfaces;
at least one magnetic element disposed around the central winding bobbin and supported on the top surfaces of the first and second lateral supports,
a plurality of leads formed of a conductive material molded in the first and second lateral supports, each of the leads includes a first end portion extending downward from the first lower surface of the corresponding one of the first and second lateral supports, and a second end portion extending along the second lower surface of the corresponding one of the lateral supports, the second lower surface lower than the first lower surface; and
at least a first coil wound about the central winding bobbin, a first end of the first coil affixed to the first end portion of a first lead of the plurality of leads, and a second end of the first coil affixed to the first end portion of a second lead of the plurality of leads.

US Pat. No. 10,559,415

COMMON MODE FILTER CAPABLE OF BALANCING INDUCED INDUCTANCE AND DISTRIBUTED CAPACITANCE

CYNTEC CO., LTD., Hsinch...

1. A common mode filter, comprising:a winding core;
an inner coil formed of an inner wire wound around the winding core, and comprising a plurality of inner turns; and
an outer coil formed of an outer wire wound around the inner coil, and comprising a plurality of outer turns and at least one cross turn, wherein a sum of the plurality of outer turns and the at least one cross turn is equal to a number of the plurality of inner turns;
wherein the at least one cross turn comprises a N-th turn of the outer coil, wound across a (N?1)th turn of the outer coil, and adjacent to two of the plurality of outer turns of the outer coil;
wherein N is an integer not less than 3 and not greater than the number of the plurality of inner turns.

US Pat. No. 10,559,414

WIRE-WOUND TYPE POWER INDUCTOR

SAMSUNG ELECTRO-MECHANICS...

1. A wire-wound type inductor, comprising:a core containing magnetic powder flakes and including a central portion, outside portions, and connection portions extending in a length direction of the core between the central portion and a respective outside portion of the outside portions; and
a winding coil disposed in the core and wound around the central portion of the core,
wherein the core has a coupling structure including first and second bodies coupled to each other in a thickness direction of the core,
the first and second bodies contain magnetic powder flakes having shape magnetic anisotropy, and long axes of the magnetic powder flakes in the central portion are arranged in parallel with a direction in which a magnetic field of the winding coil is generated in the central portion and arranged in parallel with long axes of the magnetic powder flakes in at least one of the connection portions, and
planes of the magnetic powder flakes are arranged orthogonally to a width direction of the core.

US Pat. No. 10,559,413

COIL ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A coil electronic component comprising:a first coil wound in a first direction and having a magnetic core;
a second coil sharing the magnetic core of the first coil, the second coil being wound in the first direction or in a second direction different from the first direction;
a main board disposed between the first coil and the second coil;
a first external electrode and a second external electrode connected to the first coil; and
a third external electrode and a fourth external electrode connected to the second coil,
wherein the first coil comprises a first coil pattern disposed on a first surface of a first insulating layer and connected to the first external electrode and a second coil pattern disposed on a second surface of the first insulating layer and connected to the second external electrode,
the second coil comprises a third coil pattern disposed on a first surface of a second insulating layer and connected to the third external electrode and a fourth coil pattern disposed on a second surface of the second insulating layer and connected to the fourth external electrode,
the first insulating layer comprises a through-hole forming the magnetic core of the first coil, and the second insulating layer comprises a through-hole forming a magnetic core of the second coil,
the first and second insulating layers are not disposed directly on the main board,
each of the first insulating layer and the second insulating layer has a thickness of about 10 ?m or more to about 50 ?m or less, and
each of the thicknesses of the first insulating layer and the second insulating layer is smaller than a thickness of the main board.

US Pat. No. 10,559,412

MAGNETORESISTANCE EFFECT DEVICE

TDK CORPORATION, Tokyo (...

1. A magnetoresistance effect device comprising:at least one magnetoresistance effect element including:
a first magnetization free layer;
a magnetization fixed layer or a second magnetization free layer; and
a spacer layer sandwiched between the first magnetization free layer and the magnetization fixed layer or the second magnetization free layer; and
a magnetic field applying unit configured to apply a magnetic field at least to the first magnetization free layer of the magnetoresistance effect element, wherein
the magnetic field applying unit includes:
a first ferromagnetic material having a protruding portion protruding from a first surface to the magnetoresistance effect element side in a stacking direction of the magnetoresistance effect element;
a second ferromagnetic material sandwiching the magnetoresistance effect element together with the first ferromagnetic material; and
a coil wound around the first ferromagnetic material,
the first magnetization free layer of the magnetoresistance effect element includes a portion free of overlapping with at least one of a second surface of the protruding portion on the magnetoresistance effect element side in the stacking direction and a third surface of the second ferromagnetic material on the magnetoresistance effect element side in the stacking direction in a plan view when viewed in the stacking direction, and
a center of gravity of the first magnetization free layer of the magnetoresistance effect element is positioned in a region connecting the second surface and the third surface.

US Pat. No. 10,559,411

SUPERCONDUCTING MAGNET

HITACHI, LTD., Tokyo (JP...

1. A superconducting magnet comprising:a thermal conductor connected to a refrigerator;
a superconducting coil coming in thermal contact with the thermal conductor;
a winding section support for sandwiching a winding section of the superconducting coil between the winding section support and the thermal conductor;
an elastic body capable of applying a displacement greater than shrinkages of the thermal conductor and the winding section of the superconducting coil when the thermal conductor and the superconducting coil are cooled from an ambient temperature down to a predetermined temperature; and
a fastener joined to the elastic body and fastened to the winding section support, wherein
at least one or more said elastic bodies are disposed in each of an inner circumferential side and an outer circumferential side of the coil winding section with respect to a same radial direction of the winding section.

US Pat. No. 10,559,410

GRAIN-ORIENTED ELECTRICAL STEEL SHEET AND TRANSFORMER IRON CORE USING SAME

JFE STEEL CORPORATION, T...

1. A grain-oriented electrical steel sheet subjected to magnetic domain refining by introducing linear strains having a shape of a solid line in a direction intersecting a rolling direction of the steel sheet repeatedly at a predetermined interval in the rolling direction,wherein the predetermined interval of the linear strains in the rolling direction is d mm and, when the steel sheet is placed on a flat surface, a mean value of difference between a height from the flat surface to the linear strain-introduced area of a steel sheet surface and a height from the flat surface to a median point between adjacent linear strain-introduced areas is h mm, and a ratio h/d of the h to the d is 0.0025 or more and 0.015 or less.

US Pat. No. 10,559,409

PROCESS FOR MANUFACTURING A LEADLESS FEEDTHROUGH FOR AN ACTIVE IMPLANTABLE MEDICAL DEVICE

Greatbatch Ltd., Clarenc...

1. A method for manufacturing a feedthrough that is configured for incorporation into an active implantable medical device (AIMD), the method comprising the steps of:a) forming a first sintered ceramic reinforced metal composite (CRMC) paste, comprising the steps of:
i) mixing platinum with a first ceramic material to form a first CRMC material;
ii) subjecting the first CRMC material to a first sintering step to thereby form a first sintered CRMC material;
iii) ball-milling or grinding the first sintered CRMC material to form a first powdered sintered CRMC material; and
iv) mixing the first powdered sintered CRMC material with a solvent to form the first sintered CRMC paste;
b) forming a green-state ceramic body, comprising the steps of:
i) forming a ceramic body in a green state, the green-state ceramic body having a ceramic body body fluid side opposite a ceramic body device side, wherein, when the feedthrough is attached to a housing for the AIMD, the ceramic body fluid side resides outside the AIMD and the ceramic body device side resides inside the AIMD;
ii) forming at least one first via hole comprising a first via hole inner surface extending along a longitudinal axis through the green-state ceramic body to the body fluid and device sides;
iii) filling the at least one first via hole in the green-state ceramic body with the first sintered CRMC paste extending to a first sintered CRMC paste first end residing at or adjacent to the ceramic body fluid side and a first sintered CRMC paste second end residing at or adjacent to the ceramic body device side;
iv) drying the green-state ceramic body including the first sintered CRMC paste to thereby form a second CRMC material filling the at least one first via hole in the ceramic body;
v) forming a second via hole extending through the second CRMC material to the ceramic body fluid and device sides so that an inner surface of the second CRMC material is spaced closer to the longitudinal axis than the first via hole inner surface;
vi) providing a substantially pure metal core in the second via hole; and
vii) subjecting the green-state ceramic body including the second CRMC material and the substantially pure metal core to a second sintering step to thereby form a sintered ceramic body comprising the second CRMC material surrounding the substantially pure metal core; and
c) providing an electrically conductive ferrule comprising a ferrule opening; and
d) hermetically sealing the sintered ceramic body to the ferrule in the ferrule opening.

US Pat. No. 10,559,408

FEEDTHROUGH DEVICE AND SIGNAL CONDUCTOR PATH ARRANGEMENT

ASML Netherlands B.V., V...

1. A feedthrough device for forming a hermetic seal around a plurality of signal conductors, the signal conductors extending alongside each other to form a signal conductor group with a group width, wherein the feedthrough device comprises:a slotted member, delimited by a first surface that faces predominantly towards a feedthrough direction (X), a second surface that faces predominantly opposite to the feedthrough direction, and a side surface that interconnects the first and second surfaces and faces outwards in a direction non-parallel to the feedthrough direction;
a base with a hole that extends entirely through the base along the feedthrough direction, wherein the hole is adapted to accommodate the slotted member;
wherein the slotted member further comprises at least one slot, which extends along the feedthrough direction through the slotted member and opens into the first and second surfaces, to allow the signal conductor group to pass from the first surface through the slotted member to the second surface, wherein the slot further opens into a longitudinal opening along the side surface, and extends from the side surface along a depth direction (Z; Y) transverse to the feedthrough direction up to a slot depth (?Zs; ?Ysa) into the slotted member, wherein the slot depth is equal to or larger than the group width (?Zs?Wf; ?Ysa?Wf),wherein the base defines an inner surface that directly surrounds the hole, wherein the inner surface covers at least part of the side surface and the longitudinal opening of the slotted member, when accommodated in the hole.

US Pat. No. 10,559,405

CABLE CONFIGURED TO REDUCE A RADIATED ELECTROMAGNETIC FIELD

Wireless Advanced Vehicle...

1. A transmission cable comprising:a first conductor with current flowing in a positive direction;
a second conductor with a current flowing in a negative direction, the negative direction opposite the positive direction, the current in the first conductor equal to the current in the second conductor;
a third conductor with current flowing in the positive direction;
a fourth conductor with a current flowing in the negative direction, the current in the third conductor equal to the current in the fourth conductor, wherein the first conductor, the second conductor, the third conductor, and the fourth conductor are arranged in a symmetrical square pattern from a beginning to an end of the cable, the conductors each on a corner of the square pattern, the first conductor opposite the third conductor and adjacent to the second conductor and the fourth conductor; and
one or more signal conductors located in a center of the square pattern, wherein the first, second, third and fourth conductors are alternating current (“AC”) power transmission conductors and the one or more signal conductors transmit data associated with power transmission of the first, second, third and fourth conductors.

US Pat. No. 10,559,404

TRACEABLE POWER CABLE AND METHOD

PRYSMIAN S.p.A., Milan (...

1. A power cable comprising at least one conductor and a hollow tube at least partially filled with a traceable material, wherein said traceable material comprises a tracer associated with a uniquely identifiable code and wherein said traceable material is in a liquid or gel form wherein said hollow tube is an independent element.

US Pat. No. 10,559,403

COMPOSITION HAVING OIL FILM RETENTION FUNCTION, ANTICORROSIVE AGENT USING SAME, AND INSULATED TERMINATED ELECTRIC WIRE

AUTONETWORKS TECHNOLOGIES...

1. An anticorrosive agent containing a base oil and a composition having an oil film retention function, wherein an amount of the composition having an oil film retention function in the anticorrosive agent is 10 mass % or more;the composition having an oil film retention function consists of a component (a) and a component (b); wherein
the component (a) is an adduct of an azole compound and an acidic alkyl phosphate ester, where the acidic alkyl phosphate ester includes one or more compounds represented by
General Formula (1):(Chemical Formula 1)
P(?O)(—OR1)(—OH)2  (1)
or General Formula (2):(Chemical Formula 2)
P(?O)(—OR1)2(—OH)  (2)where R1 represents an organic group having four or more carbon atoms;the component (b) is an adduct of a metal and an acidic alkyl phosphate ester having a common structure to that of the acidic alkyl phosphate ester used to form the adduct of component (a).

US Pat. No. 10,559,402

TWIST RESISTANT ELECTRICAL HARNESS

GOODRICH CORPORATION, Ch...

1. An electrical harness, comprising: an electrical cable; an inner tubing extending from a first end of the electrical harness to a second end of the electrical harness, the inner tubing encasing the electrical cable; a braid tubing extending from the first end of the electrical harness to the second end of the electrical harness, the braid tubing encasing the inner tubing; and an outer tubing extending from the first end of the electrical harness to the second end of the electrical harness, the outer tubing encasing the braid tubing; wherein the braid tubing physically contacts the inner tubing and the outer tubing; and wherein the braid tubing is mechanically locked with the inner tubing and the outer tubing.

US Pat. No. 10,559,401

CABLE, DEVICE AND METHOD OF SUPPLYING POWER

1. A cable comprising:an original cable having an insulating sheath as an outermost layer;
a first material provided on the insulating sheath of the original cable; and
a metal sheath provided on the first material and made of aluminum, magnesium, copper, rhodium, silver or gold,
wherein the first material is at least one of a hygroscopic fiber, an inorganic ion exchanger influence fiber, a supercritical influence fiber, and a composite fiber obtained by mixing two or more among the mentioned fibers, and
wherein the first material is impregnated with a silver ion nano-colloidal solution and a tungsten oxide containing solution.

US Pat. No. 10,559,400

FLEX FLAT CABLE STRUCTURE AND FIXING STRUCTURE OF CABLE CONNECTOR AND FLEX FLAT CABLE

ENERGY FULL ELECTRONICS C...

1. A flex flat cable (FFC) electrical connector fix structure, comprising:an electrical connector, comprising:
a housing;
a spacer, assembled onto the housing, and comprising a plurality of containing recesses;
a printed circuit board (PCB), comprising a plurality of conductive portions and a plurality of connecting portions, and the plurality of conductive portions being electrically connected to the plurality of corresponding connecting portions respectively;
a plurality of terminals, one end of the plurality of terminals passing through the containing recess and being connected to the plurality of connecting portions; and
a shell, assembled onto the housing; and
an FFC structure, comprising:
a plurality of metallic transmission lines, being arranged parallel, and comprising one or more power line and a plurality of signal lines; the power line being configured to transmit power; the plurality of signal lines being configured to transmit a data signal;
a plurality of first insulating jackets, each of the plurality of first insulating jackets enclosing one of the plurality of metallic transmission lines;
a second insulating jacket, surrounding the plurality of first insulating jackets;
a third insulating jacket, enclosing the plurality of first insulating jackets without any gap, and the second insulating jacket enclosing the third insulating jacket; and
a shield layer, configured to isolate the second insulating jacket from the third insulating jacket, comprising:
an insulating film, comprising a first side and a second side, and the first side and the second side being on opposite sides of the insulating film;
a first block layer, adhering to the first side of the insulating film; and
a second block layer, adhering to and contacting the first block layer,
wherein the first block layer and the second block layer are made of different materials,
wherein all of the plurality of metallic transmission wires are respectively connected to all of the plurality of conductive portions on one surface of the PCB,
wherein the printed circuit board is between the FFC structure and the spacer.

US Pat. No. 10,559,399

MULTI-PHASE BUSBAR FOR ENERGY CONDUCTION

ABB Schweiz AG, Baden (C...

1. A multi-phase busbar for conducting electric energy, the busbar comprising:a first conducting layer comprising a sheet metal coated with an electrically insulating material,
a first conducting pin mounted to the first conducting layer, the first conducting pin extending in a direction perpendicular to the first conducting layer,
a first insulating layer of a rigid insulating material arranged on the first conducting layer, the first insulating layer defining an opening through which the first conducting pin projects, and
a second conducting layer comprising a sheet metal coated with an electrically insulating material, the second conducting layer comprising a first pinhole through which the first conducting pin projects and a second conducting pin which extends in a direction parallel to the first conducting pin,
wherein the opening in the first insulating layer and the first pinhole in the second conducting layer define a common recess through which the first conducting pin projects, the recess being filled with a resin which forms a material bridge between the first conducting layer and the second conducting layer, the material bridge mechanically clamping the first conducting layer, the first rigid insulating layer, and the second conducting layer together.

US Pat. No. 10,559,398

COMPOSITE SOLID ELECTROLYTES FOR RECHARGEABLE ENERGY STORAGE DEVICES

International Business Ma...

1. A device, comprising:an ion-conducting membrane comprising ion-conducting ceramic particles in an insulating polymeric binder, wherein at least a portion of the ion-conducting ceramic particles extend from a first major surface of the insulating polymeric binder to an opposed second major surface of the insulating polymeric binder, wherein the ion-conducting ceramic particles in the portion comprise a first part extending above the first major surface of the insulating polymeric binder and a second part extending below the second major surface of the insulating polymeric binder, and wherein the first part and the second part of the ceramic particles are uncovered by the insulating polymeric binder, and
an ion-conducting polymer comprising a pressure-deformable film with a glass transition temperature lower than an operation temperature of the device, wherein the pressure-deformable film has a first major surface and a second major surface opposite the first major surface, and wherein the pressure-deformable film surrounds the ion-conducting membrane such that the first part of the ion-conducting ceramic particles is below the first major surface of the film and the second part of the ion-conducting ceramic particles is below the second major surface of the film.

US Pat. No. 10,559,397

CONDUCTIVE POLYMER COMPOSITE AND SUBSTRATE

SHIN-ETSU CHEMICAL CO., L...

1. A conductive polymer composite which comprises a conductive polymer composite comprising(A) a ?-conjugated polymer, and
(B) a dopant polymer containing a repeating unit represented by the following general formula (1) and having a weight average molecular weight in the range of 1,000 to 500,000,

wherein, R1 represents a hydrogen atom or a methyl group; Rf1 represents a linear or branched alkyl group having 1 to 4 carbon atoms or a phenyl group, and has at least one of a fluorine atom or a trifluoromethyl group in Rf1; Z1 represents a single bond, an arylene group having 6 to 12 carbon atoms or —C(?O)—O—R2—; R2 represents a linear, branched or cyclic alkylene group having 1 to 12 carbon atoms, an arylene group having 6 to 10 carbon atoms or an alkenylene group having 2 to 10 carbon atoms, and may have an ether group, a carbonyl group or an ester group in R2; and “a” is 0

US Pat. No. 10,559,396

DEVICES PROCESSED USING X-RAYS

SVXR, Inc., San Jose, CA...

1. A plurality of improved integrated circuit device packages having (1) a plurality of electrically connected components that have been individually fabricated, and (2) a plurality of features between 1 and 500 microns, the plurality of improved integrated circuit device packages having a package assembly yield of greater than 90% based on inspections by an automated high-speed x-ray inspection tool of a plurality of prior integrated circuit device packages, the plurality of improved integrated circuit device packages being produced by a process comprising the steps of:modifying, responsive to detecting one or more process variations that reduce package assembly yield by the high-speed x-ray inspection tool, one or more steps of the production process to reduce the detected process variations, wherein the modifications reduce one or more defects created during the production process; and
producing, using the modified production process, the plurality of improved integrated circuit device packages, wherein the modified production process achieves the package assembly yield of greater than 90%.

US Pat. No. 10,559,395

OPTIMIZATION OF HIGH RESOLUTION DIGITALLY ENCODED LASER SCANNERS FOR FINE FEATURE MARKING

nLIGHT, Inc., Vancouver,...

1. A method, comprising:selecting a laser beam diameter;
situating a substrate to be scanned at a scan plane associated with the selected laser beam diameter;
exposing the substrate to a laser beam with the selected laser beam diameter by scanning the laser beam with respect to the substrate, wherein the laser beam is scanned with angular scan increments corresponding to less than 1/10 of the laser beam diameter at the scan plane.

US Pat. No. 10,559,394

RADIOLOGICAL IMAGE CONVERSION SCREEN AND FLAT PANEL DETECTOR

MITSUBISHI CHEMICAL CORPO...

1. A radiological image conversion screen, comprising a support substrate and a phosphor layer stacked on the support substrate,wherein:
the phosphor layer comprises:
phosphor particles,
a polyvinyl acetal resin, and
a carboxylic acid ester having an ether group; and
the phosphor particles comprise at least one phosphor selected from the group consisting of:
a GOS phosphor,
a rare earth tantalum-based composite oxide phosphor, and
a CsI phosphor.

US Pat. No. 10,559,393

X-RAY DETECTOR FOR PHASE CONTRAST AND/OR DARK-FIELD IMAGING

KONINKLIJKE PHILIPS N.V.,...

1. An X-ray detector for phase contrast imaging and/or dark-field imaging, comprising:a scintillator layer; and
a photodiode layer;
wherein the scintillator layer is configured to convert incident X-ray radiation modulated by a phase grating structure into light to be detected by the photodiode layer;
wherein the scintillator layer comprises an array of scintillator channels periodically arranged with a pitch forming an analyzer grating structure;
wherein the scintillator layer and the photodiode layer form a first detector layer comprising a matrix of pixels
wherein each pixel comprises an array of photodiodes, each photodiode forming a sub-pixel;
wherein adjacent sub-pixels during operation receive signals having mutually shifted phases;
wherein the sub-pixels that during operation receive signals having mutually identical phase form a phase group per pixel;
wherein the signals received by the sub-pixels within the same phase group per pixel during operation are combined to provide one phase group signal;
wherein the phase group signals of different phase groups during operation are obtained in one image acquisition;
wherein the pitch of the scintillator channels is detuned by applying a correcting factor c to a fringe period (pfringe) of a periodic interference pattern (35) created by the phase grating structure, wherein 0 wherein the X-ray detector comprises a second detector layer provided on one surface of the first detector layer, which one surface is perpendicular to an orientation of the scintillator channels of the first detector layer;
where the second detector layer comprises a scintillator layer with an array of periodically arranged scintillator channels with the same pitch as the scintillator channels of the first detector layer and a photodiode layer; and
wherein each scintillator channel of the second detector layer is arranged to be displaced in surface direction in relation to the adjacent scintillator channel of the first detector layer by half of the pitch.

US Pat. No. 10,559,391

IRRADIATION TARGET PROCESSING SYSTEM

FRAMATOME GMBH, Erlangen...

1. An irradiation target processing system for insertion and retrieving irradiation targets into and from an instrumentation tube in a nuclear reactor core, the system comprising:a target retrieving system comprising a target exit port configured to be coupled to a target storage container and an exhaust system;
a target insertion system comprising a target filling device, a target retention tubing, a target diverter coupled to the target filling device, the target retention tubing and the target retrieving system, and a target supply junction at the target retention tubing, wherein the target supply junction is configured to be connected to the instrumentation tube; and
a transport gas supply system comprising a first gas supply tubing, a second gas supply tubing, and a transport gas supply junction coupled to the first and second gas supply tubing, wherein the first gas supply tubing is coupled to the exit port of the target retrieving system, and the second gas supply tubing is configured to be coupled to a junction for supplying gas to the instrumentation tube; and
wherein the target retrieving system, the target insertion system, and the transport gas supply system are mounted on a movable support.

US Pat. No. 10,559,390

ACTIVITY CROSS-CALIBRATION OF UNSEALED RADIONUCLIDES UTILIZING A PORTABLE ION CHAMBER

1. A method of cross-calibrating a radionuclide at two separate locations (A and B) comprising the steps of:(a) drawing up a known amount of activity, A0A, at location A at calibration time t0A into a pre-defined volume in a first syringe;
(b) inserting the syringe into a portable ion chamber, and placing the ion chamber into a dose calibrator;
(c) measuring the chamber's response by integrating charge for a period of time tiA and determining a calibration factor;
(d) transferring the ion chamber and the first syringe, emptied and cleaned, or an empty second syringe identical to the first syringe, to location B;
(e) drawing a second sample having the same volume of the same radionuclide into the cleaned and emptied syringe or second syringe, placing the syringe into the ion chamber, placing the ion chamber into a second dose calibrator, and measuring the ion chamber's response in the second dose calibrator for a second period of time;
(f) determining the activity of the second sample by adjusting with the location A calibration factor; and
(g) cross-calibrating the second dose calibrator with the first dose calibrator using the measured activity of the second sample.

US Pat. No. 10,559,389

MODULAR NUCLEAR REACTORS INCLUDING FUEL ELEMENTS AND HEAT PIPES EXTENDING THROUGH GRID PLATES, AND METHODS OF FORMING THE MODULAR NUCLEAR REACTORS

Battell Energy Alliance, ...

1. A modular nuclear reactor, comprising:a plurality of sections, each section comprising:
a tank comprising a front plate, a back plate, side plates, a top plate, and a bottom plate;
a plurality of grid plates within the tank, each grid plate of the plurality of grid plates comprising a plurality of apertures and vertically separated from an adjacent grid plate;
a plurality of fuel elements extending through each grid plate of the plurality of grid plates; and
a plurality of heat pipes extending through each grid plate of the plurality of grid plates, the top plate, and an upper reflector; and
a side reflector material surrounding the plurality of sections.

US Pat. No. 10,559,388

DIAGNOSTICALLY USEFUL RESULTS IN REAL TIME

CathWorks Ltd., Kfar Sab...

1. A vascular assessment apparatus comprising:a processor communicatively coupled to a medical imaging device; and
a memory storing non-transitory computer-readable instructions, which when executed, cause the processor to:
receive medical images of a coronary vessel tree of a subject from the medical imaging device;
create a first model based on the medical images, the first model indicative of volumetric dimensions of the coronary vessel tree;
create a second model based on the first model, the second model indicative of resistances to blood flow within the coronary vessel tree;
at least one of (i) determine a location of a potential stenosis within the coronary vessel tree based on the resistances to blood flow of the second model, or (ii) receive an indication of the location of the potential stenosis;
perform a virtual revascularization at the location of the potential stenosis by at least one of
(a) determine coronary vessel segments that are proximal and distal to the location of the potential stenosis, calculate a coronary edge by interpolating dimensions of the determined proximal and distal coronary vessel segments through the location of the potential stenosis, and store the interpolating dimensions as inflated dimensions of the location of the potential stenosis, or
(b) determine coronary vessel segments that are proximal and distal to the location of the potential stenosis, determine mean values of diameters of the determined proximal and distal coronary vessel segments, determine an average of the determined values, and store the determined average as an inflated diameter of the location of the potential stenosis; and
process an adjustment to at least one of the first model, the second model, or the medical images based on the virtual revascularization at the location of the potential stenosis.

US Pat. No. 10,559,387

SLEEP MONITORING FROM IMPLICITLY COLLECTED COMPUTER INTERACTIONS

Microsoft Technology Lice...

1. A method for improving performance based on sleep patterns, the method including at least one processor performing steps comprising:receiving implicitly collected computer interaction data of a user from a computing device, the implicitly collected computer interaction data collected during the user's interaction with the computing device;
accessing a data store of previously collected computer interaction data, the previously collected computer interaction data correlated with sleep patterns of at least one of the user and other users;
comparing the users implicitly collected computer interaction data to the previously collected computer interaction data;
inferring the user's sleep pattern based on the comparing using an inference model; and
presenting a suggestion to the user via at least one of an audio and a visual interface of the computing device based on the user's sleep pattern to adapt the user's experience with the computing device by making the user aware of the user's sleep pattern.

US Pat. No. 10,559,386

METHODS AND SYSTEMS FOR AN ARTIFICIAL INTELLIGENCE SUPPORT NETWORK FOR VIBRANT CONSTITUIONAL GUIDANCE

KPN Innovations, LLC, La...

1. A system for an artificial intelligence support network for vibrant constitutional guidance, the system comprising:at least a server;
at least a diagnostic engine including a prognostic label learner machine learning process and an ameliorative process label learner machine learning process that both operate on the diagnostic engine, wherein the diagnostic engine is designed and configured to:
receive a first training data set including a plurality of first data entries, each first data entry of the plurality of first data entries including at least an element of physiological state data and at least a correlated first prognostic label;
receive a second training data set including a plurality of second data entries, each second data entry of the plurality of second data entries including at least a second prognostic label and at least a correlated ameliorative process label; and
receive at least a biological extraction from a user;
wherein the prognostic label learner is designed and configured to:
generate at least a prognostic output by executing a lazy learning algorithm as a function of the first training set and the at least a biological extraction;
wherein the ameliorative process label learner is designed and configured to:
generate at least an ameliorative output by executing a supervised machine learning algorithm as a function of the second training set and the at least a prognostic output;
wherein the diagnostic module is designed and configured to generate a diagnostic output including the at least a prognostic output and the at least an ameliorative output; and
an advisory module designed and configured to:
receive at least a request for an advisory input;
generate at least an advisory output using the at least a request for an advisory input and the at least a diagnostic output;
select at least an informed advisor client device as a function of the at least a request for an advisory input, wherein the advisory module is configured to select the at least an informed advisor client device using a user-requested category of at least an informed advisor; and
transmit the at least an advisory output to the at least an informed advisor client device.

US Pat. No. 10,559,385

FORECASTING A PATIENT VITAL MEASUREMENT FOR HEALTHCARE ANALYTICS

CONDUENT BUSINESS SERVICE...

1. A computer implemented method for obtaining an unknown patient vital measurement for healthcare analytics, the method comprising:receiving, by a processor, temporally successive patient vital measurements comprising irregularly sampled observations {y1, . . . , yN}, where yj denotes the jth observation at time tj, and N is the number of samples;
communicating, by a processor, the temporally successive vital measurements to a model trained using historical data of patient vital measurements, the model generating a parameter set ?=(A,B,C,Q,R), where A is a state transition matrix, B is a control matrix, C is a matrix which maps state-space variables to observation variables, Q is an amount of noise in the state-space variables, and R is an amount of noise in the observation variables;
calculating, by a processor, state-space variables zt using the parameter set ? generated by the model; and
performing, by a processor, one of: forecasting an unknown observation yN+1, and imputing an unknown observation yt, where 1

US Pat. No. 10,559,384

DECISION SUPPORT SYSTEM USING INTELLIGENT AGENTS

PHYSIO-CONTROL, INC., Re...

1. A method for providing decision support for a medical treatment, comprising:providing a primary processing thread of instruction events for coaching treatment of a patient based on a primary rules-based service;
providing a processing thread of instruction events for coaching treatment of a patient that is independent of the primary processing thread for coaching treatment of a patient based on a conditional rules-based service; and
triggering an action by the independent processing thread of instruction events based on a conditional rules-based service on the occurrence of a pre-defined set of input conditions.

US Pat. No. 10,559,383

EMPLOYEE VISIT VERIFICATION SYSTEM

1. A visit verification (VV) system for verifying visits by a Mobile Service Provider (MSP) to a residence of a client comprising:a. a beacon having:
i. a transmitter configured for transmitting a signal;
ii. a visual code;
b. a mobile computing device (MCD) having:
i. an optical device configured for reading the visual code on the beacon;
ii. a receiver capable of receiving the signal from the beacon,
iii. a controller configured for determining the distance from the beacon based upon the received signal;
iv. a communication device configured for communicating information from the MCD;
c. a server comprising:
i. a network adapter configured for receiving information from the MCD,
ii. a memory configured for storing information;
iii. an input/output (I/O) device configured for providing output to, and receiving input from a user;
iv. a controller connected to the network adapter, the memory, the I/O device, configured to:
1. authenticate an MSP;
2. determine when the MSP is outside of an acceptable perimeter:
3. store task status information from the MCD.

US Pat. No. 10,559,382

EMPLOYEE VISIT VERIFICATION SYSTEM

1. A visit verification (VV) system for verifying visits by a Mobile Service Provider (MSP) to a residence of a client comprising:a. a beacon having:
i. an RF transmitter configured for transmitting an RF signal;
ii. a visual code;
b. a mobile computing device (MCD) having:
i. an optical device configured for reading the visual code on the beacon;
ii. a receiver capable of receiving the signal from the beacon,
iii. a controller running executable code configured for determining:
1. if the visual code matches a prestored code indicating that this is the proper beacon;
2. the distance from the beacon to the MCD based upon the received signal;
iv. a direct communication link configured for communicating information from the MCD to another local computing device;
c. a server, being a computing device, configured for receiving information periodically from the MCD relating to at least one of login information, RSSI, distance from beacon, longitude, latitude, tasks completed, task status through a manual, direct connection, storing and providing information being at least one of a task schedule, client to visit, beacon UUIDs, addresses, residence locations to the MCD.

US Pat. No. 10,559,381

MEDICAL SYSTEM AND INFORMATION NOTIFICATION METHOD

OLYMPUS CORPORATION, Tok...

1. A medical system comprising:a server device;
a first storage unit configured to store available device information including device names, locations, and scheduled use dates and times of a plurality of medical devices that are available for use;
a processor configured to:
determine whether one of the plurality of medical devices is a failed medical device;
allow selection, from among the plurality of medical devices other than the failed medical device, an alternative medical device that may be an alternative device of the failed medical device on the basis of failure information of the failed medical device and the available device information stored in the first storage unit;
transmit replacement information including a device name, a location, and a usable date and time of the alternative medical device to one or more client terminal devices corresponding to the medical devices that have not failed in order to display the replacement information on the one or more client terminal devices and instruct a user to select the alternative medical device for inspection; and
automatically restore patient information and device setting information previously stored in the failed medical device,
the plurality of medical devices including:
an endoscopic device;
a peripheral device connected to the endoscopic device, the failure information being transmitted from the endoscopic device that has detected a failure of the peripheral device; and
a portable terminal device, wherein:
the endoscopic device includes a second storage unit in which patient information and inspection information are stored,
the endoscopic device transmits one or more of:
the patient information stored in the second storage unit,
the inspection information stored in the second storage unit,
device setting information of the endoscopic device, and
device setting information of the peripheral device acquired from the peripheral device to the portable terminal device,
the portable terminal device includes:
a third storage unit in which the patient information and the inspection information stored in the second storage unit, the device identification information and the device setting information of the endoscopic device, and the device identification information and the device setting information of the peripheral device are stored by being associated with each other;
the processor further configured to:
acquire one or both of device identification information of the endoscopic device and device identification information of the peripheral device;
update corresponding information stored in the third storage unit in response to the patient information, the inspection information, the device setting information of the endoscopic device, or the device setting information of the peripheral device after a change transmitted by the endoscopic device; and
compare the device identification information of the endoscopic device and the device identification information of the peripheral device acquired by the acquisition unit with the device identification information of the endoscopic device and the device identification information of the peripheral device stored in the third storage unit, wherein:
as a result of the comparison, when the device identification information of the endoscopic device is different,
the portable terminal device transmits the patient information, the inspection information, and the device setting information of the endoscopic device stored in the third storage unit to the endoscopic device,
the endoscopic device stores the patient information and the inspection information transmitted by the portable terminal device in the second storage unit of the endoscopic device, and performs device setting of the endoscopic device in accordance with the device setting information of the endoscopic device transmitted by the portable terminal device,
the comparison, when the device identification information of the peripheral device is different, the portable terminal device transmits the device setting information of the peripheral device stored in the third storage unit to the endoscopic device, and
the endoscopic device performs device setting of the peripheral device in accordance with the device setting information of the peripheral device transmitted by the portable terminal device.

US Pat. No. 10,559,380

EVIDENCE-BASED HEALTHCARE INFORMATION MANAGEMENT PROTOCOLS

Elwha LLC, Bellevue, WA ...

1. A healthcare information management system comprising:one or more integrated circuit devices including at least:
circuitry configured for obtaining an order allocating one or more medical devices to be used in association with a patient;
circuitry configured for detecting that at least one medical device is within a predetermined vicinity of the patient;
circuitry configured for retrieving at least one medical record via at least one network at least partly based on the order allocating the one or more medical devices and the detection that the at least one medical device is within the predetermined vicinity of the patient, the at least one medical record including at least one of a scan or an annotation;
circuitry configured for determining, from the at least one medical record including the at least one of the scan or the annotation, whether one or more protocols associated with usage of the at least one medical device for treating the patient for at least one condition is conventional based at least in part on at least one prominence indication signifying at least one indication of effectiveness in treating the at least one condition by one or more entities;
circuitry configured for enabling the at least one medical device conditionally based at least in part on the order allocating the one or more medical devices, the detection that the least one medical device is within the predetermined vicinity of the patient, and whether the one or more protocols associated with usage of the at least one medical device for treating the patient for the at least one condition is conventional; and
circuitry configured for facilitating delivery of at least one of a drug or treatment to the patient via the at least one medical device in accordance with the one or more protocols.

US Pat. No. 10,559,379

DIAGNOSIS SUPPORT APPARATUS, OPERATION METHOD FOR THE SAME, AND DIAGNOSIS SUPPORT SYSTEM

FUJIFILM Corporation, To...

1. A diagnosis support apparatus comprising:a reception unit that receives entry of a disease name specified by a doctor visually recognizing a target image which is an examination image of a certain patient and is an image reading target of the doctor;
a type acquisition unit that acquires the type of extracted lesion which is a lesion present in the target image and is extracted by performing image analysis on the target image;
an information management unit that manages registered lesion information in which the disease name and a registered lesion corresponding to the disease name are registered, and reads the registered lesion corresponding to the disease name received by the reception unit;
a comparison unit that compares the type of registered lesion read by the information management unit with the type of extracted lesion acquired by the type acquisition unit; and
an output control unit that outputs reliability information regarding the reliability of the disease name received by the reception unit on the basis of a comparison result in the comparison unit.

US Pat. No. 10,559,378

SYSTEMS AND METHODS FOR PROCESSING LARGE MEDICAL IMAGE DATA

AGFA HEALTHCARE NV, Mort...

1. A method of managing medical image data items, the method comprising:receiving a medical image data item, the medical image data item including at least one medical image set where each medical image set in the at least one medical image set is from the same medical imaging procedure and defines a sub-image from the medical imaging procedure, and each medical image set has a corresponding resolution and includes at least one sub-image object;
defining a data item identifier for the received medical image data item;
analyzing the received medical image data item to identify image metadata and image pixel data;
generating a plurality of pixel objects for the medical image data item using the image pixel data, wherein each pixel object includes at least a portion of the image pixel data that corresponds to one of the sub-images, each sub-image has at least one corresponding pixel object, each portion of the image pixel data is included in one of the pixel objects, and each pixel object also includes a pixel object identifier that identifies the data item identifier and the sub-image corresponding to that pixel object;
storing the plurality of pixel objects in a first storage memory with each pixel object having an address location in the first storage memory;
generating at least one representative object for the medical image data item using the image metadata, the at least one representative object including a set representative object corresponding to each medical image set, and each set representative object defines identifying characteristics for the corresponding sub-image of the medical image set and identifies the first storage memory in which the corresponding at least one pixel object is stored, wherein the at least one representative object includes at least one overview object for the medical image data item, each overview object includes an overview pixel object and overview object metadata, the overview pixel object generated from a selected portion of the image pixel data and representing an overview of the medical image sets from the medical imaging procedure with an overview resolution that is less than the resolution of the image pixel data in the at least one medical image sets, and the overview object metadata includes a portion of the image metadata corresponding to the selected portion of the image pixel data and representative object identifiers identifying each of the at least one set representative objects; and
storing the at least one representative object including the at least one overview object in a second storage memory.

US Pat. No. 10,559,377

GRAPHICAL USER INTERFACE FOR IDENTIFYING DIAGNOSTIC AND THERAPEUTIC OPTIONS FOR MEDICAL CONDITIONS USING ELECTRONIC HEALTH RECORDS

Biomed Concepts Inc., So...

1. A non-transitory computer-readable medium (CRM) comprising instructions that enable a graphical user interface for identifying diagnostic options for medical conditions to:obtain, from a plurality of electronic health records of previously examined patients, a plurality of diagnostic action results and a plurality of diagnoses,
wherein the plurality of electronic health records is stored in an electronic health record database,
wherein the plurality of diagnostic action results, stored in the electronic health record database, comprises quantifications of the plurality of diagnostic action results;
generate, for the plurality of diagnoses, a plurality of statistical distributions of the plurality of diagnostic action results,
wherein at least one statistical distribution is generated for each of the plurality of diagnoses, and
wherein the at least one statistical distribution is specific to one of the plurality of diagnostic action results;
establish a plurality of pairs of diagnoses from the plurality of diagnoses;
obtain a plurality of overlaps from the plurality of statistical distributions by:
for each of the plurality of pairs of diagnoses, quantifying an overlap of two statistical distributions of the diagnostic action results associated with one of the plurality of pairs of diagnoses;
obtain a plurality of benefits of the plurality of diagnostic action results by:
for each of the plurality of pairs of diagnoses, obtaining, based on the overlap of two statistical distributions of the diagnostic action results associated with one of the plurality of pairs of diagnoses, a benefit of the plurality of benefits of the diagnostic action results for disambiguating the pair of diagnoses, wherein the benefit positively correlates with an inverse of the overlap;
storing the plurality of benefits of the diagnostic action results in a diagnoses statistics database; and
provide information to a user via the graphical user interface regarding a patient to be diagnosed, using the plurality of benefits of the plurality of diagnostic action results stored in the diagnoses statistics database by:
obtaining an initial differential diagnosis for the patient to be diagnosed from an electronic health record of the patient to be diagnosed,
wherein the initial differential diagnosis comprises a group of the plurality of diagnoses, the group selected to have a higher associated probability of correctly identifying a condition of the patient to be diagnosed than non-selected diagnoses of the plurality of diagnoses, based on the electronic health record of the patient to be diagnosed;
selecting a subset of the plurality of diagnostic action results for which the benefit is larger than for non-selected diagnostic action results of the plurality of diagnostic action results, to disambiguate the group of the plurality of diagnoses in the initial differential diagnosis; and
providing a selection of diagnostic actions associated with the subset of the plurality of diagnostic action results to the user accessing the graphical user interface.

US Pat. No. 10,559,376

DATA STORAGE DEVICE WITH REWRITEABLE IN-PLACE MEMORY

Seagate Technology LLC, ...

1. A data storage device comprising a selection module connected to a write cache and a non-volatile memory, the non-volatile memory comprising bit addressable memory cells separated into a first logical tier and a second logical tier, the selection module configured to restrict access to the first logical tier in response to a first data block being written to an address of the first logical tier and the first logical tier being unstable, the selection module configured to move data resident in the first logical tier to the second logical tier in response to a determination that the data is updated infrequently.

US Pat. No. 10,559,375

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:a non-volatile memory including a normal region, a self-repair region and a redundancy region, each having a plurality of cells;
a first boot-up control block suitable for controlling a first boot-up operation to detect defective cells of the normal region and store a defective address in a first latch unit;
a self-program control block suitable for controlling a self-program operation to program the defective address stored in the first latch unit into the self-repair region; and
a second boot-up control block suitable for controlling a second boot-up operation to read out data of the normal region based on an input address while reading out data of the redundancy region instead of the data of the normal region when data of the self-repair region coincides with the input address.

US Pat. No. 10,559,374

CIRCUIT TOPOLOGY OF MEMORY CHIPS WITH EMBEDDED FUNCTION TEST PATTERN GENERATION MODULE CONNECTED TO NORMAL ACCESS PORT PHYSICAL LAYER

Piecemakers Technology, I...

1. A circuit for use in a memory chip to test the memory chip, comprising: a plurality of test pads, for connecting to a tester; a plurality of interface pads, operable to function as one or more access ports under a normal operation, wherein the interface pads are connected to a physical layer (PHY) after assembly of the memory chip in a memory system; a core block, coupled to the interface pads, accessible by the interface pads; an embedded test block, disposed outside the core block, coupled to the test pads and the interface pads, wherein the embedded test block is arranged for generating at least one test pattern as a test signal, and outputting the test signal to the core block through the interface pads to test the core block as when the core block is accessed under a normal operation after assembly in the memory system, wherein the embedded test block comprises a test circuit, and the core block comprises a functional circuit; and in a test mode the test circuit receives a control input from the tester only through the test pads, generates the at least one test pattern as the test signal according to the control input, and outputs the test signal to the functional circuit only through the interface pads, to perform a die test operation so as to test the core block, wherein the interface pads is also the interface for signal transmission in the normal operation.

US Pat. No. 10,559,373

NONVOLATILE MEMORY INCLUDING ON-DIE-TERMINATION CIRCUIT AND STORAGE DEVICE INCLUDING THE NONVOLATILE MEMORY

SAMSUNG ELECTRONICS CO., ...

1. A nonvolatile memory (NVM) device performing a read operation and a write operation, the NVM device comprising:a data pin configured to output read data and to receive write data;
a control pin configured to receive a read enable signal during the read operation, the read enable signal comprising a preamble section, a toggling section and a postamble section;
an on-die termination (ODT) pin configured to receive a first ODT signal during the read operation and a second ODT signal during the write operation; and
a nonvolatile memory (NVM) chip connected to the data pin, the control pin and the ODT pin respectively, the NVM chip including a ODT circuit to perform a first ODT operation based on the first ODT signal and to perform a second ODT operation based on the second ODT signal,
wherein the first ODT signal is enabled during the preamble section of the read enable signal, and the first ODT signal is disabled during the postamble section of the read enable signal.

US Pat. No. 10,559,372

SHIFT REGISTER CIRCUIT, GATE DRIVING CIRCUIT, DISPLAY APPARATUS AND METHOD FOR DRIVING THE SAME

HEFEI XINSHENG OPTOELECTR...

1. A shift register circuit, comprising a first output sub-circuit and a second output sub-circuit; whereinthe first output sub-circuit is coupled to a clock signal terminal, a control signal terminal, a pull-up node and an output signal terminal, and is configured to output a clock signal output via the clock signal terminal to the output signal terminal under control of a control signal having first level output via the control signal terminal and the potential of the pull-up node, and to be turned off under control of a control signal having second level output via the control signal terminal; and
the second output sub-circuit is coupled to the clock signal terminal, the pull-up node and the output signal terminal, and is configured to output the clock signal to the output signal terminal under control of the potential of the pull-up node.

US Pat. No. 10,559,371

PROGRAMMING OF MEMORY CELLS IN THREE-DIMENSIONAL MEMORY DEVICES

YANGTZE MEMORY TECHNOLOGI...

1. A three-dimensional (3D) memory device, comprising:a NAND memory string extending vertically above a substrate and comprising a plurality of memory cells arranged vertically in series; and
a peripheral circuit configured to program the memory cells based on incremental step pulse programming (ISPP), wherein different verification voltages of the ISPP are applied to at least two of the memory cells,
wherein a first verification voltage applied to a first one of the memory cells is smaller than a second verification voltage applied to a second one of the memory cells that is above the first one of the memory cells in the NAND memory string, and
verification voltages applied to each of the memory cells increase from bottom to top of the NAND memory string.

US Pat. No. 10,559,370

SYSTEM AND METHOD FOR IN-SITU PROGRAMMING AND READ OPERATION ADJUSTMENTS IN A NON-VOLATILE MEMORY

SANDISK TECHNOLOGIES LLC,...

10. A system comprising:a memory array comprising a plurality of memory cells;
a plurality of bit lines connected to the plurality of memory cells;
a detection circuit configured to detect a time duration for a bit line voltage of a bit line of the plurality of bit lines to reach a target voltage level of a predetermined threshold voltage level during a pre-charge stage of a program-verify operation;
a timing circuit configured to, during the program-verify operation, determine a bit line settling time period for a verify stage of the program-verify operation corresponding to the detected time duration from a buffer associating a plurality of bit line settling time periods with a plurality of time durations of the pre-charge stage; and
a sense circuit connected to the bit line, the sense circuit configured to, during the verify stage, sense a status of a memory cell coupled to the bit line relative to the bit line settling time period.

US Pat. No. 10,559,369

VOLTAGE DEGRADATION AWARE NAND ARRAY MANAGEMENT

Micron Technology, Inc., ...

1. A controller for memory device, the controller comprising processing circuitry to:record variations in a supply voltage to a component of the memory device;
compute a statistic from at least two of the recorded variations in the supply voltage;
determine a voltage condition for the memory device from the statistic; and
select a set of operational parameters for a non-volatile memory array of the memory device, the set of operation parameters selected from several sets of operation parameters based on the voltage condition.

US Pat. No. 10,559,368

NON-VOLATILE MEMORY WITH COUNTERMEASURES FOR SELECT GATE DISTURB DURING PROGRAM PRE-CHARGE

SanDisk Technologies LLC,...

1. An apparatus, comprising:a select gate control line connected to a first select gate;
a first word line connected to a first memory cell;
a second word line connected to a second memory cell, the second memory cell connected in series with the first memory cell and the first select gate and located adjacent to the first select gate; and
a pre-charge circuit configured to pre-charge a channel coupled to the first select gate, the first memory cell and the second memory cell by concurrently:
biasing the first word line to ground;
driving the second word line at a non-selected pre-charge level above ground; and
driving the select gate control line with a voltage waveform of a plurality of steps increasing from ground to a voltage level higher than the non-selected pre-charge level; and
a programming circuit configured to apply a program pulse to the first word line subsequent to pre-charge the channel.

US Pat. No. 10,559,367

REDUCING PROGRAMMING DISTURBANCE IN MEMORY DEVICES

Micron Technology, Inc., ...

1. A method comprising:precharging channel material of strings of memory cells in both a selected sub-block and an unselected sub-block in a block of memory cells to a precharge voltage during a first portion of a programming operation; and
after precharging the channel material of the strings of memory cells in the selected sub-block and the unselected sub-block, applying a programming voltage to an access line of a selected memory cell in the selected sub-block of the block of memory cells during a second portion of the programing operation,
wherein the selected memory cell in the selected sub-block and an unselected memory cell in the unselected sub-block are coupled to the access line, and
wherein during the second portion of the programing operation, the channel material in the unselected sub-block is charged to a first voltage higher than the precharge voltage in response to a coupled voltage induced on the channel material by the programming voltage on the selected access line of the selected memory cell in the selected sub-block.

US Pat. No. 10,559,366

BOUNDARY WORD LINE VOLTAGE SHIFT

WESTERN DIGITAL TECHNOLOG...

1. An apparatus comprising:an array of non-volatile memory cells; and
a controller configured to:
detect a trigger condition associated with a last programmed word line of a partially programmed erase block of the array of non-volatile memory cells, the last programmed word line comprising programmed non-volatile memory cells that are adjacent to programmed non-volatile memory cells and unprogrammed non-volatile memory cells of the array, the trigger condition comprising detecting that a predetermined amount of time has passed since the read voltage threshold shift for the last programmed word line was determined;
determine a read voltage threshold only for use with the last programmed word line of the partially programmed erase block in response to the trigger condition; and
calculate, dynamically, a read voltage threshold shift only for use with the last programmed word line based on the determined read voltage threshold for the last programmed word line and a baseline read voltage threshold.

US Pat. No. 10,559,365

PEAK CURRENT SUPPRESSION

SanDisk Technologies LLC,...

1. An apparatus comprising:a plurality of solid-state storage elements;
a plurality of control lines coupled to the plurality of solid-state storage elements; and
control circuitry in communication with the plurality of control lines and configured to:
during a first phase of a control line pre-charging stage, charge one or more unselected control lines of the plurality of control lines using a regulated charging current for a period of time based at least in part on a bias variance state associated with the plurality of control lines; and
during a second phase of the control line pre-charging stage, charge the one or more unselected control lines to an inhibit voltage level using an unregulated charging current.

US Pat. No. 10,559,364

MEMORY DEVICE

Toshiba Memory Corporatio...

1. A memory device comprising:a substrate;
a plurality of bit lines above the substrate extending in a first direction and being separated from one another in a second direction above the substrate, the second direction crossing the first direction;
a semiconductor column extending in a third direction between the substrate and one of the bit lines, the third direction crossing the first direction and the second direction;
a first conductive layer on a first side of the semiconductor column in the first direction;
a second conductive layer on a second side of the semiconductor column, opposite to the first conductive layer in the first direction;
a third conductive layer above the first conductive layer and on the first side of the semiconductor column, wherein no conductive layer is between the first and third conductive layers in the third direction;
a fourth conductive layer on the second side of the semiconductor column, opposite to the third conductive layer in the first direction;
a fifth conductive layer above the third conductive layer and on the first side of the semiconductor column; and
a sixth conductive layer above the fourth conductive layer and on the second side of the semiconductor column, opposite to the fifth conductive layer in the first direction, wherein
during reading in which a positive voltage is applied to the one of the bit lines:
a first voltage is applied to the first conductive layer and a second voltage is applied to the second conductive layer;
a third voltage is applied to the third conductive layer and a fourth voltage is applied to the fourth conductive layer;
a fifth voltage is applied to the fifth conductive layer and a sixth voltage is applied to the sixth conductive layer;
the first voltage and the fifth voltage are higher than each of the second voltage and the sixth voltage;
the third voltage is higher than the first voltage, the fourth voltage, and the fifth voltage; and
the fifth voltage is higher than the first voltage.

US Pat. No. 10,559,363

SEMICONDUCTOR MEMORY DEVICE AND METHOD RELATED TO OPERATING THE SEMICONDUCTOR MEMORY DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor memory device comprising:a memory cell array including a plurality of memory blocks;
a peripheral circuit configured to perform a multi-page read operation on a selected memory block among the plurality of memory blocks; and
a control logic configured to control wherein the peripheral circuit to select a first word line and a second word line, both of which are coupled to the selected memory block, and which control the peripheral circuit to perform the multi-page read operation on the first and second word lines;
wherein the peripheral circuit performs the multi-page read operation by applying a read pass voltage to unselected word lines and at substantially the same time that the read pass voltage is applied to unselected word lines, substantially simultaneously applying a read voltage to both the first word line and the second word line;
wherein, data is read from two different memory pages at substantially the same time.

US Pat. No. 10,559,362

NON-VOLATILE MEMORY DEVICE AND A READ METHOD THEREOF

SAMSUNG ELECTRONICS CO., ...

1. A non-volatile memory device, comprising:a page buffer configured to latch a plurality of page data constituting one bit page of a plurality of bit pages, and
a control logic configured to compare results of a plurality of read operations performed in response to a high-priority read signal set to select one of a plurality of read signals included in the high-priority read signal set as a high-priority read signal, and determine a low-priority read signal corresponding to the high-priority read signal, wherein the high-priority read signal set is for reading high-priority page data, and the low-priority read signal is for reading low-priority page data.

US Pat. No. 10,559,361

SEMICONDUCTOR DEVICE AND CONTROL METHOD

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a first semiconductor region;
a stacked body of conductive films arranged in a stacking direction with an insulator interposed;
a semiconductor channel that penetrates the stacked body in the stacking direction, and is electrically connected at one end to the first semiconductor region;
a gate insulating film arranged between the stacked body and the semiconductor channel; and
a control circuit that supplies a first voltage to a closest conductive film of the stacked body to the first semiconductor region, and supplies a second voltage higher than the first voltage to the first semiconductor region, at a time of reading information from one of memory cells formed at positions where the conductive films intersect with the semiconductor channel.

US Pat. No. 10,559,360

APPARATUSES AND METHODS FOR DETERMINING POPULATION COUNT

Micron Technology, Inc., ...

1. An apparatus, comprising:an array of memory cells coupled to sensing circuitry and to a plurality of sense lines;
the sensing circuitry comprising a sense amplifier and a compute component coupled to the plurality of sense lines, wherein the sense amplifier comprises a primary latch and the compute component comprises a secondary latch; and
a controller configured to use the sense amplifier and the compute component to cause:
summing, in parallel and using the primary latch and the secondary latch, of data values corresponding to respective ones of a plurality of vectors stored in memory cells of the array as data value sums representing population counts thereof,
iteratively summing, in parallel and using the primary latch and the secondary latch, of the data value sums corresponding to the plurality of vectors to provide a single data value sum.

US Pat. No. 10,559,359

METHOD FOR REWRITING DATA IN NONVOLATILE MEMORY AND SEMICONDUCTOR DEVICE

LAPIS SEMICONDUCTOR CO., ...

1. A method for rewriting data already written in a nonvolatile memory constituted by a plurality of blocks comprising:data writing step, including receiving incoming data to be written as well as a logical address which indicates a writing destination block, while identifying a vacant block which is unwritten as a temporary storage block among said plurality of blocks when said writing destination block is written, and writing said incoming data to be written into said temporarily storage block; and
managing step, including assigning an index number to a pair of said writing destination block and said temporarily storage block wherein the index number corresponds to the pair, and generating a management table which indicates said index number associating with a physical address indicating a physical position of said temporarily storage block in said nonvolatile memory,
wherein said data writing step, said physical address which corresponds to said index number assigned to said writing destination block is obtained from said management table, and said incoming data to be written is written into said temporary storage block indicated by said physical address.

US Pat. No. 10,559,358

MEMORY DATA RANDOMIZER

INTERNATIONAL BUSINESS MA...

1. A computer program product for initializing a chip having synaptic Non-Volatile Random Access Memory (NVRAM) cells connected row-wise by word lines and column-wise by bit lines, the computer program product comprising a non-transitory computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer to cause the computer to perform a method comprising:driving, on selected word lines from among the word lines, a wave generated by a Phase Locked Loop (PLL) circuit;
generating standing waves from the wave on the selected word lines by implementing a resonance detection point at an input end of each the word lines;
applying a write voltage on all of the bit lines; and
simultaneously driving each of the synaptic NVRAM cells of the selected word lines by different writing currents for different durations in order to set different analog values to all of the synaptic NVRAM cells.

US Pat. No. 10,559,357

MEMORY CIRCUIT HAVING NON-VOLATILE MEMORY CELL AND METHODS OF USING

Lattice Semiconductor Cor...

1. An article of manufacture comprising:a memory circuit comprising:
a programmable volatile memory (VM) cell; and
a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:
a first magnetic tunnel junction (MTJ) device;
a second MTJ device;
a first select device connected with the first MTJ device at a first node;
a second select device connected with the second MTJ device at a second node;
a first pass device connected between the first node and an input node of the VM cell and configured to selectively pass a voltage at the first node to the input node; and
a second pass device connected between the second node and the input node and configured to selectively pass a voltage at the second node to the input node, wherein the first and second select devices are controllable by a common program-enable control signal, and wherein the VM cell is connected to receive the NVM output signal from the NVM cell at the input node and generate an output signal indicative of the program state of the NVM cell.

US Pat. No. 10,559,356

MEMORY CIRCUIT HAVING CONCURRENT WRITES AND METHOD THEREFOR

NXP USA, INC., Austin, T...

1. A memory circuit, comprising:a plurality of memory tiles, each memory tile in the plurality of memory tiles comprising:
a plurality of bit cells, and
a control circuit coupled to the plurality of bit cells, the control circuit configured to provide latched data to the plurality of bit cells during write operations;
a first write control line coupled to a first control circuit in a first memory tile in the plurality of memory tiles, the first write control line configured to receive a first write control signal to initiate a first write operation in the first memory tile; and
a second write control line coupled to a second control circuit in a second memory tile in the plurality of memory tiles, the second write control line configured to receive a second write control signal to initiate a second write operation in the second memory tile and to complete the first write operation, the second write operation initiated after the first write operation is initiated and before the first write operation is completed.

US Pat. No. 10,559,355

DEVICE AND METHOD FOR WRITING DATA TO A RESISTIVE MEMORY

1. A resistive memory comprising resistive elements arranged in rows and in columns, the columns being distributed in groups of columns, the resistance of each resistive element being capable of alternating between a high value in a first range of values and a low value in a second range of values smaller than the high value, the memory further comprising a device for switching, for each group, the resistance of at least one resistive element selected from among the resistive elements of said group between the high and low values, the device comprising a first circuit connected to all columns, configured to provide a first increasing voltage ramp, that is a function linearly increasing with time, and configured to apply the first increasing voltage ramp across each selected resistive element while the selected resistive element is at the high value or at the low value, the device further comprising, for each group, a second circuit configured to detect the switching of the resistance of the selected resistive element, the device further comprising, for each group, a third circuit configured to interrupt a current flowing through the selected resistive element of said group on detection of the switching and the device further comprising a fourth circuit configured to supply a second increasing voltage ramp, that is a function linearly increasing with time, the second circuit being configured to compare the second increasing voltage ramp with a voltage which varies according to the resistance of the selected resistive element, wherein the voltage is proportional to the second voltage ramp with a proportionality factor which varies according to the resistance of the selected resistive element.

US Pat. No. 10,559,354

MEMORY SYSTEM

SK hynix Inc., Gyeonggi-...

1. A memory system, comprising:a first cell array including a plurality of memory cells; and
a second cell array including a plurality of memory cells; and
an address operation circuit suitable for generating a first cell array address, the first cell array address used for accessing at least one first cell in the first cell array, by adding a first value to an address, and generating a second cell array address, the second cell array address used for accessing at least one second cell in the second cell array, by adding a second value to the address.

US Pat. No. 10,559,353

WEIGHT STORAGE USING MEMORY DEVICE

Micron Technology, Inc., ...

1. A device, comprising:a plurality of digit lines;
a plurality of word lines;
a neural memory unit comprising a plurality of memory cells coupled with the plurality of digit lines and the plurality of word lines, the neural memory unit configured to store an analog value, the neural memory unit comprising: a primary memory cell configured to receive a programming pulse during a write operation of the neural memory unit; and
a plurality of secondary memory cells configured to be thermally coupled with the primary memory cell during the write operation, each secondary memory cell being thermally coupled with the primary memory cell according to a thermal relationship, wherein the analog value stored in the neural memory unit is based at least in part on each thermal relationship between the plurality of secondary memory cells and the primary cell.

US Pat. No. 10,559,352

BITLINE-DRIVEN SENSE AMPLIFIER CLOCKING SCHEME

QUALCOMM Incorporated, S...

1. A memory system comprising:a sense amplifier configured to amplify a voltage swing, the sense amplifier electrically coupled to a first bitline and a second bitline associated with a column of a memory array;
a bl transistor electrically coupled to the first bitline, wherein the bl transistor is configured to receive as input a first electrical signal from the first bitline based on the first bitline being discharged; and
a blb transistor electrically coupled to the second bitline, wherein the blb transistor is configured to receive as input a second electrical signal from the second bitline based on the second bitline being discharged, wherein an output of the bl transistor and an output of the blb transistor are electrically coupled together as a common output,
wherein the sense amplifier is configured to receive as an input the common output of the bl transistor and the blb transistor as a sense amplifier enable signal, and wherein the sense amplifier is further configured to measure a voltage differential across the first bitline and the second bitline based on reception of the sense amplifier enable signal.

US Pat. No. 10,559,351

METHODS AND APPARATUS FOR REDUCED AREA CONTROL REGISTER CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:a controller configured to:
receive an address, a first write enable signal, and a first set of data;
provide an internal address based on the address;
provide a register write enable signal and a memory write enable signal based on the first write enable signal; and
provide register data and memory data based on the first set of data;
decode circuitry coupled to:
receive the internal address from the controller; and
receive the register write enable signal from the controller, wherein the decode circuitry is configured to provide a set of register write enable signals based on the register write enable signal and the internal address;
a set of control registers containing control bits for controlling circuitry, the set of control registers coupled to:
receive the set of register write enable signals from the decode circuitry; and
receive the register data from the controller;
a memory for storing data corresponding to the control bits stored in the set of control registers, the memory coupled to:
receive the internal address from the controller;
receive the memory data from the controller; and
receive the memory write enable signal from the controller; and
a data output bus coupled to the memory.

US Pat. No. 10,559,350

MEMORY CIRCUIT AND ELECTRONIC DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A memory circuit comprising:a first inverter circuit including a first input terminal, a first output terminal, a first p-channel MOS transistor in which a source terminal is connected to a first power supply line and a gate terminal is connected to the first input terminal, and a first n-channel MOS transistor in which a source terminal is connected to a second power supply line, a drain terminal is connected to a drain terminal of the first p-channel MOS transistor, and a gate terminal is connected to the first input terminal;
a second inverter circuit including a second input terminal connected to the first output terminal, a second output terminal connected to the first input terminal, a second p-channel MOS transistor in which a source terminal is connected to the first power supply line and a gate terminal is connected to the second input terminal, and a second n-channel MOS transistor in which a source terminal is connected to the second power supply line, a drain terminal is connected to a drain terminal of the second p-channel MOS transistor, and a gate terminal is connected to the second input terminal;
a third n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the first output terminal and the second input terminal, the source terminal is connected to the drain terminal, and a gate terminal is connected to a first wiring line;
a fourth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the other of the source terminal and the drain terminal of the third re-channel MOS transistor, and the other of the source terminal and the drain terminal is connected to a second wiring line, and a gate terminal is connected to a third wiring line;
a fifth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the second output terminal and the first input terminal, the source terminal is connected to the drain terminal, and a gate terminal is connected to the first wiring line; and
a sixth n-channel MOS transistor in which one of a source terminal and a drain terminal is connected to the other of the source terminal and the drain terminal of the fifth n-channel MOS transistor, the other of the source terminal and the drain terminal is connected to a fourth wiring line, and a gate terminal is connected to the third wiring line.

US Pat. No. 10,559,349

POLARIZATION GATE STACK SRAM

Intel Corporation, Santa...

1. An apparatus comprising:a first inverter comprising a first pull up transistor and a first pull down transistor;
a second inverter cross coupled to the first inverter, the second inverter comprising a second pull up transistor and a second pull down transistor;
a first access transistor coupled to the first inverter; and
a second access transistor coupled to the second inverter, a gate stack of one transistor of each inverter comprising a polarization layer between and in contact with a gate oxide and a respective channel of each transistor that comprises the polarization layer.

US Pat. No. 10,559,348

SYSTEM, APPARATUS AND METHOD FOR SIMULTANEOUS READ AND PRECHARGE OF A MEMORY

Intel Corporation, Santa...

1. An apparatus comprising:a memory array having a plurality of memory cells, a plurality of bitlines coupled to the plurality of memory cells, and a plurality of wordlines coupled to the plurality of memory cells; and
a sense amplifier circuit to sense and amplify a value stored in a memory cell of the plurality of memory cells, the sense amplifier circuit including:
a buffer circuit to store the value, the buffer circuit coupled between a first internal node of the sense amplifier circuit and a second internal node of the sense amplifier circuit, the first and second internal nodes separate from a first bitline coupled to the memory cell; and
an equalization circuit to equalize the first internal node and the second internal node while the sense amplifier circuit is decoupled from the memory array.

US Pat. No. 10,559,347

PROCESSING IN MEMORY (PIM) CAPABLE MEMORY DEVICE HAVING TIMING CIRCUITRY TO CONTROL TIMING OF OPERATIONS

Micron Technology, Inc., ...

1. An apparatus, comprising:a plurality of memory components adjacent to and coupled to one another, wherein each of the plurality of memory components comprises a plurality of partitioned banks;
a logic component comprising a plurality of partitioned logic, each partitioned logic coupled to a subset of the plurality of partitioned banks;
wherein each of the plurality of partitioned banks comprises:
an array of memory cells;
sensing circuitry coupled to the array, the sensing circuitry including a sense amplifier and a compute component; and
timing circuitry coupled to the array and sensing circuitry, the timing circuitry configured to control timing of operations for the sensing circuitry; and
wherein each of the plurality of partitioned logic comprises control logic coupled to a plurality of timing circuitries of a respective subset, the control logic configured to execute instructions to cause the sensing circuitry to perform the operations; and
wherein:
the array of memory cells is a dynamic random access memory (DRAM) array; and
the timing circuitry is separate from double data rate (DDR) registers, which are used to control read and write DRAM access requests for the array.

US Pat. No. 10,559,346

BIAS-CONTROLLED BIT-LINE SENSING SCHEME FOR EDRAM

INTERNATIONAL BUSINESS MA...

1. A bit-line sensing circuit for bias-controlled bit-line sensing, the circuit comprising:an input for receiving a single-ended local bit-line signal;
a pass device having a first terminal coupled to the input and a second terminal connected to a global bit-line node;
a first inverter having an input connected to the global bit-line node;
a header circuit coupled to the first inverter, wherein the header circuit includes two or more p-type transistors that are in series and are coupled to a high voltage rail and the first inverter, wherein the two or more p-type transistors receive a common bias signal;
a footer circuit coupled to the first inverter, wherein the footer circuit includes two or more n-type transistors that are in series and are coupled to a low voltage rail and the first inverter, wherein the two or more n-type transistors receive a common bias signal; and
a second inverter having an input coupled to an output of the first inverter.

US Pat. No. 10,559,345

ADDRESS DECODING CIRCUIT PERFORMING A MULTI-BIT SHIFT OPERATION IN A SINGLE CLOCK CYCLE

Amazon Technologies, Inc....

1. An address decoder within an Integrated Circuit (IC) to access an address space, comprising:shifting hardware for receiving a constant first input and a second input associated with a window size of an address region within the address space, the shifting hardware configured to perform a multi-bit shift operation on the constant in one clock cycle to generate a mask signal on mask signal lines, wherein the multi-bit shift operation is configured to shift a number of bit positions in the one clock cycle based on the second input associated with the window size of the address region;
XOR-based logic having a first input coupled to receive a base address of the address region and a second input coupled to receive a transaction address within the address region;
combinatorial logic coupled to the mask signal lines and coupled to an output of the XOR-based logic, wherein an output of the combinatorial logic is configured as an indicator that identifies if the transaction address is within the address region of the address space.

US Pat. No. 10,559,344

HYBRID NON-VOLATILE MEMORY DEVICES WITH STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY AND NON-VOLATILE MEMORY (NVM) ARRAY

Aspiring Sky Co. Limited,...

1. A hybrid memory device, comprising:a static random access memory (SRAM) array having a plurality of SRAM blocks; and
a non-volatile memory (NVM) array having a plurality of NVM blocks, wherein
a portion of the NVM array is configured to be mapped to a plurality of SRAM buffers to store data,
a data exchange between the SRAM array and the NVM array is at bit-level, and
the SRAM buffers are configured as a shareable system SRAM.

US Pat. No. 10,559,343

MEMORY DEVICE WITH A SIGNAL CONTROL MECHANISM

Micron Technology, Inc., ...

1. A memory device, comprising:an internal storage unit configured to store mode data corresponding to an operating speed of the memory device;
a control decoder coupled to the internal storage unit, the control decoder configured to generate a delay control signal based on the mode data; and
an input buffer coupled to the control decoder, the input buffer configured to adjust a delay of an input signal based on the delay control signal, wherein:
the input signal is associated with a timing of a second signal, and
the delay of the input signal is adjusted to maintain the timing when power levels associated with the input signal and the second signal differ.

US Pat. No. 10,559,342

DYNAMIC RANDOM ACCESS MEMORY WITH REDUCED POWER CONSUMPTION

Windbond Electronics Corp...

1. A dynamic random access memory, comprising:a temperature sensor, sensing an operating temperature of the dynamic random access memory;
a dynamic memory cell array;
a control circuit, coupled to the dynamic memory cell array, and accessing and managing the dynamic memory cell array;
a plurality of power supply circuits, supplying power to the dynamic memory cell array and the control circuit; and
a power control circuit, controlling power outputs of the power supply circuits,
wherein when the dynamic random access memory enters a self-refresh mode, the power control circuit selectively switches between a low power control state and a normal power control state according to the operating temperature of the dynamic random access memory,
wherein in case that the dynamic random access memory is in the self-refresh mode, when the operating temperature of the dynamic random access memory is higher than a threshold temperature, the power control circuit is operated in the normal power control state, and when the operating temperature of the dynamic random access memory is lower than the threshold temperature, the power control circuit is operated in the low power control state.

US Pat. No. 10,559,341

METHOD FOR OPERATING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for operating a semiconductor device comprising a CPU core, a first memory cell, and a second memory cell, the method comprising:a first step of writing a first data read by the CPU core from a region where the first data is held to the first memory cell;
a second step of executing a program in the CPU core;
a third step of interrupting the program in the CPU core;
a fourth step of reading a second data from the first memory cell;
a fifth step of comparing the first data read again by the CPU core from the region where the first data is held with the second data in the CPU core so as to determine whether the first data written in the first step deteriorates, and
a sixth step of performing a refresh operation on the first memory cell and the second memory cell and performing the second step,
wherein the second step is performed after the fifth step in the case where the first data matches the second data in the fifth step,
wherein the sixth step is performed after the fifth step in the case where the first data does not match the second data in the fifth step,
wherein the first memory cell comprises a first capacitor, and
wherein the second memory cell comprises a second capacitor.

US Pat. No. 10,559,340

SEMICONDUCTOR DEVICE

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a first buffer circuit configured to generate a first internal chip select signal by buffering a chip select signal in response to a buffer control signal; and
a second buffer circuit configured to generate a second internal chip select signal by buffering the chip select signal in response to the buffer control signal; and
a control circuit configured to generate the buffer control signal by sensing logic levels of a reset signal and the second internal chip select signal, and generate an initialization signal, which is enabled during an initializing operation period, in response to the reset signal and the buffer control signal.

US Pat. No. 10,559,339

PERIPHERY FILL AND LOCALIZED CAPACITANCE

Micron Technology, Inc., ...

1. A memory device, comprising:an array of memory cells that is coupled with a first access line;
a plurality of capacitors each coupled with a plurality of segments of the first access line and each isolated from each memory cell of the array of memory cells; and
circuitry coupled to the array of memory cells and the plurality of capacitors, wherein the array of memory cells and the plurality of capacitors overlie the circuitry.

US Pat. No. 10,559,338

MULTI-BIT CELL READ-OUT TECHNIQUES

Spin Memory, Inc., Fremo...

1. A memory device comprising:an array of Multi-Bit Cells (MBCs), the MBCs including a plurality of cell elements having different sets of state parameter values;
one or more memory circuits configured to;
sequentially apply different successive sets of state programming conditions to a selected plurality of the MBCs, wherein a respective set of state programming conditions programs a corresponding one of the plurality of cell elements to a respective state parameter value;
determine, after applying each of the set of programming conditions, a state change result for the selected plurality of the MBCs; and
determine a read state of the selected plurality of MBCs based on the determined state change results.

US Pat. No. 10,559,337

VERTICAL DECODER

Micron Technology, Inc., ...

1. A memory device, comprising:a substrate;
an array of memory cells coupled with the substrate; and
a decoder coupled with the substrate and configured to apply a voltage to an access line of the array of memory cells as part of an access operation, the decoder comprising:
a first conductive line configured to carry the voltage applied to the access line of the array of memory cells; and
a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction away from a surface of the substrate, the doped material configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

US Pat. No. 10,559,336

STORAGE DEVICE INCLUDING MULTI DATA RATE MEMORY DEVICE AND MEMORY CONTROLLER

Samsung Electronics Co., ...

1. A memory controller configured to control a first storage block operating at a first data rate and a second storage block operating at a second data rate different from the first data rate, the memory controller comprising:a memory interface configured to transceive data signal and a data strobe signal with the first storage block and the second storage block; and
a sub controller including a delay lookup table storing access information including first strobe adjustment timing information defining a first data strobe signal provided to the first storage block, and second strobe adjustment timing information defining a second data strobe signal provided to the second storage block,
wherein the first data strobe signal is provided to the first storage block and the second data strobe signal is provided to the second storage block in a sequential order defined by the access information, and
a signal frequency of the first data strobe signal and a signal frequency of the second data strobe signal are different from each other.

US Pat. No. 10,559,335

METHOD OF TRAINING DRIVE STRENGTH, ODT OF MEMORY DEVICE, COMPUTING SYSTEM PERFORMING THE SAME AND SYSTEM-ON-CHIP PERFORMING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A method of training for a memory device, the method comprising:performing an initialization operation on the memory device based on the memory device being powered on;
performing a training operation on a plurality of operating frequencies of the memory device to obtain, as a configurable operating parameter for each of the plurality of operating frequencies, at least one of a plurality of operating parameters of the memory device;
storing, as training data, the obtained configurable operating parameter for each of the plurality of operating frequencies; and
using an optimized operating parameter for the memory device based on the training data, a current operation mode of the memory device, and a current operating frequency of the memory device.

US Pat. No. 10,559,334

DATA OUTPUT CIRCUIT, MEMORY DEVICE INCLUDING THE DATA OUTPUT CIRCUIT, AND OPERATING METHOD OF THE MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A memory device comprising:a memory cell array configured to store input data;
a clock generator circuit configured to generate first clocks and second clocks, using a reference clock;
a phase information generator circuit configured to compare a phase of the reference clock and a phase of at least one of the first clocks and the second clocks, and to generate phase information as the comparison result;
an intermediate data generator circuit configured to serialize a part of the input data provided from the memory cell array using the first clocks to generate a plurality of first data, to serialize a remaining part of the input data to generate a plurality of second data, and to selectively swap the plurality of first data and the plurality of second data using the phase information to generate a plurality of intermediate data; and
an output data generator circuit configured to serialize the plurality of intermediate data using the second clocks, to output output data through one output data line.

US Pat. No. 10,559,333

MEMORY MACRO AND METHOD OF OPERATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A memory macro comprising:a first memory cell array;
a first tracking circuit comprising:
a first set of memory cells configured as a first set of loading cells responsive to a first set of control signals;
a second set of memory cells configured as a first set of pull-down cells responsive to a second set of control signals, the first set of pull-down cells and the first set of loading cells being configured to track a memory cell of the first memory cell array, the first set of memory cells and the second set of memory cells being arranged in a column of the memory macro; and
a first tracking bit line extending over the column of the memory macro, and being coupled to the first set of memory cells and the second set of memory cells;
a first pre-charge circuit coupled to a first end of the first tracking bit line; and
a second pre-charge circuit coupled to a second end of the first tracking bit line, the second pre-charge circuit and the first pre-charge circuit being configured to charge the first tracking bit line to a pre-charge voltage level responsive to a third set of control signals.

US Pat. No. 10,559,332

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a synthesis control signal generation circuit configured to generate a synthesis control signal for determining a burst sequence from a latch control signal in response to a first burst mode command and a second burst mode command; and
a data output control circuit configured to output data included in a bank group as internal data in response to the synthesis control signal,
wherein the synthesis control signal after a bubble period is set to have the same logic level as the synthesis control signal before the bubble period when the second burst mode command is generated.

US Pat. No. 10,559,331

MEMORY DEVICE AND METHOD OF OPERATING THE SAME

SK hynix Inc., Icheon-si...

1. A memory device, comprising:a memory block including a plurality of word lines;
peripheral circuits configured to perform a verify operation and a discharge operation on memory cells coupled to a selected word line which is selected from among the word lines; and
a control logic configured to control the peripheral circuits such that, during the discharge operation, word lines coupled to memory cells having threshold voltages lower than target threshold voltages and word lines coupled to memory cells having the target threshold voltages are discharged at different times.