US Pat. No. 10,484,129

PROTOCOL LAYER PACKET CODING FOR TRANSMITTER/RECEIVER BUFFER OPTIMIZATION

QUALCOMM Incorporated, S...

1. A method of wireless communication at a transmitting device, comprising:transmitting, to a receiving device, a plurality of data packets;
encoding the plurality of transmitted data packets to generate one or more parity packets, wherein the plurality of data packets are transmitted separate from the one or more parity packets;
storing the one or more parity packets in a retransmission buffer without storing the plurality of data packets in the retransmission buffer; and
transmitting, to the receiving device, the one or more parity packets stored in the retransmission buffer for recovering one or more transmitted data packets not correctly decoded without retransmitting the one or more transmitted data packets not correctly decoded, wherein the plurality of transmitted data packets are encoded at a medium access control (MAC) layer, a radio link control (RLC) layer, or a packet data convergence protocol (PDCP) layer of the transmitting device.

US Pat. No. 10,484,109

TEST ARRANGEMENT AND TEST METHOD

1. A test arrangement for testing a device under test, the test arrangement comprising:a test controller comprising a control interface for interacting with the device under test, said test controller being adapted to control the device under test to perform a predetermined test operation;
a number of impairment devices for applying test impairments to a radio communication link of the device under test;
an impairment memory for storing predetermined impairment conditions; and
an impairment controller communicatively coupled to said number of impairment devices and adapted to control said number of impairment devices to apply the test impairments,
wherein said impairment controller is adapted to apply test impairments to the radio communication link of the device under test based on the predetermined impairment conditions stored in said memory,
wherein said impairment controller is adapted to apply predetermined impairment conditions relating to impairments on a predefined mute or in a predefined geographical area.

US Pat. No. 10,484,089

DRIVER ASSISTED BY CHARGE SHARING

Hewlett Packard Enterpris...

1. A device, comprising:a switch configured to couple a current source with an output terminal upon receipt of a data signal; and
a first variable capacitor coupled in parallel to the current source at a common node on a source terminal of the switch, wherein the first variable capacitor comprises multiple capacitive elements coupled in parallel and configured to be activated by a programmable signal, and wherein the programmable signal is selected to increase a charge transfer rate from an output terminal coupled to a load, when the switch is turned on.

US Pat. No. 10,484,086

OPTICAL BRANCHING UNIT

Neptune Subsea IP Limited...

1. An optical communications apparatus comprising:a branching unit configured to be connected to first, second, and third optical cables, each of the first, second, and third optical cables comprising at least one optical fiber, the branching unit comprising a branch optical path configured to provide a first portion of all signal wavelengths that are input to the branching unit from the at least one optical fiber of the first optical cable to the at least one optical fiber of the third optical cable; and
a switching module comprising at least one optical switch, the at least one optical switch having:
a bypass configuration in which a connection via the branch optical path to a distal portion of the third optical cable is bypassed so that all signal wavelengths input to the branching unit from the at least one optical fiber of the first optical cable are routed to the at least one optical fiber of the second optical cable without first being routed through the connection to the distal portion of the third optical cable; and
a branch connecting configuration in which the branch optical path is enabled so that the first portion of all signal wavelengths that are input to the branching unit from the at least one optical fiber of the first optical cable is routed to the at least one optical fiber of the third optical cable;
wherein the branching unit further comprises:
a first optical coupler configured to provide the first portion of all signal wavelengths input to the branching unit from the at least one optical fiber of the first optical cable to the branch optical path; and
a second optical coupler configured to receive, from the first optical coupler, a second portion of all signal wavelengths input to the branching unit from the at least one optical fiber of the first optical cable;
the second optical coupler also configured to combine (i) the second portion of all signal wavelengths input to the branching unit from the at least one optical fiber of the first optical cable and (ii) signal wavelengths input to the branching unit from the at least one optical fiber of the third optical cable;
the second optical coupler further configured to output the combined signal wavelengths to the at least one optical fiber of the second optical cable.

US Pat. No. 10,484,083

SYSTEMS AND METHODS FOR INTERNET BASED AIRCRAFT COMMUNICATION

ROCKWELL COLLINS, INC., ...

1. An aircraft with Internet based communication, the aircraft comprising:a plurality of communication radios configured to communicate with a ground message manager; and
a processing circuit configured to:
receive a message from a non-Internet system of the aircraft, the non-Internet system associated with a non-Internet communication protocol;
store a conversion table, the conversion table linking a plurality of non-Internet services with a plurality of transport layer port numbers, the conversion table linking each of the plurality of non-Internet services with one of the plurality of transport layer port numbers;
identify, based on the conversion table, a transport layer port number of the plurality of transport layer port numbers, the transport layer port number linked to a non-Internet service, the non-Internet system being a first system of the non-Internet service;
encapsulate the received messages into a transport layer segment with the transport layer port number identifying a non-Internet ground system corresponding to the non-Internet system, the non-Internet ground system being a second system of the non-Internet service;
encapsulate the transport layer segment into an Internet layer packet;
add a protocol identifier to the Internet layer packet, the protocol identifier indicating to the ground message manager that the Internet layer packet is an Internet based message; and
send the Internet layer packet to the ground message manager via the plurality of communication radios to be delivered to the non-Internet ground system via the non-Internet communication protocol.

US Pat. No. 10,484,074

SYSTEMS AND METHODS FOR MAXIMIZING DATA TRANSMISSION RATES IN CONJUNCTION WITH A SPATIAL-MULTIPLEXING TRANSMISSION

Cellium Technologies, LTD...

1. A method for maximizing data transmission rates in conjunction with a spatial-multiplexing transmission, comprising:injecting, in a first room, a plurality of 64-QAM (quadrature-amplitude modulation) or higher modulation signals associated with the spatial-multiplexing transmission into a wire-based medium;
transporting the plurality of signals, via the wire-based medium, to a second room;
power-boosting the plurality of signals in the second room to a power level that is above a certain level per each of the plurality of signals; and
transmitting wirelessly the plurality of signals, which are now power-boosted, into the second room, thereby allowing a receiving wireless device located in the second room to receive the plurality of signals at a combined power level that is above ?50 dBm, thereby allowing the receiving wireless device located in the second room to decode the spatial-multiplexing transmission at 64-QAM or higher modulation, thereby facilitating physical data transmission and decoding rates of above 60 Mbps per each of the signals per a signal bandwidth of 20 MHz.

US Pat. No. 10,484,064

METHOD AND APPARATUS FOR DOWNLINK AND UPLINK CSI ACQUISITION

Samsung Electronics Co., ...

1. A user equipment (UE) comprising:a transceiver configured to receive, from a base station (BS) via radio resource control (RRC) signaling, configuration information including a channel state information (CSI) reporting configuration and a CSI resource configuration,
wherein the CSI reporting configuration includes:
information associated with a CSI reporting type which is one of periodic, semi-persistent, or aperiodic; and
information associated with a set of physical resource blocks (PRBs) for which CSI is reported; and
wherein the CSI resource configuration includes:
information associated with locations of CSI-reference signals (CSI-RSs) in a time domain and a frequency domain; and
information associated with indicating a number of CSI-RS ports; and
a processor operably connected to the transceiver, the processor configured to decode the configuration information and determine CSI based on the CSI reporting configuration and the CSI resource configuration,
wherein the transceiver is further configured to transmit the determined CSI on an uplink (UL) channel.

US Pat. No. 10,484,055

RATE-ADAPTIVE MULTIPLE INPUT/MULTIPLE OUTPUT (MIMO) SYSTEMS

SONY CORPORATION, Tokyo ...

1. A method executed in a first station having a plurality of first station antennas that communicates with a second station having M second station antennas, M>1, the method comprising:receiving, from said second station on a frequency simultaneously, a plurality of frames through two or more of said first station antennas, each frame including a training stream, a payload stream, and a control stream, wherein
respective control streams of said plurality of frames are identical streams and transmitted by transmission diversity through said two or more of said second station antennas.

US Pat. No. 10,484,054

TECHNIQUES AND APPARATUSES FOR PRIORITY-BASED RESOURCE CONFIGURATION

QUALCOMM Incorporated, S...

1. A method for wireless communication performed by a user equipment (UE), comprising:receiving configuration information that signals a first set of resources and a second set of resources,
wherein the configuration information indicates that the first set of resources is associated with high priority transmissions and the second set of resources is associated with low priority transmissions, and
wherein the first set of resources comprises one or more slots reserved for transmissions in one link direction across a plurality of cells, and the second set of resources comprises one or more slots that are not reserved for transmissions in any one link direction across the plurality of cells;
selecting, based at least in part on the configuration information and a priority of a transmission, either the first set of resources or the second set of resources for transmitting the transmission,
wherein the selecting of the first set of resources or the second set of resources is based on latency requirements or reliability requirements of transmissions to be transmitted by the UE; and
transmitting the transmission using the selected set of resources.

US Pat. No. 10,484,053

PROCESSING RADIO-FREQUENCY SIGNALS WITH TUNABLE MATCHING CIRCUITS

SKYWORKS SOLUTIONS, INC.,...

1. A method for processing a radio-frequency (RF) signal, the method comprising:amplifying a first RF signal using a first amplifier disposed along a first path corresponding to a first frequency band;
amplifying a second RF signal using a second amplifier disposed along a second path corresponding to a second frequency band;
generating a first impedance tuning signal in response to a band select signal indicating an in-band frequency band as the first frequency band and an out-of-band frequency band as the second frequency band; and
producing, based on the first impedance tuning signal, a first impedance along the first path, the first impedance configured to increase an in-band metric of the first path for the in-band frequency band and to decrease an out-of-band metric of the first path for the out-of-band frequency band.

US Pat. No. 10,484,051

APPLICATION PROVIDING SYSTEM, PORTABLE TERMINAL DEVICES, SERVER DEVICE, APPLICATION PROVIDING METHOD AND COMPUTER PROGRAMS

FELICA NETWORKS, INC., T...

4. A method comprising:receiving a transmitted message including identification information for identifying an application and parameter information relating to the application to be executed;
determining whether the application corresponding to the identification information exists in a portable terminal device;
generating a request for transmission of the application from a server device to the portable terminal device if the application determination section determines that the application does not exist in the portable terminal device;
storing, in the portable terminal device, the application transmitted by the server device;
executing, in the portable terminal device, the application corresponding to the identification information using the parameter information as input data to the application; and
displaying, on a display section, a result of execution of the application corresponding to the identification information.

US Pat. No. 10,484,033

USER INTERFACE TO ENHANCE MILLIMETER WAVE (MMWAV) COMMUNICATIONS

QUALCOMM Incorporated, S...

1. A method of wireless communication, the method comprising:receiving, by a wireless communication device, information associated with at least one antenna of the wireless communication device indicating that a signal path of the at least one antenna is at least partially blocked by an object; and
outputting, by a user interface of the wireless communication device, an indication that the signal path of the at least one antenna is at least partially blocked, the indication including at least one of a first instruction to rotate the wireless communication device along one or more axes or a second instruction to translate the wireless communication device along one or more axes.

US Pat. No. 10,484,027

GLITCH FREE PHASE SELECTION MULTIPLEXER ENABLING FRACTIONAL FEEDBACK RATIOS IN PHASE LOCKED LOOPS

Qualcomm Incorporated, S...

1. A phase selection multiplexer, comprising:a multiplexer configured to receive a plurality of phases, to select one of the plurality of phases based on a select signal, and to output the selected one of the plurality of phases at an output of the multiplexer;
a flip-flop having a clock input, a data input, and an output, wherein the clock input of the flip-flop is coupled to the output of the multiplexer; and
a gate circuit coupled to the data input of the flip-flop, and also configured to receive the output of the flip-flop and an early output signal generated using another multiplexer, wherein the gate circuit is configured to generate a gate signal based on the output of the flip-flop and the early output signal, and to output the gate signal to the data input of the flip-flop, wherein the gate signal causes the flip-flop to gate the output of the multiplexer during a glitch at the output of the multiplexer.

US Pat. No. 10,484,021

LOG-LIKELIHOOD RATIO PROCESSING FOR LINEAR BLOCK CODE DECODING

XILINX, INC., San Jose, ...

1. A decoder, comprising:a control circuit configured to receive a first sign signal, a second sign signal, a partial sum signal, a function select signal, a third sign signal, and a carry signal as an input vector to provide an output sign signal and a vector select signal;
a select generation circuit configured to receive the first sign signal, the second sign signal, and the partial sum signal to provide an add/subtract select signal;
a subtractor configured to subtract from a first absolute value signal a second absolute value signal to provide the third sign signal and a difference signal;
responsive to the add/subtract select signal, an adder/subtractor configured to either add or subtract the first absolute value signal to or from the second absolute value signal to provide the carry signal and a sum/difference signal; and
a multiplexer configured to select from the first absolute value signal, the second absolute value signal, the difference signal, and the sum/difference signal a selected value signal responsive to the vector select signal.

US Pat. No. 10,484,014

CONTROLLER, SEMICONDUCTOR MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. An operating method of a memory system including a controller and a memory device, the operating method comprising:receiving a message from a host by the controller;
generating a square message matrix of k×k based on the message by the controller;
minimizing a length of each codes included in the square message matrix;
generating an encoded message by the controller which encodes the square message matrix row by row through a Bose-Chadhuri-Hocquenghem (BCH) code; and
storing the encoded message in the memory device; and
obtaining the encoded message in the memory device by the controller for decoding,
wherein the square message matrix includes an upper triangular matrix and a lower triangular matrix, which are symmetrical to each other with reference to zero-padding blocks included in a diagonal direction in the square message matrix,
wherein the upper triangular matrix includes “?” numbers of message blocks, each of which has a size of “?+1”, and “(N??)” numbers of message blocks, each of which has a size of “?”, and
wherein “?”, “?” and N have relationships represented by equations

where “M” represents a size of the message input from the host and “N” represents a number of message blocks forming the upper triangular matrix,
wherein the generating of the encoded message includes generating a parity block for each row of the square message matrix, and
wherein each size of the zero-padding blocks is the same as the parity block.

US Pat. No. 10,484,010

APPARATUS AND METHOD FOR CHANNEL ENCODING/DECODING IN COMMUNICATION OR BROADCASTING SYSTEM

Samsung Electronics Co., ...

1. A method for channel encoding in a communication system, the method comprising:identifying a number of input bits;
identifying a block size based on the number of the input bits;
identifying a code block including at least a part of the input bits based on the block size; and
encoding the code block based at least in part on a parity check matrix corresponding to the block size,
wherein at least a part of the parity check matrix is identified based on following values,
{250 69 226 159 100 10 59 229 110 191 9 195 23 190 35 239 31 1 0}
{2 239 117 124 71 222 104 173 220 102 109 132 142 155 255 28 0 0 0}
{106 111 185 63 117 93 229 177 95 39 142 225 225 245 205 251 117 0 0}
{121 89 84 20 150 131 243 136 86 246 219 211 240 76 244 144 12 1 0}.

US Pat. No. 10,483,992

VOLTAGE CONTROLLED OSCILLATOR USING VARIABLE CAPACITOR AND PHASE LOCKED LOOP USING THE SAME

Samsung Electronics Co., ...

1. A variable capacitor comprising:a capacitor bank comprising a plurality of capacitor segments; and
a plurality of switch segments configured to control connection states of each of the plurality of capacitor segments,
wherein the capacitor bank provides a capacitance from a set of candidate capacitances based on the connection states,
wherein the connection states are controlled based on a control code,
wherein the capacitance provided by the capacitor bank is linearly changed on a log scale by linearly increasing a value of the control code,
wherein the candidate capacitances form a geometric series with a constant ratio between successive candidate capacitances, and
wherein the constant ratio is related to a quantity of the switch segments in the capacitor bank.

US Pat. No. 10,483,989

PHASE-LOCKED LOOP, PHASE-LOCKING METHOD, AND COMMUNICATION UNIT

Sony Semiconductor Soluti...

1. A phase-locked loop comprising:a detector that detects at least transition of an input clock signal;
an oscillator that generates a clock signal having a frequency corresponding to a first control signal, and changes a phase of the clock signal on a basis of a detection result in the detector, wherein the basic of the detection result comprises a pulse signal;
an adjuster that adjusts a phase difference between a phase of the input clock signal and the phase of the clock signal depending on a second control signal; and
a controller that compares the phase of the input clock signal and the phase of the clock signal at a plurality of comparison timings, and generates the first control signal and the second control signal on a basis of a result of the comparison.

US Pat. No. 10,483,986

PHASE ALIGNING PHASE LOCKED LOOP (PLL) CIRCUIT

ROCKWELL COLLINS, INC., ...

1. A signal phase aligning system, the system comprising:a signal generator configured to generate a signal;
a phase locked loop circuit configured to generate a phase locked loop signal based on the signal generated by the signal generator, wherein the phase locked loop circuit comprises:
a phase detector circuit configured to generate a voltage signal, wherein a value of the voltage signal is based on a relative difference in phase between the phase locked loop signal and the signal generated by the signal generator;
a loop filter configured to receive the voltage signal of the phase detector circuit as an input and generate a filtered signal as a loop filter output based on the voltage signal; and
a voltage controlled oscillator, wherein the voltage controlled oscillator is configured to generate the phase locked loop signal at a frequency proportional to a voltage of the filtered signal, the phase locked loop signal generated as a voltage controlled oscillator output of the voltage controlled oscillator; and
a phase aligning circuit configured to align a phase locked loop signal phase of the phase locked loop signal with a signal phase of the signal generated by the signal generator, wherein the phase aligning circuit is configured to receive a control input, wherein the phase aligning circuit receives the filtered signal as the control input, wherein the phase aligning circuit is configured to shift the phase locked loop signal phase of the phase locked loop signal based on the control input, wherein the phase aligning circuit comprises a phase shifter configured to generate a shifted signal as a phase shifter output based on the phase locked loop signal output by the voltage controlled oscillator, wherein the voltage controlled oscillator output of the voltage controlled oscillator and the loop filter output of the loop filter are both inputs to the phase shifter.

US Pat. No. 10,483,983

CLOCK GENERATING CIRCUIT AND SIGNAL PROCESSING DEVICE

NIHON DEMPA KOGYO CO., LT...

1. A clock generating circuit, comprising:a dividing unit that divides a reference clock to generate a divided clock, the divided clock having a frequency of 1/N times of a frequency of the reference clock, where N is an integer of two or more; and
a distribution unit that distributes the reference clock to a first route and a second route, the first route including an output terminal that outputs a clock with a frequency identical to the frequency of the reference clock, the second route including the dividing unit,
wherein the dividing unit comprises:
one or more amplifiers;
one or more dividing circuits; and
a correction circuit, disposed between the amplifier and the dividing circuit, the correction circuit corrects a level of an input clock input to the dividing circuit.

US Pat. No. 10,483,977

LEVEL SHIFTER

TEXAS INSTRUMENTS INCORPO...

1. A level shifter circuit, comprising:a high voltage latch circuit comprising:
a non-inverting output terminal;
an inverting output terminal;
a high state trigger input terminal; and
a low state trigger input terminal;
a low voltage latch circuit coupled to the high voltage latch circuit, and comprising:
a high state trigger input terminal coupled to the inverting output terminal of the high voltage latch circuit; and
a low state trigger input terminal coupled to the non-inverting output terminal of the high voltage latch circuit;
a high state pulse generator coupled to the high state trigger input terminal of the high voltage latch circuit; and
a low state pulse generator coupled to the low state trigger input terminal of the high voltage latch circuit.

US Pat. No. 10,483,954

CLOCK GENERATION CIRCUIT AND CHARGE PUMPING SYSTEM

TAIWAN SEMICONDUCTOR MANU...

1. A clock generation circuit comprising:a two-phase clock generation circuit configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal;
an inverter configured to generate the inverted clock signal based on an input clock signal; and
a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal, the delay circuit having a predetermined delay sufficient to induce symmetry in the first phase clock signal relative to the second phase clock signal such that durational midpoints of overlapping opposite phases of the first and second phase clock signals are substantially aligned; and
wherein:
the inverter includes a first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor being coupled in series, gates of the first P-type transistor and the first N-type transistor being coupled with an input terminal of the inverter, and drains of the first P-type transistor and the first N-type transistor being coupled with an output terminal of the inverter;
the delay circuit includes a second P-type transistor and a second N-type transistor, the second P-type transistor and the second N-type transistor being coupled in parallel between input and output terminals of the delay circuit;
the first P-type transistor has a first channel width versus channel length (W/L) ratio;
the first N-type transistor has a second ratio; and
at least one of the following conditions is true:
the second P-type transistor having a third W/L ratio less than the first W/L ratio; or
the second N-type transistor having a fourth W/L ratio less than the second W/L ratio.

US Pat. No. 10,483,945

SWITCHED CAPACITOR BASED DIGITAL STEP ATTENUATOR

TEXAS INSTRUMENTS INCORPO...

13. A computing device comprising:a processing unit;
a memory module coupled to the processing unit; and
an RF receiver coupled to the processing unit and the memory module, the RF receiver further comprising:
an input driver configured to receive a coarse signal, and configured to generate an input signal;
a digital step attenuator (DSA) coupled to the input driver and configured to receive the input signal; and
an analog to digital converter (ADC) coupled to the DSA, wherein the DSA further comprises:
a serial capacitor coupled to the input driver; and
a sampling capacitor coupled to the ADC.

US Pat. No. 10,483,941

ACOUSTIC WAVE DEVICE AND METHOD OF MANUFACTURING THE SAME

TAIYO YUDEN CO., LTD., T...

1. An acoustic wave device comprising:a single piezoelectric substrate;
an IDT that is formed on the single piezoelectric substrate and includes a pair of comb-shaped electrodes facing each other, each of the pair of comb-shaped electrodes including a grating electrode that excites an acoustic wave and a bus bar to which the grating electrode is connected; and
reforming regions that are located only inside the single piezoelectric substrate and arranged at intervals each other under the IDT, and in which a material of the single piezoelectric substrate is reformed,
wherein the reforming regions have an amorphous structure.

US Pat. No. 10,483,939

DOWNHOLE LOGGING TOOL USING RESONANT CAVITY ANTENNAS WITH REAL-TIME IMPEDANCE MATCHING

Halliburton Energy Servic...

1. A system for real-time impedance matching comprising:a transmit cavity antenna that transmits signals through a subsurface formation;
an impedance-matching circuit comprising a variable inductor or a variable capacitor, wherein the impedance-matching circuit comprises three single pole triple throw switches, one throw on each switch coupled to a variable inductor, and another throw on each switch coupled to a variable capacitor;
a cable that routes signals within the system; and
a processor that:
measures a reflection of a signal transmitted through the formation;
determines a target impedance based on the impedance of the cable and the reflection; and
adjusts the at least one variable inductor or capacitor such that the impedance of the matching circuit substantially equals the target impedance.

US Pat. No. 10,483,937

TRANSCEIVER CIRCUIT AND CONFIGURATION METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A transceiver circuit, comprising:a substrate;
a signal coupler configured on the substrate and comprising a coiled first conductive layer pattern; and
a notch filter configured on the substrate and comprising a coiled second conductive layer pattern;
wherein each of the coiled first conductive layer pattern and the coiled second conductive layer pattern is arranged as a substantially symmetrical pattern with respect to a first virtual axis;
wherein the coiled first conductive layer pattern is arranged as a substantially circular pattern and the coiled second conductive layer pattern is arranged as a substantially two-circle pattern;
wherein the substantially two-circle pattern comprises two circle patterns disposed apart from and adjacent to each other.

US Pat. No. 10,483,934

AUDIO LEVELING AND ENHANCEMENT DEVICE

1. A device for audio leveling and sound enhancement, which comprises:(a) a housing having an input port for receiving an original inputted digital audio or audio-visual signal from a source and an output port for transmitting the signal from the device to a receiving device;
(b) an audio leveler disposed within the housing and including;
(1) an input port in electrical communication with the housing input port;
(2) means for leveling the original input signal from the source;
(3) an output port for outputting the leveled original input signal;
(c) means for enhancing the original input signal received from the source the means for enhancing including;
(1) an input port for receiving the outputted leveled original input signal from the audio leveler; and
(2) an output port in electrical communication with the output port of the housing; and
(3) means for layering the inputted original signal received from the audio leveler, with at least one exact duplicate of the original input signal.

US Pat. No. 10,483,923

AMPLFIERS AND RELATED INTEGRATED CIRCUITS

NXP USA, Inc., Austin, T...

1. An amplifier circuit comprising:a first transistor die having a silicon-based transistor, a first die input, and a first die output, wherein the first die input receives a first portion of a radio frequency (RF) input signal, and the silicon-based transistor amplifies the first portion of the RF input signal and provides an amplified first portion of the RF input signal at the first die output;
first impedance matching circuitry coupled between the first die output and a first circuit output, wherein the first impedance matching circuitry comprises a high-pass impedance matching circuit topology that receives the amplified first portion of the RF input signal and produces a first output signal at the first circuit output, wherein the first impedance matching circuitry includes
a first inductive element coupled between a first node and the first circuit output, the first node being coupled to the first die output,
a second inductive element coupled to the first node, and
a first capacitive element coupled between the second inductive element and a ground reference voltage node, such that the second inductive element and the first capacitive element are configured electrically in series between the first node and the ground reference voltage node;
a second transistor die having a gallium nitride transistor, a second die input, and a second die output, wherein the second die input receives a second portion of the RF input signal, and the gallium nitride transistor amplifies the second portion of the RF input signal and provides an amplified second portion of the RF signal at the second die output; and
second impedance matching circuitry coupled between the second die output and a second circuit output, wherein the second impedance matching circuitry comprises a low-pass impedance matching circuit topology that receives the amplified second portion of the RF input signal and produces a second output signal at the second circuit output, wherein the second impedance matching circuitry includes
a third inductive element coupled between the second die output and a second node,
a fourth inductive element coupled between the second node and the second circuit output, and
a second capacitive element coupled between the second node and the ground reference voltage node.

US Pat. No. 10,483,920

RIPPLE REDUCTION FILTER FOR CHOPPED AMPLIFIERS

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:a chopped amplifier comprising an input terminal, an offset correction terminal, and an output terminal, the chopped amplifier comprising:
a modulator comprising an input terminal and an output terminal, the input terminal of the modulator coupled to the input terminal of the chopped amplifier,
an amplifier stage comprising an input terminal, an offset correction terminal, and an output terminal, the input terminal of the amplifier stage coupled to the output terminal of the modulator, the offset correction terminal of the amplifier stage coupled to the offset correction terminal of the chopped amplifier, and
a demodulator comprising an input terminal and an output terminal, the input terminal of the demodulator coupled to the output terminal of the amplifier stage and the output terminal of the demodulator coupled to the output terminal of the chopped amplifier; and
a ripple reduction filter comprising an input terminal and an output terminal, the input terminal of the ripple reduction filter coupled to the output terminal of the chopped amplifier and the output terminal of the ripple reduction filter coupled to the offset correction terminal of the chopped amplifier;
wherein the output terminal of the ripple reduction filter generates a DC signal;
wherein the ripple reduction filter further comprises:
a bandpass filter comprising an input terminal and an output terminal, the input terminal of the bandpass filter coupled to the input terminal of the ripple reduction filter; and
an amplitude limiter comprising an input terminal and an output terminal, the input terminal of the amplitude limiter coupled to the output terminal of the bandpass filter and the output terminal of the amplitude limiter coupled to the output terminal of the ripple reduction filter.

US Pat. No. 10,483,913

LOW POWER CRYSTAL OSCILLATOR

QUALCOMM Incorporated, S...

1. A circuit, comprising:a first transistor;
a current source for driving a drain of the first transistor with a bias current;
a first decoupling capacitor for isolating a direct current (DC) drain voltage for the first transistor from a DC gate voltage for the first transistor, wherein a gate of the first transistor is configured to be biased by an AC input voltage from a crystal through the first decoupling capacitor;
a first inverter configured to invert a voltage at a terminal of the first decoupling capacitor;
a second inverter configured to invert an output signal from the first inverter to provide an output voltage for the circuit;
an operational amplifier configured to further bias the gate of the first transistor responsive to a comparison between the DC drain voltage and a reference voltage to regulate the DC drain voltage to equal the reference voltage; and
a reference inverter including a reference PMOS transistor having a source connected to a power supply node for supplying a power supply voltage, a reference NMOS transistor having a source connected to ground and having a drain connected to a drain of the reference PMOS transistor, and a reference resistor connected between the drain of the reference NMOS transistor and a reference node for supplying the reference voltage, wherein the reference node is connected to a gate of the reference PMOS transistor and to a gate of the reference NMOS transistor, and wherein the reference inverter is matched to the first inverter and to the second inverter.

US Pat. No. 10,483,912

NON-INVERTING MULTI-MODE OSCILLATOR

1. An oscillator circuit, comprising:a non-inverting sustaining amplifier, the non-inverting sustaining amplifier comprises an amplifier input and an amplifier output; and
a feedback network, the feedback network comprises:
a crystal, the crystal of the feedback network connected between the amplifier input and the amplifier output of the non-inverting sustaining amplifier;
an input portion, the input portion connected between the amplifier input and ground, the input portion comprises an inductor, a tank circuit capacitor, and a tank circuit resistor, wherein the inductor forms a first path between the amplifier input and ground, and wherein the tank circuit capacitor and the tank circuit resistor are connected in series and form a second path between the amplifier input and ground, the second path being separate from but parallel to the first path; and
an output portion, the output portion connected between the amplifier output and ground, the output portion comprises a capacitor.

US Pat. No. 10,483,910

MULTIPORT INDUCTORS FOR ENHANCED SIGNAL DISTRIBUTION

Credo Technology Group Li...

1. An integrated circuit comprising:a substrate; and
an inductor having:
multiple loops on said substrate, each loop defining a corresponding dipole, said dipoles summing to zero with two side loop dipoles being equal and arranged symmetrically relative to a center loop dipole;
a drive port on an outer perimeter of the inductor; and
a sense port connected to taps on the outer perimeter, the sense port positioned diametrically opposite the drive port.

US Pat. No. 10,483,903

CONTROL DEVICE OF HOME ENERGY MANAGEMENT SYSTEM

LG ELECTRONICS INC., Seo...

1. A control device of a home energy management system (HEMS) having a plurality of home appliances, the control device comprising:a communication interface connected to an HEMS gateway;
a storage configured to store first information on power consumption of each of the home appliances connected to the HEMS gateway and second information in which each of the home appliances is used for each time zone; and
a controller configured to:
predict a power generation amount as a time-based power generation amount of a photovoltaic (PV) module connected to the HEMS gateway for time zones within a predetermined period,
set, based on the second information, priorities of the home appliances differently according to the time zone,
classify, for each time zone, at least one of the home appliances as an operable device on the basis of the predicted power generation amount, the first information, and the set priority,
generate, based on the classifying result, an operation schedule of each of the home appliances for the time zones, and
control an operation of each of the home appliances on the basis of the generated operation schedule.

US Pat. No. 10,483,897

SWITCHED RELUCTANCE MOTOR SYSTEM, AND METHOD OF CONTROLLING SWITCHED RELUCTANCE MOTOR SYSTEM

TOYOTA JIDOSHA KABUSHII K...

1. A switched reluctance motor system comprising:a switched reluctance motor;
a rotor including a plurality of salient poles;
a stator including a plurality of salient poles;
coils of three phases wound around the salient poles of the stator; and
an electronic control unit configured to drive the switched reluctance motor in a pole configuration pattern in which the salient poles of the stator that have different polarities are alternately arranged,
the electronic control unit being configured to perform current waveform control when an excitation sound frequency of a given order coincides with a resonance frequency of the switched reluctance motor, the given order being at least one of an order that is a least common multiple of the number of the salient poles of the stator and the number of salient poles of the rotor, and an order that is an integral multiple of a product of the number of the salient poles of the rotor and the number of phases of the coils, the current waveform control being a control that controls current waveforms produced when current is passed through the coils of the three phases, such that a current waveform in the coils of at least one phase has a different shape from a current waveform in the coils of another phase.

US Pat. No. 10,483,887

GAS TURBINE GENERATOR TEMPERATURE DC TO DC CONVERTER CONTROL SYSTEM

Rolls-Royce North America...

1. A system comprising:a gas turbine operable at a rated constant speed to rotate an output shaft;
a temperature sensor configured to output a temperature signal indicative of an operational temperature of the gas turbine;
a generator rotatably coupled with the output shaft and operable to output electric power;
a DC to DC converter configured to receive electric power from the generator, the DC to DC converter coupled with a load bus;
an energy storage device coupled with the load bus; and
a controller configured to receive the temperature signal and dynamically adjust a demand output of the DC to DC converter in response to the operational temperature of the gas turbine, rotating at the rated constant speed, exceeding a predetermined threshold temperature value for a predetermined period of time, the controller configured to dynamically adjust the demand output lower in proportion to a duration of time that the operational temperature exceeds the predetermined threshold temperature value.

US Pat. No. 10,483,883

DRIVING CONTROL METHOD FOR BLDC MOTOR

COAVIS, Sejong-si (KR)

1. A driving control method of a BLDC (Brushless DC) motor, comprising:a step of initial driving command input, comprising initially inputting a driving command to the BLDC motor;
a step of first position alignment, comprising compulsively aligning a rotor of the BLDC motor at a predetermined position;
a step of forced driving, comprising compulsively driving the rotor of the BLDC motor compulsively aligned by accelerating the rotor of the BLDC motor;
a step of driving off, comprising inputting a stop command and blocking current to the BLDC motor; and
after the stop command, a step of second position alignment comprising compulsively aligning the rotor of the BLDC motor at the predetermined position of the step of the first position alignment again using residual current of a BLDC driver.

US Pat. No. 10,483,878

ELECTRO-ADHESION GRIPPERS WITH FRACTAL ELECTRODES

1. An electroadhesion gripper for holding workpieces, comprising:a first electrode and a second electrode that mutually engage, in a plan view of the electrodes,
wherein, at least in a sub-region, the first electrode and the second electrode correspond to border lines of a two-dimensional fractal space-filling curve of a second or higher order, and
wherein the border lines result from enclosing a shape of the space-filling curve on both sides on an auxiliary grid that is offset with respect to a grid of the space-filling curve by half a grid spacing in each grid direction.

US Pat. No. 10,483,876

ELECTROSTATICALLY DEFLECTABLE MICROMECHANICAL DEVICE

1. A micromechanical device comprising:a deflectable element, wherein the deflectable element comprises:
an electrostatic actuator which is implemented as a plate capacitor extending along and spaced apart in a deflection direction from a neutral fiber of the deflectable element,
the capacitor comprising a distal electrode and a proximal electrode, wherein the proximal electrode is arranged between the distal electrode and the neutral fiber and the plate capacitor is subdivided along a direction into segments between which the distal electrode is fixed mechanically at segment boundaries such that the deflectable element, by providing the plate capacitor with a voltage, is deflected along the direction in or opposite to the deflection direction; and
wherein the proximal electrode is arranged at a side of an insulation material of the deflectable element facing the distal electrode and is structured along the direction so as to comprise gaps at the segment boundaries such that the distal electrode is mounted mechanically to the insulation material at the segment boundaries in a manner laterally spaced apart from the proximal electrode.

US Pat. No. 10,483,863

ISOLATED SYNCHRONOUS RECTIFICATION-TYPE DC/DC CONVERTER

ROHM CO., LTD., Tokyo (J...

1. A secondary controller used in an isolated synchronous rectification-type DC/DC converter, comprising:a control output pin to be coupled to a light emitting element of a photocoupler;
a power supply pin to be coupled to receive a power supply voltage;
a control input pin to be coupled to receive a detection voltage corresponding to an output voltage of the DC/DC converter;
a feedback circuit structured to amplify an error between the detection voltage and a reference voltage and to supply a current corresponding to the error to the light emitting element of the photocoupler; and
a power supply path coupled to supply power from the control output pin to the power supply pin.

US Pat. No. 10,483,856

SYSTEMS AND METHODS WITH PREDICTION MECHANISMS FOR SYNCHRONIZATION RECTIFIER CONTROLLERS

On-Bright Electronics (Sh...

10. A system controller for a power converter, the system controller comprising:a first controller terminal; and
a second controller terminal;
wherein the first controller terminal is configured to receive an input signal;
wherein the second controller terminal is configured to output a first drive signal to a first switch to affect a first current associated with a first winding of the power converter, the first drive signal being associated with the input signal;
wherein the system controller is configured to:
detect a first duration of a first time period for a second drive signal, the second drive signal being outputted to a second switch to affect a second current associated with a second winding of the power converter, the second winding being coupled to the first winding, the first time period including a first beginning and a first end;
detect a demagnetization duration of a demagnetization period associated with the first winding, the demagnetization period including a second beginning and a second end;
detect a second duration of a second time period for the second drive signal, the second time period including a third beginning and a third end; and
determine a third duration of a third time period for the first drive signal based at least in part on the first duration, the demagnetization duration, and the second duration, the third time period including a fourth beginning and a fourth end, the fourth end being after the first end, the second end, and the third end;
wherein:
the second switch is closed from the first beginning to the first end;
the second switch is open from the first end to the third beginning; and
the second switch is closed from the third beginning to the third end.

US Pat. No. 10,483,843

APPARATUS AND METHODS FOR MULTI-MODE CHARGE PUMPS

Skyworks Solutions, Inc.,...

1. A multi-mode charge pump comprising:a charge pump output terminal configured to provide a charge pump output voltage that is less than a reference voltage;
a mode control circuit configured to operate the multi-mode charge pump in a selected mode chosen from a plurality of modes including a first mode and a second mode;
a first switched capacitor;
a charge pump filter electrically connected to the charge pump output terminal and having a filter resistance that changes based on the selected mode;
a capacitor charging circuit configured to connect a first end of the first switched capacitor to a charging voltage in a first phase of a clock signal, and to connect the first end of the first switched capacitor to the reference voltage in a second phase of the clock signal, the capacitor charging circuit including a plurality of supply selection switches configured to control the charging voltage with a first supply voltage in the first mode and with a second supply voltage in the second mode; and
a plurality of switches configured to connect a second end of the first switched capacitor to the reference voltage in the first phase, and to connect the second end of the first switched capacitor to the charge pump output terminal in the second phase.

US Pat. No. 10,483,841

MOTOR VEHICLE

TOYOTA JIDOSHA KABUSHIKI ...

1. A motor vehicle, comprising:a motor for driving;
a power storage device;
a first converter connected with a first power line which the motor is connected with, and a second power line which the power storage device is connected with, the first converter including first and second switching elements, first and second diodes and a first reactor and being configured to transmit electric power between the first power line and the second power line through voltage conversion;
a second converter connected with the first power line and a third power line which the power storage device is connected with and which is different from the second power line, the second converter including third and fourth switching elements, third and fourth diodes and a second reactor and being configured to transmit electric power between the first power line and the third power line through voltage conversion; and
a control device configured to perform voltage control of the first converter such that a voltage of the first power line becomes equal to a target voltage and to perform current control of the second converter such that an electric current flowing in the second reactor becomes equal to a target current, wherein
in a process of cancelling shutdown of the second converter during transmission of electric power between the first power line and the second power line through the voltage conversion by the first converter in a shutdown state of the second converter, the control device performs single element switching control that switches on one switching element between the third and the fourth switching elements of the second converter while setting the other switching element off, to prevent the electric current from flowing in the second reactor in reverse to a current flow direction in the first reactor.

US Pat. No. 10,483,832

MULTI-BAR LINKAGE ELECTRIC DRIVE SYSTEM

Indigo Technologies, Inc....

1. An electric drive system comprising:a rotary motor system comprising a hub assembly, a magnetic rotor assembly, a first coil stator assembly, and a second coil stator assembly, wherein the hub assembly defines a rotational axis and wherein each of the magnetic rotor assembly, the first coil stator assembly, and the second coil stator assembly is coaxially aligned with the rotational axis and is capable of rotational movement about the rotational axis; and
a multi-bar linkage mechanism connected to each of the first and second coil stator assemblies and connected to the hub assembly, said multi-bar linkage mechanism constraining movement of the hub assembly so that the rotational axis of the hub assembly moves along a defined path that is in a transverse direction relative to the rotational axis and wherein the multi-bar linkage mechanism causes the rotational axis of the hub assembly to translate along the defined path in response to relative rotation of the first coil stator assembly and the second coil stator assembly with respect to each other,
wherein the multi-bar linkage comprises a first swing arm rotatably coupled to the first stator assembly on a first side of the magnetic rotor assembly, a second swing arm rotatably coupled to the second stator assembly on a second side of the magnetic rotor assembly, and a member parallel to the rotational axis and rotatably coupled to the first swing arm and rotatably coupled to the second swing arm.

US Pat. No. 10,483,827

BUILT-IN CAPACITOR MOTOR STRUCTURE

Sagitta Industrial Corp.,...

1. An improved built-in capacitor motor structure comprising:a housing including a front cover and a rear cover;
a stator portion received in the housing including a core frame, the core frame is provided with an annular insulating frame body, a plurality of circularly arranged docking units extending from the periphery of a side of the insulating frame body;
an insulating member connected on the insulating frame body having an accommodating space in communication with the outside, a capacitor being combined inside the accommodating space of the insulating member, and a plurality of corresponding docking units being provided at the bottom side edge of the insulating member; and
a rotor portion received in the stator portion,
wherein the plurality of corresponding docking units are engaged with the docking units of the insulating frame body, respectively, to connect the insulating member on the insulating frame body.

US Pat. No. 10,483,824

SELF-RELEASING LOCK MECHANISM

Woodward, Inc., Fort Col...

1. A self-releasing lock mechanism configured to lock a driveshaft to mechanical ground, the driveshaft being in mechanical communication with a first end of a rotor of a motor, the motor being disposed in a motor housing having a flange region that is connected to mechanical ground, the self-releasing lock mechanism comprising:a ground lock housing, the ground lock housing configured to surround at least a portion of the motor housing and the ground lock housing including a locking arrangement configured to selectively engage a second end of the rotor;
at least one locking pin that extends from the ground lock housing, the at least one locking pin configured to extend into and pass through the flange region of the motor housing;
a locking plate comprising the driveshaft and at least one locking site, the at least one locking site adapted to selectively receive the at least one locking pin; and
a biasing member disposed between the ground lock housing and the flange region;
wherein the biasing member biases the ground lock housing away from the flange region;
wherein the locking arrangement engages the second end of the rotor to overcome the bias from the biasing member when the at least one locking pin is received in the at least one locking site.

US Pat. No. 10,483,822

MOTOR

NIDEC CORPORATION, Kyoto...

1. A motor comprising:a rotating shaft extending in a central axial direction;
a stator including a core back concentric with the rotating shaft; and
a bracket housing the stator; wherein
the bracket includes a cylindrical bracket main body, and a stator frame which faces the bracket main body and holds an outer surface of the stator on a radially inward side of the bracket main body, the bracket main body and the stator frame being defined by separate members;
the bracket is provided with a cooling passage through which a cooling medium is able to flow, and an inflow port and an outflow port connected with the cooling passage;
the cooling passage includes a first portion provided directly adjacent to a radially outermost surface of the bracket main body, a second portion provided radially between a radially innermost surface of the bracket main body and the stator frame, and a communication passage coupling an output of the first portion and an input of the second portion with each other;
a cooling medium in the first portion and a cooling medium in the second portion flow in opposite circumferential directions with respect to one another;
at least a portion of the communication passage is located at a position which is farther outward in a radial direction than any portion of the second portion such that the communication passage does not overlap a radially inner surface of the second portion when viewed in a direction extending along the communication passage; and
a portion of the communication passage and a portion of the core back overlap one another when viewed from a radial direction which is orthogonal to both the central axial direction and the direction extending along the communication passage.

US Pat. No. 10,483,820

METHOD OF ENCAPSULATING INDUCTION MOTOR STATOR

Shanghai XPT Technology L...

1. An induction motor stator encapsulate method, comprising:arranging a stator of an induction motor in a case of the induction motor, wherein the stator comprises a stator core and a stator winding surrounding the stator core;
filling a first encapsulating material into the case for forming a first insulation layer, wherein the first insulation layer directly covers the stator winding; and
filling a second encapsulating material into the case for forming a second insulation layer, wherein the second insulation layer covers the first insulation layer;
wherein a shrink rate of the first encapsulating material is smaller than a shrink rate of the second encapsulating material.

US Pat. No. 10,483,818

INSULATED WIRE, MOTOR COIL, AND ELECTRICAL OR ELECTRONIC EQUIPMENT

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire, comprising at least one thermosetting resin layer and at least one thermoplastic resin layer in this order, as covering layers, on a conductor having a quadrilateral cross-section,wherein, in each of 4 covering layer portions corresponding to 4 sides of the cross-section of said insulated wire, a difference between the maximum value and the minimum value of a coating thickness is each 20 ?m or less, and in the whole of the above 4 covering layer portions, a value of the maximum value divided by the minimum value of the coating thickness is 1.3 or more.

US Pat. No. 10,483,814

SYNCHRONOUS-GENERATOR POLE STACK

Wobben Properties GmbH, ...

1. A synchronous generator rotor pole pack, comprising:a plurality of pole shoes each comprising a plurality of pole pack segments, wherein each pole pack segment comprises a pole shank portion and a pole head portion, wherein the pole shank portions of the plurality of pole pack segments form a pole shank, wherein the pole head portions of the plurality of pole pack segments form a pole head having at least three pole head sections, wherein a front edge of each of the at least three pole head sections is arranged at an angle with respect to the pole shank, wherein a depth of the pole head portions of the plurality of pole pack segments are identical, wherein the pole head portions of the plurality of pole pack segments are offset with respect to adjacent pole head portions, wherein the segment in an area of the pole shank are not arranged offset with respect to each other, and wherein the pole shank is arranged as a straight continuous portion.

US Pat. No. 10,483,805

DEVICE FOR WIRELESS TRANSMISSION OF DATA AND POWER

KONINKLIJKE PHILIPS N.V.,...

1. A device for wireless transmission of data and power between the device and another device of a system, in particular of a patient monitoring system, said device comprising:an identification unit for storing a unique identifier of the device,
a connector comprising:
a data transmission unit arranged for transmitting data to and/or receiving data from another device of the system having a counterpart connector,
a magnetic coupling unit for transmitting power to and/or receiving power from another device of the system having a counterpart connector by use of inductive coupling, and
a detection unit for detecting the strength of magnetic coupling between the magnetic coupling unit and a magnetic coupling unit of a counterpart connector of another device and for detecting the intensity of data received by the data transmission unit from a data transmission unit of the other device, and
a control unit for controlling the data transmission unit to transmit the unique identifier of the device to the other device and/or to receive the unique identifier of the other device, if i) the detected intensity of received data is above a data intensity threshold and/or its increase is above a data intensity increase threshold and ii) the detected magnetic coupling is above a magnetic coupling threshold and/or its increase is above a magnetic coupling increase threshold,wherein said magnetic coupling unit comprises:a flux concentrator, at least part of which having a U-shaped cross-section forming a recess between the legs of the U,
a first coil arranged within the recess of the flux concentrator, and
a second coil arranged outside of the recess in which the first coil is arranged, andwherein the magnetic coupling unit is arranged to allow stacking of devices upon each other so that the flux concentrator and the first coil of the device and the flux concentrator and a second coil of another device stacked upon the device together form a transformer for inductive power transmission there between and/or the flux concentrator and the second coil of the device and the flux concentrator and a first coil of another device stacked upon the device together form a transformer for inductive power transmission there between.

US Pat. No. 10,483,797

CONTACTLESS CONNECTOR AND CONTACTLESS CONNECTOR SYSTEM

11. A contactless connector system, comprising:a power transmitting connector having a primary inductive coupler connected to an input power source, a resonant circuit generating a magnetic field at the primary inductive coupler, a primary data transceiver, a primary data communication interface connected to the primary data transceiver and communicating with a primary external component, and a primary control unit controlling an operation of the resonant circuit, the primary data communication interface, and the primary data transceiver; and
a power receiving connector having a secondary inductive coupler electromagnetically coupled with the primary inductive coupler, the secondary inductive coupler receiving electric power from the primary inductive coupler, a terminal connected to a secondary external component, outputting the electric power to the secondary external component, and receiving power from an external power source different from the power transmitting connector connected to the terminal to supply power to the power receiving connector, a switch connected to the terminal and controlling the electric power output at the terminal, a secondary data transceiver forming a data link with the primary data transceiver, and a secondary data communication interface connected to the secondary data transceiver and communicating with the secondary external component, the secondary external component and the external power source are external to a structure of the power receiving connector containing the secondary inductive coupler, the switch, the secondary data transceiver, and the secondary data communication interface.

US Pat. No. 10,483,786

WIRELESS CHARGING SYSTEMS WITH MULTICOIL RECEIVERS

Apple Inc., Cupertino, C...

1. A portable electronic device that is configured to receive wireless power transmitted from an array of tiled transmitting coils in a wireless power transmitting device, wherein the tiled transmitting coils are characterized by a center-to-center spacing, the portable electronic device comprising:a battery; and
wireless power receiving circuitry that includes an array of wireless power receiving coils and that includes rectifier circuitry that is configured to rectify alternating-current wireless power signals received by the array of wireless power receiving coils and to provide a corresponding direct-current voltage to the battery, wherein the wireless power receiving coils are laterally spaced from each other in a two-dimensional array, and wherein first, second, and third wireless power receiving coils of the array of wireless power receiving coils are respectively aligned with first, second, and third vertices of an equilateral triangle that has sides with lengths equal to half of the center-to-center spacing.

US Pat. No. 10,483,771

SYSTEMS AND METHODS FOR HYBRID ENERGY HARVESTING FOR TRANSACTION CARDS

Capital One Services, LLC...

1. A transaction card, comprising:a data storage device configured to supply account information to a transaction card terminal;
a first rechargeable power source configured to receive charging energy from the transaction card terminal during a transaction using the card;
a second rechargeable power source configured to receive energy from only the first rechargeable power source; and
a power controller configured to:
determine whether the second rechargeable power source requires recharging;
control a flow of energy from the first rechargeable power source to the second rechargeable power source; and
determine, in response to a request associated with the transaction, whether the transaction card has sufficient power to complete the transaction prior to conducting the transaction.

US Pat. No. 10,483,754

FAULT DETECTION AND LOCATION IN NESTED MICROGRIDS

ABB Schweiz AG, Baden (C...

1. A microgrid comprising:a plurality of switching devices;
a plurality of distribution line segments, each distribution line segment coupled to at least one switching device of the plurality of switching devices;
a plurality of measuring devices, each measuring device corresponding to one of the plurality of switching devices; and
at least one distributed energy resource (DER) coupled to one of the plurality of distribution line segments;
a network controller configured to:
receive measurements from the plurality of measurement devices,
determine a fault is occurring within the microgrid using the measurements,
assign a topology classification to each of the plurality of distribution line segments based on whether a load or a DER is coupled to the distribution line segment following the determining a fault is occurring,
assign a proximity classification to said each of the plurality of distribution line segments based on whether a fault current may flow through the distribution line segment in one direction or two directions following the determining a fault is occurring,
determine fault location using the topology classification and the proximity classification, and
isolate the fault by transmitting open commands at least one of the plurality of switching devices closest to the fault.

US Pat. No. 10,483,750

SELECTIVE CIRCUIT BREAKER

EATON INTELLIGENT POWER L...

1. A selective circuit breaker, in operation connectable between a main supply line and a downstream circuit breaker, the selective circuit breaker comprising:a bypass switch in a supply line;
a controlled semiconductor switch connected in parallel to the bypass switch;
a bypass switch off detection circuitry; and
a short circuit detection circuitry configured to control the bypass switch and the controlled semiconductor switch in accordance with a switching characteristic,
wherein the switching characteristic is programmable,
wherein a short circuit current rating of the selective circuit breaker is substantially equal to a short circuit current rating of a downstream circuit breaker,
wherein the selective circuit breaker is operable in a normal operating mode or in a system limit selectivity mode,
wherein in the normal operating mode the selective circuit breaker is programmed to disconnect later than the downstream circuit breaker, and
wherein in the system limit selectivity mode the selective circuit breaker is programmed to apply a reconnect attempt.

US Pat. No. 10,483,747

DETECTION OF AN ELECTRIC POWER SYSTEM FAULT DIRECTION USING TRAVELING WAVES

Schweitzer Engineering La...

13. A method for detecting a fault in an electric power delivery system, comprising:receiving a plurality of representations of electrical conditions associated with at least a portion of the electric power delivery system;
detecting a traveling wave event based on the plurality of representations of electrical conditions;
calculating an energy value of the traveling wave event during an accumulation period based on the detection of the traveling wave;
determining a maximum energy value and a minimum energy value of the energy value during the accumulation period;
determining a fault direction based on the maximum energy value and the minimum energy value;
declaring the fault based on the determined fault direction; and
implementing a protective action based on the declaration of the fault.

US Pat. No. 10,483,745

METHODS OF MAKING MOISTURE-RESISTANT DOWNHOLE ELECTRICAL FEEDTHROUGHS

1. A method of forming a downhole electrical feedthrough package, the method comprising:combining at least two of the four components selected from Bi2O3, B2O3, MO, and optionally REO to form a glass mixture;
heating the glass mixture to approximately 650 to 1400 degrees Celsius;
quenching the heated glass mixture in de-ionized water bath to form glass frits;
sintering the glass frits with hollow cylinder shape and fitted into a conduit of a metal shell to form an electrical feedthrough assembly;
firing the electrical feedthrough assembly at first temperature (T1) for a first time period to form a dielectric seal and to provide a first thermal energy to the dielectric seal;
heating the electrical feedthrough assembly at second temperature (T2) for a second time period to provide a second thermal energy to the dielectric seal;
cooling the dielectric seal of the electrical feedthrough assembly to ambient temperature for a third time period; and
integrating two isolators into the conduit so that the dielectric seal is in contact with at least one of the isolators.

US Pat. No. 10,483,743

CABLE HOLDING DEVICE

PANASONIC INTELLECTUAL PR...

1. A cable holding device for holding a cable, comprising:a first member that has a first through hole through which the cable is to pass;
a second member that has a second through hole through which the cable is to pass; and
a fixing screw that fixes the second member to the first member in such a condition that the second through hole partially overlaps the first through hole to hold the cable by an inner periphery of the first through hole and an inner periphery of the second through hole,
wherein the second member is moved relative to the first member by a rotation of the fixing screw,
wherein the first member comprises a guide tab,
wherein the second member comprises a slide lever,
wherein the guide tab and the slide lever each extend in an axial direction of the cable, and
wherein a screw through hole through which the fixing screw is to pass is formed in one of the guide tab of the first member and the slide lever of the second member, and a female threaded hole, which is to engage with the fixing screw, is formed in another of the guide tab of the first member and the slide lever of the second member.

US Pat. No. 10,483,739

TEMPORARY WIRING PORTAL ASSEMBLY

1. A temporary wiring portal assembly being configured to inhibit finish wiring from being covered during drywall installation, said assembly comprising:a wall stud having a lateral surface and a front surface, said front surface having drywall being positioned thereon;
a junction box being removably fastened to said wall stud prior to installing drywall, said junction box having an input port and an output port, said junction box having a conductor extending into said input port and out of said output port; and
a tube being removably coupled to said output port, said tube having a length of at least 10.0 cm such that said tube extends outwardly beyond said front surface of said wall stud when said junction box is removably fastened to said wall stud, said tube requiring the drywall be installed around said tube when the drywall is fastened to said front surface of said wall stud thereby inhibiting the conductor from being covered by the drywall, wherein said tube is removed from said output port when the drywall is installed thereby facilitating the conductor to be accessible for trim installation.

US Pat. No. 10,483,735

NINETY DEGREE SNAP FIT ELECTRICAL FITTING FOR CONNECTION OF ELECTRICAL CABLES TO AN ELECTRICAL BOX

ARLINGTON INDUSTRIES, INC...

1. A snap fit electrical fitting, comprises:a one-piece connector body including a sidewall, a leading end having a circular outlet bore with an outlet axis, and a trailing end having a circular inlet bore with an inlet axis, said inlet axis and said outlet axis are at an angle to one another;
a leading flange extending around the periphery of said leading end of said connector body and a trailing flange between said leading end and said trailing end of said connector body;
said sidewall at said trailing end including a straight sidewall portion including a first inlet chamber and a second inlet chamber, said second inlet chamber including an inner periphery and an interior end;
a cylindrical sidewall portion extending from said straight wall portion to said leading end;
an internal shoulder is between said straight sidewall portion and said cylindrical sidewall portion;
an outer flange is between said trailing flange and said internal shoulder, said outer flange extending from said cylindrical sidewall portion of said connector body;
an outside bend and an inside bend of said connector body;
said angle between said inlet bore and said outlet bore is between 60 and 120 degrees;
a reduced-diameter seat has a constant diameter, and is on said leading end of said connector body, said seat extending from said leading flange to said trailing flange;
a snap ring is disposed on said seat;
an internal snap ring is within said first inlet chamber of said connector body;
a pusher tang is on said inside bend of said snap fit electrical fitting;
said pusher tang directing a cable inserted within said inlet bore toward said outside bend of said connector body; and
axially aligned openings extending through the sidewall on the second inlet chamber of the connector body, wherein the axially aligned openings are substantially orthogonal to a part of the straight side wall portion connecting to the outside bend.

US Pat. No. 10,483,726

POWER PEDESTAL WITH SKELETON TOWER ASSEMBLY AND COOPERATING OUTER SLEEVE AND RELATED METHODS

Eaton Intelligent Power L...

17. A power pedestal, comprising:a skeleton tower assembly comprising a skeleton tower frame that supports a first wall panel, the first panel comprising a plurality of power receptacles; and
an outer sleeve coupled to the skeleton tower frame,
wherein the outer sleeve terminates adjacent the first wall panel with the plurality of power receptacles facing outward and externally accessible, and
wherein the first wall panel resides at an angle from vertical that is in a range of about 10 and about 30 degrees.

US Pat. No. 10,483,707

PLUGGABLE MODULE WITH COAXIAL CONNECTOR INTERFACE

Methode Electronics, Inc....

1. A pluggable module comprising:a housing having a first end and an opposite second end,
an edge connector disposed at the first end,
an F-type coaxial connector at the second end, the F-type coaxial connector electrically connected to the edge connector, the edge connector for pluggably mating the first end of the housing within a host receptable; and
a miniature balun disposed within the module and electrically connected between the F-type coaxial connector and the edge connector, the miniature balun for converting between a single-ended input to a differential load of signal processing component.

US Pat. No. 10,483,705

ELECTRICAL CONNECTOR AND ELECTRICAL CONNECTION ASSEMBLY

Tyco Electronics (Shangha...

1. An electrical connection assembly for electrically connecting any one of a plurality of battery cells in a battery pack to a circuit board, the electrical assembly comprising:one or more electrical connector modules, each electrical connector module comprising:
a first connector comprising a first connecting portion and a first protruding end portion that are integrally connected with each other;
a second connector comprising a second connecting portion and a second protruding end portion that are integrally connected with each other, the second connecting portion being electrically connected to the first connecting portion; and
a retainer integrally interconnected with the first connector and the second connector;
wherein the second connector and the first connector are independently and separately formed elements;
wherein the first protruding end portion is arranged to protrude from the retainer to electrically connect to a first mating connector; and
wherein the second protruding end portion is arranged to protrude from the retainer to electrically connect to a second mating connector;
a support frame having a plurality of mounting grooves, each of the mounting grooves is configured to removably retain one of the one or more electrical connector modules;
wherein the one or more electrical connector modules are removably retained in the plurality of mounting grooves.

US Pat. No. 10,483,702

HIGH SPEED COMMUNICATION JACK

SENTINEL CONNECTOR SYSTEM...

1. A high speed communication jack comprising:a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;
a shielding case surrounding the housing;
a circuit board disposed in part between the shielding case and the housing, wherein the circuit board comprises
a substrate having a first side and a second side opposite the first side,
a plurality of pin vias extending through the substrate where each of the pin vias is configured to accommodate a pin on the housing,
a plurality of traces on the first side of the substrate where each trace extends from a corresponding one of the plurality of pin vias;
a shielding trace layer disposed on the first side of the substrate including a pair of shielding tabs disposed on opposite edges of the first side of the substrate and a shielding trace disposed on the first side of the substrate opposite the first plurality of pin vias where the shielding trace extends between and connects the shielding tabs,
a shielding plane on the second side of the substrate,
a plurality of return vias extending through the substrate with each of the return vias connecting the shielding trace layer and the shielding plane,
wherein, a height, width, length and spacing of at least two traces are adjusted such that an impedance of the at least two traces is substantially the same.

US Pat. No. 10,483,701

ELECTRICAL CONNECTION ASSEMBLY WITH ELECTRICAL CONNECTOR MOUNTED AND OVERMOLDED ON AN ELECTRIC CABLE, ASSOCIATED PRODUCTION METHOD

RAYDIALL, Voiron (FR)

1. Electrical connection assembly comprising:an electric cable comprising:
at least one central conductor;
an electrically insulating outer sheath surrounding the central conductor(s);
an electrical connector comprising:
a housing;
an outer contact (extending along at least one longitudinal axis (X), the outer contact being mounted in the housing;
at least one central contact extending at least along the longitudinal axis (X), the central contact(s) being mounted inside the outer contact with interpositioning of an electrically insulating body, the central contact(s) being provided with at least one portion that is crimped around the bare free end of the central conductor(s) of the cable;
an electrically conductive jacket surrounding the inside of the housing, the central contact(s) and the outer contact at least over the length, along the X axis, of the portion that is crimped around the free crimped end of the central conductor(s), by forming a cavity that is practically or fully closed;
a sealing and mechanical retention joint overmolded both between the jacket and a part of the housing, between the housing part and part of the sheath of the cable, and around said parts.

US Pat. No. 10,483,699

RETRACTABLE CABLE AND CABLE REWIND SPOOL CONFIGURATION

HARMAN PROFESSIONAL, INC,...

1. An apparatus, comprising:a cable spool; and
a drive adaptor configured to turn while a cable is unwound from the cable spool and to lock while the cable spool is rewound.

US Pat. No. 10,483,651

TRANSMIT-ARRAY ANTENNA COMPRISING A MECHANISM FOR REORIENTING THE DIRECTION OF THE BEAM

RADIALL, Aubervillers (F...

1. A transmit-array radiofrequency antenna comprising:a support;
a transmit-array arranged in a transmission plane, the transmit-array comprising a printed circuit and a plurality of basic cells produced in a central zone of the printed circuit,
at least one focal source, fixed on the support and arranged at the focal length from the array;
a displacement mechanism for moving the transmit-array, the mechanism being connected to the support and being adapted to translationally move the transmit-array in at least one of the two directions in the transmission plane, the displacement mechanism being connected to the printed circuit in its peripheral zone;
wherein the displacement mechanism comprises:
two servomotors;
two first pantograph devices, each comprising two deformable parallelograms each formed by four articulation segments connected pairwise by a flexible articulation forming a pivot link and one of the segments of which is common to the two parallelograms,
in which displacement mechanism, the common segment of each of the two first pantograph devices is connected to one of the two servomotors, whereas one of the segments parallel to the common segment is fixed on the printed circuit in its peripheral zone and the other one of the segments parallel to the common segment is fixed on the support, the connection between each of the common segments with one of the two servomotors being carried out such that one of the servomotors may move the common segment of one of the two first devices and hence move the printed circuit in approximately one of the two directions (X) in the transmission plane, whereas the other one of the servomotors may move the common segment of one of the two first devices and hence move the printed circuit in approximately the other one of the two directions (Y) in the transmission plane.

US Pat. No. 10,483,640

OMNIDIRECTIONAL ULTRA-WIDEBAND ANTENNA

King Saud University, Ri...

1. An omnidirectional ultra-wideband antenna, comprising:an electrically conductive conical surface having a vertex end and a base end;
a supplemental radiating element having a first portion and a second portion, the first portion extending from the base end of the electrically conductive conical surface, the first portion being positioned between the base end of the electrically conductive conical surface and the second portion, the first portion being cylindrical and the second portion being frustoconical;
a ground plane plate having opposed first and second surfaces and including a peripheral edge, the vertex end of the electrically conductive conical surface being positioned adjacent to, and spaced apart from, the first surface of the ground plane plate;
at least one electrically conductive rod having opposed first and second ends, the first end of the at least one electrically conductive rod being secured to the second portion of the supplemental radiating element, the second end of the at least one electrically conductive rod being connected to the first surface of the ground plane plate at the peripheral edge;
a coaxial cable having a center conductor and an outer conductor, the center conductor being in electrical communication with the vertex end of the electrically conductive conical surface, and the outer conductor being in electrical communication with the ground plane plate; and
a third radiating element mounted inside the electrically conductive conical surface, wherein the third radiating element is conical and includes a vertex end positioned adjacent the vertex end of the electrically conductive conical surface.

US Pat. No. 10,483,639

COMMUNICATION DEVICE AND ANTENNA ASSEMBLY THEREOF

ASUSTEK COMPUTER INC., T...

1. A communication device, comprising:a metal rim;
a device metal member, disposed in the metal rim; and
an antenna assembly, comprising:
an insulating substrate, disposed between the device metal member and the metal rim;
two electrical coupling portions, disposed at two opposite ends of the insulating substrate and electrically coupled to the device metal member and the metal rim, a sealed slot section is enclosed by the two electrical coupling portions, the device metal member, and the metal rim;
a feeding part, disposed on the insulating substrate and electrically coupled to the metal rim, so as to divide the sealed slot section into a first slot section and a second slot section whose length is less than that of the first slot section, the feeding part is configured to activate resonance modes of the first slot section in a first frequency band and a second frequency band and activate a resonance mode of the second slot section in a third frequency band; and
a feeding signal source, disposed on the insulating substrate, located between the feeding part and the device metal member, and electrically coupled to the feeding part and the device metal member.

US Pat. No. 10,483,634

POSITIVE BATTERY TERMINAL ANTENNA GROUND PLANE

DURACELL U.S. OPERATIONS,...

20. A method, comprising:providing a negative terminal of a primary alkaline battery, comprising a first surface area;
providing a positive terminal of a primary alkaline battery as a ground plane of an antenna, comprising a second surface area greater than the first surface area;
providing an antenna impedance matching circuit;
electrically connecting the antenna impedance matching circuit to the positive terminal of the battery;
electrically connecting the antenna impedance matching circuit to a communication circuit and an antenna; and
calculating data relating to the remaining capacity of the battery including corrections for load on the battery related to transmission and reception of data using the communication circuit, the antenna impedance matching circuit, the antenna, and the positive terminal of the primary alkaline battery.

US Pat. No. 10,483,632

DEVICE FOR TRANSMITTING AND/OR RECEIVING RADIOFREQUENCY SIGNALS

INSIGHT SIP, Grasse (FR)...

1. An apparatus for transmitting and/or receiving radiofrequency signals comprising at least a broadband antenna and a substrate; the antenna comprising at least a first radiating surface and being superimposed on the ground plane, the ground plane being located on a first face of the substrate, at least a side tongue of a power supply and at least a side wall connected to at least the first radiating surface, wherein:the antenna comprises at least a second radiating surface excitable by coupling with the first radiating surface,
the side wall is connected to a coupling trace located on a second face of the substrate, the second face opposite to the first face of the substrate, and the side wall and the coupling trace being configured to act as a capacitive coupling between at least the first radiating surface, the second radiating surface and the ground plane, and
wherein the coupling trace is configured to form a coupling capacitor whose value is ?S/e where ? is the dielectric constant of the dielectric material constituting the substrate. S is the surface of the coupling trace and e is the thickness between the coupling trace located on the second face of the substrate and the ground plane located on the first face of the substrate, and
wherein the first face of the substrate is a lower surface of the substrate and the second surface of the substrate is a surface of the substrate above the first face.

US Pat. No. 10,483,608

RF DIELECTRIC WAVEGUIDE DUPLEXER FILTER MODULE

CTS Corporation, Lisle, ...

2. An RF dielectric waveguide duplexer filter module for the transmission of Tx and Rx RF signals comprising:an antenna block of dielectric material including an antenna input/output, the antenna block including a plurality of exterior surfaces covered with a layer of conductive material and first and second antenna Tx and Rx signal transmission regions on one of the exterior surfaces defining a direct coupling path for the transmission of the Tx and Rx RF signals;
a Tx RF signal waveguide filter including:
stacked Tx blocks of dielectric material including exterior surfaces covered with a layer of conductive material and defining a plurality of resonators;
a plurality of Tx RF signal transmission regions defined between the stacked Tx blocks defining a direct coupling path for the transmission of the Tx RF signal between the stacked Tx blocks;
a third antenna Tx RF signal transmission region defined on one end exterior surface of one of the Tx blocks defining a direct coupling path for the transmission of the Tx RF signal from the one of the Tx blocks into the antenna block; and
a Tx RF signal input/output defined on one of the Tx blocks;
an RF Rx signal waveguide filter including:
stacked Rx blocks of dielectric material including exterior surfaces covered with a layer of conductive material and defining a plurality of resonators;
a plurality of Rx RF signal transmission regions defined between the Rx blocks defining a direct coupling path for the transmission of the Rx RF signal between the stacked Rx blocks;
a fourth antenna Rx RF signal transmission region defined on one end exterior surface of one of the Rx blocks defining a direct coupling path for the transmission of the Rx RF signal from the antenna block into the one of the Rx blocks;
an Rx RF signal input/output defined on one of the Rx blocks; and
the Tx and Rx RF signal waveguide filters being attached in side-by-side relationship and the antenna block being attached to the Tx and Rx blocks of the respective Tx and Rx signal waveguide filters in a side-by-side relationship along the end of the Tx and Rx signal blocks with the respective antenna Tx and Rx signal transmission regions.

US Pat. No. 10,483,602

BATTERY HOUSING FOR A LITHIUM-ION BATTERY

FORD GLOBAL TECHNOLOGIES,...

1. A vehicle comprising:an engine disposed within an engine compartment;
a traction motor coupled to a battery; and
a housing disposed within the engine compartment and containing the battery, the housing comprising a shell having solid thermal insulation surrounding the battery and forming first and second slots between the battery and the shell, the first slot being configured for connecting to ambient, and the second slot being configured for connecting to a vehicle cooling system, wherein the housing further comprises braces between the shell and the solid thermal insulation.

US Pat. No. 10,483,597

FIBER-CONTAINING MATS WITH ADDITIVES FOR IMPROVED PERFORMANCE OF LEAD ACID BATTERIES

Johns Manville, Denver, ...

1. A fiber-containing mat for a lead acid battery, the mat comprising:a plurality of fibers;
a binder holding the plurality of fibers together in the fiber-containing mat; and
one or more additives incorporated into the fiber-containing mat, wherein the one or more additives comprise benzyl benzoate.

US Pat. No. 10,483,582

SEMI-SOLID ELECTRODES HAVING HIGH RATE CAPABILITY

24M Technologies, Inc., ...

1. An electrochemical cell, comprising:an anode; and
a cathode;
wherein at least one of the anode and the cathode is a slurry electrode that includes about 35% to about 75% by volume of an active material and a conductive carbon in an electrolyte,
wherein the electrochemical cell has an area specific capacity of at least 7 mAh/cm2 at a C-rate of C/4, and
wherein the electrolyte is a liquid at room temperature.

US Pat. No. 10,483,579

SOLID OXIDE FUEL CELL

NISSAN MOTOR CO., LTD., ...

1. A solid oxide fuel cell comprising:a metal support which is formed from a porous metal substrate and which supports a power generation cell, wherein
the metal support includes a power generating area in which the power generation cell is disposed, a buffer area which is formed on an outer side of the power generating area in an in-plane direction, and an outer peripheral area which is formed on an outer side of the buffer area in the in-plane direction, the metal support is located on the anode side of the power generation cell, a separator is located on the anode side of the power generation cell such that a void region is formed between the separator and the buffer area of the metal support,
the power generation cell is formed as a stacked body of an anode electrode, a solid oxide electrolyte, and a cathode electrode, and
a pore in the metal support in the buffer area is filled with a filler material with a thermal conductivity lower than that of a formation material of the metal support.

US Pat. No. 10,483,576

POLYMER ELECTROLYTE MEMBRANE

LG CHEM, LTD., Seoul (KR...

1. A polymer electrolyte membrane comprising:a polymer including a unit represented by the following Chemical Formula 1; and
inorganic particles:

wherein, in Chemical Formula 1, A is —SO3H, —SO3?M+, —COOH, —COO?M+, —PO3H2, —PO3H?M+, —PO32?2M+, —O(CF2)mSO3H, —O(CF2)mSO3?M+, ?O(CF2)mCOOH, ?O(CF2)mCOO?M+, —O(CF2)mPO3H2, —O(CF2)mPO3H?M+or —O(CF2)mPO32?2M+;
m is an integer of 2 to 6;
M is a group 1 element;
R1 and R2 are the same as or different from each other, and each independently a halogen group; and
n is an integer of 2 to 10, and structures in the 2 to 10 parentheses are the same as or different from each other.

US Pat. No. 10,483,574

FUEL CELL SYSTEM WITH MERGED GASES FOR LEAK DETECTION

PANASONIC INTELLECTUAL PR...

1. A fuel cell system comprising:a reformer that generates a hydrogen containing gas from a fuel gas and includes a burner;
a fuel cell that uses the hydrogen containing gas and an oxidant gas to generate power;
an exhaust gas route for an exhaust gas discharged from the fuel cell to flow;
an air supplier that suctions air within the fuel cell system;
an air supply route for the air suctioned by the air supplier;
a merging part that is a part where the exhaust gas flowing in the exhaust gas route and the suctioned air flowing in the air supply route merge with each other;
a discharge route that discharges a mixed gas composed of the exhaust gas and the suctioned air having merged at the merging part to the atmosphere;
a gas-liquid separator disposed on the exhaust gas route between the fuel cell and the merging part; and
a combustible gas detector that is provided in the discharge route and detects concentration of a combustible gas contained in the mixed gas, wherein:
with respect to a flow of the suctioned air flowing in the air supply route and the discharge route, from an upstream side, the air supplier, the merging part, and the combustible gas detector are disposed in this order,
the exhaust gas includes an anode exhaust gas discharged from an anode of the fuel cell, and a cathode exhaust gas discharged from a cathode of the fuel cell,
the exhaust gas route includes an anode exhaust gas route for the anode exhaust gas and a cathode exhaust gas route for the cathode exhaust gas,
the burner is disposed on the anode exhaust gas route to combust the anode exhaust gas and exhaust a combustion gas,
a condenser is disposed on the cathode exhaust gas route,
the anode exhaust gas route downstream of the burner is connected to the cathode exhaust gas route at a position upstream of the condenser,
the cathode exhaust gas route bypasses the burner and is connected to the condenser,
the gas-liquid separator is a condensed water tank storing water obtained from the cathode exhaust gas and the combustion gas by the condenser, and
the condensed water tank is connected to the reformer by a condensed water route.

US Pat. No. 10,483,572

FLOW CONTROL METHOD OF COOLING MEDIUM IN A FUEL CELL SYSTEM, AND FUEL CELL SYSTEM

Toyota Jidosha Kabushiki ...

1. A fuel cell system, comprising:a fuel cell;
an internal flow path of a cooling medium formed inside the fuel cell;
an external flow path formed outside the fuel cell that forms a circulation flow path of the cooling medium by being connected to the internal flow path; and
a control device programmed to:
acquire a temperature of the fuel cell and identify a calorific value of the fuel cell,
during a time period when the temperature of the fuel cell is lower than an end temperature that is predetermined as a temperature at the time of end of a warm-up operation, determine whether or not an inlet temperature, which is the temperature of the cooling medium at an inlet to the internal flow path within the circulation flow path, is equal to or above a lower-limit temperature of a temperature range in which generated water does not freeze within the fuel cell,
when it is determined that the inlet temperature is equal to or above the lower-limit temperature during the time period, execute a first adjustment of a flow rate of the cooling medium in the circulation flow path so as to become greater than a normal flow rate corresponding to the calorific value of the fuel cell,
when it is determined that the inlet temperature is not equal to or above the lower-limit temperature during the time period, execute a second adjustment of the flow rate of the cooling medium in the circulation flow path to be a flow rate that is less than the normal flow rate and that increases in accordance with an increase in the calorific value of the fuel cell, and
adjust the flow rate of the cooling medium in the circulation flow path to be equal to the normal flow rate when the temperature of the fuel cell becomes equal to or above the end temperature, wherein the normal flow rate is a flow rate of the cooling medium determined based on the calorific value of the fuel cell.

US Pat. No. 10,483,563

CATHODE SUPPLY FOR A FUEL CELL

Volkswagen AG, Wolfsburg...

1. A cathode supply for a fuel cell of a fuel cell unit for a fuel cell system, the cathode supply comprising:a cathode supply path;
a cathode exhaust gas path; and
at least two fluid pumps for pumping a cathode operating medium for the fuel cell being fluido-mechanically coupled into the cathode supply path;
at least one first fluid pump of the at least two fluid pumps being drivable by enthalpy in a cathode exhaust gas of the fuel cell.

US Pat. No. 10,483,552

CATALYST COMPRISING COBALT CORE AND CARBON SHELL FOR ALKALINE OXYGEN REDUCTION AND METHOD FOR PREPARING THE SAME

Korea Institute of Scienc...

1. A method for preparing a catalyst, consisting of:(a) preparing a dispersion by dispersing a carbon support in a solvent;
(b) preparing a mixture solution by mixing the dispersion with a cobalt precursor and oleylamine;
(c) preparing a catalyst precursor by heat-treating the mixture solution at a low temperature of 250-350° C. under an inert gas atmosphere, wherein an oleylamine-coated cobalt oxide nanoparticle is supported on the carbon support in the catalyst precursor; and
(d) preparing a catalyst by heat-treating the catalyst precursor at a high temperature of 550-800° C. under the inert gas atmosphere, wherein the catalyst contains the carbon support and a core-shell nanoparticle supported on the carbon support,
wherein the core of the core-shell nanoparticle is cobalt metal without having the heterogeneous element and the shell of the core-shell contains carbon.

US Pat. No. 10,483,538

MIXED OXIDE CONTAINING A LITHIUM MANGANESE SPINEL AND PROCESS FOR ITS PREPARATION

Johnson Matthey Public Li...

1. A mixed oxide containinga) a mixed-substituted lithium manganese spinel as a first constituent in which a first portion of the manganese lattice sites are occupied by lithium ions and
b) a boron-oxygen compound as a second constituent,
wherein the mixed oxide is a single-phase homeotype mixed crystal comprising the constituents a) and b), wherein the second constituent is in the same phase as the first constituent, and
wherein the mixed oxide has a composition satisfied by the following formula:
[(Li1-aMa)(Mn2-c-dLicGd)Ox].(bB2O3.f*bLi2O)
wherein:
0?a<0.1;
d<1.2;
3.5 0.01 0 1 M is at least one element selected from the group of Zn, Mg and Cu; and
G is at least one element selected from the group of Al, Mg, Zn, Co, Ni, Cu and Cr; and
wherein in the mixed-substituted lithium manganese spinel an element of G occupying a second portion of the manganese lattice sites is Ni or Co, wherein when Ni is present, the contribution of Ni to “d” is 0.5+/?0.1 or when Co is present, the contribution of Co to “d” is 1+/?0.2, and
the size of the primary crystallites of the mixed oxide, measured as D50, is at least 0.5 ?m.

US Pat. No. 10,483,530

CATHODE ACTIVE MATERIAL AND FLUORIDE ION BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A cathode active material used in a fluoride ion battery, the cathode active material comprising:a Ce element, a S element, and a F element; and
a composition represented by CeSF.

US Pat. No. 10,483,504

SEALED BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A sealed battery comprising:a power generation element;
a case member having a bottomed cylindrical shape, in which the power generation element is housed;
a lid member that closes an opening of the case member and is provided with a through hole;
a collector terminal member having one end connected with the power generation element inside the case member, and the other end that is arranged in the through hole and extended outside the lid member; and
an insulating member arranged between the lid member and the collector terminal member, wherein
the other end of the collector terminal member includes a connecting portion having a columnar shape, that goes through the through hole, and a flange portion that is arranged so as to be approximately parallel with the lid member,
the insulating member includes a cylindrical portion that is positioned between the through hole and the connecting portion and surrounds the connecting portion, and a flat plate portion that is positioned between the lid member and the flange portion, the cylindrical portion and the flat plate portion being integral with the insulating member,
the flat plate portion has a first projecting portion projecting towards the lid member, and a second projecting portion projecting towards the flange portion, the first projecting portion and the second projecting portion being integral with the insulating member,
in a sectional view taken along a virtual plane including a central axis of the connecting portion,
the first projecting portion is provided at a position where a first side of the first projecting portion is linearly symmetrical with a second side of the first projecting portion, opposite from the first side, with respect to the central axis,
the second projecting portion is provided at a position where a first side of the second projecting portion is linearly symmetrical with a second side of the second projecting portion, opposite from the first side, with respect to the central axis,
a peak of the first projecting portion is provided at a position closer to the central axis than a peak position of the second projecting portion
the first projecting portion is provided into a ring shape centering about the central axis,
the second projecting portion is provided into a ring shape centering about the central axis, and
the first projecting portion is in contact with a surface of the lid member and the second projecting portion is in contact with a surface of the collector terminal.

US Pat. No. 10,483,496

ELECTROLUMINESCENT DEVICES WITH IMPROVED OPTICAL OUT-COUPLING EFFICIENCIES

NATIONAL TAIWAN UNIVERSIT...

1. An organic electroluminescent device, comprising:an optically reflective concave structure, comprising:
a first optically reflective surface; and
a second optically reflective surface, intersecting said first optically reflective surface at an obtuse angle;
a first light propagation layer in direct contact with said first optically reflective surface and said second optically reflective surface, comprising:
a first refractive surface, parallel to and separated from said first optically reflective surface;
a second refractive surface, parallel to and separated from said second optically reflective surface; and
an electroluminescent area, disposed entirely within said first light propagation layer, between said first optically reflective surface and said first refractive surface, without directly contacting any of said first optically reflective surface, said second optically reflective surface, said first refractive surface and said second refractive surface; and
a second light propagation layer, disposed on the first light propagation layer, wherein said second light propagation layer has a greater refractive index than said electroluminescent area minus 0.2.

US Pat. No. 10,483,493

ELECTRONIC DEVICE HAVING DISPLAY WITH THIN-FILM ENCAPSULATION

Apple Inc., Cupertino, C...

1. Apparatus, comprising:a glass substrate;
a thin-film encapsulation layer;
a layer of thin-film transistor circuitry including transistors and organic light-emitting diodes that is configured to form a pixel array that displays images, wherein the layer of thin-film transistor circuitry has a first surface that contacts the thin-film encapsulation layer and an opposing second surface that contacts the glass substrate;
a light-blocking layer, wherein the glass substrate layer has a first surface that is contacted by the thin-film transistor circuitry and has a second surface that is contacted by the light-blocking layer; and
a heat spreading layer, wherein the light-blocking layer is interposed between the heat spreading layer and the glass substrate.

US Pat. No. 10,483,492

DISPLAY DEVICE HAVING SEALING LAYER INCLUDING DETECTION ELECTRODE

Japan Display Inc., Toky...

1. A display device, comprising:a substrate having a first surface and a second surface opposite the first surface;
a pixel region provided on the first surface of the substrate in which a plurality of pixels is arranged;
a peripheral region provided outside of the pixel region on the first surface of the substrate;
an organic electroluminescence element arranged in each of the plurality of pixels;
a sealing layer covering a surface of the pixel region on an opposite side of a substrate side of the pixel region;
a first detection electrode extending in a first direction on a first inorganic insulating film above the pixel region on a side of the pixel region where the sealing layer is provided;
a second detection electrode extending in a second direction intersecting the first direction on a different layer than the first detection electrode; and
a polarization plate above the sealing layer, the polarization plate includes a polarizer having circular polarization,
wherein the organic electroluminescence element includes a pixel electrode, an organic layer provided above the pixel electrode, and an opposite electrode provided above the organic layer,
wherein the sealing layer includes at least an organic resin film, the first inorganic insulating film is provided above the opposite electrode and below the organic resin film, and a second inorganic insulating film provided is above the organic resin film,
wherein a first surface of the first inorganic insulating film is in contact with the opposite electrode,
a second surface of the first inorganic insulating film, opposite to the first surface of the first inorganic insulating film, is in contact with a first surface of the first detection electrode,
a second surface of the first detection electrode, opposite to the first surface of the first detection electrode, is in contact with a first surface of the organic resin film,
a second surface of the organic resin film, opposite to the first surface of the organic resin film, is in contact with a first surface of the second detection electrode,
a second surface of the second detection electrode, opposite to the first surface of the second detection electrode, is in contact with a first surface of the second inorganic insulating film,
wherein the pixel region and the peripheral region include at least one other inorganic insulating film on the substrate and at least one organic insulating film above the at least one other inorganic insulating film,
wherein the peripheral region includes an opening portion in which the at least one organic insulating film is removed, and the opening portion continuously surrounds the pixel region in a plan view,
wherein at least part of the first inorganic insulating film and the second inorganic insulating film are in contact with each other in the peripheral region,
wherein the organic resin film is sandwiched between the first inorganic insulating film and the second inorganic insulating film in the pixel region and an edge of the organic resin film is located in the opening portion, and
wherein the opposite electrode overlaps the opening portion.

US Pat. No. 10,483,487

ELECTRONIC DEVICE WITH REDUCED NON-DEVICE EDGE AREA

The Trustees of Princeton...

1. A method comprising:obtaining a flexible substrate having a first surface;
creating a notch on the first surface of the flexible substrate to create a first wall of the notch and a first edge where the first wall meets the first surface;
after creating the notch, disposing a plurality of organic light emitting diodes (OLEDs) over the first surface of the flexible substrate such that a first OLED of the plurality of OLEDs is separated from a second OLED of the plurality of OLEDs by the notch, wherein at least the first OLED has a second side and at least a first portion of the second side is disposed not more than 1.0 mm from the first edge;
after providing the flexible substrate, depositing a first barrier film so as to cover at least a portion of the first edge, at least a portion of the first wall of the notch, and a portion of each OLED of the plurality of OLEDs other than those in contact with the first surface of the flexible substrate; and
after the first barrier film is deposited, breaking the flexible substrate along the notch such that the first barrier film continues to cover the portions of the OLED other than those in contact with the first surface of the flexible substrate, including the portions of the first edge of the flexible substrate, so that the first barrier film is only in physical contact with the OLED and a portion of the flexible substrate.

US Pat. No. 10,483,486

FRAME SEALING GLUE, DISPLAY PANEL AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A frame sealing glue, comprising:a frame sealing glue body having an inner layer portion and an outer layer portion; and
an intermediate film layer disposed between the inner layer portion and the outer layer portion;
wherein a plurality of enclosed spaces are formed by the intermediate film layer and the inner layer portion or the outer layer portion of the frame sealing glue body,
wherein the intermediate film layer comprises a wave-shaped curved line having a plurality of semicircular curved line portions, the wave-shaped curved line forming a discontinuous curved line such that the intermediate film layer is disconnected at a corner of an enclosed frame formed by the frame sealing glue,
wherein a peak and a valley of the wave-shaped curved line intersect with the inner layer portion and the outer layer portion of the frame sealing glue body, respectively, or with the outer layer portion and the inner layer portion of the frame sealing glue body, respectively,
wherein each of the inner layer portion and the outer layer portion is a continuous closed line, and
wherein the intermediate film layer is made of different material from the frame sealing glue body.

US Pat. No. 10,483,483

ELECTROLUMINESCENT DEVICE AND ELECTROLUMINESCENT DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. An electroluminescent device comprising:an anode and a cathode facing each other;
a light compensation layer located between the anode and the cathode, the light compensation layer having a first refractive index;
an emitting material layer located between the light compensation layer and the cathode, the emitting material layer having a second refractive index higher than the first refractive index; and
a hole injection layer located between the emitting material layer and the light compensation layer or between the light compensation layer and the anode, wherein the hole injection layer has a third refractive index higher than the first refractive index, and
wherein the light compensation layer has a thickness smaller than a thickness of the emitting material layer and a thickness of the hole injection layer.

US Pat. No. 10,483,479

METHOD OF MANUFACTURING ORGANIC LIGHT EMITTING DEVICE AND ORGANIC LIGHT EMITTING DEVICE

PIONEER CORPORATION, Tok...

1. A method of manufacturing a light emitting device, the method comprising:a first step of coating a first region of a substrate, in which a first light emitting unit is formed, with a first solution comprising a light emitting material;
a second step of coating a second region of a substrate, in which a second light emitting unit is formed, with a second solution comprising a coating material, before or after the first step;
a third step of drying the first solution in the first region and the second solution in the second region after the first step and the second step; and
a fourth step of depositing a light emitting material in the second region after the third step.

US Pat. No. 10,483,455

MAGNETIC ELEMENT FOR MEMORY AND LOGIC

Intel Corporation, Santa...

1. An apparatus comprising:a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; and
a fin of a finFET, the fin being coupled to a substrate;
wherein the free magnetic layer includes a top surface, a bottom surface, and a sidewall circumnavigating the free magnetic layer and coupling the bottom surface to the top surface;
wherein the top surface is rectangular with a plurality of rounded corners;
wherein the top surface includes: (a)(i) a long axis and a short axis, (a)(ii) the short axis is orthogonal to the long axis, (a)(iii) two linear long sides generally parallel to the long axis, and (a)(iv) two linear short sides generally parallel to the short axis;
wherein: (b)(i) a width extends from one of the two linear long sides to another of the two linear long sides, (b)(ii) the width is parallel to the short axis, (b)(iii) a length extends from one of the two linear short sides to another of the two linear short sides, and (b)(iv) the length is parallel to the long axis;
wherein: (c)(i) the fin has opposing sidewalls, (c)(ii) the fin has a fin width, (c)(iii) the fin width includes a maximum width between the opposing sidewalls, and (c)(iv) the fin width is substantially equal to the width.

US Pat. No. 10,483,444

METHOD OF PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR COMPONENT, OPTOELECTRONIC SEMICONDUCTOR COMPONENT, AND TEMPORARY CARRIER

OSRAM Opto Semiconductors...

1. A method of producing an optoelectronic semiconductor component comprising:providing a carrier comprising two metal layers, wherein the metal layers are detachable from one another,
applying a photoresist on the first metal layer,
patterning the photoresist such that regions composed of the photoresist comprising a predefined cross section are present on the first metal layer,
electrolytically applying a further metal on free regions of the first metal layer not covered by the photoresist, wherein the further metal comprises a greater thickness than the photoresist and partly projects laterally beyond regions of the photoresist,
removing the photoresist, wherein a body composed of the further metal arises, said body comprising a laterally projecting upper edge region,
securing an optoelectronic semiconductor chip on the further metal, and
mechanically detaching the second metal layer from the first metal layer.

US Pat. No. 10,483,440

CADMIUM-FREE QUANTUM DOT NANOPARTICLES

Nanoco Technologies Ltd.,...

1. A quantum dot nanoparticle comprising:a core having an etched surface and comprising indium, phosphorus, magnesium, zinc, and sulfur;
a first shell disposed on the etched surface of the core; and
a second shell disposed on the first shell,
wherein the quantum dot nanoparticle emits light in the green region of the visible spectrum.

US Pat. No. 10,483,421

SOLAR CELL MODULE

LG ELECTRONICS INC., Seo...

1. A solar cell module comprising:a plurality of solar cells each including a semiconductor substrate, and first electrodes and second electrodes which are formed on the semiconductor substrate and collect carriers of different conductive types, wherein the first electrodes and the second electrodes are extended in a first direction and alternatively disposed in the second direction crossing the first direction;
a plurality of first lines extended in the second direction to cross the first electrodes and the second electrodes, the plurality of first lines being connected to the first electrodes by a plurality of conductive adhesives formed at crossings of the first electrodes and the plurality of first lines and being insulated from the second electrodes by a plurality of insulating layers formed at crossings of the second electrodes and the plurality of first lines;
a plurality of second lines extended in the second direction to cross the first electrodes and the second electrodes, the plurality of second lines being connected to the second electrodes by the plurality of conductive adhesives formed at crossings of the second electrodes and the plurality of second lines and being insulated from the first electrodes by the plurality of insulating layers formed at crossings of the first electrodes and the plurality of second lines; and
a connector positioned between the first solar cell and the second solar cell and connected to the plurality of first lines and the plurality of second lines,
wherein a width of the connector is equal to or greater than at least one of a first distance between the first solar cell and the connector or a second distance between the second solar cell and the connector,
wherein an application area of the insulating layer on the connector is larger than an application area of the conductive adhesive on the connector, and
wherein ends of the plurality of first lines and the plurality of second lines of adjacent solar cells are bonded to the connector so that the adjacent solar cells are serially connected.

US Pat. No. 10,483,411

SOLAR CELL AND SOLAR CELL MODULE

Panasonic Corporation, O...

1. A solar cell comprising:a first electrode;
a first hole transport layer containing nickel and lithium;
an inorganic material layer containing titanium;
a light-absorbing layer converting light into electric charge;
a second hole transport layer, located between the first hole transport layer and the inorganic material layer, containing nickel and lithium; and
a second electrode, wherein
the first electrode, the first hole transport layer, the inorganic material layer, the light-absorbing layer, and the second electrode are layered in that order,
the light-absorbing layer contains a perovskite compound represented by a formula AMX3, where A is a monovalent cation, M is a divalent cation, and X is a monovalent anion, and
an atomic ratio of lithium to all metal elements in the second hole transport layer is less than an atomic ratio of lithium to all metal elements in the first hole transport layer.

US Pat. No. 10,483,391

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a semiconductor substrate having a first surface;
an insulating isolation film disposed at the first surface; and
a gate electrode,
the semiconductor substrate having a source region disposed in contact with the first surface, a drain region disposed in contact with the first surface, a drift region disposed in contact with the first surface so as to surround the drain region, and a body region sandwiched between the drift region and the source region and disposed in contact with the first surface so as to surround the source region,
the source region, the drain region, and the drift region being of a first conductivity type,
the body region being of a second conductivity type which is opposite to the first conductivity type,
the insulating isolation film having a first portion disposed inside the drift region in plan view, a second portion protruding from the first portion in a direction toward the source region, and a third portion protruding from the first portion in the direction toward the source region and sandwiching the drift region between the second portion and the third portion,
the gate electrode facing a portion of the body region sandwiched between the source region and the drift region with being insulated from the portion, and being disposed so as to extend over the second portion and the third portion, wherein
the semiconductor substrate has a second surface opposite to the first surface,
the gate electrode has a first embedded portion embedded in the second portion, and a second embedded portion embedded in the third portion,
the drift region is sandwiched between the first embedded portion and the second embedded portion, and
the gate electrode has a third embedded portion embedded in the first portion and facing the drift region sandwiched between the second portion and the third portion.

US Pat. No. 10,483,373

SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a first insulating interlayer on a substrate;
a second insulating interlayer on the first insulating interlayer;
a gate structure extending through the first insulating interlayer and the second insulating interlayer on the substrate, a lower portion of the gate structure having a constant first width, and an upper portion of the gate structure having a second width that is greater than the first width and that gradually increases from a bottom toward a top thereof; and
a spacer structure on a sidewall of the gate structure, a width of an upper portion of the spacer structure being less than a width of a lower portion of the spacer structure.

US Pat. No. 10,483,368

SINGLE CRYSTALLINE EXTRINSIC BASES FOR BIPOLAR JUNCTION STRUCTURES

International Business Ma...

1. A method for forming a bipolar transistor (BJT) structure comprising:providing a substrate with an insulator layer and a device layer over the insulator layer;
forming an intrinsic base from the device layer;
forming emitter and collector regions from the device layer;
after forming i) the intrinsic base and ii) the emitter and collector regions, depositing a single crystalline extrinsic base over the intrinsic base;
prior to depositing the extrinsic base, forming an inter-layer dielectric (ILD) material over the structure;
forming a dummy base, with a hardmask thereon, over the device layer; and
performing chemical-mechanical planarization (CMP) on the structure to planarize the ILD in relation to the hardmask.

US Pat. No. 10,483,365

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first conductor, the first conductor being a first ring-shaped conductor;
an oxide semiconductor comprising a region extending through an inside of a ring of the first conductor;
a first insulator between the first conductor and the oxide semiconductor;
a second insulator between the first conductor and the first insulator; and
a second conductor inside the ring of the first conductor,
wherein the second conductor is inside the second insulator,
wherein the second conductor is configured to be in a floating state,
wherein an inner surface and an outer surface of the second conductor are in contact with the second insulator, and
wherein the inner surface of the second conductor faces to the first insulator.

US Pat. No. 10,483,359

METHOD OF FABRICATING A POWER SEMICONDUCTOR DEVICE

Infineon Technologies Ame...

1. A method of fabricating a power semiconductor device, said method comprising:forming a gate trench in a semiconductor substrate, said gate trench including a gate electrode; and
forming a field plate trench structure in said substrate separate from said gate trench, wherein forming said field plate trench structure comprises:
forming an upper trench situated over a lower trench in said substrate, said upper trench being wider than said lower trench and extending deeper into said substrate than said gate trench, a width of said lower trench being greater than one half a width of said upper trench;
forming a trench dielectric in said lower trench and on sidewalls of said upper trench, said trench dielectric filling completely said lower trench; and
forming a field plate electrode within said trench dielectric;
wherein said trench dielectric is formed such that a bottom thickness of said trench dielectric is greater than a sidewall thickness of said trench dielectric on said sidewalls of said upper trench.

US Pat. No. 10,483,349

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first semiconductor region including a first partial region and a second partial region and being of a first conductivity type;
a second semiconductor region separated from the first partial region in a second direction crossing a first direction, the second semiconductor region being of the first conductivity type, the first direction being from the first partial region toward the second partial region;
a third semiconductor region provided between the first partial region and the second semiconductor region, the third semiconductor region being of a second conductivity type and comprising a third partial region and a fourth partial region, the fourth partial region being positioned between the first partial region and the third partial region;
a first electrode separated from the second partial region in the second direction and separated from the second semiconductor region and the third semiconductor region in the first direction;
a first insulating film comprising a first insulating region and a second insulating region, the first insulating region being provided between the second semiconductor region and the first electrode in the first direction and between the third semiconductor region and the first electrode in the first direction, a portion of the first insulating region contacting the third partial region, the second insulating region being provided between the second partial region and the first electrode in the second direction; and
a fourth semiconductor region comprising a first portion and being of the first conductivity type, the first portion being provided between the fourth partial region and at least a portion of the first insulating film in the first direction,
wherein
an impurity concentration of the second conductivity type in the third partial region is higher than an impurity concentration of the second conductivity type in the fourth partial region,
the third semiconductor region further comprises a fifth partial region provided between the fourth partial region and the first partial region in the second direction, and
the impurity concentration of the second conductivity type in the fourth partial region is higher than an impurity concentration of the second conductivity type in the fifth partial region.

US Pat. No. 10,483,342

ORGANIC LIGHT EMITTING DIODE DISPLAY

Samsung Display Co., Ltd....

1. An organic light emitting diode display comprising:a substrate;
a scanning line on the substrate;
a data line;
a first thin film transistor coupled to the scanning line and the data line;
a first voltage line;
an organic light emitting diode;
a second thin film transistor utilizing a semiconductor layer, and electrically coupled to the first voltage line, the organic light emitting diode, and the first thin film transistor;
a third thin film transistor electrically coupled to the second thin film transistor;
an insulating layer covering the second thin film transistor; and
a storage capacitor electrically coupled to a gate electrode of the second thin film transistor,
wherein the storage capacitor comprises a first capacitor plate comprising a portion of the gate electrode of the second thin film transistor, a second capacitor plate over the first capacitor plate, and a portion of the insulating layer between the first capacitor plate and the second capacitor plate, and
wherein the semiconductor layer is extended to the third thin film transistor.

US Pat. No. 10,483,323

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

SAMSUNG ELECTRONICS CO., ...

12. A three-dimensional semiconductor device, comprising:a substrate; and
a cell array comprising:
a plurality of electrodes vertically stacked on the substrate, the plurality of electrodes forming m number of stepwise stacks at ends of the plurality of electrodes in a first direction;
a plurality of dummy electrodes vertically stacked and adjacent to the plurality of electrodes in a second direction, the second direction being perpendicular to the first direction, the plurality of dummy electrodes forming n number of stepwise stacks in the second direction;
a capping insulating layer covering the plurality of electrodes and the plurality of dummy electrodes; and
a plurality of contact plugs penetrating the capping insulating layer and contacting the plurality of electrodes at each step of the m number of stepwise stacks,
wherein the m and n are natural numbers equal to or greater than two, and the m is greater than n.

US Pat. No. 10,483,319

PIXILATED DISPLAY DEVICE BASED UPON NANOWIRE LEDS AND METHOD FOR MAKING THE SAME

GLO AB, Lund (SE)

1. A method of forming a pixilated display device, comprising:growing an array of nanowire LEDs on a substrate, each nanowire LED in the array including a vertical stack, from bottom to top, of a first-wavelength light emitting portion including a first material emitting a first-wavelength light and a second-wavelength light emitting portion including a second material emitting a second-wavelength light; and
while masking a first nanowire LED within the array with a patterned masking layer, removing a second-wavelength light emitting portion from a second nanowire LED within the array;
wherein growing the array of nanowire LEDs on the substrate comprises:
forming a growth mask over the substrate, the growth mask having a first aperture in a first area of the first nanowire LED and a second aperture in a second area of the second nanowire LED;
forming a first nanowire core through the first aperture; and
forming a second nanowire core through the second aperture:
wherein:
the first nanowire LED comprises a core-shell nanowire device that comprises the first nanowire core and a first quantum well shell comprising the first-wavelength light emitting portion, the second-wavelength light emitting portion, and a first pyramidal plane quantum well;
the second nanowire LED comprises a core-shell nanowire device that comprises the second nanowire core and a second quantum well shell comprising the first-wavelength light emitting portion, the second-wavelength light emitting portion, and a second pyramidal plane quantum well;
the first quantum well shell is formed by deposition of an InGaN layer and a GaN layer around the first nanowire core;
the second quantum well shell is formed by deposition of the InGaN layer and the GaN layer around the second nanowire core;
the first quantum well shell and the second quantum well shell are deposited during the same deposition steps;
the first-wavelength light emitting portion of the first nanowire LED comprises a lower portion of the first quantum well shell located over m-plane sidewalls of the first nanowire core;
the second-wavelength light emitting portion of the first nanowire LED comprises an eave region of the first quantum well shell located between the lower portion of the first quantum well shell and the first pyramidal plane quantum well of the first quantum well shell located over pyramidal p-plane sidewalls of the first nanowire core;
the first-wavelength light emitting portion of the second nanowire LED comprises a lower portion of the second quantum well shell located over m-plane sidewalls of the second nanowire core; and
the second-wavelength light emitting portion of the second nanowire LED comprises an eave region of the second quantum well shell located between the lower portion of the second quantum well shell and the second pyramidal plane quantum well of the second quantum well shell located over pyramidal p-plane sidewalls of the second nanowire core.

US Pat. No. 10,483,309

IMAGE SENSORS WITH MULTIPART DIFFRACTIVE LENSES

SEMIDUCTOR COMPONENTS IND...

1. An image sensor comprising a plurality of imaging pixels, wherein each imaging pixel of the plurality of imaging pixels comprises:a photodiode; and
a diffractive lens formed over the photodiode,
wherein the diffractive lens has an edge portion with a first refractive index and a center portion with a second refractive index that is different than the first refractive index and wherein the edge portion is adjacent a solid material with a third refractive index that is different than the first and second refractive indices.

US Pat. No. 10,483,298

MULTI-SENSOR OPTICAL DEVICE FOR DETECTING CHEMICAL SPECIES AND MANUFACTURING METHOD THEREOF

STMicroelectronics S.R.L....

1. A device, comprising:a substrate;
a semiconductor layer on the substrate, the semiconductor layer having a first portion with a first thickness and a second portion with a second thickness, the first portion having a first surface;
a first optical sensor in the first portion, the first optical sensor including:
a first anode recessed in the first portion, the first anode having an exposed surface coplanar with the first surface; and
a second optical sensor in the second portion.

US Pat. No. 10,483,279

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Institute of Microelectro...

1. A method of manufacturing a semiconductor device, comprising the steps of:forming a gate dielectric layer and a first amorphous channel layer on a substrate;
thinning the first amorphous channel layer;
etching the first amorphous channel layer and the gate dielectric layer until the substrate is exposed;
forming a second amorphous channel layer on the first amorphous channel layer and the substrate;
annealing such that the first amorphous channel layer and the second amorphous channel layer are converted into a polycrystalline channel layer;
thinning the polycrystalline channel layer.

US Pat. No. 10,483,275

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, the method comprising:(a) forming a first insulating film having a first thickness over a main surface of a semiconductor substrate and then forming a second insulating film having a second thickness larger than the first thickness over the first insulating film;
(b) sequentially processing the second insulating film, the first insulating film, and the semiconductor substrate to form a plurality of trenches and to form a plurality of projecting portions which include portions of the semiconductor substrate extending in a first direction along the main surface of the semiconductor substrate and are spaced apart from each other in a second direction orthogonal to the first direction along the main surface of the semiconductor substrate;
(c) depositing a third insulating film over the main surface of the semiconductor substrate such that the third insulating film is embedded in the trenches;
(d) planarizing an upper surface of the third insulating film and an upper surface of the second insulating film;
(e) removing the second insulating film;
(f) performing isotropic dry etching to remove the first insulating film, expose respective upper surfaces of the projecting portions, recess an upper surface and a side surface of the third insulating film, and expose respective side walls of the projecting portions from the upper surface of the third insulating film;
(g) forming a first gate electrode extending in the second direction such that a fourth insulating film is interposed between the first gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film; and
(h) forming a second gate electrode extending in the second direction such that a fifth insulating film including a trapping insulating film is interposed between the second gate electrode and each of the respective upper surfaces and side walls of the projecting portions which are exposed from the upper surface of the third insulating film and one of side walls of the first gate electrode,
wherein, between the projecting portions adjacent to each other in the second direction, a portion of the upper surface of the third insulating film is higher in level than a first surface obtained by connecting a position of the upper surface of the third insulating film which is in contact with the side wall of one of the projecting portions to a position of the upper surface of the third insulating film which is in contact with the side wall of other projecting portion.

US Pat. No. 10,483,272

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. A method for fabricating an electronic device including a semiconductor memory, comprising:forming a first stacked structure over a substrate, the first stacked structure including a plurality of first interlayer dielectric layers and first material layers which are alternately stacked over each other;
forming a first channel hole by selectively etching the first stacked structure;
forming a first channel layer in the first channel hole;
forming a channel connection pattern and an etch stop pattern over the first stacked structure, wherein the channel connection pattern overlaps the first channel hole and, wherein the etch stop pattern is formed of the same material as the channel connection pattern, is isolated from the channel connection pattern, and is formed at substantially the same level as the channel connection pattern;
forming a second stacked structure over the channel connection pattern and the etch stop pattern, the second stacked structure including a plurality of second interlayer dielectric layers and second material layers which are alternately stacked over each other;
forming a second channel hole to expose the channel connection pattern by selectively etching the second stacked structure;
forming a second channel layer in the second channel hole;
forming an initial slit by etching the second stacked structure to expose the etch stop pattern; and
forming a final slit by etching the exposed etch stop pattern and the first stacked structure located under the exposed etch stop pattern.

US Pat. No. 10,483,266

FLEXIBLE MERGE SCHEME FOR SOURCE/DRAIN EPITAXY REGIONS

Taiwan Semiconductor Manu...

1. A method comprising:forming a first gate stack extending on top surfaces and sidewalls of first semiconductor fins, wherein the first semiconductor fins are parallel to, and are neighboring, each other;
forming a second gate stack extending on top surfaces and sidewalls of second semiconductor fins, wherein the second semiconductor fins are parallel to, and are neighboring, each other;
forming a dielectric layer, wherein the dielectric layer comprises a first portion extending on the first gate stack and the first semiconductor fins, and a second portion extending on the second gate stack and the second semiconductor fins;
in a first etching process, etching the first portion of the dielectric layer to form first fin spacers on sidewalls of the first semiconductor fins, wherein the first fin spacers have a first height;
in a second etching process, etching the second portion of the dielectric layer to form second fin spacers on sidewalls of the second semiconductor fins, wherein the second fin spacers have a second height greater than the first height;
recessing the first semiconductor fins to form first recesses between the first fin spacers;
recessing the second semiconductor fins to form second recesses between the second fin spacers; and
simultaneously growing first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses, wherein the first epitaxy semiconductor regions grown from neighboring ones of the first recesses merge with each other, and the second epitaxy semiconductor regions grown from neighboring ones of the second recesses are separate from each other.

US Pat. No. 10,483,260

SEMICONDUCTOR CARRIER WITH VERTICAL POWER FET MODULE

1. A monolithic power management module, comprising:a chip carrier further comprising surfaces, ground traces, signal and power interconnects;
a three dimensional FET formed on the chip carrier to modulate currents through the chip carrier or on the surfaces;
a toroidal inductor or transformer coil with a ceramic magnetic core formed on the chip carrier adjacent to the three dimensional FET and having a first winding connected to the three dimensional FET, and
a plurality of passive ceramic components formed on the chip carrier surfaces including clock circuitry in a form of an LCR resonator further comprising an inductor coil, a capacitive element and a resistive element; and
wherein the three dimensional FET includes an elongated gate electrode comprising a conductor that forms a resonant transmission line by configuring the conductor to form a serpentine electrode that contains a capacitive element determined by charge-collected beneath the gate, a resistive dement determined by the conductor, length and cross-sectional area, of the conductor used to form the serpentine electrode, and an Inductive element formed by half-turns that loop the serpentine electrode winding back upon itself.

US Pat. No. 10,483,250

THREE-DIMENSIONAL SMALL FORM FACTOR SYSTEM IN PACKAGE ARCHITECTURE

Intel Corporation, Santa...

1. An apparatus comprising:a first package having a first side and an opposite second side, the first package including:
a plurality of embedded electronic components, ones of the plurality of embedded electronic components laterally adjacent to one another, and
one or more embedded via bars, each via bar including a plurality of through vias;
and
a second package having a first side and an opposite second side, the second package including:
a plurality of embedded electronic components, ones of the plurality of embedded electronic components laterally adjacent to one another;
wherein a first side of the first package and a second side of second package are coupled together by a plurality of connections, including at least a first connection connecting the second package to a first component of the first package and a second connection connecting one of the plurality of embedded electronic components of the second package to a first via bar of the one or more embedded via bars, wherein the one of the plurality of embedded electronic components of the second package is directly over the first via bar of the one of the one or more embedded via bars of the first package.

US Pat. No. 10,483,248

WAFER LEVEL CHIP SCALE FILTER PACKAGING USING SEMICONDUCTOR WAFERS WITH THROUGH WAFER VIAS

SKYWORKS SOLUTIONS, INC.,...

1. An electronics package comprising:a semiconductor substrate having one or more passive devices formed on the semiconductor substrate and a cavity defined in a first surface of the semiconductor substrate; and
a piezoelectric substrate bonded to the semiconductor substrate and having a microelectromechanical device formed on the piezoelectric substrate, the microelectromechanical device disposed within the cavity defined in the semiconductor substrate.

US Pat. No. 10,483,246

POWER DEVICE CASSETTE WITH AUXILIARY EMITTER CONTACT

Littlefuse, Inc., Chicag...

1. A method comprising:providing a power semiconductor device die so that the power semiconductor device die is disposed between a pedestal of a disc-shaped bottom plate member and a disc-shaped top plate member, wherein the disc-shaped bottom plate member, the disc-shaped top plate member, and the power semiconductor device die are parts of a press pack semiconductor device module;
providing a first conductive path between a first pad on the power semiconductor device die and a first terminal of the press pack semiconductor device module, wherein the first conductive path extends through a first contact pin that contacts the power semiconductor device die, and wherein the first conductive path extends through neither the disc-shaped top plate member nor the disc-shaped bottom plate member; and
providing a second conductive path between a second pad on the power semiconductor device die and a second terminal of the press pack semiconductor device module, wherein the second conductive path extends through a second contact pin that contacts the power semiconductor device die, and wherein the second conductive path extends through neither the disc-shaped top plate member nor the disc-shaped bottom plate member.

US Pat. No. 10,483,205

CONTACT USING MULTILAYER LINER

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:patterning an opening within a substrate of a multi-layer integrated circuit device, said substrate comprising silicon;
performing a cleaning process of the opening;
forming a lower blocking layer within the opening, and the lower blocking layer contacts a surface of the opening, wherein the cleaning process leaves oxygen and fluorine particles within an area of the substrate adjacent the lower blocking layer;
forming a middle liner layer within the opening, and the middle liner layer contacts the lower blocking layer and comprises an oxide;
forming an upper blocking layer within the opening, and the upper blocking layer contacts the middle liner layer, and the middle liner layer is formed to be between the lower blocking layer and the upper blocking layer; and
forming a conductor layer within the opening, and the conductor layer contacts the upper blocking layer and comprises a conductive contact within the multi-layer integrated circuit device.

US Pat. No. 10,483,194

INTERPOSER SUBSTRATE AND METHOD OF FABRICATING THE SAME

PHOENIX PIONEER TECHNOLOG...

1. An interposer substrate, comprising:a second dielectric material layer having opposing first and second surfaces;
a first wiring layer embedded in the second dielectric material layer and exposed from the first surface of the second dielectric material layer;
a first dielectric material layer formed on the first surface of the second dielectric material layer and the first wiring layer, wherein a portion of the first wiring layer extends continuously into the first dielectric material layer from the second dielectric material layer, and the first dielectric material layer has a plurality of openings, from which a portion of the first wiring layer is exposed;
a plurality of first conductive blocks embedded in the second dielectric material layer and having first terminal surfaces connected to the first wiring layer and second terminal surfaces opposing to the first terminal surfaces and flush with the second surface of the second dielectric material layer;
a second wiring layer formed on the second surface of the second dielectric material layer and having a first side connected to the second terminal surfaces of the first conductive blocks and a second side opposing to the first surface of the second wiring layer;
a plurality of second conductive blocks formed on the second side of the second wiring layer; and
an insulative protection layer formed on the second surface of the second dielectric material layer, the second wiring layer and the second conductive blocks, wherein an end of the second conductive blocks is exposed from the insulative protection layer, and the insulative protection layer has at least a concave portion formed between two of the second conductive blocks.

US Pat. No. 10,483,187

HEAT SPREADING DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:placing a die stack on a front side of a device wafer;
forming conductive connectors on a back side of the device wafer;
singulating the device wafer to form an integrated circuit die, the die stack disposed on the integrated circuit die;
placing the integrated circuit die on a carrier substrate;
bonding a front side of a dummy wafer to the integrated circuit die, the die stack disposed in a recess in the front side of the dummy wafer;
debonding the integrated circuit die from the carrier substrate; and
singulating the dummy wafer to form a dummy semiconductor feature, the dummy semiconductor feature laterally surrounding the die stack, the dummy semiconductor feature electrically isolated from the die stack and the integrated circuit die.

US Pat. No. 10,483,180

PROCESS FOR THE WAFER-SCALE FABRICATION OF HERMETIC ELECTRONIC MODULES

1. An electronic module comprising:a multilayer PCB circuit that comprises:
on one face, electrical connection balls for external electrical connection of the electronic module; and
a hermetically protective electrically insulating inorganic inner layer;
an electrically insulating or conductive inorganic hermetic protection layer;
one or more electronic components that are electrically connected to the PCB circuit; and
six faces with the electrically insulating or conductive inorganic hermetic protection layer entirely covering the five faces other than that formed by the PCB circuit, wherein
the hermetically protective electrically insulating inorganic inner layer is in direct contact with the electrically insulating or conductive inorganic hermetic protection layer so as to form a continuous hermetical joint around the one or more electronic components.

US Pat. No. 10,483,165

METHODS FOR FORMING CONTACT PLUGS WITH REDUCED CORROSION

Taiwan Semiconductor Manu...

1. An integrated circuit structure comprising:a semiconductor region;
a gate stack over the semiconductor region;
an Inter-layer Dielectric (ILD) having portions on opposite sides of the gate stack;
a source/drain region extending into the semiconductor region;
a source/drain silicide region over the source/drain region;
a source/drain contact plug comprising:
a conductive capping layer, the conductive capping layer comprising:
a bottom portion over the source/drain silicide region; and
sidewall portions over, and connected to, the bottom portion; and
a metal region over the bottom portion and between the sidewall portions of the conductive capping layer; and
a metal cap comprising a first portion overlapping the metal region, and second portions extending into the sidewall portions of the conductive capping layer.

US Pat. No. 10,483,154

FRONT-END-OF-LINE DEVICE STRUCTURE AND METHOD OF FORMING SUCH A FRONT-END-OF-LINE DEVICE STRUCTURE

GLOBALFOUNDRIES Inc., Gr...

14. A method, comprising:etching a first trench into a semiconductor substrate;
consecutively forming first and second insulating liners in said first trench;
forming a first insulating filling material on said first and second insulating liners in said first trench;
performing a recessing process after said first insulating filling material is formed, wherein an upper portion of said first insulating filling material is removed and an upper portion of said second insulating liner is exposed;
performing a pullback etching process, wherein said exposed upper portion of said second insulating liner material is removed and an upper surface portion of said first insulating liner is exposed; and
filling said first trench with a second insulating filling material, wherein said exposed upper surface portion of said first insulating liner is directly contacted by said second insulating filing material.

US Pat. No. 10,483,149

WAFER PROCESSING METHOD FOR DIVIDING A WAFER, INCLUDING A SHIELD TUNNEL FORMING STEP

DISCO CORPORATION, Tokyo...

1. A wafer processing method for dividing a wafer including a single-crystal silicon substrate having on a face side thereof a plurality of devices disposed in respective areas demarcated by a plurality of intersecting projected dicing lines, into individual device chips, the method comprising:a protective member placing step of placing a protective member on the face side of the wafer;
a shield tunnel forming step of, after performing the protective member placing step, applying a laser beam, which has a wavelength that is transmittable through single-crystal silicon, to areas of the wafer that correspond to the projected dicing lines from a reverse side of the wafer, thereby successively forming a plurality of shield tunnels in the wafer, each including a fine pore extending from the reverse side to the face side of the wafer and an amorphous region surrounding the fine pore; and
a dividing step of, after performing the shield tunnel forming step, dividing the wafer into individual device chips by etching the shield tunnels according to plasma etching,
wherein the pulsed laser beam used in the shield tunnel forming step has a wavelength of 1950 nm or higher.

US Pat. No. 10,483,146

ELECTROSTATIC CHUCK HEATER

NGK Insulators, Ltd., Na...

1. An electrostatic chuck heater comprising:an electrostatic chuck in which an electrostatic electrode is embedded in a ceramic sintered body;
a small-zone formation region provided inside the ceramic sintered body or a heater support body that is integrated with the ceramic sintered body, the small-zone formation region including a plurality of small zones in which small heater electrodes are wired;
a power source to which the plurality of small heater electrodes are connected in parallel; and
a small-zone control apparatus that performs control such that desired electric power is supplied to each of the small heater electrodes by using an output ratio to a suppliable output corresponding to each of the small heater electrodes,
wherein among the plurality of small heater electrodes, a small heater electrode that is wired in a small zone including a cool spot has a resistance that is set to a smaller value than that of the other small heater electrodes.

US Pat. No. 10,483,143

END EFFECTOR AND SUBSTRATE CONVEYING ROBOT

KAWASAKI JUKOGYO KABUSHIK...

1. An end effector capable of holding two or more substrates, comprising:a base at least a part of which advances below a lowermost substrate or above an uppermost substrate of a plurality of substrates stored in substrate storage;
a substrate holder provided on the base so as to hold the two or more substrates including the lowermost substrate or the uppermost substrate, the substrate holder comprising
a substrate support provided on a distal end side of an end effector body including the base, the substrate support including a surface supporting a bottom surface edge portion of the substrate, and
a connector comprising a rotary spindle connecting the substrate support to the distal end side of the end effector body so that the substrate support pivots in response to an external force when the external force is applied to the substrate support; and
a servo motor for changing a protrusion amount of the substrate holder from a reference surface including a surface of the base opposed to the lowermost substrate or the uppermost substrate,
wherein the servo motor is configured for applying a drive force to a whole of the substrate holder, and
wherein a vertical pitch of the two or more substrates held by the substrate holder is changed by changing the protrusion amount of the substrate holder by the servo motor.

US Pat. No. 10,483,141

SEMICONDUCTOR PROCESS EQUIPMENT

APPLIED MATERIALS, INC., ...

1. A substrate transport system, comprising:a chamber having an interior wall;
a planar motor disposed on the interior wall;
a substrate carrier magnetically coupled to the planar motor, the substrate carrier comprising:
a base;
a substrate supporting surface coupled to a support member extending from the base in a cantilevered orientation; and
an electrically conductive plate to apply radio frequency power to the chamber.

US Pat. No. 10,483,135

ETCHING METHOD

TOKYO ELECTRON LIMITED, ...

1. An etching method for a target object including a main surface, grooves formed in the main surface, and an etching target film covering the main surface and surfaces of the grooves, the method comprising:a first step of accommodating the target object in a processing chamber of a plasma processing apparatus;
a second step of supplying a first gas into the processing chamber; and
a third step of supplying a second gas and a high frequency power for plasma generation into the processing chamber and generating in the processing chamber a plasma of a gas including the second gas in the processing chamber,
wherein: the first gas contains an oxidizing agent that does not include a hydrogen atom;
the second gas contains a compound that includes one or more silicon atoms and one or more fluorine atoms and does not include a hydrogen atom;
the etching target film is made of a material that is dry etched by using fluorine;
portions of the etching target film which cover the surfaces of the grooves are selectively removed;
the etching target film is made of TiN; and
the temperature of the target object in the third step is lower than 250° C.

US Pat. No. 10,483,129

METHOD FOR ROUGHENING THE SURFACE OF A METAL LAYER, THIN FILM TRANSISTOR, AND METHOD FOR FABRICATING THE SAME

BOE Technology Group Co.,...

1. A method for fabricating a thin film transistor, the method comprising:forming an oxide semiconductor layer and a source-drain metal layer on an underlying substrate;
forming a first photo-resist layer on a surface of the source-drain metal layer, and processing the first photo-resist layer by pre-baking, exposing, developing, and post-baking the first photo-resist layer, wherein the post-baking is at a temperature ranging from 110° C. to 150° C.; and stripping the first photo-resist layer to roughen the surface of the source-drain metal layer; and
performing a patterning process on the roughened source-drain metal layer, and the oxide semiconductor layer to form patterns of source and drain electrodes, and a pattern of an active layer;
wherein performing the patterning process on the roughened source-drain metal layer, and the oxide semiconductor layer to form the patterns of the source and drain electrodes, and the pattern of the active layer comprises:
forming a second photo-resist layer on the roughened source-drain metal layer;
exposing and developing the second photo-resist layer to form an area where all the second photo-resist is reserved, an area where all the second photo-resist is removed, and an area where a part of the second photo-resist is reserved, wherein the area where a part of the second photo-resist is reserved corresponds to a channel area, and the area where all the second photo-resist is reserved corresponds to the patterns of the source and drain electrodes to be formed;
in the area where all the second photo-resist is removed, etching the roughened source-drain metal layer and the oxide semiconductor layer to form the pattern of the active layer;
ashing the second photo-resist layer to remove all of the second photo-resist layer located in the area where a part of the second photo-resist was reserved; and subsequently etching in the area where the part of the second photo-resist was reserved to remove the roughened source-drain metal layer to form the patterns of the source and drain electrodes;
wherein after etching the roughened source-drain metal layer and the oxide semiconductor layer to form the pattern of the active layer, the method further comprises:
over-etching the roughened source-drain metal layer and the oxide semiconductor layer for a period of time which is 5% to 20% of a length of time of etching the roughened source-drain metal layer and the oxide semiconductor layer.

US Pat. No. 10,483,124

SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:a substrate;
a first stack above the substrate and including first insulation layers and first conductive layers alternately stacked in a first direction, the first stack including a staircase-shaped portion in an end part of the first stack in a second direction parallel to a main face of the substrate, the staircase-shaped portion including steps and terraces corresponding to the first conductive layers, at least a part of the steps having arc shape curved along a third direction crossing the second direction; and
at least one second stack above the substrate and including at least one first layer and at least one second layer stacked in the first direction,
wherein, in the at least one of the second direction and the third direction, a first dimension of the first stack is larger than a second dimension of the second stack.

US Pat. No. 10,483,123

METHOD FOR MAKING A WELL DISPOSED OVER A SENSOR

LIFE TECHNOLOGIES CORPORA...

1. A method for forming a well providing access to a sensor pad, the method comprising:patterning a first photoresist layer over a dielectric structure disposed over the sensor pad;
etching a first access into the dielectric structure and over the sensor pad, the first access having a first characteristic diameter;
depositing a bottom anti-reflective coating following etching the first access, wherein the bottom anti-reflective coating is at least partially disposed in the first access;
patterning a second photoresist layer over the dielectric structure after depositing a bottom anti-reflective coating; and
etching a second access over the dielectric structure and over the sensor pad, the second access having a second characteristic diameter, the first and second accesses overlapping, a diameter ratio of the first characteristic diameter to the second characteristic diameter being not greater than 0.7, the first access exposing the sensor pad, the second access having a bottom depth less than a bottom depth of the first access.

US Pat. No. 10,483,114

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING A NONVOLATILE MEMORY AND A MISFET

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device comprising a memory cell of a nonvolatile memory formed in a semiconductor substrate located in a first region, and a metal insulator semiconductor field effect transistor (MISFET) formed in the semiconductor substrate located in a second region,the memory cell including a first gate electrode, and a second gate electrode which are formed over the semiconductor substrate to be adjacent to each other, a first gate insulating film formed between the first gate electrode and the semiconductor substrate, and a second gate insulating film formed between the second gate electrode and the semiconductor substrate and having a charge storage portion therein,
the MISFET including a third gate electrode formed over the semiconductor substrate, and a third gate insulating film formed between the third gate electrode and the semiconductor substrate, the method comprising the steps of:
(a) providing the semiconductor substrate;
(b) forming, over the semiconductor substrate located in the first region, the first gate electrode via the first gate insulating film, and the second gate electrode via the second gate insulating film;
(c) forming, over the semiconductor substrate, a first film so as to cover the first region and to expose the second region;
(d) after the step (c), forming a second film including a first conductive film over the first film in the first region and over the semiconductor substrate in the second region;
(e) patterning the second film to form a dummy gate electrode for forming the third gate electrode in the second region;
(f) after the step (e), removing the first film;
(g) after the step (f), forming, over the semiconductor substrate, a first insulating film so as to cover the first gate electrode, the second gate electrode, and the dummy gate electrode;
(h) polishing an upper surface of the first insulating film to expose the dummy gate electrode;
(i) after the step (h), removing at least one part of the dummy gate electrode; and
(j) embedding a second conductive film in a region from which the dummy gate electrode has been removed in the step (i) to form the third gate electrode,
wherein, in the step (c), an upper surface of the first film is higher than upper surfaces of the first and the second gate electrodes.

US Pat. No. 10,483,112

METAL GATE STACK HAVING TAALCN LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a gate stack over a substrate by:
depositing a gate dielectric layer over the substrate;
depositing a multi-function layer over the gate dielectric layer, wherein the depositing the multi-function layer includes depositing a first metal nitride material with a first nitrogen (N) concentration to form a first sub-layer of the multi-function layer over the gate dielectric layer and depositing a second metal nitride material with a second N concentration to form a second sub-layer of the multi-function layer over the first sub-layer, wherein the first N concentration is greater than the second N concentration; and
depositing a work function layer over the multi-function layer.

US Pat. No. 10,483,109

SELF-ALIGNED SPACER FORMATION

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:forming a sacrificial film over a substrate;
creating a pattern in the sacrificial film;
conformally depositing a first spacer layer over the patterned sacrificial film;
removing horizontal portions of the first spacer layer while substantially leaving vertical portions of the first spacer layer; and
thereafter, performing a gas phase exposure, thereby selectively depositing a second spacer layer on the first spacer layer and not on the patterned sacrificial film, wherein the first spacer layer comprises a metal-containing layer that catalyzes the selective deposition of the second spacer layer on the first spacer layer.

US Pat. No. 10,483,108

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:patterning a middle layer and a bottom layer to expose a spacer material located over a hard mask, wherein prior to the patterning the middle layer and the bottom layer are located on a first side of the spacer layer and a semiconductor substrate is located on a second side of the spacer layer opposite the first side; and
applying an etchant to be in physical contact with both the middle layer and the spacer material, wherein the etchant comprises an inhibitor which inhibits an etch rate of the spacer material.

US Pat. No. 10,483,097

METHOD FOR CLEANING, PASSIVATION AND FUNCTIONALIZATION OF SI—GE SEMICONDUCTOR SURFACES

The Regents of the Univer...

1. A method for in-situ dry cleaning of a SiGe semiconductor surface, comprising:ex-situ, degreasing the Ge containing semiconductor surface;
ex-situ, removing organic contaminants;
dosing the SiGe surface with HF (aq), or with NH4F (g) generated via NH3+NF3 or via NF3 with H2 or H2O;
in-situ dosing the SiGe surface with atomic H to remove carbon contamination;
in-situ passivating with H2O2 (g); and
in-situ nucleating with trimethylaluminum (TMA).

US Pat. No. 10,483,096

DEVICE AND METHOD FOR ANALYSIS OF BIOFLUIDS BY ION GENERATION USING WETTED POROUS MATERIAL

Indiana University Resear...

1. A mass spectrometry cartridge comprising:a sample holder;
a base;
a solid phase extraction column, wherein the solid phase extraction column is disposed within the sample holder; and
a first absorbent unit, wherein the first absorbent unit is configured for use with a mass spectrometer.

US Pat. No. 10,483,076

APPARATUS, METHOD AND SYSTEM FOR THE CALIBRATION OF A STREAK CAMERA

MCMASTER UNIVERSITY, Ham...

1. An apparatus integrated into a streak camera for real-time calibration of a streak camera during acquisition of each streak camera observation, comprising:a fiber bundle, comprising
a plurality of fibers having an input face and an output face,
the plurality of fibers being made of a material selected on a basis of supporting fiber-optic transmission,
wherein the plurality of fibers comprises at least a first fiber and a second fiber,
wherein a light travel time is defined as the time taken for light to travel from the input face to the output face of the fiber,
wherein at least one time difference between light travel times is known; and
wherein after acquisition of each streak camera observation, processing light signals emitted from said output face of said fibers through the streak camera's varying electric field to convert the light signals' temporal profile to a spatial profile, comparing the spatial profile, acquired at the same time as the streak camera observation, to a known calibration profile in order to correct for unwanted drift, amplitude variation and phase variation for each streak camera observation.

US Pat. No. 10,483,069

HIGH-CURRENT FUSE WITH ENDBELL ASSEMBLY

LITTELFUSE, INC., Chicag...

1. A method of manufacturing a fuse comprising:providing a fuse element having a first end and a second end, a first terminal electrically connected to the first end and a second terminal electrically connected to the second end;
coupling a first endbell to the first end of the fuse element and coupling a second endbell to the second end of the fuse element, the first endbell having at least two grooves formed in a surface thereof and having a first O-ring seal disposed in at least one of the grooves, the second endbell having at least two grooves formed in a surface thereof and having a second O-ring seal disposed in at least one of the grooves;
inserting the fuse element into a hollow fuse tube having an inner cavity and at least two fuse body apertures formed therethrough, the first and second O-ring seals engaging an interior of the hollow fuse tube;
filling the hollow fuse tube with an amount of arc quenching material; and
fastening end caps onto ends of the hollow fuse tube;
wherein the first endbell and the second endbell are cup-shaped such that a first chamfer is formed within the first endbell and a second chamfer is formed within the second endbell.

US Pat. No. 10,483,057

INPUT DEVICE

Panasonic Intellectual Pr...

1. An input device comprising:a projection; and
a concavity-convexity portion that contacts the projection,
wherein the concavity-convexity portion includes a plurality of concavities, each of which changes position with respect to the projection,
wherein the concavity-convexity portion includes a plurality of convexities, each of which changes position with respect to the projection,
each of the plurality of concavities and each of the plurality of convexities is arranged alternately with each other, and
wherein the input device further comprises:
a first electrode;
a second electrode which opposes the first electrode;
a third electrode in contact with or spaced apart from the second electrode; and
a contact electrically connected to the second electrode and in contact with the third electrode; and
an insulating surface in contact with the contact, wherein:
when the projection is positioned at one of the plurality of concavities, the third electrode is spaced apart from the second electrode,
when the projection is positioned at one of the plurality of convexities, the third electrode is in contact with the second electrode,
second electrode is fixed with respect to the first electrode,
the contact is movable on the third electrode and the insulating surface,
when the projection is positioned at the one of the plurality of concavities, the contact is in contact with the insulating surface, and
when the projection is positioned at the one of the plurality of convexities, the contact is in contact with the third electrode.

US Pat. No. 10,483,056

PUSH SWITCH AND ELECTRONIC DEVICE INCLUDING PUSH SWITCH

CITIZEN ELECTRONICS CO., ...

1. A push switch comprising:a resilient member being made of metal, the resilient member comprising:
a concave shape being recessed downward in a plan view, and having a bowl shape and a curved surface;
an opening being positioned at a center of a bottom of the concave shape; and
at least two protrusions each protruding outward and downward with an oblique angle around the concave shape;
a light-emitting element being arranged in the opening that is positioned at the center of the bottom of the concave shape of the resilient member, the curved surface of the concave shape of the resilient member surrounding the light-emitting element, and being configured to reflect light emitted from the light emitting element upward;
an electrically-insulating member comprising upper electrodes being arranged on an upper surface of the electrically-insulating member, wherein
the upper electrodes comprise at least one first electrode and at least one second electrode, the at least one second electrode being positioned outside of the at least one first electrode, and
the center of the bottom of the concave shape of the resilient member is in constant contact with the at least one first electrode, at least one of the at least two protrusions being arranged above the at least one second electrode; and
a film comprising a light-transmitting resin, the film being arranged over the resilient member,
wherein the at least one of the at least two protrusions coming into electric contact with the at least one second electrode when the film is pressed down from above.

US Pat. No. 10,483,055

PROGRAMMABLE ARC FAULT CIRCUIT INTERRUPTER (AFCI)

Tower Manufacturing Corp....

1. A programmable Arc Fault Circuit Interrupter (PAFCI) for disengaging alternating current (AC) power from a load, the PAFCI comprising:a relay switch disposed between the AC power and the load;
a trigger circuit for actuating the relay switch;
a plurality of sensing devices disposed between the AC power and the load;
at least one sensing circuit connectable to the plurality of sensing devices, wherein the sensing circuit determines at least one circuit parameter; and
a processor circuit connectable to the trigger circuit, wherein the processor circuit determines from the at least one circuit parameter if an arcing condition exists; and
wherein the PAFCI does not include toroidal devices for sensing arcing conditions.

US Pat. No. 10,483,052

METHOD FOR CLEANING ELECTRICAL CONTACTS OF AN ELECTRICAL SWITCHING DEVICE AND MOTOR VEHICLE

AUDI AG, Ingolstadt (DE)...

1. A method for cleaning electrical contacts of an electrical switching device, said method comprising:displacing a first electrical contact element and a second electrical contact element of an electrical contact relative to each other so that the first electrical contact element and the second electrical contact element are in a closed position; and
when the first and second electrical contact elements are in the closed position, applying an electrical waveform using a control device so that the first contact element and the second contact element are excited to undergo a mechanical vibration relative to each other without leaving the closed position.

US Pat. No. 10,483,035

SUBSTRATES WITH INTEGRATED THREE DIMENSIONAL SOLENOID INDUCTORS

Qorvo US, Inc., Greensbo...

1. A substrate comprising:a substrate body; and
a three dimensional (3D) inductor integrated into the substrate body, wherein the 3D inductor comprises:
a first vertical interconnect access structure (via) having a first via attachment surface that defines a first via surface contour;
a first plating foil integrated into the first via to provide a second via attachment surface that is opposite the first via attachment surface and defines a second via surface contour;
a first winding having a first winding end;
a second plating foil integrated into the first winding to provide a first winding surface, wherein:
the first winding surface includes a first winding end surface section that defines an exterior edge contour of the first winding end; and
the first winding end surface section is directly attached to the first via attachment surface such that an exterior edge contour of the first winding end surface section is substantially aligned with and is substantially the same as an exterior edge contour of the first via surface contour; and
a second winding having a second winding end and a second winding surface wherein the second winding end has a second winding end surface section provided by the second winding surface, wherein:
the second winding end surface section is attached to the second via attachment surface such that an exterior edge contour of the second winding end surface section is substantially aligned with and is substantially the same as an exterior edge contour of the second via surface contour; and
the first winding and the second winding are substantially aligned around a common axis, such that current is able to propagate through the first winding and the second winding in a same rotational direction.

US Pat. No. 10,483,029

CORE MEMBER, REACTOR, AND METHOD FOR MANUFACTURING CORE MEMBER

AutoNetworks Technologies...

1. A core member obtained by molding a mixture containing soft magnetic powder and a resin, the core member comprising:a base portion and a pair of projecting portions spaced apart from each other and projecting from the base portion;
an installation surface disposed on a bottom portion of the base portion, the installation surface facing an object on which the core member is to be installed and an interlinkage surface disposed on an end of each of the projecting portions, the interlinkage surface being intersected by a magnetic flux excited by a coil; and
wherein the installation surface and the interlinkage surface has a higher density than the base portion and the pair of projecting portions.

US Pat. No. 10,483,025

SUPERCONDUCTIVE COIL MODULE INCLUDING A SHAKING COIL

Korea University Research...

1. A superconductive coil module comprising:a superconductive coil including a bobbin having a cylindrical shape, and a superconductive wire member of superconductive property, surrounding an outer circumferential surface of the bobbin, the superconductive coil being configured to generate a magnetic field along a radial direction in case of a charging event;
a shaking coil being disposed adjacent to the superconductive wire member, and being configured to generate an alternating magnetic field to decrease a magnitude of a screening current induced magnetic field formed in the superconductive wire member; and
a spacer being interposed between the superconductive wire member and the shaking coil, and being configured to prevent an electrical short between the superconductive member and the shaking coil.

US Pat. No. 10,483,020

TWISTED PAIR DATA COMMUNICATION CABLE WITH INDIVIDUALLY SHIELED PAIRS USING DISCONTINUOUS SHIELDING TAPE

NEXANS, Courbevoie (FR)

1. A LAN cable comprising:four twisted pairs of insulated conductors;
a jacket surrounding said twisted pairs; and
at least two discontinuous shield tapes each having a plurality of separated metal segments,
wherein said discontinuous shielding tapes are folded and arranged between said four twisted pairs in a partially overlapping manner, separating each of said four pairs from one another.

US Pat. No. 10,483,013

INSULATED WIRE EXCELLENT IN BENDING RESISTANCE, AS WELL AS COIL AND ELECTRIC OR ELECTRONIC EQUIPMENT USING THE SAME

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire having an insulating coat layer comprising a thermoplastic resin on an outer peripheral surface of a conductor having a rectangular cross-sectional shape and also having a long side, a short side, and a corner portion having a curvature radius Rc,wherein a thickness t1 (?m) of the insulating coat layer covered on a surface which is continuing in an axial direction of the conductor, and which layer includes a long side of a transverse section of the conductor, a thickness t2 (?m) of the insulating coat layer covered on the surface which is continuing in the axial direction of the conductor, and which layer includes a short side of the transverse section of the conductor, and a corner portion thickness t3 (?m) of the insulating coat layer satisfy formula (1):
t3/{(t1+t2)/2}?1.2  Formula (1)
wherein the t1 (?m) and t2 (?m) are each independently 20 ?m or more and 50 ?m or less, and
wherein a ratio of a cross-sectional area Sc (mm2) of the conductor to a cross-sectional area Sw (mm2) of the insulated wire satisfies formula (2):
1.0>Sc/Sw?0.8.  Formula (2)

US Pat. No. 10,483,007

MODULAR TELEHEALTH CART WITH THERMAL IMAGING AND TOUCH SCREEN USER INTERFACE

INTOUCH TECHNOLOGIES, INC...

1. A telemedicine system comprising:a cart that supports a controller coupled to a camera system, a touchscreen display, a microphone, a speaker, and a network, the controller is configured to display a user interface on the touchscreen display in response to a user input received via the touchscreen display, the user interface including at least a first selectable option that causes video captured by the camera system to be displayed on the touchscreen display and a second option to transmit a request for consultation via the network; and
a remote device coupled to the controller via the network, the remote device including a camera, a display, a microphone, and a speaker and configured to establish a communication session with the controller, wherein the first selectable option causes video captured by the camera system to be displayed on the touchscreen when the system is not in session and, during the communication session, the controller causes the touchscreen display to display video captured by the camera of the remote device.

US Pat. No. 10,483,003

DYNAMICALLY DETERMINING RISK OF CLINICAL CONDITION

Cerner Innovation, Inc., ...

1. One or more computer-readable hardware devices having computer-executable instructions embodied thereon that when executed by at least a processor, facilitate at least an apparatus to:receive a portion of patient health data for a patient, the portion of patient health data including a first set of clinical concepts encoded in a first nomenclature associated with a healthcare entity;
convert the first set of clinical concepts encoded in the first clinical nomenclature to a second set of clinical concepts encoded in a second nomenclature;
determine, from the second set of clinical concepts encoded in the second nomenclature, a current state of the patient;
accessing a library of clinical condition programs that are encoded in the second nomenclature to construct a clinical condition computer program routine for the patient based on the determined current state of the patient;
use the clinical condition computer program routine to determine a set of risk factors specifically associated with a combination of at least two concurrent clinical conditions, the set of risk factors having one or more clinical concepts encoded in the second nomenclature;
convert the one or more clinical concepts associated with the set of risk factors encoded in the second nomenclature to respective one or more clinical concepts encoded in the first nomenclature; and
cause for display the set of risk factors having the respective one or more clinical concepts encoded in the first nomenclature to a healthcare provider of the patient.

US Pat. No. 10,482,998

CELL PROCESSING TECHNIQUES

General Electric Company,...

1. A cell therapy manufacturing tracking system, comprising:a cell therapy sample;
a sample container configured to hold the cell therapy sample;
a reader co-located with a sample processing location and configured to receive an identification signal from a first tracking device coupled to the sample container;
a sample processing device configured to process the cell therapy sample;
a second tracking device coupled to the sample processing device;
a controller operatively coupled to the reader and configured to:
access a cell therapy processing protocol associated with the identification signal upon receipt of the identification signal;
determine if the cell therapy sample is being processed according to the processing protocol;
provide an error signal to the sample processing device when the cell therapy sample is not being processed according to the processing protocol;
provide a verification signal to the sample processing device when the cell therapy sample is being processed according to the processing protocol;
prevent continuing operation of the sample processing device based on the error signal; and
permit continuing operation of the sample processing device based on the verification signal;
wherein one or both of the error signal and the verification signal is based on signals from the first tracking device coupled to the sample container, the second tracking device coupled to the sample processing device, and a third tracking device coupled to an operator badge.

US Pat. No. 10,482,989

DYNAMIC DIAGNOSTICS ANALYSIS FOR MEMORY BUILT-IN SELF-TEST

1. A memory built-in self-test (“MBIST”) diagnostics system, comprising:a memory, wherein the memory is tested with an algorithm for a plurality of passes;
a data compare unit;
a tester; and
a processor, wherein:
during a first pass of the test, the data compare unit is configured to provide, to the tester, a clock cycle associated with a word of the memory including at least one mis-compare,
during at least a second pass of the test, the data compare unit is further configured to (i) extract contents of the word based on the corresponding clock cycle and (ii) provide the extracted contents of the word to the tester, and
the processor is configured to generate a bit fail map report based on the extracted contents of the word, wherein the bit fail map report includes information associated with the at least one mis-compare.

US Pat. No. 10,482,988

RECLAIMABLE SEMICONDUCTOR DEVICE PACKAGE AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method of reclaiming a semiconductor device package having a plurality of semiconductor dies arranged in at least a first module of a first plurality of semiconductor dies and a second module of a second plurality of semiconductor dies, the method comprising:determining whether a first semiconductor die in the first module is inoperable and whether a second semiconductor die in the second module is inoperable, wherein the second semiconductor die is different from the first semiconductor die;
storing a configuration state at a third semiconductor die in the semiconductor device package based on whether the first semiconductor die is inoperable and the second semiconductor die is inoperable, the configuration state indicative of which modules in the semiconductor device package are operable;
coupling a package contact of the semiconductor device package with a first contact on a support substrate when none of the modules are inoperable; and
coupling the package contact of the semiconductor device package with a second contact on the support substrate when at least one of the modules is inoperable, wherein the second contact is different from the first contact.

US Pat. No. 10,482,983

READ DISTURB DETECTION BASED ON DYNAMIC BIT ERROR RATE ESTIMATION

Seagate Technology LLC, ...

1. A method comprising:counting a number of read operations applied to a first location in a non-volatile memory (NVM) to provide a read disturb count (RDC) value;
reducing the RDC value to a reduced level responsive to the RDC value reaching a predetermined RDC threshold level and responsive to a bit error statistic (BES) value indicating an acceptable rate of read errors occurred during the application of the number of read operations to the first location using a first BES threshold level;
counting additional read operations applied to the first location after the RDC value has been reduced to increase the RDC value from the reduced level; and
relocating data from the first location to a second location in the NVM responsive to the RDC value reaching the first threshold level at least a second time and the BES value indicating an unacceptable rate of read errors occurred during the application of the additional read operations using a different, second BES threshold level less than the first BES threshold level.

US Pat. No. 10,482,976

MEMORY DEVICE PERFORMING UV-ASSISTED ERASE OPERATION

SK hynix Inc., Gyeonggi-...

1. A nonvolatile memory device, comprising:a plurality of word lines that are stacked;
a pillar structure that penetrates through the word lines in a vertical direction; and
a voltage supplier suitable for supplying a plurality of biases that are required according to an operation mode, to the word lines and the pillar structure,
wherein the pillar structure includes:
a vertical channel region disposed in a core; and
a laser diode structure disposed between the word lines and the vertical channel region to surround a periphery of the vertical channel region.

US Pat. No. 10,482,975

FLASH MEMORY CELL WITH DUAL ERASE MODES FOR INCREASED CELL ENDURANCE

MICROCHIP TECHNOLOGY INCO...

1. A method, comprising:providing a memory cell including a floating gate and a pair of program/erase nodes over the floating gate; and
selectively alternate between the pair of program/erase nodes after every N erase functions, wherein N is greater than 1, to perform a series of erase functions in the memory cell.

US Pat. No. 10,482,972

MEMORY AS A PROGRAMMABLE LOGIC DEVICE

Micron Technology, Inc., ...

1. A memory, comprising:a data line;
a plurality of strings of series-connected memory cells selectively connected to the data line;
a plurality of first access lines, wherein, for each first access line of the plurality of first access lines, that first access line is coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells; and
a plurality of second access lines, wherein, for each second access line of the plurality of second access lines, that second access line is coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.

US Pat. No. 10,482,966

BLOCK DECODER OF NONVOLATILE MEMORY AND LEVEL SHIFTER

WINBOND ELECTRONICS CORP....

15. A level shifter, comprising:a first transistor, wherein the first transistor has a control terminal coupled to a first control node, a first terminal coupled to an output node, and a second terminal coupled to a first supply voltage;
a second transistor, wherein the second transistor has a control terminal coupled to a second control node, a first terminal coupled to a ground voltage, and a second terminal coupled to the output node;
a third transistor, wherein the third transistor has a control terminal coupled to the output node, a first terminal coupled to a first node, and a second terminal coupled to a second supply voltage; and
a fourth transistor, wherein the fourth transistor has a control terminal coupled to the second control node, a first terminal coupled to the first node, and a second terminal coupled to the output node.

US Pat. No. 10,482,961

MEMORY SYSTEM HAVING RESISTIVE MEMORY DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A memory system comprising:a resistive memory device comprising a memory cell array including a plurality of resistive memory cells and a peripheral circuit; and
a memory controller suitable for generating data bus inversion (DBI) information which corresponds to write data based on an access history of the resistive memory cell corresponding to an address of the write data, and providing the DBI information, the address and the write data to the peripheral circuit,
wherein the peripheral circuit is suitable for selectively inverting the write data based on the DBI information and writing the selectively inverted write data in a memory cell selected according to the address among the resistive memory cells, and
wherein the peripheral circuit applies a set pulse to the selected memory cell when writing a first logic bit of the write data, and applies a reset pulse to the selected memory cell when writing a second logic bit of the write data.

US Pat. No. 10,482,944

SEMICONDUCTOR DEVICES

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:an initial buffer signal generation circuit configured to include an initial buffer circuit which is activated if an initialization operation terminates and configured to generate an initial buffer signal from an external control signal in response to a first reference voltage signal; and
a buffer signal generation circuit configured to include a buffer circuit which is activated in response to the initial buffer signal and configured to generate a buffer signal from the external control signal in response to a second reference voltage signal;
wherein the initial buffer signal has a first logic level if the external control signal has a level which is greater than or equal to a level of the first reference voltage signal, and wherein the initial buffer signal has a second logic level if the external control signal has a level which is less than the level of the first reference voltage signal.

US Pat. No. 10,482,922

DATA RECORDING METHOD AND APPARATUS

Amazon Technologies, Inc....

1. A computer-implemented method, comprising:in a pass of a magnetic tape through a tape drive,
writing first data to a location on a first data track of the magnetic tape, the first data track partially overlapping a portion of an adjacent data track on the magnetic tape;
verifying that the first data is correctly written to the magnetic tape by reading second data from the location on the first data track and verifying that the first data matches the second data; and
verifying that data on a non-overlapped portion of the adjacent track is recoverable by reading third data from the non-overlapped portion of the adjacent data track.

US Pat. No. 10,482,919

WRITE MANAGEMENT OF PHYSICALLY COUPLED STORAGE AREAS

SEAGATE TECHNOLOGY LLC, ...

1. A method comprising:transmitting read/write characteristics of a logical block address space, the read/write characteristics including coupling information characterizing a physical arrangement of data blocks associated with different logical zones in the logical block address space; and
executing a write command instructing a data write to a target logical zone of the logical zones, the write command generated based on the transmitted coupling information.

US Pat. No. 10,482,918

CHANGING BIT SPACING FOR SELECTED SYMBOLS WRITTEN TO A MAGNETIC RECORDING MEDIUM

Seagate Technology LLC, ...

1. A method, comprising:writing a plurality of different symbols to a magnetic recording medium at a nominal bit timing;
determining a first set of the symbols that result in a relatively high error when read back;
upon writing subsequent to the determining of the first set of symbols, identifying one symbol of the first, set of symbols within a data segment ready to be mitten to the magnetic recording medium; and
writing the data segment with increased bit spacing relative to the nominal bit timing in response to identifying that the one symbol of the first set of symbols is within the data segment.

US Pat. No. 10,482,911

MULTIPLE-ACTUATOR DRIVE THAT PROVIDES DUPLICATION USING MULTIPLE VOLUMES

Seagate Technology LLC, ...

1. A data storage drive comprising:interface circuitry configured to communicate with:
first and second actuators enclosed within the drive that operate independently; and
first and second read/write heads enclosed within the drive and respectively moved over one or more disks by the first and second actuators, the one or more disks driven by a single spindle motor enclosed within the drive; and
a controller coupled to the interface circuitry and operable to:
form a first drive volume of the one or more disks that is read from and written to by the first read/write head;
form a second drive volume of the one or more disks that that is read from and written to by the second read/write head, the second volume duplicating data of the first drive volume; and
perform background validation operations on the second drive volume and not the first drive volume.

US Pat. No. 10,482,907

METHODS OF PROTECTING WRITE POLE FROM CORROSION IN HAMR HEAD

Western Digital Technolog...

1. A heat assisted magnetic recording (HAMR) head for writing to a HAMR medium, comprising:a near field transducer (NFT) comprising an end proximal to an air bearing surface (ABS) and configured to direct light from a laser to a region on the HAMR medium; and
a write pole configured to write to the region on the HAMR medium and comprising a bottom surface proximal to the ABS, a first side proximal to the NFT and a second side opposite the first side;
wherein the write pole comprises a recessed part extending from a portion of the bottom surface along a portion of the first side;
wherein the portion of the bottom surface has a length less than a total length of the bottom surface and the portion of the first side has a height less than a total length of the first side;
wherein the recessed part is embedded in the write pole.

US Pat. No. 10,482,901

SYSTEM AND METHOD FOR BEEP DETECTION AND INTERPRETATION

Alarm.com Incorporated, ...

1. A monitoring system for monitoring a property, the monitoring system comprising:one or more processors; and
one or more storage devices, the one or more storage devices storing instructions that, when executed by the one or more processors, cause the one or more processors to perform operations comprising:
obtaining, by the monitoring system, sound data of audio sounds detected by a microphone that is located at the property;
determining, by the monitoring system, whether the sound data includes data representing one or more audio tones generated by a device;
based on determining that the obtained sound data includes one or more audio tones generated by a device, generating, by the monitoring system, an audio fingerprint of the sound data;
generating, by the monitoring system, a query that includes the generated audio fingerprint as a search parameter;
obtaining, by the monitoring system and in response to the generated query, (i) a device identifier of the device that generated the one or more audio tones and (ii) a state of the device that generated the one or more audio tones; and
performing, by the monitoring system, one or more operations based on at least one of the device identifier and the state of the device that generated the one or more audio tones.

US Pat. No. 10,482,899

COORDINATION OF BEAMFORMERS FOR NOISE ESTIMATION AND NOISE SUPPRESSION

Apple Inc., Cupertino, C...

1. A process for adaptively selecting two or more beams from among a plurality of acoustic pickup beams that are produced by a beamforming process using a plurality of microphone signals from a plurality of microphones, the process comprising: producing the plurality of acoustic pickup beams based on groups of the plurality of microphones, wherein the groups are determined based on an estimation of voice activity and an estimation of noise characteristics in the microphones signals; and selecting the two or more beams from among the plurality of acoustic pickup beams, including a voice beam and a noise beam, based on thresholds for voice-separation and thresholds for noise-matching, whereinduring a period where a desired voice is deemed active, indicating presence of speech, difference between a strength of a component of the noise beam and a strength of a component of the voice beam are compared to a threshold for voice separation to determine whether there is sufficiently large voice separation between the noise beam and the voice beam, and
during a period where the desired voice is deemed inactive, indicating non-speech, difference between a strength of a component of the noise beam and a strength of a component of the voice beam are compared to a threshold for noise-matching to determine whether there is sufficient noise matching between the noise beam and the voice beam, and
wherein the voice beam is used to pick up a voice signal and the noise beam is used to provide information to estimate a noise signal; and wherein
it is determined whether the two or more beams meet the threshold for noise-matching by a) obtaining ratios between the strength of a component of the noise beam in the noise beam and a strength of a component of the voice beam over a time interval, b) comparing the ratios to the threshold for noise-matching, and c) if the threshold for noise-matching is met, setting a correction factor for noise-matching; and
it is determined whether the two or more beams meet the threshold for voice separation by calculating adjusted ratios by applying the correction factor to initial ratios between the strength of a component of the noise beam and the strength of a component of the voice beam.

US Pat. No. 10,482,896

MULTI-BAND NOISE REDUCTION SYSTEM AND METHODOLOGY FOR DIGITAL AUDIO SIGNALS

Retune DSP ApS, Kongens ...

1. A hearing instrument comprising:a microphone arrangement for picking-up acoustic signals from the surrounding environment and generating one or more microphone signals in response; and
a multi-band noise reduction system for digital audio signals comprising:
a signal input for receipt of a digital audio input signal originating from the one or more microphone signals, an analysis filter bank configured for dividing the digital audio input signal into a plurality of sub-band signals Yk(n),
a noise estimator configured for determining respective sub-band noise estimates ?k2(n) of the plurality of sub-band signals Yk(n),
a first signal-to-noise ratio estimator configured for determining respective first signal-to-noise ratio estimates ?k0(n) of the plurality of sub-band signals based on the respective sub-band noise estimation signals and the respective sub-band signals Yk(n),
a second signal-to-noise ratio estimator configured for filtering the plurality of first signal-to-noise ratio estimates ?k0(n) of the plurality of sub-band signals Yk(n) with respective time-varying low-pass filters to produce respective second signal-to-noise ratio estimates ?k(n) of the plurality of sub-band signals Yk(n) wherein a low-pass cut-off frequency of each of the time-varying low-pass filters is adaptable in accordance with the first signal-to-noise ratio estimate of the sub-band signal or the second signal-to-noise ratio estimate of the sub-band signal,
a gain calculator configured for applying respective time-varying gains Gk (n) to the plurality of sub-band signals Yk(n) based on the respective second signal-to-noise ratio estimates ?k(n) and respective sub-band gain laws to produce a plurality of noise compensated sub-band signals, and
a synthesis filter bank configured to combine the plurality of noise compensated sub-band signals into a noise reduced digital audio output signal at a signal output.

US Pat. No. 10,482,891

ENABLING SAMPLING RATE DIVERSITY IN A VOICE COMMUNICATION SYSTEM

Dolby Laboratories Licens...

1. A audio communication server for exchanging bitstreams with a plurality of audio communication endpoints,each of said bitstreams containing spectral components representing spectral content of an audio signal and conformal to a predefined bitstream format allowing transmission of spectral components up to a maximum frequency,
wherein the spectral components in each incoming bitstream relate to a frequency range extending up to an input break frequency which is selectable by each corresponding audio communication endpoint,
said server comprising:
a mixer configured to receive a plurality of incoming bitstreams and to output, based thereon, a bitstream representing an audio signal being an additive mix of at least one of the incoming bitstreams; and
a selector configured to output, from the audio communication server, an outgoing bitstream being either a bitstream output by the mixer or a bitstream reproducing an active one of the incoming bitstreams,
wherein the selector is configured to monitor the incoming bitstreams for audio activity and to output, in response to having exactly one active incoming bitstream, an outgoing bitstream reproducing the active incoming bitstream.

US Pat. No. 10,482,883

CONTEXT-SENSITIVE DYNAMIC UPDATE OF VOICE TO TEXT MODEL IN A VOICE-ENABLED ELECTRONIC DEVICE

GOOGLE LLC, Mountain Vie...

1. A method, comprising:receiving a voice input with a voice-enabled electronic device, the voice input including an original request that includes first and second portions, the second portion including a first context sensitive entity among a plurality of context sensitive entities that are associated with a context sensitive parameter and that potentially may be spoken in the voice input; and
in the voice-enabled electronic device, and responsive to receiving the first portion of the voice input:
performing local processing of the first portion of the voice input;
determining during the local processing that the first portion is associated with the context sensitive parameter; and
in response to determining that the first portion is associated with the context sensitive parameter, and prior to performing local processing of the second portion of the voice input including the first context sensitive entity:
dynamically updating a local voice to text model, used by the voice-enabled electronic device, to augment the local voice to text model based on the context sensitive entities associated with the context sensitive parameter, wherein dynamically updating the local voice to text model facilitates recognition of the first context sensitive entity in performing local processing of the second portion of the voice input.

US Pat. No. 10,482,880

COMMAND AND CONTROL OF DEVICES AND APPLICATIONS BY VOICE USING A COMMUNICATION BASE SYSTEM

CenturyLink Intellectual ...

13. A device control system comprising;a first device;
a second device; and
a base station storing computer executable instructions for wirelessly controlling the second device using voice-commands that, when executed, cause the base station to:
establish a wireless communication path directly between the first device and the base station;
establish a second wireless communication path between the base station and the second device;
receive a communication from the first device;
identify, with a command processing module, during the communication from the first device, a speech pattern as including a voice-command by detecting an address word, wherein the address word is associated with the base station and is unassociated with the voice-command;
determine a second device operation corresponding to the voice-command; and
communicate a command corresponding to the second device operation to the second device.

US Pat. No. 10,482,877

REMOTE SENSOR VOICE RECOGNITION

Hewlett-Packard Developme...

1. A computing device comprising:a processor; and
a non-transitory computer readable medium coupled to the processor and comprising instructions that when executed by the processor cause the processor to:
establish a bi-directional wireless communication link between the computing device and a remote sensor comprising a speaker and a microphone, the remote sensor separate from the computing device;
transmit a first audio signal to the remote sensor for playback on the speaker;
receive a second audio signal from the microphone in the remote sensor;
process the second audio signal to generate a processed audio signal;
send the processed audio signal to a voice recognition routine to recognize a voice command within the processed audio signal; and
initiate an automation command controlling the first audio signal transmitted to the remote sensor for playback on the speaker, based on the recognized voice command,
wherein the processor is to process the second audio signal to generate the processed audio signal by:
detecting the first audio signal within the second audio signal;
determining a time delay between the first audio signal as transmitted to the remote sensor and the first audio signal as detected within the second audio signal;
time-shifting the first audio signal as detected within the second audio signal according to the determined time delay; and
subtracting the time-shifted first audio signal as detected within the second audio signal from the second audio signal,
and wherein the computing device is to both transmit the first audio signal to the remote sensor and receive back the second audio signal from the remote sensor.

US Pat. No. 10,482,871

METHOD FOR PROCESSING SIGNALS, TERMINAL DEVICE, AND NON-TRANSITORY COMPUTER-READABLE STORAGE MEDIUM

Guangdong Oppo Mobile Tel...

1. A method for processing signals, comprising:recording, via a microphone of a headphone, a sound signal of external environment when the headphone is in a playing state;
identifying feature audio in the sound signal and acquiring reminding information corresponding to the feature audio;
inquiring of a user whether recorded sound signal is critical according to the reminding information, in response to the headphone being paused; and
detecting an input operation of the user and processing the sound signal according to the input operation of the user.

US Pat. No. 10,482,864

PORTABLE ACOUSTICAL BLOCKING SYSTEM

L.J. AVALON LLC, Tampa, ...

1. A portable acoustical blocking system for use with a support, comprising:a sheet of acoustical blocking material having a first and a second side and bound by material edge;
said sheet of acoustical blocking material having a thickness of approximately one-eighth of an inch and a density of greater than one pound per square foot;
a flexible reinforcing tape permanently affixed to said first side of said sheet of acoustical blocking material adjacent to said material edge;
a plurality of hangers secured to said sheet of acoustical blocking material and extending through said reinforcing tape and said sheet of acoustical blocking material for hanging said sheet of acoustical blocking material from the support for inhibiting the flow of acoustic energy between said first and second sides of the acoustical blocking material; and
said sheet of acoustical blocking material and said reinforcing tape being flexible for enabling the entire portable acoustical blocking system including said sheet of acoustical blocking material and reinforcing tape to be rolled as a single unit for transportation.

US Pat. No. 10,482,857

MEDIA-MEDIA AUGMENTATION SYSTEM AND METHOD OF COMPOSING A MEDIA PRODUCT

MASHTRAXX LIMITED, Warwi...

1. A media-content augmentation system comprising:a database containing a multiplicity of media files and associated metadata, each media file or part thereof mapped to at least one contextual theme defined by beginning and end timings;
a processing system coupled to the database and responsive to said metadata; and
an input coupled to the processing system, the input in the form of temporally-varying events data;
wherein the processing system is arranged:
to resolve the input into one or more of a plurality of categorized contextual themes;
to correlate said categorized contextual themes with metadata associated with selected media files or part thereof relevant to the one or more of the plurality of categorized contextual themes, and thereafter
to splice or fade together selected media files or part thereof to reflect said events as the input varies with time, thereby to generate, as an output, a media product in which transitions between media files or parts thereof are aligned with the temporally-varying events and wherein said temporarily-varying events take the form of one of:
a beginning and an end in the case of a sustained feature for the contextual theme, wherein the sustained features is one of a form function and a hit point over time; and
a specific point in time for a hit point.

US Pat. No. 10,482,855

HI-HAT CYMBAL SOUND GENERATION APPARATUS, HI-HAT CYMBAL SOUND GENERATION METHOD, AND RECORDING MEDIUM

KORG INC., Tokyo (JP)

1. A hi-hat cymbal sound generation apparatus that generates a sound of hi-hat cymbals based on information on an operation to a top pad, which corresponds to a top cymbal, and a bottom pad, which corresponds to a bottom cymbal, the top pad and the bottom pad being attached to a hi-hat stand with a pedal,wherein a distance between the top pad and the bottom pad is changeable by an operation of the pedal,
state information is information that indicates which of a predetermined number of states a state is, the state being determined by the distance between the top pad and the bottom pad,
of the states, a state in which the top pad and the bottom pad are closest to each other is designated as a close state, and
the hi-hat cymbal sound generation apparatus comprises:
an input that acquires at least the state information and vibration information, which is information on a vibration of the top pad;
a recorder that records data on a foot close sound that corresponds to a sound in the close state generated by the top cymbal and the bottom cymbal coming into contact with each other in response to an operation of the pedal, data on a foot open sound that corresponds to a sound in a state other than the close state generated by the top cymbal and the bottom cymbal coming into contact with each other in response to an operation of the pedal, and data on a predetermined number of hit sounds, which correspond to sounds generated by hitting in the states indicated by the state information;
a trigger that checks whether the vibration indicated by the vibration information falls within a predetermined range in which a sound generation procedure is to be started, and starts sound generation procedures for at least all the hit sounds when the trigger determines that the vibration falls within the range in which a sound generation procedure is to be started; and
a sound volume controller that generates an output signal by controlling a sound volume of each sound whose sound generation procedure is being performed based on the current state information and information on a change of the distance between the top pad and the bottom pad.

US Pat. No. 10,482,846

DISPLAY DEVICE HAVING PROCESSOR THAT CONTROLS COMMUNICATION WITH EXTERNAL DEVICE, CONTROL METHOD FOR DISPLAY DEVICE, AND DISPLAY SYSTEM

SEIKO EPSON CORPORATION, ...

1. A display device comprising:a communication line configured to perform communication with an external display device;
a display configured to display an image corresponding to image information; and
a processor configured to cause the communication line to transmit first information to the external display device and, when waiting to receive second information from the external display device via the communication line after causing the communication line to transmit the first information to the external display device, prohibit the display from displaying the image for a first period and thereafter cause the display to display the image,
wherein the processor starts preparation for displaying the image according to power-on of the display device and, after the preparation is completed, causes the communication line to transmit the first information to the external display device, and
wherein, when the communication line has not received the second information for a second period after the processor prohibits the display section from displaying the image according to the transmission of the first information, the processor causes the display to display the image; when the communication line receives the second information before the second period elapses, the processor prohibits the display from displaying the image for the first period and thereafter causes the display to display the image; and, when the second information reaches the communication line after the second period elapses, the processor causes the display to maintain the display of the image.