US Pat. No. 10,431,884

RADAR COVER AND METHOD OF MANUFACTURING RADAR COVER

FALTEC CO. LTD., Kawasak...

1. A radar cover for covering a radar unit which detects a situation around a vehicle, comprising:a base portion having a convex shape;
a bright layer which is formed on whole of a convex-side surface of the base portion and is a discontinuous metal layer having openings penetrating therethrough in a layer thickness direction; and
a transparent top coat layer formed on whole of the bright layer, parts of the top coat layer in close contact with the convex-side surface of the base portion through the openings of the bright layer.

US Pat. No. 10,431,883

ANTENNA SYSTEM FOR DOWNHOLE TOOL

SCHLUMBERGER TECHNOLOGY C...

1. A system for communicating signals, comprising:a plurality of components positioned in a wellbore, at least one of the components being coupled with an antenna for communication of signals along the wellbore, the antenna comprising:
a coil of wire which is wet wound, the wire having a conductive core coated with amorphous polyetheretherketone (PEEK), the wire further having a beginning portion and an ending portion which extend away from the coil for connection with the at least one of the components;
a first protective sleeve placed over the beginning portion of the wire and a second protective sleeve placed over the ending portion of the wire to protect the wire where it extends away from the coil; and
a layer of glass tape wrapped around the coil.

US Pat. No. 10,431,880

VEHICLE ANTENNA DEVICE

YOKOWO CO., LTD., Tokyo ...

1. A vehicle antenna device comprising:an antenna base;
an antenna case which is overlaid on the antenna base; and
an antenna element and an amplifier board which are disposed inside the antenna case, wherein
the antenna element has a capacitive element and a coil element,
the coil element is a winding held by a supporting portion,
a plurality of projections are disposed on the supporting portion and along an axial direction of the coil element,
at least one of the plurality of projections is provided between one end portion and the other end portion of an area of the supporting portion where the winding is held, and
at least one winding end portion of the coil element is hooked on one of the plurality of projections.

US Pat. No. 10,431,879

FABRIC ANTENNA

BAE SYSTEMS plc, London ...

1. A fabric antenna for telecommunications, the fabric antenna comprising:a host yarn, which is substantially electrically non-conductive, and
an antenna yarn, which is substantially electrically conductive, the host yarn and antenna yarn being knitted together to form a host fabric formed of host yarn comprising an antenna grid formed of antenna yarn,
wherein the antenna grid comprises a plurality of intersecting antenna tracks formed of antenna yarn, the tracks being separated by regions of the host yarn, the tracks of the antenna grid being electrically coupled together at the regions where the tracks intersect,
wherein the antenna grid comprises a plurality of grid sections,
wherein a first grid section of the plurality of grid sections comprises a first side track, a second side track, a first end track, and a second end track,
wherein the first end track and the second end track separately extend between opposite ends of the first side track and the second side tracks, and
wherein the first side track, the second side track, the first end track, and the second end track form a closed periphery of the first grid section.

US Pat. No. 10,431,878

WEARABLE DEVICE DESIGN FOR 4G ANTENNAS

Verizon Patent and Licens...

1. A wearable device, comprising:an outer wall defining a circumference of an inner core portion of the wearable device, wherein a first portion of the outer wall includes a first material and a second portion of the outer wall includes a second material that is different from the first material;
a bottom cover, coupled to a bottom portion of the outer wall, defining a bottom most portion of the inner core portion of the wearable device;
a bezel, coupled to a top portion of the outer wall, defining a top portion of the inner core portion of the wearable device, wherein a first portion of the bezel includes the first material, wherein the first portion of the bezel and the first portion of the outer wall form a contiguous gap feature that includes the first material;
a connector portion coupled to an outer edge of the outer wall, wherein the outer wall includes an opening proximate to the connector portion, such that the connector portion and the outer wall include a contiguous space;
a printed circuit board (PCB), coupled to the bottom cover by one or more metal nodes such that a first vertical space is formed between the PCB and the bottom cover,
wherein the PCB comprises circuitry to enable the wearable device to communicate with a wireless telecommunication network,
wherein the PCB extends through the opening and is situated partially within the connector portion; and
an antenna, through which the PCB communicates with the wireless telecommunications network, wherein the antenna is positioned along a circumference of an inner portion of the outer wall and above the PCB to create a second vertical space between the antenna and the PCB,
wherein the antenna includes a first antenna portion and a second antenna portion that are arranged separately along the circumference of the outer wall such that a gap exists between the first antenna portion and the second antenna portion, and
wherein the first antenna portion and the second antenna portion are positioned within the inner core portion, below the bezel and not in contact with the bezel, and above the bottom cover.

US Pat. No. 10,431,877

BASE STATION ANTENNAS HAVING PARASITIC COUPLING UNITS

CommScope Technologies LL...

1. A base station antenna, comprising:a panel that includes a ground plane;
a first linear array that includes a first plurality of radiating elements that extend forwardly from the panel, the first linear array extending along a first axis;
a second linear array that includes a second plurality of radiating elements that extend forwardly from the panel, the second linear array extending along a second axis that is generally parallel to the first axis; and
a parasitic coupling unit between a first radiating element of the first linear array and a first radiating element of the second linear array and between the first axis and the second axis,
wherein the parasitic coupling unit includes a first parasitic coupling structure, the first parasitic coupling structure including a first base that is capacitively coupled to the ground plane and a first wall that extends forwardly from the first base, the first wall including at least one slot,
wherein the ground plane includes a planar portion, the radiating elements extend forwardly from the planar portion of the ground plane, and the first base extends in parallel to the planar portion of the ground plane, and
wherein the first base, the first radiating element of the first linear array and the first radiating element of the second linear array are all on a same side of the ground plane.

US Pat. No. 10,431,873

DIVERSITY ANTENNA FOR BODYPACK TRANSMITTER

Shure Acquisitions Holdin...

1. An antenna assembly, comprising:a non-conductive housing having an open end;
an antenna element positioned inside the non-conductive housing;
an electrical cable having a first end electrically coupled to the antenna element and a second end extending out from the open end of the non-conductive housing;
at least two different dielectric materials positioned inside the non-conductive housing and in contact with the antenna element; and
a conductive gasket coupled to a portion of the electrical cable that is located adjacent to the open end and outside the non-conductive housing.

US Pat. No. 10,431,871

CONTACTLESS ANTENNA, SUPPORT STRUCTURE AND CORRESPONDING CONNECTOR

INGENICO GROUP, Paris (F...

1. A structural part of an internal architecture of a payment terminal, comprising:a rim, wherein said structural part is constituted by a rigid material;
an antenna-forming electrical cable; and
a channel on the rim, which has a variable width and grasps and guides the antenna-forming electrical cable when said antenna-forming electrical cable is wound around the rim of said structural part, wherein along a widest part of said channel at least one winding of the electrical cable is placed in parallel with at least one other winding of the electrical cable, and wherein along a narrowest part of said channel at least one winding of the electrical cable is superimposed on at least one other winding of the electrical cable.

US Pat. No. 10,431,861

COOLING STRUCTURE FOR AN ENERGY STORAGE DEVICE

FLEXTRONICS INTERNATIONAL...

1. An energy storage device, particularly for use in motor vehicles, comprisingat least one base body as well as at least one housing section fixed thereto for accommodating at least one energy storage unit, wherein the base body comprises at least one integrated cooling duct for a gaseous medium;
wherein the at least one cooling duct is connected to at least one air intake opening provided in the base body and extending substantially perpendicular to the cooling duct;
wherein the base body comprises two oppositely disposed side surfaces, wherein a housing section for accommodating the at least one energy storage unit is affixed to each of the side surfaces;
wherein the at least one cooling duct is separated by dividing bars and between each dividing bar and a lower side of the base body a distance A is provided which defines the height of the respective air intake opening into the respective cooling duct; and
wherein the distance A between the lower end of the dividing bars and the lower side of the base body is successively, stepwise reduced from the peripheral surface to the center of the base body.

US Pat. No. 10,431,856

METHOD FOR PRODUCING A BATTERY CONTACT-MAKING SYSTEM, AND BATTERY CONTACT-MAKING SYSTEM

ElringKlinger AG, Dettin...

1. A method for producing a cell contact-making system for an electrochemical device, including the following:separating out from a first starting material at least one signal conductor track group, which includes at least two signal conductor tracks of a signal conductor system of the cell contact-making system, by which signal sources or measuring points of the electrochemical device are electrically conductively connected to a signal conductor terminal connector serving as an interface for a monitoring unit of the electrochemical device, and at least one connection element by means of which at least two of the signal conductor tracks are directly connected to one another;
separating out from a second starting material, which is different from the first starting material, at least one cell connector or cell terminal connector;
connecting the signal conductor tracks of the signal conductor track group separated out from the first starting material to a respective cell connector or cell terminal connector separated out from the second starting material or to a sensor element of the cell contact-making system by a substance-to-substance bond or with positive engagement, after the separating out of the signal conductor track group from the first starting material; and
removing the at least one connection element.

US Pat. No. 10,431,855

GRAPHITE-CARBOHYDRATE ACTIVE MATERIAL PARTICLES WITH CARBONIZED CARBOHYDRATES

StoreDot Ltd., Herzeliya...

1. A method for making composite anode material comprising:milling graphite particles with carbohydrate particles to yield graphite-carbohydrate particles,
milling the graphite-carbohydrate particles with anode material particles having a native oxide layer, to form a graphite-carbohydrate layer over at least part of a surface of the anode material particles, and
carbonizing the milled anode material particles to form composite anode material particles which are de-oxidized and have at least a partial composite porous carbon-graphite coating forming an at least partial porous graphite shell over the anode material particles.

US Pat. No. 10,431,854

ENHANCED SOLID STATE BATTERY CELL

American Lithium Energy C...

1. A battery cell, comprising:a first electrode;
a second electrode;
a solid state electrolyte layer interposed between the first electrode and the second electrode; and
a resistive layer interposed between the first electrode and the second electrode, the resistive layer providing an electric resistance that limits a rate of internal current flow between the first electrode and the second electrode when an internal short circuit is formed between the first electrode and the second electrode, the internal short circuit being formed when the solid state electrolyte layer is penetrated by metal dendrites formed at the first electrode and/or the second electrode, the resistive layer comprising one or more ionically conductive material to enable a transfer of ions between the first electrode and the second electrode during a charge and/or a discharge of the battery cell, the one or more ionically conductive material including a polymer electrolyte, a polymer gel electrolyte, and/or a solid state electrolyte.

US Pat. No. 10,431,849

HIGH ENERGY DENSITY ALKALI METAL BATTERIES INCORPORATING SOLID ELECTROLYTES

GM Global Technology Oper...

1. An electrochemical cell comprising an alkali metal anode layer of one of lithium or sodium, a solid electrolyte layer, and a cathode layer, the solid electrolyte layer comprising:a glass, ceramic, or glass-ceramic, solid electrolyte layer with opposing surfaces, one of the surfaces being roughened to increase its effective surface area for increased direct physical contact with the alkali metal anode layer, the roughened surface being maintained in electrical and mechanical face-to-face contact with the alkali metal anode layer and the opposing surface being maintained in electrical and mechanical face-to-face contact with the cathode layer in the operation of the electrochemical cell by an applied pressure, the applied pressure being sufficient to cause the alkali metal anode layer material to flow into contact with the roughened surface of the solid electrolyte layer and to enable an increase in critical current density of at least 25% over a like dimensioned cell with a solid electrolyte with an un-roughened surface.

US Pat. No. 10,431,848

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO Electric Co., Ltd.,...

1. A nonaqueous electrolyte secondary battery comprising a positive electrode plate including a positive electrode current collector and a positive electrode mixture layer, formed thereon, containing a positive electrode active material; a negative electrode plate including a negative electrode current collector and a negative electrode mixture layer, formed thereon, containing a negative electrode active material; a separator; a nonaqueous electrolyte; an outer can; and a sealing body, wherein the positive electrode plate and the negative electrode plate are wound with the separator therebetween;the positive electrode active material contains a lithium-nickel composite oxide;
the lithium-nickel composite oxide is represented by the formula LiaNibCocAldO2 (0 the negative electrode active material contains graphite and a silicon material;
the negative electrode plate having two short sides and two long sides, wherein the two short sides oppose each other in a longitudinal direction, and each short side of said two short sides include a negative electrode current collector exposed portion not covered by the negative electrode mixture layer; and
the negative electrode current collector-exposed portions are each connected to a negative electrode tab.

US Pat. No. 10,431,847

STACKED FILM BATTERY ARCHITECTURE

International Business Ma...

1. A stacked battery structure comprising:two or more stacked battery layers, wherein each battery layer includes a substrate, a film battery element on the substrate and an insulator over the film battery element, the film battery element including a current collector, the insulator of a lower one of the two or more stacked battery layers having a flat top surface bonded to the substrate of an upper one of the two or more stacked battery layers; and
a through via formed within the two or more stacked battery layers and exposed at the top of the two or more stacked battery layers, the through via connecting with at least one of the current collectors of the two or more stacked battery layers.

US Pat. No. 10,431,844

METHOD FOR PRODUCING A CATALYTICALLY COATED MEMBRANE AND MEMBRANE ELECTRODE ASSEMBLY AND FUEL CELL STACK HAVING SAME

VOLKSWAGEN AG, Wolfsburg...

1. A method, comprising:producing a catalyst coated membrane that has a membrane material and a catalyst layer of a catalytic material on a flat side of the membrane material including a nonrectangular active area, which is restricted in one direction by two outer sides opposite one another and extending parallel to each other, the producing including:
continuously applying the catalytic material to the flat side of the membrane material in a coating direction, the catalytic material having a constant coating width, the area of the membrane material coated with the catalytic material at least covers the nonrectangular active area of the catalyst coated membrane, the applying including:
coating the membrane material with the catalytic material such that the coating direction has an angle that is not equal to 90° and not equal to 0° with respect to the two outer sides of the nonrectangular active area.

US Pat. No. 10,431,843

FRAME BODY, CELL FRAME, CELL STACK, AND REDOX FLOW BATTERY

Sumitomo Electric Industr...

1. A frame body for a cell frame of a redox flow battery,the frame body comprising an outer peripheral portion that is to face and contact, when a plurality of the cell frames are stacked, a frame body of another cell frame that is adjacent to the cell frame,
the outer peripheral portion including a thin region whose thickness gradually decreases in a direction from a center of the frame body toward an outer periphery of the frame body,
the frame body having a through window disposed in a central portion of the frame body, and
the frame body being formed of a resin,
wherein the thickness of the thin region gradually decreases by gradual tapering from a first flat surface of the frame body toward the outer periphery of the frame body, and by tapering from a second flat surface of the frame body toward the outer periphery of the frame body, the tapering from the first flat surface opposing the tapering from the second flat surface.

US Pat. No. 10,431,840

MEMBRANE ELECTRODE ASSEMBLY, METHOD FOR MANUFACTURING MEMBRANE ELECTRODE ASSEMBLY, FUEL CELL, AND METHOD FOR MANUFACTURING FUEL CELL

SUMITOMO ELECTRIC INDUSTR...

1. A membrane electrode assembly, comprising:a solid electrolyte layer;
an anode layer provided on one side of the solid electrolyte layer; and
a cathode layer provided on the other side of the solid electrolyte layer,
the anode layer being stacked on the solid electrolyte layer to be pressed thereagainst,
the anode layer including a porous anode member having electrical conductivity,
wherein the porous anode member is stacked to be directly pressed against the surface of the solid electrolyte layer, and
wherein the porous anode member is constituted of a metal porous body having electrical conductivity.

US Pat. No. 10,431,839

METHOD OF PRODUCTION OF CHANNEL MEMBER FOR FUEL CELL

FUTAMURA KAGAKU KABUSHIKI...

1. A method of production of a channel member for fuel cell use comprising:a step of obtaining a sheet-shaped first conductor part containing a first resin and a carbon material,
a step of laying a sheet-shaped second conductor part containing a second resin with a lower melting point than said first resin and a carbon material on at least one surface of said first conductor part to form a sheet-shaped base part,
a step of transferring a grooved surface to a surface of said base part to form a grooved base part provided with groove parts,
a step of laying a sheet-shaped third conductor part containing a third resin with a lower melting point than said first resin and a carbon material on the surface of said grooved base part where said groove parts are formed, and
a step of integrally joining said grooved base part, and said third conductor part by hot melt bonding to cover said groove parts.

US Pat. No. 10,431,837

MEMBRANE ELECTRODE ASSEMBLY

SGL CARBON SE, Wiesbaden...

1. Membrane electrode assembly for polymer electrolyte membrane (PEM) fuel cells, comprising:a proton exchange membrane, two catalyst layers including an anode catalyst layer and a cathode catalyst layer, and two gas diffusion layers (GDL), wherein an anodic GDL is based on a carbon fibre structure and has a microporous layer (MPL), comprising graphite, carbon nanotubes or carbon nanofibres, and polytetrafluoroethylene (PTFE), and in which a cathodic GDL is based on a carbon fibre structure and has a microporous layer based on carbon black, carbon nanotubes and/or carbon nanofibres, and PTFE,
wherein the porosity of the anodic carbon fibre structure is 84% and/or less, and the density thereof is at least 0.25 g/cm3, and
wherein the porosity of the carbon fibre structure of the cathodic GDL is 85% or more and the density thereof is at most 0.2 g/cm3.

US Pat. No. 10,431,827

NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SANYO ELECTRIC CO., LTD.,...

1. A non-aqueous electrolyte secondary battery comprising:a positive electrode plate in which a positive electrode mix layer is disposed on a positive electrode core body;
a negative electrode plate in which a negative electrode mix layer is disposed on a negative electrode core body;
a positive electrode terminal electrically connected to the positive electrode plate;
a negative electrode terminal electrically connected to the negative electrode plate;
a flat rolled electrode assembly in which the positive electrode plate and the negative electrode plate in the state of being insulated from each other with a separator therebetween are rolled into a flat shape;
a non-aqueous electrolytic solution; and
an outer body,
wherein a rolled positive electrode core body exposed portion is disposed at one end portion of the flat rolled electrode assembly,
a rolled negative electrode core body exposed portion is disposed at the other end portion of the flat rolled electrode assembly,
the rolled positive electrode core body exposed portion is bundled and connected to a positive electrode collector,
the rolled negative electrode core body exposed portion is bundled and connected to a negative electrode collector,
a pressure-sensitive forced short-circuit mechanism that short-circuits the positive electrode plate and the negative electrode plate in response to an increase in pressure inside the outer body,
lithium carbonate is contained in the positive electrode mix layer, and
a porous protective layer is disposed along the border with the positive electrode mix layer at the position opposite to the separator on at least one surface of the positive electrode core body exposed portion,
wherein the protective layer has electrical conductivity and is a protective layer having the electrical conductivity lower than that of the positive electrode core body, and
the protective layer contains lithium carbonate.

US Pat. No. 10,431,821

CATHODE ACTIVE MATERIAL, CATHODE, BATTERY, BATTERY PACK, ELECTRONIC APPARATUS, ELECTRIC VEHICLE, ELECTRIC STORAGE APPARATUS, AND ELECTRIC POWER SYSTEM

Murata Manufacturing Co.,...

1. A battery comprising:a cathode;
an anode; and
an electrolyte,
wherein the cathode includes a cathode active material,
the cathode active material includes a first cathode material comprising a lithium metal oxide having a layered rocksalt structure, the lithium metal oxide including lithium and a metal other than lithium, the metal comprising nickel and at least one selected from the group consisting of iron, zinc, and zirconium,
a site occupancy of metal ions other than lithium at a 3a site obtained by Rietveld analysis of a powder X-ray diffraction pattern of the first cathode material in the cathode in a discharged state is about 5% or less,
a site occupancy of metal ions other than the metal occupying a part of a 3b site at the 3b site is 1% or over, the cathode active material is covered with a coating film including a resolvent of an electrolyte salt and a resolvent of the electrolyte solvent, and
an exposed amount of the cathode active material exposed from the coating film is within a range from about 0.05% to about 8% both inclusive.

US Pat. No. 10,431,813

CARBON-SILICON COMPOSITE STRUCTURE AND METHOD OF PREPARING THE SAME

Sogang University Researc...

1. A method of preparing a carbon-silicon composite structure, comprising:polymerizing an aromatic monomer to form polymer particles;
cross-linking the polymer particles to obtain cross-linked polymer particles;
carbonizing the cross-linked polymer particles through calcination to obtain carbon particles; and
mixing the carbon particles with silicon nanoparticles to obtain a carbon particle layer in which silicon nanoparticles are dispersed,
wherein the cross-linking of the polymer particles includes cross-linking through a Friedel-Crafts acylation reaction.

US Pat. No. 10,431,811

ELECTRIC VEHICLE BATTERY CELL HAVING WATER-BASED LI-ION ANODE SLURRY AND PROCESS OF PREPARING SAME

SF MOTORS, INC., Santa C...

1. A method of providing an anode of a battery cell to power an electric vehicle, comprising:forming a powder mix comprising a carbonaceous material and a conductive additive;
dividing the powder mix into a plurality of portions each within 10% by weight of each other;
generating a slurry by:
iteratively, for each of the plurality of portions, adding one of the plurality of portions to a carboxymethyl cellulose (CMC) solution and mixing the CMC solution containing the one of the plurality of portions;
measuring a viscosity of the slurry subsequent to the mixing of the CMC solution containing the one of the plurality of portions;
adding DI water when the viscosity of the slurry is above 3000 cps;
adding additional powder mix when the viscosity of the slurry is below 2500 cps;
adding, subsequent to measuring the viscosity of the slurry, a binder including at least one of a styrene butadiene rubber solution and a polyacrylic acid solution to the slurry;
mixing the slurry containing the binder until two measurements of a slurry particle size indicate the slurry particle size is below 50 ?m;
dispensing the slurry onto a face of a conductive film to a thickness in a range between 100 ?m and 250 ?m;
forming the anode from the conductive film; and
installing the anode into the battery cell of a battery pack to power the electric vehicle.

US Pat. No. 10,431,810

METHOD FOR MAKING LITHIUM ION BATTERY ELECTRODE

Tsinghua University, Bei...

1. A method for making a lithium ion battery electrode comprising:step (S1), providing a slurry comprising an electrode active material, an adhesive, a dispersant, and a conductive agent, wherein a method for making the slurry comprises the following steps: providing the electrode active material, the adhesive, the dispersant, and the conductive agent; mixing the conductive agent and the electrode active material uniformly to obtain a mixture; and adding the adhesive and the dispersant into the mixture and stirring them to form the slurry;
step (S2), spreading the slurry over a metal sheet to form an electrode active material layer;
step (S3), applying a carbon nanotube layer structure on a surface of the electrode active material layer to form a precursor; and
step (S4), drying the precursor.

US Pat. No. 10,431,808

ELECTRODES, ELECTROCHEMICAL CELLS, AND METHODS OF FORMING ELECTRODES AND ELECTROCHEMICAL CELLS

ENEVATE CORPORATION, Irv...

1. A method of forming an electrode comprising:providing a current collector;
providing a layer of electrode attachment substance on a first side of the current collector, wherein the layer of electrode attachment substance is in a substantially solid state;
subsequently placing a solid layer comprising electrochemically active material on the layer of electrode attachment substance such that the layer of electrode attachment substance is sandwiched between the current collector and the solid layer comprising electrochemically active material; and
adhering the electrochemically active material to the current collector, wherein portions of the solid layer comprising electrochemically active material penetrate the layer of electrode attachment substance and come in direct contact with the current collector.

US Pat. No. 10,431,807

METHOD OF MANUFACTURING LITHIUM-ION SECONDARY BATTERY ELECTRODE

TOYOTA JIDOSHA KABUSHIKI ...

1. A method of manufacturing a lithium-ion secondary battery electrode, the method comprising:supplying granulated composite particles, each of the composite particles containing an active material and a binder, onto a sheet collector in a powder form; and
rolling the composite particles supplied onto the collector to form an active material layer, wherein
the granulated composite particles are prepared by spray-drying,
the rolling step includes a first rolling sub-step involving first rolling, and a second rolling sub-step to be performed after the first rolling sub-step, and
the first rolling is rubber rolling using a pair of rubber rolls.

US Pat. No. 10,431,806

THIN FILM LITHIUM CONDUCTING POWDER MATERIAL DEPOSITION FROM FLUX

QuantumScape Corporation,...

1. A method for making an electrolyte, the method comprising:providing a lithium conducting garnet electrolyte powder at a first quantity, the lithium conducting garnet electrolyte powder being characterized by a first density and a median particle size of about 100 nm to 10 ?m;
providing a first flux material at a second quantity, the first flux material comprising inorganic salts of lithium, the first flux material being characterized by a melting temperature of about 500-1000° C.;
providing a second flux material at a third quantity, the second flux material being characterized by a melting temperature of about 500-1000° C.;
mixing the first flux material and the second flux material with the lithium conducting garnet electrolyte powder to form a fluxed electrolyte powder;
shaping the fluxed electrolyte powder in to a predetermined shape;
flux sintering the shaped electrolyte powder at a temperature of greater than 100° C. and less than 800° C. to form a dense lithium conducting electrolyte, the dense lithium conducting electrolyte being characterized by a second density, the second density is at least 20% higher than the first density; and
removing the first and second flux materials from the dense lithium conducting electrolyte.

US Pat. No. 10,431,798

SEPARATOR FOR LITHIUM SECONDARY BATTERY, AND LITHIUM SECONDARY BATTERY COMPRISING SAME

Samsung SDI Co., Ltd., Y...

1. A separator for a lithium secondary battery, comprising:a substrate, and
a heat-resistance porous layer disposed on at least one surface of the substrate and including a cross-linked binder,
wherein the cross-linked binder has a cross-linking structure formed from a compound represented by Chemical Formula 2,

wherein, in Chemical Formula 2,
X1 to X3 are an oxyethylene group, respectively,
X4 is an oxyethylene group or a C1 to C10 alkyl group, when X4 is the oxyethylene group, n4 is an integer ranging from 1 to 10 and m is 1 and when X4 is the C1 to C10 alkyl group, n4 is 1 and m is 0,
R1 to R4 are a functional group of a (meth)acrylate group, a hydroxy group, a carboxyl group, an ester group, a cyanate group, an isocyanate group, an amino group, a thiol group, a C1 to C10 alkoxy group, a vinyl group, or a heterocyclic group,
each of a1 to a4 are an integer ranging from 1 to 10,
each of n1 to n3 are an integer ranging from 0 to 10, and at least one of n1 to n4 is an integer ranging from 1 to 10,
wherein the heat-resistance porous layer further comprises a non-crosslinked binder,
wherein the non-crosslinked binder comprises polyvinylidene fluoride (PVdF), a polyvinylidene fluoride-hexafluoropropylene (PVdF-HFP) copolymer, polymethylmethacrylate, polyacrylonitrile, polyvinylpyrrolidone, polyvinylacetate, polyethylene-vinylacetate copolymer, polyethyleneoxide, cellulose acetate, cellulose acetate butyrate, cellulose acetate propionate, cyanoethylpullulan, cyanoethylpolyvinyl alcohol, cyanoethyl cellulose, cyanoethylsucrose, pullulan, an acrylonitrile-styrene-butadiene copolymer, or a combination thereof, and
wherein each shrinkage ratio in a machine direction (MD) and a transverse direction (TD) of the separator is less than or equal to 5% according to Equation 1,
Shrinkage ratio (%)=[(LO?L1)/LO]×100  [Equation 1]
wherein, in Equation 1, LO indicates an initial length of a separator and L1 indicates a length of a separator after being allowed to stand at 200° C. and for 10 minutes.

US Pat. No. 10,431,792

HOUSING COMPRISING OVERPRESSURE PROTECTION

TRELLEBORG SEALING SOLUTI...

1. A housing having an overpressure protection, comprising:a pressure relief opening which extends from the housing interior to the housing external side;
a diaphragm sealing plug, from a rubber-elastic material, which is disposed in the pressure relief opening in the seal seat in order for the latter to be closed in a fluid-tight manner, wherein the diaphragm sealing plug is disposed so as to be loose in the pressure relief opening, and the diaphragm sealing plug has a central portion and an angled free peripheral portion by way of which the diaphragm sealing plug in a direction that is radial to the central axis of the diaphragm sealing plug bears in a fully circumferential and sealing manner on a housing wall that delimits the pressure relief opening, wherein the free peripheral portion in the non-pressurized operating state of the diaphragm sealing plug extends away from the central portion in the direction of the housing external side and in the axial direction extends up to the housing external side or projects beyond the housing external side, wherein a radial contact compression of the free peripheral portion of the diaphragm sealing plug against the housing wall in the non-pressurized operating state of the diaphragm sealing plug is reduced axially in the direction of the housing external side;
wherein the central portion in the non-pressurized state in the cross section is configured so as to be W-shaped and has a central concavity having an apex, said central concavity being disposed on the central axis and in the axial direction pointing toward the external side of the housing, said apex being disposed in the axial direction between the two peripheral portions of the diaphragm sealing plug, wherein the concavity of the central portion is formed by two central legs which conjointly enclose an obtuse angle ? that is open toward the housing interior; and
wherein the central portion by way of an increasing housing internal pressure in the axial direction is deformable in such a manner that the peripheral portion by way of a tension stress that is derived from the deformation of the central portion is releasable in a manner proportional to the pressure from the housing wall in the axial direction, in a progressive manner from the inside to the outside, until the diaphragm sealing plug releases the pressure relief opening when a predefined maximum housing internal pressure is reached or exceeded.

US Pat. No. 10,431,781

BATTERY LOADING MAGAZINE

General Electric Company,...

11. A method for loading battery assemblies within a storage rack, the method comprising:stacking a plurality of battery magazines onto a base member to form a battery magazine stack, the base member including at least one support wall defining an upper surface, the upper surface of the support wall defining at least one base engagement feature, each battery magazine at least partially surrounding a battery assembly, each battery magazine including a first sidewall, a second sidewall, and a transverse wall extending between the first and second sidewalls, wherein the first sidewall, the second sidewall, and the transverse wall define a cavity to receive the battery assembly, and wherein each battery magazine is configured to engage a portion of the battery assembly to prevent lateral movement of the battery assembly relative to the battery magazine when the battery assembly is positioned within the cavity, each of the first and second sidewalls extending between an upper surface and a lower surface opposite the upper surface, the lower surface of at least one of the first and second sidewalls of each battery magazine defining at least one magazine engagement feature configured to engage the at least one base engagement feature, wherein one of the at least one base engagement feature and the at least one magazine engagement feature comprises at least one engagement channel and the other of the at least one base engagement feature and the at least one magazine engagement feature comprises at least one rib configured to be received within the at least one engagement channel;
lifting the base member and the battery magazine stack relative to the storage rack, the storage rack defining a plurality of storage slots, each storage slot configured to receive one of the battery assemblies;
vertically aligning a top battery magazine of the battery magazine stack with a corresponding storage slot of the plurality of storage slots; and
laterally moving the battery assembly contained within the top battery magazine relative to an adjacent battery magazine of the battery stack to install the battery assembly into the corresponding storage slot.

US Pat. No. 10,431,779

ORGANIC LAYER DEPOSITION APPARATUS, METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE SAME, AND ORGANIC LIGHT-EMITTING DISPLAY APPARATUS MANUFACTURED USING THE METHOD

Samsung Display Co., Ltd....

1. A method of manufacturing an organic light-emitting display device by using an organic layer deposition apparatus for forming an organic layer on a substrate, the method comprising:attaching the substrate to a transfer unit in a loading unit;
transporting, into a chamber, the transfer unit to which the substrate is attached, by using a first conveyer unit passing through the chamber;
forming organic layers by depositing deposition materials discharged from a plurality of organic layer deposition assemblies on the substrate while the substrate is spaced apart from and moved relative to the organic layer deposition assemblies in the chamber;
separating the substrate on which the depositing has been completed from the transfer unit in an unloading unit; and
transporting the transfer unit from which the substrate is separated to the loading unit by using a second conveyer unit passing through the chamber,
wherein each of the organic layer deposition assemblies comprises:
a plurality of deposition sources, each of the deposition sources being configured to discharge a corresponding one of the deposition materials;
a deposition source nozzle unit at a side of each of the plurality of deposition sources and comprising one or more deposition source nozzles;
a patterning slit sheet facing the deposition source nozzle unit and comprising one or more patterning slits; and
a modification shutter located between the plurality of deposition sources and the patterning slit sheet and having an opening that is configured to allow the corresponding ones of the deposition materials from the deposition sources to pass-through towards the patterning slit sheet,
wherein the openings of adjacent ones of the modification shutters are offset from each other along a second direction perpendicular to a first direction in which the substrate is transported, and
the deposition materials discharged from the plurality of deposition sources pass through the patterning slit sheet and are deposited on the substrate in patterns.

US Pat. No. 10,431,763

LIGHT EMITTING DIODE AND PREPARATION METHOD THEREOF, ARRAY SUBSTRATE AND ELECTRONIC DEVICE

BOE TECHNOLOGY GROUP., LT...

1. A light emitting diode comprising:a substrate, and
a first electrode, a quantum rod light emitting layer and a second electrode disposed in lamination on the substrate,
wherein, the quantum rod light emitting layer comprises a plurality of quantum rods which present a directional arrangement,
wherein the light emitting diode further comprises a third electrode and a fourth electrode, the third electrode and the fourth electrode being configured to generate an electric field in parallel with or substantially in parallel with a plane of the substrate in a powered state, and
wherein the third electrode is a comb-shaped electrode.

US Pat. No. 10,431,756

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:an organic light-emitting diode structure layer including a pixel array section;
a film connected to a first edge-side region of the organic light-emitting diode structure layer and folded back onto a rear surface side of the organic light-emitting diode structure layer; and
an integrated circuit disposed on the film, wherein
a width of the film in a connection region to the organic light-emitting diode structure layer is smaller than a width of the film in a region where the integrated circuit is disposed.

US Pat. No. 10,431,752

ORGANOMETALLIC IRIDIUM COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A compound represented by Formula (G1):
wherein:
L represents a monoanionic ligand,
R1 and R2 separately represent a methyl group, an ethyl group, an isobutyl group, or a neopentyl group, and
R3 represents a methyl group, an ethyl group, an isobutyl group, a 3,5-dimethylphenyl group, a 2-methylphenyl group, a 2,6-dimethylphenyl group, or a 3,5-diethylphenyl group.

US Pat. No. 10,431,751

COMPOUND AND ORGANIC ELECTRONIC DEVICE COMPRISING THE SAME

SHANGHAI NICHEM FINE CHEM...

9. An organic electronic device, comprising:a first electrode;
a second electrode; and
an organic layer disposed between the first electrode and the second electrode, wherein the organic layer comprises the compound of claim 1.

US Pat. No. 10,431,741

METHOD OF MAKING AN ARRAY OF INTERCONNECTED SOLAR CELLS

Stichting Energieonderzoe...

1. Method of making an array of interconnected solar cells, comprising the steps ofa) providing a continuous layer stack of a prescribed thickness (t) on a substrate, the layer stack comprising an upper and a lower conductive layer having a photoactive layer and a semi conductive electron transport layer interposed there between;
b) selectively removing the upper conductive layer and the photoactive layer for obtaining a contact hole exposing the semi conductive electron transport layer;
c) selectively heating the layer stack to a first depth (d1) for obtaining a first heat affected zone at a first centre-to-centre distance (s1) from the contact hole, the first heat affected zone being transformed into a substantially insulating region with substantially the first depth (d1) in the layer stack, thereby locally providing an increased electrical resistivity to the layer stack.

US Pat. No. 10,431,736

MAINTAINING COERCIVE FIELD AFTER HIGH TEMPERATURE ANNEAL FOR MAGNETIC DEVICE APPLICATIONS WITH PERPENDICULAR MAGNETIC ANISOTROPY

TAIWAN SEMICONDUCTOR MANU...

1. A magnetic memory element formed between a first electrode and a second electrode, the magnetic memory element comprising:a tunnel barrier layer formed between a reference layer and a free;
layer, wherein the free layer comprises a first surface that forms a first interface with the tunnel barrier layer thereby inducing perpendicular magnetic anisotropy (PMA) in at least a portion of the free layer adjacent to the first interface;
an oxide layer that forms a second interface with a second surface of the free layer opposite to the first surface of the free layer, wherein each of the oxide layer and the free layer has a body centered cubic (BCC) structure that enhances the PMA in the free layer; and
a first lattice-matching layer disposed on an opposite side of the oxide layer with respect to the second interface, wherein the first lattice-matching layer has the BCC structure, comprises a non-magnetic material, and is interposed between the oxide layer and the second electrode.

US Pat. No. 10,431,735

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory,wherein the semiconductor memory comprises:
a variable resistance element exhibiting two different states for storing data; and
an upper layer disposed over the variable resistance element,
wherein the upper layer has a stepped profile and includes an upper portion and a lower portion having a wider width than the upper portion,
wherein sidewalls of the upper portion and sidewalls of the lower portion are configured to be discontinuous from each other, and
wherein a height of the upper portion is higher than a height of the lower portion.

US Pat. No. 10,431,734

ENGINEERED BARRIER LAYER INTERFACE FOR HIGH SPEED SPIN-TRANSFER TORQUE MAGNETIC RANDOM ACCESS MEMORY

QUALCOMM Incorporated, S...

1. A perpendicular magnetic tunnel junction, comprising:a free layer;
a reference layer; and
a barrier layer between the free layer and the reference layer, the barrier layer having a first interface that faces the free layer and a second interface that faces the reference layer, in which a surface of the first interface is fabricated to not physically correlate with a surface of the second interface.

US Pat. No. 10,431,729

JOSEPHSON JUNCTION USING MOLECULAR BEAM EPITAXY

Ambature, Inc., Scottsda...

1. A Josephson Junction comprising:a substrate layer adjacent to and configured to support a buffer layer, the substrate layer comprising SiC;
the buffer layer adjacent to and configured to support a template layer;
the template layer configured to orient subsequent adjacent layers in an a-axis orientation, wherein the template layer comprises LGSO or YBCO in the a-axis orientation;
a first conductive layer adjacent the template layer and oriented in the a-axis orientation, wherein the first conductive layer is YBCO in the a-axis orientation;
a barrier layer adjacent the first conductive layer; and
a second conductive layer adjacent the barrier layer and oriented in the a-axis orientation, wherein the second conductive layer is YBCO in the a-axis orientation;
wherein the template layer, the first conductive layer, the second conductive layer and the barrier layer are all formed via molecular beam epitaxy.

US Pat. No. 10,431,725

LIGHT EMITTING DEVICE INCLUDING DIFFERENT SHAPES OF LIGHT EMITTING ELEMENT HAVING HIGHER LIGHT EXTRACTION EFFICIENCY

NICHIA CORPORATION, Anan...

1. A light emitting device comprising, with reference to an X-axis, a Y-axis orthogonal to the X-axis, and a Z-axis orthogonal to the X-axis and the Y-axis:a package that forms a recess in the Z-axis direction, has a first lead and a second lead arranged on a bottom surface of the recess and a resin section on a lateralwall of the recess to fix the first lead and the second lead, and when viewed in the Z-axis direction a shape which is surrounded by an upper side of an inner area of the lateralwall of the recess is substantially rectangular;
a light emitting element that is arranged on the first lead and is in a triangular shape when viewed in the Z-axis direction, and a longest side of the light emitting element is positioned closer to a lower surface of the package;
a second wire that electrically connects the light emitting element to the second lead; and
reflective members that cover a part of an inner surface of the lateralwall and a part of the bottom surface at upper corners in the recess,
wherein one side of the light emitting element adjacent to the second lead is substantially in parallel to at least part of one side of the first lead or the second lead, when viewed in the Z-axis direction,
wherein, of four surfaces of each reflective member, three surfaces are in contact with the recess, and one remaining surface is in contact with a sealing member, and
wherein the reflective members are separated from each other.

US Pat. No. 10,431,724

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING SAME

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a substrate in a shape of rectangular,
a light emitting element mounted on the substrate,
a reflective member disposed outside one or more lateral sides of the light emitting element while being away from therefrom,
a light guide member filling between inner faces of the reflective member so as to cover the light emitting element, and
a light transmissive member disposed on the light guide member, wherein
the reflective member includes at least one first reflective member opposite at least one lateral face of the light emitting element, and a second reflective member positioned outside the first reflective member and surrounds the light emitting element, wherein
the at least one first reflective member has inner faces opposing each other, the inner faces each having an oblique or curved portion that are slanted so that a distance therebetween increases towards the light transmissive member from a side close to the substrate,
the second reflective member covers lateral faces of the light transmissive member and outer lateral faces of the at least one first reflective member, and an upper face of the second reflective member is flush with an upper face of the light transmissive member.

US Pat. No. 10,431,723

MICRO LED MIXING CUP

Apple Inc., Cupertino, C...

1. A light emitting structure comprising:a light emitting diode (LED) bonded to a substrate;
a diffuser layer adjacent the LED, the diffuser layer comprising scattering particles dispersed in a matrix;
a well structure, wherein the LED is bonded to the substrate within a well opening of the well structure that completely laterally surrounds the LED, the diffuser layer laterally surrounds the LED within the well opening, and the well structure that completely laterally surrounds the LED is thicker than a portion of the diffuser layer and the LED within the well opening;
a transparent electrode layer on a top side of the LED, and spanning over the diffuser layer within the well opening and over a top surface of the well structure outside of the well opening;
an angular filter directly over the diffuser layer and the LED; and
an overcoat layer directly over the angular filter, the LED, and the transparent electrode layer spanning over the top surface of the well structure outside of the well opening.

US Pat. No. 10,431,721

LIGHT-EMITTING DEVICE AND METHOD FOR MANUFACTURING SAME

CITIZEN ELECTRONICS CO., ...

1. A light-emitting device comprising:a substrate;
a plurality of light-emitting elements that are mounted on the substrate in a lattice manner;
a first resin layer that integrally seals the plurality of light-emitting elements and includes a first phosphor that is excited by light from the plurality of light-emitting elements at a concentration that is high as it goes to a lower end near the substrate from an upper end distant from the substrate; and
a second resin layer that is disposed on an upper side of the first resin layer via an interface, the second resin layer including a second phosphor that is the same as the first phosphor, at a uniform concentration, wherein
the first phosphor is precipitated on upper surfaces of the light-emitting elements and the upper surface of the substrate between the light-emitting elements, and the second phosphor is uniformly dispersed in the second resin layer at a concentration lower than the concentration of the first phosphor at the lower end of the first resin layer, and thereby generates a smaller amount of heat than the first phosphor.

US Pat. No. 10,431,720

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a light emitting element including:
a semiconductor structure including an n-type semiconductor layer, an active layer, and a p-type semiconductor layer, in this order, each containing a nitride semiconductor,
a p-electrode disposed on a portion of a surface of the p-type semiconductor layer on a side opposite to a surface provided with the active layer, and
an n-electrode disposed on a surface of the n-type semiconductor layer on a side opposite to a surface provided with the active layer in a region other than a region facing the p-electrode,
wherein the light emitting element has a peak wavelength of 410 nm or less; and
a protective film continuously covering a surface of the n-electrode and a surface of the n-type semiconductor layer,
wherein the protective film includes a first metal oxide film and a second metal oxide film that are layered, the first metal oxide film containing a first metal, and the second metal oxide film containing a second metal,
wherein the first metal oxide film includes one or more individual first metal oxide film layers, and
the second metal oxide film includes one or more individual second metal oxide film layers.

US Pat. No. 10,431,712

INORGANIC EMITTING PARTICLE, INORGANIC EMITTING PARTICLE FILM, AND LED PACKAGE AND DISPLAY DEVICE INCLUDING THE SAME

LG DISPLAY CO., LTD., Se...

1. An inorganic emitting particle, comprising:an inorganic oxide having a first size; and
quantum dots attached to the inorganic oxide and having a second size less than the first size,
wherein the inorganic oxide is silicon oxide having the first size of approximately 100 nm to approximately 300 nm, and
wherein the quantum dots form a layer covering an entire surface of the inorganic oxide.

US Pat. No. 10,431,709

FABRICATING THIN-FILM OPTOELECTRONIC DEVICES WITH MODIFIED SURFACE

Flisom AG, Duebendorf (C...

1. A thin-film optoelectronic device, comprising:a substrate;
a back-contact layer; and
an absorber layer comprising:
a p-type ABC chalcogenide material, wherein A represents one or more elements selected from a group consisting of Cu and Ag, B represents one or more elements selected from a group consisting of In, Ga, and Al, and C represents one or more elements selected from a group consisting of S, Se, and Te;
an n-type ABC chalcogenide material comprising one or more alkali metals; and
a plurality of cavities disposed in the n-type ABC chalcogenide material.

US Pat. No. 10,431,702

TRANSPARENT ELECTRODE, MANUFACTURING METHOD THEREOF AND ELECTRONIC DEVICE EMPLOYING THE TRANSPARENT ELECTRODE

KABUSHIKI KAISHA TOSHIBA,...

1. A transparent electrode having a laminate structure comprising:a first metal oxide layer having an amorphous structure and electroconductivity,
a metal layer which comprises a metallic material comprising silver or copper,
a second metal oxide layer having an amorphous structure and electroconductivity, and
a third metal oxide layer having an amorphous structure and continuity,
stacked in this order.

US Pat. No. 10,431,695

TRANSISTORS COMPRISING AT LEASE ONE OF GAP, GAN, AND GAAS

Micron Technology, Inc., ...

1. A transistor comprising:a pair of source/drain regions having a channel region there-between;
a transistor gate construction operatively proximate the channel region;
the channel region comprising a direction of current flow there-through between the pair of source/drain regions, the channel region comprising at least one of GaP, GaN, and GaAs extending all along the current-flow direction;
each of the source/drain regions comprising at least one of GaP, GaN, and GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction, the at least one of the GaP, the GaN, and the GaAs of the respective source/drain region being directly against the at least one of the GaP, the GaN, and the GaAs of the channel region;
each of the source/drain regions comprising at least one of elemental silicon and metal material extending completely through the respective source/drain region orthogonal to the current-flow direction;
the channel region as respects GaP, GaN, and GaAs comprising only one of the GaP, the GaN, and the GaAs extending all along the current-flow direction; and
as respects GaP, GaN, and GaAs, each of the source/drain regions comprising only one other of the GaP, the GaN, and the GaAs extending completely through the respective source/drain region orthogonal to the current-flow direction.

US Pat. No. 10,431,694

THIN FILM TRANSISTOR, DISPLAY APPARATUS HAVING THE SAME, AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A method of fabricating a thin film transistor comprising an active layer having a channel region, a source electrode contact region, and a drain electrode contact region, comprising:forming a semiconductor material layer comprising M1OaNb on a base substrate; wherein M1 is a single metal or a combination of metals, a>0, and b?0;
forming a conductive metal material layer on a side of the semiconductor material layer distal to the base substrate; and
doping a first portion of the semiconductor material layer in a region corresponding to the channel region with a dopant thereby forming the etch stop layer, the etch stop layer being substantially resistant to an etchant for etching a metal material.

US Pat. No. 10,431,693

ARRAY SUBSTRATE AND DISPLAY PANEL

HKC CORPORATION LIMITED, ...

1. An array substrate, comprising:a substrate comprising a plurality of switch assemblies; wherein each of the switch assembly comprises:
a gate electrode is formed on an upper surface of the substrate;
a gate insulating layer is formed on upper surfaces of the gate electrode and the substrate to cover the gate electrode;
a semiconductor layer is formed on an upper surface of the gate insulating layer, and is disposed above the gate electrode, wherein the semiconductor layer is formed of silicon germanium oxide, and the semiconductor layer comprises a channel portion;
a source electrode is formed on surfaces of the gate insulating layer and the semiconductor layer, and is disposed on a side of the channel portion;
a drain electrode formed is on the surfaces of the gate insulating layer and the semiconductor layer, and is disposed on the other side of the channel portion;
a protective layer is formed on upper surfaces of the source electrode and the drain electrode to cover the source electrode and the drain electrode, and the protective layer is disposed above the channel portion;
a conductive layer is formed on an upper surface of the protective layer; and
wherein the semiconductor layer comprises a doped layer and an active layer; the doped layer is disposed at a top of the semiconductor layer and is divided into two portions by the channel portion, one of the portion is adjacent to the drain electrode and the other portion is adjacent to the source electrode; the active layer is disposed at a bottom of the semiconductor layer, the doped layer is disposed on an upper surface of the active layer; the doped layer comprises a first doped layer and a second doped layer; the second doped layer is disposed at the top of the semiconductor layer, the first doped layer is disposed at the bottom of the semiconductor layer, and is between the second doped layer and the active layer; a doping concentration of the second doped layer is greater than a doping concentration of the first doped layer.

US Pat. No. 10,431,691

THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, AND LIQUID CRYSTAL DISPLAY PANEL

Wuhan China Star Optoelec...

1. A liquid crystal display panel comprising a thin film transistor, wherein the thin film transistor comprises:a substrate, a gate electrode layer and an insulating layer, wherein the gate electrode layer is disposed on the substrate, the insulating layer covers the gate electrode layer;
a semiconductor layer is disposed on the insulating layer;
a conductor layer is disposed on the semiconductor layer;
the semiconductor layer comprises a channel region, the channel region divides the semiconductor layer into left and right portions, the conductor layer is disposed on the left and right portions of the semiconductor layer to form two island structures;
an insulating spacer layer is disposed on the insulating layer;
a source-drain electrode layer is disposed on the conductor layer and the insulating spacer layer;
a passivation layer is disposed on the source-drain electrode layer and the semiconductor layer;
wherein the insulating spacer layer is disposed between the source-drain electrode layer and the semiconductor layer;
the gate electrode layer and the source-drain electrode layer are metal material; and
the insulating layer, the insulating spacer layer and the passivation layer are insulating materials;
the passivation layer is disposed above the insulating spacer layer, and the insulating spacer layer comprises a first thickness and a second thickness, the second thickness is smaller than the first thickness, and the second thickness is greater than or equal to the thickness of the semiconductor layer.

US Pat. No. 10,431,689

THIN FILM TRANSISTOR AND DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A thin film transistor, comprising: a gate, a source, a drain, an active layer and a heat transmitting layer;wherein the heat transmitting layer is arranged on at least one side of the active layer;
wherein the thin film transistor further comprises:
a substrate and a gate insulating layer;
the gate is arranged on the substrate;
the gate insulating layer is arranged on the gate, and the active layer is arranged on the gate insulating layer;
the source and the drain are arranged on the active layer, or the source and the drain are arranged on the gate insulating layer and partially covered by the active layer.

US Pat. No. 10,431,676

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

VANGUARD INTERNATIONAL SE...

1. A semiconductor device, comprising:a substrate;
a first III-V group compound semiconductor layer disposed on the substrate, wherein the first III-V group compound semiconductor layer comprises a fin structure comprising a top surface, a first sidewall, and a second sidewall opposite to the first sidewall;
a second III-V group compound semiconductor layer disposed on the first III-V group compound semiconductor layer, wherein the first III-V group compound semiconductor layer and the second III-V group compound semiconductor layer comprise different materials from each other, and the second III-V group compound semiconductor layer covers the top surface, the first sidewall, and the second sidewall of the fin structure to form a heterojunction along the top surface, the first sidewall, and the second sidewall of the fin structure;
a gate electrode disposed on the second III-V group compound semiconductor layer; and
source/drain electrodes disposed on a top surface of the second III-V group compound semiconductor layer.

US Pat. No. 10,431,665

MULTIPLE-LAYER SPACERS FOR FIELD-EFFECT TRANSISTORS

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:forming a first conformal layer comprised of silicon oxycarbonitride on a surface of a second conformal layer formed on a sidewall of a gate electrode, the first conformal layer formed by a first atomic layer deposition process performed in a reaction chamber, and the first atomic layer deposition process including:
flowing a silicon-containing precursor into the reaction chamber;
adsorbing silicon from the silicon-containing precursor on the surface;
flowing an oxygen-containing precursor into the reaction chamber;
adsorbing oxygen from the oxygen-containing precursor on the surface;
after the oxygen is adsorbed on the surface, flowing a purge gas into the reaction chamber to clear the oxygen-containing precursor from the reaction chamber;
after flowing the purge gas into the reaction chamber, flowing a carbon-containing precursor and a nitrogen-containing precursor simultaneously into the reaction chamber; and
adsorbing carbon and nitrogen from the carbon-containing precursor and the nitrogen-containing precursor simultaneously on the surface,
wherein the first conformal layer is used to form a first spacer.

US Pat. No. 10,431,664

GATE STRUCTURE AND METHODS THEREOF

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, comprising:forming a gate dielectric trench within an active region of a substrate, the active region being free of any shallow trench isolation feature;
depositing a first dielectric layer within the gate dielectric trench, wherein a top surface of the first dielectric layer is level with a top surface of the substrate;
forming a second dielectric layer over the first dielectric layer; and
forming a metal gate over the second dielectric layer, wherein the first dielectric layer, the second dielectric layer and the metal gate are part of a transistor disposed over the active region that is free of any shallow trench isolation feature.

US Pat. No. 10,431,662

THIN FILM TRANSISTOR AND METHOD FOR MAKING THE SAME

Tsinghua University, Bei...

1. A thin film transistor, comprising:a substrate;
a semiconductor layer on the substrate, wherein the semiconductor layer comprises at least one nano-scaled semiconductor material;
a source and a drain, wherein the source and the drain are on the substrate, spaced apart from each other, and electrically connected to the semiconductor layer;
a dielectric layer on the semiconductor layer, wherein the dielectric layer comprises a first sub-dielectric layer and a second sub-dielectric layer stacked on one another, and the first sub-dielectric layer is a first oxide dielectric layer grown by magnetron sputtering; and
a gate in direct contact with the first sub-dielectric layer;
wherein the first oxide dielectric layer is grown by magnetron sputtering and sandwiched between the second sub-dielectric layer and the gate; the second sub-dielectric layer is a second oxide dielectric layer or a nitride dielectric layer, the second sub-dielectric layer is grown using one of atomic layer deposition, electron beam evaporation, thermal oxidation, and plasma-enhanced chemical vapor deposition; and the current hysteresis caused by the first oxide dielectric layer is inverse to the current hysteresis caused by the second oxide dielectric layer or the nitride dielectric layer so that the thin film transistor has a reduced current hysteresis.

US Pat. No. 10,431,661

TRANSISTOR WITH INNER-GATE SPACER

INTEL CORPORATION, Santa...

1. An integrated circuit including at least one transistor, the integrated circuit comprising:a body including semiconductor material;
a source region and a drain region, the body between the source and drain regions, the source and drain regions including semiconductor material and dopant;
a first spacer and a second spacer, the first and second spacers including one or more dielectrics;
a gate structure at least above the body, the gate structure between the first and second spacers, the gate structure including one or more metals, the gate structure having an upper portion, a middle portion, and a lower portion, the middle portion of the gate structure between the lower and upper portions of the gate structure, the lower portion of the gate structure closer to the body than the middle portion of the gate structure, wherein the lower portion of the gate structure has a larger width between the first and second spacers than the middle portion of the gate structure; and
a gate dielectric between the body and the gate structure.

US Pat. No. 10,431,660

SELF-LIMITING FIN SPIKE REMOVAL

INTERNATIONAL BUSINESS MA...

1. A method for forming a semiconductor structure, the method comprising:forming a silicon fin on a silicon germanium strain relaxed buffer (SRB) layer;
laterally forming a spacer on a side of the silicon fin;
performing a thermal anneal; and
performing an etch to remove material formed by the thermal anneal;
wherein the spacer comprises germanium oxide at least partially formed on at least part of the silicon fin.

US Pat. No. 10,431,659

FABRICATION OF A VERTICAL FIN FIELD EFFECT TRANSISTOR WITH A REDUCED CONTACT RESISTANCE

INTERNATIONAL BUSINESS MA...

1. A vertical fin field effect transistor (vertical finFET) with an increased surface area between a bottom source/drain contact and a doped region, comprising:the doped region on a substrate;
one or more vertical fins on the doped region; and
the bottom source/drain contact on at least a portion of the same doped region as the one or more vertical fins, wherein the doped region has a plurality of interfacial features that increases the surface area of an interface between the bottom source/drain contact and the doped region compared to a flat bottom source/drain contact-doped region interface, wherein each of the plurality of interfacial features has the same width and lengths as each of the one or more vertical fins.

US Pat. No. 10,431,658

SILICON CARBIDE SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREFOR AND POWER CONVERSION APPARATUS

Mitsubishi Electric Corpo...

1. A silicon carbide semiconductor device comprising:a silicon carbide semiconductor layer of a first conductivity type including a protective trench provided on a top surface of the silicon carbide semiconductor layer;
a base region of a second conductivity type provided in an upper part of the silicon carbide semiconductor layer;
a source region of the first conductivity type provided on the base region;
a gate electrode provided inside a gate trench penetrating the base region and the source region via a gate insulating film;
a protective diffusion layer of the second conductivity type provided at a position deeper than the gate electrode in the silicon carbide semiconductor layer;
an inter-layer insulating film covering a surface of the gate electrode and including a cell opening;
a source electrode electrically connected to the source region via the cell opening and electrically connected to the protective diffusion layer via the protective trench; and
a plated film provided on the source electrode,
wherein a concave part is provided on a top surface of the source electrode directly above the protective trench,
a depth in a vertical direction of the concave part is equal to or less than half of a width in a horizontal direction of the concave part, and
the plated film fills the concave part of the source electrode.

US Pat. No. 10,431,657

SEMICONDUCTOR DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor device, comprising:a first semiconductor region including Alx1Ga1-x1N (0?x1<1);
a first electrode separated from the first semiconductor region in a first direction;
a second electrode separated from the first semiconductor region in the first direction, a second direction from the first electrode toward the second electrode crossing the first direction;
a third electrode separated from the first semiconductor region in the first direction, a position in the second direction of the third electrode being between a position in the second direction of the first electrode and a position in the second direction of the second electrode, the third electrode including a first portion and a second portion;
a conductive portion separated from the first semiconductor region in the first direction, a position in the second direction of the conductive portion being between the position in the second direction of the third electrode and the position in the second direction of the second electrode;
a second semiconductor region including Alx2Ga1-x2N (0 a first insulating layer, a portion of the first insulating layer being provided between the first portion and the first semiconductor region in the first direction, a direction from at least a part of the first insulating layer toward the second semiconductor region being aligned with the second direction;
a second insulating layer including a first insulating portion and a second insulating portion, the first insulating portion being positioned between the second portion and the third partial region in the first direction, the second insulating portion being positioned between the conductive portion and the second semiconductor region in the first direction, a first length along the first direction of the first insulating portion being longer than a second length along the first direction of the second insulating portion.

US Pat. No. 10,431,656

SEMICONDUCTOR CRYSTAL SUBSTRATE WITH FE DOPING

FUJITSU LIMITED, Kawasak...

1. A semiconductor crystal substrate, comprising:a first buffer layer formed of a nitride semiconductor over a substrate;
a second buffer layer formed of a nitride semiconductor on the first buffer layer;
a first semiconductor layer formed of a nitride semiconductor on or over the second buffer layer; and
a second semiconductor layer formed of a nitride semiconductor on the first semiconductor layer,
wherein an iron (Fe) concentration of the first buffer layer is higher than a carbon (C) concentration of the first buffer layer,
a C concentration of the second buffer layer is higher than an Fe concentration of the second buffer layer throughout the second buffer layer in a thickness direction of the second buffer layer, and
the Fe concentrations of the first and second buffer layers peak at an interface between the first and second buffer layers.

US Pat. No. 10,431,655

TRANSISTOR STRUCTURE

United Microelectronics C...

1. A transistor structure, comprising:a substrate, having a device region;
a transistor device, located in the device region;
a split buried layer, located under the transistor device in the substrate and comprising at least three first buried layers separated from each other; and
a second buried layer, located under the split buried layer in the substrate and connecting the first buried layers, wherein the second buried layer and the split buried layer have a first conductive type.

US Pat. No. 10,431,654

EXTRINSIC BASE DOPING FOR BIPOLAR JUNCTION TRANSISTORS

International Business Ma...

1. A method of fabricating a device structure, the method comprising:forming a first trench and a second trench in a substrate;
forming a collector in the substrate between the first trench and the second trench, wherein the first trench and the second trench establish boundaries for the collector;
forming a base layer on a top surface of the substrate over the collector;
forming an emitter on a top surface of the base layer;
forming a dielectric layer on exposed surfaces of the base layer;
forming a hardmask layer on the base layer and the dielectric layer;
forming a pattern from the hardmask with a first opening and a second opening;
removing portions of a dielectric layer from the top surface of the base layer at positions consistent with the pattern of the first opening and the second opening to form exposed surfaces defined as a first window and a second window in the dielectric layer;
limiting deposits of a dopant-containing layer on the exposed surfaces of a first portion on the top surface of the base layer inside of the first window, and a second portion on the top surface of the base layer inside of the second window, wherein the first portion is on a first side of the emitter, the second portion is on a second side of the emitter, and the first window and the second window formed in the dielectric layer bound the first portion and the second portion on the top surface of the base layer; and
transferring dopant from the dopant-containing layer into the first portion and the second portion on top of the base layer to define an extrinsic base of the device structure.

US Pat. No. 10,431,653

TRENCH-BASED DIODE AND METHOD FOR MANUFACTURING SUCH A DIODE

Robert Bosch GmbH, Stutt...

1. A semiconductor system, comprising:a planar anode contact formed of metal;
a planar cathode contact;
a first volume of n-conductive semiconductor material which has an anode-side end and a cathode-side end and extends between the planar anode contact and the planar cathode contact, a direction pointing from the planar anode contact to the planar cathode contact defining a depth direction of the first volume; and
at least one p-conductive area which extends from the anode-side end of the first volume in the depth direction toward the cathode-side end of the first volume without reaching the cathode-side end of the first volume, the p-conductive area having two sub-areas which are separated from one another in a cross section lying transversely with respect to the planar anode contact and the planar cathode contact, the two sub-areas delimit a first sub-volume of the first volume filled with n-conductive semiconductor material, the first sub-volume filled with the n-conductive semiconductor material extending through an opening toward the planar cathode contact, the opening being delimited by cathode-side ends of the two sub-areas, and a distance between the cathode-side ends of the two sub-areas defining the opening being smaller than a distance between the two sub-areas prevailing outside of the opening and lying between anode-side ends of the two sub-areas;
wherein a highly p-doped area is located on the cathode-side end of the p-doped areas, a lateral width of the highly p-doped area being greater in a lateral direction than a width of two p-doped sub-areas adjacent to the highly p-doped area, a trench of the semiconductor system being between and delimited by the two p-doped sub-areas, so that the highly p-doped area protrudes in the lateral direction over the two p-doped sub-areas delimiting the trench, the trench having trench sides and a trench bottom, wherein the lateral direction is perpendicular to the depth direction;
wherein the highly p-doped area is more highly p-doped than the two p-doped sub-areas;
wherein the trench sides and the trench bottom are completely covered by and completely directly contact the planar anode contact, and the planar anode contact contacts the first sub-volume filled with the n-conductive semiconductor material, the at least one p-conductive area, and the highly p-doped area, forms an ohmic contact with at least the first sub-volume filled with the n-conductive semiconductor material and the highly p-doped area, and connects the n-conductive semiconductor material to the highly p-doped area in an electrically conductive manner.

US Pat. No. 10,431,652

SEMICONDUCTOR DEVICE WITH SINGLE-CRYSTAL NANOWIRE FINFET

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a single crystal substrate;
a source/drain structure disposed on and contacted with a top surface of the single crystal substrate;
a nanowire structure being connected to the source/drain structure, wherein the nanowire structure, the single crystal substrate and the source/drain structure all include different crystal semiconductor materials;
a dielectric layer disposed on the single crystal substrate, only between the nanowire structure and the top surface of the single crystal substrate; and
a shallow trench isolation disposed surrounding the source/drain structure and the nanowire structure, wherein the shallow trench isolation does not directly contact the dielectric layer, and the dielectric layer is disposed above a top surface of the shallow trench isolation and spaced apart from the nanowire structure.

US Pat. No. 10,431,651

NANOSHEET TRANSISTOR WITH ROBUST SOURCE/DRAIN ISOLATION FROM SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method of fabricating a nanosheet transistor comprising:receiving a substrate structure having a plurality of nanosheet layers and a plurality of sacrificial layers stacked upon a substrate;
forming at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate;
depositing a first liner within the at least one trench;
depositing a second liner on the first liner;
selectively removing portions of the second liner to form a u-shaped portion at a bottom portion of the at least one trench, the u-shaped portion including a bottom cavity;
selectively removing portions of the first liner to a level of a top portion of the u-shaped portion at the bottom portion of the at least one trench;
selectively laterally etching edges of each of the sacrificial layers to create recesses within the sacrificial layers; and
depositing a third liner within the at least one trench to fill the recesses and the bottom cavity of the u-shaped portion.

US Pat. No. 10,431,650

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, comprising:providing a semiconductor substrate of a first conductivity type that has a front surface device structure formed on a first principal surface thereof;
a first implantation process of
implanting hydrogen atoms from a second principal surface of the semiconductor substrate, to thereby form a first semiconductor layer, and
forming, in the semiconductor substrate at the second principal surface thereof, a plurality of second semiconductor layers of the first conductivity type that each have a carrier concentration higher than that of the first semiconductor layer, the carrier concentrations having respective peak values thereof at different depths from the second principal surface of the semiconductor substrate;
applying a first heat treatment process to promote generation of donors from the hydrogen atoms;
a second implantation process of
implanting an impurity of a second conductivity type from the second principal surface of the semiconductor substrate after the first heat treatment process, and
forming a third semiconductor layer of the second conductivity type in the semiconductor substrate at the second principal surface thereof, a distance between the third semiconductor layer and the first principal surface of the semiconductor substrate being larger than a distance between each second semiconductor layer and the first principal surface of the semiconductor substrate; and
applying a second heat treatment process to heat a portion of the semiconductor substrate, which is from a laser irradiated surface to a depth of 2-3 ?m, to substantially 1000-1416° C., so as to activate the third semiconductor layer and reduce a carrier concentration at an interface between the third semiconductor layer and one of the second semiconductor layers adjacent to the third semiconductor layer.

US Pat. No. 10,431,649

SEMICONDUCTOR DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first conductive portion including
a first portion aligned with a first direction,
a second portion aligned with the first direction, a direction from the first portion toward the second portion crossing the first direction,
a third portion aligned with a second direction crossing the first direction,
a fourth portion aligned with the second direction, a direction from the third portion toward the fourth portion crossing the second direction,
a fifth portion aligned with a third direction, the third direction crossing the first direction and the second direction and being along a plane including the first direction and the second direction, and
a sixth portion aligned with the third direction, a direction from the fifth portion toward the sixth portion crossing the third direction,
the first portion being continuous with the third portion and the sixth portion, the third portion being continuous with the first portion and the fifth portion, the fifth portion being continuous with the third portion and the second portion, the fourth portion being continuous with the second portion and the sixth portion;
a first extension portion aligned with the first direction and electrically connected to the first conductive portion, the first extension portion being conductive, a first extension portion length along the first direction of the first extension portion being longer than a first portion length along the first direction of the first portion and longer than a second portion length along the first direction of the second portion;
a first conductive region provided between the first portion and the second portion, between the third portion and the fourth portion, and between the fifth portion and the sixth portion;
a first extension region aligned with the first direction and electrically connected to the first conductive region, the first extension region being conductive, a first extension region length along the first direction of the first extension region being longer than the first portion length and longer than the second portion length, a direction from the first extension region toward the first extension portion crossing the first direction;
a semiconductor portion including silicon carbide and including first to third semiconductor regions,
the first semiconductor region being of a first conductivity type and including first to fifth partial regions, a direction from the first partial region toward the first portion being aligned with a fourth direction crossing the plane, a direction from the second partial region toward the first conductive region being aligned with the fourth direction, the third partial region being positioned between the first partial region and the second partial region, a direction from the fourth partial region toward the first extension portion being aligned with the fourth direction, a direction from the fifth partial region toward the first extension region being aligned with the fourth direction,
the second semiconductor region being of the first conductivity type and including a sixth partial region, a second impurity concentration of the first conductivity type in the second semiconductor region being higher than a first impurity concentration of the first conductivity type in the first semiconductor region,
the third semiconductor region being of a second conductivity type and including seventh to tenth partial regions, the seventh partial region being positioned between the third partial region and the sixth partial region in the fourth direction, the eighth partial region being positioned between the second partial region and the first conductive region in the fourth direction, the ninth partial region being positioned between the seventh partial region and the eighth partial region, the tenth partial region being positioned between the fifth partial region and the first extension region in the fourth direction; and
an insulating portion provided between the first conductive portion and the semiconductor portion and between the first extension portion and the semiconductor portion.

US Pat. No. 10,431,647

APPARATUSES AND METHODS FOR SEMICONDUCTOR CIRCUIT LAYOUT

Micron Technology, Inc., ...

1. A semiconductor device comprising:a plate electrode elongating continuously in a horizontal direction to define first, second and third portions;
a first pad electrode overlapping the first portion of the plate electrode in a vertical direction to provide a first capacitance element therebetween;
a second pad electrode overlapping the second portion of the plate electrode in a vertical direction to provide a second capacitance element therebetween;
a third pad electrode overlapping the third portion of the plate electrode in a vertical direction to provide a third capacitance element therebetween;
a first contact coupled to the first pad electrode;
a transistor comprising a gate electrode;
a second contact coupled to the second pad electrode and the gate electrode; and
a third contact coupled to the third pad electrode.

US Pat. No. 10,431,646

ELECTRONIC DEVICES HAVING SPIRAL CONDUCTIVE STRUCTURES

INTERNATIONAL BUSINESS MA...

2. The method of claim 1, wherein the concentric segments comprise at least one of concentric semi-circular segments or concentric semi-rectangular segments.

US Pat. No. 10,431,645

DISPLAY DEVICE, METHOD FOR DRIVING THE SAME, AND ELECTRONIC APPARATUS

SONY CORPORATION, Tokyo ...

1. A display device comprising:a pixel array unit having pixels arranged in a matrix, at least one of the pixels having an electro-optical element, a first capacitor having a first electrode and a second electrode, a second capacitor having a third electrode and a fourth electrode, a sampling transistor, and a driving transistor;
a data signal line extending in a first direction; and
a scan line extending in a second direction perpendicular to the first direction,
wherein,
the first electrode and the second electrode overlap,
the fourth electrode and the third electrode overlap,
the first electrode is disposed in a first layer, the third electrode is disposed in a second layer which is different from the first layer, and the first layer is disposed over the second layer,
the second electrode is electrically connected to a control terminal of the driving transistor, and
the first electrode and the third electrode are electrically connected to a first node of the driving transistor.

US Pat. No. 10,431,644

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a display unit on a substrate, the display unit comprising a thin film transistor comprising an active layer, a gate electrode, a source electrode, and a drain electrode that are electrically coupled;
a pad unit at one outer side of the display unit on the substrate; a wiring unit comprising a plurality of wiring layers on the substrate to couple the display unit to the pad unit, each of the plurality of wiring layers comprising a plurality of wirings;
a thin film encapsulating layer covering the display unit, the thin film encapsulating layer comprising a stacked structure of a first inorganic layer, a first organic layer and a second inorganic layer, the first organic layer being between the first and second inorganic layers; and
a protrusion unit on the wiring unit, the protrusion unit overlapping a boundary of the thin film encapsulating layer,
wherein the protrusion unit is spaced apart from the gate electrode, the source electrode and the drain electrode of the thin film transistor,
the protrusion unit overlays with at least one of a boundary of the first inorganic layer and a boundary of the second inorganic layer of the thin film encapsulating layer, and
a portion of the thin film encapsulating layer is between the protrusion unit and the display unit,
wherein the protrusion unit comprises a plurality of support protrusions and a support base supporting the plurality of support protrusions, the display unit further comprises: a pixel electrode coupled to the drain electrode; an opposite electrode facing the pixel electrode;
a light-emitting layer between the pixel electrode and the opposite electrode; a planarization layer between the drain electrode and the pixel electrode; and a pixel defining layer partitioning a region of the light-emitting layer between the pixel electrode and the opposite electrode,
wherein the support base comprises a same material and is on a same layer as the planarization layer, and
the support protrusion comprises a same material and is on a same layer as the pixel defining layer.

US Pat. No. 10,431,643

DISPLAY PANEL

SAMSUNG DISPLAY CO., LTD....

1. A display panel comprising:a signal line extending in at least one of a first direction and a second direction, which crosses the first direction, in a top plan view;
a first transistor electrically connected to the signal line, and comprising a first active pattern and a first gate electrode; and
a first electrode electrically connected to the first transistor,
wherein a plurality of openings are defined in the signal line at least along a substantial length defining the signal line, the plurality of openings are dimensioned and configured to transmit an external light therethrough and outside of the display panel to improve transparency through the display panel.

US Pat. No. 10,431,642

ORGANIC LIGHT EMITTING DISPLAY DEVICE AND METHOD FOR FABRICATING THE SAME

LG DISPLAY CO., LTD., Se...

1. A method for fabricating a display device, the method comprising:providing a base film on an auxiliary substrate, wherein the base film includes a display area, and a first pad area;
providing a plurality of thin film transistors on the display area of the base film;
providing first pads on the first pad area of the base film;
providing a plurality of organic light emitting diodes connected with the plurality of thin film transistors;
providing an encapsulation layer for covering the plurality of organic light emitting diodes;
attaching a plurality of source flexible films onto the first pads, respectively;
separating the base film from the auxiliary substrate; and
cutting a part of the base film between each of the plurality of source flexible films.

US Pat. No. 10,431,641

THIN FILM TRANSISTOR SUBSTRATE, AN ORGANIC LIGHT-EMITTING DISPLAY APPARATUS USING THE SAME, AND A METHOD OF MANUFACTURING THE THIN FILM TRANSISTOR SUBSTRATE

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor (TFT) substrate comprising:a substrate;
a first electrode disposed on the substrate, wherein the first electrode is one of a source electrode and a drain electrode;
a first insulating layer disposed on the first electrode, wherein the first insulating layer exposes an upper surface of the first electrode;
a second electrode disposed on the first insulating layer, wherein the second electrode is the other one of the source electrode and the drain electrode, wherein the first insulating layer is disposed between the upper surface of the first electrode and a lower surface of the second electrode;
a semiconductor layer disposed on the first electrode, a side of the first insulating layer, and the second electrode;
a second insulating layer disposed on the semiconductor layer;
a gate electrode disposed on the second insulating layer and overlapping the semiconductor layer; and
a pixel electrode that comprises a same material as the gate electrode and is electrically connected to the second electrode.

US Pat. No. 10,431,640

DISPLAY DEVICE

Samsung Display Co., Ltd....

17. A display device comprising:a substrate comprising a display area including a plurality of pixels, and a peripheral area outside the display area and including a bending area;
a first conductive layer over the substrate;
a first insulating layer over the first conductive layer;
a second insulating layer over the first insulating layer, overlapping the bending area in a plan view, and having a first edge positioned around the bending area;
a second conductive layer over the second insulating layer such that the second insulating layer is between the second conductive layer and the first insulating layer in a sectional view; and
a third insulating layer over the second conductive layer,
wherein the first conductive layer includes a first signal wire in the peripheral area, extending to cross the first edge of the second insulating layer in the plan view, and not overlapping the bending area,
wherein the first signal wire includes a first portion that does not overlap by the second insulating layer in the plan view, and
wherein the third insulating layer includes a protector that overlaps at least a portion of the first portion, and has an edge that is parallel with an edge of the first portion in the plan view.

US Pat. No. 10,431,639

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A display substrate, comprising:a base substrate;
a pixel definition layer pattern disposed on the base substrate, wherein the pixel definition layer pattern comprises a main layer proximal to the base substrate and an oxide layer distal to the base substrate, a material layer for forming the pixel definition layer pattern is partially oxidized to obtain the main layer and the oxide layer;
the pixel definition layer pattern is made of siloxane based organic material, and the siloxane based organic material comprises at least one of hydroxylated polydimethylsiloxane or polystyrene block polydimethylsiloxane.

US Pat. No. 10,431,638

ARRAY SUBSTRATE AND OLED DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate comprising: a thin-film transistor (TFT) substrate and a plurality of driver integrated circuits (ICs), wherein the TFT substrate comprises a substrate and a plurality of pixel units disposed on one surface of the substrate; the driver ICs are disposed on the other surface of the substrate and configured to transmit signals to the pixel units, and via holes provided with a conductive material are formed in the substrate and the conductive material is protruded out from the via holes and a protruding portion of the conductive material is connected with output ends of the driver ICs, the pixel units comprise TFTs and pixel electrodes; and the TFTs comprise gate electrodes, active layers, source electrodes and drain electrodes, the gate electrodes are disposed on the substrate; the active layers are disposed over the gate electrodes; channels are provided between the source electrodes and the drain electrodes; the drain electrodes are connected with the pixel electrodes, the pixel units further comprise a gate insulating layer disposed between the gate electrodes and the active layers; through holes corresponding to the via holes are formed in the gate insulating layer and provided with the conductive material, the through holes only pass through the gate insulating layer and the conductive material is in connection with the source electrodes through the via holes and the through holes.

US Pat. No. 10,431,635

FOLDABLE OLED DEVICE WITH COMPATIBLE FLEXURAL STIFFNESS OF LAYERS

3M INNOVATIVE PROPERTIES ...

1. A flexible organic light emitting diode (OLED) display device, comprising:an upper module having a cover window film;
a lower module;
a display module between the upper module and the lower module, the display module including an OLED and an OLED substrate between the OLED and the lower module;
a touch sensor between the OLED and the upper module;
a first coupling layer between the cover window film and the touch sensor;
a second coupling layer between the touch sensor and the OLED; and
a third coupling layer between the OLED substrate and the lower module,
wherein a shear modulus of the first coupling layer is less than 70 kPa at room temperature,
wherein the upper module has a first Young's modulus, the lower module has a second Young's modulus, and the first Young's modulus is different from the second Young's modulus,
wherein 100>(LS/TW)>0.001, where L is a flexural stiffness of the lower module, S is a flexural stiffness of the OLED substrate, T is a flexural stiffness of the touch sensor, and W is a flexural stiffness of the cover window film.

US Pat. No. 10,431,634

ORGANIC ELECTROLUMINESCENCE DEVICE WITH RECESSES FILLED WITH A PHOSPHOR FILLING LAYER IN THE BASE MATERIAL

SHARP KABUSHIKI KAISHA, ...

1. An organic electroluminescence device comprising:a base material including a recessed portion on a surface side;
a reflective layer;
a filling layer having optical transparency;
a first electrode having optical transparency;
an organic layer including at least a light emitting layer; and
a second electrode having optical transparency and light reflectivity,
the reflective layer being disposed at least along a surface of the recessed portion, the filling layer being disposed in the recessed portion through the reflective layer, the first electrode being disposed at least on an upper-layer side of the filling layer, the organic layer being disposed on an upper-layer side of the first electrode, and the second electrode being disposed on an upper-layer side of the organic layer, wherein
the filling layer includes at least one type of phosphor, and
a lower face of the first electrode at a position inside the recessed portion is positioned lower than a plane including the surface side of the base material.

US Pat. No. 10,431,633

METHOD FOR PRODUCING A MULTI-COLORED LIGHT EMITTING COMPONENT

1. A method for producing a component comprising a substrate configured to emit an electromagnetic radiation in a first wavelength range and an electromagnetic radiation in a second wavelength range within one surface area, the method comprising:providing the substrate having a surface on which a plurality of electrodes are formed within the one surface area;
depositing a first layer stack on the entire one surface area, the first layer stack comprising at least one layer configured to cause emission of the electromagnetic radiation in the first wavelength range, and a first cover layer;
removing the first layer stack from a partial surface area comprising at least one of the electrodes;
depositing a second layer stack on the entire one surface area after the first layer stack was removed from the partial surface area, the second layer stack comprising at least one layer configured to cause emission of the electromagnetic radiation in the second wavelength range and a second cover layer; and
producing an electrically conductive connection between the first and second cover layers, the first and second cover layers configured to act as a counterelectrode, wherein the at least one layer of the second layer stack deposited on the first layer stack is short circuited so as not to emit the electromagnetic radiation in the second wavelength range.

US Pat. No. 10,431,632

LIGHT-EMITTING DEVICE, ELECTRONIC APPLIANCE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first light-emitting element including a first electrode, a first transparent conductive layer in contact with the first electrode, an EL layer in contact with the first transparent conductive layer, and a second electrode in contact with the EL layer;
a second light-emitting element including a third electrode, a second transparent conductive layer in contact with the third electrode, the EL layer in contact with the second transparent conductive layer, and the second electrode in contact with the EL layer; and
a third light-emitting element including a fourth electrode, the EL layer in contact with the fourth electrode, and the second electrode in contact with the EL layer,
wherein the EL layer includes a first light-emitting layer, a second light-emitting layer, and a third light-emitting layer,
wherein the light with the wavelength ?1 is emitted from the first light-emitting element,
wherein the light with the wavelength ?2 is emitted from the second light-emitting element,
wherein the light with the wavelength ?3 is emitted from the third light-emitting element,
wherein a wavelength relation of ?3>?1>?2 is satisfied,
wherein an optical path length from the first electrode to the second light-emitting layer is 3?1/4, and an optical path length from the first electrode to the second electrode is ?1 in the first light-emitting element,
wherein an optical path length from the third electrode to the third light-emitting layer is 3?2/4, and an optical path length from the third electrode to the second electrode is ?2 in the second light-emitting element, and
wherein an optical path length from the fourth electrode to the first light-emitting layer is ?3/4, and an optical path length from the fourth electrode to the second electrode is ?3/2 in the third light-emitting element.

US Pat. No. 10,431,630

METHOD FOR PRODUCING TRANSISTORS, IN PARTICULAR SELECTION TRANSISTORS FOR NON-VOLATILE MEMORY, AND CORRESPONDING DEVICE

STMicroelectronics (Rouss...

11. A method for producing a plurality of MOS transistors commonly controlled by two vertical gates, comprising:etching a semiconductor substrate to form trenches which surround a rectangular semiconductor zone doped with a first type of conductivity providing a common channel region for the plurality of MOS transistors and having a buried region doped with a second type of conductivity providing a common source region for the plurality of MOS transistors, said rectangular semiconductor zone having opposed first sides and opposed second sides, wherein the opposed first sides are longer than the opposed second sides;
forming an isolated region comprising a gate material in first ones of said trenches on at least the opposed first sides of the rectangular semiconductor zone to form the two vertical gates for the plurality of MOS transistors;
making an electrically conductive connection in second ones of said trenches trench between the two vertical gates along the opposed second sides of the rectangular semiconductor zone; and
forming, at a top surface of the surrounded rectangular semiconductor zone providing the common channel region, a plurality of drain regions for the plurality of MOS transistors, wherein the drain regions are insulated from each other and doped with the second type of conductivity.

US Pat. No. 10,431,628

DUAL CHANNEL/GATE VERTICAL FIELD-EFFECT TRANSISTOR (FET) FOR USE WITH A PERPENDICULAR MAGNETIC TUNNEL JUNCTION (PMTJ)

SPIN MEMORY, INC., Fremo...

1. A method, comprising:forming a drain material above a substrate in a film thickness direction;
forming and patterning a first masking layer above the drain material in the film thickness direction, the first masking layer being patterned to expose a portion of the drain material having a circular cross-section along a plane perpendicular to the film thickness direction;
removing all portions of the drain material except for the exposed portion of the drain material and portions positioned directly therebelow in the film thickness direction using the first masking layer;
removing the first masking layer during or after removal of the portions of the drain material;
forming a first insulative layer above portions of the substrate not covered by the drain material to a thickness consistent with an upper surface of the drain material;
forming a second insulative layer above the first insulative layer and the drain material in the film thickness direction to a desired thickness;
placing the first masking layer above the second insulative layer aligned with previous placement of the first masking layer above the substrate to expose a portion of the second insulative layer having the circular cross-section along the plane perpendicular to the film thickness direction;
removing the exposed portion of the second insulative layer to expose the upper surface of the drain material;
removing the first masking layer during or after removal of the exposed portion of the second insulative layer;
growing the second insulative layer along the plane perpendicular to the film thickness direction to shrink a diameter of a hole through the second insulative layer having the circular cross-section along the plane perpendicular to the film thickness direction;
removing exposed portions of the drain material through the hole of the second insulative layer to form a drain contact having a circular cross-sectional hole in a center thereof along the plane perpendicular to the film thickness direction;
removing the first insulative layer and the second insulative layer;
removing portions of the substrate positioned directly below the drain contact to a desired level in the film thickness direction to form a channel having the circular cross-section with a hole in a center thereof along the plane perpendicular to the film thickness direction;
forming gate dielectric layers above the drain contact and on sides of the drain contact and the channel, the gate dielectric layers having concentric circular cross-sections along the plane perpendicular to the film thickness direction, wherein the circular cross-section of the drain contact has one circular cross-sectional portion of the gate dielectric layers in direct contact on either side thereof;
forming a source layer below the channel in the film thickness direction, the source layer being electrically coupled to the channel;
forming and patterning a second masking layer above the gate dielectric layers positioned above the drain contact and above the hole in the center of the drain contact in the film thickness direction, wherein the second masking layer has a rectangular cross-section along the plane perpendicular to the film thickness direction that is positioned above a plurality of drain contacts;
removing portions of the source layer and substrate not covered by the second masking layer in the film thickness direction to form a source line that is electrically coupled to a plurality of channels along the plane perpendicular to the film thickness direction;
removing the second masking layer;
forming a third insulative layer having a thickness in the film thickness direction that corresponds to a desired height of a lower surface of subsequently formed gate layers;
forming the gate layers above the third insulative layer on sides of the gate dielectric layers to a thickness coincident with a lower surface of the drain contact in the film thickness direction, wherein an inner gate layer fills a hole through a center of a center concentric circular cross-section of the gate dielectric layers along the plane perpendicular to the film thickness direction, and wherein an outer gate layer surrounds an outside concentric circular cross-section of the gate dielectric layers along the plane perpendicular to the film thickness direction;
removing an upper portion of the gate dielectric layers above the drain contact to expose an upper surface of the drain contact;
forming an electrode above the upper surface of the drain contact; and
forming a fourth insulative layer above the third insulative layer and the gate layers in the film thickness direction, and along sides of the electrode along the plane perpendicular to the film thickness direction.

US Pat. No. 10,431,627

MAGNETIC MEMORY DEVICES AND METHODS FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A magnetic memory device comprising:a magnetic tunnel junction pattern comprising a free pattern, a reference pattern and a tunnel barrier pattern between the free pattern and the reference pattern, the free pattern comprising:
a first sub-free pattern;
a second sub-free pattern; and
a third sub-free pattern,
wherein the first sub-free pattern is between the tunnel barrier pattern and the third sub-free pattern;
wherein the second sub-free pattern is between the first sub-free pattern and the third sub-free pattern and includes nickel-cobalt-iron-boron (NiCoFeB);
wherein the third sub-free pattern includes nickel-iron-boron (NiFeB);
wherein a thickness of the first sub-free pattern is greater than a thickness of the second sub-free pattern and a thickness of the third sub-free pattern;
wherein a nickel content of the first sub-free pattern is smaller than a nickel content of the second sub-free pattern and a nickel content of the third sub-free pattern; and
wherein a cobalt content of the third sub-free pattern is smaller than a cobalt content of the second sub-free pattern.

US Pat. No. 10,431,626

IMAGE SENSOR DEVICES

Silicon Optronics, Inc., ...

1. An image sensor device, comprising:a substrate;
a plurality of photoelectric conversion units for collecting image signals disposed in the substrate;
a first dielectric layer disposed upon the substrate;
a plurality of metal layers disposed in the first dielectric layer, wherein each metal layer adjacent to the substrate is defined as a first metal layer, and each metal layer adjacent to the top of the first dielectric layer is defined as a top metal layer;
a trench disposed in the first dielectric layer and located between adjacent metal layers, extending from the top of the first dielectric layer towards the substrate to the first metal layer;
a filling material filled in the trench;
a second dielectric layer disposed upon the first dielectric layer and the trench, and directly contacting with the first dielectric layer and the trench; and
a light source or a detected object disposed over the second dielectric layer.

US Pat. No. 10,431,625

IMAGE SENSOR AND METHOD OF FABRICATING THE SAME

SK hynix Inc., Gyeonggi-...

1. An image sensor comprising:a substrate including a first element;
a trench formed in the substrate, the trench defining a light receiving region and a readout region isolated from each other by the trench;
an impurity region formed in the substrate in contact with the trench; and
a re-crystallization layer formed in the substrate in contact with bottom and side surfaces of the trench and a surface of the substrate, the re-crystallization layer having a first portion disposed in the light receiving region and a second portion disposed in the readout region,
wherein the first portion of the re-crystallization layer includes a second element,
wherein the second portion of the re-crystallization layer includes a third element which is different from the second element, and
wherein the second and third elements are different from the first element wherein the second element contained in the first re-crystallization layer disposed in the light receiving region includes at least one of helium (He), neon (Ne), argon (Ar), krypton (Kr), xenon (Xe), and radon (Rn); and
wherein the third element contained in the first re-crystallization layer disposed in the readout region includes at least one of carbon (C), silicon (Si), germanium (Ge), nitrogen (N), oxygen (O), and fluorine (F).

US Pat. No. 10,431,624

METHOD OF MANUFACTURING IMAGE SENSOR INCLUDING NANOSTRUCTURE COLOR FILTER

SAMSUNG ELECTRONICS CO., ...

1. A method of manufacturing an image sensor, the method comprising:preparing a sensor substrate comprising:
a sensor layer comprising a photosensitive cell that receives light and generates electric signals; and
a signal line layer comprising lines to receive the electric signals from the photosensitive cell;
forming a first material layer having a first refractive index on the sensor substrate; and
forming a nanopattern layer on the first material layer, the nanopattern layer comprising a material having a second refractive index greater than the first refractive index,
wherein the sensor layer is disposed between the signal line layer and the first material layer.

US Pat. No. 10,431,621

SEMICONDUCTOR DEVICE, FABRICATION METHOD FOR A SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. An imaging device, comprising:a first substrate including a photodiode, a floating diffusion, a first plurality of transistors and a first electrode at a first surface side of the first substrate opposite to a light incident surface side; and
a second substrate including a second electrode at a first surface side of the second substrate and a second plurality of transistors,
wherein the first substrate and the second substrate are bonded to each other such that the first surface side of the first substrate and the first surface side of the second substrate are facing to each other,
wherein a side of the first electrode is covered by a first insulating film,
wherein a portion of the first electrode and a portion of the first insulating film are bonded to the second electrode, and
wherein, except for a bonding face of the first electrode, the first electrode is covered by the first insulating film.

US Pat. No. 10,431,619

SOLID-STATE IMAGE PICKUP DEVICE HAVING A PIXEL SEPARATION WALL

Sony Corporation, Tokyo ...

1. A solid-state image pickup device, comprising:a plurality of pixels that perform photoelectric conversion on light, the light entering the respective pixels from a back surface of the solid-state image pickup device via different lenses for each pixel, wherein at least some of the pixels in the plurality of pixels are phase difference detection pixels;
a wiring layer provided on a front surface of the solid-state image pickup device, wherein each phase difference detection pixel includes:
a first photoelectric conversion device;
a second photoelectric conversion device;
a divided pixel separation wall extending between at least portions of the first photoelectric conversion device and the second photoelectric conversion device; and
a floating diffusion,
wherein the divided pixel separation wall includes a front-side trench formed from the front surface and a backside trench formed from the back surface.

US Pat. No. 10,431,618

STACKED LENS STRUCTURE METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A stacked lens structure comprising:a plurality of substrates including a first substrate having a first through-hole, a second substrate having a second through-hole, and a third substrate having a third through-hole; and
a plurality of lenses including a first lens disposed in the first through-hole, a second lens disposed in the second through-hole, and a third lens disposed in the third through-hole;
wherein,
the first substrate is directly bonded to the second substrate via a first insulating layer to form a first bonding surface,
the second substrate is directly bonded to the third substrate via a second insulating layer to form a second bonding surface, and
a first distance from a central line to the first bonding surface is different than a second distance from the central line to the second bonding surface, the central line passing through a central point of the stacked lens structure and running in a plane direction of the first to third substrates, the central point being a center of the stacked lens structure in a thickness direction of the stacked lens structure.

US Pat. No. 10,431,616

COLOR FILTER ARRAYS FOR IMAGE SENSORS

Google LLC, Mountain Vie...

1. An imaging device comprising:a color filter array arranged to filter incident light, the color filter array having a repeating pattern of color filter elements, the color filter elements including yellow filter elements, green filter elements, and blue filter elements;
an image sensor having photosensitive regions corresponding to the color filter elements, the photosensitive regions being configured to respectively generate electrical signals indicative of intensity of the color-filtered light at the photosensitive regions; and
one or more processors configured to generate color image data based on the electrical signals from the photosensitive regions and determine a red intensity for a pixel of the image data based on a green intensity of a first photosensitive region corresponding to a particular green filter element of the green filter elements and an average of yellow intensities of a second photosensitive region and a third photosensitive region corresponding to two particular yellow filter elements of the yellow filter elements, where the first, second, and third photosensitive regions are adjacent to each other.

US Pat. No. 10,431,615

FAN-OUT SENSOR PACKAGE AND CAMERA MODULE INCLUDING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A fan-out sensor package comprising:a first interconnection member having a through-hole and including an electrical connection structure;
a sensor disposed in the through-hole of the first interconnection member and having an active surface having connection pads and microlenses disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the first interconnection member and the active surface of the sensor and filling the through-hole of the first interconnection member, the sensor and the first interconnection member being spaced apart by the encapsulant;
a rear redistribution layer disposed on the encapsulant;
rear vias penetrating through the encapsulant and electrically connecting the connection pads of the sensor and the rear redistribution layer to each other; and
a second interconnection member disposed on the first interconnection member and the inactive surface of the sensor, the sensor and the first interconnection member being disposed between the rear distribution layer and the second interconnection member,
wherein the second interconnection member includes a redistribution layer electrically connected to the connection pads of the sensor through at least the electrical connection structure of the first interconnection member, the rear redistribution layer, and the rear vias.

US Pat. No. 10,431,614

EDGE SEALS FOR SEMICONDUCTOR PACKAGES

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor package comprising:a digital signal processor comprising a first side and a second side;
an image sensor array comprising a first side and a second side, the first side of the image sensor array coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and a first edge seal coupled directly with the HBI bond pads;
an etch stop layer comprised in the second side of the digital signal processor; and
one or more first openings extending from the second side of the image sensor array into the second side of the digital signal processor and to the etch stop layer in the second side of the digital signal processor, the one or more first openings coated with a sealing material, the one or more first openings forming a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor;
wherein the first edge seal is comprised of a first metal stack comprised within the digital signal processor directly coupled to a second metal stack comprised within the image sensor array.

US Pat. No. 10,431,611

METHOD FOR MANUFACTURING THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING ARRAY SUBSTRATE, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a thin film transistor, comprising:forming an active layer on a base substrate;
forming a metal layer on a surface of the active layer;
processing the metal layer using a patterning process for one time and an oxidation treatment process to form a source electrode, a drain electrode and a passivation layer, the source electrode and the drain electrode are in contact with the active layer, and the passivation layer is formed on a side of the source electrode and the drain electrode away from the active layer, which includes:
forming a photoresist layer on a surface of the metal layer;
processing the photoresist layer using the patterning process for one time to form a photoresist completely-removed region, photoresist partly-reserved regions and a photoresist completely-reserved region; wherein the photoresist partly-reserved regions are connected to the photoresist completely-reserved region;
performing a complete oxidation treatment on a region of the metal layer corresponding to the photoresist completely-removed region to form a first passivation portion;
removing a photoresist in the photoresist partly-reserved regions;
performing a partial oxidation treatment on a region of the metal layer corresponding to the photoresist partly-reserved regions to form the source electrode, the drain electrode and a second passivation portion; wherein the source electrode and drain electrode are in contact with the active layer, and the second passivation portion is formed on a side of the source electrode and the drain electrode away from the active layer; the first passivation portion and the second passivation portion form the passivation layer;
removing a photoresist in the photoresist completely-reserved region to form a conductive portion connected to the source electrode and the drain electrode.

US Pat. No. 10,431,610

X-RAY DETECTING PANEL AND MANUFACTURING METHOD THEREOF

Samsung Display Co., Ltd....

1. An X-ray detecting panel comprising:a substrate;
m gate lines on the substrate;
n data lines on the substrate and intersecting the m gate lines;
a thin film transistor in an area between adjacent gate lines of the first gate line to the (m?1 )th gate line on the substrate;
a non-driving element in an area between the (m?1)th gate line and the mth gate line on the substrate; and
a photoelectric converter connected to the thin film transistor, wherein the thin film transistor and the non-driving element are connected to different ones of the gate lines, wherein the non-driving element includes a gate electrode connected to the mth gate line and a semiconductor layer insulated from the gate electrode, and does not include a source electrode and a drain electrode.

US Pat. No. 10,431,609

ARRAY SUBSTRATE, DISPLAY PANEL WITH FRIT AT CUTTING EDGE FOR NARROW BEZEL

SHANGHAI TIANMA AM-OLED C...

1. An array substrate, comprising:a display region; and
an encapsulation region divided into a first region away from the display region and a second region adjacent to the display region,
wherein:
the encapsulation region includes a metal layer configured only in the second region, a frit solution layer configured in both the first region and the second region, and a cutting edge configured in the first region, the cutting edge disposed along a part of the frit solution layer in the first region and having a distance from a border line of the first region away from the second region; and
the array substrate is cut along the cutting edge.

US Pat. No. 10,431,608

DUAL CONVERSION GAIN HIGH DYNAMIC RANGE READOUT FOR COMPARATOR OF DOUBLE RAMP ANALOG TO DIGITAL CONVERTER

OmniVision Technologies, ...

1. A comparator comprising:a second stage coupled to provide an output in response to an intermediate voltage;
a first stage coupled to provide the intermediate voltage in response to an input, the first stage comprising:
a pair of cascode devices coupled to a current mirror;
a low gain input coupled to first and second inputs of the first stage via first and second switches, and further selectively coupled to the pair of cascode devices via third and fourth switches; and
a high gain input coupled to the first and second inputs of the first stage via the first and second switches, and further selectively coupled to the pair of cascode devices via fifth and sixth switches,
wherein, based on a low conversion gain mode, the low gain input is coupled to the first and second inputs by the first and second switches, and further coupled to the pair of cascode devices by the third in fourth switches in response to a control signal being in a first state, and
wherein, based on a high conversion gain mode, the high gain input is coupled to the first and second inputs by the first and second switches, and further coupled to the pair of cascode device by the fifth and sixth switch in response to the control signal being in a second state.

US Pat. No. 10,431,607

DISPLAY SUBSTRATE HAVING AN ORGANIC LAYER AND FABRICATING METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A method of fabricating a display substrate having an organic layer, comprising:forming the organic layer on a base substrate to reduce parasitic capacitance between electrodes in different layers of the display substrate;
subsequent to forming the organic layer, forming a first electrode layer on a side of the organic layer away from the base substrate, the first electrode layer formed in direct contact with the organic layer;
subjecting the organic layer to a surface treatment process to descum organic residues from a surface of the organic layer; and
subsequent to forming the first electrode layer and subsequent to subjecting the organic layer to the surface treatment process, forming an inorganic insulating passivation layer on a side of the organic layer and the first electrode layer away from the base substrate, wherein the inorganic insulating passivation layer is formed in direct contact with the first electrode layer and in direct contact with the organic layer, the inorganic insulating passivation layer is formed so that an orthographic projection of the inorganic insulating passivation layer on the base substrate substantially covers orthographic projections of the first electrode layer and the organic layer.

US Pat. No. 10,431,606

DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a display region, and a peripheral region that is outside of the display region;
a first dummy pad and a second dummy pad at the peripheral region, the first dummy pad vertically overlapping the second dummy pad;
an insulating layer completely covering the first and second dummy pads such that each of the first and second dummy pads does not contact a conductive layer, wherein a top surface of a first portion of the insulating layer above a center of the first and second dummy pads is higher than a top surface of a second portion of the insulating layer adjacent the first and second dummy pads; and
a pad over the second portion of the insulating layer at the peripheral region, the pad being electrically connected to an electronic chip or a printed circuit board.

US Pat. No. 10,431,605

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A method of manufacturing a thin film transistor array panel, the method comprising:providing a gate line and a data line comprising a drain electrode on an insulating substrate;
providing an organic insulating layer, through which a first contact hole is formed, on the gate line and the data line;
providing a common electrode, through which a second contact hole is formed, on the organic insulating layer;
providing a passivation layer on the common electrode;
forming a third contact hole through the passivation layer to expose an end of the drain electrode; and
providing a pixel electrode on the passivation layer to be in contact with the drain electrode through the third contact hole,
wherein the third contact hole is formed to be adjacent to one surface of the first contact hole.

US Pat. No. 10,431,604

DISPLAY DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a substrate including:
a main display portion;
an edge portion disposed at one of edges of the main display portion; and
a first side portion bent from the edge portion;
scan lines disposed on the substrate;
data lines disposed on the substrate;
transistors connected to the scan lines and the data lines; and
a data voltage transmission line connected to a data line disposed in the first side portion and disposed on both the edge portion and the main display portion,
wherein the data line and the data voltage transmission line are disposed in different layers from each other.

US Pat. No. 10,431,603

SEMICONDUCTOR DEVICE

JOLED INC., Tokyo (JP)

1. A semiconductor device comprising:a substrate including a first region, a second region, and a third region that are provided adjacently in this order in a predetermined direction;
a first wiring line that is provided on the substrate and provided in each of the first region, the second region, and the third region;
a semiconductor film having a low-resistance region in at least a portion of the semiconductor film, the semiconductor film being provided between the first wiring line and the substrate in the first region, and being in direct physical contact with the first wiring line in the second region;
a second wiring line that is provided at a position closer to the substrate than the semiconductor film, and is in contact with the first wiring line in the third region; and
an insulating film provided between the first wiring line in the first region and the semiconductor film in the first region.

US Pat. No. 10,431,602

ARRAY SUBSTRATE, DISPLAY PANEL, AND DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a display area; and
a surrounding area having a first signal line, and a second signal line disposed over, insulated from, and staggered at a staggering region with, the first signal line, the surrounding area encircling the display area;
wherein:
the surrounding area comprises a first zone and a second zone, wherein the first zone and the second zone are configured to have a height difference to form a substantially uneven upper surface of the array substrate to thereby allow a sealant to be securely attached onto the array substrate; and
an upper surface of the first zone is substantially flat across the first zone from over a side of the second signal line to an opposing side of the second signal line.

US Pat. No. 10,431,601

METHOD FOR MANUFACTURING ARRAY SUBSTRATE, AND ARRAY SUBSTRATE, DISPLAY PANEL AND DISPLAY DEVICE

SHANGHAI TIANMA MICRO-ELE...

1. A method for manufacturing an array substrate, comprising:forming, on one side of a substrate, a gate electrode layer, a gate insulation layer located on the gate electrode layer and a semiconductor layer located on the gate insulation layer, wherein the gate electrode layer has a same pattern as the semiconductor layer;
forming an etching stop layer on the semiconductor layer;
forming a first through hole, a second through hole and a third through hole in the etching stop layer by patterning the etching stop layer;
forming a source electrode layer on the etching stop layer and a drain electrode layer on the etching stop layer, wherein the source electrode layer is electrically connected with the semiconductor layer via the first through hole, and the drain electrode layer is electrically connected with the semiconductor layer via the second through hole; and
forming an active layer by etching the semiconductor layer at a location corresponding to the third through hole, wherein the gate electrode layer comprises a first part at the location corresponding to the third through hole and a second part, the second part of the gate electrode layer using a same pattern as the active layer and being different from the first part;
wherein the forming, on one side of the substrate, the gate electrode layer, the gate insulation layer located on the gate electrode layer and the semiconductor layer located on the gate insulation layer comprises:
forming a first metal layer on the substrate, and forming the gate electrode layer by patterning the first metal layer;
forming the gate insulation layer on the gate electrode layer;
forming a semiconductor material layer on the gate insulation layer; and
forming the semiconductor layer by patterning the semiconductor material layer by taking the gate electrode layer as a mask.

US Pat. No. 10,431,600

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A METAL OXIDE FILM

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:forming an oxide semiconductor film at a first temperature;
processing the oxide semiconductor film into an island shape;
depositing a material to be a source electrode and a drain electrode over the oxide semiconductor film by a sputtering method;
processing the material to form the source electrode and the drain electrode;
forming a protective insulating film over the oxide semiconductor film, the source electrode and the drain electrode;
heating the protective insulating film at a second temperature which is higher than the first temperature;
forming a metal oxide film over the protective insulating film by a sputtering method; and
heating the protective insulating film at a third temperature which is higher than the first temperature,
wherein at least one of the second temperature and the third temperature is the highest in the method.

US Pat. No. 10,431,599

SUBSTRATE FOR DISPLAY DEVICE AND DISPLAY DEVICE INCLUDING THE SAME

LG Display Co., Ltd., Se...

1. A display device, comprising:a substrate;
a pixel on the substrate, the pixel including:
a first TFT on the substrate, the first TFT including:
a first active layer formed of oxide semiconductor; and
a second thin film transistor (TFT) on the substrate, the second TFT including:
a gate electrode on the substrate,
at least a first part of a gate insulating film on the gate electrode,
a second active layer formed of polycrystalline silicon on the first part of the gate insulating film, wherein a bottom surface of the second active layer faces the gate electrode, and
a source electrode and a drain electrode contacting a top surface of the second active layer;
a light-emitting device electrically connected to the second TFT; and
a connection electrode contacting both of the drain electrode of the second TFT and an anode electrode of the light-emitting device between the drain electrode of the second TFT and the anode electrode.

US Pat. No. 10,431,598

VERTICAL SEMICONDUCTOR DEVICE WITH THINNED SUBSTRATE

QUALCOMM Incorporated, S...

1. An integrated circuit chip comprising:an active semiconductor region having a plurality of fabricated semiconductor structures comprising a source, drain and channel that form a vertical semiconductor device, the active semiconductor region being exposed on a bottom side by the absence of substrate material such that the drain and channel of the semiconductor structures are exposed semiconductor structures that provide the vertical semiconductor device with an electrical contact; and
a bottom side electrode connected to the drain or the channel, wherein:
the channel isolates the source from the drain;
the channel has a bottom boundary and a side boundary extending downward from a top surface of the active semiconductor region to the bottom boundary; and
the drain and channel are in contact along the side boundary and are not in contact along the bottom boundary, further wherein:
the source has a second bottom boundary and a second side boundary extending downward from the top surface of the active semiconductor region to the second bottom boundary; and
the source and the channel are in contact along the second side boundary and are not in contact along the second bottom boundary.

US Pat. No. 10,431,596

STAGGERED WORD LINE ARCHITECTURE FOR REDUCED DISTURB IN 3-DIMENSIONAL NOR MEMORY ARRAYS

SUNRISE MEMORY CORPORATIO...

1. A memory structure, comprising:a semiconductor substrate having a planar surface;
an array of memory cells sharing a common bit line that extends along a first direction substantially parallel the planar surface of the semiconductor substrate, wherein a first group of the memory cells are provided on a first side of the common bit line and wherein a second group of the memory cells are provided on a second side of the common bit line opposite the first side and wherein each memory cell comprises a storage layer;
a first plurality of conductors provided above the semiconductor substrate and below the array of memory cells, each conductor in the first plurality of conductors extending along a second direction that is parallel the planar surface and substantially perpendicular to the first direction, wherein the conductors of the first plurality of conductors are separated from each other by a first distance;
a second plurality of conductors provided above the array of memory cells, each conductor in the second plurality of conductors extending along the second direction, wherein the conductors of the second plurality of conductors are separated from each other by the first distance, and wherein the second plurality of conductors are offset from the first set of conductors by substantially half the first distance along the first direction;
a third plurality of conductors each extending along a third direction substantially perpendicular to the planar surface, wherein a first group of the third plurality of conductors each contact a conductor in the first plurality of conductors and wherein a second group of the third plurality of conductors each contact a conductor in the second plurality of conductors, wherein each conductor in the first and second groups of the third plurality of conductors are provided in contact with a storage layer of a memory cell in the first group or the second group of the memory cells, serving as a gate electrode for the memory cell.

US Pat. No. 10,431,595

MEMORY DEVICES HAVING VERTICALLY EXTENDING CHANNEL STRUCTURES THEREIN

Samsung Electronics Co., ...

1. A memory device comprising:a substrate having a first source film thereon;
an upper stacked structure on the first source film;
an electrically conductive channel structure extending through the upper stacked structure and the first source film, said channel structure comprising a channel pattern, which extends vertically through the upper stacked structure and the first source film, and an information storage pattern on a sidewall of the channel pattern;
a second source film extending between the first source film and a surface of said substrate, said second source film contacting the channel pattern and comprising an upward extending protrusion, which extends underneath the information storage pattern; and
a channel protective film extending between at least a portion of the protrusion and at least a portion of the information storage pattern.

US Pat. No. 10,431,594

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:a lower stack;
a first upper stack disposed on the lower stack;
a second upper stack disposed on the lower stack, and spaced apart from the first upper stack by a select line separation trench;
first plugs configured to pass through the first upper stack and the lower stack, each of the first plugs including a sidewall protruding further into the select line separation trench than a sidewall of the first upper stack facing the select line separation trench to define a sidewall of the select line separation trench;
second plugs configured to pass through the second upper stack and the lower stack, each of the second plugs including a sidewall protruding further into the select line separation trench than a sidewall of the second upper stack facing the select line separation trench to define a sidewall of the select line separation trench; and
a select line separation layer formed along a contour of the protruded sidewalls of the first and second plugs in the select line separation trench.

US Pat. No. 10,431,593

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES

Samsung Electronics Co., ...

1. A three-dimensional semiconductor memory device, comprising:a substrate; and
a first channel group, a second channel group, a third channel group, and a fourth channel group each arranged in a first direction on the substrate,
the first channel group to the fourth channel group being spaced apart from each other along a second direction on the substrate that crosses the first direction,
each of the first channel group, the second channel group, the third channel group, and the fourth channel group including a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate,
the first channel group and the second channel group being adjacent to each other in the second direction and spaced apart by a first distance in the second direction,
the second channel group and the third channel group being adjacent to each other in the second direction and spaced apart by a second distance less than the first distance in the second direction, and
the third channel group and the fourth channel group being adjacent to each other in the second direction and spaced apart by a third distance less than the second distance in the second direction.

US Pat. No. 10,431,592

3D MEMORY DEVICE

Trinandable S.r.l., Mila...

1. A 3D memory device comprising:a substrate;
at least one first group of four first “U”-shaped memory cells strings each including a first buried string portion, a first source line selector side string portion and a first bit line selector side string portion, wherein the first buried string portion is formed in the substrate and connects the first source line selector side string portion and the first bit line selector side string portion, each of the first “U”-shaped memory cells strings including memory cells stacks along the first source line selector side string portion and along the first bit line selector side string portion; and
at least one second group of four second “U”-shaped memory cells strings each including a second buried string portion, a second source line selector side string portion and a second bit line selector side string portion, wherein the second buried string portion is formed in the substrate and connects the second source line selector side string portion and the second bit line selector side string portion, each of the second “U”-shaped memory cells strings including memory cells stacks along the second source line selector side string portion and along the second bit line selector side string portion;
wherein the first and second source line selector side string portions are between the first and second bit line selector side string portions;
wherein a first pair of the first “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the first “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of first “U”-shaped memory cells strings and one surrounded by the other, a first pair of the second “U”-shaped memory cells strings are mutually co-planar and one surrounded by the other, a second pair of the second “U”-shaped memory cells strings are mutually co-planar but staggered with respect to the first pair of second “U”-shaped memory cells strings and one surrounded by the other;
wherein first bit line selectors surround the first bit line selector side string portions and second bit line selectors surround the second bit line selector side string portions, and wherein the first bit line selectors comprise one first bit line selector for each of the first bit line selector side string portions and the second bit line selectors comprise one second bit line selector for each of the second bit line selector side string portions;
wherein the 3D memory device comprises a first, a second, a third and a fourth bit lines operatively associated to the first and second groups of four first and second “U”-shaped memory cells strings, wherein:
the first bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of one of the first pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of one of the first pair of the second “U”-shaped memory cells strings;
the second bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of the other one of the first pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of the other one of the first pair of the second “U”-shaped memory cells strings;
the third bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of one of the second pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of one of the second pair of the second “U”-shaped memory cells strings, and
the fourth bit line is connected, through a respective first bit line selector and second bit line selector, to the first bit line selector side string portion of the other one of the second pair of the first “U”-shaped memory cells strings and to the second bit line selector side string portion of the other one of the second pair of the second “U”-shaped memory cells strings.

US Pat. No. 10,431,591

NAND MEMORY ARRAYS

Micron Technology, Inc., ...

1. A NAND memory array, comprising:a vertical stack of alternating insulative levels and wordline levels, the wordline levels having terminal ends corresponding to control gate regions;
charge-trapping material along the control gate regions of the wordline levels, and being spaced form the control gate regions by charge-blocking material; the charge-trapping material along the wordline levels being charge-trapping material segments; the charge-trapping material segments being vertically spaced from one another by intervening regions; charge migration being impeded along said intervening regions relative to charge migration within the charge-trapping material segments; and
channel material extending vertically along the stack and being spaced from the charge-trapping material segments by charge-tunneling material.

US Pat. No. 10,431,590

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a stacked body including
a first stacked unit and a second stacked unit stacked above the first stacked unit, each of the first and second stacked units including a plurality of first electrode layers alternately stacked with a plurality of first insulating layers therebetween, and
a first intermediate layer provided above the first stacked unit and below the second stacked unit, a thickness of the first intermediate layer being greater than a thickness of the first insulating layers;
a semiconductor pillar piercing the stacked body in a stacking direction of the stacked body, the semiconductor pillar including a first semiconductor film portion covering an outer periphery of a first core insulator part extending in the a first stacked unit and a second semiconductor film portion covering an outer periphery of a second core insulator part extending in the a second stacked unit, the first semiconductor film portion and the second semiconductor film portion having asymmetric configurations with respect to the first intermediate layer;
a first charge storage film provided between the first semiconductor film portion and one part of the first electrode layers included in the first stacked unit; and
a second charge storage film provided between the second semiconductor film portion and another part of the first electrode layers included in the second stacked unit, wherein
the first semiconductor film portion is electrically connected to the second semiconductor film portion via a third semiconductor film portion provided in the first intermediate layer,
the first charge storage film is discontinuous with the second charge storage film, and
the first charge storage film and the second charge storage film are not provided between the third semiconductor film portion and the first intermediate layer.

US Pat. No. 10,431,589

MEMORY CELL, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

FLOADIA CORPORATION, Tok...

10. A method for manufacturing a semiconductor integrated circuit device including:a memory circuit region in which a memory cell including a memory gate structure between a first select gate structure and a second select gate structure is disposed; and
a peripheral circuit region in which a peripheral circuit including a logic gate structure is disposed,
the method comprising:
a first dummy electrode layer forming process of forming a layered lower memory gate insulating film and a layered charge storage layer in this order on a semiconductor substrate in the memory circuit region, and then stacking a layered first insulating film and a layered logic dummy electrode layer in this order on the charge storage layer in the memory circuit region and the semiconductor substrate in the peripheral circuit region;
a dummy memory gate structure forming process of patterning the logic dummy electrode layer, the first insulating film, the charge storage layer, and the lower memory gate insulating film in the memory circuit region by using a patterned resist so that a dummy memory gate structure in which the lower memory gate insulating film, the charge storage layer, an upper memory gate insulating film, and a dummy memory gate electrode provided by patterning are stacked in this order is formed in the memory circuit region and the first insulating film and the logic dummy electrode layer remain intact in the peripheral circuit region using the resist;
a sidewall insulating film forming process of forming a layered sidewall insulating film across the memory circuit region and the peripheral circuit region, and then etching back the layered sidewall insulating film to expose the semiconductor substrate, thereby forming sidewall insulating films along facing sidewalls of the dummy memory gate structure in the memory circuit region;
a second dummy electrode layer forming process of forming a layered second insulating film across the memory circuit region and the peripheral circuit region to form sidewall spacers composed of the sidewall insulating films and the second insulating film on the respective facing sidewalls of the dummy memory gate structure, stacking a layered memory dummy electrode layer on the second insulating film, and removing the memory dummy electrode layer and the second insulating film in this order in the peripheral circuit region by using a patterned resist so that the second insulating film and the memory dummy electrode layer remain in the memory circuit region;
a dummy gate electrode forming process of patterning the logic dummy electrode layer and the first insulating film in the peripheral circuit region by using another patterned resist to form a dummy logic gate structure in which a dummy logic gate electrode is stacked on the semiconductor substrate through a logic gate insulating film, and etching back the memory dummy electrode layer and the second insulating film in the memory circuit region so that a sidewall-shaped dummy first select gate electrode is formed along one of the sidewall spacers of the dummy memory gate structure whereas the second insulating film remains below the dummy first select gate electrode to form a first select gate insulating film, and a sidewall-shaped dummy second select gate electrode is formed along the other sidewall spacer of the dummy memory gate structure whereas the second insulating film remains below the dummy second select gate electrode to form a second select gate insulating film;
an electrode exposing process of forming an interlayer insulating layer in the memory circuit region and the peripheral circuit region, and then processing the interlayer insulating layer to expose, on the interlayer insulating layer, top surfaces of the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode; and
a metal gate electrode forming process of removing the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode, and then forming, in electrode formation spaces in which the dummy memory gate electrode, the dummy first select gate electrode, the dummy second select gate electrode, and the dummy logic gate electrode have been formed, a metal memory gate electrode, a metal first select gate electrode, a metal second select gate electrode, and a metal logic gate electrode each containing a metallic material.

US Pat. No. 10,431,587

SEMICONDUCTOR DEVICE FOR AVOIDING SHORT CIRCUIT BETWEEN ADJACENT STORAGE NODES AND MANUFACTURING METHOD THEREOF

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a substrate comprising a plurality of active regions, wherein each of the active regions comprises two source/drain regions, and each of the source/drain regions is disposed at a respective end of the active area;
a plurality of word lines disposed in the substrate, wherein each of the word lines is disposed elongated in a first direction;
a plurality of bit lines disposed on the substrate, wherein each of the bit lines is disposed elongated in a second direction and straddling the word lines, and each of the source/drain regions is disposed in a region surrounded by two of the word lines adjacent to each other and two of the bit lines adjacent to each other;
a plurality of storage node contacts disposed on the source/drain regions respectively, wherein a width of a top surface of each of the storage node contacts in the second direction is smaller than a width of a bottom surface of each of the storage node contacts in the second direction; and
a cap layer disposed on the word lines, wherein each of the storage node contacts is disposed on a plane of a top surface of the cap layer, and each of the storage node contacts has a trapezoid shape in the second direction.

US Pat. No. 10,431,586

SEMICONDUCTOR DEVICE HAVING CONTACT PLUGS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate;
a first fin on the substrate;
a first source/drain on the first fin; and
a first contact plug on the first source/drain,
wherein a center of the first contact plug is offset from a center of the first fin,
wherein a bottom surface of the first contact plug is inclined with respect to a top surface of the substrate,
wherein the bottom surface of the first contact plug includes a first edge and a second edge opposite to the first edge, and
wherein the first edge is at a different level than the second edge.

US Pat. No. 10,431,585

SEMICONDUCTOR DEVICES WITH MULTI-GATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first transistor in a first region of a substrate and a second transistor in a second region of the substrate,
wherein the first transistor comprises: a first nanowire having a first channel region; a first gate electrode surrounding the first nanowire; a first gate dielectric layer between the first nanowire and the first gate electrode; a first source/drain region connected to an edge of the first nanowire; and an inner-insulating spacer between the first gate dielectric layer and the first source/drain region,
the second transistor comprises: a second nanowire having a second channel region; a second gate electrode surrounding the second nanowire; a second gate dielectric layer between the second nanowire and the second gate electrode; and a second source/drain region connected to an edge of the second nanowire,
the second gate dielectric layer extends between the second gate electrode and the second source/drain region and is in contact with the second source/drain region, and
the first source/drain region is not in contact with the first gate dielectric layer.

US Pat. No. 10,431,584

SEMICONDUCTOR DEVICE INCLUDING FIN STRUCTURES AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A fin field effect transistor (FinFET), comprising:a fin structure which has a first region made of a first semiconductor material, a second region made of a second semiconductor material different from the first semiconductor material, and a channel region made of a third semiconductor material different from the second semiconductor material;
an isolation region in which the first region and the second region are embedded, and from which at least an upper port of the channel region is exposed; and
a gate structure disposed over the channel region, wherein:
an interface between the second region and the first region is located below an upper surface of the isolation region,
the first semiconductor material includes a first Ge based semiconductor material,
the second semiconductor material includes a Si or a Si based semiconductor material,
the third semiconductor material includes a second Ge based semiconductor material, and
Ge contents of the first and second Ge based semiconductor materials are greater than a Ge content of the second semiconductor material.

US Pat. No. 10,431,582

HIGH SPEED SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:a fin extending from a substrate;
a first source/drain feature;
a second source/drain feature;
a gate structure on the fin, wherein a first distance between the gate structure and the first source/drain feature is different from a second distance between the gate structure and the second source/drain feature; and
a buried channel extending from a sidewall of the first source/drain feature to a sidewall of the second source/drain feature, wherein a top surface of the buried channel is spaced from a top surface of the substrate and a bottom surface of the buried channel is closer to the top surface of the substrate than a bottom surface of the first source/drain feature;
dopants in the buried channel, wherein a highest concentration of the dopants is under the gate structure.

US Pat. No. 10,431,581

COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) INTEGRATION WITH COMPOUND SEMICONDUCTOR DEVICES

QUALCOMM Incorporated, S...

1. A semiconductor device comprising:a substrate;
a well region disposed adjacent to the substrate;
a first fin disposed above the well region;
a second fin disposed above the substrate;
a gate region disposed adjacent to each of the first fin and the second fin;
at least one third fin disposed above the substrate;
a support layer disposed above the at least one third fin; and
a compound semiconductor device disposed above the support layer.

US Pat. No. 10,431,579

DISPLAY PANEL INCLUDING ELECTROSTATIC PROTECTION CIRCUIT, DRIVING METHOD OF THE SAME, AND DISPLAY DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A display panel, comprising:a plurality of pixel circuits arranged in a display area of the display panel, wherein the plurality of pixel circuits is arranged in rows and columns, the display area of the display panel comprises a first display area and a second display area arranged along a row direction, and an outer edge of the second display area extends stepwise along a column direction;
a plurality of data lines each extending along the column direction, wherein the plurality of data lines corresponds to a plurality of columns of the plurality of pixel circuits in one-to-one correspondence;
a plurality of signal line groups, wherein the plurality of signal line groups corresponds to a plurality of rows of the plurality of pixel circuits in one-to-one correspondence, and each of the plurality of signal line groups comprises a scan line and a light-emitting control signal line each extending along the row direction; and
a plurality of first electrostatic protection circuits, wherein the plurality of first electrostatic protection circuits corresponds and is connected to the data lines in the second display area in one-to-one correspondence, each of the plurality of first electrostatic protection circuits is electrically connected to a scan line and a light-emitting control signal line of a same signal line group, and each of the plurality of first electrostatic protection circuits is used to discharge static electricity on a data line connected to the first electrostatic protection circuit to the scan line or the light-emitting control signal line connected to the first electrostatic protection circuit.

US Pat. No. 10,431,578

ELECTROSTATIC DISCHARGE (ESD) PROTECTION DEVICE AND METHOD FOR OPERATING AN ESD PROTECTION DEVICE

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising:stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes,
wherein an emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor; and
an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node,
wherein a gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor.

US Pat. No. 10,431,576

MEMORY CELL ARRAY AND METHOD OF MANUFACTURING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a memory cell array, the method comprising:generating a first set of tiles extending in a first direction, wherein the generating the first set of tiles comprises:
generating a first layout design of a first set of memory cells, each tile of the first set of tiles corresponds to the first layout design of the first set of memory cells, and each tile of the first set of tiles is offset from an adjacent tile of the first set of tiles in a second direction different from the first direction;
generating a second set of tiles, wherein the generating the second set of tiles comprises:
generating a second layout design of a second set of memory cells, each tile of the second set of tiles corresponds to the second layout design of the second set of memory cells, and each tile of the second set of tiles is offset from an adjacent tile of the second set of tiles in the second direction,
wherein each tile of the first set of tiles extends in a third direction different from the first direction and the second direction, the first set of tiles and the second set of tiles alternate with each other in the second direction, and each tile of the second set of tiles extends in the third direction, and at least one of the above generating operations is performed by a hardware processor, and the first layout design is stored in a non-transitory computer-readable medium; and
manufacturing the memory cell array based on at least the first layout design.

US Pat. No. 10,431,575

MULTI-DIE ARRAY DEVICE

NXP B.V., Eindhoven (NL)...

1. A method for fabricating a multi-die package, the method comprising:placing a plurality of flip chip dies and a plurality of splitter dies on a sacrificial carrier, each flip chip die and each splitter die positioned in an active side down orientation on the sacrificial carrier;
performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier, wherein the sacrificial carrier comprises test probe circuitry;
testing the plurality of flip chip dies and the plurality of splitter dies in a probe test using the test probe circuitry;
replacing any faulty flip chip dies and any faulty splitter dies as indicated by the testing;
overmolding the plurality of flip chip dies and the plurality of splitter dies on the sacrificial carrier to form a panel of embedded dies;
planarizing the panel of embedded dies to expose a back surface of each flip chip die and each splitter die in a back surface of the panel of embedded dies;
forming a metallization layer across the back surface of the panel of embedded dies that contacts the back surface of each flip chip die and each splitter die; and
removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and each splitter die is exposed in the front surface of the panel of embedded dies.

US Pat. No. 10,431,574

METHODS AND SYSTEMS FOR PACKAGING SEMICONDUCTOR DEVICES TO IMPROVE YIELD

Marvell World Trade Ltd.,...

1. A method for packaging semiconductor devices in a chamber, the method comprising:arranging a carrier substrate including a first semiconductor device and a second semiconductor device within the chamber;
flowing a molding compound into the chamber to cover surfaces of the first semiconductor device, the second semiconductor device, and the carrier substrate; and
flowing a forming gas into the chamber while curing the molding compound, wherein the forming gas includes a reactive gas configured to react with the first semiconductor device and the second semiconductor device during curing,
wherein the forming gas reforms broken bonds of the first semiconductor device and the second semiconductor device resulting from the curing.

US Pat. No. 10,431,573

METHOD FOR STACKING CORE AND UNCORE DIES HAVING LANDING SLOTS

Intel Corporation, Santa...

1. A method comprising:mounting an uncore die on a package, the uncore die comprising a plurality of exposed landing slots, each landing slot including an inter-die interface usable to connect vertically to a cores die, the uncore die including a plurality of uncore components usable by cores within the cores die including a memory controller component, a level 3 (L3) cache, a system memory or system memory interface, and a core interconnect fabric or bus;
vertically coupling a first cores die comprising a first plurality of cores on top of the uncore die, the cores spaced on the first cores die to correspond to all or a first subset of the landing slots on the uncore die, each of the cores having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the first cores die is vertically coupled on top of the uncore die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die; and
vertically coupling a second cores die comprising a second plurality of cores on top of the uncore die, the cores of the second plurality spaced on the second cores die to correspond to a second subset of the landing slots on the uncore die different from the first subset, each of the cores on the second cores die having an inter-die interface positioned to be communicatively coupled to a corresponding inter-die interface within a landing slot on the uncore die when the second cores die is vertically coupled on top of the uncore die with the first cores die, wherein the communicative coupling between the inter-die interface of a core and the inter-die interface of its corresponding landing slot communicatively couples the core to the uncore components of the uncore die.

US Pat. No. 10,431,571

OPTO-ELECTRONIC MODULES, IN PARTICULAR FLASH MODULES, AND METHOD FOR MANUFACTURING THE SAME

ams Sensors Singapore Pte...

1. An opto-electronic module comprising:a substrate member;
at least two emission members mounted on said substrate member;
at least one detecting member mounted on said substrate member;
an optics member comprising a first lens and a second lens; and
a spacer member arranged between said substrate member and said optics member, the spacer member abutting a first side of the substrate member and a first side of the optics member, and establishing a well-defined distance between the substrate member and the optics member, wherein the first side of the substrate member faces the first side of the optics member;
wherein the first lens is assigned to a first of said at least two emission members and the second lens is assigned to a second of said at least two emission members, said first lens and said first emission member being arranged such that light emitted from said first emission member traverses predominantly said first lens, and said second lens and said second emission member being arranged such that light emitted from said second emission member traverses predominantly said second lens, wherein a light intensity distribution of light emitted by said first emission member through said first lens leaving the opto-electronic module is different from a light intensity distribution of light emitted by said second emission member through said second lens leaving the opto-electronic module.

US Pat. No. 10,431,570

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYODA GOSEI CO., LTD., ...

1. A light emitting device, comprising:a substrate;
a plurality of light emitting elements disposed on the substrate;
a transparent resin embedded only in a space between the plurality of light emitting elements; and
a phosphor containing resin layer formed on the plurality of light emitting elements and the transparent resin,
wherein the transparent resin includes no phosphor,
wherein the phosphor containing resin layer comprises a plurality of regions comprising different kinds of phosphors,
wherein each one of the plurality of regions is disposed on each one of the plurality of light emitting elements,
wherein the plurality of light emitting elements are disposed on the substrate in a stacking direction of the phosphor containing resin layer on the plurality of light emitting elements, and
wherein, in the stacking direction, a bottom surface of the phosphor containing resin layer and a border of the plurality of regions of the phosphor containing resin layer are disposed on a top surface of the transparent resin.

US Pat. No. 10,431,569

METHOD OF TRANSFERRING MICRO DEVICES

PlayNitride Inc., Tainan...

1. A method of transferring micro devices, comprising:providing a carrier substrate, on which a buffer layer and a plurality of micro devices are disposed, the buffer layer being located between the carrier substrate and the micro devices, an upper surface of each of the micro devices is entirely in contact with the buffer layer, the micro devices being separated from one another and positioned on the carrier substrate through the buffer layer;
providing a bonding layer between the micro devices and a receiving substrate;
making a receiving substrate contact the micro devices on the carrier substrate;
after the micro devices contact the receiving substrate, reducing bonding force between at least a portion of the micro devices and the carrier substrate by melting the buffer layer through raising a temperature of the carrier substrate; and
liquefying the bonding layer by raising a temperature of the receiving substrate such that adhesive force between the at least a portion of the micro devices and the bonding layer is greater than bonding force between the at least a portion of the micro devices and the carrier substrate, so that the at least a portion of the micro devices are released from the carrier substrate and transferred onto the receiving substrate, wherein a number of the at least a portion of the micro devices is in a range from 1000 to 2000000.

US Pat. No. 10,431,568

LIGHT EMITTING DIODES, COMPONENTS AND RELATED METHODS

Cree, Inc., Durham, NC (...

1. A light emitting diode (LED) device comprising:a submount comprising an upper surface and a bottom surface;
a plurality of LEDs disposed on the upper surface of the submount, the plurality of LEDs each comprising an upper surface of a diode and one or more sides, the LEDs being spaced apart with a gap between the LEDs;
an encapsulant comprising an upper curved surface and one or more planar side surfaces, the upper curved surface having a radius curvature that is greater than half a length or width of the submount, wherein the one or more planar side surfaces comprise truncated sections of the upper curved surface so that the encapsulant does not overhang an outermost edge of the submount, at least a portion of each of the one or more planar side surfaces extending to a respective outermost edge of the upper surface of the submount; and
a phosphor layer disposed on the upper surface of the diodes, on one or more sides of the plurality of LEDs and in the gap between the LEDs,
wherein the gap between the LEDs ranges from about 1 to about 300 micrometers (?m),
wherein a ratio of a particle size of phosphor in the gap to a width of the gap between the LEDs is approximately 30% to approximately 75%,
wherein the device, based on the gap between the LEDs and the ratio of the particle size of phosphor in the gap to the width of the gap, is configured to produce an emission pattern devoid of a deadspot.

US Pat. No. 10,431,567

WHITE CERAMIC LED PACKAGE

CREE, INC., Durham, NC (...

1. An emitter package, comprising:a casing comprising a cavity extending into the interior of said casing from a top surface of said casing;
electrically conductive bond pads integral to said casing, wherein a first set of said bond pads comprises chip carrier parts, and a second set of said bond pads comprises connection parts;
a plurality of light emitting devices (LEDs) on said first set of bond pads, with said light emitting devices and portions of said bond pads exposed through said cavity;
a plurality of electrodes at least on the bottom surface of said casing; and
through-holes integral to each of said bond pads, wherein said through-holes are embedded within said casing and extend into each of said bond pads and said electrodes to provide electrical paths between said bond pads and said electrodes;
wherein at least one of said chip carrier parts or connection parts is at least partially defined by an indentation.

US Pat. No. 10,431,565

WAFER EDGE PARTIAL DIE ENGINEERED FOR STACKED DIE YIELD

XILINX, INC., San Jose, ...

1. A method for forming a stacked wafer assembly, the method comprising:contacting an exposed dielectric material layer of a first wafer to an exposed dielectric material layer of a second wafer;
pressing the first wafer against the second wafer to cause the dielectric material layers to create a bond between the first wafer and the second wafer; and
forming electrical connections between bond pads formed over a first inductor of a partial die residing on the first wafer and bond pads formed on a partial die residing on the second wafer; and
forming electrical connections between bond pads of a full die residing on the first wafer and bond pads formed on a full die residing on the second wafer, wherein the full die and the partial die are structurally different.

US Pat. No. 10,431,564

STRUCTURE AND FORMATION METHOD OF CHIP PACKAGE STRUCTURE

MediaTek Inc., Hsin-Chu ...

1. A chip package structure, comprising:a first chip package over a printed circuit board;
a second chip package over the first chip package;
a plurality of conductive bumps extending between a substrate of the first chip package and the printed circuit board;
a plurality of thermal conductive elements extending between the substrate of the first chip package and the printed circuit board, each of the thermally conductive elements being formed of metal foil and exhibiting a sidewall perpendicular to the printed circuit board;
a first bonding layer between the plurality of thermal conductive elements and the first chip package; and
a second bonding layer between the plurality of thermal conductive elements and the printed circuit board;
wherein each of the thermal conductive elements has a thermal conductivity higher than a thermal conductivity of each of the conductive bumps,
wherein the thermal conductive elements are connected to conductive pads, the conductive pads being positioned under a source of heat such that the thermally conductive elements connected thereto dissipate heat from the source of heat, with at least some of the thermal conductive elements exhibiting different shapes or sizes.

US Pat. No. 10,431,563

CARRIER AND INTEGRATED MEMORY

International Business Ma...

1. A method of integrated circuit (IC) carrier fabrication comprising:joining a memory, a heat spreader, and a IC chip carrier with a dielectric material such that the heat spreader contacts a sidewall of the memory and such that a contact surface of the memory and an IC chip facing surface of the dielectric material are coplanar with a IC chip facing surface of the carrier;
forming a vertical interconnect access (VIA) within the heat spreader and within the dielectric material from the IC chip facing surface of the dielectric material to a system facing surface of the dielectric material;
forming a first carrier interconnect upon the contact surface of the memory, upon the IC chip facing surface of the dielectric material, and upon the IC chip facing surface of the carrier, the first carrier interconnect electrically connecting a signal contact of the memory and a wiring line within the IC chip carrier; and
forming a second carrier interconnect upon the IC chip facing surface of the dielectric material, the second carrier interconnect electrically connecting a power or ground contact of the memory and the VIA.

US Pat. No. 10,431,562

BACK SIDE METALLIZATION

Advanced Micro Devices, I...

1. A method of forming a metallization structure on a back side of a silicon wafer substrate, the silicon wafer substrate including a plurality of integrated circuits formed on a front side of the silicon wafer substrate, the method comprising:forming a first adhesion layer on the back side of the silicon wafer substrate, the first adhesion layer including at least one of: silicon dioxide and silicon nitride;
forming a first barrier layer including titanium metal over the first adhesion layer;
forming a second barrier layer including nickel over the first barrier layer; and
forming a second adhesion layer over the second barrier layer, the second adhesion layer including at least one of: silver, gold, and tin.

US Pat. No. 10,431,561

PRE-CONDUCTIVE ARRAY DISPOSED ON TARGET CIRCUIT SUBSTRATE AND CONDUCTIVE STRUCTURE ARRAY THEREOF

ULTRA DISPLAY TECHNOLOGY ...

1. A pre-conductive array disposed on a target circuit substrate, comprising:a plurality of conductive electrode groups disposed on the target circuit substrate, wherein a first distance is provided between every two of the conductive electrode groups, and each of the conductive electrode groups comprises at least a pair of conductive electrodes; and
at least a conductive particle dispose on each of the conductive electrodes of a part or all of the conductive electrode groups;
wherein the conductive particle and the corresponding pair of the conductive electrodes form a pre-conductive structure, and the pre-conductive structures form the pre-conductive array;
wherein a first density is defined to represent a number of the conductive particles within a unit area of each of the pre-conductive structures, a second density is defined to represent a number of the conductive particles within a unit area between two of the pre-conductive structures, and the first density is greater than the second density.

US Pat. No. 10,431,560

MOLDED SEMICONDUCTOR PACKAGE HAVING AN OPTICAL INSPECTION FEATURE

Infineon Technologies AG,...

1. A molded semiconductor package, comprising:a mold compound having a first main surface, a second main surface opposite the main surface, and an edge extending between the first and the second main surfaces;
a semiconductor die embedded in the mold compound; and
a plurality of metal pads embedded in the mold compound and electrically connected to the semiconductor die,
wherein the metal pads have a bottom face which is uncovered by the mold compound at the second main surface of the mold compound,
wherein the metal pads disposed around a periphery of the molded package have a side face which is uncovered by the mold compound at the edge of the mold compound,
wherein the entire side face of each metal pad disposed around the periphery of the molded package is plated and recessed inward from the edge of the mold compound.

US Pat. No. 10,431,559

METHOD FOR MANUFACTURING A SEMICONDUCTOR STRUCTURE

NANYA TECHNOLOGY CORPORAT...

1. A method of manufacturing a semiconductor structure, comprising:providing a carrier including a recess;
disposing a second dielectric layer of a first passivation over the carrier and filling the recess;
providing a substrate including a pad and a first dielectric layer of the first passivation disposed thereon, wherein the pad is covered with the first dielectric layer before bonding the first dielectric layer with the second dielectric layer;
bonding the first dielectric layer with the second dielectric layer;
removing the carrier;
removing a portion of the first passivation to expose a portion of the pad;
disposing a conductive layer over the first passivation and the portion of the pad;
disposing a second passivation over the conductive layer,
wherein the first passivation includes a protrusion protruded from the first passivation and away from the substrate, and the conductive layer disposed over the protrusion is exposed from the second passivation.

US Pat. No. 10,431,557

SECURE SEMICONDUCTOR CHIP BY PIEZOELECTRICITY

INTERNATIONAL BUSINESS MA...

1. An apparatus, comprising:a power source; and
a semiconductor chip comprising at least one circuit and a pass transistor that electrically couples the power source and the at least one circuit, wherein the pass transistor comprises a piezoelectric gate comprising a piezoelectric material that produces a voltage that causes the pass transistor to remain in an on-state based on application of a mechanical force to the piezoelectric gate.

US Pat. No. 10,431,556

SEMICONDUCTOR DEVICE INCLUDING SEMICONDUCTOR CHIPS MOUNTED OVER BOTH SURFACES OF SUBSTRATE

Micron Technology, Inc., ...

1. A method of forming a semiconductor device, the method comprising:mounting a first semiconductor chip to a first side of a substrate, the first semiconductor chip including a first short side and a plurality of first electrodes positioned along the first short side;
mounting a second semiconductor chip to a second side of the substrate, the second semiconductor chip having a second short side and a plurality of second electrodes positioned along the second short side, wherein—
the second semiconductor chip is mounted to the substrate such that (a) the first electrodes of the first semiconductor chip are laterally external to the second semiconductor chip, and (b) the second electrodes of the second semiconductor chip are laterally external to the first semiconductor chip,
the second side is opposite the first side, and
an outermost surface of the second semiconductor chip is separated from a surface of the substrate by a first distance;
forming a plurality of conductive posts at the second side of the substrate, wherein an outermost surface of the conductive posts is separated from the surface of the substrate by a second distance greater than the first distance;
sealing at least a portion of the first semiconductor chip with a first sealant; and
sealing at least a portion of the second semiconductor chip and conductive posts with a second sealant.

US Pat. No. 10,431,555

METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE

DISCO CORPORATION, Tokyo...

12. A method of manufacturing a semiconductor package including a semiconductor chip sealed by a sealing synthetic resin, comprising the steps of:preparing a wiring board having a plurality of mounts for mounting semiconductor chips thereon, the mounts being disposed in respective areas demarcated on an upper surface of a wiring board by a plurality of projected dicing lines which cross each other, upstanding encircling walls disposed between said mounts and said projected dicing lines in surrounding relation to said mounts individually, and side-surface shield layers for blocking electromagnetic waves, disposed individually in said upstanding encircling walls in surrounding relation to said mounts and extending in thicknesswise directions of said upstanding encircling walls;
mounting the semiconductor chips individually on said mounts on said wiring hoard;
supplying synthetic resin to spaces surrounded by said upstanding encircling walls over the semiconductor chips mounted on said mounts on said wiring board to seal said semiconductor chips, thereby producing a sealed board;
after said sealed board has been produced, dividing said sealed board along said projected dicing lines into individual semiconductor packages;
after said sealed board has been produced, forming an upper-surface shield layer for blocking electromagnetic waves on upper surfaces of the sealing synthetic resin of said semiconductor packages; and
after said sealed board has been produced, removing the sealing synthetic resin supplied to upper surfaces of said upstanding encircling walls along the side-surface shield layers, thereby exposing tip ends of the side-surface shield layers disposed individually in said upstanding encircling walls.

US Pat. No. 10,431,554

SEMICONDUCTOR DEVICE PACKAGE AND METHOD OF MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising:a carrier;
an electronic component disposed over a top surface of the carrier;
a package body disposed over the top surface of the carrier and covering the electronic component; and
a shield layer, comprising a first magnetically permeable layer disposed over the package body, a first electrically conductive layer disposed over the first magnetically permeable layer, and a second magnetically permeable layer disposed over the first electrically conductive layer,
wherein the first electrically conductive layer is interposed between the first magnetically permeable layer and the second magnetically permeable layer,
wherein a permeability of the first electrically conductive layer is lower than each of a permeability of the first magnetically permeable layer and a permeability of the second magnetically permeable layer.

US Pat. No. 10,431,553

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

LAPIS Semiconductor Co., ...

1. A semiconductor device, comprising:a semiconductor substrate having a primary surface;
an insulator filling a recess in the primary surface;
a semiconductor element disposed on the primary surface, the semiconductor element being sandwiched by the insulator in a plan view; and
an alignment mark overlapping with the insulator in a plan view,
wherein a distance between a bottom surface and a top surface of the insulator that sandwiches the semiconductor element in a plan view is equal to a distance between a bottom surface and a top surface of the insulator overlapping the alignment mark in a plan view.

US Pat. No. 10,431,552

DISPLAY PANEL

HannStar Display Corporat...

1. A display panel having a display area and a non-display area, wherein the display panel comprises:a first substrate, wherein a metal layer is disposed on the first substrate, the metal layer has a plurality of first alignment patterns in the non-display area, and each of the first alignment patterns comprises a first portion and a second portion; and
a second substrate, wherein a light shielding layer is disposed on the second substrate, the light shielding layer has a plurality of second alignment patterns in the non-display area, and each of the second alignment patterns comprises a third portion and a fourth portion,
wherein the second alignment patterns respectively correspond to the first alignment patterns, and the third portions respectively correspond to the first portions, and the fourth portions respectively correspond to the second portions,
wherein there is a first length difference between a length of each of the first portions along a first direction and a length of the corresponding third portion along the first direction, and at least two of the first length differences are different,
wherein there is a second length difference between a length of each of the second portions along a second direction and a length of the corresponding fourth portion along the second direction, and at least two of the second length differences are different,
wherein the light shielding layer has a plurality of openings in the non-display area, and one of the openings encompasses one of the first alignment patterns and one of the second alignment patterns.

US Pat. No. 10,431,551

VISUAL IDENTIFICATION OF SEMICONDUCTOR DIES

TEXAS INSTRUMENTS INCORPO...

1. An electronic device, comprising:a die; and
a package surrounding the die, wherein the electronic device includes a unique visual identification mark, wherein a first character of a set of characters in the unique visual identification mark includes at least one line that connects two adjacent sides of a bond pad of the die, wherein the unique visual identification mark encodes a Cartesian coordinate of the die relative to a reference point on a semiconductor wafer.

US Pat. No. 10,431,549

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Powertech Technology Inc....

1. A semiconductor package, comprising:a stacked-die structure comprising:
a first semiconductor die comprising a first active surface;
a circuit layer disposed on and not extending laterally beyond the first active surface of the first semiconductor die;
a second semiconductor die electrically connected to the first semiconductor die through the circuit layer and comprising a second active surface facing towards the first active surface of the first semiconductor die;
a plurality of conductive features disposed on the circuit layer and the first semiconductor die and electrically connected to the first semiconductor die and the second semiconductor die, wherein
a portion of the plurality of conductive features laterally surrounds the second semiconductor die, and
the plurality of conductive features comprise a first coupling structure disposed between the first semiconductor die and the second semiconductor die and a second coupling structure surrounding the first coupling structure; and
a first encapsulant encapsulating the second semiconductor die and the plurality of conductive features;
a second encapsulant laterally encapsulating the stacked-die structure, wherein a second back surface of the second semiconductor die opposite to the second active surface and a top surface of the second coupling structure are coplanar with a top surface of the first encapsulant and a top surface of the second encapsulant; and
a redistribution layer disposed on the second encapsulant and the staked-die structure, wherein
the redistribution layer is electrically connected to the staked-die structure, and
the second coupling structure is electrically connected to the first semiconductor die and the redistribution layer.

US Pat. No. 10,431,548

ELECTRONIC COMPONENT MODULE AND METHOD OF MANUFACTURING THE SAME

Samsung Electro-Mechanics...

1. An electronic device module, comprising:a first substrate;
electronic devices mounted on the first substrate;
a second substrate coupled to a lower surface of the first substrate, the second substrate comprising a device accommodating portion;
a sealing portion configured to seal an electronic device in the device accommodating portion, and comprising a lower surface sealing portion configured to cover a lower surface of the second substrate; and
an external connection terminal bonded to an electrode pad disposed in a lower surface of the second substrate, wherein side surfaces of the electrode pad are embedded by the sealing portion,
wherein bonding surfaces of the electrode pad and the external connection terminal are disposed on a same plane as a lower surface of the lower surface sealing portion.

US Pat. No. 10,431,547

SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a package substrate;
a first semiconductor chip disposed on the package substrate, the first semiconductor chip including a first surface and a second surface opposite to each other;
a plurality of first connection terminals disposed on the first surface of the first semiconductor chip and in contact with an upper surface of the package substrate;
a second semiconductor chip overlying the second surface of the first semiconductor chip, the second semiconductor chip including a third surface and a fourth surface opposite to each other; and
a plurality of second connection terminals disposed on the third surface of the second semiconductor chip and in contact with the second surface of the first semiconductor chip,
wherein an absolute value between a first area which is a sum of areas in which the plurality of first connection terminals contact the upper surface of the package substrate and a second area which is a sum of areas in which the plurality of second connection terminals contact the second surface of the first semiconductor chip is equal to or less than about 0.3 of the first area.

US Pat. No. 10,431,545

CROSS-CONNECTED MULTI-CHIP MODULES COUPLED BY SILICON BENT-BRIDGE INTERCONNECTS AND METHODS OF ASSEMBLING SAME

Intel IP Corporation, Sa...

1. A multi-chip module, comprising:a central component;
a first component, wherein the first component is coupled to the central component by a first silicon bent-bridge interconnect; and
a subsequent component, wherein the subsequent component is coupled to the central component by a subsequent silicon-bridge interconnect wherein the first silicon bent-bridge interconnect and the subsequent silicon bent-bridge interconnect are torsioned to form an overall helical form factor.

US Pat. No. 10,431,543

DIFFERENTIAL INDUCTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

ELECTRONICS AND TELECOMMU...

1. A differential inductor comprising:first circular parts and second circular parts disposed on a first layer and composing a first spiral shape;
first semi-circular parts and second semi-circular parts disposed on a second layer under the first layer and composing a second spiral shape;
a third semi-circular part disposed on the first layer at least partly within an innermost first circular part of the first circular parts, and
a fourth semi-circular part disposed outside an outermost first circular part of the first circular parts; and
connection means configured to interconnect one of the first and second circular parts and the first to fourth semi-circular parts,
wherein at least portions of the second circular parts are respectively interposed between the first circular parts, and
at least portions of the second semi-circular parts are respectively interposed between the first semi-circular parts.

US Pat. No. 10,431,542

LOW RESISTANCE SEED ENHANCEMENT SPACERS FOR VOIDLESS INTERCONNECT STRUCTURES

International Business Ma...

1. A structure comprising a first interconnect level, the first interconnect level comprising:a first interconnect dielectric material layer containing a first opening having vertical sidewalls and a bottom wall;
a first diffusion barrier liner located in the first opening and lining the vertical sidewalls and the bottom wall of the first opening;
a first seed enhancement spacer directly contacting each inner sidewall of the first diffusion barrier liner and comprising a metal or metal alloy that facilitates movement of an interconnect metal or metal alloy during a reflow anneal process, and is selected from the group consisting of at least one of ruthenium, rhodium, iridium, osmium and cobalt; and
a first interconnect metal or metal alloy structure directly contacting inner sidewalls of each first seed enhancement spacer and directly contacting a horizontal portion of the first diffusion barrier liner that is located on the bottom wall of the first opening.

US Pat. No. 10,431,541

SEMICONDUCTOR DEVICE, LAYOUT PATTERN AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:an interconnect structure, made of conductive material, and comprising a first interconnect portion and a second interconnect portion, wherein the second interconnect portion is connected to a first end of the first interconnect portion, and a width of the second interconnect portion is less than a width of the first interconnect portion; and
a first conductive line, arranged over or below the first interconnect portion and providing an electrical connection between the interconnect structure and an electrical structure, wherein a distance between the first conductive line and the first end is less than a distance between the first conductive line and a second end of the first interconnect portion which is opposite to the first end, and the first conductive line is arranged within the first interconnect portion and formed between the first end and the second end.

US Pat. No. 10,431,540

METAL-OXIDE-METAL CAPACITOR WITH REDUCED PARASITIC CAPACITANCE

QUALCOMM Incorporated, S...

1. A semiconductor device, comprising:a semiconductor substrate;
a capacitor; and
a magnetic material layer between the semiconductor substrate and the capacitor in which the magnetic material layer includes a first surface on the semiconductor substrate and a second surface opposite the first surface, in which a perimeter of the capacitor is within a perimeter of the second surface of the magnetic material layer.

US Pat. No. 10,431,538

TRANSISTOR PACKAGES

Hamilton Sundstrand Corpo...

1. A transistor package comprising:a die case having a top surface and a bottom surface opposite from the top surface;
a source bus tab extending from a first side of the die case, wherein a portion of the source bus tab that extends from the first side is spaced apart from the top surface and the bottom surface in a direction perpendicular to the top surface;
a drain bus tab extending from a second side of the die case opposite from the first side, wherein a portion of the drain bus tab that extends from the second side is spaced apart from the top surface and the bottom surface in the direction perpendicular to the top surface; and
a gate extending from a third side of the die case, wherein the gate includes a first element and a second element, wherein the first element of the gate extends in a first direction from the die case and the second element of the gate extends in a second direction from the first element, wherein the third side of the die case is perpendicular to both the first side of the die case and the second side of the die case, wherein a portion of the gate that extends from the third side is spaced apart from the top surface and the bottom surface in the direction perpendicular to the top surface, and wherein the portions of the source bus tab and the drain bus tab that extend from the die case are spaced apart from an exterior surface of the third side in a direction perpendicular to the exterior surface of the third side.

US Pat. No. 10,431,537

ELECTROMIGRATION RESISTANT AND PROFILE CONSISTENT CONTACT ARRAYS

Intel Corporation, Santa...

1. A package assembly comprising:a substrate extending from a first substrate end to a second substrate end, the substrate includes a plurality of conductive traces;
one or more die coupled along the substrate, at least a first die of the one or more die includes a first array of contacts; and
a plurality of via assemblies interposed between at least the first array of contacts and the plurality of conductive traces, and each via assembly between the first array and the plurality of conductive traces includes:
a base pad in communication with a conductive trace of the plurality of conductive traces, the base pad includes at least a first conductive material,
a cap in communication with a contact of the first array of contacts, the cap includes at least a second conductive material different from the first conductive material, and
an electromigration resistant via within a via passage between the base pad and the cap, the electromigration resistant via is configured to isolate each of the base pad and the cap from intermetallic compound growth and includes a third conductive material different from the first and second conductive materials.

US Pat. No. 10,431,536

INTERPOSER SUBSTRATE AND SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor package comprising:a first semiconductor package including a first substrate and a lower semiconductor chip mounted on the first substrate;
a second semiconductor package stacked on the first semiconductor package and including a second substrate and an upper semiconductor chip mounted on the second substrate; and
an interposer substrate interposed between the first semiconductor package and the second semiconductor package and having a recess recessed from a lower surface facing the lower semiconductor chip,
wherein the interposer substrate includes a dummy wiring layer disposed to be adjacent to the recess in a region overlapped with the lower semiconductor chip, and
wherein the dummy wiring layer is electrically floating.

US Pat. No. 10,431,535

ELECTRONIC PACKAGE AND METHOD FOR FABRICATING THE SAME

Siliconware Precision Ind...

1. A method for fabricating an electronic package, comprising:providing a packaging substrate having a circuit structure and an antenna structure, wherein the circuit structure has a first side and a second side opposite to the first side, the circuit structure comprises at least one dielectric layer and a circuit layer formed on the dielectric layer, and the antenna structure is in contact with the first side of the circuit structure, without an antenna on the second side of the circuit structure; and
disposing at least one electronic component on the second side of the circuit structure and electrically connecting the electronic component to the second side of the circuit structure, wherein the electronic component is a semiconductor chip, wherein the circuit structure further comprises a core layer.

US Pat. No. 10,431,534

PACKAGE WITH SUPPORT STRUCTURE

NXP USA, Inc., Austin, T...

1. A packaged semiconductor device comprising:a package body comprising a semiconductor die;
a redistribution layer (RDL) structure on an active side of the semiconductor die, the RDL structure including a plurality of contact pads on an outer surface of the RDL structure;
a plurality of external connections attached to the plurality of contact pads; and
a support structure comprising an attachment portion and two or more standing members extending from an inner surface of the attachment portion, wherein a back side of the package body is attached to the inner surface of the attachment portion.

US Pat. No. 10,431,533

CIRCUIT BOARD WITH CONSTRAINED SOLDER INTERCONNECT PADS

ATI Technologies ULC, Ma...

1. A method of manufacturing, comprising:forming a solder mask on a circuit board with a first opening having a sidewall;
forming a solder interconnect pad in the first opening; and
whereby the sidewall sets the lateral extent of the solder interconnect pad during the formation of the solder interconnect pad.

US Pat. No. 10,431,532

SEMICONDUCTOR DEVICE WITH NOTCHED MAIN LEAD

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor element;
a main lead on which the semiconductor element is disposed;
a first auxiliary lead and a second auxiliary lead, the first auxiliary lead and the second auxiliary lead each being electrically connected to the semiconductor element;
a first wire electrically connecting the semiconductor element to the first auxiliary lead;
a second wire electrically connecting the semiconductor element to the second auxiliary lead; and
a resin package covering the semiconductor element, the main lead, the first auxiliary lead, and the second auxiliary lead,
wherein the main lead includes a main full thickness part and a main eave part that is smaller in size in a thickness direction of the semiconductor element than the main full thickness part,
the semiconductor element overlaps with each of the main full thickness part and the main eave part in plan view,
the main eave part includes an end face that faces the first auxiliary lead and the second auxiliary lead and that is formed with a notch recessed toward a center of the main lead in plan view,
the first auxiliary lead includes a first auxiliary full thickness part and a first auxiliary eave part that is smaller in size in the thickness direction of the semiconductor element than the first auxiliary full thickness part,
the second auxiliary lead includes a second auxiliary full thickness part and a second auxiliary eave part that is smaller in size in the thickness direction of the semiconductor element than the second auxiliary full thickness part,
the first wire is bonded at a position overlapping with the first auxiliary full thickness part in plan view, and the second wire is bonded at a position overlapping with the second auxiliary full thickness part in plan view,
the first wire has an end bonded to the semiconductor element, the end of the first wire being bonded to the semiconductor element at a position that overlaps with the main full thickness part in plan view,
the main eave part is formed with a pair of main lateral connecting parts that project in mutually opposite directions from a main body of the main eave part, the main lateral connecting parts including respective front faces and respective back faces opposite to the respective front faces, the front faces being flush with the end face of the main eave part, and
the second wire has an end bonded to the semiconductor element, the end of the second wire being bonded to the semiconductor element at a position that overlaps with the main eave part in plan view and is located between the main full thickness part and an imaginary straight line connecting the back faces of the main lateral connecting parts in plan view.

US Pat. No. 10,431,531

SEMICONDUCTOR DIES WITH RECESSES, ASSOCIATED LEADFRAMES, AND ASSOCIATED SYSTEMS AND METHODS

Micron Technology, Inc., ...

1. A method comprising:electrically connecting one or more leadfingers of a leadframe to a semiconductor die;
encapsulating the semiconductor die, a removable tie, and a support paddle with an encapsulant, wherein the removable tie connects the support paddle to the leadframe, and wherein the support paddle is attached to the semiconductor die; and
removing a frame portion of the leadframe and at least portion of the removable tie from the encapsulated semiconductor die and support paddle.

US Pat. No. 10,431,528

SEMICONDUCTOR DEVICE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a semiconductor element; and
a leadframe on which the semiconductor element is mounted,
the leadframe including a die pad on which the semiconductor element is mounted, a first suspension lead, a second suspension lead, and a frame, a main surface of the die pad and a main surface of the frame being located on different planes, the die pad and the frame being connected to each other by the first and second suspension leads,
a first boundary line between the first suspension lead and the die pad running on a straight line different from a second boundary line between the second suspension lead and the die pad,
a third boundary line between the first suspension lead and the frame running on a straight line different from a fourth boundary line between the second suspension lead and the frame.

US Pat. No. 10,431,527

SEMICONDUCTOR DEVICE WITH ISLAND AND ASSOCIATED LEADS

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a resin package having a first corner portion, a second corner portion, a third corner portion and a fourth corner portion, and a package line which connects the first and the second corner portions;
an island having an exposed portion which is partly exposed from the resin package in a bottom view of the resin package, the exposed portion having a first exposed corner portion, a second exposed corner portion, a third exposed corner portion and a fourth exposed corner portion;
a semiconductor chip disposed on a surface of the island;
a first lead disposed in a vicinity of the first corner portion in the bottom view of the resin package, the first lead having a short side and a long side, both of the short side and the long side of the first lead being substantially parallel to a first exposed diagonal line imagined by connecting the first and third corner portions;
a second lead disposed in a vicinity of the second corner portion in the bottom view of the resin package, the second lead having a short side and a long side, both of the short side and the long side of the second lead being substantially parallel to the first exposed diagonal line;
a third lead disposed in a vicinity of the third corner portion in the bottom view of the resin package, the third lead having a short side and a long side, both of the short side and the long side of the third lead being substantially parallel to the first exposed diagonal line; and
a fourth lead disposed in a vicinity of the fourth corner portion in the bottom view of the resin package, the fourth lead having a short side and a long side, both of the short side and the long side of the fourth lead being substantially parallel to the first exposed diagonal line, wherein
a distance between the first exposed corner portion and the package line is longer than a length of the short side of the first lead; and
the distance between the first exposed corner portion and the package line is shorter than a length of the long side of the first lead.

US Pat. No. 10,431,525

BOND-OVER-ACTIVE CIRCUITY GALLIUM NITRIDE DEVICES

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a first layer with a plurality of cells, each cell comprising a drain finger, a source finger and a gate ring; and
a second layer comprising a drain pad and a source pad, the drain pad having a width and a source pad having a width substantially the same as the drain pad;
wherein a width of each drain finger of the first layer is wider than a width of each source finger of the first layer;
wherein each drain pad is coupled to each drain finger through a first contact and the source pad is coupled to each source finger through a second contact, where a width of the first contact is wider than a width of the second contact; and
wherein one of the drain pad or the source pad is positioned over one of the drain finger or the source finger.

US Pat. No. 10,431,524

WATER COOLING MODULE

ASIA VITAL COMPONENTS CO....

1. A water cooling module comprising:a flow-guiding main body provided with a first inlet, a first outlet, and a flow-guiding passage set; the flow-guiding passage set including a plurality of flow-guiding passages, and the first inlet and the first outlet being respectively in fluid communication with one of the flow-guiding passages; and
a pump set including a first pump having a first water inlet and a first water outlet and a second pump having a second water inlet and a second water outlet and in fluid communication with the first pump via one of the flow-guiding passages; the first water inlet and the first water outlet being respectively in fluid communication with one of the flow-guiding passages; and the second water inlet and the second water outlet being respectively in fluid communication with one of the flow-guiding passages.

US Pat. No. 10,431,523

THERMALLY ENHANCED SEMICONDUCTOR PACKAGE HAVING FIELD EFFECT TRANSISTORS WITH BACK-GATE FEATURE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a first buried oxide (BOX) layer;
a non-silicon thermal conductive component, wherein the first BOX layer resides over the non-silicon thermal conductive component;
a first epitaxial layer over the first BOX layer;
a second BOX layer over the first epitaxial layer;
a second epitaxial layer over the second BOX layer and having a source, a drain, and a channel between the source and the drain;
a gate dielectric aligned over the channel; and
a front-gate structure over the gate dielectric, wherein
a back-gate structure is formed in the first epitaxial layer and has a back-gate region aligned below the channel; and
a field effect transistor (FET) is formed by the front-gate structure, the source, the drain, the channel, and the back-gate structure.

US Pat. No. 10,431,522

THERMAL INTERFACE MATERIAL LAYER AND PACKAGE-ON-PACKAGE DEVICE INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor package device having a package-on-package (PoP) structure, the semiconductor package device comprising:a lower semiconductor package including a lower package substrate and a lower semiconductor chip mounted on the lower package substrate;
an upper semiconductor package including an upper package substrate and a first upper semiconductor chip on the upper package substrate;
a connection solder bump between the upper package substrate and the lower package substrate, the connection solder bump electrically connecting the upper semiconductor package and the lower semiconductor package;
a thermal conductive material between the lower semiconductor package and the upper semiconductor package, the thermal conductive material including a resin layer and filler particles distributed in the resin layer, the filler particles include a plurality of filler particles including at least two layers; and
a lower mold layer covering a sidewall of the lower semiconductor chip, and not covering a top surface of the lower semiconductor chip.

US Pat. No. 10,431,521

INTEGRATED ELECTRONIC COMPONENTS AND METHODS OF FORMATION THEREOF

CUBIC CORPORATION, San D...

1. A method of forming an integrated electronic component, comprising:providing an electronic device;
disposing a plurality of layers over a substrate, wherein the layers comprise one or more of dielectric, conductive and sacrificial materials; and
forming from the layers a microstructure comprising: a waveguide section comprising a plurality of waveguides, the waveguides each having a non-solid core volume within an outer conductor surrounding the core volume; and a transition structure coupling the waveguides to the electronic device,
wherein the waveguides each comprise a center conductor disposed in and surrounded by the outer conductor with the non-solid volume disposed between the center conductor and the outer conductor, and wherein the transition structure comprises a post mechanically coupling the substrate to the center conductor.

US Pat. No. 10,431,520

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device, comprising:a package portion;
a metal base which is housed in the package portion and is exposed at a lower surface of the package portion;
a semiconductor chip which is housed in the package portion and is placed above the metal base; and
a frame portion provided to surround a penetration space penetrating the package portion, wherein
a lower end of the frame portion protrudes below the lower surface of the package portion and a lower surface of the metal base, and
the frame portion has a wider portion outside the package portion, the wider portion having a greater width than a portion inserted in the penetration space of the package portion.

US Pat. No. 10,431,519

CARRIER REMOVAL BY USE OF MULTILAYER FOIL

Micron Technology, Inc., ...

1. A semiconductor device assembly comprising:a semiconductor device having a first side and a second side;
a substrate;
a foil layer attached to a surface of the substrate;
a release layer attached to the foil layer, the foil layer positioned between the release layer and the surface of the substrate; and
a layer of adhesive configured to connect the semiconductor device to the substrate, the layer of adhesive positioned between the first side of the semiconductor device and the release layer, wherein upon the application of an energy pulse to the foil layer, the foil layer is configured to generate heat to cause the release layer to selectively release the substrate from the adhesive layer, wherein the foil layer is a multilayer foil comprised of alternating layers of two materials.