US Pat. No. 10,366,973

LAYOUT MODIFICATION METHOD FOR EXPOSURE MANUFACTURING PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A layout modification method for fabricating an integrated circuit, comprising:calculating uniformity of critical dimensions of a first portion and a second portion in a patterned layer using a layout for an exposure manufacturing process to produce a semiconductor device in the integrated circuit, wherein the second portion is adjacent to the first portion, and a width of the second portion equals a penumbra size of the exposure manufacturing process, wherein the penumbra size is utilized to indicate which area of the patterned layer is affected by light leakage exposure from another exposure manufacturing process;
retrieving an adjusting parameter for modifying the layout;
determining a compensation amount based on the adjusting parameter and the uniformity of the critical dimensions; and
compensating the critical dimension of the second portion of the patterned layer by utilizing the compensation amount to generate a modified layout.

US Pat. No. 10,366,972

MICROELECTRONICS PACKAGE WITH SELF-ALIGNED STACKED-DIE ASSEMBLY

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a precursor package including a module substrate, a first flip chip die attached to an upper surface of the module substrate, and a first mold compound over and surrounding the first flip chip die, wherein:
the first flip chip die comprises a first device layer, a plurality of first interconnects extending from a lower surface of the first device layer to the upper surface of the module substrate, a first dielectric layer over an upper surface of the first device layer, and a first silicon substrate over the first dielectric layer; and
the first device layer includes a first coupling component that is embedded in the first device layer;
thinning down the first mold compound to expose a backside of the first silicon substrate of the first flip chip die;
removing substantially the first silicon substrate to form a first opening within the first mold compound and provide a first thinned flip chip die with an upper surface, wherein:
the first mold compound provides vertical walls of the first opening, which are aligned with edges of the first thinned flip chip die in both X-direction and Y-direction;
the X-direction and the Y-direction are parallel to the upper surface of the module substrate, and the X-direction and the Y-direction are orthogonal to each other; and
the upper surface of the first thinned flip chip die is exposed at a bottom of the first opening; and
placing a second die in the first opening to stack with the first thinned flip chip die, wherein:
the second die comprises a second coupling component embedded therein; and
the second coupling component is mirrored to the first coupling component.

US Pat. No. 10,366,970

3D SEMICONDUCTOR DEVICE AND STRUCTURE

MONOLITHIC 3D INC., San ...

1. A 3D semiconductor device, the device comprising:a first single crystal layer comprising a plurality of first transistors;
at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates;
a plurality of second transistors atop said first single crystal layer;
a plurality of third transistors above said plurality of second transistors;
a top metal layer above said third transistors;
first circuits below said first single crystal layer;
second circuits above said top metal layer;
a first set of connections below said at least one metal layer,
wherein said first set of connections connects said first transistors to said first circuits;
a second set of connections above said top metal layer,
wherein said second set of connections connects said first transistors to said second circuits, and
wherein said first set of connections comprises a through silicon via (TSV); and
a first memory array; and
a second memory array,
wherein said first memory array comprises a first portion of said plurality of second transistors and said second memory array comprises a section portion said plurality of third transistors,
wherein each of said plurality of second transistors comprises a source, a channel and a drain,
wherein said source, said channel, and said drain comprise the same type dopant,
wherein at least one of said plurality of second transistors comprises a polysilicon channel, and
wherein said plurality of second transistors are self-aligned to said plurality of third transistors, having been processed following the same lithography step.

US Pat. No. 10,366,969

INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION

STMicroelectronics S.r.l,...

1. A test system, comprising:a test chuck having a top surface configured to receive a wafer;
wherein the wafer includes a plurality of integrated circuit devices, and wherein each integrated circuit device comprises:
a semiconductor body region;
an insulating layer disposed adjacent a top surface of the semiconductor body region;
a device winding within the insulating layer; and
a magnetic region disposed within at least the semiconductor body region and aligned with the device winding; and
a layer of magnetic material extending between the top surface of the chuck and a bottom surface of the wafer.

US Pat. No. 10,366,968

INTERCONNECT STRUCTURE FOR A MICROELECTRONIC DEVICE

Intel IP Corporation, Sa...

1. A microelectronic device, comprising:a first semiconductor die having a first group of contacts at a first pitch relative to one another, and a second group of contacts at a second pitch relative to one another, the second pitch being less than the first pitch, wherein at least one of the first and second groups of contacts includes an array of contacts extending along both X and Y dimensions of the first semiconductor die;
a molded component extending over the first semiconductor die;
a redistribution layer having a first side coupled to the first semiconductor die, the redistribution layer having first redistribution layer contacts engaging contacts of the first group of contacts, wherein the redistribution layer includes a dielectric layer formed on both the first semiconductor die and the molded component, and further includes conductive structures supported by the dielectric layer;
a second semiconductor die on the opposite side of the redistribution layer from the first semiconductor die, the second semiconductor device having a third group of contacts at the second pitch, the contacts of the third group of contacts coupled directly to respective contacts of the second group of contacts by direct attachments of respective second and third contacts, of which contacts of at least one of the second and third groups of contacts are in the form of metallic pillars that extend through the redistribution layer to engage the contacts of the other group, and without making electrical connection with the redistribution layer;
and
wherein the second semiconductor die is secured on the opposite side of the redistribution layer from the first semiconductor die, and placed within a vertical dimension established by contact balls on that same opposite side of the redistribution layer from the first semiconductor die, and wherein the contact balls are configured for attaching the microelectronic device to an additional structure.

US Pat. No. 10,366,967

APPARATUS AND METHOD FOR MULTI-DIE INTERCONNECTION

Cerebras Systems Inc., L...

1. A semiconductor having multiple, interconnected die, the semiconductor comprising:a substrate comprising a semiconductor wafer;
a plurality of die formed with the substrate;
a circuit layer formed at each of the plurality of die;
a plurality of inter-die connections that communicatively connect disparate die formed with the substrate, wherein each of the plurality of inter-die connections extends between each pair of adjacent die of the plurality of die, and wherein each of the plurality of die comprises a protective barrier comprising a seal ring that encompasses a periphery of each of the plurality of die,
wherein the plurality of die includes:
(i) a first subset of interior die defining an interior of the substrate, wherein the first subset of interior die has inter-die connections with adjacent die along all sides of the first subset of die;
(ii) a second subset of peripheral die defining a periphery of the substrate, wherein at least one side of each of the second subset of exterior die are formed without inter-die connections.

US Pat. No. 10,366,966

METHOD OF MANUFACTURING INTEGRATED FAN-OUT PACKAGE

Taiwan Semiconductor Manu...

1. A method of manufacturing an integrated fan-out (InFO) package, comprising:forming a package array;
sequentially forming a dielectric layer and a core material layer on a first carrier;
removing a portion of the core material layer to form a core layer having a plurality of cavities;
attaching the first carrier, the dielectric layer, and the core layer onto the package array such that the core layer is located between the dielectric layer and the package array;
removing the first carrier from the dielectric layer; and
forming a plurality of first conductive patches on the dielectric layer above the plurality of cavities.

US Pat. No. 10,366,965

CHIP BONDING APPARATUS, CHIP BONDING METHOD AND A CHIP PACKAGE STRUCTURE

Industrial Technology Res...

1. A chip bonding apparatus for bonding a chip and a redistribution structure with each other, the chip bonding apparatus comprising:a pick and place module, suitable for picking up and placing the chip; and
an alignment module, moveably connected to the pick and place module, and the alignment module comprising at least one alignment protrusion, wherein the at least one alignment protrusion extends towards at least one alignment socket included in the redistribution structure, and the at least one alignment socket is configured in a non-point symmetry manner.

US Pat. No. 10,366,964

SEMICONDUCTOR DEVICE HAVING SWITCHING ELEMENTS TO PREVENT OVERCURRENT DAMAGE

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a first semiconductor switching element including a first gate pad, a plurality of first emitter pads, and a first collector pad;
a first wire for connecting adjacent pads out of the plurality of first emitter pads;
a first output wire for connecting one of the plurality of first emitter pads to an output;
a first controller for applying a gate voltage to the first gate pad;
a first emitter wire that is directly connected to a first extraction pad which is any one pad of the plurality of first emitter pads, and is directly connected to an emitter terminal attached to a case to give a ground potential of the first controller; and
a second semiconductor switching element including a second gate pad, a second emitter pad and a second collector pad connected to the output.

US Pat. No. 10,366,963

NOBLE METAL PASTE FOR BONDING OF SEMICONDUCTOR ELEMENT

TANAKA KIKINZOKU KOGYO K....

1. A precious metal paste for bonding a semiconductor element, the paste consisting essentially of either a precious metal powder and an organic solvent, or a precious metal powder, an organic solvent and surfactant, and not containing any resin, wherein the precious metal powder has a purity of 99.9 mass % or more and an average particle diameter of 0.1 to 0.5 ?m, and the organic solvent has a boiling point of 200 to 350° C., wherein the organic solvent is made of one organic solvent only, which one organic solvent is a branched-chain aliphatic dihydroxy alcohol having a carbon number of 5 to 20, and which branched-chain aliphatic dihydroxy alcohol consists of 1,5-pentanediol or derivatives thereof, and wherein the precious metal paste has a thixotropy index (TI) value of 6.1 or more, of a viscosity at a shear rate of 4/s with respect to a viscosity at a shear rate of 40/s at 23° C. by means of a rotational viscometer, and a viscosity at a shear rate of 4/s which is 100 to 1000 Pa·s.

US Pat. No. 10,366,962

THREE DIMENSIONAL DEVICE INTEGRATION METHOD AND INTEGRATED DEVICE

Invensas Bonding Technolo...

1. An integration method, comprising:preparing a first element having a first layer of bondable material for direct bonding;
preparing a second element for direct bonding;
polishing the first layer of bondable material;
bringing into direct contact the first layer of bondable material with the second element after polishing the first layer of bondable material;
directly bonding the first layer of bondable material to the second element with a covalent bond at room temperature; and
after the bonding, removing a portion of the first element by one of polishing and grinding to leave a remaining portion of the first element.

US Pat. No. 10,366,961

IMAGE SENSORS WITH DEEP SILICON ETCH AND RELATED METHODS

SEMICONDUCTOR COMPONENTS ...

1. An image sensor comprising:a silicon layer comprising a first side and a second side opposite the first side;
an opening extending into the silicon layer from the first side of the silicon layer toward the second side;
a via extending into the silicon layer from the second side of the silicon layer; and
a conductive pad within the opening, the conductive pad coupled to the via;
wherein the opening comprises a fill material;
wherein at least a portion of the fill material forms a plane that is substantially parallel with a plane formed by the first side of the silicon layer; and
wherein the conductive pad is exposed through an opening in the fill material.

US Pat. No. 10,366,960

FAN-OUT PACKAGE AND METHODS OF FORMING THEREOF

Taiwan Semiconductor Manu...

1. A structure comprising:a chip comprising a substrate and a contact pad on the substrate;
a molding compound laterally encapsulating the chip, none of the molding compound being vertically aligned with the chip;
a first dielectric layer overlying the molding compound and the chip;
a first metallization layer having a first portion and a second portion, the first portion of the first metallization layer overlying the first dielectric layer, the second portion of the first metallization layer extending through the first dielectric layer electrically coupled to the contact pad, wherein the second portion of the first metallization layer has a flat top;
a second dielectric layer overlying the first metallization layer and the first dielectric layer; and
a second metallization layer having a first portion and second portion, the first portion of the second metallization layer overlying the second dielectric layer, the second portion of the second metallization layer extending through the second dielectric layer electrically coupled to the first metallization layer, the second portion of the second metallization layer being vertically aligned with the second portion of the first metallization layer.

US Pat. No. 10,366,959

INTEGRATED FAN-OUT STRUCTURE AND METHOD OF FORMING

Taiwan Semiconductor Manu...

1. A device, comprising:a first die, the first die comprising a first substrate and a first dielectric layer overlying the first substrate, an edge of the first substrate being offset from an edge of the first dielectric layer;
a second die positioned next to the first die, the second die comprising a second substrate and a second dielectric layer overlying the second substrate, an edge of the second substrate being offset from an edge of the second dielectric layer;
a redistribution layer overlying the first die and the second die, the redistribution layer comprising a conductor that continuously extends, in a plan view, between a sidewall of the first die and a sidewall of the second die, wherein the conductor is routed across the sidewall of the first die at a first angle, wherein the first angle is measured in the plan view and with respect to a shortest line between the first die and the second die, and the first angle being greater than 0.

US Pat. No. 10,366,958

WIRE BONDING BETWEEN ISOLATION CAPACITORS FOR MULTICHIP MODULES

TEXAS INSTRUMENTS INCORPO...

1. A packaged multichip device having reinforced isolation, comprising:a first integrated circuit (IC) die on a first die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, at least a first isolation capacitor (first ISO cap) utilizing said top metal layer as a first top plate having a top dielectric layer thereon with a top plate dielectric aperture and one of said plurality of lower metal layers as its first bottom plate;
a second IC die on a second die pad including functional circuitry with a metal stack thereon including a top metal layer and a plurality of lower metal layers, including at least a second ISO cap utilizing said top metal layer as a second top plate having a top dielectric layer thereon having a top plate dielectric aperture and one of said plurality of lower metal layers as its second bottom plate;
a first end of a bondwire coupled within said top plate dielectric aperture on said first top plate, and
a second end of said bondwire coupled within said top plate dielectric aperture on said second top plate,
wherein said second end of said bondwire includes a stitch bond including a wire approach angle that is not normal to said second top plate, and
wherein said stitch bond is asymmetrically placed so that a center of said stitch bond is positioned at least 5% further from an outer edge of said second top plate on a bondwire crossover side as compared to a distance of said center of said stitch bond from a side opposite to said bondwire crossover side.

US Pat. No. 10,366,957

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a metal member;
a first semiconductor chip that is disposed on a surface of the metal member and has a first metal layer at a surface facing the metal member;
a second semiconductor chip that is formed of a material having larger Young's modulus than the first semiconductor chip and is disposed at a position different from the first semiconductor chip on the surface of the metal member, the second semiconductor chip having a second metal layer at a surface facing the metal member;
a first solder that is disposed between the metal member and the first metal layer of the first semiconductor chip and connects the metal member and the first metal layer; and
a second solder that is disposed between the metal member and the second metal layer of the second semiconductor chip and connects the metal member and the second metal layer, wherein
a thickness of the second solder is greater than a maximum thickness of the first solder at least at a portion of the second solder.

US Pat. No. 10,366,956

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:an integrated circuit;
at least one outer seal ring surrounding the integrated circuit, wherein the at least one outer seal ring comprises a plurality of metal layers in a stacked configuration, and the plurality of the metal layers are closed loops;
a dielectric layer having first and second portions; and
at least one inner seal ring disposed between the at least one outer seal ring and the integrated circuit and separated from the at least one outer seal ring, wherein the at least one inner seal ring comprises a plurality of metal layers in a stacked configuration along a first direction and has first and second seal portions separated from each other by the first portion of the dielectric layer along a second direction transverse to the first direction and third and fourth seal portions spaced apart from the first and second seal portions, separated from each other by the second portion of the dielectric layer, and in the same layer as the first and second seal portions.

US Pat. No. 10,366,955

SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE STRUCTURE HAVING NUCLEATION STRUCTURE AND METHOD OF FORMING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:an insulating structure having an opening;
a conductive pattern disposed in the opening;
a barrier structure extending between the conductive pattern and side walls of the opening, the barrier structure covering a bottom surface of the conductive pattern; and
a nucleation structure disposed between the conductive pattern and the barrier structure,
wherein the nucleation structure comprises a first nucleation layer that contacts the barrier structure, and a second nucleation layer that is spaced apart from the barrier structure and contacts lateral and bottom surfaces of the conductive pattern, and
a top end portion of the second nucleation layer is above a top end portion of the first nucleation layer.

US Pat. No. 10,366,954

STRUCTURE AND METHOD FOR FLEXIBLE POWER STAPLE INSERTION

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:receiving a design for an integrated circuit chip;
generating a layout design for placement of integrated circuit devices on the integrated circuit chip, wherein the layout design includes a power distribution structure for the integrated circuit devices, the power distribution structure comprising:
a first conductor in a first plane connecting a first integrated circuit device to a power source, wherein the first conductor includes a first axis defining a first side and a second side of the first conductor, the first axis being in approximately the middle of the first conductor, and
a second conductor in a second plane parallel to the first plane, wherein the second conductor is connected to the first conductor by first vias extending in a second direction perpendicular to the first plane, and wherein the first vias contact the first conductor in only the first side of the first conductor, the second conductor being perpendicular to the first conductor;
performing a placement process to place the first integrated circuit device on the integrated circuit chip based upon the layout design;
creating a modified layout design by adding a cut in the second conductor, wherein the cut is parallel to the first conductor and located in an area of the second side of the first conductor; and
fabricating an integrated circuit chip based on the modified layout design.

US Pat. No. 10,366,953

REDISTRIBUTION LAYER STRUCTURES FOR INTEGRATED CIRCUIT PACKAGE

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) package comprising:an IC die having a conductive via, wherein the conductive via has a peripheral edge; and
a routing structure having a conductive structure, coupled to the conductive via, comprising:
a cap region overlapping an area of the conductive via;
a routing region having a first width from a top-down view; and
an intermediate region having a second width from the top-down view along the peripheral edge of the conductive via and arranged to couple the cap region to the routing region, the second width being greater than the first width.

US Pat. No. 10,366,952

SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device, comprising:forming a porous dielectric layer including a recessed portion;
forming a conductive layer in the recessed portion of the porous dielectric layer;
forming a conformal cap layer on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the conformal cap layer; and
performing a heat treatment to burn out a pore filler of the porous dielectric layer through the exposed upper surface of the porous dielectric layer and the gap in the conformal cap layer.

US Pat. No. 10,366,951

LOCALIZED HIGH DENSITY SUBSTRATE ROUTING

Intel Corporation, Santa...

1. A method of forming an interconnect element to connect between two dies, the method comprising:forming a first layer of a medium including one of glass, ceramic, or silicon;
forming first high density interconnect routing in the first layer;
forming a second layer of the medium in contact with the first layer;
forming second high density interconnect routing in the second layer, the second high density interconnect routing electrically connected to the first high density interconnect routing;
forming a third layer of the medium, the second layer situated between the first and third layers;
forming third high density interconnect routing in the third layer, wherein the interconnect element includes only three layers with high density interconnect routing;
forming first and second pads at a first surface of the medium in electrical contact with the third high density interconnect routing, the first and second pads at least partially exposed at a first surface of the medium; and
electrically connecting first and second dies to the first and second pads, respectively, and the first and second dies to low density interconnect routing of a substrate to which the first die is electrically coupled.

US Pat. No. 10,366,950

BOTTOM-UP SELECTIVE DIELECTRIC CROSS-LINKING TO PREVENT VIA LANDING SHORTS

Intel Corporation, Santa...

1. An interconnect structure comprising:a first interlayer dielectric (ILD);
a first interconnect line extending into the first ILD;
a second interconnect line extending into the first ILD;
a second ILD positioned over the first interconnect line and the second interconnect line;
a via extending through the second ILD and electrically coupled to the first interconnect line, wherein a portion of a bottom surface of the via is positioned over the second interconnect line; and
an isolation layer positioned between the bottom surface of the via and a top surface of the second interconnect line.

US Pat. No. 10,366,949

WIRING SUBSTRATE AND SEMICONDUCTOR DEVICE

Shinko Electric Industrie...

1. A wiring substrate comprising:a first wiring structure; and
a second wiring structure stacked on the first wiring structure,
wherein the first wiring structure includes:
a first wiring layer;
a first insulating layer covering the first wiring layer, wherein the first insulating layer includes a first through hole that extends through the first insulating layer in a thickness-wise direction to expose an upper surface of the first wiring layer; and
a via wiring including an upper end surface exposed from an upper surface of the first insulating layer, wherein the first through hole of the first insulating layer is filled with the via wiring,
the second wiring structure includes:
a protective film formed on the upper surface of the first insulating layer;
a second wiring layer including a first wiring pattern, wherein the first wiring pattern is formed on the upper surface of the first insulating layer and the upper end surface of the via wiring; and
a second insulating layer stacked on the upper surface of the first insulating layer and covering the second wiring layer,
the second wiring structure has a wiring density that is higher than a wiring density of the first wiring structure, and
the first wiring pattern of the second wiring layer comprises:
a first metal barrier film formed on the upper surface of the first insulating layer and the upper end surface of the via wiring;
a first metal film formed on the first metal barrier film; and
a first metal layer formed on the first metal film,
wherein the first metal layer includes an entirely roughened side surface and an entirely smooth side surface, and includes an upper surface comprising a partially roughened upper surface and a partially smooth upper surface,
the protective film is formed on the entirely smooth side surface of the first metal layer and the partially smooth upper surface of the first metal layer, and the partially roughened upper surface is partially attached to the second insulating layer,
each of the roughened side surface and the roughened upper surface of the first metal layer has a surface roughness that is smaller than a surface roughness of the first wiring layer, and
the first metal barrier film includes a peripheral portion that projects toward an outer side from the roughened side surface of the first metal layer.

US Pat. No. 10,366,948

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip;
a plurality of leads, disposed in a periphery of the semiconductor chip; and
a sealing resin, sealing the semiconductor chip and the leads such that lower surfaces and outer end surfaces of the leads, at sides opposite the semiconductor chip, are exposed;
wherein
lead plating layers arranged to improve solder wettability are formed on the lower surfaces and the outer end surfaces of the leads, and
front surfaces of the lower surfaces of the plurality of leads excluding the lead plating layers are at higher height positions than a lower surface of the sealing resin.

US Pat. No. 10,366,947

FLAT NO-LEAD PACKAGES WITH ELECTROPLATED EDGES

TEXAS INSTRUMENTS INCORPO...

1. A method of forming packaged semiconductor devices, comprising:providing a lead frame sheet including a plurality of joined flat no-lead lead frames (lead frames) each having a semiconductor die including bond pads thereon mounted on a die pad of said lead frames with bond wires between said bond pads and terminals of said lead frames, and plastic encapsulation except on a back side of said lead frame sheet to expose a back side of said die pad to provide an exposed thermal die pad and to expose a back side of said terminals;
partial sawing in saw lanes beginning from said back side of said lead frame sheet through said terminals ending with saw lines having a line width terminating within said plastic encapsulation to provide exposed side walls of said terminals and exposed side walls of said plastic encapsulation;
shorting together said exposed thermal pad and said exposed back side of the terminals to form electrically interconnected metal surfaces;
electroplating said electrically interconnected metal surfaces with a stack of plating layers on said back side and on said exposed side walls of said terminals, said stack of plating layers includes nickel, palladium, and gold;
decoupling said interconnected surfaces, and
a second sawing in said saw lanes to finish sawing through said plastic encapsulation to provide singulation to form a plurality of said packaged semiconductor devices.

US Pat. No. 10,366,945

LEAD FRAME, LEAD FRAME WITH RESIN ATTACHED THERETO, RESIN PACKAGE, LIGHT EMITTING DEVICE, AND METHOD FOR MANUFACTURING RESIN PACKAGE

NICHIA CORPORATION, Anan...

1. A lead frame comprising:a plurality of first leads, and a plurality of second leads, wherein the first and second leads are arranged within a plurality of rectangular unit regions, wherein each of the plurality of unit region contains at least one of the first leads and at least one of the second leads, and wherein the plurality of unit regions includes a first unit region and a second unit region that are adjacent to each other in a first direction;
a plurality of coupling portions and a plurality of extending portions, wherein at least one of the coupling portions and at least one of the extending portions couple the first and second leads in the first unit region to the first and second leads in the second unit region, and wherein all of the plurality of coupling portions and the plurality of extending portions extend along the first direction and/or a second direction that is orthogonal to the first direction;
wherein, in a top plan view of the lead frame, in each of the plurality of unit regions, the coupling portions and extending portions do not extend directly along and over at least one of four sides of the unit region, and
wherein the plurality of coupling portions and the plurality of extending portions are disposed such that upper surfaces of the plurality of coupling portions and upper surfaces of the plurality of extending portions are coplanar.

US Pat. No. 10,366,944

METHODS AND APPARATUS FOR SEMICONDUCTOR DEVICE HAVING BI-MATERIAL DIE ATTACH LAYER

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:a semiconductor die having a first surface with bond pads and an opposite second surface attached to a substrate by an adhesive layer covering at least a portion of a surface area of the second surface;
the adhesive layer including first zones composed of a first polymeric compound and adding up to a first portion of the surface area, and second zones composed of a second polymeric compound and adding up to a second portion of the surface area, the first zones and the second zones being contiguous; and
the first polymeric compound having a first modulus and the second polymeric compound having a second modulus greater than the first modulus.

US Pat. No. 10,366,943

PACKAGED ELECTRONIC DEVICE HAVING STEPPED CONDUCTIVE STRUCTURE AND RELATED METHODS

Amkor Technology, Inc., ...

1. An electronic package comprising:a substrate having a first conductive element, wherein:
the first conductive element comprises a first stepped portion disposed at a first end of the first conductive element; and
the first stepped portion comprises:
a first groove extending inward from a lower surface of the first conductive element; and
a second groove extending further inward from the first groove towards an upper surface of the first conductive element;
an electronic component coupled to the first conductive element; and
an encapsulant encapsulating the electronic component and a portion of the substrate such that the first stepped portion is exposed outside a first exterior side surface of the encapsulant,wherein:the first conductive element has a first width
the first groove has a second width; and
the second groove has a third width less than the second width.

US Pat. No. 10,366,942

SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a resin;
a semiconductor chip which is sealed with the resin and includes a plurality of first pads and a plurality of second pads;
a plurality of first external leads which are arranged outside of the resin;
a plurality of second external leads which are arranged outside of the resin;
a plurality of first internal leads, including a first set, a second set and a center lead, the first set and the second set being arranged on respective sides of the center lead, which are sealed with the resin and are connected with the plurality of first external leads respectively, each of the first set and the second set including a first section, a second section, and a third section, wherein
the plurality of first sections extend in a first direction in a first plane of the semiconductor chip, are arranged spaced apart in a second direction perpendicular to the first direction, and underlay the semiconductor chip,
the center lead includes a first portion and a second portion directly connected the first portion, at least the second portion extending in the first direction,
the plurality of second sections are connected with the plurality of first sections respectively, the plurality of second sections bend towards the second portion of the center lead, and
the plurality of third sections are connected with the plurality of second sections respectively;
a plurality of second internal leads which are sealed with the resin, are connected with the plurality of second external leads respectively, and include a plurality of fourth sections respectively, wherein the plurality of fourth sections bend towards the plurality of third sections;
a plurality of first bonding wires which are sealed with the resin, electrically connect the plurality of first pads and the plurality of third sections respectively; and
a plurality of second bonding wires which are sealed with the resin, electrically connect the plurality of second pads and the plurality of fourth sections respectively.

US Pat. No. 10,366,941

PACKAGE STRUCTURE

Winbond Electronics Corp....

1. A package structure, comprising:a substrate;
a metal pad located on the substrate;
a first polymer layer located on the substrate, the first polymer layer having a first opening, the first opening exposing a portion of a top surface of the metal pad;
a second polymer layer located on the first polymer layer, the second polymer layer having a second opening, the second opening exposing the portion of the top surface of the metal pad and a first top surface of the first polymer layer;
a redistribution layer (RDL), covering the portion of the top surface of the metal pad and extending onto a portion of the first top surface of the first polymer layer and the second polymer layer; and
a third polymer layer, located on the RDL, the third polymer layer having a third opening, the third opening exposing a portion of a top surface of the RDL, wherein the third opening corresponds to the metal pad, and the third opening is greater than the first opening and smaller than the second opening.

US Pat. No. 10,366,937

COOLING DEVICE, METHOD FOR PRODUCING A COOLING DEVICE AND POWER CIRCUIT

CPT Group GmbH, Hannover...

1. A method for producing a cooling device, the method comprising:stacking aluminum sheets to form an aluminum heat sink, at least one of the aluminum sheets having cutouts for forming a cooling channel;
connecting the stacked aluminum sheets to one another to form the aluminum heat sink; and
arranging a solder mediation layer on at least one of the aluminum sheets, which forms an outer side of the aluminum heat sink, either by direct cohesive application on at least one of the aluminum sheets before or after the steps of stacking and connecting, or by soldering, wherein a soldering compound is situated between the solder mediation layer and the aluminum sheet, wherein the soldering compound situated between the solder mediation layer and the aluminum sheet is melted by the heating in order to form a solder layer between the solder mediation layer and the aluminum heat sink.

US Pat. No. 10,366,936

ELECTRONIC DEVICE COMPONENT WITH AN INTEGRAL DIAMOND HEAT SPREADER

Element Six Technologies ...

1. An electronic device component comprising:a support frame comprising a top surface, a bottom surface, and an opening extending between the top surface and bottom surface of the support frame;
a diamond heat spreader comprising a wafer of synthetic diamond material having a top face, a bottom face, wherein the diamond heat spreader is bonded to the support frame so that the diamond heat spreader extends across the opening in the support frame; and
one or more first semiconductor components mounted on, and bonded to, the top face of the diamond heat spreader,
wherein the support frame is formed of an electrically insulating ceramic material to which the diamond heat spreader is bonded,
wherein one or more electrical connections are mounted on the electrically insulating ceramic support frame and configured to electrically connect to the one or more first semiconductor components,
wherein the one or more electrical connections are formed of a metallization layer which is disposed on the top surface of the support frame and on the top face of the diamond heat spreader and which is patterned to form one or more conduction tracks on the top surface of the support frame and diamond heat spreader,
wherein one or more second semiconductor components are mounted on, and bonded to, the top surface of the support frame, and
wherein the top face of the diamond heat spreader is co-planar with the top surface of the support frame to within 500 ?m.

US Pat. No. 10,366,935

ARCHITECTURE OF DRIVE UNIT EMPLOYING GALLIUM NITRIDE SWITCHES

OTIS ELEVATOR COMPANY, F...

1. A drive unit for driving a motor, the drive unit comprising:a printed circuit board;
a first gallium nitride switch having a gate terminal, drain terminal and source terminal, the first gallium nitride switch mounted to the printed circuit board;
a second gallium nitride switch having a gate terminal, drain terminal and source terminal, the second gallium nitride switch mounted to the printed circuit board;
a gate driver generating a turn-off drive signal to turn off the first gallium nitride switch and turn off the second gallium nitride switch;
a first turn-off trace on the printed circuit board, the first turn-off trace directing the turn-off drive signal to the gate terminal of the first gallium nitride switch; and
a second turn-off trace on the printed circuit board, the second turn-off trace directing the turn-off drive signal to the gate terminal of the second gallium nitride switch;
wherein an impedance of the first turn-off trace is substantially equal to an impedance of the second turn-off trace;
a first turn-on trace on the printed circuit board, the first turn-on trace directing the turn-on drive signal to the gate terminal of the first gallium nitride switch;
a second turn-on trace on the printed circuit board, the second turn-on trace directing the turn-on drive signal to the gate terminal of the second gallium nitride switch;
wherein an impedance of the first turn-on trace is substantially equal to an impedance of the second turn-on trace;
wherein the gate driver generates a turn-on drive signal to turn on the first gallium nitride switch and turn on the second gallium nitride switch;
a via positioned in one of the first turn-off trace and the second turn-off trace, the via extending through the printed circuit board to render the impedance of the first turn-off trace substantially equal to the impedance of the second turn-off trace.

US Pat. No. 10,366,934

FACE DOWN DUAL SIDED CHIP SCALE MEMORY PACKAGE

Micron Technology, Inc., ...

1. A semiconductor device comprising:an interposer having a first side and a second side opposite of the first side;
a first die having a perimeter located on the first side of the interposer, wherein the first die comprises an active side opposite a back side, the active side of the first die facing the first side of the interposer;
a first window through the interposer, wherein at least a portion of the first window extends outside of the perimeter of the first die;
at least one bond wire electrically connecting the first die to the second side of the interposer through the first window;
a second die having a perimeter located on the second side of the interposer;
a second window through the interposer, wherein at least a portion of the second window extends outside of the perimeter of the second die; and
at least one bond wire electrically connecting the second die to the first side of the interposer through the second window.

US Pat. No. 10,366,933

CASE HAVING TERMINAL INSERTION PORTION FOR AN EXTERNAL CONNECTION TERMINAL

Mitsubishi Electric Corpo...

1. A semiconductor device comprising:a base plate;
an insulating substrate provided on an upper surface of said base plate;
a conductive pattern provided on an upper surface of said insulating substrate;
a semiconductor chip mounted on an upper surface of said conductive pattern;
a case surrounding said base plate, said insulating substrate, said conductive pattern, and said semiconductor chip, said case having a terminal insertion portion, which is L-shaped in a plan view, in a peripheral wall portion thereof;
a sealing resin sealing an interior of said case; and
a plate-like external connection terminal provided to said case, including:
a body portion formed as a plate;
a connection portion bent in a direction from one end of said body portion and connected to said conductive pattern,
a terminal portion bent in the direction from the other end of said body, such that the body portion and the terminal portion are L-shaped in plan view; and
an external connection portion configured to connect to an external control board, wherein
said terminal insertion portion enables insertion of said terminal portion of said external connection terminal to thereby enable said connection of said external connection terminal to said conductive pattern, and
with said terminal portion of said external connection terminal being inserted in said terminal insertion portion of said case, a portion of said external connection terminal other than said external connection portion is sealed by said sealing resin.

US Pat. No. 10,366,932

METHOD AND SYSTEM FOR WET CHEMICAL BATH PROCESS

TAIWAN SEMICONDUCTOR MANU...

1. A method for performing a wet chemical process over a semiconductor wafer, comprising:immersing the semiconductor wafer into a hot phosphoric acid;
detecting the concentration of Silica in the hot phosphoric acid at a plurality of preset time points;
determining a process end point time at which the concentration of the Silica is maintained at approximately a fixed value; and
removing the semiconductor wafer from the hot phosphoric acid at the process end point times.

US Pat. No. 10,366,931

NANOSHEET DEVICES WITH CMOS EPITAXY AND METHOD OF FORMING

GLOBALFOUNDRIES INC., Gr...

1. A method comprising:forming a first and second nanosheet stack on a substrate, the first and the second nanosheet stacks each including a plurality of vertically spaced nanosheets disposed on the substrate and separated by a plurality of spacing members, each of the plurality of spacing members including a sacrificial layer and a pair of inner spacers formed on lateral ends of the sacrificial layer;
growing a pair of epitaxial regions adjacent to each of the first and the second nanosheet stacks from each of the plurality of nanosheets such that each of the plurality of inner spacers is enveloped by one of the epitaxial regions;
covering the first nanosheet stack with a mask; and
forming a pair of p-type source/drain regions on the second nanosheet stack, each of the pair of p-type source/drain regions being adjacent to one of the epitaxial regions on the second nanosheet stack.

US Pat. No. 10,366,929

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:forming a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked and protruding from an isolation insulating layer;
forming a sacrificial gate structure over the fin structure;
etching the first semiconductor layers at a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, thereby forming a first source/drain space in which the second semiconductor layers are exposed;
forming a dielectric layer at the first source/drain space, thereby covering the exposed second semiconductor layers;
etching the dielectric layer and part of the second semiconductor layers, thereby forming a second source/drain space; and
forming a source/drain epitaxial layer in the second source/drain space, wherein:
at least one of the second semiconductor layers is in contact with the source/drain epitaxial layer,
at least one of the second semiconductor layers is separated from a bottom of the source/drain epitaxial layer by the dielectric layer, and
an upper surface of the isolation insulating layer is located at a level below a bottom of the source/drain epitaxial layer.

US Pat. No. 10,366,928

HYBRIDIZATION FIN REVEAL FOR UNIFORM FIN REVEAL DEPTH ACROSS DIFFERENT FIN PITCHES

International Business Ma...

1. A semiconductor device having a uniform height across different fin densities, comprising:a semiconductor substrate having fins etched therein and including dense fin regions having respective groups of the fins and dielectric material and isolation regions including the dielectric material without fins, at least two of the isolation regions having different lengths including a first isolation region having a first length defined between a first dense fin region and a second dense fin region, and a second isolation region having a second length defined between the second dense fin region and a third dense fin region; and
one or more dielectric layers formed at a base of the fins in respective ones of the dense fin regions and the isolation regions and each having a uniform height across the dense fin regions and the isolation regions, the uniform height including a less than 2 nanometer difference across the one or more dielectric layers.

US Pat. No. 10,366,927

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

16. A semiconductor device comprising:a device isolation layer provided on a substrate, the device isolation layer defining a first sub-active pattern and a second sub-active pattern, the first and second sub-active patterns extending in a first direction and spaced apart from each other in the first direction;
a first gate electrode and a second gate electrode crossing the first sub-active pattern and the second sub-active pattern, respectively;
an isolation structure provided on the device isolation layer between the first and second sub-active patterns;
a first source/drain region provided on the first sub-active pattern between the first gate electrode and the isolation structure;
a second source/drain region provided on the second sub-active pattern between the second gate electrode and the isolation structure; and
an interlayer insulating layer covering the first and second sub-active patterns, the first and second source/drain region and the isolation structure,
wherein the device isolation layer includes a diffusion break region disposed between the first and second sub-active patterns,
wherein the isolation structure covers a top surface of the diffusion break region,
wherein a top surface of the isolation structure is in contact with the interlayer insulating layer and disposed at a same level as or a lower level than a top surface of each of the first and second sub-active patterns,
wherein the first and second sub-active pattern each include first sidewalls, the first sidewalls of the first and second sub-active patterns being aligned together in the first direction,
wherein the isolation structure is formed on the first sidewalls of the first and second sub-active patterns, and
wherein, with respect to a cross section that is parallel to the first direction and extending vertically through the first and second fin-type active patterns, the isolation structure has an uppermost point with respect to an upper surface of the substrate, and the uppermost point is part of a planar surface of the isolation structure that is parallel to the upper surface of the substrate.

US Pat. No. 10,366,926

STRUCTURE AND FORMATION METHOD OF SEMICONDUCTOR DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a fin structure;
a shallow trench isolation (STI) adjacent the fin structure;
a gate structure over a portion of the fin structure and the STI, wherein the gate structure comprises a gate dielectric layer, a work function layer over the gate dielectric layer, and a conductive fill material over the work function layer;
spacers along opposing sidewalls of the gate structure, the spacers terminating at ends of the gate structure along a longitudinal axis of the gate structure; and
a first dielectric layer surrounding the gate structure and the spacers in a plan view, the first dielectric layer having a first sidewall and a second sidewall intersecting the longitudinal axis of the gate structure, wherein the work function layer terminates over the STI between the fin structure and the first dielectric layer along the longitudinal axis of the gate structure, wherein the conductive fill directly contacts the first sidewall and the second sidewall of the first dielectric layer from an upper surface of the first dielectric layer to a bottom surface of the first dielectric layer.

US Pat. No. 10,366,924

CHIP CARRIERS AND SEMICONDUCTOR DEVICES INCLUDING REDISTRIBUTION STRUCTURES WITH IMPROVED THERMAL AND ELECTRICAL PERFORMANCE

Infineon Technologies AG,...

1. A chip carrier comprising a redistribution structure, the redistribution structure comprising:a dielectric layer extending in a horizontal direction;
a first electrically conductive layer arranged over the dielectric layer and extending in the horizontal direction, wherein horizontal dimensions of the first electrically conductive layer are greater than vertical dimensions of the first electrically conductive layer;
a trench arranged in the dielectric layer and extending in the horizontal direction, wherein horizontal dimensions of the trench are greater than vertical dimensions of the trench, and wherein the horizontal dimensions of the trench are different than the horizontal dimensions of the first electrically conductive layer;
a filling material filling the trench, wherein the filling material is different from the material of the dielectric layer; and
an electrically conductive via connection extending vertically through the dielectric layer, wherein the first electrically conductive layer is electrically coupled to the via connection.

US Pat. No. 10,366,923

METHOD OF SEPARATING ELECTRONIC DEVICES HAVING A BACK LAYER AND APPARATUS

SEMICONDUCTOR COMPONENTS ...

1. A method of singulating a wafer comprising:providing a wafer having a plurality of die formed as part of the wafer and separated from each other by spaces, wherein the wafer has first and second opposing major surfaces, and wherein a layer of material is formed atop the second major surface, and wherein the layer of material comprises at least one of a conductive material, a wafer-back coating, and a die-attach film adapted to remain at least in part atop surfaces of the plurality of die upon completion of the method of singulating the wafer;
placing the wafer onto a carrier substrate;
etching portions of the wafer through the spaces to form singulation lines, wherein etching comprises stopping atop the layer of material;
providing an apparatus comprising a compression structure, a support structure, and a transducer system configured to apply high frequency mechanical vibrations to the layer of material;
placing the wafer and the carrier substrate adjacent the support structure; and
applying pressure and high frequency mechanical vibrations to the wafer to separate the layer of material in the singulation lines.

US Pat. No. 10,366,922

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device, comprising:a plurality of conductive lines including a first conductive line and a second conductive line;
a plurality of sacrificial insulating layers arranged on sidewalls of the conductive lines; and
a plurality of contact plugs including a first contact plug and a second contact plug,
the first contact plug having a first pillar portion and a first protruding portion protruding from a part of the first pillar portion overlapped with a sidewall of the first conductive line, in a horizontal direction, so as to be in alignment and contact with the sidewall of the first conductive line,
the second contact plug having a second pillar portion and a second protruding portion protruding from a part of the second pillar portion overlapped with a sidewall of the second conductive line, in the horizontal direction, so as to be in alignment and contact with the sidewall of the second conductive line,
wherein the plurality of sacrificial insulating layers include an upper sacrificial layer, a lower sacrificial layer and a first sacrificial layer disposed between the upper sacrificial layer and the lower sacrificial layer,
wherein the first protruding portion is disposed between the upper sacrificial layer and the lower sacrificial layer to be overlapped with the upper sacrificial layer and the lower sacrificial layer, and
wherein the sidewall of the first conductive line, which is not overlapped with the upper sacrificial layer and the lower sacrificial layer, contacts with the first protruding portion.

US Pat. No. 10,366,921

INTEGRATED CIRCUIT STRUCTURE INCLUDING FUSE AND METHOD THEREOF

UNITED MICROELECTRONICS C...

1. An integrated circuit structure comprising a fuse, comprising:a fuse and a first metal interconnect disposed on a substrate and in a first dielectric layer, wherein the first dielectric layer is one single layer;
a patterned dummy disposed on the first dielectric layer, the patterned dummy having a first hole exposing a part of the first dielectric layer right above the fuse without contacting the fuse, wherein the first hole passes through the patterned dummy and only a top part of the first dielectric layer right above the part of the first dielectric layer;
a second metal interconnect disposed in the same level as the patterned dummy, and the second metal interconnect and the patterned dummy being composed of same material, wherein the second metal interconnect connects the fuse by contact plugs through the first dielectric layer, and the contact plugs comprise different materials from the second metal interconnect and the fuse, wherein each of the contact plugs includes a barrier layer containing titanium or titanium nitride and a metal layer while the fuse and the second metal interconnect are composed of a single metal, and the second metal interconnect and the fuse are spaced apart, wherein the second metal interconnect is directly on the contact plugs, and the contact plugs are directly on the fuse, and a surface interface is disposed between the second metal interconnect and the contact plugs, and an another surface interface is disposed between the contact plugs and the fuse;
a passivation layer directly and fully covering the patterned dummy, an exposed sidewall of the top part of the first dielectric layer in the first hole, a top surface of the part of the first dielectric layer in the first hole, a top surface of the second dielectric layer, and an exposed sidewall of the second dielectric layer in the first hole; and
an isolation structure overlapping the fuse disposed underneath thereof and being separated by a dielectric layer therebetween.

US Pat. No. 10,366,920

LOCATION-SPECIFIC LASER ANNEALING TO IMPROVE INTERCONNECT MICROSTRUCTURE

INTERNATIONAL BUSINESS MA...

1. A method, comprising: performing an initial partial anneal of a metal interconnect and overburden layer for semiconductor devices being fabricated on a chip on a semiconductor wafer; receiving image data of a top surface of the metal interconnect and overburden layer as image data from a scanning electron microscope (SEM) equipped with electron backscatter diffraction (EBSD); detecting an orientation of an early recrystallizing grain at a specific location on the top surface of the metal overburden layer, as implemented and controlled by a processor on a computer, in a process of selectively stepping through the image data at a preset sampling interval predetermined as based on an expected overburden grain size; determining whether the detected orientation of the early recrystallizing grain is desirable or undesirable; and selectively performing a laser anneal at specific locations to at least one of promote or inhibit certain grain orientations from growing, as based on the determining of being desirable or undesirable.

US Pat. No. 10,366,918

SELF-ALIGNED TRENCH METAL-ALLOYING FOR III-V NFETS

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming source/drain regions on opposite sides of a gate structure and within a compound semiconductor channel layer, wherein the compound semiconductor channel layer is composed of a III-V compound semiconductor material and is located directly on a compound semiconductor substrate layer and wherein the source/drain regions are n-doped;
forming source/drain contact openings extending through an interlevel dielectric (ILD) layer that overlies the source/drain regions and laterally surrounds the gate structure, each of the source/drain contact openings exposing a portion of one of the source/drain regions;
removing native oxides from the top surface of the exposed portion of each of the source/drain regions to provide a treated source/drain surface;
performing plasma doping to introduce a free radical of an n-type dopant to the treated source/drain surface of each source/drain region, wherein the free-radical of the n-type dopant is selected from the group consisting of Sn radical, Te radicals and Si radicals;
forming, by selective epitaxy, a semiconductor cap only within the source/drain contact openings and extending upwards from the plasma doped and treated source/drain surface of each of the source/drain regions, wherein the removing of the native oxides and the selective epitaxy are performed in a same reactor chamber and wherein the semiconductor cap passivates the plasma doped and treated source/drain surface;
forming a metal layer over exposed surfaces of the ILD layer, the gate structure and each semiconductor cap;
forming metal semiconductor alloy regions within the source/drain contact openings by reacting an entirety of each semiconductor cap with the metal layer, wherein each of the metal semiconductor alloy regions is located at a bottom of one of the source/drain contact openings and in direct contact with a top surface of the exposed portion of one of the source/drain regions; and
forming source/drain contacts within the source/drain contact openings, each of the source/drain contacts contacting a top surface of one of the metal semiconductor alloy regions, wherein the source/drain contacts have a contact resistance that is lower than 5×10?9 ohm-cm2, and wherein the source/drain regions comprise planar source/drain regions located within the compound semiconductor channel layer and raised source/drain regions, the raised source/drain regions having a same type of doping as the planar source/drain regions, and wherein each of the raised source/drain regions comprises a same III-V compound semiconductor material as the planar source/drain regions.

US Pat. No. 10,366,917

METHODS OF PATTERNING VARIABLE WIDTH METALLIZATION LINES

GLOBALFOUNDRIES Inc., Gr...

1. A method comprising:forming a first mandrel layer over a first mask layer and a second mandrel layer underlying the first mask layer;
etching the first mandrel layer to form a plurality of first mandrel lines, the plurality of first mandrel lines having variable widths;
etching a plurality of first non-mandrel trenches in the first mask layer, the plurality of first non-mandrel trenches having variable widths;
etching a plurality of first mandrel trenches, using the plurality of first mandrel lines as an etch mask, in the first mask layer, wherein the plurality of first mandrel trenches and the plurality of first non-mandrel trenches define a mandrel pattern; and
forming a plurality of second mandrel lines in the second mandrel layer according to the mandrel pattern, the plurality of second mandrel lines having the variable widths of the plurality of first mandrel lines and the variable widths of the plurality of first non-mandrel trenches.

US Pat. No. 10,366,916

INTEGRATED CIRCUIT STRUCTURE WITH GUARD RING

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure comprising:a substrate having a first region and a second region being adjacent each other;
a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the first patterned layer; and
a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring comprises a dielectric material, includes a first width W1 and is separated and spaced a first distance D1 from the first features, W1 being greater than D1.

US Pat. No. 10,366,915

FINFET DEVICES WITH EMBEDDED AIR GAPS AND THE FABRICATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a first gate structure disposed over a substrate, the first gate structure extending in a first direction;
a second gate structure disposed over the substrate, the second gate structure extending in the first direction;
a dielectric material disposed between the first gate structure and the second gate structure;
an air gap disposed within the dielectric material; and
a high-k dielectric or a metal disposed within the dielectric material, the metal being in contact with the air gap.

US Pat. No. 10,366,914

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:(a) forming an isolation portion on a semiconductor layer side of an SOI substrate including a support substrate, a buried insulating film formed on the support substrate and a semiconductor layer formed on the buried insulating film, thereby forming an active region partitioned by the isolation portion in the SOI substrate;
(b) selectively forming a first epitaxial layer on an outer end portion of the semiconductor layer in the active region by performing a first selective epitaxial growth process on the SOI substrate; and
(c) after the step (b), selectively forming a second epitaxial layer over the semiconductor layer in the active region and the first epitaxial layer by performing a second selective epitaxial growth process on the SOI substrate,
wherein the active region includes:
a first active region having a width whose length in a first direction is greater than or equal to a first length, and
a second active region having a width whose length in the first direction is less than the first length,
wherein the first selective epitaxial growth process is performed on the first active region, and
wherein the second selective epitaxial growth process is performed on the first active region and the second active region.

US Pat. No. 10,366,913

METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT AND METHOD FOR FORMING MASK PATTERN OF THE SAME

Kabushiki Kaisha Toshiba,...

1. A method for forming a mask pattern of a semiconductor element, the method comprising:forming a mask pattern group based on a prescribed rule for providing the semiconductor element with a first gate threshold voltage, the mask pattern group including:
a well pattern defining a first region on a semiconductor region;
an interconnect pattern defining an interconnect including a gate portion extending in a first direction on the first region; and
a source/drain pattern defining a second region positioned in the first region, the gate portion crossing the second region in the first direction; and
modifying the mask pattern group to change the first gate threshold voltage to a second gate threshold voltage based on a correlation between a gate threshold voltage and at least one of first to fourth distances in the semiconductor element, wherein
the gate threshold voltage changes with an absolute change amount that increases as each of the first to fourth distances is shortened,
the first distance being defined as a distance to an outer edge of the first region from an outer edge of the second region proximal to the outer edge of the first region;
the second distance being defined as a distance from the outer edge of the second region to the gate portion in a second direction crossing the first direction;
the third distance being defined as a distance to the second region from a portion of the interconnect positioned outside the second region in one of the first direction or the second direction; and
the fourth distance being defined when the mask pattern group further includes an ion implantation pattern defining an opening of an ion implantation mask in which the second region is exposed, the fourth distance being a distance to a wall surface of the opening from the outer edge of the second region proximal to the wall surface of the opening.

US Pat. No. 10,366,912

STAGE APPARATUS AND CHARGED PARTICLE BEAM APPARATUS

Hitachi High-Technologies...

1. A stage apparatus comprising:a first table that supports a sample and moves the sample in a first direction;
a second table that moves the first table in a second direction different from the first direction; and
a first moving mechanism that generates a driving force for moving the first table in the first direction;
a second moving mechanism that generates a driving force for moving the second table in the second direction;
a movable body that supports a stator included in the first moving mechanism; and
a third moving mechanism that moves the movable body so as to follow the movement of the second table in the second movement direction.

US Pat. No. 10,366,911

CARRIER SUBSTRATE FOR CARRYING AN OLED IN MANUFACTURING PROCESS AND MANUFACTURING METHOD FOR THE SAME

Wuhan China Star Optoelec...

1. A carrier substrate for carrying an OLED in manufacturing process, comprising:a substrate; and
an attracted layer disposed on a surface of the substrate, wherein the attracted layer includes a resin layer and multiple magnetic nanoparticles distributed in the resin layer;
wherein a distribution density of the magnetic nanoparticles is gradually increased from an edge location to a center location of the resin layer.

US Pat. No. 10,366,910

PICKUP AND PLACING DEVICE AND OPERATION METHOD OF PICKING AND PLACING BY PICKUP AND PLACING DEVICE

Innolux Corporation, Mia...

1. An operation method of picking and placing by a pickup and placing device, comprising:providing a pickup and placing device comprising:
a control element;
a substrate; and
a pickup structure comprising a plurality of pickup heads used for picking up or placing a plurality of light emitting diodes respectively, wherein the substrate has an upper surface and a lower surface opposite to each other and a plurality of conductive via structures, the conductive via structures are electrically connected to the control element, the pickup structure is electrically connected to the conductive via structures, the control element provides a signal, and the signal is transmitted to the pickup structure through the conductive via structures and selects a portion of the pickup heads, and the portion of the pickup heads of the pickup structure attract the selected light emitting diodes or place the attracted light emitting diodes on an active array substrate;
wherein each of the pickup heads comprises a main body portion and a pickup portion, the main body portion comprises a first body portion and a second body portion, a channel is provided between the first body portion and the second body portion, the pickup portion is disposed on the first body portion and second body portion of the main body portion and the pickup portion exposes the channel, the pickup structure further comprises a carrier, a plurality of controllers and a plurality of valves, the carrier comprises a plurality of chambers and a plurality of conductive elements, the plurality of channels are connected to the corresponding chambers, the controllers are disposed in the carrier and connected to the conductive via structures of the substrate through the conductive elements respectively, the valves are disposed in the chambers respectively, when one of the pickup heads is going to attract one of the corresponding light emitting diodes, one of the controllers controls one of the corresponding valves, and one of the chambers and one of the corresponding channels are connected to each other for attracting one of the corresponding light emitting diodes.

US Pat. No. 10,366,909

THERMAL CHAMBER EXHAUST STRUCTURE AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. An exhaust structure comprising:an intake section comprising a first high thermal conductivity material, the intake section including an inlet;
an output section comprising a second high thermal conductivity material, the output section including an outlet; and
a piping section comprising a third high thermal conductivity material, the piping section comprising a first inner diameter from the intake section to the output section, thereby being configured to communicatively couple the intake section with the output section,
wherein
the exhaust structure is configured to provide a high thermal conductivity path from the inlet to the outlet, the high thermal conductivity path comprising the first high thermal conductivity material, the second high thermal conductivity material, and the third high thermal conductivity material,
the piping section and one of the intake section or the output section are separate components of the exhaust structure mechanically coupled to each other at a section interface, and
the one of the intake section or the output section has a second inner diameter at the section interface, the second diameter having a same value as a value of the first inner diameter.

US Pat. No. 10,366,906

ELECTRONIC PACKAGE AND ITS PACKAGE SUBSTRATE

PHOENIX PIONEER TECHNOLOG...

1. A package substrate, comprising:an insulating portion including a first side and a second side opposite to the first side;
a wiring portion embedded in the insulating portion; and
a metal board disposed on the first side of the insulating portion and in contact with the wiring portion,
wherein the metal board is defined with a plurality of electrical contacts and a heat dissipating portion separated from the plurality of electrical contacts,
wherein the metal board includes a plurality of openings, with parts of the metal board at an interior of the plurality of openings forming conductive posts being defined as the plurality of electrical contacts and a remaining part of the metal board at a periphery of the plurality of openings being defined as the heat dissipating portion separated from the plurality of electrical contacts by the plurality of openings.

US Pat. No. 10,366,905

SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:a semiconductor chip including a semiconductor layer that has a first surface on a die-bonding side, a second surface on the opposite side of the first surface, and an end surface extending in a direction crossing the first surface and the second surface, a first electrode that is formed on the first surface and has a peripheral edge at a position separated inward from the end surface, and a second electrode formed on the second surface;
a conductive substrate onto which the semiconductor chip is die-bonded;
a conductive spacer that has a planar area smaller than that of the first electrode and supports the semiconductor chip on the conductive substrate;
a resin package that seals at least the semiconductor chip and the conductive spacer; and
a bonding material that is provided between the conductive spacer and the first electrode of the semiconductor chip, and has a projecting portion projecting from the conductive spacer and fitting inside the first electrode.

US Pat. No. 10,366,904

ARTICLES HAVING HOLES WITH MORPHOLOGY ATTRIBUTES AND METHODS FOR FABRICATING THE SAME

Corning Incorporated, Co...

1. An article comprising:a glass-based substrate comprising a first surface, a second surface, and at least one hole extending from the first surface, wherein:
the at least one hole comprises an interior wall having a surface roughness Ra that is less than or equal to 1 ?m;
the at least one hole comprises a first opening having a first diameter that is present at the first surface;
a first plane is defined by the first surface of the glass-based substrate based on an average thickness of the glass-based substrate; and
a ratio of a depression depth to the first diameter of the at least one hole is less than or equal to 0.007, wherein the depression depth is measured from the first plane to the first surface at the first opening of the at least one hole;
the at least one hole is a through-hole such that a second opening of the at least one hole having a second diameter is present on the second surface;
a difference between the first diameter and the second diameter is less than or equal to 2 ?m;
a circularity of the at least one hole is less than or equal to 5 ?m;
each of the first diameter and the second diameter is in a range from 5 ?m to 250 ?m; and
an aspect ratio of the average thickness of the glass-based substrate to at least one of the first diameter and the second diameter is in a range from 1:1 to 15:1.

US Pat. No. 10,366,902

METHODS FOR CYCLIC ETCHING OF A PATTERNED LAYER

Tokyo Electron Limited, ...

1. A method for treating a substrate, comprising:receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer;
exposing the substrate to a passivation/activation plasma to concurrently form a passivation layer on the mask layer and an activation layer on the portions of the intermediate layer;
transitioning the passivation/activation plasma to a desorption plasma to concurrently remove the passivation layer and the activation layer; and
alternating between the passivation/activation plasma and the desorption plasma,
wherein the passivation layer and the activation layer are of different compositions.

US Pat. No. 10,366,901

INTEGRATED STRUCTURES, CAPACITORS AND METHODS OF FORMING CAPACITORS

Micron Technology, Inc., ...

1. A capacitor comprising:a stack of alternating first and second levels supported by a base; the first levels comprising only insulative material, and the second levels comprising insulative pillars extending through conductive material;
a plurality of slots extending through the stack; each of the slots comprised by the plurality of slots having a first end and an opposing second end with a central region between the first and second ends; the plurality of slots being arranged in multiple rows with the second ends of within a first row being spaced from the first ends of slots in a second row by a lateral distance; and
the insulative pillars within the second levels being within the lateral distance between rows of slots, the insulative pillars being of a different composition than the insulative material of the first levels.

US Pat. No. 10,366,900

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, comprising:forming a first dielectric layer over an underlying structure disposed on a substrate, and the underlying structure includes plural structures;
forming a planarization resistance layer over the first dielectric layer;
patterning the planarization resistance layer to form a patterned planarization resistance layer;
forming a second dielectric layer over the first dielectric layer and the patterned planarization resistance layer so that a bottom of a concave of the second dielectric layer is positioned on the patterned planarization resistance layer; and
performing a planarization operation on the second dielectric layer, the patterned planarization resistance layer and the first dielectric layer to remove the first dielectric layer and the second dielectric layer on top surfaces of the plural structures and to remove the patterned planarization resistance layer,
wherein the patterned planarization resistance layer is made of a material different from the first dielectric layer and having a lower etching rate in the planarization operation than the first and second dielectric layers to reduce a dishing amount between the plural structures, wherein the planarization resistance layer includes one or more of SiN, SiON, SiCN, SiC, AlO and AlON, and wherein a difference in height, between the top surfaces of the plural structures after removing the first and second dielectric layers and a lowest portion of an upper surface of the first dielectric layer between the plural structures after removing the planarization resistance layer, is between 1 nano meter and 10 nano meters.

US Pat. No. 10,366,899

METHOD OF DETECTING A CONDITION

SPTS Technologies Limited...

1. A control method of a plasma dicing process, comprising the steps of:providing a non-metallic substrate having a plurality of designated dicing lanes;
plasma etching through the substrate along the dicing lanes;
during the plasma etching, monitoring emission of infrared radiation by at least a portion of the dicing lanes of the substrate to detect an increase in infrared radiation due to emission of infrared radiation by the dicing lanes; and
determining, prior to singulation of the substrate along the dicing lanes, that a condition associated with a final phase of the plasma dicing process exists when the increase in the infrared radiation has been detected.

US Pat. No. 10,366,898

TECHNIQUES AND SYSTEMS FOR CONTINUOUS-FLOW PLASMA ENHANCED ATOMIC LAYER DEPOSITION (PEALD)

Nano-Master, Inc., Austi...

1. An atomic layer deposition (ALD) system comprising:(a) a cylindrical chamber comprising an upper portion and a lower portion such that said upper portion and said lower portion can be closed to obtain a sealed state of said chamber;
(b) said upper portion comprising a planar inductively coupled plasma (ICP) source laterally affixed at its distal end from said lower portion;
(c) said lower portion containing a platen onto which a substrate is placed, said platen and said substrate heated by a platen heater to a desired temperature;
(d) said substrate isolated from said ICP source in said chamber by a grounded metal plate laterally affixed above said substrate and a ceramic plate laterally affixed below said grounded metal plate but above said substrate, said grounded metal plate and said ceramic plate having a first plurality of holes and a second plurality of holes respectively such that each of said first plurality of holes is aligned with a corresponding hole of said second plurality of holes, and each of said second plurality of holes has a diameter less than two Debye lengths of a plasma, said ICP source configured to generate from a gas A said plasma above said grounded plate and said grounded metal plate configured to terminate said plasma;
(e) said ICP source configured to receive a continuous supply of said gas A;
(f) said lower portion configured to contain a gas B passed as a pulse from below said ceramic plate; and
(g) each of said gas A and said gas B comprising one or more individual chemical species;wherein a uniform atomically sized film is produced on said substrate by a self-limiting reaction of excited neutrals of said gas A, said gas B and said substrate.

US Pat. No. 10,366,896

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A semiconductor device, comprising:a gate electrode on a substrate, wherein the gate electrode comprises a metal gate;
a gate dielectric layer between the gate electrode and the substrate, wherein the gate dielectric layer comprises a top portion and a bottom portion and a width of the top portion is less than a width of the bottom portion, and the gate dielectric layer does not extend directly over the source/drain regions respectively;
a high-k dielectric layer between and directly contacts the gate dielectric layer and the gate electrode, wherein a width of the high-k dielectric layer is equal to the width of the top portion and less than the width of the bottom portion;
a first spacer on the bottom portion and directly contacting the high-k dielectric layer, the top portion, and the bottom portion; and
a second spacer adjacent to the first spacer, wherein a bottom surface of the second spacer is even with a bottom surface of the bottom portion, a large portion of the first spacer and the second spacer are substantially parallel and vertically arranged, and the first spacer and the second spacer end at tops thereof at substantially same point.

US Pat. No. 10,366,894

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING DEVICE, AND RECORDING MEDIUM

KOKUSAI ELECTRIC CORPORAT...

1. A method for manufacturing a semiconductor device, comprising:forming a metal carbide film including a first metal element and a second metal element on a substrate, by time-divisionally performing:
forming a first film containing the first metal element and carbon and not containing the second metal element by time-divisionally performing supplying a first precursor gas containing the first metal element and not containing carbon to the substrate to form a first metal-containing layer and supplying a reaction gas containing carbon and not containing a metal element to the first metal-containing layer; and
forming a second film containing the second metal element and carbon and not containing the first metal element on the first film by time-divisionally performing supplying a second precursor gas containing the second metal element differing from the first metal element and not containing carbon to the first film to form a second metal-containing layer on the first film and supplying the reaction gas to the second metal-containing layer,
wherein the first precursor gas and the second precursor gas are halides.

US Pat. No. 10,366,893

PROCESS FOR MAKING SILICON CARBIDE SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a silicon carbide semiconductor device, comprising:forming a gate insulating film on a silicon carbide substrate;
forming a polysilicon film on an entire surface of the gate insulating film;
ion implanting one or more dopants selected from a group consisting of N, P, As, Sb, B, Al, and Ar into the polysilicon film that is on the entire surface of the gate insulating film;
before conducting any thermal process on the polysilicon film that has been ion implanted, removing a thickness of 50 nm to 300 nm uniformly from a surface layer of the polysilicon film that has been ion implanted;
selectively forming a mask on the polysilicon film from which the thickness of 50 nm to 300 nm has been removed uniformly;
forming a polysilicon electrode by removing an exposed portion of the polysilicon film that is exposed by the mask via isotropic dry etching;
removing the mask; and
forming an interlayer insulating film on the polysilicon electrode.

US Pat. No. 10,366,892

HYBRID III-V TECHNOLOGY TO SUPPORT MULTIPLE SUPPLY VOLTAGES AND OFF STATE CURRENTS ON SAME CHIP

International Business Ma...

1. A method of forming dual III-V semiconductor channel materials on a wafer, the method comprising the steps of:providing a wafer having a first III-V semiconductor layer on an oxide;
forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer;
using shallow trench isolation to define at least one first active area and at least one second active area in the wafer;
converting the first III-V semiconductor layer in the at least one second active area to an insulator using ion implantation; and
removing the second III-V semiconductor layer from the at least one first active area selective to the first III-V semiconductor layer,
wherein the first III-V semiconductor layer in the at least one first active area and the second III-V semiconductor layer in the at least one second active area serve as the dual III-V semiconductor channel materials on the wafer.

US Pat. No. 10,366,891

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A vertical semiconductor apparatus comprising:a gallium nitride substrate;
a gallium nitride semiconductor layer provided on the gallium nitride substrate;
a p-type impurity region that is provided in the gallium nitride semiconductor layer and has an element to function as an acceptor for gallium nitride;
an n-type impurity region that is provided in the p-type impurity region and has an element to function as a donor for gallium nitride; and
an electrode provided in contact with a rear surface of the gallium nitride substrate, wherein
the element to function as the donor in the n-type impurity region includes:
a first impurity element that enters sites of gallium atoms in the gallium nitride semiconductor layer; and
a second impurity element that is an element different from the first impurity element and enters sites of nitrogen atoms in the gallium nitride semiconductor layer, and
in the n-type impurity region, a concentration of the first impurity element is higher than a concentration of the second impurity element.

US Pat. No. 10,366,890

METHOD FOR PATTERNING A SUBSTRATE USING A LAYER WITH MULTIPLE MATERIALS

Tokyo Electron Limited, ...

1. A method of patterning a substrate, the method comprising:forming mandrels on a target layer of a substrate, the mandrels being comprised of a first material, the target layer being comprised of a third material;
forming sidewall spacers on sidewalls of the mandrels by depositing a conformal film on the substrate and removing portions of the conformal film above top surfaces of the mandrels while leaving the conformal film below top surfaces of the mandrels such that the sidewall spacers are formed on vertical sidewalls of the mandrels and such that the conformal film covers the target layer between adjacent sidewall spacers, the conformal film being comprised of a second material;
forming a first etch mask on the substrate, the first etch mask defining openings that uncover regions of both the first material and the second material
executing a first etch process that selectively etches uncovered portions of the second material until the conformal film covering the target layer between adjacent sidewall spacers is removed while the sidewall spacers remain on the substrate; and
forming a second etch mask on the substrate, the second etch mask defining openings that uncover regions of both the first material and the second material; and
executing a second etch process that selectively etches uncovered portions of the first material until uncovered mandrels are removed.

US Pat. No. 10,366,889

METHOD OF FORMING SEMICONDUCTOR DEVICE

UNITED MICROELECTRONICS C...

1. A method of forming a semiconductor device, comprising:providing a material layer on a substrate;
performing a spacer patterning process to form a plurality of first mask patterns parallel with each other on the material layer, the first mask patterns extending along a first direction;
performing a pattern splitting process to remove a portion of the first mask patterns to form a plurality of second openings, the second openings parallel with each other and extending along a second direction, across the first mask patterns; and
patterning the material layer by using remaining portion of the first mask patterns as a mask, to form a plurality of patterns in an array arrangement.

US Pat. No. 10,366,888

PATTERN FORMING METHOD

Tokyo Electron Limited, ...

1. A pattern forming method comprising steps of:forming a first organic film by coating an etching target film with a composition including a polymer including a cross-linkable component;
infiltrating an inorganic substance into the first organic film;
cross-linking the polymer;
forming a second organic film on the first organic film after the steps of infiltrating and cross-linking;
forming a second organic film pattern by patterning the second organic film;
forming a first organic film pattern having a pitch reduced to one-half of a pitch of the second organic film pattern by patterning the first organic film by a self-aligned patterning method that uses the second organic film pattern as a core pattern; and
forming an etching target film pattern having a pitch reduced to one-half of a pitch of the first organic film pattern by patterning the etching target film by a self-aligned patterning method that uses the first organic film pattern as a core pattern.

US Pat. No. 10,366,887

METHOD OF USING CHEMICALLY PATTERNED GUIDE LAYERS IN CHEMOEPITAXY DIRECTING OF BLOCK CO-POLYMERS

Brewer Science, Inc., Ro...

1. A method of forming a microelectronic structure, said method comprising: providing a stack comprising:a substrate having a surface; and
one or more optional intermediate layers on said substrate surface;
forming a patternable layer having first and second surfaces, said first surface being on said intermediate layers, if present, or on said substrate surface, if no intermediate layers are present, and said second surface being remote from said first surface, said patternable layer having an initial surface property at said second surface;
exposing said patternable layer to radiation so as to selectively alter said initial surface property to yield an altered surface property at the areas of exposure, forming a patterned layer;
without altering said patterned layer, applying a self-assembling composition to the second surface of said patterned layer, said composition comprising a block copolymer comprising a first block and a second block; and
causing said composition to self-assemble into a self-assembled layer in response to the initial surface property, the altered surface property, or both, wherein said self-assembled layer comprises a first self-assembled region and a second self-assembled region different from said first self-assembled region, wherein:
said initial surface property is a lack of affinity towards one of said first and second blocks over the other of said first and second blocks; and
during said exposing, an affinity to one of said first and second blocks over the other of said first and second blocks develops, said affinity being the altered surface property.

US Pat. No. 10,366,886

PATTERN FORMING METHOD, SELF-ORGANIZATION MATERIAL, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS

Toshiba Memory Corporatio...

9. A method of manufacturing a semiconductor apparatus comprising:placing a self-organization material on an under layer, the self-organization material including a block copolymer which includes a first polymer, a second polymer, and a third polymer, the third polymer is bonded to the first polymer and has a molecular structure including oxygen attached to a cyclic structure;
phase separating the block copolymer on the under layer to form a phase-separation pattern;
removing the first polymer or second polymer from the phase-separation pattern; and
after removing the first polymer or second polymer from the phase-separation pattern, processing the under layer by using the phase-separation pattern as a mask.

US Pat. No. 10,366,885

LASER IRRADIATION METHOD AND LASER IRRADIATION DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method of manufacturing a semiconductor device comprising:forming a semiconductor film comprising amorphous silicon over a substrate;
irradiating desired regions of the semiconductor film with a plurality of laser beams to crystallize the desired regions of the semiconductor film; and
patterning the crystallized semiconductor film to form a plurality of semiconductor layers, each being comprised in a respective one of a plurality of thin film transistors,
wherein the plurality of laser beams are slantingly incident on an irradiation surface of the semiconductor film.

US Pat. No. 10,366,884

METHODS FOR FORMING A GERMANIUM ISLAND USING SELECTIVE EPITAXIAL GROWTH AND A SACRIFICIAL FILLING LAYER

STRATIO, Seoul (KR)

1. A method for obtaining a semiconductor island, the method comprising:epitaxially growing one or more semiconductor structures over a substrate with one or more mask layers defining one or more regions that are not covered by the one or more mask layers over the substrate, wherein the one or more semiconductor structures are epitaxially grown over the one or more regions that are not covered by the one or more mask layers, a respective epitaxially grown semiconductor structure of the one or more epitaxially grown semiconductor structures including a first portion located adjacent to the one or more mask layers and a second portion located away from the one or more mask layers, the first portion of the respective epitaxially grown semiconductor structure having a height that is less than a height of a portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure, the second portion of the respective epitaxially grown semiconductor structure having a height that is equal to, or greater than, the height of the portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure;
forming one or more dielectric or polysilicon filling layers directly on at least the first portion of the respective epitaxially grown semiconductor structure; and,
subsequent to forming the one or more filling layers on at least the first portion of the respective epitaxially grown semiconductor structure, removing at least a portion of the respective epitaxially grown semiconductor structure that is located above the height of the portion of the one or more mask layers located adjacent to the first portion of the respective epitaxially grown semiconductor structure.

US Pat. No. 10,366,883

HYBRID MULTILAYER DEVICE

Hewlett Packard Enterpris...

1. A multilayer device, comprising:a substrate;
a first layer disposed on the substrate;
a trench extending longitudinally through at least one of the substrate and the first layer, the trench having a first sidewall spaced apart from a second sidewall, each sidewall extending from a given surface of the substrate to another surface of the first layer that is spaced apart from the given surface by the first and second sidewalls; and
an active region disposed on the first layer, both the active region and the first layer overlying the trench, and the first layer bonded to the substrate at locations laterally outward of the first and second sidewalls of the trench.

US Pat. No. 10,366,882

SYSTEM FOR PRODUCING POLYCRYSTALLINE SILICON, APPARATUS FOR PRODUCING POLYCRYSTALLINE SILICON, AND PROCESS FOR PRODUCING POLYCRYSTALLINE SILICON

Shin-Etsu Chemical Co., L...

1. A process for producing polycrystalline silicon, comprising generating steam during growth of polycrystalline silicon while keeping a temperature of an inner wall surface of a reactor at not more than 370° C., wherein the inner wall surface of the reactor which contacts a process gas comprises a steel type comprising an alloy for which a value of a relational expression in mass content percentage among chromium, nickel, and silicon, [Cr]+[Ni]?1.5 [Si], is not less than 40%,wherein water is removed and returned to said reactor via a coolant circulation path, which comprises a first pressure control section, a second pressure control section, and a coolant tank,
wherein said steam is generated by feeding hot water, having a temperature higher than a standard boiling point, to said reactor, then vaporizing a portion of said hot water,
where the pressure of said hot water is reduced so that a portion of said hot water itself is flashed into said steam,
wherein the pressure of water discharged from said reactor is controlled by said first pressure control section and the pressure in said coolant tank is controlled by said second pressure control section, and
said hot water is flashed to generate steam and to cool the hot water simultaneously by reducing the pressure of the hot water in the first pressure control section,
wherein said first pressure control section comprises a first pressure indicator controller and a first pressure control valve configured for reducing the pressure of said hot water, and said second pressure control section comprises a second pressure indicator controller and a second pressure control valve configured for controlling pressure within said coolant tank.

US Pat. No. 10,366,881

POROUS FIN AS COMPLIANT MEDIUM TO FORM DISLOCATION-FREE HETEROEPITAXIAL FILMS

International Business Ma...

1. A semiconductor device, comprising:a porous fin formed on a monocrystalline substrate;
a hydrogenated surface formed on the porous fin; and
an epitaxial monocrystalline layer formed on the hydrogenated surface, the epitaxial monocrystalline layer including a material other than a material of the monocrystalline substrate and forming a relaxed heteroepitaxial interface with the monocrystalline substrate wherein a thickness of the porous fin and a thickness of the epitaxial monocrystalline layer include a thickness ratio configured to relax strain in the epitaxial monocrystalline layer.

US Pat. No. 10,366,880

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A method of manufacturing a semiconductor device, the method comprising:forming a semiconductor device on a semiconductor wafer;
forming an electrode layer on a first main surface of the semiconductor wafer, the electrode layer being electrically connected to the semiconductor device;
forming a first protective film on the first main surface of the semiconductor wafer, the first protective film containing a first resin and having an opening that partially exposes the electrode layer;
forming an electrode film on a surface of the electrode layer exposed in the opening;
selectively applying a second resin on surfaces of the first protective film and the electrode film by an inkjet method so as to form, along a boundary between the first protective film and the electrode film, two second protective films that extend parallel to the boundary, one of the second protective films being formed on a first side of the boundary and the other second protective film being formed on an opposite side of the boundary, and
applying a third resin between the two second protective films by the inkjet method so as to form a third protective film in contact with the two second protective films, a viscosity of the third resin being lower than a viscosity of the second resin.

US Pat. No. 10,366,877

SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS

Tokyo Electron Limited, ...

1. A substrate processing method comprising:supplying a first cleaning liquid containing water to a first surface of a substrate while the substrate is being rotated, thereby cleaning the first surface of the substrate;
supplying a second cleaning liquid containing water to a second surface of the substrate that is opposite to the first surface of the substrate while the substrate is being rotated and the first cleaning liquid is being supplied to the first surface of the substrate, thereby cleaning the second surface of the substrate;
supplying a rinsing liquid to the first surface of the substrate and the second surface of the substrate while the substrate is being rotated, thereby rinsing the first cleaning liquid and rinsing the second cleaning liquid;
stopping the supplying of the rinsing liquid to the second surface of the substrate at a predetermined time, continuing the rinsing of the first surface of the substrate after stopping the rinsing of the second surface of the substrate and thereafter supplying an organic solvent to the first surface of the substrate to substitute the rinsing liquid on the first surface such that the first surface of the substrate is not exposed to outside air while the substrate is continuously rotated, thereby removing the rinsing liquid remaining on the first surface of the substrate by the organic solvent and removing the rinsing liquid remaining on the second surface of the substrate by a centrifugal force;
supplying a water-repellent agent to the first surface of the substrate while the substrate is being rotated; and
after the supplying the water-repellent agent to the first surface of the substrate, increasing a rotation speed of the substrate thereby drying the substrate.

US Pat. No. 10,366,876

PHOSPHOR-CONTAINING FILM AND BACKLIGHT UNIT

FUJIFILM Corporation, To...

1. A phosphor-containing film, comprising:a first substrate film; and
a phosphor-containing layer at which a plurality of regions containing phosphors are discretely disposed in a resin layer having an impermeability to oxygen, the phosphor having a property that deteriorates upon exposure to oxygen by reacting with the oxygen, and the phosphor-containing layer being disposed on the first substrate film,
wherein the plurality of regions containing phosphors comprise a plurality of first fluorescent regions containing phosphors and a plurality of second fluorescent regions dispersed at different positions in a film thickness direction from positions of the plurality of first fluorescent regions, both the first fluorescent regions and the second fluorescent regions being disposed in the same resin layer having an impermeability to oxygen.

US Pat. No. 10,366,874

GAS DISCHARGE LAMP AND SPOTLIGHT SYSTEM COMPRISING GAS DISCHARGE LAMP

1. A gas discharge lamp comprising a cylindrical outer bulb providing an enclosure in which a burner including two electrodes each having an electrode connection is arranged, wherein the cylindrical outer bulb hermetically seals the enclosure against the outside and the cylindrical outer bulb is made from doped quartz glass containing samarium.

US Pat. No. 10,366,873

CRYOGENIC 2D LINEAR ION TRAP AND USES THEREOF

University of Florida Res...

1. A rectilinear ion trap comprising:spaced x and y pairs of flat RF electrodes disposed in the zx and zy plane to define a trap volume, wherein each of the x flat RF electrodes comprise a slit;
a pair of DC plates, wherein the DC plates are coupled to the x and y pairs of flat RF electrodes, wherein the DC plates are disposed in the xy plane, and wherein each DC plate comprises holes configured to receive a fastener;
a base plate, wherein the base pate is coupled to the DC plates, wherein the base plate is positioned on top of the spaced x and y pairs of flat RF electrodes, and wherein the base plate is disposed of in the zy plane, wherein the base plate is parallel to the Y pair of flat RF electrodes, and wherein the base plate comprises holes to receive a fastener,
sapphire spacers, wherein the sapphire spacers have two holes configured to receive a fastener, wherein the sapphire spacers are placed between the base plate and the DC plate, wherein the sapphire spacers are placed between the DC plates and the ends of the x and y flat RF electrodes; and
fasteners, wherein the fasteners are passed through the holes in the DC plates, base plates, x and y flat RF electrodes and sapphire spacers.

US Pat. No. 10,366,872

FREQUENCY AND AMPLITUDE SCANNED QUADRUPOLE MASS FILTER AND METHODS

The Trustees of Indiana U...

1. A method of operating a quadrupole mass filter, the method comprisingionizing a sample to produce ions, each produced ion having a mass-to-charge ratio,
passing the produced ions into a quadrupole, and
applying at least one AC voltage to the quadrupole and controlling the at least one AC voltage to separate the ions by (i) incrementally varying a frequency of the at least one AC voltage within a first range of frequencies and (ii) for each of at least some of the incremental frequencies in the first range of frequencies, incrementally varying an amplitude of the at least one AC voltage within a range of amplitudes,
wherein each incremental frequency and incremental amplitude pair of the at least one AC voltage creates a different band pass filter in the quadrupole through which produced ions having a different corresponding mass-to-charge ratio pass to a detector.

US Pat. No. 10,366,871

ANALYZER

ATONARP INC., Minato-ku,...

1. An analyzer comprising:an ionizer that is configured to ionize molecules to be analyzed;
a filter that is configured to selectively pass ions generated by the ionizer via a magnetic field;
a detector that is configured to detect ions that have passed the filter; and
a processing device that is configured (a) to measure a tuning gas having components with respective concentrations and provided at one or more predetermined intervals during an operation and (b) to adjust, based on the measuring, (i) an ion current of the ionizer, (ii) the magnetic field associated with the filter, (iii) and a sensitivity of the detector to detect the components and the respective concentrations of the components of the provided tuning gas.

US Pat. No. 10,366,870

CYLINDRICAL SPUTTERING TARGET AND PROCESS FOR PRODUCING THE SAME

TOSOH CORPORATION, Shuna...

1. A process for producing a cylindrical ceramic sputtering target comprising a bonding material filled in a cavity defined by a cylindrical ceramic target material and a cylindrical base material wherein the cylindrical base material is disposed inside the cylindrical ceramic target material, wherein as observed by an X-ray radiograph of the bonding material, the total area of portions where no bonding material exists is 10 cm2 or less per 50 cm2 of X-ray radiograph area, and the maximum area of the portions where no bonding material exists is 9 cm2 or less and wherein the volume ratio of the bonding material at 25° C. that is filled in the cavity is at least 96.8% with respect to the volume of the cavity at the melting point of the bonding material, said process comprising filling a molten bonding material in a cavity, starting cooling the molten bonding material from its one end toward its other end in a cylindrical axial direction in sequence, further filling the molten bonding material in the cavity during cooling and further comprising vibrating the molten bonding material filled in the cavity when or after filling the bonding material in the cavity.

US Pat. No. 10,366,869

ACTIVE FEEDBACK CONTROL OF SUBSYSTEMS OF A PROCESS MODULE

Lam Research Corporation,...

15. A communications system for synchronizing control signals between a plurality of subsystems coupled to a process module used for processing a substrate, comprising:a distributed controller coupled to each of the plurality of subsystems and configured to initiate a plurality of process steps, each of the process steps having a step period, each step period having a plurality of fractions, the distributed controller including a master clock having a clock speed that includes a plurality of clock cycles, each clock cycle having a duration that is pre-correlated to a feedback loop within which synchronized control signals are delivered to and received from the plurality of subsystems by the distributed controller, wherein the distributed controller is configured to assign a predefined number of clock cycles for performing a corresponding number of feedback loops for transitioning between process steps,
wherein the predefined number of clock cycles are restricted to a fraction of the step period.

US Pat. No. 10,366,868

APPARATUS AND METHOD FOR APPLYING SURFACE COATINGS

Europlasma NV, Oudenaard...

1. A plasma chamber for coating a sheet of fabric, such as a textile material, with a polymer layer, the plasma chamber havinga plurality of electrode layers each having a generally planar or plate like form arranged successively and substantially parallel to each other, within the plasma chamber,
wherein both electrode layers of at least one pair of adjacent electrode layers of the plurality of electrode layers are either radiofrequency electrode layers or ground electrode layers,
wherein one electrode layer of said pair of immediately adjacent electrode layers is disposed in use on one side of the sheet of fabric and another electrode layer of said pair of immediately adjacent electrode layers is disposed on an obverse side of the sheet of fabric,
wherein the remaining electrode layers are arranged on either side of a passage for receiving the sheet of fabric, and
wherein the plasma chamber further includes a plurality of rollers for guiding the sheet of fabric, in use, between said electrode layers thereby having coatings on both sides of the sheet of fabric.

US Pat. No. 10,366,867

TEMPERATURE MEASUREMENT FOR SUBSTRATE CARRIER USING A HEATER ELEMENT ARRAY

Applied Materials, Inc., ...

1. A method to determine a temperature profile of a substrate attached to an carrier during processing, the method comprising:measuring a first combined current load of each of a plurality of heating elements in the carrier, wherein the measuring a first combined current load comprises measuring when the plurality of heating elements are in an ON state except for a first heating element of the plurality of heating elements;
changing a power status of a first heating element of the plurality of heating elements, wherein changing a power status comprises changing the first heating element to an ON state;
measuring a second combined current load of each of the plurality of heating elements after changing the power status of the first heating element;
determining the difference between the first and second combined current loads;
determining a temperature of the first heating element using the difference; and
reverting the power status of the first heating element to that before the change and repeating changing power, measuring a current load, determining a difference, and determining a temperature for each of the other heating elements of the plurality to determine a temperature at each of the heating elements of the plurality of heating elements.

US Pat. No. 10,366,866

PLASMA DEVICE DRIVEN BY MULTIPLE-PHASE ALTERNATING OR PULSED ELECTRICAL CURRENT

AGC FLAT GLASS NORTH AMER...

1. A plasma source comprising:at least three electrodes, including a first electrode, a second electrode, and a third electrode, the at least three electrodes being arranged linearly such that a first distance between the first electrode and the second electrode is smaller than a second distance between the first electrode and the third electrode; and
a source of power capable of producing multiple output waves, including a first output wave, a second output wave, and a third output wave, wherein the first output wave and the second output wave are out of phase, the second output wave and the third output wave are out of phase, and the first output wave and the third output wave are out of phase;
wherein each electrode is electrically connected to the source of power such that the first electrode is electrically connected to the first output wave, the second electrode is electrically connected to the second output wave, and the third electrode is electrically connected to the third output wave;
wherein electrical current flows between the at least three electrodes that are out of electrical phase;
wherein each electrode alternately serves as anode and cathode when powered by the multiple output waves, and
wherein the plasma source is capable of generating a plasma between the electrodes, including a first plasma directly between the first electrode and the second electrode, a second plasma directly between the second electrode and the third electrode, and a third plasma directly between the first electrode and the third electrode.

US Pat. No. 10,366,865

GAS DISTRIBUTION SYSTEM FOR CERAMIC SHOWERHEAD OF PLASMA ETCH REACTOR

Lam Research Corporation,...

1. A gas delivery ring configured to supply process gas to an outer periphery of a showerhead of a plasma processing apparatus wherein a semiconductor substrate supported on a substrate support is subjected to plasma processing, the gas delivery ring comprising:a gas ring having a single gas inlet, a plurality of channels, and a plurality of gas outlets in fluid communication with the gas inlet via the channels;
the channels including a first channel connected to the gas inlet at a midpoint thereof with downstream ends of the first channel equidistant from the gas inlet and from each other, two second channels connected at midpoints thereof to the downstream ends of the first channel with downstream ends of the second channels equidistant from the downstream ends of the first channel and from each other, and four third channels connected at midpoints thereof to downstream ends of the second channels with downstream ends of the third channels connected to the gas outlets; and
a bottom ring and cover ring, the channels extending into an upper surface of the bottom ring and enclosed by the cover ring,
wherein an upper surface of the gas delivery ring includes mounting surfaces having mounting holes therein configured to receive fasteners of gas connection blocks which attach the gas delivery ring to the outer periphery of the showerhead, and wherein the channels are disposed within the same plane.

US Pat. No. 10,366,864

METHOD AND SYSTEM FOR IN-SITU FORMATION OF INTERMEDIATE REACTIVE SPECIES

ASM IP Holding B.V., Alm...

1. A method for providing intermediate reactive species to a reaction chamber of a reactor, the method comprising the steps of:providing a first gas to a remote plasma unit;
controlling a pressure of the remote plasma unit;
forming a plasma in the remote plasma unit;
forming intermediate reactive species from the first gas using the remote plasma unit, while maintaining steady-state conditions for the remote plasma unit; and
while maintaining the steady-state conditions in the remote plasma unit, pulsing the intermediate reactive species from the remote plasma unit to the reaction chamber by switching flow of the intermediate reactive species between the reaction chamber and a vacuum source.

US Pat. No. 10,366,863

DETECTOR SUPPLEMENT DEVICE FOR SPECTROSCOPY SETUP

1. A detector supplement device for integration in a spectroscopy setup, wherein the spectroscopy setup comprises a vacuum chamber, a light source, a sample irradiating a reflected photon beam and a charged particle beam in the same direction of propagation into a radiation detector, whereinthe detector supplement device comprises a Rogowski coil placeable inside the vacuum chamber between the sample and radiation detector, wherein the charged particle beam is guided through the hollow core of the Rogowski coil allowing synchronized measurements of electrical currents due to the charged particle beam correlated to the reflected photon beam, while irradiation of the reflected photon beam and the charged particle beam takes place in the same direction of propagation.

US Pat. No. 10,366,862

METHOD AND SYSTEM FOR NOISE MITIGATION IN A MULTI-BEAM SCANNING ELECTRON MICROSCOPY SYSTEM

KLA-Tencor Corporaton, M...

1. A multi-beam scanning electron microscopy apparatus comprising:a multi-beam scanning electron microscopy sub-system comprising:
a multi-beam electron beam source configured to generate a plurality of electron beams;
a sample stage configured to secure a sample;
an electron-optical assembly including a set of electron-optical elements configured to direct at least a portion of the plurality of electron beams onto a portion of the sample; and
a detector assembly configured to detect a plurality of electron signal beams emanating from the surface of the sample to form a plurality of images, each image associated with an electron beam of the plurality of electron beams, wherein a first image contains a first instance of a pattern element obtained from a first location of the sample and at least an additional image contains an additional instance of the pattern element at an additional location of the sample; and
a controller including one or more processors configured to execute a set of program instructions stored in memory for causing the one or more processors to:
receive the plurality of images from the detector assembly;
compare two or more of the images to identify one or more common positional noise components present in the two or more images; and
remove the identified one or more common positional noise components from one or more images of the plurality of images by shifting the one or more images by an amount equal in distance and opposite in direction to the one or more common positional noise components.

US Pat. No. 10,366,860

HIGH ASPECT RATIO X-RAY TARGETS AND USES OF SAME

FEI Company, Hillsboro, ...

1. An x-ray target, comprising:a substrate made from a soft x-ray producing material; and
a plurality of high aspect ratio structures made from a hard x-ray producing material and arranged into one or more grids or arrays,
wherein the high aspect ratio structures in one of the one or more grids or arrays are arranged as different elements of a Hadamard matrix structure.

US Pat. No. 10,366,859

ELECTROMAGNETIC INTERFERENCE CONTAINMENT FOR ACCELERATOR SYSTEMS

Varian Medical Systems, I...

1. An apparatus for attachment to a component of a microwave device, comprising:a cage;
a shield within the cage, wherein the shield is in a form of a container, and at least a majority of the shield is spaced away from an interior wall of the cage; and
a connector at the cage, wherein the connector is configured to connect to a cable connection, and wherein the connector is electrically connected to two terminals within the shield;
wherein a voltage between the two terminals has a first voltage value, and a voltage between the shield and the cage has a second voltage value that is higher than the first voltage.

US Pat. No. 10,366,858

ION BEAM DEVICE

Hitachi High-Technologies...

1. An ion beam apparatus comprising: a vacuum chamber; a gas field ion source that is installed in the vacuum chamber and has an emitter tip; an extraction electrode that is disposed to face the emitter tip; gas supply means for supplying a gas to the emitter tip; a focusing lens that focuses an ion beam emitted from the emitter tip; a deflector that deflects the ion beam that has passed through the focusing lens; and a secondary particle detector that irradiates a sample with the ion beam to detect secondary particles emitted from the sample,wherein the gas supply means includes a mixed gas chamber containing two or more types of gases including at least a hydrogen gas and a pipe that connects the vacuum chamber to the mixed gas chamber, and concentration of the hydrogen gas in the mixed gas chamber is equal to or lower than about 4% volume ratio of the hydrogen gas to a total volume of gas in the mixed gas chamber.

US Pat. No. 10,366,857

MAGNETRON FOR MICROWAVE OVEN

LG ELECTRONICS INC., Seo...

1. A magnetron for a microwave oven, comprising:a yoke forming a body of the magnetron;
an anode cylinder installed inside of the yoke;
a plurality of vanes that radially extends toward an axial center of the anode cylinder;
a filament positioned at the axial center of the anode cylinder;
a lower end shield positioned at a lower end of the filament, wherein an outer diameter of the lower end shield is about 80% to about 89% of a diameter of an inscribed circle formed by the plurality of vanes;
a center lead positioned at a center of the filament, wherein a lower end of the center lead extends downward through a center portion of the lower end shield; and
a side lead having an upper end which is connected to the lower end shield and spaced apart from the center lead.

US Pat. No. 10,366,856

NANOSCALE FIELD-EMISSION DEVICE AND METHOD OF FABRICATION

CALIFORNIA INSTITUTE OF T...

1. An apparatus including a first field-emission device, the first field-emission device comprising:a substrate;
a first electrode disposed on the substrate, the first electrode having a tip whose radius of curvature is at least 20 nm, wherein the first electrode comprises a first material having a first work function; and
a second electrode disposed on the substrate, the second electrode having a tip whose radius of curvature is at least 20 nm, wherein the second electrode comprises a second material having a second work function that is different than the first work function; and wherein the first electrode and second electrode define a first gap having a first environment that is characterized by an ionization potential;
wherein the first gap has a first separation that enables field emission of electrons from one of the first electrode and second electrode with an electron energy that is less than the ionization potential.

US Pat. No. 10,366,855

FUSE ELEMENT ASSEMBLIES

Micron Technology, Inc., ...

1. A fuse element assembly comprising:a cathode having a first end and an opposing second end; the cathode having a slit into the first end that spaces a first projecting portion from a second projecting portion, the first and second projecting portions being substantially parallel to each other and merging at a merge region; and
a fuse link extending from the merge region and beyond the second end of the cathode; and further comprising
a third projecting portion of the cathode and a fourth projecting portion of the cathode, the third and fourth projecting portions extending from the merge region toward the second end of the cathode on opposing sides of the fuse link.

US Pat. No. 10,366,854

CONTACTOR WITH COIL POLARITY REVERSING CONTROL CIRCUIT

TE CONNECTIVITY CORPORATI...

1. A contactor, comprising:a plurality of switches;
a first input circuit for receiving a power-up input signal;
a second input circuit for receiving a trip input signal;
a movable actuator mechanically coupled to switches in the plurality of switches, the actuator moveable between a tripped position and an operational position upon receipt of a power-up input signal on the first input circuit, and moveable between the operational position and the tripped position upon receipt of a trip input signal on the second input circuit;
a coil having first and second ends, the moveable actuator extending through the coil as a core, the coil capable of moving the actuator when either a power-up input signal is received by the first input circuit or a trip input signal is received by the second input circuit;
first and second switches coupled to respective first and second ends of the coil for reversing the polarity of the coil each occurrence of the actuator being actuated,
the first and second switches being switchable to include the coil in the second input circuit when the actuator is in the operational position, wherein when the trip input signal is received on the second input circuit the coil is energized to operate the actuator to transition to the tripped position, and
the first and second switches being switchable to include the coil in the first input circuit when the actuator is in the tripped position, wherein when the power-up input signal is received on the first input circuit the coil is energized to operate the actuator to transition to the operational position;
wherein as the actuator is being actuated the first and second switches change state in preparation to energize the coil to be magnetically polarized in an opposite polarization direction during a next subsequent actuation.

US Pat. No. 10,366,852

POWER RELAY FOR A VEHICLE

1. A power relay for a vehicle, comprising:a housing having a connector base and a housing can mounted on said connector base, said housing can being an injection molded component made of plastic;
two terminal studs for contacting a load circuit and inserted into said connector base;
a coil subassembly disposed in said housing and containing a solenoid coil, an armature, a force-transmission member and a contact bridge, said armature is coupled by said force-transmission member to said contact bridge and can be moved in said housing, under an action of a magnetic field generated by said solenoid coil, such that said contact bridge can be moved reversibly between a closed position, in which said contact bridge bridges said terminal studs in an electrically conducting manner, and an open position, in which said contact bridge is not in contact with said terminal studs; and
said coil subassembly further having a magnet yoke, which has a torsionally stable structure, which is accommodated nonrotatably in said housing can over an entire axial height of said housing can.

US Pat. No. 10,366,850

ELECTRONIC DEVICE INCLUDING KEY BUTTON

Samsung Electronics Co., ...

1. An electronic device comprising:a housing including a through hole;
a key button including a first extension movably inserted into the through hole;
a sealing member disposed between the through hole and the first extension; and
a separation prevention member coupled to the housing to prevent the key button from being separated from the housing, wherein the separation prevention member comprises a fixed portion fixed to an inner face of the housing and a second extension extended from the fixed portion and coupled to one or more recesses formed on a portion of the first extension of the key button, wherein, in order for the one or more recesses to receive the second extension, a width of the one or more recesses in a moving direction of the key button is larger than a thickness of the second extension.

US Pat. No. 10,366,849

METHOD TO CREATE A REDUCED STIFFNESS MICROSTRUCTURE

DUALITY REALITY ENERGY, L...

1. A method to create a reduced stiffness microstructure, comprising:forming a first buckled membrane along a first buckling direction; and
forming a second buckled membrane along a second buckling direction, the second buckling direction is opposite to the first buckling direction, the first buckled membrane is in contact with the second buckled membrane over a contact area, within an operating zone a stiffness of the reduced stiffness microstructure during contact is less than an absolute value of a stiffness of at least one of the first buckled membrane, before contact, and the second buckled membrane, before contact, when the contact area translates along either one of the first buckling directions and the second buckling direction.

US Pat. No. 10,366,848

METHOD FOR PRODUCING ELECTRIC SWITCHGEAR AND ELECTRIC SWITCHGEAR WITH ENHANCED SEAL-TIGHTNESS

SCHNEIDER ELECTRIC INDUST...

1. A method for producing low- or medium-voltage electrical switchgear comprising an electrical component, at least one electrical connector connected electrically to the electrical component and an enclosure delimiting a volume in which the electrical component is received, in which the electrical connector comprises a body which passes through the enclosure,the method comprising a step of fitting a seal in a peripheral groove formed in a wall of the body and
a step of injecting a plastic material around the body of the electrical connector and around the seal,
wherein the injection step consists of injecting the plastic material at a pressure causing an elastic crushing of the seal in the peripheral groove, and
a dimension of at least part of the peripheral groove, measured along a main axis of the electrical connector, is less than a greatest axial dimension of the seal.

US Pat. No. 10,366,847

DEVICE FOR GUIDING A SPRING IN A CONTROL MECHANISM AND ELECTRICAL PROTECTION APPARATUS COMPRISING SAME

SCHNEIDER ELECTRIC INDUST...

1. A device for guiding a spring belonging to a control mechanism having first and second axes of which at least one axis of the first and second axes is linked mechanically to an operating shaft, said device comprising:a compression spring having first and second ends;
a first slideable element including:
a guiding portion for guiding movement of the compression spring during compression and including first and second holes passing lengthwise through the guiding portion, and
a first base including (a) a notch configured to link the first base in an articulated manner to the first axis, and (b) a first bearing surface configured to abut the first end of the compression spring, wherein the first and second holes passing through the guiding portion continue through the first base;
a second slideable element including:
a second base including (a) a notch configured to link the second base in an articulated manner to the second axis, and (b) a second bearing surface configured to abut the second end of the compression spring, and
first and second parallel rods, each rod of the first and second parallel rods having (a) a fixed end being fixed onto said second base, and (b) a free end being mounted to slide through a respective one of the first and second holes and extend out of the first base.

US Pat. No. 10,366,846

REMOTE CONTROL DEVICE FOR AN ELECTRICAL DEVICE IN AN ELECTRICAL ENCLOSURE

SCHNEIDER ELECTRIC INDUST...

1. A remote control device for an electrical device in an electrical enclosure, said electrical enclosure including a bottom wall and side walls extending at right angles to the bottom wall and delimiting a housing, an electrical device being fixed, on the bottom wall, inside the housing, said remote control device comprising:a rotary control member that is fixed onto a wall of the enclosure outside the housing at a right angle to a face of the electrical device, the rotary control member remaining at a same orientation relative to the face of the electrical device when the electrical enclosure is open and when the electrical enclosure is closed, said rotary control member being selectively movable between first and second configurations,
a transmission system that mechanically links the rotary control member to a control lever of the electrical device, said control lever movable between the first and second positions, the transmission system moving the control lever between the first and second positions based on movement of the rotary control member between the first and second configurations,
wherein:
the rotary control member is mountable on one of the side walls of the housing and is rotationally mobile,
the transmission system comprises:
a first pinion, secured in rotation with the rotary control member about a first fixed axis, at right angles to the side walls,
a second pinion, meshed with the first pinion and rotationally mobile about a second fixed axis at right angles to the first fixed axis, said second pinion being coupled mechanically with the control lever to move said control lever between the first and second positions when the second pinion is moved in rotation.

US Pat. No. 10,366,845

MONITORED ADAPTABLE EMERGENCY OFF-SWITCH

1. An emergency off-switch for triggering an emergency switch-off function for safety-related shutdown of an electrical device, comprising:an actuator and at least two electrical contact points which can be connected to one another via a contact bridge, wherein a position of the contact bridge is influenced by the actuator such that the electrical contact points can selectively be opened or closed,
an active operating state, in which the emergency switch-off function can be triggered by moving the contact bridge, and a passive operating state, in which the emergency off-switch is non-functional,
a visualization unit having at least a first and a second display state, wherein the emergency off-switch is visually highlighted in the first display state, and the emergency off-switch is neutrally displayed in the second display state, the visualization unit being designed to adopt the first display state in the active operating state and to adopt the second display state in the passive operating state, and
a monitoring unit which monitors whether the visualization unit is in the first or in the second display state,
wherein, in the first display state, the visualization unit has a defined nominal current and the monitoring unit triggers the emergency switch-off function, when an actual current into the visualization unit is less than the defined nominal current.

US Pat. No. 10,366,843

CARBON FIBER AND PARYLENE STRUCTURAL CAPACITOR

1. A method of manufacturing a structural capacitor comprising:(a) forming a first layer made of a nonconductive structural material into a desired shape of a structural component of an object;
(b) placing a conductive layer including carbon fiber on the first layer;
(c) placing parylene directly on the conductive layer to form a dielectric layer; and
(d) repeating steps (b) and (c) until a desired property is achieved.

US Pat. No. 10,366,842

DYE-SENSITIZED SOLAR CELL AND METHOD FOR MANUFACTURING THEREOF

SHARP KABUSHIKI KAISHA, ...

1. A dye-sensitized solar cell comprising;a substrate,
two or more light transmitting conductive layers provided on the substrate,
a first light transmitting conductive layer which is one of the two or more light transmitting conductive layers,
a second light transmitting conductive layer which is one of the two or more light transmitting conductive layers and provided adjacent to the first light transmitting conductive layer and on the substrate,
a first insulating layer provided on the substrate between the first light transmitting conductive layer and the second light transmitting conductive layer,
a first porous semiconductor layer including first semiconductor particles and a first dye, and provided on the first light transmitting layer,
a second porous semiconductor layer including second semiconductor particles, and provided on the first porous semiconductor layer, and
a first counter electrode including a counter conductive layer and provided on the second porous semiconductor layer and the insulating layer, and the counter conductive layer connected to the second light transmitting conductive layer.

US Pat. No. 10,366,840

CAPACITOR WITH MULTIPLE ELEMENTS FOR MULTIPLE REPLACEMENT APPLICATIONS

American Radionic Company...

1. An apparatus comprising:a case having an elliptical cross-section capable of receiving a plurality of capacitive devices, one or more of the capacitive devices providing at least one capacitor having a first capacitor terminal and a second capacitor terminal, wherein a first of the plurality of capacitive devices is affixed to the case by a first bracket and a second of the plurality of capacitive devices is affixed to the case by a second bracket, wherein the first bracket includes a curved middle portion that has a shape substantially similar to a shape of an outer surface of the first of the plurality of capacitive devices, and the second bracket includes a curved middle portion that has a shape substantially similar to a shape of an outer surface of the second of the plurality of capacitive devices;
a cover assembly comprising:
a deformable cover mountable to the case,
a common cover terminal having a contact extending from the deformable cover,
at least three capacitor cover terminals, each of the at least three capacitor cover terminals having at least one contact extending from the deformable cover, wherein the deformable cover is configured to displace at least one of the at least three capacitor cover terminals upon an operative failure of at least one of the plurality of capacitive devices, and
at least four insulation structures, wherein at least one of the at least four insulation structures is associated with one of the at least three capacitor cover terminals;
a first conductor capable of electrically connecting the first capacitor terminal of a capacitor provided by one of the plurality of capacitive devices to one of the at least three capacitor cover terminals; and
a second conductor capable of electrically connecting the second capacitor terminal of the capacitor provided by the one of the plurality of capacitive devices to the common cover terminal.

US Pat. No. 10,366,839

ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. An electronic component comprising:a multilayer ceramic capacitor including a capacitor body and external electrodes disposed on opposite ends of the capacitor body in a first direction, respectively; and
an interposer including an interposer body including a woven glass fiber material and external terminals disposed on opposite ends of the interposer body in the first direction, respectively,
wherein an angle between a weaving direction of the woven glass fiber material and the first direction is 0° to 10° or 80° to 90°.

US Pat. No. 10,366,838

LAMINATED CERAMIC ELECTRONIC COMPONENT AND METHOD FOR MANUFACTURING SAME

MURATA MANUFACTURING CO.,...

1. A method for producing a laminated ceramic electronic component, the method comprising:preparing a laminate having a plurality of dielectric layers and a plurality of internal electrode layers respectively laminated, and having a first main surface and a second main surface opposed to each other in a lamination direction, a first side surface and a second side surface opposed to each other in a width direction orthogonal to the lamination direction, and a first end surface and a second end surface opposed to each other in a length direction orthogonal to the lamination direction and the width direction;
preparing an electroconductive paste containing Cu particles coated with an oxide of Al or Zr; and
applying the electroconductive paste onto the first end surface and the second end surface of the laminate.

US Pat. No. 10,366,836

ELECTRONIC COMPONENT STRUCTURES WITH REDUCED MICROPHONIC NOISE

KEMET Electronics Corpora...

1. An electronic structure comprising:a first conductive metal layer and a second conductive metal layer;
a first compliant non-metallic layer on said first conductive metal layer wherein said first compliant non-metallic layer comprises a gap wherein said gap is a via through said first compliant non-metallic layer and said gap is smaller than said first conductive metal layer;
an electronic component comprising a first external termination of a first polarity and a second external termination of a second polarity wherein said gap is smaller than said first external termination;
a transient liquid phase sintering adhesive in electrical contact with said first external termination and said first conductive metal layer wherein said transient liquid phase sintering adhesive extends through said gap;
wherein said electronic component is a multilayered ceramic capacitor comprising at least one floating electrode wherein said floating electrode is selected from the group consisting of an external floating electrode coplanar with at least one first electrode of said first electrodes and an internal floating electrode coplanar with at least one first electrode of said first electrodes; and
wherein said multilayered ceramic capacitor further comprises a shock absorbing conductor wherein said shock absorbing conductor has a shape selected from S shaped, and Z shaped.

US Pat. No. 10,366,835

PLATED TERMINATIONS

AVX Corporation, Fountai...

1. A method of electrically connecting a plurality of interior plates of a multilayer ceramic capacitor having a first surface, a second surface opposite the first surface, and additional exterior surfaces, the plurality of interior plates including each of a plurality of electrode layers and a plurality of anchor tabs, edges of at least some of the plurality of the interior plates being exposed upon at least a portion of the first surface of the ceramic capacitor, and where edges of at least some of the plurality of interior plates are also exposed upon at least a portion of the second surface of the capacitor, the method comprising:electrolessly plating a first layer of electrically-conductive first metal directly onto the first surface including where the edges of the plurality of interior plates are exposed upon the first surface, the first layer of electrically-conductive first metal on the first surface electrically connecting the edges of the plurality of interior plates that are exposed upon the first surface; and
concurrently electrolessly plating a first layer of electrically-conductive first metal directly onto the second surface including where the edges of the plates are exposed upon the second surface, the first layer of electrically-conductive first metal on the second surface electrically connecting the edges of the plurality of interior plates that are exposed upon the second surface,
wherein each of the first layer of electrically-conductive first metal on the first surface and the first layer of electrically-conductive first metal on the second surface is not deposited on any of the additional surfaces which meet the first surface, and
wherein the distance between adjacent exposed edges of adjacent plates in a column is not greater than about ten microns.

US Pat. No. 10,366,834

CERAMIC ELECTRONIC COMPONENT

SAMSUNG ELECTRO-MECHANICS...

1. A ceramic electronic component, comprising:a body including a dielectric layer and first and second internal electrodes disposed to oppose each other with the dielectric layer interposed therebetween, first and second surfaces opposing each other, third and fourth surfaces connected to the first and second surfaces and opposing each other, and fifth and sixth surfaces connected to the first to fourth surfaces and opposing each other;
a first external electrode including a first electrode layer disposed on the third surface of the body and electrically connected to the first internal electrode, a first inorganic insulating layer disposed on the first electrode layer, and a first plating layer disposed on the first inorganic insulating layer;
a second external electrode including a second electrode layer disposed on the fourth surface of the body and electrically connected to the second internal electrode, a second inorganic insulating layer disposed on the second electrode layer, and a second plating layer disposed on the second inorganic insulating layer; and
a third inorganic insulating layer disposed on the first, second, fifth, and sixth surfaces of the body and connected to the first and second inorganic insulating layers,
wherein the first, second, and third inorganic insulating layers comprise at least one selected from the group of SiO2, Al2O3 and ZrO2, and the first, second, and third inorganic insulating layers have a thickness within a range from 20 nm to 150 nm, and
wherein the first and second inorganic insulating layers have an, opening formed therein, and the first and second plating layers are in direct contact with the first and second electrode layers through the opening, respectively.

US Pat. No. 10,366,833

MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF MULTILAYER CERAMIC CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer ceramic capacitor comprising:a multilayer structure in which each of a plurality of ceramic dielectric layers and each of a plurality of internal electrode layers including a ceramic co-material are alternately stacked,
wherein a concentration of Mg in a ceramic grain that is included in the ceramic dielectric layer and contacts to the internal electrode layer is smaller than that in the co-material.

US Pat. No. 10,366,832

CAPACITOR AND ELECTRONIC DEVICE HAVING A PLURALITY OF SURFACE ELECTRODES ELECTRICALLY CONNECTED TO EACH OTHER BY AN INTERMEDIATE ELECTRODE

MURATA MANUFACTURING CO.,...

1. A capacitor comprising:a substrate having a first main surface;
a first inner electrode and a second inner electrode disposed above a side of the first main surface, the second inner electrode being arranged so as to face the first inner electrode;
a dielectric layer between the first inner electrode and the second inner electrode;
a first intermediate electrode connected to the first inner electrode at a plurality of first locations;
a plurality of first surface electrodes which are each electrically connected to the first intermediate electrode; and
a second surface electrode electrically connected to the second inner electrode at a plurality of second locations,
wherein a first layer of the capacitor containing the first inner electrode and a second layer of the capacitor containing the first intermediate electrode have different electrode patterns.

US Pat. No. 10,366,831

MULTILAYER CAPACITOR

TAIYO YUDEN CO., LTD., T...

1. A multilayer capacitor having:a laminate comprising a stack of multiple dielectric layers made of dielectric material and having a first principal face and a second principal face on an opposite side of the first principal face; and
multiple internal electrode layers whose primary component is Ni and which are arranged in parallel with the first principal face and second principal face inside the laminate in such a way that they alternate from opposing sides with the dielectric layers placed in between; wherein,
of the internal electrode layers, at least the internal electrode layer closest to the first principal face and internal electrode layer closest to the second principal face contain in its entirety at least one metal element selected from the group consisting of Pt, Ru, Rh, Re, Ir, Os, and Pd;
of the multiple internal electrode layers, the internal electrode layer closest to the first principal face has a distance of 30 ?m or less from the first principal face; and
of the multiple internal electrode layers, the internal electrode layer closest to the second principal face has a distance of 30 ?m or less from the second principal face,
wherein internal electrode layers away from the first and second principal faces, among the multiple internal electrode layers, contain none of any metal element selected from the group consisting of Pt, Ru, Rh, Re, Ir, Os, and Pd.

US Pat. No. 10,366,830

SURFACE MOUNT ELECTRONIC COMPONENT

MURATA MANUFACTURING CO.,...

1. A surface mount electronic component comprising:an element including a dielectric layer including a first main surface and a second main surface;
a first external electrode disposed on the first main surface;
a second external electrode disposed on the second main surface;
a first metal terminal connected to the first external electrode;
a second metal terminal connected to the second external electrode; and
an exterior material covering at least a portion of the element, the first and second external electrodes, and the first and second metal terminals; wherein
upper and lower surfaces of the exterior material are flat or substantially flat;
the first metal terminal includes:
a first bonding portion connected to the first external electrode;
a first extending portion connected to the first bonding portion and extending in a direction parallel or substantially parallel to the first main surface with a space from the first main surface;
a second extending portion connected to the first extending portion and extending towards the element;
a third extending portion connected to the second extending portion and extending in the direction parallel or substantially parallel to the first main surface;
a fourth extending portion connected to the third extending portion and extending in a mounting direction; and
a first mounting portion connected to the fourth extending portion and mounted on a mounting substrate;
the second metal terminal includes:
a second bonding portion connected to the second external electrode;
a fifth extending portion connected to the second bonding portion and extending in a direction parallel or substantially parallel to the second main surface with a space from the second main surface;
a sixth extending portion connected to the fifth extending portion and extending towards the element;
a seventh extending portion connected to the sixth extending portion and extending in the direction parallel or substantially parallel to the second main surface;
an eighth extending portion connected to the seventh extending portion and extending in the mounting direction; and
a second mounting portion connected to the eighth extending portion and mounted on the mounting substrate;
in the first bonding portion, a distal end of the first bonding portion is disposed in a direction away from the first main surface from an intermediate portion of the first bonding portion towards the distal end, and the first bonding portion is in surface contact with the first external electrode at the intermediate portion located on an opposite side of the distal end;
a first cut-out portion is provided in a portion in which the second extending portion of the first metal terminal and the third extending portion of the first metal terminal intersect with each other;
the second bonding portion includes a bifurcated distal end and is in surface contact with the second external electrode at the bifurcated portion;
a second cut-out portion is provided in the fifth extending portion of the second metal terminal;
a third cut-out portion is provided in a portion in which the sixth extending portion of the second metal terminal and the seventh extending portion of the second metal terminal intersect with each other; and
the first, second and third cut-out portions are covered with the exterior material.

US Pat. No. 10,366,829

COIL ASSEMBLY FOR NON-CONTACT CHARGING

OMRON AUTOMOTIVE ELECTRON...

1. A coil assembly for non-contact charging which has a power supplying surface facing a power receiving device and is provided in a power transmission device which wirelessly transmits power to the power receiving device, the coil assembly comprising:a circuit board;
a first coil positioned directly onto the circuit board;
a second coil positioned as close as, or farther than, the first coil from the power supplying surface; and
a single magnetic body that:
is positioned farther than the second coil from the power supplying surface, overlaps with the second coil, and
does not overlap with the first coil when seen from the power supplying surface.

US Pat. No. 10,366,828

APPARATUS FOR WIRELESS POWER TRANSFER, APPARATUS FOR WIRELESS POWER RECEPTION AND COIL STRUCTURE

KOREA ELECTROTECHNOLOGY R...

1. A wireless power transmitting device, comprising:a bowl-shaped transmitting device body; and
a transmitting coil unit for wirelessly transmitting power to a receiving device,
wherein the transmitting coil unit comprises:
a multi-loop coil unit wound flatways in a bottom of the transmitting device body; and
a helical coil unit extending from the maximum radius of the multi-loop coil unit, wound around a side wall of the transmitting device body, and wound to increase a radius of a coil loop in a direction to an upper part,
wherein the whole or a part of the receiving device is located in an interior area defined by the transmitting device body, and receives wireless power from the wireless power transmitting device, and
wherein the wireless power transmitting device generates a magnetic field that is formed in a wider area than the sum of magnetic fields independently generated by the helical coil unit and the multi-loop coil unit.

US Pat. No. 10,366,827

IGNITION COIL FOR INTERNAL COMBUSTION ENGINE

DENSO CORPORATION, Kariy...

1. An ignition coil for an internal combustion engine comprising:a coil main body portion having a primary coil and a secondary coil magnetically coupled to each other;
a cylindrical connecting portion for connecting the coil main body portion and a spark plug; and
a conducting member disposed inside the connecting portion and electrically connecting the coil main body portion and the spark plug; wherein
a convex surface forming portion, which is a portion constituting an inner peripheral convex surface, an inner peripheral surface of which projects toward an inner peripheral side, is disposed in the connecting portion;
the convex surface forming portion has an outer peripheral concave surface, an outer peripheral surface of which is recessed toward the inner peripheral side;
the connecting portion has a boundary portion which is a boundary between the convex surface forming portion and other portions in an axial direction;
in the convex surface forming portion, at least a part of a region where the outer peripheral concave surface is formed has a portion having an area, in a cross-section orthogonal to the axial direction, equal to or smaller than an area of a cross-section orthogonal to the axial direction in the boundary portion, and a thickness of the convex surface forming portion is equal to or thicker than a thickness of the boundary portion; and
a thickness of the convex surface forming portion is equal to or thicker than a thickness of the boundary portion.

US Pat. No. 10,366,825

BARRIER ARRANGEMENT BETWEEN TRANSFORMER COIL AND CORE

ABB Schweiz AG, Baden (C...

1. An insulation barrier for a transformer, comprising:an inner portion including a first cylindrical body and a radially outwardly extending flange extending from a first end of the first cylindrical body; and
an outer portion including a second cylindrical body and a radially inwardly extending flange extending from a second end of the second cylindrical body in overlapping relation with the radially outwardly extending flange of the inner portion, wherein the first and second cylindrical body portions are spaced from one another to form a space sized to receive a high voltage coil between the first and second cylindrical bodies.

US Pat. No. 10,366,824

DIRECT MOUNTING BRACKET

TRENCH LIMITED, Ontario ...

1. An air core reactor for use in an electric power transmission and distribution system or in an electric power system of an electrical plant, the air core reactor comprising:an electrically insulated support structure;
a coil of windings supported by the electrically insulated support structure; and
an insulator mounting bracket configured as an interface between the coil and the electrically insulated support structure, wherein the insulator mounting bracket includes:
a body that comprises a closed shape in a form of an annulus having a plurality of holes and the body comprises first and second grooves to receive a spider,
a mounting flange attached to the body, and
a plurality of attachments that are composite bands being threaded through the plurality of holes.

US Pat. No. 10,366,821

COMMON MODE NOISE FILTER

Panasonic Intellectual Pr...

1. A common mode noise filter comprising:a first insulating layer;
a second insulating layer formed under the first insulating layer;
a first coil including a first coil conductor and a second coil conductor, the first coil conductor being electrically connected to the second coil conductor;
a second coil including a third coil conductor and a fourth coil conductor, the third coil conductor being electrically connected to the fourth coil conductor; and
a third coil including a fifth coil conductor and a sixth coil conductor, the fifth coil conductor being electrically connected to the sixth coil conductor,
wherein the first coil, the second coil, and the third coil are electrically independent of one another,
the first coil conductor, the third coil conductor, and the fifth coil conductor are formed side by side on the first insulating layer in a spiral fashion such that the first coil conductor, the third coil conductor, and the fifth coil conductor are sequentially positioned from an outer side of the first insulating layer,
the first coil conductor, the third coil conductor, and the fifth coil conductor have regions disposed in parallel to one another,
the second coil conductor, the fourth coil conductor, and the sixth coil conductor are formed side by side on the second insulating layer such that the fourth coil conductor, the sixth coil conductor, and the second coil conductor are sequentially positioned from an outer side of the second insulating layer,
the second coil conductor, the fourth coil conductor, and the sixth coil conductor have regions disposed in parallel to one another,
the first coil conductor and the fourth coil conductor have regions overlapping each other as seen from a top view,
the third coil conductor and the sixth coil conductor have regions overlapping each other as seen from a top view, and
the fifth coil conductor and the second coil conductor have regions overlapping each other as seen from a top view.

US Pat. No. 10,366,820

THIN FILM INDUCTOR

TDK CORPORATION, Tokyo (...

1. A thin film inductor comprising:a coil part formed of at least one coil conductor layer and having terminal electrodes provided at both ends thereof;
a first insulating layer configured to cover the coil part; and
a second insulating layer configured to cover the first insulating layer and having a higher Young's modulus than the first insulating layer, the second insulating layer enclosing an entire outer surface of the first insulating layer, other than in a region of the first insulating layer covered by the terminal electrodes.

US Pat. No. 10,366,819

COIL COMPONENT AND METHOD OF MANUFACTURING THE SAME

TAIYO YUDEN CO., LTD., T...

1. A coil component comprising:a preformed coil that is formed of a winding part which winds a coated conductive wire continuously and spirally in an axial direction and includes an inner circumferential surface, an outer circumferential surface, and a principle face of one end portion and a principle face of the other end portion in the axial direction, and of a pair of leader parts which extends outwardly from the winding part;
a first core member that includes a shaft part disposed inside the inner circumferential surface, a side wall portion disposed in at least a portion of the outer circumferential surface, and a connection portion which is disposed such that a first gap is formed between the principle face of the one end portion and the connection portion, and through which the shaft part is connected to the side wall portion, and that contains metal magnetic grains; and
a second core member which is disposed such that a second gap is formed between the principle face of the other end portion and the second core member which contains metal magnetic grains and is provided with an adhesive, wherein:
the pair of leader parts are disposed in a portion where the side wall portion of the first core member is not formed on the outer circumferential surface of the winding part, and the pair of leader parts are not covered by the side wall portion,
the coil component further comprises a pair of terminal electrodes formed at respective ends of the leader parts in a manner extending in a same direction and facing the principle face of the other end portion of the winding part, wherein a peripheral portion of the second core member including a portion of the second gap provided with the adhesive is in direct contact with and fitted between the principle face of the other end portion of the winding part and the pair of terminal electrodes,
the second core member is of an E-type wherein the second core member includes a second shaft part facing and axially aligned with the shaft part of the first core member, a second side wall portion facing and axially aligned with the side wall portion of the first core member, and a second connection portion connecting the second shaft part and the second side wall portion, and
the first gap formed between the principle face of the one end portion of the winding part and the connection portion of the first core member is constituted by a void.

US Pat. No. 10,366,817

APPARATUS AND METHOD FOR PASSIVE COOLING OF ELECTRONIC DEVICES

General Electric Company,...

1. An electronic device assembly comprising:a heat dissipation member; and
a dielectric two-phase heat transfer device comprising:
an evaporator region coupled in thermal communication with a hot region of a heat producing component; and
a condenser region coupled in thermal communication with said heat dissipation member, said dielectric two-phase heat transfer device fabricated from a dielectric material,
wherein the heat producing component comprises a secondary winding portion of a transformer assembly, the secondary winding portion further comprising:
an upper conductive secondary turn; and
a lower conductive secondary turn,
wherein the dielectric two-phase heat transfer device extends about 180 degrees around the upper conductive secondary turn and the lower conductive secondary turn opposite a plurality of leads.

US Pat. No. 10,366,816

SOLENOID DRIVE DEVICE

HONDA MOTOR CO., LTD., T...

1. A solenoid drive device comprising:a first solenoid drive circuit including a first solenoid, a first switching element configured to perform duty control of an application voltage of the first solenoid, and a first current detection element configured to detect a first drive current supplied to the first solenoid;
a second solenoid drive circuit including a second solenoid, a second switching element configured to perform duty control of an application voltage of the second solenoid, and a second current detection element configured to detect a second drive current supplied to the second solenoid; and
a control element configured to change the first drive current and the second drive current by performing on/off duty control of the first switching element and the second switching element,
wherein the solenoid drive device includes a selection circuit configured to select either one of a first current detection signal outputted from the first current detection element and a second current detection signal outputted from the second current detection element,
wherein the control element comprises:
a duty control element configured to supply a selection command signal selecting either one of the first current detection signal and the second current detection signal to the selection circuit, acquire values of the first drive current and the second drive current based on a selection detection signal outputted from the selection circuit, and perform the on/off duty control depending on the acquired values of the first drive current and the second drive current; and
a failure determination element configured to perform failure determination with the selection circuit, the first solenoid drive circuit, and the second solenoid drive circuit as determination targets based on change characteristics of the selection detection signal,
wherein the duty control element performs the on/off duty control of the first switching element in the same control cycle as on/off duty control of the second switching element, and sets on/off switching direction of the first switching element at a start time of one control cycle and on/off switching direction of the second switching element reversely from each other, the on/off switching direction including a switching direction from on to off and a switching direction from off to on, and
wherein the failure determination element performs the failure determination based on change characteristics of the selection detection signal in a specified period when on/off states of the first switching element and the second switching element are different from each other.

US Pat. No. 10,366,815

PERMANENT MAGNET DRIVE ON-LOAD TAP-CHANGING SWITCH

1. A permanent magnet drive on-load tap-changing switch, comprising:a changing switch circuit, the changing switch circuit comprising an odd-numbered tap-changing circuit and an even-numbered tap-changing circuit that are structurally identical;
the odd-numbered tap-changing circuit and the even-numbered tap-changing circuit comprising working contactors and dual-contact synchronous transition contactors consisting of primary contactors and secondary contactors;
the working contactors being connected to the primary contactors through trigger transmitters and transition resistors;
a primary contactor of a tap-changing circuit being connected to a secondary contactor of another tap-changing circuit through a high-voltage thyristor;
a trigger transmitter being configured to provide a trigger current to the high-voltage thyristor connected with the secondary contactor of a same tap-changing circuit, wherein:
the working contactors and the dual-contact synchronous transition contactors directly face moving contactors;
the moving contactors are connected in parallel to each other;
moving contactor permanent magnets are bijectively connected to the moving contactors;
the moving contactor permanent magnets directly face, on an other extremity thereof, a moving contactor driving mechanism, the moving contactor driving mechanism comprising a moving permanent magnet which moves to change a force acting on the moving contactor permanent magnets to allow the moving contactors to get contact with or depart from the working contactors and the dual-contact synchronous transition contactors.

US Pat. No. 10,366,814

PERMANENT MAGNET

TDK CORPORATION, Tokyo (...

1. A permanent magnet with a composition ratio of RXT(100-X-Y)CY comprising a main phase with Nd5Fe17 crystal structure, wherein:R is one or more rare earth elements including Sm, and the rare earth elements are Sm, Y, La, Pr, Ce, Nd, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu; and
T is one or more transition metal elements including Fe or a combination of Fe and Co; and
23.2?X(at %)?37.1, 6.0?Y(at %)?14.7, 1.51?(100-X-Y)/X?2.92.

US Pat. No. 10,366,813

HIGH-PRECISION ADDITIVE FORMATION OF ELECTRICAL RESISTORS

1. A method of forming an electrical resistor having a target electrical resistance by additive manufacturing comprising the steps of:forming an electrically resistive layer on a substrate;
measuring an electrical resistance-related parameter of the electrically resistive layer and determining from the electrical resistance-related parameter a target length of the electrically resistive layer corresponding to the target electrical resistance; and
forming a first electrically conductive terminal and a second electrically conductive terminal contacting the electrically resistive layer, said first and second electrically conductive terminals being separated by a distance corresponding to the target length, such that an electrical resistance of a portion of the electrically resistive layer extending between the first electrically conductive terminal and the second electrically conductive terminal corresponds to the target electrical resistance.

US Pat. No. 10,366,812

CONNECTION STRUCTURE OF SUPERCONDUCTING WIRES

Furukawa Electric Co., Lt...

1. A connection structure of superconducting wires comprising:a plurality of superconducting wires are overlapped and connected with each other, each of the plurality of superconducting wires including a substrate and a superconducting layer that are laminated, a non-superconductor being provided at a part of a surface of the superconducting layer of at least one of the superconducting wires and protruding from the surface,
wherein a part of the non-superconductor is embedded in the surface of the superconducting layer,
the superconducting layer has a multilayer structure including an uppermost superconducting layer and at least one superconducting layer other than the uppermost superconducting layer, the uppermost superconducting layer having a thickness greater than a thickness of the at least one superconducting layer other than the uppermost superconducting layer, and
the part of the non-superconductor is embedded in the uppermost superconducting layer and a remaining part of the non-superconductor is protruded from the surface of the superconducting layer.

US Pat. No. 10,366,811

PARALLEL PAIR CABLE

SUMITOMO ELECTRIC INDUSTR...

1. A parallel pair cable, comprising:a pair of insulated wires arranged to be in contact with each other, parallel to each other, and not twisted;
a first resin tape wrapped around the pair of insulated wires;
a shield tape comprising a metal layer longitudinally folded on the outside of the first resin tape;
a drain wire outside the shield tape, wherein the drain wire is arranged to be in electrical contact with the metal layer of the shield tape;
a jacket layer provided around the shield tape and the drain wire; and
a conductive tape helically wrapped on the outside of the shield tape,
wherein the drain wire is arranged on the outside of the conductive tape so that the drain wire is electrically connected to the conductive tape and the shield tape; and
wherein the jacket layer is provided around the conductive tape and the drain wire.

US Pat. No. 10,366,810

EDGE INSULATION STRUCTURE FOR ELECTRICAL CABLE

3M Innovative Properties ...

1. An electrical cable comprising:a plurality of substantially parallel conductors extending along a length, and arranged along a width, of the cable, each conductor substantially surrounded by a shield;
first and second layers disposed on opposite sides of the conductors, each layer folded along the length of the cable toward the other layer, the folds defining first portions of the first and second layers facing each other and comprising a longitudinal edge of the cable, and second portions of the first and second layers facing away from each other; and
a bonding material bonding the first portions of the first and second layers to each other along the length of the cable.

US Pat. No. 10,366,809

INSULATED WIRE, COIL, AND ELECTRIC OR ELECTRONIC EQUIPMENT

FURUKAWA ELECTRIC CO., LT...

1. An insulated wire comprising a thermosetting resin layer on the outer periphery of a conductor, and a thermoplastic resin layer on the outer periphery of the thermosetting resin layer,wherein a total thickness of the thermosetting resin layer and the thermoplastic resin layer is 100 ?m or more and 250 ?m or less, and a degree of orientation of a thermoplastic resin in the thermoplastic resin layer, that is calculated by the following Formula 1, is 20% or more and 90% or less;
Formula 1 Degree of orientation H (%)=[(360??Wn)/360]×100
Wn: A half width of orientation peak in the azimuth angle intensity distribution curve by X-ray diffraction
n: the number of orientation peak at a ? angle of 0° or more and 360° or less.

US Pat. No. 10,366,808

HIGH-VOLTAGE APPARATUS AND METHOD FOR PRODUCING SAME

Siemens Aktiengesellschaf...

1. A high-voltage device, comprising:an internal conductor;
an insulating body surrounding said internal conductor along a longitudinal direction, said insulating body including:
insulating layers configured from a synthetic material that is impregnated with a resin; and
electrically conductive control inserts for providing field control, said electrically conductive control inserts being disposed in a concentric manner around said internal conductor and being spaced apart from one another by means of said insulating layers, at least one of said control inserts is a conductive base layer; and
a contact-making device, at least one of said control inserts is a contact insert that is connected in an electric manner to said internal conductor by means of said contact-making device, said contact-making device having a contact element configured from an electrically conductive material that is connected in an electrical manner to said contact insert, said contact element being fixed by means of an adhesive to said conductive base layer being in electrical contact with said internal conductor.

US Pat. No. 10,366,807

RESIN COMPOSITION FOR AUTOMOTIVE CABLE MATERIAL AND CABLE USING THE SAME

Hyundai Motor Company, S...

1. A resin composition comprising:a mixture of a base resin and a magnesium hydroxide flame retardant;
an antioxidant; and
a lubricant,
wherein the resin composition comprises an amount of about 2 to 5 parts by weight of the antioxidant and an amount of about 0.5 to 2 parts by weight of the lubricant with respect to 100 parts by weight of the mixture,
wherein the mixture comprises an amount of about 40 to 60% by weight of the base resin and an amount of about 60 to 40% by weight of the magnesium hydroxide flame retardant, based on the total weight of the mixture,
wherein a surface of the magnesium hydroxide flame retardant is treated with silane or aliphatic or polymeric fatty acid,
wherein the base resin comprises 100 parts by weight of a high crystalline polypropylene resin, an amount of about 5 to 10 parts by weight of a modified polypropylene and an amount of about 15 to 20 parts by weight of an elastomer,
wherein the high crystalline polypropylene resin comprises an amount of about 60 to 90% by weight of a high crystalline homo polypropylene resin and an amount of about 10 to 40% by weight of a high crystalline block polypropylene resin, based on the total weight of the high crystalline polypropylene resin, and
wherein the base resin further comprises maleic acid in an amount of about 0.1 to 3 parts by weight with respect to 100 parts by weight of the base resin; and an initiator.

US Pat. No. 10,366,806

VEHICLE ELECTRIC WIRE AND WIRE HARNESS USING THE SAME

YAZAKI CORPORATION, Mina...

1. A vehicle electric wire comprising:an electrical insulation coating layer which contains: a vinyl chloride resin; a plasticizer which includes one type or two or more types selected from a trimellitic acid plasticizer and a pyromellitic acid plasticizer; a compound containing a lanthanoid which is at least one of lanthanum oxide and lanthanum hydroxide; a stabilizer; and a filler; and
an electrical conductor which is coated with the electrical insulation coating layer,
wherein, in the electrical insulation coating layer, with respect to 100 parts by mass of the vinyl chloride resin, a content of the plasticizer is 25 to 49 parts by mass, a content of the stabilizer is 1 to 15 parts by mass, and a content of the compound containing the lanthanoid is 1 to 15 parts by mass, and
when dynamic viscoelasticity measurement using a dynamic viscoelasticity measurement device is performed on the electrical insulation coating layer at 0.5 Hz in frequency and under a temperature rise condition of 2° C./minute in temperature rise speed in a single cantilever measurement mode, a storage modulus at 140° C. is 0.1 MPa or more.

US Pat. No. 10,366,805

INSULATED WINDING WIRE ARTICLES HAVING CONFORMAL COATINGS

Essex Group, Inc., Fort ...

1. An article formed from an insulated winding wire, the article comprising:an insulated winding wire having a cross-sectional area greater than or equal to 0.823mm2 and formed into a predefined shape comprising at least one bend, the insulated winding wire comprising a conductor and insulation formed around the conductor, the insulation comprising at least one of polyimide or polyamideimide; and
a coating comprising parylene formed around the insulated winding wire, the parylene comprising at least one of parylene HT, parylene AF-4, or parylene F.

US Pat. No. 10,366,803

METAL OXIDE THIN FILM, METHOD FOR DEPOSITING METAL OXIDE THIN FILM AND DEVICE COMPRISING METAL OXIDE THIN FILM

Plansee SE, Reutte (AT)

1. A metal oxide thin film, comprising a film formed of ?-MoO3 having a monoclinic ?-MoO3 crystal structure and including at least one doping element selected from the group consisting of Re, Mn, and Ru.

US Pat. No. 10,366,802

COMPOSITIONS INCLUDING NANO-PARTICLES AND A NANO-STRUCTURED SUPPORT MATRIX AND METHODS OF PREPARATION AS REVERSIBLE HIGH CAPACITY ANODES IN ENERGY STORAGE SYSTEMS

1. A lithium-ion battery anode electrode, comprising:a current collector having a planar surface;
a plurality of a first nanomaterial selected from the group consisting of carbon nanotube, carbon nanowire, carbon nanorod and mixtures thereof, having a first end and a second end, the first end deposited on the planar surface of the current collector, each of said plurality of the first nanomaterial being vertically aligned with one another, perpendicular to the planar surface of the current collector, and exhibiting defined spacing between one another;
a plurality of a second nanomaterial deposited on a surface of each of the plurality of the first nanomaterial, the second nanomaterial composed of an element selected from the group consisting of metallic, metalloid, non-metallic and mixtures thereof, the second nanomaterial as-deposited in a form selected from the group consisting of nano-particle, nano-cluster, droplet and mixtures thereof, each of the plurality of the second nanomaterial exhibiting defined spacing between one another,
wherein the surface of the plurality of a first nanomaterial underlying the plurality of a second nanomaterial has excess amorphous carbon; and
an interfacial layer comprising the amorphous carbon, formed in-situ on the plurality of a first nanomaterial underlying said plurality of a second nanomaterial.

US Pat. No. 10,366,801

ELECTRIC CURRENT TRANSMISSION CABLE AND METHOD OF FABRICATING SUCH A CABLE

1. An electric current transmission cable comprising:a non-anodized bare conductor based on aluminum or an aluminum alloy, having a hydrophilic external specific surface configured to be in contact with the atmospheric environment, and an inside volume intended to conduct an electric current,
wherein the external specific surface of the bare conductor has a first roughness parameter, defined as the arithmetic mean deviation, measurable by profilometry, of peaks and valleys in comparison to a predetermined average profile over a reference length or surface, equal to or greater than 1.9 ?m, and
the inside volume of the bare conductor has oxygen doping of its aluminum-based or aluminum alloy-based components at a ratio equal to or greater than 20%, to a depth of at least 300 nm with respect to the external specific surface.

US Pat. No. 10,366,800

METHODS OF PROVIDING ELECTRICALLY-CONDUCTIVE SILVER

EASTMAN KODAK COMPANY, R...

18. A method for providing two or more electrically-conductive silver metal patterns, the method comprising:providing a continuous substrate having a first supporting side and a second opposing supporting side,
providing two or more photosensitive thin film patterns on two or more respective portions on the first supporting side of the continuous substrate from a solution of a photosensitive reducible silver ion-containing composition, comprising:
a) one or more non-hydroxylic-solvent soluble silver complexes, each comprising a reducible silver ion complexed with one or more ?-oxy carboxylates via one or more oxygen atoms and the same reducible silver ion is complexed with an oxime compound via a nitrogen atom,
each of the one or more non-hydroxylic-solvent soluble silver complexes being represented by the following formula (I):
(Ag+)a(L)b(P)c  (I)
wherein L represents the ?-oxy carboxylate; P represents the oxime compound; a is 1 or 2; b is 1 or 2; and c is 1, 2, 3, or 4, provided that when a is 1, b is 1, and when a is 2, b is 2,
solubilized in a b) solvent medium of one or more non-hydroxylic organic solvents; and
c) a photosensitizer that can either reduce the reducible silver ion or oxidize the ?-oxy carboxylate having a reduction potential;
photochemically converting reducible silver ions in each of the two or more photosensitive thin film patterns on the first supporting side of the continuous substrate to provide correspondingly two or more electrically-conductive silver metal-containing patterns on the first supporting side of the continuous substrate;
contacting each of the two or more electrically-conductive silver metal-containing patterns with water or an aqueous or non-aqueous salt solution;
optionally, contacting each of the two or more electrically-conductive silver metal-containing patterns with an aqueous or non-aqueous non-salt solution; and
optionally, drying each of the two or more electrically-conductive silver metal-containing patterns.

US Pat. No. 10,366,798

GARMENT WITH ELECTROMAGNETIC RADIATION SHIELDED POCKET

1. A garment that shields a wearer from electromagnetic radiation, the garment comprising:at least one first fabric forming a wearable garment, the at least one first fabric comprising a non-metallized fabric;
at least one pocketed area formed from a second fabric, the at least one pocketed area having at least a front side and a back side and defining an interior with the at least one pocketed area being coupled to the at least one first fabric;
a closure mechanism for selectively sealing an opening of the at least one pocketed area;
wherein the second fabric is configured to attenuate emission of electromagnetic radiation from the at least one pocketed area;
wherein the at least one pocketed area is lined with the second fabric; and
wherein the second fabric comprises about 70% to about 90% of a polyamide and about 10% to about 35% of an elastomer, with the second fabric being plated in silver, the silver having a purity of about 90% to about 99%.

US Pat. No. 10,366,796

PASSIVE DEPRESSURIZATION SYSTEM FOR PRESSURIZED CONTAINERS

ASVAD INT, S.L., Tarrago...

1. A nuclear reactor comprising a depressurization system for a pressurized container, comprising a main valve which comprises:a pneumatic actuator, and
an opening spring,
wherein:
the main valve is configured to be fluidly connected at one side to a pressurized container in which contains a gas and at the other side to the atmosphere, and
the opening spring is adjusted to set a predetermined mechanical pressure such that when a pressure inside the pressurized container is bigger than the predetermined mechanical pressure, the main valve remains closed, and that when the pressure inside the pressurized container is lower than the predetermined mechanical pressure, the main valve opens to establish a fluid communication so as to allow the pressurized gas from the pressurized container be discharged into the atmosphere.

US Pat. No. 10,366,795

LONG-LIFE HIGH-EFFICIENCY NEUTRON GENERATOR

Starfire Industries LLC, ...

1. An extended lifetime system for generating neutrons comprising:an external enclosure;
an insulating dielectric contained within the external enclosure;
a high voltage power supply;
a target at a target location capable of being loaded with hydrogen isotopes selected from the group consisting of: deuterium and tritium;
an ion source assembly configured to supply a beam of ions, the ion source assembly comprising:
a vessel comprising a wall made from an insulator material and having a plasma source cavity containing a plasma source from which a plasma is generated;
an anode electrode, connected to the high voltage power supply, the anode electrode being configured to bias the plasma;
an external applicator that is:
electrically connected to an excitation signal source, and
configured to deposit electromagnetic energy into the plasma source cavity through electromagnetic fields passing through the wall made from an insulator material,
wherein the external applicator is selected from the group consisting of an RF antenna and a microwave launcher,
wherein an insulating gap comprising the insulating dielectric separates the external applicator and the plasma source cavity; and
a target electrode electrically coupled to the target
wherein the high voltage power supply is configured to deliver a voltage between the anode electrode and the target electrode between 10 kV and 500 kV.

US Pat. No. 10,366,794

RISK PROFILING USING PORTAL BASED SCANNERS

GlobalTrak, LLC, Sterlin...

1. A hierarchical scanning system for monitoring shipping containers within a transportation system having one or more shipping cranes, the system comprising:a portal-based scanner, wherein the portal-based scanner is deployed on a structure which handles shipping containers during short term events; wherein the portal-based scanner comprises a sensor to detect the presence of a shipping container; further wherein the portal-based scanner is configured to scan and detect container anomalies; wherein the portal-based scanner is attached to a shipping crane;
a data fusion center, wherein the data fusion center is configured to receive data detected by the portal-based scanner; further wherein the data fusion center is further configured to collect and consolidate information from a plurality of additional portal-based scanners;
a first receiver, wherein the first receiver is configured to receive data from the portal-based scanner;
a processing element for identifying anomalies;
a decision module for generating an alert message containing data regarding identified anomalies; and
a first transmitter, wherein the first transmitter is configured to transmit an alert signal comprising the alert message;
wherein the data fusion center is configured to receive initial manifest data regarding the shipping container;
further wherein the initial manifest data comprises data regarding the container inventory and the container itinerary;
wherein the portal-based scanner is configured to gather data about the container in a short-term interaction and to transmit the data to the data fusion center;
wherein the data fusion center is configured to create a risk profile for the container based on data collected during the short-term interaction;
wherein the processing element is configured to compare the risk profile to at least one risk profile from a previous short-term interaction to identify anomalies.

US Pat. No. 10,366,792

SYSTEM AND METHOD FOR DETECTING RETINA DISEASE

Bio-Tree Systems, Inc., ...

1. A method of diagnosing disease in a retina, comprising:collecting a plurality of images of the retina;
processing the plurality of images to create a 3D computer model, where blood vessels are modelled as a series of stacked disks;
dividing the 3D model into a plurality of equally sized volumes;
determining a vascular density in each equally sized volume based on a number of disks in each equally sized volume; and
analyzing the vascular density in at least a portion of the equally sized volumes to determine the presence of a disease, wherein the portion of equally sized volumes comprises all equally sized volumes that are disposed in one plane.

US Pat. No. 10,366,791

METHOD AND SYSTEM FOR GLOBAL EPIDEMIC DISEASE OUTBREAK PREDICTION

EMC IP Holding Company LL...

1. A method comprising:receiving a request from a given user to predict disease outbreak information for a given location and a given time;
obtaining, from a plurality of data sources, a first set of disease outbreak patterns for the given location and the given time;
assigning weights to one or more reported diseases in the first set of disease outbreak patterns for the given location, the weights being based at least in part on an authenticity of one or more of the plurality of data sources from which data regarding the one or more reported diseases is obtained;
obtaining a second set of disease outbreak patterns for the given location at one or more historic time periods;
assigning weights to one or more reported diseases in the second set of disease outbreak patterns based at least in part on determining whether data in the second set of disease outbreak patterns correlates with data in the first set of disease outbreak patterns;
obtaining a set of personalized trends for the given user;
assigning weights to the set of personalized trends based at least in part on determining whether user profile attributes in the set of personalized trends correlate with the first set of disease outbreak patterns and the second set of disease outbreak patterns; and
generating at least one personalized alert for the given user based on the assigned weights for the first set of disease outbreak patterns, the second set of disease outbreak patterns, and the set of personalized trends; and
delivering the at least one personalized alert to a computing device associated with the given user over at least one network;
wherein the method is performed by at least one processing device comprising a processor coupled to a memory.

US Pat. No. 10,366,790

PATIENT SAFETY PROCESSOR

Lawrence A. Lynn, Columb...

1. A patient monitoring system for monitoring, in real time, a plurality of patients in a hospital system to detect the development of sepsis cascades and for identifying the patients developing the sepsis cascade, the system comprising:a plurality of local patient safety monitors, each of the plurality of local patient safety monitors configured to receive physiological measurements from at least one of a pulse oximeter or a blood pressure monitor for the plurality of patients,
a central patient safety monitor remote from the plurality of local patient safety monitors, the central patient safety monitor having a processor and memory storing instructions that, when executed by the processor, cause the system to:
receive the physiological measurements from the plurality of local patient safety monitors, and store the physiological measures in an electronic medical record;
receive the electronic medical records relating to the plurality of patients;
convert the electronic medical record into trend data, wherein the trend data is sequential, and wherein the trend data comprises information indicative of trends in physiologic parameters and laboratory data over time;
detect relational trends based on the trend data, the relational trends comprising positive or negative trends;
continuously search for and detect a sepsis cascade pattern associated with the relational trends occurring in at least one of the plurality of patients;
identify the at least one patient generating a sepsis cascade pattern detected in the continuous search;
automatically trigger, in response to the identification of the sepsis cascade pattern, generation of a real-time image of the sepsis cascade pattern at the central patient safety monitor;
compare the sepsis cascade pattern to a pattern definition to determine one or more characteristics of the sepsis cascade pattern; and
output the real-time image of the sepsis cascade pattern, an indication of the one or more characteristics of the sepsis cascade pattern, and the identity of the at least one patient to at least a display device of the central patient safety monitor by
generating a graphical display having viewing regions corresponding to physiologic systems of the patient, wherein the viewing regions include at least an inflammatory region, wherein the viewing regions are configured so that the sepsis cascade pattern is displayed such that the sepsis cascade pattern is viewable spreading over time within at least the inflammation region, and generating indications of the one or more characteristics of the cascade pattern on the graphical display, and
configuring the viewing regions so that sepsis cascade pattern is displayed as spreading within and/or across the viewing regions as the severity of the cascade patterns progress over time, such that the sepsis cascade is viewable progressively spreading over time from the origin of the sepsis cascade to the termination of the sepsis cascade, and the viewing regions are configured so that the sepsis cascade spreads along at least one axis and at least partially across the graphical display over time.

US Pat. No. 10,366,788

ADMINISTRATION SET DETECTION AND AUTHENTICATION USING CAM PROFILES

Curlin Medical Inc., Eas...

1. An administration set of a predetermined type for use with an infusion pump to administer a specified infusion protocol to a patient, wherein the predetermined type is chosen from a plurality of different administration set types, and wherein the infusion pump includes a follower, the administration set comprising:tubing for conveying an infusion liquid; and
a free-flow prevention device operable to selectively stop and permit flow of the infusion liquid through the tubing;
wherein the free-flow prevention device includes a carrier and a plunger movable relative to the carrier between an open position permitting flow of the infusion liquid through the tubing and a closed position stopping flow of the infusion liquid through the tubing, the plunger being biased toward the closed position and having a cam surface defining an uneven profile along a direction of movement of the plunger;
wherein the cam surface is exposed through a slot in the carrier and is slidably engageable by the follower, and the cam surface profile is configured to displace the follower in an elevation direction orthogonal to the direction of movement of the plunger as the plunger is moved from the closed position to the open position;
wherein the cam surface profile indicates the administration set is authorized for use with the infusion pump.

US Pat. No. 10,366,787

PHYSIOLOGICAL ALARM THRESHOLD DETERMINATION

MASIMO CORPORATION, Irvi...

1. A method of reducing nuisance alarms for a physiological parameter by determining an alarm threshold optimized for a specific care unit, the care unit including a plurality of patients being monitored for the physiological parameter, the method comprising:in the care unit, electronically measuring patient specific physiological parameters for the plurality of patients using a plurality of patient monitors;
electronically providing the patient specific physiological parameters to a threshold recommendation system;
receiving at least one recommended parameter specific alarm threshold value, said value responsive to a number of alarms triggered by said patient specific physiological parameters at said at least one recommended parameter specific alarm threshold value;
said at least one recommended parameter specific alarm threshold value calculated to reduce said number of alarms at said care center for said parameter by determining how many alarms are generated for each of a range of threshold values and choosing a threshold value from the range of threshold values that reduces a number of alarms; and
programming at least one of said plurality of patient monitors with a threshold value incorporating information gained by said suggested threshold value.

US Pat. No. 10,366,786

METHODS, SYSTEMS, AND PRODUCTS FOR FORMAT CONVERSION

1. A method, comprising:receiving, by a server, an electronic healthcare record associated with a recipient address;
comparing, by the server, the recipient address to addresses registered with a reformatting service that reformats the electronic healthcare record;
determining, by the server, that the recipient address is associated with the reformatting service;
executing, by the server, the reformatting service in response to the determining that the recipient address is associated with the reformatting service, the reformatting service generating a reformatted electronic healthcare record; and
sending, from the server, the reformatted electronic healthcare record to the recipient address.

US Pat. No. 10,366,783

IMAGING EXAMINATION PROTOCOL UPDATE RECOMMENDER

KONINKLIJKE PHILIPS N.V.,...

1. A system, comprising:a data repository configured to store a plurality of images;
a viewing station comprising:
a display monitor configured to visually present a displayed image, wherein the displayed image is selected from the plurality of images and corresponds to a scan, wherein the scan is within an electronically stored examination protocol;
at least one sensor configured evaluate a plurality of radiologist interactions reading the displayed image and to generate an output based on the evaluated radiologist interaction with the displayed image, wherein the at least one sensor is selected from the group consisting of:
a visual sensor configured to track movement of the radiologist viewing the displayed image;
an audio sensor configured to record audio uttered by the radiologist; and
an input device sensor configured to sense inputs corresponding to the displayed image; and
a computing device comprising:
a processor; and
a memory encoded with computer readable instructions which when executed by the processor cause the processor to:
determine at least one statistic based on the generated output; and
in response to determining the at least one statistic satisfies a predetermined threshold, remove the scan that corresponds to the displayed image from the examination protocol.

US Pat. No. 10,366,781

MAPPING AND DISPLAY FOR EVIDENCE BASED PERFORMANCE ASSESSMENT

IQVIA Inc., Parsippany, ...

1. A computer-implemented method for organizing clinical trial data executed by one or more processors, the method comprising:obtaining, by the one or more processors of a server system and from a selectable record in an aggregate database of the server system, identities of a plurality of investigators and data representing a set of attributes associated with each of the plurality of investigators from a first data set and a second data set, wherein:
the first data set containing proprietary data associated with at least one of the investigators and received from a first set of databases,
the second data set containing third-party data associated with at least one of the investigators and received from a second set of databases that is different from the first set of databases, and
the selectable record enables the one or more processors to perform one or more adjustments to data of the identities of the plurality of investigators included within the aggregate database in a first time period that is shorter than a second time period for performing the one or more adjustments on data of the identities of the plurality of investigators included within the first set of databases and the second set of databases but not stored within the aggregate database;
receiving, by the one or more processors and from a computing device, a user input indicating a subset of attributes from the set of attributes associated with each of the plurality of investigators;
generating, by the one or more processors, a multi-dimensional chart that organizes the identities of the plurality of investigators based on the subset of attributes and a user designation of selected dimensions to reflect two or more of attributes from the subset of attributes, the multi-dimensional chart comprising:
a first dimension representing a first attribute from the subset of attributes;
a second dimension representing a second attribute from the subset of attributes; and
a plurality of icons,
each icon representing an identity of one of the plurality of investigators,
wherein each icon is positioned on the multidimensional chart along the first dimension according to a value of the first attribute associated with the represented identity and along the second dimension according to a value of the second attribute of the represented identity, and
wherein a graphical property of each icon represents a value of a third attribute of the represented identity;
linking, by the one or more processors, each icon included in the plurality of icons to the selectable record in the aggregate database so that user interactions with icons included in the plurality of icons by the computing device cause one or more attributes associated with the icons included in the plurality of icons to be altered within the aggregate database;
providing, by the one or more processors and for display on the computing device, a graphical user interface (GUI) including the multi-dimensional chart and a clinical trial roster;
receiving, by the one or more processors and from the computing device, a user selection of one or more icons from among the plurality of icons for inclusion in a clinical trial;
in response to receiving the user selection:
adding, by the one or more processors, identities of investigators represented by the one or more selected icons to the clinical trial roster;
updating, by the one or more processors, the selectable record to reflect that the identities of investigators represented by the one or more selected icons have been added to the clinical trial roster; and
updating, by the one or more processors and based on linking each icon included in the plurality of icons to the selectable record in the aggregate database, one or more attributes in the selectable record that are associated with the one or more selected icons.

US Pat. No. 10,366,775

MEMORY DEVICE USING LEVELS OF DYNAMIC REDUNDANCY REGISTERS FOR WRITING A DATA WORD THAT FAILED A WRITE OPERATION

SPIN MEMORY, INC., Fremo...

1. A memory device comprising:a memory array of memory cells, wherein the memory array is configured to store a data word at one of a plurality of memory addresses;
a first level dynamic redundancy buffer comprising data storage elements; and
a pipeline coupled to the memory array and the first level dynamic redundancy buffer, wherein the pipeline is configured to:
write a data word into the memory array at a selected one of the plurality of memory addresses;
verify the data word written into the memory array to determine whether the data word was successfully written by the write;
responsive to a determination that the data word was not successfully written by the write, writing the data word and the selected one of the plurality of memory addresses into the first level dynamic redundancy buffer; and
attempt to re-write the data word stored in the first level dynamic redundancy buffer into the memory array at the selected one of the plurality of memory addresses.

US Pat. No. 10,366,774

DEVICE WITH DYNAMIC REDUNDANCY REGISTERS

Spin Memory, Inc., Fremo...

1. A method of writing data into a memory device, the method comprising:writing a data word into a memory bank at a selected one of a plurality of memory addresses, wherein the memory bank comprises a plurality of spin-transfer torque magnetic random access memory (STT-MRAM) memory cells, wherein each memory cell is arranged to store a data word at one of a plurality of memory addresses;
verifying the data word written into the memory bank to determine whether the data word was successfully written thereto; and
responsive to a determination that the data word was not successfully written, performing:
writing the data word and the selected one of the plurality of memory addresses into a first level dynamic redundancy register; and
re-writing the data word stored in the first level dynamic redundancy register into the memory bank at the selected one of the plurality of memory addresses.

US Pat. No. 10,366,773

E-FUSE CIRCUIT

SK hynix Inc., Icheon-si...

1. An electrical fuse (E-fuse) circuit comprising:a boot-up controller configured to generate at least one fuse address and a sensing enable signal based on a boot-up signal;
an electrical fuse (E-fuse) array configured to include a plurality of fuse sets, and output fuse data having defect fusing information of the plurality of fuse sets when a word line corresponding to the fuse address is activated;
a fail controller configured to detect failed data from the fuse data, and activate a failed signal when the failed data is detected wherein the failed data is defect of an E-fuse included in the plurality of fuse sets; and
a failed address storage circuit configured to store a failed address corresponding to a fuse-set in which a defect is detected from among the fuse addresses when the failed signal is activated,
wherein the defect fusing information indicates that a failed part has occurred in the E-fuse of the fuse set resulting in the occurrence of the failed data,
wherein the fail controller includes:
a fail processor configured to activate a masking control signal when the failed data is detected from the fuse data; and
a failed signal generator configured to generate the failed signal based on the masking control signal during activation of a test signal.

US Pat. No. 10,366,757

COMPACT NON-VOLATILE MEMORY DEVICE

STMicroelectronics (Rouss...

1. A method of erasing a memory cell, the method comprising:applying a first voltage to a control gate of the memory cell, wherein the control gate is disposed over and insulated from a floating gate of the memory cell, wherein the floating gate comprises an embedded portion disposed over and insulated from a selection gate of the memory cell, wherein the embedded portion of the floating gate is located between a first substrate region of a semiconductor substrate and a second substrate region of the semiconductor substrate, wherein the floating gate further comprises a projecting portion extending out of the semiconductor substrate and disposed over the embedded portion of the floating gate and below the control gate, wherein the selection gate is embedded in the semiconductor substrate and below the embedded portion of the floating gate, wherein the selection gate is located between the first substrate region of the semiconductor substrate and the second substrate region of the semiconductor substrate, wherein the semiconductor substrate further comprises a source region disposed below the selection gate, the first substrate region of the semiconductor substrate, and the second substrate region of the semiconductor substrate;
applying a second voltage to the first substrate region of the semiconductor substrate; and
applying a third voltage to the second substrate region of the semiconductor substrate, wherein the third voltage is different from the second voltage, wherein a potential difference between the second voltage and the first voltage is greater than an erasure threshold of the memory cell so as to perform an erasing operation on the memory cell.

US Pat. No. 10,366,754

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE WITH REDUCED POWER CONSUMPTION

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit including a content addressable memory device, comprising:a memory cell array including:
a first memory cell containing a first part of entry data and a second memory cell containing a second part of the entry data;
a first match line and a second match line coupled to the first memory cell and the second memory cell, respectively; and
a first search line carrying a first part of search data and a second search line carrying a second part of the search data, the first search line and the second search line being coupled to the first memory cell and the second memory cell, respectively;
an equalizer circuit disposed between the first match line and the second match line;
a first precharge circuit being coupled to the first match line, and precharging the first match line to a first potential; and
a second precharge circuit being coupled to the second match line, and precharging the second match line to a second potential different from the first potential,
wherein the first memory cell includes a first comparator circuit comparing the first part of the search data supplied through the first search line and the first part of the entry data,
wherein the second memory cell includes a second comparator circuit comparing the second part of the search data supplied through the second search line and the second part of the entry data,
wherein the equalizer circuit couples, in accordance with a control signal, the first match line and the second match line after the first match line and the second match line are precharged, and
wherein the first search line and the second search line are each supplied with a search signal based on a valid data at the same time as the first match line and the second match line are coupled by the equalizer circuit.

US Pat. No. 10,366,725

SERVER SIDE CROSSFADING FOR PROGRESSIVE DOWNLOAD MEDIA

Sirius XM Radio Inc., Ne...

1. A method for implementing a server side crossfade or other transitional effect, the method comprising:receiving, from each of a plurality of client devices, user data indicative of behavior or at least one preference of a user of that client device;
identifying at least one media clip to be transmitted to a first one of the plurality of client devices for playback, the at least one media clip including multiple chunks;
determining at least one chunk of the at least one media clip to process for the effect;
processing the at least one chunk based on the user data received from the first client device such that the effect is personalized for the user of that device; and
transmitting the processed at least one chunk and the remaining chunks of the at least one media clip to the first client device for playback.

US Pat. No. 10,366,720

OXIDATION RESISTANT SENSOR FOR HEAT-ASSISTED MAGNETIC RECORDING

Seagate Technology LLC, ...

1. An apparatus, comprising:a slider comprising an air bearing surface (ABS) and configured for heat-assisted magnetic recording, the slider comprising:
a writer and a reader at the ABS;
a near-field transducer (NFT) proximate the writer;
an optical waveguide optically coupled to a laser source and the NFT;
a sensor configured to contact and sense thermal asperities of a magnetic recording medium, the sensor formed from one of Ru, Rh, Pd, Os, Ir, and Pt;
a protective coating covering at least a portion of the ABS including the writer, reader, NFT, and sensor; and
the sensor is configured to operate at a temperature that degrades the protective coating and exposes the sensor leaving the sensor unprotected.

US Pat. No. 10,366,718

HARD DISK SERVO CONTROL ADAPTIVE NOTCH FILTER USING A RECURSIVE LEAST SQUARES PROCESSOR

Seagate Technology LLC, ...

1. A method comprising:monitoring a signal that provides an indicator of disturbance affecting a hard disk drive, the signal being monitored during an operational track following mode of the hard disk drive;
in response to determining that the indicator of the disturbance satisfies a threshold:
applying a lattice recursive least squares computation to the signal to determine at least one notch frequency; and
using the at least one notch frequency to form a notch filter used by a servo controller loop that positions a read/write head over a disk of the hard disk drive; and
apply the notch filter to the servo control loop for subsequent positioning of the read/write head.

US Pat. No. 10,366,708

SYSTEMS AND METHODS OF DETECTING SPEECH ACTIVITY OF HEADPHONE USER

BOSE CORPORATION, Framin...

1. A headphone system, comprising:a left earpiece;
a right earpiece;
a left microphone coupled to the left earpiece to receive a left acoustic signal and to provide a left signal derived from the left acoustic signal;
a right microphone coupled to the right earpiece to receive a right acoustic signal and to provide a right signal derived from the right acoustic signal; and
a detection circuit coupled to the left microphone and the right microphone, the detection circuit configured to process both a principal signal and a reference signal through a smoothing algorithm, the principal signal derived from a sum of the left signal and the right signal and the reference signal derived from a difference between the left signal and the right signal, the smoothing algorithm configured to calculate a principal power signal from a decaying weighted average of power of the principal signal over time, to calculate a reference power signal from a decaying weighted average of power of the reference signal over time, and to selectively indicate that the user is speaking based at least in part upon a comparison between the principle power signal and the reference power signal.

US Pat. No. 10,366,704

ACTIVE ACOUSTIC ECHO CANCELLATION FOR ULTRA-HIGH DYNAMIC RANGE

Intel Corporation, Santa...

1. An apparatus comprising:a speaker to generate audio output;
an audio input device to receive audio input and to provide an audio input signal responsive to the audio input at a first sampling rate; and
one or more processors coupled to the speaker and the audio input device, the one or more processors to:
generate an audio output signal having at least a portion thereof corresponding to a first audio frequency range, the portion of the audio output signal, when provided as first audio output from the speaker, to negate a response of the audio input device, at a response negation rate, to second audio output from the speaker in a second audio frequency range, wherein each audio frequency of the first audio frequency range exceeds a maximum audio frequency of the second audio frequency range; and
decimate the audio input signal based on the response negation rate to a second sampling rate less than the first sampling rate to generate a resultant audio input signal.

US Pat. No. 10,366,703

METHOD AND APPARATUS FOR PROCESSING AUDIO SIGNAL INCLUDING SHOCK NOISE

SAMSUNG ELECTRONICS CO., ...

1. A method of processing an audio signal in a terminal device, the method comprising:acquiring an audio signal of a frequency domain for a current frame;
dividing a frequency band into a plurality of sections;
acquiring energies of a first section and a second section from among the plurality of sections;
determining whether the audio signal of the current frame includes noise based on an energy difference between the first section and the second section; and
applying a suppression gain to the audio signal of the current frame and outputting the audio signal of the current frame applied the suppression gain, based on a result of determining,
wherein the first section and the second section are non-overlapped in the frequency band, and
wherein at least one of the first section and the second section is determined as a shock noise section based on the energy difference.

US Pat. No. 10,366,683

PERCUSSION INSTRUMENT PLAYING DEVICE

UTSUWA INC., Kyoto (JP)

1. A percussion-instrument playing apparatus comprising:a main body to be detachably fixed in front of or above a percussion instrument having, in a front surface or an upper surface, a striking surface, the main body including two fixing portions to be detachably fixed to both sides of the striking surface of the percussion instrument and an arm attachment member that bridges a space between the two fixing portions, and the arm attachment member facing the striking surface with a predetermined space from the striking surface when the two fixing portions are respectively fixed to both sides of the striking surface of the percussion instrument;
an arm supporter fixed to the arm attachment member;
one or more arms each having one end fixed to the arm supporter;
an arm head detachably fixed to the other end of the arm; and
a drive unit for driving the one or more arms under electronic control,
wherein the arm head of each of the one or more arms strikes the same striking surface of the percussion instrument to cause sounds to be emitted from the percussion instrument.

US Pat. No. 10,366,682

POSITIONING APPARATUS FOR STRINGED MUSICAL INSTRUMENTS

Ryan Letcher, Endicott, ...

1. An apparatus to be connected to a stringed instrument for positioning the stringed instrument to an upright playing position, the apparatus comprising:a rear plate, to be positioned behind the instrument;
a first stabilizer bar connected to the rear plate via a first fastener and to be positioned in front of the instrument;
a second stabilizer bar connected to the rear plate via a second fastener and to be positioned in front of the instrument;
an elevator platform connected to the rear plate and the first and second stabilizer bars via the first and second fasteners, respectively and to be positioned below the instrument and adjacently between the rear plate and the first and second stabilizer bars; and
a leg connected to the rear plate,
wherein the rear plate, first stabilizer bar, second stabilizer bar, and elevator platform grip the instrument such that the rear plate, first stabilizer bar, second stabilizer bar, elevator platform, and instrument can together be held upright on the leg.

US Pat. No. 10,366,679

DRUM PEDAL

JAW CORPORATION, Taichun...

1. A drum pedal, comprising:a base having a clamping element disposed in a front section for supporting a drum;
a column installed on and extended upward from the base;
a shaft rotatably mounted on a top end of the column;
a drum beater held in a holder mounted on the shaft;
a cam rotatably mounted on the shaft;
a pedal board having a back end hinged to a heel piece, which is attached to the base so that the pedal board may freely pivot around its back end;
a linkage having its top end fixed to the cam and a bottom end connected to a front end of the pedal board so that the pedal board is slantwise positioned relative to the base; and
an elastic element having a top end coupled to one end of the shaft and a bottom end fixed to a lower end of the column, wherein a plate is laterally extended out; a roller is fastened to the plate; a loop at a bottom end of the elastic element is hooked to the roller; a top end of the elastic element is connected to a bottom end of a threaded rod; the threaded rod and a screw cap are connected via a sleeve mounted to the outer end of the shaft; and the screw cap provides tensioning adjustment to the elastic element and, therefore, the force of exertion when pressing down the pedal board.

US Pat. No. 10,366,677

STRING INSTRUMENT WITH RESONATOR

Angelo Tagliapini, Gardo...

1. A string instrument (1; 100) comprising a resonator (2), a handle (3) and a tailpiece (4; 40), wherein said handle (3) and said tailpiece (4; 40) are bound to said resonator (2) for combining at least one string to said instrument, said instrument comprises at least one magnet pair generally opposed each other, a first magnet (11; 110) of said at least one magnet pair being bound to said resonator (2), a second magnet (12; 120) of said at least one magnet pair being arranged at a first distance from said first magnet, so that to apply, between said first magnet (11; 110) and said second magnet (12; 120), a repulsive force or an attractive force, respectively, depending on the opposed polarities, equal or opposite, of said first magnet and said second magnet, said attractive force or said repulsive force being active on said resonator (2), wherein said string instrument further comprises a plurality of magnet pairs including respective pluralities of said first and second magnets.

US Pat. No. 10,366,676

DISPLAY DEVICE

LG Display Co., Ltd., Se...

1. A display device, comprising:a display panel equipped with a plurality of pixels connected with data lines and gate lines;
a data driving circuit configured to provide data voltage to the pixels through the data lines; and
a gate driving circuit configured to drive the gate lines,
wherein a first pixel disposed in n-th pixel line among the plurality of pixels, n being a natural number, comprises:
a light emitting diode;
a driving TFT, whose source is connected to the light emitting diode, configured to control a current flowing the light emitting diode;
a capacitor connecting the source of the driving TFT and a gate of the driving TFT;
a first TFT configured to be controlled by a first gate signal which is transferred through a first gate line and generated by the gate driving circuit to connect the gate of the driving TFT to one of the data lines;
a second TFT configured to be controlled by a second gate signal which is transferred through a second gate line and generated by the gate driving circuit to connect the gate of the driving TFT to an initialization voltage; and
a third TFT configured to be controlled by the second gate signal transferred to a second pixel disposed in (n?1)-th pixel line to connect the source of the driving TFT to a reference voltage,
wherein, in a first portion of a threshold voltage sensing period, a voltage of the source of the driving thin film transistor is configured to rise to a value smaller than a value obtained by subtracting a threshold voltage of the driving thin film transistor from a voltage of the gate of the driving thin film transistor, such that a voltage higher than the threshold voltage is charged to the capacitor, and
wherein, in a second portion of the threshold voltage sensing period, the voltage of the source is configured to rise and the voltage of the gate is configured to rise due to the capacitor, wherein the voltage of the gate is configured to rise less than the voltage of the source is configured to rise such that a voltage close to the threshold voltage is charged to the capacitor.