US Pat. No. 10,249,854

SUPPORT MEMBER FOR BATTERY PACK TOP HOUSING

MILWAUKEE ELECTRIC TOOL C...

1. A battery pack connectable to and supportable by a hand-held power tool, the battery pack comprising:a plastic battery pack housing that includes a battery pack top housing, the battery pack top housing including a support portion connectable to a complementary support portion of the hand-held power tool and a support member insert molded to be included within the battery pack top housing, the support member reinforcing the support portion of the battery pack top housing, the support member being made of a different material than the plastic battery pack housing,
wherein the support member includes a first portion, a second portion, a third portion, a fourth portion, and a fifth portion,
wherein the first portion is integrally formed with the second portion and the third portion,
wherein the second portion is approximately parallel to the third portion and the fourth portion is approximately parallel to the fifth portion, and
wherein the second portion is integrally formed with the fourth portion and the third portion is integrally formed with the fifth portion, and the second portion is approximately perpendicular to the fourth portion and the third portion is approximately perpendicular to the fifth portion.

US Pat. No. 10,249,853

POWER STORAGE DEVICE

KABUSHIKI KAISHA TOYOTA J...

1. An electricity storage device comprising:one or more unit electricity storage portions, the one or more unit electricity storage portions including an electrode assembly in which a positive electrode and a negative electrode are stacked and layered while being insulated from each other and a case configured to accommodate the electrode assembly; and
a load applying mechanism that applies, to the electrode assembly, a load in a lamination direction in which the positive electrode and the negative electrode are stacked in the electrode assembly, wherein
the load applying mechanism includes:
a pair of restraint plates, which respectively contact opposite ends of a single unit electricity storage portion in the lamination direction or which respectively contact a first electricity storage portion arranged at a first end of a plurality of unit electricity storage portions in the lamination direction and a second electricity storage portion arranged at a second end of the plurality of unit electricity storage portions in the lamination direction,
four bolts, which are respectively inserted through four corners of the pair of restraint plates, and
four nuts, which are threaded to the respective bolts,
wherein
the negative electrode includes
a metal foil, and
an active material layer that covers at least part of the metal foil and contains a carbon-based material as an active material,
a density of the carbon-based material in the active material layer is 1.2 g/cm3 or higher,
a degree of orientation that is defined as a ratio (I(100)/I(002)) of an X-ray diffraction intensity I(100) of a (100) plane to a diffraction intensity I(002) of a (002) plane in the active material layer is lower than or equal to 0.3, and
the load applied by the load applying mechanism is greater than or equal to 0.2 MPa.

US Pat. No. 10,249,852

SECONDARY BATTERY INCLUDING CONNECTOR COUPLED TO ELECTRODE ASSEMBLY AND CURRENT COLLECTOR

Samsung SDI Co., Ltd., Y...

1. A secondary battery comprising:a case having an internal space;
an electrode assembly inserted into the case and including a first electrode plate, a second electrode plate, and a separator between the first electrode plate and the second electrode plate;
an electrode tab electrically connected to the electrode assembly;
a cap plate sealing the case;
a current collector electrically connected to the electrode tab;
an electrode terminal electrically connected to the current collector and configured to pass through the cap plate to protrude toward the outside along an extension direction of the electrode terminal; and
a connector having an end coupled to the electrode assembly and an other end coupled to the current collector, the connector comprising a fastening portion having a protrusion shaped as a triangular pillar and extending through the current collector along the extension direction of the electrode terminal.

US Pat. No. 10,249,851

STACKED BATTERY

TOYOTA JIDOSHA KABUSHIKI ...

1. A stacked battery comprising:a first electrode body including
a plurality of positive electrode plates,
a plurality of negative electrode plates, and
a plurality of separators,
each of the positive electrode plates and each of negative electrode plates being alternately stacked with each of the separators interposed between each of the positive electrode plates and each of the negative electrode plates;
a second electrode body including
a plurality of positive electrode plates,
a plurality of negative electrode plates, and
a plurality of separators,
each of the positive electrode plates and each of negative electrode plates being alternately stacked with each of the separators interposed between each of the positive electrode plates and each of the negative electrode plates;
the second electrode body provided above the first electrode body,
each positive electrode plate including a positive electrode protruding portion protruding more laterally than the negative electrode plate,
each negative electrode plate including a negative electrode protruding portion protruding more laterally than the positive electrode plate;
a first current collecting case being electrically conductive, the first current collecting case including a first facing portion facing the first electrode body in a stacking direction of the first electrode body and the second electrode body;
a second current collecting case being electrically conductive, the second current collecting case housing the first electrode body, the second current collecting case being disposed between the first electrode body and the second electrode body, the second current collecting case being configured to be electrically insulated from the first current collecting case, the second current collecting case including a second facing portion facing one of the first electrode body and the second electrode body in the stacking direction; and
a third current collecting case being electrically conductive, the third current collecting case housing the second electrode body, the third current collecting case being configured to be electrically insulated from the second electrode body, the third current collecting case including a third facing portion facing the second electrode body in the stacking direction,
the first current collecting case, the second current collecting case, and the third current collecting case being stacked in this order in the stacking direction,
the first current collecting case including a first positive electrode wall portion, the first positive electrode wall portion extending from an edge portion of the first facing portion such that the first positive electrode wall portion covers a first side portion where the positive electrode protruding portion of the first electrode body is located, an inner surface of the first positive electrode wall portion being electrically connected to an edge side of the positive electrode protruding portion of the first electrode body,
the second current collecting case including a second positive electrode wall portion, the second positive electrode wall portion extending from an edge portion of the second facing portion such that the second positive electrode wall portion covers a first side portion where the positive electrode protruding portion of the second electrode body is located, an inner surface of the second positive electrode wall portion being electrically connected to an edge side of the positive electrode protruding portion of the second electrode body, the second current collecting case including a first negative electrode wall portion, the first negative electrode wall portion extending from an edge portion of the second facing portion such that the first negative electrode wall portion covers a second side portion where the negative electrode protruding portion of the first electrode body is located, an inner surface of the first negative electrode wall portion being electrically connected to an edge side of the negative electrode protruding portion of the first electrode body,
the third current collecting case including a second negative electrode wall portion, the second negative electrode wall portion extending from an edge portion of the third facing portion such that the second negative electrode wall portion covers a second side portion where the negative electrode protruding portion of the second electrode body is located, an inner surface of the second negative electrode wall portion being electrically connected to an edge side of the negative electrode protruding portion of the second electrode body.

US Pat. No. 10,249,850

DISPLAY APPARATUS AND PORTABLE TERMINAL

Samsung Display Co., Ltd....

1. A display apparatus, comprising:a display panel configured to display an image
a first member under the display panel, the first member including a center portion and an edge portion surrounding the center portion, the center portion having a thickness greater than a thickness of the edge portion, the thickness of the center portion and the thickness of the edge portion being in a direction perpendicular to the display panel; and
a second member under the first member and overlapping with the edge portion.

US Pat. No. 10,249,849

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:a first electrode and a second electrode on a substrate, the first electrode being opposite to the second electrode; and
at least one emission part between the first electrode and the second electrode, the at least one emission part including at least one organic layer,
wherein the at least one organic layer comprises a peak wavelength of electroluminescence (EL) spectrum (PWES) structure where a moving range of a peak wavelength of an EL spectrum emitted from the at least one emission part is set based on at least one of a thickness and a content of a dopant of the at least one emission part, and
wherein the at least one emission part includes two emission parts, the two emission parts including a plurality of emission layers having a same wavelength range or different wavelength ranges.

US Pat. No. 10,249,848

ORGANIC LIGHT-EMITTING PANEL AND METHOD FOR PRODUCING SAME

JOLED INC., Tokyo (JP)

1. An organic light-emitting panel, comprising:a first electrode that is light-reflecting;
a functional layer having a single layer or multi-layer structure, located on the first electrode;
an organic light-emitting layer located on the functional layer, the organic light-emitting layer including a red organic light-emitting layer portion defining a red organic light-emitting element, a green organic light-emitting layer portion defining a green organic light-emitting element, and a blue organic light-emitting layer portion defining a blue organic light-emitting element;
a second electrode that is light-transmitting, located above the organic light-emitting layer;
a first layer located on the second electrode;
a second layer located on the first layer;
a sealing layer located on the second layer, the sealing layer composed of aluminum oxide;
a resin sealing layer located on the sealing layer; and
a substrate located on the resin sealing layer, the substrate being adhered to the sealing layer via the resin sealing layer, wherein
a refractive index of the second electrode is at least 2.0 and no greater than 2.4,
a refractive index of the first layer is at least 1.3 and no greater than 1.6,
a refractive index of the second layer is at least 1.7 and no greater than 2.1,
the refractive index of the first layer is lower than the refractive index of the second electrode, and a difference between the refractive index of the first layer and the refractive index of the second electrode is at least 0.4 and no greater than 1.1,
the refractive index of the first layer is lower than the refractive index of the second layer, and a difference between the refractive index of the first layer and the refractive index of the second layer is at least 0.1 and no greater than 0.8,
the first layer includes metal fluoride and has thickness of at least 75 nm and no greater than 120 nm,
a thickness of the functional layer is different below each of the red organic light-emitting layer portion, the green organic light-emitting layer portion, and the blue organic light-emitting layer portion, the thickness being set such that a resonator structure within each of the red organic light-emitting element, the green organic light-emitting element, and the blue organic light-emitting element is either a 1st cavity structure or a 2nd cavity structure,
a maximum thickness of the functional layer is no greater than 70 nm, and
the thickness of the first layer, the difference between the refractive index of the first layer and the refractive index of the second electrode, and the difference between the refractive index of the first layer and the refractive index of the second layer produce interference between light travelling along a first optical pathway and light travelling along a second optical pathway, the light travelling along the first optical pathway not being reflected at an interface between the second electrode and the first layer, the light travelling along the second optical pathway being reflected at the interface between the second electrode and the first layer and reflected by the first electrode.

US Pat. No. 10,249,847

ORGANIC LIGHT-EMITTING DIODE, ORGANIC LIGHT MODULE, AND METHOD FOR PRODUCING AN ORGANIC LIGHT-EMITTING DIODE

OSRAM OLED GMBH, Regensb...

1. An organic light-emitting diode comprisinga substrate having a top side and one or a plurality of substrate side surfaces running transversely with respect to the top side, wherein the top side and the substrate side surfaces are connected to one another in each case via a substrate edge, and
an organic layer sequence applied to the top side and having an emitter layer, which generates electromagnetic radiation during intended operation of the light-emitting diode, wherein the radiation is coupled out from the organic light-emitting diode via a luminous surface, wherein
in a plan view of the luminous surface the organic layer sequence adjoins at least a partial region of at least one substrate edge, wherein in the partial region the luminous surface extends at least as far as the corresponding substrate edge,
an encapsulation formed in an uninterrupted and continuous fashion is applied to the organic layer sequence,
the encapsulation, at least in the region of the substrate edge adjoining the organic layer sequence, is led right onto the associated substrate side surface, at least partly covers the latter and is in direct contact with the substrate side surface.

US Pat. No. 10,249,846

OLED PACKAGING METHOD AND OLED PACKAGE STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. An organic light-emitting display (OLED) packaging method, comprising the following steps:Step 1: providing a OLED device and forming a first barrier layer on the OLED device such that the first barrier layer covers an entire surface of the OLED device;
Step 2: forming a first silicon-doped diamond-like carbon layer on the first barrier layer such that the first silicon-doped diamond-like carbon layer covers an entire surface of the first barrier layer;
Step 3: forming a diamond-like carbon scattering layer on the first silicon-doped diamond-like carbon layer;
Step 4: forming a first organic buffer layer on the first silicon-doped diamond-like carbon layer and the diamond-like carbon scattering layer such that the first organic buffer layer completely covers the first silicon-doped diamond-like carbon layer and the diamond-like carbon scattering layer; and
Step 5: forming a second barrier layer on the first organic buffer layer, such that the second barrier layer covers an entire surface of the first organic buffer layer.

US Pat. No. 10,249,845

OPTOELECTRONIC COMPONENT AND METHOD FOR PRODUCING AN OPTOELECTRONIC COMPONENT

OSRAM OLED GmbH, Regensb...

1. An optoelectronic component, comprisingan electrically conductive layer,
an electrically insulating layer formed above a partial region from the electrically conductive layer,
an electrically weakly conductive encapsulation layer formed outside the partial region on the electrically conductive layer and above the partial region on the electrically insulating layer,
a first electrode formed above the partial region on the electrically weakly conductive encapsulation layer,
an organic functional layer structure formed on the first electrode, and
a second electrode formed above the partial region on the organic functional layer structure and where the second electrode is formed outside the partial region on the electrically weakly conductive encapsulation layer.

US Pat. No. 10,249,844

LIGHT-EMITTING DISPLAY PANEL

INNOLUX CORPORATION, Mia...

1. A light-emitting display panel, comprising:a substrate comprising a display area and a peripheral area surrounding the display area, and the substrate having a top surface;
a light-emitting display structure disposed on the display area;
a first section wall disposed on the peripheral area and surrounding the light-emitting display structure, wherein the first section wall is dash-circular shape;
an enclosed wall disposed on the peripheral area, wherein the enclosed wall surrounds the first section wall and is positioned outside the first section wall; and
a first inorganic material layer covering the light-emitting display structure and a portion of the top surface outside the enclosed wall.

US Pat. No. 10,249,843

DISPLAY DEVICE WITH LIGHT TRANSMISSION AREA

Samsung Display Co., Ltd....

1. A display device, comprising:a substrate comprising a first area displaying an image and a second area adjacent to the first area, the second area transmitting external light;
a first electrode and a second electrode disposed in the first area and overlapping each other;
an emission layer disposed between the first electrode and the second electrode in the first area;
a first semiconductor layer disposed in the first area; and
a second semiconductor layer disposed in the second area,
wherein the second semiconductor layer is not connected to the first electrode and the second electrode.

US Pat. No. 10,249,842

ORGANIC EL DEVICE, ORGANIC EL LIGHTING PANEL, ORGANIC EL LIGHTING APPARATUS, AND ORGANIC EL DISPLAY

NEC Lighting, Ltd., Toky...

1. An organic EL (electro-luminescence) device comprising: a first substrate; a second substrate; one or more organic EL elements; and a sealing layer, each of the one or more organic EL elements comprising an organic EL layer and a pair of electrodes, one surface of the first substrate being a mounting surface on which the one or more organic EL elements are disposed, the first substrate and the second substrate being laminated in such a manner that the mounting surface of the first substrate and one surface of the second substrate face each other with the sealing layer interposed therebetween, the sealing layer sealing a gap between the first substrate and the second substrate along an entire periphery of a region facing the second substrate on the mounting surface of the first substrate and an entire periphery of a region facing the first substrate on the one surface of the second substrate facing the first substrate, wherein the organic EL device further comprises supporting layers, the supporting layers comprise a layer of material of the sealing layer, a layer of material of one of the pair of electrodes, a layer of material of the organic EL layer, and an insulating layer that is interposed between the pair of electrodes, and the supporting layers are disposed in such a manner that the supporting layers connect the mounting surface of the first substrate and the one surface of the second substrate facing the first substrate via the other one of the pair of electrodes.

US Pat. No. 10,249,841

DISPLAY APPARATUS

Joled Inc., Tokyo (JP)

1. A method of manufacturing a display apparatus, the method comprising:providing a plurality of organic electroluminescence devices on a drive panel, each organic electroluminescence device formed by:
providing a first electrode,
providing one or more organic layers including a light-emitting layer on the first electrode, and
providing a second electrode on the one or more organic layers,
providing an adhesive member on the plurality of organic electroluminescence devices, the adhesive member including a first adhesive portion that is comprised of an ultraviolet curing material and a second adhesive portion that is comprised of a heat-curable material, and
providing a sealing panel on a least a portion of the adhesive member, the sealing panel seals and faces the drive panel at a side of the second electrode,
wherein the ultraviolet curing material is cured by applying ultraviolet rays before curing the heat-curable material.

US Pat. No. 10,249,840

OPTICAL DEVICE

PIONEER CORPORATION, Kaw...

1. A method of manufacturing an optical device, comprising:forming a joining structure in which a first conductive film is constituted by a conductive material and a second conductive film that is constituted by a metal material are joined to each other,
wherein in the joining structure,
a part of the second conductive film comes into contact with the first conductive film, and a plurality of concave portions are provided in a contact surface of the second conductive film which comes into contact with the first conductive film,
wherein, in a cross-sectional shape of at least a part of the plurality of concave portions which are provided in the contact surface, at least a part between an opening end and a bottom portion of the concave portions has a cross-sectional width that is greater than a cross-sectional width of the opening end.

US Pat. No. 10,249,839

ORGANIC ELECTROLUMINESCENCE DEVICE, ORGANIC ELECTROLUMINESCENCE UNIT, AND ELECTRONIC APPARATUS

Joled Inc., Tokyo (JP)

1. An organic electroluminescence device comprising, in order:a first electrode;
a hole transport layer configured by a coated film;
an organic light-emitting layer configured by a coated film, the organic light-emitting layer having a hole current that is larger than an electron current;
an electron transport layer; and
a second electrode,
wherein a quotient of the hole current divided by the electron current is larger than 5, and
wherein the hole transport layer comprises an insolubilized hole transport layer.

US Pat. No. 10,249,838

WHITE ORGANIC LIGHT EMITTING DEVICE HAVING EMISSION AREA CONTROL LAYER SEPARATING EMISSION AREAS OF AT LEAST TWO EMISSION LAYERS

LG Display Co., Ltd., Se...

1. A white organic light emitting device, comprising:a first emission part between a first electrode and a second electrode; and
a second emission part on the first emission part,
wherein at least one among the first emission part and the second emission part comprises:
at least two emission layers, the at least two emission layers including a first emission layer including a first dopant and a first host, and a second emission layer including a second dopant different from the first dopant; and
a layer directly adjacent to the first emission layer, the layer having at least the first dopant of the first emission layer, and including a second host having a different hole mobility than a hole mobility of the first host.

US Pat. No. 10,249,837

LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first electrode;
a first light-emitting layer, the first light-emitting layer comprising a first organic compound, a second organic compound, and a third organic compound;
a second light-emitting layer; and
a second electrode,
wherein the first light-emitting layer and the second light-emitting layer are interposed between the first electrode and the second electrode,
wherein a T1 level of the first organic compound is lower than a T1 level of the second organic compound and higher than a T1 level of the third organic compound,
wherein a lifetime of an emission from the second organic compound is more than or equal to 5 psec and less than or equal to 15 psec where the lifetime is a time required for the emission from the second organic compound to decrease in intensity to 1/100 of an initial value thereof, and
wherein an emission color from the second light-emitting layer is different from an emission color from the first light-emitting layer.

US Pat. No. 10,249,836

PHOTODETECTOR

Tsinghua University, Bei...

1. A photodetector comprising:a substrate,
an interdigital electrode layer comprising a first interdigital electrode and a second interdigital electrode, wherein the first interdigital electrode and the second interdigital electrode are spaced from and staggered with each other; and
a photoactive layer;
wherein the interdigital electrode layer is sandwiched between the substrate and the photoactive layer, the first interdigital electrode comprises a first connection part and a plurality of first interdigital parts in connection with the first connection part, and the plurality of first interdigital parts are parallel with and spaced apart from each other; the second interdigital electrode comprises a second connection part and a plurality of second interdigital parts in connection with the second connection part, and the plurality of second interdigital parts are parallel with and spaced apart from each other; the plurality of first interdigital parts and the plurality of second interdigital parts are staggered and spaced apart from each other, a distance between adjacent one of the plurality of first interdigital parts and one of the plurality of the second interdigital parts is about 20 ?m.

US Pat. No. 10,249,835

DISPLAY DEVICE AND PORTABLE TERMINAL

Samsung Display Co., Ltd....

1. A display device comprising:a display panel comprising a first portion, a second portion extending from the first portion, and a third portion extending from the second portion and facing the first portion, at least one of the first portion, the second portion, and the third portion comprising a display area configured to display an image;
a body configured to be located between the first and third portions and being configured to be separably coupled to the display panel in a first state, being configured to be separably coupled to the display panel in a second state, and being configured to be separated from each of the first portion, the second portion, and the third portion of the display panel, the body comprising a first surface, a second surface facing the first surface, a third surface connecting the first and second surfaces, and a fourth surface facing the third surface;
a driver configured to drive the display panel; and
a printed circuit board configured to apply a signal to the driver to drive the display panel, wherein the display panel covers the first, second, and third surfaces of the body in the first state, and wherein the display panel covers the first, second, and fourth surfaces of the body in the second state.

US Pat. No. 10,249,834

CARBENE METAL COMPLEXES AS OLED MATERIALS

The University of Souther...

1. A [carbene]mM-(X—Y)n compound, wherein the [carbene] ligand is of formula
wherein
Ring D is an aromatic cyclic ring or a fused aromatic cyclic ring;
Z1 is selected from a bond, O, or S;
A1 and A2 can be C or N;
R1 and R2 are independently selected from the group consisting of hydrogen, alkyl, alkenyl, alkynyl, aralkyl, CN, CF3, NR?2, NO2, OR?, SR?, halo, aryl, heteroaryl, substituted aryl, substituted heteroaryl, and a heterocyclic group; or alternatively, two adjacent R1 or R2 groups on the same or adjacent ring, together form independently a 5 or 6-member cyclic group, wherein the cyclic group is selected from cycloalkyl, cycloheteroalkyl, or heteroaryl; and wherein said cyclic group is optionally substituted by one or more substituents J, wherein each substituent J is independently selected from the group consisting of R?, CN, CF3, NR?2, NO2, OR?, and SR?, or alternatively, two J groups on adjacent ring atoms form a fused 5- or 6-membered aromatic group;
each R? is independently selected from the group consisting of halo, H, alkyl, alkenyl, alkynyl, heteroalkyl, aralkyl, aryl, and heteroaryl;
R3 is selected from the group consisting of hydrogen, alkyl, alkenyl, alkynyl, aralkyl, aryl, heteroaryl, substituted aryl, substituted heteroaryl, and a heterocyclic group;
a is 0, 1, 2, 3, or 4; c is 0, 1, or 2;
(X-Y) is selected from a photoactive ligand or an ancillary ligand; and
m is a value from 1 to a maximum number of ligands that can be attached to the metal M; and m+n is the maximum number of ligands that can be attached to the metal M.

US Pat. No. 10,249,833

PHTHALOCYANINE COMPOUND AND SYNTHESIS METHOD AND USE THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A synthesis method for a phthalocyanine compound consisting of a structure as represented by Formula I below,
wherein A represents a transition metal or a rare earth metal, and R1 represents a phenyl group, a naphthyl group, or a C4-C16 n-alkyl group, wherein the synthesis method comprises the steps of:

(1) reacting o-xylene with liquid bromine to produce a compound II of 4,5-dibromo-o-xylene;
(2) producing a compound III of 4,5-dibromo-o-phthalic acid from 4,5-dibromo-o-xylene under the action of potassium permanganate;
(3) reacting 4,5-dibromo-o-phthalic acid with R1Br in the presence of potassium hydroxide and a catalyst of tetraoctylammonium bromide to produce a compound IV;
(4) reacting the compound IV with cuprous cyanide to produce a compound V; and
(5) mixing and reacting the compound V with bis(diiminoisoindoline) and A(CH3COO)2 to produce a phthalocyanine compound consisting of a structure as represented by Formula I.

US Pat. No. 10,249,832

ORGANIC ELECTROLUMINESCENCE DEVICE AND NOVEL COMPOUND

IDEMITSU KOSAN CO., LTD.,...

1. A compound represented by the following formula (I):
wherein in the formula (I),
one or more pairs of adjacent two or more of R1 to R4 and R10 to R13 may form a substituted or unsubstituted, saturated or unsaturated ring;
R1 to R4, R10 to R13 and R17 that do not form the substituted or unsubstituted, saturated or unsaturated ring are independently a hydrogen atom, a substituted or unsubstituted aryl group including 6 to 20 ring carbon atoms or a substituted or unsubstituted monovalent heterocyclic group including 5 to 20 ring atoms;
two R17s may be the same or different; and
RA, RB, RC and RD are independently a substituted or unsubstituted aryl group including 6 to 20 ring carbon atoms.

US Pat. No. 10,249,831

ELECTRONIC DEVICE CONTAINING CYCLIC LACTAMS

Merck Patent GmbH, (DE)

1. An electronic device comprising at least one compound of the formula (1)or at least two compounds of the formula (1) that are connected via at least one common aromatic or heteroaromatic ring system Ar or at least two compounds of the formula (1) that have a common structural unitwhere the symbols used are as follows:X1, X2, X3, X4 are each independently CR or N;
Y at each instance is

Ar is the same or different at each instance and is an aromatic or heteroaromatic ring system which has 5-60 aromatic ring atoms and may be substituted by one or more R1 radicals;
Ar1is the same or different at each instance and is an aromatic or heteroaromatic ring system which has 5-30 aromatic ring atoms and may be substituted by one or more R1 radicals; at the same time, two Ar1 radicals bonded to the same nitrogen atom or phosphorus atom may also be bridged to one another by a single bond or a bridge selected from N(R1), C(R1)2 and O;
R is the same or different at each instance and is selected from the group consisting of H, D, F, Cl, Br, I, CN, CHO, NO2, Si(R2)3, B(OR2)2, N(Ar1)2, N(R1)2, C(?O)Ar1, C(?O)R1, P(?O)(Ar1)2, S(?O)Ar1, S(?O)(Ar1)2, CR2?CR2Ar1, C?CAr1, OSO2R1;
a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 carbon atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 carbon atoms or an alkenyl or alkynyl group having 2 to 40 carbon atoms, where the hydrocarbyl groups mentioned may each be substituted by one or more R1 radicals and where one or more nonadjacent CH2 groups may be replaced by R1C?CR1, —C?C—, Si(R1)2, Ge(R1)2, Sn(R1)2, C?O, C?S, C?Se, C?NR1, P(?O)(R1), SO, SO2, NR1, O, S or CONR1 and where one or more hydrogen atoms may be replaced by D, F, Cl, Br, I, CN or NO2;
an aromatic or heteroaromatic ring system which has 5 to 60 aromatic ring atoms and may be substituted in each case by one or more R1 radicals,
an aryloxy or heteroaryloxy group which has 5 to 60 aromatic ring atoms and may be substituted by one or more R1 radicals,
an aralkyl or heteroaralkyl group which has 5 to 60 aromatic ring atoms and may be substituted by one or more R1 radicals,
or a combination of these systems,
where two or more adjacent R substituents may form a monocyclic or polycyclic, aliphatic, aromatic or heteroaromatic ring system which may be substituted by one or more R1 radicals or
where the R substituent of X1 and/or the R substituent of X4 together with the adjacent N—Ar in each case may form a monocyclic or polycyclic, aliphatic, aromatic or heteroaromatic ring system which may be substituted by one or more R1 radicals;
R1 is in each case independently selected from the group consisting of H, D, F, CN, a straight-chain or branched alkyl group having 1 to 20 carbon atoms, a straight-chain or branched alkenyl group having 2 to 20 carbon atoms, an aromatic or heteroaromatic ring system which has 5 to 30 aromatic ring atoms and in which one or more hydrogen atoms may be replaced by D, F, Cl, Br, I, CN or a straight-chain or branched alkyl group having 1 to 10 carbon atoms or a straight-chain or branched alkenyl group having 2 to 10 carbon atoms,
where two or more adjacent R1 substituents together may form a mono- or polycyclic, aliphatic, aromatic or heteroaromatic ring system and
R2 is in each case independently selected from the group consisting of H, D or is an aliphatic, aromatic and/or heteroaromatic hydrocarbyl radical having 1 to 20 carbon atoms, where two or more R2 radicals together may also form a ring system.

US Pat. No. 10,249,830

CARBAZOLE-BASED COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A carbazole-based compound represented by Formula 1:
wherein, in Formulae 1 and 2,
R1 to R8 are each independently selected from a group represented by Formula 2, hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, and —Si(Q1)(Q2)(Q3), and at least one selected from R1 to R8 is a group represented by Formula 2,
ring A and ring B are each independently selected from a benzene, a naphthalene, an anthracene, and a phenanthrene,
R9 is selected from a group represented by Formula 2 and *-(L2)a2-Ar1,
L1 and L2 are each independently selected from a substituted or unsubstituted C3-C10 cycloalkylene group, a substituted or unsubstituted C1-C10 heterocycloalkylene group, a substituted or unsubstituted C3-C10 cycloalkenylene group, a substituted or unsubstituted C1-C10 heterocycloalkenylene group, a substituted or unsubstituted C6-C60 arylene group, a substituted or unsubstituted C1-C60 heteroarylene group, a substituted or unsubstituted divalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted divalent non-aromatic condensed heteropolycyclic group,
a1 and a2 are each independently selected from 0, 1, 2, 3, 4, and 5,
Ar1 is selected from a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group,
R11 and R12 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, and —Si(Q4)(Q5)(Q6),
b11 and b12 are each independently an integer selected from 0 to 9, and
at least one substituent of the substituted C3-C10 cycloalkylene group, substituted C1-C10 heterocycloalkylene group, substituted C3-C10 cycloalkenylene group, substituted C1-C10 heterocycloalkenylene group, substituted C6-C60 arylene group, substituted C1-C60 heteroarylene group, substituted divalent non-aromatic condensed polycyclic group, substituted divalent non-aromatic condensed heteropolycyclic group, substituted C1-C60 alkyl group, substituted C2-C60 alkenyl group, substituted C2-C60 alkynyl group, substituted C1-C60 alkoxy group, substituted C3-C10 cycloalkyl group, substituted C1-C10 heterocycloalkyl group, substituted C3-C10 cycloalkenyl group, substituted C1-C10 heterocycloalkenyl group, substituted C6-C60 aryl group, substituted C6-C60 aryloxy group, substituted C6-C60 arylthio group, substituted C1-C60 heteroaryl group, substituted monovalent non-aromatic condensed polycyclic group, and substituted monovalent non -aromatic condensed heteropolycyclic group is selected from the group consisting of:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q11)(Q12)(Q13), —N(Q14)(Q15), and —B(Q16)(Q17);
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a phenyl group, a biphenyl group, and a terphenyl group;
a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a phenyl group, a biphenyl group, and a terphenyl group, each substituted with at least one selected from deuterium, —F, —CI, —Br, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-Cio cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —Si(Q21)(Q22)(Q23), —N(Q24)(Q25), and —B(Q26)(Q27); and
—Si(Q31)(Q32)(Q33), —N(Q34)(Q35), and —B(Q36)(Q37),
wherein Q1 to Q6, Q11 to Q17, Q21 to Q27, and Q31 to Q37 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C1-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C1-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, a phenyl group, a biphenyl group, and a terphenyl group,
wherein, when R3 or R6 is a group represented by Formula 2; ring A and B are both a benzene; and a2 is 0, Ar1 is selected from a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C1-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C1-C10 heterocycloalkenyl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, and a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, a substituted or unsubstituted biphenyl group, a substituted or unsubstituted terphenyl group, a substituted or unsubstituted pentalenyl group, a substituted or unsubstituted indenyl group, a substituted or unsubstituted naphthyl group, a substituted or unsubstituted azulenyl group, a substituted or unsubstituted heptalenyl group, a substituted or unsubstituted indacenyl group, a substituted or unsubstituted acenaphthyl group, a substituted or unsubstituted fluorenyl group, a substituted or unsubstituted spiro-bifluorenyl group, a substituted or unsubstituted benzofluorenyl group, a substituted or unsubstituted dibenzofluorenyl group, a substituted or unsubstituted phenalenyl group, a substituted or unsubstituted phenanthrenyl group, a substituted or unsubstituted anthracenyl group, a substituted or unsubstituted fluoranthenyl group, a substituted or unsubstituted triphenylenyl group, a substituted or unsubstituted pyrenyl group, a substituted or unsubstituted chrysenyl group, a substituted or unsubstituted naphthacenyl group, a substituted or unsubstituted picenyl group, a substituted or unsubstituted perylenyl group, a substituted or unsubstituted pentaphenyl group, a substituted or unsubstituted hexacenyl group, a substituted or unsubstituted pentacenyl group, a substituted or unsubstituted rubicenyl group, a substituted or unsubstituted coronenyl group, a substituted or unsubstituted ovalenyl group, a substituted or unsubstituted pyrrolyl group, a substituted or unsubstituted thiophenyl group, a substituted or unsubstituted furanyl group, a substituted or unsubstituted imidazolyl group, a substituted or unsubstituted pyrazolyl group, a substituted or unsubstituted thiazolyl group, a substituted or unsubstituted isothiazolyl group, a substituted or unsubstituted oxazolyl group, a substituted or unsubstituted isoxazolyl group, a substituted or unsubstituted pyrazinyl group, a substituted or unsubstituted pyridazinyl group, a substituted or unsubstituted isoindolyl group, a substituted or unsubstituted indolyl group, a substituted or unsubstituted indazolyl group, a substituted or unsubstituted purinyl group, a substituted or unsubstituted quinolinyl group, a substituted or unsubstituted isoquinolinyl group, a substituted or unsubstituted benzoquinolinyl group, a substituted or unsubstituted phthalazinyl group, a substituted or unsubstituted naphthyridinyl group, a substituted or unsubstituted quinoxalinyl group, a substituted or unsubstituted quinazolinyl group, a substituted or unsubstituted cinnolinyl group, a substituted or unsubstituted carbazolyl group, a substituted or unsubstituted phenanthridinyl group, a substituted or unsubstituted acridinyl group, a substituted or unsubstituted phenanthrolinyl group, a substituted or unsubstituted phenazinyl group, a substituted or unsubstituted benzimidazolyl group, a substituted or unsubstituted benzofuranyl group, a substituted or unsubstituted dibenzofuranyl group, a substituted or unsubstituted benzothiophenyl group, a substituted or unsubstituted dibenzothiophenyl group, a substituted or unsubstituted isobenzothiazolyl group, a substituted or unsubstituted benzoxazolyl group, a substituted or unsubstituted isobenzoxazolyl group, a substituted or unsubstituted triazolyl group, a substituted or unsubstituted tetrazolyl group, a substituted or unsubstituted oxadiazolyl group, a substituted or unsubstituted benzocarbazolyl group, a substituted or unsubstituted dibenzocarbazolyl group, a substituted or unsubstituted thiadiazolyl group, a substituted or unsubstituted imidazopyridinyl group, a substituted or unsubstituted imidazopyrimidinyl group, a substituted or unsubstituted indenocarbazolyl group, a substituted or unsubstituted indolocarbazolyl group, a substituted or unsubstituted indolodibenzofuranyl group, a substituted or unsubstituted indolodibenzothiophenyl group, and a substituted or unsubstituted indolodibenzosilolyl group,
where at least one substituent of the substituted biphenyl group, substituted terphenyl group, substituted pentalenyl group, substituted indenyl group, substituted naphthyl group, substituted azulenyl group, substituted heptalenyl group, substituted indacenyl group, substituted acenaphthyl group, substituted fluorenyl group, substituted spiro-bifluorenyl group, substituted benzofluorenyl group, substituted dibenzofluorenyl group, substituted phenalenyl group, substituted phenanthrenyl group, substituted anthracenyl group, substituted fluoranthenyl group, substituted triphenylenyl group, substituted pyrenyl group, substituted chrysenyl group, substituted naphthacenyl group, substituted picenyl group, substituted perylenyl group, substituted pentaphenyl group, substituted hexacenyl group, substituted pentacenyl group, substituted rubicenyl group, substituted coronenyl group, substituted ovalenyl group, substituted pyrrolyl group, substituted thiophenyl group, substituted furanyl group, substituted imidazolyl group, substituted pyrazolyl group, substituted thiazolyl group, substituted isothiazolyl group, substituted oxazolyl group, substituted isoxazolyl group, substituted pyrazinyl group, substituted pyridazinyl group, substituted isoindolyl group, substituted indolyl group, substituted indazolyl group, substituted purinyl group, substituted quinolinyl group, substituted isoquinolinyl group, substituted benzoquinolinyl group, substituted phthalazinyl group, substituted naphthyridinyl group, substituted quinoxalinyl group, substituted quinazolinyl group, substituted cinnolinyl group, substituted carbazolyl group, substituted phenanthridinyl group, substituted acridinyl group, substituted phenanthrolinyl group, substituted phenazinyl group, substituted benzimidazolyl group, substituted benzofuranyl group, substituted dibenzofuranyl group, substituted benzothiophenyl group, substituted dibenzothiophenyl group, substituted isobenzothiazolyl group, substituted benzoxazolyl group, substituted isobenzoxazolyl group, substituted triazolyl group, substituted tetrazolyl group, substituted oxadiazolyl group, substituted benzocarbazolyl group, substituted dibenzocarbazolyl group, substituted thiadiazolyl group, substituted imidazopyridinyl group, substituted imidazopyrimidinyl group, substituted an indenocarbazolyl group, substituted indolocarbazolyl group, substituted indolodibenzofuranyl group, substituted indolodibenzothiophenyl group, and substituted indolodibenzosilolyl group is selected from the group consisting of:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, and a C1-C20 alkoxy group;
a phenyl group, a biphenyl group, a terphenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenanthrenyl group, an anthracenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isoxazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a carbazolyl group, a benzimidazolyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzoxazolyl group, an isobenzoxazolyl group, an oxadiazolyl group, a triazine group, a dibenzofuranyl group, a dibenzothiophenyl group, an imidazopyridinyl group, and an imidazopyrimidinyl group;
a phenyl group; a biphenyl group, a terphenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenanthrenyl group, an anthracenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isoxazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a carbazolyl group, a benzimidazolyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzoxazolyl group, an isobenzoxazolyl group, an oxadiazolyl group, a triazinyl group, a dibenzofuranyl group, a dibenzothiophenyl group, an imidazopyridinyl group, and an imidazopyrimidinyl group, each substituted with at least one selected from deuterium, —F, —CI, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C10 alkyl group, a C1-C10 alkoxy group, a biphenyl group, a terphenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenanthrenyl group, an anthracenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isoxazolyl group, a pyrazinyl group, a pyridazinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a quinoxalinyl group, a quinazolinyl group, a carbazolyl group, a benzimidazolyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzoxazolyl group, an isobenzoxazolyl group, an oxadiazolyl group, a dibenzofuranyl group, a dibenzothiophenyl group, an imidazopyridinyl group, an imidazopyrimidinyl group, and —Si (Q31)(Q32)(Q33); and
—Si(Q1)(Q2)(Q3),
wherein Q1 to Q3 and Q31 to Q33 are each independently selected from a C1-C10 alkyl group, a C1-C10 alkoxy group, a phenyl group, a biphenyl group, a terphenyl group, and a naphthyl group, and
when R3 or R6 is a group represented by Formula 2; ring A and B are both a benzene; and a2 is selected from 1, 2, 3, 4, and 5, L2 is selected from the group consisting of:
a pentalenylene group, an indenylene group, a naphthylene group, an azulenylene group, a heptalenylene group, an indacenylene group, an acenaphthylene group, a fluorenylene group, a spiro-fluorenylene group, a benzofluorenylene group, a dibenzofluorenylene group, a phenalenylene group, a phenanthrenylene group, an anthracenylene group, a fluoranthenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a naphthacenylene group, a picenylene group, a perylenylene group, a pentaphenylene group, a hexacenylene group, a pentacenylene group, a rubicenylene group, a coronenylene group, an ovalenylene group, a pyrrolylene group, a thiophenylene group, a furanylene group, an imidazolylene group, a pyrazolylene group, a thiazolylene group, an isothiazolylene group, an oxazolylene group, an isoxazolylene group, a pyrazinylene group, a pyridazinylene group, an isoindolylene group, an indolylene group, an indazolylene group, a purinylene group, a quinolinylene group, an isoquinolinylene group, a benzoquinolinylene group, a phthalazinylene group, a naphthyridinylene group, a quinoxalinylene group, a quinazolinylene group, a cinnolinylene group, a carbazolylene group, a phenanthridinylene group, an acridinylene group, a phenanthrolinylene group, a phenazinylene group, a benzimidazolylene group, a benzofuranylene group, a benzothiophenylene group, an isobenzothiazolylene group, a benzoxazolylene group, an isobenzoxazolylene group, a triazolylene group, a tetrazolylene group, an oxadiazolylene group, a dibenzofuranylene group, a dibenzothiophenylene group, a benzocarbazolylene group, a dibenzocarbazolylene group, a thiadiazolylene group, an imidazopyridinylene group, an imidazopyrimidinylene group, an indenocarbazolylene group, an indolocarbazolylene group, an indolodibenzofuranylene group, an indolodibenzothiophenylene group, and an indolodibenzosilolylene group; and
a pentalenylene group, an indenylene group, a naphthylene group, an azulenylene group, a heptalenylene group, an indacenylene group, an acenaphthylene group, a fluorenylene group, a spiro-fluorenylene group, a benzofluorenylene group, a dibenzofluorenylene group, a phenalenylene group, a phenanthrenylene group, an anthracenylene group, a fluoranthenylene group, a triphenylenylene group, a pyrenylene group, a chrysenylene group, a naphthacenylene group, a picenylene group, a perylenylene group, a pentaphenylene group, a hexacenylene group, a pentacenylene group, a rubicenylene group, a coronenylene group, an ovalenylene group, a pyrrolylene group, a thiophenylene group, a furanylene group, an imidazolylene group, a pyrazolylene group, a thiazolylene group, an isothiazolylene group, an oxazolylene group, an isoxazolylene group, a pyrazinylene group, a pyridazinylene group, an isoindolylene group, an indolylene group, an indazolylene group, a purinylene group, a quinolinylene group, an isoquinolinylene group, a benzoquinolinylene group, a phthalazinylene group, a naphthyridinylene group, a quinoxalinylene group, a quinazolinylene group, a cinnolinylene group, a carbazolylene group, a phenanthridinylene group, an acridinylene group, a phenanthrolinylene group, a phenazinylene group, a benzimidazolylene group, a benzofuranylene group, a benzothiophenylene group, an isobenzothiazolylene group, a benzoxazolylene group, an isobenzoxazolylene group, a triazolylene group, a tetrazolylene group, an oxadiazolylene group, a dibenzofuranylene group, a dibenzothiophenylene group, a benzocarbazolylene group, a dibenzocarbazolylene group, a thiadiazolylene group, an imidazopyridinylene group, an imidazopyrimidinylene group, an indenocarbazolylene group, an indolocarbazolylene group, an indolodibenzofuranylene group, an indolodibenzothiophenylene group, and an indolodibenzosilolylene group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C20 alkyl group, a C1-C20 alkoxy group, a cyclopentyl group, a cyclohexyl group, a cycloheptyl group, a cyclopentenyl group, a cyclohexenyl group, a phenyl group, a biphenyl group, a terphenyl group, a pentalenyl group, an indenyl group, a naphthyl group, an azulenyl group, a heptalenyl group, an indacenyl group, an acenaphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenalenyl group, a phenanthrenyl group, an anthracenyl group, a fluoranthenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, a naphthacenyl group, a picenyl group, a perylenyl group, a pentaphenyl group, a hexacenyl group, a pentacenyl group, a rubicenyl group, a coronenyl group, an ovalenyl group, a pyrrolyl group, a thiophenyl group, a furanyl group, an imidazolyl group, a pyrazolyl group, a thiazolyl group, an isothiazolyl group, an oxazolyl group, an isoxazolyl group, a pyridinyl group, a pyrazinyl group, a pyrimidinyl group, a pyridazinyl group, an isoindolyl group, an indolyl group, an indazolyl group, a purinyl group, a quinolinyl group, an isoquinolinyl group, a benzoquinolinyl group, a phthalazinyl group, a naphthyridinyl group, a quinoxalinyl group, a quinazolinyl group, a cinnolinyl group, a carbazolyl group, a phenanthridinyl group, an acridinyl group, a phenanthrolinyl group, a phenazinyl group, a benzimidazolyl group, a benzofuranyl group, a benzothiophenyl group, an isobenzothiazolyl group, a benzoxazolyl group, an isobenzoxazolyl group, a triazolyl group, a tetrazolyl group, an oxadiazolyl group, a triazinyl group, a dibenzofuranyl group, a dibenzothiophenyl group, a benzocarbazolyl group, a dibenzocarbazolyl group, a thiadiazolyl group, an imidazopyridinyl group, an imidazopyrimidinyl group, an indenocarbazolyl group, an indolocarbazolyl group, an indolodibenzofuranyl group, an indolodibenzothiophenyl group, an indolodibenzosilolyl —Si(Q31 )(Q32 )(Q33),
wherein Q31 to Q33 are each independently selected from a C1-C20 alkyl group, a C1-C20 alkoxy group, a phenyl group, a biphenyl group, a terphenyl group, a naphthyl group, a fluorenyl group, a spiro-fluorenyl group, a benzofluorenyl group, a dibenzofluorenyl group, a phenanthrenyl group, an anthracenyl group, a triphenylenyl group, a pyrenyl group, a chrysenyl group, and a carbazolyl group.

US Pat. No. 10,249,829

COMPOUND AND ORGANIC LIGHT-EMITTING DEVICE INCLUDING THE SAME

Samsung Display Co., Ltd....

1. A compound represented by Formula 1:
wherein, in Formula 1,
X and Y are each independently selected from O, S, CR11R12, and NR13,
R1, R11, R12, and R13 are each independently selected from hydrogen, deuterium, a halogen atom, a nitro group, a cyano group, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C10 cycloalkyl group, a substituted or unsubstituted C2-C10 heterocycloalkyl group, a substituted or unsubstituted C3-C10 cycloalkenyl group, a substituted or unsubstituted C2-C10 heterocycloalkenyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C1-C60 heteroaryl group, a substituted or unsubstituted monovalent non-aromatic condensed polycyclic group, a substituted or unsubstituted monovalent non-aromatic condensed heteropolycyclic group, a substituted or unsubstituted C5-C60 carbocyclic group, and a substituted or unsubstituted C1-C60 heterocyclic group,
at least one selected from X, Y, and R1 comprises —P(Ph)2=Z,
Z is selected from O and S,
at least one substituent of the substituted C1-C60 alkyl group, the substituted C2-C60 group, the substituted C2-C60 alkynyl group, the substituted C1-C60 alkoxy group, the substituted C3-C10 cycloalkyl group, the substituted C2-C10 heterocycloalkyl group, the substituted C3-C10 cycloalkenyl group, the substituted C2-C10 heterocycloalkenyl group, the substituted C6-C60 aryl group, the substituted C6-C60 aryloxy group, the substituted C6-C60 arylthio group, the substituted C1-C60 heteroaryl group, the substituted monovalent non-aromatic condensed polycyclic group, the substituted monovalent non-aromatic condensed heteropolycyclic group, the substituted or unsubstituted C5-C60 carbocyclic group, and the substituted or unsubstituted C1-C60 heterocyclic group is selected from the group consisting of:
deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 alkoxy group;
a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, and a C1-C60 group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q11)(Q12), —Si(Q13)(Q14)(Q15), and —B(Q16)(Q17);
a C3-C10 cycloalkyl group, C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group;
a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group, each substituted with at least one selected from deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 a cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C6-C60 aryloxy group, a C6-C60 arylthio group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, a monovalent non-aromatic condensed heteropolycyclic group, —N(Q21)(Q22), —Si(Q23)(Q24)(Q25), and —B(Q26)(Q27); and
—P(?O)Q1Q2 and —P(?S)Q3Q4,
wherein Q1 to Q4, Q11 to Q17, and Q21 to Q27 are each independently selected from hydrogen, deuterium, —F, —Cl, —Br, —I, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine group, a hydrazone group, a carboxylic acid group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a C1-C60 alkyl group, a C2-C60 alkenyl group, a C2-C60 alkynyl group, a C1-C60 alkoxy group, a C3-C10 cycloalkyl group, a C2-C10 heterocycloalkyl group, a C3-C10 cycloalkenyl group, a C2-C10 heterocycloalkenyl group, a C6-C60 aryl group, a C1-C60 heteroaryl group, a monovalent non-aromatic condensed polycyclic group, and a monovalent non-aromatic condensed heteropolycyclic group.

US Pat. No. 10,249,828

ORGANIC ELECTROLUMINESCENT DEVICE

Merck Patent GmbH, (DE)

1. An organic electroluminescent device comprising cathode, anode and emitting layer, which consists of the following compounds:(A) at least one luminescent organic compound which has a separation between the lowest triplet state T1 and the first excited singlet state S1 of ?0.15 eV (TADF compound);
wherein the at least one TADF compound is a luminescent organic compound which is an aromatic compound which contains both donor and acceptor substituents, where the donor substituents are selected from the group consisting of diarylamino groups, heteroarylamino groups, carbazole groups and carbazole derivatives, which may in each case also be substituted, and where the acceptor substituents are selected from the group consisting of cyano groups and electron-deficient heteroaryl groups, which are optionally substituted, and which has a separation between the lowest triplet state T1 and the first excited singlet state S1 of <0.15 eV; and
(B) at least one compound of the formula (1),

where the following applies to the symbols used:
X is on each occurrence, identically or differently, CR or N, or a group X-X stands for a group of the following formula (2), with the proviso that at least one group X-X stands for a group of the formula (2) and that a maximum of one group X-X per ring stands for a group of the formula (2),

where the C atoms with the dashed bonds indicate the bonding of the group;
Y1, Y2 are selected on each occurrence, identically or differently, from the group consisting of CR2, NR, O, S, SiR2, BR, PR and P(?O)R;
E is selected on each occurrence, identically or differently, from the group consisting of a single bond, CR2, NR, O, S, SiR2, BR, PR and P(?O)R;
W is on each occurrence, identically or differently, CR or N;
R is selected on each occurrence, identically or differently, from the group consisting of H, D, F, Cl, Br, I, CN, NO2, N(Ar)2, N(R1)2, C(?O)Ar, C(?O)R1, P(?O)(Ar)2, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 C atoms or an alkenyl or alkynyl group having 2 to 40 C atoms, each of which is optionally substituted by one or more radicals R1, where one or more non-adjacent CH2 groups is optionally replaced by R1C?CR1, C?C, Si(R1)2, C?O, C?S, C?NR1, P(?O)(R1), SO, SO2, NR1, O, S or CONR1 and where one or more H atoms is optionally replaced by D, F, CI, Br, I, CN or NO2, an aromatic or heteroaromatic ring system having 5 to 80, which may in each case be substituted by one or more radicals R?, an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, which is optionally substituted by one or more radicals R1, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, which is optionally substituted by one or more radicals R1, where two or more adjacent substituents R may optionally form a monocyclic or polycyclic, aliphatic, aromatic or heteroaromatic ring system, which is optionally substituted by one or more radicals R1;
R1 is selected on each occurrence, identically or differently, from the group consisting of H, D, F, Cl, Br, I, CN, NO2, N(Ar)2, N(R2)2, C(?O)Ar, C(?O)R2, P(?O)(Ar)2, a straight-chain alkyl, alkoxy or thioalkyl group having 1 to 40 C atoms or a branched or cyclic alkyl, alkoxy or thioalkyl group having 3 to 40 C atoms or an alkenyl or alkynyl group having 2 to 40 C atoms, each of which is optionally substituted by one or more radicals R2, where one or more non-adjacent CH2 groups is optionally replaced by R2C?CR2, C?C, Si(R2)2, C?O, C?S, C?NR2, P(?O)(R2), SO, SO2, NR2, O, S or CONR2 and where one or more H atoms is optionally replaced by D, F, Cl, Br, I, CN or NO2, an aromatic or heteroaromatic ring system having 5 to 60 aromatic ring atoms, which may in each case be substituted by one or more radicals R2, an aryloxy or heteroaryloxy group having 5 to 60 aromatic ring atoms, which is optionally substituted by one or more radicals R2, or an aralkyl or heteroaralkyl group having 5 to 60 aromatic ring atoms, where two or more adjacent substituents R1 may optionally form a monocyclic or polycyclic, aliphatic, aromatic or heteroaromatic ring system, which is optionally substituted by one or more radicals R2;
Ar is on each occurrence, identically or differently, an aromatic or heteroaromatic ring system having 5-30 aromatic ring atoms, which is optionally substituted by one or more non-aromatic radicals R2; two radicals Ar which are bonded to the same N atom or P atom here may also be bridged to one another by a single bond or a bridge selected from N(R2), C(R2)2, O or S; and
R2 is selected from the group consisting of H, D, F, CN, an aliphatic hydrocarbon radical having 1 to 20 C atoms, an aromatic or heteroaromatic ring system having 5 to 30 aromatic ring atoms, in which one or more H atoms is optionally replaced by D, F, Cl, Br, I or CN, where two or more adjacent substituents R2 may form a mono- or polycyclic, aliphatic, aromatic or heteroaromatic ring system with one another.

US Pat. No. 10,249,827

AZADIBENZOFURANS FOR ELECTRONIC APPLICATIONS

UDC Ireland Limited, Dub...

1. A compound of the formulawhereinB1 is N, or CR81,
B2 is N, or CR82,
B3 is N, or CR83,
B4 is N, or CR84,
B5 is N, or CR85,
B6 is N, or CR86,
B7 is N, or CR87,
B8 is N, or CR88,
R81, R82, R83, R84, R85, R86, R87 and R88 are independently of each other H, a C1-C25 alkyl group, which can optionally be substituted by E and or interrupted by D; a C6-C24 alkyl group, which can optionally be substituted by G, a C2-C30 heteroaryl group, which can optionally be substituted by G; or a group of formula -(A1)o-(A2)p-(A3)q-(A4)r-R16,
o is 0, or 1, p is 0, or 1, q is 0, or 1, r is 0, or 1,
A1, A2, A3 and A4 are independently of each other a C6-C24 arylene group, which can optionally be substituted by G, or a C2-C30 heteroarylene group, which can optionally be substituted by G;
R16 is —NR10R11, or —Si(R12)(R13) (R14), a C6-C24 aryl group, which can optionally be substituted by G; or a C2-C30 heteroarylene group, which can optionally be substituted by G;
R10 and R11 are independently of each other a C6-C24 aryl group, which can optionally be substituted by G; or a C2-C30 heteroaryl group, which can optionally be substituted by G;
R12, R13 and R14 are independently of each other a C1-C25 alkyl group, which can optionally be substituted by E and or interrupted by D; C6-C24 aryl group, which can optionally be substituted by G; or a C2-C30 heteroaryl group, which can optionally be substituted by G;
D is —CO—, —COO—, —S—, —SO—, —SO2—, —O—, —NR65—, —SiR70R71—, —POR72—, —CR63?CR64—, or —C?C—,
E is —OR69, —SR69, —NR65R66, —COR68, —COOR67, —CONR65R66, —CN, or F,
G is E, or a C1-C18 alkyl group, a C6-C24 aryl group, a C6-C24 aryl group, which is substituted by F, C1-C18 alkyl, or C1-C18 alkyl which is interrupted by O; a C2-C30 hereroaryl group, or a C2-C30 heteroaryl group, which is substituted by F, C1-C18 alkyl, or C1-C18 alkyl which is interrupted by —O—;
R63 and R64 are independently of each other H, C6-C18 aryl; C6-C18 aryl which is substituted by C1-C18 alkyl, or C1-C18 alkoxy; C1-C18 alkyl; or C1-C18 alkyl which is interrupted by —O—;
R65 and R66 are independently of each other a C6-C18 aryl group; a C6-C18 aryl which is substituted by C1-C18 alkyl, or C1-C18 alkoxy; a C1-C18 alkyl group; or a C1-C18 alkyl group, which is interrupted by —O—; or
R65 and R66 together fonn a five or six membered ring,
R67 is a C6-C18 aryl group; a C6-C18 aryl group, which is substituted by C1-C18 alkyl, or C1-C18 alkoxy; a C1-C18 alkyl group; or a C1-C18 alkyl group, which is interrupted by —O—,
R68 is H; n a C6-C18 aryl group; a C6-C18 aryl group, which is substituted by C1-C18 alkyl, or C1-C18 alkoxy; a C1-C18 alkyl group; or a C1-C18 alkyl group, which is interrupted by —O—,
R69 is a C6-C18 aryl; a C6-C18 aryl, which is substituted by C1-C18 alkyl, or C1-C18 alkoxy, a C1-C18 alkyl group; or a C1-C18 alkyl group, which is interrupted by —O—,
R70 and R71 are independently of each other a C1-C18 alkyl group, a C6-C18 aryl group, or a C6-C18 aryl group, which is substituted by C1-C18 alkyl, and
R72 is a C1-C18 alkyl group, a C6-C18 aryl group, or a C6-C18 aryl group, which is substituted by C1-C18 alkyl, with the proviso that
at least one of the substituents B1, B2, B3, B4, B5, B6, B7 and B8 represents N;
not more than two of the groups B1, B2, B3 and B4 represent N; and
not more than two of the groups B5, B6, B7 and B8 represent N; and
with the further proviso that at least one of the substituents R81, R82, R83, R84, R85, R86, R87 and R88 represent a group of formula -(A1)o-(A2)p-(A3)q-(A4)r-R16, wherein R16 represents a benzimidazo[1,2-a]benzimidazo-5-yl group, which can optionally be substituted by G; and/or at least one of the groups A1, A2, A3 and A4 represents a benzimidazo[1,2-a]benzimidazo-2,5-ylene group, which can optionally be substituted by G.

US Pat. No. 10,249,826

COMPOUND, ORGANIC ELECTROLUMINESCENT ELEMENT AND ELECTRONIC DEVICE

IDEMITSU KOSAN CO., LTD.,...

1. An organic electroluminescence device, comprising:an anode;
an emitting layer; and
a cathode,
wherein
wherein the emitting layer contains no metal complex,
the emitting layer comprises a first compound and a second compound,
the first compound is a delayed-fluorescent compound represented by a formula (1) below,
the first compound has a lower singlet energy than a singlet energy of the second compound, and
the second compound has at least one of a partial structure represented by a formula (21) below and a partial structure represented by a formula (22) below in one molecule,

where:
Ar11 and Ar12 are each independently a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, or a substituted or unsubstituted heterocyclic group having 5 to 30 ring atoms;
L1 is a single bond or a linking group, the linking group in L1 being a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms or a substituted or unsubstituted heterocyclic group having 5 to 30 ring atoms;
Y1 to Y12 are each independently a nitrogen atom or CR1;
X1 is an oxygen atom, a sulfur atom, N—R10, CR11R12, SiR13R14 or GeR15R16;
R1 and R10 to R16 are each independently a hydrogen atom or a substituent;
when R1 and R10 to R16 are substituents, the substituents are each selected from the group consisting of a substituted or unsubstituted aromatic hydrocarbon group having 6 to 30 ring carbon atoms, a substituted or unsubstituted heterocyclic group having 5 to 30 ring atoms, a substituted or unsubstituted alkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted fluoroalkyl group having 1 to 30 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 30 carbon atoms, a substituted or unsubstituted aralkyl group having 7 to 30 carbon atoms, a substituted silyl group, a substituted germanium group, a substituted phosphine oxide group, a fluorine atom, a cyano group, a nitro group, and a carboxy group;
a plurality of R1 are optionally mutually the same or different; and
when at least two of the plurality of R1 are substituents, the substituents R1 are optionally mutually bonded to form a cyclic structure,

in the formula (21):
Y21 to Y26 are each independently a nitrogen atom or a carbon atom bonded to another atom in the molecule of the second compound; and
at least one of Y21 to Y26 is a carbon atom bonded to another atom in the molecule of the second compound, and
in the formula (22):
Y31 to Y38 are each independently a nitrogen atom or a carbon atom bonded to another atom in the molecule of the second compound;
at least one of Y31 to Y38 is a carbon atom bonded to another atom in the molecule of the second compound; and
x2 is a nitrogen atom, an oxygen atom or a sulfur atom.

US Pat. No. 10,249,825

COMPOUND FOR ORGANIC ELECTRIC ELEMENT, ORGANIC ELECTRIC ELEMENT COMPRISING THE SAME AND ELECTRONIC DEVICE THEREOF

DUK SAN NEOLUX CO., LTD.,...

1. A compound represented by Formula 1 below:
wherein,
m is an integer from 1 to 4,
n is an integer from 1 to 3,
R1 and R2 are independently selected from the group consisting of hydrogen, deuterium, tritium, halogen, a C6-C60 aryl group, a fluorenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C1-C50 alkyl group, a C2-C20 alkenyl group, a C1-C30 alkoxy group, and a C6-C30 aryloxy group,
Ar1 is selected from the group consisting of a fluorenyl group, a C6-C60 aryl group, a C2-C20 alkenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C1-C50 alkyl group, -L2-N(Ar2)(Ar3), and a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring,
L1 and L2 are independently selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, a C2-C60 bivalent heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a bivalent fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring, and a bivalent aliphatic hydrocarbon group,
Ar2 and Ar3 are independently selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C1-C50 alkyl group, a fused ring group of a C3-C60 aliphatic ring and a C6-C60 aromatic ring, and a C2-C20 alkenyl group, and
the aryl group, heterocyclic group, fluorenyl group, alkyl group, alkenyl group, fused ring group, alkoxy group, aryloxy group, arylene group, fluorenylene group and aliphatic hydrocarbon group may be substituted by one or more substituents selected from the group consisting of deuterium, halogen, a silane group, a boron group, a germanium group, a cyano group, a nitro group, -L?-N(R?)(R?), a C1-C20 alkylthio group, a C1-C20 alkoxy group, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, a C2-C20 heterocyclic group, a C3-C20 cycloalkyl group, a C7-C20 arylalkyl group, and a C8-C20 arylalkenyl group, wherein L? is selected from the group consisting of a single bond, a C6-C60 arylene group, a fluorenylene group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P; a fused ring group of a C3-C60aliphatic ring and a C6-C60 aromatic ring, and a C2-C60 bivalent aliphatic hydrocarbon group, and R? and R? are independently from each other selected from the group consisting of a C6-C60 aryl group, a fluorenyl group, a C2-C60heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C1-C20 alkyl group, and a C2-C20 alkenyl group,
with the proviso that: where Ar1 is a substituted C6-C60 aryl group, the substituent is selected from the group consisting of deuterium, halogen, a silane group, a boron group, a germanium group, a cyano group, a nitro group, -L?-N(R?)(R?), a C1-C20 alkylthio group, a C1-C20 alkoxy group, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C6-C14 aryl group, a C6-C20 aryl group substituted by deuterium, a C2-C20 heterocyclic group, a C3-C20 cycloalkyl group, a C7-C20 arylalkyl group, and a C8-C20 arylalkenyl group; and where R1 or R2 is a substituted C6-C60 aryl group, the substituent is selected from the group consisting of deuterium, halogen, a silane group, a boron group, a germanium group, a cyano group, a nitro group, a C1-C20 alkylthio group, a C1-C20 alkoxy group, a C1-C20 alkyl group, a C2-C20 alkenyl group, a C2-C20 alkynyl group, a C6-C20 aryl group, a C6-C20 aryl group substituted by deuterium, a C2-C20 heterocyclic group, a C3-C20 cycloalkyl group, a C7-C20 arylalkyl group, and a C8-C20 arylalkenyl group, and
with the proviso that:
where Ar1 is a C6-C60 aryl group, L1 is a single bond, and one of Ar2 and Ar3 is a C6-C60 aryl group or a fluorenyl group, the other of Ar2 and Ar3 is selected from the group consisting of:
wherein Q1 is C(Ra);wherein Q1 is C(Ra);wherein Q2 is C(Rb)(Rc), N(Rd), S, or O;
wherein Ra and Re are independently selected from the group consisting of hydrogen, deuterium, a C6-C60 aryl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C1-C50 alkyl group, a C2-C20 alkenyl group, a C1-C30 alkoxy group, and a fluorenyl group, or any two adjacent groups of Res can be optionally linked together to form at least one aromatic ring,
Rb to Rd are independently selected from the group consisting of a C6-C60 aryl group, a C2-C60 heterocyclic group containing at least one heteroatom selected from the group consisting of O, N, S, Si, and P, a C1-C50 alkyl group, a C2-C20 alkenyl group, and a C1-C30 alkoxy group, wherein Rb and Rc are optionally linked together to form at least one spiro compound.

US Pat. No. 10,249,824

CONDENSED-CYCLIC COMPOUND AND ORGANIC LIGHT-EMITTING DIODE COMPRISING THE SAME

Samsung Display Co., Ltd....

1. A condensed-cyclic compound represented by Formula 1:
wherein:
X1 is N or C(R1), X2 is N or C(R2), X3 is N or C(R3), and X4 is N or C(R4), wherein at least one of X1 through X4 is N;
ring A is a substituted or unsubstituted naphthalene, a substituted or unsubstituted pyrimidine, a substituted or unsubstituted isoquinoline, a substituted or unsubstituted benzothiophene, a substituted or unsubstituted benzofuran, a substituted or unsubstituted dibenzothiophene, or a substituted or unsubstituted dibenzofuran;
each of R1 through R4, R11 and R12 is independently a hydrogen atom, a deuterium atom, a halogen atom, a hydroxyl group, a cyano group, a nitro group, an amino group, an amidino group, a hydrazine, a hydrazone, a carboxyl group or a salt thereof, a sulfonic acid group or a salt thereof, a phosphoric acid group or a salt thereof, a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C60 cycloalkyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C2-C60 heteroaryl group, —Si(R31)(R32)(R33), or —N(R34)(R35); and
each of R31 through R35 is independently a substituted or unsubstituted C1-C60 alkyl group, a substituted or unsubstituted C2-C60 alkenyl group, a substituted or unsubstituted C2-C60 alkynyl group, a substituted or unsubstituted C1-C60 alkoxy group, a substituted or unsubstituted C3-C60 cycloalkyl group, a substituted or unsubstituted C6-C60 aryl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, or a substituted or unsubstituted C2-C60 heteroaryl group; and
at least one of R11 or R12 is a substituted or unsubstituted C3-C60 cycloalkyl group, a substituted or unsubstituted C6-C60 aryloxy group, a substituted or unsubstituted C6-C60 arylthio group, a substituted or unsubstituted C2-C60 heteroaryl group, a substituted or unsubstituted phenyl group, a substituted or unsubstituted pentalenyl group, a substituted or unsubstituted indenyl group, a substituted or unsubstituted naphthyl group, a substituted or unsubstituted anthracenyl group, a substituted or unsubstituted azulenyl group, a substituted or unsubstituted heptalenyl group, a substituted or unsubstituted indacenyl group, a substituted or unsubstituted acenaphthyl group, a substituted or unsubstituted phenalenyl group, a substituted or unsubstituted anthraquinolyl group, a substituted or unsubstituted fluorenyl group, a substituted or unsubstituted phenalenyl group, a substituted or unsubstituted phenanthrenyl group, a substituted or unsubstituted anthryl group, a substituted or unsubstituted fluoranthenyl group, a substituted or unsubstituted pyrenyl group, a substituted or unsubstituted chrysenyl group, a substituted or unsubstituted naphthacenyl group, a substituted or unsubstituted picenyl group, a substituted or unsubstituted perylenyl group, a substituted or unsubstituted pentacenyl group, a substituted or unsubstituted tetraphenylenyl group, a hexaphenyl group, a substituted or unsubstituted rubicenyl group, a substituted or unsubstituted coronenyl group, a substituted or unsubstituted trinaphthylenyl group, a substituted or unsubstituted heptaphenyl group, a substituted or unsubstituted heptacenyl group, a substituted or unsubstituted pyranthrenyl group, a substituted or unsubstituted ovalenyl group, or a substituted or unsubstituted hexacenyl group.

US Pat. No. 10,249,823

FULLERENE DERIVATIVES AND PHOTOELECTRIC DEVICES AND IMAGE SENSORS

Samsung Electronics Co., ...

1. A compound, comprising:a fullerene derivative represented by Chemical Formula 1:

wherein, in Chemical Formula 1,
Ra is hydrogen or a C1 to C10 alkyl group,
R1 to R5 are independently one of
a substituted or unsubstituted C1 to C10 alkyl group, or
a substituted or unsubstituted C6 to C12 aryl group, and
at least one of R1 to R5 is
a C1 to C10 alkyl group substituted with at least one of a fluorine and a cyano group, or
a C6 to C12 aryl group substituted with at least one of a fluorine and a cyano group.

US Pat. No. 10,249,822

POLYMER BLENDS FOR A SEMICONDUCTING LAYER OF AN ORGANIC ELECTRONIC DEVICE

Cambridge Display Technol...

1. A polymer blend for a semiconducting layer of an organic electronic device, comprising: a first polymer; a second polymer which is different from the first polymer; and a semiconductor compound selected from the group of pentacene derivatives and thiophene derivatives, wherein the first polymer iswherein R1 and R2 are the same or different and each is independently selected from the group consisting of hydrogen and a linear, branched or cyclic alkyl group having from 1 to 16 carbon atoms, and wherein n is an integer of 30 or more.

US Pat. No. 10,249,820

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device comprising:a plurality of first conductive patterns on a substrate, each of the plurality of first conductive patterns extending in a first direction parallel to a top surface of the substrate;
a first selection pattern on each of the plurality of first conductive patterns;
a first structure on the first selection pattern, the first structure including a first variable resistance pattern and a first heating electrode, and the first variable resistance pattern and the first heating electrode contacting each other to have a first contact area therebetween;
a plurality of second conductive patterns on the first structures, each of the plurality of second conductive patterns extending in a second direction parallel to the top surface of the substrate, the second direction crossing the first direction;
a second selection pattern on each of the plurality of second conductive patterns;
a second structure on the second selection pattern, the second structure including a second variable resistance pattern and a second heating electrode, the second variable resistance pattern and the second heating electrode contacting each other to have a second contact area therebetween, and the second contact area being different from the first contact area; and
a plurality of third conductive patterns on the second structures,
wherein the first contact area and the second contact area are separated by each of the plurality of second conductive patterns in a third direction perpendicular to the first and second directions.

US Pat. No. 10,249,819

METHODS OF FORMING SEMICONDUCTOR STRUCTURES INCLUDING MULTI-PORTION LINERS

Micron Technology, Inc., ...

1. A method of forming a semiconductor structure, the method comprising:forming a protective portion of a liner on stack structures on a material, the protective portion comprising silicon carboxynitride and the stack structures comprising chalcogenide materials and carbon materials; and
forming a conformal portion of the liner on the protective portion of the liner, the conformal portion comprising silicon carboxynitride and the silicon carboxynitride of the protective portion comprising a lower amount of carbon than the silicon carboxynitride of the conformal portion.

US Pat. No. 10,249,818

MEMORY ELEMENT

Toshiba Memory Corporatio...

1. A memory element, comprising:a first layer, the first layer being conductive;
a second layer, the second layer being conductive; and
a third layer including hafnium oxide and being provided between the first layer and the second layer,
the first layer including
a first region including a first element and a first metallic element, the first element being selected from a group consisting of carbon and nitrogen,
a second region including a second metallic element and being provided between the first region and the third layer, and
a third region including titanium oxide and being provided between the second region and the third layer.

US Pat. No. 10,249,817

MAGNETIC DEVICE

Samsung Electronics Co., ...

1. A magnetic device, comprising:a free layer;
a pinned layer;
a tunnel barrier disposed between the free layer and the pinned layer;
a polarization enhancement layer disposed between the tunnel barrier and the pinned layer; and
a blocking layer disposed between the polarization enhancement layer and the pinned layer,
wherein the blocking layer comprises a transition metal and a magnetic material.

US Pat. No. 10,249,816

MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE

SAMSUNG ELECTRONICS CO., ...

1. A magnetoresistive random access memory device, comprising:a memory structure on a substrate, the memory structure including a lower electrode, a magnetic tunnel junction structure, and an upper electrode sequentially stacked;
a first capping layer covering a surface of the memory structure, the first capping layer having a first nitrogen concentration;
a second capping layer on the first capping layer, the second capping layer having a second nitrogen concentration greater than the first nitrogen concentration;
an insulating interlayer on the second capping layer; and
a wiring through the insulating interlayer to be electrically connected to the upper electrode.

US Pat. No. 10,249,815

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME INCLUDING VARIABLE RESISTANCE ELEMENT AND LOWER CONTACT PLUG WITH SIDEWALLS ALIGNED TO EACH OTHER

SK hynix Inc., Icheon-si...

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory comprises:a variable resistance element that exhibits different resistance states for storing data; and
a lower contact plug coupled to the variable resistance element and disposed under the variable resistance element, and
wherein the variable resistance element includes a lower electrode disposed over the lower contact plug to contact with the lower contact plug and an upper electrode disposed over the lower electrode,
wherein the semiconductor memory further includes an upper contact plug disposed over the upper electrode to contact with the upper electrode,
wherein sidewalls of the variable resistance element and the lower contact plug are aligned with each other,
wherein a sidewall of the upper electrode is not aligned with a sidewall of the upper contact plug, and
wherein widths of the lower contact plug, the lower electrode, the variable resistance element, and the upper electrode increase from a top surface of the upper electrode to a bottom surface of the lower contact plug.

US Pat. No. 10,249,814

DYNAMIC MEMORY PROTECTION

QUALCOMM Incorporated, S...

1. A method of protecting data in a memory in an electronic device, comprising:storing data in a first memory in the electronic device;
determining, via a magnetic sensor, a strength of an ambient magnetic field;
comparing the strength of the ambient magnetic field to a threshold;
transferring the data in the first memory to a second memory in the electronic device upon determining that the strength of the ambient magnetic field exceeds the threshold; and
transferring the data from the second memory to the first memory upon determining that the strength of the ambient magnetic field no longer exceeds the threshold.

US Pat. No. 10,249,812

FILTER AND MULTIPLEXER

TAIYO YUDEN CO., LTD., T...

1. A filter comprising:an input terminal;
an output terminal; and
a ladder circuit that includes one or more series acoustic wave resonators connected in series between the input terminal and the output terminal and one or more parallel acoustic wave resonators connected in parallel between the input terminal and the output terminal, and in which characteristic impedance of at least one point in a pathway between the input terminal and the output terminal at a center frequency of a passband is greater than input impedance of the input terminal and output impedance of the output terminal at the center frequency of the passband.

US Pat. No. 10,249,811

PIEZOELECTRIC DRIVING DEVICE, ROBOT, AND DRIVING METHOD OF THE SAME

Seiko Epson Corporation, ...

1. A piezoelectric driving device comprising:a first vibrating plate;
a first electrode that is provided on the first vibrating plate;
a piezoelectric member that is provided above the first vibrating plate;
a second electrode that is provided on the piezoelectric member;
a second vibrating plate that is provided above the first and second electrodes, the second vibrating plate having top and bottom surfaces opposite to each other, the bottom surface facing the first and second electrodes; and
a wiring pattern that is provided on the bottom surface of the second vibrating plate, the wiring pattern including a wiring member, the wiring member being located at a first area of the bottom surface,
wherein the first area correspond to the second electrode in a plan view, and
the wiring member of the wiring pattern is electrically connected to the second electrode.

US Pat. No. 10,249,810

STRUCTURALLY EMBEDDED AND INHOSPITABLE ENVIRONMENT SYSTEMS AND DEVICES HAVING AUTONOMOUS ELECTRICAL POWER SOURCES

1. An electrically-energized device, comprising:at least one of an electrically-energized sensor and an electrically-energized communication element;
an electrical power source configured to provide electrical energy to power the at least one of the electrically-energized sensor and the electrically-energized communication element, the electrical power source including one or more electrical power source components, at least one of the one or more electrical power source components comprising:
a first conductor formed of a first conductive material and having a first surface and a second surface, the first surface of the first conductor facing away from a build surface and being conditioned to have a first work function value,
a dielectric layer with a thickness in a range of 200 angstroms or less formed over the conditioned first surface of the first conductor, and
a second conductor formed of a second conductive material and having a first surface with a second work function value, and having a second surface, and being arranged over the dielectric layer such that the first surface of the second conductor faces the dielectric layer,
the first conductor, the dielectric layer and the second conductor forming a layered structure of the electrical power source component;
a first electrical lead and a second electrical lead electrically connecting the at least one of the electrically-energized sensor and the electrically-energized communication element with the electrical power source,
the first work function value and the second work function value being in a range of 5.0 electron volts (eV) or less, and
the first work function value being at least 1.0 eV less than the second work function value.

US Pat. No. 10,249,809

ELECTRIC POWER GENERATION

1. A system comprising: a feed water pump; a line linking the feed water pump to a boiler, the boiler heating cold fluid from the feed water pump to produce hot fluid; a line linking the boiler to a turbine and a feed water reheater, the line providing a first portion of the hot fluid from the boiler to the turbine and a second portion of the hot fluid from the boiler to the feed water reheater; and a first generator unit for receiving hot fluid only from the feed water reheater and condensate from a condenser, the first generator unit generating electric power from a difference between a temperature of the hot fluid from the feed water reheater and the temperature of the condensate from the condenser.

US Pat. No. 10,249,808

SURFACE DOPING OF NANOSTRUCTURES

The Regents of the Univer...

1. A material comprising:a plurality of tellurium nanowires, the plurality of tellurium nanowires comprising a p-type semiconductor, the plurality of tellurium nanowires consisting essentially of tellurium; and
S2? or SH? species disposed on surfaces of each of the plurality of tellurium nanowires, charge carriers comprising electrons being transferred between the S2? or SH? species and the plurality of tellurium nanowires, the S2? or SH? species shifting the Fermi level of each the plurality of tellurium nanowires towards the conduction band, and the S2? or SH? species changing the plurality of tellurium nanowires to an n-type semiconductor.

US Pat. No. 10,249,806

SOLID STATE OPTOELECTRONIC DEVICE WITH PREFORMED METAL SUPPORT SUBSTRATE

Micron Technology, Inc., ...

1. A method of manufacturing a plurality of solid state lighting (“SSL”) devices, the method comprising:providing a light emitting structure having a first semiconductor material, a second semiconductor material, and an active region between the first and second semiconductor materials;
forming a metal bonding structure on the light emitting structure; and
bonding a preformed metal substrate to the metal bonding structure, wherein the light emitting structure extends continuously over a surface of the preformed metal substrate.

US Pat. No. 10,249,805

LIGHT EMITTING DIODE PACKAGE HAVING FRAME WITH BOTTOM SURFACE HAVING TWO SURFACES DIFFERENT IN HEIGHT

LG INNOTEK CO., LTD., Se...

1. A light emitting diode package, comprising:a substrate;
a light emitting diode on the substrate;
an electrode electrically connected to the light emitting diode;
a frame surrounding the light emitting diode and configured to reflect light emitted from the light emitting diode; and
at least one hole passing through the substrate and configured to connect both upper and bottom surfaces of the substrate,
wherein a top surface of the frame is positioned higher than a top surface of the light emitting diode,
wherein a portion of the frame has an inclined inner surface,
wherein the frame includes at least one protruding portion protruding from an imaginary surface where the light emitting diode is disposed,
wherein a bottom surface of the at least one protruding portion contacts the substrate,
wherein the at least one protruding portion is located at a portion outside of the light emitting diode, and
wherein the at least one hole is vertically overlapped with the light emitting diode.

US Pat. No. 10,249,804

SEMICONDUCTOR DEVICE, BASE, AND METHOD FOR MANUFACTURING SAME

NICHIA CORPORATION, Anan...

1. A semiconductor device comprising:a base comprising:
a base member,
a reflective film located above the base member, the reflective film containing silver as a major component and containing particles formed of at least one material selected from the group consisting of an oxide, a nitride, and a carbide, and
a distributed Bragg reflector film, a portion of which contacts an upper surface of the reflective film; and
a semiconductor element disposed on the base.

US Pat. No. 10,249,803

LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING LIGHT-EMITTING DEVICE

Industrial Technology Res...

1. A light-emitting device comprising:a transparent substrate having a first surface and a second surface opposite to the first surface and having a first through hole penetrating the first surface and the second surface;
a light-emitting structure disposed on the first surface of the transparent substrate, and the light-emitting structure having at least a second through hole corresponding to the first through hole, wherein the light-emitting structure comprises a cathode layer, an anode layer, and a light-emitting layer disposed between the cathode layer and the anode layer;
a sealing layer disposed on the transparent substrate and covering the light-emitting structure, and the sealing layer having a third through hole corresponding to the first through hole;
a carrier board attached to the transparent substrate, and the sealing layer disposed between the carrier board and the transparent substrate, wherein the carrier board has a fourth through hole corresponding to the first through hole, wherein the inner wall of the first, third and fourth through holes is continuous having a same cross section view from the top; and
a positive electrode and a negative electrode electrically connected to the anode layer and the cathode layer respectively, and at least one of the positive electrode and the negative electrode disposed on the second surface of the transparent substrate.

US Pat. No. 10,249,802

LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

15. A light emitting device comprising:a light emitting element having:
a first face,
a second face opposing the first face,
a plurality of lateral faces extending between the first face and the second face, the plurality of lateral faces including a first lateral face and a second lateral face adjacent to the first lateral face, and
a plurality of corners, each located where the second face meets two respective ones of the plurality of lateral faces, the plurality of corners including a first corner located where the second face meets the first lateral face and the second lateral face,
wherein the light emitting element comprises a pair of electrodes at a second face side of the light emitting element;
a light transmissive member covering a portion of the first lateral face and a portion of an edge where the first lateral face meets the second face, such that the first corner and a portion of an edge where the first lateral face meets the second lateral face are exposed from the light transmissive member; and
a covering member covering the first corner of the light emitting element, the portion of the edge where the first lateral face meets the second lateral face, and an exterior of the light transmissive member, such that the pair of electrodes are exposed from the covering member;
wherein a thermal expansion coefficient of the covering member is lower than a thermal expansion coefficient of the light transmissive member.

US Pat. No. 10,249,801

LIGHT EMITTING DIODE PACKAGE AND MANUFACTURING METHOD THEREOF

Seoul Semiconductor Co., ...

1. A light-emitting diode package, comprising:a light-emitting diode chip disposed in a housing;
a first phosphor configured to emit green light having a full width at half maximum (FWHM) less than or equal to about 35 nm; and
a second phosphor configured to emit red light,
wherein:
white light is configured to be formed by a synthesis of light emitted from the light emitting diode chip, the first phosphor, and the second phosphor, and
the second phosphor has a chemical formula of A2MF6:Mn4+, A is one of Li, Na, K, Rb,Ce, and NH4, and M is one of Si, Ti, Nb, and Ta.

US Pat. No. 10,249,800

STACKED TRANSPARENT PIXEL STRUCTURES FOR ELECTRONIC DISPLAYS

Lockheed Martin Corporati...

1. A system comprising:a substrate;
a plurality of hexagon-shaped pixels coupled to the substrate, each hexagon-shaped pixel comprising:
a first subpixel formed on the substrate;
a second subpixel stacked on top of the first subpixel; and
a third subpixel stacked on top of the second subpixel; and
a plurality of connector columns that electrically couple the first, second, and third subpixels to the substrate;
wherein:
each of the first, second, and third subpixels comprises an emissive layer located between a transparent cathode layer and a transparent anode layer; and
each transparent cathode layer and transparent anode layer of each subpixel is electrically coupled to the substrate through a respective one of the plurality of connector columns.

US Pat. No. 10,249,799

METHOD FOR PRODUCING LIGHT-EMITTING DEVICE

TOYODA GOSEI CO., LTD., ...

1. A method for producing a Group III nitride semiconductor light-emitting device having a reflective electrode on a p-type layer, the method comprising:forming a light transmitting film made of a transparent material having a refractive index different from a refractive index of the p-type layer on a region for forming a reflective electrode layer on the p-type layer;
forming a resist layer with an opening on the p-type layer and the light transmitting film, and exposing the surface of the light transmitting film in the bottom of the opening;
removing the center of the light transmitting film by wet etching, and leaving the ends of the light transmitting film to form a ring-shaped light transmitting film;
forming a reflective film containing Ag or Ag alloy on the p-type layer and the resist layer;
forming the reflective electrode by removing the resist layer along with the reflective film on the resist layer to leave the reflective film on the p-type layer; and
forming a cover metal layer on the reflective electrode and the ring-shaped light transmitting film,
wherein the ring-shaped light transmitting film is a ring-shaped transparent electrode.

US Pat. No. 10,249,798

LIGHT EMITTING DEVICE

Seoul Viosys Co., Ltd., ...

1. A light emitting device comprising:a light emitting structure including a first conductive type semiconductor layer, a second conductive type semiconductor layer disposed on the first conductive type semiconductor layer, and an active layer disposed between the first conductive type semiconductor layer and the second conductive type semiconductor layer;
a first electrode electrically connected to the first conductive type semiconductor layer;
a second electrode disposed on and electrically connected to the second conductive type semiconductor layer;
a support structure comprising a first bulk electrode disposed on and electrically connected to the first electrode, and a second bulk electrode disposed on and electrically connected to the second electrode, and wherein the first bulk electrode and the second bulk electrode are separated from each other with an insulation support layer disposed between the first bulk electrode and the second bulk electrode; and
a substrate disposed adjacent to the support structure,
wherein each of the first and second bulk electrodes comprises an upper region and a lower region, with the upper regions of the first and second bulk electrodes being separated from each other by a first distance,
wherein the substrate includes a first interconnection portion and a second interconnection portion electrically connected to the first bulk electrode and the second bulk electrode, respectively, and separated from each other by a second distance greater than the first distance,
wherein the first bulk electrode comprises a first plane facing the second bulk electrode and a second plane disposed opposite the first plane,
wherein the second bulk electrode comprises a third plane facing the first bulk electrode and a fourth plane disposed opposite the third plane,
wherein the first bulk electrode comprises a first depression inset from a lower most edge of the first plane and defining a lower most edge of the first bulk electrode,
wherein the second bulk electrode comprises a second depression inset from a lower most edge of the third plane and defining a lower most edge of the second bulk electrode, and
wherein the insulation support layer is disposed between the lower most edge of the first bulk electrode and the lower most edge of the second bulk electrode such that the insulation support layer extends along the entirety of the lower most edge of the first bulk electrode and the entirety of the lower most edge of the second bulk electrode.

US Pat. No. 10,249,797

HIGH EFFICIENCY LIGHT EMITTING DIODE AND METHOD OF FABRICATING THE SAME

Seoul Viosys Co., Ltd., ...

1. A light emitting diode (LED), comprising:a substrate;
a semiconductor stack disposed on the substrate, the semiconductor stack comprising:
a p-type semiconductor layer;
an active layer; and
an n-type semiconductor layer, the n-type comprising a roughened surface and a protrusion region having a flat surface facing away from the substrate in a vertical direction;
a first metal layer interposed between the substrate and the semiconductor stack, the first metal layer ohmic-contacted with the semiconductor stack;
a first electrode pad disposed on the semiconductor stack;
an electrode extension extending from the first electrode pad, the electrode extension comprising a contact region that directly contacts the n-type semiconductor layer;
the electrode extension disposed on the flat surface of the n-type semiconductor layer wherein the flat surface is surrounded by the roughened surface;
a width of electrode extension is narrower than a width of the flat surface;
a first insulating layer interposed between the substrate and the semiconductor stack, the first insulating layer covering a first region of the p-type semiconductor layer under the contact region of the electrode extension; and
a second insulating layer interposed between the first electrode pad and the semiconductor stack in a direction perpendicular to the top surface of the substrate, such that the second insulating layer prevents the first electrode pad from directly contacting the semiconductor stack and overlaps at least a part of the roughened surface of the n-type semiconductor layer in the vertical direction,
wherein the first insulating layer comprises at least one groove exposing the semiconductor stack, wherein the first metal layer is interposed between the first insulating layer and the substrate, and is ohmic-contacted with the semiconductor stack by filling the at least one groove,
wherein the at least one groove does not overlap with the electrode extension,
wherein the second insulating layer comprises a first distal end extending away from the semiconductor stack and directly contacting the first insulating layer and is disposed directly on the roughened surface of peripheral of the n-type semiconductor layer in the vertical direction and a side of the semiconductor stack, and
wherein the second insulating layer comprising at least one opening exposing the n-type semiconductor layer overlapping the contact region of the electrode extension, through which the contact region of the electrode extension is directly contacts the n-type semiconductor layer.

US Pat. No. 10,249,796

LIGHT EMITTING DIODE AND METHOD OF MANUFACTURING THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. A light emitting diode, comprising:a base substrate; and
a first semiconductor layer on the base substrate;
a quantum well active layer on a side of the first semiconductor layer distal to the base substrate;
a second semiconductor layer on a side of the quantum well active layer distal to the first semiconductor layer;
a first electrode connected to the first semiconductor layer;
a second electrode connected to the second semiconductor layer; and
a transparent protective layer on a side of the second semiconductor layer distal to the base substrate;
wherein at least the second semiconductor layer is an uneven layer comprising a plurality of ridges adapted to concentrate light emitting from the light emitting layer;
the transparent protective layer is on a side of each of the plurality of ridges distal to the base substrate; and
the first semiconductor layer and the second semiconductor layer are two different layers selected from an N-type doped layer and a P-type doped layer;
wherein the light emitting diode comprises a notch extending through a portion of the second semiconductor layer and a portion of the quantum well active layer to expose a portion of a top surface of the first semiconductor layer;
the notch is adjacent to peripheries of the second semiconductor layer and the quantum well active layer; and
the first electrode extends through the notch to be in direct contact with the portion of the top surface of the first semiconductor layer.

US Pat. No. 10,249,795

LED CHIP WITH INTEGRATED ELECTROMECHANICAL SWITCH

Koninklijke Philips N.V.,...

2. An LED chip, comprising:a semiconductor substrate;
first and second external terminals;
an LED structure connected between the first and second external terminals, the LED structure comprising a first semiconductor layer and a second semiconductor layer over the first semiconductor layer, each layer having a top surface and a bottom surface;
a suspended beam electrostatic switch connected in series with the LED structure between the first and second external terminals, or in parallel with the LED structure;
a third external terminal;
a control electrode connected to the third external terminal for controlling the suspended beam electrostatic switch,
the first semiconductor layer comprising two electrically isolated sub-portions isolated by a dividing channel in the first semiconductor layer and physically connected at their bottom surfaces by the semiconductor substrate,
the second semiconductor layer partially covering the top surface of the first semiconductor layer,
an internal terminal being connected to an anode or cathode of the LED structure and disposed on the top surface of one sub-portion of the first semiconductor layer, and
the second external terminal being disposed on the top surface of the other sub-portion of the first semiconductor layer, and the control electrode being disposed on a surface within the dividing channel,
wherein the suspended beam electrostatic switch comprises a suspended clamp electrode suspended above the dividing channel, being physically connected to, and electrically isolated from, a floating bridge electrode, the bridge electrode having a first end suspended above the internal terminal and a second end suspended above the second external terminal, and both electrodes hinge from a secondary support structure positioned adjacent to the lower semiconductor layer, spanning across the dividing channel.

US Pat. No. 10,249,794

DIODE WITH AN IMPROVED ELECTRIC CURRENT INJECTION

1. A diode, comprising:a first semiconductor region having a first conductivity type;
a first electrode configured to bias the first semiconductor region, wherein the first electrode comprises, in a top view, a plurality of conductive elements, including:
a polygonal ring having a center, a plurality of vertices and a plurality of sides;
wherein each vertex of the plurality of vertices comprises:
a first rectilinear bar extending between the vertex and the center of the polygonal ring, substantially along a direction running from the vertex to the center of the polygonal ring;
wherein the first rectilinear bar comprises a plurality of second rectilinear bars extending from the first rectilinear bar substantially parallel to the plurality of sides of the polygonal ring; and
wherein the vertex forms an origin of the first rectilinear bar;
a second semiconductor region formed in a vertical stack with and having a second conductivity type different from the first conductivity type;
wherein the first electrode is arranged in a trench extending from a surface of the second semiconductor region opposite to the first semiconductor region; and
wherein the dimensions of the first and second rectilinear bars of each of the plurality of vertices of the polygonal ring are such that a volume of the second semiconductor region located, in top view, within the polygonal ring, is continuous.

US Pat. No. 10,249,793

TRANSPARENT ELECTRON BLOCKING HOLE TRANSPORTING LAYER

Palo Alto Research Center...

1. A light emitting diode, comprising:an active region configured to emit light;
a composite electrical contact layer comprising:
an array of padlets with gaps between the padlets, the padlets comprising:
a first sub-layer comprising a III-nitride material; and
a second sub-layer comprising a material different from the first sub-layer, wherein the material of the second sub-layer comprises a conducting oxide; and
a reflective sub-layer disposed in the gaps and over the padlets, the reflective sub-layer configured to reflect the light emitted by the active region; and
a transparent electron blocking hole transporting layer (TEBHTL) arranged between the composite electrical contact layer and the active region and having a thickness that extends at least a majority of a distance between the active region and the electrical contact layer, the TEBHTL having a band-gap greater than a band-gap of light emitting portions of the active region, the band-gap of the TEBHTL decreasing as a function of distance from the active region to the composite electrical contact layer over a majority of the thickness of the TEBHTL.

US Pat. No. 10,249,792

PROTECTIVE CAPPING LAYER FOR SPALLED GALLIUM NITRIDE

INTERNATIONAL BUSINESS MA...

1. A method of producing a semiconductor device comprising:forming a stack including a semiconductor material comprising:
a Group III nitride semiconductor material formed on a growth substrate,
a protective layer formed over the Group III nitride semiconductor material, and
a handle layer and a stressor layer formed over the protective layer; and
spalling the stack to separate the growth substrate from the stack.

US Pat. No. 10,249,791

HIGH-BRIGHTNESS LIGHT-EMITTING DIODE WITH SURFACE MICROSTRUCTURES

XIAMEN SANAN OPTOELECTRON...


(3) dipping the epitaxial wafer processed by Step (1) in the roughening solution prepared by Step (2) for 1-8 min;
wherein for the resulting LED:
the light-emitting surface has a surface microstructure; and
a ratio of total roughened surface area of the light-emitting surface to a vertically-projected area is not less 1.5.

US Pat. No. 10,249,790

LIGHT EMITTING DIODE AND FABRICATION METHOD THEROF

XIAMEN SANAN OPTOELECTRON...

1. A light emitting diode comprising:a first semiconductor layer;
an active layer; and
a second semiconductor layer,
wherein:
an upper surface of the first semiconductor layer has at least a first growth region and a second growth region;
the active layer is formed in the first growth region but not in the second growth region via selective epitaxial growth;
the second semiconductor layer covers the active layer and the second growth region of the first semiconductor layer via epitaxial growth;
when current is injected in the active layer, part of light is emitted from the active layer, and then emitted out from the second growth region after reflection;
the upper surface of the first semiconductor layer has the first growth region, the second growth region, and a third growth region;
the first and the third growth regions are separated by the second growth region;
the active layer is formed only in the first growth region and the third growth region via epitaxial growth;
the active layer in the third growth region and the active layer in the first growth region form an alternating active layer by having a height difference in the third growth region and the first growth region, thereby reducing secondary absorption during light reflection while maintaining a light emitting area; and
the second semiconductor layer covers the active layer and the second growth region of the first semiconductor layer.

US Pat. No. 10,249,789

LIGHT EMITTING DIODE CHIP AND FABRICATION METHOD

XIAMEN SANAN OPTOELECTRON...

1. A method of fabricating a light-emitting diode (LED) chip, the method comprising:(1) providing a substrate;
(2) fabricating an epitaxial layer over the substrate, wherein the epitaxial layer comprises, from bottom up:
at least a first type of a semiconductor layer;
a light-emitting layer; and a second type of semiconductor layer with a plurality of recess portions and protrusion portions;
(3) forming a light transmission layer over the epitaxial layer between top ends of adjacent protrusion portions and forming holes with the recess portions, wherein a horizontal size of the light transmission layer is larger than a width between two adjacent protrusion portions;
(4) covering a top surface of the light transmission layer and a top surface of the epitaxial layer not masked by the light transmission layer with a current spreading layer with a thin-film structure in a continuous distribution; and
(5) fabricating a first electrode and a second electrode respectively arranged over a portion of the current spreading layer and below the substrate.

US Pat. No. 10,249,788

SEMICONDUCTOR SUBSTRATE, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR SUBSTRATE

ENKRIS SEMICONDUCTOR, INC...

1. A semiconductor substrate, comprising a first semiconductor layer and a second semiconductor layer located on the first semiconductor layer; whereinthe first semiconductor layer and the second semiconductor layer have different cleavage planes in a vertical direction; or
a semiconductor layer obtained by symmetrically rotating the first semiconductor layer according to a lattice structure of the first semiconductor layer has a different cleavage plane in the vertical direction as that of the second semiconductor layer; or
a semiconductor layer obtained by symmetrically rotating the second semiconductor layer according to a lattice structure of the second semiconductor layer has a different cleavage plane in the vertical direction as that of the first semiconductor layer; or
the semiconductor layer obtained by symmetrically rotating the first semiconductor layer according to the lattice structure of the first semiconductor layer and the semiconductor layer obtained by symmetrically rotating the second semiconductor layer according to the lattice structure of the second semiconductor layer have different cleavage planes in the vertical direction;
wherein the first semiconductor layer and the second semiconductor layer have different lattice structures, and non-coincident crystallographic directions in a horizontal direction, the first semiconductor layer and the second semiconductor layer are laminated sequentially and alternately to form a laminated structure having three or more layers, and the laminated structure comprises a dielectric layer between the first semiconductor layer and the second semiconductor layer and a third semiconductor layer having a same lattice structure with the first semiconductor layer, wherein the third semiconductor layer and the first semiconductor layer have same cleavage planes in the vertical direction and the second semiconductor layer is located between the first semiconductor layer and the third semiconductor layer.

US Pat. No. 10,249,787

COMPONENT HAVING A MULTIPLE QUANTUM WELL STRUCTURE

OSRAM OPTO SEMICONDUCTORS...

1. A component having a semiconductor layer sequence comprising a p-conductive semiconductor layer, an n-conductive semiconductor layer and an active zone arranged between the p-conductive semiconductor layer and the n-conductive semiconductor layer, whereinthe active zone comprises a multiple quantum well structure, which, from the p-conductive semiconductor layer towards the n-conductive semiconductor layer, comprises a plurality of p-side barrier layers with intermediate quantum well layers and a plurality of n-side barrier layers with intermediate quantum layers,
in the semiconductor layer sequence on the side of the p-conductive semiconductor layer, recesses are formed which have sidewalls, wherein the quantum well layers and/or the plurality of n- and p-side barrier layers extend at least in places conformally with the sidewalls of the recesses,
the plurality of the n- and p-side barrier layers have layer thicknesses that increase monotonically from the p-conductive semiconductor layer towards the n-conductive semiconductor layer, such that the active zone has a gradient with increasing layer thickness of the barrier layers towards the n-conductive semiconductor layer, and
the n-side barrier layers have a greater average layer thickness than the p-side barrier layers.

US Pat. No. 10,249,786

THIN FILM AND SUBSTRATE-REMOVED GROUP III-NITRIDE BASED DEVICES AND METHOD

PALO ALTO RESEARCH CENTER...

1. A method of thinning a bulk aluminum nitride substrate, comprising:providing a bulk aluminum nitride (AlN) substrate with at least one epitaxially grown group-III-nitride layer on a first side of the substrate;
applying a slurry having a high pH to a second side of the substrate opposite the first side;
chemical mechanically polishing the second side of the substrate using the slurry to remove at least a portion of the substrate, resulting in a thinned layer with a thickness less than 50 microns; and
bonding the epitaxial layer to a non-native substrate.

US Pat. No. 10,249,785

REDUCING DARK CURRENT IN GERMANIUM PHOTODIODES BY ELECTRICAL OVER-STRESS

International Business Ma...

1. A method for reducing dark current in a photodiode, comprising:heating a photodiode above room temperature;
measuring the dark current generated by the photodiode; and
applying a reverse bias voltage to the heated photodiode to reduce a dark current generated by the photodiode, increasing the reverse bias voltage until the measured dark current stabilizes to maximize a stable dark current reduction after the photodiode returns to room temperature.

US Pat. No. 10,249,784

OPTICAL SENSOR CAPABLE OF BEING APPLIED TO A TILT SENSOR

HAMAMATSU PHOTONICS K.K.,...

1. An optical sensor comprising:a light emitting element;
a lower substrate on which the light emitting element is provided;
an upper substrate provided so that the light emitting element is positioned between the upper substrate and the lower substrate; and
an optical block provided on the upper substrate,
wherein the upper substrate includes a position detection type light detecting element, and
wherein the optical block is configured to reflect light emitted from the light emitting element toward a measurement target, and light reflected by the measurement target is incident onto the position detection type light detecting element,
wherein the upper substrate includes
a semiconductor substrate main body of a first conductivity type having an impurity concentration of 1×1018 /cm3 or greater;
a first semiconductor region of the first conductivity type formed on a front surface of the semiconductor substrate main body and having an impurity concentration of less than 1×1018 /cm3; and
a single or a plurality of second semiconductor regions of a second conductivity type formed in the first semiconductor region, and
wherein the position detection type light detecting element includes the first semiconductor region and the second semiconductor region.

US Pat. No. 10,249,783

HIGH VOLTAGE PHOTOVOLTAICS INTEGRATED WITH LIGHT EMITTING DIODE CONTAINING ZINC OXIDE CONTAINING LAYER

International Business Ma...

1. A method of forming an electrical device is comprising:growing an LED junction on a supporting substrate;
forming an zinc oxide interface layer on the LED junction;
forming a photovoltaic device junction on the zinc oxide interface layer by molecular beam epitaxial growth, wherein the zinc oxide interface layer entirely physically separates the LED junction from the photovoltaic device junction, the zinc oxide interface layer extending an entire width of the photovoltaic device junction; and
forming contacts to the LED junction and the photovoltaic device junction, wherein the semiconductor material layers in the photovoltaic device junction that is at a light receiving end of the electrical device have a wider band gap than the LED junction that is not at the light receiving end of the electrical device.

US Pat. No. 10,249,782

HIGH VOLTAGE PHOTOVOLTAICS INTEGRATED WITH LIGHT EMITTING DIODE CONTAINING ZINC OXIDE CONTAINING LAYER

International Business Ma...

1. An electrical device comprising:a material stack present on a supporting substrate;
an LED at a first end of the material stack having a first set of bandgap materials;
a photovoltaic device at a second end of the material stack having a second set of bandgap materials, the second end of the material stack being a light receiving end, wherein a width of the bandgap material for the second set of bandgap material is greater than a width of a bandgap material for the first set of bandgap materials; and
a zinc oxide interface layer between the LED and the photovoltaic device, wherein the zinc oxide interface layer is a layer within the material stack that entirely physically separates the LED from the photovoltaic device, the zinc oxide interface layer extending an entire width of the photovoltaic device.

US Pat. No. 10,249,781

APPARATUS FOR COUNTING SINGLE PHOTONS AND METHOD THEREOF

1. An apparatus for counting single photons, comprising:an edge combiner configured to detect an edge of each of applied clocks using a plurality of Phase-Locked Loops (PLL) to generate a combined signal;
a sampling unit configured to sample all events occurring in each SPAD of a single photon detection diode (SPAD) array using an OR tree and an XOR tree; and
a calculation unit configured to count the sampled events based on the combined signal to count single photons.

US Pat. No. 10,249,780

HIGH QUALITY ALSB FOR RADIATION DETECTION

STC.UNM, Albuquerque, NM...

1. A radiation detector, comprising:a substrate comprising Si; anda thin film disposed over the substrate, wherein the thin film comprises UHV-MBE grown AlSb and a background carrier concentration of less than 1015 cm?3.

US Pat. No. 10,249,779

SOLAR COLLECTOR

Violeta Doci, Hamburg (D...

1. A light collector (10) having an optical unit (20) and an energy conversion unit, whereby the energy conversion unit comprises a number of conversion cells (12, 14, 16) that are located along a first main axis, in which the optical unit (20) triggers a light refraction and encloses the energy conversion unit by at least 180 degrees, and the optical unit (20) focuses parallel incident light on a focal area,wherein the focal area has its largest dimension along a second main axis, and the second main axis extends along the first main axis, the optical unit (20) comprises a light-transmitting dish and a fill medium, and the optical unit (20) has a variable index of refraction along the first main axis for the refraction of light, the conversion cells comprising a first conversion cell (12) at a distance from a second conversion cell (14), the first conversion cell (12) being dedicated to a first fill medium and the second conversion cell (14) being dedicated to a fill medium (42) that is different from the first fill medium (40), the dish having an upper part (22) and an underneath part (24), the energy conversion unit being located within the upper part (22) of the dish, the optical unit (20) being supported by a carrier element (26) below the underneath part (24) of the dish, the conversion cells (12,14,16) generating electric current and being connected together and spaced apart by spacers (18), and the spacers (18) being electrically conductive.

US Pat. No. 10,249,778

SOLAR CELL STRUCTURE FOR WIRELESS CHARGING

Industrial Technology Res...

1. A solar cell structure for wireless charging, comprising:a plane substrate; and
at least one thin film solar cell, disposed on a first surface of the plane substrate, wherein the at least one thin film solar cell has a first winding coil structure with two ends and having a central axis, the at least one thin film solar cell comprises:
a back electrode, formed on the plane substrate;
a light absorption layer, formed on the back electrode; and
a transparent electrode layer, formed on the light absorption layer, wherein the back electrode, the light absorption layer, and the transparent electrode layer are the first winding coil structure, and the central axis of the first winding coil structure is perpendicular to the first surface of the plane substrate.

US Pat. No. 10,249,777

INFRARED LIGHT EMITTING DIODE

1. An infrared light-emitting diode, comprising: a first cladding layer; an active layer; and a second cladding layer; wherein: the first cladding layer is InxGa1-xAs, where, In component is 0?X?5%, and a difference of lattice match between layers ?0 is <3,800 ppm, and the light-emitting peak wavelength of the active layer is above 930 nm.

US Pat. No. 10,249,776

HETEROJUNCTION SOLAR CELL AND MANUFACTURING METHOD THEREOF

LG ELECTRONICS INC., Seo...

1. A method for manufacturing a heterojunction solar cell, the method comprising:Forming a tunnel layer on a semiconductor substrate;
forming a metal compound on the tunnel layer;
forming a transparent conductive oxide on the metal compound;
forming an electrode forming material on the transparent conductive oxide;
sintering the electrode forming material using light sintering to form an electrode part,
wherein the transparent conductive oxide is also sintered by the light sintering to form a transparent conductive oxide layer formed of the transparent conductive oxide,
wherein the transparent conductive oxide layer and the electrode part are simultaneously formed by light sintering the transparent conductive oxide when light sintering the electrode forming material, and
wherein a metal compound layer formed of the metal compound, the transparent conductive oxide layer, and the electrode part are simultaneously formed by light sintering the metal compound when light sintering the transparent conductive oxide and the electrode forming material.

US Pat. No. 10,249,775

SOLAR CELL AND METHOD FOR PRODUCING SOLAR CELL

SHIN-ETSU CHEMICAL CO., L...

1. A solar cell comprising:a semiconductor substrate of a first conductivity type having a first conductivity type diffusion layer and a second conductivity type diffusion layer which are formed on a backside of a light-receiving surface of the semiconductor substrate,
a first electrode portion joined to the first conductivity type diffusion layer, and a second electrode portion joined to the second conductivity type diffusion layer,
a first electrode line portion formed on the first electrode portion,
a second electrode line portion formed on the second electrode portion,
a first electrode bus bar portion connected with the first electrode line portion,
a second electrode bus bar portion connected with the second electrode line portion,
an intersection region of the second electrode portion and the first electrode bus bar portion,
an intersection region of the first electrode portion and the second electrode bus bar portion,
a first insulator film which is formed so as to cover a side portion and a top of the second electrode portion at least in the intersection region of the second electrode portion and the first electrode bus bar portion, and
a second insulator film which is formed so as to cover a side portion and a top of the first electrode portion at least in the intersection region of the first electrode portion and the second electrode bus bar portion,
wherein
the second electrode portion is formed continuously in a line shape under the first insulator film,
the first electrode portion is formed continuously in a line shape under the second insulator film,
the first electrode line portion is provided on the first electrode portion except at an intersection region of the first electrode portion and the first electrode bus bar portion,
the second electrode line portion is provided on the second electrode portion except at an intersection region of the second electrode portion and the second electrode bus bar portion, and
the first electrode portion and the first electrode line portion constitute a first finger electrode, and the second electrode portion and the second electrode line portion constitute a second finger electrode.

US Pat. No. 10,249,773

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTOELECTRON...

1. A fabrication method of a light-emitting diode, comprising:1) providing a light-emitting epitaxial laminated layer having an upper surface and an opposing lower surface, including a first semiconductor layer, a second semiconductor layer and an active therebetween;
2) fabricating a dielectric layer having a conductive through-hole array comprising a plurality of uniformly-distributed conductive through-holes over the lower surface of the light-emitting epitaxial laminated layer;
3) fabricating a metal conductive layer over a lower surface of the dielectric layer and filling up the plurality of uniformly-distributed conductive through-holes, forming ohmic-contact with the light-emitting epitaxial laminated layer;
4) providing a conductive substrate and connecting the conductive substrate to the metal conductive layer for supporting the light-emitting epitaxial laminated layer; and
5) forming a first electrode comprising a bonding pad electrode and a finger-shaped electrode over the upper surface of the light-emitting epitaxial laminated layer, wherein, a rotation angle is formed between the finger-shaped electrode and the conductive through-hole array formed in step 2), wherein the rotation angle is selected to prevent a preferred number of conductive through-holes from being shielded by the bonding pad electrode and the finger-shape electrode.

US Pat. No. 10,249,772

SOLAR CELL

Industrial Technology Res...

1. A solar cell, comprising:a first electrode;
a second electrode;
a photoelectric conversion layer, disposed between the first electrode and the second electrode; and
a first electrical modulating stack layer, disposed on the first electrode, wherein the first electrical modulating stack layer includes at least one positively charged layer and at least one negatively charged layer stacked alternately, and the first electrode is disposed between the first electrical modulating stack layer and the photoelectric conversion layer,
wherein the positively charged layer and the negatively charged layer of the first electrical modulating stack layer are separately deposited layers.

US Pat. No. 10,249,770

SOLAR CELL MODULE

LG INNOTEK CO., LTD., Se...

1. A solar cell module comprising:a support substrate;
a back electrode layer on the support substrate;
a light absorbing layer on the back electrode layer;
a front electrode layer on the light absorbing layer; and
a bus bar,
wherein the back electrode layer is configured to be formed with a groove upon which a portion of the bus bar is disposed, the groove being formed by a top surface of the back electrode layer on the support substrate, and first at second lateral surfaces of the back electrode layer, wherein the bus bar is in contact with a top surface and the first lateral surface of the back electrode layer, and the second lateral surface of the back electrode layer is exposed by the groove; and
wherein top surface includes molybdenum diselenide (MoSe2), and the first and second lateral surfaces each includes molybdenum (Mo) and molybdenum diselenide.

US Pat. No. 10,249,769

ON-CHIP TUNEABLE DIFFUSION RESISTOR

Dialog Semiconductor, Inc...

1. An on-chip tuneable diffusion resistor, comprising:a metal or polysilicon layer, deposited on top of an insulating layer;
a diffusion N-well, implanted beneath said insulating layer, in a silicon substrate; and
two implant regions adjacent to said metal or insulating layer, configured to define a first terminal and a second terminal in said diffusion N-well, and configured to be connected independently from said metal or insulating layer of said on-chip tuneable diffusion resistor.

US Pat. No. 10,249,768

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor and a second transistor each over a first insulating
the first transistor comprising:
a first oxide semiconductor film;
a second oxide semiconductor film on and in contact with the first oxide semiconductor film;
a third oxide semiconductor film on and in contact with a top surface of the second oxide semiconductor film and side surfaces of the first oxide semiconductor film and the second oxide semiconductor film;
a first gate insulating film on and in contact with the third oxide semiconductor film; and
a first gate electrode over the first gate insulating film; and
the second transistor comprising:
a fourth oxide semiconductor film;
a second gate insulating film on and in contact with the fourth oxide semiconductor film; and
a second gate electrode over the second gate insulating film,
wherein each of the first oxide semiconductor film, the second oxide semiconductor film, the third oxide semiconductor film, and the fourth oxide semiconductor film comprises indium, gallium, and zinc, and
wherein, in each of the third oxide semiconductor film and the fourth oxide semiconductor film, a proportion of indium atoms is lower than or equal to a proportion of gallium atoms.

US Pat. No. 10,249,767

GA2O3-BASED SEMICONDUCTOR ELEMENT

TAMURA CORPORATION, Toky...

1. A Ga2O3-based semiconductor element, comprising:an undoped ?-Ga2O3 single crystal film disposed on a surface of a ?-Ga2O3 substrate;
a source electrode and a drain electrode disposed on a same side of the undoped ?-Ga2O3 single crystal film;
a gate electrode disposed on the undoped ?-Ga2O3 single crystal film between the source electrode and the drain electrode via a gate insulating film; and
a source region and a drain region formed in the undoped ?-Ga2O3 single crystal film under the source electrode and the drain electrode, respectively, and including a controlled dopant concentration,
wherein the ?-Ga2O3 substrate comprises a semi-insulating ?-Ga2O3 single crystal doped with an element selected from Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, Pb, N, or P,
wherein a channel is formed in a region of the undoped ?-Ga2O3 single crystal film when a voltage of more than a threshold is applied to the gate electrode, and
wherein a current only flow from the source electrode to the drain electrode through the undoped ?-Ga2O3 single crystal film when the voltage is applied to the gate electrode.

US Pat. No. 10,249,766

SEMICONDUCTOR DEVICE INCLUDING A TRANSISTOR, A WIRING AND A BARRIER FILM

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first oxygen barrier film;
an oxide insulating film over the first oxygen barrier film;
a transistor comprising an oxide semiconductor film;
a wiring electrically connected to the transistor; and
a second oxygen barrier film in contact with the wiring and the first oxygen barrier film,
wherein the oxide semiconductor film is over the oxide insulating film,
wherein the oxide semiconductor film comprises a channel formation region,
wherein the second oxygen barrier film penetrates the first oxygen barrier film,
wherein the second oxygen barrier film comprises aluminum oxide, and
wherein the wiring comprises tungsten.

US Pat. No. 10,249,765

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a capacitor comprising;
a first electrode comprising a protruding portion;
a first insulating film over and in direct contact with a top surface of the protruding portion;
a second insulating film covering the first electrode and the first insulating film; and
a second electrode over the second insulating film,
wherein the first electrode comprises a metal material, or an alloy material,
wherein a peripheral portion of the second electrode comprises a region which overlaps with the first electrode with the first insulating film and the second insulating film provided therebetween,
wherein the second insulating film is in direct contact with a side surface of the protruding portion of the first electrode and a top surface of the first electrode, and
wherein the first insulating film comprises a ring shape.

US Pat. No. 10,249,764

SEMICONDUCTOR DEVICE, DISPLAY DEVICE INCLUDING SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE INCLUDING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:forming a gate electrode;
forming a gate insulating film over the gate electrode;
forming an oxide semiconductor film over the gate electrode with the gate insulating film interposed between the gate electrode and the oxide semiconductor film; and
forming a source electrode and a drain electrode over the oxide semiconductor film,
wherein the steps of forming the source electrode and the drain electrode comprise the steps of:
forming a first metal film;
forming a second metal film over the first metal film;
performing a first photolithography process on the second metal film and partly removing the second metal film by first etching;
forming a third metal film over the first metal film and the second metal film to cover the second metal film; and
performing a second photolithography process on the third metal film and partly removing the first metal film and the third metal film by second etching, and
wherein the second etching partly removes the first metal film and the third metal film at an outer side of end portions of the second metal film which is removed by the first etching.

US Pat. No. 10,249,763

ARRAY SUBSTRATE, AND DISPLAY DEVICE, AND FABRICATION METHODS

BOE TECHNOLOGY GROUP CO.,...

1. A semiconductor device, comprising:a first electrode, an insulating layer, and a second electrode, over a substrate;
a conductive layer arranged on the insulating layer at a side away from the substrate;
a semiconductor layer: on the first electrode, on a first sidewall of the insulating layer, on the conductive layer, on a second sidewall of the insulating layer, and on the second electrode, wherein:
the semiconductor layer contacts the first sidewall of the insulating layer, the conductive layer, and the second sidewall of the insulating layer,
the second sidewall is located at an opposite side of the first sidewall, and
the conductive layer is patterned and located between the first sidewall and the second sidewall;
a first gate electrode over a portion of the semiconductor layer that is on the first sidewall of the insulating layer; and
a second gate electrode over a portion of the semiconductor layer that is on the second sidewall of the insulating layer.

US Pat. No. 10,249,762

VERTICALLY ALIGNED NANOWIRE CHANNELS WITH SOURCE/DRAIN INTERCONNECTS FOR NANOSHEET TRANSISTORS

International Business Ma...

1. A method for forming a semiconductor structure, the method comprising:forming a structure comprising at least an alternating stack of semiconductor layers and metal gate material layers formed on a substrate, a metal gate formed on and in contact with a top layer of the alternating stack, a source region and a drain region in contact with the alternating stack, and dielectric layers formed on and in contact with a top surface of the source and drain regions, respectively;
removing a portion of the semiconductor layers and metal gate material layers, wherein the removing forms trenches exposing at least sidewalls of the source and drain regions;
forming a first plurality of interconnects between and in contact with the semiconductor layers and the source region; and
forming a second plurality of interconnects between and in contact with the semiconductor layers and the drain region.

US Pat. No. 10,249,761

THIN-FILM TRANSISTOR SUBSTRATE

JOLED INC., Tokyo (JP)

1. A thin-film transistor substrate, comprising:a substrate;
a thin-film transistor above the substrate; and
a capacitor above the substrate and electrically connected with the thin-film transistor,
wherein the capacitor includes:
a first electrode layer disposed above the substrate and including an electrically conductive material as a main component;
a second electrode layer above and opposed to the first electrode layer and including, as a main component, an oxide semiconductor material to which electrical conductivity is given; and
an insulating layer between the first electrode layer and the second electrode layer,
an extension extending outward from at least a portion of an outer edge of the first electrode layer in plan view id provided to the first electrode layer, and
in plan view, the second electrode layer covers the outer edge of the first electrode layer where no extension is formed.

US Pat. No. 10,249,760

THIN FILM TRANSISTOR AND LIQUID CRYSTAL DISPLAY PANEL

Shenzhen China Star Optoe...

1. A thin film transistor, wherein the thin film transistor comprises:a substrate,
a source electrode pattern and a drain electrode pattern separately disposed on the substrate,
a first doping pattern and a second doping pattern respectively comprising a first portion and a second portion, wherein the first portions are respectively covered on the source electrode pattern and the drain electrode pattern, and
an active pattern contacting electrically with the first doping pattern and the second doping pattern respectively,
wherein the second portions of the first doping pattern and the second doping pattern are disposed adjacent to a sidewall of the source electrode pattern and a sidewall of the drain electrode pattern, respectively, a first transition pattern is disposed between the source electrode pattern and the first doping pattern, a second transition pattern is disposed between the drain electrode pattern and the second doping pattern, the first transition pattern and the second transition pattern respectively cover the sidewall of the source electrode pattern and the sidewall of the drain electrode pattern, and the sidewalls of the first doping pattern and the second doping pattern are adjacent to the active pattern, so as to insulate the active pattern from the sidewall of the source electrode pattern and the sidewall of the drain electrode.

US Pat. No. 10,249,759

CONNECTION ARRANGEMENTS FOR INTEGRATED LATERAL DIFFUSION FIELD EFFECT TRANSISTORS

Silanna Asia Pte Ltd, Si...

1. A semiconductor device, comprising:a semiconductor substrate supporting an overlying active layer;
a first lateral diffusion field effect transistor (LDFET) in the active layer and comprising a source, a drain, and a gate;
a second LDFET in the active layer and comprising a source, a drain, and a gate;
a common node electrically and physically connected to the source of the first LDFET and the drain of the second LDFET;
a first front-side contact over the active layer and electrically and physically connected to a first one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a second front-side contact over the active layer and electrically and physically connected to a second one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a substrate contact electrically and physically connected to the semiconductor substrate and a third one of: the drain of the first LDFET, the source of the second LDFET, and the common node;
a buried dielectric layer between the semiconductor substrate and the active layer, wherein the substrate contact extends through the buried dielectric layer; and
a dielectric isolation barrier disposed between the first LDFET and the second LDFET and that extends through the active layer to the buried dielectric layer;
wherein each of the first front-side contact, the second front-side contact, and the substrate contact is electrically and physically connected to a different respective one of the drain of the first LDFET, the source of the second LDFET, and the common node.

US Pat. No. 10,249,758

FINFET WITH SIGMA RECESSED SOURCE/DRAIN AND UN-DOPED BUFFER LAYER EPITAXY FOR UNIFORM JUNCTION FORMATION

International Business Ma...

1. A method of forming a semiconductor structure comprising:forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, wherein the gate structure comprises a gate stack straddling a channel portion of the semiconductor fin and a gate spacer present on sidewalls of the gate stack;
forming a sigma cavity within the semiconductor fin on each side of the gate structure, wherein the sigma cavity comprises a first horizontal tip region extending beneath the gate spacer and a bottom region extending towards the semiconductor substrate portion;
forming a second sigma cavity intersecting the bottom portion of the sigma cavity, wherein the second sigma cavity comprises a second horizontal tip region located beneath the first horizontal tip region, wherein the second horizontal tip region extends beneath the gate spacer and is adjacent to the channel region of the semiconductor fin;
epitaxially growing a semiconductor buffer region from faceted surfaces of the sigma cavity and the second sigma cavity, wherein the semiconductor buffer region completely fills the first and second horizontal tip regions and the bottom region of the sigma cavity, wherein an unfilled portion of the sigma cavity has substantially vertical sidewalls; and
epitaxially growing a doped semiconductor region from the semiconductor buffer region, wherein the doped semiconductor region completely fills the unfilled portion of the sigma cavity and has substantially vertical sidewalls.

US Pat. No. 10,249,757

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a pattern forming region and a peripheral region;
a first strain relaxed buffer layer on the pattern forming region of the substrate;
a second strain relaxed buffer layer on the peripheral region of the substrate;
a first insulating film pattern on the substrate, an upper portion of the first insulating film pattern being disposed within the first strain relaxed buffer layer, and an upper surface of the first insulating film pattern being covered with the first strain relaxed buffer layer, and a lower portion of the first insulating film patter being disposed within the substrate;
a second insulating film pattern on the substrate, at least a portion of the second insulating film pattern being disposed within the second strain relaxed buffer layer, and an upper surface of the second insulating film pattern being covered with the second strain relaxed buffer layer; and
a gate electrode on the first strain relaxed buffer layer.

US Pat. No. 10,249,756

SEMICONDUCTOR DEVICE INCLUDING MEMORY AND LOGIC CIRCUIT HAVING FETS WITH FERROELECTRIC LAYER AND MANUFACTURING METHODS THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:a memory circuit including:
a word line;
a bit line;
a common line; and
a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line; and
a logic circuit including:
a logic transistor having a gate, a drain and a source, wherein:
the gate of the memory transistor has a gate electrode layer formed on a gate dielectric layer, the gate dielectric layer including a first insulating layer and a first ferroelectric (FE) material layer, and
the gate of the logic transistor has a gate electrode layer formed on a gate dielectric layer, the gate dielectric layer including a second insulating layer and a second FE material layer,
wherein a thickness of the first insulating layer is different from a thickness of the second insulating layer.

US Pat. No. 10,249,755

TRANSISTOR WITH ASYMMETRIC SOURCE/DRAIN OVERLAP

International Business Ma...

1. A method of fabricating an asymmetric field-effect transistor device, comprising:obtaining a structure including a semiconductor substrate, sacrificial mandrels on the semiconductor substrate, dummy gates on sidewalls of the sacrificial mandrels, and a vertical trench between a pair of the dummy gates;
filling the vertical trench with a filling material having a different composition from the mandrels and dummy gates;
selectively removing the mandrels to expose first portions of the semiconductor substrate;
subjecting the first portions of the semiconductor substrate to a first etching process, thereby forming first recesses within the first portions of the semiconductor substrate;
removing the filling material from the vertical trench to expose a second portion of the semiconductor substrate;
subjecting the first and second portions of the semiconductor substrate to a second etching process, thereby enlarging the first recesses within the first portions of the semiconductor substrate and forming a second recess in the second portion of the semiconductor substrate, the first recesses extending further vertically within the semiconductor substrate than the second recess following the second etching process;
epitaxially growing embedded source regions within the first recesses in the first portions of the semiconductor substrate;
epitaxially growing an embedded drain region within the second recess on the second portion of the semiconductor substrate;
removing the dummy gates, and
replacing the dummy gates with a gate dielectric layer and metal gate material on the gate dielectric layer.

US Pat. No. 10,249,754

PRECISE JUNCTION PLACEMENT IN VERTICAL SEMICONDUCTOR DEVICES USING ETCH STOP LAYERS

International Business Ma...

1. A semiconductor device comprising:a first source region and a first drain region made of a first semiconductor material, wherein the first source region has an upper portion and a lower portion;
an etch stop layer made of a second semiconductor material different from the first semiconductor material between the upper portion and the lower portion of the first source region; and
a channel semiconductor material on an upper surface of the upper portion of the first source region, wherein the first drain region is on the channel semiconductor material.

US Pat. No. 10,249,753

GATE CUT ON A VERTICAL FIELD EFFECT TRANSISTOR WITH A DEFINED-WIDTH INORGANIC MASK

INTERNATIONAL BUSINESS MA...

1. A vertical field effect transistor (VFET) comprising:a first spacer disposed on a silicon substrate;
fins from the substrate through the spacer;
an oxide layer disposed on the fins;
a hard mask layer disposed on the oxide layer; and
a second spacer with a defined width disposed around the fins, oxide layer and hard mask layer, forming a gate around the fins.

US Pat. No. 10,249,752

SEMICONDUCTOR DEVICES HAVING SEGMENTED RING STRUCTURES

Semiconductor Components ...

1. A semiconducting device comprising:a semiconductor substrate of a first conductivity type;
a first layer of the first conductivity type overlying the semiconductor substrate;
an active region; and
one or more ring structures surrounding the active region, the ring structures each comprising:
two or more first segments each comprising a first super-junction trench, wherein the first super-junction trench comprises:
a first semiconducting region having a second conductivity type;
a second semiconducting region adjacent to the first semiconducting region, wherein the second semiconducting region has a third conductivity type that is different than the second conductivity type;
a first buffer region adjacent to the second semiconducting region;
a third semiconducting region adjacent to the first buffer region, wherein the third semiconducting region has the third conductivity type; and
a fourth semiconducting region adjacent to the third semiconducting region, wherein the fourth semiconducting region has the second conductivity type; and
two or more second segments each comprising a fifth semiconducting region having the first conductivity type,
wherein the first segments and the second segments have different structures and are alternatively arranged to form the ring structure.

US Pat. No. 10,249,751

HIGH-SPEED DIODE WITH CRYSTAL DEFECTS AND METHOD OF MANUFACTURING

ROHM CO., LTD., Kyoto (J...

1. A high-speed diode comprising:an n-type semiconductor layer; and
a p-type semiconductor layer which is laminated on the n-type semiconductor layer,
wherein a pn junction is formed in a boundary portion between the n-type semiconductor layer and the p-type semiconductor layer,
crystal defects are formed away from the p-type semiconductor layer and such that a frequency of appearance is gradually decreased from an upper surface of the p-type semiconductor layer toward a bottom surface of the n-type semiconductor layer,
the high-speed diode has a profile of a positive hole concentration distribution when having a low current in which a forward current density is equal to or less than 1 A/mm2,
the profile includes an inflection point spaced apart from a surface of the p-type semiconductor layer, and
a positive hole concentration of the profile decreases from the surface of the p-type semiconductor layer towards the inflection point and increases from the inflection point towards the bottom surface of n-type semiconductor layer.

US Pat. No. 10,249,750

SEMICONDUCTOR DEVICE

ELECTRONICS AND TELECOMMU...

1. A semiconductor device, comprising:a first semiconductor layer;
a second semiconductor layer disposed on the first semiconductor layer;
a structure layer disposed on the second semiconductor layer;
a metal film covering a side surface of the first semiconductor layer, a side surface of the second semiconductor layer, and an upper surface of the structure layer; and
a flexible substrate covering the metal film,
wherein a width of the first semiconductor layer is smaller than a width of the second semiconductor layer,
wherein the width of the second semiconductor layer is smaller than a width of the structure layer.

US Pat. No. 10,249,749

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

FUJITSU LIMITED, Kawasak...

1. A semiconductor device comprising:a buffer layer;
a channel layer over the buffer layer;
a carrier supply layer over the channel layer;
a first recess and a second recess that are formed in the channel layer and the carrier supply layer, and that reach the buffer layer;
a first nitride semiconductor layer in the first recess;
a second nitride semiconductor layer in the second recess;
a source electrode over the first nitride semiconductor layer;
a drain electrode over the second nitride semiconductor layer; and
a gate electrode over the carrier supply layer between the first recess and the second recess,
wherein each of the first nitride semiconductor layer and the second nitride semiconductor layer includes
a first region containing donors, and
a second region under the first region,
wherein an interface between the first region and the second region is positioned deeper than two-dimensional electron gas on a surface side of the channel layer, and
wherein energy at a bottom of a conduction band of the second region is higher than energy at a bottom of a conduction band of the first region.

US Pat. No. 10,249,748

NITRIDE SEMICONDUCTOR DEVICE

Panasonic Corporation, O...

1. A nitride semiconductor device, comprising:a substrate of a first conductivity type having a first surface and a second surface on a side of the substrate opposite the first surface;
a first nitride semiconductor layer of the first conductivity type which is disposed on the first surface of the substrate and includes an acceptor impurity;
a second nitride semiconductor layer of a second conductivity type disposed on the first nitride semiconductor layer, the second conductivity type being opposite to the first conductivity type;
a first electrode disposed on the second surface of the substrate;
a second electrode disposed on the first nitride semiconductor layer; and
a gate electrode disposed on the second nitride semiconductor layer.

US Pat. No. 10,249,747

TURN-OFF POWER SEMICONDUCTOR DEVICE WITH IMPROVED CENTERING AND FIXING OF A GATE RING, AND METHOD FOR MANUFACTURING THE SAME

ABB Schweiz AG, Baden (C...

1. Turn-off power semiconductor device comprising:a wafer having a first main side, a second main side parallel to the first main side and extending in a lateral direction, an active region and a termination region on the first main side laterally surrounding the active region;
at least one thyristor cell in the active region between the first main side and the second main side, the at least one thyristor cell comprising in the order from the first main side to the second main side:
(a) a first cathode electrode;
(b) a cathode semiconductor layer of a first conductivity type;
(c) a base semiconductor layer of a second conductivity type different from the first conductivity type;
(d) a drift semiconductor layer of the first conductivity type;
(e) an anode semiconductor layer of the second conductivity type;
(f) a first anode electrode,
wherein the at least one thyristor cell further comprises a gate electrode which is arranged lateral to the cathode semiconductor layer and contacting the base semiconductor layer, and
wherein the at least one gate electrode of the at least one thyristor cell is electrically connected to a ring-shaped contact for contacting the at least one gate electrode of the at least one thyristor cell, wherein the ring-shaped contact is formed on the first main side of the wafer in the termination region and surrounds the active region;
the device further comprising:
a rubber ring arranged on the termination region and surrounding the active region; and
an electrically conductive gate ring for contacting the ring-shaped contact from outside, wherein the gate ring is disposed on and electrically connected to the ring-shaped contact within the rubber ring,
wherein an outer circumferential surface of the gate ring is in contact with the rubber ring to define the inner border of the rubber ring,
wherein an upper surface of the gate ring and an upper surface of the rubber ring form a continuous surface extending in a plane parallel to the first main side of the wafer.

US Pat. No. 10,249,746

BIPOLAR TRANSISTOR WITH SUPERJUNCTION STRUCTURE

Infineon Technologies AG,...

1. A superjunction bipolar transistor, comprising:an active transistor cell area comprising active transistor cells electrically connected to a first load electrode at a front side of a semiconductor body;
a superjunction area overlapping the active transistor cell area, the superjunction area comprising a low-resistive region and a reservoir region outside of the low-resistive region, wherein the low-resistive region comprises a first superjunction structure with a first vertical extension with respect to a first surface at the front side of the semiconductor body, and wherein the reservoir region comprises no superjunction structure such that the reservoir region comprises the semiconductor body that extends from a region located at the first surface to a drain region; and
a collector structure directly electrically connected to a second load electrode at a reverse side opposite to the front side and forming a continuous layer directly adjoining a second surface of the semiconductor body opposite to the first surface, wherein the collector structure forms a pn junction with a drift structure that comprises the first superjunction structure.

US Pat. No. 10,249,745

METHOD FOR MAKING A SEMICONDUCTOR DEVICE INCLUDING A RESONANT TUNNELING DIODE STRUCTURE HAVING A SUPERLATTICE

ATOMERA INCORPORATED, Lo...

1. A method for making a semiconductor device comprising:forming at least one double-barrier resonant tunneling diode (DBRTD) by
forming a first doped semiconductor layer,
forming a first barrier layer on the first doped semiconductor layer and comprising a first superlattice, the first superlattice comprising a plurality of stacked groups of layers, each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions,
forming an intrinsic semiconductor layer on the first barrier layer,
forming a second barrier layer on the intrinsic semiconductor layer, and
forming a second doped semiconductor layer on the second barrier layer.

US Pat. No. 10,249,744

TUNNEL FIELD-EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING TUNNEL FIELD-EFFECT TRANSISTOR

HUAWEI TECHNOLOGIES CO., ...

1. A tunnel field-effect transistor, comprising:a substrate;
an oxide structure, wherein the oxide structure is located on a surface of the substrate;
insulation layers, wherein the insulation layers are located on the surface of the substrate and two sides of the oxide structure;
source regions, wherein the source regions are located on surfaces of the insulation layers and the two sides of the oxide structure, and an end face on an end that is of the source region and that is away from the substrate is lower than an end face on a side that is of the oxide structure and that is away from the substrate;
epitaxial layer, wherein the epitaxial layer is located on the surface of the insulation layer and a surface on a side that is of the source region and that is away from the oxide structure, and an end face on a side that is of the epitaxial layer and that is away from the substrate is flush with an end face on a side that is of the source region and that is away from the substrate;
a gate structure, wherein the gate structure is located on the surface of the insulation layer and a surface on a side that is of the epitaxial layer and that is away from the source region;
channel layers, wherein the channel layers are located on the two sides of the oxide structure and cover the source regions and the epitaxial layer, and an end face on a side that is of the channel layer and that is away from the substrate is flush with the end face on the side that is of the oxide structure and that is away from the substrate; and
a drain region, wherein the drain region covers the oxide structure and the channel layers.

US Pat. No. 10,249,743

SEMICONDUCTOR DEVICE WITH LOW BAND-TO-BAND TUNNELING

International Business Ma...

1. A semiconductor device comprising:a dielectric layer on an insulator layer over a semiconductor substrate;
a source and a drain in the dielectric layer;
a channel between the source and drain, the channel including a first region having a first bandgap adjacent to a second region having a second bandgap, wherein the first bandgap is larger than the second bandgap; and
a gate over the channel;
wherein the first region further comprises:
a first subregion and a second subregion;
wherein the first subregion is adjacent to the source and wherein the second subregion is adjacent to the drain.

US Pat. No. 10,249,742

OFFSTATE PARASITIC LEAKAGE REDUCTION FOR TUNNELING FIELD EFFECT TRANSISTORS

Intel Corporation, Santa...

1. A method comprising:forming a non-planar conducting channel of a device between junction regions on a substrate, the substrate comprising a blocking material beneath the channel, the blocking material comprising a property to inhibit carrier leakage, wherein the blocking material comprises an air gap and after forming the channel, the method comprises removing a portion of the substrate beneath the channel; and
forming a gate stack on the channel, the gate stack comprising a dielectric material and a gate electrode.

US Pat. No. 10,249,741

SYSTEM AND METHOD FOR ION-SELECTIVE, FIELD EFFECT TRANSISTOR ON FLEXIBLE SUBSTRATE

1. A flexible ion-selective field effect transistor comprising:a flexible substrate;
a thin film transistor disposed on the flexible substrate, the thin film transistor including a source, a drain, a gate, and an active channel layer, the gate is isolated from the atmosphere; and
a surface sensing layer in electronic communication with the gate,
wherein the flexible ion-selective field effect transistor has a structure that provides a flexible thin film transistor display, wherein the flexible thin film transistor display is provided when the surface sensing layer is only in electronic communication with the source or the drain, wherein the surface sensing layer serves as a transparent top electrode of the flexible thin film transistor display.

US Pat. No. 10,249,740

GE NANO WIRE TRANSISTOR WITH GAAS AS THE SACRIFICIAL LAYER

Intel Corporation, Santa...

1. An apparatus comprising:a three-dimensional semiconductor body comprising a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body comprising:
a plurality of nanowires comprising a germanium material disposed in respective planes separated in the junction regions by a second material, wherein a lattice constant of the second material is similar to a lattice constant of the germanium material; and
a gate stack disposed on the channel region, the gate stack comprising a gate electrode disposed on a gate dielectric.

US Pat. No. 10,249,739

NANOSHEET MOSFET WITH PARTIAL RELEASE AND SOURCE/DRAIN EPITAXY

International Business Ma...

1. A method of forming a nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure, the method comprising:forming a heteroepitaxial film stack including at least one sacrificial layer and at least one channel layer;
patterning the heteroepitaxial film stack;
forming a dummy gate stack and sidewall spacers;
forming a cladded or embedded epitaxial source/drain region directly contacting sidewalls of each of the at least one sacrificial layer and each of the at least one channel layer such that elastic relaxation of the at least one sacrificial layer causes tensile strain to the at least one channel layer;
removing the dummy gate stack;
partially removing sections of the at least one sacrificial layer such that remaining sections of the at least one sacrificial layer preserve the tensile strain in the at least one channel layer; and
forming a replacement gate stack directly in contact with the remaining sections of the at least one sacrificial layer.

US Pat. No. 10,249,738

NANOSHEET CHANNEL-TO-SOURCE AND DRAIN ISOLATION

INTERNATIONAL BUSINESS MA...

1. A structure used to fabricate a nanosheet semiconductor device, the structure comprising:a substrate;
two or more sets of silicon layers formed above the substrate, wherein each of the two or more sets of silicon layers is parallel to others of the two or more sets of silicon layers in a first direction and each of the two or more sets of silicon layers includes gaps between adjacent ones of the silicon layers of each respective set of silicon layers; and
a dielectric material configured to anchor each of the two or more sets of silicon layers at a first end and a second end of each of the two or more sets of silicon layer along a second direction, which is perpendicular to the first direction, wherein the dielectric material partially fills the gaps between the adjacent ones of the silicon layers of each respective set of silicon layers of the two or more sets of silicon layers and is between adjacent ones of the two or more sets of silicon layers.

US Pat. No. 10,249,737

SILICON GERMANIUM-ON-INSULATOR FORMATION BY THERMAL MIXING

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:forming an amorphous silicon layer portion directly on a topmost surface of an active silicon germanium (SiGe) region of a silicon germanium-on-insulator material;
forming a gate structure on a topmost surface of said amorphous silicon layer portion, wherein said gate structure comprises a gate dielectric portion present directly on the topmost surface of said amorphous silicon layer portion and a gate conductor portion present on said dielectric portion;
forming a gate dielectric spacer on sidewalls of said gate structure and sidewalls of said amorphous silicon layer portion, wherein a bottommost surface of said gate dielectric spacer is in direct contact with said topmost surface of said active SiGe region and is coplanar with a bottommost surface of said amorphous silicon layer portion; and
forming an embedded SiGe channel region in said active SiGe region directly beneath said gate structure utilizing a thermal mixing process in which silicon atoms from said amorphous silicon layer portion intermix with germanium atoms in said SiGe active region to form said embedded SiGe channel region, wherein said thermal mixing process entirely removes the amorphous silicon layer from the semiconductor structure such that a topmost surface of said embedded SiGe channel region is in direct physical contact with a bottommost surface of said gate dielectric portion and said embedded SiGe channel region has a lower germanium content than said active SiGe region.

US Pat. No. 10,249,736

ASPECT RATIO TRAPPING IN CHANNEL LAST PROCESS

International Business Ma...

1. A method of forming the fin structure comprising:forming a replacement gate structure on a channel region of the at least one replacement fin structure, the replacement fin structure extending from a supporting substrate;
forming an encapsulating dielectric on the supporting substrate and the at least one replacement gate structure, wherein the encapsulating dielectric encapsulates the replacement fin structure and a portion of the replacement gate structure is exposed;
etching an exposed portion of the replacement gate structure to provide an opening through the encapsulating dielectric to the replacement fin structure;
etching the replacement fin structure selectively to the encapsulating dielectric to remove an entirety of the replacement fin structure and to remove a portion of underlying supporting substrate and provide a fin opening having a geometry dictated by the encapsulating dielectric that exposes a growth surface of the substrate; and
epitaxially growing functional fin structures of a second semiconductor material on the growth surface of the supporting substrate substantially filling the fin opening.

US Pat. No. 10,249,735

THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a thin film transistor (TFT), comprising steps of:forming a pattern of a gate electrode on a base substrate;
forming a gate insulation layer with an even surface;
forming a pattern of a polysilicon semiconductor layer;
depositing an amorphous silicon highly-doped P+layer;
patterning the amorphous silicon highly-doped P+layer to form a pattern of the amorphous silicon highly-doped P+layer at a source electrode contact region and a drain electrode contact region on the polysilicon semiconductor layer; and
forming patterns of a source electrode and a drain electrode, wherein the pattern of the amorphous silicon highly-doped P+layer contacts directly the patterns of the source electrode and the drain electrode, and the pattern of the amorphous silicon highly-doped P+layer contacts directly the polysilicon semiconductor layer;
wherein the step of forming the pattern of the polysilicon semiconductor layer comprises:
depositing an amorphous silicon layer;
patterning the amorphous silicon layer to form a pattern of the amorphous silicon layer; and
crystallizing the pattern of the amorphous silicon layer to form the pattern of the polysilicon semiconductor layer; and
wherein the forming the gate insulation layer with the even surface comprises:
depositing a gate insulation layer film on the base substrate and the pattern of the gate electrode; and
removing a protrusion on the gate insulation layer film to form the gate insulation layer with the even surface, wherein the distance between an upper surface of the protrusion of the gate insulation layer film and an upper surface of the base substrate is greater than the sum of the thickness of the gate insulation layer with an even surface and the thickness of the gate electrode.

US Pat. No. 10,249,734

POLY-SILICON THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method for manufacturing a poly-silicon thin film transistor comprising: forming an active layer on a base substrate, and a gate insulation layer and a gate electrode above the active layer, the active layer including a first poly-silicon area, lightly doped areas located at both sides of the first poly-silicon area, and heavily doped areas located at a side of the lightly doped areas away from the first poly-silicon area,wherein forming of the lightly doped areas of the active layer includes:
forming a poly-silicon layer on the base substrate, the poly-silicon layer including the first poly-silicon area, second poly-silicon areas located at both sides of the first poly-silicon area, and third poly-silicon areas located at a side of the second poly-silicon areas away from the first poly-silicon area;
with a film layer covering the first poly-silicon area and the second poly-silicon areas as a mask, the third poly-silicon areas are doped to form the heavily doped areas;
forming a barrier layer between the gate electrode and the gate insulation layer by a dry etching method so that the barrier layer corresponds to the first poly-silicon area; and
after doping the third poly-silicon areas with the film layer covering the first poly-silicon area and the second poly-silicon areas as the mask, doping the second poly-silicon areas with the barrier layer covering the first poly-silicon area as a mask, to form the lightly doped areas,
wherein the barrier layer is a layer which serves as the mask for doping and which has an orthographic projection on the poly-silicon layer coinciding with the first poly-silicon area, and the dry etching method for directly forming the barrier layer is before etching for directly forming the gate electrode.

US Pat. No. 10,249,732

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE TO UNIFORMLY FORM THICKNESS OF GATE INSULATING LAYER

Hyundai Motor Company, S...

1. A manufacturing method of a semiconductor device, comprising:sequentially forming an n? type of layer, a p type of region, and an n+ type of region on a first surface of a substrate;
forming a preliminary trench including a lower surface upwardly convex with respect to the first surface of the substrate in the n? type of layer by performing a first etching process;
forming a preliminary gate insulating layer including a preliminary first portion disposed at a lateral surface of the preliminary trench and a preliminary second portion disposed at the lower surface of the preliminary trench by performing a first thermal oxidation process;
etching the lower surface of the preliminary trench and the preliminary second portion to form a trench by performing a second etching process; and
forming a gate insulating layer in the trench by performing a second thermal oxidation process,
wherein the gate insulating layer includes a first portion disposed at a lateral surface of the trench and a second portion disposed at a lower surface of the trench,
wherein a thickness of the preliminary first portion is greater than a thickness of the preliminary second portion,
wherein the thickness of the preliminary first portion is greater than a thickness of the first portion,
wherein the thickness of the first portion is the same as a thickness of the second portion, and
wherein the thickness of the second portion is uniform.

US Pat. No. 10,249,731

VERTICAL FET WITH SHARP JUNCTIONS

International Business Ma...

1. A method of forming a vertical field-effect transistor (VFET) device, the method comprising the steps of:forming a silicon germanium (SiGe) layer on a substrate, wherein the SiGe layer as formed on the substrate is undoped;
forming a silicon (Si) layer on the SiGe layer, wherein the Si layer as formed on the SiGe layer is undoped;
patterning fins in the Si layer by forming fin hardmasks on the Si layer, and etching the fins in the Si layer using the fin hardmasks;
forming sacrificial spacers along sidewalls of the fins;
forming recesses in the SiGe layer between the fins;
growing an epitaxial material in the recesses, wherein the epitaxial material grown in the recesses comprises a source and drain dopant;
annealing the epitaxial material to diffuse the source drain dopant into the SiGe layer under the fins forming bottom source and drains of the VFET device;
removing the sacrificial spacers;
forming a bottom spacer on the bottom source and drains of the VFET device;
depositing a gate dielectric onto the fins and the bottom spacer;
depositing a gate conductor onto the gate dielectric;
depositing an organic planarizing layer (OPL) over the fins;
recessing the OPL below tops of the fins;
recessing the gate dielectric and the gate conductor to expose the fin hardmasks on the tops of the fins;
forming a top spacer on the OPL in between the tops of the fins;
removing the fin hardmasks; and
forming top source and drains of the VFET device on the tops of the fins.

US Pat. No. 10,249,730

CONTROLLING GATE PROFILE BY INTER-LAYER DIELECTRIC (ILD) NANOLAMINATES

International Business Ma...

1. A method comprising:providing a semiconductor structure including a substrate, a plurality of parallel fins extending above the substrate, a plurality of gate structures perpendicular to the plurality of fins and including a plurality of sidewall spacers, and a plurality of source-drain regions intermediate the plurality of gate structures;
depositing over outer surfaces of said plurality of gate structures a liner of a silicon-containing material;
depositing over said liner of silicon-containing material an inter-layer dielectric material; and
annealing said semiconductor substrate with said deposited liner of silicon-containing material and deposited inter-layer dielectric material, to at least partially consume said liner of silicon-containing material into said inter-layer dielectric material, to control residual stress such that resultant gate structures following said annealing have an aspect ratio range of 3:1 to 10:1, and are uniform in range to within seven percent of a target critical dimension.

US Pat. No. 10,249,729

METHOD FOR FABRICATING METAL REPLACEMENT GATE SEMICONDUCTOR DEVICE USING DUMMY GATE AND COMPOSITE SPACER STRUCTURE

UNITED MICROELECTRONICS C...

1. A method for fabricating a semiconductor device, comprising:providing a silicon substrate;
forming a first gate dielectric layer on the silicon substrate;
forming a dummy gate on the first gate dielectric layer;
conformally depositing a composite spacer film on the dummy gate and the silicon substrate, wherein the composite spacer film comprises a first nitride-containing layer, an oxide layer on the first nitride-containing layer, and a second nitride-containing layer on the oxide layer;
conformally depositing a hard mask layer on the composite spacer film;
anisotropically etching the hard mask layer and the composite spacer film, thereby forming a composite spacer structure on each sidewall of the dummy gate;
forming a recessed region in the silicon substrate and adjacent to the composite spacer structure;
forming a SiGe epitaxial layer in the recessed region;
removing the hard mask layer from the composite spacer structure;
conformally depositing a contact etch stop layer (CESL) on the composite spacer structure and the SiGe epitaxial layer;
depositing an inter-layer dielectric (ILD) layer on the CESL;
subjecting the ILD layer to a polishing process so as to expose a top surface of the dummy gate;
removing the dummy gate and a first portion of the first nitride-containing layer, thereby forming a gate trench and exposing the first gate dielectric layer; and
removing the first gate dielectric layer from the gate trench, and selectively removing a second portion of the first nitride-containing layer and the oxide layer from the composite spacer structure, while leaving the second nitride-containing layer intact.

US Pat. No. 10,249,728

AIR-GAP GATE SIDEWALL SPACER AND METHOD

GLOBALFOUNDRIES INC., Gr...

1. An integrated circuit structure comprising:a gate adjacent to a semiconductor body at a channel region, the channel region being positioned laterally between source/drain regions;
a gate contact above and immediately adjacent to the gate;
metal plugs on the source/drain regions;
plug caps above and immediately adjacent to the metal plugs; and
a dielectric spacer comprising:
a lower air-gap segment positioned laterally between the gate and the metal plugs; and
an upper solid segment positioned laterally between the gate contact and the plug caps, wherein the lower air-gap segment is wider than a top portion of the upper solid segment.

US Pat. No. 10,249,727

SEMICONDUCTOR DEVICE WITH SILICON NITRIDE FILM OVER NITRIDE SEMICONDUCTOR LAYER AND BETWEEN ELECTRODES

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:a first nitride semiconductor layer formed above a substrate;
a gate electrode arranged over the first nitride semiconductor layer via a gate insulating film;
a first electrode and a second electrode that are formed above the first nitride semiconductor layer on both sides of the gate electrode, respectively;
a silicon nitride film, including:
a first portion of the silicon nitride film formed on the first nitride semiconductor layer between the first electrode and the gate electrode;
a second portion of the silicon nitride film formed on the first nitride semiconductor layer between the second electrode and the gate electrode; and
a third portion of the silicon nitride film formed between the gate electrode and the gate insulating film,
wherein a concentration of two-dimensional electron gas in the first nitride semiconductor layer below the first portion of the silicon nitride film and the second portion of the silicon nitride film is higher than that of the two-dimensional electron gas in the first nitride semiconductor layer below the gate insulating film.

US Pat. No. 10,249,726

METHODS OF FORMING A PROTECTION LAYER ON A SEMICONDUCTOR DEVICE AND THE RESULTING DEVICE

GLOBALFOUNDRIES Inc., Gr...

1. A transistor device, comprising:a gate structure;
first and second spacers positioned adjacent opposite sides of said gate structure, said first and second spacers having upper surfaces; and
a multi-layer gate cap structure positioned above said gate structure and said upper surfaces of said first and second spacers, wherein said multi-layer gate cap structure comprises:
a first gate cap material layer positioned on an upper surface of said gate structure and on said upper surfaces of said first and second spacers;
a first high-k protection layer positioned on an upper surface of said first gate cap material layer; and
a second gate cap material layer positioned on an upper surface of said first high-k protection layer, wherein said first and second spacers, said first and second gate cap layers, and said high-k protection layer comprise dielectric materials, and said first and second gate cap layers comprise different materials than said first high-k protection layer.

US Pat. No. 10,249,725

TRANSISTOR WITH A GATE METAL LAYER HAVING VARYING WIDTH

DELTA ELECTRONICS, INC., ...

1. A semiconductor device comprising:an active layer;
at least one source electrode and at least one drain electrode present on the active layer;
at least one gate electrode present on the active layer and between the source electrode and the drain electrode;
a first insulating layer present on the source electrode, the drain electrode, and the gate electrode;
at least one gate metal layer present on the gate electrode and the first insulating layer, wherein the gate metal layer comprises a plurality of narrow portions and a plurality of wider portions arranged along a direction, at least one of the wider portions of the gate metal layer is in direct contact with two adjacent narrow portions of the gate metal layer, and the gate electrode is arranged along the direction;
a plurality of vias present between the gate metal layer and the gate electrode;
at least one first source metal layer present on the source electrode and the first insulating layer;
at least one drain metal layer present on the drain electrode and the first insulating layer; and
at least one second source metal layer present on the first insulating layer and at the same level as the gate metal layer and the drain metal layer, wherein the second source metal layer comprises a plurality of narrow portions and a plurality of wider portions, the narrow portions of the second source metal layer are adjacent respectively to the wider portions of the gate metal layer, and the wider portions of the second source metal layer are adjacent respectively to the narrow portions of the gate metal layer, and a projection of all of the gate metal layer onto the active layer in a direction normal to the upper surface of the substrate is separated from a projection of the second source metal layer onto the active layer in the direction normal to the upper surface of the substrate and a projection of the drain metal layer onto the active layer in the direction normal to the upper surface of the substrate.

US Pat. No. 10,249,724

LOW RESISTANCE CONTACT STRUCTURES FOR TRENCH STRUCTURES

INTERNATIONAL BUSINESS MA...

1. An electrical device comprising:at least one contact surface and an interlevel dielectric layer present atop the electrical device, wherein the interlevel dielectric layer includes at least one trench to the at least one contact surface of the electrical device;
a metal semiconductor alloy region that is in direct contact with the at least one contact surface;
a conformal titanium liner present on the sidewalls of the trench and is in direct contact with the metal semiconductor alloy region that is atop the at least one contact surface; and
a metal fills the at least one trench, and is in direct contact with the conformal titanium liner, the metal is selected from the group consisting of comprising ruthenium (Ru), iridium (Ir), osmium (Os), molybdenum (Mo), copper (Cu) and a combination thereof, wherein a contact provided by a combination of the conformal titanium liner and the metal fill have a resistance of 45 micro ohms per cm or less.

US Pat. No. 10,249,723

SEMICONDUCTOR DEVICE

Infineon Technologies Aus...

20. A semiconductor device, comprising:a semiconductor body having a surface;
a trench arranged within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body;
a first electrode and a first insulator arranged within the trench, the first insulator insulating the first electrode from the semiconductor body; and
a second electrode and a second insulator arranged within the trench, the second insulator insulating the second electrode from the first electrode,
wherein the first electrode extends deeper within the trench than the second electrode and forms a well incorporating each of the second electrode and the second insulator,
wherein at a first lateral termination area between the active region and the non-active region, each of the first electrode and the second electrode extend towards the surface such that the first electrode and the second electrode have a common lateral extension range and a common vertical extension range,
wherein a groove is formed in a lateral extremity of the second electrode, at the first lateral termination area.

US Pat. No. 10,249,722

REDUCED PARASITIC CAPACITANCE WITH SLOTTED CONTACT

International Business Ma...

1. A semiconductor device, the device comprising:a first conductor formed on a substrate, having a first top surface with a first height that is positioned above the substrate, wherein:
a first insulating material is provided over the first conductor and the substrate;
one or more openings disposed in the first insulating material defined by two opposing surfaces that are in contact with the first insulating material and a bottom surface that is in contact with the substrate; and
a thin layer of metal silicide is provided in the one or more openings of the first insulating material such that the thin layer of metal silicide is adjacent to the first conductor;
a second conductor formed on the metal silicide, the second conductor having a second top surface with a second height that is positioned above the substrate and a bottom surface that interacts directly with a first top surface of the metal silicide, wherein:
a portion of the second conductor is removed to provide a slot,
the slot is defined by opposing interior sidewalls and a bottom portion such that the bottom portion of the slot is below the first height of the first conductor,
the top of the slot is at the second height of the second conductor,
a long direction of the slot is perpendicular to a silicon fin and the silicon fin is perpendicular to and passes through the first conductor, and
a second insulating material disposed into the slot, the second insulating material having a third top surface with a third height above the substrate, the third height being below the second height of the second conductor to provide a space within the slot for a third conductor, wherein:
the second insulating material is different than the first insulating material, and
the third conductor is a contact metal selected from a group comprising:
tungsten, copper, and aluminum; and
the third conductor deposited into the space within the slot, the third conductor having a fourth top surface with a fourth height above the substrate, the fourth height being equal to the second height of the second conductor without the use of lithography, wherein:
the second insulating material is a six-sided feature including two faces and four sides,
the two faces of the second insulating material are in contact with the first insulating material,
three of the four sides of the second insulating material are in contact with the second conductor,
one of the four sides of the second insulating material is in contact with the third conductor, and
the third height of the second insulating material is determined at least in part by resistance requirements of the semiconductor device.

US Pat. No. 10,249,721

SEMICONDUCTOR DEVICE INCLUDING A GATE TRENCH AND A SOURCE TRENCH

Infineon Technologies Aus...

1. A semiconductor device, comprising:a source trench extending into a semiconductor body from a first surface of the semiconductor body;
a source trench dielectric and a source trench electrode in the source trench;
a gate trench dielectric and a gate trench electrode in a gate trench extending into the semiconductor body from the first surface;
a body region of a first conductivity type between the gate and source trenches;
a source region of a second conductivity type different from the first conductivity type between the gate and source trenches;
an interconnection electrically coupling the body region and the source trench electrode,
wherein the interconnection laterally extends through the source trench dielectric in a direction that is parallel to the first surface and adjoins a lateral face of the source trench electrode and of the body region, the lateral face of the source trench electrode and of the body region being perpendicular to the first surface,
and wherein an interface between the source trench dielectric and the semiconductor body at a sidewall of the source trench is step shaped at a transition between lower and upper parts of the source trench dielectric; wherein the step shaped interface between the source trench dielectric and the semiconductor body directly contacts the source trench dielectric and the semiconductor body, and
a source contact on the source trench electrode at the first surface.

US Pat. No. 10,249,720

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device that includes an active region, comprising:a semiconductor substrate having first and second principal surfaces;
a first conductive type region disposed in a first principal side of the semiconductor substrate;
a second conductive type region disposed on the first conductive type region;
a trench disposed farther outward than the active region, the trench having a width extending in a first direction, and a depth extending in a second direction, away from the first principal surface of the semiconductor substrate, the trench having first and second side walls;
a pn junction between the second conductivity type region and the first conductivity type region, the pn junction extending outwardly from the active region in the first direction and being terminated by the trench;
an insulating film embedded inside the trench;
a first field plate disposed inside the insulating film and extending in the second direction, a distance between the first side wall of the trench and the first field plate in the first direction being greater than a width of the first field plate, the first field plate curving away from the first side wall of the trench in the first direction, as a depth of the first field plate from the first principal surface of the semiconductor substrate increases;
a first electrode contacting the second conductivity type region and the first field plate; and
a second electrode disposed at the second principal surface of the semiconductor substrate.

US Pat. No. 10,249,719

DEVICE ISOLATION USING PREFERENTIAL OXIDATION OF THE BULK SUBSTRATE

INTERNATIONAL BUSINESS MA...

1. A method, comprising:providing a structure including a substrate, a buffer layer formed on the substrate and a semiconductor layer formed on the buffer layer;
etching the semiconductor layer so as to form a fin and exposing the buffer layer;
etching the buffer layer such that a portion of the buffer layer, disposed under the fin, is exposed; and
oxidizing the buffer layer and the fin so as to form an oxide layer under the fin,
wherein a distance between a top surface of the oxide layer and a top surface of the buffer layer is more than a distance between a bottom surface of the fin and the top surface of the buffer layer such that, a distance between a bottom surface of the substrate and the top surface of the oxide layer is more than a distance between the bottom surface of the substrate and the bottom surface of the fin.

US Pat. No. 10,249,718

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

Kabushiki Kaisha Toshiba,...

1. A semiconductor device comprising:a metal layer;
an n-type first silicon carbide region; and
a second silicon carbide region of metal containing at least one element selected from the group consisting of nickel (Ni), palladium (Pd), and platinum (Pt), and positioned between the metal layer and the first silicon carbide region,
wherein
the at least one element is present at a carbon site of a crystal structure of silicon carbide.

US Pat. No. 10,249,717

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a first electrode;
a second electrode, the second electrode including a first electrode region, a second electrode region, and a third electrode region, a first direction being from the first electrode toward the first electrode region and crossing a second direction, the second direction being from the first electrode region toward the second electrode region, a position of the third electrode region in the first direction being between a position of the first electrode region in the first direction and a position of the first electrode in the first direction;
a first semiconductor region of a first conductivity type, the first semiconductor region including a first partial region, a second partial region, a third partial region, a fourth partial region, and a fifth partial region, the first partial region being separated from the first electrode in a third direction, the third direction crossing the first direction and the second direction, the second partial region being separated from the first electrode region in the third direction, a position of the third partial region in the first direction being between a position of the first partial region in the first direction and a position of the second partial region in the first direction, at least a portion of the third partial region being between the first electrode and the first electrode region in the first direction, the fourth partial region being separated from the second electrode region in the third direction, the fifth partial region being between the second partial region and the fourth partial region;
a second semiconductor region of a second conductivity type, the second semiconductor region including a sixth partial region, a seventh partial region, an eighth partial region, and a ninth partial region, the sixth partial region being positioned between the second partial region and the first electrode region in the third direction, a portion of the seventh partial region being positioned between the first electrode region and the at least a portion of the third partial region in the first direction, the eighth partial region being positioned between the fourth partial region and the second electrode region in the third direction, at least a portion of the ninth partial region being positioned between the first electrode region and the second electrode region in the second direction;
a third semiconductor region of the second conductivity type, the third semiconductor region being connected to the second semiconductor region, the third semiconductor region being positioned between the third electrode region and the at least a portion of the third partial region in the third direction, the third semiconductor region being positioned between the first electrode and another portion of the seventh partial region in the first direction;
a fourth semiconductor region of the first conductivity type, the fourth semiconductor region being electrically connected to the second electrode, the fourth semiconductor region including a tenth partial region, an eleventh partial region, and a twelfth partial region, the tenth partial region being positioned between the third semiconductor region and a portion of the third electrode region in the third direction, the eleventh partial region being positioned between the seventh partial region and another portion of the third electrode region in the third direction, the twelfth partial region being positioned between the ninth partial region and the second electrode in the third direction; and
a first insulating film being provided between the first electrode and the first semiconductor region, between the first electrode and the third semiconductor region, and between the first electrode and the fourth semiconductor region.

US Pat. No. 10,249,716

IGBT ASSEMBLY HAVING SATURABLE INDUCTOR FOR SOFT LANDING A DIODE RECOVERY CURRENT

IXYS, LLC, Milpitas, CA ...

1. A method of manufacture comprising:depositing a volume of a liquid in an immediate vicinity of a conductor, wherein the liquid contains ferromagnetic particles, wherein the conductor is a part of an electronic device assembly;
causing the liquid to solidify so that the conductor and the solidified liquid together form a saturable inductor structure, wherein the saturable inductor structure has an unsaturated inductance of at least 200 nH, wherein the saturable inductor structure has a saturated inductance that is smaller than the unsaturated inductance, and wherein the solidified liquid holds the ferromagnetic particles in place with respect to the conductor; andassembling the saturable inductor structure, a diode and an insulated-gate bipolar transistor (IGBT) such that the diode and the saturable inductor structure are coupled in series between an emitter of the IGBT and a collector of the IGBT.

US Pat. No. 10,249,715

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a first nitride semiconductor layer formed above a substrate;
a second nitride semiconductor layer formed over the first nitride semiconductor layer;
a third nitride semiconductor layer formed over the second nitride semiconductor layer;
a fourth nitride semiconductor layer formed over the third nitride semiconductor layer;
a trench that extends up to the middle of the third nitride semiconductor layer while penetrating through the fourth nitride semiconductor layer;
a gate electrode disposed in the trench with a gate insulating film in between;
a first electrode and a second electrode formed above the fourth nitride semiconductor layer on both sides of the gate electrode; and
a coupling electrode electrically coupled to the first nitride semiconductor layer,
wherein electron affinity of the second nitride semiconductor layer is equal to or larger than electron affinity of the first nitride semiconductor layer,
wherein electron affinity of the third nitride semiconductor layer is equal to or larger than the electron affinity of the first nitride semiconductor layer,
wherein electron affinity of the fourth nitride semiconductor layer is smaller than the electron affinity of the first nitride semiconductor layer,
wherein the coupling electrode is electrically isolated from the first electrode, and
wherein a voltage applied to the coupling electrode is different from a voltage applied to the first electrode.

US Pat. No. 10,249,714

METHOD OF FORMING EPITAXIAL BUFFER LAYER FOR FINFET SOURCE AND DRAIN JUNCTION LEAKAGE REDUCTION

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor device comprising:forming a fin structure from a semiconductor substrate, wherein an upper surface of the fin structure is provided by an upper surface of the semiconductor substrate and a length of a sidewall of the fin structure extends from the upper surface of the fin structure to a recessed surface of the semiconductor substrate present at a base of the fin structure;
forming a lightly doped semiconductor material on the fin structure, wherein a portion of the lightly doped semiconductor material is formed on a recessed surface of a semiconductor substrate that is present at the base of the fin structure wherein a dopant concentration in the lightly doped semiconductor material ranges from 1×1019 to 5×1019; and
epitaxially growing a doped semiconductor material on the lightly doped semiconductor material, the doped semiconductor material having a greater dopant concentration than the lightly doped semiconductor material.

US Pat. No. 10,249,713

SEMICONDUCTOR DEVICE INCLUDING AN ESD PROTECTION ELEMENT

ABLIC Inc., (JP)

1. A semiconductor device including an ESD protection element,the semiconductor device comprising an element in an internal circuit region and having an operating voltage,
the ESD protection element comprising an N-type MOS transistor provided on one of a P well and a P-type semiconductor substrate,
the N-type MOS transistor including a gate electrode connected to one of the P well and the P-type semiconductor substrate such that the gate electrode has one of a well potential that is a potential of the P well and a ground potential that is a potential of the P-type semiconductor substrate,
the N-type MOS transistor having a drain active region in which an N-type high-concentration drain region and a P-type drain region are adjacent to each other to form a PN junction,
the P-type drain region having a potential that comprises one of the potential of the P well and the potential of the P-type semiconductor substrate,
the P-type drain region being adjacent to an end portion of the drain active region in a W direction, and another P-type drain region being provided in a region away from the end portion in the W direction, and
the ESD protection element having a withstand voltage that comprises a junction withstand voltage of the PN junction in the drain active region.

US Pat. No. 10,249,712

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor device comprising:a semiconductor substrate doped with impurities;
a front surface-side electrode provided on a front surface side of the semiconductor substrate; and
a back surface-side electrode provided on a back surface side of the semiconductor substrate; wherein
the semiconductor substrate has:
a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration;
a high concentration region arranged closer to a front surface than the peak region and having a gentler distribution of the impurity concentration than the one or more peaks; and
a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region,
wherein the impurity concentration at a boundary between the peak region and the high concentration region is higher than the impurity concentration in the low concentration region,
the high concentration region is adjacent to a front surface side of the peak region, and the low concentration region is adjacent to a front surface side of the high concentration region, and
the peak region, the high concentration region, and the low concentration region form a contiguous region of the semiconductor device in a depth direction.

US Pat. No. 10,249,711

FET WITH MICRO-SCALE DEVICE ARRAY

1. A field-effect transistor (FET), comprising:a substrate comprising a crystal structure on which an epitaxial active channel area has been grown;
a plurality of micro-cells uniformly distributed over said active channel area, each of said micro-cells comprising:
a source electrode;
a drain electrode; and
at least one gate electrode;
wherein one of said source or drain electrodes is at the center of said micro-cell and the other of said source or drain electrodes is along the perimeter of said micro-cell, said at least one gate electrode aligned parallel to one of the crystal planes of said substrate comprising a crystal structure;
said micro-cell arranged such that there are not gate electrodes aligned parallel to at least some of said crystal planes such that at least some of the regions around the electrode at the center of said micro-cell are electrically isolated; and
a multi-layer interconnection arrangement, wherein a first metal layer interconnects one of said drain or source electrodes, a second metal layer interconnects said gate electrodes, and a third metal layer interconnects the other of said drain or source electrodes.

US Pat. No. 10,249,710

METHODS, APPARATUS, AND SYSTEM FOR IMPROVED NANOWIRE/NANOSHEET SPACERS

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor structure, comprising:a semiconductor substrate;
at least one fin, wherein the at least one fin comprises one or more first layers comprising a first material and one or more second layers comprising a second material, wherein the first layers and the second layers are interspersed and the first layers laterally extend further than the second layers;
a dummy gate structure comprising a first spacer material disposed on sidewalls of the dummy gate;
a second spacer material disposed adjacent to each of the second layers, wherein sidewalls of the fin comprise exposed portions of each of the first layers and the second spacer material, and the second spacer material differs from the first spacer material; and
an epitaxial source/drain material disposed on at least the exposed portions of each of the first layers.

US Pat. No. 10,249,709

STACKED NANOSHEET FIELD EFFECT TRANSISTOR DEVICE WITH SUBSTRATE ISOLATION

International Business Ma...

1. A semiconductor device, comprising:a nanosheet stack structure formed on a semiconductor substrate, wherein the nanosheet stack structure comprises a rare earth oxide (REO) layer formed on the semiconductor substrate, and a semiconductor channel layer disposed adjacent to the REO layer;
a metal gate structure formed over the nanosheet stack structure;
a gate insulating spacer disposed on vertical sidewalls of the metal gate structure, wherein end portions of the semiconductor channel layer are exposed through the gate insulating spacer; and
a first source/drain region and a second source/drain region formed in contact with a respective one of the end portions of the semiconductor channel layer exposed through the gate insulating spacer;
wherein a portion of the metal gate structure is disposed between the semiconductor channel layer and the REO layer, wherein the REO layer isolates the metal gate structure from the semiconductor substrate;
wherein the first and second source/drain regions comprise an epitaxial semiconductor material that is epitaxially grown on the end portions of the semiconductor channel layer, and wherein the first and second source/drain regions are formed in contact with portions of the REO layer which extend past the gate insulating spacer such that the REO layer isolates the first and second source/drain regions from the semiconductor substrate.

US Pat. No. 10,249,708

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device having a lateral insulated gate field effect transistor portion, comprising:a semiconductor substrate having a main surface and an insulating layer formed on said main surface;
a semiconductor layer formed on said insulating layer;
a trench formed to penetrate, in order, the semiconductor layer and the insulating layer, and to reach the semiconductor substrate;
a gate electrode of said insulated gate field effect transistor portion embedded within said trench;
a first impurity region of a first conductivity type, which has first and second portions separated from each other along said trench, in said semiconductor layer, and serves as a source or an emitter;
a second impurity region, which is arranged in said semiconductor layer on a side of the first impurity region opposite to said trench, and serves as a drain of the first conductivity type or a collector of a second conductivity type; and
a back gate region of the second conductivity type, which is arranged in said semiconductor layer between said first and second portions of said first impurity region, and between the second impurity region and said first and second portions of said first impurity region.

US Pat. No. 10,249,707

LATERALLY DIFFUSED METAL OXIDE SEMICONDUCTOR FIELD-EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREFOR

CSMC TECHNOLOGIES FAB2 CO...

1. A laterally diffused metal oxide semiconductor field-effect transistor, comprising:a substrate;
a source;
a drain;
a body region; and
a well region on the substrate,
wherein the well region comprises:
an inserting type well having a P-doping type, wherein the inserting type well is disposed below the drain and is in contact with the drain;
an N well disposed on both sides of the inserting type well; and
a P well disposed adjacent to the N well and in contact with the N well,
wherein the source and the body region are disposed in the P well,
the inserting type well is in direct contact with the substrate,
the N well is in direct contact with the substrate,
the P well is in direct contact with the substrate, and
wherein the well region comprises a first well region on the substrate and a second well region on the first well region; the inserting type well comprises a first inserting type well in the first well region and a second inserting type well in the second well region; the N well comprises a first N well in the first well region and a second N well in the second well region; the P well comprises a first P well in the first well region and a second P well in the second well region.

US Pat. No. 10,249,706

SEMICONDUCTOR STRUCTURE

UNITED MICROELECTRONICS C...

1. A semiconductor structure, comprising:a substrate having a cell region defined thereon;
a plurality of lower electrode structures located in the cell region;
an top support structure, contacting a top region of the lower electrode structure; and
at least one middle support structure located between the substrate and the top support structure, contacting a middle region of the lower electrode structure, wherein when viewed in a top view, the top support structure and the middle support structure do not completely overlapped with each other, wherein a vertical height from a top surface of the substrate to the upper support structure is H1, and a vertical height from the top surface of the substrate to the middle support structure is H2, and wherein H2/H1 is between 0.4 and 0.6.

US Pat. No. 10,249,705

CAPACITOR ARRAY STRUCTURE

ALi Corporation, Hsinchu...

1. A capacitor array structure, comprising:N capacitor units each comprising an upper electrode and a lower electrode,
wherein the upper electrode and the lower electrode comprise a plurality of metal portions, and the metal portions are patterned,
wherein the capacitor units are arranged adjacent to one another along a first axial direction to form a capacitor series, and an ith capacitor unit of the capacitor units comprises:
a first metal layer comprising a first metal portion of the lower electrode;
a second metal layer disposed above the first metal layer and comprising a second metal portion of the lower electrode and a first metal portion of the upper electrode; and
a third metal layer disposed above the second metal layer and comprising a third metal portion of the lower electrode, a fourth metal portion of the lower electrode, and a second metal portion of the upper electrode,
wherein i is a positive integer not larger than N and N is a positive integer, wherein i is larger than or equal to 2,
wherein the second metal portion of the lower electrode has an opening, and a side of the first metal portion of the upper electrode is exposed in the opening, such that the side of the first metal portion of the upper electrode is adjacent to the lower electrode of an (i-1)th capacitor unit.

US Pat. No. 10,249,704

CAPACITOR

MURATA MANUFACTURING CO.,...

1. A capacitor comprising:a conductive porous base material with a porous part having a plurality of pores;
an upper electrode opposite the porous part, the upper electrode comprising, as a main constituent thereof, a material selected from the group consisting of ruthenium, platinum, and an alloy of ruthenium and platinum; and
a dielectric layer between the upper electrode and the conductive porous base material,
wherein the upper electrode and the dielectric layer extend into the plurality of pores of the porous part.

US Pat. No. 10,249,703

METAL RESISTORS HAVING NITRIDIZED METAL SURFACE LAYERS WITH DIFFERENT NITROGEN CONTENT

International Business Ma...

1. A method of forming a semiconductor structure, said method comprising:providing a dielectric-containing substrate comprising at least an interconnect dielectric material layer;
forming a first metal layer portion on a first portion of a topmost surface of said interconnect dielectric material layer, and a second metal layer portion on a second portion of said topmost surface of said interconnect dielectric material layer;
performing a first nitridation process to provide a first nitridized metal surface layer having a first nitrogen content within said first metal layer portion, wherein said first metal layer portion and said first nitridized metal surface layer provide a first metal resistor structure; and
performing a second nitridation process to provide a second nitridized metal surface layer having a second nitrogen content that differs from said first nitrogen content within said second metal layer portion, wherein said second metal layer portion and said second nitridized metal surface layer provide a second metal resistor structure.

US Pat. No. 10,249,702

METAL RESISTORS HAVING VARYING RESISTIVITY

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:providing a dielectric-containing substrate comprising at least an interconnect dielectric material layer;
performing a first nitridation process to provide a first nitridized dielectric surface layer having a first nitrogen content in a first region of the dielectric-containing substrate and within a portion of the interconnect dielectric material layer;
performing a second nitridation process to provide a second nitridized dielectric surface layer having a second nitrogen content that differs from the first nitrogen content in a second region of the dielectric-containing substrate and within another portion of the interconnect dielectric material layer;
forming a metal layer on the first nitridized dielectric surface layer and the second nitridized dielectric surface layer;
forming a dielectric capping layer on the metal layer; and
patterning the dielectric capping layer, the metal layer, the first nitridized dielectric surface layer and the second nitridized dielectric surface layer to provide a first metal resistor structure spaced apart from a second metal resistor structure.

US Pat. No. 10,249,701

DISPLAY DEVICE

Japan Display Inc., Toky...

1. A display device comprising:a display region comprising a plurality of pixels each including a transistor, an insulating film above the transistor, a pixel electrode arranged above the insulating film and electrically connected to the transistor, and a common electrode above the insulating film; and
a peripheral region outside of the display region, the peripheral region including:
a plurality of first terminals arranged in a first direction;
a second terminal;
a third terminal; and
a first wiring connected to the second terminal and the third terminal,
wherein the first terminals are located between the second terminal and the third terminal in the first direction, and
the first wiring has a first part extending in the first direction between the display region and the first terminals, a second part connecting to the second terminal and the first part, and a third part connecting to the third terminal and the first part.

US Pat. No. 10,249,700

OLED ARRAY SUBSTRATE, DISPLAY APPARATUS AND METHOD FOR REPAIRING DARK SPOT THEREON

BOE TECHNOLOGY GROUP CO.,...

1. An organic light-emitting diode (OLED) array substrate, comprising:a base substrate;
a power line and a connection component both disposed on the base substrate;
a pixel structure disposed in a pixel region, wherein the pixel structure comprises a driving transistor and an OLED device;
wherein the driving transistor comprises a gate electrode, a first source/drain electrode and a second source/drain electrode; the first source/drain electrode is connected with the OLED device; and the second source/drain electrode is connected to the power line;
the OLED device comprises a first electrode and a second electrode, and the first electrode is electrically connected with the first source/drain electrode of the driving transistor;
the connection component is configured to electrically insulate the first electrode from the power line before repairing the OLED array substrate; and
the connection component is further configured to electrically connect the first electrode with the power line in a case of repairing the OLED array substrate.

US Pat. No. 10,249,699

ORGANIC LIGHT EMITTING DIODE SUBSTRATE, METHOD OF FABRICATING THE SAME AND DISPLAY APPARATUS HAVING THE SAME

BOE TECHNOLOGY GROUP CO.,...

1. An organic light emitting diode (OLED) substrate, comprising:a base substrate;
an organic electroluminescence unit on the base substrate;
a thin film encapsulation layer on the organic electroluminescence unit; and
a plurality of first electrodes and a plurality of second electrodes in the thin film encapsulation layer,
wherein the thin film encapsulation layer comprises N numbers of inorganic film layers and N numbers of organic film layers, where N is an integer equal to or larger than 2, the N numbers of inorganic film layers and the N numbers of organic film layers are alternately stacked on the organic electroluminescence unit along a direction away from the base substrate, and each of the N numbers of organic film layers is stacked on a respective one of the N numbers of inorganic film layers,
and wherein the plurality of first electrodes are embedded in one of the N numbers of organic film layers, and the plurality of second electrodes are embedded in another one of the N numbers of organic film layers.

US Pat. No. 10,249,698

TRANSPARENT OLED DISPLAY PANEL

SHENZHEN CHINA STAR OPTOE...

1. A transparent OLED display panel, comprising: a plurality of display pixels arranged in an array, each of the plurality of display pixels comprising a display region and a transparent region sequentially arranged in a vertical direction, each display region comprising a first, a second, and a third sub-pixels sequentially arranged in a horizontal direction;wherein a horizontal scanning line and a horizontal first power supply line electrically connected to a row of the display pixels are provided corresponding to each row of the display pixels, a vertical second power supply line electrically connected to the horizontal first power supply line is provided corresponding to each column of the display pixels, a first data line electrically connected to the first sub-pixel is provided corresponding to each column of the first sub-pixel, a second data line electrically connected to the second sub-pixel is provided corresponding to each column of the second sub-pixel, a third data line electrically connected to the third sub-pixel is provided corresponding to each column of the third sub-pixel;
the horizontal first power supply line and the horizontal scanning line are located in a first metal layer, the first data line and the second data line are located in a second metal layer stacked above the first metal layer, an insulating layer is provided between the first metal layer and the second metal layer;
the vertical second power supply line comprises: a first extension portion and a first bridge portion, the first extension portion is located in the first metal layer, the first bridge portion is located in the second metal layer, the first bridge portion is electrically connected to the first extension portion through a first via hole in the insulating layer, and the vertical second power supply line is insulated from and cross the horizontal scanning line by the first bridge portion; the third data line comprising a second extension portion and a second bridge portion, the second extension portion is located in the first metal layer, the second bridge portion is located in the second metal layer, the second bridge portion is electrically connected to the second extension portion through a second via hole in the insulating layer, and the third data line is insulated from and cross the horizontal first power supply line by the second bridge portion and the horizontal scanning line; and
in the transparent region, the first data line is insulated and stacked to the vertical second power supply line, and the second data line is insulated and stacked to the third data line.

US Pat. No. 10,249,697

DISPLAY PANEL AND DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A display panel, comprising:an active area; and
two GOA driving circuit areas which are arranged respectively on a right side and a left side of the active area,
wherein the display panel is bent along bending positions formed by gaps between the active area and each of the GOA driving circuit areas,
wherein a serpentine metal line connecting a GOA driving circuit and an internal circuit of the active area is arranged in the display panel at a position corresponding to each of the bending positions,
wherein the serpentine metal line is contained in a jumper joint structure of different layers of metal lines,
wherein the jumper joint structure of different layers of metal lines comprises:
a first metal layer, which is in a same layer as a first lead line of the GOA driving circuit and a second lead line of the internal circuit of the active area, wherein metal jumper lines without contacting each other, are arranged between the first lead line and the second lead line;
a first insulating layer, arranged on the first metal layer;
an inorganic dielectric layer, arranged on the first insulating layer, and having via holes at positions corresponding to two ends of each of the metal jumper lines;
jumpers without contacting each other, arranged on the inorganic dielectric layer and connected to the corresponding metal jumper lines in sequence through the via holes to form the serpentine metal line; and
an organic dielectric layer, arranged on the jumpers and the exposed inorganic dielectric layer.

US Pat. No. 10,249,696

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate including a pixel region and a peripheral region;
a plurality of pixels provided in the pixel region of the substrate;
a scan line and a data line spaced apart and intersecting each other;
a transistor provided in the pixel region, the transistor including a first transistor connected to the scan line and the data line and a second transistor connected to the first transistor;
a light emitting element connected to the transistor;
a first blocking layer disposed between the substrate and the first transistor, the first blocking layer being electrically connected to the first transistor; and
a second blocking layer disposed between the substrate and the second transistor, the second blocking layer being electrically connected to the second transistor,
wherein the first blocking layer is connected to a gate electrode of the first transistor, and the second blocking layer is connected to any one of source and drain electrodes of the second transistor.

US Pat. No. 10,249,695

DISPLAYS WITH SILICON AND SEMICONDUCTING-OXIDE TOP-GATE THIN-FILM TRANSISTORS

Apple Inc., Cupertino, C...

1. A display comprising:a semiconducting-oxide drive transistor, wherein the semiconducting-oxide drive transistor is a top-gate transistor;
a storage capacitor coupled to the drive transistor, wherein the storage capacitor comprises conductive oxide, and wherein the storage capacitor is formed in the same layer in the display as the semiconducting-oxide drive transistor;
a silicon switching transistor coupled to the semiconducting-oxide drive transistor, wherein the silicon switching transistor is formed on a substrate, and wherein the semiconducting-oxide drive transistor is formed above the silicon switching transistor;
an organic layer formed on the semiconducting-oxide drive transistor;
a metal layer laterally coupling a source-drain terminal of the semiconducting-oxide drive transistor to a source-drain terminal of the silicon switching transistor, wherein the metal layer is not formed through the organic layer; and
a conductive structure electrically coupled to a gate conductor of the top-gate transistor, wherein the conductive structure is not formed through the organic layer.

US Pat. No. 10,249,694

ORGANIC EL DISPLAY DEVICE

SHARP KABUSHIKI KAISHA, ...

1. An organic EL display device comprising:a first resin substrate;
a basecoat film provided on the first resin substrate;
an organic EL element provided over the basecoat film;
a first sealing film covering the organic EL element;
a second resin substrate facing the first resin substrate, and provided closer to the first sealing film with an adhesive layer interposed between the second resin substrate and the first sealing film; and
a second sealing film provided outside the first sealing film, and enhancing adhesion between the basecoat film and a stack including the first sealing film and the adhesive layer, wherein
in a plan view, a peripheral edge of the first resin substrate is located inside a peripheral edge of the second resin substrate,
the second sealing layer covers at least a portion of each of the adhesive layer, the first resin substrate, and the basecoat film,
in the plan view, a peripheral edge of the adhesive layer is located inside the peripheral edge of the first resin substrate, and
a resin layer is provided between the second sealing film and a stack including the adhesive layer and the first resin substrate such that the resin layer covers a step between the adhesive layer and the first resin substrate.

US Pat. No. 10,249,693

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

Samsung Display Co., Ltd....

1. An organic light-emitting display apparatus comprising:a substrate;
an organic light-emitting device on the substrate;
a sealing member on the organic light-emitting device;
a phase retardation layer on a surface of the organic light emitting device; and
a linear polarization layer on another surface of the organic light-emitting device,
wherein the linear polarization layer is located to be closer to a source of external light than the phase retardation layer, and
wherein the linear polarization layer comprises a photochromic material.

US Pat. No. 10,249,692

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Seoul Viosys Co., Ltd., ...

1. A display device comprising:a base substrate;
a display element disposed on the base substrate;
a thin film encapsulation layer covering the display element;
a first organic layer disposed on the thin film encapsulation layer;
an inorganic layer disposed on the first organic layer;
touch electrodes disposed on the inorganic layer; and
a second organic layer disposed on the inorganic layer, the second organic layer covering the touch electrodes,
wherein the second organic layer is in contact with the inorganic layer.

US Pat. No. 10,249,691

FLEXIBLE ORGANIC LIGHT-EMITTING DISPLAY PANEL AND ELECTRONIC DEVICE

WUHAN TIANMA MICRO-ELECTR...

1. A flexible organic light-emitting display panel, comprising:a display region and a non-display region surrounding the display region, wherein the non-display region comprises a bendable region and a non-bendable region;
at least one metal bridge pressure-sensitive detection unit, which is at least partially provided in the bendable region and extends along a bending direction of the flexible organic light-emitting display panel, the at least one metal bridge pressure-sensitive detection unit comprises a first resistor, a second resistor, a third resistor and a fourth resistor; and
a plurality of semiconductor pressure-sensitive detection units, at least one of which is provided in the non-bendable region;
wherein a first end of the first resistor is electrically connected to a first end of the third resistor, a second end of the first resistor is electrically connected to a first end of the fourth resistor, a first end of the second resistor is electrically connected to a second end of the third resistor, and a second end of the second resistor is electrically connected to a second end of the fourth resistor;
wherein each of the first, second, third and fourth resistors of the at least one metal bridge pressure-sensitive detection unit takes a form of a serpentine metal film wiring, a wire resistance of the first resistor is equal to a wire resistance of the second resistor, and a wire resistance of the third resistor is equal to a wire resistance of the fourth resistor, the wire resistance of the first resistor is less than the wire resistance of the third resistor; and
wherein the first resistor and the second resistor both extend along the bending direction of the flexible organic light-emitting display panel, at least a part of the second resistor is arranged in the bendable region.

US Pat. No. 10,249,690

DISPLAY DEVICE HAVING A SUPPRESSION

SHARP KABUSHIKI KAISHA, ...

1. A display device including a display portion, the display device comprising:a flexible substrate in which the display portion is provided;
an inorganic film with a plurality of layers provided on the substrate;
a display element portion that is provided on the inorganic film and is provided to form the display portion; and
a suppression portion that is provided outside the display portion and suppresses progression of cracking that has occurred in a peripheral portion of the substrate,
wherein the plurality of layers of the inorganic film includes a first inorganic film and a second inorganic film formed on the first inorganic film, and
the suppression portion is constituted by a semiconductor layer formed between the first inorganic film and the second inorganic film.

US Pat. No. 10,249,689

COLOR-CONVERSION PANEL, METHOD OF MANUFACTURING THE PANEL, AND DISPLAY DEVICE INCLUDING THE PANEL

Samsung Display Co., Ltd....

1. A color conversion panel comprising:a substrate;
a first color filter and a second color filter adjacent to the first color filter disposed on the substrate;
a first color conversion layer disposed on the first color filter and comprising a first side and second side, wherein a material of the first side is identical to the second side, and wherein the first side is disposed between the first color filter and the second side in a first direction, and wherein the first direction is perpendicular to the substrate;
a second color conversion layer disposed on the second color filter;
a third color layer disposed on the substrate and comprising a first face and a second face, wherein a material of the first face is identical to a material of the second face, wherein the first face is disposed between the substrate and the second face in the first direction, and wherein the second face is disposed farther than the first side from the substrate;
a light blocking member disposed between the first color filter and the second color filter and comprising a first edge and a second edge,
wherein the second edge is disposed between the first edge and the first side in the first direction, is disposed farther than the first face from the substrate, and is disposed closer than the second face to the substrate,
wherein each of the first color conversion layer and the second color conversion layer includes at least two quantum dots representing different colors, and
wherein the first color filter displays a different color from the second color filter.

US Pat. No. 10,249,688

ORGANIC LIGHT EMITTING DISPLAY DEVICE WITH BANK STRUCTURE FOR ENHANCED IMAGE QUALITY AND HEAD MOUNTED DISPLAY INCLUDING THE SAME

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device comprising:two adjacent pixels including two adjacent anode electrodes, respectively;
an organic light-emitting layer disposed on the two adjacent anode electrodes; and
red, green, and blue color filters disposed on the organic light-emitting layer,
wherein a bank is disposed between the two adjacent anode electrodes of the two adjacent pixels, and separates the two adjacent anode electrodes from each other,
wherein the bank includes at least one color changing material that changes light emitted from the organic light-emitting layer into a predetermined color corresponding to one of the red, green, and blue color filters disposed on the organic light-emitting layer and outputs the changed color light,
wherein the organic light-emitting layer is disposed between the bank and the red, green, and blue color filters.

US Pat. No. 10,249,687

SELF-LIGHT EMITTING DISPLAY UNIT AND ELECTRONIC DEVICE

Sony Corporation, Tokyo ...

1. An organic EL display device comprising:a pixel layer including a first color pixel, a second color pixel and a third color pixel; and
a pixel circuit layer including a first color pixel circuit, a second color pixel circuit, and a third color pixel circuit,
wherein
the first color pixel has a first anode electrode,
the second color pixel has a second anode electrode,
the third color pixel has a third anode electrode,
the first color pixel circuit includes a first capacitor including a first electrode and a second electrode, a first sampling transistor, and a first drive transistor including a control terminal, a first current terminal and a second current terminal configured to flow a drive current to the first color pixel,
the second color pixel circuit includes a second capacitor including a third electrode and a fourth electrode, a second sampling transistor, and a second drive transistor including a control terminal, a first current terminal and a second current terminal configured to flow a drive current to the second color pixel,
the third color pixel circuit includes a third capacitor including a fifth electrode and a sixth electrode, a third sampling transistor, and a third drive transistor including a control terminal, a first current terminal and a second current terminal configured to flow a drive current to the third color pixel,
a portion of the first anode electrode overlaps with a portion of the first capacitor and a portion of the first driving transistor in a plan view,
a portion of the second anode electrode overlaps with a portion of the second capacitor and a portion of the first driving transistor in the plan view,
a shape of the second electrode is different from a shape of the fourth electrode in the plan view,
a first layer comprises the first electrode, the third electrode, and the first current terminal and the second current terminal of the first and the second driving transistor,
a second layer, formed distinctly from the first layer, comprises the second electrode and the fourth electrode, and
a third layer, formed distinctly from the first layer and the second layer, comprises the control terminals of the first and second driving transistors.

US Pat. No. 10,249,686

ORGANIC LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

Wuhan China Star Optoelec...

1. An organic light-emitting device, comprising:a substrate layer, a first electrode layer, light-emitting layers, and a second electrode arranged in layers defining a display zone of the organic light-emitting device;
the display zone comprising a plurality of primary pixels; each of the plurality of primary pixels comprising a first subpixel, a second subpixel, and a third subpixel; the first subpixel being a white subpixel; the second subpixel comprising a first light-emitting material for synthesizing white light; the third subpixel comprising a second light-emitting material; and
the organic light-emitting device further comprising a third light-emitting material for synthesizing the white light; the first light-emitting material comprising an original color zone and a synthesized color zone; the first light-emitting material for synthesizing the white light corresponding to the synthesized color zone and one portion of the third light-emitting material being layered or mixed to form the white subpixel;
the other portion of the third light-emitting material and the second light-emitting material being layered; a transmission distance of an exciton produced by the second light-emitting material being smaller than a thickness of the second light-emitting material; the third light-emitting material being formed in a zone corresponding to the white subpixel and the third subpixel;
wherein all function layers apart from the light-emitting layers of all of the subpixels are integrally formed.

US Pat. No. 10,249,685

HIGH RESOLUTION LOW POWER CONSUMPTION OLED DISPLAY WITH EXTENDED LIFETIME

Universal Display Corpora...

1. A full-color pixel arrangement for an OLED device, the full-color pixel arrangement comprising:a first sub-pixel comprising an emissive region of a first color and having a first optical path length;
a second sub-pixel comprising an emissive region of the first color, the second sub-pixel having a second optical path length different than the first optical path length;
a third sub-pixel comprising an emissive region of a second color;wherein the full-color pixel arrangement comprises emissive regions of exactly two different colors.

US Pat. No. 10,249,684

RESISTIVE CHANGE ELEMENTS INCORPORATING CARBON BASED DIODE SELECT DEVICES

Nantero, Inc., Woburn, M...

1. A resistive change memory element, comprising:a non-volatile resistive block switch, wherein said non-volatile resistive block switch comprises:
a first metal layer; and
a switch carbon layer in electrical contact with said first metal layer; and
a diode in a series connection with said non-volatile resistive block switch, wherein said diode comprises:
a conductive layer;
a semiconducting carbon layer in electrical contact with said conductive layer, wherein said conductive layer and said semiconducting carbon layer are configured to create a conductive path when sufficient voltage is applied; and
an intervening material layer placed between said conductive layer and said semiconducting carbon layer.

US Pat. No. 10,249,683

THREE-DIMENSIONAL PHASE CHANGE MEMORY ARRAYS AND METHODS OF MANUFACTURING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A phase change memory device containing a phase change memory material layer, the device comprising:a vertically repeating sequence of unit layer stacks located over a substrate, wherein each of the unit layer stacks comprises an insulating layer, at least one of the phase change memory material layer or a threshold switch material layer, and an electrically conductive word line layer;
a plurality of openings vertically extending through the vertically repeating sequence;
a plurality of vertical bit lines located within a respective one of the plurality of openings; and
vertical stacks of insulating spacers, wherein each of the insulating spacers laterally surrounds a respective one of the plurality of vertical bit lines, and contacts a sidewall of a respective one of the electrically conductive word line layers;
wherein the phase change memory device further comprises at least one feature selected from:
(i) a first feature in which the threshold switch material layer is located within one of the plurality of openings, contacts the vertical stack of insulating spacers and the phase change memory material layer in each unit layer stack, and laterally encloses a respective one of the plurality of vertical bit lines; and
each unit layer stack contains the phase change memory material layer which contacts a horizontal surface of the respective insulating layer and a horizontal surface of a conductive material layer within the unit layer stack; or
(ii) a second feature in which the phase change memory material layer is located within one of the plurality of openings, contacts the vertical stack of insulating spacers and the threshold switch material layer in each unit layer stack, and laterally encloses a respective one of the plurality of vertical bit lines; and
each unit layer stack contains the threshold switch material layer which contacts a horizontal surface of the respective insulating layer and a horizontal surface of the conductive material layer within the unit layer stack; or
(iii) a third feature in which the plurality of openings comprises line trenches that laterally extend along a horizontal direction;
the insulating spacers comprise insulating rail structures that laterally extend along the horizontal direction; and
the phase change memory device further comprises dielectric pillar structures located between each neighboring pair of vertical bit lines among the plurality of vertical bit lines that are laterally spaced along the horizontal direction; or
(iv) a fourth feature in which the threshold switch material layer comprises an ovonic threshold switch material layer; and
the plurality of openings comprise a plurality of discrete openings arranged as a two-dimensional array in the vertically repeating sequence of unit layer stacks.

US Pat. No. 10,249,682

NON-VOLATILE MEMORY SYSTEM WITH SERIALLY CONNECTED NON-VOLATILE REVERSIBLE RESISTANCE-SWITCHING MEMORY CELLS

SANDISK TECHNOLOGIES LLC,...

1. A non-volatile storage apparatus, comprising:a first plurality of serially connected non-volatile reversible resistance-switching memory cells comprising a dielectric region having a set of pockets, physically separate active regions positioned in the pockets and a barrier layer in contact with the active regions to form reversible resistance-switching interfaces;
a first plurality of word lines, each of the memory cells of the plurality are connected to a different word line of the first plurality of word lines, the word lines are surrounded by the dielectric region;
a first bit line connected to a first end of the first plurality of serially connected non-volatile reversible resistance-switching memory cells; and
a first switch connected to a second end of the first plurality of serially connected non-volatile reversible resistance-switching memory cells.

US Pat. No. 10,249,681

CROSS-POINT MEMORY ARRAY DEVICE AND METHOD OF MANUFACTURING THE SAME

SK HYNIX INC., Icheon (K...

1. A cross-point memory array device comprising:a plurality of first conductive line patterns disposed on a substrate, the plurality of first conductive line patterns extending in a first direction;
an insulating layer disposed on the first conductive line patterns, the insulating layer including a plurality of insulating film patterns and a plurality of switching film patterns;
a plurality of memory structures disposed on the plurality of switching film patterns, respectively; and
a plurality of second conductive line patterns disposed on the plurality of memory structures, the plurality of second conductive line patterns extending in a second direction that is nonparallel to the first direction,
wherein each of the plurality of switching film patterns has a variable resistance characteristic,
wherein the plurality of insulating film patterns comprise an oxide material and the plurality of switching film patterns comprise the oxide material with an dopant,
wherein the device further comprises a plurality of resistive element structures electrically connected in series to the plurality of switching film patterns, respectively, and to the plurality of memory structures, respectively,
wherein the plurality of resistive element structures each have an electrical resistance, and
wherein the plurality of resistive element structures prevent an operating current flowing through the switching film patterns and the memory structures from exceeding an upper limit.

US Pat. No. 10,249,680

THERMAL MANAGEMENT OF SELECTOR

WESTERN DIGITAL TECHNOLOG...

1. A memory device, comprising:a word line;
a bit line disposed perpendicular to the word line; and
a stack disposed between the word line and the bit line, wherein the stack comprises:
a memory element;
a selector having a plurality of sides, wherein the selector comprises alternating layers of selector elements and heat sinks;
a spacer layer disposed between the memory element and the selector;
a first insulating layer disposed between the word line and the bit line;
a second insulating layer disposed in direct contact with the first insulating layer; and
a dissipation layer disposed in direct contact with the first insulating layer;
wherein the dissipation layer is adjacent to the second insulating layer and a same width as the second insulating layer.

US Pat. No. 10,249,679

METHOD OF WIRELESS COMMUNICATION USING THERMOELECTRIC GENERATORS

STMICROELECTRONICS (ROUSS...

1. A method, comprising:generating a first signal by a first device, the first signal having a first value or a second value;
electrically powering a first thermoelectric generator as a function of the first signal to generate a first thermal gradient in the first thermoelectric generator, wherein the first thermoelectric generator comprises a plurality of semiconducting regions disposed at least in part in an interconnect region of a first integrated circuit, the interconnect region being disposed above a semiconducting substrate of the first integrated circuit, wherein the interconnect region comprises a plurality of metallization layers disposed in one or more insulation materials, the plurality of semiconducting regions underlies the plurality of metallization layers, and wherein a first metallization layer of the plurality of metallization layers extends between a second metallization layer of the plurality of metallization layers and the plurality of semiconducting regions in a direction that is perpendicular to a major surface of the semiconducting substrate;
generating a second thermal gradient in a second thermoelectric generator, the second thermal gradient caused by the first thermal gradient; and
generating a second signal by a second device on a basis of electrical energy produced by the second thermoelectric generator in response to the second thermal gradient, the second signal having a third value or a fourth value, wherein when the first signal has the first value the second signal has the third value, and when the first signal has the second value the second signal has the fourth value.

US Pat. No. 10,249,678

IMAGING DEVICE, METHOD OF DRIVING IMAGING DEVICE, AND IMAGING SYSTEM

CANON KABUSHIKI KAISHA, ...

1. An imaging device comprising:a plurality of pixels, each of the plurality of pixels including a photoelectric converter that generates charges by photoelectric conversion, a holding portion that holds the charges transferred from the photoelectric converter, and an amplifier unit that outputs a signal based on the charges transferred from the holding portion; and
an output line which is connected to the plurality of pixels and to which signals are output from the plurality of pixels,
wherein each of the plurality of pixels is configured to output a signal based on charges generated by the photoelectric converter during an exposure period, the exposure period including
a first period during which the photoelectric converter holds charges generated by the photoelectric converter in the first period and
a second period during which the photoelectric converter or the holding portion holds charges generated by the photoelectric converter in the second period while the holding portion is holding charges generated in the first period, and
wherein each of the plurality of pixels is further configured to reset the holding portion after outputting a signal based on charges held in the holding portion in the first period and before transferring charges generated in the first period from the photoelectric converter to the holding portion.

US Pat. No. 10,249,677

PIXEL HAVING TWO SEMICONDUCTOR LAYERS, IMAGE SENSOR INCLUDING THE PIXEL, AND IMAGE PROCESSING SYSTEM INCLUDING THE IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. An image sensor comprising:a first semiconductor layer having at least one transistor;
a first interlayer insulating layer, disposed on the first semiconductor layer;
a second interlayer insulating layer disposed on the first interlayer insulating layer;
a second semiconductor layer having a photodiode that includes an T-type region and a P-type region, the second semiconductor layer being disposed on the second interlayer insulating layer;
a first conductive plug that penetrates the first interlayer insulating layer and is electrically connected to the first semiconductor layer;
a second conductive plug that penetrates the second interlayer insulating layer and is electrically connected to the second semiconductor layer; and
a conductive pattern between the first and second semiconductor layers,
wherein the first semiconductor layer is electrically connected to the second semiconductor layer by the first conductive plug, the second conductive plug, and the conductive pattern,
wherein the second semiconductor layer further comprises a transfer transistor, and at least a portion of the transfer transistor overlaps the N-type region in a plan view,
wherein the second interlayer insulating layer is disposed between the first interlayer insulating layer and the second semiconductor layer, and is in contact with at least one surface of a gate of the transfer transistor.

US Pat. No. 10,249,676

IMAGE PICKUP APPARATUS

OLYMPUS CORPORATION, Tok...

1. An image pickup apparatus comprising:an image pickup device including a light receiving surface where a light receiving portion is formed, an opposite surface opposing the light receiving surface, and an inclined surface inclined at an acute first angle to the light receiving surface, the image pickup device being provided with a plurality of light receiving surface electrodes electrically connected with the light receiving portion, the plurality of light receiving surface electrodes being formed on the light receiving surface;
a transparent member joined so as to cover the light receiving surface; and
a wiring board including a plurality of second bond electrodes disposed on a main surface,
wherein the transparent member and the plurality of light receiving surface electrodes are extended to an outside of an end side of the inclined surface, and back surfaces of the plurality of light receiving surface electrodes are exposed from a side of the opposite surface,
the image pickup device includes a plurality of extended wiring patterns disposed on the opposite surface, the plurality of extended wiring patterns being electrically connected to respective back surfaces of the plurality of light receiving surface electrodes, the plurality of extended wiring patterns extending from the plurality of light receiving surface electrodes through the inclined surface and to the opposite surface, each of the extended wiring patterns including a first bond electrode on the opposite surface, and
the main surface of the wiring board and the opposite surface of the image pickup device are arranged in parallel, and the first bond electrode and each of the plurality of second bond electrodes are bonded through a bump to electrically connect the first bond electrodes to the second bond electrodes and to mechanically connect the wiring board to the image pickup device.

US Pat. No. 10,249,675

BACKSIDE ILLUMINATED IMAGE SENSOR WITH SELF-ALIGNED METAL PAD STRUCTURES

OmniVision Technolgies, I...

1. An image sensor, comprising:a semiconductor material having a front side and a back side opposite the front side;
a dielectric layer disposed on the front side of the semiconductor material;
a poly layer disposed on the dielectric layer;
an interlayer dielectric material covering both the poly layer and the dielectric layer;
an inter-metal layer disposed on the interlayer dielectric material, wherein a metal interconnect is disposed in the inter-metal layer; and
a contact pad trench extending from the back side of the semiconductor material into the semiconductor material, wherein the contact pad trench comprises:
a contact pad disposed in the contact pad trench, wherein the contact pad and the metal interconnect are coupled with a plurality of contact plugs; and
at least an air gap between the contact pad and side walls of the contact pad trench.

US Pat. No. 10,249,674

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING A SEMICONDUCTOR DEVICE HAVING BONDED SENSOR AND LOGIC SUBSTRATES

Sony Corporation, Tokyo ...

1. A semiconductor device comprising:a sensor substrate including:
a first semiconductor substrate;
a first wiring layer formed at a first main surface side of the first semiconductor substrate;
an insulating material layer formed at a second main surface side of the first semiconductor substrate;
a conductive layer, wherein a portion of the conductive layer is formed on the insulating material layer and has an upper surface side that faces away from the second main surface side of the first semiconductor substrate, and wherein the upper surface side of the portion of the conductive layer includes a concave portion;
a first film formed on the portion of the conductive layer and covering an inner face of the concave portion; and
a second film formed on the first film, wherein at least a portion of the first film and the second film are within the concave portion; and
a logic substrate including:
a second semiconductor substrate; and
a second wiring layer formed at a first main surface side of the second semiconductor substrate,
wherein the sensor substrate and the logic substrate are bonded together such that the first wiring layer faces the second wiring layer, and
wherein the conductive layer electrically connects a first wiring in the first wiring layer and a second wiring in the second wiring layer.