US Pat. No. 10,217,815

INTEGRATED CIRCUIT DEVICE WITH SOURCE/DRAIN BARRIER

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:receiving a workpiece that includes:
a substrate; and
a device fin extending above the substrate, wherein the device fin includes a channel region;
etching a portion of the device fin adjacent the channel region, wherein the etching creates a source/drain recess and forms a dielectric barrier within the source/drain recess;
cleaning the workpiece to remove a first portion of the dielectric barrier from the source/drain recess such that a bottommost portion of the dielectric barrier remains within a bottommost portion of the source/drain recess; and
forming a source/drain feature within the source/drain recess such that the bottommost portion of the dielectric barrier is disposed between the source/drain feature and a remainder of the device fin.

US Pat. No. 10,217,814

SEMICONDUCTOR DEVICE

Nuvoton Technology Corpor...

1. A semiconductor device, comprising:a metal-oxide-semiconductor field-effect transistor (MOSFET), disposed on a substrate, wherein the MOSFET comprises a source region, a drain region, and a gate structure disposed between the source region and the drain region;
a plurality of junction gate field-effect transistors (JFETs) connected in parallel, being connected with the MOSFET in series, wherein each of the JFETs laterally extends between the source region and the drain region; and
a plurality of first isolation structures, respectively disposed among the JFETs, wherein each of the first isolation structures laterally extends between the source region and the drain region.

US Pat. No. 10,217,813

METHOD FOR MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE AND SILICON CARBIDE SEMICONDUCTOR DEVICE

Sumitomo Electric Industr...

1. A silicon carbide semiconductor device comprising:a silicon carbide substrate having a first main surface and a second main surface located on a side opposite to said first main surface;
an epitaxial layer formed on said first main surface, said epitaxial layer having a first conductivity type and having a third main surface located on a side opposite to a side on which said silicon carbide substrate is located;
a trench which is formed in said epitaxial layer and includes side walls intersecting with said third main surface and a bottom portion connected to said side walls; and
an embedded region, which is formed in said trench and has a second conductivity type different from said first conductivity type, said trench being filled with said embedded region;
an opening of said trench being wider than said bottom portion, and said epitaxial layer adjacent to said embedded region and said embedded region constituting a superjunction structure, said silicon carbide semiconductor device further comprising:
an impurity region formed on said embedded region and having said second conductivity type;
a first electrode provided on said impurity region; and
a second electrode in contact with said second main surface.

US Pat. No. 10,217,812

SILICON-ON-INSULATOR CHIP HAVING MULTIPLE CRYSTAL ORIENTATIONS

Infineon Technologies AG,...

1. A silicon-on-insulator device having multiple crystal orientations comprising:a substrate layer;
an insulating layer disposed on the substrate layer;
a first strained silicon layer having a first crystal orientation disposed directly on a portion of the insulating layer;
a strain inducing layer comprising a strained material disposed on another portion of the insulation layer; and
a second strained silicon layer disposed directly on the strain inducing layer so as to be spaced from the insulating layer by the strain inducing layer and having a crystal orientation different from the first crystal orientation.

US Pat. No. 10,217,811

SEMICONDUCTOR DEVICE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVING DEVICE, VEHICLE, AND ELEVATOR

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a silicon carbide layer having a front surface inclined at 0° or more and 10° or less with respect to a (0001) face;
a silicon oxide layer; and
a region located between the front surface and the silicon oxide layer and having the number of carbon-carbon single bonds larger than the number of carbon-carbon double bonds.

US Pat. No. 10,217,810

CAPACITOR FORMED ON HEAVILY DOPED SUBSTRATE

MICROCHIP TECHNOLOGY INCO...

1. A method for manufacturing a capacitor, the method comprising:depositing an oxide layer on a first side of a heavily doped substrate, wherein the oxide layer has a thickness of at least 14 ?m to provide a break down voltage above at least 6 kV;
depositing a first metal layer on the oxide layer; and
depositing a second metal layer on a second side of the heavily doped substrate so that the first metal layer and the second metal layer are physically separated at all points by the oxide layer; and
providing a first electrode connection to the first metal layer on the first side of the substrate and a second electrode connection to the second metal layer on the second side of the substrate.

US Pat. No. 10,217,809

METHOD OF FORMING RESISTORS WITH CONTROLLED RESISTIVITY

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:forming a doped metallic insulator layer having an insulating phase atop a substrate;
performing a controlled surface treatment process to an upper portion of the doped metallic insulator layer to convert the upper portion of the doped metallic insulator layer into an electrical conducting resistive material layer having an electrical conducting phase, the electrical conducting resistive material layer is selected from the group consisting of a metallic nitride, a metallic oxide, and a metallic nitride-oxide;
patterning the doped metallic insulator layer and the electrical conducting resistive material layer to provide a resistor structure comprising a remaining portion of the doped metallic insulator layer and a remaining portion of the electrical conducting resistive material layer; and
forming an interconnect dielectric material on the substrate and the resistor structure.

US Pat. No. 10,217,808

DISPLAY DEVICE

Japan Display Inc., Mina...

1. A display device comprising:an insulating base material;
a metal layer that is provided inside the insulating base material, and is electrically connected to an electric power supply;
an insulating layer that is provided over the insulating base material;
pixels arranged in a matrix form on the insulating layer, each of the pixels including an organic light emitting diode and a pixel circuit connected to the organic light emitting diode;
a power supply line which is arranged on the insulating layer and is connected to the pixels;
a driver integrated circuit connected to the pixels on the insulating layer;
a first through hole which is arranged in the insulating layer and electrically connects the power supply line and the metal layer to each other; and
second through holes which are arranged in the insulating layer and electrically connect the pixels and the metal layer to each other,
wherein the metal layer is arranged directly below the pixels and the power supply line,
wherein the metal layer continuously surrounds a pixel array including the pixels in a planar view, and
wherein the power supply line, the pixels, the second through holes, and the driver integrated circuit are arranged in sequential order.

US Pat. No. 10,217,807

ANISOTROPIC CONDUCTIVE FILM AND DISPLAY DEVICE USING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a substrate;
a display unit over the substrate;
a pad unit over one edge of the substrate and connected to the display unit;
a driving integrated circuit (IC) electrically connected to the pad unit; and
an anisotropic conductive film between the pad unit and the driving IC and electrically connecting the pad unit to the driving IC,
wherein the anisotropic conductive film comprises an adhesive resin insulating portion and a plurality of conductive particles dispersed in the adhesive resin insulating portion, and
wherein each of the plurality of conductive particles comprises a surface having a plurality of needle-shaped protrusions each having a conical shape, wherein some of the plurality of needle-shaped protrusions having the conical shape are stuck to the pad unit,
wherein the pad unit comprises a second layer and a third layer that are sequentially stacked, and
wherein the some of the plurality of needle-shaped protrusions having the conical shape contact the second layer through the third layer.

US Pat. No. 10,217,806

DISPLAY APPARATUS HAVING GROOVED TERMINALS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus, comprising:a display panel comprising a display substrate on which a plurality of pad terminals are disposed; and
a driving unit comprising a plurality of driving terminals electrically connected to the plurality of pad terminals,
wherein each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.

US Pat. No. 10,217,805

DISPLAY APPARATUS

Sony Corporation, Tokyo ...

1. A display apparatus comprising:a plurality of pixels,
wherein each of the pixels includes:
a gate electrode of a driving transistor, a source region of the driving transistor is a portion of a polysilicon layer;
a first electrode of an accumulating capacitor that is physically connected to the gate electrode of the driving transistor, the gate electrode of the driving transistor is a portion of a lower layer and the first electrode of the accumulating capacitor is another portion of the lower layer;
a first electrode of an additional capacitor, a different portion of the lower layer is the first electrode of the additional capacitor;
a second electrode of the additional capacitor, a different portion of the polysilicon layer is the second electrode of the additional capacitor;
a second electrode of the accumulating capacitor that is physically connected to the second electrode of the additional capacitor, another portion of the polysilicon layer is the second electrode of the accumulating capacitor;
an intermediate layer between the lower layer and an upper layer, the intermediate layer is between the upper layer and the polysilicon layer; and
a first contact hole that at least partially overlaps a second contact hole in a plan view of a display panel, the second contact hole in the plan view of the display panel is larger than the first contact hole,
wherein a portion of the upper layer in the first contact hole is physically connected to the portion of the intermediate layer,
wherein the lower layer is a metal and the upper layer is a conductive layer that includes silver, the intermediate layer is a metal layer.

US Pat. No. 10,217,804

DRIVING AND SCANNING CIRCUIT, DISPLAY SCREEN AND MOBILE TERMINAL

HUIZHOU TCL MOBILE COMMUN...

1. A driving and scanning circuit, comprising:a plurality of driving and scanning units which are distributed in an array, wherein each driving and scanning unit comprises an AMOLED driving unit for driving an OLED to emit light and a fingerprint scanning unit for forming pixel capacitances, wherein
the AMOLED driving unit comprises a first thin film transistor, a second thin film transistor, a third thin film transistor and an OLED, the first thin film transistor is connected with a first driving voltage and a first switching voltage, the second thin film transistor and the third thin film transistor are respectively connected with an anode terminal and a cathode terminal, and the OLED is positioned between the cathode terminal and the second thin film transistor;
the cathode terminal comprises a fourth thin film transistor, and the fourth thin film transistor is connected with a second driving voltage and a second switching voltage;
one and only one of the AMOLED driving unit and the fingerprint scanning unit is in a conducting state;
in the fingerprint scanning unit: a gate of the fourth thin film transistor is connected with the second switching voltage, and a source and a drain are respectively connected with the OLED and the second driving voltage; the first switching voltage and the first driving voltage are respectively connected with a first scanning line and a first signal line, and the second switching voltage and the second driving voltage are respectively connected with a second scanning line and a second signal line.

US Pat. No. 10,217,803

ORGANIC LIGHT-EMITTING DISPLAY AND AN ELECTRONIC APPARATUS INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting diode display comprising:a substrate comprising an active area and a dead area surrounding the active area;
a first organic light-emitting device disposed in the active area;
a second organic light-emitting device disposed in the dead area;
a sensor configured to sense light emitted from the second organic light-emitting device,
wherein the first organic light-emitting device emits light in a first direction, and the second organic light-emitting device emits light in a second direction that is opposite to the first direction and is toward the sensor;
an interlayer insulating layer disposed on the substrate; and
an insulating layer disposed on the interlayer insulating layer, wherein one of a first pixel electrode of the first organic light-emitting device or a second pixel electrode of the second organic light-emitting device is disposed between the insulating layer and the interlayer insulating layer, and the other one of the first pixel electrode and the second pixel electrode is not disposed between the insulating layer and the interlayer insulating layer.

US Pat. No. 10,217,802

ORGANIC LIGHT-EMITTING DISPLAY DEVICE WITH HIGH RESOLUTION AND HIGH DEFINITION

LG Display Co., Ltd., Se...

1. An organic light-emitting display (OLED) device comprising:a substrate having a display area including a plurality of sub-pixels each comprising an anode, an organic emitting layer and a cathode;
a first data line disposed on the substrate and configured to apply a first data voltage to a first sub-pixel emitting light of a first color and to a second sub-pixel emitting light of a second color different from the first color; and
a first line disposed between the first data line and an anode overlapping the first data line among the anodes of the plurality of sub-pixels,
wherein the first line is insulated from the first data line.

US Pat. No. 10,217,801

LIGHT-EMITTING STRUCTURE, DISPLAY DEVICE AND LIGHT SOURCE DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A light-emitting structure, comprising:a first light-emitting component and a second light-emitting component that are electrically connected, wherein,
the first light-emitting component comprises a first light-emitting layer and a second light-emitting layer, and the second light-emitting component comprises a third light-emitting layer;
a combination by electrical connection of the first light-emitting component and the second light-emitting component is driven by alternate current (AC) as a whole; the first light-emitting layer and the second light-emitting layer do not emit light at the same time;
the third light-emitting layer is configured to emit light at the same time as the first light-emitting layer and the third light-emitting layer is also configured to emit light at the same time as the second light-emitting layer;
the first light-emitting component further comprises an intermediate electrode; the second light-emitting component further comprises a fourth electrode; the intermediate electrode is connected to the fourth electrode via a second connection electrode, the intermediate electrode is in direct contact with the second connection electrode, and a center line of the second connection electrode, a center line of the intermediate electrode, and a center line of the fourth electrode are substantially on a same straight line.

US Pat. No. 10,217,800

RESISTANCE CHANGE MEMORY DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a resistance change element,
wherein the resistance change element includes:
first and second electrodes spaced apart from each other;
a metal material layer adjacent to the first electrode;
an oxide layer adjacent to each of the metal material layer and the first electrode; and
a resistance change layer disposed continuously between the second and first electrodes and between the second electrode and the oxide layer,
wherein the resistance change layer is made of a metal oxide,
wherein the metal material layer is made of a metal or a metal compound,
wherein the oxide layer is made of an oxide of the material forming the metal material layer,
wherein the first electrode is made of ruthenium, ruthenium oxide, iridium, iridium oxide, platinum, gold, or copper, and
wherein a free energy of oxide formation of the oxide forming the oxide layer is higher than a free energy of oxide formation of the oxide forming the resistance change layer.

US Pat. No. 10,217,799

CELL PILLAR STRUCTURES AND INTEGRATED FLOWS

Micron Technology, Inc., ...

1. An apparatus, comprising:a source material including a transition metal combined with a semiconductor material;
an active switching device;
a memory stack arranged between the source material and the active switching device and having alternating levels of conductive materials and dielectric materials such that each level of conductive material is separated from another level of conductive material by a level of dielectric material, at least some of the conductive materials including a recessed charge storage structure formed substantially within a level of respective ones of the conductive material and separated from adjacent portions of the dielectric material by a charge-blocking dielectric material;
a buffer material formed between a level corresponding to the source material and the memory stack; and
a channel-fill material that is continuous from the source material to a level of the active switching device, the charge storage structures formed laterally away from the channel-fill material.

US Pat. No. 10,217,798

SYSTEMS AND METHODS FOR IMPLEMENTING SELECT DEVICES CONSTRUCTED FROM 2D MATERIALS

Inston, Inc., Santa Moni...

1. A stacked crossbar memory system comprising:a plurality of memory sub-systems and at least one insulation layer, wherein each insulation layer separates two of the plurality of memory sub-systems, wherein each memory sub-system comprises:
a first set of connection lines;
a second set of connection lines; and
an array of memory cells, each memory cell in the array comprising:
a select device; and
a memory device, wherein the memory device is one of: a spin-transfer torque random-access-memory device and a magneto-electric random-access-memory device;
wherein:
each memory cell in the array is coupled to a unique combination of one connection line in the first set of connection lines and one connection line in the second set of connection lines;
at least one of the select devices of the array of memory cells is crystalline; and
at least one of the select devices of the array of memory cells comprises a van der Waals heterostructure and thereby comprises a 2D material.

US Pat. No. 10,217,797

SWITCHING DEVICE, AND RESISTIVE RANDOM ACCESS MEMORY INCLUDING THE SAME AS A SELECTION DEVICE

SK HYNIX INC., Icheon (K...

1. A switching device, comprising:a first electrode, a switching layer having a non-memory characteristic, and a second electrode that are disposed over a substrate,
wherein the switching layer includes an oxide of a first atom or a nitride of the first atom, and a second atom doped in the oxide or the nitride,
wherein the switching layer includes a trap site formed by the second atom,
wherein the trap site traps a conductive carrier in the switching layer when a voltage having an absolute value that is smaller than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes, and
wherein the trap site provides a moving path through which the conductive carrier moves between the first electrode and the second electrode when a voltage having an absolute value that is greater than an absolute value of a predetermined threshold voltage is applied between the first and the second electrodes.

US Pat. No. 10,217,796

SEMICONDUCTOR DEVICE COMPRISING AN OXIDE LAYER AND AN OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode;
a gate insulating film over the gate electrode;
a multilayer film over the gate insulating film, the multilayer film comprising an oxide layer and an oxide semiconductor layer;
a source electrode in contact with a top surface of the oxide layer; and
a drain electrode in contact with the top surface of the oxide layer,
wherein the oxide layer comprises indium and a metal element,
wherein the oxide semiconductor layer comprises indium and the metal element,
wherein an absorption coefficient of the multilayer film measured from a constant photocurrent method is lower than 1×10?3 cm?1, and
wherein the oxide layer has a larger energy gap than the oxide semiconductor layer.

US Pat. No. 10,217,795

MEMORY CELL FOR NON-VOLATILE MEMORY SYSTEM

SanDisk Technologies LLC,...

1. A non-volatile storage apparatus, comprising:a first a reversible resistance-switching structure;
a second a reversible resistance-switching structure; and
a control region comprising a word line layer and an offset layer adjacent to the word line layer, the word line layer on a first side of the control region facing the first reversible resistance-switching structure, the offset layer on a second side of the control region facing the second reversible resistance-switching structure, the offset layer shielding the word line layer from controlling the second reversible resistance-switching structure.

US Pat. No. 10,217,794

INTEGRATED CIRCUITS WITH VERTICAL CAPACITORS AND METHODS FOR PRODUCING THE SAME

GLOBALFOUNDRIES SINGAPORE...

1. An integrated circuit comprising:a capacitor comprising a first capacitor plate and a second capacitor plate, wherein the first capacitor plate comprises a first memory cell, and wherein the second capacitor plate comprises a second memory cell, and wherein the capacitor is utilized within the integrated circuit as a functional capacitor.

US Pat. No. 10,217,793

MASKLESS PARALLEL PICK-AND-PLACE TRANSFER OF MICRO-DEVICES

Applied Materials, Inc., ...

1. An apparatus for positioning micro-devices on a destination substrate, the apparatus comprising:a first support to hold a destination substrate;
a second support to provide or hold a transfer body having a surface to receive an adhesive layer;
one or more actuators configured to provide relative motion between the transfer body and the first support;
a light source to generate a light beam;
a mirror configured to adjustably position the light beam on the adhesive layer on the transfer body; and
a controller configured to
cause the one or more actuators to create relative motion such that a plurality of micro-devices attached to the adhesive layer on the transfer body contact the destination substrate,
cause the light source to generate the light beam and adjust the mirror to position the light beam on the adhesive layer so as to selectively expose one or more portions of the adhesive layer to create one or more neutralized portions, and
cause the one or more actuators to create relative motion such that the transfer body and the destination substrate are moved away from each other and one or more micro-devices corresponding to the one or more neutralized portions of the adhesive layer remain on the destination substrate.

US Pat. No. 10,217,792

METHOD FOR PRODUCING AN OPTOELECTRONIC SEMICONDUCTOR CHIP AND OPTOELECTRONIC SEMICONDUCTOR CHIP

OSRAM OPTO SEMICONDUCTORS...

1. A method for producing an optoelectronic semiconductor chip, comprising the steps:a) Providing a semiconductor layer sequence including a first semiconductor layer and a second semiconductor layer, as well as a first contact layer, which extends laterally along the first semiconductor layer and electrically contacts the same;
b) Applying a third semiconductor layer on a side of the first contact layer facing away from the semiconductor layer sequence;
c) Forming a recess, which extends through the third semiconductor layer, the first contact layer and the first semiconductor layer and into the second semiconductor layer;
d) Applying a passivation layer on a side of the third semiconductor layer facing away from the semiconductor layer sequence;
e) Forming at least a first through-opening and at least a second through-opening in the passivation layer; and
f) Applying a second contact layer, wherein the second contact layer electrically contacts the second semiconductor layer in the region of the at least one first through-opening, and electrically contacts the third semiconductor layer in the region of the at least one second through-opening.

US Pat. No. 10,217,791

METHOD OF MANUFACTURING BONDED SUBSTRATE, BONDED SUBSTRATE, METHOD OF MANUFACTURING SOLID-STATE IMAGING APPARATUS, SOLID-STATE IMAGING APPARATUS, AND CAMERA

Sony Corporation, Tokyo ...

1. A device comprising:a semiconductor layer having an electronic circuit;
a support substrate supporting the semiconductor layer;
a first bonding layer formed on a surface of and in direct physical contact with the semiconductor layer at the support substrate side; and
a second bonding layer formed on a surface of the support substrate at the semiconductor layer side and which is bonded to the first bonding layer,
wherein both the first bonding layer and the second bonding layer have silicon carbonitride, and
a layer having silicon carbonitride formed at a surface of at least a part of at least one of the first bonding layer and the second bonding laver.

US Pat. No. 10,217,790

IMAGING DETECTOR MODULE ASSEMBLY

KONINKLIJKE PHILIPS N.V.,...

1. A module assembly device configured for assembling a module assembly for a detector array of an imaging system, the module assembly including a module substrate, an application-specific integrated circuit (ASIC), a photo-detector array tile, and a scintillator, the module assembly device, comprising:a base having a long axis;
a first surface of the base;
side walls protruding perpendicular up from the first surface and extending in a direction of the long axis along at least two sides of the base, wherein the first surface and side walls form a recess configured to receive the module substrate on the surface and within the side walls; and
protrusions protruding from the side walls in a direction of the side walls, the protrusions and side walls interface forming a ledge which serves as a photo-detector array tile support configured to receive the photo-detector array tile directly over the ASIC and the module substrate.

US Pat. No. 10,217,789

INTERPOSER AND CHIP-SCALE PACKAGING FOR WAFER-LEVEL CAMERA

OmniVision Technologies, ...

1. A chip-scale packaging process for wafer-level camera manufacture, comprising:aligning an optics component wafer with an interposer wafer based on a photoresist pattern disposed on a first side of the interposer wafer;
forming a plurality of holes through the interposer wafer based on the photoresist pattern;
bonding the aligned optics component wafer to the first side of the interposer wafer;
dicing the bonded optics component wafer and interposer wafer into a plurality of optics components with interposers, such that each optics component with interposer includes a transparent region formed by the photoresist pattern;
dicing an image sensor wafer into a plurality of image sensors, wherein each of the plurality of image sensors has a pixel array;
aligning the pixel array of each of the plurality of image sensors with a respective one of the plurality of optics components with interposers based on the transparent region of the optics component with interposer; and
bonding each of the plurality of image sensors to its respective one of the plurality of optics components with interposers, thereby forming a plurality of wafer-level cameras.

US Pat. No. 10,217,788

IMAGING DEVICE

Ricoh Company, Ltd., Tok...

1. An imaging device comprising a plurality of arranged imaging elements,each of the plurality of imaging elements comprising:
a light-receiving element configured to generate charge from received light by photoelectric conversion,
a floating diffusion configured to convert the charge generated by the light-receiving element into voltage,
a charge transfer switch configured to transfer the charge from the light-receiving element to the floating diffusion,
a reset switch configured to reset the voltage of the floating diffusion, and
a source follower configured to amplify the voltage of the floating diffusion,
the reset switch being configured to reset the voltage of the floating diffusion a plurality of times for each of predetermined pixel groups in a single image data acquisition period, and
the charge transfer switch being configured to transfer the charge from the light-receiving element to the floating diffusion a plurality of times for each of the pixel groups in the single image data acquisition period.

US Pat. No. 10,217,787

BACKSIDE ILLUMINATED IMAGE SENSOR AND METHOD OF MANUFACTURING THE SAME

DB Hitek Co., Ltd., Seou...

1. A backside illuminated image sensor comprising:a substrate having a front surface and a back surface;
a photodiode disposed in the substrate;
a first insulating layer disposed on the front surface of the substrate;
a first bonding pad disposed on a front surface of the first insulating layer;
a metal wiring layer disposed on the front surface of the first insulating layer;
a second insulating layer disposed on the front surface of the first insulating layer, the bonding pad and the metal wiring layer, and having an aperture extending from a front surface of the second insulating layer to the first bonding pad, such that a portion of a front surface of the first bonding pad is exposed; and
a second bonding pad disposed in part on the portion of the front surface of the first bonding pad exposed by the aperture of the second insulating layer, and in part on the front surface of second insulating layer,
wherein the substrate and the first insulating layer comprise structures defining an opening that partially exposes a back surface of the first bonding pad, and the first bonding pad comprises the same material as the metal wiring layer.

US Pat. No. 10,217,786

SOLID-STATE IMAGE PICKUP DEVICE

CANON KABUSHIKI KAISHA, ...

1. A member for a device, the device comprising:a first substrate which is provided with a first transistor;
a first structure which is disposed on the first substrate, the first structure including a first portion containing a conductive material and including a first wiring layer arranged between the first portion and the first substrate;
a second substrate provided with a second transistor;
a second structure disposed on the second substrate, the second structure including a second portion containing a conductive material and including a second wiring layer arranged between the second portion and the second substrate,
wherein the first structure and the second structure are arranged between the first substrate and the second substrate so that the first portion and the second portion are connected to each other,
wherein the first structure includes a first insulating film and a second insulating film, the first insulating film is arranged between the second insulating film and the first substrate, a material of the second insulating film is different from a material of the first insulating film, the first wiring layer is arranged between the first insulating film and the first substrate, and the first portion is arranged in a first groove formed of at least the first insulating film and the second insulating film,
wherein the second structure includes a third insulating film, the second wiring layer is arranged between the third insulating film and the second substrate, and the second portion is arranged in a second groove formed of at least the third insulating film, and
wherein the member comprises the first substrate and the first structure, and an upper face of the first structure is formed of the second insulating film and the first portion.

US Pat. No. 10,217,785

SOLID-STATE IMAGING DEVICE, MANUFACTURING METHOD OF SOLID-STATE IMAGING DEVICE, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A solid-state imaging device including:a first substrate having a pixel circuit including a pixel array unit formed thereon;
a second substrate having a plurality of signal processing circuits formed thereon,
wherein the plurality of signal processing circuits are arranged adjacent to one another and include a spacing region therebetween,
wherein the first substrate and the second substrate are stacked,
wherein a first signal processing circuit of the plurality of signal processing circuits and a second signal processing circuit of the plurality of signal processing circuits are electrically connected, and
wherein the first signal processing circuit and the second signal processing circuit are electrically connected through a first wiring layer formed on the second substrate;
a first moisture-resistant structure that surrounds at least a part of a periphery of the first signal processing circuit; and
a second moisture-resistant structure that surrounds at least a part of a periphery of the second signal processing circuit.

US Pat. No. 10,217,784

ISOLATION STRUCTURE AND IMAGE SENSOR HAVING THE SAME

DB Hitek Co., Ltd, Seoul...

1. An image sensor comprising:a deep well region of a first conductive type disposed in a substrate of a second conductive type;
at least two charge accumulation regions of the second conductive type disposed on the deep well region and configured to accumulate photo-charges;
an isolation region of the first conductive type disposed between the at least two charge accumulation regions;
an insulating layer disposed on the isolation region; an electrode disposed on the insulating layer;
a charge pump connected with the electrode to form an electric field in the isolation region so that second photo-charges are accumulated in the isolation region;
a power supply for applying a first voltage to the deep well region to remove the second photo-charges; and
at least two low concentration impurity regions of the second conductive type, each of the at least two low concentration impurity regions being disposed between the at least two charge accumulation regions and the deep well region,
wherein the isolation region is connected with the deep well region to electrically isolate the at least two charge accumulation regions,
the at least two low concentration impurity regions have an impurity concentration lower than an impurity concentration of the at least two charge accumulation regions, and
wherein the at least two charge accumulation regions are p-type impurity regions for accumulating holes, the charge pump applies a second voltage to the electrode to accumulate electrons in the isolation region, and the second voltage is equal to or higher than the first voltage.

US Pat. No. 10,217,783

METHODS FOR FORMING IMAGE SENSORS WITH INTEGRATED BOND PAD STRUCTURES

SEMICONDUCTOR COMPONENTS ...

1. Imaging circuitry, comprising:a substrate;
a first plurality of photodiodes in the substrate;
a second plurality of photodiodes in the substrate;
a light shielding layer on the substrate, wherein the light shielding layer has a shielding portion that covers the first plurality of photodiodes and shields the first plurality of photodiodes from receiving incoming light, wherein the light shielding layer has a grid portion that covers the second plurality of photodiodes, and wherein the second plurality of photodiodes receives incoming light through the grid portion;
a conductive layer over the light shielding layer, wherein a portion of the conductive layer serves as a bond pad region; and
a dielectric layer interposed between the conductive layer and the light shielding layer, wherein the dielectric layer has an opening and the conductive layer and the shielding portion are electrically connected through the opening.

US Pat. No. 10,217,782

IMAGE PICKUP MODULE AND MANUFACTURING METHOD OF IMAGE PICKUP MODULE

OLYMPUS CORPORATION, Tok...

1. An image pickup module comprising:an image pickup device including a light receiving surface where a light receiving portion is formed, an opposite surface opposing the light receiving surface, and an inclined surface inclined at an acute first angle to the light receiving surface, and provided with a plurality of electrode pads lined up on the inclined surface;
a transparent member joined through an adhesive layer so as to cover the light receiving surface of the image pickup device; and
a flexible wiring board arranged on a side of the opposite surface of the image pickup device and provided with a plurality of bond electrodes each bonded with each of the plurality of electrode pads of the image pickup device and lined up in parallel to an end side,
wherein the image pickup module further comprising a holding portion that is a triangular angle regulating portion extended from a side face of the wiring board, an angle of which formed by a first side and a second side is the first angle, and a resin member fixing the opposite surface of the image pickup device and a distal end portion of a main surface of the wiring board, a relative angle of which is regulated to the first angle by the holding portion; and
the holding portion and the wiring board are configured from a same base substance.

US Pat. No. 10,217,781

ONE TRANSISTOR ACTIVE PIXEL SENSOR WITH TUNNEL FET

ECOLE POLYTECHNIQUE FEDER...

1. A tunneling field effect transistor for light detection, comprising:a p-type region connected to a source terminal;
a n-type region connected to a drain terminal;
an intrinsic region located between the p-type region and the n-type region to form a P-I junction and an N-I junction with the p-type region and the n-type region, respectively;
a first insulating layer and a first gate electrode, the first gate electrode covering a portion of the intrinsic region on one side, the first gate configured for applying a gate bias voltage for band-to-band tunneling; and
a second insulating layer and a second gate electrode, the second insulating layer and the second gate electrode covering an entire other side of the intrinsic region opposite to the one side, the second gate electrode configured for generating a potential well in the intrinsic region,
wherein an area of the intrinsic region that is not covered by the first gate electrode forms a non-gated intrinsic area configured for light absorption.

US Pat. No. 10,217,780

SOLID-STATE IMAGING APPARATUS, METHOD FOR MANUFACTURING THE SAME, AND IMAGING SYSTEM

Canon Kabushiki Kaisha, ...

1. A solid-state imaging apparatus comprising:a first semiconductor region of a first conductivity type provided on a substrate;
a second semiconductor region of the first conductivity type provided on the first semiconductor region;
a third semiconductor region of a second conductivity type provided in the second semiconductor region such that a pn junction is formed between the second semiconductor region and the third semiconductor region;
a fourth semiconductor region of the second conductivity type provided on the first semiconductor region; and
a MOS transistor having a source region of the second conductivity type and a drain region of the second conductivity type which are provided in a well of the first conductivity type,
wherein the second semiconductor region and the fourth semiconductor region are arranged in a lateral direction which is perpendicular to a depth direction,
the first semiconductor region includes a first portion and a second portion,
the well, a portion of the fourth semiconductor region which is provided under the well, the first portion of the first semiconductor region and the second portion of the first semiconductor region are arranged in the depth direction in this order toward the substrate, and
an impurity concentration of the first portion of the first semiconductor region is lower than an impurity concentration of the second portion of the first semiconductor region.

US Pat. No. 10,217,779

SYSTEMS AND METHODS FOR IMPROVING A SPECTRAL RESPONSE CURVE OF A PHOTO SENSOR

1. A photo sensor array comprising:a plurality of photodiodes;
a first portion of the plurality of photodiodes having a red filter;
a second portion of the plurality of photodiodes having a green filter;
a third portion of the plurality of photodiodes having a blue filter;
a fourth portion of the plurality of photodiodes having no filter
a fifth portion of the plurality of photodiodes having spectral photo sensors; and
a sixth portion of the plurality of photodiodes having temperature compensation sensors.

US Pat. No. 10,217,778

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method of an array substrate, comprising the following steps:(1) providing a base plate, depositing a common electrode film on the base plate, and depositing a first metal layer on the common electrode film;
(2) applying a first mask-based operation to pattern the common electrode film and the first metal layer so as to form a common electrode and a gate electrode and a common electrode connection line located on the common electrode;
(3) depositing, in sequence from bottom to top, a gate insulation layer, an oxide semiconductor layer film, and a reduction metal layer on the base plate, the common electrode, the gate electrode, and the common electrode connection line;
(4) applying a second mask-based operation to pattern the oxide semiconductor layer film and the reduction metal layer to form a source pattern, a drain pattern, and a pixel electrode pattern, which are to be reduced, and an oxide semiconductor layer,
wherein the oxide semiconductor layer is located on the gate electrode; the source pattern and the drain pattern are arranged, in a manner of being spaced from each other, at two ends of the oxide semiconductor layer and in connection with the oxide semiconductor layer; the drain pattern is in connection with the pixel electrode pattern; and the source pattern, the drain pattern, and the pixel electrode pattern which are to be reduced, each comprise a part of the oxide semiconductor layer film and a part of the reduction metal layer stacked in sequence from bottom to top, wherein the part of the oxide semiconductor layer film entirely corresponds, in size and shape, to the part of the reduction metal layer;
(5) conducting laser annealing on the source pattern, the drain pattern, and the pixel electrode pattern, which are to be reduced, to have the source pattern, the drain pattern, and the pixel electrode pattern reduced to conductors for forming a source electrode, a drain electrode, and a pixel electrode, wherein the part of the oxide semiconductor layer film of each of the source pattern, the drain pattern, and the pixel electrode pattern to be reduced is converted through reduction by the part of the reduction metal layer to which the part of the oxide semiconductor layer film corresponds into the conductor in the form of a single layer corresponding, in size and shape, to the part of the reduction metal layer; and
(6) depositing a passivation layer on the source electrode, the drain electrode, the pixel electrode, the oxide semiconductor layer, and the gate insulation layer to complete manufacturing of the array substrate.

US Pat. No. 10,217,777

DISPLAY DEVICE, SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE

Sony Corporation, Tokyo ...

1. A display device comprising, in this order:a substrate;
a semiconductor film;
a first insulating film;
a first metal film;
a second insulating film;
a second metal film;
a third insulating film;
a third metal film;
a fourth insulating film; and
a pixel electrode film,
wherein a pixel circuit region includes:
(1) a transistor including a first portion of the semiconductor film, a first portion of the first insulating film and a first portion of the first metal film;
(2) a first capacitor including a first portion of the second metal film, a first portion of the third insulating film and a first portion of the third metal film;
(3) a second capacitor including a second portion of the semiconductor film, a second portion of the first insulating film and a second portion of the first metal film; and
(4) a first wiring including a second portion of the second metal film, and the first wiring is electrically connected to the transistor,
wherein the first capacitor overlaps with the second capacitor in a plan view, and
wherein the pixel electrode film is disposed over the first capacitor.

US Pat. No. 10,217,776

SEMICONDUCTOR DEVICE COMPRISING FIRST METAL OXIDE FILM AND SECOND METAL OXIDE FILM

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first insulating film;
a first metal oxide film portion on and in contact with the first insulating film;
a second metal oxide film portion on and in contact with the first insulating film;
a transistor comprising the first metal oxide film portion as a channel formation region; and
a pixel electrode overlapping the second metal oxide film portion,
wherein a second insulating film is on and in direct contact with the second metal oxide film portion and overlaps the first metal oxide film portion,
wherein a third insulating film is interposed between the first metal oxide film portion and the second insulating film and overlaps the second metal oxide film portion, and
wherein a concentration in hydrogen of the second metal oxide film portion is greater than or equal to 8×1019 atoms/cm3.

US Pat. No. 10,217,775

DISPLAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE Technology Group Co.,...

1. A display substrate comprising a display region and a peripheral region, wherein:the peripheral region is provided with a capacitor therein, the capacitor comprises a first electrode and a second electrode with an electrical insulation layer provided therebetween,
the display region is provided with an insulation layer and conductive layers therein, the first electrode and the second electrode are remaining portions of films for forming the conductive layers left in the peripheral region, and the electrical insulation layer is a remaining portion of a film for forming the insulation layer left in the peripheral region,
the first electrode comprises a first transparent conductive layer and a first light shielding conductive layer, and the second electrode comprises a second transparent conductive layer and a second light shielding conductive layer.

US Pat. No. 10,217,774

THIN FILM TRANSISTOR AND MANUFACTURING METHOD THEREOF, ARRAY SUBSTRATE, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. A method of manufacturing a thin film transistor, comprising: forming a gate electrode, an active layer, source/drain electrodes, one or more insulating layers and a pixel electrode on a base substrate,wherein at least one of the insulating layers comprises a silicon oxide sub-layer contacting the active layer and a silicon oxide sub-layer not contacting the active layer, and the silicon oxide sub-layer not contacting the active layer has a hydrogen content higher than that of the silicon oxide sub-layer contacting the active layer, and
wherein the method comprising: depositing the silicon oxide sub-layer contacting the active layer at 200-300° C. with a silane gas flow rate of 300-800 sccm and depositing the silicon oxide sub-layer not contacting the active layer at 240-340° C. with a silane gas flow rate of 600-1200 sccm, in order that the hydrogen content of the silicon oxide sub-layer not contacting the active layer is 5%˜10%, and the hydrogen content of the silicon oxide sub-layer contacting the active layer is 1%˜5%.

US Pat. No. 10,217,773

ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY PANEL AND FABRICATION METHOD THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, whereina passivation layer of the array substrate is made of a black insulation material and the passivation layer is provided with an opening at a pixel display region of the array substrate,
the array substrate comprises a thin film transistor provided below the passivation layer and a pixel electrode provided on the passivation layer,
the passivation layer has a lower surface directly contacting the thin film transistor and an upper surface directly contacting the pixel electrode, and
a thickness of the passivation layer with its lower surface directly contacting the thin film transistor and its upper surface directly contacting the pixel electrode is no less than
where n represents an optical density of the black insulation material with a thickness of 1 micron, and the thickness of the passivation layer with its lower surface directly contacting the thin film transistor and its upper surface directly contacting the pixel electrode is no more than 1 micron.

US Pat. No. 10,217,772

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:a first display element comprising a first electrode, the first display element electrically connected to a first transistor;
a second display element comprising a second electrode, the second display element electrically connected to a second transistor;
a third display element comprising a third electrode, the third display element electrically connected to a third transistor;
a fourth display element comprising a fourth electrode, the fourth display element electrically connected to a fourth transistor;
a first wiring;
a second wiring; and
a third wiring;
wherein the first transistor and the second transistor are along a first direction,
wherein the third transistor and the fourth transistor are along the first direction,
wherein the first transistor and the third transistor are along a second direction perpendicular to the first direction,
wherein the second transistor and the fourth transistor are along the second direction,
wherein the first electrode, the second electrode, the third electrode, and the fourth electrode, are along the second direction,
wherein the first wiring is electrically connected to a gate of the first transistor and a gate of the third transistor,
wherein the second wiring is electrically connected to a gate of the second transistor and a gate of the fourth transistor, and
wherein the third wiring is electrically connected to one of a source and a drain of the first transistor and one of a source and a drain of the fourth transistor.

US Pat. No. 10,217,771

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a gate electrode on the substrate;
a gate insulating layer on the gate electrode;
a semiconductor member including a channel region overlapping the gate electrode with the gate insulating layer interposed therebetween, and a source region and a drain region that face each other with the channel region interposed therebetween;
an interlayer insulating layer on the semiconductor member;
a data conductor on the interlayer insulating layer; and
a passivation layer on the data conductor,
wherein the interlayer insulating layer has a first hole on the channel region, and a second hole on the source region or the drain region,
the first hole and the second hole are separated from each other such that the interlayer insulating layer remains between the first hole and the second hole in a plan view, and
the data conductor is connected to the source region or the drain region via the second hole.

US Pat. No. 10,217,770

PIXEL UNIT, COA SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL HAVING THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A COA substrate, comprising:a substrate;
a scanning line, a data line and a first pixel unit all formed on the substrate, wherein,
the data line is configured to transmit a data signal;
the scanning line is configured to transmit a scanning signal; and
the first pixel unit is configured to display a picture according to the data signal line and comprises:
a thin film transistor configured to control, according to the scanning signal, whether to transmit the data signal to a pixel electrode through a drain of the thin film transistor;
a color resist layer, which has an actual color resist opening and is configured to form a color filter; wherein the actual color resist opening has an opening edge;
a first bridging hole and a second bridging hole adjacent to the first bridging hole for electrical connection;
and the pixel electrode disposed on the color resist layer and electrically connected to the drain of the thin film transistor through one of the first and second bridging holes, the pixel electrode being configured to control corresponding liquid crystal molecules according to the data signal, wherein,
the first bridging hole and the second bridging hole in the first pixel unit are included in the actual color resistor opening; wherein there is a first spacing between a hole edge of the first bridging hole and the opening edge of the actual color resist opening, and there is a second spacing between a hole edge of the second bridging hole and the opening edge of the actual color resist opening; and
a spacing between the hole edge of the first bridging hole and the hole edge of the second bridging hole is less than a sum of the first spacing and the second spacing; wherein
a second pixel unit is further formed on the substrate;
the second pixel unit is configured to display a picture according to the data signal, and the second pixel unit is adjacent to the first pixel unit in a same row and has a third bridging hole; the third bridging hole in the second pixel unit is included in the actual color resist opening and adjacent to the second bridging hole; wherein there is a third spacing between a hole edge of the third bridging hole and the opening edge of the actual color resist opening; and
a spacing between the hole edge of the second bridging hole and the hole edge of the third bridging hole is less than a sum of the second spacing and the third spacing.

US Pat. No. 10,217,769

LIGHT-EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME

Semiconductor Energy Labo...

1. A light-emitting device comprising:an adhesive layer over a flexible substrate;
a transistor over the flexible substrate with the adhesive layer therebetween, wherein the transistor comprises an oxide semiconductor layer, and wherein the oxide semiconductor layer is in contact with a source electrode layer and a drain electrode layer;
a first insulating film over and in contact with the transistor;
a color filter over and in contact with the first insulating film;
a second insulating film over and in contact with the color filter, the second insulating film comprising the same material as the first insulating film;
a partition layer over the second insulating film, the partition layer comprising a tapered surface and an even surface; and
a light-emitting element over the color filter, the light-emitting element comprising a first electrode over the color filter, an EL layer over the partition layer and the first electrode, and a second electrode over the EL layer,
wherein the transistor and the color filter overlap each other in a vertical direction, and
wherein the source electrode layer and the drain electrode layer are in direct contact with the color filter and the second insulating film in an opening of the color filter and an opening of the second insulating film.

US Pat. No. 10,217,768

DISPLAY DEVICE WITH SUPPORT MEMBER HAVING A DENT

Japan Display Inc., Toky...

1. A display device comprising:a plurality of pixels in matrix;
a substrate on which the plurality of pixels are formed; and
a support member under the substrate;
wherein the substrate is arranged on a front surface of the support member; wherein each of the substrate and the support member is formed in substantially rectangular shape and has a first side, a second side, a third side facing to the first side, and a fourth side facing to the second side;
wherein a dent is formed on a rear surface of the support member and covers a whole region of the rear surface; and
wherein a first width of a cross section of the dent gradually becomes thicker in a first direction extending from a first end portion of the substrate corresponding to the first side to a central portion of the substrate, and a second width of the cross section of the dent gradually becomes thicker in a second direction opposite to the first direction extending from a second end portion of the substrate corresponding to the third side to the central portion of the substrate.

US Pat. No. 10,217,767

THIN FILM TRANSISTOR ARRAY PANEL AND MANUFACTURING METHOD THEREOF

SAMSUNG DISPLAY CO., LTD....

1. A thin film transistor array panel comprising:a substrate;
a thin film transistor disposed on a surface of the substrate and including a semiconductor, a source electrode, and a drain electrode that are disposed on a same layer as one another, wherein the semiconductor is between the source electrode and the drain electrode;
a buffer layer disposed between the semiconductor and the substrate and including an inorganic insulating material,
wherein a first edge of the buffer layer is substantially parallel to an adjacent edge of the semiconductor, a second edge of the buffer layer is substantially parallel to an adjacent edge of the source electrode, and a third edge of the buffer layer is substantially parallel to an adjacent edge of the drain electrode;
a light blocking film disposed between the buffer layer and the substrate;
a gate conductor disposed on the substrate;
an interlayer insulating layer disposed on the thin film transistor and including a first contact hole overlapping the drain electrode, a second contact hole overlapping the light blocking film and a third contact hole overlapping the gate conductor, wherein a depth of the third contact hole is substantially the same as a depth of the first contact hole or a depth of the second contact hole.

US Pat. No. 10,217,766

SYSTEM ON CHIP FULLY-DEPLETED SILICON ON INSULATOR WITH RF AND MM-WAVE INTEGRATED FUNCTIONS

International Business Ma...

1. A method for fabricating radio frequency fully depleted silicon on insulator (RF-FDSOI) devices, the method comprising:constructing a silicon wafer for digital circuits using fully depleted silicon on insulator technology having a thin buried oxide layer; and
constructing localized areas of the silicon wafer comprising at least one of radio frequency circuits and passive devices, and further comprising a trap rich layer implanted underneath a thin buried oxide layer.

US Pat. No. 10,217,765

SEMICONDUCTOR INTEGRATED CIRCUIT

FUJI ELECTRIC CO., LTD., ...

1. A semiconductor integrated circuit comprising:a semiconductor layer of a first conductivity type stacked on a support substrate with an insulating layer interposed between the semiconductor layer and the support substrate;
a first well region of a second conductivity type buried in an upper part of the semiconductor layer so as to be separated from the insulating layer;
a second well region of the first conductivity type buried in an upper part of the first well region; and
an isolation region of the first conductivity type buried in the upper part of the semiconductor layer such that the isolation region surrounds the first well region and is separated from the first well region and the insulating layer so that the isolation region does not contact the first well region and does not contact the insulating layer.

US Pat. No. 10,217,764

LIGHT-EMITTING DEVICE AND INPUT/OUTPUT DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:a first substrate;
a transistor over the first substrate;
a first insulating layer over the transistor;
a first conductive layer over the first insulating layer;
a second insulating layer covering an edge portion of the first conductive layer;
a layer comprising an organic compound over the first conductive layer and the second insulating layer;
a second conductive layer over the layer;
a bonding layer over the second conductive layer;
a third conductive layer over and in contact with the bonding layer and the second conductive layer;
a third insulating layer over the third conductive layer;
a fourth conductive layer over the third insulating layer and the third conductive layer; and
a second substrate over the fourth conductive layer,
wherein the bonding layer comprises a resin,
wherein the first conductive layer is electrically connected to the transistor,
wherein the third conductive layer is electrically connected to the fourth conductive layer,
wherein the third insulating layer comprises an opening, and
wherein the fourth conductive layer and the opening of the third insulating layer overlap each other.

US Pat. No. 10,217,763

SEMICONDUCTOR CHIP HAVING REGION INCLUDING GATE ELECTRODE FEATURES OF RECTANGULAR SHAPE ON GATE HORIZONTAL GRID AND FIRST-METAL STRUCTURES OF RECTANGULAR SHAPE ON AT LEAST EIGHT FIRST-METAL GRIDLINES OF FIRST-METAL VERTICAL GRID

Tela Innovations, Inc., ...

1. A semiconductor chip, comprising:gate electrode features formed within a region of the semiconductor chip, the gate electrode features positioned in accordance with a gate horizontal grid that includes at least seven gate gridlines, wherein all gate gridlines extend in a y-direction, wherein adjacent gate gridlines are separated from each other by a gate pitch, each gate electrode feature in the region having a substantially rectangular shape and positioned to extend lengthwise in the y-direction in a substantially centered manner along an associated gate gridline, wherein each gate gridline has at least one gate electrode feature positioned thereon, wherein at least one gate electrode feature within the region forms at least one gate electrode of at least one transistor of a first transistor type and does not form a gate electrode of a transistor of a second transistor type, wherein at least one gate electrode feature within the region forms at least one gate electrode of at least one transistor of the second transistor type and does not form a gate electrode of a transistor of the first transistor type;
at least six gate contact structures formed within the region of the semiconductor chip, wherein at least six gate electrode features within the region have a respective top surface in physical and electrical contact with a corresponding one of the at least six gate contact structures, each of the at least six gate contact structures having a substantially rectangular shape with a corresponding length greater than a corresponding width and with the corresponding length oriented in an x-direction, each of the at least six gate contact structures positioned and sized to overlap both edges of the top surface of the gate electrode feature to which it is in physical and electrical contact; and
a first-metal layer formed above top surfaces of the gate electrode features within the region of the semiconductor chip, the first-metal layer positioned first in a stack of metal layers counting upward from top surfaces of the gate electrode features, the first-metal layer separated from the top surfaces of the gate electrode features by at least one insulator material, wherein the first-metal layer includes first-metal structures positioned in accordance with a first-metal vertical grid, the first-metal vertical grid including at least eight first-metal gridlines, wherein all first-metal gridlines extend in the x-direction, wherein at least eight of the at least eight first-metal gridlines have at least one first-metal structure positioned thereon, each first-metal structure in the region having a substantially rectangular shape and positioned to extend lengthwise in the x-direction in a substantially centered manner on an associated first-metal gridline,
wherein the region includes at least four transistors of the first transistor type and at least four transistors of the second transistor type that collectively form part of a logic circuit, wherein electrical connections within the logic circuit collectively include at least five first-metal structures respectively positioned on at least five different first-metal gridlines,
wherein each transistor within the region of the semiconductor chip is formed in part by a corresponding diffusion region, wherein some diffusion regions within the region of the semiconductor chip are physically and electrically contacted by at least one diffusion contact structure, each diffusion contact structure within the region positioned in a substantially centered manner along an associated diffusion contact gridline of a diffusion contact grid, the diffusion contact grid having a diffusion contact gridline-to-diffusion contact gridline spacing measured in the x-direction equal to the gate pitch.

US Pat. No. 10,217,762

DOPING CHANNELS OF EDGE CELLS TO PROVIDE UNIFORM PROGRAMMING SPEED AND REDUCE READ DISTURB

SanDisk Technologies LLC,...

1. A memory device, comprising:a plurality of word line layers which are vertically spaced apart from one another by dielectric layers in a stack; and
a set of NAND strings extending through the plurality of word line layers, the set of NAND strings are arranged between first and second isolation regions which extend vertically in the stack, the set of NAND strings comprises NAND strings in a first edge region of the stack adjacent to the first isolation region and in a second edge region of the stack adjacent to the second isolation region, and NAND strings in an interior region between the first and second edge regions, the NAND strings in the first and second edge regions comprising doped channels and the NAND strings in the interior region comprising undoped channels.

US Pat. No. 10,217,761

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

MACRONIX International Co...

1. A semiconductor structure for a three-dimensional memory device, comprising:a substrate;
a stacked structure, disposed on the substrate and having a plurality of openings penetrating through the stacked structure and extending into the substrate, wherein the stacked structure comprises a plurality of insulating layers and a plurality of gate layers alternately stacked, each of the plurality of openings comprises a first portion located above a surface of the substrate and a second portion located below the surface of the substrate, and an aspect ratio of the second portion is greater than 1; and
an epitaxial layer, disposed in each of the plurality of openings, wherein a top surface of the epitaxial layer is between a top surface of and a bottom surface of an i-th insulating layer as counted upward from the substrate, and i?2.

US Pat. No. 10,217,760

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor device comprising:interlayer insulating layers and conductive patterns that are alternately stacked;
a channel layer passing through the interlayer insulating layers and the conductive patterns;
cell blocking insulating layers respectively arranged between the channel layer and the conductive patterns, each of the cell blocking insulating layers having a first portion overlapping with the interlayer insulating layers and a second portion closer to a side wall of the channel layer than the first portion, wherein the second portion does not overlap with each of the interlayer insulating layers;
dummy blocking insulating layers respectively arranged between the channel layer and the interlayer insulating layers, each of the dummy blocking insulating layers having a first dummy portion overlapping with the second portion and a second dummy portion closer to the side wall of the channel layer than the first dummy portion, wherein the second dummy portion does not overlap with each of the cell blocking insulating layers; and
a data storage layer surrounding the side wall of the channel layer and formed on a concavo-convex structure defined by the second portion of each of the cell blocking insulating layers and the second dummy portion of each of the dummy blocking insulating layers.

US Pat. No. 10,217,759

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a semiconductor substrate;
a protruding portion which is a portion of the semiconductor substrate, protrudes from an upper surface of the semiconductor substrate, and extends in a first direction along the upper surface of the semiconductor substrate;
a first gate electrode formed over the protruding portion via a first insulating film and extending in a second direction orthogonal to the first direction;
a second gate electrode formed over the protruding portion via a second insulating film including a charge accumulation portion, adjacent to one of side surfaces of the first gate electrode via the second insulating film, and extending in the second direction; and
an n type source region and an n type drain region formed in an upper surface of the protruding portion so as to sandwich, in the first direction, a part of the protruding portion immediately below a pattern having the first gate electrode and the second gate electrode,
wherein the second gate electrode has an upper portion extending across the upper surface of the protruding portion and a lower portion extending along both side surfaces of the protruding portion,
wherein the first gate electrode, the second gate electrode, the source region, and the drain region constitute parts of a nonvolatile memory element, and
wherein an n type impurity concentration of the upper portion of the second gate electrode is lower than an n type impurity concentration of the lower portion of the second gate electrode.

US Pat. No. 10,217,758

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. An electronic device comprising a semiconductor memory, the semiconductor memory comprising:a first channel layer formed over a substrate and extending in a vertical direction;
a first stacked structure comprising a plurality of first interlayer dielectric layers and a plurality of first gate electrode layers which are alternately stacked along the first channel layer;
a first memory layer interposed between the first channel layer and the first gate electrode layers;
a second channel layer formed over the first channel layer and extending in the vertical direction;
a second stacked structure comprising a plurality of second interlayer dielectric layers and a plurality of second gate electrode layers which are alternately stacked along the second channel layer;
a second memory layer interposed between the second channel layer and the second gate electrode layers;
a first channel connection pattern formed between the first channel layer and the second channel layer and coupling the first and the second channel layers to each other; and
a first stop pattern formed between the first and second stacked structures and at the same level as the first channel connection pattern.

US Pat. No. 10,217,757

SEMICONDUCTOR MEMORY DEVICE INCLUDING A SUBSTRATE, VARIOUS INTERCONNECTIONS, SEMICONDUCTOR MEMBER, CHARGE STORAGE MEMBER AND A CONDUCTIVE MEMBER

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a substrate;
a first interconnect provided on one side of the substrate in a first direction;
a second interconnect provided on the one side of the first interconnect;
a plurality of third interconnects extending in a second direction, being arranged to be separated from each other along the first direction, and being provided on the one side of the second interconnect, the second direction crossing the first direction;
a fourth interconnect provided on the one side of the third interconnects;
a semiconductor member extending in the first direction and piercing the plurality of third interconnects, one end portion of the semiconductor member being connected to the second interconnect;
a charge storage member provided between the semiconductor member and one of the plurality of third interconnects; and
a conductive member connected between the first interconnect and the fourth interconnect and insulated from the second interconnect and the plurality of third interconnects,
one of the plurality of third interconnects being disposed on two second-direction sides of the conductive member, and portions of the one of the plurality of third interconnects disposed on the two second-direction sides of the conductive member being formed as one body.

US Pat. No. 10,217,756

METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

United Microelectronics C...

1. A method for fabricating a semiconductor device, comprising:providing a substrate having a logic transistor and a non-volatile memory (NVM) cell thereon; and
forming a contact etching stop layer (CESL), comprising:
forming a first silicon nitride layer on the logic transistor but not on the NVM cell;
forming a silicon oxide layer on the first silicon nitride layer and on the NVM cell; and
forming a second silicon nitride layer on the silicon oxide layer over the logic transistor, and also on the silicon oxide layer on the NVM cell.

US Pat. No. 10,217,755

FLASH MEMORY CELLS, COMPONENTS, AND METHODS

Intel Corporation, Santa...

1. A flash memory component, comprising:a plurality of insulative layers vertically spaced apart from one another;
a vertically oriented conductive channel extending through the plurality of insulative layers;
a charge storage structure disposed between adjacent insulative layers and having a vertical cross section with a first side oriented toward the conductive channel and a second side opposite the first side, wherein a length of the first side is greater than a length of the second side; and
a control gate positioned between the plurality of insulative layers and lateral to the charge storage structure such that the charge storage structure is between the control gate and the conductive channel, wherein no portion of the control gate extends between the insulative layers and the charge storage structure.

US Pat. No. 10,217,754

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

MACRONIX International Co...

1. A memory device, comprising:a substrate, having a first region, a second region, and a third region, wherein the third region is located between the first region and the second region and has a plurality of first self-align trenches;
a first embedded doped region extending along a first direction, and located in a portion of the substrate in a part of the first region, a portion of the substrate in a part of the second region, and a portion of the substrate in a part of the third region;
a second embedded doped region extending along a second direction, located in the substrate at bottoms and around sidewalls of the plurality of first self-align trenches in the third region, the first embedded doped region being electrically connected to the second embedded doped region, and the first direction being different from the second direction;
a plurality of control gates extending along the second direction, located at two sides of the second embedded doped region, and crossed over the first embedded doped region;
a plurality of floating gates, each of the plurality of floating gates being located between an overlapping control gate among the plurality of control gates and the substrate;
a plurality of tunneling dielectric layers, each of the plurality of tunneling dielectric layers being located between an overlapping floating gate among the plurality of floating gates and the substrate;
a plurality of inter-gate dielectric layers, each of the plurality of inter-gate dielectric layers being located between an underlying floating gate among the plurality of floating gates and an overlapping control gate among the plurality of control gates;
a plurality of first doped regions located in the substrate at two sides of each of the control gates in the first region;
a plurality of second doped regions located in the substrate at two sides of each of the control gates in the second region; and
a plurality of third doped regions located in the substrate in the third region, wherein
the first embedded doped region crosses under the plurality of control gates and is in contact with at least two of the plurality of first doped regions, at least two of the plurality of second doped regions and at least two of the plurality of third doped regions, and the second embedded doped region is electrically connected to the plurality of third doped regions.

US Pat. No. 10,217,753

MEMORY CELLS

Micron Technology, Inc., ...

1. A memory cell, comprising:a select device;
a capacitor electrically coupled in series with the select device, the capacitor comprising two conductive capacitor electrodes having ferroelectric material there-between, the capacitor comprising an intrinsic current leakage path from one of the capacitor electrodes to the other through the ferroelectric material; and
a parallel current leakage path from the one capacitor electrode to the other, the parallel current leakage path being circuit-parallel the intrinsic current leakage path and of lower total resistance than the intrinsic current leakage path; the parallel current leakage path comprising one or more of amorphous silicon, germanium, a metal dichalcogenide, silicon-rich silicon nitride, silicon-rich silicon oxide, and intrinsically dielectric material comprising at least one of SiO2 and Si3N4 doped with one or more of Ti, Ta, Nb, Mo, Sr, Y, Cr, Hf, Zr, and lanthanide series ions.

US Pat. No. 10,217,752

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a memory cell comprising a first transistor, a second transistor, and a capacitor,
wherein:
a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor and one electrode of the capacitor,
the first transistor and the second transistor each comprise an oxide semiconductor layer containing indium (In), an element M, and zinc (Zn),
in the first transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by g:h:i (each of g, h, i is a positive number),
in the second transistor, an atomic ratio between In, M, and Zn of the oxide semiconductor layer is represented by d:e:f (each of d, e, f is a positive number), and
g/(g+h+i) is smaller than d/(d+e+f).

US Pat. No. 10,217,751

STATIC RANDOM ACCESS MEMORY DEVICE WITH HALO REGIONS HAVING DIFFERENT IMPURITY CONCENTRATIONS

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing a semiconductor device having a static random access memory, comprising the steps of:defining a first element formation region and a second element formation region by forming an element isolation insulation film on a main surface of a semiconductor substrate, a transistor of first conductivity type being to be formed in said first element formation region, a transistor of second conductivity type being to be formed in said second element formation region;
forming a gate structure, the step of forming said gate structure including a step of forming an access gate structure above a region interposed between a first region and a second region and forming a drive gate structure above a region interposed between a third region and a fourth region in said first element formation region, a first source-drain region electrically connected to a predetermined bit line of a pair of bit lines being to be formed in said first region, a second source-drain region electrically connected to a storage node being to be formed in said second region, said first region and said second region being spaced away from each other, a third source-drain region electrically connected to said storage node being to be formed in said third region, a fourth source-drain region electrically connected to a ground interconnection being to be formed in said fourth region, said third region and said fourth region being spaced away from each other;
forming a first halo implantation mask that exposes a first side surface of said access gate structure at a side of said second region, said second region, said drive gate structure, said third region, and said fourth region, and that covers a second side surface of said access gate structure at a side of said first region, said first region, and said second element formation region;
implanting a first impurity of second conductivity type into the exposed regions of said semiconductor substrate through said first halo implantation mask, at an angle oblique to a direction perpendicular to said main surface;
forming a second halo implantation mask that exposes a first side surface of said drive gate structure at a side of said third region, said third region, said access gate structure, said first region, and said second region, and that covers a second side surface of said drive gate structure at a side of said fourth region, said fourth region, and said second element formation region;
implanting a second impurity of the second conductivity type into the exposed regions of said semiconductor substrate through said second halo implantation mask, at an angle oblique to the direction perpendicular to said main surface; and
forming said first source-drain region, said second source-drain region, said third source-drain region, and said fourth source-drain region by implanting an impurity of first conductivity type,
by forming said first source-drain region to said fourth source-drain region by implanting said first impurity of the second conductivity type and implanting said second impurity of the second conductivity type,
in a region just below said access gate structure, a first halo region having a first impurity concentration and the second conductivity type being formed adjacent to said first source-drain region, a second halo region having a second impurity concentration higher than said first impurity concentration and the second conductivity type being formed adjacent to said second source-drain region,
in a region just below said drive gate structure, a third halo region having a third impurity concentration and the second conductivity type being formed adjacent to said third source-drain region, a fourth halo region having a fourth impurity concentration and the second conductivity type being formed adjacent to said fourth source-drain region, said fourth impurity concentration being lower than said third impurity concentration and different from said first impurity concentration.

US Pat. No. 10,217,750

BURIED WORD LINE STRUCTURE AND METHOD OF MAKING THE SAME

UNITED MICROELECTRONICS C...

1. A buried word line structure, comprising:a substrate;
a word line trench disposed within the substrate, wherein the word line trench comprises:
a first trench comprising an opening and a first sidewall; and
a second trench connecting to the first trench, wherein the second trench comprises a second sidewall and a bottom, a width of the opening is greater than the width of the bottom, the second sidewall comprises an arced corner, and the arced corner connects to the first sidewall;
a silicon oxide layer covering the second trench, wherein a thickness of the silicon oxide layer contacting the arced corner is greater than a thickness of the silicon oxide layer contacting the bottom;
a word line disposed within the second trench;
a cap layer disposed in the first trench; and
two source/drain doped regions in the substrate at two sides of the word line.

US Pat. No. 10,217,749

MANUFACTURING METHOD OF SEMICONDUCTOR MEMORY DEVICE

UNITED MICROELECTRONICS C...

1. A manufacturing method of a semiconductor memory device, comprising:providing a semiconductor substrate having a memory cell region and a peripheral region defined thereon;
forming bit line structures on the memory cell region;
forming at least one gate structure on the peripheral region;
forming a spacer layer covering the semiconductor substrate, the gate structure, and the bit line structures, wherein the spacer layer is partly disposed on the memory cell region and partly disposed on the peripheral region;
performing a first etching process to the spacer layer for removing a part of the spacer layer on the memory cell region, wherein at least a part of the spacer layer remains on the memory cell region after the first etching process; and
performing a second etching process after the first etching process for removing the spacer layer remaining on the memory cell region, wherein the first etching process is different from the second etching process, the first etching process comprises an anisotropic etching process, and the second etching process comprises an isotropic etching process.

US Pat. No. 10,217,748

DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF MANUFACTURING THE SAME

Winbond Electronics Corp....

1. A dynamic random access memory (DRAM) comprising:a bit line located on a substrate;
a capacitor contact aside the bit line, wherein an upper surface of the capacitor contact is higher than an upper surface of the bit line, such that upper sidewalls of the capacitor contact are exposed by the bit line;
a dielectric structure located on the upper surface of the bit line and extending to one portion of the upper sidewalls of the capacitor contact, wherein the dielectric structure comprises a first liner layer being partially removed for defining an opening exposing the upper surface of the capacitor contact;
a capacitor located above and electrically contacted to the capacitor contact; and
a landing pad formed in the opening, wherein the landing pad is located between the capacitor contact and the capacitor to electrically connect the capacitor contact and the capacitor together, the landing pad at least covers one portion of the upper surface of the capacitor contact, wherein a contact area between the landing pad and the capacitor contact is greater than a contact area between the landing pad and the capacitor.

US Pat. No. 10,217,747

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate having a device isolation layer defining an active region;
a first cell gate structure buried in the substrate and crossing the active region in a first direction, the first cell gate structure comprising a gate conductive layer and a capping layer on the gate conductive layer, the active region including a first impurity region and a second impurity region separated from each other by the first cell gate structure therebetween;
a first contact structure connected to the second impurity region,
a capacitor connected to the first contact structure, and
a bit line connected to the first impurity region and extending in a second direction crossing the first direction,
wherein the capping layer includes a recessed portion contacting the first contact structure such that the recessed portion is filled with a portion of the first contact structure,
wherein a topmost surface of the capping layer is lower than a topmost surface of the first contact structure, the recessed portion including a side surface and a bottom surface, the bottom surface of the recessed portion being lower than the topmost surface of the capping layer and contacting the first contact structure, and
wherein the side surface of the recessed portion is disposed between the topmost surface of the capping layer and the bottom surface of the recessed portion.

US Pat. No. 10,217,746

THREE-DIMENSIONAL MEMORY DEVICE HAVING L-SHAPED WORD LINES AND A SUPPORT STRUCTURE AND METHODS OF MAKING THE SAME

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device, comprising:a first alternating stack of first insulating layers and first electrically conductive layers located over a top surface of a substrate, wherein each of the first insulating layers and the first electrically conductive layers includes a respective horizontally-extending portion and a respective non-horizontally-extending portion;
memory stack structures extending through a memory array region of the first alternating stack that includes the horizontally-extending portions of the first electrically conductive layers, wherein each of the memory stack structures comprises a memory film and a vertical semiconductor channel;
a mesa structure located over the substrate, wherein each respective non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers is located over a sidewall of the mesa structure;
contact structures that contact a respective one of the non-horizontally-extending portions of the first electrically conductive layers;
a support structure extending through the first alternating stack; and
metal line structures having a respective first end portion that electrically contacts a respective contact structure and a respective second end portion that electrically contacts a respective contact pad structure;
wherein:
the mesa structure comprises a dielectric sidewall that contacts a sidewall of a non-horizontally-extending portion of a most proximal one of the first insulating layers;
the support structure comprises a support panel structure comprising a first sidewall that contacts a second dielectric sidewall of the mesa structure and sidewalls of the non-horizontally-extending portions of the first electrically conductive layers; and
each non-horizontally-extending portion of the first insulating layers and the first electrically conductive layers has a respective pair of sidewalls that are parallel to the first dielectric sidewall of the mesa structure.

US Pat. No. 10,217,745

HIGH-K GATE DIELECTRIC AND METAL GATE CONDUCTOR STACK FOR FIN-TYPE FIELD EFFECT TRANSISTORS FORMED ON TYPE III-V SEMICONDUCTOR MATERIAL AND SILICON GERMANIUM SEMICONDUCTOR MATERIAL

INTERNATIONAL BUSINESS MA...

1. An electrical device comprising:a first fin structure and a second fin structure of a germanium containing semiconductor material;
an n-type FinFET including a channel region in the first fin structure, the n-type finFET including a n-type work function gate structure including a first interface layer of an aluminum containing dopant at an interface of the channel region, and a first metal work function adjusting layer; and
a p-type FinFET including a channel region in the second fin structure, the p-type finFET including a p-type work function gate structure including a second interface layer including a dopant of a group IIA element, a group IIIB element or a combination thereof at an interface of the channel region, wherein the first interface layer includes oxygen to provide an oxygen source so that the oxygen vacancy concentration in the p-type FinFET is greater than an oxygen vacancy concentration in the n-type FinFET.

US Pat. No. 10,217,743

DETECTING PROCESS VARIATION OF MEMORY CELLS

ARM Limited, Cambridge (...

1. An integrated circuit, comprising:a memory cell array disposed in a first area of the integrated circuit, the memory cell array having memory cells with first transistors of multiple types; and
a process sensor disposed in a second area of the integrated circuit that is different than the first area, the process sensor having a process detector with second transistors of the multiple types that are separate from the first transistors,
wherein the second transistors of the process detector are arranged for detecting process variation of the memory cells of the memory cell array based at least in part on detecting a process point of the memory cells skewing to a process corner of one or more process corners.

US Pat. No. 10,217,742

SEMICONDUCTOR DEVICE HAVING DUMMY ACTIVE FIN PATTERNS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a circuit region and a dummy region adjacent to each other;
circuit active fin patterns in the circuit region and having a linear shape extended in a first direction;
dummy active fin patterns in the dummy region and having a linear shape extended in the first direction, the dummy active fin patterns including first-side fin patterns having end portions opposing end portions of the circuit active fin patterns;
circuit gate lines in the circuit region and intersecting the circuit active fin patterns; and
dummy gate lines in the dummy region and having end portions opposing end portions of the circuit gate lines,
wherein sides of the circuit active fin patterns and sides of the first-side fin patterns are aligned with each other, and
wherein sides of the circuit gate lines and sides of the dummy gate lines are aligned with each other.

US Pat. No. 10,217,741

FIN STRUCTURE AND METHOD OF FORMING SAME THROUGH TWO-STEP ETCHING PROCESSES

Taiwan Semiconductor Manu...

1. A method comprising:in a first etching step, etching a semiconductor substrate to form first recesses in a first device region and second recesses in a second device region simultaneously, wherein a first semiconductor strip is formed between the first recesses, and a second semiconductor strip is formed between the second recesses;
in a second etching step, etching the semiconductor substrate in the second device region to extend the second recesses lower than the first recesses, wherein when the semiconductor substrate in the second device region is etched, portions of the semiconductor substrate on opposite sides of the first semiconductor strip are etched to form a semiconductor base, and wherein a plurality of semiconductor strips comprising the first semiconductor strip are on top of the semiconductor base;
filling the first recesses and the second recesses with a dielectric material to form first isolation regions in the first recesses and second isolation regions in the second recesses;
recessing the first isolation regions and the second isolation regions, wherein portions of the semiconductor substrate in the first device region protrude higher than top surfaces of the first isolation regions to form a first semiconductor fin, and portions of the semiconductor substrate in the second device region protrude higher than top surfaces of the second isolation regions to form a second semiconductor fin; and
wherein after the second etching step, the first semiconductor strip has a first sidewall having a first straight portion close to a bottom of the first semiconductor strip, and the second semiconductor strip has a second sidewall having a second straight portion close to a bottom of the second semiconductor strip, and the first sidewall has a first tilt angle smaller than a second tilt angle of the second sidewall.

US Pat. No. 10,217,740

SEMICONDUCTOR DEVICE AND RADIO FREQUENCY MODULE FORMED ON HIGH RESISTIVITY SUBSTRATE

DB Hitek Co., Ltd, Seoul...

1. A semiconductor device comprising:a high resistivity substrate;
a first deep well region having a first conductive type and arranged within the high resistivity substrate;
a second deep well region having a second conductive type and arranged on the first deep well region;
a first well region having the first conductive type and arranged on the second deep well region;
a transistor arranged on the first well region;
a device isolation region arranged in the high resistivity substrate to surround the first well region and comprising a deep trench device isolation region;
a second well region having the second conductive type and arranged outside the device isolation region; and
a third well region having the first conductive type and arranged outside the second well region,
wherein the second deep well region is arranged wider than the first well region,
the first deep well region is arranged wider than the second deep well region, and
the device isolation region extends through the second deep well region and the first deep well region so as to be deeper than the first deep well region and has a slit to electrically connect the second deep well region with the second well region and the first deep well region with the third well region.

US Pat. No. 10,217,739

BIPOLAR JUNCTION TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

DB Hitek Co., Ltd, Seoul...

1. A bipolar junction transistor comprising:a well region disposed in a substrate;
a plurality of emitter regions disposed on the well region in the substrate;
a plurality of first base regions disposed on the well region in the substrate, each of the plurality of first base regions having a ring shape that surrounds a corresponding emitter region;
a common collector region disposed on the well region in the substrate and comprising an outer portion having a ring shape that surrounds the plurality of first base regions and an inner portion disposed between the plurality of first base regions and connected with the outer portion;
a second base region disposed on the well region in the substrate to be electrically connected with the plurality of first base regions by the well region and having a ring shape that surrounds the common collector region;
a plurality of emitter contact regions disposed on the plurality of emitter regions;
a collector contact region disposed on the collector region; and
a base contact region disposed on the second base region.

US Pat. No. 10,217,738

IGBT SEMICONDUCTOR DEVICE

SMK Corporation, Tokyo (...

16. A semiconductor device comprising:a semiconductor substrate;
a base region formed in the semiconductor substrate on a front surface side thereof;
a singular gate trench extending from a front surface side of the base region and penetrating through the base region;
a singular dummy trench extending from the front surface side of the base region and penetrating through the base region, a portion of the singular dummy trench that extends beyond a back surface of the base region being longer than a portion of the singular gate trench that extends beyond the back surface of the base region; and
a well region formed in the semiconductor substrate on the front surface side thereof, the well region being positioned closer to an edge of the semiconductor substrate than the base region is, wherein
on the front surface side of the semiconductor substrate, an opening width of the singular gate trench is smaller than an opening width of the singular dummy trench, and
the singular dummy trench has a branch portion extending in a direction parallel to an edge of the well region at the front surface of the semiconductor substrate.

US Pat. No. 10,217,737

CASCODE SEMICONDUCTOR DEVICE STRUCTURE AND METHOD THEREFOR

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device comprising:a semiconductor substrate having a first major surface and an opposing second major surface, wherein the semiconductor substrate comprises a first doped region having a first conductivity type adjacent the second major surface;
a heterostructure adjacent the first major surface, wherein the heterostructure comprises:
a channel layer comprising a group III-V material; and
a barrier layer disposed over the channel layer and comprising a group III-V material;
a first electrode disposed proximate to a first portion of the channel layer;
a second electrode disposed proximate to a second portion of the channel layer and spaced apart from the first electrode;
a control electrode disposed between the first electrode and the second electrode;
a first trench electrode extending through the heterostructure into the semiconductor substrate, wherein the first trench electrode is electrically coupled to the first electrode;
a second trench electrode extending through the heterostructure and the semiconductor substrate at least to the first doped region, wherein the second trench electrode electrically connects the control electrode to a third electrode disposed adjacent to the second major surface, and wherein the control electrode is electrically coupled to the third electrode through the semiconductor substrate; and
a rectifier device comprising a second doped region of a second conductivity type opposite to the first conductivity type disposed adjoining the first trench electrode in the semiconductor substrate, wherein:
the rectifier device is electrically coupled to the first trench electrode and electrically coupled to the third electrode, but not electrically coupled to the second electrode;
the rectifier device is configured to provide a current path generally perpendicular to the channel layer; and
the semiconductor device is configured as a two terminal device.

US Pat. No. 10,217,736

SEMICONDUCTOR DEVICE INCLUDING TRANSISTOR AND CAPACITOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:a semiconductor;
a first conductive film and a second conductive film each comprising a region in contact with a top surface and a side surface of the semiconductor;
a first insulating film comprising a region in contact with the top surface and the side surface of the semiconductor;
a third conductive film comprising a region facing the top surface and the side surface of the semiconductor with the first insulating film between the third conductive film and the semiconductor;
a second insulating film which is in contact with the first conductive film and comprises an opening reaching the first conductive film;
a fourth conductive film comprising a first region facing the first conductive film and a second region in contact with a side surface of the opening;
a third insulating film comprising a region facing the first region and the side surface of the opening with the fourth conductive film between the third insulating film and the side surface of the opening; and
a fifth conductive film comprising a region facing the fourth conductive film with the third insulating film between the fifth conductive film and the fourth conductive film;
wherein a part of a top surface of the fourth conductive film is located below a bottom surface of the semiconductor.

US Pat. No. 10,217,735

SEMICONDUCTOR SWITCH DEVICE

NXP B.V., Eindhoven (NL)...

1. A semiconductor switch device comprisinga field effect transistor located on a semiconductor substrate,
wherein the field effect transistor comprises a plurality of gates,
each gate comprising a gate electrode and gate dielectric arranged in a loop on a major surface of the substrate,
wherein the loops formed by the gates are arranged concentrically;
wherein adjacent to each gate is
a source region located adjacent to one of an inner edge or an outer edge of the loop formed by that gate and
a drain region located adjacent to another of said inner edge or said outer edge of the loop formed by that gate;
wherein the field effect transistor includes at least one isolation region arranged in a loop; and
wherein the loop formed by the isolation region is located in between the source or drain region adjacent to the inner edge of one of said gates and the source or drain region adjacent to the outer edge of another of said gates.

US Pat. No. 10,217,734

SEMICONDUCTOR DEVICE

DENSO CORPORATION, Kariy...

1. A semiconductor device comprising:a control unit that controls a potential difference between a first terminal and a second terminal of a switching element to a predetermined clamp voltage, the switching element being connected in series to a load between a power source node having a power source potential and a first reference node having a predetermined reference potential, the first terminal of the switching element being adjacent to the power source node and the second terminal of the switching element being adjacent to the first reference node, the switching element including a control terminal for controlling a current flowing between the first terminal and the second terminal;
a first clamping circuit that is connected between the first terminal and the control terminal, and is energized at a voltage equal to or higher than a first clamp voltage;
a second clamping circuit that is connected between the control terminal and a second reference node having a reference potential of the control unit, and clamps the potential difference to a second clamp voltage lower than the first clamp voltage by charging or discharging charges of the control terminal; and
a third clamping circuit that is connected between the control terminal and the second terminal, and discharges the charges of the control terminal, wherein
the control unit includes a current detector that detects a load current flowing in the load, and
the control unit activates the second clamping circuit when the load current is equal to or greater than a predetermined threshold, and activates the third clamping circuit when a predetermined time period elapses after the second clamping circuit is activated.

US Pat. No. 10,217,733

FAST SCR STRUCTURE FOR ESD PROTECTION

SEMICONDUCTOR COMPONENTS ...

1. A semiconductor device for protection against electrostatic discharge (ESD), the device comprising:a substrate, the substrate being a semiconductor of a first conductivity type;
a lightly-doped epitaxial layer on the substrate with an intervening heavily-doped buried layer in at least one region, the epitaxial layer and buried layer having a second conductivity type different than the first; and
a semiconductor-controlled rectifier (SCR) structure within said at least one region, the SCR structure including, between a ground terminal and a pad terminal:
a first shallow region heavily-doped to be of the first conductivity type within a first well moderately-doped to be of the second conductivity type, the first shallow region and first well forming an emitter-base junction of a trigger transistor;
a second shallow region heavily-doped to be of the second conductivity type within a second well moderately-doped to be of the first conductivity type, the second shallow region and second well forming an emitter-base junction of a latching transistor, wherein the first and second wells are separated by a lightly-doped portion of the epitaxial layer;
a PN junction coupled to either the first or second shallow region as a series diode that is forward-biased for current flow from the pad terminal to the ground terminal to increase a holding voltage of the SCR structure; and
a third well moderately-doped to be of the first conductivity type, the third well interposed between the second well and the lightly-doped portion of the epitaxial layer to enhance a holding current of the device.

US Pat. No. 10,217,732

TECHNIQUES FOR FORMING A COMPACTED ARRAY OF FUNCTIONAL CELLS

INTEL CORPORATION, Santa...

1. An integrated circuit comprising:a substrate;
a grid including diffusion lines extending from the substrate: and
an array of functional cells including two adjacent cells, the two adjacent cells at least in part on at least three diffusion lines included in the grid, each cell having a boundary with no diffusion lines between the boundaries of the two adjacent cells, such that one of the two adjacent cells includes two or more of the at least three diffusion lines and the other of the two adjacent cells includes one or more of the at least three diffusion lines;
wherein a distance between the boundaries of the two adjacent cells is less than 50 nanometers (nm).

US Pat. No. 10,217,731

METHOD OF PRODUCING OPTOELECTRONIC MODULES AND AN ASSEMBLY HAVING A MODULE

OSRAM Opto Semiconductors...

1. A method of producing a plurality of optoelectronic modules comprising:A) providing a metal carrier composite having a plurality of carrier units,
B) applying at least one logic chip each having at least one integrated circuit to the carrier units,
C) attaching a plurality of light-emitting diode chips comprising in each case multiple emitter regions individually electrically-controllable, which are based on a semiconductor material and configured to generate radiation and can be controlled individually, to the logic chips attached to the carrier units,
D) covering the emitter regions and the logic chips with a protective material so that upper sides of at least one of the emitter regions and the logic chips facing away from the carrier units are covered by the protective material,
E) molding around the emitter regions and the logic chips so that a cast body is produced, which connects at least the carrier units and the logic chips with one another,
F) removing the protective material and applying electrical conductor paths at least to the upper sides of the logic chips and to a cast body upper side of the cast body facing away from the carrier units, and
G) severing the carrier assembly into the modules, wherein the carrier units as a whole or at least carrier isles on which the emitter regions and the logic chip are located do not have any electrical function in the finished module, and electrically controlling the emitter regions is effected exclusively via the logic chip of the respective module.

US Pat. No. 10,217,730

EFFICIENTLY MICRO-TRANSFER PRINTING MICRO-SCALE DEVICES ONTO LARGE-FORMAT SUBSTRATES

X-Celeprint Limited, Cor...

1. A method of making a micro-transfer printed system, comprising:providing a source wafer having a plurality of micro-transfer printable source devices arranged in or on the source wafer at a source spatial density;
providing an intermediate wafer having a plurality of micro-transfer printable intermediate supports arranged in or on the intermediate wafer at an intermediate spatial density less than or equal to the source spatial density;
providing a destination substrate;
micro-transfer printing the source devices from the source wafer to the intermediate supports of the intermediate wafer with a source stamp having a plurality of stamp posts at a source transfer density to make an intermediate device on each intermediate support; and
micro-transfer printing the intermediate devices from the intermediate wafer to the destination substrate at a destination spatial density less than the source spatial density with an intermediate stamp having a plurality of stamp posts at an intermediate transfer density less than the source transfer density.

US Pat. No. 10,217,729

APPARATUS FOR MICRO PICK AND BOND

Intel Corporation, Santa...

1. A method of transferring micro light emitting diodes (LEDs), comprising:aligning a donor substrate with a macro transfer head, wherein the donor substrate includes a plurality of micro LEDs, and wherein the macro transfer head includes a plurality of micro transfer heads;
moving the donor substrate towards the macro transfer head so that the plurality of micro LEDs each contact one of the micro transfer heads, wherein the micro transfer heads each secure one of the micro LEDs;
removing the micro LEDs from the donor substrate by moving the donor substrate away from the macro transfer head;
aligning a host substrate with the macro transfer head;
moving the host substrate towards the macro transfer head so that the plurality of micro LEDs contact the host substrate; and
bonding the micro LEDs to the host substrate; wherein the macro transfer head is substantially stationary during the transfer process.

US Pat. No. 10,217,728

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a first semiconductor die;
a first encapsulant enclosing the first semiconductor die and having a top surface and a lateral surface;
a first redistribution layer disposed on the top surface of the first encapsulant and electrically connected to the first semiconductor die, wherein a portion of the first redistribution layer is exposed from the lateral surface of the first encapsulant;
a second encapsulant covering the first encapsulant and the first redistribution layer; and
a patterned conductive layer disposed on at least one of the lateral surface of the first encapsulant or a lateral surface of the second encapsulant, wherein the patterned conductive layer is electrically connected to the first redistribution layer and comprises a plurality of bonding pads.

US Pat. No. 10,217,727

SEMICONDUCTOR DEVICE AND ELECTRONIC APPARATUS INCLUDING A FIRST SEMICONDUCTOR CHIP INCLUDING AN INSULATED GATE BIPOLAR TRANSISTOR AND A SECOND SEMICONDUCTOR CHIP INCLUDING A DIODE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a first semiconductor chip including an insulated gate bipolar transistor, a first front surface in which an emitter electrode pad is formed, and a first back surface in which a collector electrode is formed and which is a surface opposite to the first front surface;
a second semiconductor chip including a diode, a second front surface in which an anode electrode pad is formed and a second back surface in which a cathode electrode is formed and which is a surface opposite to the second front surface;
a first chip mounting portion including a first upper surface on which the first semiconductor chip is mounted and which is electrically connected to the first back surface of the first semiconductor chip, and a first lower surface which is a surface opposite to the first upper surface;
a second chip mounting portion including a second upper surface on which the second semiconductor chip is mounted and which is electrically connected to the second hack surface of the second semiconductor chip, and a second lower surface which is a surface opposite to the second upper surface;
a first lead electrically connected to the emitter electrode pad of the first semiconductor chip via a first conductive member;
a second lead electrically connected to the anode electrode pad of the second semiconductor chip via a second conductive member; and
a sealing material including a first main surface which includes a first side and a second side opposite to the first side, and a second main surface which is a surface opposite to the first main surface, the sealing material sealing the first semiconductor chip, the second semiconductor chip, a part of the first chip mounting portion, a part of the second chip mounting portion, a part of the first lead, and a part of the second lead,
wherein the first lower surface of the first chip mounting portion and the second lower surface of the second chip mounting portion are exposed from the second main surface of the sealing material,
wherein the first lead and the second lead are arranged so as to line along the first side of the sealing material extending in a first direction in a plan view,
wherein the first chip mounting portion is electrically separated from the second chip mounting portion,
wherein the first conductive member is electrically separated from the second conductive member,
wherein the emitter electrode pad, of the insulated gate bipolar transistor is electrically isolated from the anode electrode pad of the diode, and
wherein the collector electrode of the insulated gate bipolar transistor is electrically isolated from the cathode electrode of the diode.

US Pat. No. 10,217,726

STACKED SEMICONDUCTOR DIES INCLUDING INDUCTORS AND ASSOCIATED METHODS

Micron Technology, Inc., ...

1. A semiconductor device comprising:a package substrate having an upper surface and a lower surface;
a stack of dies attached to the upper surface of the substrate, wherein the stack includes—
a first die including a front side and one or more first inductors at the front side; and
a second die disposed over and offset from the first die, the second die including a front side facing the first die and one or more second inductors at the front side of the second die, wherein one or more of the second inductors are inductively coupled to one or more of the first inductors;
a first plurality of wirebonds electrically coupling a first plurality of substrate bond pads on the upper surface of the substrate to a first plurality of die bond pads on the front side of the first die;
a second plurality of wirebonds electrically coupling a second plurality of substrate bond pads on the lower surface of the substrate to a second plurality of die bond pads on the front side of the second die; and
a mold material encapsulating at least a portion of the stack and the substrate, wherein the mold material covers only a portion of each of the second plurality of wirebonds.

US Pat. No. 10,217,725

MICROSTRUCTURE MODULATION FOR METAL WAFER-WAFER BONDING

International Business Ma...

1. A three-dimensional (3D) bonded semiconductor structure comprising:a first structure comprising a first semiconductor wafer, a first interconnect structure, a first bonding oxide layer, and at least one first metallic bonding structure embedded in the first bonding oxide layer; and
a second semiconductor structure comprising a second semiconductor wafer, a second interconnect structure, a second bonding oxide layer, and at least one second metallic bonding structure embedded in the second bonding oxide layer, wherein each of the first and second metallic bonding structures has a columnar grain microstructure, and wherein a bonding interface is present between the first and second bonding oxide layers and another bonding interface is present between the at least one first and second metallic bonding structures, wherein at least one columnar grain extends across the another bonding interface that is present between the first and second metallic bonding structures.

US Pat. No. 10,217,724

SEMICONDUCTOR PACKAGE ASSEMBLY WITH EMBEDDED IPD

MediaTek Inc., Hsin-Chu ...

1. A semiconductor package assembly, comprising:a first semiconductor package, comprising:
a first redistribution layer (RDL) structure having a first surface and a second surface opposite thereto;
a first semiconductor die disposed on the first surface of the first RDL structure;
a first molding compound disposed on the first surface of the first RDL structure and surrounding the first semiconductor die; and
an integrated passive device (IPD) embedded in the first RDL structure, wherein:
the IPD is electrically coupled to the first semiconductor die located above the IPD through the first RDL structure,
the IPD comprises first and second electrode layers disposed respectively at least on first and second portions of a lower surface of a body of the IPD, and
the first electrode layer of the IPD is electrically coupled to a first conductive trace of the first RDL structure and the second electrode layer of the IPD is electrically coupled to a second conductive trace of the first RDL structure, the first and second conductive traces being located below the body of the IPD.

US Pat. No. 10,217,723

SEMICONDUCTOR PACKAGE WITH IMPROVED BANDWIDTH

MEDIATEK INC., Hsin-Chu ...

1. A semiconductor chip package, comprising:a first semiconductor die and a second semiconductor die, wherein the first semiconductor die and second semiconductor die are coplanar and disposed in proximity to each other in a side-by-side fashion;
a non-straight line shaped interface gap between the first semiconductor die and second semiconductor die;
a molding compound surrounding the first semiconductor die and second semiconductor die; and
a redistribution layer (RDL) structure on the first semiconductor die, the second semiconductor die and on the molding compound, wherein the first semiconductor die is electrically connected to the second semiconductor die through the RDL structure.

US Pat. No. 10,217,722

SEMICONDUCTOR PACKAGES HAVING ASYMMETRIC CHIP STACK STRUCTURE

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first sub-chip stack including first sub-chips which are stacked on a package substrate and offset in a first offset direction;
a second sub-chip stack including second sub-chips which are stacked on the first sub-chip stack, wherein each of the second sub-chips has a thickness which is different than a thickness of each of the first sub-chips;
a first chip stack including the first sub-chip stack, the second sub-chip stack, and a first spacer between the first and second sub-chip stacks; and
a second chip stack disposed on the package substrate,
wherein a first protrusion corner of the first chip stack protruding toward the second chip stack vertically overlaps with a second protrusion corner of the second chip stack protruding toward the first chip stack.

US Pat. No. 10,217,721

DUAL-SIDED MEMORY MODULE WITH CHANNELS ALIGNED IN OPPOSITION

Apple Inc., Cupertino, C...

1. A memory module comprising:a circuit board;
at least four first packages mounted on a first side of the circuit board, each first package including a separate single channel and four ranks; and
at least four second packages mounted on a second side of the circuit board directly opposite the four first packages, each second package including separate single channel and four ranks;
wherein the circuit board further comprises four package area interconnects electrically connecting the four first packages to the four second packages, each of the package area interconnects comprising:
a first plurality of interconnects electrically connecting power landing pads on the first side of the circuit board to power landing pads on the second side of the circuit board; and
a second plurality of interconnects electrically connecting power and signal landing pads on the first side of the circuit board to power and signal landing pads on the second side of the circuit board;
wherein the second plurality of interconnects is greater than the first plurality of interconnects.

US Pat. No. 10,217,720

MULTI-CHIP MODULES FORMED USING WAFER-LEVEL PROCESSING OF A RECONSTITUTE WAFER

Invensas Corporation, Sa...

1. An apparatus for a microelectronic device, comprising:a first integrated circuit die having first contacts on a die surface thereof in a molding layer of a reconstituted wafer having a wafer surface including a layer surface of the molding layer and the die surface of the first integrated circuit die;
a redistribution layer on the wafer surface including electrically conductive layers and dielectric layers to provide conductive routing and shortest path vertically oriented conductors, the conductors extending away from the die surface of the first integrated circuit die and respectively coupled to the first contacts at bottom ends of the conductors;
at least second and third integrated circuit dies respectively having second contacts on die surfaces thereof interconnected to the first integrated circuit die through the conductors of the redistribution layer;
a first portion of the second contacts of each of the at least second and third integrated circuit dies interconnected to top ends of the conductors opposite the bottom ends thereof, the top ends of the conductors in part for alignment of the at least second and third integrated circuit dies to the first integrated circuit die located below the redistribution layer; and
a second portion of the second contacts interconnected to one another through the conductive routing.

US Pat. No. 10,217,719

SEMICONDUCTOR DEVICE ASSEMBLIES WITH MOLDED SUPPORT SUBSTRATES

Micron Technology, Inc., ...

1. A semiconductor device assembly, comprising:a support substrate formed from a molded material, wherein the support substrate includes a first side and a second side opposite the first side;
a first semiconductor die at least partially embedded within the support substrate;
a plurality of interconnects extending at least partially through the molded material;
a second semiconductor die coupled to the first side of the support substrate;
a third semiconductor die coupled to the first side of the support substrate; and
a plurality of conductive contacts at the second side of the support substrate, wherein the conductive contacts are operably coupled to at least one of the first, second and third semiconductor dies via the plurality of interconnects,
wherein the first semiconductor die is an interface die including a communication component, the second semiconductor die includes a memory controller, and the third semiconductor die includes a memory circuit.

US Pat. No. 10,217,718

METHOD FOR WAFER-LEVEL SEMICONDUCTOR DIE ATTACHMENT

DenseLight Semiconductors...

1. A wafer-level semiconductor die attachment method, comprising:placing a first semiconductor die of a plurality of semiconductor dies at an initial placement position to overlap a first portion of a sub-mount pad on a first sub-mount of a plurality of sub-mounts of a pre-singulated wafer, wherein a die pad of the first semiconductor die is in contact with a first portion of a solder layer deposited over the sub-mount pad, and wherein the first semiconductor die includes a first plurality of die mating features, and the first sub-mount includes a first plurality of sub-mount mating features;
heating the first portion of the solder layer that is in contact with the die pad of the first semiconductor die to temporarily hold the first semiconductor die at the initial placement position; and
reflowing the pre-singulated wafer,
whereby the first semiconductor die slides from the initial placement position to a final placement position, and a contact is established between the first plurality of die mating features and the corresponding first plurality of sub-mount mating features, and whereby the first semiconductor die is permanently attached to the first sub-mount at the final placement position.

US Pat. No. 10,217,717

DISTRIBUTION OF ELECTRONIC CIRCUIT POWER SUPPLY POTENTIALS

STMicroelectronics (Rouss...

1. An integrated circuit, comprising:a first peripheral conductive pad located adjacent a first edge of an integrated circuit chip;
a second peripheral conductive pad located adjacent a second edge of the integrated circuit chip, said second edge being opposite from the first edge;
wherein the first and second peripheral conductive pads are interconnected by a first peripheral conductive track within the integrated circuit chip;
a first conductive wire external to the integrated circuit chip, said first conductive wire having a first end in direct contact with the first peripheral conductive pad and having a second end in direct contact with the second peripheral conductive pad;
a package encapsulating the integrated circuit chip and said first conductive wire, wherein said package includes an external terminal; and
a further conductive wire having a first end in direct contact with said external terminal and having a second end in direct contact with a third peripheral conductive pad, said third peripheral conductive pad being connected to the first peripheral conductive track; and
said package further encapsulating the further conductive wire.

US Pat. No. 10,217,716

SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME

MEDIATEK INC., Hsin-Chu ...

1. A semiconductor package, comprising:a redistribution layer (RDL) structure having opposite first and second surfaces, wherein the RDL structure comprises at least a bump pad on the first surface;
a semiconductor die mounted on the first surface of the RDL structure, wherein the semiconductor die is a flip-chip with its active surface facing toward the RDL structure, wherein a plurality of input/output (I/O) pads is disposed on the active surface of the semiconductor die, and wherein a connecting element is disposed on each of the I/O pads, and wherein the connecting element is connected to the bump pad;
a passive device mounted on the first surface of the RDL structure, wherein the passive device is spaced apart from the semiconductor die;
a molding compound encapsulating the semiconductor die and covering the first surface of the RDL structure; and
a plurality of conductive structure mounted on the second surface of the RDL structure.

US Pat. No. 10,217,715

SEMICONDUCTOR DEVICE WITH A BUMP CONTACT ON A TSV COMPRISING A CAVITY AND METHOD OF PRODUCING SUCH A SEMICONDUCTOR DEVICE

ams AG, Unterpremstaette...

1. A semiconductor device comprising:a semiconductor substrate having a main surface and a further main surface opposite the main surface;
a TSV penetrating the substrate from the main surface to the further main surface;
a cavity of the TSV;
an under-bump metallization arranged adjacent to the cavity at the further main surface;
a bump contact arranged on the under-bump metallization, the bump contact covering the cavity at least partially;
a metallization of the TSV being arranged between the substrate and the cavity;
an opening of the cavity at the main surface or at the further main surface, the opening providing a communication between the cavity and an environment;
a cover layer being arranged above the TSV at the main surface; and
a hole in the cover layer, the opening being provided by the hole.

US Pat. No. 10,217,713

SEMICONDUCTOR DEVICE ATTACHED TO AN EXPOSED PAD

NXP USA, Inc., Austin, T...

1. A packaged semiconductor device comprising:a die having an active surface and a backside surface opposite the active surface;
an exposed pad of a lead frame; and
a die attach material layer between the backside surface of the die and the exposed pad,
wherein
a first surface of the exposed pad is joined to the die attach material layer,
the die attach material layer is further joined to the backside surface of the die,
the exposed pad comprises a plurality of openings through the exposed pad within a perimeter of the die,
the backside surface of the die is exposed through the plurality of openings and through the die attach material layer,
the die comprises a plurality of recesses on the backside surface of the die,
the plurality of recesses are aligned with the plurality of openings,
each of the plurality of recesses includes a solderable surface of the die, and
solderable surfaces of the plurality of recesses are exposed through the plurality of openings and through the die attach material layer.

US Pat. No. 10,217,712

SEMICONDUCTOR PACKAGE AND SEMICONDUCTOR PROCESS FOR MANUFACTURING THE SAME

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a substrate including at least one first pad;
a dielectric layer disposed on the substrate and defining at least one through hole corresponding to the at least one first pad, the dielectric layer having a top surface and a bottom surface opposite to the top surface;
at least one conductive pillar disposed in the at least one through hole, the at least one conductive pillar including a body portion and a cap portion, such that a gap is defined between a sidewall of the at least one through hole and the conductive pillar, and the cap portion is located between the top surface of the dielectric layer and the bottom surface of the dielectric layer; and
an electrical device disposed on the dielectric layer and electrically connected to the body portion of the at least one conductive pillar;
wherein the body portion is physically connected to the cap portion, the cap portion is electrically connected to the at least one first pad, the cap portion is located between the body portion and the first pad, and a maximum width of the cap portion is greater than a maximum width of the body portion.

US Pat. No. 10,217,711

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

Samsung Electro-Mechanics...

1. A semiconductor package, comprising:a substrate;
a ground electrode disposed on an upper surface of the substrate;
at least one electronic component disposed on the upper surface of the substrate;
an internal sealing member sealing the electronic component; and
a shielding member surrounding the electronic component and disposed in an external sealing member,
wherein the shielding member separates the internal sealing member from the external sealing member.

US Pat. No. 10,217,710

WIRING BOARD WITH EMBEDDED COMPONENT AND INTEGRATED STIFFENER, METHOD OF MAKING THE SAME AND FACE-TO-FACE SEMICONDUCTOR ASSEMBLY USING THE SAME

BRIDGE SEMICONDUCTOR CORP...

1. A wiring board, comprising:an electronic component that includes a first semiconductor device having an active surface, an encapsulant, an array of vertical connecting elements each having a first end and a second end, a first routing circuitry and a second routing circuitry, wherein (i) the encapsulant laterally covers the first semiconductor device and the vertical connecting elements and has a first surface facing the first routing circuitry and a second surface opposite to the first surface, (ii) the first routing circuitry extends over the first surface of the encapsulant, the active surface of the first semiconductor device, and the first ends of the vertical connecting elements, thereby electrically coupling the first semiconductor device and the vertical connecting elements to the first routing circuitry, and (iii) the second routing circuitry is disposed on the second surface of the encapsulant and on the second ends of the vertical connecting elements so that the second routing circuitry is electrically connected to the first routing circuitry through the vertical connecting elements;
a stiffener that laterally surrounds the electronic component and has an interior sidewall surface adjacent to peripheral edges of the electronic component; and
a third routing circuitry that is disposed over the second routing circuitry and laterally extends over the stiffener, wherein the third routing circuitry is electrically coupled to the second routing circuitry.

US Pat. No. 10,217,708

HIGH BANDWIDTH ROUTING FOR DIE TO DIE INTERPOSER AND ON-CHIP APPLICATIONS

Apple Inc., Cupertino, C...

1. A routing structure comprising:a first die area;
a second die area;
a signal routing connecting the first die area and the second die area, wherein the signal routing comprises:
a first group of stacked reference lines in a corresponding plurality of metal layers;
a second group of stacked reference lines in the corresponding plurality of metal layers;
a group of stacked trace lines horizontally between the first and second groups of stacked reference lines in the corresponding plurality of metal layers; and
a plurality of inter-layer switch regions and intra-layer switch regions interconnecting the group of stacked trace lines to form a bundle of twisted signal lines with corresponding signal paths that periodically change between the plurality of metal layers.

US Pat. No. 10,217,707

TRENCH CONTACT RESISTANCE REDUCTION

International Business Ma...

1. A method of forming a semiconductor device, the method comprising:forming a source/drain over a semiconductor substrate;
epitaxially growing a single sacrificial layer directly in contact with only the source/drain to protect the source/drain from subsequent etches;
forming an inter-level dielectric (ILD) layer contacting the single sacrificial layer;
forming a first portion of trenches that extend through the ILD layer at an oblique angle with respect to the semiconductor substrate, and into a first section of the single sacrificial layer such that the single sacrificial layer remains in contact with an entire upper surface of the source/drain;
removing a second section of the single sacrificial layer to expose the entire upper surface of the source/drain and to create a second portion of the trenches which extends laterally beyond sidewalls of the first portion of the trenches; and
filling the first and second portions of the trenches with a plurality of conducting materials extending laterally over all the exposed portions of the source/drain.

US Pat. No. 10,217,706

SEMICONDUCTOR CONSTRUCTIONS

Micron Technology, Inc., ...

1. A semiconductor construction comprising a pair of adjacent electrically conductive lines, the pair of adjacent lines being substantially parallel to one another except in a region where the lines merge into one another; the pair of lines curving inward toward one another in the region where the lines merge, each of the lines being collinear on either side of the region where the lines merge.

US Pat. No. 10,217,705

SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A semiconductor device, comprising:a first conductive element;
a first insulating layer and a second insulating layer sequentially stacked on the first conductive element;
a conductive via in the first insulating layer and the second insulating layer, wherein the conductive via is connected to the first conductive element;
a via extension portion in the second insulating layer, the via extension portion extending along an upper surface of the first insulating layer from one side surface of the conductive via; and
a second conductive element on the second insulating layer, wherein the second conductive element is connected to the via extension portion.

US Pat. No. 10,217,704

METHOD FOR SIMULTANEOUS MODIFICATION OF MULTIPLE SEMICONDUCTOR DEVICE FEATURES

1. A method, comprising:simultaneously modifying a plurality of features of a previously manufactured semiconductor device, wherein the semiconductor device comprises a plurality of layers deposited on a substrate, the plurality of layers defining the plurality of features of the semiconductor device, the modifying the plurality of features comprising:
applying a mask layer to the previously manufactured semiconductor device;
forming a pattern in the mask layer, the pattern aligned with the plurality of features of the semiconductor device;
etching one or more of the layers based upon the pattern to create a plurality of vias, each of the vias extending through one or more of the layers to a respective feature in the features; and
forming a plurality of connections between the features and a surface of the semiconductor device by way of the vias.

US Pat. No. 10,217,703

CIRCUITS FOR AND METHODS OF IMPLEMENTING AN INDUCTOR AND A PATTERN GROUND SHIELD IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. An integrated circuit device, comprising:a substrate;
a plurality of metal routing interconnect layers;
an inductor formed in at least one metal layer of the plurality of metal routing interconnect layers; and
a bottom metal layer between the plurality of metal routing interconnect layers and the substrate;
wherein a pattern ground shield is formed in the bottom metal layer, the pattern ground shield comprising bottom metal traces in the bottom metal layer, a metal routing interconnect layer of the plurality of metal routing interconnect layers being over and adjacent the bottom metal layer, the metal routing interconnect layer comprising a first metal trace and a second metal trace, the first metal trace and the second metal trace being connected to alternating ones of the bottom metal traces by respective vias.

US Pat. No. 10,217,702

SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN EMBEDDED SOP FAN-OUT PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a semiconductor package including a first semiconductor die and a first encapsulant disposed over the first semiconductor die;
disposing a second semiconductor die over the semiconductor package;
forming a plurality of bumps over the semiconductor package and around the second semiconductor die;
depositing a second encapsulant in contact with the semiconductor package and around the second semiconductor die and in contact with the bumps, wherein a portion of the bumps extends outward beyond the second encapsulant and an active surface of the second semiconductor die is coplanar with a surface of the second encapsulant; and
forming an interconnect structure over the second semiconductor die and second encapsulant and contacting the bumps after depositing the second encapsulant.

US Pat. No. 10,217,701

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a package substrate having a first surface and a second surface opposite to the first surface;
a semiconductor chip wire bonded to the first surface of the package substrate and comprising a semiconductor element;
an adhesive provided directly between the semiconductor chip and the package substrate; and
a metal bump provided on the second surface of the package substrate, wherein
the package substrate is a multilayer substrate that includes:
a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer;
a first resin layer provided between the first wiring layer and the second wiring layer;
a second resin layer provided between the second wiring layer and the third wiring layer; and
a third resin layer provided between the third wiring layer and the fourth wiring layer,
an expression (1) is satisfied when where a coefficient of thermal expansion of the semiconductor chip is CTE1, a coefficient of thermal expansion of each of the first, second and third resin layers is CTE2, a coefficient of thermal expansion of each of the first, second, third, and fourth wiring layers is CTE3, and a coefficient of thermal expansion of the adhesive is CTE4:
CTE1 an expression (2) is satisfied where an elastic modulus of the semiconductor chip is EM1, an elastic modulus of each of the first, second, and third resin layers is EM2, an elastic modulus of each of the first, second, third, and fourth wiring layers is EM3, and an elastic modulus of the adhesive is EM4:
EM1>EM3>EM2>EM4  (2).

US Pat. No. 10,217,700

LEAD FRAME FOR INTEGRATED CIRCUIT DEVICE HAVING J-LEADS AND GULL WING LEADS

NXP USA, INC., Austin, T...

1. An article of manufacture, comprising:a central die receiving area configured for receiving at least one integrated circuit die;
a plurality of first leads surrounding the die receiving area and extending outwardly therefrom in a first plane;
a plurality of second leads surrounding the die receiving area and extending outwardly therefrom in the first plane,
wherein the plurality of second leads are interleaved with the plurality of first leads;
wherein each lead of the pluralities of first and second leads has a first inner lead area proximate to the die receiving area, said first inner lead area configured for electrical connection to bonding pads of the at least one integrated circuit die, a second inner lead area extending from the first inner lead area to a package boundary, and an outer lead area that extends beyond the package boundary; and
wherein each of the second leads includes a down-set portion that extends from the second inner lead area to the outer lead area, wherein the down-set portion facilitates maintaining the first inner lead area in the first plane when a force from a mold tool presses the outer lead area proximate to the inner lead areas downwards.

US Pat. No. 10,217,699

PREFORMED LEAD FRAME

Chang Wah Technology Co.,...

1. A preformed lead frame, comprising:a plurality of lead frame units arranged in intersecting rows, each of said lead frame units including at least one die pad, and a plurality of spaced-apart leads;
a plurality of intersecting cutting paths, each of said cutting paths extending between two adjacent rows of said lead frame units, and having a plurality of spaced-apart metallic connecting portions and a plurality of spaced-apart etched grooves, each of said metallic connecting portions being connected between an adjacent one of said leads of one of said lead frame units and an adjacent one of said leads of the other one of said lead frame units; and
a molding layer embedding said die pads and said leads of said lead frame units and said metallic connecting portions of said cutting paths, said molding layer having a top surface exposing a top surface of each of said die pads and a top surface of each of said leads, and a bottom surface exposing a bottom surface of each of said die pads and a bottom surface of each of said leads, and bottom surfaces of said metallic connecting portions,
wherein each of said metallic connecting portions extends upwardly from said bottom surface of said molding layer to a level lower than said top surface of said molding layer, each of said etched grooves being indented from said top surface of said molding layer, being confined between an adjacent one of said leads of one of said lead frame units and an adjacent one of said leads of the other one of said lead frame units, and being located immediately above a respective one of said metallic connecting portions;
wherein each of said etched grooves has a top open end, a bottom end opposite to said top open end and bordered by a top surface of one of said metallic connecting portions, two opposite side ends each connected between said top open end and said bottom end and bordered by said molding layer, and two opposite lateral ends each connected between said top open end and said bottom end and interposed between said side ends, said lateral ends being respectively bordered by lead lateral surfaces of two of said leads, which are connected to said one of said metallic connecting portions, said lead lateral surfaces extending downwardly from said top open end to said bottom end and cooperating with said bottom end to form a curved surface concave relative to said top open end;
wherein said top open end of each of said etched grooves includes two opposite curved edges respectively meeting said adjacent one of said leads of said one of said lead frame units and said adjacent one of said leads of said the other one of said lead frame units;
wherein said two curved edges of said top open end of each of said etched grooves are respectively convex toward said adjacent one of said leads of said one of said lead frame units and said adjacent one of said leads of said the other one of said lead frame units; and
wherein each of said curved edges of said top open end of each of said etched grooves has two end points and a vertex point, a distance between said vertex point and a phantom line passing said end points ranging from 5 ?m to 50 ?m.

US Pat. No. 10,217,698

DIE ATTACHMENT FOR PACKAGED SEMICONDUCTOR DEVICE

NXP USA, Inc., Austin, T...

1. A packaged semiconductor device, comprising:a package substrate comprising a plurality of first protrusions and a plurality of second protrusions extending from a top surface of the package substrate, each of the first and second protrusions having a top surface;
a plurality of first die attach material portions, each first die attach material portion in contact with each top surface of the first protrusions;
a plurality of second die attach material portions, each second die attach material portion in contact with each top surface of the second protrusions;
a first semiconductor die over the plurality of first protrusions, wherein the first semiconductor die is spaced apart from the top surface of the package substrate, wherein the first semiconductor die has a bottom surface having no bond pads that is in contact with the first die attach material portions, and wherein a first region is defined between the first semiconductor die and the top surface of the package substrate and around the first protrusions;
a second semiconductor die over the plurality of second protrusions, wherein the second semiconductor die is spaced apart from the top surface of the package substrate, wherein the second semiconductor die has a bottom surface having no bond pads that is in contact with the second die attach material portions, and wherein a second region is defined between the second semiconductor die and the top surface of the package substrate around the second protrusions;
wire interconnects formed between bond pads on a top surface of the first and second semiconductor dies and bonding areas on the top surface of the package substrate, wherein the top surfaces of the first and second protrusions are not in a same plane as the top surfaces of the bonding areas;
an underfill material within the first and second regions, wherein the underfill material contacts the top surface of the package substrate and the bottom surface of the first and second semiconductor dies between the plurality of first and second die attach material portions; and
an encapsulant over the first and second semiconductor dies and over the wire interconnects.

US Pat. No. 10,217,697

SEMICONDUCTOR DEVICE AND LEAD FRAME WITH HIGH DENSITY LEAD ARRAY

NXP B.V., San Jose, CA (...

1. A semiconductor device, comprising:a lead frame having a plurality of leads arranged in an array that comprises a plurality of columns extending in a first direction and a plurality of rows extending in a second direction, wherein each lead comprises a bond pad portion located in a first plane, and a solder pad portion located in a second plane that is parallel to and down-set from the first plane, wherein the bond pad portion and the solder pad portion of each lead are staggered, and the solder pad portion horizontally extends from the bond pad portion in the first direction;
a semiconductor die mounted on the bond pad portions of a first set of the plurality of leads and electrically connected to the bond pad portion of at least one lead of a second set of the plurality of leads, wherein the first and second sets of the plurality of leads do not intersect; and
a molding material encapsulating the semiconductor die, and the plurality of leads, wherein the molding material defines a package body and the solder pad portion of each lead is exposed at a back side of the package body.

US Pat. No. 10,217,696

NON-BRIDGING CONTACT VIA STRUCTURES IN PROXIMITY

International Business Ma...

1. A structure comprising:a stack of a template layer and a contiguous spacer layer, wherein said contiguous spacer layer is located on an entire topmost surface of said template layer, and wherein sidewall surfaces of said template layer are vertically aligned to sidewall surfaces of said contiguous spacer layer;
an etch-resistant material portion overlying an entirety of a recessed portion of said stack, wherein said etch resistant material portion has sidewall surfaces that are vertically aligned to sidewall surfaces of said recessed portion of said stack; and
a pair of via structures embedded within said stack and laterally spaced by said etch-resistant material portion and said recessed portion of said stack, wherein a top surface of said contiguous spacer layer, a top surface of said etch-resistant material portion, and top surfaces of said pair of via structures are coplanar among one another, and wherein said etch-resistant material portion has an H-shaped pattern, and a lateral extent of said pair of via structures is bounded by a pair of parallel line portions within said H-shaped pattern.

US Pat. No. 10,217,695

CONNECTOR BLOCK WITH TWO SORTS OF THROUGH CONNECTIONS, AND ELECTRONIC DEVICE COMPRISING A CONNECTOR BLOCK

Infineon Technologies AG,...

1. A connector block for providing a vertical interconnection between opposing main surface regions of a semiconductor package, the connector block comprising:an encapsulant;
at least one first electrically conductive through connection, in particular a plurality of first electrically conductive through connections, extending through the encapsulant from a first surface of the encapsulant to a second surface of the encapsulant;
at least one second electrically conductive through connection, in particular a plurality of second electrically conductive through connections, extending along an exterior third surface of the encapsulant from the first surface of the encapsulant to the second surface of the encapsulant,
wherein a cross-sectional area of the at least one first electrically conductive through connections is larger than a cross sectional area of the at least one second electrically conductive through connections in a plane perpendicular to a direction extending from the first surface of the encapsulant to the second surface of the encapsulant by a factor of at least 3.

US Pat. No. 10,217,694

LDMOS TRANSISTOR AND METHOD

Infineon Technologies AG,...

1. A method for electrically coupling an electrode of a transistor structure arranged at a first surface of a substrate to a third conductive layer arranged at a second surface of the substrate opposing the first surface, the method comprising:forming a blind via in the substrate adjacent the transistor structure;
depositing a first conductive layer onto side walls of the blind via and a region of a second conductive layer arranged on the first surface of the substrate adjacent the blind via and coupled to the electrode of the transistor structure, the first conductive layer consists of a single integral unit consisting of a same material throughout;
working the second surface of the substrate so as to expose a portion of the first conductive layer; and
depositing the third conductive layer onto the second surface of the substrate and the portion of the first conductive layer so as to electrically couple the third conductive layer with the electrode of the transistor structure,
wherein the transistor structure is a LDMOS (Lateral Diffused Metal Oxide Semiconductor) transistor structure and the electrode is a highly doped source region of a silicon substrate, wherein the source region has a doping concentration of at least 5·1019 cm?3,
wherein the single integral unit of the first conductive layer directly contacts a sidewall of the blind via and directly contacts a portion of the first surface of the substrate between the sidewall of the blind via and the region of the second conductive layer arranged on the first surface.

US Pat. No. 10,217,693

METHODS AND SYSTEMS FOR HIGH VOLTAGE COMPONENT COOLING IN ELECTRIC VEHICLE FOR FAST CHARGE

NIO USA, Inc., San Jose,...

1. A junction box of a vehicle, the junction box comprising:one or more relays;
one or more bus bars connected to one or more of the one or more relays;
one or more terminals that interconnect with a battery of the vehicle and one of the one or more relays; and
one or more phase change materials contained in one or more malleable plastic containers, wherein the one or more malleable plastic containers are attached to at least one of the relays, bus bars, and/or terminals, wherein the one or more phase change materials limit heat generation during a charging of a battery of the vehicle.

US Pat. No. 10,217,692

HEAT TRANSFER DEVICE FOR HIGH HEAT FLUX APPLICATIONS AND RELATED METHODS THEREOF

University of Virginia Pa...

46. An apparatus, said apparatus comprising:a first reservoir configured for carrying a first working fluid in said first reservoir;
a first integrated circuit (IC) die, said first IC die comprises a first heat source and a first two phase heat transfer device; wherein
said first two phase heat transfer device of said first IC die comprises:
a first base member, said first base member configured to receive thermal energy from the first heat source;
first elongated members having at least one wall, said first elongated members extending distally away from said first base member and configured to define respective first passages between adjacent first elongated members;
at least some of said first elongated members configured to be at least partially inserted into the first working fluid;
a first recess topography disposed on said at least one wall of said first elongated members, wherein said first recess topography is configured to accommodate the first working fluid;
said first elongated members having a proximal end and a distal end substantially opposed from one another, wherein said proximal end to be closer to the first heat source and said distal end to be inserted in the first working fluid;
wherein said first recess topography comprises first fractal topology, wherein said first fractal topology comprises:
first recesses, wherein the number of first recesses toward said proximal end of said first elongated members is greater than the number of first recesses toward said distal end of said first elongated members; and
said first passages are configured to accommodate vapor produced from the first working fluid so as to define a first vapor space;
a second reservoir configured for carrying a second working fluid in said second reservoir;
a second integrated circuit (IC) die, said second IC die comprises a second heat source and a second two phase heat transfer device; wherein
said second two phase heat transfer device of said second IC die comprises:
a second base member, said second base member configured to receive thermal energy from the second heat source;
second elongated members having at least one wall, said second elongated members extending distally away from said second base member and configured to define respective second passages between adjacent said second elongated members;
at least some of said second elongated members configured to be at least partially inserted into the second working fluid;
a second recess topography disposed on said at least one wall of said second elongated members, wherein said second recess topography is configured to accommodate the second working fluid; and
said second passages are configured to accommodate vapor produced from the second working fluid so as to define a second vapor space; and
said first IC die and said second IC die operatively coupled together.

US Pat. No. 10,217,690

SEMICONDUCTOR MODULE THAT HAVE MULTIPLE PATHS FOR HEAT DISSIPATION

KABUSHIKI KAISHA TOSHIBA,...

1. A semiconductor module, comprising:a substrate comprising a metal layer and an insulating layer on the metal layer, the insulating layer comprising a resin and a filler, the filler comprising at least one of boron nitride, alumina, aluminum nitride, silicon nitride, and silicon carbide;
a case along an outer periphery of the substrate;
first and second wirings on the substrate;
a first semiconductor package disposed on the first wiring; and
a third wiring including a planar portion and bent portion, the third wiring being outside of the first semiconductor package and connecting to a top surface of the first semiconductor package and the second wiring, wherein
the first semiconductor package comprises:
a first main electrode having a first surface in a same plane as the top surface of the first semiconductor package, the first surface being exposed from the first semiconductor package;
a second main electrode having a second surface located in a same plane as a bottom surface of the first semiconductor package, the second surface being exposed from the first semiconductor package;
a semiconductor element between the first and second main electrodes; and
a material sealing the first and second main electrodes and the semiconductor element.

US Pat. No. 10,217,689

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND METHOD FOR MANUFACTURING THE SAME

ROHM CO., LTD., Kyoto (J...

1. A semiconductor integrated circuit device comprising:an insulating substrate;
a via which penetrates through the insulating substrate;
a first metal layer disposed on a front surface of the insulating substrate;
a first resist layer disposed on the first metal layer in the vicinity of the via;
a solder layer disposed on the first metal layer, the via and the first resist layer;
a gap region formed between the solder layer and the first resist layer; and
a semiconductor integrated circuit, including an island and a semiconductor integrated circuit chip, disposed on the solder layer,
wherein the island is fused to the solder layer and the semiconductor integrated circuit chip is disposed on the island.

US Pat. No. 10,217,688

ELECTRONIC COMPONENT HAVING A HEAT-SINK THERMALLY COUPLED TO A HEAT-SPREADER

Infineon Technologies Aus...

1. An electronic component, comprising:one or more semiconductor dice embedded in a first dielectric layer;
a heat-spreader embedded in a second dielectric layer, wherein the heat-spreader has a higher thermal conductivity in directions substantially parallel to the major surface of the one or more semiconductor dice than in directions substantially perpendicular to the major surface of the one or more semiconductor dice; and
a heat-sink thermally coupled to the heat-spreader, wherein the heat-sink has a thermal conductivity in directions substantially perpendicular to the major surface of the one or more semiconductor dice that is higher than the thermal conductivity of the heat-spreader in directions substantially perpendicular to the major surface of the one or more semiconductor dice, and the heat-spreader and the heat-sink provide a heat dissipation path from the one or more semiconductor dice having a lateral thermal resistance which increases with increasing distance from the one or more semiconductor dice.

US Pat. No. 10,217,687

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a conductive pad over the semiconductor substrate;
a conductor over the conductive pad;
a polymeric material over the semiconductor substrate and surrounding the conductor; and
a seed layer between the polymeric material and the conductor,wherein a bottom surface and longitudinal sidewalls of the conductor are in contact with the seed layer, a top surface of the conductor is entirely exposed through the seed layer and the polymeric material, and the top surface of the polymeric material is entirely exposed through the seed layer.

US Pat. No. 10,217,686

AIR-CAVITY PACKAGE WITH ENHANCED PACKAGE INTEGRATION LEVEL AND THERMAL PERFORMANCE

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a bottom package precursor, which comprises a bottom substrate and a bottom electronic component, wherein:
the bottom substrate comprises a bottom substrate body having an upper side and a lower side and at least one bottom metal structure on the upper side of the bottom substrate body; and
the bottom electronic component is mounted on the upper side of the bottom substrate body;
providing a top package precursor, which comprises a top substrate, a top electronic component, and an external electronic component, wherein:
the top substrate comprises a top substrate body having an upper side and a lower side and at least one top metal structure on the lower side of the top substrate body;
the top electronic component is mounted on the lower side of the top substrate body; and
the external electronic component is mounted on the upper side of the top substrate body;
providing a perimeter wall, which comprises at least one signal via structure extending from an upper surface of the perimeter wall through the perimeter wall to a lower surface of the perimeter wall; and
assembling the bottom package precursor, the perimeter wall, and the top package precursor, wherein:
the perimeter wall extends from a periphery of the lower side of the top substrate body to a periphery of the upper side of the bottom substrate body such that a cavity is defined by a portion of the upper side of the bottom substrate body, an inside surface of the perimeter wall, and a portion of the lower side of the top substrate body;
the bottom electronic component and the top electronic component are exposed to the cavity;
the external electronic component is not within the cavity; and
the at least one signal via structure is electrically coupled to the at least one bottom metal structure and the at least one top metal structure.

US Pat. No. 10,217,685

AIR-CAVITY PACKAGE WITH DUAL SIGNAL-TRANSITION SIDES

Qorvo US, Inc., Greensbo...

1. A method comprising:providing a bottom package precursor, which comprises a bottom substrate and a bottom electronic component, wherein:
the bottom substrate comprises a bottom substrate body having an upper side and a lower side, at least one first bottom metal structure on the upper side of the bottom substrate body, at least one second bottom metal structure on the lower side of the bottom substrate body, and at least one bottom signal via that extends from the upper side of the bottom substrate body through the bottom substrate body to the lower side of the bottom substrate body and is electrically coupled to the at least one second bottom metal structure; and
the bottom electronic component is mounted on the upper side of the bottom substrate body and electrically coupled to the at least one bottom signal via;
providing a top package precursor, which comprises a top substrate and a top electronic component, wherein:
the top substrate comprises a top substrate body having an upper side and a lower side, at least one first top metal structure on the upper side of the top substrate body, at least one second top metal structure on the lower side of the top substrate body, and at least one top signal via that extends from the upper side of the top substrate body through the top substrate body to the lower side of the top substrate body and is electrically coupled to the at least one first top metal structure; and
the top electronic component is mounted on the lower side of the top substrate body and electrically coupled to the at least one top signal via;
providing a perimeter wall, which comprises at least one signal via structure extending from an upper surface of the perimeter wall through the perimeter wall to a lower surface of the perimeter wall; and
assembling the bottom package precursor, the perimeter wall, and the top package precursor, wherein:
the perimeter wall extends from a periphery of the lower side of the top substrate body to a periphery of the upper side of the bottom substrate body such that a cavity is defined by a portion of the upper side of the bottom substrate body, an inside surface of the perimeter wall, and a portion of the lower side of the top substrate body;
the bottom electronic component and the top electronic component are exposed to the cavity; and
the at least one signal via structure is electrically coupled to the at least one first bottom metal structure and the at least one second top metal structure.

US Pat. No. 10,217,684

RESIN MOLDING AND SENSOR DEVICE

Hitachi Automotive System...

1. A resin molding comprising:a semiconductor element;
a circuit board on which a conductor connected to the semiconductor element is formed; and
a resin adhered and integrated with the circuit board,
wherein a resin leakage suppression layer including a material having a higher thermal conductivity than a thermal conductivity of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin; and
wherein the resin leakage suppression layer is formed of a same material as the conductor.

US Pat. No. 10,217,683

MOUNTED SEMICONDUCTOR MODULE WITH A MOLD RESIN PORTION

Mitsubishi Electric Corpo...

1. A semiconductor module comprising:a semiconductor element that is mounted;
a mold resin portion, wherein the mold resin portion comprises:
a plurality of sides;
a plurality of corner portions; and
a holding side portion provided at each of at least two diagonally opposing corner portions, from among the plurality of corner portions; and
a plurality of outside connecting modules drawn from a first side of the mold resin portion;
wherein a surface of at least one of the holding side portions is oblique relative to the first side of the mold resin portion.

US Pat. No. 10,217,682

TIME TEMPERATURE MONITORING SYSTEM

International Business Ma...

1. A time temperature monitoring system, comprising:a substrate having an active region;
a dopant source located proximate the active region;
an activation system for activating a diffusion of the dopant source into the active region; and
a set of spatially distributed transistors embedded in the active region of the substrate, wherein the transistors are configured to detect the diffusion correlated to time and temperature in the active region at varying distances from the dopant source to provide time temperature information.

US Pat. No. 10,217,681

GASES FOR LOW DAMAGE SELECTIVE SILICON NITRIDE ETCHING

American Air Liquide, Inc...

1. A silicon nitride plasma etching process for etching a SiN layer from a substrate, the method comprising:generating on the SiN layer a SiN roughness layer of between approximately 0 nm and approximately 10 nm thickness during the silicon nitride plasma etching process by simultaneously introducing an oxidizer at a flow rate and an etch gas into a plasma reaction chamber containing the substrate, the etch gas having the formula CxHyFz, wherein x is 2-5, z is 1 or 2, 2x+2=y+z, and a fluorine atom is located on a terminal carbon atom of the etch gas and the flow rate is selected to simultaneously yield infinite SiN to substrate selectivity and the SiN roughness layer of between approximately 0 nm and approximately 10 nm thickness.

US Pat. No. 10,217,680

TEST APPARATUS AND MANUFACTURING APPARATUS OF LIGHT EMITTING DEVICE PACKAGE

SAMSUNG ELECTRONICS CO., ...

1. A method of testing an object, comprising:radiating light from a lighting unit to a test object having a light transmitting resin containing a light conversion material;
obtaining an image of the test object by a camera unit while the light transmitting resin is receiving light emitted by the lighting unit; and
determining whether the test object is defective by calculating gray values corresponding to the image obtained by the camera unit.

US Pat. No. 10,217,679

METHOD FOR POSITIONING A CARRIER WITH ELECTRONIC COMPONENTS AND ELECTRONIC COMPONENT PRODUCED WITH SUCH METHOD

Besi Netherlands B.V., D...

1. A method of processing a solder masked carrier with electronic components, comprising the method steps:A) detecting at least one carrier related reference;
B) processing the at least one detected carrier related reference into a position of the carrier;
C) detecting at least one solder mask dependent reference; and
D) processing the at least one detected solder mask dependent reference into a position of the solder mask on the carrier, thereby detecting inaccuracies in the positioning of the solder mask to the carrier;
wherein the method further comprises the method step of E) processing the solder masked carrier with electronic components dependent on the position of the solder mask as such on the carrier, thereby compensating for the inaccuracies in the positioning of the solder mask to the carrier; and
wherein the processing of the solder masked carrier with electronic components according step E) comprises the separation of the solder masked electronic components.

US Pat. No. 10,217,678

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE DISPLAY DEVICE

INNOLUX CORPORATION, Mia...

1. A display device, comprising:a substrate;
a first transistor disposed on the substrate;
a second transistor disposed on the substrate, and the second transistor comprises a gate electrode;
a conductive connection portion disposed on the substrate, and the first transistor is electrically connected to the gate electrode of the second transistor through the conductive connection portion;
an insulating layer disposed on the conductive connection portion;
a pixel electrode disposed on the insulating layer and electrically connected to the second transistor, wherein the pixel electrode is at least partially overlapped with the conductive connection portion; and
a light-emitting element disposed on the pixel electrode;
wherein the conductive connection portion and the pixel electrode form a capacitor, the capacitor has an equivalent permittivity and a thickness, and a ratio of the equivalent permittivity to the thickness is in a range from 0.4*(1E+5)F/m?2 to 296.48*(1E+5)F/m?2.

US Pat. No. 10,217,677

REMOVABLE SACRIFICIAL CONNECTIONS FOR SEMICONDUCTOR DEVICES

Qorvo US, Inc., Greensbo...

1. A semiconductor device comprising:a semiconductor layer comprising:
a circuit layout on the semiconductor layer comprising:
a plurality of bump pads comprising a plurality of ground bump pads and a plurality of signal bump pads;
at least one ground probe pad connected to at least one of the plurality of ground bump pads; and
at least one signal probe pad connected to at least one of the plurality of signal bump pads;
a saw street on the periphery of the circuit layout; and
one or more sacrificial connections connecting at least two of the plurality of bump pads in the circuit layout.

US Pat. No. 10,217,676

METHOD AND APPARATUS FOR MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF SEMICONDUCTOR CHIPS CONNECTED WITH BUMPS

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor device including a plurality of semiconductor chips, the method comprising:placing, on a first semiconductor chip, a second semiconductor chip, such that a plurality of bumps is located between the first semiconductor chip and the second semiconductor chip;
after said placing, softening and then solidifying the plurality of bumps to bond the first semiconductor chip and the second semiconductor chip to each other;
measuring a position of a head for holding a semiconductor chip to be placed at least one of when the plurality of bumps is softened and when the plurality of bumps is solidified, while the head holds the second semiconductor chip;
determining a distance between the first semiconductor chip and the second semiconductor chip placed thereon, based on a position of the head when the first semiconductor chip is placed on a substrate by the head, the measured position of the head, and a thickness of the second semiconductor chip; and
determining whether or not the distance is within a predetermined range and stopping placement of additional chips if the distance is determined to be outside the predetermined range.

US Pat. No. 10,217,675

PLACEMENT METHOD FOR CIRCUIT CARRIER AND CIRCUIT CARRIER

A.B. MIKROELEKTRONIK GESE...

1. A process for the production of a circuit carrier equipped with at least one surface-mount LED (SMD-LED) for a motor vehicle, wherein the at least one SMD-LED is positioned in oriented relationship to one or more reference points of the circuit carrier on the circuit carrier, wherein a position of a light-emitting region of the at least one SMD-LED is optically detected in the SMD-LED by illuminating the SMD-LED with a light source that is separate from the SMD-LED, and wherein the at least one SMD-LED is mounted to the circuit carrier in dependence on the detected position of the light-emitting region of the at least one SMD-LED.

US Pat. No. 10,217,674

THREE-DIMENSIONAL MONOLITHIC VERTICAL FIELD EFFECT TRANSISTOR LOGIC GATES

INTERNATIONAL BUSINESS MA...

1. A logic device, comprising:a first vertical transport field effect transistor formed over and adjacent a substrate;
a first bonding film deposited over the first vertical transport field effect transistor;
a second vertical transport field effect transistor comprising a second bonding film and stacked on the first vertical transport field effect transistor, wherein the second bonding film affixes the second vertical transport field effect transistor to the first vertical transport field effect transistor; and
one or more monolithic inter-layer vias that extend from first respective portions of the second vertical transport field effect transistor to second respective portions of the first vertical transport field effect transistor and through the first bonding film and the second bonding film.

US Pat. No. 10,217,673

INTEGRATED CIRCUIT DIE HAVING REDUCED DEFECT GROUP III-NITRIDE STRUCTURES AND METHODS ASSOCIATED THEREWITH

Intel Corporation, Santa...

1. An integrated circuit (IC) die comprising:a semiconductor substrate;
a buffer layer disposed over the semiconductor substrate, the buffer layer having a plurality of openings formed therein; and
a plurality of group III-Nitride structures, wherein individual group III-Nitride structures of the plurality of group III-Nitride structures include a lower portion disposed in a respective opening of the plurality of openings and an upper portion disposed over the respective opening, the upper portion including a base extending radially from sidewalls of the respective opening over a surface of the buffer layer to form a perimeter around the respective opening; and
wherein a shape of an upper portion of at least one group III-Nitride structure of the plurality of group III-Nitride structures is one of a substantially pyramidal structure or a substantially frustum pyramidal structure or a substantially cuboidal structure and wherein glide planes for defects in the at least one group III-Nitride structure extend vertically in the respective opening and terminate at respective faces of the at least one group III-Nitride structure, wherein regions of the cuboidal structure disposed above the buffer layer have a reduced defect density in comparison to group III-Nitride material disposed above the opening.

US Pat. No. 10,217,672

VERTICAL TRANSISTOR DEVICES WITH DIFFERENT EFFECTIVE GATE LENGTHS

GLOBALFOUNDRIES Inc., Gr...

1. A device, comprising:a first vertical transistor device positioned above a semiconductor substrate, said first vertical transistor device comprising:
a first gate structure;
a first top spacer positioned above said first gate structure and having a first thickness in a vertical direction, wherein said first top spacer comprises a plurality of layers; and
a first doped top source/drain structure positioned above said first top spacer; and
a second vertical transistor device positioned above said semiconductor substrate, said second vertical transistor device comprising:
a second gate structure;
a second top spacer positioned above said second gate structure and having a second thickness in a vertical direction less than said first thickness, wherein said second top spacer comprises a lesser number of layers than said first top spacer; and
a second doped top source/drain structure positioned above said second top spacer.

US Pat. No. 10,217,671

SEMICONDUCTOR DEVICE COMPRISING A SWITCH

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising a switch, the device having a layout comprising one or more rectangular unit cells, each unit cell comprising:a gate comprising:
a substantially cross-shaped part comprising four arms that divide the unit cell into quadrants; and
a substantially loop-shaped part, wherein a center of the cross-shaped part is located inside the loop-shaped part, and wherein the loop-shaped part intersects each arm of the cross-shaped part to divide each quadrant into:
an inner region located inside the loop-shaped part; and
an outer region located outside the loop-shaped part;
a substantially loop-shaped active region forming a source and drain of the switch,
wherein first and second parts of the loop-shaped active region located in respective first and second diagonally opposite quadrants of the unit cell each include an inner source region located inside the loop-shaped part of the gate and an outer drain region located on an outer side of the loop-shaped part of the gate,
wherein third and fourth parts of the loop-shaped active region located in respective third and fourth diagonally opposite quadrants of the unit cell each include an inner drain region located inside the loop-shaped part of the gate and an outer source region located on an outer side of the loop-shaped part of the gate; and
a plurality of connection members extending over the gate, source and drain for providing electrical connections to the source and drain.

US Pat. No. 10,217,670

WRAP-AROUND CONTACT INTEGRATION SCHEME

Tokyo Electron Limited, ...

1. A substrate processing method, comprising:providing a substrate containing raised contacts in a first dielectric film and a second dielectric film above the first dielectric film;
depositing a metal-containing film on the second dielectric film;
forming a patterned metal-containing film by etching mask openings in the metal-containing film; and
anisotropically etching recessed features in the second dielectric film above the raised contacts using the patterned metal-containing film as a mask, wherein the anisotropically etching forms a metal-containing sidewall protection film by redeposition of a portion of the patterned metal-containing film on sidewalls of the recessed features.

US Pat. No. 10,217,669

ISOLATION COMPONENTS FOR TRANSISTORS FORMED ON FIN FEATURES OF SEMICONDUCTOR SUBSTRATES

Marvell World Trade Ltd.,...

1. A method comprising:forming a fin feature on a portion of a surface of a substrate, wherein the fin feature extends in a direction perpendicular to a planar portion of the surface of the substrate;
forming a dielectric layer over the planar portion of the surface of the substrate, wherein the dielectric layer extends outward from a base of the fin feature;
forming a first region of polycrystalline silicon over a first portion of the fin feature of the substrate;
forming a second region of polycrystalline silicon over a second portion of the fin feature of the substrate;
forming a third region of polycrystalline silicon over a third portion of the fin feature of the substrate, wherein the third region of polycrystalline silicon is disposed between (i) the first region of polycrystalline silicon and (ii) the second region of polycrystalline silicon;
forming a first spacer region between (i) the first region of polycrystalline silicon and (ii) the third region of polycrystalline silicon, wherein the first spacer region includes a first dielectric material;
forming a second spacer region between (i) the second region of polycrystalline silicon and (ii) the third region of polycrystalline silicon, wherein the second spacer region includes the first dielectric material;
subsequent to forming the first spacer region and the second spacer region, removing (i) the third region of polycrystalline silicon and (ii) at least a portion of the fin feature formed under the third region of polycrystalline silicon to thereby form a gap between the first spacer region and the second spacer region; and
disposing only one or more other dielectric materials into the gap to form an isolation component, wherein:
the one or more other dielectric materials completely fill the gap between (i) the first spacer region and (ii) the second spacer region,
the one or more dielectric materials comprise at least a second dielectric material, and
a dielectric constant of the second dielectric material is less than a dielectric constant of the dielectric layer formed over the planar portion of the surface of the substrate.

US Pat. No. 10,217,668

ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME

MIE FUJITSU SEMICONDUCTOR...

1. A field effect transistor (FET) formed in a doped well, the FET having a source, a drain, and a gate stack having a gate length, the FET comprising:a screening region positioned above the doped well, the screening region being doped with a first type of dopant, the screening region being electrically coupled to the doped well, the screening region being positioned below the gate stack;
a substantially undoped semiconductive layer formed above the screening region, the substantially undoped semiconductive layer being adjacent to the screening region;
a threshold voltage setting region in the substantially undoped semiconductive layer, the threshold voltage setting region being doped with the first type of dopant, the threshold voltage setting region dopant concentration modifying a threshold voltage of the FET;
wherein the gate stack is positioned above the doped well to control conduction between a drain and a source, the source and the drain being doped with a second type of dopant;
wherein at least a portion of the substantially undoped semiconductive layer is maintained as a substantially undoped channel region having a dopant concentration less than 1×1017 atoms/cm3, with the substantially undoped channel region laterally positioned between the source and the drain and vertically positioned between the gate stack and the threshold voltage setting region, and the threshold voltage setting region is vertically positioned between the substantially undoped channel region and the screening region;
wherein the screening region has a dopant concentration greater than ten times the dopant concentration of the substantially undoped channel region and sets a depth of a depletion layer below the gate stack in a direction from the substantially undoped channel region toward the screening region.

US Pat. No. 10,217,667

3D SEMICONDUCTOR DEVICE, FABRICATION METHOD AND SYSTEM

MONOLITHIC 3D INC., San ...

15. A method for fabrication of a 3D semiconductor device, the method comprising:providing a substrate comprising a single crystal layer;
forming a plurality of first transistors in and on said single crystal layer; then
forming at least one metal layer, said at least one metal layer comprising connections between said first transistors,
wherein a portion of said at least one metal layer comprising said connections between said first transistors form memory peripheral circuits; then
forming a stack of at least sixteen layers,
wherein said stack of at least sixteen layers comprises odd numbered layers and even numbered layers,
wherein said odd numbered layers comprise a first material and said even numbered layers comprise a second material,
wherein said first material is of a different composition than said second material, and
wherein said forming said stack is performed as part of forming a multilevel memory structure; and then
processing said stack of at least sixteen layers forming at least eight layers of memory cells,
wherein said at least eight layers of memory cells are controlled by said periphery circuits.

US Pat. No. 10,217,666

STACKED STRUCTURE HAVING A PROTECTIVE LAYER BETWEEN AN INSULATION LAYER AND WIRING

SONY SEMICONDUCTOR SOLUTI...

1. A stacked structure, comprising:a wiring;
a first insulating layer;
a substrate;
an element in the substrate;
a protective layer; and
a connection section in the first insulating layer and the protective layer,
wherein the connection section connects the element to the wiring,
wherein the first insulating layer is stacked on the substrate, the protective layer is stacked on the first insulating layer, and the wiring is stacked on the protective layer,
wherein an end portion of the wiring projects from a side face of the stacked structure,
wherein the protective layer comprises a Silicon Nitride (SiN) based material, and
wherein the protective layer has a first etching rate for an etching condition different from a second etching rate of a material of the first insulating layer.

US Pat. No. 10,217,665

SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

UNISANTIS ELECTRONICS SIN...

1. A semiconductor device comprising:a first pillar-shaped semiconductor on a semiconductor substrate;
a first first-conductivity-type semiconductor layer in the first pillar-shaped semiconductor;
a second first-conductivity-type semiconductor layer in the first pillar-shaped semiconductor;
a third first-conductivity-type semiconductor layer in the first pillar-shaped semiconductor and located at a higher position than the first first-conductivity-type semiconductor layer;
a first gate insulating film surrounding a first body region of the first pillar-shaped semiconductor, the first body region sandwiched between and in direct contact with the first first-conductivity-type semiconductor layer and the second first-conductivity-type semiconductor layer;
a first gate surrounding the first gate insulating film;
a second gate insulating film surrounding a second body region of the first pillar-shaped semiconductor, the second body region sandwiched between and in direct contact with the second first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; and
a second gate surrounding the second gate insulating film,
wherein the first gate and the second gate are mutually connected.

US Pat. No. 10,217,664

REFLOW INTERCONNECT USING RU

INTERNATIONAL BUSINESS MA...

1. A method for forming conductive structures for a semiconductor device, comprising:forming a repeating sequence of reflow materials on reflow liners that is present on walls of an opening formed in a dielectric layer, the reflow liner comprised of a material having a higher melting temperature than the reflow material; and
reflowing the reflow material to collect in a lower portion of the openings prior to reflowing the reflow liners to fill the opening.

US Pat. No. 10,217,663

APPARATUS FOR UNIFORM METAL DEPOSITION

SEMICONDUCTOR MANUFACTURI...

1. An apparatus for manufacturing a semiconductor device, comprising:a deposition chamber comprising a first station, a second station, and one or more third stations;
a delivery system configured to provide a substrate to the deposition chamber for processing;
a processing system configured to process the substrate;
a controller configured to control the delivery system and the processing system; and
an etch chamber,
wherein:
the delivery system provides the substrate to the first station, where the processing system performs a nucleation process on the substrate to form a metal nucleation layer under the control of the controller;
the substrate including the metal nucleation layer is provided by the delivery system to the second station, where the processing system performs a first deposition process at a first temperature to form a first metal layer;
the delivery system provides the substrate including the first metal layer to the etch chamber, where an etch-back process is performed using a first gas on the first metal layer;
the delivery system returns the substrate with the etched-back first metal layer back to the first station, wherein the processing system performs a cleaning process on the substrate using a second gas;
the delivery system provides the cleaned substrate to the second station or the one or more third stations, where a second deposition is performed to form a second metal layer on the etched-back first metal layer.

US Pat. No. 10,217,662

METHOD FOR PROCESSING INTERCONNECTION STRUCTURE FOR MINIMIZING BARRIER SIDEWALL RECESS

ACM Research (Shanghai) I...

1. A method for processing an interconnection structure for minimizing barrier sidewall recess, comprising:step 1, removing a metal layer to generate a uniform dishing value inside the recessed area, the uniform dishing value is generated to make sure that the top surface of the metal layer in the recessed area is aligned with the bottom surface of the hard mask layer;
step 2, introducing noble-gas-halogen compound gas to remove a first barrier layer on top surface and at least a portion of a second barrier layer on sidewall by a gas phase chemical reaction process, the top surface of the second barrier layer on sidewall is aligned with the bottom surface of the hard mask layer;
step 3, introducing oxidizing gas to generate a barrier surface oxide on the top surface of the second barrier layer on sidewall, a metal surface oxide is generated at the same time;
step 4, introducing noble-gas-halogen compound gas to remove hard mask layer by a gas phase chemical reaction process;
step 5, reducing or removing the metal surface oxide.

US Pat. No. 10,217,661

ARTICLES INCLUDING ULTRA LOW DIELECTRIC LAYERS

International Business Ma...

1. An article comprising:a structure comprising a patterned metal on a surface of a substrate, the patterned metal comprising metal features separated by gaps of an average gap dimension of less than about 100 nm; and
a porous low dielectric constant material having a dielectric value of less than about 2.7 substantially occupying all gaps, wherein an interfacial region between the metal features and the porous low dielectric constant material comprises less than about 0.1% by volume of voids.

US Pat. No. 10,217,660

TECHNIQUE FOR PATTERNING ACTIVE REGIONS OF TRANSISTOR ELEMENTS IN A LATE MANUFACTURING STAGE

GLOBALFOUNDRIES Inc., Gr...

1. A method, comprising:bordering a semiconductor region of a semiconductor device along a length direction, wherein bordering said semiconductor region comprises forming an isolation structure in a semiconductor substrate and laterally adjacent to a lateral bounding surface of said semiconductor region;
forming at least a portion of each of a plurality of gate electrode structures above said semiconductor region, said at least said portion of each of said plurality of gate electrode structures having a length dimension extending along said length direction and a width dimension extending along a width direction, the width direction being transverse to the length direction; and
after forming said plurality of gate electrode structures, bordering said semiconductor region along said width direction.

US Pat. No. 10,217,659

DUAL ISOLATION FIN AND METHOD OF MAKING

INTERNATIONAL BUSINESS MA...

1. A semiconductor structure comprising:a substrate;
a fin of a second epitaxially formed material provided on a dielectric layer provided on the substrate, a first isolation region on the dielectric layer and adjacent a fin sidewall, and a second isolation region adjacent another fin sidewall including a bottom portion in contact with the substrate by:
applying a mask to portions of the substrate and etching exposed areas of the substrate to form a mandrel;
forming the dielectric layer disposed on a surface of the substrate and adjacent to the mandrel;
forming a first epitaxially formed material on an exposed portion of the mandrel;
forming the second epitaxially formed material on the first epitaxially formed material;
forming a first isolation layer on top of the dielectric layer and adjacent to the second epitaxially formed material;
removing the mask and mandrel after forming the first isolation layer to form an open area of the substrate;
removing the first epitaxially formed material after removing the mask and mandrel; and
forming a second isolation layer in the open area of the substrate such that the second isolation layer is formed on a sidewall and directly on a portion of a top surface of the dielectric layer;
wherein:
the first isolation layer has a thickness equal to a height of the second epitaxially formed material; and
wherein the second epitaxially formed material has fewer defects relative to forming the second epitaxially formed material without the first epitaxially formed material.

US Pat. No. 10,217,658

METHOD AND STRUCTURE FOR MINIMIZING FIN REVEAL VARIATION IN FINFET TRANSISTOR

International Business Ma...

1. A semiconductor device, comprising:a plurality of fins spaced apart from each other on a substrate, wherein a gate structure is around each of the fins;
a liner layer on the substrate between each fin of the plurality of fins and on at least a portion of a sidewall of each fin; and
a plurality of isolation regions on a top surface of the liner layer on the substrate and adjacent and between the plurality of fins;
wherein the plurality of isolation regions comprise:
a dielectric layer; and
a doped region on the dielectric layer.

US Pat. No. 10,217,657

ACTIVE SUBSTRATE ALIGNMENT SYSTEM AND METHOD

Varian Semiconductor Equi...

1. An active substrate alignment system for an ion implanter comprising:a platen;
a registration device adapted to selectively move a substrate engagement surface disposed adjacent the platen for limiting movement of a substrate disposed on the platen;
a camera configured to capture an image of the substrate before the substrate is disposed on the platen; and
a controller in communication with the camera and the registration device, the controller configured to command the registration device to move the substrate engagement surface based on the image to limit movement of the substrate in a predetermined manner.

US Pat. No. 10,217,656

PURGE APPARATUS AND PURGE METHOD

MURATA MACHINERY, LTD., ...

1. A purge apparatus for purging by purge gas a container that houses an article and includes a gas introduction hole in a bottom portion thereof, the purge apparatus comprising:a platform on which the container is placed;
a nozzle that protrudes upward from the platform and contacts the gas introduction hole of the container to inject purge gas; and
an alignment member that aligns the container; wherein
a side surface of a tip portion of the nozzle includes a guide surface that guides the container; and
an upper surface of the nozzle is supported by an elastic member such that the upper surface of the nozzle is lowered in response to a load applied from the container.

US Pat. No. 10,217,655

WAFER CONTAINER WITH SHOCK CONDITION PROTECTION

ENTEGRIS, INC., Billeric...

1. A wafer container for receiving and transporting bonded wafers, the wafer container comprising:a container portion including an open front defining an open interior and a back wall having an inside surface;
a door that closes the open front defining the open interior, the door having an inside surface;
a wafer support attached to one of the inside surface of the front door and the inside surface of the back wall of the, the wafer support having a plurality of pairs of wafer edge engagement portions having a first wafer edge engagement portion and a second wafer edge engagement portion, each wafer edge engagement portion defining a recess having a primary seating position, each of the wafer edge engagement portions comprised of a first polymeric material, wherein an edge of a wafer is in the primary seating position when the wafer container is not in a shock condition, the wafer support further including a shock deflection region axially offset from each primary seating position,
each shock deflection region having a shock deflection contact portion positioned to contact a wafer when the wafer container is in a shock condition, wherein the shock deflection contact portion is comprised of a second polymeric material wherein the second polymeric material is softer than the first polymeric material of the wafer edge engagement portions.

US Pat. No. 10,217,654

EMBEDDED FEATURES FOR INTERLOCKS USING ADDITIVE MANUFACTURING

Varian Semiconductor Equi...

1. An ion implantation system comprising:a controller in communication with a receiver; and
a component having a cavity and an identification feature disposed in the cavity;
wherein the controller outputs a signal which is received and modified by the identification feature before being transmitted to the receiver.

US Pat. No. 10,217,653

APPARATUS FOR TREATING SUBSTRATE

Samsung Electronics Co., ...

1. A substrate-treating apparatus comprising:a support unit on which a substrate is loaded;
a blade unit at a side of the support unit and configured to remove a layer on the substrate loaded on the support unit;
an optical measurement unit configured to provide light to the substrate to obtain image data, the optical measurement unit configured to,
check whether the substrate is abnormal or not, based on the image data, and
check a wear level of the blade unit; and
a controller configured to control the support unit and the optical measurement unit, the controller configured to process the image data transmitted from the optical measurement unit,
wherein the controller includes,
an interlock configured to perform an interlock operation interrupting a process performed on the substrate if an abnormal signal is detected from the image data, and
wherein the controller is configured to perform an interlock operation interrupting operation of the blade unit, based on the wear level of the blade unit.

US Pat. No. 10,217,652

HEAT TREATMENT APPARATUS, HEAT TREATMENT METHOD, AND STORAGE MEDIUM

Tokyo Electron Limited, ...

1. A heat treatment apparatus for performing a heat treatment on a coating film formed on a substrate, the apparatus comprising:a placing table provided within a processing container, and configured to place the substrate thereon;
a heater configured to heat the substrate placed on the placing table;
a top plate having a bottom surface which faces an upper surface of the placing table across a gap in the processing container, the top plate including:
a plurality of outer circumferential exhaust ports opened circumferentially along and radially within an edge portion of the bottom surface of the top plate, and configured to exhaust an inside of the processing container; and
a central exhaust port opened in a central portion at the bottom surface of the top plate such that a center of the central exhaust port coincides with a center of the substrate placed on the placing table, and configured to exhaust the inside of the processing container; and
a cylindrical shutter provided to surround the placing table and configured to block an entire circumference of the gap formed between the placing table and the top plate to form a processing space in the processing container, the cylindrical shutter including a gas supply port formed at equal intervals over an entire circumference of an inner circumferential surface of the cylindrical shutter and configured to supply gas into the processing space of the processing container, wherein the gas supply port is opened at a position lower than the substrate.

US Pat. No. 10,217,651

WASHING DEVICE

LG Display Co., Ltd., Se...

1. A washing device comprising:a plasma irradiating cleaner having a plasma irradiating unit and an air jetting unit spaced apart from the plasma irradiating unit, and configured to receive a substrate, the plasma irradiating unit further configured to remove dirt from the substrate by irradiating the substrate with plasma, and the air jetting unit having a first plurality of air output nozzles positioned adjacent to the plasma irradiating unit, the plurality of first air output nozzles configured to jet air upward against the substrate with sufficient force to assist to support the substrate in the plasma irradiating cleaner and position the substrate spaced apart from the plurality of first air output nozzles while the substrate is within the plasma irradiating cleaner;
a dirt washing assembly configured to receive the substrate from the plasma irradiating cleaner, having an upper dirt washing unit and a lower dirt washing unit separated by a space sized and dimensioned to receive the substrate and the upper and lower dirt washing units further configured to remove dirt remaining on the substrate, the upper and lower dirt washing units including a second plurality of air output nozzles positioned to jet air against the upper and lower surfaces of the substrate to assist to support the substrate in the dirt washing assembly and position the substrate spaced apart from the upper dirt washing unit and the lower dirt washing unit;
a finishing washing assembly configured to receive the substrate from the dirt washing assembly, and the finishing washing assembly further configured to wash the substrate;
a drying assembly configured to receive the substrate from the finishing washing assembly, and the drying assembly further configured to dry the substrate and to jet air upward against the substrate;
a substrate unloading assembly configured to receive the substrate from the drying assembly, and the substrate unloading assembly further configured to unload the substrate; and
a plurality of transfer rollers configured to transfer the substrate by applying a longitudinal force thereto, the plurality of transfer rollers comprising:
a first transfer roller mounted to transfer the substrate to the plasma irradiating cleaner, the first transfer roller being disposed outside the plasma irradiating cleaner;
a second transfer roller mounted between the plasma irradiating cleaner and the dirt washing assembly to transfer the substrate from the plasma irradiating cleaner to the dirt washing assembly, the second transfer roller being disposed outside the plasma irradiating cleaner;
a third transfer roller mounted between the dirt washing assembly and the drying assembly to transfer the substrate from the dirt washing assembly to the drying assembly; and
a fourth transfer roller mounted to the substrate unloading assembly to transfer the substrate from the drying assembly to the outside,
wherein the finishing washing assembly is disposed above the third transfer roller and there are no transfer rollers within the plasma irradiating cleaner or the dirt washing assembly.

US Pat. No. 10,217,650

METHODS AND APPARATUS FOR SUBSTRATE EDGE CLEANING

APPLIED MATERIALS, INC., ...

1. A method of cleaning contaminants from a substrate, the method comprising:(a) supporting a substrate atop a substrate support disposed within an inner volume of a process chamber;
(b) rotating the substrate about a central axis normal to a first side of the substrate;
(c) directing a first cleaning gas of solid and gaseous carbon dioxide from a liquid carbon dioxide source to a region of the inner volume corresponding to the position of an edge of the substrate when the substrate is supported by the substrate support; and
(d) flowing a first gas over the first side of the substrate such that a velocity of the first gas as it flows past the edge of the substrate increases as compared to the velocity of the first gas as it flows over the first side proximate a center of the substrate.

US Pat. No. 10,217,649

SEMICONDUCTOR DEVICE PACKAGE HAVING AN UNDERFILL BARRIER

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor device package, comprising;a substrate including:
a top surface defining a mounting area, and
a barrier section on the top surface and adjacent to the mounting area;
a semiconductor device mounted on the mounting area of the substrate; and
an underfill disposed between the semiconductor device and the mounting area of the substrate, wherein a contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

US Pat. No. 10,217,648

FABRICATION OF MICROFLUIDIC CHANNELS IN DIAMOND

HRL Laboratories, LLC, M...

1. A method of forming a diamond microchannel structure, the method comprising:patterning a base layer of sacrificial material on a substrate to define a location and dimensions of a microchannel;
depositing a layer of diamond using chemical vapor deposition (CVD) to cover the patterned base layer; and
selectively removing the patterned sacrificial material from underneath the CVD deposited diamond layer to form a CVD diamond microchannel on the substrate.

US Pat. No. 10,217,647

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Samsung Electronics Co., ...

1. A method of manufacturing a semiconductor device comprising:forming active patterns extending in a first direction and spaced apart from one another along a second direction perpendicular to the first direction on a substrate;
forming a polygonal mask pattern having a first width and a second width along the second direction on the active patterns;
forming an active region having the first width and the second width by executing a first etching process using the mask pattern;
forming a first cutting mask for removing a first corner rounding at which a width of the active region is the first width;
removing the first corner rounding by executing a second etching process using the first cutting mask;
forming a second cutting mask for removing a second corner rounding at which the width of the active region is changed from the first width to the second width; and
removing the second corner rounding by executing a third etching process using the second cutting mask.

US Pat. No. 10,217,646

TRANSITION METAL DRY ETCH BY ATOMIC LAYER REMOVAL OF OXIDE LAYERS FOR DEVICE FABRICATION

Intel Corporation, Santa...

1. A method of etching a film, the method comprising:reacting a surface layer of a transition metal species of a transition metal-containing film with a molecular oxidant species, wherein reacting the surface layer of the transition metal species of the transition metal-containing film with the molecular oxidant species comprises transferring oxygen from molecules having a reactive nitrogen based organic skeleton;
removing volatile fragments of the reacted molecular oxidant species to provide an oxidized surface layer of the transition metal species;
reacting the oxidized surface layer of the transition metal species with a molecular etchant; and
removing the reacted oxidized surface layer of the transition metal species and the reacted molecular etchant by volatlilization.

US Pat. No. 10,217,644

PRODUCTION OF ADHESION STRUCTURES IN DIELECTRIC LAYERS USING PHOTOPROCESS TECHNOLOGY AND DEVICES INCORPORATING ADHESION STRUCTURES

INFINEON TECHNOLOGIES AG,...

1. A semiconductor device structure, comprising:at least one semiconductor device comprising a semiconductor substrate;
a first dielectric layer having a top surface and a bottom surface,
wherein the bottom surface adjoins the semiconductor substrate;
geometric structures formed in the first dielectric layer,
wherein each of the geometric structures defines a respective blind hole in the first dielectric layer extending from the top surface to a respective intermediate surface of the first dielectric layer that is between the top surface and the bottom surface, and
at least one of the geometric structures has an undercut profile in the first dielectric layer, such that a cross-sectional gap width of the first dielectric layer increases, at least in part, from the top surface towards the respective intermediate surface; and
a conductive layer on the first dielectric layer,
wherein the conductive layer is at least located over the geometric structures and completely fills the geometric structures.

US Pat. No. 10,217,643

METHOD OF PROCESSING TARGET OBJECT

TOKYO ELECTRON LIMITED, ...

1. A method of processing a target object, the method comprising:preparing the target object including a first protrusion portion, a second protrusion portion, an etching target layer and a groove portion, the etching target layer having a region belonging to the first protrusion portion and a region belonging to the second protrusion portion, the groove portion being provided on a main surface of the target object, being provided on the etching target layer and being defined by the first protrusion portion and the second protrusion portion, and an inner surface of the groove portion being included in the main surface of the target object, and
performing a first sequence repeatedly N times (N is an integer equal to or larger than 2),
wherein the first sequence comprises:
forming a protection film conformally on the main surface of the target object in a processing vessel of a plasma processing apparatus in which the target object is accommodated; and
etching a bottom portion of the groove portion of the target object with plasma of a gas generated within the processing vessel after the forming of the protection film conformally is performed,
wherein a mask is formed on the region belonging to the first protrusion portion while the mask is not formed on the region belonging to the second protrusion portion, and
a deposition film is formed on the mask.

US Pat. No. 10,217,642

SUBSTRATE PROCESSING APPARATUS, SUBSTRATE PROCESSING METHOD AND SUBSTRATE HOLDING MEMBER

TOKYO ELECTRON LIMITED, ...

1. A substrate processing apparatus comprising:a process chamber;
a turntable provided in the process chamber and including a substrate holding region formed in a top surface along a circumferential direction of the turntable, the substrate holding region having a first depth;
a surface area increasing region provided in the top surface of the turntable around the substrate holding region and configured to increase a surface area of the top surface of the turntable to an area larger than a surface area of a flat surface by including a concavo-convex pattern in its top surface, the concavo-convex pattern having a second depth that is shallower than the first depth of the substrate holding region; and
a process gas supply unit configured to supply a process gas to the top surface of the turntable.

US Pat. No. 10,217,641

CONTROL OF CURRENT COLLAPSE IN THIN PATTERNED GAN

International Business Ma...

1. A semiconductor device comprising:a substrate having a recessed region disposed in a surface thereof, the recessed region includes a first vertical sidewall of the substrate, a second vertical sidewall of the substrate, and a horizontal surface of a semiconductor material of the substrate;
a seed layer disposed within the recessed region and directly on the horizontal surface of the semiconductor material, wherein the seed layer extends continuously from the first vertical sidewall to the second vertical sidewall of the recess region; and
a layered structure disposed on the seed layer, the layered structure comprising a buffer layer and a gallium nitride layer, wherein the buffer layer is present directly on a topmost surface of the seed layer and extends continuously from the first vertical sidewall to the second vertical sidewall, and wherein the seed layer and the layered structure have outermost vertical sidewalls that are vertically aligned to each other, wherein the first and second vertical sidewalls include a sidewall of a dielectric material and a sidewall of a topmost semiconductor layer, the sidewall of the dielectric material is between the sidewall of the topmost semiconductor layer and the horizontal surface of the semiconductor material of the substrate.

US Pat. No. 10,217,640

METHODS OF FABRICATING SEMICONDUCTOR DEVICES

Samsung Electronics Co., ...

1. A method of fabricating a semiconductor device, the method comprising:forming a first gate dielectric layer and a second gate dielectric layer on a first region and a second region included in a semiconductor substrate, respectively;
forming a first metal-containing layer on the first and second gate dielectric layers;
performing a first annealing process with respect to the first metal-containing layer;
removing the first metal-containing layer from the first region;
forming a second metal-containing layer on an entire surface of the semiconductor substrate;
performing a second annealing process with respect to the second metal-containing layer;
forming a gate electrode layer on the second metal-containing layer;
partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form a first gate pattern and a second gate pattern on the first region and the second region, respectively; and
performing a third annealing process after the removing the first metal-containing layer from the first region and before the forming the second metal-containing layer.

US Pat. No. 10,217,639

METHOD OF FORMING DRAIN EXTENDED MOS TRANSISTORS FOR HIGH VOLTAGE CIRCUITS

Cypress Semiconductor Cor...

1. A method comprising:implanting a first type of ions at a first energy level in a first drain portion of a first drain extended metal-on-semiconductor (DE_MOS) transistor in a DE_MOS region of a substrate;
implanting the first type of ions at the first energy level in a low-voltage metal-on-semiconductor (LV_MOS) region of the substrate, the LV_MOS region being located where a first LV_MOS transistor is to be formed, the implanting of the first type of ions in the LV_MOS region adjusting a voltage threshold of the first LV_MOS transistor, and the implanting of the first type of ions the first drain portion being concurrent with the implanting of the first type of ions in the LV_MOS region, wherein the first DE_MOS transistor and the first LV_MOS transistor are of an opposite type of transistors;
implanting the first type of ions at a second energy level in the first drain portion of the first DE_MOS transistor; and
subsequent to implanting the first type of ions at the second energy level in the first drain portion of the first DE_MOS transistor, forming a gate oxide of the first DE_MOS transistor.

US Pat. No. 10,217,638

METHOD FOR REMOVING CRYSTAL ORIGINATED PARTICLES FROM A CRYSTALLINE SILICON BODY USING AN ETCH PROCESS

Infineon Technologies AG,...

1. A method for removing crystal originated particles from a crystalline silicon body having opposite first and second surfaces, the method comprising:increasing a surface area of at least one of the first and second surfaces by an etch process, the etch process comprising etching a plurality of trenches into the crystalline silicon body;
oxidizing the increased surface area at a temperature of at least 1000° C. and for a duration of at least 20 minutes; and
forming at least one of: an electrically conductive electrode and semiconductor material in the plurality of trenches after the oxidizing.

US Pat. No. 10,217,637

CHIP HANDLING AND ELECTRONIC COMPONENT INTEGRATION

International Business Ma...

1. An assembly for integrating electronic elements into an electronic package assembly, comprising:a semiconductor structure including:
a device wafer comprising an array of singulated electronic elements, the singulated electronic elements including a plurality of targeted electronic elements,
a handle wafer bonded to the device wafer,
one or more first alignment markers, the targeted electronic elements being located at selected distances from the one or more first alignment markers, and
a release layer between the device wafer and the handle wafer;
a carrier assembly including one or more second alignment markers and selected surface areas configured for attaching the targeted electronic elements, the selected surface areas being configured for alignment with the targeted electronic elements when the one or more first alignment markers are aligned with the one or more second alignment markers;
an electromagnetic radiation source configured to direct electromagnetic radiation through the handle wafer, at least one of the electromagnetic radiation source and the handle wafer being configured to allow ablation of discrete, selected portions of the release layer beneath and corresponding to the targeted plurality of the singulated electronic elements using the electromagnetic radiation source;
an electronic package assembly include one or more third alignment markers and a plurality of targeted bonding sites, the selected surface areas of the carrier assembly being configured for alignment with the targeted bonding sites when the one or more second alignment markers are aligned with the one or more third alignment markers.

US Pat. No. 10,217,636

METHOD OF MANUFACTURING A SILICON CARBIDE SEMICONDUCTOR DEVICE BY REMOVING AMORPHIZED PORTIONS

Infineon Technologies AG,...

1. A semiconductor device comprising:a trench gate structure extending from a first surface into a semiconductor body,
wherein the trench gate structure fills a trench,
wherein the trench being rounded and/or chamfered along a rim section of the first surface, and
wherein, in a horizontal cross-section parallel to the first surface, the trench gate structure includes a long side, a short side and a rounded transition between the short side and the long side.