US Pat. No. 10,142,086

REPEATER AND METHODS FOR USE THEREWITH

1. A repeater device, comprising:an amplifier configured to amplify first channel signals and a reference signal to generate amplified first channel signals and an amplified reference signal, wherein the first channel signals and reference signal are extracted from a distributed antenna system;
a first transceiver configured to select one or more of the amplified first channel signals via channel selection filtration and to convert the one or more of the amplified first channel signals to a spectral segment for wireless transmission to at least one device via a first antenna of the distributed antenna system based on the amplified reference signal, wherein the amplified reference signal reduces a phase error in converting the one or more of the amplified first channel signals to the spectral segment;
a second transceiver; and
a duplexer configured to transfer at least a portion of the amplified first channel signals to the second transceiver for transmission to an other repeater device of the distributed antenna system having a second antenna and further to transfer the first channel signals to the first transceiver.

US Pat. No. 10,142,082

PRE-CODING IN OFDM

Genghiscomm Holdings, LLC...

1. A method employed by a radio transceiver, comprising:selecting a data symbol block comprising a plurality N of data symbols;
spreading the data symbol block to produce N spread symbols, wherein each spread symbol is expressible by
wherein wm is an mth one of the N spread symbols, ?m is an mth complex-valued scaling factor, sn is an nth one of the plurality N of data symbols, e is natural log, i=??1, ? is mathematical constant Pi, m and n are indices each having integer values of 0 to N?1, e?i2?mn/N expresses elements of a Discrete Fourier Transform (DFT) spreading matrix, and N is equal to a number of Orthogonal Frequency Division Multiplexing (OFDM) subcarriers assigned to the radio transceiver for transmission, where N>2;mapping each of the N spread symbols to one of the OFDM subcarriers; and
impressing each of the N spread symbols onto one of the OFDM subcarriers to generate an OFDM transmission signal comprising a superposition of data-bearing subcarriers, wherein the spreading provides the superposition with a reduced peak-to-average-power ratio.

US Pat. No. 10,142,075

METHOD AND APPARATUS FOR TRANSMITTING REFERENCE SIGNAL IN WIRELESS COMMUNICATION SYSTEM BASED ON MULTIPLE ANTENNAS

LG Electronics Inc., Seo...

1. A method for transmitting demodulation-reference signal (DM-RS) sequences to a terminal by a base station in a wireless communication system supporting 8 layers, the method comprising:grouping 8 DM-RS ports corresponding to the 8 layers into 4 antenna port groups including a first antenna port group, a second antenna port group, a third antenna port group, and a fourth antenna port group,
wherein each of the 4 antenna port groups includes two DM-RS ports;
mapping DM-RS sequences for the 8 layers to resource elements (REs) for the 4 antenna port groups based on a predetermined DM-RS pattern,
wherein REs for each of the 4 antenna port groups occupy 12 REs including a plurality of two consecutive REs in a first physical resource block (PRB) pair and a plurality of two consecutive REs in a second PRB pair,
wherein two DM-RS sequences of layers corresponding to DM-RS ports included in a same antenna port group are mapped to same REs for the same antenna port group, and the two DM-RS sequences are code division multiplexed (CDM) based on an orthogonal cover code (OCC) having a length of 2; and
transmitting DM-RS sequences for the 8 layers to the terminal through the 8 DM-RS ports,
wherein the predetermined DM-RS pattern is defined such that the first antenna port group occupies 1st and 11th subcarriers of a first slot of the first PRB pair and a second slot of the second PRB pair, and 6th subcarriers of a second slot of the first PRB pair and a first slot of the second PRB pair,
the second antenna port group occupies 6th subcarriers of the first slot of the first PRB pair and the second slot of the second PRB pair, 1st and 11th subcarriers of the second slot of the first PRB pair and the first slot of the second PRB pair,
the third antenna port group occupies 2nd and 12th subcarriers of the first slot of the first PRB pair and the second slot of the second PRB pair, and 7th subcarriers of the second slot of the first PRB pair and the first slot of the second PRB pair, and
the fourth antenna port group occupies 7th subcarriers of the first slot of the first PRB pair and the second slot of the second PRB pair, 2nd and 12th subcarriers of the second slot of the first PRB pair and the first slot of the second PRB pair.

US Pat. No. 10,142,071

DETERMINING REFERENCE SIGNAL LOCATIONS

Motorola Mobility LLC, C...

1. A method comprising:determining, by use of a processor, a number of Transmission Time Intervals (TTI) in a scheduled transmission of a plurality of TTI; and
determining one or more reference signal locations based on the number of TTI, wherein in response to one TTI in the scheduled transmission, the one or more reference signal locations are determined to be in a first predetermined TTI instance of the plurality of TTI, in response to three consecutive TTI in the scheduled transmission, the one or more reference signal locations are determined to be in the first predetermined TTI instance and a third predetermined TTI instance of the plurality of TTI, and in response to seven consecutive TTI in the scheduled transmission, the one or more reference signal locations are determined to be in the first predetermined TTI instance, the third predetermined TTI instance, and a seventh predetermined TTI instance of the plurality of TTI.

US Pat. No. 10,142,066

JITTER ANALYSIS SYSTEMS AND METHODS

Keysight Technologies, In...

1. A method comprising:generating a first detection threshold by a decision feedback equalizer, the generating comprising the decision feedback equalizer operating upon at least a first symbol present in an input signal;
detecting at least a first transition in the input signal by utilizing the first detection threshold; and
evaluating one or more timing characteristics of the input signal by evaluating at least the first transition in the input signal.

US Pat. No. 10,142,063

HYBRID AUTOMATIC REPEAT REQUEST METHOD AND RELATED APPARATUS

HUAWEI TECHNOLOGIES CO., ...

1. A hybrid automatic repeat request method, comprising:receiving a packet from a transmit end, the packet comprising N data sub-blocks, and N comprising an integer greater than or equal to two;
checking the N data sub-blocks comprised in the packet to generate a check result for each of the N data sub-blocks, the check result for each of the N data sub-blocks indicating whether each of the N data sub-blocks is correct or incorrect;
buffering a first portion of the N data sub-blocks that have the check result indicating that the data sub-blocks are correct;
discarding a second portion of the N data sub-blocks that have the check result indicating that the data sub-blocks are incorrect;
generating feedback information according to the check result for each of the N data sub-blocks, the feedback information comprising N check characters and N serial numbers corresponding to the N data sub-blocks, each of the N check characters comprising an acknowledgment character (ACK) or a negative acknowledgment character (NACK), and each of the N serial numbers differentiating and identifying one of the N data sub-blocks;
returning the feedback information to the transmit end;
receiving a second packet from the transmit end that comprises retransmitted data sub-blocks corresponding to the second portion of the N data sub-blocks that were discarded; and
assembling the first portion of the N data sub-blocks with the data sub-blocks from the second packet to form a third packet having correct data.

US Pat. No. 10,142,057

METHOD AND DEVICE FOR RECEIVING DATA

LG Electronics Inc., Seo...

1. A method for receiving data in a wireless communication system, the method comprising:receiving, by a wireless device, a code block from one cell among a plurality of configured cells; and
upon detecting a decoding error of the code block, storing, by the wireless device, a part or all of the code block wherein the number of coded bits of the code block stored in the reception buffer is determined based on a maximum modulation order supported by the cell from which the code block is received, and
wherein the plurality of configured cells comprise at least one high order cell supporting a modulation order higher than a reference modulation order and at least one low order cell supporting a modulation order lower than or equal to the reference modulation order.

US Pat. No. 10,142,056

TRANSMISSION METHOD, TRANSMITTER, RECEPTION METHOD, AND RECEIVER

PANASONIC CORPORATION, O...

1. A transmission method for transmitting one coded block over NRF (NRF is an integer of 2 or more) frequency channels and NC (NC is an integer of 1 or more) cycles by dividing the one coded block into a plurality of slices, the transmission method comprising:coding, using transmission circuitry, a data block by using a quasi-cyclic low-density parity check (QC LDPC) code to generate a coded block, the coded block including a number N of cyclic blocks, each of the N cyclic blocks including a number Q of bits, each of the N cyclic blocks being divided into floor(N/M) sections and rem{N,M} cyclic blocks, each of the floor(N/M) sections including M cyclic blocks, where M is an integer;
generating, using the transmission circuitry, a D-dimensional constellation block including a number D of components from (Q×M) bits of corresponding one of the floor(N/M) sections, each of the D number of components being a real value;
generating, using the transmission circuitry, a D-dimensional rotation constellation block including D rotation components from each of the D-dimensional constellation blocks of the sections by using an orthogonal matrix of D of rows and D columns, each of the D rotation components being a real value;
mapping, using the transmission circuitry, each of the D rotation components of the D-dimensional rotation constellation blocks of each of the floor(N/M) sections to one frequency channel of the NRF frequency channels; and
transmitting the coded block,
wherein the mapping of each of the D rotation components to the one frequency channel is performed by:
in each of the floor(N/M) sections, writing the D rotation components, in a column direction, in a real interleaver matrix of D rows and Q columns and converting the real interleaver matrix into a complex interleaver matrix of D rows and (Q/2) columns in which the D rotation components of two consecutive columns in an identical row are replaced with a cell that is of one complex value;
coupling the complex interleaver matrix of D rows and (Q/2) columns for each of the floor(N/M) sections to generate a combined complex interleaver matrix of ({floor(N/M)}×D) rows and (Q/2) columns by arranging the complex interleaver matrix of D rows and (Q/2) columns for each of the floor(N/M) sections;
applying a cyclic shift to each row of the combined complex interleaver matrix by shifting cells allocated to the row using a cyclic shift value of (k×floor(Q/max{D,(NRF×NC)}/2)); and
mapping cells into a number of columns defined by Q/2 multiplied by NRF×NC while sequentially repeating the NRF frequency channels, and
the cyclic shift is performed such that k has a value equal to 2 or more at least once in each of the floor(N/M) sections, the value of k being predetermined from values ranging from 0 to max{D,(NRF×NC)}?1.

US Pat. No. 10,142,044

MANAGED TIMING ENGINE

QULSAR, INC., San Jose, ...

1. A method, comprising operating a managed timing engine that providesa physical-layer timing output aligned to a physical-layer input timing reference using a phase locked loop, the physical-layer input timing reference selected from a multiplicity of physical-layer input timing references, and
a packet-based clock providing timing outputs synchronized to a packet-layer input timing reference,
wherein the managed timing engine has programmable multipier ratios for each of the physical-layer references,
wherein a time-stamping clock in the packet-based clock is derived from a physical-layer clock,
wherein the packet-based clock timing outputs include a 1-PPS signal with a programmable delay offset and
wherein at least one of the multiplicity of physical-layer input timing references that are not selected is measured against the physical-layer input timing reference that is selected using a digital phase lock loop where divider and multiplier factors are chosen to generate two nominal comparison frequency versions that are compared using a clock phase comparator and a phase differences signal is filtered to generate a correction term for a programmable multiplier.

US Pat. No. 10,142,036

CONFIGURATION SUB-SYSTEM FOR TELECOMMUNICATION SYSTEMS

Andrew Wireless Systems G...

1. A configuration sub-system comprising:an input communicatively coupleable to a base station;
a test signal generator integrated into the configuration sub-system, wherein the configuration sub-system is configured to switch between a first mode and a second mode, wherein in the first mode the configuration sub-system is configured to provide a test signal generated by the test signal generator to a downlink path, wherein in the second mode the configuration sub-system is configured to provide an RF downlink signal that is received via the input from the base station to the downlink path and deactivate the test signal generator, wherein the configuration sub-system is configured to provide the RF downlink signal to the downlink path only in the second mode;
a power measurement device integrated into the configuration sub-system, the power measurement device being configured to:
measure a test signal power of the test signal at a measurement point in the downlink path, and
measure a downlink signal power of the RF downlink signal at the measurement point; and
a controller configured to normalize signals transmitted using a distributed antenna system via the configuration sub-system by adjusting a downlink path gain for the downlink path based on the test signal power measured by the power measurement device, wherein the distributed antenna system is configured to transmit the RF downlink signal using the downlink path gain as adjusted by the controller.

US Pat. No. 10,142,033

COMMUNICATION APPARATUS AND COMMUNICATION METHOD FOR SUCCESSIVE QUANTUM KEY DISTRIBUTION

Korea Institute of Scienc...

11. A communication method performed by a communication apparatus, the communication method comprising:receiving, from an other communication apparatus coupled to the communication apparatus, a synchronization signal and a first quantum signal generated by a first light source of the other communication apparatus;
detecting the synchronization signal received from the other communication apparatus;
generating, by a second light source, a decoy signal to be added to a second quantum signal, generated by reflecting the first quantum signal off a reflector, that is to be sent to the other communication apparatus in response to the first quantum signal being generated and received from the first light source of the other communication apparatus according to a result of the detecting of the synchronization signal; and
adding the generated decoy signal to pairs of photon pulses in second the quantum signal based on the result of the detecting of the synchronization signal, to monitor hacking of an eavesdropper in a plug and play quantum key distribution.

US Pat. No. 10,142,031

APPARATUS, METHOD AND COMPUTER PROGRAM FOR A RECEIVER OF AN OPTICAL SIGNAL

ALCATEL LUCENT, Boulogne...

1. An apparatus for a receiver of an optical signal being configured to:input digitized samples of the optical signal at a first sampling rate;
filter the digitized samples based on a plurality of filter coefficients to obtain filtered samples of the optical signal at a second sampling rate, the second sampling rate being different from the first sampling rate; and
output the filtered samples of the optical signal at the second sampling rate;
wherein the apparatus is further configured to:
filter, via an adaptive filter, the digitized samples at the first sampling rate;
base an updating of coefficients of the adaptive filter on a fraction of output samples of the adaptive filter;
select samples which are used to update the coefficients of the adaptive filter as samples of the filtered samples of the optical signal; and
determine other samples of the filtered samples of the optical signal.

US Pat. No. 10,142,018

VISIBLE LIGHT COMMUNICATION VIA SOLID STATE LIGHTING DEVICES

Cree, Inc., Durham, NC (...

1. A solid-state lighting fixture comprising:a first plurality of solid-state light elements configured to emit visible light at a first wavelength;
a second plurality of solid-state light elements configured to emit the visible light at a second wavelength, which is different than the first wavelength; and
a light controller modulator configured to simultaneously:
modulate the visible light emitted from the first plurality of solid-state light elements, to emit a modulation pattern of the emitted visible light that communicates a first subset of data while being undetectable to a human eye; and
modulate the visible light emitted from the second plurality of solid-state light elements, to emit the modulation pattern of the emitted visible light that communicates a second subset of data while being undetectable to the human eye.

US Pat. No. 10,142,015

METHOD AND APPARATUS FOR DETECTING SHARED RISK LINK GROUPS

Alibaba Group Holding Lim...

2. A method of detecting shared risk link groups, the method comprising:injecting probe beams into a first test link and a second test link;
receiving a first backlight and a second backlight of the probe beams back from the first test link and the second test link, respectively;
filtering the first backlight with a first polarizer such that light with a first designated direction can pass through the first polarizer, and filtering the second backlight with a second polarizer such that light with a second designated direction can pass through the second polarizer;
detecting and recording a first time-varying response of a power level of the light that passes through the first polarizer, and detecting and recording a second time-varying response of a power level of the light that passes through the second polarizer;
calculating a resemblance value for the first time-varying response and the second time-varying response by:
associating the first and second time-varying responses with a timeline, transforming the timeline into a series of discrete time points, and associating a first power value from the first response and a second power value from the second response with each discrete time point; and
calculating the resemblance value from the first power value and the second power value associated with each discrete time point; and
determining, based on the resemblance value, whether the first test link and the second test link are located in a same shared risk link group.

US Pat. No. 10,142,012

CO-ORBITING LASER COMMUNICATIONS RELAY SATELLITE

THE AEROSPACE CORPORATION...

1. A relay satellite for relaying data from a client satellite to thereby reduce power and pointing accuracy requirements of the client satellite, said relay satellite comprising:a short-range communications link configured to receive data from the client satellite; and
a long-range communications link configured to retransmit the received data to a ground station or another satellite,
wherein the relay satellite is deployed in one of (a) a quasi-orbit with respect to the client satellite such that the relay satellite and the client satellite can be kept within a pre-determined distance or (b) the same orbit as the client satellite but with an in-track offset that keeps the relay satellite and the client satellite within a pre-determined distance;
wherein the short-range communications link can be used to receive data from the client satellite when the client satellite is within a pre-determined distance of the relay satellite;
wherein the relay satellite is deployable from the client satellite after the client satellite reaches orbit.

US Pat. No. 10,142,010

REPEATER AND METHODS FOR USE THEREWITH

1. A repeater device, comprising:an amplifier configured to amplify first channel signals to generate amplified first channel signals, wherein the first channel signals are extracted via a first coupler from a first transmission medium of a distributed antenna system as first guided electromagnetic waves, wherein the first guided electromagnetic waves propagate along the first transmission medium without requiring an electrical return path;
a channel selection filter configured to select one or more of the amplified first channel signals for wireless transmission to at least one device via a first antenna of the distributed antenna system; and
a channel duplexer configured to transfer to the distributed antenna system via a second coupler, at least a portion of the amplified first channel signals for use by an other repeater device of the distributed antenna system having a second antenna and further to transfer the first channel signals to the channel selection filter, wherein the second coupler launches second guided electromagnetic waves conveying the amplified first channel signals on a second transmission medium of the distributed antenna system and wherein the second guided electromagnetic waves propagate along the second transmission medium without requiring an electrical return path.

US Pat. No. 10,142,005

BEAMFORMING TRAINING

LG ELECTRONICS INC., Seo...

1. A method for performing beamforming training in a wireless local area network (WLAN), the method performed by a responding device including a processor, a transceiver, a first array antenna and second array antenna, the method comprising:receiving a plurality of beacon frames from an initiating device through a plurality of sectors during a transmission (TX) beamforming (BF) interval,
wherein the plurality of sectors correspond to a plurality of transmit antenna patterns for the initiating device;
transmitting a first sector sweep feedback to the initiating device during a reception (RX) BF interval,
wherein the first sector sweep feedback includes a first antenna identifier (ID) indicating the first array antenna and a first TX ID indicating a first TX sector determined by the responding device for the first array antenna based on the plurality of beacon frames;
determining whether a first sector sweep acknowledgement (ACK) is received from the initiating device in response to the first sector sweep feedback; and
transmitting a second sector sweep feedback including a redundant feedback to the initiating device during the RX BF interval if the first sector sweep ACK is not received,
wherein the second sector sweep feedback includes a second antenna ID indicating the second array antenna and a second TX ID indicating a second TX sector determined by the responding device for the second array antenna based on the plurality of beacon frames, and
wherein the redundant feedback includes a third antenna ID indicating the first array antenna and a third TX ID indicating the first TX sector.

US Pat. No. 10,142,001

METHOD AND SYSTEM FOR HYBRID RADIO FREQUENCY DIGITAL BEAMFORMING

Maxlinear, Inc., Carlsba...

1. An electronic device, the device comprising:one or more circuits coupled to an antenna array comprising antennas arranged along first and second directions, said one or more circuits being operable to:
beamform signals in an analog domain along the first direction of the antenna array; and
beamform signals in a digital domain along the second direction of the antenna array, with wider beam steering in the second direction as compared to narrower beam steering in the first direction.

US Pat. No. 10,141,999

REFERENCE SIGNAL TRACKING IN A WIRELESS COMMUNICATION SYSTEM

TELEFONAKTIEBOLAGET LM ER...

1. A method performed by network equipment in a wireless communication system, the method comprising:transmitting a tracking process base signal to a wireless device;
responsive to receiving a report from the wireless device indicating reception of the tracking process base signal, configuring the wireless device with a tracking process for the wireless device to track a reference type signal by tuning a receiver configuration with which the wireless device received the tracking process base signal; and
transmitting a reference signal to the wireless device and identifying to the wireless device that the reference signal is to be tracked with the configured tracking process.

US Pat. No. 10,141,997

POWER AMPLIFIER ADJUSTMENT FOR TRANSMIT BEAMFORMING IN MULTI-ANTENNA WIRELESS SYSTEMS

Marvell World Trade Ltd.,...

1. A method, comprising:applying, at one or more integrated circuits, one or more beamsteering matrices to one or more signals to produce a plurality of signals to be transmitted via multiple antennas;
after applying the one or more beamsteering matrices to the one or more signals, providing the plurality of signals to a plurality of power amplifiers coupled to the multiple antennas;
determining, at the one or more integrated circuits, signal energies for the plurality of signals provided to the plurality of power amplifiers;
determining, at the one or more integrated circuits, a highest signal energy among the determined signal energies;
determining, at the one or more integrated circuits, respective measures of relative signal energies corresponding to one or more other signal energies among the determined signal energies relative to the determined highest signal energy; and
adjusting, based on the determined respective measures of relative signal energies, output power levels of the plurality of power amplifiers to make the output power levels of the plurality of power amplifiers equal.

US Pat. No. 10,141,990

METHOD FOR DETERMINING PRECODING MATRIX INDICATOR, USER EQUIPMENT, AND BASE STATION

HUAWEI TECHNOLOGIES CO., ...

1. A method for determining a precoding matrix indicator, comprising:receiving a first reference signal set sent by a base station, wherein the first reference signal set is associated with a user equipment-specific matrix set that includes at least two matrices;
selecting a precoding matrix based on the first reference signal set, wherein the precoding matrix w is a product of two matrices W1 and W2, wherein W=W1W2;
wherein the matrix W1 is a block diagonal matrix that comprises at least two block matrices, each block matrix X is a function of matrix A in the user equipment-specific matrix set or matrix B in the user equipment-specific matrix set, wherein the Matrix W2 is used for selection or weighted combination of column vectors in the matrix W1, wherein the precoding matrix w has the following matrix structure:

wherein []T is a matrix transpose, both M and N are positive integers, and ?, ? and ? are phase shifts; and
sending a precoding matrix indicator (PMI) to the base station, wherein the PMI corresponds to the selected precoding matrix.

US Pat. No. 10,141,980

WIRELESS POWER TRANSMISSION SYSTEM, AND COMMUNICATION AND PROTECTION METHODS FOR THE SAME

MINEBEA MITSUMI INC., Na...

1. A wireless power transmission system comprising a power supply device and a power receiving device,the power supply device comprising:
a power supply coil wirelessly transmitting electric power;
an inverter driving the power supply coil;
a first radio unit performing radio communication with the power receiving device; and
a first processor controlling the first radio unit and the inverter, and
the power receiving device comprising:
a resonant circuit including a power receiving coil wirelessly receiving electric power from the power supply coil of the power supply device and a capacitor to generate a resonant voltage;
a rectifying circuit rectifying the resonant voltage to output a rectified voltage;
a second radio unit performing radio communication with the first radio unit included in the power supply device; and
a second processor controlling the second radio unit,
wherein the second processor transmits a communication packet to the power supply device in a predetermined period of time, the communication packet including information about a rectified voltage value generated based on the rectified voltage and a circulation index value indicating transmission sequence and
the first processor outputs a signal according to the rectified voltage value included in the communication packet every time the first processor receives the communication packet without delay.

US Pat. No. 10,141,974

HIGH-CAPACITY FHSS-MA DEVICES AND METHODS

Shai Waxman, Sunnyvale, ...

1. A Frequency Hopped Spread Spectrum (FHSS) signals wireless receiver apparatus comprising:an antenna that receives a FHSS-MA signal comprising multiple FHSS signals, and
a radio frequency (RF) synthesizer that generates a synthesized radio frequency, and
a RF downconverter that down-converts the FHSS-MA signal using the synthesized radio frequency to an intermediate frequency (IF) signal, and
at least one wide band select filter with bandwidth greater-than at least 5 times the bandwidth of each of the FHSS signals, that filters the IF signal to reject out-of-band interference and outputs a filtered signal, and
at least one analog to digital converter that converts the filtered signal to a digitized signal, and
a I/Q imbalance correction circuit that inputs the digitized signal and outputs an array of multiple FHSS intermediate frequency (IF) I and Q signals, using an array of coefficients dynamically selected from a pre-populated coefficients memory as a function of the FHSS signals' center frequencies.

US Pat. No. 10,141,968

DEVICE FOR REFLECTING, DEFLECTING, AND/OR ABSORBING ELECTROMAGENTIC RADIATION EMITTED FROM AN ELECTRONIC DEVICE AND METHOD THEREFOR

ROWTAN TECHNOLOGIES, LLC,...

1. A device for deflecting radio frequency (RF) radiation away from a user of a mobile phone comprising:a metallic plate configured to be positioned between the mobile phone and at least one of a decorative or protective cover, the metallic plate positioned over a rear surface of the mobile phone, wherein the metallic plate is removable and non-permanently attached to the mobile phone and the at least one of a decorative or protective cover and wherein the metallic plate includes:
a copper plate; and
a powder coating formed over the copper plate.

US Pat. No. 10,141,967

VIRTUAL NETWORK INTERFACE CONNECTIVITY

Ford Global Technologies,...

1. A system comprising:a mobile device programmed to
receive a message from a vehicle computing platform via remote process communication (RPC),
update an origin address of the message to indicate the mobile device,
send the message to a destination address of the message,
receive a response message from the destination,
update a destination address of the response message to indicate the computing platform, and
send the response message to the computing platform via the RPC.

US Pat. No. 10,141,961

PASSIVE INTERMODULATION CANCELLATION

NanoSemi, Inc., Waltham,...

1. A method for enhancing a received signal to remove distortion components of a concurrently transmitted signal, the method comprising:receiving a reference signal corresponding to a transmit signal transmitted in a radio frequency transmission band;
receiving via receiving circuitry a received signal acquired in a radio frequency reception band concurrently with transmission of the transmit signal in the transmit frequency band, wherein the received signal includes a distortion component of the transmit signal, and wherein the transmit frequency band and the receive frequency band are non-overlapping bands;
upsampling the reference signal to yield an upsampled transmit signal, and upsampling the received signal to yield an upsampled received signal, wherein the upsampled reference signal and the upsampled received signal have a same sampling rate, and wherein a relative frequency between the upsampled reference signal and the upsampled received signal matches a relative frequency between the transmit frequency band and the receive frequency band;
passing the upsampled reference signal to a configurable predictor configured with predictor parameters, the configurable predictor providing an upsampled distortion signal determined from the upsampled reference signal as input;
downsampling the upsampled distortion signal to yield a distortion signal;
enhancing the received signal using the distortion signal by removing components from the received signal corresponding to the distortion signal;
correlating the upsampled distortion signal and the upsampled received signal to determine a relative delay, wherein upsampling the reference signal includes synchronizing the upsampled reference signal and the upsampled received signal according to the relative delay; and
estimating the parameters for the predictor using the upsampled reference signal and the upsampled received signal.

US Pat. No. 10,141,957

RADIO FREQUENCY FRONT END CIRCUITRY WITH REDUCED INSERTION LOSS

Qorvo US, Inc., Greensbo...

1. Circuitry comprising:a primary antenna node and a secondary antenna node;
a first set of input/output nodes, each associated with radio frequency (RF) signals within a first RF frequency band;
a second set of input/output nodes, each associated with RF signals within a second RF frequency band;
a first diplexer configured to separate RF signals within the first RF frequency band from RF signals within a first subset of the second RF frequency band;
a second diplexer configured to separate RF signals within the first RF frequency band from RF signals within a second subset of the second RF frequency band;
switching circuitry coupled between the primary antenna node, the secondary antenna node, the first set of input/output nodes, the second set of input/output nodes, the first diplexer, and the second diplexer; and
means for controlling the switching circuitry configured to cause the switching circuitry to:
in a carrier aggregation mode of operation between RF signals within the first RF frequency band and RF signals within the second RF frequency band, couple at least one of the first set of input/output nodes and at least one of the second set of input/output nodes to one of the primary antenna node and the secondary antenna node via one of the first diplexer and the second diplexer such that an insertion loss due to switching elements in the path between the at least one of the first set of input/output nodes and the primary antenna node is between 0.575 dB and 0.9 dB; and
in a non-carrier aggregation mode of operation, couple at least one of the first set of input/output nodes and the second set of input/output nodes to one of the primary antenna node and the secondary antenna node such that the first diplexer and the second diplexer are bypassed and an insertion loss due to switching elements in the path between the at least one of the first set of input/output nodes and the primary antenna node is between 0.625 dB and 0.9 dB.

US Pat. No. 10,141,955

METHOD AND APPARATUS FOR SELECTIVE AND POWER-AWARE MEMORY ERROR PROTECTION AND MEMORY MANAGEMENT

International Business Ma...

1. A method for providing selective error protection for a memory in a computing system, the method comprising:predicting a number of future errors likely to occur in at least one portion of the memory;
obtaining an active error correcting code (ECC) configuration for the at least one portion of the memory;
determining whether the active ECC configuration is sufficient to correct the number of predicted future errors in the at least one portion of the memory;
at least when the active ECC configuration is insufficient, determining whether data in the at least one portion of the memory is critical to an application running on the computing system;
when the data is not critical, tolerating corruption of the data; and
when the data is critical, determining whether a stronger ECC level is available and, when the stronger ECC level is available, increasing a strength of the active ECC configuration for the at least one portion of the memory.

US Pat. No. 10,141,950

LOW DENSITY PARITY CHECK DECODER

1. A low density parity check (LDPC) code decoder, comprising:decoding circuitry configured to process blocks of an LDPC matrix, the decoding circuitry comprising:
a control unit that controls processing by the decoding circuitry, the control unit configured to cause the decoding circuitry to process blocks of a layer of the LDPC matrix out of order,
wherein the control unit is configured to cause the decoding circuitry to process each block of the LDPC matrix in processing substeps comprising:
an R new update substep that provides an R new message, wherein the R new message is produced for a block of a different layer of the matrix from a layer containing a block currently being processed;
an R old update substep that selects an R old message, wherein the R old message is produced for a layer of the matrix currently being processed;
a P message substep that generates updated P messages;
a Q message substep that computes variable node messages (Q messages); and
a partial state substep that updates partial state of a block row based on Q messages computed for the block (check node unit (CNU) Partial state processing).

US Pat. No. 10,141,948

DELTA-SIGMA MODULATOR, ANALOG-TO-DIGITAL CONVERTER AND ASSOCIATED SIGNAL CONVERSION METHOD BASED ON MULTI STAGE NOISE SHAPING STRUCTURE

MediaTek Inc., Hsin-Chu ...

1. A delta-sigma modulator, for digitizing a first stage input, comprising:a first signal converter, comprising:
a first input summer, for summing a first converted output and the first stage input to generate a first delta signal;
a first loop filter, coupled to the first input summer, for filtering the first delta signal to generate a first sigma signal;
a noise shaping quantizer, coupled to the first loop filter, for quantizing the first sigma signal to generate the first converted output, and shaping a first stage quantization error to generate a second stage input, wherein the first stage quantization error is inherent in quantization operation of the noise shaping quantizer, and the first stage input and the second stage input are analog signals;
a second signal converter, for converting the second stage input to a second converted output; and
a digital cancellation logic, coupled to the first input summer, the noise shaping quantizer and the second signal converter for generating a digital output according to the first converted output and the second converted output,
wherein the noise shaping quantizer comprises:
a first inner summer, coupled to the first loop filter, for summing the first converted output and the first sigma signal to generate a first inner summation signal, wherein the first inner summation signal is used as the second stage input;
a noise shaping filter, coupled to the first inner summer, for filtering the first inner summation signal to generate a noise shaped signal;
a second inner summer, coupled to the first loop filter, the noise shaping filter and the first inner summer, for summing the noise shaped signal and the first sigma signal to generate a second inner summation signal; and
a first noise shaping quantizer, coupled to the first inner summer, the second inner summer and the digital cancellation logic, for quantizing the second inner summation signal to generate the first converted output, wherein the first stage quantization error is generated by the first noise shaping quantizer.

US Pat. No. 10,141,945

RADIO FREQUENCY FLASH ADC CIRCUITS

Maxlinear Asia Singapore ...

1. A system, the system comprising:a plurality of capacitors, a first port of each of the plurality of capacitors being operably coupled to a radio frequency (RF) input;
a plurality of resistors, a first port of each of the plurality of resistors being operably coupled to a reference level of a plurality of reference levels, a second port of each of the plurality of resistors being operably coupled to a second port of each of the plurality of capacitors; and
a sampling circuit operably coupled to the second port of each of the plurality of resistors, wherein the sampling circuit is operable to produce a plurality of digital outputs.

US Pat. No. 10,141,944

METHOD AND SYSTEM FOR BROADBAND ANALOG TO DIGITAL CONVERTER TECHNOLOGY

MAXLINEAR, INC., Carlsba...

1. A method, comprising:in an electronic device that performs analog-to-digital conversion:
generating a distorted digital signal by sampling an output from a non-linear analog frontend;
generating a corrected digital signal by applying a compensation signal to said distorted digital signal; and
generating said compensation signal according to a non-linearity estimation and a spectral analysis of said corrected digital signal.

US Pat. No. 10,141,943

HIGH SPEED ACQUISITION SYSTEM FOR PHASE LOCKED LOOPS

TELEDYNE DEFENSE ELECTRON...

1. A signal generator, comprising:a voltage window generator to receive an analog frequency select signal from a digital-to-analog converter (DAC) and to generate a first reference threshold voltage and a second reference threshold voltage based on the analog frequency select signal;
a window comparator coupled to the voltage window generator, the window comparator to receive a voltage controlled oscillator (VCO) tuning voltage from a phase locked loop (PLL), receive the first and second reference threshold voltages from the voltage window generator, and generate a first steering current control signal and a second steering current control signal; and
a steering current circuit coupled to the window comparator, the steering current circuit to receive the first and second steering current control signals to control a steering current coupled to a PLL and apply a phase comparator/detector signal to an PLL based on the first and second steering current control signals.

US Pat. No. 10,141,942

APPARATUSES AND METHODS FOR PROVIDING FREQUENCY DIVIDED CLOCKS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first circuit configured to provide a first intermediate clock responsive, at least in part, to a first input clock, the first intermediate clock being lower in frequency than the first input clock;
a second circuit configured to provide a second intermediate clock and a third intermediate clock responsive, at least in part, to a second input clock, the second intermediate clock being complementary to the third intermediate clock and lower in frequency than the second input clock; and
a third circuit configured to select and provide as an output clock one of the second and third intermediate clocks responsive, at least in part, to the first and second intermediate clocks, wherein the third circuit comprises:
a delay circuit configured to delay the first intermediate clock to produce a delayed intermediate clock;
a phase detector configured to compare a phase of the delayed intermediate clock and the second intermediate clock; and
a multiplexer coupled to receive the second and third intermediate clocks, the multiplexer configured to select one of the second and third intermediate clocks responsive, at least in part, to an output from a phase detector, the multiplexer comprising:
a first logic gate including a first input coupled to receive the second intermediate clock;
a first inverter circuit including an output coupled to a second input of the first logic gate;
a second logic gate including a first input coupled to receive the third intermediate clock;
a second inverter circuit including an input coupled to an output of the first inverter circuit and further including an output coupled to a second input of the second logic gate; and
a third logic gate coupled to receive outputs of the first and second logic gates and including an output from which the output clock is provided.

US Pat. No. 10,141,940

FORWARDED CLOCK RECEIVER BASED ON DELAY-LOCKED LOOP

1. A delay-locked loop comprising:a voltage-controlled delay line generating a clock signal; and
a phase detector obtaining a first sample group by sampling a data signal in at least two positions at a unit interval based on the clock signal and a second sample group by sampling the data signal in at least two positions at the unit interval based on the clock signal, wherein a difference between the positions in which the second sample group is obtained and the positions in which the first sample group is obtained is a half of the unit interval,
selecting, for a first mode, the first sample group as an edge sample of the data signal and the second sample group as a data sample of the data signal, and for a second mode, the first sample group as the data sample of the data signal and the second sample group as the edge sample of the data signal, and
controlling the voltage-controlled delay line by toggling between the first mode and the second mode.

US Pat. No. 10,141,939

CONFIGURABLE COMPUTING ARRAY USING TWO-SIDED INTEGRATION

ChengDu HaiCun IP Technol...

1. A configurable computing-array die, comprising:a semiconductor substrate having a first side and a second side;
an array of configurable computing elements including first and second configurable computing elements disposed on said first side of said semiconductor substrate, wherein said first configurable computing element comprises a first memory for storing a first look-up table (LUT) for a first math function; and, said second configurable computing element comprises a second memory for storing a second LUT for a second math function;
an array of configurable logic elements including a configurable logic element disposed on said second side of said semiconductor substrate, wherein said configurable logic element selectively realizes a logic function from a logic library;
a plurality of through-substrate vias through said semiconductor substrate for coupling said configurable computing elements and said configurable logic elements;
whereby said configurable computing-array die realizes a complex math function by programming said configurable computing elements and said configurable logic elements, wherein said complex math function is a combination of at least said first and second math functions.

US Pat. No. 10,141,937

PULSE-WIDTH MODULATION (PWM) CONTROL LOOP FOR POWER APPLICATION

ANDAPT, INC., San Jose, ...

1. A method comprising:receiving error signals from a signal wrapper of a programmable fabric, wherein the programmable fabric and the signal wrapper are integrated in a programmable logic device (PLD);
looking up one or more lookup tables storing rows of pre-calculated data and obtaining a matching pre-calculated data corresponding to the error signals; and
generating a compensated output signal using the matching pre-calculated data to drive a switch of a power regulator,
wherein the pre-populated data stored in the one or more lookup tables are programmably changed by programming a plurality of parameters of the programmable fabric and loading the pre-populated data to the one or more lookup tables via the signal wrapper, and
wherein the PLD comprises a high voltage power transistor, and the PLD is configured as the power regulator by configuring the high voltage power transistor, and wherein the compensated output signal is a pulse width of a pulse-width modulation (PWM) signal of a digital filter for driving a switch of the high voltage power transistor.

US Pat. No. 10,141,934

HIGH SPEED LEVEL-SHIFTER

Taiwan Semiconductor Manu...

1. A level shifter circuit, comprising:a latch with a first plurality of transistors and a second plurality of transistors, wherein drains of the second plurality of transistors are electrically connected to a logic low voltage pin;
a third plurality of transistors operatively connected to the latch;
a fourth plurality of transistors operatively connected between the third plurality of transistors and ground; and
a plurality of capacitors operatively connected between the latch and the gates of the fourth plurality of transistors.

US Pat. No. 10,141,928

QUANTUM LIMITED JOSEPHSON AMPLIFIER WITH SPATIAL SEPARATION BETWEEN SPECTRALLY DEGENERATE SIGNAL AND IDLER MODES

INTERNATIONAL BUSINESS MA...

1. A system for remotely entangling qubits via measurement, the system comprising:a Josephson parametric converter (JPC);
a first qubit-resonator system connected to the JPC, the first qubit-resonator system including a first qubit coupled to a first readout resonator; and
a second qubit-resonator system connected to the JPC, the second qubit-resonator system including a second qubit coupled to a second readout resonator, wherein the JPC is configured to remotely entangle the first qubit and the second qubit by reading out both the first and the second readout resonators at a frequency X.

US Pat. No. 10,141,924

SEMICONDUCTOR CIRCUIT, VOLTAGE DETECTION CIRCUIT, AND VOLTAGE DETERMINATION CIRCUIT

LAPIS SEMICONDUCTOR CO., ...

1. A semiconductor circuit comprising:a PMOS transistor that includes a first source connected to a power supply, a first drain, and a first gate to which a fixed potential is supplied;
an output circuit that outputs a first output signal, which is a reset signal or a power-on signal, and that outputs a second output signal according to a potential of the first drain;
a first constant current source connected to the first drain; and
a control circuit including an NMOS transistor that includes a second source to which a fixed potential is supplied, a second drain connected to the first drain, and a second gate to which the second output signal from the output circuit is applied,
wherein, according to the second output signal which is output from the output circuit, the control circuit is configured to control the NMOS transistor to increase a reference current flowing in the PMOS transistor such that a threshold voltage of the PMOS transistor increases in a case in which the power supply is in a rising state, and to control the NMOS transistor to decrease the reference current flowing in the PMOS transistor such that the threshold voltage of the PMOS transistor decreases in a case in which the power supply is in a falling state.

US Pat. No. 10,141,919

RESOLUTION-ENHANCING CMOS ALL-DIGITAL PULSE-MIXING METHOD AND DEVICE THEREOF

National Kaohsiung First ...

1. A CMOS all-digital pulse-mixing method comprising:providing a plurality of odd combination positions and a plurality of even combination positions on a basic element sequence which is formed from a series of basic elements;
providing a plurality of homogeneous logic elements, at least one first element parallel connection set and at least one second element parallel connection set for forming an all-digital pulse-mixing device;
arranging the at least one first element parallel connection set as an odd-positioned element parallel connection set, with the at least one first element parallel connection set having a first parallel connection number of first logic elements;
arranging the at least one second element parallel connection set as an even-positioned element parallel connection set, with the at least one second element parallel connection set having a second parallel connection number of second logic elements;
serially connecting the at least one first element parallel connection set with a first predetermined position of the plurality of odd combination positions and serially connecting the at least one second element parallel connection set with a second predetermined position of the plurality of even combination positions; and
utilizing the at least one first element parallel connection set and the at least one second element parallel connection set to stretch or shrink a pulse signal, with mixing a first degree of pulse stretching and a second degree of pulse shrinking to generate a stretched pulse signal or a shrunk pulse signal.

US Pat. No. 10,141,914

OSCILLATION CIRCUIT

Kabushiki Kaisha Toshiba,...

1. An oscillation circuit comprising:a delay circuit that includes a first inverter having an input terminal connected to a first node; and
a delay adjustment circuit including a first current supply path and a second current supply path through which the first node is charged in response to an output signal of the delay circuit, wherein,
during charging of the first node, a current with positive temperature characteristics is supplied to the first node through the first current supply path, and a current with negative temperature characteristics is supplied to the first node through the second current supply path, and
the second current supply path includes a source-drain path of an NMOS transistor having a gate to which a bias voltage with negative temperature characteristics is applied.

US Pat. No. 10,141,909

METHOD AND APPARATUS FOR DUAL NOTCH RIPPLE FILTERING

GENERAL ELECTRIC COMPANY,...

1. An apparatus comprising:a self-coupled transformer having first, second, and third windings that are operatively connected in series between higher and lower potential input terminals, with the second winding connected out-of-phase to the first and third windings;
a first band stop filter connected in series between the second and third windings of the self-coupled transformer;
a first tuning capacitor connected in parallel across the second winding of the self-coupled transformer; and
output terminals operatively connected between the first and second windings and between the second and third windings.

US Pat. No. 10,141,908

MULTI-DENSITY MIM CAPACITOR FOR IMPROVED PASSIVE ON GLASS (POG) MULTIPLEXER PERFORMANCE

QUALCOMM Incorporated, S...

1. A passive on glass (POG) device, comprising:a spiral inductor comprising a single layer of a plurality of interconnected trace segments; and
a plurality of parallel plate capacitors, each of the plurality of parallel plate capacitors having a dielectric layer between a pair of conductive plates, and each of the plurality of parallel plate capacitors is overlapped by only one of the plurality of interconnected trace segments of the single layer spiral inductor.

US Pat. No. 10,141,905

AMPLIFIER WITH ADJUSTMENT OF THE AUTOMATIC SOUND LEVEL

DEVIALET, Paris (FR)

10. An amplifier for producing a volume gain to at least one audio signal, according to a desired volume gain selected by a user, comprising:a calculator for calculating a standardized total slow sound level from the-at least one audio signal;
a calculator for calculating a maximum slow volume gain and a minimum slow volume gain as the quotient of the product of the desired volume gain by a maximum slow gain, respectively by a minimum slow gain divided by the standardized total slow sound level;
a device for determining a first minimum volume gain out of the desired volume gain and the maximum slow volume gain;
a device for determining a second minimum volume gain out of the desired volume gain multiplied by a maximum volume gain and the minimum slow volume gain;
a device for determining, as a slow volume gain, the maximum of the first and second determined minimum volume gains: and
a calculator for calculating the volume gain according to the slow volume gain.

US Pat. No. 10,141,900

OFFSET TRIMMING FOR DIFFERENTIAL AMPLIFIER

SANDISK TECHNOLOGIES LLC,...

1. An apparatus comprising:a differential amplifier comprising a non-inverting input, an inverting input, and an output coupled to the inverting input via a voltage divider;
a first variable current source coupled to the non-inverting input, such that increasing a current from the first variable current source increases a voltage at the non-inverting input; and
a second variable current source coupled to the inverting input, and to the output via the voltage divider, such that increasing a current from the second variable current source decreases a voltage at the output.

US Pat. No. 10,141,899

BROADBAND RADIO FREQUENCY POWER AMPLIFIERS, AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A packaged amplifier device having a bandwidth defined by a range of frequencies between a low cutoff frequency and an upper cutoff frequency, the amplifier device comprising:an input lead configured to receive an input radio frequency (RF) signal;
an output lead configured to produce an amplified RF signal;
a reference node;
a transistor die that includes
a first node,
a second node,
a transistor having a gate, a first current conducting terminal coupled to the output lead, and a second current conducting terminal coupled to the reference node,
a first integrated capacitance having a first terminal coupled to the first node, and a second terminal coupled to the reference node,
a first inductance having a first terminal coupled to the first node, and a second terminal coupled to the second node, and
a second integrated capacitance having a first terminal coupled to the second node, and a second terminal coupled to the reference node; and
a second inductance having a first terminal coupled to the input lead and a second terminal coupled to the first node of the transistor die,
wherein the first inductance, the first integrated capacitance, the second inductance, and the second integrated capacitance form a multiple pole filter of an input impedance matching circuit that is configured to filter the input RF signal to produce a filtered RF signal at the gate of the transistor, and wherein a first pole of the multiple pole filter is positioned at a first frequency within the bandwidth, and a second pole of the multiple pole filter is positioned at a second frequency outside the bandwidth.

US Pat. No. 10,141,893

INPUT STAGE OF AN AMPLIFIER AND CORRESPONDING AMPLIFIER

Devialet, Paris (FR)

1. An input stage of an amplifier comprising:an input for the digital signal to be converted;
a voltage output for the converted voltage;
a digital-to-analog converter, the input of which forms the input for the digital signal to be converted, the digital-to-analog converter comprising a signal terminal for generating a current;
a resistance for converting the current into a voltage, connected to said voltage output and to a reference potential; and
a current-voltage converter with a voltage output, connected to said signal terminal and to said voltage output, the current-voltage converter comprising a transistor such that the gate of the transistor is connected to a voltage source, the drain of the transistor is connected to a current source and the source of the transistor is connected to said digital-to-analog converter, the current source generating a continuous current,wherein the source of said transistor is exclusively connected to said signal terminal of said digital-to-analog converter and wherein said digital-to-analog converter is able to generate a current comprising a continuous component and a fixed component, the current source being able to provide a current equal to the continuous component of the current generated by said digital-to-analog converter, said digital-to-analog converter being connected between a fixed potential and the source of said transistor.

US Pat. No. 10,141,892

BIAS CIRCUIT FOR SUPPLYING A BIAS CURRENT TO A RF POWER AMPLIFIER

RAFAEL MICROELECTRONICS, ...

1. A bias circuit for supplying a bias current to an RF power amplifier, said bias circuit comprising:a first bipolar transistor having a base terminal, a collector terminal and an emitter terminal, wherein the emitter terminal is electrically coupled to the RF power amplifier;
a first voltage reference circuit for clamping a first terminal of first voltage reference circuit at a first reference voltage, wherein the first terminal of the first voltage reference circuit is electrically coupled to base terminal of the first bipolar transistor through a first resistive component, and a second terminal of the first voltage reference circuit is electrically coupled to a ground; and
a second voltage reference circuit for clamping a first terminal of second voltage reference circuit at a second reference voltage, wherein the first terminal of the second voltage reference circuit is electrically coupled to the first terminal of the first voltage reference circuit transistor through a second resistive component, and a second terminal of the second voltage reference circuit is electrically coupled to the ground;
wherein a first terminal of the second voltage reference circuit is electrically coupled to a voltage supply through a third resistive component so as to generate a bias current to the RF power amplifier through the emitter terminal of the first bipolar transistor;
wherein the first resistive component, the second resistive component and the third resistive component are connected in series one by one in a conductive path connecting the base terminal of the first bipolar transistor to the voltage supply, wherein the second resistive component is located between the first resistive component and the third resistive component in said conductive path.

US Pat. No. 10,141,891

POWER AMPLIFIER WITH SUPPLY SWITCHING

Avago Technologies Genera...

1. A power amplifier, comprising:a gain circuit;
a supply switch circuit configured to:
detect a magnitude of an outgoing broadband communication signal; and
determine whether the magnitude of the outgoing broadband communication signal exceeds a predetermined voltage threshold;
a first bias transformer coupled to a first voltage supply rail and configured to bias the gain circuit with the first voltage supply rail;
a second bias transformer coupled to a second voltage supply rail and configured to bias the gain circuit with the second voltage supply rail; and
a capacitive coupling combiner coupled to the first bias transformer and the second bias transformer and configured to reduce a residual flux change between the first bias transformer and the second bias transformer,
wherein the gain circuit is configured to:
apply a first gain to the outgoing broadband communication signal using a first voltage supply rail when it is determined that the magnitude exceeds the predetermined voltage threshold;
apply a second gain to the outgoing broadband communication signal using a second voltage supply rail when it is determined that the magnitude does not exceed the predetermined voltage threshold, the second voltage supply rail being smaller than the first voltage supply rail; and
produce an output signal from the outgoing broadband communication signal with the applied first gain or the applied second gain,
wherein a current of the outgoing broadband communication signal is switched between the first voltage supply rail and the second voltage supply rail in response to the magnitude being detected by the supply switch circuit.

US Pat. No. 10,141,890

POWER AMPLIFIER MODULE

MURATA MANUFACTURING CO.,...

1. A power amplifier module comprising:an amplifier transistor having a plurality of fingers and to which a first power supply voltage or a second power supply voltage is supplied based on a mode signal supplied to the power amplifier module, the amplifier transistor receiving a first signal and outputting a second signal obtained by amplifying the first signal; and
a bias circuit that supplies a bias current to the amplifier transistor, the bias circuit including:
a plurality of bias transistors connected in parallel, each of the plurality of bias transistors being turned ON by a bias control voltage based on a mode signal indicating an operation mode to be used to amplify the first signal;
a first resistor;
a common node, wherein the first resistor is connected at a first end to an emitter of a first of the plurality of bias transistors and at a second end to the common node, and wherein an emitter of a second of the plurality of bias transistors is connected to the common node; and
a plurality of resistors, wherein each one of the plurality of resistors is connected at a first end to the common node and at a second end to a respective one of the plurality of fingers of the amplifier transistor.

US Pat. No. 10,141,883

INPUT STAGE FOR A MOTOR CONTROLLER, AND MOTOR CONTROLLER, ESPECIALLY FOR AN ELECTRIC MOTOR

ZIEHL-ABEGG SE, Kunzelsa...

1. An input stage for a motor controller, in particular a motor controller for an electric motor, wherein the input stage has an input for inputting an input signal, and an output for connecting to the motor controller, wherein the input stage is designed to generate a control signal from an input signal between a first voltage Uunten and a second voltage Uoben>Uunten, and to output the control signal as a target value parameter to the motor controller via the output, characterized by a first comparator for comparing the input signal with a first threshold voltage US1>oben, and a data output unit, wherein the data output unit generates a communication signal on the basis of at least a portion of the input signal, wherein the first comparator outputs an activation signal when the first threshold voltage US1 has been reached or exceeded by the input signal, which activates an outputting of the communication signal to the output by the data output unit.

US Pat. No. 10,141,882

MOTOR HEALTH MONITORING AND MEDICAL DEVICE INCORPORATING SAME

Medtronic MiniMed, Inc., ...

1. A method of detecting degradation in a drive system including a motor, the method comprising:applying a modulated voltage to the motor;
adjusting a duty cycle of the modulated voltage to achieve a commanded rotation of a rotor of the motor; and
identifying a degradation condition based on the duty cycle.

US Pat. No. 10,141,850

COMPARATOR CIRCUIT, POWER SUPPLY CONTROL IC, AND SWITCHING POWER SUPPLY DEVICE

Rohm Co., Ltd., Kyoto (J...

1. A comparator circuit comprising:a first comparator arranged to compare an input signal with a reference voltage so as to generate a first comparison signal;
a second comparator arranged to compare the input signal with a variable reference voltage so as to generate a second comparison signal;
a variable reference voltage generator arranged to generate the variable reference voltage; and
a logic unit arranged to output one of the first comparison signal and the second comparison signal as a comparison signal, wherein
a response speed of the first comparator is faster than a response speed of the second comparator, and a power consumption of the second comparator is smaller than a power consumption of the first comparator, and wherein
the logic unit outputs the first comparison signal as the comparison signal while controlling the variable reference voltage generator to sweep the variable reference voltage until, as a result of the variable reference voltage crossing the reference voltage and the second comparator responding faster than the first comparator, a logic level of the second comparison signal is switched before a logic level of the first comparison signal is switched, and moves to a state capable of outputting the second comparison signal as the comparison signal after the sweep of the variable reference voltage is completed.

US Pat. No. 10,141,826

LINEAR VIBRATION MOTOR IN WHICH A PRINTED CIRCUIT BOARD HAVING A COIL COUPLED THERETO IS POSITIONED TO COVER THE COIL, SUCH THAT THE COIL DOES NOT DIRECTLY CONTACT A STATOR PART, THEREBY PREVENTING A PHENOMENON THAT THE COIL IS UNWOUND OR DISCONNECTED AND

MPLUS CO., LTD., Suwon-s...

1. A linear vibration motor, comprising:a stator part comprising a magnet;
a vibrator part comprising a coil positioned to face the magnet and a printed circuit board coupled to the coil and accommodated in an internal space of the stator part; and
an elastic member connecting the stator part and the vibrator part to each other,
wherein the printed circuit board has one end coupled to the stator part and the other end coupled to the vibrator part and at least partially covers the coil facing the stator part,
wherein the printed circuit board comprises:
a coupling plate fixed to the stator part;
an elastic part extended from the coupling plate in a spiral direction to have elastic force;
a contact part connected to the elastic part and having an end portion of the coil coupled thereto; and
a disk part connected to the contact part and having the coil coupled thereto,
wherein the coil is coupled to the disk part to be covered with the disk part; and
wherein the stator part corresponding to the disk part is mounted with a first damping member,
wherein the stator part comprises:
a case having the internal space formed therein to accommodate the vibrator part and having an opened one side;
a bracket closing the internal space of the case; and
a second damping member facing the vibrator part and installed on a surface of the case,
wherein the first damping member faces the vibrator part and is installed on a surface of the bracket;
wherein the first damping member and the second damping member are each ring-shaped, are each aligned with the coil, are each spaced apart from the coil and each at least partially overlap the coil in the movement direction, and
wherein the contact part of the printed circuit board is positioned in the outer area of the disk part not to overlap the first damping member.

US Pat. No. 10,141,780

MULTI-AGENT FUNCTION AND DISPATCH ON A SMART GRID MONITORING SYSTEM

INSTITUTE OF NUCLEAR ENER...

1. A multi-agent function device, applicable to be coupled to one electric unit of a power dispatch transaction system, and the monitoring device comprising:a measurement module, operable to measure at least one real-time electric signal of the power dispatch transaction system or the electric unit;
a communication module, coupled to a main computer of the power dispatch transaction system and the other monitoring devices, and the main computer being coupled to a power company; and
a control module, coupled to the electric unit externally, and coupled to the measurement module and the communication module internally, wherein the control module executes a self-developed program to determine that the control module is a generation agent, a load agent and a storage agent and then controls the electric unit according to the at least one real-time electric signal;
wherein the communication module transmits the at least one real-time electric signal to the other monitoring devices or the main computer of the power dispatch transaction system, or receives electric demand signals from the power company or the other monitoring devices of the power dispatch transaction system via the main computer for the main computer to execute an electricity transaction with a bidding mechanism; in the bidding mechanism, when the control module is the load agent or the storage agent and receives an electricity consumption decrease request from the power company via the main computer, the control module transmits a permissible electricity consumption decrease and a desired electricity consumption decrease bonus to the main computer for the main computer to determine whether the monitor device is able to win a bid in an electricity transaction; when the control module is the generation agent or the storage agent, and receives an electricity generation increase request from the power company via the main computer, the control module transmits a permissible electricity generation increase and a desired electricity generation increase bonus to the main computer for the main computer to determine whether the monitor device is able to win the bid in the electricity transaction.

US Pat. No. 10,141,774

CHARGING CIRCUIT AND TERMINAL FOR WIRED AND WIRELESS CHARGING

Huawei Device (Dongguan) ...

1. A charging circuit, comprising:a wired connection module, a wireless charging module, a switch circuit, a control circuit, a shunt circuit, and a charging management module, wherein:
a first input/output end of the wired connection module is configured to connect to an output end of a wired charger, a second input/output end of the wired connection module connects to a first input end of the switch circuit, and the second input/output end further connects to a first input/output end of the shunt circuit;
a first input end of the control circuit connects to the second input/output end of the wired connection module, and an output end of the control circuit connects to an enabling end of the wireless charging module;
an output end of the wireless charging module connects to a second input end of the switch circuit;
a first output end of the switch circuit connects to an input/output end of the charging management module;
a second input/output end of the shunt circuit connects to the input/output end of the charging management module, and a third end of the shunt circuit connects to the output end of the wireless charging module; and
an output end of the charging management module is configured to connect to a battery.

US Pat. No. 10,141,706

DISTRIBUTED LASER POWER ARCHITECTURE FOR LASER DIODE ARRAYS

nLIGHT, Inc., Vancouver,...

1. A laser diode driver, comprising:a switching power supply;
a sense resistor coupled to the switching power supply and to a first output of the laser diode driver; and
a voltage controller coupled to a second output of the laser diode driver, wherein the first output and the second output of the laser diode driver are coupled to provide a laser diode array drive current such that the sense resistor is in series with the first output and the second output of the laser diode driver and a laser diode array that receives the laser diode array drive current.

US Pat. No. 10,141,688

PLUG CONNECTOR WITH RESILIENT ENGAGEMENT ELEMENT AND SEAL

Radiall S.A., Aubervilli...

1. A connector comprising:a first connector portion; and
a second connector portion,
said first connector portion comprising a seal, a resilient detent element, a first inner conductor portion, a first outer conductor portion and a first insulating portion, said first insulating portion supporting said first inner conductor portion radially inward of and coaxially to said first outer conductor portion, a portion of said resilient detent element contacting a radially outward facing surface of said first outer conductor portion,
said second connector portion comprising a counterpart detent element, a second inner conductor portion, a second outer conductor portion and a second insulating portion, said second insulating portion supporting said second inner conductor portion radially inward of and coaxially to said second outer conductor portion,
in a mated configuration of said first connector portion and said second connector portion, said first inner conductor portion electrically and mechanically contacts said second inner conductor portion, and said first outer conductor portion electrically and mechanically contacts said second outer conductor portion,
in said mated configuration said resilient detent element engages said counterpart detent element and locks said first connector portion to said second connector portion, and
a compression of said seal in said mated configuration effecting a force parallel to a longitudinal axis of said first connector portion, said force inhibiting play between said resilient detent element and said counterpart detent element.

US Pat. No. 10,141,677

ELECTRICAL CONNECTOR

LOTES CO., LTD, Keelung ...

1. An electrical connector, comprising:an insulating body, having at least two body units, each of the at least two body units accommodating and fixed with a plurality of terminals, and the at least two body units being spliced to each other, wherein each of the at least two body units has at least two edge portions, and the insulating body is provided with at least four fixing portions such that each of the at least two edge portions of each of the at least two body units is provided with at least one of the at least four fixing portions;
at least four metal members, correspondingly and fixedly provided on the at least four fixing portions respectively; and
at least two metal sheets, provided outside the at least two body units, wherein each of the at least two metal sheets is soldered and fixed to at least one metal member provided on each of the at least two body units.

US Pat. No. 10,141,592

RESIN-FRAMED MEMBRANE ELECTRODE ASSEMBLY FOR FUEL CELL

HONDA MOTOR CO., LTD., T...

4. A resin-framed membrane electrode assembly for a fuel cell, comprising:a stepped membrane electrode assembly comprising:
a solid polymer electrolyte membrane having a first surface and a second surface opposite to the first surface;
an anode electrode disposed on the first surface of the solid polymer electrolyte membrane and including an anode catalyst layer and an anode diffusion layer; and
a cathode electrode disposed on the second surface of the solid polymer electrolyte membrane and including a cathode catalyst layer and a cathode diffusion layer, the cathode electrode having a size in plan view that is smaller than a size in plan view of the anode electrode;
a resin frame member surrounding an outer periphery of the solid polymer electrolyte membrane and including an inner protruding portion that protrudes from an inner peripheral base portion toward the cathode electrode and that has a first thickness, the inner protruding portion having an adhesive application portion to which an adhesive is applied so as to surround a part of the inner protruding portion, the part being in contact with the stepped membrane electrode assembly;
a thickness of the cathode diffusion layer being larger than a thickness of the anode diffusion layer; and
the first thickness of the inner protruding portion of the resin frame member being:
larger than the thickness of the cathode diffusion layer, and
larger than a second thickness of the inner protruding portion at which the adhesive is in direct contact with the inner protruding portion at a location at which the inner protruding portion overlaps the solid polymer electrolyte membrane,
wherein the inner protruding portion has an inward-facing end surface forming an inward-most end surface of the resin frame member that is in direct contact with the adhesive.

US Pat. No. 10,141,579

METAL OXIDE-CARBON NANOMATERIAL COMPOSITE, METHOD OF PREPARING THE SAME, CATALYST, METHOD OF PREPARING THE SAME, AND CATALYST LAYER FOR FUEL CELL ELECTRODES

Korea Institute of Energy...

1. A metal oxide-carbon nanomaterial composite comprisinga metal oxide particle having a specific surface area of 5 square meters per gram (m2/g) or less; and
a carbon nanomaterial formed on a surface of the metal oxide particle.

US Pat. No. 10,141,524

PHOSPHORESCENT ORGANOMETALLIC IRIDIUM COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A method for synthesizing a compound represented by Formula (G1),
wherein R1 represents an alkyl group having 1 to 6 carbon atoms, and
wherein R2 to R10 independently represent hydrogen or alkyl group having 1 to 6 carbon atoms,
the method comprising:
making a first compound react with a second compound,
wherein the first compound is represented by Formula (G0),

wherein the second compound is an iridium compound containing halogen or an iridium organometallic compound.

US Pat. No. 10,141,497

THIN FILM STACK

HEWLETT-PACKARD DEVELOPME...

1. A thin film stack, comprising a substrate, a metal layer, and an adhesive layer, wherein the adhesive layer comprises a blend of zinc oxide and tin oxide, wherein the adhesive layer is adhered to the substrate and the metal layer, and wherein the blend of zinc oxide and tin oxide comprises from 90 at % to 100 at % of the adhesive layer, and is present at a zinc oxide to tin oxide atomic ratio of 1:20 to 20:1.

US Pat. No. 10,141,489

LED ILLUMINATION APPARATUS

Shoichi Nakamura, Higash...

1. An LED illumination apparatus comprising:a tubular lens casing that has a first end face at which illuminating lenses are provided and a second end face;
an LED holding part on which LED elements are mounted;
a base part provided on the second end face side of the lens casing;
a concave part formed in the base part so as to house the LED holding part;
a coupling part that holds a coupling state between the lens casing and the base part by fitting the lens casing to the concave part at the second end face to hermetically seal the internal space of the lens casing;
support columns formed so as to protrude from the base part to a space outside the LED illumination apparatus;anda fan device having a frame supported by the support columns, wherein
the fan device makes taken-in air collide with the end face of the base part that faces away from the concave part and exhausts the air through the window parts each formed by adjacent support columns as a pair of side frames thereof and the sides of the respective frame and base part that face each other as upper and lower frames thereof.

US Pat. No. 10,141,484

LIGHT EMITTING DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device composing:a light emitting element having a peak emission wavelength in a range of 410 nm to 440 nm; and
a phosphor member, the phosphor member containing a phosphor comprising:
a first phosphor having a peak emission wavelength in a range of 430 nm to 500 nm and containing an alkaline-earth phosphate, which includes Cl and is activated with Eu;
a second phosphor having a peak emission wavelength in a range of 440 nm to 550 nm and containing at least one of an alkaline-earth aluminate, which is activated with Eu, and a silicate, which includes Ca, Mg, and Cl and is activated with Eu;
a third phosphor having a peak emission wavelength in a range of 500 nm to 600 nm and containing a rare-earth aluminate, which is activated with Ce;
a fourth phosphor having a peak emission wavelength in a range of 610 nm to 650 nm and containing a silicon nitride, which includes Al and at least one of Sr and Ca and is activated with Eu; and
a fifth phosphor having a peak emission wavelength in a range of 650 nm to 670 nm and containing a fluorogermanate, which is activated with Mn,
wherein a percentage content of the first phosphor to a total content of the phosphor is in a range of 20 mass % to 80 mass %,
wherein a content ratio of the first phosphor to the third phosphor is 0.3 to 7,
wherein a half value width of the emission spectrum of the third phosphor is 95 nm to 115 nm; and
wherein the light emitting device is configured to emit light of correlated color temperature in a range of 4,500 K to 5,500 K, and a ratio of peak optical intensity of the first phosphor to the light emitting element is in a range of 0.6 to 1.5, and a special color rendering Index R12 of the light emitting device is 90 or greater and a sum of special color rendering Indices R9 to R15 of the light emitting device is 660 or greater.

US Pat. No. 10,141,476

LIGHT EMITTING DIODE CHIP SCALE PACKAGING STRUCTURE

LEXTAR ELECTRONICS CORPOR...

1. A light emitting diode chip scale packaging structure, comprising:a light emitting unit comprising a light emitting diode chip; and
a lens covering the light emitting diode chip, wherein a curve of an outer surface of the lens in a cross-section view substantially complies with a polynomial of:
z=?0.0005y6?0.0059y5+0.0871y4?0.3718y3+0.5658y2?0.0709y+2.5046,
z is a variable of vertical axis of the curve, y is a variable of horizontal axis of the curve, a center point of the curve corresponding to the light emitting diode chip is a coordinate where y is 0 and z is 2.5046, wherein a correlation coefficient calculated from fitting the curve to the polynomial is larger than or equal to 0.995, the outer surface has a concave structure, the center point of the curve is the lowest point of the concave structure, the lens is in contact with the light emitting unit, and no air gap is between the lens and the light emitting unit.

US Pat. No. 10,141,475

METHOD FOR BINDING MICRO DEVICE TO CONDUCTIVE PAD

MIKRO MESA TECHNOLOGY CO....

1. A method for binding a micro device to a conductive pad of an array substrate, the method comprising:lowering a temperature of the conductive pad in an environment comprising a vapor such that at least a portion of the vapor is condensed to form a liquid layer on the conductive pad;
disposing the micro device over the conductive pad such that the micro device is in contact with the liquid layer and is gripped by a capillary force produced by the liquid layer between the micro device and the conductive pad, wherein the micro device comprises an electrode facing the conductive pad; and
evaporating the liquid layer such that the electrode is bound to and is in electrical contact with the conductive pad.

US Pat. No. 10,141,471

PROXIMITY DETECTOR DEVICE WITH INTERCONNECT LAYERS AND RELATED METHODS

1. A device, comprising:a first interconnect layer comprising a first dielectric layer and a plurality of first electrically conductive traces;
an integrated circuit (IC) layer overlying the first interconnect layer and comprising an image sensor IC and a light source IC laterally spaced from the image sensor IC;
a second interconnect layer overlying the IC layer and comprising a second dielectric layer and a plurality of second electrically conductive traces, the second interconnect layer having first and second openings respectively aligned with the image sensor IC and the light source IC, the image sensor IC and the light source IC being electrically coupled to the plurality of first electrically conductive traces and the plurality of second electrically conductive traces;
a transparent adhesive material filling the first and second openings and contacting surfaces of the image sensor IC and the light source IC;
a lens assembly overlying the second interconnect layer and comprising first and second lenses respectively aligned with the first and second openings, the first and second lenses being adhered to the transparent adhesive material; and
a plurality of contacts coupled respectively to the plurality of first electrically conductive traces.

US Pat. No. 10,141,450

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a substrate;
a gate electrode and an oxide semiconductor film over the substrate, the gate electrode and the oxide semiconductor film overlapping each other with a gate insulating film therebetween;
a metal oxide film in contact with the oxide semiconductor film, the metal oxide film and a first region of the oxide semiconductor film overlapping each other with a second region of the oxide semiconductor film therebetween; and
a conductive film in contact with the metal oxide film, the conductive film comprising a metal element,
wherein the metal oxide film is in contact with the second region of the oxide semiconductor film,
wherein each of the first region of the oxide semiconductor film and the second region of the oxide semiconductor film comprises a first metal and oxygen,
wherein a concentration of the first metal in the second region of the oxide semiconductor film is higher than a concentration of the first metal in the first region of the oxide semiconductor film, and
wherein the concentration of the first metal in the second region of the oxide semiconductor film is higher than a concentration of the first metal in the metal oxide film.

US Pat. No. 10,141,449

OXIDE THIN FILM TRANSISTOR, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An oxide thin film transistor, comprising:a gate oxide layer; and
an oxide channel layer comprising a front channel oxide layer and a back channel oxide layer, the front channel oxide layer located between the back channel oxide layer and the gate oxide layer and in contact with the gate oxide layer, a conduction band bottom of the back channel oxide layer higher than a conduction band bottom of the front channel oxide layer, and a band gap of the back channel oxide layer larger than a band gap of the front channel oxide layer;
wherein a material of the back channel oxide layer is the same as a material of the front channel oxide layer, the material of the back channel oxide layer includes ion-doping, and the material of the front channel oxide layer includes no ion-doping or includes ion-doping different from that of the material of the back channel oxide layer.

US Pat. No. 10,141,423

THIN FILM TRANSISTOR AND FABRICATION METHOD THEREOF, ARRAY SUBSTRATE AND FABRICATION METHOD THEREOF, DISPLAY APPARATUS

BOE TECHNOLOGY GROUP CO.,...

1. A fabrication method of a thin film transistor (TFT), comprising steps of:forming a protection layer in an area above an active layer between a source electrode and a drain electrode to be formed;
forming a source-drain metal layer above the active layer having the protection layer formed thereabove;
coating a photoresist on the source-drain metal layer, and forming a photoresist reserved area and a photoresist non-reserved area, wherein the photoresist reserved area corresponds to areas of the source electrode and the drain electrode to be formed, and the photoresist non-reserved area corresponds to the other area;
etching off the source-drain metal layer corresponding to the photoresist non-reserved area to form the source electrode and the drain electrode and expose the protection layer above the active layer; and
removing the photoresist above the source electrode and the drain electrode and the protection layer.

US Pat. No. 10,141,417

GATE STRUCTURE, SEMICONDUCTOR DEVICE AND THE METHOD OF FORMING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A gate structure comprising:a gate stack comprising:
a doped work function metal (WFM) stack; and
a metal gate electrode overlying the doped WFM stack;
a doped oxide layer in physical contact with a first portion of a sidewall of the gate stack, wherein a surface of the doped oxide layer that extends away from the gate stack and is facing away from a semiconductor substrate is planar; and
a doped spacer over and contacting the doped oxide layer, wherein the doped spacer is in physical contact with a second portion of the sidewall of the gate stack, wherein the doped WFM stack has a dopant concentration lower than a dopant concentration of the doped spacer.

US Pat. No. 10,141,390

ORGANIC LIGHT-EMITTING DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. An organic light-emitting apparatus, comprising:a substrate comprising an active area, a dead area surrounding the active area, and a pad area in an outer region of the dead area;
at least one thin-film transistor disposed in the active area, the at least one thin-film transistor comprising an active pattern, a gate electrode, a source electrode, and drain electrode;
at least one pixel electrode disposed in the active area and electrically connected to one of the source electrode and the drain electrode;
a common electrode facing the substrate and comprising a protrusion, the protrusion being disposed at an end portion of the common electrode adjacent to the pad area and extending towards the pad area;
a first voltage supply unit disposed on the dead area and the pad area and contacting the protrusion of the common electrode, the first voltage supply unit being configured to apply a first voltage to the common electrode;
a second voltage supply unit overlapping the common electrode, and spaced apart and electrically insulated therefrom; and
an insulating layer disposed over the active area and the dead area, and between the common electrode and the second voltage supply unit,
wherein:
the common electrode is disposed on the at least one thin-film transistor and the at least one pixel electrode; and
an end portion of the insulating layer adjacent to the first voltage supply unit contacts an end portion of the first voltage supply unit adjacent to the active area.

US Pat. No. 10,141,380

ORGANIC LIGHT EMITTING DISPLAY DEVICE

LG DISPLAY CO., LTD., Se...

1. An organic light emitting display device, comprising:a plurality of pixels, each of the plurality of pixels having a plurality of first sub pixels, at least one second sub pixel, and at least one third sub pixel,
wherein the plurality of first sub pixels of one pixel of the plurality of pixels are disposed along a first line extended in a first direction,
wherein the at least one second sub pixel of the one pixel is disposed on one side of the first line and the at least one third sub pixel of the one pixel is disposed on the other side of the first line,
wherein the at least one second sub pixel and the at least one third sub pixel of the one pixel are disposed along a second line extended in a second direction different from the first direction, and
wherein a reference pixel among the plurality of pixels and an adjacent pixel adjacent to the reference pixel in the second direction are symmetric with respect to a boundary line between the reference pixel and the adjacent pixel.

US Pat. No. 10,141,378

LIGHT EMITTING DEVICE FREE OF TFT AND CHIPLET

INDUSTRIAL TECHNOLOGY RES...

1. A light emitting device, comprising:a first electrode layer;
an organic light emitting layer formed on the first electrode layer; and
a second electrode layer formed on the organic light emitting layer,
wherein the organic light emitting layer is sandwiched between the first electrode layer and the second electrode layer, the second electrode layer includes a plurality of electrode patterns separated from one another, the electrode patterns of the second electrode correspond to a plurality of monochromatic blocks and have different sizes or numbers to form different density, and the electrode patterns are divided into a plurality of electrode pattern groups that are arranged in an alternate manner, wherein each of the electrode patterns is free from being connected to a thin film transistor (TFT) and a chiplet.

US Pat. No. 10,141,350

ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:a substrate; and
a plurality of data lines and a plurality of gate lines disposed on the substrate, the data lines and the gate lines being configured to define a plurality of pixel units,
wherein each pixel units comprises:
a pixel electrode;
a thin film transistor electrically connected to the data line and the gate line and configured to drive the pixel electrode; and
a resin layer disposed on the data line and/or the gate line and provided with at least one gas discharging structure each having an opening facing away from the substrate.

US Pat. No. 10,141,348

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Display Co., Ltd....

1. A display device comprising:a first base;
a first thin-film transistor (TFT) and a second TFT which are disposed on the first base to be adjacent to each other along a first direction;
an organic layer which covers the first TFT and the second TFT and comprises a first opening overlapping a first drain electrode of the first TFT and a second opening overlapping a second drain electrode of the second TFT;
a common electrode which is located on the organic layer and comprises a first common electrode opening overlapping the first opening and a second common electrode opening overlapping the second opening;
a bump spacer which is located on the common electrode;
an insulating layer which is located on the common electrode and the bump spacer;
a first pixel electrode which is disposed on the insulating layer to overlap the common electrode and is electrically connected to the first TFT; and
a second pixel electrode which is disposed on the insulating layer to overlap the common electrode and is electrically connected to the second TFT,
wherein a minimum distance between the bump spacer and the first common electrode opening is equal to a minimum distance between the bump spacer and the second common electrode opening in a plan view,
wherein the bump spacer and the insulating layer are formed of different materials.

US Pat. No. 10,141,345

ARRAY SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO.,...

1. An array substrate, comprising:common electrodes;
pixel electrodes overlapped with the common electrodes in a direction perpendicular to the array substrate;
common electrode lines;
at least one auxiliary common electrode line formed in a same layer as the pixel electrodes;
a passivation layer and an insulation layer provided between the common electrode lines and the at least one auxiliary common electrode line; and
data lines provided between the insulation layer and the passivation layer,
wherein the at least one auxiliary common electrode line is arranged to intersect with the common electrode lines and be electrically connected to the common electrode lines through via holes formed in the insulation layer and the passivation layer, and
wherein the at least one auxiliary common electrode line is disposed overlapped with the data lines in the direction perpendicular to the array substrate, the at least one auxiliary common electrode line is arranged parallel to the data lines, and the insulation layer is provided between the at least one auxiliary common electrode line and the data lines.

US Pat. No. 10,141,344

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor comprising:
a first conductor over a substrate;
a first insulator over the first conductor;
a first oxide over the first insulator;
a second insulator over the first oxide;
a second conductor over the second insulator;
a third insulator over the second conductor;
a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and
a fifth insulator in contact with the first oxide and the fourth insulator,
a second transistor comprising:
a third conductor;
a fourth conductor at least part of which overlaps with the third conductor; and
a second oxide between the third conductor and the fourth conductor,
wherein the third conductor and the fourth conductor are electrically connected to the first conductor.

US Pat. No. 10,141,342

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first circuit comprising an integrator circuit comprising an operational amplifier;
a second circuit;
a first transistor; and
a second transistor,
wherein one of a source and a drain of the first transistor is directly connected to an inverting input terminal of the operational amplifier,
wherein one of a source and a drain of the second transistor is directly connected to the inverting input terminal of the operational amplifier,
wherein a first analog signal is input to an input terminal of the integrator circuit via the first transistor,
wherein a second analog signal is input to the input terminal of the integrator circuit via the second transistor,
wherein the integrator circuit is configured to change capacitance between the inverting input terminal of the operational amplifier and an output terminal of the operational amplifier,
wherein the first circuit is configured to convert the first analog signal into a first digital signal,
wherein the second circuit is configured to generate a second digital signal based on the first digital signal,
wherein the first circuit is configured to convert the second analog signal into a third digital signal based on the second digital signal, and
wherein at least one of the first transistor and the second transistor comprises an oxide semiconductor in a channel formation region.

US Pat. No. 10,141,340

THIN-FILM-TRANSISTOR, THIN-FILM-TRANSISTOR ARRAY SUBSTRATE, FABRICATING METHODS THEREOF, AND DISPLAY PANEL

BOE TECHNOLOGY GROUP CO.,...

1. A method for fabricating a thin-film-transistor (TFT), the method comprising:forming an initial conductive layer on a base substrate;
forming an oxidation preventing layer on a portion of the initial conductive layer to be removed;
performing an oxidization process to partially oxidize the initial conductive layer to form an oxidized insulating sub-layer and a non-oxidized conductive sub-layer, a portion of the non-oxidized conductive sub-layer being exposed through the oxidized insulating sub-layer;
removing the oxidation preventing layer after forming the oxidized insulating sub-layer;
removing, after the oxidation preventing layer is removed, the portion of the initial conductive layer to be removed to expose a portion of the base substrate; and
forming an active layer, a source electrode and a drain electrode over a portion of the oxidized insulating sub-layer that is separated by the exposed portion of the base substrate from the portion of the non-oxidized conductive sub-layer exposed through the oxidized insulating sub-layer.

US Pat. No. 10,141,333

DOMAIN WALL CONTROL IN FERROELECTRIC DEVICES

International Business Ma...

1. A ferroelectric device comprising:a first electrode comprising one or more electrically conductive layers,
a second electrode comprising one or more electrically conductive layers;
a layer of ferroelectric material disposed between, and in electrical communication with, the first electrode and the second electrode;
wherein at least one of the first electrode and the second electrode comprises a recessed region and the layer of ferroelectric material comprises a corresponding region of increased thickness;
wherein a programming signal that is applied across the first and second electrodes does not change a polarity of a portion of the layer of ferroelectric material that is proximate to the region of increased thickness; and
wherein the programming signal that is applied across the first and second electrodes changes a polarity of one or more other portions of the layer of ferroelectric material.

US Pat. No. 10,141,332

MANUFACTURING METHOD FOR SEMICONDUCTOR DEVICE HAVING HOLE PENETRATING STACK STRUCTURE

SK Hynix Inc., Gyeonggi-...

1. A method for manufacturing a semiconductor device, the method comprising:repeatedly stacking a first material layer and a second material layer to form a first stack structure;
forming a first hole passing through the first stack structure;
forming an overlay measurement pattern in the first hole, wherein the overlay measurement pattern includes a different material from the first material layer and the second material layer;
forming an etch stop layer in the first hole and over the overlay measurement pattern;
repeatedly stacking a third material layer and a fourth material layer over the first stack structure to form a second stack structure; and
forming a second hole passing through the second stack structure to expose the etch stop layer,
wherein the first hole includes an air-gap surrounded by the overlay measurement pattern and disposed below the etch stop layer.

US Pat. No. 10,141,316

SEMICONDUCTOR DEVICE WITH PILLAR AND BACKGROUND PATTERNS AND METHOD FOR FABRICATING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including spaced-apart active regions, and device isolating regions isolating the active regions from each other;
bit lines on the substrate, the bit lines including bit line contacts on the active regions;
a pillar array pattern including a plurality of pillar patterns overlapping the active regions, the plurality of pillar patterns being spaced apart from each other at an equal distance in a first direction and in a second direction intersecting the first direction, and the plurality of pillar patterns having a non-overlapping relationship with the bit line contacts; and
a background pattern on the substrate, the background pattern being completely peripheral with respect to all the plurality of pillar patterns in the pillar array pattern,
wherein the plurality of pillar patterns includes first pillar patterns and second pillar patterns disposed alternatingly in the first direction and in the second direction, and
wherein a distance between the background pattern and a most adjacent one of the plurality of pillar patterns is larger than a distance between two adjacent ones of the plurality of pillar patterns.

US Pat. No. 10,141,308

LOW RESISTANCE SOURCE/DRAIN CONTACTS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES

International Business Ma...

1. A semiconductor device, comprising:source/drain regions (S/D) in an n-type field effect transistor (NFET) region and in a p-type field effect transistor (PFET) region;
contacts formed to recrystallized layers of the S/D regions in the NFET and PFET regions; and
metastable recrystallized interface layers formed between the contacts and the S/D regions in respective NFET and PFET regions, the recrystallized interface layers including an alloy element concentration that exceeds solubility with a respective material of the S/D regions in the respective NFET and PFET regions.

US Pat. No. 10,141,304

SEMICONDUCTOR DEVICE

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
an upper electrode provided on an upper surface of the semiconductor substrate; and
a lower electrode provided on a lower surface of the semiconductor substrate;
wherein
an anode region and an upper Insulated Gate Bipolar Transistor (IGBT) structure are provided in a range in the semiconductor substrate that is exposed at the upper surface,
a trench is provided in the upper surface,
the anode region is separated from the upper IGBT structure by the trench, the anode region is in contact with the trench, and the upper IGBT structure is in contact with the trench,
the anode region is a p-type region connected to the upper electrode,
the upper IGBT structure includes an n-type emitter region and a p-type body region, the emitter region connected to the upper electrode, and the body region being in contact with the emitter region and connected to the upper electrode,
a gate insulating film and a gate electrode are provided in the trench,
a cathode region and a collector region are provided in a range in the semiconductor substrate that is exposed at the lower surface, the cathode region bordering the collector region at an interface;
the cathode region is an n-type region connected to the lower electrode and provided in at least a part of a region below the anode region,
the collector region is a p-type region connected to the lower electrode, provided in at least a part of a region below the upper IGBT structure, and being in contact with the cathode region,
an n-type drift region is provided between an upper structure including the anode region and the upper IGBT structure and a lower structure including the cathode region and the collector region,
a crystal defect region is provided across a portion of the drift region that is above the cathode region and a portion of the drift region that is above the collector region so that the crystal defect region is provided in a part of the portion of the drift region that is above the collector region,
the crystal defect region having a density of crystal defects higher than a density of crystal defects in a surrounding region of the crystal defect region,
the semiconductor substrate has a dimension that satisfies a relationship of y?0.007x2?1.09x+126 within a range of 165 ?m?x?60 ?m, where x is a number in the unit of ?m and represents a thickness of the semiconductor substrate and y is a number in the unit of ?m and represents a width of a portion of the crystal defect region that protrudes along a direction parallel to the upper surface of the semiconductor substrate from the portion of the drift region that is above the cathode region to the portion of the drift region that is above the collector region,
the trench and the interface are separate from each other when viewed in plan view, with the trench above the collector region and the interface below the anode region and without the interface directly below the trench, such that the anode region extends toward the upper IGBT structure more than the cathode region does, and
the portion of the crystal defect region does not protrude beyond the trench to a portion of the drift region that is below the upper IGBT structure.

US Pat. No. 10,141,303

RF AMPLIFIER PACKAGE WITH BIASING STRIP

Cree, Inc., Durham, NC (...

1. An RF amplifier package, comprising:a flange shaped body section,
an electrically conductive die pad centrally located on the body section;
an electrically insulating window frame disposed on an upper surface of the body section and surrounding the die pad;
a first electrically conductive lead disposed on the window frame adjacent to a first side of the die pad and extending away from the first side of the die pad towards a first edge side of the body section
a second electrically conductive lead disposed on the window frame adjacent to a second side of the die pad and extending away from the second side of the die pad towards a second edge side of the body section, the second side of the die pad being opposite the first side of the die pad; and
a first electrically conductive biasing strip that is: disposed on the window frame, continuously connected to the second lead, and extends along and a third side of the die pad, the third side of the die pad extending between the first and second sides of the die pad.

US Pat. No. 10,141,302

HIGH CURRENT, LOW SWITCHING LOSS SIC POWER MODULE

Cree, Inc., Durham, NC (...

1. A power module comprising:a housing with an interior chamber; and
a plurality of switch modules mounted within the interior chamber and interconnected to facilitate switching power to a load wherein each of the plurality of switch modules comprises at least one transistor and at least one diode and the power module is able to block at least 1200 volts, conduct at least 120 amperes, and has switching losses less than 25 milli-Joules.

US Pat. No. 10,141,295

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the steps of:(a) mounting a first semiconductor chip over a second semiconductor chip such that a first surface of the first semiconductor chip faces to a second surface of the second semiconductor chip,
wherein the second semiconductor chip includes a plurality of electrode pads and a recognition mark arranged on the second surface, and a plurality of through electrodes electrically coupled with the electrode pads respectively, and
wherein the first semiconductor chip includes a plurality of projection electrodes arranged on the first surface,
the (a) step including the steps of:
(a1) recognizing the recognition mark;
(a2) performing alignment of the first semiconductor chip and the second semiconductor chip based on a result of having recognized the recognition mark; and
(a3) mounting the first semiconductor chip over the second semiconductor chip, and electrically coupling the electrode pads of the second semiconductor chip and the projection electrodes of the first semiconductor chip respectively,
(b) before the (a) step, forming the through electrodes such that the through electrodes are formed penetrating a silicon base portion of the first semiconductor chip, and
(c) after the (b) step, forming the recognition mark on the second surface such that the recognition mark is electrically separated from the through electrodes and not overlapped with the through electrodes in plan view.

US Pat. No. 10,141,292

DRIVING CHIP BUMP HAVING IRREGULAR SURFACE PROFILE, DISPLAY PANEL CONNECTED THERETO AND DISPLAY DEVICE INCLUDING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display device comprising:a display panel driven to display an image, the display panel comprising a substrate, the substrate comprising a display area at which the image is displayed;
a terminal pad on the substrate and through which a driving signal is applied to the display area;
a driving chip through which the driving signal is applied to the terminal pad; and
a non-conductive film which fixes the driving chip to the substrate,
wherein the driving chip comprises:
an elastic support body projected from a surface of the driving chip;
a bump wiring on the elastic support body, the bump wiring directly contacting the terminal pad to apply the driving signal to the terminal pad; and
a dispersed particle on the elastic support body,
wherein
the dispersed particle is disposed inside a first portion of the bump wiring,
a second portion of the bump wiring is adjacent to the first portion thereof,
the first portion of the bump wiring at the dispersed particle protrudes further from the elastic support body than the second portion of the bump wiring adjacent to the first portion thereof, and
the protruded first portion of the bump wiring corresponds to a shape of the dispersed particle.

US Pat. No. 10,141,290

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MIKRO MESA TECHNOLOGY CO....

1. A method for manufacturing a display device, the method comprising:forming at least two bottom conductive lines on an array substrate;
disposing at least four micro light emitting devices respectively on the bottom conductive lines;
forming at least one filling material covering the micro light emitting devices;
forming at least four openings in the filling material by photolithography, such that the micro light emitting devices are respectively exposed by the openings; and
forming at least two upper conductive lines on the filling material, wherein the upper conductive lines are electrically connected to the micro light emitting devices through the openings, the upper conductive lines and the bottom conductive lines cross at the micro light emitting devices, and a vertical projection of one of the bottom conductive lines on the array substrate overlaps with a vertical projection of each of the upper conductive lines on the array substrate.

US Pat. No. 10,141,285

EXTERNALLY INDUCED CHARGE PATTERNING USING RECTIFYING DEVICES

Palo Alto Research Center...

1. A system for forming charge patterns on micro objects, said system comprising:a micro object including a rectifying device, the rectifying device exhibiting an asymmetric current-voltage (I-V) response curve, the micro object includes a substrate, and wherein the rectifying device is formed on or in the substrate; and
a device external to the micro object, configured to generate an electric or magnetic field to induce a flow of charge through the rectifying device, wherein the device external to the micro object induces the flow of charge through the rectifying device using capacitive or magnetic coupling, and wherein the device external to the micro object which generates the electric or magnetic field, uses at least a part of the electric or magnetic field to generate charge patterns, and wherein motion is induced as an interaction of the electric or magnetic field, induced charge and the micro-object.

US Pat. No. 10,141,284

METHOD OF BONDING SEMICONDUCTOR SUBSTRATES

IMEC vzw, Leuven (BE)

1. A method of bonding semiconductor substrates, the method comprising:providing a first semiconductor substrate and a second semiconductor substrate to be bonded;
pre-bond processing each of the first and second semiconductor substrates prior to bonding, pre-bond processing comprising:
depositing a dielectric layer on a major surface of the each of first and second semiconductor substrates,
chemical-mechanical polishing the dielectric layer of the each of the first and second semiconductor substrates to reduce the roughness of the dielectric layer,
depositing a silicon carbon nitride (SiCN) layer on the dielectric layer of the each of the first and second semiconductor substrates,
pre-bond annealing the each of the first and second semiconductor substrates, and
chemical-mechanical polishing the SiCN layer to reduce the roughness of the SiCN layer;
bonding the first and second semiconductor substrates, bonding comprising:
aligning the first and second substrates, and
contacting the SiCN layers of the first and second substrates, thereby forming an assembly of bonded substrates; and
post-bond annealing the assembly of bonded substrates.

US Pat. No. 10,141,283

SINTERABLE BONDING MATERIAL AND SEMICONDUCTOR DEVICE USING THE SAME

1. A sinterable bonding material comprising a silver filler and an organic base compound as a sintering promoter, wherein the silver filler comprises a flake-shaped filler, and wherein the organic base compound is a nitrogen containing hetero ring compound having an amidine moiety and/or a guanidine moiety.

US Pat. No. 10,141,269

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE WIRE WITH INCREASED ATTACHMENT ANGLE AND METHOD

Amkor Technology, Inc., ...

1. A semiconductor device comprising:a substrate;
a semiconductor die mounted to the substrate;
a shielding wire spaced apart from a major surface the semiconductor die and formed across the major surface of the semiconductor die; and
an auxiliary structure supporting the shielding wire under the shielding wire, wherein:
the shielding wire comprises opposing ends attached to the substrate;
the auxiliary structure physically contacts the shielding wire at a location other than either of the opposing ends; and
the auxiliary structure is attached to the substrate along only one side of the semiconductor die without overlapping the major surface of the semiconductor die.

US Pat. No. 10,141,267

FAN-OUT SEMICONDUCTOR PACKAGE

SAMSUNG ELECTRO-MECHANICS...

1. A fan-out semiconductor package comprising:a first connection member including a redistribution layer;
a first semiconductor chip disposed on the first connection member and having an active surface having a first connection pad disposed thereon and an inactive surface opposing the active surface;
a first encapsulant disposed on the first connection member and encapsulating at least portions of the first semiconductor chip;
a second semiconductor chip disposed on the first encapsulant and having an active surface having a second connection pad disposed thereon and an inactive surface opposing the active surface;
a second encapsulant disposed on the first encapsulant and encapsulating at least portions of the second semiconductor chip; and
a second connection member having a through-hole,
wherein the active surfaces of the first semiconductor chip and the second semiconductor chip face the first connection member,
the first connection pad and the second connection pad are electrically connected to the redistribution layer of the first connection member through a first via and a second via that do not overlap each other, respectively,
the first semiconductor chip is disposed in the through-hole of the second connection member, and
the first encapsulant encapsulates at least portions of the second connection member.

US Pat. No. 10,141,253

SEMICONDUCTOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

16. A method comprising:receiving an interposer, the interposer comprising a first redistribution layer (RDL) over a first side of a substrate, and a plurality of external connectors attached to a second side of the substrate opposing the first side;
attaching a plurality of dies to the first RDL, wherein after attaching the plurality of dies, the first RDL is between the substrate and the plurality of dies;
filling a space between the plurality of dies and the first RDL with an underfill material;
forming a molding material over the first RDL and around the plurality of dies and the underfill material;
dispensing a polymer material on the second side of the substrate without covering top surfaces of the plurality of external connectors distal the substrate; and
curing the polymer material.

US Pat. No. 10,141,252

SEMICONDUCTOR PACKAGES

ADVANCED SEMICONDUCTOR EN...

1. A semiconductor package, comprising:a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole further defined by a first sidewall and a second sidewall of the passivation layer;
a first conductive layer on the first surface of the passivation layer and the first sidewall;
a second conductive layer on the second surface of the passivation layer and the second sidewall; and
a third conductive layer between the first conductive layer and the second conductive layer,
wherein the third conductive layer comprises a first seed layer adjacent to the first conductive layer and a second seed layer adjacent to the second conductive layer,
wherein the passivation layer comprises a first polymer layer and a second polymer layer,
wherein the first seed layer is disposed between the first conductive layer and the first polymer layer and the second seed layer is disposed between the second conductive layer and the second polymer layer.

US Pat. No. 10,141,251

ELECTRONIC PACKAGES WITH PRE-DEFINED VIA PATTERNS AND METHODS OF MAKING AND USING THE SAME

GENERAL ELECTRIC COMPANY,...

1. An electronic package, comprising:a substrate having a first side and a second side;
a seed metal layer disposed on at least a portion of the first side of the substrate;
a patterned resist layer disposed on at least a portion of the seed metal layer, wherein the patterned resist layer and the seed metal layer are at least partly removed exposing the first side of the substrate during formation of the electronic package to define a plurality of pre-defined via locations, a plurality of pre-defined via patterns, and a plurality of pre-defined trace patterns;
a metal built-up layer disposed on at least a portion of the seed metal layer corresponding to the plurality of pre-defined via locations and the plurality of pre-defined trace patterns, the metal built-up layer disposed on at least a portion of the seed metal layer such that the seed metal layer is disposed between the substrate and the metal built-up layer,
an adhesive layer disposed on at least a portion of the second side of the substrate;
a contact pad disposed on at least a portion of the adhesive layer and aligned with at least one of the plurality of pre-defined via locations;
an electronic device coupled to the contact pad and aligned with one of the plurality of pre-defined via locations, the plurality of pre-defined via patterns, and the plurality of pre-defined trace patterns, wherein the substrate and the adhesive layer are at least partly removed to extend the plurality of pre-defined via locations to the electronic device;
a first conductive layer disposed on at least a portion of the plurality of pre-defined via locations, the plurality of pre-defined via patterns, and the plurality of pre-defined trace patterns; and
a second conductive layer disposed on the first conductive layer such that the second conductive layer is disposed within the plurality of pre-defined via locations,
wherein a plurality of vias, a plurality of via patterns and a plurality of trace patterns are formed by selectively removing a portion of the first conductive layer and the second conductive layer disposed outside the plurality of pre-defined via locations, the plurality of pre-defined via patterns and the plurality of pre-defined trace patterns.

US Pat. No. 10,141,247

POWER SEMICONDUCTOR DEVICE

1. A power semiconductor device, comprising:a substrate and power semiconductor components arranged on the substrate and electrically conductively connected to the substrate;
an electrically conductive DC voltage bus bar system and comprising a capacitor electrically conductively connected to the DC voltage bus bar system;
wherein the power semiconductor device further comprises:
a capacitor securing apparatus for securing the capacitor and a receptacle device for receiving the capacitor, in which at least part of the capacitor is arranged;
wherein, from the DC voltage bus bar system, a plurality of electrically conductive bus bar system terminal elements are electrically conductively connected thereto and run in a direction of the substrate;
at least one elastic first deformation element is materially bonded to the capacitor securing apparatus and is formed from an elastomer and is arranged on a facing side of the capacitor securing apparatus facing the DC voltage bus bar system;
wherein the capacitor securing apparatus, via the at least one first deformation element, presses the DC voltage bus bar system in the direction of the substrate and thereby further presses the bus bar system terminal elements against designated electrically conductive contact areas of the substrate such that the bus bar system terminal elements are electrically conductively pressure-contacted with said contact areas of the substrate.

US Pat. No. 10,141,246

LEADFRAME PACKAGE WITH SIDE SOLDER BALL CONTACT AND METHOD OF MANUFACTURING

STMicroelectronics, Inc.,...

1. A method, comprising:removing portions of a metal layer on a first surface and a second surface of a leadframe;
forming a first plurality of recesses and a second plurality of recesses in the first surface of the leadframe;
coupling a solder ball to each of the first plurality of recesses;
coupling a die to the metal layer on the first surface of the leadframe;
coupling a plurality of wires between the die and the first surface of the leadframe;
encapsulating the die, the plurality of wires and at least a portion of each solder ball with an encapsulant, a portion of each solder ball extending from a sidewall of the leadframe and into a body of the encapsulant;
removing remaining portions of a body of the leadframe opposite the first plurality of recesses and the second plurality of recesses; and
cutting the encapsulant, the leadframe and the plurality of solder balls to form a leadframe package.

US Pat. No. 10,141,245

HIGH-POWER ACOUSTIC DEVICE WITH IMPROVED PERFORMANCE

Qorvo US, Inc., Greensbo...

1. An apparatus comprising:a substrate comprising a substrate body and a die pad on a top surface of the substrate body;
a die-attach material applied over the die pad, wherein the die-attach material is a sintered material;
an acoustic die coupled to the die pad via the die-attach material, wherein:
the acoustic die includes a plurality of acoustic components, a die body and a metallization structure;
the plurality of acoustic components resides over a top surface of the die body and the metallization structure resides over a bottom surface of the die body; and
the metallization structure is vertically sandwiched between the die body and the die-attach material.

US Pat. No. 10,141,244

TSV LAYOUT STRUCTURE AND TSV INTERCONNECT STRUCTURE, AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of fabricating a TSV interconnect structure, comprising:providing a semiconductor substrate including a first region and a second region that have a total surface area equal to an area of a single chip;
forming a plurality of through-holes in both the first region and the second region by controlling a difference of an average area ratio of through-holes between the first region and the entire semiconductor substrate, such that a polishing rate difference of a metal layer in the through-holes between the first and second regions is reduced, wherein:
an average through-hole area ratio of the first region is greater than an average through-hole area ratio of the entire semiconductor substrate and the average through-hole area ratio of the entire semiconductor substrate is less than or equal to about 2%, and
the second region is a continuous region connecting to the first region and has an average through-hole area ratio less than the first region, and
through-holes in the first region are closely packed, while through-holes in the second region are loosely packed;
forming the metal layer to fill the plurality of through-holes in the semiconductor substrate; and
planarizing the metal layer by a chemical mechanical polishing process to form a TSV interconnect structure, wherein:
when the semiconductor substrate in the first region has a surface area of less than or equal to about 28 mm2 and greater than about 14 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 1.25%,
when the semiconductor substrate in the first region has the surface area of less than or equal to about 14 mm2 and greater than about 3 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 2.75%,
when the semiconductor substrate in the first region has the surface area of less than or equal to about 3 mm2 and greater than about 0.5 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 4.75%, and
when the semiconductor substrate in the first region has the surface area of less than or equal to about 0.5 mm2 and greater than about 0.16 mm2, the difference of the average through-hole area ratio between the first region and the entire semiconductor substrate is less than or equal to about 6.75%.

US Pat. No. 10,141,240

SEMICONDUCTOR DEVICE, CORRESPONDING CIRCUIT AND METHOD

STMICROELECTRONICS S.R.L....

1. A semiconductor device comprising:at least one semiconductor die;
a package, the at least one semiconductor die embedded in the package, the at least one semiconductor die coupled to a thermally-conductive element, wherein the package includes a layered package including:
an intermediate layer, the at least one semiconductor die arranged in an opening in the intermediate layer;
first and second outer layers, the thermally-conductive element including a thermally-conductive inlay in the first outer layer, wherein the second outer layer is provided with electrical contact formations coupled to the at least one semiconductor die; and
a heat sink member thermally coupled to the thermally-conductive inlay.

US Pat. No. 10,141,237

FINGERPRINT RECOGNITION MODULE AND MANUFACTURING METHOD THEREFOR

PRIMAX ELECTRONICS LTD., ...

1. A manufacturing method for a fingerprint recognition module, comprising the following steps:(a) directly connecting and fixing a die to a flexible printed circuit (FPC) board, and electrically connecting the die to the FPC board;
(b) coating an adhesive layer on an upper surface of the die;
(c) covering the adhesive layer with a cover plate, to adhere the cover plate to the adhesive layer; and
(d) applying low pressure injection modeling encapsulation to an encapsulation space defined between the cover plate and the FPC board, so as to form an encapsulation layer in the encapsulation space, wherein step (d) further comprises the following steps:
(d1) placing the FPC board, the die, the adhesive layer, and the cover plate together into a mold;
(d2) adjusting pressure of the mold into a range of 1.5 to 40 bars; and
(d3) injecting a hot melt material into the mold to make the hot melt material flow into the encapsulation space and be cured in the encapsulation space to form the encapsulation layer, wherein the encapsulation layer seals the die.

US Pat. No. 10,141,236

FLIP CHIP BALL GRID ARRAY WITH LOW IMPEDENCE AND GROUNDED LID

International Business Ma...

1. A process for providing electrical conductivity and heat transfer between an electrical substrate and an electrically conductive heat spreader comprising operatively associating said electrical substrate and said electrically conductive heat spreader with an article of manufacture comprising a contact spring so that said article of manufacture conducts heat and electricity from said electrical substrate to said electrically conductive heat spreader, wherein said article of manufacture comprises a contact spring structured to both conduct heat from said electrical substrate to said electrically conductive heat spreader and to electrically connect said electrical substrate and electrically conductive heat spreader, wherein said contact spring comprises a flat single element but configured as a plurality of polygons joined to one another, one edge of one polygon to one edge of a contiguous polygon to form a pattern of repeating polygons substantially lying in a plane and extending substantially in a straight line, the length of said contact spring being greater than its width, said contact spring comprising one or multiple device contacts in the body of said contact springthat extend at least from one side edge of said contact spring, or from at least one surface of said contact spring, or both said side edge and said surface said device contacts arranged so that said contact spring comprises at least one device contact to abut up against said electrically conductive heat spreader and at least one device contact to abut up against said electrical substrate.

US Pat. No. 10,141,232

VERTICAL CMOS DEVICES WITH COMMON GATE STACKS

International Business Ma...

1. A semiconductor structure, comprising:a first nanowire of a first material disposed on a top surface of a substrate;
at least a second nanowire of a second material different than the first material disposed on the top surface of the substrate; and
a common gate stack surrounding the first nanowire and the second nanowire;
wherein the first nanowire and the second nanowire are vertical with respect to a horizontal plane of the top surface of the substrate;
wherein the first nanowire forms at least a portion of a negative field-effect transistor (NFET) vertical transport channel of a complementary metal-oxide-semiconductor (CMOS) device;
wherein the second nanowire forms at least a portion of a positive field-effect transistor (PFET) vertical transport channel of the CMOS device; and
wherein the first material comprises a group III-V material and the second material comprises a group IV material.

US Pat. No. 10,141,229

PROCESS FOR FORMING SEMICONDUCTOR LAYERS OF DIFFERENT THICKNESS IN FDSOI TECHNOLOGIES

GLOBALFOUNDRIES Inc., Gr...

1. A method of forming semiconductor devices, the method comprising:epitaxially growing a portion of a first semiconductor layer above a buried insulating layer in a first device region, said first semiconductor layer having a first thickness after said epitaxial growth process is performed;
forming a second semiconductor layer of a second thickness above said buried insulating layer in a second device region, said second thickness differing from said first thickness, wherein forming said second semiconductor layer comprises, prior to epitaxially growing said portion of said first semiconductor layer, epitaxially growing a portion of said second semiconductor layer so as to obtain said second thickness, forming a growth mask above said second semiconductor layer, and selectively epitaxially growing said portion of said first semiconductor layer by using said growth mask;
forming a first transistor element in and on said first semiconductor layer; and
forming a second transistor element in and on said second semiconductor layer, said second transistor element comprising a fully depleted channel region.

US Pat. No. 10,141,221

METHOD FOR MANUFACTURING THREE DIMENSIONAL STACKED SEMICONDUCTOR STRUCTURE AND STRUCTURE MANUFACTURED BY THE SAME

MACRONIX INTERNATIONAL CO...

1. A method of manufacturing a three-dimensional (3D) stacked semiconductor structure, comprising:forming a multi-layered stack above a substrate, and the multi-layered stack comprising a plurality of nitride layers and polysilicon layers arranged alternately;
forming a plurality of channel holes vertically to the substrate;
patterning the multi-layered stack to form linear spaces between the plurality of channel holes and vertical to the substrate, wherein the linear spaces extend downwardly to expose sidewalls of the plurality of nitride layers and the plurality of polysilicon layers;
replacing the plurality of polysilicon layers with insulating layers having air-gaps through the linear spaces; and
replacing the plurality of nitride layers with conductive layers through the linear spaces.

US Pat. No. 10,141,219

COMBINED PRODUCTION METHOD FOR SEPARATING A NUMBER OF THIN LAYERS OF SOLID MATERIAL FROM A THICK SOLID BODY

Siltectra GmbH, Dresden ...

1. A method for producing layers of solid material comprising:providing a solid body to be split into a number of layers of solid material, the solid body having a first level surface portion and a second level surface portion;
introducing or generating defects in the solid body using laser beams in order to determine a first detachment plane along which a first layer of solid material is separated from the solid body, the laser beams penetrating into the solid body via the second level surface portion;
providing a receiving layer for holding the layer of solid material on the second level surface portion of the solid body, the receiving layer being in the form of a polymer layer;
applying heat to the receiving layer in order to mechanically generate stresses in the solid body, the application of heat including cooling of the receiving layer to a temperature below ambient temperature, the cooling taking place such that the polymer layer undergoes a glass transition and such that due to the stresses a crack propagates in the solid body along the detachment plane, the crack separating the first layer of solid material from the solid body, wherein the second level surface portion is part of the first layer, wherein the first detachment plane is determined closer to the second level surface portion than to the first level surface portion;
introducing or generating defects in the solid body in order to determine a second detachment plane along which a second layer of solid material is separated from the solid body, then providing a second receiving layer for holding another layer of solid material on the solid body reduced by the first layer of solid material; and
applying heat to the second receiving layer in order to mechanically generate stresses in the solid body such that due to the stresses a crack propagates in the solid body along the second detachment plane, the crack separating the second layer of solid material from the solid body.

US Pat. No. 10,141,218

ROOM TEMPERATURE METAL DIRECT BONDING

INVENSAS BONDING TECHNOLO...

1. A method of bonding substrates, comprising:providing a first substrate having a first non-metallic region proximate to a first plurality of metallic pads;
providing a second substrate having a second non-metallic region proximate to a second plurality of metallic pads;
directly contacting the first non-metallic region with the second non-metallic region, wherein a first pad of the first plurality of metallic pads is spaced from a second pad of the second plurality of metallic pads by a gap after directly contacting the first non-metallic region with the second non-metallic region;
non-adhesively bonding the first non-metallic region to the second non-metallic region along an interface without an adhesive and without application of external pressure; and
after directly contacting the first non-metallic region with the second non-metallic region, directly contacting the first pad with the second pad to form a contact between the first pad and the second pad, the interface between the first non-metallic region and the second non-metallic region extending substantially to the contact.

US Pat. No. 10,141,210

PURGE MODULE AND LOAD PORT HAVING THE SAME

RORZE SYSTEMS CORPORATION...

1. A purge module comprising:a jig detachably attached to an upper side of a stage of a load port, the jig comprising a gas inlet for providing a wafer carrier with gas and a gas outlet for receiving gas from the wafer carrier;
a gas control box detachably attached to the load port to control gas flow; and
pipes connecting the jig and the gas control box,
wherein at least one of the gas inlet and the gas outlet further comprises a sealing member making contact with the wafer carrier, when the wafer carrier is disposed thereon, the sealing member including an elastic material;
a sealing protection member disposed surrounding the sealing member; and
wherein the sealing protection member is higher than the sealing member with respect to a surface of the jig.

US Pat. No. 10,141,195

SUBSTRATE PROCESSING METHOD

Tokyo Electron Limited, ...

1. A substrate processing method performed on a substrate having a recess formed in a surface thereof, a first silicon-containing film formed on a bottom surface of the recess, a second silicon-containing film formed on both sides of the recess, comprising:depositing a carbon-based deposit on the surface of the substrate;
removing the first silicon-containing film by performing a COR (Chemical Oxide Removal) process in which the first silicon-containing film is modified to a reaction product using a processing gas, on the substrate; and
removing the deposited carbon-based deposit,
wherein the recess has an aspect ratio of 4 or more.

US Pat. No. 10,141,189

METHODS FOR FORMING SEMICONDUCTORS BY DIFFUSION

ASM IP HOLDING B.V., Alm...

1. A method for making a semiconductor device, comprising:forming a transistor channel region, wherein forming the transistor channel region comprises:
providing a silicon protrusion;
forming an oxide layer on a surface of the silicon protrusion;
selectively removing, relative to other exposed materials, material forming exposed surfaces of the oxide layer to reduce an overall thickness of the oxide layer;
subsequently depositing silicon-germanium on the oxide layer; and
converting the silicon protrusion into a silicon germanium structure by annealing the silicon-germanium and silicon structure in an oxidizing environment to drive the germanium through the oxide layer and into the silicon protrusion.

US Pat. No. 10,141,188

RESIST HAVING TUNED INTERFACE HARDMASK LAYER FOR EUV EXPOSURE

International Business Ma...

1. A method to prepare a substrate for photolithography, comprising:forming an underlayer over a surface of the substrate;
depositing an interface hardmask layer on the underlayer using one of a vapor phase deposition process or an atomic layer deposition process; and
forming a layer of extreme UV (EUV) resist on the interface hardmask layer, where
the interface hardmask layer is comprised of material having a composition and properties tuned to achieve a certain secondary electron yield from the interface hardmask layer;
where depositing the interface hardmask layer is accomplished at a temperature less than a melting temperature of a material that comprises the underlayer.

US Pat. No. 10,141,182

MICROELECTRONIC SYSTEMS CONTAINING EMBEDDED HEAT DISSIPATION STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A method for fabricating a microelectronic system, comprising:obtaining a substrate having a tunnel therethrough:
attaching a microelectronic component to a frontside of the substrate at a location enclosing the tunnel utilizing a solder material having a first thermal conductivity; and
producing an embedded heat dissipation structure at least partially contained within the tunnel after attaching the microelectronic component to the substrate, producing comprising:
applying a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate;
curing the bond layer precursor material to form a thermally-conductive component bond layer in contact with the microelectronic component; and
formulating the bond layer precursor material such that, after curing, the thermally-conductive component bond layer has a second thermal conductivity substantially equivalent to or exceeding the first thermal conductivity.

US Pat. No. 10,141,181

TIN PULL-BACK AND CLEANING COMPOSITION

BASF SE, Ludwigshafen (D...

1. A composition, comprising the following components a)-f), based on total weight of the composition:a) 0.05-4 wt. % of an aliphatic or aromatic sulfonic acid;
b) 0.1 to 10 wt % of an inhibitor selected from the group consisting of imidazolidinones, imidazolidines, and 2-oxazolidinones;
c) 5 to 50 wt % of an aprotic solvent;
d) 1 to 60 wt % of a glycol ether;
e) water; and
an oxidant,
wherein a weight ratio of the aprotic solvent to the water is from 1:10 to 2:1 and wherein the oxidant is present in a volume ratio of components a) to e)to the oxidant ranging from 65:1 to 8:1.

US Pat. No. 10,141,178

MINIATURE CHARGED PARTICLE TRAP WITH ELONGATED TRAPPING REGION FOR MASS SPECTROMETRY

The University of North C...

1. A mass spectrometry system, comprising:an ion source;
an ion detector; and
an ion trap positioned along a longitudinal axis of the system between the ion source and the ion detector,
wherein the ion trap comprises:
a central electrode extending in a plane and comprising a central aperture extending through the central electrode along the longitudinal axis for a distance of less than 10 mm, the central aperture having a length in the plane and a width in the plane; and
a first endcap electrode comprising a first aperture having a length and a width, wherein the first aperture length and the first aperture width are parallel to the central aperture length and the central aperture width, respectively;
wherein the central aperture comprises a linear aperture segment having a length and a width, the linear aperture segment length being measured between end points of the linear aperture segment in the plane of the central electrode, and the linear aperture segment width being measured in a direction perpendicular to the length in the plane;
wherein a ratio of the linear aperture segment length to the linear aperture segment width is greater than 1.5; and
wherein at least one of:
the first aperture length is greater than the central aperture length; and
the first aperture width is greater than the central aperture width.

US Pat. No. 10,141,176

MULTI-REFLECTION MASS SPECTROMETER WITH DECELERATION STAGE

Thermo Fisher Scientific ...

1. A multi-reflection mass spectrometer comprising two ion mirrors spaced apart and opposing each other in an X direction, each mirror elongated generally along a drift direction Y, the X direction being orthogonal to the drift direction Y, and an ion injector for injecting ions as an ion beam into the space between the ion mirrors at an inclination angle to the X direction, wherein along a first portion of their length in the drift direction Y the ion mirrors converge with a first degree of convergence and along a second portion of their length in the drift direction Y the ion mirrors converge with a second degree of convergence or are parallel, the first portion of their length being closer to the ion injector than the second portion and the first degree of convergence being greater than the second degree of convergence.

US Pat. No. 10,141,172

SYNCHRONISED VARIATION OF SOURCE CONDITIONS OF AN ATMOSPHERIC PRESSURE CHEMICAL IONISATION MASS SPECTROMETER COUPLED TO A GAS CHROMATOGRAPH TO IMPROVE STABILITY DURING ANALYSIS

MICROMASS UK LIMITED, Wi...

1. A mass spectrometer comprising:a gas chromatography separation device;
an atmospheric pressure ionisation ion source; and
a control system arranged and adapted:
(i) to operate said atmospheric pressure ionisation ion source at one or more first settings for a first period of time whilst one or more solvents elute from said gas chromatography separation device during a solvent front free of analytes which is prior to the elution of one or more analytes from said gas chromatography separation device; and then
(ii) to operate said atmospheric pressure ionisation ion source at one or more second different settings for a second subsequent period of time whilst said one or more analytes elute from said gas chromatography separation device.

US Pat. No. 10,141,171

METHOD AND KIT FOR DETERMINING METABOLITES ON DRIED BLOOD SPOT SAMPLES

AZIENDA OSPEDALIERO UNIVE...

1. A kit specially designed to be used for the preparation of a dried blood sample for a direct tandem MS analytical determination of Adenosine and Deoxyadenosine concurrently with more than one metabolite selected from the group consisting of amino acids, free carnitine, acylcarnitines and any combinations thereof, from said dried blood sample, said kit comprising:at least one container containing stable isotope-labelled Adenosine and Deoxyadenosine as internal standards and more than one additional internal standards selected from the group consisting of amino acids, acylcarnitines and free carnitine, wherein the isotope label is selected from the group consisting of 2H (D), 15N, 13C and 18O;
at least one dried blood spot as a control, wherein said dried blood spot is enriched with Adenosine and Deoxyadenosine at known concentrations and enriched with one or more metabolites selected from the group consisting of amino acids, free carnitine, acylcarnitines and any combinations thereof at known concentrations; and
at least one container containing an extraction solution comprising a C1-3 linear or branched chain monoalcohol.

US Pat. No. 10,141,166

METHOD OF REAL TIME IN-SITU CHAMBER CONDITION MONITORING USING SENSORS AND RF COMMUNICATION

Applied Materials, Inc., ...

1. A reactor for processing a workpiece, the reactor comprising:a chamber comprising:
a cylindrical sidewall;
a ceiling;
a floor; and
a pedestal for supporting a workpiece inside said chamber;
plural wireless sensors each having a wireless transceiver and secured to said chamber and fixed in locations inside said chamber;
a process controller outside of said chamber and connected to said chamber to govern process parameters in said chamber, wherein said cylindrical sidewall, said ceiling, and said floor are conductive such that said chamber blocks wireless communication channels between respective ones of said sensors and said process controller;
a wireless communication hub inside of said chamber and programmed to maintain respective independent wireless communication channels between the wireless transceiver of respective ones of said sensors and said wireless communication hub; and
a communication path between said wireless communication hub and said process controller.

US Pat. No. 10,141,165

PLASMA PROCESSING APPARATUS AND SAMPLE STAGE THEREOF

HITACHI HIGH-TECHNOLOGIES...

1. A plasma processing apparatus comprising: a processing chamber disposed in a vacuum vessel in which a wafer located therein is processed using plasma generated therein; a sample stage disposed in the processing chamber on which the wafer is mounted on a top surface thereof; an electrode disposed in the sample stage which is constituted by an electrically conductive material; a radio frequency power supply which is electrically connected to the electrode in the sample stage and supplies the radio frequency power for generating a bias potential above the wafer mounted on the sample stage to the electrode; a plurality of heater units each of which are respectively disposed in each of a plurality of areas in a cylindrical interior of the sample stage, the plurality of areas including a central region of the cylindrical interior of the sample stage and a plurality of ring-shaped regions which are disposed on an outer circumference of the central region and surrounds the central region; one or more DC power supplies which is connected to each of the plurality of heater units disposed in each of the ring-shaped regions and is configured to supply DC power to each of the plurality of heater units; a plurality of arcuate heaters which constitutes each of the plurality of heater units disposed in each of the plurality of ring-shaped regions and is circumferentially disposed around the central region of the sample stage, the plurality of arcuate heaters in each of the heater units in each of the plurality of the ring-shaped regions being connected in series to the one or more DC power supplies which is connected to the one of the plurality of heater units disposed in the one or more ring-shaped regions and constituting a circuit; wherein each of the plurality of arcuate heaters constituting the circuit in the each of the heater units disposed in each of the plurality of the ring-shaped regions is connected to the adjacent arcuate heater by each of a plurality of connection portions and has a same length forming a same circumferential angle around the central region, and, the each of the heater units disposed in each of the plurality of the ring-shaped regions constitutes a loop, and the arcuate heaters disposed in one of the ring-shaped region closer to the center region form greater circumferential angle around the central region than those of the arcuate heaters disposed in the ring-shaped region outwardly located, and the apparatus further comprising: a plurality of adjusting devices each of which is connected with the circuit in front and behind of each of the plurality of the arcuate heaters in parallel thereto, the plurality of adjusting devices are configured to be capable of adjusting amounts of current from the one or more DC power supplies flowing through the each of the plurality of arcuate heaters to which the each of the plurality of adjusting devices is connected in parallel; a control unit which is configured to be enable to adjust amounts of heat generated by the one of the plurality of heater units disposed in the one or more ring-shaped regions by adjusting operations of the plurality of adjusting devices.

US Pat. No. 10,141,153

MAGNETRON HAVING ENHANCED COOLING CHARACTERISTICS

Applied Materials, Inc., ...

1. A cooling assembly, comprising:a plurality of cooling fins, each cooling fin having a central opening; and
one or more flow directing structures formed between neighboring cooling fins, wherein the one or more flow directing structures form a flow channel between the neighboring cooling fins, wherein each flow directing structure intersects two or more cooling fins, wherein the one or more flow directing structures comprises channel walls that are contiguous from a front edge of the cooling fin to an air restriction facing a rear edge of the cooling fin, and wherein the channel walls define the flow channel that expands in a cone-shape from the air restriction adjacent the rear edge to the front edge.

US Pat. No. 10,141,150

HIGH CURRENT ONE-PIECE FUSE ELEMENT AND SPLIT BODY

LITTELFUSE, INC., Chicag...

1. A high breaking capacity fuse comprising:a first outer insulative layer, the first outer insulative layer having a first cavity formed therein;
a second outer insulative layer disposed on the first outer insulative layer, the second outer insulative layer having a second cavity formed therein;
a cup-shaped first ceramic insert disposed within the first cavity;
a cup-shaped second ceramic insert disposed within the second cavity, wherein the first and second ceramic inserts fit together to define a chamber; and
a single piece fusible element disposed between the first outer insulative layer and the second outer insulative layer, the single piece fusible element comprising a first terminal portion, a second terminal portion, a fusible element portion having a plurality of rolls along its longitudinal axis, a first mid portion connecting the fusible element portion to the first terminal portion, and a second mid portion connecting the fusible element to the second terminal portion, wherein the fusible element portion is disposed at least partially within the chamber, wherein the first terminal portion extends along at least one outer surface of the second outer insulative layer, and the second terminal portion extends along at least one outer surface of the second outer insulative layer;
wherein each of the first and second terminal portions has grooves formed in opposing sides thereof, and wherein the first outer insulative layer includes tongue portions formed in a top edge thereof, the tongue portions disposed within the grooves.

US Pat. No. 10,141,149

THIN FILM FUSE

Continental Automotive Sy...

1. A thin film fuse comprising:a non-conductive substrate having a surface;
first and second substantially planar conductors, each conductor having a corresponding thickness and a peripheral edge, the planar conductors being disposed on the substrate's surface, the first conductor having a substantially rectangular-shaped first portion from which extends a substantially key-hole shaped second portion, the second conductor being substantially oarlock-shaped and partially surrounding the substantially key-hole shaped second portion of the first substantially planar conductor, the substantially oarlock-shaped portion having a break through which extends a part of the substantially rectangular-shaped first portion of the first conductor, the peripheral edges of the substantially key-hole shaped second portion and the substantially oarlock-shaped second conductor being separated from each other by a substantially C-shaped gap having a predetermined substantially uniform-width, the gap being located between the key-hole shaped portion and the oarlock-shaped portion, the gap also having a predetermined gap length;
a thin metallic film disposed on the top of the substantially key-hole shaped second portion and the substantially oarlock-shaped second conductor and extending across the substantially uniform width gap.

US Pat. No. 10,141,148

AFFIXED OBJECT, FUSIBLE LINK, AND AFFIXING STRUCTURE FOR FUSIBLE LINK

Yazaki Corporation, Toky...

1. An affixed object affixed to an affixing object including an installation surface portion, an intersection surface portion extending in a direction intersecting the installation surface portion, and a locking portion provided in the intersection surface portion, the affixed object comprising:an affixed-object body to be installed in the installation surface portion; and
a locking member, attached to the affixed-object body, including:
a locked portion to be locked to the locking portion;
a first arm portion extending from the affixed-object body along the installation surface portion;
a connection portion which is elastically deformed and has one end connected to an end portion of the first arm portion; and
a second arm portion having an end portion connected to the other end of the connection portion, extending along the intersection surface portion, and provided with the locked portion,
wherein the locking member is provided on a wall portion of the affixed-object body such that the affixed-object body is sandwiched between the locking member and the affixing object when the affixed object is affixed to the affixing object,
wherein the connection portion is bent such that the one end of the connection portion extends away from the installation surface portion as the connection portion extends away from the first arm portion, and the other end of the connection portion extends away from the intersection surface portion as the connection portion extends away from the second arm portion, and
wherein a gap is formed between the connection portion and the affixing object.

US Pat. No. 10,141,145

RELAY APPARATUS HAVING PLURALITY OF RELAYS AND RELAY SYSTEM INCORPORATING THE RELAY APPARATUS

NIPPON SOKEN, INC., Nish...

1. A relay apparatus, comprising:a first relay, the first relay comprising:
a first electromagnetic coil;
a first movable magnetic member;
a first electromagnetic coil; and
a first contact switch, the first contact switch being set to a predetermined one of a conducting condition and a non-conducting condition by a magnetic flux produced by the first electromagnetic coil acting on the first movable magnetic member;
a second relay, the second relay comprising:
a second electromagnetic coil;
a second movable magnetic member; and
a second contact switch, the second contact switch being set to a predetermined one of the conducting condition and non-conducting condition by a magnetic flux produced by the second electromagnetic coil acting on the second movable magnetic member;
a yoke, the yoke being configured to partially surround each of the first electromagnetic coil and the second electromagnetic coil;
a first magnetic circuit extending around the first electromagnetic coil and through a first core and the yoke, the relay apparatus being operable for producing a flow of a first magnetic flux via the first magnetic circuit by passing a current through the first electromagnetic coil;
a second magnetic circuit extending around the second electromagnetic coil and through a second core and the yoke, the relay apparatus being operable for producing a flow of a second magnetic flux via the second magnetic circuit by passing a current through the second electromagnetic coil; and
a third magnetic circuit extending successively through the first core, the yoke, and the second core, the relay apparatus being operable for producing a flow of a third magnetic flux via a third magnetic circuit by passing respective currents concurrently through the first electromagnetic coil and the second electromagnetic coil,
wherein the yoke comprises a magnetic flux restriction portion formed to restrict the flow of magnetic flux via the third magnetic circuit.

US Pat. No. 10,141,134

KEY SWITCH AND KEYBOARD

FUJITSU COMPONENT LIMITED...

1. A key switch comprising:a key top;
a pair of links that support the key top such that the key top is capable of being elevated and lowered; and
a switch that opens and closes a contact point in accordance with an elevating operation of the key top,
wherein each of the links includes
two arms,
a connection portion that connects the two arms,
two first shafts respectively formed at outer portions of the two arms, and
two second shafts respectively formed at inner portions of the two arms, and
wherein the key top includes
at least four first support portions each being provided with a first guide groove in which the respective first shaft is slidable, and
at least four second support portions each being provided with a second guide groove in which the respective second shaft is slidable.

US Pat. No. 10,141,133

ELECTRONIC DEVICE INCLUDING KEY

Samsung Electronics Co., ...

1. An electronic device including a key, comprising:a housing covering at least a portion of a front of an electronic device and having a lower portion that includes a through-hole formed therein;
a structure provided on a back side of the electronic device, wherein the structure comprises a lower part corresponding to the lower portion of the housing;
a key having a front surface at least partially exposed through the through-hole and a rear surface facing opposite the front surface, wherein the key is configured to be pressed by a user in a direction toward the structure;
a key switch located between the rear surface of the key and the structure, wherein the key switch is configured to enable the key to be pressed;
a dummy detachably provided between the housing and the structure, wherein the dummy, when attached, supports the key and the key switch such that the key and the key switch are capable of being pressed in the through-hole toward the direction of the structure;
a flange protruded from an outer periphery of the key; and
at least one or more adhesive members are provided between the lower surface of the dummy and the structure,
wherein the dummy, when attached, be stacked on the one or more adhesive members, and
wherein the dummy is provided on an upper surface of at least part of the flange.

US Pat. No. 10,141,127

HIGH-SPEED COMMUNICATIONS COUPLING FOR USE IN A CIRCUIT BREAKER ASSEMBLY

ABB Schweiz AG, Baden (C...

1. A secondary disconnect assembly for use with a circuit breaker moveable between a connected position and a disconnected position, said secondary disconnect assembly comprising:a first secondary disconnect apparatus comprising:
a first coupling portion comprising a body portion integrally formed with said first secondary disconnect apparatus, wherein said body portion at least partially houses at least one high speed communications connector, said first coupling portion further comprising a cover coupled to said body portion, configured to restrict movement of said high speed communications connector; and
a first alignment feature comprising a first pair of angled ramp surfaces; and
a second secondary disconnect apparatus comprising:
a second alignment feature configured to couple to said first alignment feature when the circuit breaker is in the connected position, wherein said second alignment feature comprises a second pair of angled ramp surfaces configured to mate with said first pair of angled surfaces when the circuit breaker is in the connected position; and
a second coupling portion removably coupled to said first coupling portion, said second coupling portion comprising at least one opening configured to receive said high speed communications connector when the circuit breaker is moved from the disconnected position to the connected position to enable high speed data transmission through said first coupling portion and said second coupling portion.

US Pat. No. 10,141,124

ELECTRONIC COMPONENT FABRICATION METHOD USING REMOVABLE SPACERS

Yen Technologies, LLC, W...

1. An apparatus comprising:a plurality of electrodes in a stack, wherein spacing between adjacent electrodes in the stack is determined by one or more removable spacers that are removed prior to bonding adjacent electrodes together to fix the spacing.

US Pat. No. 10,141,122

ELECTRIC DOUBLE LAYER CAPACITANCE DEVICE

EnerG2, Inc., Seattle, W...

1. An electrode comprising:A) an activated carbon material having a surface area of greater than about 1500 m2/g, as determined by nitrogen sorption at 77 K and BET analysis, and a pore structure comprising mesopores having a diameter ranging from about 2.0 nm to about 10.0 nm, a pore volume ranging from about 0.01 cc/g to about 0.25 cc/g for pores having a pore diameter of 0.6 nm to 1.0 nm, and micropores having an effective length of less than about 10 nm as determined by transmission electron microscopy (TEM) measurements; and
B) a metal oxide or conductive polymer,
the electrode further comprising a specific capacitance of at least 100 F/g and a specific power of at least 25 W/g as determined in an electric double layer capacitor device comprising the electrode and an electrolyte comprising equal volumes of propylene carbonate and dimethylcarbonate and further comprising about 1.0 M tetraethylammonium tetrafluoroborate.

US Pat. No. 10,141,119

DYE-SENSITIZED SOLAR CELLS INCLUDING CARBON NANOTUBE YARNS

Florida State University ...

1. A dye-sensitized solar cell, comprising:a working electrode comprising seven twisted carbon nanotube yarns;
a hybrid sensitizer which comprises:
a nanoporous titanium oxide layer coated on the seven twisted carbon nanotube yarns,
a microporous titanium oxide layer coated onto the nanoporous titanium oxide layer, and
dye particles and quantum dots disposed in the pores of the microporous titanium oxide layer, wherein the dye particles comprise N719 dye, and the quantum dots comprise CdS and CdSe;
a conducting electrode comprising one carbon nanotube yarn disposed about the hybrid sensitizer or three twisted carbon nanotube yarns disposed about the hybrid sensitizer; and
a solid state electrolyte disposed about the hybrid sensitizer.

US Pat. No. 10,141,118

CARRIER SYSTEM AND PHOTOELECTRIC CONVERSION DEVICE

ADEKA CORPORATION, Tokyo...

1. A carrier system comprising a carrier, a dye (A) and a co-adsorbent (B), wherein said dye (A) and co-adsorbent (B) are bonded or adsorbed to said carrier, and said co-adsorbent (B) is represented by general formula (1) below:
wherein, ring A represents a 5- or 6-membered heterocycle and may further be fused with another cyclic group;
a hydrogen atom in the ring A may be replaced by a halogen atom, a cyano group, a nitro group, an —OR2 group, an —SR2 group, or a hydrocarbon group that has a substituent or that is not substituted;
Z represents a divalent aliphatic hydrocarbon group that is interrupted zero to three times by —O—, —S—, —CO—, —COO—, —OCO—, —CONR3—, —NR3CO—, or —Z1—;
Z1 represents a divalent aromatic group;
R1 represents a group selected from a carboxylic acid group, a sulfonic acid group, a phosphoric acid group, and a phosphonic acid group;
R2 and R3 each independently represent a hydrogen atom or a hydrocarbon group that has a substituent or that is not substituted;
Anm? represents an m-valent anion;
m represents an integer of 1 or 2; and
p represents a coefficient for keeping the electrical charge neutral.

US Pat. No. 10,141,115

THIN FILM CAPACITOR INCLUDING ALTERNATIVELY DISPOSED DIELECTRIC LAYERS HAVING DIFFERENT THICKNESSES

SAMSUNG ELECTRO-MECHANICS...

1. A thin film capacitor comprising:a body having first and second electrode layers and first and second dielectric layers alternately stacked on a substrate, each of the number of the first dielectric layers, the number of the second dielectric layers, the number of the first electrode layers, and the number of the second electrode layers being two or greater; and
first and second vias electrically connected to the first and second electrode layers, respectively,
wherein a thickness of the first dielectric layer is 1.2 to 3 times that of the second dielectric layer.

US Pat. No. 10,141,114

MULTI-LAYER CERAMIC CAPACITOR AND METHOD OF PRODUCING THE SAME

Taiyo Yuden Co., Ltd., T...

1. A multi-layer ceramic capacitor, comprising:a body including
a first end surface and a second end surface that face each other,
a side surface that extends between the first end surface and the second end surface,
a first recess that extends along a first ridge of the first end surface and the side surface,
a second recess that extends along a second ridge of the second end surface and the side surface,
a first internal electrode that is drawn to the first end surface and the first recess, and
a second internal electrode that faces the first internal electrode and is drawn to the second end surface and the second recess;
a first external electrode that covers the body from the first end surface; and
a second external electrode that covers the body from the second end surface,
wherein a depth of the first recess from the first end surface is 30% or less of an interval between the first end surface and the second internal electrode, and a depth of the second recess from the second end surface is 30% or less of an interval between the second end surface and the first internal electrode.

US Pat. No. 10,141,110

MULTILAYER CERAMIC CAPACITOR AND BOARD HAVING THE SAME

SAMSUNG ELECTRO-MECHANICS...

1. A multilayer ceramic capacitor comprising:a ceramic body in which a plurality of dielectric layers are stacked and first and second internal electrodes are alternately disposed with respective dielectric layers interposed therebetween; and
first and second external electrodes disposed on first and second surfaces of the ceramic body opposite each other in a length direction, respectively, extending onto portions of a mounting surface of the ceramic body and portions of third and fourth surfaces of the ceramic body opposite each other in a width direction, respectively,
wherein the first internal electrode includes a first body portion disposed to be spaced apart from an edge of the dielectric layer in the length direction and first and second edges of the dielectric layer in the width direction and a first lead portion extending from the first body portion to be exposed to the first surface of the ceramic body in the length direction and portions of the third and fourth surfaces of the ceramic body in the width direction,
the second internal electrode includes a second body portion disposed to be spaced apart from the edge of the dielectric layer in the length direction and the first and second edges of the dielectric layer in the width direction and a second lead portion extending from the second body portion to be exposed to the second surface of the ceramic body in the length direction and portions of the third and fourth surfaces of the ceramic body in the width direction, and
first and second insulating layers are disposed on the third and fourth surfaces of the ceramic body opposite each other in the width direction, respectively, and each has a length shorter than a length of the ceramic body such that the first and second lead portions each contact the first and second insulating layers and a respective one of the first and second external electrodes on the third and fourth surfaces of the ceramic body.

US Pat. No. 10,141,109

POWER STORAGE MODULE

AutoNetworks Technologies...

1. A power storage module comprising:a plurality of power storage elements that each have cathode and anode electrode portions;
a connection member that connects the cathodes and anodes of the power storage elements to each other and is fixed to the power storage elements by a fixing means; and
an insulating protector in which the connection member is housed,
wherein the insulating protector includes an opposing portion that opposes one surface of the connection member, and a partition wall that surrounds the connection member, the partition wall including a withdrawal restriction portion that protrudes inward from the partition wall and extends in a cantilevered manner so that he withdrawal restriction portion is capable of bending deformation and restricts withdrawal of the connection member from another surface side of the connection member, and the opposing portion and the withdrawal restriction portion have a first clearance that is the sum of a clearance between the one surface of the connection member and the opposing portion and a separate clearance between the other surface of the connection member and the withdrawal restriction portion in a state where the connection member is fixed to the power storage elements by the fixing means, and
the insulating protector further includes a restriction portion that restricts movement relative to the power storage elements by an amount greater than or equal to a second clearance that is smaller than the first clearance.

US Pat. No. 10,141,107

MINIATURE PLANAR TRANSFORMER

Analog Devices, Inc., No...

1. An inductive device, comprising:a substrate;
a pair of half-shell magnetically-conductive housings each having a cavity and being joined together to define a first, enclosed cavity between them, and disposed fully within a second cavity in the substrate; and
primary and secondary windings provided spatially within the first cavity to provide magnetic coupling between them, the windings electrically insulated from each other by an insulator disposed between the windings that extends into the cavity of each of the half-shell magnetically-conductive housings, wherein terminals of the primary and secondary windings traverse to an exterior of the inductive device.

US Pat. No. 10,141,104

CONTACTLESS CONNECTOR

1. A contactless connector, comprising:an inductive coupling element having a coil winding;
a first contact lead and a second contact lead connected to the coil winding and carrying electric currents in opposing directions;
a base plate formed of a ferritic material and having a first lead receiving passageway receiving a contact lead of the first contact lead or the second contact lead, a second lead receiving passageway provided opposite the first lead receiving passageway receiving a contact lead of the other of the first contact lead or the second contact lead, an air gap extending continuously between the first and second lead receiving passageways and along a peripheral surface of the base plate and arranged in a magnetic path of a magnetic field induced by electric current flowing through the contact lead of the first contact lead or the second contact lead, and a component receiving passageway, a portion of the air gap along the peripheral surface of the base plate is filled with a non-magnetic material;
an inner ferrite element formed as a single part with the base plate, the component receiving passageway extending through the base plate and the inner ferrite element; and
an outer ferrite element partially surrounding the inductive coupling element, magnetically coupled to the base plate, and open to the inductive coupling element at a mating end of the outer ferrite element opposite the base plate.

US Pat. No. 10,141,102

REACTOR

AutoNetworks Technologies...

1. A reactor comprising:an assembly having a magnetic core and a coil that has a winding portion bounding an opening; and
a temperature sensor that measures the temperature of the reactor,
wherein the magnetic core has an inner core portion that is inserted into the opening of winding portion, and a sensor disposition groove is formed in an outer peripheral face of the inner core portion and is disposed inside the opening of the winding portion,
the inner core portion is constituted by a composite material that includes a soft magnetic powder and a resin, and
the temperature sensor is provided in the sensor disposition groove.

US Pat. No. 10,141,101

TRANSFORMER AND SWITCHED-MODE POWER SUPPLY APPARATUS

Tamura Corporation, Toky...

1. A transformer, comprising:a core having a linear center leg portion in a center portion thereof;
a primary winding that is provided around the linear center leg portion of the core and is configured to be electrically connected to an external power source, wherein the primary winding creates a varying flux in the core in response to an input voltage applied from the external power source;
at least two secondary windings provided around the linear center leg portion of the core and having a winding axis which is the same as a winding axis of the primary winding, wherein each of the at least two secondary windings is configured to induce a voltage in response to the created varying flux in the core in order to provide the induced voltage to a load; and
at least two auxiliary windings provided around the linear center leg portion of the core and having a winding axis which is the same as the winding axis of the primary winding, the auxiliary windings respectively neighboring the secondary windings, wherein each of the at least two auxiliary windings is configured to induce a voltage in response to the created varying flux in the core, the auxiliary windings being connected with each other in a parallel electric connection,
wherein the auxiliary windings are electrically connected with a control circuit for controlling a switching element which is electrically connected with the primary winding and the auxiliary windings provide the control circuit with the induced voltage for driving the switching element, and
wherein the secondary windings are disposed at both sides of the primary winding in a winding axis direction of the primary winding and are disposed closer to the primary winding than the auxiliary windings, in the winding axis direction of the primary winding.

US Pat. No. 10,141,100

COMMON-MODE NOISE REDUCTION

GOOGLE LLC, Mountain Vie...

1. A converter circuit comprising:a magnetic core; and
a coil assembly, the coil assembly including:
a primary winding assembly comprising a conductive medium arranged in at least a first primary winding layer, a second primary winding layer, and a third primary winding layer;
a secondary winding assembly comprising a conductive medium arranged in at least a first secondary winding layer and a second secondary winding layer; and
an auxiliary winding assembly comprising a conductive medium arranged in at least one auxiliary winding layer, the at least one auxiliary winding layer comprising an auxiliary winding layer disposed adjacent to a layer of the at least one primary winding layer and adjacent to a layer of the at least one secondary winding layer, wherein:
the first secondary winding layer is adjacent to the first primary winding layer;
the first primary winding layer is adjacent to the second secondary winding layer;
the second secondary winding layer is adjacent to the auxiliary winding layer;
the auxiliary winding layer is adjacent to the second primary winding layer; and
the second primary winding layer is adjacent to the third primary winding layer.

US Pat. No. 10,141,098

COIL COMPONENT

Murata Manufacturing Co.,...

1. A coil component comprising:a core having a winding core portion and first and second flange portions disposed on opposite ends of the winding core portion in a length direction, each of the first and second flange portions having an end surface to which a respective one of the opposite ends of the winding core portion is connected;
a plurality of wires wound around the winding core portion; and
a plurality of electrode portions disposed on bottom surfaces of the first and second flange portions and connected to the plurality of wires, wherein
the plurality of wires includes two wires crossing each other at the first flange portion,
the first flange portion has a groove adjacent to a position of crossing of the two wires,
the lower one of the two wires passes through the groove and the upper one of the two wires does not pass through the groove so that the two wires are separated from each other,
the first flange portion has a protrusion adjacent to the position of crossing of the two wires, and the upper one of the two wires passes through the protrusion so that the two wires are separated from each other, and
the protrusion and the groove being disposed on an end edge of the bottom surface of the first flange portion and directly adjacent to each other, the end edge being adjacent to the end surface of the first flange portion, and the protrusion protruding from the end surface of the first flange portion.

US Pat. No. 10,141,096

ENERGY SAVING DEVICE WITH INDUCTIVE CAPACITIVE REACTOR

Basic Power, Inc., East ...

1. An energy saving device for reducing electrical consumption utilizing at least one inductive capacitive reactor, for residential and similar amperage needs, wherein that at least one reactor functions as a multifaceted transformer with both inductive and capacitor functionalities and that operates iteratively, which comprises:a.) components of an energy saving device that includes: an EMI filter; surge suppression mechanism; harmonic filters; a snubber network filter; and storage components; and
b.) at least one inductive capacitive reactor, wherein said at least one inductive capacitive reactor includes a stacked group of hollow centered continuous loop components sequentially arranged as follows:
(i) a first ferrite toroidal component;
(ii) a first separator component, being a doped separator component;
(iii) a non-magnetic conductive metal toroidal component having a plurality of protrusions with notches between said protrusions;
(iv) a second separator component, selected from the group consisting of doped and non-doped;
(v) a second ferrite toroidal component;
and windings, including:
(vi) at least a first incoming wire being wrapped around a portion of at least said first ferrite toroidal component, being a hot wire;
(vii) at least a second incoming wire being wrapped around a portion of at least a first ferrite toroidal component, being a ground wire.

US Pat. No. 10,141,092

POCKET HOLSTER

1. A system for carrying a device, comprising:at least one first ferromagnetic area disposed on at least one surface of the device;
at least one second ferromagnetic area configured to interact with the at least one first ferromagnetic area, the at least one second ferromagnetic area including at least:
a first raised area;
a second recessed area; and
a third raised area, wherein the first and third raised areas are substantially co-planar; and
at least one magnet configured to be removably received by the at least one second ferromagnetic area, the at least one magnet configured to fit within the second recessed area.

US Pat. No. 10,141,091

MAGNETOPLUMBITE-TYPE FERRITE MAGNETIC MATERIAL AND SEGMENT-TYPE PERMANENT MAGNET DERIVED THEREFROM

UNION MATERIALS CORPORATI...

1. A ferrite magnetic material comprising a primary phase of a hexagonal magnetoplumbite ferrite, the primary phase having a composition represented by formula (I):Ca(1-x-y-z)SrxBayAzFe(2n-m1-m2)Mm1M?m2O19  (I)wherein,A is bismuth (Bi) and at least one element selected from the group consisting of La, Nd, Pr, and Sm, with La being essentially contained in A;
M is at least one element selected from the group consisting of Co, Mn, Ni, and Zn, with Co being essentially contained in M;
M? is Cr;
0.02?x?0.3;
0.02?y?0.09;
0.35?z?0.5;
0.2?m1?0.4;
0.02?m2?0.07;
9.0?2n?11.0,wherein the values of x, y and m2 satisfy the conditions of 0.1?x+y<0.3, and 0.04?y+m2?0.16, and wherein the values of x, y, z, m1 and m2 satisfy the conditions of 0.09?y/(x+y)?0.5, 0.3?(x+y)/(m1+m2)?0.8, and 1.4?(1?z)/(m1+m2)?1.6.

US Pat. No. 10,141,050

PAGE WRITES FOR TRIPLE LEVEL CELL FLASH MEMORY

Pure Storage, Inc., Moun...

1. A method for page writes for triple level cell, or higher level cell, flash memory, comprising:receiving data in a storage system, from a client that is agnostic of page write requirements for the triple level cell, or higher level cell, flash memory, wherein the page write requirements specify an amount of data and a sequence of writing data for a set of pages to assure read data coherency for the set of pages;
accumulating the received data, in random-access memory (RAM) in the storage system to satisfy the page write requirements for the triple level cell, or higher level cell, flash memory in the storage system; and
writing at least a portion of the accumulated data in accordance with the page write requirements, from the RAM to the triple level cell, or higher level cell, flash memory in the storage system as an atomic write, wherein the page write requirements for the triple level cell, or higher level cell, flash memory comprise writing a lower page, an upper page and an extra page to assure read coherency of cells, and the writing at least the portion of received data comprises writing the lower page, the upper page and the extra page as the atomic write.

US Pat. No. 10,141,020

DISPLAY DEVICE AND DRIVE METHOD FOR SAME

SHARP KABUSHIKI KAISHA, ...

1. A current drive-type display device, comprising:a plurality of pixels arranged two-dimensionally, each including a display element and a drive element provided in series with the display element to control an amount of a current flowing through the display element;
a current measurement circuit configured to measure a current which passes through the drive element and is output to an outside of the pixel, without passing through the display element;
a correction calculation unit configured to correct a video signal based on a current measurement result by the current measurement circuit; and
a drive circuit configured to write a voltage in accordance with a corrected video signal to the pixel, wherein the correction calculation unit includes:
a light emission current efficiency calculation unit configured to obtain a light emission current efficiency of the display element for each pixel based on the current measurement result;
a first correction unit configured to correct the video signal for each pixel in view of characteristics of each pixel, based on the current measurement result and the light emission current efficiency; and
a second correction unit configured to obtain a correction term for each pixel in view of a difference in the light emission current efficiency compared to neighboring pixels, based on a two-dimensional distribution of the light emission current efficiency, and
the correction calculation unit is configured to obtain the corrected video signal based on the video signal corrected by the first correction unit and the correction term obtained by the second correction unit; wherein
the correction calculation unit comprising:
a light emission current efficiency storage unit configured to store for each pixel a light emission current efficiency obtained by the light emission current efficiency calculation unit.

US Pat. No. 10,141,019

OPTICAL DISK DRIVE

Acer Incorporated, New T...

1. An optical disk drive (ODD), comprising:a housing;
a tray, movably disposed at the housing to move into or move out of the housing;
a panel, connected to the tray and located at a side of the housing;
a first linkage, rotatably disposed on the panel and located between the housing and the panel; and
a second linkage, rotatably disposed on the panel and located between the first linkage and the panel,
by rotating the first linkage with respect to the panel in a first rotating direction, the second linkage being pushed by the first linkage and rotating with respect to the panel in a second rotating direction opposite to the first rotating direction so as to actuate the tray to move out of the housing.

US Pat. No. 10,141,017

LUBRICANT FOR MAGNETIC RECORDING MEDIUM, AND MAGNETIC RECORDING MEDIUM

Dexerials Corporation, T...

1. A lubricant for a magnetic recording medium, comprising:an ionic liquid including a Bronsted acid and a Bronsted base that is primary amine as constituents of the ionic liquid,
wherein the Bronsted acid includes a fluorine-containing chain,
wherein the Bronsted base includes a fluorine-containing chain that is a perfluoroalkyl chain or a perfluoropolyether chain,
wherein the fluorine-containing chain in the Bronsted acid is a perfluoropolyether chain or the fluorine-containing chain in the Bronsted base is the perfluoropolyether chain, or the fluorine-containing chain in the Bronsted acid is the perfluoropolyether chain and the fluorine-containing chain in the Bronsted base is the perfluoropolyether chain, and
wherein a number average molecular weight of the fluorine-containing chain in the Bronsted acid is 1,500 or less.

US Pat. No. 10,141,013

SHINGLED MAGNETIC RECORDING DEVICE CAPABLE OF SETTING TRACK-PITCH AT TARGET TRACK AND TWO ADJACENT TRACKS

Kabushiki Kaisha Toshiba,...

1. A magnetic disk device comprising:a disk;
a head which writes data to the disk; and
a controller which sets a first track pitch between a first track of the disk and a second track away from the first track in a first direction of a radial direction of the disk based on fringing when the second track is written, sets a second track pitch between the first track and a third track away from the first track in a second direction opposite to the first direction based on fringing when the third track is written, calculates a difference between the first track pitch and the second track pitch, sets, when the difference is less than or equal to a reference value, an area to which the first track is written in a first recording area for wiring a track to a position away from an adjacent track, and sets, when the difference is greater than the reference value, the area to which the first track is written in a second recording area for writing a track such that the track partially overlaps an adjacent track.

US Pat. No. 10,141,012

MANUAL TO AUTOMATIC TURNTABLE PLAYER CONVERSION

1. A conversion device for converting a manual record player to an automatic record player, the manual record player having a housing, a turntable, and a tonearm, the tonearm being structured for movement between a rest position and a record ending position adjacent to a central portion of the turntable, the tonearm defining a range of tonearm motion between the rest position and the record ending position, the conversion device comprising:a base unit that is structured to be secured to the housing of the manual record player below a portion of the range of motion of the tonearm, the base unit comprising:
a piston assembly, comprising:
a piston, the piston being movable between a lower position and an upper position, the piston being structured to engage a piston-engaging tonearm element, and to elevate the tonearm, when the piston is in its upper position, the piston being further structured to disengage the piston-engaging tonearm element when in the lower position;
a first motor assembly, the first motor assembly being structured to move the piston between its lower position and its upper position;
a drive assembly having a second motor assembly, the second motor assembly being operatively connected to the piston assembly, the drive assembly being structured to move the piston assembly between a first position and a second position, the first position corresponding to the rest position of the tonearm, the second position corresponding to the record ending position of the tonearm; and
a control system, the control system being structured to selectively raise and lower the piston, and to selectively move the piston assembly towards the first position and the second position;
whereby the tonearm may be moved to a preselected position by moving the piston assembly under the piston-engaging tonearm element, raising the piston, moving the piston generally horizontally until the tonearm is in a preselected position, and lowering the piston.

US Pat. No. 10,141,010

AUTOMATIC CENSORING OF OBJECTIONABLE SONG LYRICS IN AUDIO

Google LLC, Mountain Vie...

1. A method of censoring audio data comprising:receiving audio data comprising a tag and first amplitude data as a function of time, wherein the first amplitude data represents a plurality of spoken words occurring over a duration, as well as non-spoken word sounds overlapping with at least some of the spoken words during the duration;
accessing a database with the tag to obtain a set of lyrics comprising a plurality of words;
comparing the words in the lyrics to a blacklist to identify a subset of blacklisted words;
processing, by a processor, both the set of lyrics and the first amplitude data together to identify a plurality of starting timestamps in the first amplitude data, each of the starting timestamps indicating a time during the duration when one of the subset of blacklisted words begins in the first amplitude data, wherein the processing comprises matching, by the processor, the first amplitude data to training data comprising second amplitude data representing identified spoken phonemes of at least one spoken word sound related to the subset of blacklisted words;
identifying, by the processor, the plurality of starting timestamps based on the matching;
adjusting, by the processor, the first amplitude data by replacing the first amplitude data starting at the starting timestamps of the subset of blacklisted words with other amplitude data to render the audio at the subset of blacklisted words inaudible; and
providing, by the processor, the adjusted first amplitude data for playback of the audio data.

US Pat. No. 10,141,003

NOISE LEVEL ESTIMATION

Dolby Laboratories Licens...

1. A method for noise level estimation, comprising:responsive to an increase of a signal level of a noise signal, calculating an impulsive noise probability of the noise signal, the impulsive noise probability indicating a likelihood that the noise signal is an impulsive noise;
determining a variable smoothing factor for noise level estimation based on the impulsive noise probability, the variable smoothing factor being associated with a previous estimated level of the noise signal; and
smoothing the noise signal with the variable smoothing factor so as to determine a current estimated level of the noise signal.

US Pat. No. 10,141,002

COMMUNICATION DEVICES AND METHODS FOR TEMPORAL ANALYSIS OF VOICE CALLS

Plantronics, Inc., Santa...

1. A headset comprising:a communications interface to receive a remote call participant speech from a remote call participant during a voice call;
a microphone arranged to receive a headset wearer speech during the voice call;
a speaker arranged to output the remote call participant speech during the voice call; and
a processor configured to analyze the remote call participant speech to identify a speech characteristic of the remote call participant and determine a headset wearer call performance utilizing the speech characteristic of the remote call participant, the processor further configured to analyze the headset wearer speech to determine the headset wearer call performance by determining a temporal analysis metric of the speech characteristic of the remote call participant relative to the headset wearer speech, and the processor further configured to send an alert message over the communications interface if the headset wearer call performance indicates a problematic voice call.

US Pat. No. 10,141,000

HIERARCHICAL DECORRELATION OF MULTICHANNEL AUDIO

GOOGLE LLC, Mountain Vie...

1. A method for encoding an audio signal comprised of a plurality of channels, the method comprising:segmenting an audio signal into frames;
transforming each of the frames into a frequency domain representation;
estimating, for each frame, a signal model;
quantizing the signal model for each frame;
performing hierarchical decorrelation using the frequency domain representation and the quantized signal model for each of the frames; and
quantizing an outcome of the hierarchical decorrelation using a quantizer,
wherein performing the hierarchical decorrelation includes:
selecting a set of channels, of the plurality of channels of the audio signal, based on a number of bits saved for audio compression;
performing a unitary transform on the selected set of channels, yielding a set of decorrelated channels; and
combining the set of decorrelated channels with remaining channels of the plurality of channels other than the selected set of channels.

US Pat. No. 10,140,999

METHOD AND APPARATUS FOR TRANSMITTING AND RECEIVING OF THE OBJECT-BASED AUDIO CONTENTS

ELECTRONICS AND TELECOMMU...

1. A method of transmitting object-based audio contents comprising:identifying a plurality of elementary stream related to an object;
packetizing the plurality of elementary stream using a PID (packet identification);
generating an object-based audio contents including the packetized elementary stream,
wherein the object-based audio contents includes the 3D location information of the object represented in the 3D coordinate axis (X, Y, and Z), and a volume of the object,
wherein the object-based audio contents include common information related to the object,
wherein the common information includes at least one of a length of packet, a type of the elementary streams, and time information related to the elementary streams.

US Pat. No. 10,140,991

USING AUDIO CHARACTERISTICS TO IDENTIFY SPEAKERS AND MEDIA ITEMS

Google LLC, Mountain Vie...

1. A method performed by one or more computers, the method comprising:receiving, by the one or more computers, a request from a client device for media content, the request including at least a portion of a first media item or a URL corresponding to the first media item, the first media item including speech of a person;
based on the data indicating the first media item, selecting, by the one or more computers, one or more other media items based on one or more representations of acoustic characteristics of the one or more other media items,
wherein the one or more representations of acoustic characteristics of the one or more other media items comprise, for each of the one or more other media items, a speaker representation that includes (i) an i-vector or d-vector generated from the other media item, or (ii) a hash of an i-vector or d-vector generated from the other media item;
wherein each of the one or more other media items is selected based on a comparison of (i) an i-vector, d-vector or hash determined from speech in the first media item with (ii) the speaker representation for the other media item,
wherein:
each of the selected one or more other media items is different from the first media item;
each of the selected one or more other media items includes speech of the same person whose speech is included in the first media item; and
each of the selected one or more other media items is determined, based on the acoustic characteristics of the media item, to include speech demonstrating speaker characteristics that have at least a threshold level of similarity with speaker characteristics determined from speech in the first media item;
generating, by the one or more computers, data indicating the selected one or more other media items that are each different from the first media item and that each include speech of the same person whose speech is included in the first media item; and
providing, by the one or more computers and to the client device, a response to the request that includes the data indicating the selected one or more other media items that are each different from the first media item and that each include speech of the same person whose speech is included in the first media item.

US Pat. No. 10,140,981

DYNAMIC ARC WEIGHTS IN SPEECH RECOGNITION MODELS

Amazon Technologies, Inc....

1. A system comprising:a computer-readable memory storing executable instructions; and
one or more processors in communication with the computer-readable memory, wherein the one or more processors are programmed by the executable instructions to at least:
obtain audio data, generated by a microphone, regarding an utterance of a user;
obtain context information regarding a context associated with the utterance;
obtain a language model comprising a finite state transducer, wherein the finite state transducer comprises a plurality of states and a plurality of weights, and wherein the plurality of weights comprises:
a first default weight corresponding to a transition from a first state of the plurality of states to a second state of the plurality of states; and
a second default weight corresponding to a transition from the first state to a third state of the plurality of states;
select a replacement weight, from a plurality of predetermined replacement weights that correspond to the transition from the first state to the second state,
wherein the replacement weight is selected from the plurality of predetermined replacement weights based at least partly on the context information,
wherein the context information indicates the utterance is associated with a first context,
wherein the transition from the first state to the second state is a transition to a portion of the finite state transducer comprising a first subset of states trained for recognition of a first plurality of words associated with the first context,
wherein the transition from the first state to the third state is a transition to a portion of the finite state transducer comprising a second subset of states trained for recognition of a second plurality of words associated with a second context different than the first context, and
wherein use of the replacement weight increases a likelihood of the transition from the first state to the second state in comparison with a transition from the first state to the third state;
replace the first default weight in the language model with the replacement weight, wherein a third default weight corresponding to a transition from the second state to a fourth state remains part of the language model during use of the language model with the replacement weight;
generate speech recognition results using the audio data, the language model, and the replacement weight, wherein a quantity of states of the finite state transducer is the same during use of the replacement weight as when using the first default weight; and
present, via a user interface, a response to the utterance, wherein the response is based at least partly on the speech recognition results.

US Pat. No. 10,140,980

COMPLEX LINEAR PROJECTION FOR ACOUSTIC MODELING

Google LCC, Mountain Vie...

1. A computer-implemented method comprising:receiving, by one or more computers, audio data corresponding to an utterance;
generating, by the one or more computers, frequency domain data using the audio data;
processing, by the one or more computers, the frequency domain data using complex linear projection;
providing, by the one or more computers, the processed frequency domain data to a neural network trained as an acoustic model; and
generating, by the one or more computers, a transcription for the utterance that is determined based at least on output that the neural network provides in response to receiving the processed frequency domain data.

US Pat. No. 10,140,978

SELECTING ALTERNATES IN SPEECH RECOGNITION

Google LLC, Mountain Vie...

1. A method comprising:obtaining, by one or more computers, acoustic data for an utterance;
determining, by the one or more computers, speech recognition candidates for the utterance based on the acoustic data;
obtaining, by the one or more computers, a ranking of the speech recognition candidates determined by a speech recognizer;
selecting, by the one or more computers, a transcription for the acoustic data from among the speech recognition candidates;
determining, by the one or more computers, feature scores from the ranking of the speech recognition candidates;
generating, by the one or more computers, a classifier output for each of at least some of the speech recognition candidates, wherein each of the classifier outputs is an output that a trained machine learning classifier provided in response to receiving at least one of the feature scores as input;
selecting, by the one or more computers, a subset of the speech recognition candidates based on the classifier outputs of the trained machine learning classifier; and
providing, by the one or more computers and for display at a client device, data indicating (i) the transcription for the utterance and (ii) the subset of the speech recognition candidates as a set of alternative transcriptions for the utterance, wherein the one or more computers are configured to provide different quantities of alternative transcriptions for different utterances.

US Pat. No. 10,140,977

GENERATING ADDITIONAL TRAINING DATA FOR A NATURAL LANGUAGE UNDERSTANDING ENGINE

botbotbotbot Inc., Palo ...

1. A system comprising one or more computers and one or more storage devices storing instructions that when executed by the one or more computers cause the one or more computers to perform operations comprising:obtaining, during operation of a computer-implemented dialogue system comprising a natural language understanding engine, data identifying (i) a first input conversational turn that was provided as input to the natural language understanding engine during a dialogue between a user and the computer-implemented dialogue system and (ii) a first annotation of the first input conversational turn generated by the natural language understanding engine, wherein the natural language understanding engine has been trained on a first set of training data comprising a plurality of training conversational turns;
determining that the first annotation accurately characterized the first input conversational turn;
determining, based on the training conversational turns in the first set of training data, that the natural language understanding engine is likely to generate inaccurate annotations of other conversational turns that are similar to the first input conversational turn;
in response to determining that (i) the first annotation accurately characterized the first input conversational turn but (ii) the natural language understanding engine is likely to generate inaccurate annotations of other conversational turns that are similar to the first input conversational turn:
obtaining one or more first paraphrases of the first input conversational turn; and
generating, for each of the one or more first paraphrases, a respective first training example that identifies the first annotation as the correct annotation for the first paraphrase; and
training the natural language understanding engine on at least the first training examples.

US Pat. No. 10,140,975

SPEECH ENDPOINTING BASED ON WORD COMPARISONS

Google LLC, Mountain Vie...

1. A computer-implemented method comprising:receiving, from a given user and by a microphone of a mobile device that includes (i) the microphone, (ii) an automated speech recognition system, and (iii) an end of utterance detector that is configured to identify an endpoint of an utterance spoken by a user in response to determining that a speaker has stopped speaking for a fixed duration, a first utterance;
determining, by the end of utterance detector, that the given user has stopped speaking for the fixed duration after the first utterance;
generating, by the automated speech recognition system, a first transcription of the first utterance;
based on the first transcription of the first utterance, maintaining the microphone in an active state without endpointing the first utterance;
after the given user has stopped speaking for at least the fixed duration after the first utterance, receiving, by the microphone and from the given user, a second utterance;
generating, by the automated speech recognition system, a second transcription of the second utterance;
based on both the first transcription and the second transcription, deactivating the microphone and endpointing the second utterance;
in response to endpointing the second utterance, submitting, by the mobile device, a single search query that includes both the first transcription and the second transcription;
receiving, by the mobile device, search results in response to the single search query that includes both the first transcription and the second transcription; and
providing, for output by the mobile device, the search results.

US Pat. No. 10,140,969

MICROPHONE ARRAY DEVICE

FUJITSU LIMITED, Kawasak...

1. A microphone array device comprising:a memory, and
a processor coupled to the memory and configured to execute a process, the process comprising:
obtaining a first sound signal that is input from a first microphone;
obtaining a second sound signal that is input from a second microphone different from the first microphone;
generating first spectra obtained by converting the first sound signal into frequency components;
generating second spectra obtained by converting the second sound signal into the frequency components;
calculating phase spectrum differences between the first spectra and the second spectra for each of the frequency components based on the first spectra and the second spectra;
obtaining an evaluation parameter to evaluate an influence of a non-target sound on a target sound based on a spectrum, whose direction indicated by the phase spectrum difference for the each of the frequency components is included in a predetermined suppression range, among the first spectra;
controlling the predetermined suppression range based on the evaluation parameter; and
suppressing the non-target sound included in the first spectra based on the predetermined suppression range controlled based on the evaluation parameter.

US Pat. No. 10,140,967

MUSICAL INSTRUMENT WITH INTELLIGENT INTERFACE

Magic Instruments, Inc., ...

1. A device for playing music with a configurable playing interface, comprising:a housing,
a plurality of chord selectors displaced on the housing;
an actuator displaced on the housing;
an antenna and circuitry for communication with a remote device, the antenna in communication with the circuitry for communication with the remote device, the circuitry for communication with the remote device displaced within the housing;
logic connected to the plurality of chord selectors and the actuator that maps note data to the plurality of chord selectors, the note data mapped to the plurality of chord selectors based on a key and scale selection associated with the device,
the logic outputting note data in response to a first input received to a selected chord selector of the plurality of chord selectors and a second input to the actuator, the note data output to audio processing circuitry that creates audio based on the note data, the circuitry for communication with the remote device communicating at least one of the note data and the audio to the remote device; and
logic for automatically mapping note data to each chord selector based on the selected scale and the selected key.

US Pat. No. 10,140,965

AUTOMATED MUSICAL PERFORMANCE SYSTEM AND METHOD

YAMAHA CORPORATION, Shiz...

1. A performance system comprising:a performance controller configured to cause a performance device to carry out an automatic performance of a musical piece; and
a notification controller configured to cause a notification device to carry out an operation to visually notify a performer of an actual performance of the musical piece of the progress of the automatic performance,
the notification controller being configured to cause the notification device to carry out a normal operation to visually notify the performer of continuous change of a normal body movement of a virtual performer of the performance device for carrying out the automatic performance of the musical piece,
the notification controller being further configured to cause the notification device to carry out an instruction operation, before notifying the performer of the continuous change of the normal body movement, to visually notify the performer of a special body movement of the virtual performer, the special body movement being visually distinguished from the normal body movement.

US Pat. No. 10,140,960

AUTOMATIC ADJUSTABLE DISPLAY SYSTEM AND ADJUSTING METHOD AND ADJUSTING DEVICE THEREOF

BOE TECHNOLOGY GROUP CO.,...

1. An automatic adjustable display system, comprising a display unit, an image acquiring unit, a control unit and an implementing unit, wherein:the image acquiring unit is configured to acquire a user image of a user in real time and to send the user image to the control unit;
the control unit comprises:
memory;
one or more processors; and
one or more modules stored in the memory and configured for execution by the one or more processors, the one or more modules comprising instructions that are executable to receive and analyze the user image to determine user state information, and to generate a first adjusting instruction for adjusting a distance between the display unit and the user and send the first adjusting instruction to the implementing unit when the user state information meets a first preset condition; and
the implementing unit is configured to receive the first adjusting instruction sent by the control unit and adjust the distance between the user and the display unit according to the first adjusting instruction,
wherein the user state information includes a ratio between a width of the user's head and a width of the user's shoulder in the user image,
wherein the one or more modules comprise instructions that are executable to analyze the user images to determine the ratio between the width of the user's head and the width of the user's shoulder, and to send a warning instruction for warning the user to maintain a proper seated gesture to the implementing unit, when the ratio between the width of the user's head and the width of the user's shoulder in each of the plurality of successive user images falls outside a third predetermined range.

US Pat. No. 10,140,959

MOBILE TERMINAL AND METHOD OF CONTROLLING THE SAME

LG ELECTRONICS INC., Seo...

1. A mobile terminal comprising:a display; and
a controller configured to:
cause the display to display a home screen page comprising a plurality of graphic objects;
set a specific region of the home screen page based on a first touch input received on the home screen page, the first touch input received while the plurality of graphic objects are displayed on the home screen page;
cause the display to display a guide image indicating the specific region when the specific region is set, the guide image displayed on the home screen page comprising the plurality of graphic objects;
detect a graphic object displayed in the specific region or overlapping the specific region when the specific region is set, wherein a visual effect is applied to the detected graphic object such that the detected graphic object is visually distinguished from other graphic objects of the plurality of graphic objects;
cause the display to display a plurality of images indicating expected output regions where the detected graphic object is to be displayed while the graphic object and the guide image are displayed on the home screen page, wherein the plurality of images are displayed outside of the specific region;
cause the display to display the detected graphic object at a first region of the home screen page corresponding to a first image of the plurality of images in response to a second touch input received at the first image, the second touch input received while the graphic object and the plurality of images are displayed on the home screen page; and
cause the display to stop displaying the plurality of images when the graphic object is displayed at the first region of the home screen page,
wherein the first image is replaced by the graphic object when the graphic object is displayed at the first region of the home screen page such that the graphic object is no longer displayed in the specific region or overlapping the specific region.

US Pat. No. 10,140,958

MANAGING MULTIPLE SYSTEMS IN A COMPUTER DEVICE

STMicroelectronics (Greno...

1. A computer device, comprising:a first processing system having at least one processing core configured to concurrently execute at least two computer programs stored in a memory, the at least two computer programs including a first computer program that stores first displayable graphics data in a first virtual frame buffer and a second computer program that stores second displayable graphics data in a second virtual frame buffer, the first processing system having a resource manager configured to manage at least one resource and configured to deliver program execution output from both the first computer program and the second computer program via an output resource;
a set of resources dedicated to the first processing system wherein the set of resources includes the output resource; and
a second processing system coupled to the set of resources and configured to execute the second computer program, the second processing system having a supervisor application configured to grant control to individual resources of the set of resources to the resource manager of the first processing system, wherein the first processing system has access to the individual resources only after the supervisor application has granted control of the individual resources, wherein control of the output resource is granted by the supervisor application to the first processing system transparently to the first computer program, wherein a first portion of a display is driven by the first displayable graphics data from the first computer program in the first virtual frame buffer and a second portion of the display is driven by the second displayable graphics data from the second computer program in the second frame buffer.

US Pat. No. 10,140,939

DATA CONVERSION METHOD AND DISPLAY DEVICE USING THE SAME

Sitronix Technology Corp....

1. A data conversion method for converting display data of a display device, the data conversion method comprising:detecting an ambient temperature of the display device;
receiving a specific display data to be displayed by the display device, a previous display data in N row before the specific display data, and a next display data in N row after the specific display data;
converting the specific display data into a display output data according to the previous display data, the next display data and the ambient temperature; and
outputting the display output data to perform displaying;
wherein the step of converting the specific display data into the display output data according to the previous display data, the next display data and the ambient temperature comprises:
obtaining a lookup table corresponding to the ambient temperature; and
obtaining the display output data from the lookup table according to a first data change amount between the previous display data and the specific display data and a second data change amount between the specific display data and the next display data;
wherein the display output data is same as the specific display data or the display output data is nearer to the next display data in comparison with the specific display data when the first data change amount is smaller than a data change threshold corresponding to the ambient temperature and the second data change amount is greater than the data change threshold.

US Pat. No. 10,140,932

SIMULTANEOUS WIDE LIGHTING DISTRIBUTION AND DISPLAY

ABL IP Holding LLC, Cony...

1. A luminaire comprising:a general illumination device for illumination of a space, including:
an array of illumination light source emitters controllable to emit illumination lighting for the space;
an image display device configured to display an image, including:
a pixel matrix including an array of pixel light emitters, each pixel light emitter being controllable to emit light for a respective pixel of the displayed image;
gaps between pixel light emitters of the pixel matrix;
a light waveguide grid including an array of waveguides coupling a respective illumination light source emitter of the general illumination device with at least one respective gap between pixel light emitters of the image display device, each waveguide having a housing including:
an input interface optically coupled to the respective illumination light source emitter to steer illumination lighting from the illumination light source emitter;
an output interface opposing the input interface and optically coupled to the at least one respective gap; and
at least one reflective wall having an internal reflective surface encompassing and extending from the input interface and the output interface;
wherein each waveguide housing is hollow and each waveguide housing further comprises:
a curved optical element positioned over the illumination light source emitter and optically coupled to the input interface of the waveguide and the illumination light source emitter to steer the illumination lighting from the illumination light source emitter through the waveguide; and
the curved optical element includes a transparent convex dome surface of the input interface that is integral with the waveguide housing, curves inwards towards the output interface, and is positioned adjacent to the illumination light source emitter.

US Pat. No. 10,140,931

SHADOW MASK ASSEMBLIES AND REUSING METHODS OF SHADOW MASK ASSEMBLIES THEREOF

Shenzhen China Star Optoe...

1. A backlight control circuit for adjusting the current of an LED module of an electronic device, the LED module comprises a positive terminal, a ground terminal, and at least one LED lamp and a detection resistor connected between the positive terminal and the ground terminal, wherein, the backlight control circuit comprises:a driving chip comprising a feedback terminal, a reference voltage terminal and an output terminal, the reference voltage terminal is connected with a reference voltage;
a feedback voltage regulating unit connected between the feedback terminal of the driving chip and a remote terminal of the detection resistor for adjusting the detection voltage of the remote terminal of the detection resistor to the feedback terminal voltage of the feedback terminal; and
a power supply regulating unit connected between the power supply circuit of the electronic device and the positive terminal of the LED module and connected with the output terminal of the driving chip for adjusting the power supply circuit to output to a supply voltage of the LED module in response to the control of the driving chip;
wherein the feedback voltage adjustment unit is also connected to a 2D/3D signal terminal for receiving a two-dimensional signal or a three-dimensional signal generated by the 2D/3D signal terminal, wherein the 2D/3D signal terminal generates a two-dimensional signal when the electronic device is in the two-dimensional mode and generates a three-dimensional signal when the electronic device is in the three-dimensional mode; when the three-dimensional signal is received, the feedback voltage regulating unit controls the lowering of the feedback voltage of the detection voltage to the feedback terminal so that the feedback terminal voltage is smaller than the reference voltage, the driving chip controls the power supply adjusting unit to increase the supply voltage to the LED module when the feedback terminal voltage is less than the reference voltage to increase the current flowing through the LED lamp of the LED module.