US Pat. No. 10,115,878

OPTICAL SENSOR

Shinko Electric Industrie...

1. An optical sensor comprising:a flexible substrate;
a light emitting element;
a light receiving element;
a plurality of element mounting portions formed on an upper surface of the substrate, wherein each of the light emitting element and the light receiving element is mounted on one of the element mounting portions;
a plurality of element connection portions formed on the upper surface of the substrate, wherein each of the element connection portions is connected to one of the light emitting element and the light receiving element by a wire;
a plurality of through wirings respectively formed in a plurality of through holes extending through the substrate, wherein
each of the through wirings is bonded to one of the element mounting portions or one of the element connection portions, and
the through wirings include a heat radiation through wiring that is located immediately below the light emitting element and bonded to the element mounting portion on which the light emitting element is mounted;
a plurality of light shielding materials that are each frame-shaped, wherein each of the light emitting element and the light receiving element is surrounded by one of the light shielding materials; and
a plurality of encapsulation resins each arranged within a region surrounded by one of the light shielding materials, wherein each of the light emitting element and the light receiving element is encapsulated by one of the encapsulation resins.

US Pat. No. 10,115,877

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a semiconductor device, the method comprising:(a) providing a support, and a semiconductor light-emitting element disposed on the support, the semiconductor light-emitting element including:
a semiconductor structure, and
a first electrode and a second electrode that are disposed on the semiconductor structure;
(b) providing a base including a first interconnect terminal corresponding to the first electrode, and a second interconnect terminal corresponding to the second electrode;
(c) forming a first metal layer that is continuous and covers both a surface of the first electrode and a surface of the second electrode;
(d) forming a second metal layer that is continuous and covers both a surface of the first interconnect terminal and a surface of the second interconnect terminal;
(e) arranging the first and second electrodes to face the first and second interconnect terminals, respectively, and electrically connecting the first and second electrodes to the first and second interconnect terminals, respectively, by atomic diffusion joining, such that:
a first portion of the first and second metal layers is in a region between the first electrode and the first interconnect terminal,
a second portion of the first and second metal layers is in a region between the second electrode and the second interconnect terminal, and
a third portion of the first and second metal layers is in a region other than the first and second portions; and
(f) rendering electrically insulative or removing the third portion of the first and second metal layers.

US Pat. No. 10,115,876

LIGHT EMITTING DEVICE MOUNT, LEADFRAME, AND LIGHT EMITTING APPARATUS

NICHIA CORPORATION, Anan...

1. A light emitting device mount comprising:a positive lead terminal and a negative lead terminal, each of which includes
a first main surface,
a second main surface opposite to said first main surface in a thickness direction of each of said positive lead terminal and said negative lead terminal, and
an end surface which is provided between said first main surface and said second main surface, said end surface including
a first recessed surface area and
a second recessed surface area between said positive lead terminal and said negative lead terminal facing each other, said first recessed surface area extending from a first point of said first main surface in cross section, said second recessed surface area extending from a second point of said second main surface in cross section, said first point being arranged on an exterior side relative to said second point in cross section, said first recessed surface area and said second recessed surface area define a protruding portion protruding outwardly,
wherein at least one of said positive lead terminal and said negative lead terminal includes a middle area between said first and second recessed surface areas, forming an end surface of said protruding portion, that is arranged on an exterior side relative to said first point.

US Pat. No. 10,115,875

LIGHT-EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

NICHIA CORPORATION, Anan...

1. A light-emitting device comprising:a base member having a plurality of first recesses each defined by a bottom surface and lateral surfaces that are inner surfaces of a lateral wall separating adjacent first recesses of the plurality of first recesses;
at least one light-emitting element mounted in each of the plurality of first recesses; and
a plurality of light-transmissive members, each having a flat upper surface and covering one of the plurality of first recesses, wherein
the plurality of light-transmissive members are separated from each other by the lateral wall separating the adjacent first recesses; and
the upper surface of each of the plurality of light transmissive members is located higher than an uppermost portion of the lateral wall, wherein
the base member comprises a substrate and the lateral wall, and
in a cross-sectional view of each of the plurality of first recesses, a virtual line passing through an edge of an upper surface of the at least one light-emitting element and an edge of an upper surface of the lateral wall forms an angle of 0 to 5 degrees with respect to an upper surface of the substrate.

US Pat. No. 10,115,874

LIGHT-EMITTING DEVICE INCLUDING PHOTOLUMINESCENT LAYER

PANASONIC INTELLECTUAL PR...

1. A light-emitting device comprising:a photoluminescent layer that has a first surface perpendicular to a thickness direction thereof and emits light including first light in an infrared region, an area of the first surface being larger than a sectional area of the photoluminescent layer perpendicular to the first surface, the first light having a wavelength ?a in air; and
a light-transmissive layer located on the photoluminescent layer,
wherein at least one of the photoluminescent layer and the light-transmissive layer has a periodic structure having projections or recesses or both arranged perpendicular to the thickness direction of the photoluminescent layer,
at least one of the photoluminescent layer and the light-transmissive layer has a light emitting surface perpendicular to the thickness direction of the photoluminescent layer, the first light being emitted from the light emitting surface,
a refractive index nwav-a of the photoluminescent layer for the first light and a period pa of the periodic structure satisfy ?a/nwav-a a thickness of the photoluminescent layer, the refractive index nwav-a and the period pa are set to limit a directional angle of the first light emitted from the light emitting surface.

US Pat. No. 10,115,873

SURFACE-MODIFIED PHOSPHOR AND LIGHT EMITTING DEVICE

SAMSUNG DISPLAY CO., LTD....

1. A surface-modified phosphor comprising:a phosphor matrix comprising
a compound represented by Chemical Formula 1
K2SiF6:Mn4+; and  Chemical Formula 1
a nano-sized phosphor disposed on the phosphor matrix,
wherein the phosphor matrix has a crack, and wherein the crack is filled with the nano-sized phosphor, and
wherein the nano-sized phosphor comprises at least a compound represented by any one of Chemical Formulas 2 and 3,
Li2TiO3:Mn4+, and  Chemical Formula 2
CaAlSiN:Eu2+.  Chemical Formula 3

US Pat. No. 10,115,872

LIGHT EMITTING DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYODA GOSEI CO., LTD., ...

1. A light emitting device, comprising:a first light emitting element that outputs a first emitted light having a first peak wavelength;
a second light emitting element that outputs a second emitted light having a second peak wavelength; and
a phosphor layer including a plurality of phosphors, which is disposed on the first and second light emitting elements,
wherein the phosphor layer receives the first and second emitted light and outputs a plurality of emitted light based on the plurality of phosphors so as to form a first synthesized emission spectrum that is distributed at a longer wavelength side than the first peak wavelength of the first emitted light and includes an emission spectrum formed by the first and second emitted light, and
wherein the second light emitting element comprises an emission spectrum to reduce a depth of a deepest dip of at least one dip in a second synthesized emission spectrum that is formed by removing an emission spectrum of the second emitted light from the first synthesized emission spectrum.

US Pat. No. 10,115,871

OPTOELECTRONIC SEMICONDUCTOR COMPONENT AND METHOD FOR PRODUCING SAME

OSRAM OPTO SEMICONDUCTORS...

1. A method for producing a plurality of optoelectronic semiconductor components the method comprising:applying a plurality of semiconductor chips, which emit electromagnetic radiation of a first wavelength range from a radiation exit surface during operation, onto an auxiliary carrier;
applying a first conversion material into interstices between the semiconductor chips, wherein the first conversion material is suitable for converting electromagnetic radiation of the first wavelength range into electromagnetic radiation of a second wavelength range;
applying a second conversion material over the first conversion material, wherein the second conversion material is suitable for converting electromagnetic radiation of the first wavelength range into electromagnetic radiation of a second wavelength range or of a third wavelength range;
removing the auxiliary carrier; and
singulating the semiconductor components, wherein the first conversion material forms a first conversion layer on lateral flanks of the semiconductor chips and the second conversion material forms a second conversion layer on the radiation exit surface of the semiconductor chips,
wherein the first conversion material and the second conversion material are a first liquid resin and a second liquid resin into which phosphor particles have been introduced,
wherein the phosphor particles from the second liquid resin sediment into the first liquid resin,
wherein the first liquid resin and second liquid resin are cured before a singulation process, and
wherein, before applying the first conversion material, a reflective material is applied into the interstices between the semiconductor chips.

US Pat. No. 10,115,870

LIGHT EMITTING DEVICE, RESIN PACKAGE, RESIN-MOLDED BODY, AND METHODS FOR MANUFACTURING LIGHT EMITTING DEVICE, RESIN PACKAGE AND RESIN-MOLDED BODY

NICHIA CORPORATION, Anan...

1. A method of manufacturing a plurality of light emitting devices, each comprising a resin package that includes a first lead, a second lead and a resin part, and a light emitting element mounted on the resin package, each resin package including a first outer side surface and a second outer side surface opposing the first outer side surface, the method comprising:providing a structure comprising:
a lead frame including first portions to become the first leads, and second portions to become the second leads, and
a resin-molded body,
wherein the structure includes a plurality of areas, each of which will become one of the resin packages, and each of which has a first outer side corresponding to the first outer side surface of the corresponding resin package, and a second outer side opposing the first outer side and corresponding to the second outer side surface of the corresponding resin package,
wherein each area of said structure has a concave portion on its upper side,
wherein the lead frame is exposed from the resin-molded body at a bottom face of each concave portion, such that a part of one of the first portions and a part of one of the second portions of the lead frame are located at each respective bottom face, separated by a portion of the resin-molded body,
wherein the lead frame has a plurality of first notch parts in which a portion of the resin-molded body is disposed,
wherein, in each area, a respective one of the first notch parts is located between said first portion to become the first lead and said second portion to become the second lead, and extends from the first outer side of said area to the second outer side of said area, and
wherein, in each area, in a plane of an uppermost surface of the lead frame, a width of each first notch part at the first and second outer sides is wider than a width of the first notch part within the bottom face of the concave portion in a direction along the first and second outer sides;
mounting light emitting elements on the bottom faces of the concave portions; and
cutting said structure so as to expose the portion of the resin-molded body disposed in each first notch part, to thereby obtain a plurality of light emitting devices in each of which both the first lead and the second lead are exposed from the resin part and substantially coplanar with a portion of the resin part disposed in the first notch part at each of the first and second outer side surfaces.

US Pat. No. 10,115,869

OPTOELECTRONIC SEMICONDUCTOR CHIP, OPTOELECTRONIC COMPONENT AND METHOD FOR SINGULATING SEMICONDUCTOR CHIPS

OSRAM Opto Semiconductors...

1. An optoelectronic semiconductor chip having a carrier and a semiconductor body comprising an active layer provided for generating electromagnetic radiation, whereinthe carrier comprises a first major surface facing towards the semiconductor body, a second major surface facing away from the semiconductor body and a side flank arranged between the first major surface and the second major surface,
the carrier comprises a structured region for enlarging a total surface area of the side flank, the structured region comprising singulating traces,
the structured region comprises a barrier groove, which is circumferential with respect to the carrier, on the side flank,
a lateral extent of the barrier groove is between 3 ?m and 60 ?m inclusive,
the barrier groove is spaced apart from the first major surface and from the second major surface, and
the optoelectronic semiconductor chip comprises one of the following additional features (i) and (ii), namely:
(i) the structured region further comprises on the side flank a plurality of indentations and a lateral extent of the barrier groove is at least twice and at the most ten times as large as a lateral extent of the indentations, or
(ii) the structured region comprises an indentation on the side flank, wherein a lateral width of the indentation is between 0.3 ?m and 6 ?m inclusive and the indentation has a vertical depth which is between 1 times and 5 times the lateral width of the indentation inclusive.

US Pat. No. 10,115,868

OPTOELECTRONIC SEMICONDUCTOR CHIP, OPTOELECTRONIC COMPONENT, AND METHOD OF PRODUCING SEMICONDUCTOR CHIPS

OSRAM Opto Semiconductors...

1. An optoelectronic component comprising an optoelectronic semiconductor chip and a housing body, said optoelectronic semiconductor chip comprising a carrier and a semiconductor body having an active layer that generates electromagnetic radiation during operation of the optoelectronic semiconductor chip, whereinthe semiconductor body is arranged on the carrier,
the semiconductor body has a first main surface facing away from the carrier and a second main surface facing the carrier,
a side surface of the optoelectronic semiconductor chip has an anchoring structure,
the second main surface is arranged between the first main surface and the anchoring structure,
the side surface has roughnesses,
the anchoring structure comprises a plurality of indentations formed in the carrier and spatially arranged apart from one another in a vertical direction, wherein a cross section of the indentations is at least three times larger than a cross section of the roughnesses of the side surface, and a depth of the indentations is at least three times larger than a depth of the roughnesses of the side surface, said depth of the indentation being a lateral extent of the indentation into the carrier, and
the housing body encloses the optoelectronic semiconductor chip in a lateral direction such that a material of the housing body engages into the anchoring structure, and the first main surface and a rear side of the optoelectronic semiconductor chip are free of the material of the housing body.

US Pat. No. 10,115,867

OPTOELECTRONIC SEMICONDUCTOR CHIP

OSRAM OPTO SEMICONDUCTORS...

1. An optoelectronic semiconductor chip comprising:a semiconductor body of semiconductor material;
a p-contact layer; and
an n-contact layer,
wherein:
the semiconductor body comprises an active layer intended for generating radiation,
the semiconductor body comprises a p-side and an n-side, between which the active layer is arranged,
the p-contact layer is capable of electrically contacting the p-side of the semiconductor body,
the n-contact layer is capable of electrically contacting the n-side of the semiconductor body,
the n-contact layer contains a TCO layer and a mirror layer,
the TCO layer is arranged between the n-side of the semiconductor body and the mirror layer, and
the n-contact layer is not in direct contact with the semiconductor body.

US Pat. No. 10,115,866

LIGHT EMITTING DEVICE AND PROJECTOR

Seiko Epson Corporation, ...

1. A light emitting device comprising:a laminated body having an active layer capable of producing light when current is injected thereinto and a first cladding layer and a second cladding layer that sandwich the active layer; and
a first electrode and a second electrode that inject current into the active layer,
wherein the second cladding layer has a ridge section thicker than another portion of the second cladding layer,
the active layer forms an optical waveguide that guides light,
the optical waveguide has a first light exiting surface and a second light exiting surface through which the light exits,
the optical waveguide extends in a direction inclined with respect to a normal to the first light exiting surface and a normal to the second light exiting surface,
the laminated body has a connection area that overlaps with the ridge section when viewed in a direction in which the active layer is laminated on the first cladding layer and is connected to the second electrode,
the ridge section has a first tapered section having a width that increases with distance from a center position that is equidistant from the first light exiting surface and the second light exiting surface toward the first light exiting surface when viewed from the laminated direction and a second tapered section having a width that increases from the center position toward the second light exiting surface when viewed from the laminated direction,
the connection area has a third tapered section having a width that increases from the center position toward the first light exiting surface when viewed from the laminated direction and a fourth tapered section having a width that increases from the center position toward the second light exiting surface when viewed from the laminated direction,
an angle of outer edges of the connection area that specify the width of the third tapered section with respect to a center line of the optical waveguide is greater than an angle of outer edges of the ridge section that specify the width of the first tapered section with respect to the center line when viewed from the laminated direction, and
an angle of outer edges of the connection area that specify the width of the fourth tapered section with respect to the center line is greater than an angle of outer edges of the ridge section that specify the width of the second tapered section with respect to the center line when viewed from the laminated direction.

US Pat. No. 10,115,865

HIGH-PERFORMANCE LED FABRICATION

Soraa, Inc., Fremont, CA...

1. An LED package comprising:a ceramic substrate having a substrate top surface;
a plurality of traces overlaying said substrate top surface;
a plurality of contacts, each contact being electrically connected to one of said traces;
a reflective material disposed over at least a portion of said traces, said reflective material not extending above said plurality of contacts; and
a flip-chip LED die having LED contacts said LED contacts contacting said plurality of contacts.

US Pat. No. 10,115,864

OPTOELECTRONIC DEVICE WITH LIGHT-EMITTING DIODES AND AN IMPROVED RADIATION PATTERN

Aledia, Grenoble (FR)

1. An optoelectronic device comprising:a support comprising a conductive layer;
an electrode,
wherein the conductive layer comprises a portion having a concave or convex shape, and the electrode has a concave or convex shape, respectively; and
at least one light-emitting diode disposed between the portion and the electrode, wherein:
the at least one light-emitting diode comprises at least one cylindrical, conical or tapered semiconductor element in contact with a surface of the portion;
an amplitude of a deflection of the surface between the at least one semiconductor element and the portion is smaller than or equal to 0.5 ?m; and
an amplitude of a deflection of the portion is greater than 1/20th of a chord of the portion.

US Pat. No. 10,115,863

STRAINED ALGAINP LAYERS FOR EFFICIENT ELECTRON AND HOLE BLOCKING IN LIGHT EMITTING DEVICES

Lumileds LLC, San Jose, ...

1. A light-emitting device, comprising:an electron blocking layer, wherein at least a portion of the electron blocking layer is arranged to have a tensile strain;
a hole blocking layer, wherein at least a portion of the hole blocking layer is arranged to have a compressive strain; and
an active layer disposed between the hole blocking layer and the electron blocking layer.

US Pat. No. 10,115,862

FLUIDIC ASSEMBLY TOP-CONTACT LED DISK

eLux Inc., Vancouver, WA...

1. A top-contact light emitting diode (LED) display, the display comprising:a transparent substrate with a top surface comprising a number of wells;
a top-contact LED formed in each of the number of wells, each LED comprising:
a lower disk comprising a material with a first dopant selected from a group consisting of: a p-dopant, and an n-dopant; the lower disk having a bottom surface and a top surface;
a multiple quantum well (MQW) disk overlying the lower disk top surface;
an upper disk comprising a material with a second dopant, wherein the second dopant is opposite the first dopant; the upper disk having a bottom surface overlying the MQW disk, a top surface and a first diameter;
an electrical insulator disk overlying the upper disk top surface, having a second diameter smaller than the first diameter such that at least a portion of a perimeter of the upper disk extending to an outer edge of the upper disk top surface remains uncovered by the electrical insulator disk; and, a via formed through the electrical insulator disk upper disk, and MQW disk, exposing a center contact region of the lower disk top surface.

US Pat. No. 10,115,861

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

XIAMEN SANAN OPTOELECTRON...

1. A light-emitting diode, comprising:an epitaxial-laminated layer, comprising from bottom to up:
an n-type ohmic contact layer;
a first n-type transition layer;
an n-type etching-stop layer;
a second n-type transition layer;
an n-type confinement layer;
an active layer;
a p-type confinement layer;
a p-type transition layer; and
a p-type window layer;
a p electrode over an upper surface of the p-type window layer;
a metal bonding layer over a bottom surface of the n-type ohmic contact layer, wherein: a portion corresponding to a position of the p electrode extends upwards and passes through the n-type ohmic contact layer and the first n-type transition layer, till the n-type etching-stop layer, thereby forming a current distribution adjustment structure such that injected current does not flow towards the epitaxial-laminated layer right below the p electrode; and
a conductive substrate located over a bottom surface of the metal bonding layer.

US Pat. No. 10,115,860

HIGH VOLTAGE MONOLITHIC LED CHIP

CREE, INC., Durham, NC (...

1. A monolithic LED chip, comprising:a plurality of active regions on a submount;
integral electrically conductive interconnect elements in electrical contact with said plurality of active regions and electrically connecting at least some active regions of said plurality of active regions in parallel or in series-parallel, wherein said interconnect elements are completely embedded within said submount; and
one or more integral insulating layers surrounding at least a portion of said interconnect elements and isolating said at least a portion of said interconnect elements from other elements of said monolithic LED chip.

US Pat. No. 10,115,859

NITRIDE BASED DEVICES INCLUDING A SYMMETRICAL QUANTUM WELL ACTIVE LAYER HAVING A CENTRAL LOW BANDGAP DELTA-LAYER

Lehigh University, Bethl...

1. A III-nitride based semiconductor device comprising:a substrate;
a first barrier layer comprising a GaN-based material formed over said substrate;
a second barrier layer comprising a GaN-based material disposed over said first barrier layer; and
an InGaN-delta-InN quantum well active layer positioned between said first and second barrier layers, said quantum well active layer comprising:
an inner quantum well delta layer of an InN material, said inner quantum well delta layer having a thickness of approximately 6 ? or less, said first nitride-based material having a first bandgap characteristic; and
a pair of outer quantum well layers, each of said pair of outer quantum well layers being of an InGaN material having an Indium content in the range of about 15% to 35%, said pair of outer quantum well layers sandwiching said inner quantum well delta layer, each of said pair of outer quantum well layers having a respective thickness greater than said thickness of said inner quantum well delta layer and measuring approximately 15 ? to 30 ?;
wherein said InGaN-delta-InN quantum well active layer emits light in a wavelength range of about 500 nm to about 750 nm when the semiconductor device is energized.

US Pat. No. 10,115,858

LIGHT EMITTING DIODE AND FABRICATION METHOD THEREOF

1. A method of fabricating a light emitting diode, the method comprising:providing a substrate;
forming an N-type layer over the substrate;
forming an active layer over the N-type layer;
forming an electronic blocking layer over the active layer; and
forming a P-type layer over the electronic blocking layer, wherein:
the P-type layer comprises a Mg-doped GaN material layer having a Mg impurity concentration of about 2×1019-2×1020 cm?3; and
the P-type layer has a thickness of less than or equal to about 250 ?, and has a surface density of V-type defects of less than or equal to about 5×106 cm?2.

US Pat. No. 10,115,857

METHOD FOR MANUFACTURING SEMICONDUCTOR ELEMENT OF POLYGON SHAPE

NICHIA CORPORATION, Anan...

1. A method for manufacturing a semiconductor element, comprising:providing a semiconductor wafer including a substrate, a semiconductor structure on the substrate, and electrodes;
forming a cleavage starting portion in the semiconductor wafer, without dividing the semiconductor structure; and
dividing the semiconductor wafer into a plurality of semiconductor elements by transferring a pressing member on the semiconductor wafer in a state where the pressing member is pressed against the semiconductor wafer before separating the semiconductor structure, thereby the semiconductor wafer is separated at the cleavage starting portion, wherein
the pressing member includes a tip portion to be pressed on the semiconductor wafer,
the tip portion has a spherical surface, and
each of the plurality of semiconductor elements has a shape of a polygon having five or more angles in a plan view.

US Pat. No. 10,115,856

SYSTEM AND METHOD FOR CURING CONDUCTIVE PASTE USING INDUCTION HEATING

Tesla, Inc., Palo Alto, ...

1. A system for curing conductive paste applied on a plurality photovoltaic structures, comprising:a wafer carrier for carrying the photovoltaic structures on a first side of the wafer carrier, wherein the wafer carrier includes a base and a strip carrier that is in direct contact with the photovoltaic structures; and
a heater positioned on the first side of the wafer carrier, wherein the heater includes an induction coil configured to operate near the photovoltaic structures, thereby providing localized induced heat for curing the conductive paste, and
two shields positioned on the first side of the wafer carrier and configured to shield a magnetic field caused by the induction coil from metallic parts of the photovoltaic structures other than the conductive paste, wherein a gap between the two shields allows the conductive paste to be exposed to the magnetic field produced by the induction coil.

US Pat. No. 10,115,855

CONDUCTIVE FOIL BASED METALLIZATION OF SOLAR CELLS

SunPower Corporation, Sa...

1. A method of fabricating a solar cell, the method comprising:forming a first cut portion from a conductive foil;
aligning the first cut portion to a first doped region of a first semiconductor substrate, wherein the first cut portion is aligned substantially parallel to the first doped region, wherein aligning the first cut portion to the first doped region of the first semiconductor substrate comprises placing the first cut portion in an aligner having a plurality of slots; and
bonding the first cut portion to the first doped region.

US Pat. No. 10,115,854

METHOD FOR FORMING A VIRTUAL GERMANIUM SUBSTRATE USING A LASER

NewSouth Innovations Pty ...

1. A method for manufacturing a semiconductor device comprising the steps of:providing a substrate;
forming a germanium layer over the substrate, the germanium layer having a concentration of lattice defects;
depositing a dielectric layer onto the germanium layer; thereafter
exposing a region of the germanium layer to laser light through the dielectric layer; thereafter
removing the dielectric layer; and thereafter
forming at least one semiconductor device on a surface portion of the exposed region of the germanium layer comprising growing a plurality of layers comprising III-V compound materials on the formed germanium layer;
wherein the step of exposing the region of the germanium layer to laser light comprises: generating a continuous-wave laser beam and directing the continuous-wave laser beam towards a first edge of the germanium layer and laterally moving the laser beam along the length of the germanium layer from the first edge to a second edge.

US Pat. No. 10,115,853

ELECTRONIC POWER CELL MEMORY BACK-UP BATTERY

Colossus EPC Inc., Gilbe...

1. An electronic power cell memory back-up battery comprising:a light source, wherein the light source emits light in response to receiving light source input power;
a photovoltaic device, wherein the photovoltaic device outputs photovoltaic-generated electrical power in response to receiving light from the light source;
power modulation circuitry electrically coupled to the light source and photovoltaic device;
wherein a first portion of the photovoltaic-generated electrical power output by the photovoltaic device is the light source input power;
wherein the power modulation circuitry receives the light source input power, alters the light source input power to provide a periodic light source input power, and provides the periodic light source input power to the light source;
wherein a second portion of the photovoltaic-generated electrical power output by the photovoltaic device is a power source output power; and
wherein the light source comprises:
a light-emitting device, wherein the light emitting device emits light of a first peak wavelength in response to receiving light source input power; and
a light photon releaser (LPR) material, wherein the LPR material emits light of a second peak wavelength in response to receiving light of the first peak wavelength from the light-emitting device, wherein the LPR material comprises a compound doped with phosphorus, europium, and/or elements from the Lanthanide series; and
a block of optical coupling material, wherein the light-emitting device and the LPR material are embedded in the block of optical coupling material;
wherein the battery further comprises at least one mirror having an interior surface facing the light source and coated with LPR material, wherein the LPR material coating is in contact with the optical coupling material.

US Pat. No. 10,115,852

SOLAR CELL MODULE

Panasonic Intellectual Pr...

1. A solar cell module comprising:first and second solar cell strings, each of the first and second solar cell strings including solar cells arranged in an arrangement direction and wiring members electrically connecting the solar cells to one another;
a light diffusion sheet disposed between the first and second solar cell strings; and
a sealant member sealing the light diffusion sheet and the solar cells of the first and second solar cell strings,whereinthe first and second solar cell strings are disposed adjacent to each other and parallel to each other along the arrangement direction,
the light diffusion sheet is disposed on a front side as a light-receiving side with respect to the solar cells such that both side edge portions of the light diffusion sheet overlap side edge portions of the first and second solar cell strings and the light diffusion sheet does not overlap the wiring members of the first and second solar cell strings in a planar view of the solar cell module, and
the light diffusion sheet comprises:
a base material having a resin sheet; and
a metal film deposited on a front side of the base material, wherein the light diffusion sheet is in direct contact with a light-receiving surface of the solar cells of each of the first solar cell string and the second solar cell string and a side surface of the solar cells of each of the first solar cell string and the second solar cell string.

US Pat. No. 10,115,851

SOLAR CELL HAVING A DIELECTRIC REAR FACE COATING AND METHOD FOR PRODUCING SAME

Centrotherm Photovoltaics...

1. A method for production of a solar cell, comprising:arranging a solar cell substrate in a retaining device having at least one retaining collar, being brought to abut against the at least one retaining collar;
inserting the retaining device into a coating device and depositing a dielectric coating on the back side of the solar cell substrate;
applying a planar contact on at least parts of the dielectric coating;
when the planar contact is applied on at least some parts of the dielectric coating, leaving free those areas which have been shaded by the retaining collars during the deposition of the dielectric coating;
configuring the planar contact in such a way that its boundary line has at least one recess; and
configuring and arranging the planar contact in such a way that the at least one recess leaves at least part of those areas which have been shaded by the retaining collars during the deposition of the dielectric coating free from a covering with the planar contact.

US Pat. No. 10,115,850

ROOF INTEGRATED SOLAR PANEL SYSTEM WITH SIDE MOUNTED MICRO INVERTERS

Building Materials Invest...

1. A roof integrated solar power system for generating electrical power from sunlight, the solar power system comprising:a plurality of modules configured to be installed in overlapping courses on a roof, each module including:
a frame having a top surface with an exposure portion to be exposed to sunlight when the module is installed and a headlap portion to be covered by a module in a next higher course of modules when the power system is installed, the exposure portion having opposed ends;
a photovoltaic panel recess formed in the exposure portion of the frame, the photovoltaic panel recess having a first end adjacent one of the opposed ends of the frame and a second end spaced from the other one of the opposed ends of the frame;
a photovoltaic panel having ends, a forward edge, a rear edge, and a top surface and being mounted within the photovoltaic panel recess;
an electronics compartment recess formed in the exposure portion of the frame within the space between the second end of the photovoltaic panel recess and the other one of the opposed ends of the frame;
a micro-inverter and first wiring mounted within the electronics compartment recess; an access panel removably attached to the top of the frame covering the electronics compartment recess, the access panel having a forward edge aligned with the forward edge of the photovoltaic panel and a rear edge aligned with the rear edge of the photovoltaic panel when the access panel is attached to the top of the frame; and
a top surface of the access panel and the top surface of the photovoltaic panel being flush with the top surface of the frame.

US Pat. No. 10,115,849

SOLAR CELL AND METHOD OF FABRICATING THE SAME

LG INNOTEK CO., LTD., Se...

1. A method of fabricating a solar cell, the method comprising:forming a back electrode layer on a substrate;
forming a light absorbing layer on the back electrode layer;
forming a first buffer layer on the light absorbing layer;
forming a second buffer layer on the first buffer layer; and
forming a front electrode layer on the second buffer layer;
wherein the first buffer layer or the second buffer layer comprises at least one of zinc sulfide (ZnS), zinc oxide (ZnO), and zinc hydroxide (Zn(OH)2),
wherein in order to form the buffer layer, the substrate is dipped into the solution in which an ammonia water is dissolved
wherein the forming the first buffer layer, the concentration of the ammonia water is in the range of 1 M to 4 M,
wherein the forming the second buffer layer, the concentration of the ammonia water is in the range of 5 M to 7 M,
wherein a difference in the concentration of ammonia water between the steps of forming the first and second buffer layers is in the range of 3 M to 6 M,
wherein simultaneously with the forming the first buffer layer, the second buffer layer is formed by adjusting the concentration of the ammonia water of the solution,
wherein the second buffer layer is in direct physical contact with the front electrode layer,
wherein the first buffer layer or the second buffer layer has a thickness in a range of about 15 nm to about 50 nm.

US Pat. No. 10,115,848

METHOD OF TRANSFERRING THIN FILM

NATIONAL TSING HUA UNIVER...

1. A method of transferring a thin film, comprising:providing a first element structure, wherein the first element structure includes a first substrate and a functional film layer formed on the first substrate;
completely removing the first substrate, wherein steps of the completely removing the first substrate include conducting an etching step to erode the first substrate and conducting a grinding step to planarize the eroded first substrate, and wherein the etching step and the grinding step are separately and repeatedly conducted until the first substrate is completely removed; and
after completely removing the first substrate, attaching the functional film layer on a second substrate to form a second element structure without flipping the functional film layer;
wherein the first substrate is a soda glass substrate, the functional film layer is a solar cell layer, and the functional film layer includes a back electrode layer, a light absorbing layer, a buffer layer, and a transparent conductive layer, and wherein the light absorbing layer is disposed between the back electrode layer and the transparent conductive layer, and the buffer layer is disposed between the light absorbing layer and the transparent conductive layer.

US Pat. No. 10,115,847

CUPRIC OXIDE SEMICONDUCTORS

Trustees of Tufts College...

1. A cupric oxide semiconductor comprising a substrate and a cupric oxide film overlaying the substrate, wherein the cupric oxide film, containing polycrystalline cupric oxide, amorphous cupric oxide, or both, has an electrical resistivity of 10 to 105 ?·cm, a thickness of 50 to 10000 nm, a bulk density of 1 to 6.4 g/cm3, a surface area of 1 to 100 m2/g, a bandgap of 1.1 to 1.8 eV, and a capacitance of 50 to 100000 mF/g.

US Pat. No. 10,115,846

SOLAR CELL AND SOLAR CELL MANUFACTURING METHOD

Panasonic Intellectual Pr...

1. A solar cell comprising:a photoelectric conversion element including:
a light incident surface and a back surface opposed to the light incident surface; and
a side surface provided between the light incident surface and the back surface,
wherein the photoelectric conversion element has a plurality of sides; and
a light diffusion portion on an outer peripheral area of the light incident surface and the side surface,
the light diffusion portion having:
a lower side light diffusion portion in direct contact with the outer peripheral area of the light incident surface and the side surface on a lower side that is one of the plurality of sides; and
an upper side light diffusion portion in direct contact with the outer peripheral area of the light incident surface and the side surface on an upper side that is one of the plurality of sides and opposed to the lower side,
wherein a width of the lower side light diffusion portion on the side surface in a direction from the light incident surface toward the back surface is smaller than a width of the upper side light diffusion portion on the side surface in the direction from the light incident surface toward the back surface,
wherein a first corner portion constituted by a part of the light incident surface and a part of the side surface is exposed from the light diffusion portion, and
wherein the first corner portion is located along the lower side or the upper side.

US Pat. No. 10,115,845

COMPOSITION FOR FORMING SOLAR CELL ELECTRODES AND ELECTRODES FABRICATED USING THE SAME

SAMSUNG SDI CO., LTD., Y...

1. A composition for forming solar cell electrodes, the composition comprising a conductive powder, a glass frit, an organic vehicle, and a surface tension modifier having a surface tension of 40 to 60 mN/m, the composition for forming solar cell electrodes having a tackiness of 60% to 90% represented by the following Expression 1:
wherein, in Expression 1, A represents a minimum shear stress value of shear stress measured while detaching a pair of circular plates, from each other, which have a diameter of 25 mm and have been laminated in parallel to each other by a medium of the composition for forming solar cell electrodes, by applying an external force, and B represents a shear stress value at a point at which an instantaneous rate of change of shear stress with respect to a gap between the plates (d (shear stress)/d (gap)) is 0.05.

US Pat. No. 10,115,844

ELECTRODES COMPRISING NANOSTRUCTURED CARBON

SEERSTONE LLC, Provo, UT...

1. A method of producing a sintered object, comprising:mixing a mass of nanostructured carbon particles with at least one fluid containing a dissolved carbon source to produce a paste;
pyrolyzing the paste such that the dissolved carbon source forms residual solid carbon within a cohesive body of the nanostructured carbon particles; and
sintering the cohesive body of the nanostructured carbon particles with the residual solid carbon at a pressure from about 10 MPa to about 1000 MPa to form contacts between adjacent nanostructured carbon particles to provide an electrical path between at least two remote points of the cohesive body.

US Pat. No. 10,115,843

BROADBAND ANTIREFLECTION COATINGS UNDER COVERGLASS USING ION GUN ASSISTED EVAPORATION

THE BOEING COMPANY, Chic...

1. A method of forming an antireflective coating, comprising:depositing a first layer comprising titanium dioxide and having a first index of refraction within a range of about 2.3 to about 2.7 using ion beam-assisted deposition;
depositing an intermediate layer by e-beam evaporation comprising titanium dioxide on the first layer, the intermediate layer having an index of refraction and a density less than the first layer;
depositing a second layer on the intermediate layer by e-beam evaporation, the second layer having an index of refraction less than the intermediate layer and within a range of about 1.8 to about 2.1; and
depositing a third layer on the second layer, the third layer having an index of refraction within a range of about 1.6 to about 1.8.

US Pat. No. 10,115,842

SEMICONDUCTOR OPTICAL PACKAGE AND METHOD

STMICROELECTRONICS PTE LT...

1. A device, comprising:a first substrate;
a second semiconductor substrate having a first surface on the first substrate and a second surface opposite the first surface, the semiconductor substrate including a first optical device and a second optical device that receive light from the second surface;
a first sidewall on the first substrate;
a second sidewall on the first substrate, the second semiconductor substrate being between the first and second sidewall;
a transparent layer extending between the first and second sidewall and overlapping the second surface of the semiconductor substrate;
a first light protection coating on the transparent layer, the transparent layer being between the first light protection coating and the second surface of the semiconductor substrate;
a first opening in the first light protection coating; and
a second opening in the first light protection coating.

US Pat. No. 10,115,841

INTEGRATED PHOTOVOLTAIC PANEL CIRCUITRY

Solaredge Technologies Lt...

1. An apparatus comprising:a photovoltaic panel comprising a plurality of photovoltaic cells;
a casing that holds the photovoltaic cells; and
a converter circuit comprising first and second input terminals, the first input terminal directly connected to the casing by the first input terminal being bonded to the casing, and the second input terminal directly connected to the photovoltaic panel, and the converter circuit comprising first and second output terminals galvanically isolated from the first and second input terminals and electrically disconnected from the first and second input terminals, wherein the converter circuit converts first direct current (DC) power on the second input terminal to second DC power on the first output terminal, wherein the first output terminal of the converter circuit outputs power received by the converter circuit,
wherein the first and second input terminals of the converter circuit are integrated with the casing and the photovoltaic panel, respectively.

US Pat. No. 10,115,840

SOLAR CELL AND METHOD FOR PRODUCING THEREOF

SHIN-ETSU CHEMICAL CO., L...

1. A solar cell comprising:a semiconductor substrate of a first conductivity type comprising main surfaces that are opposite to each other wherein one of the main surfaces is a light-receiving surface, the other main surface is a backside, and the backside of the semiconductor substrate has a region of the first conductivity type and a region of a second conductivity type, being an opposite conductivity type to the first conductivity type;
a first finger electrode composed of a first contact portion joined to the region of the first conductivity type and a first current collector formed on the first contact portion;
a second finger electrode composed of a second contact portion joined to the region of the second conductivity type and a second current collector formed on the second contact portion;
a first bus bar electrode being in electrical contact with the first current collector;
a second bus bar electrode being in electrical contact with the second current collector;
a first insulator film disposed at least in the whole area just under the first bus bar electrode; and
a second insulator film disposed at least in the whole area just under the second bus bar electrode;
wherein the entire area of the first bus bar electrode is disposed on the first insulator film;
the entire area of the second bus bar electrode is disposed on the second insulator film;
the electrical contact between the first current collector and the first bus bar electrode is made on the first insulator film;
the electrical contact between the second current collector and the second bus bar electrode is made on the second insulator film;
the first contact portion is in a continuous line shape at least just under the second insulator film; and
the second contact portion is in a continuous line shape at least just under the first insulator film.

US Pat. No. 10,115,839

MODULE FABRICATION OF SOLAR CELLS WITH LOW RESISTIVITY ELECTRODES

Tesla, Inc., Palo Alto, ...

1. A solar module, comprising:a first solar cell having a first back-side emitter layer, and having only an area along one edge on a back-side surface covered by a first busbar; and
a second solar cell having only an area along one edge on a front-side surface covered by a second busbar;
wherein the first solar cell and second solar cell are coupled by overlapping the first busbar and second busbar.

US Pat. No. 10,115,838

PHOTOVOLTAIC STRUCTURES WITH INTERLOCKING BUSBARS

Tesla, Inc., Palo Alto, ...

1. A photovoltaic structure, comprising:a first metallic grid positioned on a first surface of the photovoltaic structure, wherein the first metallic grid includes a first set of discontinuous segments positioned near an edge of the photovoltaic structure; and
a second metallic grid positioned on a second surface of the photovoltaic structure, wherein the second metallic grid includes a second set of discontinuous segments positioned near an opposite edge of the photovoltaic structure;
wherein the first and the second sets of discontinuous segments have substantially complementary topology profiles such that, when the edge of the photovoltaic structure overlaps with an opposite edge of an adjacent photovoltaic structure with a same metallic-grid configuration, a respective segment on the first surface of the photovoltaic structure fits in a corresponding gap between two neighboring segments on the second surface of the adjacent photovoltaic structure, thereby facilitating interlocking of the segments between the two photovoltaic structures wherein, within each of the first and second metallic grids, the discontinuous segments are not directly coupled to one another by a metallic material except by segments of another grid when two photovoltaic structures are overlapped.

US Pat. No. 10,115,837

INTEGRATED CIRCUITS WITH SOLAR CELLS AND METHODS FOR PRODUCING THE SAME

Globalfoundries Singapore...

1. An integrated circuit comprising:a substrate comprising a handle layer, a buried insulator layer overlying the handle layer, and an active layer overlying the buried insulator layer, wherein the handle layer comprises monocrystalline silicon and the active layer comprises monocrystalline silicon;
a transistor overlying the buried insulator layer;
a solar cell within the handle layer such that the buried insulator layer is between the solar cell and the transistor, wherein the solar cell comprises a solar cell outer layer in electrical communication with a solar cell outer layer contact, a solar cell inner layer in electrical communication with a solar cell inner layer contact, and wherein the solar cell inner layer and the solar cell outer layer are monocrystalline silicon;
a deep bias well underlying the buried insulator layer and the transistor, wherein the deep bias well overlies the solar cell inner layer; and
a deep bias well contact in electrical communication with the deep bias well.

US Pat. No. 10,115,835

VARIABLE CAPACITOR BASED ON BURIED OXIDE PROCESS

QUALCOMM Incorporated, S...

1. A semiconductor variable capacitor comprising:a substrate;
a first conductive pad coupled to a first non-insulative region;
a second conductive pad coupled to a second non-insulative region, wherein the second non-insulative region is coupled to a first semiconductor region;
a first control region coupled to the first semiconductor region such that a capacitance between the first conductive pad and the second conductive pad is configured to be adjusted by varying a control voltage applied to the first control region; and
a first insulator region between the first semiconductor region and the substrate with respect to an axis perpendicular to the substrate, wherein at least a portion of the first non-insulative region is separated from the first semiconductor region by the first insulator region such that the first conductive pad is electrically isolated from the second conductive pad.

US Pat. No. 10,115,834

METHOD FOR MANUFACTURING AN EDGE TERMINATION FOR A SILICON CARBIDE POWER SEMICONDUCTOR DEVICE

ABB Schweiz AG, Baden (C...

17. A silicon carbide power semiconductor device having a central region and an edge region between a first main side and a second main side opposite to the first main side,wherein an n doped silicon carbide substrate layer is arranged on the second main side,
an n-doped silicon carbide drift layer, which is lower doped than the silicon carbide substrate layer, is arranged on the first main side, in the edge region on the first main side at least one p doped termination layer and an (n??) doped doping reduction layer is arranged, which has lower doping concentration than the drift layer,
wherein the doping reduction layer is arranged in a doping reduction layer depth range between a depth of a doping concentration minimum of the doping reduction layer below the first main side up to a maximum doping reduction layer depth, wherein the depth of the doping concentration minimum of the doping reduction layer is deeper than the maximum termination layer depth, wherein the doping reduction layer depth range is less than 10 ?m, wherein the doping reduction layer comprises a plurality of doping reduction regions, each of which has a depth of the doping concentration minimum of the doping reduction region, a maximum doping reduction region depth and a doping reduction region depth range being the deviation between the maximum doping reduction region depth and the depth of the doping concentration minimum and wherein each doping reduction region depth range is less than 1 ?m.

US Pat. No. 10,115,833

SELF-ALIGNED HETEROJUNCTION FIELD EFFECT TRANSISTOR

International Business Ma...

1. A junction field effect transistor comprising:an insulating carrier substrate;
a base semiconductor substrate formed on the insulating carrier substrate;
a gate region formed on the base semiconductor substrate wherein the gate region forms a junction with the base semiconductor substrate;
a first source/drain region formed on the base semiconductor substrate and located on a first side of the gate region;
a second source/drain region formed on the base semiconductor substrate and located on a second side of the gate region; and
a gate stack deposited on the gate region, a first source/drain stack deposited on the first source/drain region and a second source/drain stack deposited on the second source/drain region;
wherein at least a portion of the first source/drain stack and a portion of the second source/drain stack overlaps a top surface of the gate stack in the gate region.

US Pat. No. 10,115,832

THIN FILM TRANSISTOR, METHOD FOR MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY DEVICE

BOE TECHNOLOGY GROUP CO. ...

1. A thin film transistor (TFT), comprising an active layer, wherein the active layer includes a first active layer and two second active layers, the second active layer is made of an oxide semiconductor material, and the first active layer has conductivity greater than conductivity of the second active layer; whereinthe TFT further comprises a base substrate, a source electrode and a drain electrode, wherein at least one of the at least one second active layer is, relative to the first active layer, closer to a portion of the source electrode and the drain electrode of which an orthogonal projection onto the base substrate overlaps orthogonal projections of the first active layer and the two second active layers onto the base substrate;
wherein the first active layer is arranged between the two second active layers, and the two second active layers are in contact with each other.

US Pat. No. 10,115,831

SEMICONDUCTOR DEVICE HAVING AN OXIDE SEMICONDUCTOR LAYER COMPRISING A NANOCRYSTAL

Semiconductor Energy Labo...

1. A semiconductor device comprising:a gate electrode layer;
a gate insulating layer over the gate electrode layer;
an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer comprising:
a first region;
a second region;
a third region between the first region and the second region;
a fourth region between the first region and the third region; and
a fifth region between the second region and the third region;
a first insulating layer over the oxide semiconductor layer, the first insulating layer comprising oxygen;
a source electrode layer over the oxide semiconductor layer; and
a drain electrode layer over the oxide semiconductor layer,
wherein the first region is in contact with the source electrode layer,
wherein the second region is in contact with the drain electrode layer,
wherein the third region is in contact with the first insulating layer,
wherein the fourth region has a thickness less than the third region,
wherein the fifth region has a thickness less than the third region, and
wherein the oxide semiconductor layer comprises a nanocrystal.

US Pat. No. 10,115,830

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising:forming an oxide semiconductor film;
forming a gate insulating film over the oxide semiconductor film;
forming a gate electrode over the gate insulating film;
forming an interlayer insulating film over the oxide semiconductor film and the gate electrode;
performing planarization treatment on the interlayer insulating film;
forming a first opening and a second opening in the interlayer insulating film subjected to the planarization treatment;
forming a first conductive film in the first opening and the second opening and over the interlayer insulating film subjected to the planarization treatment;
forming a second conductive film and a third conductive film by performing planarization treatment on the first conductive film; and
forming a first region and a second region in the oxide semiconductor film by adding an impurity to the second conductive film and the third conductive film,
wherein the first region and the first opening overlap with each other, and
wherein the first region is formed by an impact caused by addition of the impurity to the second conductive film.

US Pat. No. 10,115,829

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising a transistor, the transistor comprising:a gate electrode over a substrate;
an insulating film over the gate electrode;
an oxide semiconductor layer over the insulating film, the oxide semiconductor layer comprising a channel formation region of the transistor overlapping with the gate electrode;
a channel protective layer over the channel formation region;
a source electrode and a drain electrode over the channel protective layer, the source electrode and the drain electrode each electrically connected to the oxide semiconductor layer;
a first titanium oxide between the oxide semiconductor layer and the source electrode; and
a second titanium oxide between the oxide semiconductor layer and the drain electrode,
wherein at least one of the first titanium oxide and the second titanium oxide comprises indium or zinc,
wherein a top inner edge of the first titanium oxide is over the channel protective layer and extends inward from a bottom inner edge of the source electrode, and
wherein a top inner edge of the second titanium oxide is over the channel protective layer and extends inward from a bottom inner edge of the drain electrode.

US Pat. No. 10,115,828

FIELD-EFFECT TRANSISTOR, DISPLAY ELEMENT, IMAGE DISPLAY DEVICE, AND SYSTEM

RICOH COMPANY, LTD., Tok...

1. A field-effect transistor comprising:a gate electrode, which is configured to apply gate voltage;
a source electrode and a drain electrode, which are configured to take electric current out;
an active layer, which is disposed to be adjacent to the source electrode and the drain electrode and includes a n-type oxide semiconductor; and
a gate insulating layer, which is disposed between the gate electrode and the active layer,
wherein the n-type oxide semiconductor is substitutionally doped with at least one cation dopant selected from the group consisting of a divalent cation, a trivalent cation, a tetravalent cation, a pentavalent cation, a hexavalent cation, a heptavalent cation, and an octavalent cation,
wherein the n-type oxide semiconductor includes a metal ion as a component, and a valence of the cation dopant is greater than a valence of the metal ion, and the cation dopant and the metal ion included in the n-type oxide semiconductor are not the same element, and
wherein the source electrode and the drain electrode include a material selected from the group consisting of the following (i) and (ii), in at least contact regions of the source electrode and the drain electrode with the active layer, the material selected from the group consisting of (i) and (ii) being disposed to be in contact with the n-type oxide semiconductor:
(i) metals of Au, Pt and Pd; and
(ii) alloys including at least any one of Au, Pt and Pd.

US Pat. No. 10,115,826

SEMICONDUCTOR STRUCTURE AND THE MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a FINFET, comprising:forming a plurality of fin structures on a layer having a larger lattice constant than that of the fin structure by a patterning operation;
oxidizing the fin structure and the layer to transform the layer into a first oxide layer;
filling insulating material between adjacent fin structures after oxidizing the fin structure and the layer; and
etching the insulating material to expose a top surface and at least a portion of a sidewall of the fin structure.

US Pat. No. 10,115,825

STRUCTURE AND METHOD FOR FINFET DEVICE WITH ASYMMETRIC CONTACT

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:a fin-type active region extruded from a semiconductor substrate;
a gate stack disposed on the fin-type active region;
a source/drain feature formed in the fin-type active region and disposed on a side of the gate stack;
an elongated contact feature landing on the source/drain feature; and
a dielectric material layer disposed on sidewalls of the elongated contact feature and free from ends of the elongated contact feature, wherein the sidewalls of the elongated contact feature are parallel with the gate stack.

US Pat. No. 10,115,824

FORMING A CONTACT FOR A SEMICONDUCTOR DEVICE

INTERNATIONAL BUSINESS MA...

1. A semiconductor device comprising a PFET and a NFET:a gate stack arranged over a channel region of a semiconductor substrate;
a spacer arranged adjacent to the gate stack;
a first source and drain region of the PFET arranged adjacent to the spacer,
the first source and drain region comprising:
a first doped crystalline semiconductor material arranged on the semiconductor substrate:
a second doped crystalline semiconductor material arranged on the first doped crystalline semiconductor material;
a first liner layer comprising a conductive metallic oxide material arranged on the second doped crystalline semiconductor material; and
a second liner layer comprising a metallic material arranged on the first liner layer;
a second source and drain region of the NFET arranged adjacent to the spacer the second source and drain region comprising:
a third doped crystalline semiconductor material arranged on the semiconductor substrate; and
the second liner layer formed directly on the third doped crystalline semiconductor material; and
a conductive contact material arranged on the second liner layer in the first source and drain region of the PFET and the second source and drain region of the NFET.

US Pat. No. 10,115,823

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a Fin Field-Effect Transistor (Fin FET) device including:
a fin structure extending in a first direction and protruding from an isolation insulating layer, the fin structure and the isolation insulating layer being disposed over a substrate, the fin structure including a well layer, an oxide layer disposed over the well layer and a channel layer disposed over the oxide layer;
a gate stack including a gate electrode layer, covering a portion of the fin structure and extending in a second direction perpendicular to the first direction;
a source and a drain, each including a stressor layer disposed over recessed portions formed in the fin structure; and
seed layers disposed in contact with the oxide layer,
wherein the stressor layer is in contact with the seed layer.

US Pat. No. 10,115,822

METHODS OF FORMING LOW BAND GAP SOURCE AND DRAIN STRUCTURES IN MICROELECTRONIC DEVICES

Intel Corporation, Santa...

1. A method of forming a device comprising:forming source/drain regions in a device substrate;
alloying source/drain material of the source/drain regions with tin to reduce its band gap to close to zero, the source/drain material comprising germanium; and
forming source/drain contacts to couple to the source/drain regions, wherein a small band gap of the alloyed region results in small metal contact resistance, wherein the alloyed region comprises Ge0.7Sn0.3, and wherein the device is ambipolar.

US Pat. No. 10,115,821

FDSOI LDMOS SEMICONDUCTOR DEVICE

Avago Technologies Genera...

14. A fully depleted silicon-on-insulator (FDSOI) semiconductor device, comprising:an extended drain region comprising:
a drain region disposed above a first type well;
a first drain extension region disposed above the first type well; and
a second drain extension region disposed above the first type well,
wherein the drain region, the first drain extension region, and the second drain extension region are laterally spaced apart from each other, and
wherein the first drain extension region is electrically coupled with the second drain extension region;
a source region disposed above a second type well and laterally spaced apart from the extended drain region; and
a channel layer disposed above the second type well and disposed laterally between the source region and the extended drain region,
wherein the drain region and the first drain extension region are disposed above and in contact with a bulk region of the FDSOI semiconductor device, and
wherein the source region, the channel layer, and the second drain extension region are disposed above and in contact with a silicon-on-insulator (SOI) region of the FDSOI semiconductor device.

US Pat. No. 10,115,820

VERTICAL TRANSISTORS WITH SIDEWALL GATE AIR GAPS AND METHODS THEREFOR

SanDisk Technologies LLC,...

1. A method comprising:forming a first vertically-oriented transistor above a substrate, the first vertically-oriented transistor comprising a first sidewall gate disposed in a first direction;
forming a second vertically-oriented transistor above the substrate, the second vertically-oriented transistor comprising a second sidewall gate disposed in the first direction; and
forming an air gap chamber above the substrate disposed between the first sidewall gate and the second sidewall gate, and extending in the first direction, the air gap chamber comprising an air gap, wherein forming the air gap chamber comprises:
forming a first sidewall liner on the first sidewall gate and a second sidewall liner on the second sidewall gate;
etching a top edge of the first sidewall gate below a top edge of the first sidewall liner; and
etching a top edge of the second sidewall gate below a top edge of the second sidewall liner,
wherein:
the first sidewall liner comprises a first upper section and the second sidewall liner comprises a second upper section; and
the first upper section bends or pitches towards the second upper section.

US Pat. No. 10,115,819

RECESSED HIGH VOLTAGE METAL OXIDE SEMICONDUCTOR TRANSISTOR FOR RRAM CELL

CROSSBAR, INC., Santa Cl...

1. A memory recessed MOS transistor device, comprising:a resistive switching device;
a recessed MOS transistor device comprising:
a semiconductor substrate;
a gate formed at least in part in a recess in a top surface of the semiconductor substrate and having a feature size in a direction parallel to the top surface of the semiconductor substrate that is less than about 100 nm;
a dielectric material between the gate and the semiconductor substrate; and
a source region on a first side of the gate and a drain region on an opposing side of the gate, wherein at least one of the source region and drain region is connected to the resistive switching device, and wherein the recessed MOS transistor device and the resistive switching device form a 1T-1R memory device and
wherein the recessed MOS transistor device has a channel length, characterized by a length of a conductive path between the source region and the drain region, that is a function of the feature size and a depth of the recess and is less than or equal to about 430 nanometers (nm), and wherein the recessed MOS transistor device is a high voltage transistor device that is configured to maintain a deactivated state in response to a voltage between the source region and the drain region that is greater than three volts.

US Pat. No. 10,115,818

REDUCING MOSFET BODY CURRENT

SEMICONDUCTOR COMPONENTS ...

1. A bidirectional MOSFET switch having reduced body current, the switch comprising:a body region that is a semiconductor of a first type separating a source region and a drain region that are a semiconductor of a second type, the body region being connected to a body terminal, the source region being connected to a source terminal, and the drain region being connected to a drain terminal;
a buried layer that is a semiconductor of the second type separating the body region from a substrate that is a semiconductor of the first type, the buried layer being coupled to a buried layer terminal;
a gate terminal drivable to form a channel in the body region, thereby enabling conduction between the source terminal and the drain terminal;
a first configuration switch that disconnects the body terminal from the source terminal when the source terminal voltage exceeds the drain terminal voltage; and
a second configuration switch that connects the body terminal to the buried layer terminal when the source terminal voltage exceeds the drain terminal voltage.

US Pat. No. 10,115,817

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Infineon Technologies AG,...

1. A method of manufacturing a semiconductor device, the method comprising:forming a first semiconductor layer on a semiconductor substrate of a first conductivity type having a continuous first area and a second area; thereafter
introducing dopants of the first conductivity type in the continuous first area of the first semiconductor layer; and thereafter
forming a second semiconductor layer on the first semiconductor layer; and
forming trenches in the second semiconductor layer in the continuous first area.

US Pat. No. 10,115,816

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Hyundai Motor Company, S...

1. A semiconductor device, comprising:an n? type layer disposed on a first surface of an n+ type silicon carbide substrate;
a trench disposed within the n? type layer;
an n+ type region and a first p type region disposed at the n? type layer and at a lateral surface of the trench;
a plurality of second p type regions disposed at the n? type layer and are spaced apart from the first p type region;
a gate electrode that includes a first gate electrode disposed at the trench and a plurality of second gate electrodes that extend from the first gate electrode;
a source electrode disposed on the gate electrode and insulated from the gate electrode; and
a drain electrode disposed on a second surface of the n+ type silicon carbide substrate,
wherein the plurality of second p type regions are spaced apart from each other, and the source electrode contacts the plurality of second p type regions and the n? type layer disposed between the plurality of second p type regions,
wherein the semiconductor device comprises a MOSFET region and a diode region,
wherein the MOFET region comprises the n? type layer, the first p type region, the n+ type region, the first gate electrode, the second gate electrode, the source electrode, and the drain electrode,
wherein the diode region comprises the n? type layer, the first p type region, the second p type regions, the source electrode, and the drain electrode, and
wherein the plurality of second gate electrodes extend from the first gate electrode to an upper portion of the second p type region adjacent to the first p type region.

US Pat. No. 10,115,815

TRANSISTOR STRUCTURES HAVING A DEEP RECESSED P+ JUNCTION AND METHODS FOR MAKING SAME

Cree, Inc., Durham, NC (...

1. A transistor device comprising:a gate and a source on an upper surface of the transistor device;
at least one doped well region of a first conductivity type that is different from a second conductivity type of a source region within the transistor device, the at least one doped well region having a recessed portion below the source and extending from the at least one doped well region by a depth sufficient to reduce an electrical field on a gate oxide on the gate, the recessed portion having a doping concentration that is less than a doping concentration of the at least one doped well region; and
a termination area adjacent the at least one doped well region, the termination area including at least one termination structure adjacent the at least one doped well region where the recessed portion is recessed deeper than the termination structure.

US Pat. No. 10,115,814

PROCESS METHOD AND STRUCTURE FOR HIGH VOLTAGE MOSFETS

Alpha and Omega Semicondu...

1. A method for manufacturing a semiconductor power device on a semiconductor substrate comprising:depositing a hard mask atop the semiconductor substrate and patterning the hard mask according to a pre-determined trench configuration;
etching the semiconductor substrate through the patterned hard mask to form a plurality of trenches in the top portion of the semiconductor substrate each having a trench endpoint with an endpoint sidewall perpendicular to a longitudinal direction of the trench with the endpoint sidewall extends vertically downward from a top surface to a trench bottom surface;
applying vertical high energy implant to form trench bottom dopant regions below the trench bottom surface followed by removing the hard mask;
depositing an insulation layer for covering trench sidewalls and an insulation layer for covering the trench bottom surfaces;
applying a low energy tilt implant to form a sidewall dopant region along the endpoint sidewall wherein the sidewall dopant region extends vertically downward along the endpoint sidewall of the trench to reach the trench bottom dopant region to pick-up the trench bottom dopant region to the top surface of the semiconductor substrate; and
forming at least two of the endpoint sidewall body dopant regions in at least two of the endpoint sidewalls that are immediately adjacent to each other as adjacent endpoint sidewall body dopant regions with the adjacent endpoint sidewall body dopant regions extend through an entire semiconductor region between at least two of the endpoint sidewalls and merging the adjacent endpoint sidewall body dopant regions into a joined endpoint sidewall body dopant region to extend vertically downward along an entire length of the endpoint sidewalls of the adjacent trenches to reach and directly contact the laterally extended region of the trench bottom body dopant region.

US Pat. No. 10,115,813

SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:a first III-V compound layer;
a second III-V compound layer over the first III-V compound layer and different from the first III-V compound layer in composition, wherein a carrier channel is located at an interface of the first III-V compound layer and the second III-V compound layer, and wherein the second III-V compound layer is doped providing a contiguous constant composition of the second III-V compound layer;
an opening in a dielectric layer over the second III-V compound layer, wherein the opening continues through the dielectric layer to extends below a top surface of the second III-V compound layer having the contiguous constant composition;
slanted field plates in the opening, wherein the slanted field plates interface the contiguous constant composition wherein the dielectric layer interfaces the contiguous constant composition; and
a gate electrode in the opening and interfacing with the second III-V compound layer and the slanted field plates.

US Pat. No. 10,115,812

SEMICONDUCTOR DEVICE HAVING A SUPERJUNCTION STRUCTURE

Infineon Technologies Ame...

1. A semiconductor device, comprising:a first semiconductor region of a first conductivity type;
a second semiconductor region of a second conductivity type situated below the first semiconductor region;
a third semiconductor region of the second conductivity type situated above the first semiconductor region;
a fourth semiconductor region of the first conductivity type situated between the first and the third semiconductor regions;
first and second control trenches extending through the third and the fourth semiconductor regions into the first semiconductor region, each control trench being bordered by a diffusion region of the first conductivity type; and
a superjunction structure situated in the first semiconductor region between the first and the second control trenches so that the superjunction structure does not extend under either the first or the second control trench, the superjunction structure being separated from the third semiconductor region by the fourth semiconductor region and comprising alternating regions of the first and the second conductivity types.

US Pat. No. 10,115,811

VERTICAL CHANNEL SEMICONDUCTOR DEVICE WITH A REDUCED SATURATION VOLTAGE

STMICROELECTRONICS S.R.L....

1. A vertical channel semiconductor device comprising:a semiconductor body including a substrate having a first conductivity type and a front layer having a second conductivity type, said semiconductor body being delimited by a front surface;
a first trench portion extending within the semiconductor body starting from the front surface and laterally delimiting a first semiconductor region of the semiconductor body;
a second trench portion extending within the semiconductor body starting from the front surface and laterally delimiting a second semiconductor region of the semiconductor body, said first semiconductor region having a maximum width greater than a maximum width of the second semiconductor region;
a first conductive region and a first insulating layer in the first trench portion, the first insulating layer surrounding the first conductive region and contacting the front layer;
a second conductive region and a second insulating layer in the second trench portion, the second insulating layer surrounding the second conductive region and contacting the front layer;
a top region having the second conductivity type; and
a first emitter region having the first conductivity type, which extends into the front layer starting from the front surface and includes:
a full portion which extends in said second semiconductor region, between the first and second trench portions; and
a first annular emitter portion which extends in said first semiconductor region, in contact with said full portion and with the first and second insulation layers, said first annular emitter portion laterally surrounding the top region having the second conductivity type.

US Pat. No. 10,115,810

HETEROJUNCTION BIPOLAR TRANSISTOR WITH A THICKENED EXTRINSIC BASE

GLOBALFOUNDRIES Inc., Gr...

1. A method for forming a heterojunction bipolar transistor, the method comprising:epitaxially growing a first semiconductor layer on a top surface of a substrate;
epitaxially growing a second semiconductor layer on the first semiconductor layer;
amorphizing a first section of the second semiconductor layer;
doping a second section of the second semiconductor layer that has a lateral arrangement relative to the first section of the second semiconductor layer; and
etching the second semiconductor layer beneath the first section and selective to the first section and the second section of the second semiconductor layer to form an emitter beneath the first section and a first cavity that laterally separates the second section from the emitter.

US Pat. No. 10,115,809

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor memory device, the method comprising:forming a channel region by implanting ions into a semiconductor substrate in which active regions and isolation regions are alternately defined parallel to each other, and a support region is defined in a direction perpendicularly crossing the active regions and the isolation regions;
forming first trenches in the isolation regions;
forming an etch mask along inner sidewalls of the first trenches and over the support region;
forming second trenches and a support layer by an etching process using the etch mask; and
forming drain select lines, word lines and source select lines on the semiconductor substrate of the active regions and the isolation regions,
wherein the second trenches are formed under the first trenches and the active regions with a bottom surface lower than a bottom surface of the first trenches wherein the second trenches are not formed in the support region, wherein the support layer is formed in the support region, is perpendicular to the second trenches,
wherein the second trenches are separated by the support layer, and
wherein the support layer is extended under the active regions.

US Pat. No. 10,115,808

FINFET DEVICE AND METHODS OF FORMING

Taiwan Semiconductor Manu...

1. A method comprising:depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate;
forming a first gate spacer along a sidewall of the dummy gate;
plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer;
forming a source/drain region adjacent a channel region of the fin; and
diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region, wherein the first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.

US Pat. No. 10,115,807

METHOD, APPARATUS AND SYSTEM FOR IMPROVED PERFORMANCE USING TALL FINS IN FINFET DEVICES

GLOBALFOUNDRIES INC., Gr...

1. A method, comprising:forming at least a first fin of a transistor, wherein said first fin comprises a first portion comprising silicon, a second portion comprising silicon germanium, and a third portion comprising silicon;
performing an oxide fill process for filling oxide up to said second portion, thereby covering the sides of said first portion and leaving exposed the sides of said second portion;
forming a gate structure above said third portion;
performing an etching process for removing said silicon germanium of said second portion that is not below said gate structure;
forming a first epitaxy region above said first portion; and
forming a second epitaxy region vertically aligned with said first epitaxy region and above said second portion.

US Pat. No. 10,115,806

SEMICONDUCTOR DEVICES

SAMSUNG ELECTRONICS CO., ...

7. A semiconductor device, comprising:at least one active fin extending in a first direction on a semiconductor substrate;
at least one gate line crossing the active fin in a second direction;
semiconductor junctions on the active fin around the gate line;
an insulation interlayer pattern covering the gate line and having at least one contact hole therethrough, at least a portion of the semiconductor junctions being exposed through the at least one contact hole; and
a contact structure contacting the exposed portion of the semiconductor junction through the contact hole, the contact structure including:
a barrier pattern having an upper barrier on an upper portion of a sidewall of the contact hole, and a lower barrier filling a lower portion of the contact hole, a thickness of the lower barrier between top and bottom surfaces being larger than a thickness of the upper barrier between opposite lateral surfaces, and
a conductive contact pattern filling an upper portion of the contact hole defined by the upper barrier and the lower barrier,
wherein the contact structure has a reverse trapezoidal shape having an upper width of 14 nm to 20 nm and a lower width of 5 nm to 10 nm,
wherein the at least one gate line includes:
a gate insulation pattern extending in the second direction and covering top and side surfaces of the at least one active fin and a surface of the semiconductor substrate between the at least one active fin and a neighboring active fin,
a gate conductive pattern arranged on the gate insulation pattern and having a predetermined thickness filling a gap space between the at least one active fin and the neighboring active fin, and
a gate capping pattern arranged on the gate conductive pattern and having an upper surface coplanar with an upper surface of the insulation interlayer pattern.

US Pat. No. 10,115,805

EXTREMELY THIN SILICON-ON-INSULATOR SILICON GERMANIUM DEVICE WITHOUT EDGE STRAIN RELAXATION

International Business Ma...

1. A method of forming a semiconductor structure, the method comprising:forming a strained silicon germanium layer on top of a substrate;
forming at least one patterned hard mask layer on and in contact with at least a first portion of the strained silicon germanium layer; and
oxidizing at least a first exposed portion and a second exposed portion of the strained silicon germanium layer, the oxidizing forming at least one patterned strained silicon germanium area within the strained silicon germanium layer comprising a first oxide end region and a second oxide end region corresponding to first and second exposed portions, respectively, of the strained silicon germanium layer.

US Pat. No. 10,115,804

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

INSTITUTE OF MICROELECTRO...

1. A method for manufacturing a semiconductor device, comprising:forming a gate trench on a substrate;
forming a gate dielectric layer and a metal gate layer thereon in the gate trench;
forming a first tungsten (W) layer on a surface of the metal gate layer, and
forming a tungsten nitride (WN) blocking layer by injecting nitrogen (N) ions into the first W layer; and
forming a second tungsten (W) layer on the tungsten nitride (WN) blocking layer through an Atomic Layer Deposition (ALD) process;
wherein the WN blocking layer is used to prevent elements in the precursors when forming the second W layer from diffusing downwards; and
wherein in forming the WN blocking layer, the N content in WN is controlled, such that elements in the metal gate layer is less than or equal to 5%, or a diffusion depth of the elements is less than or equal to 5% of a total thickness of the metal gate layer when forming the second W layer.

US Pat. No. 10,115,803

FIELD-EFFECT TRANSISTOR AND METHOD FOR THE FABRICATION THEREOF

Fraunhofer-Gesellschaft z...

1. Field-effect transistor having at least one channel layer, said channel layer comprising a group-III-nitride compound semiconductor, wherein the field-effect transistor comprises at least one source electrode and at least one drain electrode, with the at least one source electrode and the at least one drain electrode each having at least one contact, with the at least one contact having a same or smaller depth than the channel layer;said source electrode and drain electrode comprising at least one doped region extending from the same surface into the at least one channel layer, wherein the depth of penetration of said doped region is selected from approximately 10 nm to approximately 200 nm, and a depth of penetration is equal or smaller than a channel depth, and the gradient of the dopant concentration at the lower interface between the channel layer and the doped region is smaller than 14 nm/decade.

US Pat. No. 10,115,802

MANUFACTURING METHOD FOR COMPOUND SEMICONDUCTOR DEVICE

ADVANTEST CORPORATION, T...

1. A manufacturing method for a compound semiconductor device, wherein a semiconductor element is formed on an N-plane side of a GaN epitaxial substrate grown in a Ga-polar direction,wherein the GaN epitaxial substrate has a multilayer structure in which an n-type conductive layer, a first GaN layer that functions as an electron transport layer, an electron supply layer, and a second GaN layer are multilayered in this order in the Ga-polar direction.

US Pat. No. 10,115,801

VERTICAL TRANSISTOR GATED DIODE

International Business Ma...

1. A semiconductor structure comprising:a first doped semiconductor segment of a first conductivity type extending upwards from a doped bottom semiconductor layer located on a substrate;
a second doped semiconductor segment of a second conductivity type located on the first doped semiconductor segment, wherein the second conductivity type is opposite from the first conductivity type;
a doped top semiconductor region laterally surrounding a top portion of the second doped semiconductor segment;
a gate structure laterally surrounding the first doped semiconductor segment and the second doped semiconductor segment located between the doped bottom semiconductor layer and the doped top semiconductor region;
a top spacer located on the gate structure, wherein the top spacer laterally surrounding the second doped semiconductor segment;
a sidewall spacer atop the top spacer, wherein the sidewall spacer laterally surrounding the doped top semiconductor region; and
a first contact structure atop the second doped semiconductor segment and the doped top semiconductor region, wherein the first contact structure is laterally surrounded by the sidewall spacer.

US Pat. No. 10,115,800

VERTICAL FIN BIPOLAR JUNCTION TRANSISTOR WITH HIGH GERMANIUM CONTENT SILICON GERMANIUM BASE

INTERNATIONAL BUSINESS MA...

1. A method of manufacturing a bipolar junction transistor (BJT) structure comprising:providing a substrate having a first semiconductor layer, a silicon germanium layer and a second semiconductor layer sequentially stacked on the substrate;
pattern etching through the second semiconductor layer and recessing the silicon germanium layer to form a plurality of vertical fins spaced apart in a first direction and extending in a second direction crossing the first direction, each of the plurality of vertical fins comprising a silicon germanium pattern, a second semiconductor pattern and a hard mask pattern sequentially stacked on the first semiconductor layer;
forming first spacers on sidewalls of the plurality of vertical fins;
directionally etching away exposed silicon germanium layer above the first semiconductor layer;
depositing a germanium oxide layer to conformally coat exposed top and sidewall surfaces of the plurality of vertical fins and the first semiconductor layer;
performing condensation annealing followed by silicon oxide strip;
removing the first spacers, remaining germanium oxide layer and the hard mask pattern of each of the plurality of vertical fins;
depositing a dielectric material over the first semiconductor layer to fill all spaces among the plurality of vertical fins; and
forming an emitter contact, a base contact and a collector contact connected to the second semiconductor pattern, the silicon germanium pattern and the first semiconductor layer, respectively, in the dielectric material.

US Pat. No. 10,115,799

NON-VOLATILE MEMORY DEVICES AND MANUFACTURING METHODS THEREOF

Samsung Electronics Co., ...

1. A non-volatile memory device, comprising:a channel region extending in a direction perpendicular to an upper surface of a substrate;
gate electrodes and interlayer insulating layers alternately stacked on the upper surface of the substrate along outer side walls of the channel region to provide a vertical stack of layers;
a gate dielectric layer including a tunneling layer, an electric charge storage layer, and a blocking layer including a high-k layer and a low-k layer that is between the high-k layer and the electric charge storage layer, the tunneling layer, the electric charge storage layer, and the blocking layer being sequentially disposed between the channel region and the gate electrodes; and
an anti-oxidation layer disposed on contiguous layers of the vertical stack of layers and between the blocking layer and the gate electrodes.

US Pat. No. 10,115,798

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOYOTA JIDOSHA KABUSHIKI ...

1. A semiconductor device comprising:a semiconductor substrate;
a first electrode disposed on a surface of the semiconductor device and configured to be soldered to a conductive member; and
a second electrode disposed on the surface of the semiconductor device and configured to be wire-bonded to a conductive member,
wherein
the first electrode comprises a first metal layer, a second metal layer, and a third metal layer, the second metal layer being located between the first metal layer and the third metal layer, and a metallic material of the second metal layer being greater in tensile strength than a metallic material of each one of the first metal layer and the third metal layer, and
the second electrode comprises a layer constituted of a same metallic material as one of the first metal layer and the third metal layer, and does not comprise any layers constituted of a same metallic material as the second metal layer.

US Pat. No. 10,115,797

FINFET SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Samsung Electronics Co., ...

1. A semiconductor device comprising:a substrate having a fin-type active region;
a gate insulating layer that covers at least a portion of an upper surface and side portions of the fin-type active region;
a gate line that extends and intersects the fin-type active region while covering at least the portion of the upper surface and the side portions of the fin-type active region, the gate line being on the gate insulating layer; and
a pair of gate spacer layers at side portions of the gate line,
wherein the gate insulating layer extends from between the fin-type active region and the gate line to between the pair of gate spacer layers and the gate line,
wherein a central portion of an upper surface of the gate line in a cross-section perpendicular to an extending direction of the gate line has a concave shape,
wherein the gate line comprises:
a first gate electrode layer that extends while covering the upper surface and the side portions of the fin-type active region and sides of the pair of gate spacer layers, the sides of the pair of gate spacer layers facing each other and the first gate electrode layer defining a recess space; and
a second gate electrode layer that extends while filling the recess space, wherein an upper surface of the second gate electrode layer in a cross-section perpendicular to the extending direction of the gate line has a concave shape, and the second gate electrode layer is spaced apart from the gate spacer layers by the first gate electrode layer, and
wherein a level of an upper surface of the first gate electrode layer with respect to the substrate is gradually reduced such that an inner region of the upper surface of the first gate electrode layer is lower in vertical position relative to an outer region of the upper surface of the first gate electrode, and
wherein a part of an upper surface of the first gate electrode layer, the part being adjacent to the gate insulating layer, has a level higher than that of a part adjacent to the second gate electrode layer with respect to the substrate.

US Pat. No. 10,115,796

METHOD OF PULLING-BACK SIDEWALL METAL LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:forming a first trench, a second trench, and a third trench extending through a dielectric layer over a substrate, wherein the first trench and the second trench have a first width, and further wherein the third trench has a second width that is greater than the first width;
forming a material layer in the first trench, the second trench, and the third trench;
forming a sacrificial layer over the material layer, wherein the sacrificial layer fills the first trench and the second trench while partially filling the third trench, wherein a height of the sacrificial layer in the first trench, a height of the sacrificial layer in the second trench, and a height of the sacrificial layer in the third trench are substantially the same;
forming a patterning layer over the sacrificial layer in the third trench, wherein the patterning layer fills a remaining portion of the third trench;
recessing the sacrificial layer in the first trench and the second trench, wherein a height of sacrificial layer remaining in the first trench is substantially the same as a height of sacrificial layer remaining in the second trench;
recessing the material layer in the first trench and in the second trench, wherein a height of the material layer remaining in the first trench is substantially the same as a height of the material layer remaining in the second trench; and
completely removing the patterning layer, the sacrificial layer remaining in the first trench and the second trench, and the sacrificial layer in the third trench.

US Pat. No. 10,115,795

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate having a square shape in plan view;
an active portion provided in the semiconductor substrate;
a peripheral portion provided around the active portion; and
a resistive field plate provided in the peripheral portion and surrounding the active portion,
wherein the resistive field plate comprises:
an outer-peripheral-side resistive field plate surrounding the active portion;
an inner-circumferential-side resistive field plate surrounding the active portion, disposed between the outer-peripheral-side resistive field plate and the active region, and being spaced apart from the outer-peripheral-side resistive field plate; and
an intermediate resistive field plate provided between the inner-circumferential-side resistive field plate and the outer-circumferential-side resistive field plate and electrically coupling the inner-circumferential-side resistive field plate to the outer-circumferential-side resistive field plate,
wherein the intermediate resistive field plate comprises:
a first intermediate resistive field plate; and
a plurality of second intermediate resistive field plates,
wherein one end of the first intermediate resistive field plate is coupled to the inner-circumferential-side resistive field plate, and another end of the first intermediate resistive field plate is coupled to the outer-circumferential-side resistive field plate,
wherein the first intermediate resistive field plate connects the inner-circumferential-side resistive field plate and the outer-circumferential-side resistive field plate to each other, and has first portions separated from each other in a first direction and connection portions connecting the first portions to each other, each of the first portions extending in a second direction orthogonal to the first direction, and
wherein the second intermediate resistive field plates have end portions respectively connected with first end portions of the first portions of the first intermediate resistive filed plate on one side of the first portions of the first intermediate resistive filed plate, have end portions opened on a side opposite to the end portions of the second intermediate resistive field plates connected with the first end portion of the first portions of the first intermediate resistive filed plate, and respectively extend at least with a curvature.

US Pat. No. 10,115,794

SEMICONDUCTOR DEVICE COMPRISING ACCUMULATION LAYER CHANNEL AND INVERSION LAYER CHANNEL

HYUNDAI MOTOR COMPANY, S...

1. A semiconductor device comprising:an n? type layer disposed on a first surface of an n+ type silicon carbide substrate;
a first trench formed in the n? type layer;
a p type region disposed on both side surfaces of the first trench;
an n+ type region disposed on both side surfaces of the first trench and disposed on the n? type layer and the p type region;
a gate insulating layer disposed inside the first trench;
a gate electrode disposed on the gate insulating layer;
an oxide layer disposed on the gate electrode;
a source electrode disposed on the oxide layer and the n+ region; and
a drain electrode disposed on the second surface of the n+ type silicon carbide substrate,
wherein a first channel as an accumulation layer channel and a second channel as an inversion layer channel are disposed in both side surfaces of the first trench, and
the first channel and the second channel are disposed to be adjacent in a horizontal direction for the first surface of the n+ type silicon carbide substrate.

US Pat. No. 10,115,793

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface;
a first semiconductor layer having a first conductivity type and formed in the semiconductor substrate;
a second semiconductor layer having a second conductivity type different from the first conductivity type and formed in the semiconductor substrate located between the first semiconductor layer and the second main surface;
a plurality of element portions provided in the first main surface of the semiconductor substrate to be spaced apart from each other in a first direction in plan view and extend in a second direction orthogonal to the first direction; and
a plurality of interposed portions provided in the first main surface of the semiconductor substrate to be interposed between the element portions in plan view,
wherein each of the element portions has:
a first trench provided in one of boundary portions between the element portion and the interposed portions to extend from the first main surface in the second direction in plan view and reach a middle point in the first semiconductor layer;
a second trench provided in the other of the boundary portions between the element portion and the interposed portions to extend from the first main surface in the second direction in plan view and reach a middle point in the first semiconductor layer;
a third trench provided between the first and second trenches to extend from the first main surface in the second direction in plan view and reach a middle point in the first semiconductor layer;
a first trench electrode embedded in the first trench via a first insulating film;
a second trench electrode embedded in the second trench via a second insulating film;
a third trench electrode embedded in the third trench via a third insulating film;
a first semiconductor region having the second conductivity type and formed in the first main surface of the semiconductor substrate located between the first and third trenches to come in contact with the first and third insulating films;
a second semiconductor region having the second conductivity type and formed in the first main surface of the semiconductor substrate located between the second and third trenches to come in contact with the second and third insulating films;
a first coupling portion provided between the first and third trenches to extend in the second direction in plan view and reach a middle point in the first semiconductor region;
a second coupling portion provided between the second and third trenches to extend in the second direction in plan view and reach a middle point in the second semiconductor region; and
a plurality of third semiconductor regions each having the first conductivity type and formed in the first main surface of the semiconductor substrate located between the first coupling portion and the third trench and between the second coupling portion and the third trench in contact relation with the third insulating film to be shallower than the first and second coupling portions and spaced apart at a regular interval in the second direction in plan view,
wherein each of the interposed portions has a fourth semiconductor region having the second conductivity type and reaching the first semiconductor layer from the first main surface, and
wherein, with regard to two of the element portions which are adjacent to each other in the first direction with the interposed portion being interposed therebetween, one of the third semiconductor regions formed in one of the adjacent two element portions is disposed in the first direction from a region interposed between two of the third semiconductor regions formed in the other of the adjacent two element portions which are adjacent to each other in the second direction.

US Pat. No. 10,115,792

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

ROHM CO., LTD., Kyoto (J...

1. A semiconductor device comprising:an insulating layer formed selectively on a semiconductor layer to isolate an active region in the semiconductor layer;
a lower electrode, formed on the insulating layer, having an end portion at a position spaced apart by a predetermined distance inward from a periphery of the insulating layer;
a dielectric film formed on the lower electrode;
an upper electrode, formed on the dielectric film, facing the lower electrode with the dielectric film interposed between the upper electrode and the lower electrode; and
a passivation film, interposed between the insulating layer and the lower electrode, the passivation film including an insulating material having an etching selectivity with respect to the insulating layer,
wherein an end portion of the passivation film is flush with the periphery of the insulating layer on a boundary between the insulating layer and the active region.

US Pat. No. 10,115,791

SEMICONDUCTOR DEVICE INCLUDING A SUPER JUNCTION STRUCTURE IN A SIC SEMICONDUCTOR BODY

Infineon Technologies AG,...

1. A semiconductor device, comprising:a body region of a first conductivity type in a SiC semiconductor body of a second conductivity type; and
a super junction structure in the SiC semiconductor body, and comprising a drift zone section of the second conductivity type and a compensation structure of the first conductivity type,
wherein the compensation structure adjoins the body region and includes compensation sub-structures consecutively arranged along a vertical direction perpendicular to a surface of the SiC semiconductor body,
wherein the compensation sub-structures include a first compensation sub-structure and a second compensation sub-structure,
wherein a resistance of the second compensation sub-structure between opposite ends of the second compensation sub-structure along the vertical direction is at least five times larger than a resistance of the first compensation sub-stricture between opposite ends of the first compensation sub-structure along the vertical direction.

US Pat. No. 10,115,790

ELECTRONIC DEVICE INCLUDING AN INSULATING STRUCTURE

SEMICONDUCTOR COMPONENTS ...

1. A process of forming an electronic device comprising:patterning a substrate to define a trench and a first anchor having a proximal portion and a distal portion, wherein
the first anchor extends from a sidewall of the trench,
the sidewall is closer to the proximal portion than to the distal portion, and
the proximal portion has a width that is less than a width of the distal portion; and
forming an insulating structure within the trench and adjacent to the first anchor.

US Pat. No. 10,115,789

NONVOLATILE MEMORY CELL WITH IMPROVED ISOLATION STRUCTURES

WAFERTECH, LLC, Camas, W...

16. A method for forming a non-volatile memory cell, comprising:forming a P-field region in a semiconductor substrate, the P-field region having a first impurity concentration;
forming a plurality of spaced apart higher concentration P+ regions within the P-field region, the higher concentration P+ regions each having a higher concentration than the first impurity concentration; and
forming a plurality of floating gate transistors in the P-field region between the higher concentration P+ regions, wherein two respective adjacent ones of the plurality of floating gate transistors are isolated from each other by a respective one of the plurality of higher concentration P+ regions, and wherein the non-volatile memory cell is free of shallow trench isolation (STI).

US Pat. No. 10,115,788

SEMICONDUCTOR DEVICES WITH HORIZONTAL GATE ALL AROUND STRUCTURE AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device having a horizontal gate all around structure, the semiconductor device comprising:a fin that is disposed on a substrate and includes
a source-facing side and a drain-facing side,
an anti-punch-through (APT) layer above and physically contacting the substrate,
a barrier layer above and physically contacting the APT layer, wherein the barrier has a different composition from the substrate,
a metal gate above the barrier layer, and
a nanowire above the metal gate;
a source located alongside the fin's source-facing side and projecting upward from the barrier layer to a location above the nanowire, such that a portion of the barrier layer is sandwiched between the APT layer and the source; and
a drain located alongside the fin's drain-facing side and projecting upward from the barrier layer to a location above the nanowire, such that the nanowire extends horizontally from physical contact with the source to physical contact with the drain.

US Pat. No. 10,115,787

LOW LEAKAGE FET

pSemi Corporation, San D...

1. A FET fabricated on a silicon-on-insulator substrate, including:(a) an isolated silicon island;
(b) a gate structure overlying the isolated silicon island and having a center length L, the gate structure having central and edge regions each with an associated work function ?MF
(c) source and drain regions within the isolated silicon island and defined by the gate structure;
(d) a central conduction channel between the source and drain regions, the central conduction channel having a threshold voltage VtC; and
(e) at least one edge transistor defined by a corresponding edge region of the gate structure overlying the isolated silicon island, each edge transistor having a threshold voltage VtE determined in part by the work function ?MF of the corresponding edge region of the gate structure;wherein the work function ?MF of at least one corresponding edge region of the gate structure is increased sufficiently to increase the VtE of such corresponding edge transistor to be approximately equal to or greater than VtC.

US Pat. No. 10,115,786

CAPACITOR AND METHOD FOR FABRICATING THE SAME

UNITED MICROELECTRONICS C...

1. A capacitor, comprising:a bottom electrode on a substrate;
a middle electrode on the bottom electrode, wherein in a cross-section view, the middle electrode comprises a first H-shape, a second H-shape adjacent to the first H-shape, and a first horizontal portion connecting the first H-shaped and the second H-shape, wherein the first H-shape comprises two vertical portions and a second horizontal portion and the two vertical portions are orthogonal to a top surface of the substrate and a bottom surface of the first horizontal portion is substantially coplanar with a bottom surface of the two vertical portions;
a first dielectric layer between the bottom electrode and the middle electrode, wherein the first dielectric layer fully covers a bottom surface of the second horizontal portion; and
a top electrode on the middle electrode, wherein the bottom electrode has a flat bottom surface spanning entire width of the capacitor.

US Pat. No. 10,115,785

MEMORY CELLS AND DEVICES

Xerox Corporation, Norwa...

1. A memory cell comprising a flexible substrate layer and a layer comprising a crosslinked mixture of an acrylic polyol, an alkylene urea-glyoxal resin, and an acid catalyst, wherein said acrylic polyol possesses an OH equivalent weight of from about 300 to about 1,500, and a glass transition temperature of from about ?20° C. to about 90° C.

US Pat. No. 10,115,784

SEMICONDUCTOR DEVICE, MIM CAPACITOR AND ASSOCIATED FABRICATING METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:a semiconductor substrate;
a first dielectric layer over the semiconductor substrate;
a second dielectric layer over the first dielectric layer;
a via extending through the second dielectric layer;
a bottom conductive layer conformably formed at a bottom and along side walls of the via;
a third dielectric layer conformably formed over the bottom conductive layer;
an upper conductive layer conformably formed over the third dielectric layer; and
an upper contact formed over and coupled to the upper conductive layer and filling the via;
wherein the upper conductive layer provides a diffusion barrier between the upper contact and the third dielectric layer.

US Pat. No. 10,115,783

SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME, AND SIGNAL TRANSMITTING/RECEIVING METHOD USING THE SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:a semiconductor substrate;
an internal circuit provided on the semiconductor substrate;
a plurality of external connection pads provided on the semiconductor substrate and electrically connected to the internal circuit to transmit and receive signals to and from an outside of the semiconductor device;
an inductor provided on the semiconductor substrate and including the internal circuit and the plurality of external connection pads and connected to the internal circuit;
a shield member provided on the semiconductor substrate and positioned among the inductor, the internal circuit, and the plurality of external connection pads;
a power supply circuit provided on the semiconductor substrate; and
a power supply receiving inductor for supplying power to the internal circuit,
wherein the power supply receiving inductor is connected to the power supply circuit and supplies power to the internal circuit via the power supply circuit, and
wherein the plurality of external connection pads include a power supply external connection pad and a plurality of signal external connection pads.

US Pat. No. 10,115,782

DISPLAY DEVICE WITH DURABLE WIRING

Japan Display Inc., Toky...

6. A display device comprising:a first substrate including a display region having pixels and a peripheral region surrounding the display region;
a gate line driver circuit in the peripheral region, the gate line driver circuit comprising a first circuit, a second circuit, and a wiring connecting the first circuit to the second circuit; and
a gate line electrically connected to the display region and the gate line driver circuit, wherein
the gate line and the wiring each have a zigzag structure, and
a pitch of the zigzag structure of the gate line is larger than that of the wiring.

US Pat. No. 10,115,781

ORGANIC LIGHT-EMITTING DIODE DISPLAY

Chunghwa Picture Tubes, L...

1. An organic light-emitting diode display comprising:a pixel array substrate comprising:
a first substrate having a plurality of pixel regions arranged in an array and a peripheral region surrounding the pixel regions;
a plurality of pixel units located in the pixel regions, each of the pixel units comprising:
a switch transistor having an input electrode, a control electrode, and an output electrode;
a driver transistor having an input electrode, a control electrode, and an output electrode, wherein the output electrode of the switch transistor is electrically coupled to the control electrode of the driver transistor; and
a pixel electrode electrically coupled to the output electrode of the driver transistor;
a plurality of data lines located on the first substrate and electrically coupled to the input electrodes of the switch transistors;
a plurality of scan lines located on the first substrate and electrically coupled to the control electrodes of the switch transistors;
a plurality of constant voltage lines located on the first substrate and electrically coupled to the input electrodes of the driver transistors;
a constant voltage source located on the peripheral region of the first substrate, the constant voltage source providing a constant voltage to the constant voltage lines; and
a conductive pattern located on the first substrate and overlapped with the control electrode of each of the driver transistors;
a second substrate opposite to the first substrate;
an organic light-emitting diode layer located between the second substrate and the pixel electrodes; and
a common electrode layer located between the second substrate and the organic light-emitting diode layer and overlapped with the control electrodes of the driver transistors, wherein a film layer where the control electrodes of the driver transistors are located is between the first substrate and a film layer where the input electrodes of the driver transistors are located, the film layer where the input electrodes of the driver transistors are located is between a film layer where the conductive pattern is located and the film layer where the control electrodes of the driver transistors are located, the film layer where the conductive pattern is located is between the organic light-emitting diode layer and the film layer where the input electrodes of the driver transistors are located, and the conductive pattern is in electrical and physical contact with the common electrode layer.

US Pat. No. 10,115,780

DISPLAY DEVICE

Samsung Display Co., Ltd....

1. A display device comprising:a substrate comprising a first display region having a first width in a first direction, a second display region having a second width smaller than the first width in the first direction, a peripheral region at a periphery of the first and second display regions, and a dummy region in the peripheral region;
a first pixel in the first display region;
a second pixel in the second display region;
a first control line connected to the first pixel, the first control line extending along the first direction in the first display region;
a second control line connected to the second pixel, the second control line extending along the first direction in the second display region; and
a dummy line connected to the second control line, the dummy line being in the dummy region,
wherein the second control line is at a first conductive layer on a first insulating layer, the first insulating layer is on the substrate, the dummy line is at a second conductive layer on a second insulating layer, and the second insulating layer is on the first conductive layer.

US Pat. No. 10,115,779

DISPLAY UNIT

Sony Corporation, (JP)

1. A display unit comprising:a first pixel including a first organic EL device configured to emit green light, and a first driving circuit configured to drive the first organic EL device;
a second pixel including a second organic EL device configured to emit blue light, and a second driving circuit configured to drive the second organic EL device;
a third pixel including a third organic EL device configured to emit red light, and a third driving circuit configured to drive the third organic EL device; and
a control line connected to each of the first driving circuit, the second driving circuit, and the third driving circuit,
wherein the second driving circuit is located between the first driving circuit and the third driving circuit,
wherein the first driving circuit includes a first driving transistor, a first sampling transistor, and a first capacitor having a first electrode and a second electrode, the first capacitor being connected to a gate electrode of the first driving transistor, the first electrode is disposed over the second electrode,
wherein the second driving circuit includes a second driving transistor, a second sampling transistor, and a second capacitor having a first electrode and a second electrode, the second capacitor being connected to a gate electrode of the second driving transistor, the first electrode is disposed over the second electrode,
wherein the third driving circuit includes a third driving transistor, a third sampling transistor, and a third capacitor having a first electrode and a second electrode, the third capacitor being connected to a gate electrode of the third driving transistor, the first electrode is disposed over the second electrode,
wherein the second organic EL device has a blue light emission area overlapping the second capacitor in a plan view,
wherein a distance between a channel region of the first driving transistor and the blue light emission area is larger than a distance between the first electrode of the first capacitor and the blue light emission area, and
wherein a distance between a channel region of the third driving transistor and the blue light emission is larger than a distance between the first electrode of the third capacitor and the blue light emission area.

US Pat. No. 10,115,778

ELECTRO-OPTICAL APPARATUS, MANUFACTURING METHOD FOR ELECTRO-OPTICAL APPARATUS, AND ELECTRONIC DEVICE

SEIKO EPSON CORPORATION, ...

1. A light-emitting device, the light-emitting device comprising:a light-reflective layer;
an opposing electrode;
a functional layer including a light-emitting layer, the functional layer being disposed between the light-reflective layer and the opposing electrode;
a first pixel electrode disposed between the light-reflective layer and the functional layer;
a second pixel electrode disposed between the light-reflective layer and the functional layer;
a third pixel electrode disposed between the light-reflective layer and the functional layer;
an insulating layer having a first insulating layer, a second insulating layer, and a third insulating layer,
wherein the first insulating layer is disposed between the first pixel electrode and the light-reflective layer,
wherein the first insulating layer and the third insulating layer are disposed between the second pixel electrode and the light-reflective layer,
wherein the first insulating layer, the second insulating layer, and the third insulating layer are disposed between the third pixel electrode and the light-reflective layer,
wherein the second insulating layer is disposed between the first insulating layer and the third insulating layer in a region that the third pixel electrode overlaps the light-reflective layer,
wherein the third insulating layer physically contacts the first insulating layer in a region that the second pixel electrode overlaps the light-reflective layer, and
wherein at least part of an edge of the second insulating layer is covered by the third insulating layer, and
wherein at least one of the first, second and third insulating layers is made of a material different from others of the first, second and third insulating layers.

US Pat. No. 10,115,777

DISPLAY DEVICE

Japan Display Inc., Toky...

6. A display device comprising:a plurality of pixel electrodes including a first pixel electrode;
a bank covering an edge part of the first pixel electrode, and a region between adjacent pixel electrodes;
a first electrode arranged separated from the first pixel electrode and above the bank;
a first organic layer arranged above the first pixel electrode, above the first electrode and above the bank;
a second organic layer arranged above the first organic layer overlapping the first pixel electrode;
a third organic layer arranged above the second organic layer, above the first organic layer overlapping the first electrode, and above the first organic layer overlapping the bank;
an opposing electrode arranged above the third organic layer overlapping the first pixel electrode; and
a second electrode arranged above the third organic layer overlapping the first electrode, wherein
a region stacked with the first pixel electrode, the first organic layer, the second organic layer, the third organic layer and the opposing electrode corresponds to a region of a light emitting element, and
a region stacked with the first electrode, the first organic layer, the third organic layer and the second electrode corresponds to a region of a light receiving element.

US Pat. No. 10,115,776

ORGANIC LIGHT EMITTING DISPLAY DEVICES

Samsung Display Co., Ltd....

1. An electroluminescent device, comprising:a substrate;
a plurality of first electrodes located on the substrate to be spaced apart from each other;
a pixel defining layer disposed on the substrate to expose portions of the first electrodes;
an intermediate layer disposed on the pixel defining layer and the first electrodes;
an emitting layer disposed on the intermediate layer to overlap the first electrode;
a second electrode disposed on the emitting layer; and
wherein the intermediate layer has a first pattern overlapping the portion of the plurality of first electrodes exposed by the pixel defining layer, a second pattern being sloped to confine at least a portion of the emitting layer, and a third pattern overlapping a portion of the substrate between adjacent first electrodes that are spaced apart from each other;
wherein a charge from each first electrode advances to the emitting layer through the first pattern;
wherein at least one of the second and third patterns has a different property from a remaining portion of the intermediate layer;
wherein the different property is at least one selected from the group consisting of an electrical conductivity smaller than the first pattern, an electrical resistance greater than the first pattern, an ink-affinity smaller than the first pattern, and a surface energy smaller than the first pattern; and
wherein the at least one of the second and third patterns has a chemical element diffused from the pixel defining layer to be fixed in the at least one of the second and third patterns.

US Pat. No. 10,115,775

OLED DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF, AND DISPLAY APPARATUS

BOE Technology Group Co.,...

1. A method for manufacturing an organic light-emitting diode (OLED) display device comprising:forming an array comprising first electrodes on a base substrate, wherein an area to which the first electrodes correspond is a display area;
forming pixel defining layers in intervals, with each of the pixel defining layers disposed between two adjacent first electrodes so that a width of a cross section of each pixel defining layer is relatively larger at a middle portion and reduced gradually towards an upper portion and towards a lower portion, and a side surface of the lower portion of the pixel defining layer and an upper surface of the first electrode intersect with each other and form an angle smaller than 90° therebetween;
forming organic light-emitting layers respectively on the first electrodes between the pixel defining layers; and
forming a second electrode which is at least provided on the organic light-emitting layers,
wherein each of the pixel defining layers is a single-layered structure and made of a same material, and
a thickness of each of the organic light-emitting layers formed is not smaller than a height of a widest position at the middle portion of each of the pixel defining layers;
wherein the forming the pixel defining layers comprises:
forming a photoresist on the base substrate on which the first electrodes are formed;
irradiating light, which passes through a mask plate, on the photoresist at a predetermined first incident angle with respect to a direction perpendicular to the base substrate, to perform first exposure to the photoresist; and
irradiating light, which passes through the mask plate, onto the photoresist at a predetermined second incident angle with respect to the direction perpendicular to the base substrate, to perform second exposure to the photoresist, and developing to remove the photoresist corresponding to the display area and hence exposing the first electrodes, wherein lines in which an incident direction of the light in the first exposure is located and lines in which an incident direction of the light in the second exposure is located are respectively arranged on opposite sides of normal lines which respectively pass through centers of the first electrodes exposed, so that the width of the cross section of each pixel defining layer formed is relatively larger at the middle portion and reduced gradually towards the upper portion and towards the lower portion, and the predetermined first incident angle and the predetermined second incident angle are both larger than 0° and smaller than 90°.

US Pat. No. 10,115,774

DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME

Japan Display Inc., Toky...

1. A method of manufacturing a display device, comprising the steps of:preparing a base body including a plurality of first regions and a second region having a shape surrounding each of the first regions, and forming a resin layer in the plurality of first regions;
forming, in the second region, a buried layer that is made of silicon glass and has a moisture-proof property higher than the resin layer, the buried layer including a first portion directly overlying an upper surface of the resin layer and a second portion surrounding a peripheral edge of the resin layer;
forming, on the buried layer and the resin layer, an overcoat layer that includes a metal oxide material or a metal nitride material;
forming, on the overcoat layer, a functional layer that includes pixels, each of the pixels including an organic light emitting element; and
cutting the buried layer and the functional layer along a line passing through the second region, so as to separate the resin layer into a plurality of portions respectively corresponding to the plurality of first regions, wherein
a first thickness of the second portion gradually decreases from a cut edge of the buried layer toward the peripheral edge of the resin layer in a cross-sectional view.

US Pat. No. 10,115,773

HYBRID HIGH ELECTRON MOBILITY TRANSISTOR AND ACTIVE MATRIX STRUCTURE

International Business Ma...

1. A high electron mobility field-effect transistor comprising:an inorganic semiconductor layer;
a gate electrode;
first and second ohmic contacts operatively associated with the inorganic semiconductor layer, and
an organic gate barrier layer operatively associated with the gate electrode, the organic gate barrier layer being positioned between the gate electrode and the inorganic semiconductor layer and including one or more organic semiconductor layers operative to block electrons and holes.

US Pat. No. 10,115,772

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device comprising a resistance random access memory in which transistors and resistance change elements that are coupled in series to the transistors are arranged over a semiconductor substrate,wherein the resistance change element comprises a first electrode that applies a positive voltage when being transited from a low resistance state to a high resistance state, a second electrode that faces the first electrode, and a resistance change layer that is sandwiched between the first electrode and the second electrode and comprises an oxide of transition metal,
wherein the resistance change layer contains nitrogen, and
wherein the concentration of nitrogen on the first electrode side in the resistance change layer is higher than that on the second electrode side,
wherein the concentration of nitrogen contained in the resistance change layer continuously declines from the first electrode side to either: the second electrode side, or a distance from the first electrode side at which the concentration of nitrogen reaches approximately zero.

US Pat. No. 10,115,771

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:a substrate;
a first wiring extending in a first direction;
a second wiring being provided between the substrate and the first wiring extending in the first direction, the second wiring being located away from the first wiring in a second direction crossing the first direction and perpendicular to the substrate;
a third wiring being provided between the first wiring and the second wiring, the third wiring extending in a third direction crossing the first and the second directions, the third direction being parallel to the substrate;
a first variable resistance element being provided between the first wiring and the third wiring;
a second variable resistance element being provided between the second wiring and the third wiring;
a first contact extending in the second direction, one end of the first contact being connected to the first wiring, and a length between the first contact and the third wiring in the first direction being a first length and a length between the first contact and the second wiring in the first direction being a second length shorter than the first length;
a second contact being located below the second wiring in the second direction, one end of the second contact being connected to the other end of the first contact, and the second contact extending in the second direction; and
a third contact being connected to the second wiring, the third contact extending in the second direction, and a length between the second contact and the third contact in the first direction being a third length longer than the second length.

US Pat. No. 10,115,770

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NONVOLATILE MEMORY

SanDisk Technologies LLC,...

1. A method comprising:forming a dielectric material and a first sacrificial material above a substrate;
forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material;
forming a first hole in the second sacrificial material, the first hole disposed in a first direction;
forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction;
forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole;
forming a second hole in the second sacrificial material;
forming a second portion of the nonvolatile memory material on a sidewall of the second hole;
forming a local bit line in the second hole; and
forming a memory cell comprising the nonvolatile memory material at an intersection of the local bit line and the word line layer, wherein the method further comprising: forming a plurality of alternating dielectric material layers and first sacrificial material layers above the substrate and disposed adjacent the second sacrificial material; forming a plurality of word line layers above the substrate via the first hole, each of the plurality of word line layers disposed in the second direction; and forming a plurality of memory cells comprising the nonvolatile memory material, each of the memory cells formed at an intersection of the local bit line and a corresponding one of the word line layers.

US Pat. No. 10,115,769

RESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

MACRONIX INTERNATIONAL CO...

1. A resistive random access memory (ReRAM) device, comprising:a first dielectric layer disposed on a substrate and covering a gate oxide structure on the substrate, and the first dielectric layer comprising:
a first insulating layer disposed on the substrate; and
a stop layer disposed on the first insulating layer and directly contacting a top surface of the gate oxide structure, wherein the stop layer is a hydrogen controlled layer;
a first conductive connecting structure disposed on the substrate and penetrating the first dielectric layer; and
a ReRAM unit disposed on the first conductive connecting structure.

US Pat. No. 10,115,768

LIGHT EMITTING DEVICE AND DISPLAY DEVICE

NICHIA CORPORATION, Anan...

1. A light emitting device comprising:a first light emitting element to emit from a first front surface a first light having a peak wavelength in a range from 440 nm to 485 nm, the first front surface having a polygonal shape with five or more sides and being substantially perpendicular to a front-rear direction of the light emitting device;
a second light emitting element to emit from a second front surface a second light having a peak wavelength in a range from 495 nm to 573 nm, the second front surface having a polygonal shape with five or more sides and being substantially perpendicular to the front-rear direction;
a third light emitting element including a third front surface, a bottom surface opposite to the third front surface in the front-rear direction, and a side surface connecting the third front surface and the bottom surface, the third light emitting element being configured to emit from the third front surface a third light having a peak wavelength in a range from 440 nm to 485 nm, the third front surface having a polygonal shape with five or more sides and being substantially perpendicular to the front-rear direction;
a fluorescent material provided on the third front surface of the third light emitting element and having a fluorescent side surface extending along the front-rear direction;
a film provided to surround the side surface of the third light emitting element and the fluorescent side surface of the fluorescent material;
a first lens provided over the first front surface of the first light emitting element;
a second lens provided over the second front surface of the second light emitting element; and
a third lens provided over the third front surface of the third light emitting element, the film being provided between the third light emitting element and the third lens.

US Pat. No. 10,115,767

DUAL LIGHT EMISSION MEMBER, DISPLAY APPARATUS HAVING THE SAME AND LIGHTING APPARATUS HAVING THE SAME

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a substrate comprising:
a first area at which an image is displayed in a first direction with light, and
a second area at which an image is displayed in a second direction opposite to the first direction with light, wherein a portion of the substrate at the second area is light-transmissive;
a first light-emitting member on the substrate and disposed in the first area of the substrate; and
a lens commonly disposed over the first area and the second area of the substrate so as to cover the first light-emitting member,
wherein
at the first area, the light with which the image is displayed in the first direction passes through the lens, and
at the second area, the light with which the image is displayed in the second direction opposite to the first direction passes through the substrate.

US Pat. No. 10,115,766

STRETCHABLE DISPLAY APPARATUS

SAMSUNG DISPLAY CO., LTD....

1. A display apparatus comprising:a plurality of light-emitting diodes;
a stretchable substrate comprising:
a flat portion including a flat surface; and
a plurality of protrusions protruding from the flat portion, wherein each of the protrusions is stretchable and has an inclined surface with respect to the flat surface, and at least some light-emitting diodes of the plurality of light-emitting diodes are disposed on the inclined surface, wherein an inclination angle of the inclined surface is variable with respect to extension or reduction of the stretchable substrate; and
a plurality of thin film transistors disposed inside the stretchable substrate and connected to the light-emitting diodes.

US Pat. No. 10,115,765

X-RAY FLAT-PANEL DETECTOR AND METHOD FOR PREPARING THE SAME, AND WHITE INSULATING MATERIAL

BOE TECHNOLOGY GROUP CO.,...

1. An X-ray flat-panel detector, comprising:a thin-film transistor substrate;
an insulating reflection layer, which is provided on the thin-film transistor substrate and has a diffuse reflection function, wherein the insulating reflection layer is provided with a contact hole through which a source electrode of the thin-film transistor substrate is exposed, the insulating reflection layer being made of a white insulating material containing, by weight percentage, 80%-98% of a resin matrix and 2%-20% of a light-beam diffuse reflection functional material powder;
a pixel electrode, which is provided on the insulating reflection layer, wherein the pixel electrode is electrically connected to the source electrode of the thin-film transistor substrate via the contact hole;
a photodiode, which covers the pixel electrode;
an electrode, which is provided on the photodiode; and
an X-ray conversion layer, which is provided on the electrode.

US Pat. No. 10,115,764

MULTI-BAND POSITION SENSITIVE IMAGING ARRAYS

RAYTHEON COMPANY, Waltha...

1. A light detection device, comprising:a first array of pixels formed from a first layer of semiconductor material having a bandgap corresponding to a first range of wavelengths, the first array of pixels disposed along a focal plane, each pixel of the first array of pixels configured as a position sensing pixel and to output one or more first signals in proportion to a position of photons incident thereon that are within the first range of wavelengths, the one or more first signals referenced to a ground common;
a first contact disposed on at least a portion of each pixel of the first array of pixels;
at least one barrier layer disposed on a surface of the first layer of semiconductor material;
a second array of pixels monolithically formed on the first array of pixels and formed from a second layer of semiconductor material disposed on a first portion of a surface of the at least one barrier layer, the second layer of semiconductor material having a bandgap corresponding to a second range of wavelengths different from the first range of wavelengths, the second array of pixels disposed along the focal plane, each pixel of the second array of pixels configured as an image sensing pixel and to generate one or more second signals in proportion to a number of photons incident thereon that are within the second range of wavelengths, the one or more second signals referenced to the ground common, wherein the pixels of the second array are sized to be smaller than the pixels of the first array;
a second contact disposed on at least a portion of each pixel of the second array of pixels; and
a third contact disposed on a second portion of the surface of the at least one barrier layer,
wherein the second array of pixels are formed on and disposed outwardly from the first array of pixels such that a plurality of pixels of the second array are associated with and spatially co-registered along the same axis of an optical path of incident photons with each pixel of the first array of pixels, the first and second arrays of pixels arranged along respective planes that are parallel to each other and to the focal plane and that are perpendicular to the optical path, such that the incident photons travel along the optical path from the first array of pixels to the second array of pixels.

US Pat. No. 10,115,763

SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A semiconductor device, comprising:a first substrate including a pixel array and first connection pads;
a second substrate bonded to the first substrate, the second substrate including second connection pads and a logic circuit for driving the pixel array, wherein the first connection pads are located at a different level in the semiconductor device than the second connection pads; and
connection wirings that electrically connect the first connection pads to the second connection pads,
wherein, in a plan view, pairs including one of the first connection pads and one of the second connection pads form a connection pad array, and
wherein, in the plan view, at least one of the first connection pads partially overlaps at least one of the second connection pads.

US Pat. No. 10,115,762

SOLID-STATE IMAGE PICKUP DEVICE, METHOD OF MANUFACTURING THEREOF, AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A solid-state image pickup device comprising:a plurality of pixels, each of which includes a photoelectric conversion portion and a pixel transistor formed in a front surface side of a substrate, wherein a rear surface side of the substrate is set as a light receiving plane of the photoelectric conversion portion; and
an element, which becomes a passive element or an active element, which is disposed in the front surface side of the substrate so as to be superimposed on the photoelectric conversion portion.

US Pat. No. 10,115,761

SOLID-STATE IMAGING DEVICE AND MANUFACTURING METHOD THEREOF

Sony Semiconductor Soluti...

1. An imaging device comprising:a gate electrode of a first transfer transistor between a floating diffusion unit and a first photoelectric conversion region;
a gate electrode of a second transfer transistor between the floating diffusion unit and a second photoelectric conversion region;
a gate electrode of a selection transistor between a first semiconductor region and a second semiconductor region;
a gate electrode of an amplification transistor between the second semiconductor region and a third semiconductor region; and
an element separation region adjacent to the first photoelectric conversion region,
wherein the gate electrode of the first transfer transistor extends over a part of the element separation region, and
wherein the first photoelectric conversion region includes a first portion having a first conductivity-type and a second portion having a second conductivity-type.

US Pat. No. 10,115,760

PIXEL CELL AND ITS METHOD FOR APPLYING VOLTAGE GENERATED IN A PHOTOSENSOR TO A GATE CAPACITANCE AND ALTERNATELY RESETTING THE APPLIED VOLTAGE

Fraunhofer-Gesellschaft z...

1. A pixel cell, comprising:an output;
a photosensor designed in order to generate as a function of a radiation in a first measurement cycle a first measurement current and in a second measurement cycle a second measurement current;
an output node;
a current storage device designed so that in a first operating mode a current can be impressed by the current storage device as a function of the first measurement current and that in a second operating mode the current storage device is designed to hold the impressed current so that the impressed current can be recorded at the output node; and
a switching unit designed in order to form in a readout cycle a difference of the impressed current and the second measurement current at the output node and to couple the output node to output.

US Pat. No. 10,115,759

CMOS IMAGE SENSOR

SAMSUNG ELECTRONICS CO., ...

1. A complementary metal-oxide semiconductor (CMOS) image sensor, comprising:a device isolation layer provided in a trench of a substrate, the device isolation layer defining a pixel; and
a photoelectric conversion device provided in the pixel,
wherein the device isolation layer comprises:
a conductive layer;
a tunneling layer interposed between the conductive layer and the substrate; and
a trap layer interposed between the tunneling layer and the conductive layer, the trap layer defining a plurality of trap patterns, each of the plurality of trap patterns having a flat surface in contact with the tunneling layer and a non-flat surface spaced apart from the tunneling layer, and
wherein the trap layer is a silicon-containing conductive material.

US Pat. No. 10,115,758

ISOLATION STRUCTURE FOR REDUCING CROSSTALK BETWEEN PIXELS AND FABRICATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method for fabricating a semiconductor device, the method comprising:forming a first trench in a semiconductor substrate;
forming a dielectric layer covering the semiconductor substrate, wherein the dielectric layer has a trench portion located in the first trench of the semiconductor substrate;
forming a reflective material layer on the trench portion of the dielectric layer; and
etching the reflective material layer to form an isolation structure, wherein the isolation structure comprises a bottom portion in a second trench formed by the trench portion of the dielectric layer and a top portion located on the bottom portion of the isolation structure, wherein a top surface of the top portion of the isolation structure is in a position higher than a top surface of the semiconductor substrate.

US Pat. No. 10,115,757

IMAGE SENSOR AND ELECTRONIC DEVICE HAVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. An image sensor comprising:a substrate comprising a photoelectric conversion element;
a pixel lens formed over the substrate and comprising a plurality of light condensing layers in which a lower layer has a larger area than an upper layer;
a color filter layer covering an entire surface of the pixel lens; and
an anti-reflection structure formed over the color filter layer, wherein the anti-reflection structure prevents reflection of incident light,
wherein each of the plurality of light condensing layers has a flat surface, and the lower layer exposed by the upper layer has a smaller width than the wavelength of the incident light, and
wherein the upper layer has a smaller effective refractive index than the lower layer, and the upper layer and the lower layer are formed of a same material.

US Pat. No. 10,115,756

SOLID-STATE IMAGE PICKUP DEVICE AND IMAGE PICKUP SYSTEM HAVING LIGHT SHIELDING PORTION WITH FIRST AND SECOND FILMS ON RESPECTIVE UNDER FACE AND UPPER FACE SIDES

CANON KABUSHIKI KAISHA, ...

1. A solid-state image pickup device, comprising:an image pickup pixel having a first photoelectric conversion portion and a first transistor for reading out a signal based on a charge generated in the photoelectric conversion portion;
a focus detection pixel having a second photoelectric conversion portion, a second transistor for reading out a signal based on a charge generated in the second photoelectric conversion portion, and a light shielding portion formed in a first wiring layer and having an opening, the second photoelectric conversion portion having a light receiving face that receives light through the opening;
a first film containing titanium and being provided on an under face side of the light shielding portion and not extending through the opening;
a second film containing titanium nitride and being provided on an upper face side of the light shielding portion and not extending through the opening and below a first insulating film, the upper face side being positioned farther apart from the light receiving face than from the under face side;
a third film containing titanium and being provided between the first film and the second photoelectric conversion portion; and
a wiring line for the first transistor and the second transistor provided above the first transistor and the second transistor,
wherein a thickness of the second film is larger than that of the first film in height direction,
wherein the wiring line and a structure having the light shielding portion, the first film, the second film, and the third film are provided in the same layer, and
wherein the second film is formed between the light shielding portion and a second wiring layer above the first wiring layer.

US Pat. No. 10,115,755

SOLID-STATE IMAGE PICKUP DEVICE, IMAGE PICKUP SYSTEM USING SOLID-STATE IMAGE PICKUP DEVICE, AND METHOD OF MANUFACTURING SOLID-STATE IMAGE PICKUP DEVICE

Canon Kabushiki Kaisha, ...

1. A solid-state image pickup device comprising:a plurality of pixels, each of the plurality of pixels including:
a first transfer transistor configured to transfer carriers stored at a first semiconductor region of a first conductive type disposed in a substrate to a second semiconductor region of the first conductive type disposed in the substrate;
a second transfer transistor configured to transfer the carriers held at the second semiconductor region to a third semiconductor region of the first conductive type disposed in the substrate, and
an amplification transistor configured to output a signal based on a potential of the third semiconductor region; and
a metal film
including
a first bottom surface located above an upper surface of a gate electrode of the first transfer transistor,
a second bottom surface located above the first semiconductor region, and
a third bottom surface located above the second semiconductor region,
wherein
with respect to a distance in a direction perpendicular to a surface of the substrate, a first distance between the second bottom surface and the surface of the substrate and a second distance between the third bottom surface and the surface of the substrate are each smaller than a third distance between the upper surface of the gate electrode and the surface of the substrate.

US Pat. No. 10,115,754

IMAGE PICKUP DEVICE AND IMAGE PICKUP SYSTEM

CANON KABUSHIKI KAISHA, ...

1. An image pickup device, comprising:a pixel region including a plurality of pixels;
a well region in which the plurality of pixels are provided;
first and second well wires configured to supply a potential to the well region, the first and second well wires being arranged in the pixel region;
first and second well contacts connected to the well region, the first and second well contacts being connected in the first well wire at a first interval; and
third and fourth well contacts connected to the well region, the third and fourth well contacts being connected in the second well wire at a second interval larger than the first interval,
a number of pixels arranged in the second interval is larger than a number of pixels arranged in the first interval.

US Pat. No. 10,115,753

IMAGE SENSOR INCLUDING PIXELS HAVING PLURAL PHOTOELECTRIC CONVERTERS CONFIGURED TO CONVERT LIGHT OF DIFFERENT WAVELENGTHS AND IMAGING APPARATUS INCLUDING THE SAME

Samsung Electronics Co., ...

1. An image sensor of a multi-layered sensor structure, the image sensor comprising:a plurality of sensing pixels, each of the plurality of sensing pixels including,
a micro lens configured to collect light,
a first photoelectric converter configured to convert the light of a first wavelength band into an electrical signal, and
a second photoelectric converter configured to convert the light of a second wavelength band into the electrical signal, the second photoelectric converter including a first photoelectric conversion device and a second photoelectric conversion device, the first photoelectric conversion device being spaced apart from the second photoelectric conversion device based on an optical axis of the micro lens, wherein the first photoelectric converter includes,
a first color selection layer configured to photoelectrically convert the light of the first wavelength band into the electrical signal, and
a first electrode and a second electrode spaced apart from the optical axis, the first electrode and the second electrode configured to output converted electrical signals.

US Pat. No. 10,115,752

SOLID-STATE IMAGING DEVICE AND ELECTRONIC APPARATUS

Sony Semiconductor Soluti...

1. A solid-state imaging device comprising:a pixel array unit including a plurality of pixels, wherein the plurality of pixels are in a two-dimensionally array in the pixel array unit,
wherein each pixel of the plurality of pixels comprises:
a first photoelectric conversion unit configured to generate a signal charge based on light absorbed of a first color component; and
a second photoelectric conversion unit configured to generate a signal charge that corresponds to an amount of incident light,
wherein the second photoelectric conversion unit comprises a photodiode, and
wherein the plurality of pixels comprise:
a first pixel configured to:
photoelectrically convert light of the first color component with the first photoelectric conversion unit, and
photoelectrically convert light of a third color component with the second photoelectric conversion unit,
wherein the light of the third color component passes through a first color filter and the first photoelectric conversion unit, and
wherein light of a second color component passes through the first color filter;
a second pixel configured to:
photoelectrically convert the light of the first color component with the first photoelectric conversion unit, and
photoelectrically convert light of a fifth color component with the second photoelectric conversion unit,
wherein the light of the fifth color component passes through a second color filter and the first photoelectric conversion unit,
wherein light of a fourth color component passes through the second color filter; and
a third pixel configured to:
photoelectrically convert the light of the first color component with the first photoelectric conversion unit, and
photoelectrically convert light of a sixth color component with the second photoelectric conversion unit,
wherein the light of the sixth color component passes through the first photoelectric conversion unit; and
wherein the first color component and the sixth color component are mixed to generate white (W),
wherein:
 the first color filter and the second color filter are below the first photoelectric conversion unit on a light incident side;
 the first color component is green (G);
 the second color component is red (R);
 the third color component is red (R);
 the fourth color component is blue (B);
 the fifth color component is blue (B); and
 the sixth color component is magenta (Mg).

US Pat. No. 10,115,751

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:a pixel which includes:
first and second active regions each formed in a first main surface of a semiconductor substrate and surrounded by an isolation region in plan view;
a photodiode formed in the first active region; and
a transfer transistor formed in the first active region to transfer charges generated by the photodiode,
wherein, in the semiconductor substrate, a p-type semiconductor region is formed so as to include the first and second active regions in plan view,
wherein, over the p-type semiconductor region in the second active region, a contact portion for supplying a grounding potential is formed and electrically coupled to the p-type semiconductor region,
wherein the photodiode has a first n-type semiconductor region which is formed in the p-type semiconductor region in the first active region,
wherein the transfer transistor has a second n-type semiconductor region which is formed in the p-type semiconductor region in the first active region to function as a drain region of the transfer transistor,
wherein the first n-type semiconductor region functions also as a source region of the transfer transistor, and
wherein, in the second n-type semiconductor region, a gettering element is introduced while, in the p-type semiconductor region in the second active region, the gettering element is not introduced.

US Pat. No. 10,115,750

SENSORS INCLUDING COMPLEMENTARY LATERAL BIPOLAR JUNCTION TRANSISTORS

International Business Ma...

1. A method of fabricating a sensor for detecting radiation comprising:obtaining a substrate including a substrate layer, a semiconductor layer, and an electrically insulating layer between and adjoining the substrate layer and the semiconductor layer;
forming a first lateral bipolar junction transistor having a first polarity on said substrate, the first lateral bipolar junction transistor being configured to generate an output signal indicative of a change in stored charge in the electrically insulating layer resulting from ionizing radiation;
forming a second lateral bipolar junction transistor having a second polarity opposite to the first polarity on said substrate, the second bipolar junction transistor being configured to amplify the output signal of the first bipolar junction transistor, the first and second bipolar junction transistors being formed adjacent to one another on the substrate, and
forming an electrical connection between an output terminal of the first lateral bipolar junction transistor and a base of the second lateral bipolar junction transistor.

US Pat. No. 10,115,749

ARRAY SUBSTRATES AND THE MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method of array substrates, comprising:depositing a conductive layer on a substrate, and forming three poles of at least one thin film transistor (TFT), a first signal line, and a second signal line by etching the conductive layer via a first mask, wherein the first signal line comprises a first portion and a second portion respectively at two sides of the second signal line;
depositing an intermediate layer in sequence, and forming a first connecting bridge connecting the first portion and the second portion by etching the intermediate layer via a second mask; and
depositing a conductive electrode, and forming at least one pixel electrode and a connecting line between the first portion and the second portion by etching the conductive electrode via a third mask.

US Pat. No. 10,115,748

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND MANUFACTURE METHOD OF THIN FILM TRANSISTOR ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A manufacture method of a thin film transistor array substrate, wherein the manufacture method of the thin film transistor array substrate comprises:providing a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located;
forming a gate, and the gate is located on the first surface;
forming a first insulative layer, and the first insulative layer covers on the gate;
forming a metal oxide semiconductor layer on the first insulative layer;
implementing ion implantation to two end regions of the metal oxide semiconductor layer, and the two end regions of the metal oxide semiconductor layer after the ion implantation respectively are a source and a drain, and a region of the metal oxide semiconductor layer without the ion implantation is an active layer;
forming a second insulative layer, and the second insulative layer covers the source, the drain and the active layer;
opening a via employed to expose the source or the drain in the second insulative layer;
forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and is connected with the source or the drain through the via;
wherein the step of opening a via employed to expose the source or the drain in the second insulative layer comprises:
opening a first via and a second via in the second insulative layer, and the first via is located corresponding to the source, and the second via is located corresponding to the drain;
correspondingly, the step of forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and is connected with the source or the drain through the via comprises:
forming a pixel electrode, and the pixel electrode is located on the second insulative layer, and the pixel electrode is connected with the drain through the second via;
the manufacture method of the thin film transistor array substrate further comprises:
forming a first electrode, and the first electrode is connected with the source through the first via;
wherein the step of opening a first via and a second via in the second insulative layer, and the first via is located corresponding to the source, and the second via is located corresponding to the drain comprises:
covering the second insulative layer with a second photoresist layer;
patterning the second photoresist layer to remove the second photoresist layer correspondingly right above the source and the drain to expose a portion of the second photoresist layer;
employing the patterned second photoresist layer as a mask to etch the second photoresist layer to open the first via and the second via in the second insulative layer;
stripping the second photoresist layer; and
wherein the pixel electrode and the first electrode are manufactured in the same process:
forming a transparent conductive layer, and the transparent conductive layer covers the second insulative layer, the source and the drain;
patterning the transparent conductive layer to preserve the transparent conductive layer located on the source and the drain, and a transparent conductive layer connected with the transparent conductive layer located on the drain, wherein the transparent conductive layer located on the source is the first electrode, and the transparent conductive layer located on the drain is the pixel electrode.

US Pat. No. 10,115,747

METHOD OF PRODUCING COMPONENT BOARD

SHARP KABUSHIKI KAISHA, ...

1. A method of producing a component board comprising:a separation film forming process for forming a separation film on a supporting substrate;
a component support forming process for forming a component support for forming a component support on the separation film;
a thin film component forming process for forming a thin film component on the component support;
a light applying process for applying light to the separation film for accelerating a removal of the component support;
a determining process for determining whether a degree of adhesion between the separation film and the component support is high or low based on image data obtained through capturing of an image of the separation film; and
a removing process for removing the component support from the supporting substrate if the degree of adhesion is determined low in the determining process.

US Pat. No. 10,115,746

MANUFACTURING METHOD FOR ACTIVE MATRIX SUBSTRATE, ACTIVE MATRIX SUBSTRATE AND DISPLAY APPARATUS

Sakai Display Products Co...

1. A method of manufacturing an active matrix substrate, the method comprising:forming, on a base substrate, a gate wiring and a source wiring which crosses the gate wiring above the gate wiring;
forming a thin film transistor near a region where the gate wiring and the source wiring face each other;
forming an interlayer dielectric film containing a spin-on-glass (SOG) material having photosensitivity in at least an area between the gate wiring and the source wiring in the region;
forming a hole in the interlayer dielectric film at a position overlapping only one of two outer edges along the longitudinal direction of the gate wiring formed on the base substrate so that a boundary viewed from above between the base substrate and the gate wiring is visually recognized through the hole; and
forming a semiconductor film after the interlayer dielectric film is formed,
wherein the method further comprises:
viewing the position of the boundary through the hole;
forming a film after the interlayer dielectric film is formed while adjusting a position of the film formed after the interlayer dielectric film based on the position of the boundary viewed through the hole.

US Pat. No. 10,115,745

TFT ARRAY SUBSTRATE AND METHOD OF FORMING THE SAME

Shenzhen China Star Optoe...

1. A method of forming a thin-film transistor (TFT) array substrate, comprising:forming a semi-conductor layer on a substrate, wherein the semi-conductor layer is a single continuous layer of a semi-conductor material formed on the substrate;
forming a gate insulating layer on the semi-conductor layer, such that the gate insulating layer covers a first part of the semi-conductor layer with a second part of the semi-conductor layer being exposed as being not covered by the gate insulating layer, wherein the first part and the second part are both integral parts of the semi-conductor layer and adjoin each other;
forming a gate electrode on the gate insulating layer;
forming an ILD layer on the semi-conductor layer so as to cover the gate insulating layer and the gate electrode, wherein the ILD layer comprises a SiNx layer that is in direct contact with the second part of the semi-conductor layer;
annealing the ILD layer so that hydrogen in the ILD layer is diffused into the second part of the semi-conductor layer to form a pixel electrode with the second part of the semi-conductor layer that is not covered by the gate insulating layer;
forming contact holes in the ILD layer and the gate insulating layer so as to expose spaced portions of the first part of the semi-conductor layer, and forming an opening in the ILD layer so as to expose a portion of the pixel electrode; and
forming a source electrode and a drain electrode on the ILD layer, wherein the source electrode electrically connects the semi-conductor layer through a first one of the contact holes, and the drain electrode electrically connects the semi-conductor layer and pixel electrode through a second one of the contact holes and the opening, respectively;
wherein the second part of the semi-conductor layer that is diffused with hydrogen of the ILD layer is an integral part of the semi-conductor layer and is in direct contact and connection with the first part of the semi-conductor layer so that the pixel electrode is directly connected to the first part of the semi-conductor layer that is not diffused with hydrogen.

US Pat. No. 10,115,744

ARRAY SUBSTRATE AND FABRICATION METHOD, DISPLAY PANEL, AND DISPLAY DEVICE

Shanghai Tianma AM-OLED C...

1. An array substrate, comprising: a substrate; a first functional layer configured on one side of the substrate; a first insulating layer configured on the first functional layer facing away from the substrate; a second functional layer configured on the first insulating layer facing away from the substrate; a second insulating layer configured on the second functional layer facing away from the substrate; a third functional layer configured on the second insulating layer facing away from the substrate; a third insulating layer configured on the third functional layer facing away from the substrate; a fourth functional layer configured on the third insulating layer facing away from the substrate; a plurality of through-holes configured to electrically connect different functional layers, wherein a depth of any through-holes does not exceed the thickness of two adjacent insulating layers; and a plurality of pixel driving circuits, wherein a pixel driving circuit comprises a first transistor, wherein a semiconductor layer of the first transistor is located in the first functional layer, a gate electrode of the first transistor is located in the second functional layer, and a source electrode and a drain electrode of the first transistor are both located in the fourth functional layer.

US Pat. No. 10,115,743

ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first transistor;
a second transistor comprising an oxide semiconductor layer including a channel region;
a third transistor;
an insulating layer including an opening over the first transistor, the second transistor, and the third transistor;
a color filter over the insulating layer;
a light-emitting element including a first electrode over the color filter; and
a capacitor;
a signal line; and
a power supply line;
wherein one of a source and a drain of the first transistor is directly connected to the signal line,
wherein the other one of the source and the drain of the first transistor is directly connected to a gate of the second transistor and one terminal of the capacitor,
wherein the other one terminal of the capacitor is directly connected to one of the source and the drain of the second transistor, one of a source and a drain of the third transistor, and the light-emitting element,
wherein the other one of the source and the drain of the second transistor is directly connected to the power supply line,
wherein the opening does not overlap with the color filter and an edge portion of the opening does not align with an edge portion of the color filter,
wherein the oxide semiconductor layer comprises In, Ga, and Zn, and
wherein the first electrode is directly connected to the one of the source and the drain of the second transistor through the opening.

US Pat. No. 10,115,742

SEMICONDUCTOR DEVICE AND DISPLAY DEVICE INCLUDING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A transistor comprising:a first gate electrode;
an oxide semiconductor film, the oxide semiconductor film including a drain region;
a second gate electrode;
an insulating film over the oxide semiconductor film, the insulating film including an opening; and
a drain electrode over the insulating film, the drain electrode being in contact with the drain region in the opening,
wherein the first gate electrode and the second gate electrode are electrically connected to each other,
wherein, under a first condition, a difference between a minimum value and a maximum value of field-effect mobility of the transistor is less than or equal to 15 cm2/Vs, and
wherein the first condition is that voltages applied to the first gate electrode and the second gate electrode are in a range from 3 V to 10 V and a voltage applied to the drain region of the oxide semiconductor film is 20 V.

US Pat. No. 10,115,741

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:a first circuit comprising a first transistor and a capacitor electrically connected to a drain of the first transistor; and
a second circuit comprising a second transistor and a node electrically connected to a gate of the second transistor,
wherein:
the first transistor comprises a first semiconductor layer and a first back gate,
the second transistor comprises a second semiconductor layer,
the first circuit is configured to write data by turning on the first transistor, and to retain the data in the capacitor by turning off the first transistor,
the second circuit is configured to supply a potential at which the first transistor is turned off to the first back gate by turning on the second transistor, and to retain the potential in the node by turning off the second transistor, and
a threshold voltage of the second transistor is higher than a threshold voltage of the first transistor when a potential of the first back gate is set to the same as a potential of a source or a gate of the first transistor.

US Pat. No. 10,115,740

SEMICONDUCTOR DEVICE

Japan Display Inc., Mina...

1. A semiconductor device comprising:an insulating substrate;
a first semiconductor layer formed of silicon and positioned above the insulating substrate;
a second semiconductor layer formed of a metal oxide and positioned above the first semiconductor layer;
a first insulating film formed of a silicon nitride and positioned between the first semiconductor layer and the second semiconductor layer;
a second insulating film formed of a silicon oxide and positioned between the first insulating film and the second semiconductor layer;
a first gate electrode opposed to an upper surface of the first semiconductor layer;
a second gate electrode opposed to an upper surface of the second semiconductor layer;
an interlayer insulating film formed of a silicon oxide and positioned between the second semiconductor layer and the second gate electrode; and
a block layer between the first insulating film and the second semiconductor layer, the block layer having lower hydrogen diffusion than hydrogen diffusion of the first insulating film, wherein
the block layer continuously extends to a position opposed to the first semiconductor layer and a position opposed to the second semiconductor layer.

US Pat. No. 10,115,739

DISPLAY UNIT AND ELECTRONIC APPARATUS

Sony Corporation, Tokyo ...

1. A display unit, comprising:a plurality of pixel circuits each including a light-emitting element, a drive transistor that has a drain and a source and supplies a current to the light-emitting element, and a control transistor connected to the drain or the source of the drive transistor,
wherein one channel portion is formed for two control transistors in respective adjacent two of the pixel circuits.

US Pat. No. 10,115,738

SELF-ALIGNED BACK-PLANE AND WELL CONTACTS FOR FULLY DEPLETED SILICON ON INSULATOR DEVICE

GLOBALFOUNDRIES INC., Gr...

1. A structure comprising:a back-plane, a p-well and an n-well formed within a bulk substrate;
a contact extending from each of the back-plane, the p-well and the n-well;
a gate structure formed above the back-plane, the p-well and the n-well;
at least one deep trench isolation (DTI) structure extending through the back-plane and the p-well and into the n-well; and
an insulating spacer isolating the contact of the back-plane from the gate structure and the at least one DTI structure.

US Pat. No. 10,115,737

CHARGE STORAGE REGION IN NON-VOLATILE MEMORY

SanDisk Technologies LLC,...

1. A memory cell, comprising:a semiconductor channel;
a tunnel dielectric;
a charge storage region comprising: a first p-type silicon region adjacent the tunnel dielectric, a second p-type silicon region, an n-type silicon region between the first and second p-type silicon regions, a first dielectric region between the first p-type silicon region and the n-type silicon region, a second dielectric region between the n-type silicon region and the second p-type silicon region;
a conductive control gate; and
a control gate dielectric between the control gate and the charge storage region, the charge storage region being between the tunnel dielectric and the control gate dielectric, the second p-type silicon region being adjacent to the control gate dielectric.

US Pat. No. 10,115,736

METHODS AND APPARATUS FOR THREE-DIMENSIONAL NAND NON-VOLATILE MEMORY DEVICES WITH SIDE SOURCE LINE AND MECHANICAL SUPPORT

SanDisk Technologies LLC,...

1. A method of fabricating a monolithic three dimensional memory structure, the method comprising:forming a stack of alternating word line and dielectric layers above a substrate;
forming a source line above the substrate;
forming a memory hole extending through the alternating word line and dielectric layers and the source line; and
forming a mechanical support element on the substrate adjacent to the memory hole, the mechanical support element extending through the source line.

US Pat. No. 10,115,735

SEMICONDUCTOR DEVICE CONTAINING MULTILAYER TITANIUM NITRIDE DIFFUSION BARRIER AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A semiconductor device, comprising:a silicon surface;
a titanium silicide layer contacting the silicon surface;
a first titanium nitride layer located over the titanium silicide layer;
a titanium oxynitride layer contacting the first titanium nitride layer;
a second titanium nitride layer contacting the titanium oxynitride layer; and
a metallic fill material portion located over the second titanium nitride layer.

US Pat. No. 10,115,734

SEMICONDUCTOR DEVICE INCLUDING INTERLAYER SUPPORT PATTERNS ON A SUBSTRATE

Samsung Electronics Co., ...

1. A semiconductor device comprising:a stack of interlayer support patterns on a substrate;
a stack of horizontal conductive patterns on the substrate and disposed laterally of the stack of interlayer support patterns;
an interlayer insulating layer interposed between vertically adjacent ones of the interlayer support patterns in the stack of interlayer support patterns, extending between vertically adjacent ones of the horizontal conductive patterns in the stack of horizontal conductive patterns, and disposed parallel to a surface of the substrate, the interlayer insulating layer being in contact with the vertically adjacent ones of the interlayer support patterns;
a conductive structure extending in a direction perpendicular to said surface of the substrate;
first vertical structures each extending vertically through the vertically adjacent ones of the horizontal conductive patterns and the interlayer insulating layer extending between the vertically adjacent ones of the horizontal conductive patterns; and
second vertical structures each extending vertically through the vertically adjacent ones of the interlayer support patterns and the interlayer insulating layer extending between the vertically adjacent ones of the interlayer support patterns,
wherein each of the first vertical structures and each of the second vertical structures includes a channel semiconductor layer extending in a direction perpendicular to the substrate.

US Pat. No. 10,115,733

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:a connecting member having a through hole;
a first insulating film provided on the connecting member;
a stacked body provided on the first insulating film, the stacked body including electrode films and second insulating films, each of the electrode films and each of the second insulating films being alternately stacked;
a semiconductor pillar extending in a stacking direction of the electrode films and the second insulating films, piercing through the stacked body and the first insulating film, the semiconductor pillar being electrically connected to the connecting member;
a third insulating film provided between the semiconductor pillar and the stacked body; and
a support portion disposed in the through-hole of the connecting member.

US Pat. No. 10,115,732

THREE DIMENSIONAL MEMORY DEVICE CONTAINING DISCRETE SILICON NITRIDE CHARGE STORAGE REGIONS

SANDISK TECHNOLOGIES LLC,...

1. A structure comprising:an alternating stack of insulating layers and electrically conductive layers located over a substrate; and
a memory stack structure extending through a memory opening in the alternating stack and comprising memory elements laterally surrounding a vertical semiconductor channel, wherein:
each of the memory elements comprise, from outside to inside, a blocking dielectric portion that is a region of a continuous blocking dielectric layer, a charge trapping material portion having a vertical sidewall portion and comprising silicon nitride, and a tunneling dielectric portion that is a region of a continuous tunneling dielectric layer directly contacting the continuous blocking dielectric layer, wherein a continuous interface between the continuous blocking dielectric layer and the alternating stack vertically extends through multiple electrically conductive layers of the alternating stack, and a continuous interface between the continuous tunneling dielectric layer and the vertical semiconductor channel vertically extends through the multiple electrically conductive layers of the alternating stack;
each of the insulating layers includes an upper recessed annular rim, a lower recessed annular rim, and an annular center portion located between the upper and lower recessed annular rims, wherein the annular center portion protrudes inward toward a vertical axis of the memory opening relative to the upper and lower recessed rims; and
each of the charge trapping material portions is vertically spaced from one another, and does not contact any other of the charge trapping material portions.

US Pat. No. 10,115,731

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:an interconnect layer including a conductive layer and a semiconductor layer of a first conductivity type provided on the conductive layer;
a stacked body including a plurality of electrode layers stacked on the interconnect layer,
a semiconductor pillar provided in the stacked body and extending through the plurality of electrode layers in a stacking direction thereof; and
an insulating layer provided on the interconnect layer and extending along a lateral surface of the stacked body,
the semiconductor layer including a first semiconductor region of a second conductivity type positioned between the insulating layer and the conductive layer, and the first semiconductor region being in contact with the conductive layer.

US Pat. No. 10,115,730

THREE-DIMENSIONAL MEMORY DEVICE CONTAINING STRUCTURALLY REINFORCED PEDESTAL CHANNEL PORTIONS AND METHOD OF MAKING THEREOF

SANDISK TECHNOLOGIES LLC,...

1. A three-dimensional memory device comprising:an alternating stack of insulating layers and electrically conductive layers located over a semiconductor surface;
a memory opening extending through the alternating stack;
a pedestal channel portion located at a bottom portion of the memory opening, comprising a semiconductor material, and contacting a top surface of the semiconductor surface; and
a memory stack structure located in the memory opening and contacting a top surface of the pedestal channel portion, wherein the memory stack structure comprises a memory film and a vertical semiconductor channel located inside the memory film,
wherein:
a maximum lateral extent of the pedestal channel portion is greater than a maximum lateral dimension of an entire interface between the pedestal channel portion and the memory stack structure, the entire interface includes all surfaces at which the pedestal channel portion directly contacts the memory stack structure; and
the maximum lateral extent of the pedestal channel portion is provided above a horizontal plane including a top surface of the bottommost electrically conductive layer among the electrically conductive layers or below a horizontal plane including a bottom surface of a bottommost electrically conductive layer.

US Pat. No. 10,115,729

ANTI-FUSE NONVOLATILE MEMORY DEVICES EMPLOYING LATERAL BIPOLAR JUNCTION TRANSISTORS AS SELECTION TRANSISTORS

SK Hynix Inc., Gyeonggi-...

1. An anti-fuse nonvolatile memory device comprising:an anti-fuse memory cell; and
a select transistor having a structure of bipolar junction transistor,
wherein the structure of bipolar junction transistor comprises;
a well region of a first conductivity type acting as a base region, the well region having first, second and third upper portions, the third upper portion of the well region being spaced apart from the second upper portion of the well region;
a first collector region of a second conductivity type disposed in the second upper portion of the well region, wherein an end of the second upper portion of the well region overlaps with an end of the first upper portion of the well region in a first direction;
an emitter region of the second conductivity type disposed in the third upper portion of the well region; and
a contact region of the first conductivity type disposed in the well region,
wherein the anti-fuse memory cell includes an anti-fuse insulation layer on a first upper portion of the well region and a gate stacked on the anti-fuse insulation layer; and
wherein the gate is coupled to a word line, the contact region is coupled to a well bias line, the emitter region is coupled to a bit line, and the first collector region is electrically floated.

US Pat. No. 10,115,728

LASER SPIKE ANNEALING FOR SOLID PHASE EPITAXY AND LOW CONTACT RESISTANCE IN AN SRAM WITH A SHARED PFET AND NFET TRENCH

INTERNATIONAL BUSINESS MA...

1. A method for fabricating a semiconductor device, the method comprising:forming a first semiconductor fin opposite a surface of a substrate;
forming a second semiconductor fin opposite the surface of the substrate and adjacent to the first semiconductor fin;
prior to forming a replacement metal gate (RMG), forming a first doped region over portions of the first semiconductor fin and a second doped region over portions of the second semiconductor fin;
forming a dielectric layer over the first and second doped regions;
after forming the RMG, forming a shared trench in the dielectric layer exposing portions of the first and second doped regions;
concurrently amorphizing the exposed first and second doped regions; and
concurrently recrystallizing the amorphized first and second doped regions.

US Pat. No. 10,115,727

METHOD FOR MANUFACTURING A MICROELECTRONIC CIRCUIT AND CORRESPONDING MICROELECTRONIC CIRCUIT

Fraunhofer-Gesellschaft z...

1. A method for manufacturing a microelectronic circuit, comprising:providing a substrate,
producing a source contact, a bulk contact and a drain contact each for a transistor and for a memory transistor,
producing, in a common step, an insulating layer of the transistor and an insulating layer of the memory transistor,
producing, in a common step, a metal layer of the transistor and a metal layer of the memory transistor,
producing the metal layer and the insulating layer of the memory transistor as parts of a MOS capacitor,
producing at least one capacitor as part of the memory transistor,
producing a gate contact connected to the metal layer of the transistor, and
producing a gate contact connected to a metal layer of the capacitor of the memory transistor.

US Pat. No. 10,115,726

METHOD AND SYSTEM FOR FORMING MEMORY FIN PATTERNS

Tokyo Electron Limited, ...

1. A method for patterning a substrate, the method comprising:forming a multi-line layer above a memorization layer on a substrate, the multi-line layer including a region having a pattern of alternating lines of three materials that differ chemically from each other by having different etch resistivities relative to each other, the three materials include material A, material B, and material C, the pattern of alternating lines of three materials includes a repeating sequence of A-B-C-B-A-B-C-B in that materials alternate in a direction parallel to a working surface of the substrate, each line of material extending from a top surface of the multi-line layer to a bottom surface of the multi-line layer;
forming a first etch mask above the multi-line layer, the first etch mask defining first trenches that uncover a first portion of the multi-line layer such that defined first trenches elevationally intersect multiple lines from the pattern of alternating lines;
etching through uncovered portions of material A and portions of the memorization layer directly underneath the uncovered portions of material A using the first etch mask;
forming a second etch mask above the multi-line layer, the second etch mask defining second trenches that uncover a second portion of the multi-line layer such that defined second trenches elevationally intersect multiple lines from the pattern of alternating lines;
etching through uncovered portions of material C and portions of the memorization layer directly underneath the uncovered portions of material C using the second etch mask; and
etching through material B and portions of the memorization layer directly underneath material B while the multi-line layer is uncovered.

US Pat. No. 10,115,725

STRUCTURE AND METHOD FOR HARD MASK REMOVAL ON AN SOI SUBSTRATE WITHOUT USING CMP PROCESS

International Business Ma...

1. A device, comprising:a semiconductor-on-insulator (SOI) substrate having an SOI layer, a BOX layer and a substrate layer;
a pad nitride layer deposited on a top surface of the SOI layer;
a trench formed in the SOI substrate, wherein the trench extends into the substrate layer;
a node dielectric layer deposited on a bottom and sidewalls of the first trench;
a liner layer deposited on the node dielectric layer;
a first conductive material deposited in the trench, wherein a top surface of the first conductive material is below a bottom surface of the SOI layer and above a top surface of the substrate layer, wherein a top surface of the node dielectric layer and a top surface of the liner layer are coplanar with the top surface of the first conductive material; and
a second conductive material deposited on the top surface of the first conductive material, wherein a top surface of the second conductive material is below the top surface of the SOI layer and below a bottom surface of the pad nitride layer.

US Pat. No. 10,115,724

DOUBLE DIFFUSION BREAK GATE STRUCTURE WITHOUT VESTIGIAL ANTENNA CAPACITANCE

International Business Ma...

1. A semiconductor structure comprising:a double diffusion break region located between a first device region and a second device region, wherein the double diffusion break region includes a sacrificial gate material and wherein an interlevel dielectric material is present adjacent to each side of the sacrificial gate material and beneath at least a portion of the sacrificial gate material.

US Pat. No. 10,115,723

COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) DEVICES EMPLOYING PLASMA-DOPED SOURCE/DRAIN STRUCTURES AND RELATED METHODS

QUALCOMM Incorporated, S...

1. A complementary metal oxide semiconductor (CMOS) device, comprising:a substrate;
a semiconductor material structure disposed above the substrate, the semiconductor material structure comprising one or more channel structures, each channel structure comprising:
a semiconductor material having a first end portion and a second end portion;
a source in the first end portion, the source comprising a first plasma-doped portion comprising a dopant above a solid state solubility of the semiconductor material structure of the semiconductor material at the first end portion;
a drain in the second end portion of the semiconductor material, the drain comprising a second plasma-doped portion comprising a dopant above the solid state solubility of the semiconductor material structure of the semiconductor material at the second end portion; and
a channel disposed between the source and the drain; and
a gate material disposed adjacent to the channel.

US Pat. No. 10,115,722

SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor device, comprising:a substrate including a plurality of logic cells disposed along a first direction;
active patterns protruding from the substrate; and
a device isolation layer on the substrate, the device isolation layer including a first double diffusion break region that has a first width, as measured along the first direction, and is disposed between a pair of adjacent logic cells and a second double diffusion break region that has a second width, as measured along the first direction, greater than the first width and is disposed between another pair of adjacent logic cells,
wherein the active patterns comprise:
a plurality of pairs of first active patterns spaced apart from each other along the first direction with the first double diffusion break region interposed therebetween; and
a plurality of pairs of second active patterns spaced apart from each other along the first direction with the second double diffusion break region interposed therebetween,
wherein the first active patterns comprise first end portions that are adjacent to a side of the first double diffusion break region and are aligned along a second direction crossing the first direction, and
wherein the second active patterns comprise second end portions that are adjacent to a side of the second double diffusion break region, and wherein one of the second end portions is offset from another of the second end portions along the first direction.

US Pat. No. 10,115,721

PLANAR DEVICE ON FIN-BASED TRANSISTOR ARCHITECTURE

INTEL CORPORATION, Santa...

1. An integrated circuit comprising:a semiconductor substrate having a plurality of fins extending from a surface thereof;
a semiconductor body over a first sub-set of the plurality of fins and having a planar surface, wherein the semiconductor body merges the first sub-set of fins; and
a first planar transistor having a gate body over the planar surface of the semiconductor body.

US Pat. No. 10,115,720

INTEGRATED SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Magnachip Semiconductor, ...

10. A manufacturing method for a semiconductor device, the method comprising:providing a substrate comprising a first region and a second region;
forming a thick gate insulating layer on the first region;
forming a gate electrode on the thick gate insulating layer;
performing a wet etching process on the thick gate insulating layer disposed outside the gate electrode such that a thin buffer insulating layer is formed adjacent to the thick gate insulating layer, located outside of the gate electrode;
performing a sidewall oxidation of the gate electrode:
forming an LDD region in the substrate; and
forming a first spacer on the thin buffer insulating layer.

US Pat. No. 10,115,719

INTEGRATED CIRCUITS WITH RESISTOR STRUCTURES FORMED FROM MIM CAPACITOR MATERIAL AND METHODS FOR FABRICATING SAME

GLOBALFOUNDRIES, Inc., G...

1. A method for fabricating an integrated circuit, the method comprising:providing a semiconductor substrate with a resistor area and a capacitor area;
depositing a conductive capacitor material over the resistor area and the capacitor area of the semiconductor substrate;
forming a resistor structure from the conductive capacitor material in the resistor area;
forming electrical connections to the resistor structure in the resistor area; and
forming a resistor shield around the resistor structure in the resistor area, wherein the resistor shield includes a first shield portion and a second shield portion, and wherein the resistor structure is located directly between the first shield portion and the second shield portion.

US Pat. No. 10,115,718

METHOD, APPARATUS, AND SYSTEM FOR METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

GLOBALFOUNDRIES INC., Gr...

1. A semiconductor device, comprising:a semiconductor substrate;
a field-effect transistor (FET) comprising a gate disposed on the semiconductor substrate, a source disposed on or in the semiconductor substrate, and a drain disposed on or in the semiconductor substrate, wherein the gate, the source, and the drain extend parallel to each other in a first horizontal direction;
at least one source electrostatic discharge (ESD) protection circuit comprising a source contact disposed on the source at a first location, and a first source ballasting resistor, wherein said source ballasting resistor comprises a first source conductive element disposed on the source contact and extending in a second horizontal direction perpendicular to the first horizontal direction between a position above the first location and a position above a second location, wherein the second location is on the drain;
a source terminal disposed above and in electrical contact with the first source ballasting resistor, wherein the source terminal extends in the first direction;
at least one drain ESD protection circuit comprising a first drain ballasting resistor; and
a drain terminal disposed above and in electrical contact with the first drain ballasting resistor, wherein the drain terminal extends in the first horizontal direction.

US Pat. No. 10,115,717

ELECTROSTATIC DISCHARGE PROTECTION STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. An electrostatic discharge (ESD) protection structure, comprising:a substrate having a first region and a second region, wherein the first region and the second region are separated by a preset distance;
a well area formed in the substrate, wherein the well area covers the first region, the second region, and a region between the first region and the second region;
a first fin portion formed in the substrate in the first region and a second fin portion formed in the substrate in the second region, wherein the first fin portion has first-type doping ions and the second fin portion has second-type doping ions;
a dielectric layer, wherein the dielectric layer covers the well area between the first region and the second region, the first fin portion, and the second fin portion;
a supporting gate structure formed in the dielectric layer, wherein the supporting gate structure includes a first supporting gate crossing the first fin portion and covering portions of top and side surfaces of the first fin portion, and a second supporting gate crossing the second fin portion and covering portions of top and side surfaces of the second fin portion;
a conductive structure formed in the dielectric layer, wherein the conductive structure includes a first conductive structure connecting to the first fin portion and being configured to connect to a first bias voltage, and a second conductive structure connecting to the second fin portion and being configured to connect to a second bias voltage, and the first bias voltage and the second bias voltage are not equal to one another;
a first conductive layer formed on the dielectric layer and a top surface of the first supporting gate; and
a second conductive layer formed on the dielectric layer and a top surface of the second supporting gate.

US Pat. No. 10,115,716

DIE BONDING TO A BOARD

SEMICONDUCTOR COMPONENTS ...

1. A method of bonding a plurality of die having a plurality of metal layers on a die surface to a board or metal lead frame, comprising:placing a first die onto a solderable surface of the board or the metal lead frame, the first die comprising at least three metal layers, the board comprising one of a ceramic board or substrate board, or a metal lead frame wherein a top metal die layer is disposed against the solderable surface of the first die;
first reflowing at least one of first and second metal die layers of the first die at a first reflow temperature in a range of 220 degrees C. to 260 degrees C. for a first period to form a first alloy to create a bond between the first die and the board or metal lead frame; and
maintaining heat at the first reflow temperature for a second period to reflow the board or metal lead frame and the first and second metal die layers to form a second alloy
placing a second die onto the solderable surface of the board or the metal lead frame, the second die comprising at least three metal layers, wherein a top metal die layer is disposed against the solderable surface of the second die;
second reflowing at least one of first and second metal die layers of the second die at the first reflow temperature in the range of 220 degrees C. to 260 degrees C. for the first period to form the first alloy to create a bond between the second die and the board or metal lead frame; and
maintaining heat at the first reflow temperature for the second period to reflow the board or metal lead frame and the first and second metal die layers of the second die to form the second alloy,
wherein the first and second alloys have melting temperature temperatures that are higher than 260 degrees C.

US Pat. No. 10,115,715

METHODS OF MAKING SEMICONDUCTOR DEVICE PACKAGES AND RELATED SEMICONDUCTOR DEVICE PACKAGES

Micron Technology, Inc., ...

1. A method of fabricating a semiconductor device package, comprising:providing a fan out wafer comprising semiconductor-device-package locations at a base level, each semiconductor-device-package location comprising:
at least two mutually spaced semiconductor dice and a dielectric material laterally surrounding each of the at least two mutually spaced semiconductor dice and extending between adjacent semiconductor-device-package locations; and
electrically conductive traces extending over active surfaces of the at least two semiconductor dice and laterally beyond peripheries of the at least two semiconductor dice over the dielectric material to locations of electrically conductive vias extending from the electrically conductive traces through the dielectric material;
stacking laterally offset semiconductor dice on at least some semiconductor-device-package locations of the fan out wafer to expose bond pads at a lateral periphery of each of the laterally offset semiconductor dice;
electrically connecting the laterally offset semiconductor dice to one another and associated electrically conductive traces of the at least some semiconductor-device-package locations by forming wire bonds extending from a respective bond pad of an overlying semiconductor die of the laterally offset semiconductor dice to an adjacent bond pad of an underlying semiconductor die of the laterally offset semiconductor dice and by forming a wire bond extending from a respective bond pad of a lowest semiconductor die of the laterally offset semiconductor dice to an adjacent via of the electrically conductive vias or to an adjacent trace of the electrically conductive traces; and
singulating the semiconductor-device-package locations having stacks of semiconductor dice thereon from the fan out wafer.

US Pat. No. 10,115,714

SEMICONDUCTOR DEVICE AND OPTICAL COUPLING DEVICE

Kabushiki Kaisha Toshiba,...

1. A semiconductor device, comprising:a substrate having a first surface side and a second surface side opposite the first surface side, the first surface side including a first surface region at a first end of the substrate in a first direction and a second surface region on a second end of the substrate in the first direction opposite the first end;
a wiring pattern on the second surface side of the substrate;
a first terminal and a second terminal on the substrate in the first surface region;
a third terminal and a fourth terminal on the substrate in the second surface region;
a first semiconductor element having a first surface, the first semiconductor element being bonded to the substrate on the first surface side between the first and second surface regions;
a second semiconductor element having a lower surface bonded to the first surface of the first semiconductor element;
a first bonding wire connecting the first terminal and anode terminal of the second semiconductor element;
a second bonding wire connecting the second terminal and a cathode terminal of the second semiconductor element;
a third semiconductor element bonded to the substrate on the first surface side between the first semiconductor element and the second surface region;
a third bonding wire connecting the first semiconductor element and the third semiconductor element, the third bonding wire being connected to a pad on the first surface of the first semiconductor element;
a silicone gel covering an upper surface of the second semiconductor element and contacting a portion of the first surface of the first semiconductor device; and
a resin portion covering the silicone gel, the first semiconductor element, the third semiconductor element, the first bonding wire, the second bonding wire, the third bonding wire, the first surface region, and the second surface region, wherein
the resin portion has a durometer-measured hardness greater than a durometer-measured hardness of the silicone gel,
the first semiconductor element includes a light receiving element facing the first surface of the first semiconductor element,
the second semiconductor element includes a light emitting element that emits light at the lower surface of the second semiconductor element, and
the silicone gel is opaque at a wavelength of light emitted by the light emitting element.

US Pat. No. 10,115,713

OPTOELECTRONIC ASSEMBLY AND METHOD OF OPERATING AN OPTOELECTRONIC ASSEMBLY

OSRAM Opto Semiconductors...

1. An optoelectronic assembly comprising:a semiconductor chip comprising:at least one first component that emits a first electromagnetic radiation;
a first photosensitive component that controls the first component electrically connected in parallel with the first component and comprises a first radiation-sensitive region arranged in a beam path of the first electromagnetic radiation, wherein the first photosensitive component connected in parallel with the first component is an automatic control of the first component such that the photosensitive component connected in parallel with the first component results in the automatic control without needing to provide an associated open loop control, and the first component and the first photosensitive component are integrated into the semiconductor chip;
a first carrier on which the first component and the first photosensitive component are arranged, wherein on the first carrier a first contact region is configured, a second contact region electrically insulated from the first contact region is configured on the first carrier, the first component comprises a carrier layer and a functional layer deposited on the carrier layer, the carrier layer is configured in an electrically conductive manner, the first photosensitive component is arranged on the first component, a first electrical contact of the first component and a first electrical contact of the first photosensitive component are electrically coupled by a first contact pad, the first contact pad is electrically coupled to the first contact region by a first bond wire, a second electrical contact of the first component is arranged at a bottom side of the first component and is electrically and physically coupled to the second contact region, a second electrical contact of the first photosensitive component is physically connected to the electrically conductive carrier layer of the first component and is electrically coupled to the second contact region, and between the first component and the first photosensitive component and between the first contact pad and the carrier layer, an insulator is formed; and
at least a second component that emits a second electromagnetic radiation and comprises a second photosensitive component electrically connected in parallel with the second component and a second radiation-sensitive region, wherein the second radiation-sensitive region is arranged in the beam path of the second electromagnetic radiation, the second radiation-sensitive region of the second photosensitive component is arranged in the beam path of the first electromagnetic radiation, a second beam filter is arranged in the beam path between the first component and the second photosensitive component, the second beam filter blocking the first electromagnetic radiation, and the second photosensitive component is coated with a beam-filter material of the second beam filter, and
wherein the first radiation-sensitive region of the first photosensitive component is arranged outside of a beam path of the second electromagnetic radiation.

US Pat. No. 10,115,712

ELECTRONIC MODULE

Siliconware Precision Ind...

1. An electronic module, comprising:a first package having an encapsulant and an electronic element embedded in the encapsulant, wherein the encapsulant has opposite first and second surfaces, wherein a first circuit structure has a dielectric layer formed on the first surface of the encapsulant and at least a circuit layer formed on the dielectric layer for electrically connecting the electronic element; and
a second package disposed on the first circuit structure formed on the first surface of the encapsulant through a plurality of conductive elements, wherein the second package has an insulating layer having opposite third and fourth surfaces and an antenna structure formed on the third surface of the insulating layer and extending through the insulating layer, the insulating layer being bonded to the first surface of the encapsulant via the fourth surface thereof and the antenna structure being electrically connected to the circuit layer and the electronic element, wherein a metal layer is formed on the fourth surface of the insulating layer and electrically connected to the antenna structure and at least one of the conductive elements, and wherein the metal layer is free from being in contact with the first circuit structure.

US Pat. No. 10,115,711

VERTICAL LIGHT EMITTING DIODE WITH MAGNETIC BACK CONTACT

International Business Ma...

1. A structure comprising:an opening located in a display substrate;
a first contact structure lining at least one sidewall of the opening and a bottom wall of the opening and present on a topmost surface of the display substrate;
a first magnetic material located on a portion of the first contact structure that is located on the bottom wall of the opening;
a second magnetic material located on a surface of the first magnetic material;
a vertical light emitting diode located on a surface of the second magnetic material and having a topmost surface that is located entirely below a topmost surface of the first contact structure that is located on the topmost surface of the display substrate; and
a pair of second contact structures, wherein one of the pair of second contact structures is in direct contact with a topmost surface of the vertical light emitting diode, and another of the pair of second contact structures is in direct contact with a surface of the first contact structure.

US Pat. No. 10,115,710

PACKAGE INCLUDING A PLURALITY OF STACKED SEMICONDUCTOR DEVICES, AN INTERPOSER AND INTERFACE CONNECTIONS

1. A package, comprising:a first dynamic random access memory (DRAM) semiconductor device, a second DRAM semiconductor device, and a third DRAM semiconductor device stacked in a first direction above a first surface of an interposer;
a first wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and a second surface, opposite the first surface, of the interposer;
a first external connection formed on the second surface of the interposer, the first wiring electrically connected at a central portion of the first external connection, the first external connection configured to receive a first power supply potential;
the first DRAM semiconductor device includes a first through via, the first through via providing an electrical connection between a first surface and a second surface of the first DRAM semiconductor device;
the second DRAM semiconductor device includes a second through via, the second through via providing an electrical connection between a first surface and a second surface of the second DRAM semiconductor device;
the third DRAM semiconductor device includes a third through via, the third through via providing an electrical connection between a first surface and a second surface of the third DRAM semiconductor device;
a first interface connection formed between the first DRAM semiconductor device and the second DRAM semiconductor device providing an electrical connection between the first and second through vias;
a second interface connection formed between the second DRAM semiconductor device and the third DRAM semiconductor device providing an electrical connection between the second and third through vias;
a third interface connection formed between the interposer and the first DRAM semiconductor device providing an electrical connection between the first wiring and the first through via, the first wiring providing an electrical connection between the third interface connection and the first external connection;
a second wiring formed in the interposer providing an electrical connection essentially orthogonal to and between the first surface and the second surface, opposite the first surface, of the interposer; and
a second external connection formed on the second surface of the interposer, the second wiring electrically connected at a central portion of the second external connection, the second external connection configured to receive a first data signal.

US Pat. No. 10,115,709

APPARATUSES COMPRISING SEMICONDUCTOR DIES IN FACE-TO-FACE ARRANGEMENTS

Micron Technology, Inc., ...

1. An apparatus, comprising:a first chip and a second chip; each of the first and second chips comprising:
a multilevel wiring structure including a first level wiring layer, a second level wiring layer and an insulating film between the first level wiring layer and the second level wiring layer; and
a redistribution wiring layer over the multilevel wiring structure, the redistribution wiring layer including a redistribution wiring and a pad electrically coupled to the redistribution wiring;
wherein the first chip is mounted above the second chip so that the redistribution wiring layer of the first chip faces the redistribution wiring layer of the second chip, and the pad of the first chip faces the pad of the second chip; the pad of the first chip being vertically spaced from the pad of the second chip by an intervening insulative region; the redistribution wiring of the second chip being electrically coupled to the redistribution wiring of the first chip through a bonding region; the pad of the first chip being electrically coupled to the pad of the second chip through the redistribution wiring of the first chip and the redistribution wiring of the second chip; and
wherein:
the first redistribution wiring includes first bonding pads;
the second redistribution wiring includes second bonding pads;
the first bonding pads are not overlapped by the second chip;
the second bonding pads are not overlapped by the first chip; and
the first chip is shifted relative to the second chip by a distance “a”, wherein the bonding region includes a first coupling region from the first chip and second coupling region from the second chip; and wherein the first coupling region is offset from the pad of the first chip by a distance of a/2, and the second coupling region is offset from the pad of the second chip by the distance of a/2.

US Pat. No. 10,115,708

SEMICONDUCTOR PACKAGE HAVING A REDISTRIBUTION LINE STRUCTURE

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:a first semiconductor chip having first bonding pads which are arranged in two rows on a middle portion of a first active surface;
a second semiconductor chip having substantially the same size as the first semiconductor chip, and having second bonding pads which are arranged in two rows on a middle portion of a second active surface;
redistribution lines formed on the first active surface, and corresponding to the first bonding pads, respectively, the redistribution lines each having a redistribution line pad, a wire bonding pad, and coupling lines electrically coupling the redistribution line pad, the wire bonding pad and the corresponding first bonding pad; and
bumps formed on the second bonding pads of the second semiconductor chip, respectively,
wherein the location of the second bonding pads in relation to the second semiconductor chip is the same as the location of the corresponding first bonding pads in relation to the first semiconductor chip,
wherein the first semiconductor chip and the second semiconductor chip are stacked such that the first active surface and the second active surface face each other, and are disposed to be offset from each other, and
wherein the bumps are bonded to the redistribution line pads of the redistribution lines, respectively.

US Pat. No. 10,115,707

ADHESIVE FILM AND SEMICONDUCTOR PACKAGE USING ADHESIVE FILM

FURUKAWA ELECTRIC CO., LT...

1. An adhesive film, which comprises: (A) a bismaleimide resin; (B) a radical initiator; and (C) a coupling agent that contains a (meth)acrylic group, wherein at least one of the following applies:(1) radical initiator (B) has a one-hour half-life temperature of 140° C. or higher, or
(2) a filler (D) is present, having a content of 75 percent or higher by mass based on 100 percent by mass in the adhesive film.

US Pat. No. 10,115,706

SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS

SAMSUNG ELECTRONICS CO., ...

1. A semiconductor chip comprising a plurality of input/output units, the semiconductor chip comprising:a plurality of additional pads disposed on a surface of the semiconductor chip, wherein the plurality of additional pads comprise at least one of a first additional pad to which a ground voltage is applied and a second additional pad to which a power supply voltage is applied; and
a plurality of pads disposed on the surface of the semiconductor chip, wherein the plurality of pads comprise at least one of a first pad to which the ground voltage is applied and a second pad to which the power supply voltage is applied, and further comprise a third pad through which a signal is input and/or output,
wherein the at least one of the first additional pad and the second additional pad is disposed on an input/output unit where the third pad is disposed, among the plurality of input/output units, and
wherein, when the plurality of additional pads comprise the first additional pad and the plurality of pads comprise the first pad, the first additional pad is electrically connected to the first pad through an internal interconnection underneath the surface.

US Pat. No. 10,115,705

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

AMKOR TECHNOLOGY, INC., ...

1. A semiconductor package comprising:a first semiconductor device electrically connected to a second semiconductor device, wherein:
the first semiconductor device comprises a first surface, and the first surface comprises at least a first portion and a second portion that does not overlap with the first portion, wherein the first portion is a portion of the first surface that is not under the second semiconductor device; a first encapsulant material surrounding side edges of the first semiconductor device; a first dielectric layer above the first encapsulant material and the first portion; at least one redistribution layer (RDL) above the first dielectric layer; a second dielectric layer above the at least one RDL and the second portion, wherein:
a maximum thickness of the second dielectric layer above the second portion and adjacent to the second semiconductor device is less than a sum of the thicknesses of the first dielectric layer above the first portion, the at least one RDL, and the second dielectric layer above the at least one RDL; and
a passivation layer directly above the first surface, wherein:
the passivation layer directly contacts both the first dielectric layer and the first surface, and
the passivation layer directly contacts both the second dielectric layer and the first surface.

US Pat. No. 10,115,704

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first semiconductor chip having a first surface, a second surface on a side of the first semiconductor chip opposite to that of the first surface, a first electrode on the first surface, a second electrode on the second surface, and a first contact electrically connecting the first electrode and the second electrode;
a second semiconductor chip having a third surface that faces the first surface, a fourth surface on a side of the second semiconductor chip opposite to that of the third surface, and a third electrode on the fourth surface;
a metal wire that electrically connects the third electrode to the first electrode;
a first insulating layer that is on the second surface of the first semiconductor chip and includes a first opening;
a first conductive layer that is in the first opening and on a part of the first insulating layer and is electrically connected to the second electrode;
a second conductive layer that is directly in contact with the first conductive layer;
a second insulating layer that is on the first insulating layer and the second conductive layer and includes a second opening;
a third conductive layer that is in the second opening and is electrically connected to the second conductive layer; and
a first external terminal in direct contact with the third conductive layer, wherein
no wiring substrate is present between the first semiconductor chip and the first external terminal.

US Pat. No. 10,115,703

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:a first semiconductor substrate;
a second semiconductor substrate facing the first semiconductor substrate;
a first pad electrode disposed on a surface of the first semiconductor substrate facing the second semiconductor substrate;
a second pad electrode disposed on a surface of the second semiconductor substrate facing the first semiconductor substrate;
a first insulating layer disposed on an edge portion of the first semiconductor substrate and the first pad electrode;
a second insulating layer disposed on an edge portion the second semiconductor substrate and the second pad electrode;
a base metal layer disposed on the second insulating layer and a center portion of the second pad electrode, the base metal layer having a stepped first surface and a planar second surface opposite the stepped first surface;
a first metal layer disposed over the first semiconductor substrate and facing the second semiconductor substrate;
a second metal layer disposed on the base metal layer and facing the first metal layer, the second metal layer having a planar first surface in contact with the base metal layer, and a planar second surface opposite the planar first surface;
a third metal layer disposed between the first metal layer and the second metal layer;
a first alloy layer disposed between the first metal layer and the third metal layer comprising a component of the first metal layer and a component of the third metal layer; and
a second alloy layer disposed between the second metal layer and the third metal layer, comprising a component of the second metal layer and a component of the third metal layer,
wherein the first metal layer includes a stepped surface adjacent to and in contact with the first alloy layer, the stepped surface of the first metal layer including edge portions that extend beyond a central portion thereof.

US Pat. No. 10,115,702

SEMICONDUCTOR CHIP FOR SENSING TEMPERATURE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

Samsung Electronics Co., ...

1. A semiconductor system comprising:a first chip configured to generate first temperature information of the first chip, the first temperature information being based on at least one temperature measurement using at least one first temperature sensor; and
a second chip including a second temperature sensor configured to be controlled based on at least the first temperature information, the second temperature sensor configured to generate a control signal based on the first temperature information and temperature measured by the second temperature sensor, the control signal adjusting an operation performed on the second chip, wherein
the second chip is a dynamic random access memory (DRAM) chip, and
the control signal is configured to determine a self-refresh interval of the DRAM chip.