US Pat. No. 9,948,308

MULTI-MODULUS PRESCALER WITH IMPROVED NOISE PERFORMANCE

pSemi Corporation, San D...

1. A method for reducing phase noise in a multi-modulus prescaler electronic circuit, including:(a) providing a feed-forward signal path for the multi-modulus prescaler electronic circuit;
(b) providing at least one feedback path within the multi-modulus prescaler electronic circuit; and
(c) buffering each feedback path and the feed-forward path such that the feed-forward signal path and each feedback path serve as a separate but parallel buffered feed-forward signal path and feedback paths.

US Pat. No. 10,141,958

ADAPTIVE TUNING NETWORK FOR COMBINABLE FILTERS

pSemi Corporation, San D...

1. A multi-path radio-frequency (RF) adaptive tuning network switch architecture configurable to operate in a carrier aggregation mode and in a non-carrier aggregation mode, including:(a) a multi-path tunable switch having (1) a plurality of signal ports each configured to be coupled to a corresponding RF band filter and (2) a common port, the multi-path tunable switch configured to concurrently connect at least two selected signal ports to the common port in at least one mode of operation;
(b) a single digitally-controlled tunable matching network coupled to the common port of the multi-path tunable switch and selectively controlled to counteract impedance mismatch conditions arising from coupling more than one selected RF band filter concurrently to the common port; and
(c) at least one digitally-controlled filter pre-match network for improving impedance matching and configured to be selectively coupled to or uncoupled from a corresponding signal port of the multi-path tunable switch, wherein at least one of the at least one digitally-controlled filter pre-match network is uncoupled from the corresponding signal port of the multi-path tunable switch when that corresponding signal port is operating in a non-carrier aggregation mode.

US Pat. No. 10,027,283

UNIVERSAL RF AMPLIFIER CONTROLLER

pSemi Corporation, San D...

1. A circuital arrangement comprising:a plurality of variable-gain amplifiers arranged in a cascaded configuration, each variable-gain amplifier of the plurality of variable-gain amplifiers configured to act on an input current to provide a calibrated output current that is an amplified version of the input current according to a current amplification range of the each variable-gain amplifier, the current amplification range having a low value and a high value,
wherein the cascaded configuration connects outputs to inputs of successively arranged amplifiers of the plurality of variable-gain amplifiers, to provide a multiplicative current chain having a current amplification range that is based on multiplying of the current amplification range of the each variable-gain amplifier,
wherein an arrangement order by which the plurality of variable-gain amplifiers are arranged in the cascaded configuration is according to the high value of the current amplification range of the each variable-gain amplifier, starting from a lowest high value and ending at a highest high value, and
wherein the plurality of variable-gain amplifiers are configured to amplify a reference current provided to a first variable-gain amplifier of the plurality of variable-gain amplifiers and generate, based on the current amplification range of the multiplicative current chain, a calibrated control current adapted to control an output power of a radio frequency (RF) amplifier.

US Pat. No. 9,960,737

STACKED PA POWER CONTROL

pSemi Corporation, San D...

1. A circuital arrangement comprising:a stack of a plurality of transistors arranged in a cascode configuration, comprising:
(i) an input transistor adapted to receive an input radio frequency (RF) signal; and
(ii) one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor adapted to output, at an adjustable output power, an output RF signal based on the input RF signal;
a first resistor tree comprising a plurality of series connected resistors; and
a low dropout (LDO) regulator coupled to the first resistor tree,
wherein:
the adjustable output power is controlled by varying at least one gate voltage of the one or more cascoded transistors of the stack,
a node of the first resistor tree is configured to provide the at least one gate voltage, and
a control voltage to the LDO regulator varies the at least one gate voltage to provide the adjustable output power from the stack.

US Pat. No. 10,074,714

LOW LEAKAGE FET

pSemi Corporation, San D...

1. A FET fabricated on a silicon-on-insulator substrate, including:(a) an isolated silicon island;
(b) a gate structure overlying the isolated silicon island and having a center length L, the gate structure having central and edge regions each with an associated work function ?MF
(c) source and drain regions within the isolated silicon island and defined by the gate structure;
(d) a central conduction channel between the source and drain regions, the central conduction channel having a threshold voltage VtC; and
(e) at least one edge transistor defined by a corresponding edge region of the gate structure overlying the isolated silicon island, each edge transistor having a threshold voltage VtE determined in part by the work function ?MF of the corresponding edge region of the gate structure;
wherein the work function ?MF of at least one corresponding edge region of the gate structure is increased sufficiently to increase the VtE of such corresponding edge transistor to be approximately equal to or greater than VtC.

US Pat. No. 10,069,481

STATE CHANGE STABILIZATION IN A PHASE SHIFTER/ATTENUATOR CIRCUIT

pSemi Corporation, San D...

1. An electronic circuit for modifying an applied radio frequency, including:(a) at least one of (1) a phase shifter circuit for modifying the phase of the applied radio frequency signal in response to applied phase state digital control words, and (2) an attenuator circuit for selectively attenuating the applied radio frequency signal in response to applied attenuation state digital control words;
(b) a fine adjustment circuit coupled to at least one of the phase shifter circuit and the attenuator circuit, the fine adjustment circuit including at least one of (1) an adjustment attenuator circuit for providing a selectable attenuation adjustment as a function of the applied phase state digital control words to substantially equalize insertion loss variations between phase states selected by the applied phase state digital control words, and (2) an adjustment phase shifter circuit for providing a selectable phase shift adjustment as a function of the applied attenuation state digital control words to substantially equalize phase variations between attenuation states selected by the applied attenuation digital control words; and
(c) an adjustment control circuit coupled to the fine adjustment circuit, wherein the adjustment control circuit includes a look-up table that maps at least one of the applied phase state digital control words or the applied attenuation state digital control words to at least one set of adjustment digital control words, and wherein at least one set of the adjustment digital control words is coupled to the fine adjustment circuit.

US Pat. No. 10,062,946

REFLECTION-BASED RF PHASE SHIFTER

pSemi Corporation, San D...

1. A programmable multi-reflective radio frequency (RF) phase shifter, including:(a) a hybrid coupler having an input port, an output port, a coupled port, and a direct port;
(b) first and second multi-reflective terminating circuits coupled respectively to the coupled port and the direct port of the hybrid coupler, each multi-reflective terminating circuit including two or more switchable reactive elements; and
(c) thermometric coding control circuitry coupled to the first and second multi-reflective terminating circuits for sequentially controlling the switchable reactive elements so as to generate multiple equidistant phase shifts of a signal applied to the input port of the hybrid coupler.

US Pat. No. 9,979,387

HIGH SPEED AND HIGH VOLTAGE DRIVER

pSemi Corporation, San D...

1. A high speed high voltage (HSHV) open drain driver comprising:a main stack of transistors of a first type coupled between a reference voltage and an output node of the HSHV driver;
a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of transistors of a second type;
wherein:
gate nodes of a first to a last transistor of the main stack are coupled sequentially and in a one to one relationship to source and/or drain nodes of a first to a last transistor of the biasing stack,
source nodes of transistors of the main stack of transistors are coupled in a one to one relationship to gate nodes of transistors of the biasing stack,
the output node is a drain node of an output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and
transistors of the main stack and the biasing stack having desired operating voltages substantially smaller than the high voltage.

US Pat. No. 9,966,988

INTEGRATED RF FRONT END WITH STACKED TRANSISTOR SWITCH

pSemi Corporation, San D...

1. An integrated RF Power Amplifier (PA) circuit, comprising:a. an input node to accept an input signal with respect to a reference voltage Vref, the input node connected to a first gate of a first MOSFET, wherein a source of MOSFET is connected to Vref;
b. one or more MOSFETs connected in series with the first MOSFET to form a transistor stack, wherein the first MOSFET comprises a bottom transistor of the transistor stack, and the one or more MOSFETs comprises a top transistor of the transistor stack, wherein the transistor stack is configured to control conduction between the reference voltage Vref and an output drive node, and wherein the output drive node is connected to a drain of the top transistor of the transistor stack; and
c. one or more predominantly capacitive elements connected directly between a corresponding gate of the one or more MOSFETs and Vref.

US Pat. No. 10,074,746

METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK—HARMONIC WRINKLE REDUCTION

pSemi Corporation, San D...

1. An accumulated charge control N-type MOSFET (ACC N-MOSFET) adapted to control charge accumulated in a body of the ACC N-MOSFET, comprising:a) a gate, drain, source and a gate oxide layer positioned between the gate and the body, wherein the ACC N-MOSFET is biased to operate in an accumulated charge regime when the ACC N-MOSFET is operated in a non-conducting or near non-conducting state;
b) a first accumulated charge sink (ACS) region positioned proximate a first distal end of the body, wherein the first ACS region is coupled to the body, and wherein, when the ACC N-MOSFET is operated in the accumulated charge regime, a first ACS bias voltage is applied to the first ACS region to control or to remove accumulated charge from the ACC N-MOSFET body via the first ACS region; and
c) a second accumulated charge sink (ACS) positioned proximate a second distal end of the body, wherein the second ACS region is coupled to the body and wherein, when the ACC N-MOSFET is operated in the accumulated charge regime, a second ACS bias voltage is applied to the second ACS region to control or to remove accumulated charge from the ACC N-MOSFET body via the second ACS region,wherein the first ACS bias voltage and the second ACS bias voltage are negative with respect to ground, drain and source.

US Pat. No. 10,075,159

HIGH FREQUENCY PHASE SHIFTER USING LIMITED GROUND PLANE TRANSITION AND SWITCHING ARRANGEMENT

pSemi Corporation, San D...

1. A switching arrangement comprising:a first inner signal conductor, a first outer conductor and a second outer conductor;
a second inner signal conductor, a third outer conductor and a fourth outer conductor;
a switching matrix;
a signal input; and
a signal output;
wherein:
(a) the switching arrangement is configured to receive a differential input signal from the signal input, and
(b) the switching arrangement is configured to exhibit:
(i) a through state, wherein the switching matrix is configured to connect the first inner signal conductor to the second inner signal conductor, the first outer conductor to the third outer conductor and the second outer conductor to the fourth outer conductor, thereby configuring the switching arrangement to pass the differential input signal through; and
(ii) a changeover state, wherein the switching matrix is configured to connect the first inner signal conductor to both the third outer conductor and the fourth outer conductor, and to connect the second inner signal conductor to both the first outer conductor and the second outer conductor, thereby configuring the switching arrangement to output a differential output signal to the signal output, the differential output signal being the differential input signal with a phase shift.

US Pat. No. 9,948,252

DEVICE STACK WITH NOVEL GATE CAPACITOR TOPOLOGY

pSemi Corporation, San D...

1. A monolithically integrated circuital arrangement comprising:a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor;
N gate capacitors, each gate capacitor of the N gate capacitors connected, at a first terminal of the each gate capacitor, to a gate of a respective transistor of the N cascode transistors, wherein at least one gate capacitor of the N gate capacitors is connected, at a second terminal of the at least one gate capacitor, to a first terminal of a coupling gate capacitor of the N gate capacitors, and remaining gate capacitors of the N gate capacitors are connected, at a second terminal of each gate capacitor of the remaining gate capacitors, to the reference voltage.

US Pat. No. 9,941,849

PROGRAMMABLE OPTIMIZED BAND SWITCHING LNA FOR OPERATION IN MULTIPLE NARROW-BAND FREQUENCY RANGES

pSemi Corporation, San D...

1. An amplifier module comprising:(a) at least one amplifier having an output transistor configured in a common gate configuration and no more than one input transistor, the input transistor configured in a common source configuration, the amplifier for use in at least two frequency ranges;
(b) an amplifier output;
(c) an amplifier output port;
(d) an output impedance matching network coupled between the amplifier output and the amplifier output port; and
(e) at least one selectable impedance circuit (SIC) comprising: (i) a first and second terminal, the impedance of the at least one SIC being selected from at least two impedance values; and (ii) at least a parallel-coupled output SIC having the first terminal coupled to the amplifier output and the second terminal coupled to the amplifier output port.

US Pat. No. 9,935,614

MULTI-STATE ATTENUATOR

pSemi Corporation, San D...

1. A programmable multi-state attenuator for a signal, including:(a) a throughput section having an input terminal, an output terminal, at least one connection node, and at least two selectable signal attenuation paths coupled between the input terminal and the output terminal, for selectably coupling an applied signal from the input terminal to the output terminal through at least one of the at least two selectable signal attenuation paths to provide a corresponding attenuation state for the applied signal; and
(b) a shunt section including at least one shunt leg coupled between a corresponding one of the at least one connection node of the throughput section and a reference voltage, each shunt leg for selectively coupling its corresponding one connection node to the reference voltage, at least one shunt leg including (1) at least one selectable shunt switch, and (2) at least two series-connected impedance elements coupled in series with a corresponding one of the at least one selectable shunt switch, at least one of the at least two series-connected impedance elements being selectably configurable to provide at least two impedance states for the at least one shunt leg, each impedance state corresponding to an attenuation state of the throughput section.

US Pat. No. 9,923,521

STACKED PA POWER CONTROL

pSemi Corporation, San D...

1. A circuital arrangement comprising:
a stack of a plurality of transistors arranged in a cascode configuration, comprising:
(i) an input transistor adapted to receive an input radio frequency (RF) signal; and
(ii) one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor adapted to output,
at an adjustable output power, an output RF signal based on the input RF signal;

a first resistor tree comprising a plurality of series connected resistors; and
a low dropout (LDO) regulator coupled to the first resistor tree,
wherein:
the adjustable output power is controlled by varying at least one gate voltage of the one or more cascoded transistors of
the stack,

a node of the first resistor tree is configured to provide the at least one gate voltage, and
a control voltage to the LDO regulator varies the at least one gate voltage to provide the adjustable output power from the
stack.

US Pat. No. 10,114,391

LOW-NOISE HIGH EFFICIENCY BIAS GENERATION CIRCUITS AND METHOD

pSemi Corporation, San D...

1. An apparatus for generating a steady state positive voltage signal (PVS) and a steady state negative voltage signal (NVS), including:a bias signal generation module (BSGM) for generating a steady state reference voltage signal (RVS), the RVS having a voltage level less than the PVS;
a positive signal generation module (PSGM) generating the PVS, the PSGM including a first capacitor, the PSGM employing the first capacitor to generate a portion of the PVS based on the RVS; and
a negative signal generation module (NSGM) generating the NVS, the NSGM including a second capacitor, the NSGM employing the second capacitor to generate a portion of the NVS based on the RVS.

US Pat. No. 10,038,414

RF SWITCH WITH SPLIT TUNABLE MATCHING NETWORK

pSemi Corporation, San D...

1. A radio frequency (RF) integrated circuit chip including:(a) a selector switch with an input port; and
(b) an on-chip impedance matching network (IMN) tuner coupled to the input port of the selector switch and configured to be coupled to an off-chip set of IMN components;
wherein the on-chip IMN tuner and the off-chip set of IMN components together comprise an impedance matching network, and wherein the on-chip IMN tuner and the selector switch are integrated in close enough proximity such that the resonant frequency from parasitic inductance is more than about twice the operating frequency of the integrated circuit.

US Pat. No. 10,033,333

UNIVERSAL RF AMPLIFIER CONTROLLER

pSemi Corporation, San D...

1. A circuital arrangement comprising:a plurality of calibration and control blocks arranged in a cascaded configuration, each calibration and control block of the plurality of calibration and control blocks configured to act on an input current to provide a calibrated output current that is an amplified version of the input current according to a current amplification range of the each calibration and control block, the current amplification range having a low value and a high value; and
an offset current generator configured to generate an offset current that is added to the calibrated output current of one calibration and control block of the plurality of calibration and control blocks,
wherein the plurality of calibration and control blocks are configured to amplify a reference current provided to a first calibration and control block of the plurality of calibration and control blocks and generate a calibrated control current adapted to control an output power of a radio frequency (RF) amplifier.

US Pat. No. 10,033,349

LOW LOSS MULTI-STATE PHASE SHIFTER

pSemi Corporation, San D...

1. A multi-state phase shifter circuit for selectively shifting the phase of a radio frequency signal, including:(a) a first port and a second port; and
(b) at least two parallel phase shifting signal paths connected between the first port and the second port, each parallel phase shifting signal path comprising at least one switch and at least one associated phase shift element series-connected to such at least one switch, each switch of each signal path being operable independently of each switch of each other signal path;
wherein more than one signal path may be concurrently switched into series connection between the first port and the second port at the same time, and
wherein selection of a signal path induces a phase shift state for an applied radio frequency signal, and the phase difference between two phase shift states remains approximately constant as a function of frequency and substantially independent of electrical lengths of each signal path.

US Pat. No. 9,998,002

DIFFERENTIAL CHARGE PUMP

pSemi Corporation, San D...

1. A differential charge pump, including:(a) a clock signal having a first phase and a second phase, the second phase being different from the first phase, for controlling switch devices regulating charge pumping cycles of the differential charge pump;
(b) at least two charge pump sections electrically coupled in parallel to an input voltage source separate from the clock signal, wherein each charge pump section generates an output voltage different from an input voltage from the input voltage source, each charge pump section including at least two charge pumping stages having an input and an output, the input of each charge pumping stage being switchably coupled to an associated input voltage source separate from the clock signal and the output of each charge pumping stage being switchably coupled to one of (i) an associated intermediate storage capacitance coupled to and shared with at least one other of the at least two charge pump sections or (ii) a common terminal storage capacitance, each charge pumping stage including:
(1) a fly capacitor having an input and an output;
(2) a first switch device coupled between the input of the fly capacitor and an intermediate node, and coupled to and controlled by a selected one of the first phase or the second phase of the clock signal; and
(3) a second switch device coupled between the intermediate node and the output of the fly capacitor, and coupled to and controlled by a selected one of the second phase or the first phase of the clock signal, the selected phase controlling the second switch device being different from the selected phase controlling the first switch device;
wherein the charge pumping cycle in at least a first one of the charge pump sections is initiated on the first phase of the clock signal, and the charge pumping cycle in at least a second one of the charge pump sections is initiated on the second phase of the clock signal.

US Pat. No. 9,998,075

LDO WITH FAST RECOVERY FROM SATURATION

pSemi Corporation, San D...

1. A circuital arrangement for providing burst power at an output voltage node, the circuital arrangement comprising:a pass device, configured to provide a conduction path between a supply voltage node and the output voltage node through operation of the pass device in one of a saturation region and a triode region of the pass device;
an operational amplifier, coupled, through an output node of the operational amplifier, to an input node of the pass device, the operational amplifier configured to provide a control voltage at the output node of the operational amplifier to the input node of the pass device to control the region of operation and biasing of the pass device; and
a current boost circuit coupled to the output voltage node and to the output node of the operational amplifier, the current boost circuit comprising a mirrored circuit that mirrors a current at an output stage of the operational amplifier in correspondence of the control voltage to provide a mirrored output node;
wherein:
the current boost circuit is configured to provide a current boost to the operational amplifier to increase a current drive capability of the output stage of the operational amplifier during a transition of the pass device from one of the saturation region and the triode region of operation to the other of the saturation region and the triode region of operation based on a detected ramping of the control voltage at the mirrored output node.

US Pat. No. 9,973,149

SOURCE SWITCHED SPLIT LNA

pSemi Corporation, San D...

1. An amplifier including:(a) plurality of low noise amplifiers (LNA), each including; an input transistor and an output transistor;
(b) at least two control input terminals, each coupled to an output transistor of a corresponding one of the LNAs;
(c) at least one source switch connecting source terminals of the input transistors of at least two of the LNAs during a first mode of operation and disconnecting the source terminals during at least a second mode of operation; and
(d) a gate capacitance module, the gate capacitance module having a first and second terminal, the first terminal coupled to the gate of an associated one of the input transistors and the second terminal coupled to the source of the associated input transistor.

US Pat. No. 9,960,098

SYSTEMS AND METHODS FOR THERMAL CONDUCTION USING S-CONTACTS

pSemi Corporation, San D...

1. A semiconductor integrated circuit comprising:(a) a heat source fabricated within the semiconductor integrated circuit;
(b) a semiconductor substrate fabricated within the semiconductor integrated circuit providing an electrical base upon which the heat source is fabricated;
(c) an insulator layer within the semiconductor integrated circuit disposed on the semiconductor substrate;
(d) a thermal structure within the semiconductor integrated circuit disposed on the insulator layer; and
(e) a plurality of substrate contacts (“S-contacts”) penetrating the insulator layer to provide a thermal conduction path from the substrate to the thermal structure and spaced over an area that underlies the thermal structure to provide a thermal conduction path.

US Pat. No. 9,929,701

LNA WITH PROGRAMMABLE LINEARITY

pSemi Corporation, San D...

1. An amplifier comprising:(a) a plurality of amplifier branches at least one which includes a plurality of FETs;
(b) a plurality of branch control switches, each branch control switch coupled to a corresponding amplifier branch;
(c) a load inductance coupled between a drain of a common-gate amplifier and a voltage supply and a plurality of gain control resistors selectively placed in parallel with the load inductance; and
(d) a plurality of gain control compensation switches, each gain control compensation switch corresponding to one of a plurality of gain control compensation capacitors and coupled to the corresponding gain control compensation capacitor to place the corresponding gain control compensation capacitor in parallel with an output capacitor when the corresponding gain control compensation switch is closed.

US Pat. No. 10,020,787

POWER AMPLIFIER SELF-HEATING COMPENSATION CIRCUIT

pSemi Corporation, San D...

1. A compensation circuit configured to monitor a target circuit having one or more performance parameters affected by self-heating during operation of the target circuit, wherein the compensation circuit is configured to be coupled to and adjust one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating during operation of the target circuit on the one or more performance parameters, the compensation circuit including:(a) at least one sensor located with respect to the target circuit so as to measure the temperature T of the target circuit and generate an output signal representing such temperature T;
(b) at least one tracking circuit, each coupled to at least one sensor, configured to capture a temperature T(t=t0) at a time t0 after the commencement of operation of the target circuit, and to sample a temperature T(t>t0) at times after time t0 and during operation of the target circuit, the at least one tracking circuit including:
(1) a differential amplifier having a first input coupled to the output signal of a corresponding sensor, a second input, and an output representing the difference between signals applied to the first input and the second input; and
(2) a storage capacitor coupled to the second input of the differential amplifier and selectively coupled to the differential amplifier output;
wherein:
(A) in a first phase, the output of the differential amplifier is coupled to the storage capacitor and to the second input of the differential amplifier at least at time t0, such that a charge on the capacitor represents an initial temperature T(t=t0); and
(B) in a second phase, the output of the differential amplifier is uncoupled from the storage capacitor and represents the difference AT between (i) the output signal of the corresponding sensor coupled to the first input and representing the temperature T(t>t0), and (ii) the storage capacitor charge coupled to the second input and representing the temperature T(t=t0); and
(c) a correction circuit, coupled to at least one tracking circuit, for generating a correction signal as a function of AT from the coupled at least one tracking circuit, the correction signal being configured to be coupled to and adjust the one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating during operation of the target circuit on the one or more performance parameters.

US Pat. No. 9,947,688

INTEGRATED CIRCUITS WITH COMPONENTS ON BOTH SIDES OF A SELECTED SUBSTRATE AND METHODS OF FABRICATION

pSemi Corporation, San D...

1. A method for forming integrated circuits (ICs) from a semiconductor wafer including an active layer, a buffer layer for improved electrical isolation between electronic components, and a silicon substrate, a first surface of the buffer layer coupled to the active layer, and a second, opposite surface of the buffer layer coupled to the silicon substrate, comprising:a) forming a first circuit layer of active and/or passive electronic components in the active layer of the semiconductor wafer;
b) removing the silicon substrate from the semiconductor wafer to expose the second surface of the buffer layer;
c) coupling the second surface of the buffer layer to a first surface of a monolithic insulating substrate suitable for forming active and/or passive electronic components; and,
d) forming a second circuit layer of active and/or passive electronic components on a second, opposite surface of the insulating substrate.

US Pat. No. 9,941,347

FLOATING BODY CONTACT CIRCUIT METHOD FOR IMPROVING ESD PERFORMANCE AND SWITCHING SPEED

pSemi Corporation, San D...

1. An electronic circuit including:(a) at least one field effect transistor (FET), each FET including:
(1) a gate, a drain, a source, and a body;
(2) a gate resistor series connected to the gate of such FET;
(3) an accumulated charge sink (ACS) circuit connected to the body of such FET; and
(4) an ACS resistance series connected to the ACS circuit, wherein the series-connected ACS resistance and the ACS circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate; and
(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including:
(1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and
(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal.

US Pat. No. 10,141,895

SYSTEMS AND METHODS FOR OPTIMIZING AMPLIFIER OPERATIONS

pSemi Corporation, San D...

3. A system for optimizing amplifier operations, including:an amplifier configured to receive an input signal and generate an output signal therefrom having a desired characteristic that includes at least one of a power level, a voltage range, or a current level; and
a feed-forward control circuit including a look-up table and configured to receive the input signal, analyze the input signal using a circuit element detector configured to measure component parameters of coupled circuit elements, apply the analyzed input signal to the look-up table to generate a control signal as a function of the analyzed input signal, and provide the control signal to the amplifier to modify at least one operating characteristic of the amplifier, thereby altering the desired characteristic of the output signal.

US Pat. No. 10,142,039

INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE

pSemi Corporation, San D...

1. A method for calibrating a radio frequency (RF) integrated circuit, including:(a) providing a primary RF transmission path and a primary RF reception path on an integrated circuit;
(b) selectively connecting at least one RF transceiver front-end circuit through a multi-way switch complex to the primary RF transmission path and the primary RF reception path;
(c) coupling at least one switchable internal calibration path to the at least one RF transceiver front-end circuit;
(d) configuring the at least one switchable internal calibration path to convey, in a calibration mode, an RF test signal from the primary RF transmission path through the multi-way switch complex and thence through at least a portion of the coupled at least one RF transceiver front-end circuit to the primary RF reception path; and
(e) providing at least one inter-chip switch for enabling selectable access from external to the integrated circuit to at least one of the primary RF transmission path, the primary RF reception path, and/or the at least one switchable internal calibration path; wherein at least one RF transceiver front-end circuit comprises a phase-attenuation core.

US Pat. No. 10,128,963

INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE

pSemi Corporation, San D...

1. A radio frequency (RF) integrated circuit including:(a) a primary RF transmission path;
(b) a primary RF reception path;
(c) at least one RF transceiver front-end circuit, each selectively connectable to the primary RF transmission path and the primary RF reception path; and
(d) at least one switchable internal calibration path coupled to the at least one RF transceiver front-end circuit and configured to convey, in a calibration mode, an RF test signal from the primary RF transmission path through at least a portion of the coupled at least one RF transceiver front-end circuit to the primary RF reception path;
wherein at least one RF transceiver front-end circuit includes at least one of a phase-attenuation core or an input/output circuit.

US Pat. No. 10,044,347

DEAD TIME CONTROL CIRCUIT FOR A LEVEL SHIFTER

pSemi Corporation, San D...

1. A circuital arrangement configured to control a high side (HS) device and a low side (LS) device arranged in a stacked configuration, the HS device and the LS device capable of withstanding a voltage higher than or equal to a first voltage, the circuital arrangement comprising:a HS control circuit operating between a first switching voltage and a second switching voltage based on the first switching voltage, the first switching voltage being an output voltage at a common output node of the stacked HS device and LS device, the HS control circuit configured to provide a HS output control signal at a voltage higher than the first voltage to the HS device;
a LS control circuit configured to provide a LS output control signal to the LS device; and
a dead time control circuit configured, to generate timing information for the HS output control signal and the LS output control signal,
wherein all transistor devices of the HS control circuit, the LS control circuit and the dead time controller circuit, are each configured to withstand a second voltage substantially smaller than the first voltage,
wherein the timing information for the HS output control signal is coupled to the transistor devices of the HS control circuit by way of a DC blocking edge detection circuit comprising:
i) a first capacitive coupling configured to receive a first HS input timing control signal containing the timing information for the HS output control signal, and
ii) a second capacitive coupling configured to receive a second HS input timing control signal that is an inverted version of the first input timing control signal, wherein:
each of the first and second capacitive couplings comprises two series connected capacitors and a common node between the series connected capacitors, the common node configured to receive a respective one of the first and the second HS input timing control signals,
for each of the first and second capacitive couplings, a first capacitor of the two series connected capacitors is coupled via a resistor connected to a terminal of the first capacitor away from the common node to the first switching voltage, so to generate a positive pulse (CUvss, CDvss) in correspondence of a rising edge of a respective input timing control signal (CUb, CDb) and no pulse in correspondence of a falling edge of said input timing control signal,
for each of the first and second capacitive couplings, a second capacitor of the two series connected capacitors is coupled via a resistor connected to a terminal of the second capacitor away from the common node to the second switching voltage, so to generate a negative pulse (CUvdd, CDvdd) in correspondence of a falling edge of the respective input timing control signal (CUb, CDb) and no pulse in correspondence of a rising edge of said input timing control signal, and
a first edge of the HS output control signal corresponds to concurrent detection of the positive pulse in correspondence of the rising edge of the first input timing control signal and the negative pulse in correspondence of the falling edge of the second input timing control signal, and a second edge of the HS output control signal corresponds to concurrent detection of the positive pulse in correspondence of the rising edge of the second input timing control signal and the negative pulse in correspondence of the falling edge of the first input timing control signal.

US Pat. No. 10,038,418

OPTIMIZED MULTI GAIN LNA ENABLING LOW CURRENT AND HIGH LINEARITY INCLUDING HIGHLY LINEAR ACTIVE BYPASS

pSemi Corporation, San D...

1. A Low Noise Amplifier (LNA) comprising:(a) a first path including a first input field effect transistor (FET) coupled in series with a first output FET, a gate of the first output FET being coupled to a bias voltage source;
(b) a second path including a second input FET coupled in series with a second output FET, a gate of the first input FET coupled to a gate of the second input FET and a gate of the second output FET selectively coupled to a gate of the first output FET; and
(c) a first inductive element coupled between the first input FET and ground;
(d) a second inductive element coupled between the second input FET and ground; and
(e) a source switch coupled between the source of the first and second input FETs such that when the source switch is closed, the source of the first input FET is coupled to the source of the second input FET and when the source switch is open, the source of the first input FET is disconnected from the source of the second input FET.

US Pat. No. 10,020,798

LOW PHASE SHIFT, HIGH FREQUENCY ATTENUATOR

pSemi Corporation, San D...

1. A radio frequency attenuator circuit including:(a) an In port and an Out port;
(b) a bypass path coupled to the In port and the Out port, and including a plurality of serially-connected first distributed transmission line elements, and a plurality of first shunt switches each having an OFF capacitance COFF and each coupled between a respective one of the plurality of first distributed transmission line elements and a reference voltage; and
(c) at least one attenuation path coupled to the In port and the Out port, each attenuation path including a plurality of serially-connected second distributed transmission line elements, a plurality of second shunt switches each having an OFF capacitance COFF and each coupled between a respective one of the plurality of second distributed transmission line elements and the reference voltage, and at least one attenuator element serially connected to the plurality of second distributed transmission line elements;wherein the first distributed transmission line elements are configured to essentially tune out the OFF capacitances COFF of the plurality of first shunt switches and the second distributed transmission line elements are configured to essentially tune out the OFF capacitances COFF of the plurality of second shunt switches.

US Pat. No. 10,003,322

TEMPERATURE COMPENSATED DIGITAL STEP ATTENUATOR

pSemi Corporation, San D...

4. A temperature-compensated attenuator cell, including:(a) at least one shunt switch having a first-order resistance temperature coefficient of a first type;
(b) at least one shunt resistance element, each coupled to a corresponding shunt switch, and each including a first resistor having a first-order resistance temperature coefficient of a second type complementary to the first-order resistance temperature coefficient of the first type, and a second resistor coupled in parallel with the first resistor and having a first-order resistance temperature coefficient of the first type;
(c) at least one series resistance element operatively coupled to at least one shunt resistance element in an attenuation configuration and having a first-order resistance temperature coefficient of the first type; and
(d) a series switch coupled in parallel across at least one series resistance and having a first-order resistance temperature coefficient of the first type.

US Pat. No. 9,973,145

AMPLIFIER DYNAMIC BIAS ADJUSTMENT FOR ENVELOPE TRACKING

pSemi Corporation, San D...

1. A circuital arrangement comprising:an amplifier comprising:
stacked transistors having a plurality of gate terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;
an input port operatively connected to a gate terminal of an input transistor of the stacked transistors configured to receive a radio frequency (RF) signal;
an output port operatively connected to an output transistor of the stacked transistors configured to output an amplified version of the RF signal; and
a reference terminal operatively coupling the input transistor to a reference potential, wherein the stacked transistors comprise a first subset and a second subset of transistors operatively arranged in series:
a) the first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and the second subset; and
b) the second subset comprises:
i) one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to a drain terminal of the output transistor; and
ii) one or more gate capacitors, each gate capacitor of the one or more gate capacitors connected between a respective gate terminal of each transistor of the one or more transistors of the second subset and the reference potential, wherein the each gate capacitor is configured to allow a gate voltage at the respective gate terminal to vary along with a radio frequency (RF) voltage at a drain of the each transistor.

US Pat. No. 9,941,843

AMPLIFIER DYNAMIC BIAS ADJUSTMENT FOR ENVELOPE TRACKING

pSemi Corporation, San D...

1. A circuital arrangement comprising:an amplifier comprising:
stacked transistors having a plurality of gate terminals configured to operatively provide a plurality of dynamic bias voltages or currents to the stacked transistors;
an input port operatively connected to a gate terminal of an input transistor of the stacked transistors;
an output port operatively connected to an output transistor of the stacked transistors configured to output an amplified version of the RF signal;
a reference terminal operatively coupling the input transistor to a reference potential, and
a plurality of series connected resistors configured as a voltage divider coupled to the stacked transistors by way of nodes formed by two consecutive resistors of the plurality of series connected resistors,
wherein:
the stacked transistors comprise two subsets of transistors operatively arranged in series:
a) a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal; and
b) a second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable output supply bias voltage or current provided to a drain terminal of the output transistor, and
the nodes of the plurality of series connected resistors are configured to provide the dynamic bias voltages or currents to the gate terminals of the one or more transistors of the second subset.

US Pat. No. 9,921,594

LOW DROPOUT REGULATOR WITH THIN PASS DEVICE

pSemi Corporation, San D...

1. A circuit arrangement comprising:
a stack of at least two transistors arranged in a cascode configuration, comprising an input transistor and a first cascode
transistor; and

a biasing circuit configured to provide a first bias voltage to the first cascode transistor,
wherein:
a supply voltage to the stack is a varying supply voltage,
the first bias voltage is a function of the varying supply voltage and an output voltage at an output of the stack,
the varying supply voltage varies between a low supply voltage and a high supply voltage,
the output voltage is bound by a low output voltage and a high output voltage, and
a voltage gain of the biasing circuit is configured to change according to at least two conditions:
i) a first condition wherein the varying supply voltage is at the high supply voltage and the output voltage is at the low
output voltage, and

ii) a second condition wherein the varying supply voltage is at the low supply voltage and the output voltage is at the high
output voltage,

wherein the voltage gain of the biasing circuit during operation according to the first condition is higher than the voltage
gain of the biasing circuit during operation according to the second condition, the voltage gain being defined as a ratio
of the first bias voltage and the varying supply voltage.

US Pat. No. 10,148,234

DEVICE STACK WITH NOVEL GATE CAPACITOR TOPOLOGY

pSemi Corporation, San D...

1. A monolithically integrated circuital arrangement comprising:a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and N cascode transistors comprising an output transistor, N being an integer equal to or larger than two, the stack configured to operate between a supply voltage provided at a drain of the output transistor and a reference voltage provided at a source of the input transistor;
a first gate capacitor connected, at a first terminal of the first gate capacitor, to a gate of a first transistor of the N cascode transistors, and connected, at a second terminal of the first gate capacitor, to a gate of a second transistor of the N cascode transistors; and
a second gate capacitor, connected at a first terminal of the second gate capacitor, to the gate of the second transistor, and connected, at a second terminal of the second gate capacitor, to the reference voltage.

US Pat. No. 10,148,265

RADIO FREQUENCY SWITCHING CIRCUIT WITH DISTRIBUTED SWITCHES

pSemi Corporation, San D...

1. A radio frequency switching device including:(a) at least one common port;
(b) at least one field effect transistor (FET) series switch, each coupled to at least one common port;
(c) at least one terminal port;
(d) at least one transmission line, the ends of each transmission line being series coupled between a respective one of the at least one FET series switch and a respective one of the at least one terminal port, each transmission line being arrayed on an integrated circuit so as to define a first side and a second side of such transmission line; and
(e) for at least one such transmission line, at least two FET shunt switch units connected between circuit ground and such transmission line in a tuning network configuration;
wherein at least two FET shunt switch units are positioned with respect to at least one arrayed transmission line such that at least one such FET shunt switch unit is positioned adjacent the first side of such arrayed transmission line and at least one other FET shunt switch unit is positioned adjacent the second side of such arrayed transmission line, and wherein the connection to the arrayed transmission line of at least one FET shunt unit positioned on the first side of such arrayed transmission line is offset relative to the connection to the arrayed transmission line of at least one FET shunt unit positioned on the second side of such arrayed transmission line.

US Pat. No. 10,141,888

DOUBLE BALANCED MIXER

pSemi Corporation, San D...

1. A double balanced mixer fabricated as an integrated circuit and configured to be coupled to both (1) a first balun having an unbalanced side configured to pass a local oscillator (LO) signal and a pair of ports on a balanced side and (2) a second balun having an unbalanced side configured to pass a radio frequency (RF) signal and a pair of ports on a balanced side, the double balanced mixer including:a four-node ring including four branches, each branch including at least one low threshold voltage field effect transistor (FET) having a close-to-zero turn-on voltage, each FET having a source, a drain, and a gate, wherein the source of each FET is connected to the drain of a next FET in the four-node FET ring and the gate and the drain of each FET are connected together as a diode,
wherein a first pair of opposing nodes of the four-node FET ring are configured to be connected to the pair of ports on the balanced side of the first balun, and a second pair of opposing nodes of the four-node FET ring are configured to be connected through corresponding capacitors to the pair of ports on the balanced side of the second balun.

US Pat. No. 10,141,907

INTEGRATED BPF AND LNA INPUT MATCH

pSemi Corporation, San D...

1. An RF receiver comprising:a first shunt element;
a second shunt element;
a series element connected with the first shunt element and the second shunt element;
an LNA comprising a transistor being connected to a degenerative inductor at a source of said transistor and to the second shunt element at a gate of said transistor; and
a switch comprising a first end and a second end;
wherein:
the first shunt element and the second shunt element are configured to reject set out-of-band frequencies;
the series element is configured i) to pass set in-band frequencies and ii) as an impedance matching element, to match a first impedance to a second impedance;
a combination of the set in-band frequencies and the set out-of-band frequencies corresponds to one of a i) band-pass filtering mask or ii) low-pass filtering mask or iii) high-pass filtering mask;
the series element comprises a series resonator;
when the switch is in a closed state, the LNA is bypassed;
the first end is connected with a point of connection within or at the input of the series resonator, and
the second end is connected with an output of the LNA.

US Pat. No. 10,141,927

OPTIMIZED RF SWITCHING DEVICE ARCHITECTURE FOR IMPEDANCE CONTROL APPLICATIONS

pSemi Corporation, San D...

1. A switching device having open reflective unselected ports, including:(a) at least one series switch, each series switch being coupled to a common port and to an associated selectable port such that selection of at least one series switch electrically couples the common port to the selectable port associated with each such selected series switch, and decouples the common port from all unselected selectable ports; and
(b) for each series switch, an associated shuntable switch, each shuntable switch being coupled between a node and the selectable port associated with such series switch;
wherein the shuntable switch for at least one selectable port is biased in a first mode of operation to be in a constant open state regardless of the open or closed state of the associated series switch, such that the at least one selectable port is in an open reflective configuration when unselected.

US Pat. No. 10,116,272

VARIABLE IMPEDANCE MATCH AND VARIABLE HARMONIC TERMINATIONS FOR DIFFERENT MODES AND FREQUENCY BANDS

pSemi Corporation, San D...

1. An arrangement configured to receive and amplify a first signal, the arrangement comprising:an amplifier having an amplifier output terminal, wherein, during operation of the arrangement, the amplifier generates a second signal by amplifying the first signal;
a first harmonic termination arrangement comprising a first set of one or more harmonic terminations operatively connected in series;
a second harmonic termination arrangement comprising a second set of one or more harmonic terminations operatively connected in series; and
a switching arrangement;
wherein:
the switching arrangement is configured to selectively provide a conduction path of the second signal through one of the first set and the second set of one or more harmonic terminations operatively connected in series; and
each of the first set and the second set of one or more harmonic terminations is configured to resonate at a corresponding harmonic resonant frequency.

US Pat. No. 10,038,409

RF SWITCH WITH INTEGRATED TUNING

pSemi Corporation, San D...

1. A radio frequency (RF) circuital arrangement configured to receive an RF signal at an input RF receive port of the RF circuital arrangement and provide a tuned version of the RF signal at a transceiver RF receive port, comprising:an RF transceiver switch comprising a common terminal and a plurality of switching terminals,
an RF tuning circuit coupled to the common terminal of the RF transceiver switch via a first terminal of the RF tuning circuit,
a plurality of RF receive paths connected to the plurality of switching terminals of the RF transceiver switch, wherein the plurality of RF receive paths are coupled to the input RF receive port via an RF receive switch, and wherein during operation of the RF circuital arrangement, the RF receive switch is configured to selectively route the RF signal at the input RF receive port to an RF receive path of the plurality of RF receive paths, and
one or more filters in correspondence of a plurality of modes with different modulation schemes and bands of operation of the RF circuital arrangement,
wherein, during operation of the RF circuital arrangement:
the RF transceiver switch is configured to selectively couple an RF signal at a switching terminal of the plurality of switching terminals to the first terminal of the RF tuning circuit, and
the RF tuning circuit is configured to tune a characteristic of the RF signal at the first terminal of the RF tuning circuit based on the selected switching terminal and provide a tuned version of the RF signal at a second terminal of the RF tuning circuit coupled to the transceiver RF receive port,
wherein:
a conduction path of the RF signal between the input RF receive port and the transceiver RF receive port consists of a combination of reactive and resistive conduction paths and is devoid of an active device so as to maintain a frequency content of the RF signal,
the transceiver receive port is an input port of a low noise amplifier of a transceiver unit, the transceiver unit configured to down-convert the tuned version of the RF signal at an output of the low noise amplifier, and
the plurality of RF receive paths are in correspondence of the plurality of modes with different modulation schemes and bands of operation of the RF circuital arrangement.

US Pat. No. 10,153,760

RECONFIGURABLE DIRECT MAPPING FOR RF SWITCH CONTROL

pSemi Corporation, San D...

25. A circuit architecture for setting a switch state configuration of a radio frequency integrated circuit (IC) switch circuit, including a comparison circuit, configured to receive at least one programmable binary coded mapping value representing a control word bit position and to receive at least one control word intended to select a state for a corresponding mapped path selection element of the IC switch circuit, for comparing a selected decoded binary coded mapping value to a corresponding control word and setting a particular state for the corresponding mapped path selection element if the selected decoded binary coded mapping value matches a corresponding bit position value within the control word.

US Pat. No. 10,116,297

DC-COUPLED HIGH-VOLTAGE LEVEL SHIFTER

pSemi Corporation, San D...

1. A control circuit configured to control a high voltage device capable of withstanding a voltage higher than a first voltage (VIN), the control circuit comprising:low voltage transistor devices configured to operate between a first switching voltage (SW) and a second switching voltage (Vdd2+SW);
a first terminal configured to carry the first switching voltage, the first switching voltage switching between a reference voltage and the first voltage;
a second terminal configured to carry the second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and a second voltage (Vdd2) substantially lower than the first voltage;
input nodes configured to receive input timing control pulse signals;
a parallel resistive-capacitive coupling, coupled to the input nodes, configured to receive the input timing control pulse signals and transmit edge information and DC level information of the input timing control pulse signals to the low voltage transistor devices; and
an output node configured to provide an output timing control signal at a voltage higher than the first switching voltage for control of the high voltage device, the output timing control signal being based on the transmitted edge information and DC level information of the input timing control pulse signals through the parallel resistive-capacitive coupling.

US Pat. No. 10,084,415

FAST CHARGE FOR QUICK AMPLIFIER SETTLING

pSemi Corporation, San D...

1. A switching control logic comprising:a serial bus interface, the serial bus interface comprising an interface bus;
a glue logic, the glue logic comprising a fast charge (FC) bus, and
a fast charge pulse conditioning block (FCPCB), the FCPCB comprising a fast charge one shot (FCOS) bus;wherein:the glue logic is connected with the serial bus interface via the interface bus;
the glue logic is connected with the FCPCB via the FC bus, and
the FC bus is configured such that a first serial bus interface transaction will assert a signal on the FC bus, thereby generating a fast charge one shot (FCOS) pulse with a pulse width ‘T1’ on the FCOS bus, and a second serial bus interface transaction following the first serial bus interface transaction will de-assert the signal on the FC bus.

US Pat. No. 10,056,889

DELAY LINE SYSTEM AND SWITCHING APPARATUS WITH EMBEDDED ATTENUATORS

pSemi Corporation, San D...

30. A method for reducing input return loss in a monolithically integrated single pole double throw (SPDT) switch, the method comprising:providing in a conduction path between a pole terminal and a first throw terminal of the SPDT integrated switch an attenuator block comprising one or more switches and one or more shunting resistors;
based on the providing, selecting a resistance value of the one or more shunting resistors based on an ON resistance of the one or more switches and a desired load impedance at the first throw terminal;
based on the selecting, decreasing an impedance value seen at the first throw terminal; and
based on the decreasing, substantially matching the impedance value seen at the first throw terminal to the desired load impedance, thereby reducing the input return loss at the first throw terminal.

US Pat. No. 10,027,224

CHARGE PUMP STABILITY CONTROL

pSemi Corporation, San D...

1. An apparatus comprising a switching-network and a control system to control switches in said switching network to cause a set of pump capacitors to cycle through different arrangements of pump capacitors in said set, wherein each cycle begins with an initial arrangement and ends with a final arrangement, wherein said switching network has a terminal connected to a circuit that includes an inductor, wherein, at the start of a first cycle, said pump capacitors are in a state and wherein, at the start of a subsequent cycle that follows said first cycle, said capacitors have been restored to said state, wherein said state corresponds to an extent to which each of said capacitors in said set of pump capacitors is charged.

US Pat. No. 9,960,736

CONTROL SYSTEMS AND METHODS FOR POWER AMPLIFIERS OPERATING IN ENVELOPE TRACKING MODE

pSemi Corporation, San D...

1. A system for affecting operation of an envelope tracking (ET) amplifier, comprising:an ET amplifier configured to receive an RF input signal at an input terminal of the ET amplifier and generate therefrom, at an output terminal of the ET amplifier, an RF output signal based on a response of the ET amplifier; and
a set of operating parameters defining the response of the ET amplifier;
a control circuit adapted to detect an envelope of the RF input signal and generate based on said envelope signal a set of input-control signals that is provided to the ET amplifier for affecting the response according to the set of operating parameters, wherein at least two input-control signals of the set of input-control signals are bound by a mathematical relationship comprising at least one of: a) scaling, b) amplitude shifting, c) phase shifting, and d) inverting.

US Pat. No. 10,128,864

NON-LINEAR CONVERTER TO LINEARIZE THE NON-LINEAR OUTPUT OF MEASUREMENT DEVICES

pSemi Corporation, San D...

1. A non-linear converter comprising:a non-linear voltage divider having a plurality of resistors representing a non-linear transfer function;
an analog multiplexer having analog multiplexer inputs coupled to said non-linear voltage divider and configured to output an analog multiplexer output based on a logic signal and said non-linear transfer function;
an analog comparator having an analog comparator first input configured to receive an analog input voltage, an analog comparator second input configured to receive said analog multiplexer output and the analog comparator configured to output a comparator voltage output; and
a logic loop coupled to said analog comparator and configured to receive said comparator voltage output and configured to output said logic signal, wherein said logic signal represents a linearized digital word.

US Pat. No. 10,115,787

LOW LEAKAGE FET

pSemi Corporation, San D...

1. A FET fabricated on a silicon-on-insulator substrate, including:(a) an isolated silicon island;
(b) a gate structure overlying the isolated silicon island and having a center length L, the gate structure having central and edge regions each with an associated work function ?MF
(c) source and drain regions within the isolated silicon island and defined by the gate structure;
(d) a central conduction channel between the source and drain regions, the central conduction channel having a threshold voltage VtC; and
(e) at least one edge transistor defined by a corresponding edge region of the gate structure overlying the isolated silicon island, each edge transistor having a threshold voltage VtE determined in part by the work function ?MF of the corresponding edge region of the gate structure;wherein the work function ?MF of at least one corresponding edge region of the gate structure is increased sufficiently to increase the VtE of such corresponding edge transistor to be approximately equal to or greater than VtC.

US Pat. No. 10,097,232

APPARATUS FOR REDUCING RF CROSSOVER COUPLING

pSemi Corporation, San D...

1. A monolithically integrated 4-port switch, comprising:four ports, each adapted to carry a radio frequency (RF) signal with a frequency content that is within a frequency range from DC to 50 GHz;
a plurality of separate switchable conduction paths, each selectively, and independently from any other conduction path of the plurality of switchable conduction paths, connecting and disconnecting respective two ports of the four ports so that any port of the four ports is adapted to be selectively connected to any other port of the four ports by way of a single conduction path of the plurality of switchable conduction paths, the plurality of switchable conduction paths comprising:
i) four peripheral switchable conduction paths, each devoid of a crossing path with a different conduction path of the plurality of switchable conduction paths; and
ii) two crossing switchable conduction paths crossing one another at a central region of symmetry of the 4-port switch by way of a single crossover structure, and each devoid of a crossing path with a different conduction path of the plurality of switchable conduction paths,
wherein each switchable conduction path of the plurality of switchable conduction paths:
a) is configured to selectively operate in one of an ON state and an OFF state, the ON state providing a low impedance path between the respective two ports of the each switchable conduction path, and the OFF state providing a high impedance path between the respective two ports,
b) in the ON state, provides an insertion loss between the respective two ports that is smaller than 3.5 dB at the frequency range, and
c) in the OFF state, provides an isolation between the respective two ports, and between any of the respective two ports and any of the remaining ports of the four ports, that is greater than 40 dB at the frequency range.

US Pat. No. 10,084,443

DC-COUPLED HIGH-VOLTAGE LEVEL SHIFTER

pSemi Corporation, San D...

1. A control circuit configured to control a high voltage device capable of withstanding a voltage higher than a first voltage (VIN), the control circuit comprising:low voltage transistor devices configured to operate between a first switching voltage (SW) and a second switching voltage (Vdd2+SW);
a first terminal configured to carry the first switching voltage, the first switching voltage switching between a reference voltage and the first voltage;
a second terminal configured to carry the second switching voltage as a function of the first switching voltage, the second switching voltage substantially corresponding to a sum of the first switching voltage and a second voltage (Vdd2) substantially lower than the first voltage;
input nodes configured to receive input timing control pulse signals;
a parallel resistive-capacitive coupling, coupled to the input nodes, configured to receive the input timing control pulse signals and transmit edge information and DC level information of the input timing control pulse signals to the low voltage transistor devices; and
an output node configured to provide an output timing control signal at a voltage higher than the first switching voltage for control of the high voltage device, the output timing control signal being based on the transmitted edge information and DC level information of the input timing control pulse signals through the parallel resistive-capacitive coupling.

US Pat. No. 9,991,889

HIGH THROW-COUNT RF SWITCH

pSemi Corporation, San D...

1. A high throw-count multiple-pole RF switch including:(a) a common port;
(b) at least two series-coupled sections, each section including at least one branch, each branch including at least two corresponding signal ports, each signal port coupled to the corresponding branch by an independently selectable switching element; and
(c) at least one branch isolation switch, each branch isolation switch connected between corresponding adjacent sections;
wherein when a selected signal port is coupled to the common port, any branch isolation switches between the selected signal port and the common port are configured in a conducting state and all other branch isolation switches are configured in a blocking state.

US Pat. No. 9,915,963

METHODS FOR ADAPTIVE COMPENSATION OF LINEAR VOLTAGE REGULATORS

pSemi Corporation, San D...

1. A low drop out voltage regulator (LDO) configured to receive an input voltage at an input terminal and to output an output
voltage to an output terminal, comprising:
(i) a feedback circuit configured to generate a feedback voltage as a function of the output voltage;
(ii) an operational amplifier configured to receive a reference voltage and the feedback voltage, and to generate an error
signal based on a combination of the feedback voltage and the reference voltage;

(iii) a first transistor configured to receive the error signal and to generate a corresponding load current; and
(iv) a tracking circuit;
wherein:
(a) the output terminal is connectable to a load, the load comprising a load resistance and a load capacitance;
(b) a ratio of a regulated output voltage to the input voltage has a transfer function comprising a load pole and a zero,
wherein:

(b1) the load pole is a function of a combination of the load resistance and the load capacitance; and
(b2) the zero is a function of the load capacitance and an equivalent series resistance of the load capacitance; and
(c) the tracking circuit is configured to adjust the zero to track movements of the load pole due to variations of the load
current.

US Pat. No. 9,917,613

FINE AND COARSE PHASE AND AMPLITUDE CONTROL

pSemi Corporation, San D...

1. A digitally controlled circuit for selectively altering at least one of phase of an applied radio frequency (RF) signal
and attenuation of the applied RF signal, the digitally controlled circuit providing (1) excess full range coverage for at
least one of phase shifting and attenuation, and (2) at least one fine range for at least one of phase shifting and attenuation
that is greater than the LSB of the corresponding next coarser range for phase shifting or attenuation.

US Pat. No. 10,187,013

STACKED PA POWER CONTROL

pSemi Corporation, San D...

1. A method for controlling an output power of an amplifier arrangement, the method comprising:providing a stack of a plurality of transistors arranged in a cascode configuration, comprising an input transistor and one or more cascoded transistors, the one or more cascoded transistors comprising an output transistor;
providing a gate voltage control module;
coupling voltage control nodes of the gate voltage control module to gates of the one or more transistors of the stack;
supplying a supply voltage across the stack;
based on the coupling, providing gate voltages to the one or more cascoded transistors;
inputting a constant envelope radio frequency (RF) signal to the input transistor;
based on the inputting, obtaining an amplified RF signal at the output transistor;
varying, independently from the supply voltage, at least one gate voltage of the gate voltages to the one or more cascoded transistors; and
based on the varying, controlling the output power of the amplified RF signal,
wherein a voltage control node of coupled voltage control nodes of the gate voltage control module is configured to provide the at least one gate voltage, and
wherein a control voltage to the gate voltage control module varies the at least one gate voltage for controlling of the output power of the amplified RF signal.

US Pat. No. 10,184,973

MISMATCH DETECTION USING REPLICA CIRCUIT

pSemi Corporation, San D...

1. A circuital arrangement, comprising:a sensing circuit;
a first radio frequency (RF) path coupled, through one or more sensing points of the first RF path, to the sensing circuit, the first RF path comprising a first active circuit; and
at least one second RF path coupled, through one or more sensing points of the second RF path in correspondence of the one or more sensing points of the first RF path, to the sensing circuit, the second RF path comprising a second active circuit, the second active circuit being a reduced size replica of the first active circuit,
wherein the sensing circuit is adapted to sense a difference between one or more operating characteristics of the first RF path, sensed at the one or more sensing points of the first RF path, and one or more reference operating characteristics of the second RF path, sensed at corresponding one or more sensing points of the second RF path.

US Pat. No. 10,172,231

METHODS AND APPARATUS FOR REDUCING RF CROSSOVER COUPLING

pSemi Corporation, San D...

15. An integrated circuit comprising:a first non-conductive layer;
a first metal layer overlying the first non-conductive layer, the first metal layer comprising:
i) a ground return region of a substantially symmetrical shape with respect to a centerline of the ground return region, isolated from a remaining portion of the first metal layer;
ii) a first transmission line of a substantially symmetrical shape with respect to the centerline, formed within the ground return region, separated from the ground return region by a fixed distance gap along a length of the first transmission line; and
iii) a second transmission line of a substantially symmetrical shape with respect to the centerline, formed within the ground return region, the second transmission line comprising a first segment and a last segment collinear with the first segment, the first segment and the last segment separated from the ground return region by the fixed distance gap along the length of the first and last segments, the first segment and the last segment separated from one another at a middle region of the second transmission line;
a second non-conductive layer overlying the first metal layer; and
a second metal layer comprising a middle segment of the second transmission linecollinear with the first and last segments and electrically connected to the first and last segments through vias formed in the second non-conductive layer,
wherein:
the first transmission line and the second transmission line cross at the middle region of the second transmission line to form a symmetrical crossing pattern with respect to the centerline, and
the integrated circuit further comprises:
a third non-conductive layer overlying the first metal layer and separating the first metal layer and the second non-conductive layer; and
a third metal layer overlying the third non-conductive layer and separating the third non-conductive layer and the second non-conductive layer, the third metal layer comprising a ground shield region isolated from a remaining portion of the third metal layer, the ground shield region having a symmetrical geometry with respect to the centerline of the ground return region, the ground shield region comprising:
a) a center region comprising two crossing lines crossing at the centerline of the ground return region, the crossing lines defining a symmetrical crossing pattern of the center region comprising four extremes away from the centerline; and
b) four regions of a substantially same geometry each connected to one of the four extremes of the symmetrical crossing pattern of the center region, wherein:
the four regions are electrically connected to the ground return region through vias formed in the third non-conductive layer, and
projection of each of the four regions onto the ground return region clears regions of the first and the second transmission lines and corresponding fixed distance gap regions.

US Pat. No. 10,153,767

SWITCH CIRCUIT AND METHOD OF SWITCHING RADIO FREQUENCY SIGNALS

pSemi Corporation, San D...

1. An RF switching circuit comprising:(a) a switch transistor grouping having a first switch node and a second switch node;
(b) a shunt transistor grouping having a first shunt node coupled with the second switch node and a second shunt node coupled with a reference voltage;
(c) a control logic configured to output a first control signal and a second control signal; and
(d) a negative voltage generator coupled with the control logic, the negative voltage generator being configured to generate a negative power supply voltage with respect to the reference voltage;
wherein:
(i) the switch transistor grouping has a control switch node configured to receive the first control signal;
(ii) the shunt transistor grouping has a control shunt node configured to receive the second control signal; and
(iii) the RF switching circuit is fabricated as a monolithic integrated circuit.

US Pat. No. 10,141,910

INTEGRATED AND COMBINED PHASE SHIFTER AND ISOLATION SWITCH

pSemi Corporation, San D...

1. A digitally-controlled phase shifter, including:(a) at least two phase shift signal paths, each coupled to first and second ports, for providing a phase shift to a signal applied to at least one of the first and second ports and responsive to a corresponding independent path selection control signal for selectively independently enabling communication of the applied signal from the first port to the second port through the corresponding phase shift signal path when not in an isolation mode, and disabling communication of the applied signal from the first port to the second port through the corresponding phase shift signal path when in the isolation mode; and
(b) at least one selectable termination circuit, each operatively coupled to a corresponding one of the first or second ports, and responsive to a distinct isolation circuit control signal for isolating the first port from the second port in the isolation mode.

US Pat. No. 10,128,745

CHARGE BALANCED CHARGE PUMP CONTROL

pSemi Corporation, San D...

1. An apparatus for coupling to capacitors to form a charge pump circuit, said apparatus comprising a first set of switch elements, a controller circuit, and a second set of switch elements, wherein said switch elements are coupled to said controller circuit, wherein said controller circuit is configured to cause said switch elements to cycle through a sequence of states, each of which defines a corresponding switch-element configuration, wherein said first set of switch elements comprises switch elements that are configured to couple terminals of capacitor elements to permit charge transfer between said capacitor elements, wherein said second set of switch elements comprises switch elements that are configured to couple terminals of at least some of said capacitor elements to a first terminal, wherein at least three of said states define different configurations of said switch elements, each of which permits charge transfer between a pair of elements, wherein said first terminal is selected from the group consisting of a high-voltage terminal and a low-voltage terminal, wherein said pair of elements is selected from the group consisting of a first capacitor and a second capacitor and a first capacitor and said first terminal, wherein said configured cycle of states provides a voltage conversion between said high-voltage terminal and said low-voltage terminal, and wherein said controller circuit is configured to maintain each state for a corresponding duration of a fraction of a charge pump cycle time, wherein said durations of said states are selected to maintain a balanced charging and discharging of each of said capacitors through said sequence of states of each cycle.

US Pat. No. 10,050,616

DEVICES AND METHODS FOR IMPROVING VOLTAGE HANDLING AND/OR BI-DIRECTIONALITY OF STACKS OF ELEMENTS WHEN CONNECTED BETWEEN TERMINALS

pSemi Corporation, San D...

1. An integrated circuit block comprising:a first node;
a second node;
a series arrangement of one or more capacitive elements; and
a series arrangement of three or more switches;
wherein:
the one or more capacitive elements are in series with the three or more switches regardless of states of switches of the three or more switches;
a combination of the one or more capacitive elements and the three or more switches is coupled between the first node and the second node;
the three or more switches are configured to withstand a voltage greater than a voltage withstood by one switch;
the three or more switches are configured to receive a control signal to enable or disable the switches and thereby adjusting the capacitance between the two nodes, and
compensation capacitive elements are coupled across at least one of the three or more switches.

US Pat. No. 9,935,678

BROADBAND POWER LIMITER

pSemi Corporation, San D...

1. A broadband power limiter circuit having a distributed architecture, the broadband power limiter circuit including:(a) a plurality of limiter segments, each limiter segment comprising a stack of one or more self-activating power limiters, each limiter segment separated from an adjacent limiter segment by an associated intermediate matching inductor, each limiter segment configured to initiate limiting of at least one of power, voltage, or current of a signal applied to such limiter segment only when such power, voltage, or current exceeds a set threshold for such limiter segment;
(b) a first terminal coupled to a first end one of the plurality of limiter segments; and
(c) a second terminal coupled to a second end one of the plurality of limiter segments;
wherein the first terminal, the second terminal, and the combined plurality of limiter segments and associated intermediate matching inductors comprise a signal line.

US Pat. No. 10,109,537

ELECTRICALLY TESTABLE MICROWAVE INTEGRATED CIRCUIT PACKAGING

pSemi Corporation, San D...

1. A method for fabricating and testing a microwave integrated circuit, including:(a) flip-chip assembling a plurality of integrated circuit dies on a thin-film tile provisioned with probe-compatible connection pads such that the probe-compatible connection pads are accessible after assembly for connection to probes;
(b) automatically testing at least some of the plurality of dies through the probe-compatible connection pads; and
(c) singulating at least some of the plurality of the dies and corresponding segments of the tile into die/tile assemblies.

US Pat. No. 10,110,166

LNA WITH VARIABLE GAIN AND SWITCHED DEGENERATION INDUCTOR

pSemi Corporation, San D...

1. An amplifier including:(a) a plurality of amplifier branches;
(b) a plurality of branch control switches, each branch control switch coupled to a corresponding amplifier branch;
(c) a degeneration module including:
(1) a degeneration inductor having at least one tap; and
(2) at least one degeneration switch having a first terminal coupled to a corresponding one of the taps and a second terminal coupled to ground;
wherein the degeneration switches have a control input and wherein the amplifier further includes a gain control module having at least one switch control output, each switch control output coupled to the control input of a corresponding one of the degeneration switches.

US Pat. No. 10,083,947

MULTI-LAYER POWER CONVERTER WITH DEVICES HAVING REDUCED LATERAL CURRENT

pSemi Corporation, San D...

1. An apparatus comprising a power-converter circuit, said power-converter circuit comprising an interconnection, a first layer, and a second layer, wherein said first and second layers are constituent layers of a stack of layers, wherein said first layer has a device face and a device-free face, wherein a first set of devices is disposed on said device face thereof, wherein said second layer has a device face and a device-free face, wherein said second layer comprises a second set of devices disposed on said device face thereof, wherein said interconnection is configured to enable said devices disposed on said device face of said first layer to be interconnected with said devices disposed on said device face of said second layer, wherein said interconnection comprises a thru via extending through at least one of said first layer and said second layer, and wherein said first layer and said second layer are wafer-bonded to each other.

US Pat. No. 10,056,874

POWER AMPLIFIER SELF-HEATING COMPENSATION CIRCUIT

pSemi Corporation, San D...

1. A compensation circuit configured to monitor a target circuit having one or more performance parameters affected by self-heating during operation of the target circuit, wherein the compensation circuit is configured to be coupled to and adjust one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating during operation of the target circuit on the one or more performance parameters, the compensation circuit including:(a) at least one sensor located with respect to the target circuit so as to measure the temperature T of the target circuit and generate an output signal representing such temperature T;
(b) at least one tracking circuit, each coupled to at least one sensor, configured to capture a temperature T(t=t0) at a time t0 after the commencement of operation of the target circuit, and to sample a temperature T(t>t0) at times after time t0 and during operation of the target circuit, the at least one tracking circuit including:
(1) a differential amplifier having a first input coupled to the output signal of a corresponding sensor, a second input, and an output representing the difference between signals applied to the first input and the second input; and
(2) a storage capacitor coupled to the second input of the differential amplifier and selectively coupled to the differential amplifier output;
wherein:
(A) in a first phase, the output of the differential amplifier is coupled to the storage capacitor and to the second input of the differential amplifier at least at time t0, such that a charge on the capacitor represents an initial temperature T(t=t0); and
(B) in a second phase, the output of the differential amplifier is uncoupled from the storage capacitor and represents the difference AT between (i) the output signal of the corresponding sensor coupled to the first input and representing the temperature T(t>t0), and (ii) the storage capacitor charge coupled to the second input and representing the temperature T(t=t0); and
(c) a correction circuit, coupled to at least one tracking circuit, for generating a correction signal as a function of AT from the coupled at least one tracking circuit, the correction signal being configured to be coupled to and adjust the one or more circuit parameters of the target circuit sufficient to substantially offset the effect of self-heating during operation of the target circuit on the one or more performance parameters.

US Pat. No. 9,991,973

INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE

pSemi Corporation, San D...

1. A radio frequency (RF) integrated circuit including:(a) a primary RF transmission path;
(b) a primary RF reception path;
(c) at least one RF transceiver front-end circuit, each selectively connectable through a multi-way switch complex to the primary RF transmission path and the primary RF reception path;
(d) at least one switchable internal calibration path coupled to the at least one RF transceiver front-end circuit and configured to convey, in a calibration mode, an RF test signal from the primary RF transmission path through the multi-way switch complex and thence through at least a portion of the coupled at least one RF transceiver front-end circuit to the primary RF reception path; and
(e) at least one inter-chip switch for providing selectable access from external to the integrated circuit to at least one of the primary RF transmission path, the primary RF reception path, and/or the at least one switchable internal calibration path.

US Pat. No. 10,211,801

HYBRID COUPLER WITH PHASE AND ATTENUATION CONTROL

pSemi Corporation, San D...

1. A hybrid coupler with phase and attenuation control, including:(a) a hybrid coupler having an RF input port, an RF output port, a first termination port, and a second termination port; (b) a first parallel resistance-reactance circuit coupled between the first termination port and RF ground, wherein the resistance-reactance circuit includes a resistor connected directly between the first termination port and RF ground; and (c) a second parallel resistance-reactance circuit coupled between the second termination port and RF ground, wherein the second resistance-reactance circuit includes a resistor connected directly between the second termination port and RF ground.

US Pat. No. 10,210,118

SERIAL-BUS INTERFACE FOR MULTI-DIE MODULE

pSemi Corporation, San D...

1. A circuit module for housing a plurality of integrated circuits (ICs) while presenting a single unique address to a system control/status serial bus, including:(a) an internal module serial bus configured to be coupled to the system control/status serial bus;
(b) a primary IC having at least one addressable control register and a control/status interface coupled to the internal module serial bus; and
(c) at least one secondary IC, each having at least one addressable control register and a control/status interface coupled to the internal module serial bus in parallel with the control/status interface of the primary IC;
wherein the primary IC and each secondary IC respond to control commands received through the internal module serial bus from the system control/status serial bus that correspond to a unique addressable control register within the primary IC or the secondary IC, and wherein only the primary IC responds to status requests received through the internal module serial bus from the system control/status serial bus, and each secondary IC is configured to not respond to status requests.

US Pat. No. 10,210,130

SERIAL-BUS INTERFACE FOR MULTI-DIE MODULE

pSemi Corporation, San D...

1. A circuit module for housing a plurality of integrated circuits (ICs) while presenting a single unique address to a system control/status serial bus, including:(a) an internal module serial bus configured to be coupled to the system control/status serial bus;
(b) a primary IC having at least one addressable control register and a control/status interface coupled to the internal module serial bus, and a pass-through interface coupled to the control/status interface of the primary IC; and
(c) a first secondary IC having at least one addressable control register and a control/status interface coupled to the pass-through interface of the primary IC;
wherein the primary IC and the first secondary IC respond to control commands received through the internal module serial bus from the system control/status serial bus that correspond to a unique addressable control register within the primary IC or the first secondary IC, and wherein only the primary IC responds to status requests received through the internal module serial bus from the system control/status serial bus.

US Pat. No. 10,193,531

DIGITAL STEP ATTENUATOR

pSemi Corporation, San D...

1. An electronic digital step attenuator circuit for selectively attenuating an applied signal, including:(a) a first signal port for receiving the applied signal, and a second signal port for conveying the applied signal;
(b) a plurality of binary-weighted selectable attenuator cells serially coupled between the first and second signal ports, each binary-weighted attenuator cell providing a bypass state and at least one selectable attenuation state and having a stack of series-connected field effect transistors (FETs) having a series stack size equal to a count of the series-connected FETs of the binary-weighted attenuator cell; and
(c) a plurality of thermometer-weighted selectable attenuator cells serially coupled between the first and second signal ports and serially coupled to the plurality of binary-weighted attenuator cells, each thermometer-weighted attenuator cell providing a bypass state and at least one selectable attenuation state and having a stack of series-connected FETs having a series stack size equal to a count of the series-connected FETs of the thermometer-weighted attenuator cell;
wherein the series stack size of at least one of the thermometer-weighted selectable attenuator cells is configured to withstand a maximum power level of the applied signal, and remaining thermometer-weighted selectable attenuator cells include smaller series stack sizes configured to withstand only an attenuated signal having a power level less than the maximum power level of the applied signal, wherein a total of the series stack sizes of the thermometer-weighted selectable attenuator cells is configured to reduce an overall insertion loss for the electronic digital step attenuator circuit.

US Pat. No. 10,193,441

DC-DC TRANSFORMER WITH INDUCTOR FOR THE FACILITATION OF ADIABATIC INTER-CAPACITOR CHARGE TRANSPORT

pSemi Corporation, San D...

1. An apparatus for power transformation, said apparatus comprising a power converter, said power converter comprising a charge pump, a first regulator, and a magnetic filter, wherein said magnetic filter is connected to a terminal of said charge pump, wherein said terminal is selected to facilitate adiabatic inter-capacitor charge transport within said charge pump, and wherein said first regulator is configured to regulate power provided by said power converter.

US Pat. No. 10,181,819

STANDBY VOLTAGE CONDITION FOR FAST RF AMPLIFIER BIAS RECOVERY

pSemi Corporation, San D...

1. A circuital arrangement comprising:a transistor stack configured to operate as an amplifier, the transistor stack comprising a plurality of stacked transistors comprising an input transistor and an output transistor, the transistor stack configured to operate between a first supply voltage coupled to the output transistor and a reference voltage coupled to the input transistor; and
a biasing circuit comprising a replica circuit of the transistor stack, the biasing circuit configured to provide an input gate biasing voltage to the input transistor and to a corresponding first transistor of the replica circuit, the replica circuit configured to operate between a second supply voltage coupled to a last transistor of the replica circuit in correspondence of the output transistor, and the reference voltage coupled to the first transistor;
wherein the circuital arrangement is configured to operate in at least a first mode and a second mode,
wherein during operation in the first mode, the biasing circuit:
couples the last transistor of the replica circuit to the second supply voltage through a reference current source that generates a reference current, and
regulates the input gate biasing voltage so as the reference current is conducted through the replica circuit, and
wherein during operation in the second mode, the biasing circuit:
sets the input gate biasing voltage to a voltage so as essentially no current is conducted though the replica circuit,
deactivates the reference current source, and
couples the last transistor of the replica circuit to the second supply voltage.

US Pat. No. 10,181,823

INTEGRATED ULTRA-COMPACT VSWR INSENSITIVE COUPLER

pSemi Corporation, San D...

1. A radio frequency (RF) power amplifier circuit including:(a) a final amplifier stage having (1) an input and (2) an output with a first output impedance, for amplifying an RF signal applied to the input and providing forward power at the output;
(b) an output impedance matching network (IMN) having an IMN input, an IMN output, for matching the first output impedance to a second output impedance;
(c) at least one coupler situated between the final amplifier stage and the output IMN, for coupling a portion of the forward power, as coupled forward power, to a selected port, each coupler including:
(1) an input port electrically connected to the output of the final amplifier stage;
(2) an output port electrically connected to the IMN input;
(3) a first inductor electrically connected between the input port and the output port, the first inductor including a coupling segment that is shorter than the first inductor;
(4) a coupled port electrically connected to a second inductor, and capacitively and inductively coupled to the input port through interaction of the second inductor with the coupling segment of the first inductor, wherein the coupled port is the selected port;
(5) an isolated port electrically connected to the coupled port by the second inductor, and capacitively and inductively coupled to the output port through interaction of the second inductor with the coupling segment of the first inductor;
(6) a first terminating impedance coupled to the isolated port; and
(7) a second terminating impedance coupled to the coupled port;
wherein the first inductor is electrically shared with the output IMN, the second inductor is shorter than the first inductor and defines the length of the coupling segment of the first inductor, and the first output impedance has a characteristic value that is substantially less than the characteristic value of the second output impedance.

US Pat. No. 10,181,631

COMPACT LOW LOSS SIGNAL COUPLER

pSemi Corporation, San D...

1. A bi-directional radio frequency (RF) coupler configuration, including:(a) a first coupler having an input port, a coupled port, an isolated port, an output port, and a first polarity;
(b) a second coupler having an input port, a coupled port, an isolated port, an output port, and a second polarity opposite the first polarity;
(c) an electrical connection between the output port of the first coupler and the output port of the second coupler; and
(d) at least one tuning element connected between a common potential and at least one of the coupled port and/or the isolated port of the first coupler and/or of the second coupler;
wherein a portion of energy from a first RF signal applied to the input port of the first coupler is available at the coupled port of the first coupler and essentially absent at the coupled port of the second coupler, and a portion of energy from a second RF signal applied to the input port of the second coupler is available at the coupled port of the second coupler and essentially absent at the coupled port of the first coupler.

US Pat. No. 10,177,895

SYSTEMS AND METHODS FOR MINIMIZING INSERTION LOSS IN A MULTI-MODE COMMUNICATIONS SYSTEM

pSemi Corporation, San D...

1. A circuital arrangement comprising a multifunctional filter, wherein:the circuital arrangement is configurable to operate in a first mode based on a first filtering function of the multifunctional filter for propagation of a first type of signal through the circuital arrangement,
the circuital arrangement is configurable to operate in a second mode based on a second filtering function of the multifunctional filter for propagation of a second type of signal through the circuital arrangement, the second mode providing a lower insertion loss upon the second type of signal than the first mode, and
configuration of the circuital arrangement to operate in one of the first mode and the second mode is respectively based on a configuration of the multifunctional filter to operate according to the first filtering function and the second filtering function,
wherein the multifunctional filter comprises:
a plurality of independently selectable serial filter components, a plurality of independently selectable shunt filter components, a plurality of parallel switches connected in parallel with the plurality of independently selectable serial filter components and a plurality of serial switches connected in serial with the plurality of independently selectable shunt filter components.

US Pat. No. 10,177,715

FRONT END MODULE WITH INPUT MATCH CONFIGURABILITY

pSemi Corporation, San D...

1. A front end module (FEM), including:(a) a first FEM input;
(b) an output selector switch having a plurality of switch inputs, the first of the plurality of switch inputs coupled to the first FEM input, the output selector switch further having a switch output, the switch output being selectively coupled to one of the plurality of switch inputs;
(c) a switchable tank circuit having a first and second terminal, the first terminal coupled to the first FEM input; and
(d) an amplifier having an amplifier input and an amplifier output, the amplifier input coupled to the second terminal of the tank circuit and the amplifier output coupled to a second of the plurality of switch inputs.

US Pat. No. 10,171,075

HIGH SPEED AND HIGH VOLTAGE DRIVER

pSemi Corporation, San D...

1. A high speed high voltage (HSHV) open drain driver comprising:a main stack of N transistors of a first type coupled between a reference voltage and an output node of the HSHV driver, the N transistors comprising a first transistor as an input transistor of the HSHV open drain driver and an Nth transistor as an output transistor of the HSHV open drain driver, N being an integer equal to or greater than three;
a biasing circuit configured to provide biasing voltages to the main stack, the biasing circuit comprising a biasing stack of N?1 transistors of a second type;
wherein:
a gate node of the first transistor of the main stack is coupled to a drain node of a first transistor of the biasing stack,
gate nodes of a second to the (N?1)th transistor of the main stack are coupled to respective N?2 common source-drain nodes of the transistors of the biasing stack,
a gate node of the Nth transistor of the main stack is coupled to a source node of the (N?1)th transistor of the biasing stack,
N?1 common source-drain nodes of transistors of the main stack are coupled to respective N?1 gate nodes of transistors of the biasing stack,
the output node is a drain node of the output transistor of the main stack of transistors adapted to be coupled to a high voltage by way of a pull-up element, and
transistors of the main stack and the biasing stack have operating voltages substantially smaller than the high voltage.

US Pat. No. 10,171,076

INDEPENDENT CONTROL OF BRANCH FETS FOR RF PERFORMANCE IMPROVEMENT

pSemi Corporation, San D...

1. A switch circuit including:(a) at least two switching branches, each switching branch including:
(1) at least two gateway switches configured to be connected to respective external circuit elements;
(2) a common node coupled to the at least two gateway switches; and
(3) a shunt circuit connected to the common node and programmatically settable to selectively isolate such switching branch independently of any other switching branch.

US Pat. No. 10,153,763

METHOD AND APPARATUS FOR USE IN IMPROVING LINEARITY OF MOSFETS USING AN ACCUMULATED CHARGE SINK

pSemi Corporation, San D...

1. A Radio Frequency (RF) switching method comprising the steps of:providing an RF input port;
configuring the RF input port to receive an RF signal;
providing an RF output port;
providing a switch transistor grouping having a first node and second node;
coupling the first node of the switch transistor grouping to the RF input port;
coupling the second node of the switch transistor grouping to the RF output port;
providing a shunt transistor grouping having a first node and a second node, the shunt transistor grouping comprising one or more accumulated charge control N-type MOSFETs (ACC N-MOSFET) wherein each of the one or more ACC-NMOSFETs comprises:
a gate, drain, source and a gate oxide layer, where the gate oxide layer is positioned between the gate and a body; and
an accumulated charge sink (ACS) region connected to the body;
coupling the first node of the shunt transistor grouping to the RF input port;
coupling the second node of the switch transistor grouping to ground;
in a first state:
(a) enabling the switch transistor grouping and disabling the shunt transistor grouping thereby passing the RF input signal from the RF input port to the RF output port;
(b) biasing each of the one or more ACC-MOSFETs to operate in an accumulated charge regime;
(c) for each of the one or more ACC N-MOSFETs: applying a bias voltage, to the ACS region to control or to remove accumulated charge from the body via the ACS region, wherein the bias voltage is negative with respect to ground, the drain and the source;
in a second state:
(d) enabling the shunt transistor grouping and disabling the switch transistor grouping, thereby isolating the RF input port from the RF output port.

US Pat. No. 10,147,740

METHODS AND STRUCTURES FOR REDUCING BACK GATE EFFECT IN A SEMICONDUCTOR DEVICE

pSemi Corporation, San D...

1. A silicon on insulator (SOI) structure comprising:a silicon substrate configured to be coupled to a reference potential;
a buried oxide (BOX) layer overlying the silicon substrate;
a thin silicon layer overlying the BOX layer;
a first circuit formed in a first silicon region of the thin silicon layer, the first circuit configured to be coupled to a first potential;
a second circuit formed in a second silicon region of the thin silicon layer, the second circuit configured to be coupled to a second potential different from the first potential;
at least one N-type implant formed in a region of the silicon substrate underlying a local silicon region of one of the first and the second silicon region of the silicon substrate, and comprising a surface region of the silicon substrate proximate the local silicon region; and
at least one through BOX contact (TBC) resistively coupling the local silicon region to the at least one N-type implant,
wherein:
a potential difference between the first potential and the reference potential is equal to or larger than 10 V, and a potential difference between the second potential and the reference potential is equal to or smaller than 3 V,
the local silicon region comprises one or more transistors sensitive to a back gate effect, and
the TBC is configured to bias the N-type implant to a potential substantially equal to one of the first potential and the second potential coupled to the local silicon region, thereby reducing the back gate effect over the one or more transistors.

US Pat. No. 10,148,255

LOW NOISE CHARGE PUMP METHOD AND APPARATUS

pSemi Corporation, San D...

1. Charge pump apparatus for generating a low noise output voltage supply within a circuit, comprising:a) a transfer capacitor having an input terminal and an output terminal;
b) a plurality of transfer capacitor coupling switches, each switchable between a conducting state and a nonconducting state under control of a single-phase clock signal, the plurality of transfer capacitor coupling switches including at least:
(1) a first transfer capacitor coupling switch coupled between the input terminal of the transfer capacitor and a voltage source;
(2) a second transfer capacitor coupling switch coupled between the input terminal of the transfer capacitor and a common reference;
(3) a third transfer capacitor coupling switch coupled between the output terminal of the transfer capacitor and a voltage output terminal; and
(4) a fourth transfer capacitor coupling switch coupled between the output terminal of the transfer capacitor and the common reference; and
c) a charge pump clock generating circuit generating the single-phase clock signal coupled to control switching of at least the first and second transfer capacitor coupling switches, the charge pump clock generating circuit including a ring oscillator comprising an odd number of inverting driver sections cascaded sequentially in a ring such that each driver section has an output coupled to a next driver section input, wherein a first driver section is next after a last driver section and one of the driver section outputs constitutes the single-phase clock signal, and wherein each driver section includes active limiting circuitry configured with circuit values that limit a rate of rise of voltage and a rate of fall of voltage at the output of such driver section so as to cause the clock signal to have a substantially sine-like shape;wherein the plurality of transfer capacitor coupling switches are controlled so as to couple the input terminal of the transfer capacitor to the voltage source during periodic first times, and to couple the output terminal of the transfer capacitor to the voltage output terminal during periodic second times that are not concurrent with the first times, and wherein the third and fourth transfer capacitor coupling switches are passive switches.

US Pat. No. 10,236,836

TUNED AMPLIFIER MATCHING BASED ON BAND SWITCH SETTING

pSemi Corporation, San D...

1. A radio frequency (RF) circuital arrangement configured to process an RF signal for operation over a plurality of frequency bands, the circuital arrangement comprising:a configurable amplifier configured to be tuned according to any one of the plurality of frequency bands, the configurable amplifier comprising one or more tunable elements for tuning of the configurable amplifier;
a band switch configured to selectively couple the configurable amplifier to a filter of a plurality of narrow band filters based on a switch control signal provided to the band switch, and
a mapping circuit that is configured to map data values of the switch control signal to data values of configuration control signals for tuning of the one or more tunable elements,
wherein the plurality of narrow band filters are respectively associated, in a one to one correspondence, to the plurality of frequency bands; and
wherein a tuning of the configurable amplifier is based on the switch control signal.

US Pat. No. 10,236,863

PROGRAMMABLE VOLTAGE VARIABLE ATTENUATOR

pSemi Corporation, San D...

11. A programmable voltage variable attenuator, configured to be coupled to an applied control voltage, for continuously varying the attenuation of a radio frequency signal applied to the programmable voltage variable attenuator, including:(a) a first voltage controlled variable resistance series element, configured be coupled to an applied series variable voltage derived from the applied control voltage, and configured to receive an applied radio frequency signal;
(b) a second voltage controlled variable resistance series element, series-connected to the first voltage controlled variable resistance series element and configured be coupled to the applied series variable voltage, for outputting an attenuated radio frequency signal;
(c) a voltage controlled variable resistance shunt element coupled between the first and second voltage controlled variable resistance series elements and circuit ground, and configured to be coupled to an applied shunt variable voltage derived from the applied control voltage, for continuously varying the attenuation of the applied radio frequency signal in response to the applied control voltage; and
(d) at least two impedance control loop circuits, each selectably connectable to the programmable voltage variable attenuator and each corresponding to a different characteristic impedance, for maintaining a selected corresponding attenuation level as a function of the applied control voltage for a corresponding different characteristic impedance.

US Pat. No. 10,236,872

AC COUPLING MODULES FOR BIAS LADDERS

pSemi Corporation, San D...

1. A FET switch stack, including:(a) a plurality of series-coupled FETs, including a first end FET having a first signal terminal and a second end FET having a second signal terminal;
(b) a gate bias resistor ladder coupled to the gates of the series-coupled FETs and configured to be coupled to a gate control voltage that controls the ON or OFF switch state of each series-coupled FET; and
(c) an AC coupling gate module coupled to at least one end of the gate bias resistor ladder and configured to be coupled to a radio frequency voltage source;
wherein in response to the OFF switch state of each series-coupled FET, a signal applied to the first or second signal terminal is blocked from conduction through the plurality of series-coupled FETs, and wherein in response to the ON switch state of each series-coupled FET, a signal applied to the first or second signal terminal is conducted through the plurality of series-coupled FETs.

US Pat. No. 10,205,439

DIGITAL STEP ATTENUATOR WITH REDUCED RELATIVE PHASE ERROR

pSemi Corporation, San D...

1. A digital step attenuator (DSA) cell comprising:a) an input port;
b) an output port;
c) a first control input port;
d) a first resistive element having a first end and a second end;
e) a first switch element having an input, an output and a control, the input being coupled to the input port and the output being coupled to the output port and the control being coupled to the first control input port;
f) a first inductive coupling having an inductance and a first end and a second end, the first end coupled to the input port, the second end coupled to the first end of the first resistive element;
g) a second inductive coupling having an inductance and a first end and a second end, the first end of the second inductive coupling coupled to the output port and the second end of the second inductive coupling coupled to the second end of the first resistive element;wherein the inductances of the first and second inductive couplings are selected to result in a reduction in the difference in relative phase in the signal output by the DSA cell respect to the signal applied to the input of the DSA cell from the difference that would present in the output signal were the inductances not presented.

US Pat. No. 10,199,996

OPTIMIZED MULTI-LNA SOLUTION FOR WIDEBAND AUXILIARY INPUTS SUPPORTING MULTIPLE BANDS

pSemi Corporation, San D...

1. A low noise amplifier integrated circuit (LNAIC) comprising:a first low noise amplifier (LNA) having an input and an output;
a second LNA having an input and an output;
a first input select switch having at least two inputs, at least one input being an auxiliary (AUX) input, the input select switch configured to couple at least one of the inputs to the first LNA input; and
an second input select switch having at least two inputs, including at least one AUX input, the second input select switch configured to couple at least one of the inputs to the second LNA input;
wherein the AUX input of the first select switch is coupled to the AUX input of the second select switch.

US Pat. No. 10,200,026

HIGH POWER HANDLING SWITCH USING REDUCED OPERATING IMPEDANCE

pSemi Corporation, San D...

1. A switch network comprising:(a) at least one switch control input;
(b) a first impedance transformation network having an external terminal and an internal terminal, the external terminal of the first impedance transformation network presenting a first relatively high impedance and the internal terminal of the first impedance transformation network presenting a second relatively low impedance;
(c) a second impedance transformation network having an external terminal and an internal terminal, the external terminal of the second impedance transformation network presenting a third relatively high impedance and the internal terminal of the second impedance transformation network presenting a fourth relatively low impedance;
(d) a third impedance transformation network having an external terminal and an internal terminal, the external terminal of the third impedance transformation network presenting a fifth relatively high impedance and the internal terminal of the third impedance transformation network presenting a sixth relatively low impedance;
(e) a first through switch having a first and second signal terminal and having a control terminal, the first signal terminal coupled to the internal terminal of the first impedance transformation network, the second signal terminal coupled to the internal terminal of the second impedance transformation network and the control terminal coupled to at least a first switch control input;
(f) a second through switch having a first and second signal terminal and having a control terminal, the first signal terminal of the second through switch being coupled to the first signal terminal of the first through switch, the second signal terminal of the second through switch being coupled to the internal terminal of the third impedance transformation network and the control terminal of the second through switch being coupled to at least a second switch control input.

US Pat. No. 10,192,884

BUTTED BODY CONTACT FOR SOI TRANSISTOR

pSemi Corporation, San D...

1. A semiconductor structure comprising:a first gate polysilicon structure defining a first body region, the first body region having a first conductivity type;
a second gate polysilicon structure defining a second body region, the second body region having the first conductivity type;
a first drain region adjacent to the first body region having a second conductivity type;
a first source region adjacent to the first body region having the second conductivity type;
a second source region adjacent to the second body region having the second conductivity type;
a second drain region adjacent to the second body region having the second conductivity type,
the first source region and the second drain region defining a first common source/drain region having the second conductivity type;
a first non-conductive isolation region configured to form an interruption in the second body region to divide the second body region in two separate second body regions;
at least one first body contact region of the first conductivity type formed within the first common source/drain region separate from the first and the second body regions and abutting the first non-conductive isolation region; and
at least one first body tab of the first conductivity type extending across the first common source/drain region in contact with the first body region and the at least one first body contact region,
wherein the first non-conductive isolation region, the at least one first body contact region and the at least one first body tab define a first butted body tie structure.

US Pat. No. 10,181,850

HIGH THROW-COUNT RF SWITCH

pSemi Corporation, San D...

1. A high throw-count multiple-pole RF switch including:(a) a common path;
(b) a common port coupled to the common path;
(c) a plurality of sections each containing at least one signal port coupled to the common path through a series-shunt switching element; and
(d) at least one isolation switch connected to the common path between two adjacent sections;wherein when a selected signal port is coupled to the common port, any isolation switches between the selected signal port and the common port are configured in a conducting state and all other isolation switches are configured in a blocking state.

US Pat. No. 10,162,376

CHARGE PUMP WITH TEMPORALLY-VARYING ADIABATICITY

pSemi Corporation, San D...

1. An apparatus comprising a switched-capacitor charge pump configured to provide voltage conversion between first and second terminals thereof, a compensation circuit coupled to a first terminal of said charge pump, said compensation circuit having a first configuration and a second configuration, wherein, in said first configuration, said first terminal of said charge pump couples to a capacitance, wherein, in said second configuration, said capacitance is decoupled from said first terminal of said charge pump, and a controller coupled to said charge pump and said compensation circuit, said controller comprising an output for configuring said compensation circuit, and a first sensor input for accepting a first sensor-signal that, at least in part, characterizes operation of a circuit selected from the group consisting of said charge pump and a peripheral circuit directly coupled to said charge pump, wherein said controller is configured to configure said compensation circuit based at least in part on said first sensor-signal to promote efficiency of power conversion between a power source coupled to said charge pump and a load coupled to said charge pump via said compensation circuit.

US Pat. No. 10,256,287

FLOATING BODY CONTACT CIRCUIT METHOD FOR IMPROVING ESD PERFORMANCE AND SWITCHING SPEED

pSemi Corporation, San D...

1. An electronic circuit including:(a) at least one field effect transistor (FET), each FET including:
(1) a gate, a drain, a source, and a body;
(2) a gate resistor series connected to the gate of such FET;
(3) an accumulated charge sink (ACS) diode circuit connected to the body of such FET; and
(4) an ACS resistance series connected to the ACS diode circuit, wherein the series-connected ACS resistance and the ACS diode circuit are connected to the gate resistor of such FET at a node opposite to the connection of the gate resistor to the gate, and the ACS resistance is sized to provide substantial ESD tolerance without substantially impairing the function of the ACS diode circuit; and
(b) at least one electrostatic discharge (ESD) protection electronic circuit, each ESD protection electronic circuit including:
(1) a selectable resistor coupled in series between a common control terminal for at least one FET and the gate resistor of at least one FET; and
(2) a bypass module coupled in parallel with the selectable resistor and having a control signal input for receiving a control signal, the bypass module being configured to respond to the control signal to (A) in a bypass mode, conduct signals applied to the coupled common control terminal through the bypass module and around the selectable resistor, and (B) in a protection mode, cause signals applied to the coupled common control terminal to be conducted through the selectable resistor, wherein in the bypass mode, the bypass module presents no significant added resistance, relative to the gate resistor of the at least one coupled FET, to signals applied to the coupled common control terminal.

US Pat. No. 10,250,339

INTEGRATED CIRCUIT CALIBRATION ARCHITECTURE

pSemi Corporation, San D...

1. A radio frequency (RF) integrated circuit including:(a) a primary RF transmission path;
(b) a primary RF reception path;
(c) at least one RF transceiver front-end circuit, each selectively connectable to the primary RF transmission path and the primary RF reception path; and
(d) at least one switchable internal calibration path selectively configurable between the primary RF transmission path and the primary RF reception path to convey, in a calibration mode, a test signal from the primary RF transmission path to the primary RF reception path through at least a portion of at least one RF transceiver front-end circuit undergoing calibration;
wherein at least one RF transceiver front-end circuit includes at least one of a phase-attenuation core or an input/output circuit.

US Pat. No. 10,250,131

LOW-NOISE HIGH EFFICIENCY BIAS GENERATION CIRCUITS AND METHOD

pSemi Corporation, San D...

1. A charge pump having a plurality of transfer control switches (“TCSwitches”) coupled to one or more transfer capacitors, such that in a first state of the TCSwitches charge is transferred from an input supply to a transfer capacitor, and in a second state of the TCSwitches charge is transferred from the transfer capacitor to an output supply, the charge pump including a charge pump clock whose output controls the switches, the charge pump clock being a ring oscillator comprising:a plurality of ring oscillator inverter stages coupled together in a ring whereby each inverter stage has an input coupled to an output of an immediately preceding inverter stage and an output coupled to an input of an immediately subsequent inverter stage;wherein:the charge pump clock output is substantially sine-like, and
a transfer control switch of the plurality of transfer control switches comprises:
a transistor coupled, by way of a first node of the transistor, to a transfer capacitor of the one or more transfer capacitors, and capacitively coupled, by way of a second node of the transistor, to the charge pump clock; and
an active biasing resistor coupled, by way of a first node of the active biasing resistor, to a biasing voltage node adapted to carry a biasing voltage, and coupled, by way of a second node of the active biasing resistor, to the second node of the transistor,
wherein more average current flows from the first node to the second node of the active biasing resistor when an average voltage of the first node is greater than an average voltage of the second node, but
current does not flow between the first node and second node of the active biasing circuit during significant portions of a cyclic waveform appearing between the first and second nodes.

US Pat. No. 10,250,199

CASCODE AMPLIFIER BIAS CIRCUITS

pSemi Corporation, San D...

1. An amplifier circuit including:(a) a cascode amplifier having at least two serially connected field effect transistor (FET) stages, each FET stage having a gate, a drain, and a source, the bottom FET stage having an input configured to be coupled to an RF input signal to be amplified, and the top FET stage of the cascode amplifier having an output for providing an amplified RF input signal;
(b) a cascode reference circuit having at least two serially connected FET stages, each FET having a gate, a drain, and a source, the gates of the bottom two FET stages of the cascode reference circuit being coupled to the corresponding gates of the bottom two FET stages of the cascode amplifier, for biasing the cascode amplifier to output a final current approximately equal to a multiple of a mirror current in the cascode reference circuit;
(c) a closed loop bias control circuit, having at least one input coupled to the cascode reference circuit and an output coupled to the gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit, responsive to variations in voltage and/or current in the cascode reference circuit to output an adjustment gate bias voltage applied to the respective gates of the bottom FET stage of the cascode amplifier and of the cascode reference circuit that forces the mirror current in the cascode reference circuit to be approximately equal to a selected current value; and
(d) a respective decoupling network coupled between corresponding gates of each of the bottom two FET stages of the cascode amplifier, wherein at least one decoupling network includes a programmable resistance element for varying bias levels to the coupled gates.

US Pat. No. 10,243,519

BIAS CONTROL FOR STACKED TRANSISTOR CONFIGURATION

pSemi Corporation, San D...

1. A circuital arrangement comprising:i) an amplifier comprising:
stacked transistors having a plurality of bias terminals comprising a plurality of gate terminals of the stacked transistors and a drain terminal of an output transistor of the stacked transistors;
an input port operatively connected to an input transistor of the stacked transistors;
an output port operatively connected to the drain terminal of the output transistor; and
a reference terminal operatively coupling the input transistor to a reference potential, wherein:
the stacked transistors comprise two subsets of transistors operatively arranged in series, a first subset comprising the input transistor operatively connected between the reference potential at the reference terminal and a second subset, the second subset comprising one or more transistors operatively connected in series with each other, at least one transistor of the one or more transistors being the output transistor, the second subset operatively connected between the first subset and a variable supply voltage provided to the output transistor; and
ii) a gate bias circuit,
wherein:
the gate bias circuit is configured to operatively provide at a gate terminal of each transistor of the one or more transistors of the second subset a bias voltage, the bias voltage comprising:
a) a dynamic bias voltage which is a function of the variable supply voltage when a voltage value of the variable supply voltage is above a predetermined value associated to the each transistor, the dynamic bias voltage configured to control the each transistor to operate in its saturation region of operation; and
b) a fixed bias voltage when the voltage value of the variable supply voltage is below the predetermined value associated to the each transistor, the fixed bias voltage configured to control the each transistor to operate in its triode region of operation in a top to down sequence so that the output transistor operates in its triode region of operation first, followed by a transistor of the one or more transistors of the second subset connected to the top transistor, and ending with a transistor of the one or more transistors of the second subset connected to the input transistor.