US Pat. No. 9,209,809

CIRCUITS FOR AND METHODS OF CONTROLLING OUTPUT SWING IN A CURRENT-MODE LOGIC CIRCUIT

XILINX, INC., San Jose, ...

1. A circuit for controlling output swing in a current-mode logic circuit, the circuit comprising:
a plurality of current-mode logic circuits coupled in series;
a first current-mode logic circuit of the plurality of current-mode logic circuits coupled to provide a signal to a second
current-mode logic circuit of the plurality of current-mode logic circuits;

a plurality of amplitude detectors, wherein each amplitude detector is coupled to a corresponding current-mode logic circuit
of the plurality of current-mode logic circuits;

a selection circuit coupled to outputs of the plurality of amplitude detectors, wherein an output of an amplitude detector
of the plurality of amplitude detectors is selected; and

a control circuit coupled to the selection circuit to receive the selected output, wherein the control circuit generates an
amplitude control signal for controlling an output swing of a current-mode logic circuit of the plurality of current-mode
logic circuits based upon the detected amplitude of the selected output.

US Pat. No. 9,348,959

OPTIMIZING SUPPLY VOLTAGE AND THRESHOLD VOLTAGE

XILINX, INC., San Jose, ...

1. A method for determining or configuring supply voltage and threshold voltage for a design implementation of a given electronic
design, comprising:
determining, from a set of supply voltage-threshold voltage combinations, a first subset of supply voltage-threshold voltage
combinations that meet timing requirements for the design implementation;

using a processor to determine amounts of power consumption of the design implementation for the first subset of the supply
voltage-threshold voltage combinations;

selecting a supply voltage-threshold voltage combination from the first subset of supply voltage-threshold voltage combinations
having a lowest determined amount of power consumption;

determining a first body bias voltage value and a second bias body voltage value that provide the threshold voltage of the
selected supply voltage-threshold voltage combination on a programmable IC; and

storing a bitstream in a configuration memory, the bitstream configured to:
cause a first regulator to regulate a supply voltage of the programmable integrated circuit (IC) using the supply voltage
of the selected supply voltage-threshold voltage combination;

cause a second regulator to regulate a first body bias voltage of the programmable IC using the first body bias voltage value;
and

cause a third regulator to regulate a second body bias voltage of the programmable IC using the second body bias voltage value.

US Pat. No. 9,083,340

MEMORY MATRIX

XILINX, INC., San Jose, ...

1. An integrated circuit comprising a memory matrix, the memory matrix comprising:
a first memory cell array;
a first multiplexer (MUX) coupled to an input of the first memory cell array;
a second MUX coupled to an output of the first memory cell array;
a second memory cell array;
a third MUX coupled to an input of the second memory cell array; and
a fourth MUX coupled to an output of the second memory cell array;
wherein the second MUX is coupled to the fourth MUX, the fourth MUX configured to pass a selected one of: (1) an output from
the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX.

US Pat. No. 9,065,482

CIRCUIT FOR FORWARD ERROR CORRECTION ENCODING OF DATA BLOCKS

XILINX, INC., San Jose, ...

1. A method for encoding N symbols of a sequence in parallel using an R parity symbol encoding algorithm, comprising operating
at least one circuit that performs operations of:
adding a first symbol matrix including symbols 1 through L of the N symbols to a first parity matrix over a finite field to
produce a first intermediate matrix, the first parity matrix including parity symbols calculated from a first set of symbols
of the sequence that precedes the N symbols in the sequence, wherein N=L+M;

multiplying the first intermediate matrix by at least a first coefficient matrix and a second coefficient matrix over the
finite field to produce a second intermediate matrix, the first coefficient matrix including a first respective set of constants
for each one of L coefficients of an R-coefficient code generation polynomial, and the second coefficient matrix including
a respective set of constants for each one of M coefficients of the R-coefficient code generation polynomial;

multiplying a second symbol matrix by at least the second coefficient matrix to produce a third intermediate matrix, the second
symbol matrix including M symbols that immediately follow the L symbols in the sequence;

adding at least the second and third intermediate matrices to produce a second parity matrix; and
outputting a codeword, including the N symbols of the sequence and the second parity matrix, for forward error correction,
wherein N?4.

US Pat. No. 9,436,785

HIERARCHICAL PRESET AND RULE BASED CONFIGURATION OF A SYSTEM-ON-CHIP

XILINX, INC., San Jose, ...

1. A method, comprising:
receiving a user input selecting a first circuit block of a system-on-chip for enablement;
determining, using a processor, a first top level preset according to the user input for the first circuit block;
determining selected intermediate presets from a plurality of hierarchically ordered presets for the first circuit block;
automatically determining low level presets for the first circuit block according to the selected intermediate presets for
the first circuit block; and

configuring the system-on-chip by loading control register values specified by the low level presets into a control register
of a processor system of the system-on-chip.

US Pat. No. 9,355,696

CALIBRATION IN A CONTROL DEVICE RECEIVING FROM A SOURCE SYNCHRONOUS INTERFACE

XILINX, INC., San Jose, ...

1. A control device for receiving from a source synchronous interface having a data bus and a source clock, the control device
comprising:
a data path comprising a data delay unit coupled to a data input of a sampling circuit;
a clock path comprising a clock delay unit coupled to a clock input of the sampling circuit;
a multiplexing circuit operable to selectively couple a reference clock or the data bus to an input of the data delay unit,
and selectively couple the reference clock or the source clock to an input of the clock delay unit; and

a calibration unit coupled to a data output of the sampling circuit, the calibration unit operable to adjust delay values
of the data delay unit and the clock delay unit based on the data output of the sampling circuit to establish and maintain
a relative delay between the data path and the clock path.

US Pat. No. 9,337,841

CIRCUITS FOR AND METHODS OF PROVIDING VOLTAGE LEVEL SHIFTING IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. A circuit for providing voltage level shifting, the circuit comprising:
an inverter having an input coupled to receive an input signal having a first voltage level;
an output stage having a first transistor coupled in series with a second transistor, and an output node between the first
transistor and the second transistor generating an output signal having a second voltage level;

wherein a gate of the second transistor is coupled to an output of the inverter;
a pull-up transistor coupled between a reference voltage having the second voltage level and a gate of the first transistor;
and

a switch coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the
gate of the first transistor, wherein:

the first transistor comprises a first p-channel transistor;
the second transistor comprises a first n-channel transistor; and
the switch comprises a second p-channel transistor coupled in parallel with a second n-channel transistor.

US Pat. No. 9,839,159

DISPENSE PATTERN FOR THERMAL INTERFACE MATERIAL FOR A HIGH ASPECT RATIO THERMAL INTERFACE

XILINX, INC., San Jose, ...

1. A method, comprising: applying thermal interface material to a first thermal interface element that forms an interface
area having a rectangular aspect ratio with a second thermal interface element, wherein the first thermal interface element
has thermal interface material applied thereto, the thermal interface material being laid out in a dual star-shaped pattern
that includes two star-shaped patterns of thermal interface material laid out in a longer direction of the interface area
such that respective local centers of the two star-shaped patterns are disposed on a common axis that is parallel to the longer
direction and wherein the thermal interface material for both of the two start-shaped patterns extends to a midline which
is disposed on the interface area that is perpendicular to the common axis.

US Pat. No. 9,323,457

MEMORY ARRANGEMENT FOR IMPLEMENTATION OF HIGH-THROUGHPUT KEY-VALUE STORES

XILINX, INC., San Jose, ...

1. A circuit for processing data, the circuit comprising:
an input for receiving a request for implementing a key-value store data transaction that enables access to a store associated
with a key;

a plurality of memory interfaces associated with different memory types enabling access to a plurality of memory devices associated
with a key-value store;

a first memory device of a first type storing a first portion of a value of a store associated with the key-value store data
transaction;

a second memory device of a second type storing a second portion of the value of the store associated with the key-value store
data transaction, wherein the second portion of the value of the store associated with the key-value store data transaction
is different than the first portion of the value of the store associated with the key-value store data transaction; and

a memory management circuit controlling the routing of data by way of the plurality of memory interfaces based upon a data
transfer criterion.

US Pat. No. 9,337,138

CAPACITORS WITHIN AN INTERPOSER COUPLED TO SUPPLY AND GROUND PLANES OF A SUBSTRATE

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a first integrated circuit die and a second integrated circuit die;
an interposer coupled to the first integrated circuit die and the second integrated circuit die using a first plurality of
interconnects, the interposer including an upper surface having at least one open space between the first integrated circuit
die and the second integrated circuit die, the interposer including a lower surface having a second plurality of interconnects,
the interposer including a first cross-sectional region beneath the first integrated circuit die and the second integrated
circuit die and a second cross-sectional region beneath the at least one open space, the first and second cross-sectional
regions being disjoint, the second cross-sectional region being devoid of any through substrate vias extending between the
upper surface and the lower surface;

a substrate coupled to the interposer using the second plurality of interconnects;
wherein the substrate includes a supply voltage plane and a ground plane each of which is coupled to the first integrated
circuit die using the second plurality of interconnects, the interposer, and the first plurality of interconnects;

wherein the interposer includes a plurality of capacitors entirely disposed in the second cross-sectional region, the plurality
of capacitors coupled in parallel using the supply voltage plane, the ground plane, and the second plurality of interconnects;
and

wherein the plurality of capacitors of the interposer provide capacitance to the first integrated circuit die using the supply
voltage plane and the ground plane of the substrate.

US Pat. No. 9,331,701

RECEIVERS AND METHODS OF ENABLING THE CALIBRATION OF CIRCUITS RECEIVING INPUT DATA

XILINX, INC., San Jose, ...

1. A data interface enabling the calibration of circuits receiving input data, the data interface comprising:
a first data receiver having a first plurality of input data lines coupled to receive a corresponding first plurality of data
bits associated with a data bus, the first data receiver having a first control circuit enabling a calibration of the first
plurality of input data lines; and

a second data receiver having a second plurality of input data lines coupled to receive a corresponding second plurality of
data bits associated with the data bus, the second data receiver having a second control circuit enabling a calibration of
the second plurality of input data lines;

wherein the first plurality of input data lines of the first data receiver are calibrated in parallel with the second plurality
of input data lines of the second data receiver; and

wherein the first data receiver receives a first local reference clock signal.

US Pat. No. 9,178,552

CHANNEL ADAPTIVE RECEIVER SWITCHABLE FROM A DIGITAL-BASED RECEIVER MODE TO AN ANALOG-BASED RECEIVER MODE

XILINX, INC., San Jose, ...

1. A method for channel adaptation, comprising:
receiving an analog input signal with a bimodal receiver via a communications channel;
converting the analog input signal to a digital input signal with an analog-to-digital converter of a digital receiver of
the bimodal receiver;

detecting channel coefficients for the digital input signal associated with the communications channel;
wherein the channel coefficients indicate a number of post-cursor taps of the bimodal receiver to be used to provide an equalized
digital output signal from the digital input signal;

determining whether the number of post-cursor taps or a value associated therewith is equal to or less than a threshold number;
and

switching from the receiving of the analog input signal by the digital receiver to an analog receiver of the bimodal receiver
to provide the equalized digital output signal for the analog input signal.

US Pat. No. 9,177,944

SEMICONDUCTOR DEVICE WITH STACKED POWER CONVERTER

XILINX, INC., San Jose, ...

1. A semiconductor device, comprising:
a first integrated circuit (IC) die having solder bumps; and
a second IC die mounted on the first IC die, the second IC die having an active side and a backside opposite the active side,
the second IC die including bond pads on the active side configured for wire-bonding, and solder bumps disposed on a backside
opposite the active side, the second IC die including at least one power converter circuit receiving an input from a bond
pad of the bond pads by way of a first wire bond, the input having a first voltage and a first current, the second IC die
having through-die vias (TDVs) extending between the active side and the backside;

wherein the solder bumps of the first IC die are electrically and mechanically coupled to the solder bumps of the second IC
die to form bump bonds, wherein the at least one power converter circuit provides, responsive to the input, an output having
a second voltage and a second current to the first IC die by way of the TDVs of the second IC die and the bump bonds, and
wherein the second current is greater than the first current;

wherein the first IC die includes bond pads that are configured for wire bonding, and a second wire bond electrically couples
a bond pad of the bond pads of the first IC die to a substrate to provide power to the first IC die having a third current
that is a lower current than the second current; and

wherein the second IC die further includes an inductor formed on the backside and coupled to the TDVs.

US Pat. No. 9,325,277

VOLTAGE CONTROLLED OSCILLATOR INCLUDING MUGFETS

XILINX, INC., San Jose, ...

1. A voltage-controlled oscillator, comprising:
an inductor having a tap and having or coupled to a positive-side output node and a negative side output node, wherein the
tap is configured to receive a first current;

a coarse grain capacitor array coupled to the positive-side output node and the negative side output node and configured to
respectively receive select signals;

a varactor coupled to the positive-side output node and the negative side output node and configured to receive a control
voltage;

wherein the varactor includes first MuGFETs;
a transconductance cell coupled to the positive-side output node and the negative side output node and having a common node;
and

a frequency scaled resistor network coupled to the common node and configured to receive the select signals for a resistance
for a path for a second current;

wherein:
cells of the coarse grain capacitor array are spaced apart from one another as coupled to the positive-side output node and
the negative side output node;

the cells are progressively spaced away from a coil of the inductor; and
the cells are configured to respectively receive the select signals.

US Pat. No. 9,048,860

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
an analog-to-digital converter (“ADC”) configured for successive approximations;
wherein the ADC comprises a digital-to-analog converter (“DAC”), a comparator, and a control block;
wherein the DAC is coupled to receive a first reference input signal and a feedback input signal to provide an analog output
signal;

wherein the analog output signal is capacitively coupled to an analog input node through a capacitor;
wherein the analog input node is coupled through a switch to sample an analog input signal;
wherein the capacitor is coupled between an output port of the DAC and a first input port of the comparator to provide capacitive
coupling therebetween;

wherein the first input port of the comparator is further coupled to the analog input node;
wherein a second input port of the comparator is coupled to receive a second reference input signal;
wherein the comparator is coupled to provide a comparator output signal to the control block;
wherein the control block is configured for successive approximations to provide a digital output signal to a digital output
node; and

wherein the DAC is coupled to the digital output node to receive the digital output signal as the feedback input signal.

US Pat. No. 9,356,556

CIRCUITS FOR AND METHODS OF IMPLEMENTING A DUAL-MODE OSCILLATOR

XILINX, INC., San Jose, ...

1. A circuit for implementing a dual-mode oscillator, the circuit comprising:
a first oscillator portion having a first inductor coupled in parallel with a first capacitor between a first node and a second
node;

a first pair of output nodes coupled to the first and second nodes;
a second oscillator portion inductively coupled to the first oscillator portion, the second oscillator portion having a second
inductor coupled in parallel with a second capacitor between a third node and a fourth node;

a second pair of output nodes coupled to the third and fourth nodes; and
a control circuit coupled to enable a supply of current to either the first oscillator portion in a first mode or the second
oscillator portion in a second mode;

wherein the first capacitor and the second capacitor are programmable to enable a selection of a ratio of the capacitances
of the first capacitor and the second capacitor so that a phase of the dual-mode oscillator crosses a zero phase line only
once;

and wherein the selection of the ratio of the capacitances of the first capacitor and the second capacitor enables operation
of the dual mode oscillator in both the first mode and the second mode.

US Pat. No. 9,348,750

CIRCUIT FOR AND METHOD OF REALIGNING DATA AT A RECEIVER

XILINX, INC., San Jose, ...

1. A circuit for realigning data received at a receiver, the circuit comprising:
a plurality of memory arrays, each memory array having a predetermined data width;
a plurality of multiplexers responsive to selection signals associated with a shift value, wherein each multiplexer is coupled
to select an address comprising a current address or a previous address for data to be output by a memory array of the plurality
of memory arrays based upon the shift value indicating data of the previous address which is to be simultaneously output with
data of the current address;

an output multiplexer coupled to select an order of the outputs of the plurality of memory arrays as a single output word
based upon the selected addresses, wherein the outputs of the plurality of memory arrays are provided in an order based upon
the shift value; and

a memory control circuit coupled to the plurality of multiplexers and the output multiplexer, the memory control circuit coupling
select signals to the plurality of multiplexers and the output multiplexer to enable generating realigned data comprising
the outputs of the predetermined data width from each memory array of the plurality of memory arrays.

US Pat. No. 9,111,675

STACKED INDUCTOR STRUCTURE

XILINX, INC., San Jose, ...

1. An inductor implemented in an integrated circuit, the inductor comprising:
a plurality of loops of the inductor in at least a first metal layer, a second metal layer, and a third metal layer of a plurality
of metal layers, the inductor extending from a first terminal in the first metal layer to a second terminal in the first metal
layer; and

a plurality of vias connecting ends of loops of the plurality of loops in different metal layers;
wherein each loop of the first metal layer which is connected to a corresponding loop of the second metal layer overlies the
corresponding loop of the second metal layer; and

wherein the inductor comprises an outer coil having a first plurality of loops extending from the first metal layer to the
third metal layer, an inner coil having a second plurality of loops extending from the third metal layer to the second metal
layer, and a loop positioned within the inner coil in the third metal layer and having a first end connected to a loop of
the second plurality of loops in the second metal layer and a second end connected to the second terminal in the first metal
layer, the loop positioned within the inner coil in the third metal layer having a size which is smaller than a size of the
loops of the second plurality of loops.

US Pat. No. 9,325,489

DATA RECEIVERS AND METHODS OF IMPLEMENTING DATA RECEIVERS IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A data receiver implemented in an integrated circuit, the data receiver comprising:
an input receiving a data signal;
a phase locked loop configured to generate a reference clock signal;
a first equalization circuit configured to receive the data signal, wherein the first equalization circuit is used to receive
data of the data signal;

a first register coupled to an output of the first equalization circuit;
a first phase interpolator configured to receive the reference clock signal, wherein the first phase interpolator is configured
to control the first register using a first clock signal;

a second equalization circuit configured to receive the data signal;
a second register coupled to an output of the second equalization circuit; and
a second phase interpolator configured to receive the reference clock signal, wherein the second phase interpolator is configured
to control the second register using a second clock signal that is different than the first clock signal, wherein the first
clock signal is generated separately from the second clock signal, and wherein the second phase interpolator enables adjusting
a clock phase offset associated with drifting of the reference clock signal;

wherein the second equalization circuit is different than the first equalization circuit; and
wherein the first phase interpolator enables a first function of said controlling the first register using the first clock
signal while the second phase interpolator enables a second function of said adjusting the clock phase offset using the second
clock signal.

US Pat. No. 9,312,586

SYSTEM AND METHOD FOR REDUCING EFFECTS OF SWITCHED CAPACITOR KICKBACK NOISE

XILINX, INC., San Jose, ...

1. A circuit, comprising:
a first input terminal;
a first transmission line;
a first sampling switch coupled to the first input terminal through the first transmission line;
a first sampling capacitor coupled to the sampling switch; and
a first open-circuit quarter wavelength stub coupled to the first transmission line, the first open-circuit quarter wavelength
stub configured to reduce kickback noise on the first transmission line, wherein a length of the first open-circuit quarter
wavelength stub is tuned to a first frequency associated with the kickback noise on the first transmission line.

US Pat. No. 9,167,058

TIMESTAMP CORRECTION IN A MULTI-LANE COMMUNICATION LINK WITH SKEW

XILINX, INC., San Jose, ...

1. A method for correcting for skew in a multi-lane communication link having a plurality of lanes, comprising:
receiving a data packet, a time stamp for the data packet and a fill level for a lane of the plurality of lanes that is carrying
the data packet;

calculating a corrected timestamp for the data packet as a function of at least the time stamp, the fill level, and a reference
fill level that is derived from respective fill levels for all of the plurality of lanes;

replacing the time stamp for the data packet with the corrected timestamp; and
assembling a plurality of packets including the data packet in a prescribed order in a buffer, using the corrected timestamp,
wherein the plurality of packets is received over the plurality of lanes.

US Pat. No. 9,054,096

NOISE ATTENUATION WALL

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
an interposer having a plurality of first vias;
a plurality of first interconnects and a plurality of second interconnects respectively coupled on opposite surfaces of the
interposer;

wherein a first portion of the plurality of first interconnects and a second portion of the plurality of first interconnects
are spaced apart from one another defining an isolation region therebetween;

a substrate having a plurality of second vias;
a plurality of third interconnects and the plurality of second interconnects respectively coupled on opposite surfaces of
the substrate; and

wherein a first portion of the plurality of first vias and a first portion of the plurality of second vias are both in the
isolation region and are coupled to one another with a first portion of the plurality of second interconnects;

wherein each of the plurality of second vias of the first portion thereof extend to each of the opposite surfaces of the substrate
and each of the plurality of second vias of the first portion thereof are coupled to one another within the substrate.

US Pat. No. 9,412,674

SHIELDED WIRE ARRANGEMENT FOR DIE TESTING

XILINX, INC., San Jose, ...

1. An integrated circuit, comprising:
a passive die comprising a conductive layer;
wherein the conductive layer comprises a data wire, a first power supply wire of a first voltage potential, and a second power
supply wire of a second voltage potential different from the first voltage potential;

wherein a segment of the data wire is located between, and substantially parallel to, a segment of the first power supply
wire and a segment of the second power supply wire;

wherein the first power supply wire is coupled to a first probe structure and the second power supply wire is coupled to a
second probe structure;

wherein the passive die is configured as a common mounting surface for a plurality of dies and to electrically couple the
plurality of dies using the first power supply wire, the second power supply wire, and the data wire; and

wherein the passive die is configured for detecting short circuits between the first power supply wire, the second power supply
wire, and the data wire.

US Pat. No. 9,343,418

SOLDER BUMP ARRANGEMENTS FOR LARGE AREA ANALOG CIRCUITRY

XILINX, INC., San Jose, ...

1. An integrated circuit, comprising:
an analog region of a die of the integrated circuit comprising analog circuitry; and
a plurality of solder bumps implemented on a surface of the die in an area in vertical alignment with the analog region of
the die;

wherein the plurality of solder bumps comprises:
a first column of solder bumps with constant spacing; and
a second column of solder bumps parallel to the first column of solder bumps;
wherein the second column of solder bumps is offset from the first column of solder bumps in a direction parallel to the second
column of solder bumps; and

wherein vertical spacing between adjacent solder bumps in the second column varies nonlinearly with an increasing vertical
offset that doubles between consecutive pairs of solder bumps in the second column.

US Pat. No. 9,313,078

PULSE CANCELLATION CREST FACTOR REDUCTION WITH A LOW SAMPLING RATE

XILINX, INC., San Jose, ...

1. A method for data transmission, comprising:
detecting by a peak detector a signal peak of an input signal exceeding a threshold amplitude;
wherein the detecting comprises sampling the input signal at a sampling frequency to provide a sampled signal, the sampling
frequency in a range greater than a bandwidth frequency of a carrier signal used for providing the input signal and less than
twice the bandwidth frequency;

interpolating samples of the sampled signal proximate to the signal peak with a bandlimited interpolation to provide a reconstructed
peak;

applying a cancellation pulse by a cancellation pulse generator to the samples to reduce the signal peak; and
outputting a version of the input signal after application of the cancellation pulse.

US Pat. No. 9,100,015

FIND-FIRST-SET BIT CIRCUIT AND METHOD

XILINX, INC., San Jose, ...

1. A method of finding a first bit that is set in an n-bit input word, comprising:
generating by a first logic circuit, n n-bit patterns in response to the n-bit input word, each pattern corresponding to one
bit position of the n-bit input word;

wherein in response to the bit at the one bit position of the n-bit input word having a logic 1 value, the corresponding pattern
has a logic 1 value in a corresponding bit position of the n-bit pattern, a logic 1 value in each bit position left of the
corresponding bit position in the n-bit pattern, and a logic 0 value in each bit position right of the corresponding bit position
in the n-bit pattern; and

wherein in response to the bit at the one bit position of the n-bit input word having a logic 0 value, the corresponding pattern
has a logic 0 value in each bit position of the n-bit pattern;

combining by a second logic circuit, the n n-bit patterns into one merged n-bit pattern; and
generating by a third logic circuit, an output n-bit pattern in response to the merged n-bit pattern, the output n-bit pattern
having a logic 1 value in one bit position and a logic 0 value in every other bit position, the one bit position equal to
a rightmost bit position of the n-bit input word having a logic 1 value.

US Pat. No. 9,413,390

HIGH THROUGHPUT LOW-DENSITY PARITY-CHECK (LDPC) DECODER VIA RESCHEDULING

XILINX, INC., San Jose, ...

1. A method for a low-density parity-check (LDPC) decoder, the method
comprising:
performing, using a processing unit, a forward scan in a first direction of layer L1 of a parity check matrix, wherein the parity check matrix comprises N number of layers and M number of columns;

performing, using the processing unit, a backwards scan in a second direction of the layer L1 of the parity check matrix, after the forward scan of the layer L1 is completed;

updating, using the processing unit, layer L2 of the parity check matrix based on a result from the forward scan of layer L1 and a result from the backward scan of layer L1;

performing, using the processing unit, a forward scan in the second direction of the layer L2 of the parity check matrix, wherein the act of performing the forward scan in the second direction of the layer L2 of the parity check matrix begins (1) after a predetermined time has elapsed since the backwards scan of the layer L1 has begun and (2) before the backwards scan of the layer L1 is completed; and

performing, using the processing unit, a backwards scan in the first direction of the layer L2 of the parity check matrix, after the forward scan of the layer L2 is completed.

US Pat. No. 9,306,585

FRACTIONAL-N MULTIPLYING INJECTION-LOCKED OSCILLATION

XILINX, INC., San Jose, ...

1. An apparatus for generating an oscillating signal, comprising:
a fractional-N generator for receiving a frequency control word and a reference signal;
a multiplying injection-locked oscillator coupled to the fractional-N generator for receiving a clock signal, and for outputting
an oscillating signal; and

a frequency tracking loop coupled to the fractional-N generator for receiving the clock signal, and further coupled to the
multiplying injection-locked oscillator for receiving the oscillating signal.

US Pat. No. 9,305,362

IMAGE STABILIZATION

XILINX, INC., San Jose, ...

1. A method, comprising:
preprocessing an image for noise suppression and edge detection with filters;
hierarchically decomposing the image to provide an image pyramid;
wherein the hierarchically decomposing includes successively down-scaling the image to provide different resolutions of the
image corresponding to levels of the image pyramid;

wherein the image and the different resolutions of the image provide a set of images;
performing a scene analysis of the set of images;
wherein the performing of the scene analysis includes determining variance values for blocks of the set of images for feature
tracking;

selecting a subset of the blocks determined to be qualified for the feature tracking responsive to a subset of the variance
values associated with the subset of the blocks being above a variance qualifier threshold; and

performing motion estimation on the subset of the blocks;
wherein the performing of the motion estimation uses a hierarchical set of motion estimation engines corresponding to levels
of the image pyramid.

US Pat. No. 9,130,559

PROGRAMMABLE IC WITH SAFETY SUB-SYSTEM

XILINX, INC., San Jose, ...

1. A programmable integrated circuit (IC), comprising:
a programmable logic sub-system including a plurality of programmable logic circuits configured in response to a first subset
of configuration data;

a processing sub-system including one or more processing circuits configured to execute a software program in response to
a second subset of configuration data; and

a safety sub-system configured to perform safety functions that detect and/or mitigate errors in circuits of the programmable
IC, wherein the safety sub-system includes:

a set of hard-wired circuits configured to perform hardware-based safety functions for a first subset of circuits of the programmable
IC; and

a processing circuit configured to execute software-based safety functions for a second subset of circuits of the programmable
IC.

US Pat. No. 9,407,254

POWER ON-RESET WITH BUILT-IN HYSTERESIS

XILINX, INC., San Jose, ...

1. A device for controlling a power-on reset signal, comprising:
a constant current source for controlling a reference current that is independent of a supply voltage of the device;
a trip point detector circuit driven by the reference current, for detecting when the supply voltage of the device exceeds
a first trip point voltage and for de-asserting the power-on reset signal when the supply voltage exceeds the first trip point
voltage;

wherein the first trip point voltage is controlled by a sum of a threshold voltage of a first n-type metal-oxide-semiconductor
transistor, a voltage drop across a first resistor, and a threshold voltage of a first p-type metal-oxide-semiconductor transistor;

wherein a current through the first resistor and the first n-type metal-oxide-semiconductor transistor comprises the reference
current; and

a hysteresis circuit for detecting when the supply voltage falls below a second trip point voltage and for causing the trip
point detector circuit to reassert the power-on reset signal when the supply voltage has fallen below the second trip point
voltage.

US Pat. No. 9,379,880

CLOCK RECOVERY CIRCUIT

XILINX, INC., San Jose, ...

1. A clock data recovery device comprising:
a phase change determination circuit configured to:
detect a phase difference between a data signal and a clock signal; and
generate, based upon the detected phase difference, a delta signal and a delta selection signal; and
a speculative calculation circuit that includes:
a first calculation circuit configured to generate a first set of phase interpolation (PI) codes from a first prior value
of the delta signal;

a second calculation circuit configured to generate a second set of PI codes from a second prior value of the delta signal;
a third calculation circuit configured to generate a third set of PI codes from a speculative value of the delta signal that
is based upon the first prior value and the second prior value of the delta signal; and

a selection circuit configured to select, in response to the delta selection signal, between the first, second, and third
sets of PI codes to provide the selection as an output of the clock data recovery device.

US Pat. No. 9,317,895

NON-LINEAR IMAGE MAPPING

XILINX, INC., San Jose, ...

10. A vehicle, comprising:
a video and graphics processing module having an image predistorter;
the image predistorter having a filter coefficient module including an oversampled filter configured to predistort a digital
image for a non-linear image mapping of a display image to a three dimensional perspective;

the image predistorter including:
a mapper configured to receive destination pixel information in terms of a source pixel space, and configured to generate
a 2-dimensional filter kernel for source pixels for the destination pixel information;

wherein the destination pixel information is for the navigation symbology;
the oversampled filter including predetermined coefficients having a first grid finer than a second grid of the source pixel
space;

the oversampled filter coupled to the mapper and configured to filter the source pixels to the first grid pattern of the predetermined
coefficients for selection of filter coefficients from the predetermined coefficients;

the filter coefficient module configured to select the filter coefficients from the predetermined coefficients stored in the
oversampled filter based on proximity to the source pixels in the filter kernel for each of the source pixels in the filter
kernel; and

the filter coefficient module configured to predistort the digital image associated with the source pixels for the non-linear
image mapping thereof;

a head up display (“HUD”) coupled to the video and graphics processing module;
a global positioning system coupled to the video and graphics processing module;
at least one camera coupled to the video and graphics processing module;
wherein the global positioning system is configured to generate navigation symbology for the video and graphics processing
module responsive to position information;

wherein the video and graphics processing module is configured to register the navigation symbology from the global positioning
system with image information from the at least one camera, and further configured to provide the display image;

wherein the image predistorter is configured to predistort the digital image for projection of the display image onto a windshield
in the three dimensional perspective; and

wherein the HUD is configured to receive the predistorted display image for projection thereof.

US Pat. No. 9,275,180

PROGRAMMABLE INTEGRATED CIRCUIT HAVING DIFFERENT TYPES OF CONFIGURATION MEMORY

XILINX, INC., San Jose, ...

1. A method of generating an implementation of a circuit design on a programmable integrated circuit (IC), comprising:
on a programmed processor, performing operations of:
inputting the circuit design;
generating first data for implementing the circuit design;
determining a critical portion and a non-critical portion of the circuit design, wherein the determining of the critical portion
includes determining lookup tables (LUTs) having numbers of used inputs greater than a threshold;

generating second data for programming configuration memory cells of the programmable IC to implement the circuit design;
wherein a first subset of the second data is assigned to program a first type of configuration memory cells to implement the
critical portion of the circuit design on a first subset of programmable logic resources and a first subset of programmable
interconnect resources of the programmable IC;

wherein a second subset of the second data is assigned to program a second type of configuration memory cells to implement
the non-critical portion of the circuit design on a second subset of programmable logic resources and a second subset of programmable
interconnect resources of the programmable IC; and

storing the second data in an electronically readable storage medium.

US Pat. No. 9,083,347

BUILT-IN INTEGRATED CIRCUIT DEBUG DESIGN

XILINX, INC., San Jose, ...

1. A circuit, comprising:
a shift register configured to receive data values of an input data set over a plurality of cycles;
a counter unit configured to receive a trigger signal and to output the trigger signal after a number of cycles following
receipt of the trigger signal, wherein the trigger signal indicates a trigger event; and

a switch configured to receive the trigger signal from the counter unit and to open a connection between an input interface
and the shift register in response to receiving the trigger signal.

US Pat. No. 9,503,093

VIRTUALIZATION OF PROGRAMMABLE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A programmable integrated circuit (IC), comprising:
a configuration memory;
a plurality of programmable resources including programmable logic circuits and programmable routing resources, wherein in
response to a configuration datastream being loaded into the configuration memory, the programmable resources are configured
to concurrently implement two or more different user designs of a plurality of user designs specified in the configuration
datastream using respective subsets of the programmable resources;

a plurality of shareable logic circuits coupled to the plurality of programmable resources, wherein the plurality of sharable
logic circuits are exclusive from the respective subsets of the programmable resources used to implement the two of more user
designs;

a virtualization circuit configured to manage sharing of access to the plurality of shareable logic circuits between the two
or more user designs according to a resource allocation policy derived from the configuration datastream; and

wherein the plurality of user designs are communicatively isolated from one another on the programmable IC.

US Pat. No. 9,355,690

TIME-MULTIPLEXED, ASYNCHRONOUS DEVICE

XILINX, INC., San Jose, ...

1. A method for asynchronous time multiplexing of information with synchronous interfacing, comprising:
receiving a clock signal;
responsive to a first edge of the clock signal, asynchronously loading first data into a first asynchronous shift register;
wherein the first data includes first multiple sets of data for multiple operations;
asynchronously unloading the first data from the first asynchronous shift register to a function block;
processing the first data with the function block to provide second data;
wherein the second data includes second multiple sets of data as results for the multiple operations;
asynchronously loading the second data into a second asynchronous shift register; and
responsive to a second edge of the clock signal, asynchronously unloading the second data from the second asynchronous shift
register as the results of the multiple operations;

wherein the first edge and the second edge of the clock signal are associated with a same period of the clock signal.

US Pat. No. 9,350,385

MODULAR AND SCALABLE CYCLIC REDUNDANCY CHECK COMPUTATION CIRCUIT

XILINX, INC., San Jose, ...

1. A device, comprising:
a splitter for splitting a data word comprising a plurality of bits into a plurality of paths, wherein each path of the plurality
of paths carries a subset of the plurality of bits;

a plurality of cyclic redundancy check units, wherein each of the cyclic redundancy check units is for processing a respective
one of the paths, wherein each of the cyclic redundancy check units comprises:

a first output port for outputting a first cyclic redundancy check value for a first packet that ends within the subset of
the plurality of bits processed by the cyclic redundancy check unit; and

a second output port for outputting a second cyclic redundancy check value for a second packet that starts or is ongoing within
the subset of the plurality of bits processed by the cyclic redundancy check unit.

US Pat. No. 9,338,039

EFFICIENT SIGNAL CLASSIFICATION IN DIGITAL PRE-DISTORTION SYSTEMS

XILINX, INC., San Jose, ...

1. An apparatus for signal classification in a digital pre-distortion (DPD) system, comprising:
a positive frequency path including a first half-band low pass filter (LPF) operable to filter input digital samples after
positive frequency translation;

a negative frequency path including a second half-band LPF operable to filter the input digital samples after negative frequency
translation;

a power estimation circuit coupled to the positive frequency path and the negative frequency path, the power estimation circuit
operable to determine a first average power based on output of the first half-band LPF, a second average power based on output
of the second half-band LPF, and a total average power of the input digital samples; and

a controller operable to determine a frequency content metric from the first average power and the second average power, and
to select a set of filter coefficients for the DPD system based on the frequency content metric and the total average power.

US Pat. No. 9,281,807

MASTER-SLAVE FLIP-FLOPS AND METHODS OF IMPLEMENTING MASTER-SLAVE FLIP-FLOPS IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A master-slave flip-flop implemented in an integrated circuit, the master-slave flip-flop comprising:
a master latch coupled to receive data at an input;
a first inverter coupled to an output of the master latch;
a slave latch comprising a first slave latch inverter, a second slave latch inverter, a third slave latch inverter and a fourth
slave latch inverter, wherein an output of the first inverter is coupled to a first slave latch inverter output of the first
slave latch inverter and a third slave latch inverter output of the third slave latch inverter, and the input of the master
latch is coupled to a second slave latch inverter output of the second slave latch inverter and a fourth slave latch inverter
output of the fourth slave latch inverter; and

a second inverter coupled to an output of the slave latch at the second slave latch inverter output and the fourth slave latch
inverter output.

US Pat. No. 9,246,492

POWER GRID ARCHITECTURE FOR VOLTAGE SCALING IN PROGRAMMABLE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A programmable integrated circuit (IC), comprising:
a first logic tile in a first power domain having a first local voltage, the first logic tile including:
a driver operable to use the first local voltage to output a signal having a logic-level referenced to the first local voltage;
and

a level-shifter coupled to receive the signal from the driver and operable to output a level-shifted signal having a logic-level
referenced to a global handshaking voltage; and

a second logic tile in a second power domain having a second local voltage, the second logic tile including a receiver operable
to use the second local voltage to receive the level-shifted signal;

wherein the global handshaking voltage is at least as high as the first local voltage and at least as high as the second local
voltage.

US Pat. No. 9,235,660

SELECTIVE ADDITION OF CLOCK BUFFERS TO A CIRCUIT DESIGN

XILINX, INC., San Jose, ...

1. A method of processing a circuit design, comprising:
on a programmed processor, performing operations including:
inputting a placed circuit design that has been placed on programmable resources of a programmable integrated circuit (IC);
wherein the programmable resources include pluralities of sequential elements, clock buffers, and programmable logic, and
the plurality of clock buffers includes a plurality of different types of clock buffers;

wherein ones of the plurality of clock buffers that are assigned to the placed circuit design are used clock buffers, and
ones of the plurality of clock buffers that are not assigned to the placed circuit design are unused clock buffers;

determining a critical path from a first sequential element to a second sequential element, the first and second sequential
elements being ones of the plurality of sequential elements assigned to the placed circuit design;

determining a first clock buffer of the used clock buffers that provides a clock signal to the first and second sequential
elements;

selecting one of the unused clock buffers of the same type as the first clock buffer and based on proximity to the first sequential
element; and

modifying the placed circuit design to include the one unused clock buffer as a second clock buffer coupled to receive a clock
signal in parallel with the first clock buffer and to provide the clock signal to the first sequential element;

determining after the modifying, whether or not timing of the clock signal at the first and second sequential elements satisfies
a timing constraint;

selecting, in response to the timing not satisfying the timing constraint, another unused clock buffer of the unused clock
buffers as a third clock buffer, the third clock buffer being of a different type from the first clock buffer; and

replacing the second clock buffer with the third clock buffer in the placed circuit design.

US Pat. No. 9,117,046

METHOD OF GENERATING DATA FOR ESTIMATING RESOURCE REQUIREMENTS FOR A CIRCUIT DESIGN

XILINX, INC., San Jose, ...

1. A method of generating data for estimating resource requirements for a circuit design using a computer to perform a process,
the process comprising:
identifying a plurality of intermediate circuit modules of netlists for circuit designs;
establishing a plurality of parameter sets for each intermediate circuit module, wherein each parameter set of the plurality
of parameter sets comprises a parameter identifying an integrated circuit device;

characterizing each intermediate circuit module of the plurality of intermediate circuit modules according to an associated
plurality of parameter sets;

generating, by the computer and for each intermediate circuit module, data comprising an estimate of resources for each parameter
set of the associated plurality of parameter sets;

generating functions representing the data to enable estimating the resource requirements for the circuit design;
identifying, for an intermediate circuit module, a parameter which is selected as a switch;
generating a plurality of equations characterizing the data for the intermediate circuit module, wherein the number of equations
is based upon the number of values for the parameter selected as a switch; and

generating an estimate of resource requirements for the circuit design implemented in the integrated circuit device identified
by the parameter.

US Pat. No. 9,525,423

POWER DISTRIBUTION NETWORK IP BLOCK

XILINX, INC., San Jose, ...

1. A device, comprising:
a semiconductor substrate;
a programmable logic device on the semiconductor substrate;
a power distribution network comprising at least one voltage regulator on the semiconductor substrate; and
a power management bus for communication between the at least one voltage regulator and the programmable logic device,
wherein the programmable logic device comprises a processing module configured to perform a diagnostic analysis of the power
distribution network;

wherein the processing module comprises a frequency identifier configured to identify one or more frequencies where a power
frequency resonance will occur.

US Pat. No. 9,432,036

RADIO FREQUENCY CURRENT STEERING DIGITAL TO ANALOG CONVERTER

XILINX, INC., San Jose, ...

1. A current steering circuit for a digital-to-analog converter (DAC), comprising:
a source-coupled transistor pair responsive to a differential gate voltage;
a current source coupled to the source-coupled transistor pair operable to source a bias current;
a load circuit coupled to the source-coupled transistor pair operable to provide a differential output voltage;
a driver having a first input, a second input, and a differential output, the differential output providing the differential
gate voltage; and

combinatorial logic having a data input, a clock input, a true output, and a complement output, the true output and the complement
output respectively coupled to the first input and the second input of the driver, the combinatorial logic operable to exclusively
OR a data signal on the data input and a clock signal on the clock input.

US Pat. No. 9,287,899

FORWARD ERROR CORRECTION

XILINX, INC., San Jose, ...

1. A method for forward error correction (FEC) decoding, comprising:
receiving a plurality of symbols in an interleaved format of rows and columns of the symbols;
performing a plurality of FEC decoding iterations on the plurality of symbols, each decoding iteration including:
performing FEC decoding of the rows of the plurality of symbols; and
performing FEC decoding of the columns of the plurality of symbols;
after performing the FEC decoding iterations, determining rows in error of the plurality of symbols and columns in error of
the plurality of symbols; and

in response to the determined rows in error and the determined columns in error matching a deadlock pattern of a set of deadlock
patterns:

determining symbols of the plurality of symbols at intersections of the determined rows in error and the determined columns
in error; and

inverting bits of one or more symbols of the determined symbols; and
performing one or more of the FEC decoding iterations after the inverting of the bits.

US Pat. No. 9,270,469

AUTHENTICATION USING PUBLIC KEYS AND SESSION KEYS

XILINX, INC., San Jose, ...

9. An authentication system, comprising:
non-volatile memory configurable for storage of a plurality of combinations of representations of public keys and session
key IDs and storage for a plurality of key states in association with the plurality of combinations of representations of
public keys and session key IDs, respectively, wherein each key state indicates whether or not the associated combination
is valid;

a processor coupled to the non-volatile storage, the processor configured to:
input a payload and accompanying public key, session key ID, and signature of the payload, wherein the signature is a function
of the payload and a private key of a key pair that includes the accompanying public key and the private key;

determine whether or not one of the combinations has a representation of a public key that matches the accompanying public
key and whether or not the combination is valid from the key state associated with the combination;

in response to determining that the one of the combinations has the representation of a public key that matches the accompanying
public key and is not valid, designate the payload to be not authentic;

determine whether or not the payload is authentic, from the accompanying public key and session key ID and the combinations
stored in the non-volatile memory, and from the signature and the payload;

responsive to determining that the payload is authentic, process the payload; and
responsive to determining that the payload is not authentic, disable processing of the payload.

US Pat. No. 9,148,032

ESTIMATING POWER CONSUMPTION OF AN ELECTRONIC CIRCUIT

XILINX, INC., San Jose, ...

1. A method of estimating power consumption of an electronic circuit from values of configuration parameters of the circuit,
comprising:
using a computer processor, prompting for values of a first subset of the configuration parameters in a first user interface
window that is separate from a second user interface window that provides default values of a second subset of the configuration
parameters;

receiving user-entered values of the first subset of parameters via the first user interface window;
in response to user submission of the values of the first subset of parameters via the first user interface window, determining
with the computer processor an estimated level of power consumption of the electronic circuit as a function of the user-entered
values of the first subset of parameters and the default values of the second subset of parameters; and

simultaneously displaying in a third user interface window, the estimated level of power consumption, the user-entered values
of the first subset of parameters, and the default values of the second subset of parameters, wherein values of both the first
subset and second subset of parameters are editable in the third user interface window.

US Pat. No. 9,098,500

REVISION HISTORY STORAGE AND MAINTENANCE

XILINX, INC., San Jose, ...

1. A method of updating a software design environment workspace, comprising:
retrieving, by a processor, a hardware design revision history, the hardware design revision history indicating revision data
for each change to module definition parameters of the hardware design, the revision data indicating a revision identifier
and an updated value of each changed module definition parameter;

determining a revision identifier of a current configuration of the workspace;
parsing the hardware design revision history;
determining a current value for each module definition parameter corresponding to a most recent revision identifier in the
hardware design revision history;

for each module definition parameter, determining differences between the current value and a value of the parameter in the
workspace; and

in a window on a display device, simultaneously displaying a plurality of user-selectable revision identifiers of revisions
of the hardware design, and in response to a first user selection of one of the revision identifiers simultaneously displaying,
for only revisions from the one of the user-selectable revision identifiers to a most recent revision and module definition
parameters having changed values, module definition parameter identifiers of module definition parameters of the hardware
design and values of the module definition parameters corresponding to the revision identifiers of the revisions from the
one of the user-selectable revision identifiers to the most recent revision;

in response to a user-initiated restore function and a selected revision identifier, for each object in the revision history
data, determining a value corresponding to the selected revision identifier; and

generating a modified version of the workspace, the modified version of the workspace having the value of each object corresponding
to an object in the revision history data set to the value corresponding to the selected revision identifier.

US Pat. No. 9,082,633

MULTI-DIE INTEGRATED CIRCUIT STRUCTURE WITH HEAT SINK

XILINX, INC., San Jose, ...

1. An integrated circuit structure, comprising:
a first die comprising a first surface and a second surface;
a second die comprising a first surface and a second surface;
wherein the first die and the second die are semiconductor dice;
wherein the second die is mounted on the first die with the second surface of the second die facing the first surface of the
first die; and

a heat sink mounted on the first surface of the first die and the first surface of the second die;
wherein the first die is an interposer and comprises a first thermal wire coupled to the heat sink;
wherein the first thermal wire is not configured to propagate an electrical signal;
wherein the first thermal wire comprises a first portion formed of a via coupled to the heat sink and extending from the first
surface of the interposer and into the interposer and a second portion formed of a first interconnect layer within the interposer
that is parallel to the surface of the interposer and perpendicular to the via; and

wherein the second die comprises a second thermal wire coupled to the heat sink, and the second thermal wire comprises a first
portion formed of a via coupled to the heat sink and extending from the first surface of the second die and into the second
die and a second portion formed of an interconnect layer of the second die that is parallel to the surface of the interposer
and perpendicular to the via of the second thermal wire.

US Pat. No. 9,509,640

LATENCY CONTROL IN A TRANSMITTER/RECEIVER BUFFER

XILINX, INC., San Jose, ...

1. A method for buffering, comprising:
operating a buffer to buffer data responsive to a read clock signal and a write clock signal provided to the buffer;
obtaining a flag signal from the buffer responsive to fill level of the buffer by a state machine;
toggling the flag signal responsive to the data buffered being either above or below a set point for the fill level;
adjusting a phase of the write clock signal to a phase of the read clock signal responsive to the toggling of the flag signal;
and

outputting the write clock signal for the operating of the buffer with controlled latency thereof, wherein the latency of
the buffer is controlled responsive to the adjusting;

wherein the adjusting of the phase of the write clock signal comprises:
generating an override signal by the state machine responsive to the toggling of the flag signal; and
inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write
clock signal to the phase of the read clock signal during the operating of the buffer;

wherein the phase adjuster is configured to adjust delay of the read clock signal responsive to the override signal to align
the phase of the write clock signal to the phase of the read clock signal for the adjusting.

US Pat. No. 9,490,832

ANALOG-TO-DIGITAL CONVERTER CIRCUIT AND METHOD OF IMPLEMENTING AN ANALOG-TO-DIGITAL CONVERTER CIRCUIT

XILINX, INC., San Jose, ...

1. An analog-to-digital converter circuit comprising:
an amplifier circuit configured to receive a differential analog input signal at a first amplifier input associated with a
first amplifier current path and a second amplifier input associated with a second amplifier current path, and to amplify
the differential analog input signal to generate a differential analog output signal at a first amplifier output associated
with the first amplifier current path and at a second amplifier output associated with the second amplifier current path,
wherein:

the amplifier circuit comprises a first resistive load coupled between a reference voltage and a first transistor of the first
amplifier current path;

a first input signal of the differential analog input signal is coupled to a gate of the first transistor;
the amplifier circuit further comprises a second resistive load coupled between the reference voltage and a second transistor
of the second amplifier current path; and

a second input signal of the differential analog input signal is coupled to a gate of the second transistor;
a first capacitor coupled between the first amplifier input and the second amplifier output;
a second capacitor coupled between the second amplifier input and the first amplifier output; and
a latch circuit having a first latch input coupled to the first amplifier output and a second latch input coupled to the second
amplifier output, wherein the latch circuit is configured to generate a differential digital output signal, based upon the
differential analog output signal, at a first latch output and a second latch output.

US Pat. No. 9,454,498

INTEGRATED CIRCUIT WITH PROGRAMMABLE CIRCUITRY AND AN EMBEDDED PROCESSOR SYSTEM

XILINX, INC., San Jose, ...

1. An integrated circuit comprising:
a processor system having a core complex configured to execute program code, wherein the processor system is hard-wired; and
a programmable circuitry configurable to implement a physical circuit specified by configuration data, wherein the programmable
circuitry is coupled to the processor system and the processor system controls operation of the programmable circuitry, wherein
the core complex comprises a cache memory and the programmable circuitry has direct read and write access to the cache memory.

US Pat. No. 9,208,043

METHOD AND APPARATUS FOR FAULT INJECTION AND VERIFICATION ON AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A method for performing fault injection and verification on an integrated circuit including a plurality of modules arranged
in a hierarchical design, the method comprising:
generating, by a processor, a mask file for one or more modules of the plurality of modules of the hierarchical design, wherein
the mask file identifies one or more essential bits;

receiving, by the processor, a selection of one of the one or more modules as a selected module for the fault injection and
the verification to be applied;

performing, by the processor, the fault injection on at least one essential bit of the selected module based upon the mask
file for the selected module; and

performing, by the processor, the verification on the selected module, wherein the fault injection and the verification are
limited to the selected module.

US Pat. No. 9,081,634

DIGITAL SIGNAL PROCESSING BLOCK

XILINX, INC., San Jose, ...

1. An integrated circuit, comprising:
a first digital signal processing (“DSP”) block having an input interface for receiving a first operand input, a second operand
input, a third operand input, and a fourth operand input;

wherein the first DSP block comprises:
a preadder-register block coupled to receive the first operand input, the second operand input, and the fourth operand input;
a multiplier coupled to the preadder-register block to receive a multiplicand operand and a multiplier operand therefrom;
a first register block coupled to the multiplier to receive a first set of partial products and a second set of partial products
from the multiplier;

a second register block coupled to receive the third operand input;
an arithmetic logic unit (“ALU”) block coupled to the pre-adder-register block, the first register block and the second register
block;

wherein the ALU block comprises:
a first multiplexer coupled to receive the third operand input from the second register block and a feedback product input
from a product output of the ALU block;

a second multiplexer coupled to receive the first set of partial products and the product input fed back;
a third multiplexer coupled to receive the second set of partial products and the third operand input from the second register
block;

a fourth multiplexer coupled to receive the product input fed back and the third operand input from the second register block;
and

an ALU coupled to receive outputs from each of the first multiplexer, the second multiplexer, the third multiplexer, and the
fourth multiplexer;

wherein the ALU block includes an XOR tree;
wherein the XOR tree comprises:
a first level of XOR gates provided from logic operation circuitry of the ALU;
a second level of XOR gates higher than the first level of XOR gates coupled to outputs of the first level of XOR gates;
wherein the second level of XOR gates is provided separately from the logic operation circuitry of the ALU;
a third level of XOR gates higher than the second level of XOR gates coupled to outputs of the second level of XOR gates;
and

an XOR gate higher than the third level of XOR gates coupled to outputs of the third level of XOR gates;
a plurality of output registers;
wherein a first portion of the plurality of output registers is respectively coupled to outputs of the plurality of multiplexers;
and

wherein a second portion of the plurality of output registers is coupled to an output tap of the output taps of the XOR tree.

US Pat. No. 9,047,241

MINIMUM MEAN SQUARE ERROR PROCESSING

XILINX, INC., San Jose, ...

1. A systolic array for right multiplication, left multiplication, and cross diagonal transposition, comprising:
a plurality of processing cells, including boundary cells and internal cells, and arranged into:
N rows of processing cells, each row M beginning with a boundary cell and continuing with a number of internal cells equal
to the number N minus M, wherein 1?M?N; and

N columns of processing cells, each column L containing L minus one internal cells followed by one boundary cell, wherein
1?L?N;

wherein:
the systolic array is configurable to operate in a first mode and a second mode;
while operating in the first mode, processing cells of the systolic array are configured and interconnected to receive first
and second input matrices and perform left multiplication of the first input matrix with the second input matrix to produce
a first output matrix;

while operating in the second mode:
processing cells of the systolic array are configured and interconnected to produce a cross diagonal transposition on the
first output matrix; and

perform right multiplication of the cross diagonal transposition of the first output matrix with the first input matrix to
produce a second output matrix.

US Pat. No. 9,465,903

PROGRAMMABLE IC DESIGN CREATION USING CIRCUIT BOARD DATA

XILINX, INC., San Jose, ...

1. A method of implementing a circuit design in a circuit design tool for configuration in a programmable integrated circuit
(IC) connected to components on a circuit board, the method comprising:
processing a first file associated with the circuit board to obtain descriptions of circuit board interfaces of the components
on the circuit board;

merging a second file associated with a daughter circuit board connected to the circuit board with the first file associated
with the circuit board, the second file including descriptions of circuit board interfaces of components on the daughter circuit
board;

displaying a graphic user interface (GUI) of the circuit design tool to connect a selected circuit board interface described
in the first file with a circuit design interface in the circuit design;

generating physical constraints on the circuit design interface with respect to input/outputs of the programmable IC described
as being connected to the selected circuit board interface; and

generating a bitstream to configure the programmable IC, the bitstream including a physical implementation of the circuit
design satisfying the physical constraints.

US Pat. No. 9,337,886

DIGITAL PRE-DISTORTION WITH SHARED OBSERVATION PATH RECEIVER

XILINX, INC., San Jose, ...

1. A system for digital pre-distortion, comprising:
a transmitter, coupled to a transmit antenna, configured to transmit at least one transmission data signal via the transmit
antenna;

a receiver, coupled to a receive antenna, configured to receive at least one receive data signal and to receive the at least
one transmission data signal via the receive antenna;

the receiver, comprising:
a receive amplifier, coupled to the receive antenna, configured to amplify output of the receive antenna;
a switch configured to separately output the amplified at least one transmission data signal and the amplified at least one
receive data signal;

at least one processor, coupled to the switch, configured to generate at least one pre-distortion control signal using the
separately output at least one transmission data signal; and

at least one transmit amplifier, within the transmitter, configured to receive the at least one pre-distortion control signal
sent from the receiver and reduce distortion based on the received at least one pre-distortion control signal.

US Pat. No. 9,065,446

GENERATING DELAY VALUES FOR DIFFERENT CONTEXTS OF A CIRCUIT

XILINX, INC., San Jose, ...

1. A method of generating delay values for instances of a circuit, comprising:
on a programmed processor, performing operations including:
inputting a plurality of contexts, wherein each context includes a respective delay value and a combination of possible types
of a plurality of characteristics of the circuit, and each characteristic is of one type of a plurality of alternative types
of the characteristic;

inputting a plurality of classification parameters, the classification parameters indicating selected ones of the characteristics,
and each of the plurality of characteristics not indicated by a classification parameter being a non-selected characteristic;

selecting groups of contexts based on the plurality of classification parameters, wherein:
each group includes one or more of the contexts, and each context includes the plurality of characteristics; and
a combination of types of the selected characteristics in each context in a group is equal to the combination of types of
the selected characteristics of each other context in the group;

determining for each group and from the contexts in each group, a mean and a standard deviation of the respective delay values;
and

outputting the mean and standard deviation of each group.

US Pat. No. 9,417,309

TEST STRUCTURE AND METHOD FOR CALIBRATING THREE-DIMENSIONAL THERMOGRAPHY FAULT ISOLATION TOOL

XILINX, INC., San Jose, ...

13. A method involving a three-dimensional thermography fault isolation tool, comprising:
providing an apparatus comprising a substrate having two or more pins, a first semiconductor die coupled to the substrate,
a first heat generating test component, and a second heat generating test component, wherein the first heat generating test
component and the second heat generating test component are located at different respective heights;

applying one or more voltages, using the three-dimensional thermography fault isolation tool, to the two or more pins of the
substrate to cause a first temperature change in the first heat generating test component, and a second temperature change
in the second heat generating test component;

determining a first time difference between the application of the one or more voltages and an occurrence of the first temperature
change in the first heat generating test component;

determining a second time difference between the application of the one or more voltages and an occurrence of the second temperature
change in the second heat generating test component; and

processing the first time difference and the second time difference by a processing unit to obtain a result for calibrating
the three dimensional thermography fault isolation tool.

US Pat. No. 9,379,109

INTEGRATED CIRCUIT HAVING IMPROVED RADIATION IMMUNITY

XILINX, INC., San Jose, ...

1. An integrated circuit device having improved radiation immunity, comprising:
an n-type die from an n-type wafer having a first surface and a second surface;
a p-type epitaxial layer formed on the first surface of the n-type die, the p-type epitaxial layer having first elements storing
charge and a p-tap, wherein the p-tap is coupled to a contact configured to receive a ground voltage or a negative voltage;

an n-well formed in the p-type epitaxial layer, the n-well having second elements storing charge and an n-type region; and
a deep n-well contact coupled to the first surface of the n-type die;
wherein the deep n-well contact is coupled to a first positive voltage contact configured to receive a positive voltage;
wherein the n-type region of the n-well is coupled to a second positive voltage contact configured to receive a positive voltage;
and

wherein the n-well and the p-type epitaxial layer form a first p-n junction to attract excess minority carriers in the p-type
epitaxial layer, and the n-type die and the p-type epitaxial layer form a second p-n junction to attract excess minority carriers
in the p-type epitaxial layer.

US Pat. No. 9,372,948

INTERCONNECT SPEED MODEL CHARACTERIZATION IN PROGRAMMABLE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A speed measurement circuit for measuring speed parameters of a programmable integrated circuit comprising:
a ring oscillator configured in the programmable integrated circuit, the ring oscillator including:
an AND gate with an inverting input and a non-inverting input,
a programmable interconnect point context (PIP-context) having a first programmable interconnect point (PIP), a first interconnect,
a second PIP, and a second interconnect coupled in series, and

a third interconnect and a third PIP coupled in series with the PIP-context and with an inverting input of the AND gate; and
a counter circuit coupled to an output of the AND gate and configured in the programmable integrated circuit.

US Pat. No. 9,281,049

READ CLOCK FORWARDING FOR MULTIPLE SOURCE-SYNCHRONOUS MEMORY INTERFACES

XILINX, INC., San Jose, ...

1. A device, comprising:
a first module for a first byte of the device, wherein the first module comprises a first circuit for a first nibble of the
first byte, the first circuit comprising:

a first XNOR gate;
wherein a first input of the first XNOR gate is for receiving a first data strobe signal from a memory;
wherein a second input of the first XNOR gate is for receiving a first forwarded strobe signal from a second module for a
second byte of the device; and

wherein an output of the first XNOR gate is for outputting one of the first data strobe signal from the memory or the first
forwarded strobe signal from the second module for the second byte, to be used for sampling data from the memory and to be
forwarded to a third module for a third byte of the device.

US Pat. No. 9,222,976

METHODS AND CIRCUITS FOR DEBUGGING MULTIPLE IC PACKAGES

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a first IC package, including:
a first logic circuit; and
a first logic analyzer circuit coupled to the first logic circuit and configured to:
determine a first latency of a first data link; and
in response to receiving test input data:
communicate the test input data via the first data link;
capture a first set of data signals from the first logic circuit;
align the first set of data signals with a second set of data signals received via the first data link, based on the determined
first latency, to produce an aligned set of data signals; and

output the aligned set of data signals; and
a second IC package communicatively coupled to the first IC package via the first data link and including:
a second logic circuit; and
a second logic analyzer circuit coupled to the second logic circuit and configured to, in response to receiving the test input
data via the first data link:

capture the second set of data signals from the second logic circuit; and
communicate the second set of data signals to the first logic analyzer circuit via the first data link.

US Pat. No. 9,081,925

ESTIMATING SYSTEM PERFORMANCE USING AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

9. An integrated circuit, comprising:
a processor;
a first generic accelerator;
wherein the first generic accelerator comprises:
a first port through which the first generic accelerator is programmed;
a second port coupled to the processor through which the first generic accelerator communicates with the processor during
emulation; and

a monitor circuit configured to monitor communication between the first generic accelerator and the processor during emulation;
wherein the first generic accelerator mimics behavior of a segment of a design selected for hardware emulation from a plurality
of segments of the design and the design is specified using processor-executable instructions; and

wherein the first generic accelerator is programmed to generate a first data traffic pattern derived from the selected segment
of the design selected for hardware emulation without performing an exact function of the selected segment.

US Pat. No. 9,065,601

CIRCUITS FOR AND METHODS OF IMPLEMENTING A RECEIVER IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. A transceiver in an integrated circuit device comprising:
a receiver circuit having a clock and data recovery circuit coupled to receive data signals modulated with a transmitter clock
signal generated at another transceiver;

a transmitter circuit coupled to receive a reference clock signal; and
a clock generator of the transmitter circuit coupled to receive an output of the clock and data recovery circuit, the clock
generator providing a modulated reference clock to a phase interpolator of the receiver circuit, based upon the reference
clock signal which is independent of the transmitter clock signal;

wherein the modulated reference clock is synchronized with the transmitter clock signal.

US Pat. No. 9,558,528

ADAPTIVE VIDEO DIRECT MEMORY ACCESS MODULE

XILINX, INC., San Jose, ...

1. A method for arbitrating data for channels in a video pipeline, the method comprising:
determining arbitration weights for the channels;
determining which channels have arbitration weights above a threshold;
issuing data to the channels with arbitration weights above the threshold during an arbitration cycle;
decrementing arbitration weights for channels for which data is issued during the arbitration cycle using a lowest one of
normalized bandwidth values assigned to the channels; and

repeating the determining, issuing, and decrementing until no channels have arbitration weights above the threshold.

US Pat. No. 9,143,316

NON-DISRUPTIVE EYE SCAN FOR DATA RECOVERY UNITS BASED ON OVERSAMPLING

XILINX, INC., San Jose, ...

1. A data recovery unit, comprising:
a phase locked loop configured to receive data samples and generate an output;
a first sample selector coupled to the phase locked loop, wherein the first sample selector is configured to receive the data
samples and the output of the phase locked loop; and

an eye scanner coupled to the phase locked loop, wherein the eye scanner comprises a second sample selector coupled to the
phase locked loop via a first horizontal shift module, a first XOR unit having a first input coupled to an output of the first
sample selector and a second input coupled to an output of the second sample selector, and a first accumulator coupled to
the first XOR unit.

US Pat. No. 9,092,305

MEMORY INTERFACE CIRCUIT

XILINX, INC., San Jose, ...

1. A circuit for communicating with a memory, comprising:
a sorting circuit configured and arranged to:
receive a plurality of read transactions and a plurality of write transactions;
sort the write transactions according to respective sizes of data to be written by the write transactions to the memory over
a first serial data link; and

sort the read transactions according to respective sizes of data to be read by the read transactions from the memory over
a second serial data link;

a selection circuit coupled to the sorting circuit and configured and arranged to select from the sorted read and write transactions,
read and write transactions for transmission to the memory in an order that balances a quantity of data to be written to the
memory over the first serial data link with a quantity of data to be read from the memory over the second serial data link;
and

a transmitter coupled to the selection circuit and configured and arranged to transmit the selected ones of the plurality
of read and write transactions to the memory device on the first serial data link.

US Pat. No. 9,225,332

ADJUSTABLE BUFFER CIRCUIT

XILINX, INC., San Jose, ...

1. A common mode logic (CML) buffer device comprising:
a differential input signal pair that includes a first input and a second input;
a differential output signal pair that includes a first output and a second output;
a current source;
a reference voltage;
a first metal-oxide-semiconductor (MOS) transistor pair including:
a first MOS transistor with a gate connected to the first input and connected in series between the current source and the
first output, and

a second MOS transistor with a gate connected to the second input and connected in series between the current source and the
second output;

a second MOS transistor pair including:
a third MOS transistor connected in series between the reference voltage and the first output, and
a fourth MOS transistor connected in series between the reference voltage and the second output;
a first adjustment circuit configured to adjust, in response to a control signal, a first resistance value between the first
output and a gate of the third MOS transistor; and

a second adjustment circuit configured to adjust, in response to the control signal, a second resistance value between the
second output and a gate of the fourth MOS transistor.

US Pat. No. 9,208,130

PHASE INTERPOLATOR

XILINX, INC., San Jose, ...

1. A phase interpolator comprising:
a first plurality of digital-to-analog converters coupled to receive a first phase of a clock signal;
a second plurality of digital-to-analog converters coupled to receive a second phase of the clock signal;
a third plurality of digital-to-analog converters coupled to both the first phase of the clock signal and the second phase
of the clock; wherein each digital-to-analog converter of the third plurality of digital-to-analog converters is configurable
to receive either the first phase of the clock signal or the second phase of the clock signal; and

a control circuit coupled to generate control signals for the third plurality of digital-to-analog converters based upon a
phase code associated with a phase of an output clock signal, wherein the control signals configure digital-to-analog converters
of the third plurality of digital-to-analog converters to receive either the first phase of the clock signal or the second
phase of the clock signal.

US Pat. No. 9,110,524

HIGH THROUGHPUT FINITE STATE MACHINE

XILINX, INC., San Jose, ...

1. A finite state machine circuit, comprising:
look-ahead-cascade modules coupled to receive possible states of the finite state machine circuit and coupled to receive data
inputs,

wherein the possible states include possible states P0 through PN-1 for N a positive integer greater than one, N representing a number of states in the finite state machine circuit;

wherein the look-ahead-cascade modules are coupled to receive corresponding subsets of the data inputs;
merge modules coupled to a second-to-the-lowest order to the highest order of the look-ahead-cascade modules;
a second-to-the-lowest order to the highest order of disambiguation modules coupled to at least a portion of the merge modules;
the lowest order of the disambiguation modules coupled to the lowest order of the look-ahead-cascade modules;
wherein the lowest order to the highest order of the disambiguation modules are coupled to receive respective sets of interim
states of rN states each to select respective sets of next states of r states each for r a positive integer greater than one;
and

a state register coupled to receive a portion of the highest order of the sets of next states for registration to provide
a select signal;

wherein each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states
of the r states each.

US Pat. No. 10,015,916

REMOVAL OF ELECTROSTATIC CHARGES FROM AN INTERPOSER VIA A GROUND PAD THEREOF FOR DIE ATTACH FOR FORMATION OF A STACKED DIE

XILINX, INC., San Jose, ...

1. An apparatus, comprising:a passive interposer having a plurality of conductors for coupling two or more integrated circuit dies to the interposer to provide a stacked die and one or more microbumps extending from one or more microbump pads, the microbumps configured for coupling to the two or more integrated circuit dies;
wherein the interposer includes an exposed conductive pad disposed outward and clear of areas of the interposer configured to receive the two or more integrated circuit dies, the exposed conductive pad coupled to a conductive network of the interposer configured to dissipate electrostatic charge from the interposer prior to the two or more integrated circuit dies being coupled to the interposer, and
wherein the exposed conductive pad has a larger plan area than each of the one or more microbump pads.

US Pat. No. 9,448,937

CACHE COHERENCY

XILINX, INC., San Jose, ...

1. A system, comprising:
a first memory;
a processing sub-system including:
one or more processing circuits configured to access a first set of addresses of the first memory;
a first cache circuit configured to cache the first set of addresses of the first memory;
a first coherent interface circuit configured to communicate data transactions between the first cache circuit and the first
memory;

a programmable logic sub-system including a set of programmable resources configured to implement:
a logic circuit specified in a set of configuration data and configured to access the first set of addresses of the first
memory;

a second cache circuit configured to cache the first set of addresses of the first memory; and
a second coherent interface circuit configured to communicate data transactions between the second cache circuit and the first
memory;

a communication device coupled to a cache coherent interconnect configured to access the first memory without caching data
from the first memory; and

the cache coherent interconnect configured to maintain coherency and ownership between the first cache circuit and the second
cache circuit for the first set of addresses; and

in response to a write request to a first address of the first set of addresses from the communication device:
forward the write transaction to the first memory; and
invalidate the first address in one of the first cache circuit or second cache circuit having ownership of the first address.

US Pat. No. 9,214,941

INPUT/OUTPUT CIRCUITS AND METHODS OF IMPLEMENTING AN INPUT/OUTPUT CIRCUIT

XILINX, INC., San Jose, ...

1. An input/output circuit implemented in an integrated circuit, the input/output circuit comprising:
a first input/output pad;
a voltage control circuit coupled to the first input/output pad; and
a second input/output pad, wherein the second input/output pad is coupled to the voltage control circuit;
wherein the voltage control circuit sets a voltage at the first input/output pad at a first voltage when the first input/output
pad is implemented as an input pad and at a second voltage when the first input/output pad is implemented as an output pad.

US Pat. No. 9,436,562

CIRCUIT NETWORK WITH AN ERROR DETECTION SYSTEM FOR MITIGATION OF ERROR PROPAGATION

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a first data bus and a second data bus;
a first circuit coupled for communication via the first data bus;
a second circuit coupled for communication via the second data bus;
a plurality of storage elements coupled to the first data bus and the second data bus;
an error detection system coupled to the first data bus and the second data bus;
the error detection system configured to compare first data on the first data bus with corresponding second data on the second
data bus;

the error detection system configured to generate an error signal responsive to mismatch between the first data and the second
data;

first routing nodes of the first data bus to provide the first data to both the plurality of storage elements and the error
detection system;

second routing nodes of the second data bus to provide the second data to both the error detection system and the second circuit;
the first routing nodes coupled nearer to the first circuit for a first routing pipeline coverage end of the error detection
system as associated with the first data on the first data bus; and

the second routing nodes coupled nearer to the second circuit for a second routing pipeline coverage end of the error detection
system as associated with the second data on the second data bus.

US Pat. No. 9,418,909

STACKED SILICON PACKAGE ASSEMBLY HAVING ENHANCED LID ADHESION

XILINX, INC., San Jose, ...

1. A chip package assembly, comprising:
a package substrate;
an IC die coupled to the package substrate;
a lid having a first surface and a second surface, the second surface facing away from the first surface and towards the IC
die, the second surface having a plurality of engineered features; and

an adhesive coupling the plurality of engineered features of the second surface of the lid to the IC die;
wherein the engineered features have a shape configured to form a mechanical interlock with the adhesive; and
wherein the engineered features are disposed on the second surface of the lid in a pattern that prevents any uninterrupted
linear line of sight across a region of the lid disposed over the IC die.

US Pat. No. 9,413,524

DYNAMIC GAIN CLOCK DATA RECOVERY IN A RECEIVER

XILINX, INC., San Jose, ...

1. An apparatus for clock data recovery (CDR), comprising:
at least one data register;
at least one edge register having an input coupled to an output of the at least one data register;
a phase detector having inputs coupled to the output of the at least one data register and an output of the at least one edge
register;

a frequency accumulator coupled to an output of the phase detector;
a dynamic gain circuit coupled to the output of the phase detector; and
a phase accumulator and code generator circuit configured to generate codes to control a phase interpolator based on an output
of the dynamic gain circuit and an output of the frequency accumulator.

US Pat. No. 9,356,602

MANAGEMENT OF MEMORY RESOURCES IN A PROGRAMMABLE INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A method of managing memory in a programmable integrated circuit (IC), comprising:
configuring a memory map of the programmable IC with an association of a first subset of addresses of memory address space
of the programmable IC to physical memory of the programmable IC;

configuring the memory map with an association of a second subset of addresses of the memory address space to a virtual memory
block; and

locking at least a portion of a cache memory of the programmable IC to the second subset of addresses.

US Pat. No. 9,483,416

SECURE PROCESSOR OPERATION USING INTEGRATED CIRCUIT CONFIGURATION CIRCUITRY

XILINX, INC., San Jose, ...

1. A method, comprising:
loading encrypted program code encapsulated within a bitstream into an integrated circuit (IC) through a configuration port
of the IC;

decrypting the encrypted program code using a decryptor of the IC resulting in decrypted program code;
wherein the decryptor and the configuration port are implemented as non-programmable hard circuitry within the IC and the
decrypted program code is executable by a processor; and

providing the decrypted program code to the processor by outputting the decrypted program code from the IC through the configuration
port of the IC.

US Pat. No. 9,324,409

METHOD AND APPARATUS FOR GATING A STROBE SIGNAL FROM A MEMORY AND SUBSEQUENT TRACKING OF THE STROBE SIGNAL OVER TIME

XILINX, INC., San Jose, ...

1. A method for gating a strobe (DQS) signal, comprising:
sending, by a memory controller, a read command to a memory;
sending, by the memory controller, a strobe clock signal after the read command is sent and before the DQS signal is received
from the memory, wherein the strobe clock signal comprises a duration equal to a duration of the DQS signal;

gating, by the memory controller, the DQS signal based on the strobe clock signal to generate a positively gated strobe signal
indicating a rising edge of the DQS signal, wherein the gating is performed during a pre-amble of the DQS signal; and

generating, by the memory controller, a negatively gated strobe signal based on the positively gated strobe signal indicating
a falling edge of the DQS signal.

US Pat. No. 10,057,976

POWER-GROUND CO-REFERENCE TRANSCEIVER STRUCTURE TO DELIVER ULTRA-LOW CROSSTALK

XILINX, INC., San Jose, ...

1. An interface layout for a vertical interface of a first semiconductor component, comprising:a first one or more conductors configured to carry power signals extending vertically from the first semiconductor component;
a second one or more conductors configured to carry data signals extending vertically from the first semiconductor component;
a third one or more conductors configured to carry ground signals extending vertically from the first semiconductor component,
wherein the first one or more conductors are further configured to shield and separate the second one or more conductors;
a fourth one or more conductors extending horizontally from the first one or more conductors adjacent to and terminating proximal to the third one or more conductors; and
a fifth one or more conductors extending horizontally from the third one or more conductors adjacent to and terminating proximal to the first one or more conductors and the fourth one or more conductors,
wherein the fourth one or more conductors and the corresponding adjacent fifth one or more conductors forms a plate capacitor.

US Pat. No. 9,356,775

CLOCK DATA RECOVERY (CDR) PHASE WALK SCHEME IN A PHASE-INTERPOLATER-BASED TRANSCEIVER SYSTEM

XILINX, INC., San Jose, ...

1. A method of performing clock and data recovery, comprising:
detecting occurrence of a reset condition;
in response to occurrence of the reset condition, stepping, in a clock and data recovery (CDR) circuit, at least one of a
data phase interpolator (PI) code or a crossing PI code for each cycle of a clock;

stopping the stepping based on one or more criteria of the data PI code or the crossing PI code to generate a predetermined
state of the data PI code and the crossing PI code, wherein the predetermined state comprises an offset between the data PI
code and the crossing PI code;

receiving a data stream; and
performing the clock and data recovery on the data stream based on the offset between the data PI code and the crossing PI
code.

US Pat. No. 9,130,807

DATA RECOVERY UNIT (DRU) BASED ON FREE RUNNING OVERSAMPLING WITH ZERO-LATENCY LOOP

XILINX, INC., San Jose, ...

1. A data recovery unit (DRU), comprising:
an oscillator;
a phase detector unit configured to receive a reference phase and to receive input data through N wires, where N is an integer
greater than 1, to compare the reference phase with the input data to obtain phase errors, and to determine an average of
the phase errors;

a subtractor to subtract an output of the oscillator from the average of the phase errors to obtain an unbiased phase error;
a delay unit to receive the input data; and
a sample selector configured to receive an output from the delay unit and the output of the oscillator, and to output recovered
data.

US Pat. No. 9,235,671

COMBINING LOGIC ELEMENTS INTO PAIRS IN A CIRCUIT DESIGN SYSTEM

XILINX, INC., San Jose, ...

1. A method of implementing a circuit design for an integrated circuit (IC), comprising:
on at least one programmed processor, performing operations including: processing a description of the circuit design having
logic elements into a graph having nodes representing the logic elements and edges representing potential pairs of the logic
elements;

determining a packing of pairs of the nodes to divide the graph into selected nodes and unselected nodes and selected edges
and unselected edges by performing iterations of:

identifying an augmenting path in the graph between a pair of unselected nodes; and
modifying the selected nodes and unselected nodes and the selected edges and unselected edges based on the augmenting path;
and
grouping the logic elements in the description into pairs of logic elements based on the packing of pairs of the nodes.

US Pat. No. 9,075,930

CONFIGURABLE EMBEDDED MEMORY SYSTEM

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a memory module, wherein the memory module is a reconfigurable hard macro and a first portion of the memory module comprises:
a data input multiplexer coupled to select between cascaded data and direct/bused data;
a memory coupled to receive output from the data input multiplexer for storage therein;
a register input multiplexer coupled to select between read data from the memory and the cascaded data;
a register coupled to receive output from the register input multiplexer;
a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register;
and

a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer
to provide output data.

US Pat. No. 9,530,022

PROTECTION OF DESIGNS FOR ELECTRONIC SYSTEMS

XILINX, INC., San Jose, ...

1. A method of protecting a design, comprising:
generating a plurality of implementations of the design, wherein each implementation includes a different embedded secret
and an identification function;

selecting one of the plurality of implementations as a current implementation for installation on one or more of a plurality
of target electronic systems;

installing the current implementation of the design on the one or more of the target electronic systems;
for each electronic system of the one or more of the target electronic systems,
generating by the identification function an output value based on the embedded secret;
determining whether or not the current implementation is an authorized version on the electronic system from the output value
of the identification function;

if the current implementation is not an authorized version on the electronic system, outputting a signal indicating that the
current implementation is not an authorized version on the electronic system;

periodically selecting one of the plurality of implementations other than the current implementation as a new current implementation
for installation on one or more others of the target electronic systems on which an implementation of the plurality of implementations
has not been installed; and

repeating the installing, determining, outputting, and periodically selecting using the new current implementation as the
current implementation on the one or more others of the target electronic systems.

US Pat. No. 9,377,802

DYNAMIC CONFIGURATION OF EQUIVALENT SERIES RESISTANCE

XILINX, INC., San Jose, ...

1. An integrated circuit (IC), comprising:
a power distribution network having a first set of power distribution lines connected to a source voltage and a second set
of power distribution lines connected to a ground voltage;

a first capacitor formed in the IC;
a first variable resistive element electrically coupled in series with the first capacitor between the first and second sets
of power lines of the power distribution network; and

a control circuit formed in the IC and coupled to the first variable resistive element, the control circuit configured and
arranged to:

adjust a level of resistance of the first variable resistive element in response to an input signal, wherein adjustment of
the level of resistance adjusts an equivalent series resistance of the power distribution network; and

after adjusting of the level of resistance of the first variable resistive element, monitor an operating temperature of the
IC and adjust the level of resistance of the first variable resistive element in response to and as a function of changes
in the operating temperature of the IC.

US Pat. No. 9,153,292

INTEGRATED CIRCUIT DEVICES HAVING MEMORY AND METHODS OF IMPLEMENTING MEMORY IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. An integrated circuit device having memory, the integrated circuit device comprising:
programmable resources having at least a first portion and a second portion;
programmable interconnect elements coupled to the programmable resources, the programmable interconnect elements enabling
a communication of signals with the programmable resources;

a plurality of memory blocks;
a first dedicated interconnect element comprising an input interconnect element coupled to the plurality of memory blocks,
the first dedicated interconnect element enabling the routing of data from the first portion of programmable resources to
selected memory blocks of the plurality of memory blocks by first data lines; and

a second dedicated interconnect element comprising an output interconnect element coupled to the plurality of memory blocks
by second data lines, the second dedicated interconnect element enabling the routing of the data from the selected memory
blocks to the second portion of programmable resources;

wherein the programmable resources comprise a plurality of SRAM blocks each having a first size, and each memory block of
the plurality of memory blocks is an SRAM block having a second size which is larger than the first size.

US Pat. No. 9,608,871

INTELLECTUAL PROPERTY CORES WITH TRAFFIC SCENARIO DATA

XILINX, INC., San Jose, ...

1. A method, comprising:
determining, using a processor of a data processing system, data traffic patterns stored within a core library of an electronic
design automation system;

wherein the data traffic patterns are specified by cores stored within the core library;
displaying, using a display device, the determined data traffic patterns as modeling options;
receiving a user input selecting a displayed data traffic pattern associated with a selected core; and
executing the selected data traffic pattern as part of modeling an electronic system to generate data traffic that mimics
operation of the selected core by programming an emulation circuit implemented within an integrated circuit with the selected
data traffic pattern and executing the selected data traffic pattern to generate the data traffic between the emulation circuit
and a processor system of the integrated circuit.

US Pat. No. 9,449,131

EXTRACTING SYSTEM ARCHITECTURE IN HIGH LEVEL SYNTHESIS

XILINX, INC., San Jose, ...

1. A method, comprising:
determining a first function of a high level programming language description and a second function contained within a control
flow construct of the high level programming description;

determining that the second function is a data consuming function of the first function;
automatically generating, within a circuit design and using a processor, a port comprising a local memory, wherein the port
couples a first circuit block implementation of the first function to a second circuit block implementation of the second
function within the circuit design; and

automatically generating, within the circuit design, control circuitry controlling operation of the second circuit block by
performing handshake signaling between the first circuit block and the second circuit block as a non-self-synchronized port.

US Pat. No. 9,378,102

SAFETY HARDWARE AND/OR SOFTWARE FAULT TOLERANCE USING REDUNDANT CHANNELS

XILINX, INC., San Jose, ...

1. A system on a chip (SoC) for providing safety hardware fault tolerance and/or safety software fault tolerance, comprising:
a first safety sub-system having a first safety channel;
a second safety sub-system having a second safety channel; and
a third sub-system;
wherein the first safety sub-system is independent of the second safety sub-system to allow the second safety sub-system to
communicate through the second safety channel when the first safety sub-system or the third sub-system fails, and further
to allow the first safety sub-system to communicate through the first safety channel when the second safety sub-system or
the third sub-system fails.

US Pat. No. 9,379,920

DECISION FEEDBACK EQUALIZATION WITH PRECURSOR INTER-SYMBOL INTERFERENCE REDUCTION

XILINX, INC., San Jose, ...

1. A receiver for coupling to a communications channel, comprising:
a decision feedback equalizer for receiving an analog input signal, wherein the decision feedback equalizer includes a filter
for subtracting a plurality of weighted postcursor decisions from the analog input signal to provide an analog output signal;

a postcursor decision circuit coupled to the decision feedback equalizer for receiving the analog output signal and comparing
the analog output signal against positive and negative values of a postcursor coefficient to provide a first possible decision
and a second possible decision, respectively, and for selecting a current postcursor-based decision as between the first possible
decision and the second possible decision responsive to a previous postcursor-based decision; and

a precursor cancellation circuit for receiving the analog output signal, the previous postcursor-based decision and the current
postcursor-based decision for providing a digital output signal for a previous sample of the analog input signal.

US Pat. No. 9,336,010

MULTI-BOOT OR FALLBACK BOOT OF A SYSTEM-ON-CHIP USING A FILE-BASED BOOT DEVICE

XILINX, INC., San Jose, ...

1. A method, comprising:
initiating a boot of a system-on-chip coupled to a boot device;
wherein the boot is initiated from boot code stored in nonvolatile memory of the system-on-chip responsive to a power-on-reset;
and

under control of the boot code, performing the following operations:
loading a first register value into a register of the system-on-chip;
accessing a name string from the boot code;
obtaining the first register value from the register;
converting the first register value and the name string to a first string value;
wherein the first string value is provided as a first filename;
searching the boot device for a boot image file with the first filename; and
in response to finding the first filename in the boot device,
validating the boot image having the first filename; and
in response to the boot image being invalid,
incrementing the first register value to provide a second register value; and
repeating the obtaining, converting, and searching using a second filename generated using the second register value, wherein
a valid filename for the boot image file is iteratively generated;

if the first filename is not found in the boot device,
incrementing the first register value to provide the second register value; and
repeating the obtaining, converting, and searching using the second filename generated using the second register value, wherein
a valid filename for the boot image file is iteratively generated.

US Pat. No. 9,237,047

CIRCUITS FOR AND METHODS OF RECEIVING DATA IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A circuit for receiving data in an integrated circuit, the circuit comprising:
a receiver configured to receive an input signal and to generate output data based upon the input signal, the receiver having
a level detection circuit coupled to receive the input signal; and

a calibration circuit coupled to the receiver, the calibration circuit having:
an input for receiving the input signal;
an error detection circuit coupled to the input, the error detection circuit coupled to receive the input signal, a first
reference voltage and a second reference voltage; and

a control circuit coupled to an output of the error detection circuit, wherein the control circuit selectively generates either
an offset control signal or an amplitude control signal based upon comparisons of the input signal to the first reference
voltage and the second reference voltage.

US Pat. No. 9,152,794

SECURE KEY HANDLING FOR AUTHENTICATION OF SOFTWARE FOR A SYSTEM-ON-CHIP

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
an image generator coupled to receive partitions and a public key and configured to generate respective hashes of the partitions
and a hash of the public key;

a signature generator in communication with the image generator to generate respective signatures for the hashes of the partitions
in association with the public key and a signature of the hash of the public key;

wherein the image generator and the signature generator are programmed into a general-purpose computer to provide a special-purpose
computer;

wherein the special-purpose computer is configured to output an image file for an embedded device; and
wherein the image file includes the public key, the signatures of the hashes of the partitions, and the signature of the hash
of the public key.

US Pat. No. 9,276,782

PRECURSOR INTER-SYMBOL INTERFERENCE REDUCTION

XILINX, INC., San Jose, ...

1. A receiver for coupling to a communications channel, comprising:
a precursor iterative canceller having a first path and a second path,
a postcursor decision block coupled to the precursor iterative canceller to provide a decision signal thereto;
wherein the precursor iterative canceller comprises:
a plurality of comparators for receiving an input signal and for receiving corresponding threshold inputs, the threshold inputs
for precursor inter-symbol interference (“ISI”) speculation;

select circuits for selecting a first speculative input for the first path and a second speculative input for the second path,
the first speculative input and the second speculative input are respectively associated with a negative precursor contribution
and a positive precursor contribution;

wherein the first path and the second path in combination include at least a first stage and a second stage for processing
the first speculative input and the second speculative input;

wherein the decision signal is provided to the first stage and to the select circuits; and
wherein the select circuits are coupled to receive the decision signal for selection of the first speculative input and the
second speculative input.

US Pat. No. 9,484,919

SELECTION OF LOGIC PATHS FOR REDUNDANCY

XILINX, INC., San Jose, ...

1. A method of processing a circuit design for protecting against single event upsets (SEUs), comprising:
performing on a programmed processor operations including:
selecting a logic path of the circuit design for redundancy based on a total of failure rates of circuit elements in the logic
path being greater than a product of a target reduction in failure rate of the logic path and a failure rate of a voting circuit;

modifying the circuit design to include at least three instances of the logic path coupled in parallel and the voting circuit
coupled to receive output signals from the at least three instances; and

storing the circuit design as modified in a processor readable memory.

US Pat. No. 9,405,871

DETERMINATION OF PATH DELAYS IN CIRCUIT DESIGNS

XILINX, INC., San Jose, ...

1. A method of determining delays, comprising:
performing on a computer processor, operations including:
inputting a circuit design having a plurality of paths, each path having a source storage element coupled to a destination
storage element through a signal route;

determining whether or not each path of the plurality of paths matches a path definition of a plurality of path definitions
in a path database;

for each path of the plurality of paths that matches one of the plurality of path definitions, reading from the path database
a first path delay value associated with the one path definition and associating the first path delay value from the path
database with the path;

for each path of the plurality of paths that does not match any of the plurality of path definitions:
reading respective element delay values of elements of the path from an element database; and
computing a second path delay value of the path as a function of the respective element delay values and associating the second
path delay value with the path; and

outputting each first path delay value, each second path delay value and information indicating the associated paths.

US Pat. No. 9,223,910

PERFORMANCE AND MEMORY EFFICIENT MODELING OF HDL PORTS FOR SIMULATION

XILINX, INC., San Jose, ...

1. A method of compiling a hardware description language (HDL) specification for simulation of a circuit design, the method
comprising:
using one or more processors, performing operations including:
elaborating the circuit design from the HDL specification;
allocating memory locations for formals and actuals of the elaborated circuit design, the allocating of memory locations including:
for each port of the elaborated circuit design having a formal and an actual that are compatible, setting a reference pointer
for the formal and a reference pointer for the actual to reference a same one of the memory locations; and

for each port of the elaborated circuit design having a formal and an actual that are incompatible, setting the reference
pointer for the formal and the reference pointer for the actual to reference different respective ones of the memory locations;
and

generating simulation code that models the elaborated circuit design, the simulation code configured and arranged to, during
simulation runtime, for each set of a formal and an actual having reference pointers that reference the same one of the memory
locations and in response to a call to an update function corresponding to the set, update the formal and the actual of the
set using a single write operation to the same memory location referenced by the reference pointers of the formal and the
actual, thereby using fewer computation and memory resources during simulation runtime in comparison to a set of a formal
and an actual having incompatible reference pointers.

US Pat. No. 9,178,503

DIFFERENTIAL COMPARATOR CIRCUIT HAVING A WIDE COMMON MODE INPUT RANGE

XILINX, INC., San Jose, ...

1. A circuit arrangement, comprising:
a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second
differential amplifier;

for each differential amplifier, a respective adjustable current control circuit coupled to the differential amplifier to
limit a tail current passing through the differential amplifier, the adjustable current control circuit being configured to
operate in one state of a discrete set of states including fully-on, fully-off, and partially-on, wherein operation of the
adjustable current control circuit in the partially-on state causes the differential amplifier to exhibit non-linearity; and

a gain control circuit coupled to the adjustable current control circuits, the gain control circuit configured to adjust,
while the adjustable current control circuits for two or more of the plurality of differential amplifiers are operated in
respective states other than the fully-off state, the adjustable current control circuits such that only one of the plurality
of respective current control circuits can be operated in the partially-on state at a given time, thereby limiting non-linearity
exhibited by the plurality of differential amplifiers.

US Pat. No. 9,088,399

CIRCUIT AND METHOD FOR TESTING JITTER TOLERANCE

XILINX, INC., San Jose, ...

1. A transceiver circuit, comprising:
an input terminal and an output terminal;
a transmitter circuit having an output coupled to the output terminal, the transmitter including a phase interpolation circuit,
a phase locked loop (PLL) circuit, and an emphasis circuit;

a receiver circuit having an input coupled to the input terminal;
a loopback path configured to provide a signal transmitted by the transmitter circuit on the output terminal to the input
of the receiver circuit; and

a test control circuit configured and arranged to introduce jitter in the signal transmitted by the transmitter circuit when
the test control circuit is operating in a self-test mode but not when the test control circuit is operating in a non-test
mode, wherein the test control circuit is configured and arranged to introduce the jitter in the signal by adjusting one or
more parameters of each of the phase interpolation circuit, the PLL circuit, and the emphasis circuit.

US Pat. No. 9,652,252

SYSTEM AND METHOD FOR POWER BASED SELECTION OF BOOT IMAGES

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a memory circuit disposed on an integrated circuit (IC) die;
a processor disposed on the IC die, coupled to the memory circuit, and configured and arranged to retrieve and execute instructions
from the memory circuit;

a power management circuit disposed on the IC die and configured to determine a value indicative of an amount of power available
to power the IC die; and

a boot loader circuit disposed on the IC die, coupled to the power management circuit, and configured to:
select one of a plurality of boot images based on the determined value indicative of the amount of power available and respective
power ranges associated with the plurality of boot images, wherein each power range of the respective power ranges is a function
of a size of the associated boot image;

load a set of instructions included in the selected one of the boot images into the memory circuit; and
enable the processor to execute the set of instructions.

US Pat. No. 9,500,700

CIRCUITS FOR AND METHODS OF TESTING THE OPERATION OF AN INPUT/OUTPUT PORT

XILINX, INC., San Jose, ...

1. A circuit for testing the operation of an input/output port of an integrated circuit device, the circuit comprising:
a first input/output port having a first input/output pad configured to receive a test signal, a test signal output, and an
input signal line enabling the transfer of data between the first input/output port and other circuits of the integrated circuit
device; and

a second input/output port having a second input/output pad and a selection circuit configured to receive the test signal
and an output signal, the selection circuit enabling routing the test signal received by way of the first input/output pad
and the test signal output of the first input/output port to the second input/output pad.

US Pat. No. 9,418,966

SEMICONDUCTOR ASSEMBLY HAVING BRIDGE MODULE FOR DIE-TO-DIE INTERCONNECTION

XILINX, INC., San Jose, ...

1. A semiconductor assembly, comprising:
a first integrated circuit (IC) die having, on a top side thereof, first solder bumps of a plurality of solder bumps and first
inter-die contacts of a plurality of inter-die contacts;

a second IC die having, on a top side thereof, second solder bumps of the plurality of solder bumps and second inter-die contacts
of the plurality of inter-die contracts; and

a bridge module disposed between the first solder bumps and the second solder bumps, the bridge module including:
bridge interconnects on a top side of the bridge module, the bridge interconnects mechanically and electrically coupled to
the plurality of inter-die contacts; and

one or more layers of conductive interconnect disposed on the top side of the bridge module configured to route signals between
the first IC and the second IC; and

wherein a back side of the bridge module does not extend beyond a height of the plurality of solder bumps.

US Pat. No. 9,348,619

INTERACTIVE DATASHEET SYSTEM

XILINX, INC., San Jose, ...

1. A method of estimating performance of an electronic system on a programmable integrated circuit (IC), comprising:
providing a user interface for selection of a previously specified scenario from a plurality of previously specified scenarios,
wherein each previously specified scenario includes a previously specified topology of the electronic system, one or more
previously specified parameter values applied to the electronic system, a previously specified traffic profile, and respective
precompiled values of a plurality of measurands including at least a read latency and a write latency;

wherein the programmable IC includes a processor and programmable logic resources;
in response to user selection of one of the previously specified scenarios, reading from a database respective precompiled
values of the measurands associated with the one scenario and displaying the respective precompiled values of the measurands;

wherein the user interface further provides for specification of a scenario, including specification of a topology of the
electronic system, specification of one or more parameter values to apply to the electronic system, specification of a traffic
profile, and selection of at least one measurand;

wherein specification of the traffic profile includes specification of a selectable ratio of read transactions and write transactions
and a selectable one of a linear addressing mode or a random addressing mode;

in response to user specification of a scenario, configuring traffic emulation circuitry in the programmable IC to execute
the specified scenario;

emulating the system with the traffic emulation circuitry configured to execute the specified scenario, the emulating including
generating stimuli and measuring responses for determining a value of the at least one measurand;

computing the value of the at least one measurand;
storing the computed value of the at least one measurand in association with the specified scenario in the database; and
displaying the computed value of the at least one measurand.

US Pat. No. 9,230,112

SECURED BOOTING OF A FIELD PROGRAMMABLE SYSTEM-ON-CHIP INCLUDING AUTHENTICATION OF A FIRST STAGE BOOT LOADER TO MITIGATE AGAINST DIFFERENTIAL POWER ANALYSIS

XILINX, INC., San Jose, ...

1. A system, comprising:
a system-on-chip (“SoC”) having dedicated hardware including a processing unit,
a first internal memory, a second internal memory, an authentication engine, and a decryption engine;
a storage device coupled to the SoC;
wherein the storage device has access to a boot image including a configuration information;
wherein the first internal memory has boot code stored therein;
wherein the boot code is for a secure boot of the SoC;
wherein the boot code is configured to cause the processing unit to control the secure boot;
wherein the SoC comprises a field programmable system-on-chip (“FPSoC”);
wherein the boot code under control of the processing unit is configured to authenticate a first stage bootloader (“FSBL”)
of the boot image; and

wherein the FSBL is configured for pre-authentication by the decryption engine to limit an amount of data of the FSBL to mitigate
against Differential Power Analysis;

wherein the boot image further includes a second stage bootloader (“SSBL”), the boot image having a first partition for the
FSBL and a second partition for the SSBL; and

wherein the configuration information is for a decryptor for authentication of the FSBL.

US Pat. No. 9,183,338

SINGLE-EVENT UPSET MITIGATION IN CIRCUIT DESIGN FOR PROGRAMMABLE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A method of implementing a circuit design for a programmable integrated circuit (IC), comprising:
identifying combinatorial logic functions of the circuit design;
mapping, according to a first constraint, a first threshold percentage of the combinatorial logic functions onto a first type
of lookup tables (LUTs) of the programmable IC in favor of second type of LUTs of the programmable IC, the second type of
LUTs being more susceptible to single event upsets than the first type of LUTs; and

generating a first physical implementation of the circuit design for the programmable IC based on the mapping.

US Pat. No. 9,438,409

CENTERING BAUD-RATE CDR SAMPLING PHASE IN A RECEIVER

XILINX, INC., San Jose, ...

1. An apparatus for clock data recovery (CDR), comprising:
a data slicer operable to generate data samples derived from a transmitted signal;
an error slicer operable to generate error samples derived from the transmitted signal;
a CDR circuit operable to generate a common sampling clock phase for both the data slicer and the error slicer from output
of the data samples and the error samples; and

a decision adapt circuit operable to set a decision threshold of the error slicer, wherein for each main-cursor data sample
of the data samples the decision adapt circuit is operable to adjust the decision threshold based on a sum of at least one
term, each of the at least one term being a product of a scalar and one of a pre-cursor data sample or a post-cursor data
sample.

US Pat. No. 9,270,517

TUPLE CONSTRUCTION FROM DATA PACKETS

XILINX, INC., San Jose, ...

10. A packet processing circuit, comprising:
a plurality of pipeline stages, each stage including:
a field extraction circuit configured to receive a data packet and configurable to extract none or a plurality of packet field
values from the data packet; and

a tuple construction circuit coupled to receive an input tuple, a respective programmable offset value, and each packet field
value from the field extraction circuit, the tuple construction circuit configured to insert a respective tuple field value
based on the received packet field values into the input tuple at a respective offset and output a tuple having the inserted
respective tuple field value;

wherein each tuple construction circuit includes:
a first circuit configured to:
create a mask word in a mask register having a subset of bits equal in number to a number of bits of the respective tuple
field value and positioned in the mask word in response to the respective programmable offset value, and

clear bits of the input tuple using the subset of bits in the mask word; and
a second circuit configured to replace the cleared bits of the input tuple with the respective tuple field value.

US Pat. No. 9,245,886

SWITCH SUPPORTING VOLTAGES GREATER THAN SUPPLY

XILINX, INC., San Jose, ...

1. A device, comprising:
a first p-type metal oxide semiconductor transistor, wherein a source of the first p-type metal oxide semiconductor transistor
is connected to an input of the device; and

a first circuit, for delivering a signal on the input of the device to a gate of the first p-type metal oxide semiconductor
transistor when an enable signal is deactivated and for delivering a ground voltage to the gate of the first p-type metal
oxide semiconductor transistor when the enable signal is activated, wherein the first circuit comprises:

a second p-type metal oxide semiconductor transistor, wherein a source of the second p-type metal oxide semiconductor transistor
is connected to the input of the device and wherein a gate of the second p-type metal oxide semiconductor transistor is connected
to the enable signal;

a first n-type metal oxide semiconductor transistor, wherein a source of the first n-type metal oxide semiconductor transistor
is connected to ground, wherein a drain of the first n-type metal oxide semiconductor transistor is connected to a drain of
the second p-type metal oxide semiconductor transistor, wherein a gate of the first n-type metal oxide semiconductor transistor
is connected to the enable signal; and

a second n-type metal oxide semiconductor transistor, wherein a gate of the second n-type metal oxide semiconductor transistor
is connected to an inversion of the enable signal, wherein a source of the second n-type metal oxide semiconductor transistor
is connected to the input of the device, and wherein the drain of the second p-type metal oxide semiconductor transistor,
the drain of the first n-type metal oxide semiconductor transistor, and a drain of the second n-type metal oxide semiconductor
transistor are connected to the gate of the first p-type metal oxide semiconductor transistor.

US Pat. No. 9,183,339

SYSTEM AND METHOD FOR PREPARING PARTIALLY RECONFIGURABLE CIRCUIT DESIGNS

XILINX, INC., San Jose, ...

1. A method of preparing a partially reconfigurable circuit design, comprising:
creating, by a computer processor, a circuit design in a computer memory in response to user input to the computer processor,
the circuit design having a static portion;

instantiating a virtual socket in the circuit design in response to user input;
instantiating decouplers in the virtual socket for the reconfigurable modules;
instantiating one or more reconfigurable modules in the virtual socket in response to user input;
coupling one or more modules of the static portion to the one or more reconfigurable modules via the decouplers; and
generating configuration data from the circuit design, the configuration data including a configuration bitstream corresponding
to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more
reconfigurable modules.

US Pat. No. 9,058,135

SYNCHRONIZATION OF TIMERS ACROSS CLOCK DOMAINS IN A DIGITAL SYSTEM

XILINX, INC., San Jose, ...

1. A method of testing a digital system, comprising:
calculating a first ratio of a first clock frequency for a first clock domain and a second clock frequency for a second clock
domain different from the first clock domain using a processing device;

calculating a first offset between a first timer in the first clock domain and a second timer in the second clock domain using
the processing device; and

using an expression dependent upon the first offset and the first ratio, converting event data from at least one of the first
clock domain or the second clock domain to a common clock domain;

wherein calculating the ratio comprises:
responsive to receiving a first timer value from the first timer within the second clock domain, determining a first timer
value from the second timer in the second clock domain:

responsive to receiving a second timer value from the first timer within the second clock domain, determining a second timer
value from the second timer in the second clock domain; and

the second timer value from the first timer is sent responsive to a message sent from the second clock domain to the first
clock domain responsive to the first timer value from the first timer.

US Pat. No. 9,054,645

PROGRAMMABLE RECEIVERS IMPLEMENTED IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. A programmable receiver implemented in an integrated circuit device, the programmable receiver comprising:
a pre-amplifier circuit coupled to receive an input signal, the pre-amplifier circuit having a programmable current source;
and

an amplifier circuit coupled to receive an output of the pre-amplifier circuit;
wherein the pre-amplifier circuit comprises a first conductive path coupled to a first input of the amplifier circuit and
a second conductive path coupled to a second input of the amplifier circuit, and the programmable current source controls
a current in at least one of the first conductive path or the second conductive path; and

wherein the programmable current source is coupled to receive a control signal to enable the receiver to be switched between
a high performance mode and a low performance mode.

US Pat. No. 9,652,570

AUTOMATIC IMPLEMENTATION OF A CUSTOMIZED SYSTEM-ON-CHIP

XILINX, INC., San Jose, ...

1. A computer-implemented method of implementing a system-on-chip design specified as a high level programming language application,
comprising:
querying, using the computer, a platform description to determine an available interface of a platform for a target integrated
circuit, wherein the platform is a circuit design adapted for implementation in the target integrated circuit, and the platform
description specifies existing interfaces of the platform not in use;

generating, using the computer, hardware for a function of the high level programming language application and hardware coupling
the function with the available interface of the platform, wherein the generated hardware is for hardware accelerating the
function;

modifying, using the computer, the high level programming language application with program code configured to access the
generated hardware for the function; and

building, using the computer, the hardware and the software of the system-on-chip design.

US Pat. No. 9,614,537

DIGITAL FRACTIONAL-N MULTIPLYING INJECTION LOCKED OSCILLATOR

XILINX, INC., San Jose, ...

1. A clock generator circuit, comprising:
a fractional reference generator configured to generate a reference clock in response to a base reference clock and a phase
error signal, the reference clock having a frequency that is a rational multiple of a frequency of the base reference clock;

a digitally controlled delay line (DCDL) configured to delay the reference clock based on a first control code;
a pulse generator configured to generate pulses based on the delayed reference clock;
a digitally controlled oscillator (DCO) including an injection input coupled to the pulse generator to receive the pulses,
the DCO configured to generate an output clock based on the pulses and a second control code;

a phase detector configured to compare phases of the output clock and the reference clock and generate the phase error signal;
and

a control circuit configured to generate the first and second control codes based on the phase error signal.

US Pat. No. 9,606,572

CIRCUITS FOR AND METHODS OF PROCESSING DATA IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. A circuit for processing data in an integrated circuit device, the circuit comprising:
a lookup table;
a selection circuit coupled to the lookup table;
a first register coupled to a first output of the selection circuit;
a second register implemented as a latch and coupled to a second output of the selection circuit;
a signal line coupled between the output of the first register and an input of the selection circuit;
a configuration memory having configuration bits for configuring the selection circuit to enable the coupling of the output
of the first register to an input of the second register; and

a first clock control circuit having a clock selection multiplexer coupled to receive the clock signal at a first input and
further coupled to receive an inverted clock signal generated at the output of the first inverter at a second input;

wherein the clock signal is coupled to a clock input of the first register and an output of the clock selection multiplexer
is coupled to a clock input of the second register;

wherein the selection circuit enables the coupling of an output signal of the first register to the input of the second register.

US Pat. No. 9,503,301

NOISE-SHAPING CREST FACTOR REDUCTION WITH POLYPHASE TRANSFORMING

XILINX, INC., San Jose, ...

1. An apparatus for data communication, comprising:
a delay coupled to receive a composite signal having multiple carriers to provide a delayed version of the composite signal;
a waveform generator coupled to receive the composite signal to provide a waveform;
wherein the waveform generator is coupled for noise-shaping crest factor reduction;
a signal combiner coupled to the delay to receive the delayed version of the composite signal and coupled to the waveform
generator to receive the waveform; and

wherein the signal combiner is coupled to reduce at least one peak in the delayed version of the composite signal by application
of the waveform to the delayed version of the composite signal for peak-to-average power ratio reduction thereof;

wherein the waveform generator comprises:
a threshold and clip block coupled to receive the composite signal to provide clipping noise with the composite signal;
a polyphase transform block coupled to convert the clipping noise with the composite signal to first spectrally translated
components channelized for channels corresponding to the multiple carriers;

a filter block coupled to receive the first spectrally translated components to provide filtered components corresponding
to the first spectrally translated components for removing therefrom original components of the composite signal, as well
as some in-band and out-of-band distortion; and

an inverse polyphase transform block coupled to receive the filtered components to provide second spectrally translated components
for composition as the waveform.

US Pat. No. 9,495,302

VIRTUALIZATION OF MEMORY FOR PROGRAMMABLE LOGIC

XILINX, INC., San Jose, ...

1. An electronic system, comprising:
a processing sub-system configured to execute a program using a set of virtual memory addresses to reference memory locations
for storage of variables of the program;

a programmable logic sub-system configured to implement a set of circuits specified in a configuration data stream, the set
of circuits including a plurality of input/output circuits, each input/output circuit having a respective identifier (ID)
and configured to access a respective one of the variables;

a memory;
a memory management circuit configured to:
map the set of virtual memory addresses to physical memory addresses of the memory; and
for each of the plurality of input/output circuits that accesses the respective one of the variables, map the respective ID
of the input/output circuit to the physical memory address that corresponds to the variable; and

at least one translation look-aside buffer (TLB) coupled to at least one input/output circuit of the plurality of input/output
circuits, the at least one translation look-aside buffer configured to determine, in response to receiving a memory access
request indicating an ID, a physical memory address based on the ID indicated in the memory access request and not on a virtual
address, and provide to the memory a memory access request indicating the physical memory address.

US Pat. No. 9,460,253

SELECTING PREDEFINED CIRCUIT IMPLEMENTATIONS IN A CIRCUIT DESIGN SYSTEM

XILINX, INC., San Jose, ...

1. A method of processing a circuit design, comprising:
determining a first partition in a description of the circuit design having a hierarchy of design objects, the first partition
including at least one design object in the hierarchy of design objects;

generating a signature for the first partition using a hash function, the signature being a hash value generated by the hash
function based on input of parameter values and a circuit design language description of one or more design objects of the
first partition;

querying a database, which includes entries that relate signatures to predefined implementations, with the signature of the
first partition to identify a plurality of predefined implementations of the first partition; and

generating an implementation of the circuit design for a target integrated circuit (IC) based on a selected predefined implementation
of the plurality of predefined implementations for the first partition.

US Pat. No. 9,460,007

PROGRAMMABLE HARDWARE BLOCKS FOR TIME-SHARING ARITHMETIC UNITS USING MEMORY MAPPING OF PERIODIC FUNCTIONS

XILINX, INC., San Jose, ...

1. An apparatus for time sharing of an arithmetic unit, comprising:
a controller coupled to provide read pointers and write pointers for a pattern representing a function;
a memory block coupled to receive the read pointers and the write pointers;
a selection network coupled to the memory block and the arithmetic unit;
wherein the memory block comprises a write-data network, a read-data network, and memory banks; and
the memory block configured to receive the read pointers and the write pointers to dynamically control the selection network
for time multiplexing and context switching of the arithmetic unit for the pattern.

US Pat. No. 9,444,618

DEFENSE AGAINST ATTACKS ON RING OSCILLATOR-BASED PHYSICALLY UNCLONABLE FUNCTIONS

XILINX, INC., San Jose, ...

1. A circuit, comprising:
a ring oscillator-based physically unclonable function (PUF);
a control circuit coupled to the ring oscillator-based PUF;
a non-volatile memory coupled to the control circuit and configured with a plurality of frequency-versus-time profiles, each
frequency-versus-time profile associated with a different operating temperature; and

wherein the control circuit is configured to monitor operating conditions of the ring oscillator-based PUF, disable the ring
oscillator-based PUF in response to the operating conditions being out-of-tolerance, and enable the ring oscillator-based
PUF in response to the operating conditions being in-tolerance;

wherein the control circuit includes:
a temperature sensor configured and arranged to measure a temperature of the ring oscillator-based PUF; and
a frequency monitor coupled to the temperature sensor and configured and arranged to sample frequencies of a ring oscillator
of the ring oscillator-based PUF over a sample period when the temperature is measured, generate a measured frequency-versus-time
profile based on the sampled frequencies, and compare the measured frequency-versus-time profile to one of the plurality of
frequency-versus-time profiles corresponding to the measured temperature to determine whether or not the sampled frequencies
are within an acceptable range for the temperature and detect out-of-tolerance operation of the ring oscillator-based PUF;

wherein the control circuit is further configured to:
count 0 values and 1 values of the output signal from the ring oscillator during the sample period;
detect out-of-tolerance operation of the ring oscillator-based PUF in response to all logic 0 values or all logic 1 values
in the sample period;

monitor a level of current drawn by a ring oscillator of the ring oscillator-based PUF to detect out-of-tolerance operation
of the ring oscillator-based PUF;

monitor a frequency of an output signal from a ring oscillator of the ring oscillator-based PUF for a period of time beginning
at initial application of power to the ring oscillator-based PUF to detect out-of-tolerance operation of the ring oscillator-based
PUF; and

monitor an electromagnetic field proximate the ring oscillator-based PUF to detect out-of-tolerance operation of the ring
oscillator-based PUF.

US Pat. No. 9,432,121

OPTICAL COMMUNICATION CIRCUITS

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
an optical serializer, including:
a plurality of optical modulators, each configured and arranged to receive a respective bit of a parallel N-bit data bus,
the respective bit having a first bit period, and output a respective optical pulse representing a value of the respective
bit and having a duration less than the first bit period, wherein N is greater than or equal to 2;

for each of the plurality of optical modulators, a respective optical delay line configured and arranged to delay the respective
optical pulses of the optical modulator by a respective length of time unique to the optical modulator to produce a respective
optical output signal; and

an optical combiner configured and arranged to combine the respective optical output signals produced by the optical delay
line into a single optical beam.

US Pat. No. 9,378,003

COMPILER DIRECTED CACHE COHERENCE FOR MANY CACHES GENERATED FROM HIGH-LEVEL LANGUAGE SOURCE CODE

XILINX, INC., San Jose, ...

16. A method for operating an electronic system, comprising:
executing software on a processor, the software including a call to a hardware function and accessing an address space;
initiating the hardware function on a function accelerator in response to the call to the hardware function by the software;
storing data accessed by the hardware function in a plurality of caches on the function accelerator, wherein each cache is
dedicated to a particular region of the address space;

for each of the plurality of caches to which the hardware function stores data, generating a respective flush signal in response
to a flush instruction in the software that follows an instruction in the software that is the last to store a data item in
the cache by the hardware function; and

transferring, in response to a respective flush signal to one of the plurality of caches, data from the one of the caches
to a memory that is accessible to the software executing on the processor.

US Pat. No. 9,224,697

MULTI-DIE INTEGRATED CIRCUITS IMPLEMENTED USING SPACER DIES

XILINX, INC., San Jose, ...

1. An integrated circuit, comprising:
an interposer die comprising a surface;
a first die mechanically and electrically attached to the surface of the interposer die;
a second die only mechanically attached to the surface of the interposer die using a die attach adhesive;
a third die mechanically and electrically attached to the first surface of the interposer die; and
wherein the first die and the third die are communicatively linked by a wire of the interposer die.

US Pat. No. 9,213,866

CIRCUITS FOR AND METHODS OF PREVENTING UNAUTHORIZED ACCESS IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A circuit for preventing unauthorized access in an integrated circuit, the circuit comprising:
a plurality of circuit blocks; and
a plurality of protection circuits, each protection circuit being coupled to an input of a corresponding circuit block of
the plurality of circuit blocks;

wherein each protection circuit determines whether an access request to the corresponding circuit block is authorized;
wherein a protection circuit of the plurality of protection circuits generates a poisoned request if it is determined that
an access request is not authorized; and

wherein the poisoned request comprises an address associated with a poisoned address space.

US Pat. No. 9,166,584

CURRENT-ENCODED SIGNALING

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a first logic block including:
a first voltage-mode logic (VML) circuit configured and arranged to provide a first voltage-encoded binary signal; and
an encoder circuit configured and arranged to convert the first voltage-encoded binary signal to a current-encoded binary
signal, wherein the encoder circuit is further configured and arranged to:

set the current-encoded binary signal to have a current greater than a threshold current in response to the first voltage-encoded
binary signal having a logic-high value; and

set the current-encoded binary signal to have a current less than the threshold current in response to the first voltage-encoded
binary signal having a logic-low value; and

a second logic block including:
a decoder circuit configured and arranged to receive the current-encoded binary signal from the first logic block and convert
the current-encoded binary signal to a second voltage-encoded binary signal, wherein logic states encoded by the second voltage-encoded
binary signal are equal to logic states encoded by the first voltage-encoded binary signal;

a second VML circuit coupled to the decoder circuit and configured and arranged to receive and process the second voltage-encoded
binary signal.

US Pat. No. 9,935,604

VARIABLE BANDWIDTH FILTERING

XILINX, INC., San Jose, ...

1. An apparatus for variable bandwidth filtering, comprising:an analysis filter bank having path filters associated with different bandwidths and configured for filtering and transforming an input signal having a first bandwidth into a first interleaved output,
wherein the first interleaved output includes a plurality of narrowband time signals having bands with alternating first width and second width different from the first width;
a mask coupled to the analysis filter bank and configured for masking at least one narrowband time signal of the first interleaved output;
a synthesis filter bank coupled to the mask and configured for transforming and filtering the masked first interleaved output to generate a second interleaved output for constructing an output signal having a second bandwidth; and
wherein the second bandwidth is different than the first bandwidth for the variable bandwidth filtering.

US Pat. No. 9,450,569

VERY LOW POWER REAL TIME CLOCK

XILINX, INC., San Jose, ...

1. A real-time clock system, comprising:
a real-time clock core module operable in a first power supply domain, the real-time clock core module including a tick counter
operable to advance a seconds counter based on an oscillator input; and

a real-time clock controller operable in a second power supply domain and operable to provide an interface for reading a seconds
count from the seconds counter,

wherein the first power supply domain is powered by a battery when an electronic device that includes the real-time clock
system is powered off and by a real-time clock core power supply when the electronic device is powered on, and

wherein the second power supply domain is unpowered when the electronic device is powered off and is powered by a real-time
clock controller power supply when the electronic device is powered on.

US Pat. No. 9,438,244

CIRCUITS FOR AND METHODS OF CONTROLLING POWER WITHIN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A circuit for controlling power within an integrated circuit, the circuit comprising:
a plurality of circuit blocks;
a global control signal routed within the integrated circuit; and
a plurality of power control blocks, wherein each power control block is coupled to a corresponding circuit block of the plurality
of circuit bocks and has a first input configured to receive a reference voltage and a second input configured to receive
the global control signal;

wherein each power control block further comprises a selection circuit having a first input configured to receive the global
control signal, a second input configured to receive a second control signal, and a third input configured to receive a power
control signal;

wherein the global control signal when selected enables, for each circuit block, a coupling of the reference voltage to a
first input of the corresponding circuit block; and

wherein the power control signal enables, for each circuit block, a selection of the global control signal or the second control
signal to enable an operating mode of the circuit block.

US Pat. No. 9,377,795

TEMPERATURE CORRECTION OF AN ON-CHIP VOLTAGE REFERENCE

XILINX, INC., San Jose, ...

1. A temperature-corrected voltage reference circuit for use in an integrated circuit (IC), comprising:
a voltage reference circuit;
a programmable gain amplifier having a first input coupled to the voltage reference circuit, a second input coupled to receive
a control signal, and an output coupled to provide a temperature-corrected voltage reference; and

a digital control circuit having an input coupled to receive a temperature signal indicative of temperature of the IC and
an output coupled to the second input of the programmable gain amplifier, the digital control circuit including a memory storing
trim data that includes a control code associated with a first gain corresponding to a reference temperature and a temperature
profile that includes a plurality of codes for selecting gain values corresponding to temperatures above and below the reference
temperature, the digital control circuit generating the control signal in response to the temperature signal and based on
the trim data and the temperature profile.

US Pat. No. 9,235,498

CIRCUITS FOR AND METHODS OF ENABLING THE MODIFICATION OF AN INPUT DATA STREAM

XILINX, INC., San Jose, ...

1. A circuit for enabling a modification of a data stream, the circuit comprising:
a first plurality of registers coupled in series;
an input register of the first plurality of registers coupled to receive an input data stream;
an output register of the first plurality of registers positioned at an end of the first plurality of registers; and
a control circuit for providing a data value which is independent of the input data stream at an input of a register of the
plurality of registers and generated at an output of the register at a predetermined time;

wherein the control circuit enables a modification of an output data stream generated at an output of the first plurality
of registers by providing the data value which is independent of the input data stream at the input of the register.

US Pat. No. 9,172,409

MULTI-PATH DIGITAL PRE-DISTORTION

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a single-band digital predistorter engine having a first sample path and a second sample path;
an input stage of the digital predistorter engine configured to receive input samples and configured to separate the input
samples into first samples and second samples;

the input stage further configured to provide first magnitudes for the first samples and second magnitudes for the second
samples;

a first set of digital predistorters of the digital predistorter engine configured to receive the first samples, the first
magnitudes and the second magnitudes;

a second set of digital predistorters of the digital predistorter engine configured to receive the second samples, the second
magnitudes and the first magnitudes; and

an output stage of the digital predistorter engine configured to receive predistorted outputs from the first set of digital
predistorters and the second set of digital predistorters and configured to provide a digital predistorted composite signal
of the predistorted outputs from the first set of digital predistorters and the second set of digital predistorters.

US Pat. No. 9,130,563

PROGRAMMABLE RECEIVERS AND METHODS OF IMPLEMENTING A PROGRAMMABLE RECEIVER IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A programmable receiver of an integrated circuit, the programmable receiver comprising:
an input;
a first programmable receiver circuit coupled to the input, wherein the first programmable receiver circuit has a first pull-up
branch and a first pull-down branch and is controlled by a first enable circuit;

a second programmable receiver circuit coupled to the input, wherein the second programmable receiver circuit has a second
pull-up branch and a second pull-down branch and is controlled by a second enable circuit; and

an output stage coupled to the first programmable receiver circuit and the second programmable receiver circuit, wherein the
output stage receives an output of one of the first programmable receiver circuit and the second programmable receiver circuit.

US Pat. No. 9,091,727

CONFIGURATION AND TESTING OF MULTIPLE-DIE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A method of operating a circuit, comprising:
inputting a configuration data sequence to a first programmable integrated circuit (IC);
determining by a configuration control circuit in the first programmable IC whether the first programmable IC is a master
programmable IC or a slave programmable IC based on a voltage status of a micro-bump of the first programmable IC; and

in response to the configuration control circuit in the first programmable IC determining the first programmable IC is a master
programmable IC and control bits in the configuration data sequence:

transmitting the configuration data sequence from the master programmable IC to one or more slave programmable ICs; and
configuring the master programmable IC and the one or more slave programmable ICs in parallel with configuration bits from
the configuration data sequence.

US Pat. No. 9,608,827

MEMORY CELL WITH DE-INITIALIZATION CIRCUITRY

XILINX, INC., San Jose, ...

1. A memory circuit, comprising:
a plurality of memory cells, each memory cell including:
a pair of cross-coupled inverters;
a first access transistor coupled to the pair of cross-coupled inverters; and
a second access transistor coupled to the pair of cross-coupled inverters;
a first bit line coupled to the first access transistor;
a second bit line coupled to the second access transistor;
a de-initialization circuit coupled to the first and second bit lines, wherein the de-initialization circuit is configured
and arranged to equalize signal states on the first and second bit lines in response to a first state of a de-initialization
signal; and

a control circuit coupled to the de-initialization circuit, wherein the control circuit is configured and arranged to:
enable power to the plurality of memory cells,
disable power to the plurality of memory cells after the enabling of power to the plurality of memory cells,
assert the de-initialization signal to the first state while power is disabled to the plurality of memory cells,
de-assert the de-initialization signal to a second state after the equalizing and while power is disabled to the plurality
of memory cells.

US Pat. No. 9,600,018

CLOCK STOPPAGE IN INTEGRATED CIRCUITS WITH MULTIPLE ASYNCHRONOUS CLOCK DOMAINS

XILINX, INC., San Jose, ...

1. A circuit, comprising:
a plurality of clock groups including a first clock group, the first clock group including:
a first clock domain;
a first clock multiplexer; and
a first synchronizer;
a plurality of programmable flip-flops; and
a controller, wherein the controller is configured to select at least one of the programmable flip-flops for choosing a sub-set
of the plurality of clock groups including at least the first clock group for which clocks are to be stopped first during
a clock stop process, and to generate an alternative clock signal and initiate the clock stop process of the circuit by sending
an alternative mode signal to the first synchronizer, wherein the first synchronizer is configured to synchronize the alternative
mode signal to a clock of the first clock domain, and wherein the first synchronizer is further configured to output, to a
select line of the first clock multiplexer, the alternative mode signal that is synchronized to the clock of the first clock
domain, wherein the select line of the first clock multiplexer is for selecting from between an input of the first clock multiplexer
for the clock of the first clock domain and an alternative mode clock input of the first clock multiplexer for the alternative
clock signal generated by the controller.

US Pat. No. 9,557,766

HIGH-SPEED SERIAL DATA INTERFACE FOR A PHYSICAL LAYER INTERFACE

XILINX, INC., San Jose, ...

7. A method for communicating data, comprising:
first updating of a first data eye adjustable delay for a first data stream provided to a first receive data path;
second updating of a second data eye adjustable delay for a second data stream provided to a second receive data path;
wherein the first updating and the second updating respectively adjust a first delay of the first data stream and a second
delay of the second data stream with respect to at least one clock signal;

using a first data output of the first receive data path as a live output; and
using a second data output of the second receive data path as a monitor output.

US Pat. No. 9,501,604

TESTING CRITICAL PATHS OF A CIRCUIT DESIGN

XILINX, INC., San Jose, ...

1. A method of testing a circuit design, comprising:
inputting the circuit design to a processor, wherein the circuit design includes a plurality of critical paths, and each critical
path includes a plurality of nets

generating by the processor, for each net of each critical path of the plurality of critical paths in the circuit design,
a respective ring oscillator circuit design having a source gate coupled to a destination gate via the net and a feedback
path that couples an output pin of the destination gate to an input pin of the source gate;

generating configuration data to implement a respective ring oscillator circuit from each ring oscillator circuit design;
configuring a programmable integrated circuit with the configuration data; and
determining a delay of the net of each ring oscillator circuit.

US Pat. No. 9,483,599

CIRCUIT DESIGN-SPECIFIC FAILURE IN TIME RATE FOR SINGLE EVENT UPSETS

XILINX, INC., San Jose, ...

1. A method, comprising:
determining, using a processor, a number of critical interconnect multiplexer bits for a circuit design for a target integrated
circuit;

determining a number of critical look-up table bits for the circuit design by calculating a number of look-up tables of the
target integrated circuit used by the circuit design and a number of inputs used for each look-up table of the target integrated
circuit used by the circuit design;

estimating, using the processor, a device vulnerability factor for the circuit design for the target integrated circuit using
the number of critical interconnect multiplexer bits and the number of critical look-up table bits;

wherein the device vulnerability factor indicates a failures in time for single event upsets in the target integrated circuit
implementing the circuit design and the target integrated circuit is a programmable integrated circuit; and

storing the estimated device vulnerability factor.

US Pat. No. 9,454,630

GRAPHICAL REPRESENTATION OF INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A system for graphics generation, comprising:
a processor configured to implement processes including:
a modeling process configured to:
generate a first graphics model including a plurality of objects, each object defining a respective graphical depiction for
a respective element of a programmable IC;

serialize objects of the first graphics model to produce a serialized graphics model by replacing instances of the objects
in the first graphics model with respective markers referencing the object in a first application programming interface (API)
definition file; and

provide the serialized graphics model to a graphical user interface (GUI) process by communicating an amount of data that
is less than an amount of data required to be communicated in order to provide the first graphics model to the second process;
and

the GUI process, the GUI process being configured to:
in response to receiving one or more objects of the serialized graphics model, deserialize the one or more objects of the
serialized graphics model according to the first API definition file to produce a second graphics model; and

render the one or more objects of the second graphics model.

US Pat. No. 9,431,812

DYNAMIC CAPACITORS FOR TUNING OF CIRCUITS

XILINX, INC., San Jose, ...

1. A circuit having a structure, comprising:
a signal line formed of at least one conductive element;
a shield at least partially encompassing the signal line, wherein the shield is positioned parallel to the signal line; and
a first dynamic capacitor configured to provide a first variable amount of capacitance, wherein the first dynamic capacitor
comprises:

a first conductive element located between the signal line and the shield;
wherein the first conductive element is positioned parallel to the signal line; and
a first switch configured to couple the first conductive element to a low impedance node in a first state or decouple the
first conductive element from the low impedance node and float the first conductive element in a second state responsive to
a control signal, wherein the first state and the second state of the first dynamic capacitor provide different amounts of
capacitance for the first variable amount of capacitance.

US Pat. No. 9,313,054

CIRCUITS FOR AND METHODS OF FILTERING INTER-SYMBOL INTERFERENCE FOR SERDES APPLICATIONS

XILINX, INC., San Jose, ...

1. A circuit for filtering inter-symbol interference in an integrated circuit, the circuit comprising:
a first stage coupled to receive digital samples of an input signal, wherein the first stage generates first decision outputs
based upon the digital samples of the input signal; and

a second stage coupled to receive the digital samples of the input signal;
wherein the second stage comprises a pre-filter coupled to an output of a delay element for receiving delayed digital samples,
and a filter receiving the first decision outputs and generating filtered decisions, the delay element aligning an output
of the pre-filter with the filtered decisions; and

wherein the second stage generates second decision outputs based upon the digital samples of the input signal that are filtered
before inter-symbol interference cancellation and detected inter-symbol interference associated with the first decision outputs.

US Pat. No. 9,214,433

CHARGE DAMAGE PROTECTION ON AN INTERPOSER FOR A STACKED DIE ASSEMBLY

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
an interposer having one or more conductive layers disposed on a top surface of an interposer substrate, the interposer substrate
having a plurality of conductors and a plurality of passive charge attracting structures;

wherein the plurality of passive charge attracting structures are configured to protect at least one integrated circuit die
to be coupled to the interposer to provide a stacked die;

wherein the plurality of conductors include a plurality of through-substrate vias formed through the interposer substrate
and coupled within the interposer substrate to the plurality of passive charge attracting structures through one or more conductive
layer;

a first well formed in the interposer substrate;
a first region formed in the first well;
a second region formed in the interposer substrate;
wherein a first portion of the second region extends into the first well and a second portion of the second region does not
extend into the first well;

a first contact formed for conducting charge therefrom to the first region;
a second contact formed for conducting charge therefrom to the second region;
wherein the second portion of the second region and the second contact in combination provide a first charge attracting structure
of the plurality of passive charge attracting substrates to attract first charged particles; and

wherein the first well, the first region, the first portion of the second region, and the first contact in combination provide
a second charge attracting structure of the plurality of passive charge attracting substrates to attract second charged particles.

US Pat. No. 9,203,440

MATRIX EXPANSION

XILINX, INC., San Jose, ...

1. A method, comprising:
Progressive Edge Growth (“PEG”) expanding an H matrix by a low density parity-check (“LDPC”) encoder (“a coder”) to provide
an expanded H matrix, wherein the coder includes a parity check matrix block for providing a parity check matrix, the coder
including an index filter, an accumulator, a repetition coder, and a permuter for providing bits for the parity check matrix;

Approximate Cycle Extrinsic Message Degree (“ACE”) expanding the expanded H matrix by the coder to provide the parity check
matrix for a code;

wherein the ACE expanding comprises:
initializing a first index to increment in a first range associated with a PEG expansion factor;
expanding each non-zero element in the expanded H matrix with a random shifted identity matrix for the first range;
initializing a second index to increment in a second range associated with the first index and an ACE expansion factor; and
performing an ACE detection for each variable node in the second range for the variable nodes of the parity check matrix;
and

outputting information by the coder using the parity check matrix.

US Pat. No. 9,183,337

CIRCUIT DESIGN WITH PREDEFINED CONFIGURATION OF PARAMETERIZED CORES

XILINX, INC., San Jose, ...

16. A computer system including a circuit design tool executing therein configured to process a circuit design, comprising:
a design entry module configured to:
identify selection of a parameterized core to be instantiated in a description of the circuit design managed by the circuit
design tool and configured for implementation in target hardware;

process a configuration file for the parameterized core to select a set of parameter values from a plurality of sets of parameter
values dynamically based at least in part on the target hardware; and

create an instance of the parameterized core in the circuit design having the selected set of parameter values; and
an implementation module configured to implement the circuit design for the target hardware.

US Pat. No. 9,130,566

PROGRAMMABLE IC WITH POWER FAULT TOLERANCE

XILINX, INC., San Jose, ...

1. A programmable integrated circuit (IC), comprising:
a programmable logic sub-system including a plurality of programmable logic circuits configured to form a set of circuits
indicated in a set of configuration data;

a processing sub-system configured to execute a software program; and
a safety sub-system configured and arranged to:
in response to a power failure of the processing sub-system and continued power to the programmable logic sub-system, suspend
configuration of the programmable logic sub-system by the processing sub-system; and

in response to a power failure of the programmable logic sub-system and continued power to the processing sub-system, reset
only the programmable logic sub-system.

US Pat. No. 9,123,738

TRANSMISSION LINE VIA STRUCTURE

XILINX, INC., San Jose, ...

1. A transmission line via structure in a substrate, comprising:
a plurality of sub-structures stacked in a via through the substrate along a longitudinal axis thereof, each of the sub-structures
including:

a center conductor portion extending along the longitudinal axis;
an outer conductor portion disposed around the center conductor portion; and
at least one dielectric support member supporting the center conductor portion, separating the outer conductor portion and
the center conductor portion and providing a non-solid volume between the outer conductor portion and the center conductor
portion, the at least one dielectric support member being disposed outside the non-solid volume; and

conductive paste disposed between the center and outer conductor portions of successive ones of the plurality of sub-structures
to form an outer conductor and a center conductor.

US Pat. No. 9,117,043

NET SENSITIVITY RANGES FOR DETECTION OF SIMULATION EVENTS

XILINX, INC., San Jose, ...

1. A method of hardware description language simulation for a circuit design, the method comprising:
generating, from the circuit design and using a processor, a simulation executable, wherein generating the simulation executable
comprises:

translating, using the processor, hardware description language code comprising a first net sensitivity range of a net that
partially overlaps a second net sensitivity range of the net into hardware description language code where the first net sensitivity
range is split into at least two net sensitivity ranges at a location determined from a starting index of the second net sensitivity
range and where the net sensitivity ranges resulting from the split do not partially overlap the second net sensitivity range;

wherein each net sensitivity range defines a subset of signals of the net that a process of the circuit design depends upon;
constructing, using the processor, a net sensitivity tree comprising hierarchically ordered nodes;
wherein each node specifies a net sensitivity range of the net subsequent to the translation;
generating, using the processor, a transaction function for the net of the circuit design as part of the simulation executable,
wherein the transaction function is configured to implement a search process defined by the net sensitivity tree; and

during execution of the simulation executable, scheduling execute functions of the simulation executable by determining whether
to resume execute functions comprising procedural logic of the circuit design that are dependent upon a changed value of at
least one signal of the net according to the search process by execution of the transaction function using the processor.

US Pat. No. 9,112,529

METHOD AND SYSTEM FOR FORWARD ERROR CORRECTION OF INTERLEAVED-FORMATED DATA

XILINX, INC., San Jose, ...

1. A device, comprising:
a first formatting circuit configured to add zero padding bits to a received data block;
a forward error correction (FEC) encoder circuit coupled to the first formatting circuit and configured to determine parity
bits for the data block at a first code rate; and

a second formatting circuit coupled to the FEC encoder circuit and configured to combine the parity bits with the data block
and remove the zero padding bits to provide an FEC coded data block at a second code rate, the second code rate being less
than the first code rate;

wherein the first formatting circuit includes:
a row de-interleaver circuit configured to format the received data block into a row-aligned format, wherein each row of the
data block in the row-aligned format includes data bits equal to data bits in a corresponding row in a de-interleaved format;
and

a column de-interleaver circuit configured to format the received data block into a column-aligned format, wherein each row
of the data block in the column-aligned format includes data bits equal to data bits in a corresponding column in the de-interleaved
format;

the FEC encoder circuit includes:
a row encoding circuit coupled to the first formatting circuit and configured to perform FEC coding on the rows of the data
block in the row-aligned format to produce a row-coded data block; and

a column encoding circuit coupled to the second formatting circuit and configured to perform FEC coding on rows of the data
block in the column-aligned format, the rows corresponding to respective columns of the data block in the de-interleaved format,
to produce a column-coded data block; and

the second formatting circuit is configured to combine the row-coded data block and the column-coded data block to produce
an FEC coded data block and remove the zero padding bits.

US Pat. No. 9,496,871

PROGRAMMABLE POWER REDUCTION TECHNIQUE USING TRANSISTOR THRESHOLD DROPS

XILINX, INC., San Jose, ...

1. An integrated circuit, comprising:
a voltage rail;
voltage control circuitry coupled to the voltage rail; and
a circuit block coupled to the voltage control circuitry;
wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of
operation or a second mode of operation;

wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of
the voltage rail, and operates at a first speed;

wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage
rail by a threshold voltage, and operates at a second speed that is slower than the first speed; and

wherein the circuit block is configured to operate in the first mode of operation or the second mode of operation based at
least in part on whether the circuit block is on a path having a slack that is less than a predetermined threshold, the slack
being a measure of a margin by which the path meets a timing requirement of the integrated circuit.

US Pat. No. 9,453,870

TESTING FOR SHORTS BETWEEN INTERNAL NODES OF A POWER DISTRIBUTION GRID

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
an integrated circuit die having a regulated power supply, a power supply grid, and a test circuit;
wherein the regulated power supply is biased between a source supply node and a source ground node;
wherein the source supply node and the source ground node are externally accessible nodes of the integrated circuit die;
wherein an internal supply node of the power supply grid is coupled to an output side of the regulated power supply, the internal
supply node being inaccessible to direct probe pin contact;

wherein the test circuit is coupled to the internal supply node of the power supply grid;
wherein the test circuit is configured to test for at least one short in the power supply grid, the at least one short including
at an end thereof an inaccessible node to direct probe pin contact;

wherein the test circuit is configured to limit power through the power supply grid to less than that of a probe tip tolerance;
and

wherein the test circuit is configured to test for the at least one short with background current leakage of the power supply
grid being present.

US Pat. No. 9,218,443

HETEROGENEOUS MULTIPROCESSOR PROGRAM COMPILATION TARGETING PROGRAMMABLE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A method, comprising:
generating, using a processor, a register transfer level description of a first kernel of a heterogeneous, multiprocessor
design;

integrating the register transfer level description of the first kernel with a base platform circuit design providing a static
region within a programmable integrated circuit that provides an interface to a host of the heterogeneous, multiprocessor
design;

generating, from the register transfer level description of the first kernel and using the processor, a first configuration
bitstream specifying a hardware implementation of the first kernel and supporting data for the configuration bitstream; and

including the first configuration bitstream and the supporting data within a binary container.

US Pat. No. 9,135,384

COMPILATION AND SIMULATION OF A CIRCUIT DESIGN

XILINX, INC., San Jose, ...

1. A method for compiling a hardware description language (HDL) specification for simulation of a circuit design, the method
comprising using one or more processors to perform operations including:
elaborating the circuit design from the HDL specification, the circuit design including instances of a plurality of modules;
and

generating and storing on a storage device, simulation code that models the circuit design, the simulation code including:
for each hardware configuration of each of the plurality of modules, a respective first function configured and arranged to
model the hardware configuration of the module using a set of nets indicated in one or more arguments of the function; and

a second function configured and arranged to simulate first and second ones of the instances that have a same hardware configuration
of a same one of the plurality of modules, by performing operations including:

in response to an indication to simulate the first instance, executing a function call to the respective first function, corresponding
to the hardware configuration and module of the first and second instances, with a first set of nets corresponding to the
first instance indicated by one or more arguments in the function call; and

in response to an indication to simulate the second instance, reexecuting the function call to the respective first function,
with a second set of nets corresponding to the second instance indicated by the one or more arguments in the function call.

US Pat. No. 9,054,928

CREST FACTOR REDUCTION

XILINX, INC., San Jose, ...

11. A method for crest factor reduction (CFR), comprising:
receiving input signal (xk) by a peak detector;

generating, using a running maximum filter, a scaling factor based on a window gain (Gk) and a filter length, wherein the window gain (Gk) is based on the input signal (xk) and a threshold value (T);

generating, using a window CFR gain filter, a gain correction (Fk) based on the scaling factor and the filter length;

delaying, by a delay, the input signal (xk) to obtain a delayed input signal;

multiplying, using a multiplier, the gain correction (Fk) by the delayed input signal to obtain a peak correction value; and

adding the peak correction value to the delayed input signal to obtain an output signal (yk);

wherein the peak detector, the running maximum filter, the window CFR gain filter, the delay, the multiplier, or any combination
of the foregoing, is implemented in at least one integrated circuit.

US Pat. No. 9,054,684

SINGLE EVENT UPSET ENHANCED ARCHITECTURE

XILINX, INC., San Jose, ...

1. A circuit block within an integrated circuit, the circuit block comprising:
a multiplexor configured to pass either a first signal or a second signal;
wherein the first signal is independent of the second signal;
a first flip-flop configured to receive an output of the multiplexor;
wherein the first flip-flop has a first output and a second output;
a second flip-flop comprising a first input configured to receive the second signal and a single event upset input coupled
to a C-element block within the second flip-flop;

wherein in a first mode of operation:
the multiplexor passes the first signal to the first flip-flop; and
the first flip flop and the second flip-flop operate independently of one another with the second output of the first flip-flop
gated so as to not transition; and

wherein in a second mode of operation:
the multiplexor passes the second signal to the first flip-flop;
the first flip-flop and the second flip-flop both receive the second signal; and
a first result signal generated by the second output of the first flip-flop is provided to the single event upset input of
the second flip-flop bypassing a D-type element of the second flip-flop through which the second signal provided to the first
input of the second flip-flop is processed.

US Pat. No. 9,865,567

HETEROGENEOUS INTEGRATION OF INTEGRATED CIRCUIT DEVICE AND COMPANION DEVICE

XILINX, INC., San Jose, ...

1. A method of manufacturing a semiconductor assembly, comprising:
forming first integrated circuit (IC) dies and dummy dies;
forming an interposer wafer including a top side having first mounting sites for the first IC dies and second mounting sites
for second IC dies;

attaching the first IC dies to the interposer wafer at the first mounting sites and the dummy dies to the interposer wafer
at the second mounting sites;

processing a backside and the top side of the interposer wafer;
removing the dummy dies from the top side of the interposer wafer to expose the second mounting sites; and
attaching the second IC dies to the interposer wafer at the exposed second mounting sites.

US Pat. No. 9,811,618

SIMULATION OF SYSTEM DESIGNS

XILINX, INC., San Jose, ...

1. A method for simulating operation of a system design including a program executable by a processor on a programmable IC
and a circuit implemented by programmable resources on the programmable IC, the circuit being configured to communicate with
the program executing on the processor via an interface circuit that uses a first communication protocol, the method comprising:
configuring a processor on the programmable IC to execute the program;
configuring programmable resources on the programmable IC with a configuration data stream;
wherein the configuration data stream is configured to implement a plurality of alternative interface circuits together using
the programmable resources;

wherein each of the plurality of alternative interface circuits is configured to use a respective communication protocol to
communicate data between the processor and a simulation environment over a set of communication channels, and the plurality
of alternative interface circuits includes an interface circuit that uses the first communication protocol;

determining and selecting by the simulation environment, one of the plurality of alternative interface circuits that is configured
to use the first communication protocol based on metadata included with the plurality of alternative interface circuits and
the system design;

enabling the determined one of the plurality of alternative interface circuits and disabling other ones of the plurality of
alternative interface circuits after configuring the programmable IC with the configuration data stream;

simulating the circuit of the system design using the simulation environment on a computing platform coupled to the programmable
IC; and

during the simulating, executing the program on the processor and communicating data between the processor and the computing
platform via the determined one of the plurality of alternative interface circuits.

US Pat. No. 9,330,749

DYNAMIC SELECTION OF OUTPUT DELAY IN A MEMORY CONTROL DEVICE

XILINX, INC., San Jose, ...

1. A memory control device, comprising:
an output circuit coupled to provide an output signal comprising a data signal or data strobe signal for a synchronous dynamic
random access memory (SDRAM) system having a plurality of ranks;

an output delay unit coupled to apply an output delay to a bitstream to be transmitted to generate the output signal, the
output delay comprising an aggregate of a de-skew delay and a write-levelization delay; and

a write-levelization delay controller coupled to adjust the write-levelization delay for each write transaction to the SDRAM
system of a plurality of write transactions based on a selected rank of the plurality of ranks;

wherein the de-skew delay is the same across the plurality of ranks for each of the plurality of write transactions.

US Pat. No. 9,304,174

CROSS-COUPLED VOLTAGE AND TEMPERATURE MONITORING IN PROGRAMMABLE INTEGRATED CIRCUITS

XILINX, INC., San Jose, ...

1. A method for monitoring a first power supply voltage providing power to a first processing domain and a second power supply
voltage providing power to a second processing domain, the first processing domain including user-configurable electronic
logic, the second processing domain including hard-wired electronic logic, the method comprising:
receiving, at a processing domain, the first power supply voltage;
comparing, at the processing domain, the first power supply voltage to a first reference voltage;
receiving, at the processing domain, the second power supply voltage;
comparing, at the processing domain, the second power supply voltage to a second reference voltage;
determining that the first power supply voltage exceeds the first reference voltage or that the second power supply voltage
exceeds the second reference voltage; and

transmitting one or more alarms corresponding to one or more of the first power supply voltage and the second power supply
voltage in response to determining that the first power supply voltage exceeds the first reference voltage or that the second
power supply voltage exceeds the second reference voltage,

wherein the processing domain comprises either the first processing domain or the second processing domain.

US Pat. No. 9,270,247

HIGH QUALITY FACTOR INDUCTIVE AND CAPACITIVE CIRCUIT STRUCTURE

XILINX, INC., San Jose, ...

10. A circuit, comprising:
a first plurality of finger capacitors implemented in a first plane;
wherein each finger capacitor of the first plurality of finger capacitors comprises a first bus line coupled to a first plurality
of finger elements and a second bus line parallel to the first bus line and coupled to a second plurality of finger elements;

a second plurality of finger capacitors implemented in the first plane;
wherein each finger capacitor of the second plurality of finger capacitors comprises a third bus line coupled to a third plurality
of finger elements and a fourth bus line parallel to the third bus line and coupled to a fourth plurality of finger elements;

wherein the third bus line is parallel to the first bus line;
an inductor comprising a first leg oriented perpendicular to the first bus line and a second leg parallel to the first leg;
wherein the first leg of the inductor is coupled to a center of each first bus line of the first plurality of finger capacitors;
wherein the second leg of the inductor is coupled to a center of each third bus line of the second plurality of finger capacitors;
wherein the first leg and the second leg are implemented within a conductive layer above the first and second plurality of
finger capacitors; and

wherein the first leg bisects each of the finger capacitors of the first plurality of finger capacitors and the second leg
bisects each of the finger capacitors of the second plurality of finger capacitors.

US Pat. No. 9,268,901

EMULATING POWER GATING FOR A CIRCUIT DESIGN USING A PROGRAMMABLE INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. An integrated circuit, comprising:
a first power region;
a second power region;
a power gate emulation circuit coupled to an output signal of the first power region, an isolation signal for the second power
region, and a power gate signal for the first power region; and

an isolation circuit comprising a first input coupled to an output of the power gate emulation circuit, a second input coupled
to the isolation signal, and an output coupled to an input of the second power region;

wherein the power gate emulation circuit is configured to pass the output signal of the first power region, or an inverted
version of the output signal of the first power region, according to a state of the power gate signal and a state of the isolation
signal.

US Pat. No. 9,160,594

PEAK DETECTION IN SIGNAL PROCESSING

XILINX, INC., San Jose, ...

1. An apparatus for peak detection, comprising:
a peak identification unit configured to determine an identifier of a peak location;
an interpolator configured to interpolate an input signal to provide at least one interpolated signal;
a magnitude squared unit configured to provide at least one magnitude squared signal, wherein the magnitude squared unit is
configured to provide the at least one magnitude squared signal based on the at least one interpolated signal;

a first delay configured to delay the at least one magnitude squared signal to provide at least one delayed magnitude squared
signal, wherein the peak identification unit is configured to determine the identifier of the peak location based on the at
least one delayed magnitude squared signal;

a first multiplexer configured to receive the at least one delayed magnitude squared signal to produce first multiple output
signals;

a first differential filter configured to provide coefficients for a first polynomial, wherein the first differential filter
is configured to provide the coefficients for the first polynomial based on the first multiple output signals from the first
multiplexer;

a fractional locator configured to determine a fractional location of a peak in a time domain based on the coefficients for
the first polynomial and the identifier of the peak location; and

a first fractional interpolator to determine a first peak amplitude based on the fractional location of the peak and the coefficients
for the first polynomial,
wherein the peak identification unit, the first differential filter, the fractional locator, the first fractional interpolator,
and any combination thereof, is implemented in at least one integrated circuit.

US Pat. No. 9,118,310

PROGRAMMABLE DELAY CIRCUIT BLOCK

XILINX, INC., San Jose, ...

1. A programmable delay circuit block, comprising:
an input stage comprising a cascade input and a clock input;
wherein the input stage passes a signal received at the cascade input or a signal received at the clock input;
a delay block configured to generate a delayed signal by applying a selected amount of delay to the signal passed from the
input stage;

a pulse generator configured to generate a pulse signal having a pulse width that depends upon the amount of delay; and
an output stage comprising a cascade output and a clock output;
wherein the output stage is configured to pass an inverted version of the pulse signal or the delayed signal from the cascade
output and pass the signal received at the clock input, the inverted version of the pulse signal, or the delayed signal from
the clock output.

US Pat. No. 9,075,624

COMPILATION OF SYSTEM DESIGNS

XILINX, INC., San Jose, ...

1. A method for compiling a high-level language (HLL) program, comprising:
performing on a programmed processor operations including:
inputting a command having a first field that indicates a set of one or more HLL source files to be compiled and a second
field that indicates a set of one or more functions that are to be implemented on programmable circuitry of a programmable
integrated circuit (IC);

for each HLL source file of the set:
in response to the HLL source file including one or more functions of the set:
for each of the one of more functions of the set:
 generating a respective netlist from HLL code included in the function;
 generating interface code for communication with the netlist;
 wherein the generating of the interface code for communication with the netlist includes:
 generating code configured and arranged to communicate input arguments of the HLL source file to the netlist:
 generating code that triggers execution of the netlist;
 generating code that causes execution of the HLL code to halt; and
 generating code configured and arranged to receive result data from the netlist; and
 replacing HLL code of the function in the HLL source file with the generated interface code;
compiling the HLL source file to produce a respective object file; and
appending the netlist generated for one of the one or more functions of the set to the object file compiled from the HLL source
file that includes the one of the one or more functions of the set;

linking each of the object files to generate a program executable on a processor of the programmable IC; and
generating a configuration data stream that implements each generated netlist on the programmable circuitry of the programmable
IC.

US Pat. No. 9,047,474

CIRCUITS FOR AND METHODS OF PROVIDING ISOLATION IN AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A circuit for providing isolation in an integrated circuit, the circuit comprising:
a first circuit block having circuits associated with a first security level;
a second circuit block having circuits associated with a second security level; and
a third circuit block having programmable resources, the third circuit block providing isolation between the first circuit
block and the second circuit block and being programmable to enable connections between the first circuit block and the second
circuit block.

US Pat. No. 9,652,410

AUTOMATED MODIFICATION OF CONFIGURATION SETTINGS OF AN INTEGRATED CIRCUIT

XILINX, INC., San Jose, ...

1. A method, comprising:
receiving, within a data processing system, desired data for a configuration setting of an IC, wherein the IC is a system-on-chip;
reading, using the data processing system, stored data for the configuration setting;
comparing, using the data processing system, the stored data with the desired data;
determining, using the data processing system, whether updating the configuration setting within the IC requires implementation
of at least a portion of a boot process of the IC;

determining a selected stage from a plurality of ordered stages of the boot process of the IC where modification of the configuration
setting is permitted, wherein the selected stage is subsequent to a first stage; and

responsive to the determining that updating the configuration setting within the IC requires implementing at least the portion
of the boot process and that the stored data differs from the desired data by the comparing, providing configuration data
to the IC, wherein the configuration data comprises the desired data from the data processing system and an instruction to
implement the boot process of the IC from the selected stage, wherein the IC automatically initiates the boot process from
the selected stage of the boot process using the configuration data.

US Pat. No. 9,509,307

INTERCONNECT MULTIPLEXERS AND METHODS OF REDUCING CONTENTION CURRENTS IN AN INTERCONNECT MULTIPLEXER

XILINX, INC., San Jose, ...

1. An interconnect multiplexer, comprising:
a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer;
an output inverter having an input coupled to outputs of the plurality of CMOS pass gates, wherein an output of the output
inverter is an output of the interconnect multiplexer; and

a plurality of memory elements coupled to the plurality of CMOS pass gates;
wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode; and
wherein address lines of the plurality of memory elements are pulled to a first predetermined potential and data lines of
the plurality of memory elements are pulled to a second predetermined potential using global signals during a power-up sequence.

US Pat. No. 9,313,017

BAUD-RATE CDR CIRCUIT AND METHOD FOR LOW POWER APPLICATIONS

XILINX, INC., San Jose, ...

1. A clock data recovery (CDR) circuit for a receiver, comprising:
a timing error detector circuit coupled to receive, at a baud-rate, data samples and error samples for symbols received by
the receiver, the timing error detector circuit operable to generate both a timing error value and an estimated waveform value
per symbol based on the data samples and the error samples;

a loop filter coupled to the timing error detector to receive timing error values; and
a phase interpolator coupled to the loop filter to receive filtered timing error values, the phase interpolator operable to
generate a control signal to adjust a sampling phase used to generate the data samples and the error samples.

US Pat. No. 9,276,576

CIRCUITS FOR AND METHODS OF PROVIDING VOLTAGE LEVEL SHIFTING IN AN INTEGRATED CIRCUIT DEVICE

XILINX, INC., San Jose, ...

1. A circuit for providing voltage level shifting, the circuit comprising:
an inverter having an input coupled to receive an input signal having a first voltage level;
an output stage having a first transistor coupled in series with a second transistor, and an output node between the first
transistor and the second transistor generating an output signal having a second voltage level;

wherein a gate of the second transistor is coupled to an output of the inverter;
a pull-up transistor coupled between a reference voltage having the second voltage level and a gate of the first transistor;
and

a switch coupled between the gate of the first transistor and the gate of the second transistor to control a voltage at the
gate of the first transistor, wherein:

the first transistor comprises a first p-channel transistor;
the second transistor comprises a first n-channel transistor; and
the switch comprises a second p-channel transistor coupled in parallel with a second n-channel transistor.

US Pat. No. 9,244,885

PIPELINED PHASE ACCUMULATOR

XILINX, INC., San Jose, ...

20. An apparatus, comprising:
a first accumulation circuit coupled to receive an offset operand and a carry value fed back to provide a first sum result;
a second accumulation circuit coupled to the first accumulation circuit to receive the first sum result;
wherein the second accumulation circuit is configured to select between the first sum result and the carry value fed back
responsive to the carry value to provide a first input to an adder;

wherein the second accumulation circuit is coupled to receive an input operand as a second input to the adder to provide a
second sum result;

wherein the second accumulation circuit includes a register circuit to register the second sum result to provide an offset-accumulated
result;

a subtraction-bypass-register circuit coupled to receive the offset operand and a modulus operand to provide a registered
difference and a registered offset operand; and

a consolidation circuit coupled to receive the registered offset operand, the registered difference and the offset-accumulated
result to provide a consolidated accumulated result.

US Pat. No. 9,245,865

INTEGRATED CIRCUIT PACKAGE WITH MULTI-TRENCH STRUCTURE ON FLIPPED SUBSTRATE CONTACTING UNDERFILL

XILINX, INC., San Jose, ...

1. An integrated circuit (IC) package, comprising:
a package substrate;
an IC die having a front surface and a back surface, the front surface facing the package substrate and including a conductive
interface;

solder bumps coupling the conductive interface to the package substrate;
a first plurality of trenches including at least one trench proximate each corner of the IC die, the first plurality of trenches
formed in the front surface of the IC die in an area between the conductive interface and a perimeter of the IC die; and

underfill material disposed between the front surface of the IC die and the package substrate, the underfill material in contact
with the first plurality of trenches.

US Pat. No. 9,236,367

METHOD AND APPARATUS FOR TRACKING INTERPOSER DIES IN A SILICON STACKED INTERCONNECT TECHNOLOGY (SSIT) PRODUCT

XILINX, INC., San Jose, ...

1. An apparatus for a stacked silicon interconnect technology (SSIT) product, comprising:
an interposer die;
a plurality of integrated circuit dies;
a plurality of active components forming an active connection between the integrated circuit dies and the interposer die;
a plurality of dummy components at the interposer die, the dummy components not forming an active connection between the integrated
circuit dies and the interposer die;

wherein at least a subset of the dummy components forms a pattern; and
wherein the pattern comprises an identifier for the interposer die.

US Pat. No. 9,118,447

SAMPLING POSITION TUNING

XILINX, INC., San Jose, ...

1. An apparatus, comprising:
a phase interpolator;
a detector;
a slicer coupled to the phase interpolator for providing a sampling signal for a sampling position of the phase interpolator;
the detector being coupled to the slicer for receiving the sampling signal;
the detector for adjusting a code of the phase interpolator to adjust the sampling position in response to the sampling signal;
the detector including a running average module for receiving the sampling signal for providing a running average signal;
the detector including a controller for receiving the running average signal for providing a set signal to the phase interpolator;
and

the controller for adjusting the code of the phase interpolator for adjusting the sampling position responsive to the sampling
signal for tuning the sampling position.

US Pat. No. 9,330,823

INTEGRATED CIRCUIT STRUCTURE WITH INDUCTOR IN SILICON INTERPOSER

XILINX, INC., San Jose, ...

1. An integrated circuit structure, comprising:
an interposer comprising a plurality of conductive layers, a first interconnect region that includes one or more of the plurality
of conductive layers, a second interconnect region that includes one or more of the plurality of conductive layers, wherein
the first interconnect region is separated from and coupled to the second interconnect region by a plurality of through silicon
vias;

a first die coupled to the second interconnect region of the interposer through an internal interconnect structure; and
an inductor implemented within at least one of the conductive layers of the first interconnect region of the interposer and
fully enclosed within the interposer;

wherein the inductor comprises a first terminal and a second terminal;
wherein the first terminal is coupled to the first die via the internal interconnect structure and the second terminal is
coupled to the first die via the internal interconnect structure; and

wherein the interposer has a substrate resistivity that is higher than a substrate resistivity of the first die.