US Pat. No. 9,888,587

CURVATURE REMOTELY ADJUSTABLE CURVED-SURFACE DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A curvature remotely adjustable curved-surface display device, comprising:
a display panel having a plurality of pixels used to display an image;
an active rod, one end thereof being pivotally connected to a first side of the display panel and the other end thereof having
a gear disposed;

a first slave rod, one end thereof being pivotally connected to a second side opposite to the first side of the display panel
and the other end thereof having a rack bar disposed, the gear at the other end of the active rod being engaged with the rack
bar at the other end of the first slave rod;

a second slave rod, one end thereof being pivotally connected between the first side and the second side of the display panel
and the other end thereof being pivotally connected to the first slave rod; and

a remotely controllable motor connecting or coupling to the gear disposed on the active rod, wherein the remotely controllable
motor receives a remote control signal transmitted from a remote terminal and supplies power to the gear of the active rod
based on the remote control signal so as to make the gear rotate, thereby making the first slave rod move toward or away from
the active rod as a result of the engaging movement between the gear and the rack bar.

US Pat. No. 10,045,445

FLEXIBLE DISPLAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method for flexible display substrate, which comprises:Step 1: providing a carrier substrate, and forming a first organic layer on the carrier substrate;
Step 2: forming a patterned first inorganic separation layer on the first organic layer, the first inorganic separation layer comprising a plurality of inorganic separation units arranged with gaps in-between the units;
Step 3: forming a second organic layer on the first organic layer and the first inorganic separation layer, the second organic layer contacting the first organic layer at the gaps between the plurality of inorganic separation units;
Step 4: forming a second inorganic separation layer on the second organic layer to obtain a flexible substrate comprising the first organic layer, the first inorganic separation layer, the second organic layer and the second inorganic separation layer;
Step 5: forming a display component on the flexible substrate, and
Step 6: peeling the flexible substrate off the carrier substrate.

US Pat. No. 9,933,889

GOA DRIVING CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A GOA driving circuit, comprising GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage comprises: a forward-backward scan control module, a basic output module, a basic output pull-down module, a first node control module, a second node control module, an output control module, a reset module, a voltage stabilizing module and a second node charging module;n is set to be a positive integer, and except the GOA unit of the first stage, the GOA unit of the second stage, the GOA unit of the next to last stage and the GOA unit of the last stage, in the GOA unit of the nth stage:
the forward-backward scan control module comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is coupled to an output end of the two former n?2th stage GOA unit, and a source receives a forward scan control signal, and a drain is electrically coupled to a first node; and a tenth thin film transistor, and a gate of the tenth thin film transistor is coupled to an output end of the two latter stage n+2th GOA unit, and a source receives a backward scan control signal, and a drain is electrically coupled to the first node;
the basic output module comprises: a seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to a drain of a sixth thin film transistor, and a source receives a Mth clock signal, and a drain is electrically coupled to an output end; and a first capacitor, and one end of the first capacitor is electrically coupled to the drain of the sixth thin film transistor, and the other end is electrically coupled to the output end;
the basic output pull-down module comprises: an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to a second node, and a source receives a composite signal, and a drain is electrically coupled to the output end; and a second capacitor, and one end of the second capacitor is electrically coupled to the second node, and the other end receives the composite signal;
the first node control module comprises: a fourth thin film transistor, and a gate of the fourth thin film transistor receives the Mth clock signal, and a source is electrically coupled to the a drain of a fifth thin film transistor, and a drain is electrically coupled to the first node; and the fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the second node, and a source receives the composite signal;
the second node control module comprises: an eleventh thin film transistor, and a gate of the eleventh thin film transistor receives a first global control signal, and a source receives the composite signal, and a drain is electrically coupled to the second node;
the output control module comprises: a twelfth thin film transistor, and both a gate and a source of the twelfth thin film transistor receive the first global control signal, and a drain is electrically coupled to the output end; and a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor receives a second global control signal, and a source receives the composite signal, and a drain is electrically coupled to the output end;
the reset module comprises: a first thin film transistor, and both a gate and a source of the first thin film transistor receives a reset signal, and a drain is electrically coupled to the second node;
the voltage stabilizing module comprises: the sixth thin film transistor, and a gate of the sixth thin film transistor receives a control voltage level, and a source is electrically coupled to the first node, and a drain is electrically coupled to the gate of the seventh thin film transistor;
the second node charging module comprises: a third thin film transistor, and a gate of the third thin film transistor receives a M?2th clock signal, and a source receives the control voltage level, and a drain is electrically coupled to the second node; and a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the first node, and a source receives the M?2th clock signal, and a drain is electrically coupled to the second node;
a working procedure of the GOA driving circuit comprises: a screen awakening stage, a reset stage, a normal display stage and a touch scan stage in order;
in the screen awakening stage, the first global control signal controls the twelfth thin film transistors and the eleventh thin film transistors of the GOA units of all stages to be activated, and the second global control signal controls the thirteenth thin film transistors of the GOA units of all stages to be deactivated; in the reset stage and the normal display stage, the first global control signal controls the twelfth thin film transistors and the eleventh thin film transistors of the GOA units of all stages to be deactivated, and the second global control signal controls the thirteenth thin film transistors of the GOA units of all stages to be deactivated; in the touch scan stage, the second global control signal controls the thirteenth thin film transistors of the GOA units of all stages to be activated, and the first global control signal controls the twelfth thin film transistors and the eleventh thin film transistors of the GOA units of all stages to be deactivated;
in the reset stage, the reset signal provides a single pulse to control the first thin film transistor to be activated to reset a voltage level of the second node, and a duration of the single pulse of the reset signal is at least a sum of durations of initial pulses of a first clock signal and a second clock signal;
in the reset stage and the normal display stage, voltage levels of the composite signal and the control voltage level are one high and one low, and voltage levels of the forward scan control signal and the backward scan control signal are one high and one low; in the touch scan stage, the composite signal is a pulse signal having the same frequency with a touch scan signal.

US Pat. No. 9,858,876

DRIVING CIRCUIT AND SHIFT REGISTER CIRCUIT

Shenzhen China Star Optoe...

1. A driving circuit, comprising a plurality of shift register circuits disposed in cascade, each of the plurality of shift
register circuits comprising a clock control transmittance circuit and a latch circuit, the clock control transmittance circuit
being triggered by a first clock pulse, a driving pulse of a Q node at previous two stages being transmitted to the latch
circuit and latched by the latch circuit, further, the latch circuit being triggered by a second clock pulse, and then a gate
driving pulse and a driving pulse of the Q node being output, and the clock control transmittance circuit and the latch circuit
being rising edge-triggered;
wherein the latch circuit at least comprises a first transmission gate, a second transmission gate, a first inverter, a second
inverter, and an NOR gate; a first controlling terminal of the first transmission gate and a second controlling terminal of
the second transmission gate are connected to an output terminal of the clock control transmittance circuit; an input terminal
of the first transmission gate is connected to a Q node at the previous two stages, a second controlling terminal of the first
transmission gate and a first controlling terminal of the second transmission gate both are connected to the first clock pulse;
an output terminal of the first transmission gate is connected to an input terminal of the second transmission gate and an
input terminal of the first inverter; an output terminal of the first inverter is connected to an input terminal of the second
inverter; an output terminal of the second inverter and an output terminal of the second transmission gate both are connected
to a first input terminal of the NOR gate; and a second input terminal of the NOR gate is connected to the second clock pulse.

US Pat. No. 9,857,647

DISPLAY PANEL AND DISPLAY DEVICE THEREOF

Shenzhen China Star Optoe...

1. A display panel, wherein, the display panel is an OLED display panel and the display panel comprises a thin film transistor
(TFT) substrate, a color filter substrate and a conductive polarizer; the conductive polarizer and the TFT substrate together
form a space for electrostatic shielding, and the color filter substrate is located in the space; the conductive polarizer
is a flexible stacked structure comprising a polarizer base and a conductive layer disposed on the polarizer base, the conductive
polarizer covers a light radiation surface of the color filter substrate, a side surface of the color filter substrate perpendicular
to the light radiation surface and a side surface of the TFT substrate and thereby the side surface of the color filter substrate
and the side surface of the TFT substrate are covered by the conductive layer as well as the polarizer base.

US Pat. No. 9,508,745

ARRAY SUBSTRATE AND METHOD OF FABRICATING THE SAME

WUHAN CHINA STAR OPTOELEC...

1. A method of fabricating an array substrate, comprising the following steps of:
providing a transparent substrate having a first portion and a second portion neighboring each other, and a first surface
and a second surface facing each other;

forming a buffer layer on the first surface of the transparent substrate, wherein the buffer layer is located on the first
portion and the second portion;

forming a first gate pattern and a second gate pattern on the buffer layer, wherein the first gate pattern and the second
gate pattern are formed respectively on the first portion and the second portion;

providing a transparent insulating layer covering the first gate pattern, the second gate pattern and the buffer layer;
forming a first polysilicon pattern and a second polysilicon pattern on the transparent insulating layer, wherein the first
polysilicon pattern has a first region and a second region adjacent to the first region, and the second polysilicon pattern
has a third region and a fourth region adjacent to the third region;

providing a photoresist layer covering the first polysilicon pattern, the second polysilicon pattern and the transparent insulating
layer;

providing an exposure light source in a direction from the second surface toward the first surface of the transparent substrate
by using the first gate pattern and the second gate pattern as a light shielding layer, such that the photoresist layer forms
a first photoresist pattern on the first region of the first polysilicon pattern and a second photoresist pattern on the third
region of the second polysilicon pattern; and

performing a first doping step to the first polysilicon pattern and the second polysilicon pattern in a direction from the
first surface toward the second surface of the transparent substrate, such that the second region forms a first lightly doped
polysilicon region and the fourth region forms a second lightly doped polysilicon region.

US Pat. No. 9,810,960

LIQUID CRYSTAL DISPLAY PANEL AND ARRAY SUBSTRATE THEREOF

Shenzhen China Star Optoe...

1. An array substrate comprising:
a first glass substrate;
a first metallic layer, disposed on the first glass substrate, for forming a scan line and a gate of a thin film field effect
transistor;

a first insulating layer, disposed on the first metallic layer;
a semiconductor layer, disposed on the first insulating layer, for forming a channel of the thin film field effect transistor;
a second metallic layer, disposed on the semiconductor layer, for forming a source and a drain of the thin film field effect
transistor and forming a data line;

a color resist layer, disposed on the second metallic layer and the first insulting layer, for forming a color filter;
a pixel electrode layer, disposed on the color resist layer and connected to the drain of the thin film field effect transistor
through a via hole penetrating the color resist layer, for forming a pixel electrode;

a passivation layer, disposed on the pixel electrode layer;
a black matrix layer, disposed on the passivation layer, for forming a black matrix;
a common electrode, disposed on the passivation layer and the black matrix layer, for forming a common electrode; and
a spacer, disposed on the common electrode layer above the black matrix, for retaining a cell gap;
wherein the via hole is defined between two adjacent color resists of the color resist layer, and the black matrix is disposed
corresponding to the color filter and the pixel electrode so that the black matrix is exactly disposed above the via hole.

US Pat. No. 9,865,213

SCAN DRIVER CIRCUIT FOR DRIVING SCANNING LINES OF LIQUID CRYSTAL DISPLAY

WUHAN CHINA STAR OPTOELEC...

12. A scan driver circuit, for driving scanning lines, comprising:
a pull-down control module, for receiving a previous stage scanning signal or a next stage scanning signal and generating
a low-voltage-level scanning level signal at the corresponding scanning line according to the previous stage scanning signal
or the next stage scanning signal;

a pull-down module, for lowering a scanning signal at the corresponding scanning line according to the scanning level signal;
a recovering control module, for receiving a previous stage clock signal or a next stage clock signal and generating a recovering
signal at the corresponding scanning line according to the previous stage clock signal or the next stage clock signal;

a recovering module, for elevating a scanning signal at the corresponding scanning line according to the recovering signal;
a downlink module, for generating and sending a current stage clock signal and a pull-down control signal according to the
scanning signal at the scanning line;

a first bootstrap capacitor, for generating a scanning level signal with a low level voltage or a high level voltage at the
scanning line;

a constant low voltage supply, for supplying the low-voltage-level signal; and
a constant high voltage supply, for supplying the high-voltage-level signal.

US Pat. No. 10,025,438

DEVICE AND METHOD FOR DETECTING DEFECTS IN SELF-CAPACITIVE TOUCH PANEL

SHENZHEN CHINA STAR OPTOE...

1. A device for detecting defects in a self-capacitive touch panel, which is provided with a plurality of drive circuits respectively connected to a plurality of rows of touch electrodes, the drive circuit comprising:a pre-charging unit, for generating a charge control signal for simultaneously presetting a first voltage for the touch electrodes;
a synchronization unit, for generating a charge control signal for applying a second voltage row by row to the touch electrodes;
an output unit, which outputs the first voltage and the second voltage respectively according to the charge control signals to charge the touch electrodes; and
a cutoff unit, for controlling, according to a voltage of a row of touch electrodes, activation and deactivation of a charging path of a preceding row of touch electrodes.

US Pat. No. 9,971,214

ARRAY SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

1. A manufacturing method of an array substrate structure, comprising the following steps:(1) providing a base plate and depositing a buffer layer on the base plate;
(2) depositing and patterning a semiconductor layer on the buffer layer and subjecting a partial area of the semiconductor layer to N-type heavy doping so as to form a source/drain contact zone for contact engagement with a source/drain terminal;
(3) sequentially depositing a gate insulation layer and an interlayer dielectric layer on the semiconductor layer and subjecting the gate insulation layer and the interlayer dielectric layer to patterning so as to form a first via in the gate insulation layer and the interlayer dielectric layer to correspond to the source/drain contact zone of the semiconductor layer;
(4) depositing and patterning a first metal layer on the interlayer dielectric layer so as to form a source/drain terminal, wherein the source/drain terminal is set in engagement with the source/drain contact zone of the semiconductor layer through the first via;
(5) depositing a planarization layer on the source/drain terminal and the interlayer dielectric layer;
(6) depositing and patterning a second metal layer on the planarization layer;
(7) depositing and patterning a first insulation layer on the second metal layer and the planarization layer so as to form a second via in the first insulation layer to correspond to the second metal layer;
(8) depositing and patterning a first oxide conductive layer on the first insulation layer so as to form a common electrode, wherein the common electrode is set in engagement with the second metal layer through the second via;
(9) depositing a reduction resistant layer on the common electrode and the first insulation layer;
(10) depositing a second insulation layer on the reduction resistant layer and simultaneously subjecting the second insulation layer, the reduction resistant layer, the first insulation layer, and the planarization layer to patterning so as to form a third via in the second insulation layer, the reduction resistant layer, the first insulation layer, and the planarization layer to correspond to the source/drain terminal; and
(11) depositing and patterning a second oxide conductive layer on the second insulation layer so as to form a pixel electrode, wherein the pixel electrode is set in engagement with the source/drain terminal through the third via.

US Pat. No. 9,786,240

SCAN DRIVING CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A scan driving circuit configured for driving cascaded scan lines, the scan driving circuit comprising:
an input control module inputted with a first clock signal of a current stage and cascade signals of a preceding stage, and
for generating a control signal based on the first clock signal of the current stage and the cascade signals of the preceding
stage;

a latch module for performing a latch operation for the control signal;
a driving-signal generation module for generating a driving signal based on the control signal and a second clock signal of
the current stage;

an output control module for outputting a scanning signal of the current stage and a cascade signal of the current stage based
on the driving signal;

a high gate voltage source for supplying a high voltage; and
a low gate voltage source for supplying a low voltage;
wherein the cascade signals include a first cascade signal and a second cascade signal that are opposite in phase;
wherein the input control module comprises a first switching transistor, a second switching transistor, a third switching
transistor, and a fourth switching transistor;

a control terminal of the first switching transistor is inputted with a first cascade signal of the preceding stage, an input
terminal of the first switching transistor is connected to the high gate voltage source, and an output terminal of the first
switching transistor is connected to an input terminal of the second switching transistor;

a control terminal of the second switching transistor is inputted with the first clock signal of the current stage, and an
output terminal of the second switching transistor is respectively connected to an input terminal of the third switching transistor
and an output terminal of the control signal;

a control terminal of the third switching transistor is inputted with the first clock signal of the current stage, and an
output terminal of the third switching transistor is connected to an output terminal of the fourth switching transistor;

a control terminal of the fourth switching transistor is inputted with a second cascade signal of the preceding stage, and
an input terminal of the fourth switching transistor is connected to the low gate voltage source;

wherein the latch module comprises a fifth switching transistor, a sixth switching transistor, a seventh switching transistor,
and an eighth switching transistor;

an input terminal of the fifth switching transistor is connected to the high gate voltage source, and an output terminal of
the fifth switching transistor is connected to the output terminal of the control signal,

a control terminal of the sixth switching transistor is connected to the control terminal of the fifth switching transistor,
an input terminal of the sixth switching transistor is connected to the low gate voltage source, and an output terminal of
the sixth switching transistor is connected to the output terminal of the control signal;

a control terminal of the seventh switching transistor is connected to the output terminal of the control signal, an input
terminal of the seventh switching transistor is connected to the high gate voltage source, and an output terminal of the seventh
switching transistor is connected to the control terminal of the fifth switching transistor; and

a control terminal of the eighth switching transistor is connected to the output terminal of the control signal, an input
terminal of the eighth switching transistor is connected to the low gate voltage source, and an output terminal of the eighth
switching transistor is connected to the control terminal of the fifth switching transistor;

wherein the fifth switching transistor and the seventh switching transistor are PMOS transistors, and the sixth switching
transistor and the eighth switching transistor are NMOS transistors.

US Pat. No. 9,507,071

LIGHT GUIDE PLATE AND BACKLIGHT MODULE

WUHAN CHINA STAR OPTOELEC...

1. A light guide plate, comprising a first end surface, a second end surface opposite to the first end surface, an upper surface
connected to upper ends of the first end surface and the second end surface, and a lower surface connected to lower ends of
the first end surface and the second end surface;
wherein the first end surface comprises an arc configuration bulging outwardly of the light guide plate;
wherein the upper surface comprises three sections, which are respectively a first horizontal surface, a first slope surface,
and a second horizontal surface, the first horizontal surface being connected to the first end surface, the first slope surface
being connected, at an inclination, between the first horizontal surface and the second horizontal surface, the first horizontal
surface and the first slope surface defining therebetween a first included angle, the first included angle being an obtuse
angle;

wherein the lower surface comprises three sections, which are respectively a third horizontal surface, a second slope surface,
and a fourth horizontal surface, the third horizontal surface being connected to the first end surface, the second slope surface
being connected, at an inclination, between the third horizontal surface and the fourth horizontal surface, the third horizontal
surface and the second slope surface defining therebetween a second included angle, the second included angle being an obtuse
angle; and

wherein the first end surface serves as a light incident surface of the light guide plate and the second horizontal surface
serves as a light exit surface of the light guide plate.

US Pat. No. 9,857,626

SUBSTRATES FOR LIQUID CRYSTAL PANELS AND LIQUID CRYSTAL PANELS

Wuhan China Star Optoelec...

1. A substrate of liquid crystal panels, comprising:
a glass substrate;
a wire grid layer arranged on the glass substrate, the wire grid layer comprises:
a dielectric layer arranged on one side of the glass substrate;
a metal layer arranged on the dielectric layer, the metal layer comprises a plurality of first metal bars and a plurality
of second metal bars, the second metal bars are configured to intersect with each other to divide the metal layer into a first
area, a second area, and a third area cyclically arranged, the first area, the second area, and the third area respectively
correspond to sub-pixel areas on an array substrate, the first metal bars are arranged within the first area, the second area,
and the third area in sequence, and the first metal bars are parallel to and are spaced apart from each other, the first metal
bars within the first area, the second area, and the third area respectively comprise a first period, a second period, and
a third period different from each other, wherein the first period of the first metal bars is defined as a width of the first
metal bar plus two gaps between the first metal bar and the two adjacent first metal bars.

US Pat. No. 9,885,924

LIQUID-CRYSTAL DISPLAY PANEL AND DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A liquid-crystal display panel, comprising:
a first substrate;
a second substrate disposed opposite to the first substrate, comprising a pixel electrode and a first common electrode; and
a liquid-crystal layer disposed between the first substrate and the second substrate;
wherein the pixel electrode is spiral; the pixel electrode includes at least two pixel electrode spiral pitches, and any two
of the pixel electrode spiral pitches are not equal;

the first common electrode and the pixel electrode are interlaced and arranged at intervals, and the first common electrode
is also spiral.

US Pat. No. 9,865,207

LIQUID CRYSTAL DISPLAY PANEL OF COLUMN INVERSION DRIVING MODE AND DRIVING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A liquid crystal display panel of column inversion driving mode, comprising a plurality of data lines, which are mutually
parallel, sequentially aligned and vertical, a plurality of scan lines, which are mutually parallel, sequentially aligned
and horizontal and a plurality of pixels arranged in array, and each pixel comprises a pixel driving circuit inside; all the
plurality of pixel driving circuits in the pixels of the same row are electrically coupled to the scan line corresponding
to the pixel of the row; all the plurality of pixel driving circuits in the pixels of odd column and in the pixels of even
column respectively at the left, right sides of each data line are electrically coupled to the data line;
the pixel driving circuit comprises: a driving thin film transistor, a charge control thin film transistor, a storage capacitor
and a liquid crystal capacitor; one of the charge control thin film transistor in the pixel of even column and the charge
control thin film transistor in the pixel of odd column is controlled by a high voltage level to be on, and the other is controlled
by a low voltage level to be on;

both gates of the charge control thin film transistor in the pixel of even column and the charge control thin film transistor
in the pixel of odd column are electrically coupled to a clock signal; the clock signal alternately provides the high, low
voltage levels to control the charge control thin film transistor in the pixel of even column and the charge control thin
film transistor in the pixel of odd column to be alternately on;

as the liquid crystal display panel of column inversion driving mode shows two adjacent frames: in the previous frame, the
scan line provides a scan signal of which the duration is a first duration, and the clock signal first provides the high voltage
level of which the duration is a second duration to control the charge control thin film transistor in the pixel of even column
or the charge control thin film transistor in the pixel of odd column to be on, and meanwhile, the data line provides a positive
voltage to make a source voltage of the driving thin film transistor in the pixel of even column or a source voltage of the
driving thin film transistor in the pixel of odd column to be positive for charging the pixel of even column or the pixel
of odd column; then, the clock signal provides a low voltage level of which the duration is a third duration to control the
charge control thin film transistor in the pixel of odd column or the charge control thin film transistor in the pixel of
even column, which is not on in the second duration to be on, and meanwhile, the data line provides a negative voltage to
make the source voltage of the driving thin film transistor in the pixel of odd column or the source voltage of the driving
thin film transistor in the pixel of even column to be negative for charging the pixel of odd column or the pixel of even
column;

in the latter frame, the scan line provides the scan signal of which the duration is the first duration, and the clock signal
first provides the high voltage level of which the duration is the third duration to control the charge control thin film
transistor in the pixel of even column or the charge control thin film transistor in the pixel of odd column to be on, and
meanwhile, the data line provides a negative voltage to make a source voltage of the driving thin film transistor in the pixel
of even column or a source voltage of the driving thin film transistor in the pixel of odd column to be negative for charging
the pixel of even column or the pixel of odd column; then, the clock signal provides the low voltage level of which the duration
is the second duration to control the charge control thin film transistor in the pixel of odd column or the charge control
thin film transistor in the pixel of even column, which is not on in the third duration to be on, and meanwhile, the data
line provides a positive voltage to make the source voltage of the driving thin film transistor in the pixel of odd column
or the source voltage of the driving thin film transistor in the pixel of even column to be positive for charging the pixel
of odd column or the pixel of even column;

the first duration is a sum of the second duration and the third duration.

US Pat. No. 9,858,874

SCAN DRIVING CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A scan driving circuit for driving scan line in cascade, comprising:
a pull-down controlling module for receiving a scan signal of a previous stage and generating a scan voltage signal having
a low voltage level in the corresponding scan line, according to the scan signal of the previous stage;

a pull-down module for pulling down a scan signal of the corresponding scan line according to the scan voltage signal;
a reset-controlling module for receiving a clock signal of a next stage and generating a reset signal of the corresponding
scan line according to the clock signal of the next stage;

a resetting module for pulling up the scan signal of the corresponding scan line according to the reset signal;
a downward-transferring module for generating and transmitting a clock signal of a present stage according to the scan signal
of the scan line;

a first bootstrap capacitor for generating the scan voltage signal having either the low voltage level or a high voltage level
in the scan line;

a constant low voltage level source for providing a low voltage level signal; and a constant high voltage level source for
providing a high voltage level signal, wherein the resetting module comprises a fourth transistor, a fifth transistor, a sixth
transistor, a seventh transistor, and an eleventh transistor; the reset signal is inputted into a control terminal of the
fourth transistor;

an input terminal of the fourth transistor is connected with the constant low voltage level source, and an output terminal
of the fourth transistor is connected with an output terminal of the sixth transistor;

a control terminal of the fifth transistor is connected with the output terminal of the sixth level source, and an output
terminal of the fifth transistor is connected with an output of the pull-down module;

a control terminal of the sixth transistor is connected with an output terminal of the eleventh transistor, and an input terminal
of the sixth transistor is connected with the constant high voltage level source; a control terminal of the seventh transistor
is connected with the output terminal of the sixth transistor, an input terminal of the seventh transistor is connected with
the constant high voltage level source, and an output terminal of the seventh transistor is connected with an output terminal
of the scan line which outputs the scan signal;

a control terminal of the eleventh transistor is connected with the constant low voltage level source, an input terminal of
the eleventh transistor is connected with the pull-down module, and the output terminal of the eleventh transistor is connected
with the control terminal of the sixth transistor;

wherein the resetting module further comprises a second bootstrap capacitor, a terminal of the second bootstrap capacitor
is connected with the constant high voltage level source, and another terminal of the second bootstrap capacitor is connected
with the output terminal of the fourth transistor; and the scan driving circuit utilizes either P-type metal-oxide semiconductor
transistors or N-type metal-oxide semiconductor transistors to control the pull-down controlling module, the pull-down module,
the resetting module, the reset-controlling module, and the downward-transferring module; and

wherein the pull-down controlling module is further used for receiving a scan signal of the next stage and generating the
scan voltage signal having the low voltage level in the corresponding scan line, according to the scan signal of the next
stage; and the reset-controlling module is further used for receiving a clock signal of the previous stage and generating
the reset signal of the corresponding scan line, according to the clock signal of the previous stage.

US Pat. No. 9,841,547

BACKLIGHT MODULES AND LIQUID CRYSTAL DEVICES

WUHAN CHINA STAR OPTOELEC...

1. A backlight module, comprising:
a LED component, a light guiding plate, a quantum dot (QD) layer, and a graphite sheet, the QD layer is arranged between the
LED component and the light guiding plate, the QD layer is arranged on the graphite sheet;

wherein a surface of the QD layer comprises at least two first protrusions, and the surface of the QD layer contacts with
the graphite sheet, the graphite sheet comprises first holes engaging with the first protrusions, and the QD layer is inserted
into the graphite sheet.

US Pat. No. 9,857,773

SMART WATCH AND MULTIPLE NUMERICAL OPERATION METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A smart watch, which comprises: a dial (10), a first strap (20) and a second strap (24), connected respectively to both sides of the dial (10), a main display (12) disposed on a front of the dial (10), a first secondary display (13) disposed on the end of the first strap (20) connected to the dial (10), and a second secondary display (14) disposed on the end of the second strap (24) and connected to the dial (10);
wherein the main display (12), the first secondary display (13) and the second secondary display (14) are monolithically made from a display motherboard (100), and are controlled by the same control circuit; and

wherein the display motherboard (100) is a flexible organic light-emitting diode (OLED) display motherboard;

the display motherboard (100) comprises: a substrate (110), a light-emitting layer (120) disposed on the substrate (110), an encapsulation layer (130) disposed on the substrate (110) surrounding the light-emitting layer (120), and a control circuit connection area (140) disposed on the substrate (110) outside of the layer encapsulation layer (130);

the substrate (110) being a flexible substrate, comprising a first light-emitting area (111), a first bending area (112), a second light-emitting area (113), a second bending area (114), and a third light-emitting area (115) disposed consecutively;

the light-emitting layer (120) covering the first light-emitting area (111), the second light-emitting area (113) and the third light-emitting area (115), and being disposed with a trench corresponding to the locations of the first bending area (112) and the second bending area (114);

the light-emitting layer (120) covering the first light-emitting area (111), the second light-emitting area (113) and the third light-emitting area (115) being electrically connected through metal wires of the trench; and

the display motherboard (100) having a bend at the first bending area (112) and a second bending area (114) respectively, and being connected to a control circuit through the control circuit connection area (140) to form the main display (12), the first secondary display (13) and the second secondary display (14).

US Pat. No. 9,857,619

DISPLAY PANEL

Wuhan China Star Optoelec...

1. A display panel, wherein the display panel comprises:
a color filter plate substrate and an array substrate;
the color filter plate substrate comprises a black matrix and a protective layer;
the color filter plate substrate and the array substrate are disposed opposite;
the protective layer is disposed on a side of the black matrix oriented to the array substrate in a laser incidence region;
wherein the protective layer is formed by a plurality of alternate spacers disposed on the black matrix layer;
wherein the array substrate comprises a thin film transistor (TFT) and a metal wire, a spacer is disposed on the black matrix
of a position corresponding to the TFT and metal wire;

wherein distribution of the each spacer corresponding to the TFT and metal wire is more compact than that of the each spacer
corresponding to the peripheral region of the array substrate.

US Pat. No. 9,805,672

LIQUID CRYSTAL DISPLAY PANEL AND DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A liquid crystal display panel, comprising:
a first substrate including a first transparent conductive layer positioned on an inner side of the first substrate close
to a liquid crystal layer, wherein the first transparent conductive layer is configured to introduce a first polarity electric
charge accumulated on the first substrate;

the liquid crystal layer disposed between the first substrate and a second substrate; and
the second substrate disposed opposite to the first substrate and including a second transparent conductive layer positioned
on an inner side of the second substrate, wherein the second transparent conductive layer is configured to introduce a second
polarity electric charge accumulated on the second substrate;

wherein a connecting component is disposed on the first substrate and/or the second substrate; and only when pressing the
liquid crystal display panel, the first transparent conductive layer and the second transparent conductive layer are electrically
connected to each other by the connecting component;

wherein the connecting component is a protrusion, and the material of the protrusion is resin,
wherein the liquid crystal display panel includes a display area configured to display image signals; and the connecting component
is positioned out of the display area.

US Pat. No. 9,698,177

METHOD FOR MANUFACTURING N-TYPE TFT

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing an N-type thin-film transistor (TFT), comprising the following steps:
(1) providing a substrate, depositing a light shielding layer on the substrate, and subjecting the light shielding layer to
a grating like patternization treatment so as to obtain multiple mutually spaced independent light shielding blocks that are
spaced from each other;

(2) sequentially depositing a buffer layer and an amorphous silicon layer on the multiple independent light shielding blocks
and the substrate and having the amorphous silicon layer crystallized and converted into a poly-silicon layer,

wherein the poly-silicon layer has first zones that correspond to the multiple independent light shielding blocks and have
crystalline grains of a smallest size, second zones that correspond to separation spaces each between two adjacent ones of
the independent light shielding blocks and have crystalline grains of a largest size, and remaining, third zones that have
crystalline grains of an intermediate size;

(3) depositing a gate insulation layer on the poly-silicon layer;
(4) depositing and patterning a conductive film on the gate insulation layer to obtain a gate conductor layer,
wherein the gate conductor layer is located exactly above the multiple mutually spaced independent light shielding blocks
with the third zones and parts of the first zones of the poly-silicon layer exposed at two opposite sides thereof; and

(5) subjecting the poly-silicon layer to one N-type ion doping operation by using the gate conductor layer as a shielding
layer, wherein the N-type ion doped third zones of the poly-silicon layer have electrical resistivity that is smaller than
electrical resistivity of the parts of the N-type ion doped first zones of the poly-silicon layer so that the parts of the
N-type ion doped first zones of the poly-silicon layer are equivalent to lightly-doped zones.

US Pat. No. 9,876,120

LOW TEMPERATURE POLY-SILICON TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A low temperature poly-silicon (LTPS) thin-film transistor (TFT) substrate manufacturing method, comprising the following
steps:
(1) providing a base plate, depositing a first metal layer on the base plate, and subjecting the first metal layer to a patterning
operation to form a gate electrode;

(2) depositing a gate insulation layer on the base plate and the gate electrode;
(3) forming a poly-silicon layer on the gate insulation layer;
(4) subjecting two opposite sides of the poly-silicon layer to ion implantation to form source/drain contact zones; and subjecting
a central area of the poly-silicon layer to ion implantation to form a channel zone;

(5) depositing a second metal layer on the gate insulation layer and the poly-silicon layer and subjecting the second metal
layer to a patterning operation to form a source electrode, a drain electrode, and a metal layer located between the source
electrode and the drain electrode; and

(6) using the metal layer and the source and drain electrodes as a mask to subject the poly-silicon layer to ion implantation
so as to form lightly-doped drain (LDD) zones located respectively between the source/drain contact zones and the channel
zone.

US Pat. No. 9,818,361

GOA CIRCUITS AND LIQUID CRYSTAL DEVICES

Shenzhen China Star Optoe...

1. A gate driver on array (GOA) circuit of liquid crystal devices (LCDs), comprising:
a plurality of cascaded GOA units, each of the cascaded GOA units is configured for charging corresponding horizontal scanning
lines within a display area when being driven by a first level clock, a second level clock, a first control clock, and a second
control clock, the first level clock and the second level clock are configured for controlling an input of level signals of
the GOA unit and for controlling generation of gate driving signals, the first control clock and the second control clock
are configured for controlling the gate driving signals to be at a first level, and wherein the level signals are turn-on
pulse signals or the gate driving signals of adjacent GOA units; and

after the horizontal scanning lines have been charged completely by the GOA circuit, a control module is configured for resetting
the gate driving signals, except for first gate driving signals, to be the first level via the turn-on pulse signals and a
negative-voltage constant-voltage source, before the first gate driving signals are outputted, the horizontal scanning lines
are prevented from generating redundant pulse signals, at the same time, load on a signal line of the turn-on pulse signals
is decreased, the negative-voltage constant-voltage source is configured for providing constant low level signals for each
of the GOA units;

wherein the GOA unit comprises a forward-backward scanning unit, an input control unit, a pull-up maintaining unit, an output
control unit, a GAS signal operation unit, and a bootstrap capacitance unit;

the forward-backward scanning unit is configured for controlling a forward driven method or a backward driven method of the
GOA circuit to maintain the common signal point at a second level in response to the first control clock or the second control
clock;

the input control unit is configured for charging the gate signal point after the first level clock controls an input of the
level signals;

the pull-up maintaining unit is configured for maintaining the gate signal point to be at the first level during a non-operation
period in accordance with the common signal point;

the output control unit controls the output of the gate driving signals corresponding to the gate signal point in accordance
with the second level clock;

the GAS signal operation unit controls the gate driving signals to be at the second level so as to charge the horizontal scanning
line corresponding to the GOA unit; and

the bootstrap capacitance unit lifts a voltage of the gate signal point.

US Pat. No. 9,817,171

LIGHT GUIDE PLAT AND BACKLIGHT MODULE HAVING THE SAME

Wuhan China Star Optoelec...

1. A light guide plate, comprising:
a plate body having a top surface functioned as a light emitting surface, and a second bottom surface; and
a wedge-shaped body having an inclined surface, and extended upward along a terminal of the plate body, and wherein the wedge-shaped
body further includes a first bottom surface disposed opposite to the inclined surface, a first terminal surface functioned
as a light incident surface, and a second terminal surface disposed opposite to the first terminal surface and connected with
the plate body;

wherein, the top surface of the plate body is connected smoothly with the inclined surface of the wedge-shaped body;
wherein, the inclined surface is provided with multiple first protrusion blocks arranged at intervals and extended along a
first direction, multiple second protrusion blocks arranged at intervals and extended along a second direction, and a first
spaced region disposed between the multiple first protrusion blocks and the multiple second protrusion blocks;

wherein, the top surface is provided with multiple third protrusion blocks extended along a third direction; and
wherein, the third direction is a symmetric axis of the first direction and the second direction.

US Pat. No. 9,651,815

SELF-CAPACITANCE IN-CELL TOUCH SCREEN AND METHOD OF MANUFACTURING THE SAME, LIQUID CRYSTAL DISPLAY

WUHAN CHINA STAR OPTOELEC...

1. A self-capacitance in-cell touch screen comprising an array substrate which has a glass substrate, thin film transistors
disposed on the glass substrate, and pixel electrodes electrically connected with the thin film transistors, a planarizing
layer being disposed between the pixel electrodes and the thin film transistors, wherein a transparent touch control sensing
electrode, a first insulation layer, a second insulation layer, and a metal connection line are disposed on the planarizing
layer in sequence, and the metal connection line is electrically connected to the touch control sensing electrode through
via holes disposed in the first insulation layer and the second insulation layer; wherein the first insulation layer extends
to a position between the planarizing layer and the pixel electrode, and the second insulation layer extends to be located
on the pixel electrodes which are electrically connected to the thin film transistors through a via hole disposed in the first
insulation layer and the planarizing layer; and
wherein the touch control sensing electrode is further configured as a common electrode to transfer a common voltage and a
touch scan signal by time-sharing during a period of displaying one frame image.

US Pat. No. 9,651,818

LIQUID CRYSTAL DISPLAY PANEL COMPRISING DIFFERENT SPACING DISTANCES BETWEEN PIXEL ELECTRODES CORRESPONDING TO SPECIFIC COLOR RESIST BLOCKS

WUHAN CHINA STAR OPTOELEC...

1. A liquid crystal display panel, comprising: a color filter substrate (100) and an array substrate (200) that are arranged opposite to each other and a liquid crystal layer interposed between the color filter substrate (100) and the array substrate (200);
the color filter substrate (100) comprising a first backing plate (1) and a color resist layer (2) and a black matrix (3) arranged on the first backing plate (1), the color resist layer (2) comprising a plurality of color resist blocks (20) that is arranged in an array, wherein the plurality of color resist blocks (20) comprises red resist blocks (21), green resist blocks (22), and blue resist blocks (23), the black matrix (3) comprising a plurality of black light-shielding strips (30) respectively located in spacing zones between the plurality of color resist blocks (20);

the array substrate (200) comprises a second backing plate (7), a thin-film transistor (TFT) layer (6) arranged on the second backing plate (7), and a pixel electrode layer (4) arranged on the TFT layer (6), the pixel electrode layer (4) comprising a plurality of pixel electrodes (40) corresponding respectively to the plurality of color resist blocks (20), the plurality of pixel electrodes (40) comprising first pixel electrodes (41) corresponding to the red resist blocks (21), second pixel electrodes (42) corresponding to the green resist blocks (22), and third pixel electrodes (43) corresponding to the blue resist blocks (23);

wherein a spacing distance (b1) between the second pixel electrodes (42) that correspond to the green resist blocks (22) and the first pixel electrodes (41) that correspond to the red resist blocks (21) and a spacing distance (b2) between the second pixel electrodes (42) that correspond to the green resist blocks (22) and the third pixel electrodes (43) that correspond to the blue resist blocks (23) are both greater than a spacing distance (b3) between the first pixel electrodes (41) that correspond to the red resist blocks (21) and the third pixel electrodes (43) that correspond to the blue resist blocks (23).

US Pat. No. 9,664,941

COLOR FILTER SUBSTRATE AND CURVED LIQUID CRYSTAL DISPLAY PANEL COMPRISING SAME

WUHAN CHINA STAR OPTOELEC...

1. A color filter (CF) substrate, comprising a transparent substrate, a plurality of pixel zones arranged on the transparent
substrate in a manner of being spaced from each other, a black matrix arranged on the transparent substrate and located between
the plurality of pixel zones, and a plurality of main photo spacers and a plurality of sub photo spacers arranged on the black
matrix;
the black matrix comprising a plurality of longitudinally-arranged and laterally-arranged light-shielding strips and a plurality
of expanded sections formed on two sides of the light-shielding strips, the plurality of main photo spacers and the plurality
of sub photo spacers being arranged in a central area of light-shielding strips to be spaced from each other in an extension
direction of the light-shielding strip, the plurality of expanded sections being arranged on the two sides of the light-shielding
strips to respectively correspond to the plurality of main photo spacers, the expanded sections located in an edge area of
the CF substrate having an area that is less than an area of the expanded sections located in the central area of the CF substrate;

wherein the light-shielding strips of the black matrix that are located in the edge area of the CF substrate have a width
that is less than a width of the light-shielding strips of the black matrix that are located in the central area of the CF
substrate.

US Pat. No. 9,841,647

LIQUID CRYSTAL DISPLAY, ELECTRONIC DEVICE AND LIQUID CRYSTAL PANEL

WUHAN CHINA STAR OPTOELEC...

1. A liquid crystal panel, comprising an array substrate and a color film substrate disposed opposite to the array substrate,
wherein the liquid crystal panel further comprises a polarizer, the polarizer comprises a main body and a extension part,
a transparent conductive adhesive is disposed on the main body and the extension part, the main body is attached to a side
of the color film substrate away from the array substrate through the transparent conductive adhesive, the extension part
extends from a edge of the main body to the color film substrate, a ground point is disposed on the array substrate, the extension
part is attached to the ground point through the transparent conductive adhesive, so as to form a discharge loop between the
ground point and the main body.

US Pat. No. 9,842,935

LOW TEMPERATURE POLY SILICON (LTPS) THIN FILM TRANSISTOR (TFT) AND THE MANUFACTURING METHOD THEREOF

Shenzhen China Star Optoe...

1. A manufacturing method of low temperature poly silicon (LTPS) thin film transistors (TFTs), comprising:
forming a semiconductor layer and a LTPS layer on one surface on a base layer;
forming an oxide layer is formed on one side of the semiconductor layer facing away the base layer, and forming the oxide
layer on one side of the LTPS layer facing away the base layer;

a forming a plurality of first photoresist layers of a first thickness on the oxide layer;
arranging a corresponding first cobalt layer on each of the photoresist layers, a vertical projection of the first cobalt
layer overlaps with a vertical projection of the corresponding first photoresist layer;

doping high concentration doping ions into a first area of the semiconductor layer, and the high-concentration being larger
than 1×1017/cm3;

removing the first cobalt layer, and applying an ashing process to a portion of the first photoresist layers to obtain second
photoresist layers of a second thickness, the second thickness is less than the first thickness;

arranging a corresponding second cobalt layer on the second photoresist layer, a vertical projection of the second cobalt
layer is overlapped with the vertical projection of the corresponding second photoresist layer;

doping low concentration doping ions into a second area of the semiconductor layer, and the low-concentration being less than
1×1014/cm3; and

removing the second cobalt layer, and applying the ashing process to the second photoresist layers to remove the second photoresist
layers.

US Pat. No. 9,818,357

GOA CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A Gate on Array (GOA) circuit applied in a liquid crystal display device, comprising: multiple cascaded GOA units, wherein,
each of the multiple cascaded GOA units is used for charging a corresponding horizontal scanning line in a display area through
driving of a first stage-transferring clock, a second stage-transferring clock, a first control clock and a second control
clock; the first stage-transferring clock and the second stage-transferring clock are used to control an inputting of a stage-transferring
signal of the GOA unit and a generation of a gate driving signal of the GOA unit; the first control clock and the second control
clock are used to control the gate driving signal to be in a first voltage level; wherein, the stage-transferring signal is
a starting pulse signal or agate driving signal of an adjacent GOA unit;
the GOA unit includes a forward and backward scanning unit, an input control unit, a pull-up holding unit, an output control
unit, a GAS (gate-all-select) signal function unit and a bootstrap capacitor unit;

the forward and backward scanning unit is used for controlling a forward driving or a backward driving of the GOA circuit,
and under the control of the first control clock and the second control clock, controlling a common signal node to be held
in a second voltage level;

the input control unit is used for controlling the inputting of the stage-transferring signal according to the first stage-transferring
clock in order to finish a charging of a gate signal node;

the pull-up holding unit is used for controlling the gate signal node to be held in a first voltage level in a non-operation
period according to the common signal node;

the output control unit is used for controlling an outputting of the gate driving signal corresponding to the gate signal
node according to the second stage-transferring clock;

the GAS signal function unit is used for controlling the gate driving signal to be in the second voltage level in order to
realize the charging of the horizontal scanning line corresponding to the GOA unit; and

the bootstrap capacitor is used for boosting a voltage of the gate signal node again;
the forward and backward scanning unit includes a first transistor, a second transistor, a third transistor and a fourth transistor;
a gate of the first transistor receives a first scanning control signal; a source of the first transistor receives a gate
driving signal outputted from a next stage GOA unit; a gate of the second transistor receives a second scanning control signal;
a source of the second transistor receives a gate driving signal outputted from a previous stage GOA unit; a drain of the
first transistor and a drain of the second transistor are connected with each other and are connected with the input control
unit; a gate of the third transistor receives the first control clock; a gate of the fourth transistor receives the second
scanning control signal; a source of the fourth transistor receives the second control clock; a drain of the third transistor
and a drain of the fourth transistor are connected with each other and are connected with the pull-up holding unit;

the input control unit includes a fifth transistor; a gate of the fifth transistor receives the first stage-transferring clock;
a source of the fifth transistor is connected with a drain of the first transistor and a drain of the second transistor; a
drain of the fifth transistor is connected with the gate signal node;

the pull-up holding unit includes a sixth transistor, a seventh transistor, a ninth transistor, a tenth transistor and a first
capacitor; a gate of the sixth transistor is connected with the common signal node; a source of the sixth transistor is connected
with a drain of the fifth transistor; a drain of the sixth transistor is connected with a first constant voltage source; a
gate of the seventh transistor is connected with a drain of the fifth transistor; a source of the seventh transistor is connected
with the common signal node; a drain of the seventh transistor is connected with the first constant voltage source, that is,
the positive constant voltage source; a gate of the ninth transistor is connected with a drain of the third transistor and
a drain of the fourth transistor; a source of the ninth transistor is connected with a second constant voltage source; a drain
of the ninth transistor is connected with the common signal node; a gate of the ninth transistor is connected with the common
signal node; a source of the ninth transistor is connected with the gate driving signal; a drain of the tenth transistor is
connected with the first constant voltage source; one terminal of the first capacitor is connected with the first constant
voltage source; the other terminal of the first capacitor is connected with the common signal node;

the output control unit includes an eleventh transistor and a second capacitor; a gate of the eleventh transistor is connected
with the gate signal node; a drain of the eleventh transistor is connected with the gate driving signal; a source of the eleventh
transistor receives the second stage-transferring clock; one terminal of the second capacitor is connected with the gate signal
node; the other terminal of the second capacitor is connected with the gate driving signal;

the GAS (gate-all-select) signal function unit includes a thirteenth transistor and a fourteenth transistor; a gate of the
thirteenth transistor, a gate and a drain of the fourteenth transistor receive a GAS signal; a drain of the thirteenth transistor
is connected with the first constant voltage source; a source of the thirteenth transistor is connected with the common signal
node; a source of the of the thirteenth transistor is connected with the gate driving signal;

the bootstrap capacitor unit includes a bootstrap capacitor; one terminal of the bootstrap capacitor is connected with the
gate driving signal, and the other terminal of the bootstrap capacitor is connected to a ground signal;

the GOA unit further includes a voltage regulation unit and a pull-up auxiliary unit; the voltage regulation unit includes
an eighth transistor; the eighth transistor is connected in series between a source of the fifth transistor and the gate signal
node; a gate of the eighth transistor is connected with the second constant voltage source; a drain of the eighth transistor
and a drain of the fifth transistor are connected; a source of the eighth transistor is connected with the gate signal node;
the pull-up auxiliary unit includes a twelfth transistor; a gate of the twelfth transistor is connected with the drain of
the first transistor and a drain of the second transistor; a source of the twelfth transistor is connected with the common
signal node; a drain of the twelfth transistor is connected with the positive constant voltage source;

the GOA circuit further includes a control module used to control the gate driving signals except the gate driving signal
of the first stage GOA unit to be reset to the first voltage level after the GOA circuit finishes a charging for all of the
horizontal scanning lines simultaneously through the starting pulse signal such that a redundant pulse signal generated on
the horizontal scanning lines before the gate driving signal of the first stage GOA unit is outputted is avoid; and

the control module includes multiple first control transistors corresponding to the GOA units one by one except the first
stage GOA unit; a first terminal and a second terminal of each first control transistor are connected to receive the starting
pulse signal; a third terminal of each first control transistor is connected with the common signal node of a corresponding
GOA unit.

US Pat. No. 9,818,358

SCANNING DRIVING CIRCUIT AND THE LIQUID CRYSTAL DISPLAY APPARATUS WITH THE SCANNING DRIVING CIRCUIT THEREOF

Shenzhen China Star Optoe...

1. A scanning driving circuit, wherein scanning driving circuit comprising:
a latch module to receive an upper level control signal, a first and a second clock signal and a reset signal and perform
a calculation to the upper level control signal, the first and the second clock signal and the reset signal to get a first
control signal, and latch and output the first control signal;

a logic control module connected to the latch module to receive the first control signal output from the latch module and
perform a logic calculation to the first control signal, the second control signal and the third clock signal to get a logic
control signal, and output the logic control signal, wherein the logic control module comprising: a second to fifth controllable
switch;

an output module connected to the logic control module to receive the logic control signal output from the logic control module
and perform a calculation to the logic control signal and the second control signal to get a scanning driving signal, and
output the scanning driving signal; and

a scan line connected to the output module to transmit the scanning driving signal output from the output module to the pixel
unit.

US Pat. No. 9,799,293

LIQUID CRYSTAL DISPLAY DEVICE AND GATE DRIVING CIRCUIT

Shenzhen China Star Optoe...

1. A gate driving circuit, wherein, the gate driving circuit includes multiple-stage gate driving units and a control chip,
wherein each stage gate driving unit comprises:
a first pulling control circuit for outputting a first pulling control signal at a first node;
a first pulling circuit coupled with the first node, receiving a first clock signal, pulling a voltage level of an output
terminal of a gate driving signal to a first voltage level according to the first pulling control signal and first clock signal
in order to output the gate driving signal;

a second pulling control circuit for outputting a second pulling control signal at a second node;
a second pulling circuit coupled with the first node and the second node, receiving a first voltage reference signal, and
pulling a voltage level of the first node to a second voltage level of the first voltage reference signal according to the
second pulling control signal, and the second pulling circuit pulls a voltage level of the gate driving signal to the second
voltage level;

a first control circuit coupled with the first node, receiving a first control signal and the first voltage reference signal,
pulling the voltage level of the first node to the second voltage level according to the first control signal;

a second control circuit coupled with the second node, receiving the first control signal and a second voltage reference signal,
pulling a voltage level of the second node to a third voltage level of the second voltage reference signal according to the
first control signal; and

a third control circuit coupled with the output terminal of the gate driving signal, receiving the first control signal and
a second control signal, and pulling the voltage level of the gate driving signal according to the first control signal and
the second control signal;

wherein, control chip is used for pulling the first clock signal, the first voltage reference signal, the first control signal
and the second control signal to the first voltage level such that scanning lines driven by the gate driving circuit are all
turned on;

wherein, the first pulling control circuit includes a first thin-film transistor and a second thin-film transistor;
a first terminal of the first thin-film transistor receives a first signal, a second terminal of the first thin-film transistor
receives a gate driving signal of a previous stage, and a third terminal of the first thin-film transistor is connected with
the first node; and

a first terminal of the second thin-film transistor receives a second signal; a second terminal of the second thin-film transistor
receives a gate driving signal of a next stage, and a third terminal of the second thin-film transistor is connected with
the first node;

wherein, the first pulling circuit includes a third thin-film transistor and a first capacitor, a first terminal of the third
thin-film transistor receives the first clock signal, a second terminal of the third thin-film transistor is connected with
the first node, a third terminal of the third thin-film transistor is the output terminal of the gate driving signal, and
the first capacitor is connected between the second terminal and the third terminal of the third thin-film transistor;

wherein, the first control circuit includes a fourth thin-film transistor, a first terminal of the fourth thin-film transistor
is connected with the first node, a second terminal of the fourth thin-film transistor receives the first control signal,
and a third terminal of the thin-film transistor receives the first voltage reference signal;

wherein, the second control circuit includes a fifth thin-film transistor, a first terminal of the fifth thin-film transistor
receives the second voltage reference signal, a second terminal of the fifth thin-film transistor receives the first control
signal, and a third terminal of the fifth thin-film transistor is connected with the second node;

wherein, the second pulling control circuit includes a sixth thin-film transistor and a seventh thin-film transistor, a first
terminal of the sixth thin-film transistor receives the second clock signal, a second terminal of the sixth thin-film transistor
is connected with the first terminal of the fourth thin-film transistor, a third terminal of the sixth thin-film transistor
is connected with a third terminal of the seventh thin-film transistor and the second node, a first terminal of the seventh
thin-film transistor receives the second voltage reference signal, a second terminal of the seventh thin-film transistor receives
the second clock signal; and

the second pulling circuit includes an eighth thin-film transistor, a ninth thin-film transistor, a tenth thin-film transistor
and a second capacitor, a first terminal of the eighth thin-film transistor is connected with the second terminal of the third
thin-film transistor, a second terminal of the eighth thin-film transistor receives the first clock signal, a third terminal
of the eighth thin-film transistor is connected with a first terminal of the ninth thin-film transistor, a second terminal
of the ninth thin-film transistor is connected with the third terminal of the seventh thin-film transistor, a third terminal
of the ninth thin-film transistor receives the first voltage reference signal, a first terminal of the tenth thin-film transistor
is connected with the third terminal of the thin-film transistor, a second terminal of the tenth thin-film transistor is connected
with the second terminal of the ninth thin-film transistor, a third terminal of the tenth thin-film transistor receives the
first voltage reference signal, the second capacitor is connected between the second terminal and the third terminal of the
tenth thin-film transistor.

US Pat. No. 9,786,722

DOUBLE-SIDE OLED DISPLAY

Wuhan China Star Optoelec...

1. A double-side OLED display, wherein it comprises a first light-emitting substrate, a second light-emitting substrate and
a color film layer, the first light-emitting substrate and the second light-emitting substrate are disposed opposite, the
color film layer is disposed between the first light-emitting substrate and the second light-emitting substrate, light from
the first light-emitting substrate partially penetrates the color film layer and forms a second display image on a side of
the second light-emitting substrate, light from the second light-emitting substrate partially penetrates the color film layer
and forms a first display image on a side of the first light-emitting substrate,
wherein the color film layer comprises a plurality of optical filter units.

US Pat. No. 9,760,203

SENSING CIRCUIT AND CAPACITIVE TOUCH PANEL HAVING THE SENSING CIRCUIT

Shenzhen China Star Optoe...

1. A sensing circuit, comprising signal input channels and signal output channels, and the sensing circuit further comprises:
first lead wires extending in a first direction, second lead wires and third lead wires, wherein,
an amount of the second lead wires is N, where N is a positive integer greater than 1, and every two adjacent second lead
wires are mutually parallel and extending in a second direction, and the second lead wires are isolated from the first lead
wires and the second direction intersects with first direction;

an amount of the third lead wires is N, and the third lead wires extend in a third direction and are respectively isolated
from the second lead wires and the first lead wires, and the third direction intersects with the first direction;

each signal input channel is coupled to the first lead wire corresponding thereto;
the signal output channels comprise second lead wire signal output channels and two third lead wire signal output channels,
wherein each third lead wire signal output channel is coupled to the N/2 third lead wires, and each third lead wire is coupled
to one third lead wire signal output channels, and an amount of the second lead wire signal output channels is N/2, and each
second lead wire signal output channel is coupled to two second lead wires, and each second lead wire is coupled to one second
lead wire signal output channel.

US Pat. No. 9,632,611

GOA CIRCUIT FOR IN-CELL TYPE TOUCH DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit for in-cell type touch display panel, which comprises: a plurality of cascade GOA
units, N being a positive integer, the N-th stage GOA unit further comprising: a forward and backward scan control module,
a first node pull-down control module, a second node control module, a second node reset module, a stop-duration output control
module, a black-screen-duration output control module, and a normal-display-duration output control module;
the black-screen-duration output control module further comprising: a thirteenth N-type thin film transistor (TFT); a gate
and a source of the thirteenth N-type TFT both connected to a first global control signal, and a drain being connected to
a scan output end; the first global control signal providing a constant positive voltage during black screen duration to make
the thirteenth N-type TFT of GOA unit of each stage conductive so that the scan driving signals of each stage being raised
to a high level voltage;

the second node control module further comprising: a twelfth N-type TFT; a gate of the twelfth N-type TFT being connected
to the first global control signal, a source connected to a negative voltage and a drain connected to a second node; during
black screen duration, the twelfth N-type TFT of GOA unit of each stage being controlled by the first global control signal
to become conductive, and the negative voltage providing a constant negative voltage during the black screen duration to pull
down the voltage level of the second node;

the second node reset module further comprising: a fourteenth N-type TFT; a gate and a source of the fourteenth N-type TFT
being connected to a reset signal, a drain being connected to the second node; the reset signal providing a single positive
voltage pulse signal when awakening from the black screen duration to make the fourteenth N-type TFT of GOA unit of each stage
conductive so that the second node of GOA unit of each stage being reset to the high level;

the stop-duration output control module further comprising: a fifteenth N-type TFT, a gate of the fifteenth N-type TFT connected
to a second global control signal, a source connected to the negative voltage, and a drain being connected to the scan output
end; the second global control signal providing a constant positive voltage during the stop duration to make the fifteenth
N-type TFT of GOA unit of each stage conductive; the negative voltage providing a pulse signal the same as a touch signal
in amplitude, phase and frequency during the stop duration so as to reduce the cross-talk between the touch signal and the
scan output end.

US Pat. No. 9,628,050

SCAN DRIVING CIRCUIT

Wuhan China Star Optoelec...

1. A scan driving circuit configured for driving cascaded scan lines, the scan driving circuit comprising:
an input control module inputted with a first clock signal of a current stage, cascade signals of a preceding stage, and cascades
signal of a succeeding stage, and for generating a control signal based upon the first clock signal of the current stage,
the cascade signals of the preceding stage, and the cascade signals of the succeeding stage;

a latch module for performing a latch operation for the control signal;
a driving-signal generation module for generating a driving signal based upon the control signal and a second clock signal
of the current stage;

an output control module for outputting a scanning signal of the current stage based upon the driving signal;
a constant high voltage source for providing a high voltage; and
a constant low voltage source for providing a low voltage,
wherein an inverted signal of the control signal is used as cascade signals on the current stage and outputted into the scan
driving circuit on the succeeding stage,

wherein the input control module includes a 19th switching transistor, a 20th switching transistor, a 21st switching transistor,
a 22nd switching transistor, a 23rd switching transistor, and a 24th switching transistor,

wherein a control end of the 19th switching transistor is connected with an output end of the driving-signal generation module,
an input end of the 19th switching transistor is connected with the constant high voltage source, and an output end of the
19th switching transistor is connected with a control end of the 21st switching transistor and a control end of the 22nd switching
transistor,

wherein a control end of the 20th switching transistor is connected with the output end of the driving-signal generation module,
an input end of the 20th switching transistor is connected with the constant low voltage source, and an output end of the
20th switching transistor is connected with the control end of the 21st switching transistor and the control end of the 22nd
switching transistor,

wherein an input end of the 21st switching transistor is connected with the constant high voltage source, and an output end
of the 21st switching transistor is connected with a control end of the 23rd switching transistor and a control end of the
24th switching transistor,

wherein an input end of the 22nd switching transistor is connected with the constant low voltage source, and an output end
of the 22nd switching transistor is connected with the control end of the 23rd switching transistor and the control end of
the 24th switching transistor,

wherein an input end of the 23rd switching transistor is connected with the constant high voltage source, and an output end
of the 23rd switching transistor is connected with an output end of the output control module,

wherein an input end of the 24th switching transistor is connected with the constant low voltage source, and an output end
of the 24th switching transistor is connected with the output end of the input control module,

wherein the 19th switching transistor, the 21st switching transistor and the 23rd switching transistor are PMOS transistors,
and the 20th switching transistor, the 22nd switching transistor and the 24th switching transistor are NMOS transistors,

the input control module includes a 1st switching transistor, a 2nd switching transistor, a 3rd switching transistor, a 4th
switching transistor, a 5th switching transistor, and a 6th switching transistor,

wherein a control end of the 1st switching transistor is inputted with the first clock signal of the current stage, an input
end of the 1st switching transistor is connected with the constant high voltage source, and an output end of the 1st switching
transistor is connected with an output end of the input control module,

wherein a control end of the 2nd switching transistor is inputted with the cascade signals of the preceding stage, an input
end of the 2nd switching transistor is connected with the constant high voltage source, and an output end of the 2nd switching
transistor is connected with an input end of the 3rd switching transistor,

wherein a control end of the 3rd switching transistor is inputted with the cascade signals on the succeeding stage, and an
output end of the 3rd switching transistor is connected with the output end of the input control module,

wherein a control end of the 4th switching transistor is inputted with the first clock signal of the current stage, an input
end of the 4th switching transistor is connected with an output end of the 5th switching transistor, and an output end of
the 4th switching transistor is connected with the output end of the input control module,

wherein a control end of the 5th switching transistor is inputted with the cascade signals of the preceding stage, and an
input end of the 5th switching transistor is connected with the constant low voltage source,

wherein a control end of the 6th switching transistor is inputted with the cascade signals of the succeeding stage, an input
end of the 6th switching transistor is connected with the constant low voltage source, and an output end of the 6th switching
transistor is connected with the output end of the 5th switching transistor.

US Pat. No. 10,071,935

METHOD FOR MANUFACTURING FLEXIBLE GRAPHENE ELECTRICALLY CONDUCTIVE FILM

WUHAN CHINA STAR OPTOELEC...

1. A method for manufacturing a flexible graphene electrically conductive film, comprising the following steps:(1) providing a base and forming a graphene layer on a surface of the base;
(2) providing polyvinyl alcohol, dissolving polyvinyl alcohol in water and heating to form a colloidal solution, which after cooling, forms a polyvinyl alcohol colloidal solution; and coating the polyvinyl alcohol colloidal solution on a surface of the graphene layer and drying so as to form a supporting layer on the surface of the graphene layer;
(3) removing the base from the graphene layer to obtain the graphene layer that is covered with the supporting layer; and
(4) placing the graphene layer that is covered with the supporting layer in water to allow the supporting layer on the surface of the graphene layer to dissolve in water thereby obtaining a flexible graphene electrically conductive film that is free of surface residue;
wherein the base is made of a material comprising a metal; and step (1) applies a chemical vapor deposition process to heat the base and at the same time supplies a hydrocarbon gas and a carrier gas to the surface of the base so as to form the graphene layer on the surface of the base.

US Pat. No. 9,824,621

GATE DRIVE CIRCUIT AND DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A gate drive circuit, comprising a shifting register, a first follower and a second follower, wherein
an output end of the shifting register is connected to input ends of the first follower and the second follower, respectively,
an output end of the first follower is connected to a first gate line and an output end of the second follower is connected
to a second gate line;

the shifting register comprises a latch and a first NAND gate circuit, wherein the latch is configured to receive a first
trigger signal and output a second trigger signal before a first scanning period and a second scanning period start, and continuously
output the second trigger signal in the first scanning period and the second scanning period, and the first NAND gate circuit
is configured to be driven by the second trigger signal to output a primary drive signal into the first follower and the second
follower in the first scanning period and the second scanning period;

the first follower comprises a second NAND gate circuit and a first buffer and is configured to be driven by the primary drive
signal to output a first gate drive signal to the first gate line in the first scanning period; and

the second follower comprises a third NAND gate circuit and a second buffer and is configured to be driven by the primary
drive signal to output a second gate drive signal to the second gate line in the second scanning period.

US Pat. No. 9,818,360

LIQUID CRYSTAL DISPLAY AND CONTROL METHOD FOR THE SAME

Shenzhen China Star Optoe...

1. A liquid crystal display, comprising:
multiple data lines, multiple scanning lines, and multiple pixel units arranged as a matrix, wherein each pixel unit includes
a first pixel and a second pixel, and the first pixel and the second pixel in each pixel unit is charged by a same corresponding
data line;

a first frequency division circuit for receiving a first control signal, performing a frequency division to the first control
signal in order to obtain a first clock signal;

a second frequency division circuit for receiving a second control signal, performing a frequency division to the second control
signal in order to obtain a second clock signal;

a gate-driver-on-array (GOA) circuit for generating a scanning signal according to the first clock signal and the second clock
signal;

a control circuit for receiving the first control signal and the second control signal, and when the scanning signal is effective,
controlling a first pixel and a second pixel corresponding to the scanning signal to be charged in a time-division manner
according to the first control signal and the second control signal;

wherein, the first frequency division circuit is a D (data) flip-flop, a clock terminal of the data flip-flop receives the
first control signal, a first output terminal of the data flip-flop is connected with a data input terminal of the data flip-flop,
a second output terminal of the data flip-flop outputs the first clock signal such that a frequency of the first clock is
one half of a frequency of the first control signal; and

wherein, the second frequency division circuit includes a first inverter, a data flip-flop and a second inverter; an input
terminal of the first inverter receives the second control signal; an output terminal of the first inverter is connected with
a clock terminal of the data flip-flop; an first output terminal of the data flip-flop is connected with a data input terminal
of the data flip-flop; a second output terminal of the data flip-flop is connected with an input terminal of the second inverter;
an output terminal of the second inverter outputs the second clock signal such that a frequency of the second clock signal
is one half of a frequency of the second control signal;

wherein the control circuit includes multiple control units corresponding to the multiple data lines one by one; each control
unit includes a first switching element and a second switching element; first terminals of the first switching element and
the second switching element are respectively connected with the first pixel and the second pixel; second terminals of the
first switching element and the second switching element are connected with a same corresponding data line after the second
terminals are connected with each other; the third terminals of the first switching element and the second switching element
correspondingly receive the first control signal and the second control signal;

wherein, when the first control signal is effective, the first switching element is turned on such that the data line charges
the first pixel; and

when the second control signal is effective, the second switching element is turned on such that the data line charges the
second pixel.

US Pat. No. 9,805,675

GOA CIRCUIT BASED ON THE LTPS AND A DISPLAY APPARATUS

WUHAN CHINA STAR OPTOELEC...

1. A GOA circuit based on the LTPS, comprising:
a modulation circuit;
a charging circuit;
an input signal terminal and an output signal terminal, wherein an output scanning signal is output from the output signal
terminal;

wherein the modulation circuit and the charging circuit are connected to the input signal terminal and the output signal terminal
to make the modulation circuit and the charging circuit in parallel connection, and the charging circuit is used to charge
the output scanning signal during mutation process to increase the mutation speed of the output scanning signal;

wherein the modulation circuit comprises a Hth level COA unit circuits in cascade connected, a Nth level GOA unit circuit
comprising: a forward and reverse scanning part, an input control part, a pull up maintain part, a potential stable part,
a pull up assistant part, an output control part, wherein the H and N are positive whole numbers and N is smaller or equal
to H;

the forward and reverse scanning part comprising a No. zero transistor, a first transistor, a second transistor, a third transistor,
a forward scanning signal, a reverse scanning signal, a N+1th level scanning driving signal, a N?1th level scanning driving
signal, a M+1th clock signal, a M+3th clock signal;

the forward scanning signal is connected to gates of the first transistor and the third transistor separately, the reverse
scanning signal is connected to gates of the No. zero transistor and the second transistor, the N+1th level scanning driving
signal is connected to a source of the No. zero transistor, the N?1th level scanning driving signal is connected to a source
of the first transistor, the M+1th clock signal is connected to a source of the third transistor, the M+3th clock signal is
connected to a source of the second transistor, drains of the No. zero transistor and the first transistor are connected,
and drains of the second transistor and the third transistor are connected;

wherein when N=1, the N?1th level scanning driving signal is connected to a startup signal, when N=H, the N+1th level scanning
driving signal is connected to the startup signal;

the input control part comprising a fourth transistor, a M+2th clock signal, a source of the fourth transistor is connected
to the drains of the No. zero transistor and the first transistor, the M+2th clock signal is connected to a gate of the fourth
transistor;

the pull up maintain part comprising a fifth transistor, a sixth transistor, an eighth transistor, a ninth transistor, a first
capacitor, a gate of the fifth transistor is connected to a first node, a source of the fifth transistor is connected to a
drain of the fourth transistor, a drain of the fifth transistor is connected to the first electrical potential; a gate of
the sixth transistor is connected to the first node, a source of the sixth transistor is connected to a drain of the eighth
transistor; a gate of the eighth transistor is connected to the drains of the second transistor and the third transistor,
a source of the eighth transistor is connected to the second electrical potential, the drain of the eighth transistor is connected
to the first node; a gate of the ninth transistor is connected to the first node, a source of the ninth transistor is connected
to the second node, a drain of the ninth transistor is connected to the first electrical potential, the first capacitor is
connected between the first node and the first electrical potential;

the potential stable part comprising a seventh transistor, a gate of the seventh transistor is connected to the second electrical
potential, a source of the seventh transistor is connected to the drain of the fourth transistor, and a drain of the seventh
transistor is connected to the second node;

the pull up assistant part comprising an eleventh transistor, a gate of the eleventh transistor is connected to the drains
of the No. zero transistor and the first transistor, a source of the eleventh transistor is connected to the first node, a
drain of the eleventh transistor is connected to the first electrical potential;

the output control part comprising a tenth transistor and a second capacitor, a gate of the tenth transistor is connected
to the second node, a source of the tenth transistor is connected to a Mth clock signal, a drain of the tenth transistor is
connected to the source of the ninth transistor, the second capacitor is connected to the second node and the drain of the
tenth transistor, the drain of the tenth transistor is connected to the Nth level scanning driving signal; and

wherein when M=N, the Mth clock signal, the M+1th clock signal, the M+2th clock signal and the M+3th clock signal is four
clock signals in one set of the clock signal in a cycle.

US Pat. No. 9,799,295

SCAN DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE CIRCUIT

Shenzhen China Star Optoe...

1. A scan driving circuit comprising:
an input module configured for receiving a preceding-stage control signal, a first clock signal and a second clock signal,
performing a calculation on the preceding-stage control signal, the first clock signal and the second clock signal to obtain
a first control signal and outputting the first control signal;

a resetting module, connected to the input module and configured for receiving a reset signal and resetting a control signal
node of the scan driving circuit according to the reset signal;

a latching module, configured for receiving the first control signal outputted by the input module, receiving the first clock
signal and the second clock signal, performing a calculation on the first control signal, the first clock signal and the second
clock signal to obtain a second control signal, and latching and outputting the second control signal at the control signal
node;

a logic processing module, connected to the latching module and configured for receiving the second control signal at the
control signal node outputted by the latching module, receiving a third clock signal, performing a logical calculation on
the second control signal and the third clock signal to obtain a logic control signal and outputting the logic control signal;

an output module, connected to the logic processing module and configured for receiving the logic control signal outputted
by the logic processing module, performing a calculation on the logic control signal to obtain a scan driving signal and outputting
the scan driving signal; and

a scan line, connected to the output module and configured for transmitting the scan driving signal outputted by the output
module to a pixel unit;

wherein the input module has a first output terminal for outputting the first control signal, the resetting module has a second
output terminal, the latching module has a first input terminal for receiving the first control signal, the first output terminal,
the second output terminal and the first input terminal are connected to a first common connection node among the input module,
the resetting module and the latching module;

wherein the control signal node is a second common connection node between the latching module and the logic processing module;
wherein latching module comprises a first inverter connected between the first common connection node and the second common
connection node and for inverting a signal at the second output terminal of the resetting module.

US Pat. No. 9,733,501

ARRAY SUBSTRATE OF LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY

WUHAN CHINA STAR OPTOELEC...

1. An array substrate of a liquid crystal display, comprising:
a glass substrate; and
a driving circuit for generating a data signal and a scanning signal, and driving components in a display area;
wherein the driving circuit is disposed on a periphery of the glass substrate, the driving circuit includes a flexible circuit
board and a driver chip disposed on the flexible circuit board, and the driver chip and the flexible circuit board are integrally
combined;
wherein a fanout wire is disposed on the glass substrate on an inner edge of the driving circuit, and a shape of the fanout
wire corresponds to the shape of the driving circuit.

US Pat. No. 9,726,939

TRANSFLECTIVE TYPE BLUE PHASE LIQUID CRYSTAL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY MODULE OF THE SAME

Shenzhen China Star Optoe...

1. A transflective type blue phase liquid crystal display module, comprising:
an upper substrate;
a lower substrate disposed oppositely to the upper substrate; and
blue phase liquid crystal molecules disposed between the upper substrate and the lower substrate;
wherein, the lower substrate is provided with multiple solid protrusion structures, multiple pixel electrodes and multiple
common electrodes are disposed alternately and disposed at intervals on an upper surface of each solid protrusion structure,
each solid protrusion structure includes an upper portion and a lower portion, the upper portion of the solid protrusion structure
is corresponding to a transmissive region, a location of the lower substrate corresponding to the lower portion which is not
overlapped with the upper portion of the solid protrusion structure is provided with a reflective layer in order to form a
reflective region; and

between the pixel electrodes and the common electrodes, electric fields that are in parallel with a surface of each solid
protrusion structure are generated in order to drive the blue phase liquid crystal molecules, slope inclination angles of
the upper portion and the lower portion of each solid protrusion structure are different such that optical delay properties
at the transmissive region and the reflective region are identical.

US Pat. No. 10,073,312

STRUCTURE FOR LCD PANEL

WUHAN CHINA STAR OPTOELEC...

1. A structure for liquid crystal display (LCD) panel, which comprises: in an active area of the LCD panel, a plurality of parallel horizontal gate scan lines, a plurality of parallel vertical data lines, a plurality of sub-pixels arranged in an array form, a plurality of common voltage branch lines disposed horizontally corresponding to sub-pixels of each column, and a first common voltage bus and a second common voltage bus, disposed vertically respectively at two sides of the active area, a zeroth scan line disposed horizontally outside of the active area, and a zeroth common voltage branch disposed horizontally outside of the active area, the first common voltage bus transmitting a first common voltage Vcom1 different from a common voltage Vcom2 transmitted by the second common voltage bus;each sub-pixel comprising: a thin film transistor (TFT), and a storage capacitor and a liquid crystal (LC) capacitor, connected in parallel;
for a positive integer s, the sources of the TFTs of the sub-pixels in the s-th column connected to the s-th data line;
for a positive integer n, the n-th gate scan line located above the sub-pixels of the n-th column, the n-th common voltage branch located below the sub-pixels of the n-th column; the gates of the TFTs of sub-pixels of the n-th column connected to the n-th scan line;
for an odd number i, one end of the storage capacitor and the LC capacitor of any sub-pixel in the i-th column connected to the drain of the corresponding TFT, for sub-pixels in the odd-numbered rows of the i-th column, the other end connected to the corresponding i-th common voltage branch, and for sub-pixels in the even-numbered rows of the i-th column, the other end connected to the (i?1)-th common voltage branch; the corresponding i-th common voltage branch connected through a first switch TFT to the first common voltage bus, and the (i?1)-th common voltage branch connected through a second switch TFT to the second common voltage bus; the first switch TFT having the gate connected to the corresponding i-th scan line, the source connected to the second common voltage bus, and the drain connected to corresponding i-th common voltage branch;
for the (i+1)-th column, one end of the storage capacitor and the LC capacitor of any sub-pixel connected to the drain of the corresponding TFT, for sub-pixels in the odd-numbered rows of the (i+1)-th column, the other end connected to the corresponding (i+1)-th common voltage branch, for sub-pixels in the even-numbered rows of the (i+1)-th column, the other end connected to the i-th common voltage branch; the corresponding (i+1)-th common voltage branch connected through a second switch TFT to the second common voltage bus; and
the first switch TFT having the gate connected to the corresponding odd-numbered scan line, the source connected to the first common voltage bus, and the drain connected to corresponding odd-numbered common voltage branch; the second switch TFT having the gate connected to the corresponding even-numbered scan line or the zeroth scan line, the source connected to the second common voltage bus, and the drain connected to corresponding even-numbered common voltage branch or the zeroth common voltage branch.

US Pat. No. 10,031,373

LIQUID CRYSTAL DISPLAY PANEL

Shenzhen China Star Optoe...

1. A liquid crystal display panel, comprising:a first baseplate;
a second baseplate, arranged at a position opposite to the first baseplate and being provided with a pixel electrode and a common electrode thereon; and
an auxiliary spacer, arranged between the first baseplate and the second baseplate and fixed on the first baseplate,
wherein the auxiliary spacer is provided with a top electrode, and the second baseplate is provided with an extending electrode of the common electrode and an extending electrode of the pixel electrode at a position corresponding to the top electrode, so that the top electrode touches the extending electrode of the common electrode and the extending electrode of the pixel electrode and enables the common electrode and the pixel electrode to be connected with each other when the panel is pressed and a distance between the first baseplate and the second baseplate gets smaller.

US Pat. No. 9,922,997

GOA CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A GOA circuit, comprising: GOA units of a plurality of stages which are cascade coupled, and the GOA unit of each stage
comprises: a forward-backward scan control module, a forward-backward scan pull-down control module, a first node control
module, an output module, a second node control module, an output end pull-down module, a voltage stabilizing module and a
capacitor;
n is set to be a positive integer, and except the GOA unit of the first stage, the GOA unit of the second stage, the GOA unit
of the next to last stage and the GOA unit of the last stage, in the GOA unit of the nth stage:

the forward-backward scan control module comprises: a first thin film transistor, and a gate of the first thin film transistor
is electrically coupled to an output end of the two former n?2th stage GOA unit, and a source receives a forward scan control
signal, and a drain is electrically coupled to a first node; and a second thin film transistor, and a gate of the second thin
film transistor is electrically coupled to an output end of the two latter stage n+2th GOA unit, and a source receives a backward
scan control signal, and a drain is electrically coupled to the first node;

the forward-backward scan pull-down control module comprises: a third thin film transistor, and a gate of the third thin film
transistor receives the forward scan control signal, and a source receives a M+1th clock signal, and a drain is electrically
coupled to a gate of an eighth thin film transistor; and a fourth thin film transistor, and a gate of the fourth thin film
transistor receives the backward scan control signal, and a source receives a M?1th clock signal, and a drain is electrically
coupled to the gate of the eighth thin film transistor;

the first node control module comprises: a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically
coupled to a second node, and a source receives a composite signal, and a drain is electrically coupled to the first node;
and an eleventh thin film transistor, and a gate of the eleventh thin film transistor is electrically coupled to the output
end of the two former n?2th stage GOA unit, and a source receives the composite signal, and a drain is electrically coupled
to the second node;

the output module comprises: a tenth thin film transistor, and a gate of the tenth thin film transistor is electrically coupled
to a drain of a seventh thin film transistor, and a source receives a Mth clock signal, and a drain is electrically coupled
to a source of a thirteenth thin film transistor; the thirteenth thin film transistor, and a gate of the thirteenth thin film
transistor receives the Mth clock signal, and a drain is electrically coupled to an output end;

the second node control module comprises: a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically
coupled to the first node, and a source receives the composite signal, and a drain is electrically coupled to the second node;
and the eighth thin film transistor, and the gate of the eighth thin film transistor is electrically coupled to the drain
of the third thin film transistor and the drain of the fourth third thin film transistor, and a source receives a constant
voltage level, and a drain is electrically coupled to the second node;

the output end pull-down module comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically
coupled to the second node, and a source receives the composite signal, and a drain is electrically coupled to the output
end; and a twelfth thin film transistor, and a gate of the twelfth thin film transistor receives a global control signal,
and a source receives the composite signal, and a drain is electrically coupled to the output end;

the voltage stabilizing module comprises: the seventh thin film transistor, and a gate of the seventh thin film transistor
receives the constant voltage level, and a source is electrically coupled to the first node, and a drain is electrically coupled
to the gate of the tenth thin film transistor;

one end of the capacitor is electrically coupled to the second node, and the other end receives the composite signal;
as a panel performs normal display, the voltage levels of the composite signal and the constant voltage level are one high
and one low, and the voltages of the forward scan control signal and the backward scan control signal are one high and one
low, and the global control signal controls the twelfth thin film transistors in all stage GOA units to be deactivated, and
the output end employs the Mth clock signal to be a gate scan driving signal to be outputted; as the panel enters signal interrupt
and performs touch scan, the composite signal is a pulse signal consistent with a touch scan signal, and the voltages of the
forward scan control signal and the backward scan control signal are high or low at the same time, and the Mth clock signal
controls the thirteenth thin film transistor to be deactivated, and the global control signal controls the twelfth thin film
transistors in all stage GOA units to be activated, and the output ends of all stage GOA units outputs the composite signal
consistent with the touch scan signal.

US Pat. No. 9,886,890

DISPLAY DEVICE AND METHOD FOR DISPLAYING AN IMAGE THEREON

SHENZHEN CHINA STAR OPTOE...

1. A display device, wherein the display device comprises:
a display panel, used to display an image according to a first gray scale voltage signal and a first common voltage signal;
a gray scale voltage output circuit, used for outputting the first gray scale voltage signal to the display panel;
a common voltage output circuit, used for outputting the first common voltage signal to the display panel;
a timer, used for calculating a display time of the display panel;
a memory storing a second gray scale voltage value and a second common voltage value; and
a control circuit being used at the predetermined time for controlling the gray scale voltage output circuit and the common
voltage output circuit respectively to output a second gray scale voltage signal and a second common voltage to the display
panel;

wherein the second gray scale voltage signal and the second common voltage signal are supplied to the display panel for displaying
another image, and for causing a blink rate of the displayed image of the display panel to be within a predetermined range;

the control circuit, used for deciding whether the predetermined time arrives or not in accordance with the display time,
when at the predetermined time, controlling the gray scale voltage output circuit and the common voltage output circuit respectively
to output the second gray scale voltage signal and the second common voltage signal to the display panel;

the control circuit, further used for reading the second gray scale voltage value and the second common voltage value from
the memory when at the predetermined time, and according to the second gray scale voltage value and the second common voltage
value, used for controlling the gray scale voltage output circuit and the common voltage output circuit respectively to output
the second gray scale voltage signal and the second common voltage to the display panel;

the gray scale voltage output circuit and the common voltage output circuit both connected to the display panel, and the control
circuit connected with the gray scale voltage output circuit and the common voltage output circuit;

wherein the second gray scale voltage signal corresponds to the second gray scale voltage value, the second common voltage
signal corresponds to the second common voltage value;

wherein the memory stores a set of preset data, the set of preset data includes a time information, the second gray scale
voltage value and the second common voltage value;

the second gray scale voltage value and the second common voltage value both corresponding to the time information;
the control circuit comparing the display time with the time corresponding to the time information, and according to the comparison,
reads the second gray scale voltage value and the second common voltage value from the memory when at the predetermined time,
and according to the second gray scale voltage value and the second common voltage value, and controls the gray scale voltage
output circuit and the common voltage output circuit respectively to output the second gay scale voltage signal and the second
common voltage to the display panel.

US Pat. No. 9,835,917

BASEPLATE CIRCUIT AND DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. A baseplate circuit, disposed in a baseplate, the baseplate circuit comprising:
an IC (Integrated Chip) region;
a plurality of WOA (Wire On Array) regions, each of the WOA regions comprising a plurality of baseplate conducting wires,
each of the baseplate conducting, wires being electrically connected with the IC region;

a plurality of GOA (Gate On Array) regions, each of the GOA regions comprising a plurality of gate lines, each of the gate
lines being electrically connected with one of the baseplate conducting wires;

a plurality of switches, each of the switches being used to directly electrically connect one of the gate lines and one of
the baseplate conducting wires;

an active region, being used to connect with the GOA regions, the active region comprising a plurality of pixel units, the
pixel units being connected with the GOA regions and a plurality of data lines of the IC region;

a FPC (Flexible Printed Circuit) region, being used to connect with an external assembly module; and
an external connecting region, being used to accommodate the data lines, being used to connect the active region and the IC
region;

wherein the IC region outputs a control signal used to selectively switch on/off the switches, the IC region further outputs
a testing signal used to pass through the WOA regions and the GOA regions or the WOA regions only, according to the control
signal, the baseplate is a glass baseplate.

US Pat. No. 9,817,290

TFT SUBSTRATE AND DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A TFT substrate, wherein the TFT substrate comprises a plurality of mutually parallel scan lines, a plurality of mutually
parallel data lines and a common electrode covering on the scan lines and data lines, wherein:
the multiple data lines and the multiple scan lines are disposed in a stagger to form a plurality of regions, each region
being a pixel unit;

the common electrode comprises a plurality of common electrode units and a plurality of bridging portions overlapping with
the scan lines and the data lines, wherein the common electrode unit and the pixel unit are correspondingly disposed, each
bridging portion is connected with at least two adjacent common electrodes in order to make all of the common electrodes be
electrically connected;

wherein the bridging portion is a conductive film, which is plated on the position corresponded to the scan lines and the
data lines.

US Pat. No. 9,818,359

SCANNING-DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE HAVING THE SAME

Shenzhen China Star Optoe...

1. A scanning-driving circuit, wherein the scanning-driving circuit comprises:
a forward-backward scanning module to output a forward scanning-driving signal and a backward scanning-driving signal to drive
the scanning-driving circuit;

a pull-up holding module connected to the forward-backward scanning module to receive a selecting signal outputted from the
forward-backward scanning module and to pull up a voltage level of a pull-down control signal node according to the received
selecting signal;

an input module connected to the forward-backward scanning module and the pull-up holding module to receive a previous-stage
clock signal and to charge a pull-up control signal node according to the received previous-stage clock signal;

a control module connected to the pull-up holding module to receive a present-stage clock signal and to control the pull-up
holding module according the received the present-stage clock signal;

an output module connected to the pull-up holding module and the control module to output a scanning-driving signal to a scanning
line; and the scanning line transmitting the scanning-driving signal to a pixel unit;

wherein the scanning-driving circuit further comprises a pull-up auxiliary module to prevent the input module from leaking
electricity during charging the pull-up control signal node of the output module.

US Pat. No. 9,799,286

GOA CIRCUITS AND LIQUID CRYSTAL DEVICES

Shenzhen China Star Optoe...

1. A gate driver on array (GOA) circuit, comprising:
a plurality of cascaded GOA units, each of the GOA units being driven by a first level of transfer clock, a second level of
transfer clock, a first control clock and a second control clock to charge horizontal signal lines corresponding to a display
area, the first level of transfer clock and the second level of transfer clock configured to control an input of level signals
of the GOA units and to generate gate driving signals, the first control clock and the second control clock configured to
control the gate driving signals to be at a predetermined level, wherein the level signals are turn-on pulse signals or the
gate driving signals between the adjacent GOA units; and

a control module configured to mask the first level of transfer clock and the second level of transfer clock when all of the
horizontal signal lines being charged completely by the GOA circuit, the gate driving signals on the horizontal signal lines
controlled by the first control clock and the second control clock being discharged until the level of the gate driving signals
equals to the predetermined level, such that the horizontal signal lines being prevented from generating redundant pulse signals
before the first gate driving signals are outputted,

wherein the control module comprises a first control module and a second control module,
wherein the GOA circuit receives first clock signals, second clock signals, third clock signals, and fourth clock signals,
and the first clock signals, the second clock signals, the third clock signals, and the fourth clock signals are respectively
valid within one operating period in turn;

the GOA circuit comprising a first GOA sub-circuit being formed by the cascaded GOA units at odd levels, when being driven
by the first level of transfer clock, the second level of transfer clock, the first control signals, and the second control
signals, the first GOA sub-circuit charges the horizontal signal lines at odd levels;

within the first GOA sub-circuit, the first level of transfer clock and the second level of transfer clock corresponding to
the first clock signals and the third clock signals, and the first control signals and the second control signals corresponding
to the second clock signals and the fourth clock signals,

wherein the first control module corresponds to the first GOA sub-circuit, the first control module is configured to mask
the first clock signals and the third clock signals of the first GOA sub-circuit such that the gate driving signals on the
horizontal signal lines at odd levels being discharged until the level equals to the predetermined level when being controlled
by the second clock signals and the fourth clock signals,

wherein the GOA circuit further comprises a second GOA sub-circuit being formed by the cascaded GOA units at even levels,
when being driven by the first level of transfer clock, the second level of transfer clock, the first control signals, and
the second control signals, the second GOA sub-circuit charges the horizontal signal lines at even levels;

within the second GOA sub-circuit, the first level of transfer clock and the second level of transfer clock correspond to
the second clock signals and the fourth clock signals, and the first control signals and the second control signals correspond
to the first clock signals and the third clock signals; and the second control module corresponds to the second GOA sub-circuit,
the second control module is configured to mask the second clock signals and the fourth clock signals of the first GOA sub-circuit
such that the gate driving signals on the horizontal signal lines at even levels being discharged until the level equals to
the predetermined level when being controlled by the first clock signals and the third clock signals.

US Pat. No. 10,115,923

DISPLAY PANEL WITH LUMINESCENT MATERIAL BLOCKS

SHENZHEN CHINA STAR OPTOE...

1. A display panel comprising:at least a display unit, the display unit being divided into a first region, a second region, a third region, a fourth region, and a fifth region, wherein the display unit comprises:
an anode layer comprising:
a first anode provided in the first region;
a second anode provided in the second region;
a third anode provided in the third region;
a fourth anode provided in the fourth region; and
a fifth anode provided in the fifth region;
a hole injection layer;
a hole transport layer;
a luminescent material layer including:
a first light-emitting section located in the first region, the first light-emitting section being formed solely by a portion located in the first region of a first luminescent material block;
a second light-emitting section located in the second region, the second light light-emitting section being formed by stacking a portion located in the second region of the first luminescent material block and a portion located in the second region of a second luminescent material block;
a third light-emitting section located in the third region, the third light-emitting section being a portion located in the third region of the second luminescent material block;
a fourth light-emitting section located in the fourth region, the fourth light-emitting section being formed by stacking a portion located in the fourth region of the second luminescent material block and a portion located in the fourth region of a third luminescent material block; and
a fifth light-emitting section located in the fifth region, the fifth light-emitting section being a portion located in the fifth region of the third luminescent material block;
an electron transporting layer;
an electron injection layer; and
a cathode layer;
the display unit further comprising a switching component, which includes
a first switch thin film transistor (TFT) connected to the first anode;
a second switch TFT connected to the second anode;
a third switch TFT connected to the third anode;
a fourth switch TFT connected to the fourth anode; and
a fifth switch TFT connected to the fifth anode;
wherein the first luminescent material block is located in the first region and second region, the second luminescent material is located in the second region, the third region, and the fourth region, as well as the third luminescent material is located in the fourth region and the fifth region.

US Pat. No. 9,995,955

PRESSURE TOUCH LIQUID CRYSTAL DISPLAY PANEL AND MANUFACTURE METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

5. A pressure touch liquid crystal display panel, comprising:A liquid crystal panel;
a top polarizer, disposed on an upper surface of the liquid crystal panel, and used for filtering a polarized light setting a polarized state;
a touch screen, disposed on an upper surface of the top polarizer, and used for receiving a touch signal;
a force sensing layer, disposed on a lower surface of the liquid crystal panel, and used as a first substrate of a force sensing capacitor;
a bottom polarizer, disposed on a lower surface of the force sensing layer, and used for filtering a polarized light setting a polarized state;
a backlight, disposed on a lower surface of the bottom polarizer, and used for providing a display light source; and
an iron frame, disposed outside the backlight, and used as a second substrate of the force sensing capacitor, wherein a gap is set between the iron frame and the backlight.

US Pat. No. 9,835,784

ILLUMINATING DEVICE COMPRISING QUANTUM DOT TUBE, BACKLIGHT MODULE, AND LCD

Wuhan China Star Optoelec...

1. A backlight module, comprising:
an illuminating device comprising a quantum dot tube, comprising a transparent tubular encapsulation device and a quantum
dot encapsulated in the transparent tubular encapsulation device, the transparent tubular encapsulation device comprising
a light incident surface and a light emergent surface, and a plurality of bumps and a plurality of grooves being disposed
on one surface of the light incident surface at intervals;

a plurality of light emitting diodes (LEDs), each of the plurality of LEDs being arranged in the groove arranged between any
two of the adjacent bumps in the light incident surface of the illuminating device tube;

a light guide plate, comprising a light incident side, the light incident side of the light guide plate and the light emergent
surface of the illuminating device tube arranged opposite to each other;

wherein a plurality of bumps and a plurality of grooves are disposed on one surface of the light emergent surface at intervals;
a plurality of protrusions and a plurality of recesses are disposed on the light incident side of the light guide plate, and
each of the plurality of protrusions disposed on the light incident side of the light guide plate is disposed on the groove
arranged between any two of the adjacent bumps on the light emergent surface of the illuminating device tube;

the shape of the groove in the light incident surface of the illuminating device matches the shape of the accommodated LED.

US Pat. No. 10,141,351

ARRAY SUBSTRATE, DISPLAY DEVICE AND MANUFACTURING METHOD FOR ARRAY SUBSTRATE

Wuhan China Star Optoelec...

1. An array substrate, comprising:a substrate adopting an organic material;
an isolation layer adopting a metal material selected only from one of a titanium material, an aluminum material, a copper material and a nickel material, and the isolation layer is directly formed on the substrate;
a buffering layer directly formed at a side of the isolation layer away from the substrate;
wherein the buffering layer includes an oxide material and/or a nitride material;
wherein, the array substrate further includes multiple thin-film transistors, the multiple thin-film transistors are formed at a side of the buffering layer back to the isolation layer;
wherein each of the multiple thin-film transistors includes a low-temperature polysilicon layer, a gate insulation layer, a gate electrode, a dielectric layer, a source region, a drain region and a planarization layer;
wherein the low-temperature polysilicon layer is directly formed on the buffering layer; and
wherein the gate insulation layer directly covers the low-temperature polysilicon layer and the buffering layer.

US Pat. No. 10,088,723

PIXEL STRUCTURE, ARRAY SUBSTRATE AND DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A pixel structure of an in-cell touch panel, comprising scan lines, data lines and pixel areas, and the scan lines are separately arranged in parallel along a horizontal direction, and the data lines are separately arranged in parallel along a vertical direction, and the scan lines and the data lines overlap with each other to form the pixel areas, wherein the pixel structure further comprises a connection electrode employed to coupled to pixel areas for sensing touches to the pixel areas, and the connection electrode comprises a first connection layer and a second connection layer, and the first connection layer is in the same pattern layer with the scan lines and intersects with the scan lines, and the first connection layer at an intersecting position with the scan line is disconnected, and the second connection layer is in the same pattern layer with the data lines and crosses with the scan lines, and two sides of the first connection layer at the intersecting position with the scan line are electrically coupled to the second connection layer through a first via hole.

US Pat. No. 9,946,394

GATE DRIVERS AND THE TOUCH PANELS HAVING THE GATE DRIVERS

Shenzhen China Star Optoe...

1. A gate driver, comprising:a plurality of gate driver units, each of the gate driver units comprising a gate driver on array (GOA) driving circuit and at least one buffer GOA driving circuits at multiple levels;
the GOA driving circuit outputting output signals during a display stage, wherein the output signals are transmitted to gate lines and the buffer GOA driving circuits at multiple levels; and
the output signals are transmitted between the levels when the buffer GOA driving circuits at the multiple levels are during a touch stage, and the output signals are transmitted to the GOA driving circuit of the driving unit at the next level;
wherein the GOA driving circuit comprises:
a level transfer device configured for receiving the output signals outputted from the previous level and second clock signals, and for outputting first control signals in accordance with the output signals outputted from the previous level and the second clock signals, wherein the GOA driving circuit of the driving unit at the first level receives default initial signals and the second clock signals;
an output device configured for receiving the first control signals and the first clock signals, outputting the output signals in accordance with the first control signals and the first clock signals, wherein the first clock signals and the second clock signals are opposite to each other;
a pull-down device configured for receiving the first control signals and low level signals, and for stopping the output device from outputting in accordance with the first control signals and the low level signals; and
a pull-down maintaining device configured for receiving high level signals, the low level signals, and the second clock signals, and for outputting pull-down control signals in accordance with the high level signals, the low level signals and the second clock signals, and wherein the pull-down control signals controls the pull-down device to stop the output of the output device;
wherein the level transfer device further comprises a first transistor, a control end of the first transistor receives the second clock signals, an input end of the first transistor receives the output signals of the previous level, and an output end of the first transistor outputs the first control signals;
wherein the output device comprises a second transistor and a third transistor, a control end of the second transistor connects to the output end of the first transistor, an input end of the second transistor receives the first clock signals, and an output end of the second transistor outputs the output signals; and
a control end of the third transistor connects to the output end of the first transistor, an input end of the third transistor receives the first clock signals, and an output end of the third transistor outputs the output signals;
wherein the pull-down device comprises a fourth transistor and a fifth transistor, a control end of the fourth transistor receives the pull-down control signals, an input end of the fourth transistor connects to the output end of the third transistor, and the output end of the fourth transistor receives the low level signals; and
a control end of the fifth transistor receives the pull-down control signals, an input end of the fifth transistor connects to the output end of the first transistor, and the output end of the fifth transistor receives the low-level signals;
wherein the pull-down maintaining device comprises a sixth transistor, a seventh transistor, an eighth transistor and a capacitor;
wherein a control end of the sixth transistor connects to the output end of the first transistor, an input end of the sixth transistor connects to the control end of the fifth transistor, and the output end of the sixth transistor receives the low level signals;
a control end of the seventh transistor connects to an input end of the eighth transistor, an input end of the seventh transistor receives the high level signals, and an output end of the seventh transistor connects to the control end of the fifth transistor;
a control end of the eighth transistor connects to the output end of the first transistor, and an output end of the eighth transistor receives the low level signals; and
one end of the capacitor receives the second clock signals, and the other end of the capacitor connects to the input end of the eighth transistor.

US Pat. No. 9,886,927

DISPLAY DEVICE, TFT SUBSTRATE AND GOA DRIVING CIRCUIT

Shenzhen China Star Optoe...

1. A Gate-On-Array (GOA) driving circuit including multiple staged driving units, and each driving unit comprises:
an input module for receiving a touch control signal, a low voltage level signal, a high voltage level signal and an output
signal of a previous stage driving unit, and for outputting a first control signal according to the signals received, wherein,
the input module of the first stage driving unit receives the touch control signal, the low voltage level signal, the high
voltage level signal and a preset starting signal;

an output module for receiving the first control signal and a first clock signal, and for outputting a first output control
signal according to the first control signal and the first clock signal;

a pull-down module for receiving the first control signal, a second clock signal and the low voltage level signal, and for
outputting a pull-down signal according to the first control signal, the second clock signal and the low voltage level signal,
the second clock signal and the first clock signal are opposite in phase; and

a pull-down maintaining module for receiving the pull-down signal, the high voltage level signal and the first clock signal,
and for outputting a second output control signal according to the pull-down signal, the high voltage level signal and the
first clock signal, wherein, the first output control signal and the second output control signal act commonly in order to
obtain an output signal.

US Pat. No. 10,120,482

DRIVING METHOD FOR IN-CELL TYPE TOUCH DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. A driving method for in-cell type touch display panel, which comprises:Step 1: providing an in-cell type touch display panel, the in-cell type touch display panel using a GOA circuit for gate scan driving, the GOA circuit comprising a plurality of cascade GOA units, the GOA unit of each stage inputting a clock signal, an inverted clock signal, and a constant voltage, and outputting a scan driver signal to the GOA unit of corresponding stage; the first stage GOA unit inputting a scan activation signal;
Step 2: for natural numbers m and n, during displaying an m-th frame, setting a touch scan signal to turn on when an n-th stage GOA unit finishing outputting the scan driver signal, the in-cell type touch display panel transiting from a display duration into a touch signal sensing duration; and
Step 3: during displaying an (m+1)-th frame, setting a touch scan signal to turn on when a GOA unit of any stage other than the n-th stage finishing outputting the scan driver signal, the in-cell type touch display panel transiting from a display duration into a touch signal sensing duration;
wherein each GOA unit of each stage comprises a plurality of N-type TFTs;
wherein the constant voltage is a constant negative voltage, the touch scan signal turns on when transiting from low level to high level, the scan activation signal comprises a single high level pulse, the clock signal and the inverted clock signal comprises a plurality of high level pulses during the display duration of each frame, and pulled down to low level during the touch signal sensing duration of each frame;
wherein the n-th stage GOA unit comprises: a pre-charged control module, a pull-down control module, a first TFT, a second TFT, a third TFT, and a capacitor;
the pre-charged control module having an input end connected to input the scan driver signal of the previous stage ((n?1)-th stage) GOA unit, an output end connected to a first node; the gate of the first TFT connected to an output end of the pull-down control module, the source connected to the first node, and the drain connected to the scan driver signal of the n-th stage GOA unit; the gate of the second TFT connected to the first node, the drain connected to the scan driver signal of the n-th stage GOA unit; the gate of the third TFT connected to the gate of the first TFT, the source connected to the constant voltage, and the drain connected to the scan driver signal of the n-th stage GOA unit; one end of the capacitor connected to the first node and the other connected to the scan driver signal of the n-th stage GOA unit; and
for any two GOA units of adjacent stages, one of the two GOA units having the input end of the pull-down control module connected to the clock signal and the source of the second TFT connected to the inverted clock signal, while the other GOA unit having the input end of the pull-down control module connected to the inverted clock signal and the source of the second TFT connected to the clock signal.

US Pat. No. 10,049,638

DEMULTIPLEX TYPE DISPLAY DRIVING CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A demultiplex type display driving circuit, comprising: a plurality of driving units, and each driving unit comprises: twenty-four data lines, which are mutually parallel, sequentially aligned and vertical, at least two scan lines, which are mutually parallel, sequentially aligned and horizontal, sub pixels of at least two rows-twenty-four columns, and forty-eight in total, which are aligned in array, and eight demultiplex modules;each sub pixel is electrically coupled to the scan line corresponded with the row where the sub pixel is and the data line corresponded with the column where the sub pixel is;
each demultiplex module comprises three thin film transistors, and gates of the three thin film transistors are electrically coupled to a first branch control signal, a second branch control signal, and a third branch control signal respectively, and source are all electrically coupled to the same data signal, and drains are electrically coupled to one data line, respectively;
the first demultiplex module comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a first data signal, and a drain is electrically coupled to a first data line; a second thin film transistor, and a gate of the second thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the first data signal, and a drain is electrically coupled to a fourth data line; and a third thin film transistor, and a gate of the third thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a first data signal, and a drain is electrically coupled to a sixth data line;
the second demultiplex module comprises: a fourth thin film transistor, and a gate of the fourth thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a second data signal, and a drain is electrically coupled to a second data line; a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the second data signal, and a drain is electrically coupled to a third data line; and a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a second data signal, and a drain is electrically coupled to a fifth data line;
the third demultiplex module comprises: a seventh thin film transistor, and a gate of the seventh thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a third data signal, and a drain is electrically coupled to a seventh data line; an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the third data signal, and a drain is electrically coupled to a ninth data line; and a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a third data signal, and a drain is electrically coupled to a twelfth data line;
the fourth demultiplex module comprises: a tenth thin film transistor, and a gate of the tenth thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a fourth data signal, and a drain is electrically coupled to an eighth data line; an eleventh thin film transistor, and a gate of the eleventh thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the fourth data signal, and a drain is electrically coupled to a tenth data line; and a twelfth thin film transistor, and a gate of the twelfth thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a fourth data signal, and a drain is electrically coupled to an eleventh data line;
the fifth demultiplex module comprises: a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a fifth data signal, and a drain is electrically coupled to a fourteenth data line; a fourteenth thin film transistor, and a gate of the fourteenth thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the fifth data signal, and a drain is electrically coupled to a fifteenth data line; and a fifteenth thin film transistor, and a gate of the fifteenth thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a fifth data signal, and a drain is electrically coupled to a seventeenth data line;
the sixth demultiplex module comprises: a sixteenth thin film transistor, and a gate of the sixteenth thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a sixth data signal, and a drain is electrically coupled to a thirteenth data line; a seventeenth thin film transistor, and a gate of the seventeenth thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the sixth data signal, and a drain is electrically coupled to a sixteenth data line; and an eighteenth thin film transistor, and a gate of the eighteenth thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a sixth data signal, and a drain is electrically coupled to an eighteenth data line;
the seventh demultiplex module comprises: a nineteenth thin film transistor, and a gate of the nineteenth thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to a seventh data signal, and a drain is electrically coupled to a twelfth data line; a twentieth thin film transistor, and a gate of the twentieth thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the seventh data signal, and a drain is electrically coupled to a twenty-second data line; and an twenty-first thin film transistor, and a gate of the twenty-first thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to a seventh data signal, and a drain is electrically coupled to a twenty-third data line;
the eighth demultiplex module comprises: a twenty-second thin film transistor, and a gate of the twenty-second thin film transistor is electrically coupled to the first branch control signal, and a source is electrically coupled to an eighth data signal, and a drain is electrically coupled to a nineteenth data line; a twenty-third thin film transistor, and a gate of the twenty-third thin film transistor is electrically coupled to the second branch control signal, and a source is electrically coupled to the eighth data signal, and a drain is electrically coupled to a twenty-first data line; and an twenty-fourth thin film transistor, and a gate of the twenty-fourth thin film transistor is electrically coupled to the third branch control signal, and a source is electrically coupled to an eighth data signal, and a drain is electrically coupled to a twenty-fourth data line;
polarities of two adjacent data signals are opposite;
wherein the sub pixels comprise: red sub pixels, green sub pixels, blue sub pixels and white sub pixels; and one red sub pixel, one green sub pixel, one blue sub pixel and one white sub pixel commonly construct one display pixel;
wherein the polarities of the sub pixels of the same column are the same; in the display pixels of the same row, the polarities of sub pixels of the same color in the display pixels of two adjacent columns are different; in the display pixels of the same column, the polarities of sub pixels of the same color in the display pixels of two adjacent rows are different; and
wherein in the display pixels of the first row, the green sub pixel, the blue sub pixel, the red sub pixel and the white sub pixel are sequentially aligned; in the display pixels of the second row, the red sub pixel, the white sub pixel, the green sub pixel and the blue sub pixel are sequentially aligned; in the display pixels of the third row, the green sub pixel, the red sub pixel, the blue sub pixel and the white sub pixel are sequentially aligned; in the display pixels of the fourth row, the blue sub pixel, the white sub pixel, the green sub pixel and the red sub pixel are sequentially aligned.

US Pat. No. 9,841,832

SELF-CAPACITIVE TOUCH PANEL STRUCTURE, IN-CELL TOUCH PANEL, AND LIQUID CRYSTAL DISPLAY

Shenzhen China Star Optoe...

1. A self-capacitive touch panel structure, comprising:
a touch detection chip; and
multiple self-capacitance electrodes arranged as a matrix and isolated from each other, each self-capacitance electrode connected
with the touch detection chip through a connection line, each self-capacitance electrode electrically connected with a corresponding
connection line through at least one via hole;

wherein, a group of connection lines connected with a same column of the multiple self-capacitance electrodes are divided
into an odd number group and an even number group, the odd number group comprises only odd-numbered connection lines of the
group of connection lines, the even number group comprises only even-numbered connection lines of the group of connection
lines, the connection lines in the odd number group are sequentially connected with respective self-capacitance electrode
of the same column of the self-capacitance electrodes, and the connection lines in the even number group are sequentially
connected with respective self-capacitance electrode of the same column of the self-capacitance electrodes; and

wherein, the touch detection chip is located at a bottom side of the multiple self-capacitance electrodes, each column of
the multiple self-capacitance electrodes includes a 1st to a Mth self-capacitance electrodes from a bottom to a top, the group
of connection lines connected with the same column of the multiple self-capacitance electrodes includes a 1st to a Mth connection
lines from a left to a right, wherein, a 1st, a 3rd, a 5th . . . connection lines of the odd number group are sequentially
connected with a 1st, a 2nd, a 3rd . . . self-capacitance electrodes in the same column; a 2nd, a 4th, a 6th . . . connection
lines of the even number group are sequentially connected with a Mth, a (M?1)th, a (M?2)th . . . self-capacitance electrodes
in the same column.

US Pat. No. 9,805,682

SCANNING DRIVING CIRCUITS AND THE LIQUID CRYSTAL DEVICES WITH THE SAME

Shenzhen China Star Optoe...

1. A scanning driving circuit, comprising:
a plurality of cascaded scanning driving units, each of the scanning driving units comprising:
an input module outputting low level signals in accordance with received first clock signals, downstream signals at upper
level, and downstream signals at current level; and

a plurality of driving circuits, each of the driving circuits driving a corresponding scanning line, each of the driving circuits
comprising:

a control module connecting with the input module for receiving the low level signals outputted by the input module, and outputting
control signals in accordance with the low level signals, second clock signals, and reset signals;

an output module connecting with the control module for receiving the control signals outputted from the control module, and
the output module is turned on or off in accordance with the control signals;

a pull down module connects with the control module and the output module, the pull down module receives the control signals
from the control module and is turned on or off in accordance with the control signals;

at least one scanning line connected with the output module and the pull down module for outputting scanning driving signals
at high level or at low level to pixel cells; and

when the output module is turned off, the pull down module is turned on, and the scanning line outputs the scanning driving
signals at low level to the pixel cells, when the output module is turned on, the pull down module is turned off, and the
scanning line outputs the scanning driving signals at high level to the pixel cell

wherein the input module comprises ten controllable switches comprising a first, a second, a third, a fourth, a fifth, a sixth,
a seventh, an eighth, a ninth, and a tenth controllable switches, a control end of the first controllable switch connects
with the first clock signals, an input end of the first controllable switch connects with a high level end, an output end
of the first controllable switch connects with an output end of the second controllable switch, a control end of the second
controllable switch connects with the first clock signals and the control end of the first controllable switch, an input end
of the second controllable switch connects a low level end, a control end of the third controllable switch connects with the
downstream signals at current level, an input end of the third controllable switch connects with the low level end, and an
output end of the third controllable switch connects with an input end of the fourth controllable switch, a control end of
the fourth controllable switch connects with the output end of the first controllable switch, an output end of the fourth
controllable switch connects with an output end of the fifth controllable switch, and a control end of the fifth controllable
switch connects with the downstream signals at upper level, an input end of the fifth controllable switch connects with an
output end of the sixth controllable switch, a control end of the sixth controllable switch connects with the output end of
the first controllable switch, an input end of the sixth controllable switch connects with the high level end, an input end
of the seventh controllable switch connects with the input end of the sixth controllable switch and the high level end, a
control end of the seventh controllable switch connects with the first clock signals, and an output end of the seventh controllable
switch connects with an input end of the eighth controllable switch, a control end of the eighth controllable switch connects
with the downstream signals at current level, an output end of the eighth controllable switch connects with an output end
of the ninth controllable switch, a control end of the ninth controllable switch connects with the first clock signals, an
input end of the ninth controllable switch connects with an output end of the tenth controllable switch, a control end of
the tenth controllable switch connects with the downstream signals at upper level, an input end of the tenth controllable
switch connects with the low level end, the output ends of the fourth controllable switch and the ninth controllable switch
are connected to operate as the output end of the input module, and the output end of the input module connects with each
of the driving circuits;

wherein each of the driving circuits comprises the eleventh, the twelfth, and the thirteen controllable switches, a control
end of the eleventh controllable switch connects with the second clock signals, an input end of the eleventh controllable
switch connects with the output end of the input module, and an output end of the eleventh controllable switch connects with
output ends of the twelfth controllable switch and the thirteenth controllable switch, input ends of the twelfth controllable
switch and the thirteenth controllable switch connect with the high level end, a control end of the twelfth controllable switch
connects with third clock signals, a control end of the thirteenth controllable switch connects with the reset signals, and
the output ends of the twelfth controllable switch and the thirteenth controllable switch are connected to operate as the
output end of the control module, and the output end of the control module connects with the output module and the pull down
module;

wherein each of the driving circuits comprises a fourteenth, a fifteenth, a sixteenth, and a seventeenth controllable switches,
a control end of the fourteenth controllable switch connects with control ends of the fifteenth controllable switch and the
control module, an input end of the fourteenth controllable switch connects with the high level end, an output end of the
fourteenth controllable switch connects with an output end of the fifteenth controllable switch, an input end of the fifteenth
controllable switch connects with the low level end, a control end of the sixteenth controllable switch connects with the
output end of the fourteenth controllable switch, an input end of the sixteenth controllable switch connects with an input
end of the seventeenth controllable switch and fourth clock signals, an output end of the sixteenth controllable switch connects
with the scanning line corresponding to the driving circuit and an output end of the seventeenth controllable switch, a control
end of the seventeenth controllable switch connects with the output end of the control module and the pull down module.

US Pat. No. 9,798,065

LIGHT GUIDE PLATE AND BACKLIGHT MODULE USING THE LIGHT GUIDE PLATE

Shenzhen China Star Optoe...

1. A light guide plate comprising a light-emitting surface, wherein a plurality of V-shaped grooves is formed on the light-emitting
surface; each of the V-shaped grooves extends along a curved path, wherein the curved path is arc-shaped; the light emitting
surface comprises a light source near part and a light source far part; the V-shaped grooves are arranged one by one from
the light source near part of the light emitting surface to the light source far part of the light emitting surface and the
light source near part of the light emitting surface is arranged at the concave side of the curved path of each V-shaped groove,
wherein the distance between two adjacent V-shaped grooves decreases gradually from the light source near part of the light-emitting
surface to the light source far part of the light-emitting surface; and
wherein the curved path of the first V-shaped groove comprises at least two arc segments connecting successively from the
light source near part of the light emitting surface to the light source far part of the light emitting surface.

US Pat. No. 10,089,916

FLAT PANEL DISPLAY DEVICE AND SCAN DRIVING CIRCUIT THEREOF

Wuhan China Star Optoelec...

1. A scan driving circuit, wherein the scan driving circuit comprises a plurality of cascaded scan drivers, each of the scan drivers comprising:a forward/backward scanning circuit, configured to receive a first scanning control signal, a second scanning control signal, a driving signal and a scanning signal on a next stage, as well as outputting a forward/backward control signal, the forward/backward control signal configured to control the scan drivers to scan forward or backward;
an output circuit, connected with the forward/backward scanning circuit, configured to receive a first clock signal, a second clock signal, a third clock signal, a fourth clock signal as well as receiving the forward/backward control signal from the forward/backward scanning circuit and outputting a first scanning signal, a second scanning signal and a third scanning signal;
a pull-down circuit, connected with the output circuit, configured to pull-up charge or pull-down discharge a first node;
a pull-down control circuit, connected with the pull-down circuit, configured to receive the first clock signal and a first voltage reference, configured to control the first node, for pull-down controlling the first scanning signal, the second scanning signal and the third scanning signal,
wherein the output circuit comprises a first output circuit, a second output circuit and a third output circuit, the first output circuit outputs the first scanning signal according to the forward/backward control signal, the first clock signal and the second clock signal; the second output circuit outputs the second scanning signal according to the second clock signal, the third clock signal and the first scanning signal; the third output circuit outputs the third scanning signal according to the third clock signal, the fourth clock signal and the second scanning signal,
wherein the forward/backward scanning circuit comprises a first controllable switch and a second controllable switch, a control terminal of the first controllable switch receives the first scanning control signal, a first terminal of the first controllable switch receives the driving signal, a second terminal of the first controllable switch and a second terminal of the second controllable switch are connected with the output circuit, a control terminal of the second controllable switch receives the second scanning control signal, a first terminal of the second controllable switch receives the scanning signal on the next stage,
wherein the first output circuit comprises a third controllable switch, a fourth controllable switch, a fifth controllable switch and a first capacitor, a control terminal of the third controllable switch receives the first clock signal, a first terminal of the third controllable switch is connected with a second terminal of the second controllable switch and a second terminal of the first controllable switch, a second terminal of the third controllable switch is connected with a first terminal of the fourth controllable switch, a control terminal of the fourth controllable switch receives the first voltage reference, a second terminal of the fourth controllable switch is connected with a first terminal of the first capacitor and a control terminal of the fifth controllable switch, a first terminal of the fifth controllable switch receives the second clock signal, a second terminal of the fifth controllable switch is connected with a second terminal of the first capacitor, and outputting the first scanning signal;
the second output circuit comprises a sixth controllable switch, a seventh controllable switch, an eighth controllable switch and a second capacitor, a first terminal of the sixth controllable switch connected with a second terminal of the first capacitor and a second terminal of the fifth controllable switch, a control terminal of the sixth controllable switch receives the second clock signal, a second terminal of the sixth controllable switch connected with a first terminal of the seventh controllable switch, a control terminal of the seventh controllable switch receives the first voltage reference, a second terminal of the seventh controllable switch connected with a first terminal of the second capacitor and a control terminal of the eighth controllable switch, a first terminal of the eighth controllable switch receives the third clock signal, a second terminal of the eighth controllable switch connected with a second terminal of the second capacitor, and outputting the second scanning signal;
the third output circuit comprises a ninth controllable switch, a tenth controllable switch, an eleventh controllable switch and a third capacitor, a first terminal of the ninth controllable switch connected with a second terminal of the second capacitor, a control terminal of the ninth controllable switch receives the third clock signal, a second terminal of the ninth controllable switch, a first terminal of the tenth controllable switch and a control terminal of the tenth controllable switch receive the first voltage reference, a second terminal of the tenth controllable switch connected with a first terminal of the third capacitor and a control terminal of the eleventh controllable switch, a first terminal of the eleventh controllable switch receives the fourth clock signal, a second terminal of the eleventh controllable switch connected with a second terminal of the third capacitor, and outputting the third scanning signal,
wherein the pull-down circuit comprises a twelfth controllable switch, a thirteenth controllable switch, a fourteenth controllable switch, a fifteenth controllable switch, a sixteenth controllable switch, a seventeenth controllable switch and a fourth capacitor, a control terminal of the twelfth controllable switch, a control terminal of the thirteenth controllable switch, a control terminal of the fourteenth controllable switch, a control terminal of the fifteenth controllable switch, a control terminal of the sixteenth controllable switch, a control terminal of the seventeenth controllable switch, and a first terminal of the fourth capacitor are connected with the pull-down control circuit, a second terminal of the twelfth controllable switch, a second terminal of the thirteenth controllable switch, a second terminal of the fourteenth controllable switch, a second terminal of the fifteenth controllable switch, a second terminal of the sixteenth controllable switch, a second terminal of the seventeenth controllable switch, and a second terminal of the fourth capacitor receive a second voltage reference, a first terminal of the twelfth controllable switch is connected with a second terminal of the third controllable switch, a first terminal of the thirteenth controllable switch is connected with a second terminal of the first capacitor, a first terminal of the fourteenth controllable switch is connected with a second terminal of the sixth controllable switch, a first terminal of the fifteenth controllable switch is connected with a second terminal of the second capacitor, a first terminal of the sixteenth controllable switch is connected with a second terminal of the ninth controllable switch, a first terminal of the seventeenth controllable switch is connected with a second terminal of the third capacitor, and
wherein the pull-down control circuit comprises an eighteenth controllable switch, a nineteenth controllable switch, a twentieth controllable switch and a fifth capacitor, a control terminal of the eighteenth controllable switch and a control terminal of the nineteenth controllable switch are connected with a second terminal of the third controllable switch, a second terminal of the eighteenth controllable switch and a second terminal of the nineteenth controllable switch receive the second voltage reference, a first terminal of the eighteenth controllable switch is connected with a second terminal of the fifth capacitor and a control terminal of the twentieth controllable switch, a first terminal of the fifth capacitor receives the first clock signal, a first terminal of the twentieth controllable switch receives the first voltage reference, a second terminal of the twentieth controllable switch and a first terminal of the nineteenth controllable switch are connected with a control terminal of the twelfth controllable switch.

US Pat. No. 10,048,785

TOUCH DISPLAY DEVICE PROMOTING TOUCH ACCURACY

Shenzhen China Star Optoe...

1. A touch display device promoting touch accuracy, comprising:a sensing layer, an isolation layer and a common electrode layer from top to bottom in sequence, wherein the common electrode layer comprises a plurality of driving regions having with driving region electrodes inside and is arranged in a rectangular array, and a plurality of floating regions having floating region electrodes inside and is located between the driving regions of two adjacent columns, and the two adjacent floating regions are located in space to construct a floating region pair, and isolating regions among the driving regions and the floating regions; floating connection lines are distributed at the sensing layer, and one point of a floating connection line is electrically coupled to the floating region electrode in one floating region in the floating region pair with a first via in the isolation layer, and another point of the floating connection line is electrically coupled to the floating region electrode in other floating region in the floating region pair with a second via in the isolation layer,
wherein the common electrode layer further comprises a driving lead line penetrating the isolating regions between two adjacent floating regions, wherein: the driving region electrodes in the two adjacent driving regions in the same row are electrically coupled with the driving lead line,
wherein the driving region electrode and the floating region electrode are both electrically coupled to a common voltage output end in a driving circuit as the touch display device shows an image; or the driving region electrode is electrically coupled to the common voltage output end in the driving circuit, and the floating region electrode is set null as the touch display device implements touch scanning,
wherein the sensing layer further comprises a plurality of first sensing regions corresponding to the floating regions one by one, and the first sensing region is located right above the floating region corresponded with the first sensing region, and the first sensing region comprises a sensing region electrode,
wherein the sensing region electrode in the first sensing region is one of a metal mesh, a transparent Indium Tin Oxide (ITO) electrode and a carbon nano-tube electrode, and
wherein the sensing layer further comprises a plurality of second sensing regions corresponding to the driving regions one by one, and the second sensing region is located right above the driving region corresponded with the second sensing region, and the second sensing region comprises a sensing region electrode, wherein:the sensing region electrode in the second sensing region is electrically coupled to the driving region electrode in the driving region corresponded with the second sensing region.

US Pat. No. 10,043,991

ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of an array substrate, comprising steps of:forming a buffer layer on a base substrate;
forming a first metal layer on the buffer layer, and patterning the first metal layer to form a gate electrode;
forming a gate insulation layer on the gate electrode and a portion of the base substrate uncovered with the gate electrode;
forming a second metal layer on the gate insulation layer, and patterning the second metal layer to form a drain electrode and a source electrode;
forming a barrier layer on the second metal layer, and patterning the barrier layer to form a gap portion by etching a portion of the barrier layer corresponding to a channel location, wherein a width of one side of the gap portion close to the second metal layer is greater than that of the other side of the gap portion far away from the second metal layer;
depositing an organic semiconductor material on the barrier layer, forming a channel in a region of the organic semiconductor material corresponding to the gap portion, and forming a deposition portion on the barrier layer;
removing the deposition portion and the barrier layer;
forming a second insulation layer on the channel;
forming a conductive through hole in the second insulation layer to connect with the second metal layer; and
forming a transparent conducting layer on the second insulation layer and in the conductive through hole.

US Pat. No. 9,983,434

TRANSFLECTIVE LIQUID CRYSTAL DISPLAY PANEL AND TRANSFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A transflective liquid crystal display panel, comprising:an array substrate which is provided thereon with a plurality of sub-pixel areas, each of the sub-pixel areas comprising a transmissive area and a reflecting area, and
a polarizer arranged at an outer surface of the array substrate and having a first surface facing a backlight source,
wherein an area of the first surface, which corresponds to the reflecting area, is at least partly provided therein with a reflecting layer,
wherein the reflecting layer has a thickness configured to increase gradually along a direction from an end thereof close to the transmissive area to the reflecting area, and
wherein the reflecting layer comprises a transparent film layer arranged on the polarizer, and a metal layer coated on the transparent film layer, the transparent film layer arranged between the polarizer and the metal layer.

US Pat. No. 9,798,411

TOUCH DISPLAY PANEL AND TOUCH DISPLAY DEVICE CAPABLE OF IMPROVING YIELD RATE

SHENZHEN CHINA STAR OPTOE...

1. A touch display panel capable of improving a yield rate, comprising:
a color filter substrate;
an array substrate;
a liquid crystal layer disposed between the color filter substrate and the array substrate;
wherein the array substrate includes:
a thin film transistor array layer having thin film transistors to transmit scan signals and data signals;
a common electrode layer disposed on the thin film transistor array layer, wherein the common electrode layer is used to provide
common signals and receive touch signals, and includes a driving portion, a sensing portion and a common signal portion;

a sensing layer disposed on the common electrode layer, and comprising driving circuits and sensing circuits, wherein the
driving circuits which transmit the same one touch driving signal are connected to each other through the driving portion
of the common electrode layer, and the sensing circuits which receive the same one touch sensing signal are connected to each
other through the sensing portion of the common electrode layer, wherein the sensing layer is formed with the sensing circuits
in a metal-mesh configuration; and

a pixel electrode layer connected to the thin film transistor through a first through-hole, wherein the pixel electrode layer
is disposed on the sensing layer, and the sensing circuits of the sensing layer are disposed right over the common signal
portion;

wherein the thin film transistor array layer, the common electrode layer, the sensing layer and the pixel electrode layer
are separated from each other through a dielectric layer, respectively;

wherein the adjacent driving circuits which transmit the same one touch driving signal are connected to the same one driving
portion of the common electrode layer through a second through-hole; and

wherein the adjacent sensing circuits which receive the same one touch sensing signal are connected to the same one sensing
portion of the common electrode layer through a third through-hole.

US Pat. No. 10,139,674

REFLECTIVE LIQUID CRYSTAL DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

10. A reflective liquid crystal display device, comprising an upper substrate and a lower substrate that are opposite to each other, a liquid crystal layer between the upper and lower substrates, a transparent plastic layer bonded to a surface of the lower substrate that is distant from the liquid crystal layer, and a mirror-reflection layer that is attached by the transparent plastic layer to the lower substrate;wherein the transparent plastic layer comprises a transparent plastic material and transparent particles mixed in the transparent plastic material;
wherein the surface of the lower substrate is a flat surface and the transparent plastic material of the transparent plastic layer is formed as a continuous layer attached to the flat surface of the lower substrate to completely cover the entirety of the flat surface and the transparent particles are mixed in and enclosed by the transparent plastic material and are distributed over the entirety of the flat surface of the lower substrate, wherein the transparent plastic layer is sandwiched between the flat surface of the lower substrate and the mirror-reflection layer and is in direct contact with the flat surface of the lower substrate and the mirror-reflection layer, such that light transmitting through the lower substrate travels through the transparent plastic layer and reflected by the mirror-reflection layer;
wherein the transparent particles and the transparent plastic material have different reflectivity;
wherein the upper substrate is a color filter substrate; and
wherein the lower substrate is a thin-film transistor array substrate.

US Pat. No. 10,108,063

IN-CELL TOUCH LIQUID CRYSTAL PANEL AND ARRAY SUBSTRATE THEREOF

WUHAN CHINA STAR OPTOELEC...

1. An array substrate of an in-cell touch liquid crystal panel, comprising a glass substrate and a first metal layer, a second metal layer, a third metal layer and a common electrode layer that are sequentially formed on the glass substrate and are insulated with each other;a plurality of data lines extending in a first direction being disposed in the first metal layer;
a plurality of scan lines extending in a second direction being disposed in the second metal layer;
a plurality of connection wirings extending in the first direction being disposed in the third metal layer;
the common electrode layer being divided into a plurality of touch control inductive electrodes that are electrically connected to a touch control detection chip through the connection wirings,
wherein a plurality of metal lines extending in the first direction being disposed in the second metal layer between two adjacent scan lines, the metal lines are disposed at positions corresponding to projections of the connection wirings in the second metal layer respectively, the metal lines and the scan lines are insulated with each other, and two ends of each metal line are electrically connected to the connection wiring located right above the meal line respectively; and
wherein, the second direction and the first direction are perpendicular to each other.

US Pat. No. 9,898,978

LIQUID CRYSTAL PANELS AND THE DRIVING CIRCUITS THEREOF

Shenzhen China Star Optoe...

1. A liquid crystal panel, comprising:
a plurality of source driving circuits and a plurality of sub-pixel rows extending along a row direction, each of the sub-pixel
rows comprising a plurality of sub-pixels of different colors and the sub-pixels being arranged periodically along the row
direction, within one scanning frame, polarity of driving voltage of at least one sub-pixel within one arranging period being
opposite to that of other sub-pixels, and the polarity of each of the sub-pixels within the arranging period being the same
with or being opposite to that of the sub-pixels of corresponding color of adjacent arranging period;

each of the source driving circuit comprising at least two output ends respectively connecting to at least two sub-pixels
having the same polarity of driving voltage within the same scanning frame to provide the driving voltage of the same polarity
to the at least two sub-pixels, wherein a number of the output ends of each of the source driving circuits being the same
with the sub-pixels within each of the arranging periods, each of the source driving circuit being configured for obtaining
voltage data corresponding to the sub-pixels within two adjacent arranging periods, wherein the sub-pixels having the same
polarity of driving voltage within the same scanning frame, and the source driving circuit being configured for outputting
via the four output ends, the output ends respectively connecting to the sub-pixels of two adjacent arranging periods, and
wherein the polarity of the driving voltage of sub-pixels in the same scanning frame being the same;

the color of each of the sub-pixels being the same with the corresponding sub-pixel within the adjacent arranging periods;
the liquid crystal panel further comprising four control lines, each of the source driving circuit comprising a data processing
unit, a source IC chip, and four switches; and

the source IC chip comprising: an input end and an output end, the switch comprises: an input end, an output end, and a control
end, the input end of the source IC chip connects to the data processing unit, the output end of the source IC chip connects
to the input end of the four switches, the output ends of the four switches connects to the four output ends of the source
driving circuit, and the control end of the four switches respectively connect to the four control lines.

US Pat. No. 9,805,680

LIQUID CRYSTAL DISPLAY DEVICE AND GATE DRIVING CIRCUIT

Shenzhen China Star Optoe...

1. A gate driving circuit, wherein, the gate driving circuit includes multiple-stage gate driving units and a control chip,
wherein each stage gate driving unit comprises:
a first pulling control circuit for outputting a first pulling control signal at a first node;
a first pulling circuit coupled with the first node, receiving a first clock signal, pulling a voltage level of an output
terminal of a gate driving signal to a first voltage level according to the first pulling control signal and first clock signal
in order to output the gate driving signal;

a second pulling control circuit for outputting a second pulling control signal at a second node;
a second pulling circuit coupled with the first node and the second node, receiving a first voltage reference signal, and
pulling a voltage level of the first node to a second voltage level of the first voltage reference signal according to the
second pulling control signal, and the second pulling circuit pulls a voltage level of the gate driving signal to the second
voltage level;

a first reset circuit coupled with the first node, receiving a reset signal and the first voltage reference signal, pulling
the voltage level of the first node to the second voltage level according to the reset signal; and

a second reset circuit coupled with the second node, receiving the reset signal and a second voltage reference signal, pulling
a voltage level of the second node to a third voltage level of the second voltage reference signal according to the reset
signal;

wherein, control chip is used for pulling the first clock signal and the first voltage reference signal to the first voltage
level such that scanning lines driven by the gate driving circuit are all turned on;

wherein, the first pulling control circuit includes a first thin-film transistor and a second thin-film transistor;
a first terminal of the first thin-film transistor receives a first signal, a second terminal of the first thin-film transistor
receives a gate driving signal of a previous stage, and a third terminal of the first thin-film transistor is connected with
the first node; and

a first terminal of the second thin-film transistor receives a second signal; a second terminal of the second thin-film transistor
receives a gate driving signal of a next stage, and a third terminal of the second thin-film transistor is connected with
the first node;

wherein, the first pulling circuit includes a third thin-film transistor and a first capacitor, a first terminal of the third
thin-film transistor receives the first clock signal, a second terminal of the third thin-film transistor is connected with
the first node, a third terminal of the third thin-film transistor is the output terminal of the gate driving signal, and
the first capacitor is connected between the second terminal and the third terminal of the third thin-film transistor;

wherein, the first reset circuit includes a fourth thin-film transistor, a first terminal of the fourth thin-film transistor
is connected with the first node, a second terminal of the fourth thin-film transistor receives the reset signal, and a third
terminal of the thin-film transistor receives the first voltage reference signal;

wherein, the second reset circuit includes a fifth thin-film transistor, a first terminal of the fifth thin-film transistor
receives the second voltage reference signal, a second terminal of the fifth thin-film transistor receives the reset signal,
and a third terminal of the fifth thin-film transistor is connected with the second node;

wherein, the second pulling control circuit includes a sixth thin-film transistor and a seventh thin-film transistor, a first
terminal of the sixth thin-film transistor receives the second clock signal, a second terminal of the sixth thin-film transistor
is connected with the first terminal of the fourth thin-film transistor, a third terminal of the sixth thin-film transistor
is connected with a third terminal of the seventh thin-film transistor and the second node, a first terminal of the seventh
thin-film transistor receives the second voltage reference signal, a second terminal of the seventh thin-film transistor receives
the second clock signal; and

the second pulling circuit includes an eighth thin-film transistor, a ninth thin-film transistor, a tenth thin-film transistor
and a second capacitor, a first terminal of the eighth thin-film transistor is connected with the second terminal of the third
thin-film transistor, a second terminal of the eighth thin-film transistor receives the first clock signal, a third terminal
of the eighth thin-film transistor is connected with a first terminal of the ninth thin-film transistor, a second terminal
of the ninth thin-film transistor is connected with the third terminal of the seventh thin-film transistor, a third terminal
of the ninth thin-film transistor receives the first voltage reference signal, a first terminal of the tenth thin-film transistor
is connected with the third terminal of the thin-film transistor, a second terminal of the tenth thin-film transistor is connected
with the second terminal of the ninth thin-film transistor, a third terminal of the tenth thin-film transistor receives the
first voltage reference signal, the second capacitor is connected between the second terminal and the third terminal of the
tenth thin-film transistor.

US Pat. No. 9,784,981

LIQUID CRYSTAL DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY MODULE THEREOF

Wuhan China Star Optoelec...

1. A liquid crystal display module for realizing a switching between 2D and 3D images, comprising: a backlight unit, a liquid
crystal display unit and a 2D/3D conversion adjustment unit successively stacked and parallel with one another; wherein the
2D/3D conversion adjustment unit comprises a upper glass substrate, a lower glass substrate, and electrodes and a liquid crystal
disposed between the upper substrate and the lower glass substrate; the electrodes comprise a planar electrode and a non-planar
electrode, the planar electrode is attached to the lower glass substrate, the non-planar electrode is attached to the upper
glass substrate, the liquid crystal is disposed between the planar electrode and the non-planar electrode, the liquid crystal
is a positive liquid crystal material, an initial state of the liquid crystal is unoriented and thus is isotropic, a shape
of an end surface of the non-planar electrode comprises continuous arches.

US Pat. No. 9,760,206

SELF-CAPACITIVE TOUCH PANEL STRUCTURE, IN-CELL TOUCH PANEL, AND LIQUID CRYSTAL DISPLAY

Shenzhen China Star Optoe...

1. A self-capacitive touch panel structure, comprising:
a touch detection chip; and
multiple self-capacitance electrodes which are isolated with each other and arranged as a matrix, each self-capacitance electrode
is connected with the touch detection chip through a connection line, each self-capacitance electrode is connected with a
corresponding connection line through at least one via hole;

wherein, a same column of the multiple self-capacitance electrodes is divided into multiple groups including a first group
and a second group according to a sequence of gradually far away from the touch detection chip, each of the first group and
the second group includes two self-capacitance electrodes, each cross-sectional area of the two connection lines respectively
connected with the two self-capacitance electrodes in the second group is larger than each cross-sectional area of the two
connection lines respectively connected with the two self-capacitance electrodes in the first group, the cross-sectional areas
of the two connection lines connected with the self-capacitance electrodes of the first group are the same, and the cross-sectional
areas of the two connection lines connected with the self-capacitance electrodes of the second group are the same.

US Pat. No. 9,722,094

TFT, ARRAY SUBSTRATE AND METHOD OF FORMING THE SAME

Shenzhen China Star Optoe...

1. A thin-film transistor (TFT), comprising:
a substrate;
a buffer layer on the substrate;
a patterned polycrystalline silicon (poly-si) layer, disposed on the buffer layer, comprising a heavily doped source and a
heavily doped drain disposed respectively on one of the two outer sides of the patterned poly-si layer, and a channel that
is between the heavily doped source and the heavily doped drain;

an isolation layer covered on the patterned poly-si layer;
a gate layer, disposed on the isolation layer, comprising a first gate area and a second gate area disposed in parallel and
corresponding to the channel;

an insulating layer covered on the gate layer; and
a source/drain pattern layer, disposed on the insulating layer, comprising a source pattern, a drain pattern and a bridge
pattern, with the source pattern electrically connecting the heavily doped source, the drain pattern electrically connecting
the heavily doped drain, and one end of the bridge pattern connecting the first gate area, and the other end of the bridge
pattern connecting the second gate area.

US Pat. No. 10,114,227

LIQUID CRYSTAL LENS AND 3D DISPLAY

Wuhan China Star Optoelec...

1. A liquid crystal lens comprises an upper substrate, a lower substrate, and both a liquid crystal layer and spacers disposed between the upper substrate and the lower substrate; wherein the surfaces of the spacers are coated with a ?/4 phase retardation film.

US Pat. No. 9,910,309

ARRAY SUBSTRATE HAVING A TOUCH FUNCTION AND DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A display device having a touch function, comprising:
a plurality of touch electrodes arranged in an array;
a plurality of pixel electrodes;
a plurality of scan lines; and
a plurality of data lines, wherein the plurality of scan lines and the plurality of data lines intersect with each other to
define a plurality of pixel regions on the display device, each of the pixel electrode is arranged in the corresponding pixel
region and electrically connects to the corresponding scan line and the corresponding data line;

wherein each touch electrode corresponds to at least one pixel electrode; the touch electrodes are formed with a plurality
of opening portions at the overlapping regions between each of the touch electrode and at least one of the scan line and the
data line, along the extending direction of the at least one of the scan line and the data line to reduce the coupling capacitance
between the touch electrode and the at least one of the scan line and the data line;

wherein the width of the opening portion is identical to the width of the at least one of the corresponding scan line and
the corresponding data line.

US Pat. No. 9,847,069

GOA CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A Gate Driver on Array (GOA) circuit, comprising GOA units of a plurality of stages which are cascade coupled, and the
GOA unit of each stage comprises: a control input unit, a voltage stabilizing unit, an output unit, a second node control
unit, a first node pull-down unit, a pull-down holding unit, a global control unit, a stage transfer pull-down unit, a stage
transfer unit and a global control auxiliary unit;
N is set to be a positive integer and except the GOA unit of the first and second stages, in the GOA unit of the Nth stage:
the control input unit comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically
coupled to a M+2th clock signal, and a source is electrically coupled to a stage transfer end of two former stage n?2th GOA
unit, and a drain is electrically coupled to a third node;

the voltage stabilizing unit comprises: a second thin film transistor, and a gate of the second thin film transistor is electrically
coupled to a first constant voltage level, and a source is electrically coupled to the third node, and a drain is electrically
coupled to a first node;

the output unit comprises: a third thin film transistor, and a gate of the third thin film transistor is electrically coupled
to the first node, and a source is electrically coupled to a Mth clock signal, and a drain is electrically coupled to an output
end; and a first capacitor, and one end of the first capacitor is electrically coupled to the first node, and the other end
is electrically coupled to the output end;

the second node control unit comprises: a fourth thin film transistor, and a gate of the fourth thin film transistor is electrically
coupled to the third node, and a source is electrically coupled to the M+2th clock signal, and a drain is electrically coupled
to the second node; and an eighth thin film transistor, and a gate of the eighth thin film transistor is electrically coupled
to the M+2th clock signal, and a source is electrically coupled to the first constant voltage level, and a drain is electrically
coupled to the second node;

the first node pull-down unit comprises: a sixth thin film transistor, and a gate of the sixth thin film transistor is electrically
coupled to the Mth clock signal, and a source is electrically coupled to a drain of a seventh thin film transistor, and a
drain is electrically coupled to the third node; and the seventh thin film transistor, and a gate of the seventh thin film
transistor is electrically coupled to the second node, and a source is electrically coupled to a second constant voltage level;

the pull-down holding unit comprises: a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically
coupled to the second node, and a source is electrically coupled to the second constant voltage level, and a drain is electrically
coupled to the output end; and a second capacitor, and one end of the second capacitor is electrically coupled to the second
node, and the other end is electrically coupled to the second constant voltage level;

the global control unit comprises: an eleventh thin film transistor, and a gate of the eleventh thin film transistor is electrically
coupled to a global control signal, and a source is electrically coupled to the second constant voltage level, and a drain
is electrically coupled to the second node; and a twelfth thin film transistor, and both a gate and a source of the twelfth
thin film transistor are electrically coupled to the global control signal, and a drain is electrically coupled to the output
end;

the stage transfer pull-down unit comprises: a tenth thin film transistor, and a gate of the tenth thin film transistor is
electrically coupled to the second node, and a source is electrically coupled to the second constant voltage level, and a
drain is electrically coupled to the stage transfer end;

the stage transfer comprises: a ninth thin film transistor, and a gate of the ninth thin film transistor is electrically coupled
to the first node, and a source is electrically coupled to the Mth clock signal, and a drain is electrically coupled to the
stage transfer end;

the global control auxiliary unit comprises: a thirteenth thin film transistor, and a gate of the thirteenth thin film transistor
is electrically coupled to the output end, and a source is electrically coupled to a drain of a fourteenth thin film transistor,
and a drain is electrically coupled to the stage transfer end; and the fourteenth thin film transistor, and a gate of the
fourteenth thin film transistor is electrically coupled to the global control signal, and a source is electrically coupled
to the second constant voltage level.

US Pat. No. 9,785,023

ARRAY SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF

SHENZHEN CHINA STAR OPTOE...

5. An array substrate structure, comprising a base plate, a buffer layer formed on the base plate, a semiconductor layer formed
on the buffer layer, a gate insulation layer formed on the buffer layer and the semiconductor layer, an interlayer dielectric
layer formed on the gate insulation layer, a source/drain terminal formed on the interlayer dielectric layer, a planarization
layer formed on the source/drain terminal and the interlayer dielectric layer, a second metal layer formed on the planarization
layer, a first insulation layer formed on the second metal layer and the planarization layer, a common electrode formed on
the first insulation layer, a reduction resistant layer formed on the common electrode and the first insulation layer, a second
insulation layer formed on the reduction resistant layer, and a pixel electrode formed on the second insulation layer;
wherein a first via is formed in the gate insulation layer and the interlayer dielectric layer to correspond to the semiconductor
layer; a second via is formed in the first insulation layer to correspond to the second metal layer; and a third via is formed
in the planarization layer, the first insulation layer, the reduction resistant layer, and the second insulation layer to
correspond to the source/drain terminal; and

the semiconductor layer comprises a source/drain contact zone and the source/drain terminal is set in engagement with the
source/drain contact zone of the semiconductor layer through the first via; the common electrode is set in engagement with
the second metal layer through the second via; and the pixel electrode is set in engagement with the source/drain terminal
through the third via;

wherein the reduction resistant layer comprises a material of composition-variable SiNxOy, x?0, 0?y?2, in which in a direction from the common electrode to the second insulation layer, x gradually increases from
0 and y gradually decreases from 2 to 0;

wherein the first insulation layer and the second insulation layer comprise a material of SiNx, x>0; and

wherein the source/drain contact zone of the semiconductor layer comprises a material of N-type heavily-doped silicon; and
the common electrode and the pixel electrode both comprise a material of indium tin oxide (ITO).

US Pat. No. 9,778,523

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate, wherein the array substrate comprises a substrate base material and a first metal layer, an insulating
layer, a polycrystalline semiconductor layer and a second metal layer formed on the substrate base material, the first metal
layer comprises a spaced first zone and a spaced second zone, the first metal layer of the first zone is a gate electrode
of a TFT of the array substrate, the second metal layer comprises a spaced third zone and a spaced fourth zone, the second
metal layer of the third zone and the second metal layer of the fourth zone are respectively a source electrode and a drain
electrode of the TFT, wherein the polycrystalline semiconductor layer and the first metal layer of the second zone are insulating
overlapped by the sandwiched insulating layer to form a MIS storage capacitor of the array substrate;
wherein the array substrate further comprises a dielectric isolation layer formed between the first metal layer and the second
metal layer, the polycrystalline semiconductor layer is connected with a conductive metal layer of the array substrate, a
first contact hole is formed by the dielectric isolation layer, the first metal layer of the second zone is connected with
the second metal layer of the fourth zone by the first contact hole, thus the MIS storage capacitor is formed in the polycrystalline
semiconductor layer, the first metal layer of the second zone and the insulating layer located between the two.

US Pat. No. 9,741,752

METHOD FOR MANUFACTURING TFT SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A method for manufacturing a thin-film transistor (TFT) substrate, comprising the following steps:
(1) providing a base plate and depositing, in sequence, a buffer layer, a semiconductor layer, an insulation layer, and a
gate metal layer on the base plate;

(2) coating a layer of photoresist material on the gate metal layer and subjecting the layer of photoresist material to patterning
treatment by using a partial transmitting mask so as to form a center-raised-side-recessed photoresist layer, wherein the
photoresist layer comprises a first photoresist segment located at a central portion and second photoresist segments respectively
located at two opposite sides of the first photoresist segment with a thickness of the first photoresist segment being greater
than a thickness of the second photoresist segments;

(3) applying a first etching operation to remove portions of the gate metal layer and the insulation layer that are not covered
by the photoresist layer; and

applying a second etching operation to remove a portion of the semiconductor layer that is not covered by the photoresist
layer to form an active layer;

(4) subjecting the photoresist layer to an ashing operation so as to thin the first photoresist segment and remove the second
photoresist segments;

applying an etching operation to remove portions of the gate metal layer and the insulation layer that are not covered by
the photoresist layer so as to form a gate electrode and a gate insulation layer; and

applying treatment to the active layer, with the photoresist layer, the gate electrode, and the gate insulation layer as a
blocking layer, so as to enhance electrical conductivity of portions of the active layer that are not covered by the gate
electrode and the gate insulation layer to form a source contact zone, a drain contact zone, and a channel zone that is located
between the source contact zone and the drain contact zone;

(5) removing a remaining portion of the photoresist layer and depositing an interlayer dielectric layer on the gate electrode,
the active layer, and the buffer layer and subjecting the interlayer dielectric layer to patterning treatment by using one
mask so as to form, in the interlayer dielectric layer, a first via and a second via respectively corresponding to the source
contact zone and the drain contact zone; and

(6) depositing a source/drain metal layer on the interlayer dielectric layer, subjecting the source/drain metal layer to patterning
treatment by using one mask so as to form a source electrode and a drain electrode, wherein the source electrode and the drain
electrode are respectively in contact engagement with the source contact zone and the drain contact zone of the active layer
through the first via and the second via thereby forming a TFT substrate.

US Pat. No. 9,720,294

LIQUID CRYSTAL PANEL WITH SHORT RESPONSE TIME COMPRISING A LIQUID CRYSTAL HAVING FALLING AND RISING STATES AND DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A liquid crystal panel with short response time, comprising:
a first substrate, a second substrate, a liquid crystal, a first pixel electrode, a first common electrode, a second pixel
electrode, and a second common electrode;

wherein, the first substrate and the second substrate are parallel to each other, the liquid crystal is encapsulated between
the first substrate and the second substrate;

wherein, the first pixel electrode and the first common electrode are respectively provided on the two disparate substrates
and corresponding to each other;

wherein, the second pixel electrode and the second common electrode provided on the first substrate and the second substrate
with an interval, which are projected between the first substrate and the second substrate, and the second pixel electrode
and the second common electrode are insulated from the first pixel electrode and the first common electrode;

wherein, when the liquid crystal is in a rising state, it only applies voltage to the first pixel electrode and the first
common electrode without applying voltage to the second pixel electrode and the second common electrode, so that an electric
field perpendicular to the first substrate is formed between the first pixel electrode and the first common electrode;

when the liquid crystal is in a falling state, it only applies voltage to the second pixel electrode and the second common
electrode without applying voltage to the first pixel electrode and the first common electrode, so that an electric field
parallel to the first substrate is formed between the second pixel electrode and the second common electrode.

US Pat. No. 9,697,761

CONVERSION METHOD AND CONVERSION SYSTEM OF THREE-COLOR DATA TO FOUR-COLOR DATA

Shenzhen China Star Optoe...

1. A conversion method of three-color data to four-color data, comprising steps:
A) converting input RGB data to intermediate RGBW data according to a first predetermined saturation parameter, a second predetermined
saturation parameter and a third predetermined saturation parameter;

B) obtaining a first saturation adjust parameter, a second saturation adjust parameter and a third saturation adjust parameter
according to the intermediate RGBW data and predetermined RGBW data;

C) using the first saturation adjust parameter, the second saturation adjust parameter and the third saturation adjust parameter
to respectively adjust the first predetermined saturation parameter, the second predetermined saturation parameter and the
third predetermined saturation parameter; and

D) using the first predetermined saturation parameter after being adjusted, the second predetermined saturation parameter
after being adjusted and the third predetermined saturation parameter after being adjusted to convert the input RGB data to
output RGBW data.

US Pat. No. 9,671,646

METHOD FOR MANUFACTURING EYE-PROTECTING LIQUID CRYSTAL DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A method for manufacturing an eye-protecting liquid crystal display device, comprising the following steps:
(1) preparing an array substrate, wherein the array substrate comprises a first backing plate; a light-shielding layer located
on the first backing plate; a buffer layer located on the light-shielding layer and the plate; a first poly-silicon section
and a second poly-silicon section located on the buffer layer; a gate insulation layer located on the first poly-silicon section,
the second poly-silicon section, and the buffer layer; a first gate electrode and a second gate electrode located on the gate
insulation layer; an interlayer insulation layer located on the first gate electrode, the second gate electrode, and the gate
insulation layer; a first source electrode, a first drain electrode, a second source electrode, and a second drain electrode
located on the interlayer insulation layer; a first planarization layer located on the first source electrode, the first drain
electrode, the second source electrode, the second drain electrode, and the interlayer insulation layer; a common electrode
located on the first planarization layer; a passivation layer located on the common electrode and the first planarization
layer; and a pixel electrode located on the passivation layer, wherein the first planarization layer comprises an ultraviolet
light emitting material and an ultraviolet absorbent;

(2) preparing a color filter substrate, wherein the color filter substrate comprises a second backing plate; a black matrix
arranged on the second backing plate; a color resist layer arranged on the black matrix and the second backing plate; a second
planarization layer arranged on the color resist layer; and a plurality of photo spacers arranged on the second planarization
layer, wherein the second planarization layer comprises an ultraviolet light emitting material and an ultraviolet absorbent;
and

(3) laminating the array substrate and the color filter substrate to each other and filling liquid crystal molecules between
the array substrate and the color filter substrate, followed by sealing, to form an eye-protecting liquid crystal display
panel; and providing a backlight module and combining the eye-protecting liquid crystal display panel and the backlight module
together to form an eye-protecting liquid crystal display device;

wherein the ultraviolet absorbents contained in the first planarization layer of the array substrate and the second planarization
layer of the color filter substrate absorb short-wavelength blue light having a wavelengths less than 400 nm and ultraviolet
light emitting from the backlight module; and the short-wavelength blue light and the ultraviolet light so absorbed excite
the ultraviolet light emitting materials to give off long-wavelength visible blue light having a wavelength greater than 400
nm, so as to provide a function of eye protection, while avoiding lowering display brightness of the liquid crystal display
panel thereby ensuring the backlighting efficiency and transmittance of the liquid crystal display device;

wherein the ultraviolet light emitting materials comprise an inorganic ultraviolet light emitting material or an organic ultraviolet
light emitting material;

wherein the inorganic ultraviolet light emitting material comprises one of 3Ca3(PO4)2.Ca(F,Cl)2: Sb,Mn, Y2O3:Eu, MgAl11O19:
Ce,Tb, BaMg2Al16O27:Eu, manganese activated magnesium fluogermanate powder, tin activated zincstrontium phosphate powder,
YVO4:Eu, Y(PV)O4:Eu, (BaSi2O3):Pb, (Ca, Zn)3(PO4)2:Tl, Sr2P2O7:Eu, MgGa2O4:Mn, and Zn2SiO4:Mn or a combination of multiple
ones thereof; and

wherein the organic ultraviolet light emitting material comprises one of distyryl-biphenyl disulfonic acid sodium salt, 2,5-bis
(5-tert butyl-2-benzoxazolyl) thiophene, 1-(p-sulfonamidophenyl)-3-(p-chlorophenyl)-2-pyrazoline, and phthalimide or a combination
of multiple ones thereof.

US Pat. No. 9,562,668

LUMINOUS DEVICE COMPRISING A WAVELENGTH CONVERSION UNIT HAVING AN ARC-SHAPED JUNCTION PORTION AND LIQUID CRYSTAL DISPLAY DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A luminous device, comprising:
a base;
a luminous element, disposed on the base, for providing light, and the luminous element comprising a body section, an anode
section, a cathode section, a first luminous side surface, a second luminous side surface, a luminous top surface, and a luminous
bottom surface; and

a wavelength conversion unit, disposed on the luminous element, for converting a wavelength of the light emitting from the
luminous element, the wavelength conversion unit comprising a first wavelength conversion side surface, a second wavelength
conversion side surface, a wavelength conversion top surface, and a wavelength conversion bottom surface,

wherein a difference value between a first distance and a second distance is less than a preset value, wherein the first distance
is a distance between the first luminous side surface and the first wavelength conversion side surface or a distance between
the second luminous side surface and the second wavelength conversion side surface, and the second distance is a distance
between the luminous top surface and the wavelength conversion top surface; and a distance between the first wavelength conversion
side surface and the first luminous side surface is less than a distance between the second wavelength conversion side surface
and the first luminous side surface;

a shape at a junction portion between the first wavelength conversion side surface and the wavelength conversion top surface
is arc-shaped, and a shape at a junction portion between the second wavelength conversion side surface and the wavelength
conversion top surface is arc-shaped; and

a shape at a junction portion between the first luminous side surface and the luminous top surface is arc-shaped, and a shape
at a junction portion between the second luminous side surface and the luminous top surface is arc-shaped.

US Pat. No. 10,089,919

SCANNING DRIVING CIRCUITS

Wuhan China Star Optoelec...

1. A scanning driving circuit, comprising: a plurality of cascaded-connected scanning driving units, and each of the scanning driving unit includes: a forward-backward scanning circuit configured to receive a first scanning control voltage, a second scanning control voltage, driving signals, first clock signals, second clock signals, first scanning driving signals, second scanning driving signals, and down-level scanning driving signals to output forward-backward control signals to control the scanning driving circuit to conduct a forward scanning or a backward scanning;a first input circuit configured to receive third clock signals and to receive the forward-backward control signals from the forward-backward scanning circuit to output first input signals;
a second input circuit configured to receive fourth clock signals and to receive the forward-backward control signals from the forward-backward scanning circuit to output second input signals;
a pull-down circuit configured to receive the forward-backward control signals and the first input signals, to output first pull-down signals, and to pull-down or charge a first pull-down control signal point, or the pull-down circuit is configured to receive the forward-backward control signals and the second input signals, to output second pull-down signals, and to pull-down or charge a second pull-down control signal point;
a first control circuit configured to receive the first input signals from the first input circuit and to charge the first pull-up control signal point in accordance with the first input signals, or is configured to receive the first pull-down signals from the pull-down circuit and to pull down the first pull-up control signal point in accordance with the first pull-down signals;
a second control circuit configured to receive the second input signals from the second input circuit and to charge a second pull-up control signal point in accordance with the second input signals, or is configured to receive the second pull-down signals from the pull-down circuit and to pull down the second pull-up control signal point in accordance with the second pull-down signals;
a first output circuit configured to receive fourth clock signals and to generate first scanning driving signals in accordance with the fourth clock signals, and the first scanning driving signals are outputted to the first scanning line to drive pixel cells; and
a second output circuit configured to receive third clock signals and to generate second scanning driving signals in accordance with the third clock signals, and the second scanning driving signals are outputted to the second scanning line to drive the pixel cells,
wherein the forward-backward scanning circuit comprises a first to sixth controllable transistors, a control end of the first controllable transistor receives the first scanning control voltage, a first end of the first controllable transistor receives the driving signals, a second end of the first controllable transistor connects to a second end of a second controllable transistor and the first input circuit, a first end of the second controllable transistor connects to the second scanning line to receive the second scanning driving signals, a control end of the second controllable transistor connects to a control end of the third controllable transistor and receives the second scanning control voltage, a first end of the third controllable transistor receives the first clock signals, a second end of the third controllable transistor connects to a second end of the fourth controllable transistor and the pull-down circuit, a first end of the fourth controllable transistor receives the second clock signals, a control end of the fourth controllable transistor connects to a control end of the fifth controllable transistor and receives the first scanning control voltage, a first end of the fifth controllable transistor connects to the first scanning line to receive the first scanning driving signals, a second end of the fifth controllable transistor connects to a second end of the sixth controllable transistor and the second input circuit, a first end of the sixth controllable transistor connects to the scanning line at a down level to receive the scanning driving signals from the down level, and a control end of the sixth controllable transistor receives the second scanning control voltage,
wherein the first input circuit comprises a seventh controllable transistor, a control end of the seventh controllable transistor receives the third clock signals, a first end of the seventh controllable transistor connects to the second end of the first controllable transistor and the second end of the second controllable transistor, and a second end of the seventh controllable transistor connects to the pull-down circuit and the first control circuit,
wherein the pull-down circuit comprises eighth to fifteenth controllable transistor, a first capacitor, and a second capacitor, a control end of the eighth controllable transistor connects to the second end of the seventh controllable transistor, a first end of the ninth controllable transistor and the first control circuit, a first end of the eighth controllable transistor receives turn-off voltage end signals, a second end of the eighth controllable transistor connects to a control end of a ninth controllable transistor, a control end of the tenth controllable transistor, a control end of the fourteenth controllable transistor, a control end of the fifteenth controllable transistor, a first end of the thirteenth controllable transistor, a second end of the eleventh controllable transistor, and a first end of the twelfth controllable transistor, a second end of the ninth controllable transistor connects to the first end of the tenth controllable transistor, the second end of the fourteenth controllable transistor, and the first end of the fifteenth controllable transistor to receive the turn-off voltage end signals, the second end of the tenth controllable transistor connects to the control end of the thirteenth controllable transistor, the second input circuit, and the second control circuit, the first end of the eleventh controllable transistor receives turn-on voltage end signals, the control end of the eleventh controllable transistor connects to the control end of the twelfth controllable transistor, the second end of the third controllable transistor, and the second end of the fourth controllable transistor, the second end of the twelfth controllable transistor receives the turn-on voltage end signals, the control end of the thirteenth controllable transistor connects to the second input circuit, the second control circuit, and the second end of the tenth controllable transistor, the second end of the thirteenth controllable transistor receives the turn-off voltage end signals, the first end of the fourteenth controllable transistor connects to the first output circuit, the second end of the fifteenth controllable transistor connects to the second output circuit, the first capacitor connects between the first end and the second end of the eleventh controllable transistor, and the second capacitor connects between the first end and the second end of the twelfth controllable transistor,
wherein the first control circuit comprises a sixteenth controllable transistor, a control end of the sixteenth controllable transistor receives the turn-on voltage end signals, a first end of the sixteenth controllable transistor connects to the second end of the seventh controllable transistor, the control end of the eighth controllable transistor, and the first end of the ninth controllable transistor, a second end of the sixteenth controllable transistor connects to the first output circuit, and
wherein the first output circuit comprises a seventeenth controllable transistor and a third capacitor, a control end of the seventeenth controllable transistor connects to the second end of the sixteenth controllable transistor, a first end of the seventeenth controllable transistor receives fourth clock signals, a second end of the seventeenth controllable transistor connects to the first scanning line and the first end of the fourteenth controllable transistor, and the third capacitor connects between the control end and the second end of the seventeenth controllable transistor.

US Pat. No. 9,985,253

METHOD OF MANUFACTURING LIGHT SCATTERING LAYER AND ORGANIC LIGHT-EMITTING DIODE

WUHAN CHINA STAR OPTOELEC...

1. A method of manufacturing a light scattering layer, comprising:manufacturing a mask on a base, the mask having a plurality of hole structures;
depositing a material having a first refractive index value in the hole structures of the mask;
removing the mask after the material having the first refractive index value is deposited, thereby forming a plurality of raised structures on the base;
depositing a material having a second refractive index value between the plurality of raised structures for forming a planarization layer which is used for covering the plurality of raised structures, thereby manufacturing a scattering layer which is constituted by the plurality of raised structures and the planarization layer on the base, wherein the second refractive index value is greater than the first refractive index value,
wherein the step of manufacturing a mask having a plurality of hole structures on a base comprises:
employing an open mask on the base and manufacturing an aluminum film by the open mask, where a pattern of the aluminum film is the same as a pattern of the open mask by using a vacuum evaporation method or a physical vapor deposition method;
anodizing the aluminum film first time and removing an aluminum oxide formed by oxidation, so as to form the aluminum film having a plurality of notches each having a hexagonal close-packed structure; and
anodizing the aluminum film having the plurality of notches each having a hexagonal close-packed structure second time until aluminum located under the notches is completely oxidized to form the hole structures.

US Pat. No. 9,922,611

GOA CIRCUIT FOR NARROW BORDER LCD PANEL

WUHAN CHINA STAR OPTOELEC...

11. A gate driver on array (GOA) circuit for liquid crystal display (LCD) panel, which comprises: a plurality of cascade GOA
units, with GOA unit each stage comprising: a control input unit, a regulation unit, a control output unit, a pull-down holding
unit, a pull-down unit, a second node control unit, and a first node leakage prevention unit;
for a positive integer n, in the GOA unit of the n-th stage:
the control input unit comprising: a first thin film transistor (TFT), with gate connected to a stage-propagated signal, source
connected to a first constant voltage, and drain connected to a third node;

the regulation unit comprising: a second TFT, with gate connected to the first constant voltage, source connected to the third
node, and drain connected to a first node;

the control output unit comprising: a third TFT, with gate connected to the first node, source connected to an output clock
signal, and drain connected to an output end; and a first capacitor, with one end connected to the first node, and the other
connected to the output end;

the pull-down holding unit comprising: a fifth TFT, with gate connected to a second node, source connected to the output end,
and drain connected to a second constant voltage; and a second capacitor, with one end connected to the second node, and the
other connected to the second constant voltage;

the pull-down unit comprising: a sixth TFT, with gate connected to a fourth node, source connected to the third node, and
drain to a source of a seventh TFT; and a seventh TFT, with gate connected to the second node, and drain connected to the
second constant voltage;

the second node control unit comprising: a fourth TFT, with gate connected to the third node, source connected to the control
clock signal, and drain connected to the second node; and an eighth TFT, with gate connected to the control clock signal,
source connected to the first constant voltage, and drain connected to the second node;

the first node leakage prevention unit comprising: a ninth TFT, with gate and source connected to the output clock signal,
and drain connected to the fourth node; a tenth TFT, with gate connected to the stage-propagated signal, source connected
to the fourth node, and drain connected to the second constant voltage; and a third capacitor, with one end connected to the
fourth node and the other connected to the second constant voltage;

wherein when applied to a display panel with dual-side progressive scanning architecture, a GOA circuit is disposed on both
the left side and the right side of the display panel, the GOA circuit on both sides comprising GOA units of each stage; the
GOA unit of each stage on both sides receiving two clock signals: a first clock signal and a second clock signal; the first
clock signal and the second clock signal having opposite phases;

wherein in the GOA unit of each stage, the first clock signal and the second clock signal alternatingly serve as the output
clock signal and the control clock signal, respectively;

wherein other than the first stage, the stage-propagated signal for the n-th GOA unit is the output signal of the previous
stage GOA unit, ((n?1)-th stage GOA unit); and

the stage-propagated signal for the first stage GOA unit is a circuit start signal.

US Pat. No. 9,897,881

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL

Shenzhen China Star Optoe...

1. A thin film transistor array substrate, wherein the thin film transistor array substrate comprises:
a substrate;
a light shielding layer, located at a middle part on a surface of the substrate;
a buffer layer, covering the light shielding layer;
a Low Temperature Poly-silicon layer, being located on the buffer layer, and corresponding to the light shielding layer;
an isolation layer, covering the Low Temperature Poly-silicon layer, and the isolation layer comprises a through hole, wherein
a width of the through hole is smaller than a width of the light shielding layer;

a metal layer, located on the isolation layer, and the metal layer is connected with the Low Temperature Poly-silicon layer
via the through hole;

wherein the metal layer comprises a data line and a source connected to the data line, and widths at respective positions
of the metal layer are equal, and a part of the source is located close to the data line in accordance with the through hole,
and is connected to the Low Temperature Poly-silicon layer via the through hole.

US Pat. No. 9,869,912

LOW TEMPERATURE POLY-SILICON TFT SUBSTRATE

SHENZHEN CHINA STAR OPTOE...

1. A low temperature poly-silicon (LTPS) thin-film transistor (TFT) substrate, comprising a base plate, a first buffer layer
formed on the base plate, a black matrix formed on the first buffer layer, a second buffer layer formed on the first buffer
layer and the black matrix, a poly-silicon layer formed on the second buffer layer, a gate insulation layer formed on the
poly-silicon layer, a gate electrode formed on the gate insulation layer, an interlayer insulation layer formed on the gate
insulation layer and the gate electrode, a source electrode and a drain electrode formed on the interlayer insulation layer,
a planarization layer formed on the interlayer insulation layer, the source electrode, and the drain electrode, a common electrode
formed on the planarization layer, a passivation layer formed on the common electrode, and a pixel electrode formed on the
passivation layer;
wherein the source electrode, the drain electrode, the gate electrode, and the poly-silicon layer collectively constitute
a TFT device, wherein the black matrix is interposed between the first and second buffer layers at a location where the black
matrix shields an area in which the TFT device is formed to prevent the TFT device from being influenced by light irradiation
and also blocks leaking light of pixels so as to prevent mixture of light colors of the pixels.

US Pat. No. 9,847,500

METHOD FOR MANUFACTURING FLEXIBLE DISPLAY DEVICE AND FLEXIBLE DISPLAY DEVICE SO MANUFACTURED

SHENZHEN CHINA STAR OPTOE...

1. A method for manufacturing a flexible display device, comprising the following steps:
(1) providing a carrier board and depositing a connection layer on the carrier board by plasma enhanced chemical vapor deposition
(PECVD);

(2) forming a flexible base plate on the connection layer, wherein the flexible base plate comprises a soft glass plate and
a thermal isolation layer that is provided on at least one side of the soft glass plate;

(3) forming a blocking layer on the flexible base plate;
(4) forming a display structure unit and a package structure unit that is arranged on the display structure unit on the blocking
layer; and

(5) applying a laser based process to separate the carrier board and the flexible base plate with the connection layer attached
to the flexible base plate so as to obtain a flexible display device, wherein the flexible display device comprises the flexible
base plate, the connection layer that is on a lower surface of the flexible base plate, a blocking layer that is on an upper
surface of the flexible base plate, the display structure unit on the blocking layer, and the package structure unit on the
display structure unit;

wherein the thermal isolation layer is arranged on a side of the soft glass plate that is close to the connection layer.

US Pat. No. 9,841,834

IN-CELL TOUCH LIQUID CRYSTAL PANELS AND THE ARRAY SUBSTRATES THEREOF

Shenzhen China Star Optoe...

11. An in-cell touch liquid crystal panel, comprising:
a TFT array substrate, a color film substrate opposite to the TFT array substrate, and a liquid crystal layer between the
TFT array substrate and the color film substrate, the TFT array substrate comprises:

a glass substrate and at least one TFT, a common electrode layer, and at least one pixel electrode formed on the glass substrate
in turn, a first insulation layer is arranged between the common electrode layer and the TFT, a passivation layer is arranged
between the common electrode layer and the pixel electrode, and the pixel electrode electrically connects with the TFT via
a first through hole;

the common electrode layer comprises a plurality of bar-shaped touch driving electrodes insulated from each other, the touch
driving electrodes extend along a first direction, each of the touch driving electrodes comprises a plurality of suspended
electrodes arranged along the first direction, and the suspended electrodes are insulated from the touch driving electrode;

a second insulation layer and a metal wiring layer are arranged between the common electrode layer and the passivation layer
in sequence, wherein the second insulation layer comprises a second through hole and a plurality of third through holes corresponding
to each of the touch driving electrodes, each of the third through holes corresponds to one of the suspended electrodes within
each of the touch driving electrodes, the metal wiring layer comprises a plurality of driving electrode wirings, a plurality
of suspended electrode wirings, and a plurality of touch sensing electrodes extending along the second direction, and the
driving electrode wirings, the suspended electrode wirings, the touch sensing electrodes are insulated from each other;

the driving electrode wirings correspond to the touch driving electrodes one by one, each of the driving electrode wirings
electrically connects to one of the touch driving electrodes via the second through hole, and each of the suspended electrode
wirings electrically connects to the suspended electrodes arranged along the second direction via the third through hole;
and

wherein the first direction is orthogonal to the second direction.

US Pat. No. 9,841,620

GOA CIRCUIT BASED ON LTPS SEMICONDUCTOR THIN FILM TRANSISTOR

WUHAN CHINA STAR OPTOELEC...

1. A GOA circuit based on LTPS semiconductor thin film transistor, comprising GOA units of a plurality of stages which are
cascade coupled, and the GOA unit of each stage comprises: a scan control unit, a forward scan pull-down unit, a backward
scan pull-down unit and an output unit;
n is set to be a positive integer and except the GOA units of the first, the second, the next to last and the last stages,
in the nth stage GOA unit:

the scan control unit comprises: a first thin film transistor, and a gate of the first thin film transistor is electrically
coupled to an output end of a two former stage n?2th GOA unit, and a source is electrically coupled to a forward scan direct
current control signal, and a drain is electrically coupled to a source of a fourth thin film transistor; and a third thin
film transistor, and a gate of the third thin film transistor is electrically coupled to an output end of a two latter stage
n+2th GOA unit, and a drain is electrically coupled to the source of the fourth thin film transistor, and a source is electrically
coupled to a backward scan direct current control signal; and the fourth thin film transistor, a gate of the fourth thin film
transistor is electrically coupled to a constant high voltage level, and a drain is electrically coupled to a first node;

the forward scan pull-down unit comprises: a fifth thin film transistor, and a gate of the fifth thin film transistor is electrically
coupled to the forward scan direct current control signal, and a source is electrically coupled to the constant high voltage
level, and a drain is electrically coupled to a second node; a sixth thin film transistor, and a gate of the sixth thin film
transistor is electrically coupled to the backward scan direct current control signal, and a drain is electrically coupled
to the second node, and a source is electrically coupled to the constant low voltage level; a thirteenth thin film transistor,
and a gate of the thirteenth thin film transistor is electrically coupled to the first node, and a drain is electrically coupled
to the second node, and a source is electrically coupled to the constant low voltage level; a ninth thin film transistor,
and a gate of the ninth thin film transistor is electrically coupled to the second node, and a source is electrically coupled
to the constant low voltage level, and a drain is electrically coupled to the first node; and a tenth thin film transistor,
a gate of the tenth thin film transistor is electrically coupled to the second node, and a source is electrically coupled
to the constant low voltage level, and a drain is electrically coupled to and output end;

the backward scan pull-down unit comprises: an eighth thin film transistor, and a gate of the eighth thin film transistor
is electrically coupled to the forward scan direct current control signal, and a source is electrically coupled to the constant
low voltage level, and a drain is electrically coupled to a third node; a seventh thin film transistor, and a gate of the
seventh thin film transistor is electrically coupled to the backward scan direct current control signal, and a source is electrically
coupled to the constant high voltage level, and a drain is electrically coupled to the third node; a fourteenth thin film
transistor, and a gate of the fourteenth thin film transistor is electrically coupled to the first node, and a drain is electrically
coupled to the third node, and a source is electrically coupled to the constant low voltage level; an eleventh thin film transistor,
a gate of the eleventh thin film transistor is electrically coupled to the third node, and a source is electrically coupled
to the constant low voltage level, and a drain is electrically coupled to the first node; and a twelfth thin film transistor,
and a gate of the twelfth thin film transistor is electrically coupled to the third node, and a source is electrically coupled
to the constant low voltage level, and a drain is electrically coupled to the output end;

the output unit comprises: a second thin film transistor, and a gate of the second thin film transistor is electrically coupled
to the first node, and a source is electrically coupled to a Mth clock signal, and a drain is electrically coupled to an output
end; and a bootstrap capacitor, and one end of the bootstrap capacitor is electrically coupled to a first node, and the other
end is electrically coupled to the output end;

voltage levels of the forward scan direct current control signal and the backward scan direct current control signal are opposite.

US Pat. No. 9,830,855

FOLDABLE DISPLAY DEVICE AND DRIVE METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A foldable display device, comprising: a flexible substrate (1), a plurality of horizontal scan lines (S1-Sn), which are mutually parallel and in interval on the flexible substrate (1), and a plurality of sub pixels (10) aligned in array on the flexible substrate (1);
wherein one scan line is located corresponding to the sub pixels (10) of each row, and the sub pixels (10) at the same row are electrically coupled to the same scan line;

the flexible substrate (1) comprises: a first display region (100), a first folding region (200), a second display region (300), a second folding region (400) and a third display region (500), which are continuously aligned in sequence along a horizontal direction;

control switch units of one column are respectively located in the first display region (100) and the second display region (300) and located adjacent to the sub pixels (10) of two columns, and each scan line is correspondingly coupled to one of the control switch units, and the control switch
unit activates or deactivates the second display region (300) and the third display region (500) under control of a control signal (En).

US Pat. No. 9,817,516

GATE DRIVER ON ARRAY CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A Gate driver on Array circuit, and the Gate driver on Array circuit comprises: shift register SR circuits of multiple
stages and a signal connection circuit of the shift register SR circuits of multiple stages, and the shift register SR circuit
of each stage comprises: a pre-charge controller, three thin film transistors and a capacitor; wherein,
the SR circuit of each stage further comprises: at least one switch, and a G electrode of the switch is inputted with a touch
panel scan TP SCAN signal, and a S electrode of the switch is coupled to a K output end of the signal connection circuit of
the shift register SR circuits of multiple stages, and a D electrode of the switch is coupled to a scan line gate electrode
signal of the SR circuit; the K output end inputs a K signal, and the K signal is synchronized with a touch panel signal TP
signal;

wherein the signal connection circuit of the shift register SR circuits of multiple stages comprises: an external switch set,
and the external switch set comprises at least two switches;

the at least two switches comprises a first time slot signal CK switch and a second time slot signal XCK switch; wherein both
G electrodes of the CK switch and the XCK switch are inputted with the TP SCAN signals, and both the S electrodes of the CK
switch and the XCK switch are inputted with the K signal, and the D electrodes of the CK switch and the XCK switch are respectively
inputted with CK and XCK.

US Pat. No. 9,817,172

BACKLIGHT MODULE AND LIQUID CRYSTAL DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A backlight module comprising:
a light guide plate;
a frame surrounding the light guide plate; and
a light source assembly arranged between the light incident surface of the light guide plate and the frame, the light source
assembly comprising a substrate, a light emitting body, and a transparent body packaging the light emitting body on the substrate;

wherein the outer surface of the transparent body facing the light emitting body is a light exiting surface, the light exiting
surface having a groove formed thereon facing the light incident surface of the light guide plate;

wherein the transparent body comprises a pair of limiting portions arranged at the two sides of the light exiting surface;
the pair of limiting portions match with the top surface and the bottom surface of the light guide plate to limit the light
incident surface of the light guide plate between the limiting portions.

US Pat. No. 9,817,180

BACKLIGHT MODULE AND LIQUID CRYSTAL DISPLAY

WUHAN CHINA STAR OPTOELEC...

1. A backlight module, comprising an optical film assembly, a light guide plate, a reflector sheet, and the reflective sheet
comprises a hollow display region, a side wall, a reflective region, and the display region is oppositely located to the reflective
region, and the side wall is connected between the display region and the reflective region to form an accommodation space,
and the light guide plate and the optical film assembly stack up together inside the accommodation space, and the light guide
plate is located between the reflective region and the optical film assembly, and the optical film assembly is located between
the light guide plate and the display region, wherein the reflective sheet further comprises a junction part, and the junction
part is at an arbitrary edge position of the reflective sheet, and the reflective sheet is connected with the junction part
with a single-side tape to surround the accommodation space.

US Pat. No. 9,786,700

LOW TEMPERATURE POLY-SILICON (LTPS) THIN FILM TRANSISTORS (TFT) UNITS AND THE MANUFACTURING METHOD THEREOF

Wuhan China Star Optoelec...

1. A manufacturing method of low temperature poly-silicon (LTPS) thin film transistor (TFT) units for liquid crystal modules,
comprising:
forming a SiNx layer on a glass substrate;
forming a SiOx layer and an a-Si layer on the SiNx layer in sequence;
scanning the a-Si layer by laser beams to remove hydrogen within the a-Si layer;
adopting excimer laser to re-crystallization anneal the a-Si layer to form the polysilicon layer;
forming a gate insulation layer on the polysilicon layer;
forming a gate on the gate insulation layer; and
forming a drain insulation layer on the gate, the drain insulation layer comprising one SiOx layer and one SiNx layer arranged
above the SiOx layer, and the SiOx layer being arranged in a rim of the gate.

US Pat. No. 9,786,242

GATE DRIVER ON ARRAY CIRCUIT AND DISPLAY USING THE SAME

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit, comprising:
a plurality of GOA circuit units, coupled in cascade, each of the plurality of GOA circuit units at each stage for outputting
a scanning signal via an output terminal according to a scanning signal output by a GOA circuit unit at previous two stages,
a scanning signal output by a GOA circuit unit at next two stages, a first clock signal, a second clock signal, a third clock
signal, a fourth clock signal, a first enabling signal, and a second enabling signal, wherein the GOA circuit units at every
two stages share a pull-down circuit, and the pull-down circuit comprises:

a first transistor, comprising a gate electrically connected to the first enabling signal, a drain electrically connected
to the first clock signal or the second clock signal;

a second transistor, comprising a gate electrically connected to the second enabling signal, a drain electrically connected
to the second clock signal or the first clock signal; and

a third transistor, comprising a gate electrically connected to a source of the first transistor and a source of the second
transistor, and a drain electrically connected to a first constant voltage;

each of the plurality of GOA circuit units comprising:
an input control module, electrically connected to a controlling node, for controlling a voltage imposed on the controlling
node according to the first enabling signal, the second enabling signal, the scanning signal output by the GOA circuit unit
at previous two stages, and the scanning signal output by the GOA circuit unit at next two stages;

an output control module, electrically connected to the controlling node, for outputting the scanning signal according to
the voltage imposed on the controlling node; and

a pull-down holding module, electrically connected to the input control module and the output control module, for holding
the scanning signal at low voltage level.

US Pat. No. 9,778,773

METHOD AND DEVICE FOR DECREASING LEAKAGE CURRENT OF IN-CELL TOUCH LIQUID CRYSTAL PANEL

Shenzhen China Star Optoe...

1. A method for decreasing a leakage current of an in-cell touch liquid crystal panel, wherein the panel comprises a pixel
array and a scan line and a data line connected to each pixel in the pixel array, the method comprising:
during a time period of scanning a touch signal, and according to a voltage detected on the data line connected to the pixel
and a signal input to a common electrode of the pixel, outputting a signal indicating the voltage has been adjusted through
the data line so as to decrease a drain source voltage of a thin film transistor in the pixel,

wherein the thin film transistor is a P type transistor or a N type transistor, and
during the time period of scanning the touch signal, and when the voltage on the date line is in a positive half period and
the signal input to the common electrode of the pixel for scanning the touch signal has transformed from a low pulse signal
to a high pulse signal, outputting a signal through the data line indicating that the voltage has been increased, and

during the time period of scanning the touch signal, and when the voltage on the date line is in a negative half period and
the signal input to the common electrode of the pixel for scanning the touch signal has transformed from the high pulse signal
to the low pulse signal, outputting a signal through the data line indicating that the voltage has been decreased,

wherein a voltage region of the signal after increasing the voltage is:
[Vdata(min)+(Vgh?Vgl)*Cgs/(Clcmin+Cst)] to

[Vdata(max)+(Vgh?Vgl)*Cgs/(Clcmax+Cst)],

wherein a voltage region of the signal after decreasing the voltage is:
[?Vdata(min))?(Vgh?Vgl)*Cgs/(Clcmin+Cst)] to

[?Vdata(max)?(Vgh?Vgl)*Cgs/(Clcmax+Cst)],

wherein, Vdata(min) indicates a minimum voltage on the data line, Vdata(max) indicates a maximum voltage on the data line, Vgh indicates a maximum voltage on the scan line, Vgl indicates a minimum voltage
on the scan line, Cgs indicates a capacitance value of a parasitic capacitor between a gate and a source of the thin film
transistor, Cst indicates a capacitance value of a storage capacitor, Clcmin indicates a minimum capacitance value of a liquid crystal capacitor, and Clcmax indicates a maximum capacitance value of the liquid crystal capacitor.

US Pat. No. 9,779,684

GATE DRIVER ON ARRAY CIRCUIT AND DISPLAY USING THE SAME

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit, comprising:
a plurality of GOA circuit units coupled in series, each GOA circuit unit for outputting a scanning signal at an output terminal
according to a scanning signal output by a GOA circuit unit at a previous stage, a scanning signal output by a GOA circuit
unit at a next stage, a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first gate
turn-on signal, and a second gate turn-on signal, wherein each GOA circuit unit comprises:

an input control module, for outputting a controlling signal at a controlling node according to the first clock signal, the
third clock signal, and the first gate turn-on signal, comprising:

a first transistor, comprising a gate electrically connected to the first clock signal, a drain electrically connected to
the scanning signal output by the GOA circuit unit at the previous stage;

a second transistor, comprising a gate electrically connected to the first gate turn-on signal, a drain electrically connected
to a source of the first transistor, and a source electrically connected to the controlling node;

a third transistor, comprising a gate electrically connected to the first gate turn-on signal, and a drain electrically connected
to a source of the second transistor; and

a fourth transistor, comprising a gate electrically connected to the third clock signal, a drain electrically connected to
a source of the third transistor, and a source electrically connected to the scanning signal output by the GOA circuit unit
at the next stage;

an output control module, electrically connected to the controlling node, for outputting the scanning signal at the output
terminal according to the controlling signal and the second clock signal;

a pull-down module, electrically connected to the output control module, for pulling the scanning signal down to be at low
level; and

a pull-up holding module, electrically connected to the output terminal and the second gate turn-on signal, for keeping the
scanning signal output by the output terminal at high level when receiving the second gate turn-on signal.

US Pat. No. 9,746,717

CURVED LIQUID CRYSTAL DISPLAY MODULE AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME

Wuhan China Star Optoelec...

1. A curved liquid crystal display module, comprising:
a color filter substrate;
an array substrate; and
multiple isolation-cushion parts disposed between the color filter substrate and the array substrate;
wherein, the multiple isolation-cushion parts are densely distributed near a center position of the color filter substrate
and the array substrate, and the multiple isolation-cushion parts are gradually sparsely distributed toward two edges of the
color filter substrate and the array substrate;

wherein, the multiple isolation-cushion parts are different in shape; and
wherein, the multiple isolation-cushion parts located at the center position of the color filter substrate and the array substrate
are strip-shaped, and the multiple isolation-cushion parts located at the two edges are dotted.

US Pat. No. 9,746,726

LIQUID CRYSTAL DISPLAY, A METHOD IMPROVING THE RESPONSE TIME THEREOF, AND AN ARRAY SUBSTRATE

Wuhan China Star Optoelec...

1. An array substrate, comprising a substrate and multiple pixel units provided in the array on the substrate; each said pixel
unit comprising a first pixel electrode and a second pixel electrode spaced from each other provided along a first direction,
a third pixel electrode and a fourth pixel electrode spaced from each other provided along a second direction, and a common
electrode and a first insulating layer provided on the substrate in sequence;
wherein, the first pixel electrode, the second pixel electrode, the third pixel electrode, and the fourth pixel electrode
are located at the side of the first insulating layer away from the common electrode;

wherein, the first pixel electrode and the second pixel electrode are used to generate a first horizontal electric field to
control liquid crystal molecules deflected from an initial direction to a predetermined angle, the third pixel electrode and
the fourth pixel electrode are used to generate a second horizontal electric field to control liquid crystal molecules deflected
from the predetermined angle to the initial direction.

US Pat. No. 9,747,851

COMPENSATION METHOD OF MURA PHENOMENON

SHENZHEN CHINA STAR OPTOE...

10. A compensation method of Mura phenomenon, comprising steps of:
step 1, providing a LCD display panel, and the LCD display panel is divided into a plurality of display partitions arranged in array,
and both M, N are integers larger than 1, and each display partition comprises M rows, N columns pixel dots, and a border
position of the LCD display panel having less than M×N pixel dots is considered to be a border display partition;

step 2, selecting k gray scales including a 0 gray scale and a maximum gray scale, and k is an integer, and the 0 to the maximum
gray scales are divided into (k?1) gray scale sections; selecting a pre-selected pixel dot of a determined position of mth
row, nth column in each display partition comprising M rows, N columns pixel dots, wherein 1?m?M, 1?n?N, and obtaining gray
scale compensation data of the pre-selected pixel dot at k gray scales;

step 3, calculating a first horizontal interpolation coefficient A1, a second horizontal interpolation coefficient A2, a first vertical interpolation coefficient B1, a second vertical interpolation coefficient B2, a first gray scale interpolation coefficient C1 and a second gray scale interpolation coefficient C2 of a requested pixel dot in a corresponding display partition;

step 4, employing a formula (1) to calculate a gray scale compensation data d of a gray scale of the requested pixel dot in a non-border
display partition according to gray scale compensation data of four pre-selected pixel dots around and closest to a position
of the requested pixel dot:

d=C1×(B1×(d1×A1+d2×A2)+B2×(d3×A1+d4×A2))+C2×(B1×(d5×A1+d6×A2)+B2×(d7×A1+d8×A2))   (1)

wherein d1 and d5 are gray scale compensation data of two border gray scales in the gray scale section of the gray scale of the request pixel
dot, in which the pre-selected pixel dot of a top left corner of a rectangle constructed by the four pre-selected pixel dots
around and closest to the position of the requested pixel dot is, and d2 and d6 are gray scale compensation data of two border gray scales in the gray scale section of the gray scale of the request pixel
dot, in which the pre-selected pixel dot of a top right corner of a rectangle constructed by the four pre-selected pixel dots
around and closest to the position of the requested pixel dot is, and d3 and d7 are gray scale compensation data of two border gray scales in the gray scale section of the gray scale of the request pixel
dot, in which the pre-selected pixel dot of a bottom left corner of a rectangle constructed by the four pre-selected pixel
dots around and closest to the position of the requested pixel dot is, and d4 and d8 are gray scale compensation data of two border gray scales in the gray scale section of the gray scale of the request pixel
dot, in which the pre-selected pixel dot of a bottom right corner of a rectangle constructed by the four pre-selected pixel
dots around and closest to the position of the requested pixel dot is;

the compensation method further comprises: step 5, a pixel dot of mth row, nth column or closest to mth row, nth column is selected to be the pre-selected pixel dot in each
border display partition, and with known gray scale compensation data of K gray scales of the pre-selected pixel dots in each
border display partition, the formula (2) is employed to calculate the gray scale compensation data of any gray scales, at
which the pre-selected pixel dot is in each border display partition, and gray scale compensation data of other pixel dots
and the gray scale compensation data of the pre-selected pixel dot in the corresponding border display partition are the same;

d=d1×C1+d2×C2   (2)

wherein d1 is gray scale compensation data of a right border of a gray scale section, in which a requested gray scale of the pre-selected
pixel dot, and d2 is gray scale compensation data of a left border of the gray scale section, in which the requested gray scale of the pre-selected
pixel dot; the first gray scale interpolation coefficient C1 is a ratio of a difference value of the requested gray scale and the right border of the gray scale section and a length
of an entire gray scale section, and the second gray scale interpolation coefficient C2 is a ratio of a difference value of the requested gray scale and the left border of the gray scale section and the length
of the entire gray scale section;

wherein in the step 3:

0?A1?1, 0?A2?1; and A1+A2=1 for the same requested pixel dot; in one display partition comprising M rows, N columns pixel dots, for starting from a
column where the pre-selected pixel dot is in the display partition to the right in sequence, and reaching a right border
of the display partition and turning to a left border, and keeping to the right until reaching a column adjacent to the column
where the pre-selected pixel dot is at the left side in sequence, the first horizontal gray scale interpolation coefficients
A1 of the requested pixel dots of respective columns sequentially are N/N, N?1/N, . . . , 1/N, and the second horizontal gray
scale interpolation coefficients A2 sequentially are 0/N, 1/N, . . . , N?1/N;

0?B1?1, 0?B2?1; and B1+B2=1 for the same requested pixel dot; in one display partition comprising M rows, N columns pixel dots, for starting from a
row where the pre-selected pixel dot is in the display partition to the bottom in sequence, and reaching a bottom border of
the display partition and turning to a top border, and keeping to the bottom until reaching a row adjacent to the column where
the pre-selected pixel dot is at the top side in sequence, the first vertical interpolation coefficient B1 of the requested pixel dots of respective rows sequentially are M/M, M?1/M, . . . , 1/M, and the second vertical interpolation
coefficient B2 sequentially are 0/M, 1/M, . . . , M?1/M;

according to comparison of the grays scale compensation data of the requested pixel dot and the known K gray scales, the gray
scale section of the gray scale of the request pixel dot is obtained; 0?C1?1, 0?C2?1; and C1+C2=1 for the same requested pixel dot; the first gray scale interpolation coefficient C1 is a ratio of a difference value of the gray scale of the requested pixel dot and the right border of the gray scale section
and a length of an entire gray scale section, and the second gray scale interpolation coefficient C2 is a ratio of a difference value of the gray scale of the requested pixel dot and the left border of the gray scale section
and the length of the entire gray scale section;

wherein in the step 4, the four pre-selected pixel dots around and closest to the position of the requested pixel dot respectively are the pre-selected
pixel dot in the display partition where the requested pixel is, the pre-selected pixel dot in the display partition at the
right and adjacent to the display partition where the requested pixel is, the pre-selected pixel dot in the display partition
at the bottom and adjacent to the display partition where the requested pixel is and the pre-selected pixel dot in the display
partition at the bottom right corner and adjacent to the display partition where the requested pixel is.

US Pat. No. 9,766,510

PIXEL UNIT AND ARRAY SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A pixel unit, comprising a pixel zone that comprises two long edges opposite to each other and two short edges respectively
connected to the two long edges, a pixel electrode arranged at a center of the pixel zone, a data line arranged alone one
of the long edges of the pixel zone, and a gate line perpendicular to the data line and extending through the pixel electrode;
the pixel electrode comprising a connection section located at a center thereof and four branch sections extending from the
connection section to a perimeter of the pixel zone, the four branch sections being symmetric, in a top-bottom direction and
a left-right direction, with respect to straight lines that extend through the connection section and are respectively parallel
to the long edges and the short edges of the pixel zone, the branch sections each starting from the connection section, then
extending in a direction, which is parallel to the long edges of the pixel zone, toward the short edges of the pixel zone,
and further extending toward the long edges of the pixel zone at a location close to the short edges of the pixel zone, wherein
each of the branch sections comprises an electrode strip that is of a closed form having a starting point and an ending point
both coincident with the connection section.

US Pat. No. 9,761,194

CMOS GOA CIRCUIT

SHENZHEN CHINA STAR OPTOE...

1. A CMOS Gate Driver on Array (GOA) circuit, comprising a plurality of GOA unit circuits, which are cascade connected as
multiple sequentially-arranged stages;
wherein N is set to be positive integer, and the GOA unit circuit of an Nth one of the multiple stages comprises: an input
control module, a latch module electrically coupled to the input control module, a signal process module electrically coupled
to the latch module, an output buffer module electrically coupled to the signal process module and a storage capacitor electrically
coupled to the latch module and the signal process module;

the input control module receives a stage transfer signal of the GOA unit circuit of an N?1th stage, which is one of the multiple
stages that is immediately previous of the Nth stage, a first clock signal, a global signal, a constant high voltage level
signal and a constant low voltage level signal; the input control module comprises a first NOR gate and a second NOR gate;
a first input end of the first NOR gate receives the stage transfer signal of the GOA unit circuit of the N?1th stage, and
a second end receives the global signal, and an output end outputs a NOR Logic process result of the stage transfer signal
of the GOA unit circuit of the N?1th stage and the global signal; a first input end of the second NOR gate receives the first
clock signal, and a second end receives the global signal, and an output end uses a NOR Logic process result of the first
clock signal and the global signal to be a first inverted clock signal to be outputted; the input control module inverts the
NOR Logic process result of the stage transfer signal of the GOA unit circuit of the N?1th stage and the global signal to
obtain an inverted stage transfer signal, and inputs the inverted stage transfer signal into the latch module;

the latch module comprises a first inverter, and input end of the first inverter is inputted with the inverted stage transfer
signal, output end outputs the stage transfer signal; the latch module latches the stage transfer signal;

the signal process module receives the stage transfer signal, a second clock signal, the constant high voltage level signal,
the constant low voltage level signal and the global signal, and is employed to implement NAND logic process to the second
clock signal and the stage transfer signal to generate a scan driving signal of the GOA unit circuit of the Nth stage; implements
NOR Logic process to the global signal with a result of implementing AND logic process to the second clock signal and the
stage transfer signal to realize that the global signal controls all the scan driving signals of respective stages raised
up to high voltage levels simultaneously;

the output buffer module comprises a plurality of second inverters which are sequentially coupled in series, which are employed
to output the scan driving signal and to increase a driving ability of the scan driving signal;

one end of the storage capacitor is electrically coupled to a node between the latch module and the signal process module,
and the other end is grounded, and employed to store a voltage level of the stage transfer signal;

the global signal comprises a single pulse, and as the single pulse is high voltage level, all the scan driving signals of
the respective stages are controlled to be raised up to high voltage levels at same time, and meanwhile, both the first NOR
gate and the second NOR gate outputs low voltage levels to control the inverted stage transfer signal to be high voltage level,
and the first inverter in the latch module is employed to pull down voltage levels of the stage transfer signals of the respective
stages to clear and reset the stage transfer signals of the respective stages;

wherein the input control module further comprises a first P-type thin film transistor (TFT), a second P-type TFT, a third
N-type TFT and a fourth N-type TFT, which are sequentially coupled in series; a gate of the first P-type TFT receives the
first inverted clock signal, and a source receives the constant high voltage level signal; both gates of the second P-type
TFT and the third N-type TFT are coupled to the output end of the first NOR gate; the drains of the second P-type TFT and
the third N-type TFT are coupled to each other and output inverted stage transfer signal; a gate of the fourth N-type TFT
receives the first clock signal, and a source receives the constant low voltage level signal;

the latch module further comprises a fifth P-type TFT, a sixth P-type TFT, a seventh N-type TFT and an eighth N-type TFT,
which are sequentially coupled in series; a gate of the fifth P-type TFT receives the first clock signal, and a source receives
the constant high voltage level signal; both gates of the sixth P-type TFT and the seventh N-type TFT receives the stage transfer
signal; the drains of the sixth P-type TFT and the seventh N-type TFT are coupled to each other and electrically coupled to
the drains of the second P-type TFT and the third N-type TFT; a gate of the eighth N-type TFT receives the first inverted
clock signal, and a source receives the constant low voltage level signal;

the signal process module further comprises: a ninth P-type TFT, and a gate of the ninth P-type TFT receives the global signal,
and a source receives the constant high voltage level signal; a tenth P-type TFT, and a gate of the tenth P-type TFT receives
the stage transfer signal, and a source is electrically coupled to the drain of the ninth P-type TFT, and a drain is electrically
coupled to a node; an eleventh P-type TFT, and a gate of the eleventh P-type TFT receives the second clock signal, and a source
is electrically coupled to the drain of the ninth P-type TFT, and a drain is electrically coupled to the node; a twelfth N-type
TFT, and a gate of the twelfth N-type TFT receives the stage transfer signal, and a drain is electrically coupled to the node;
a thirteenth N-type TFT, and a gate of the thirteenth N-type TFT receives the second clock signal, and a drain is electrically
coupled to the source of the twelfth N-type TFT, and a source receives the constant low voltage level signal; a fourteenth
N-type TFT, and a gate of the fourteenth N-type TFT receives the global signal, and a source receives the constant low voltage
level signal, and a drain is electrically coupled to the node.

US Pat. No. 9,756,325

NOISE DETECTION DEVICE OF DISPLAY MODULE AND NOISE DETECTION METHOD

WUHAN CHINA STAR OPTOELEC...

1. A noise detection device of a display module, comprising:
a digital data storage,
a processor, and
an encoder;
the digital data storage is used to store parallel video data, the processor is used to transmit the stored parallel video
data to the encoder, the encoder is used to convert the stored parallel video data into serial video data through encoding
and to transmit the converted serial video data to a timing controller of a display module;

the processor is used to receive mini-LVDS data generated by the timing controller based on the converted serial data, and
to convert the mini-LVDS data into the parallel video data; the processor is used to compare the stored parallel video data
with the converted parallel video data, and to determine whether the display module is qualified for noise control according
to the comparison result.

US Pat. No. 9,716,116

TFT ARRAY SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A thin-film transistor (TFT) array substrate, comprising a backing plate, a buffer layer formed on the backing plate, a
plurality of TFTs formed on the buffer layer and arranged in an array, a planarization layer formed on the TFTs, a common
electrode formed on the planarization layer, a protection layer formed on the common electrode, and a patterned pixel electrode
formed on the protection layer;
the TFTs each comprising a poly-silicon semiconductor layer formed on the buffer layer, a gate insulation layer set on and
covering the poly-silicon semiconductor layer, a gate electrode formed on the gate insulation layer and located above the
poly-silicon semiconductor layer, an interlayer insulation layer set on and covering the gate electrode and the gate insulation
layer, and a source electrode and a drain electrode formed on the interlayer insulation layer;

the pixel electrode being electrically connected to the drain electrode;
the drain electrode overlapping a portion of a horizontal projection of the common electrode;
the drain electrode and the common electrode constituting a first storage capacitor, the pixel electrode and the common electrode
constituting a second storage capacitor, the first storage capacitor and the second storage capacitor being connected in parallel
to form a storage capacitor;

wherein the drain electrode, the common electrode, and the pixel electrode are arranged such that the drain electrode and
the pixel electrode are respectively on two opposite sides of common electrode, where the drain electrode faces a first one
of the two opposite sides of the common electrode to collectively form the first storage capacitor and the pixel electrode
faces a second one of the two opposite sides of the common electrode to collectively form the second storage capacitor.

US Pat. No. 9,607,543

DRIVING CIRCUIT

Wuhan China Star Optoelec...

1. A driving circuit, comprising:
at least two driving units arranged in an array and coupled with each other, a first driving unit of the at least two driving
units utilized to receive at least one second sub signal of a second driving signal set which is generated by a second driving
unit, and to generate a first driving signal set, wherein the second driving unit is a driving unit except the first driving
unit in the at least two the driving units;

wherein the driving unit comprises:
a control unit utilized to control an output of a stage transmission signal according to forward and reverse scanning signals;
a stage transmission signal latch unit utilized to receive the stage transmission signal and to latch the stage transmission
signal for generating a latch signal;

a first scanning signal generation unit utilized to generate a first scanning signal;
a second scanning signal generation unit utilized to generate a second scanning signal;
a first inverted output unit utilized to invert the first scanning signal and generate an inverted first scanning signal;
and

a second inverted output unit utilized to invert the second scanning signal generate an inverted second scanning signal;
the control unit comprising a first stage transmission signal input terminal, a second stage transmission signal input terminal,
a first switch control signal input terminal, a second switch control signal input terminal, and a first stage transmission
signal output terminal;

the control unit further comprising:
a first TFT comprising a first gate, a first source, and a first drain, the first gate coupled to the first switch control
signal input terminal, the first source coupled to the first stage transmission signal input terminal, the first drain coupled
to the first stage transmission signal output terminal, the first TFT utilized to control an output of a first stage transmission
signal of the first stage transmission signal input terminal according to a first switch control signal provided by the first
switch control signal input terminal;

a second TFT comprising a second gate, a second source, and a second drain, the second gate coupled to the first switch control
signal input terminal, the second source coupled to the second stage transmission signal input terminal, the second drain
coupled to the first stage transmission signal output terminal, the second TFT utilized to control an output of a second stage
transmission signal of the second stage transmission signal input terminal according to the first switch control signal;

a third TFT comprising a third gate, a third source, and a third drain, the third gate coupled to the second switch control
signal input terminal, the third source coupled to the first stage transmission signal input terminal, the third drain coupled
to the first stage transmission signal output terminal, the third TFT utilized to control the output of the first stage transmission
signal according to a second switch control signal provided by the second switch control signal input terminal; and

a fourth TFT comprising a fourth gate, a fourth source, and a fourth drain, the fourth gate coupled to the second switch control
signal input terminal, the fourth source coupled to the second stage transmission signal input terminal, the fourth drain
coupled to the first stage transmission signal output terminal, the fourth TFT utilized to control the output of the second
stage transmission signal according to the second switch control signal;

the stage transmission signal latch unit comprising a first clock signal input terminal, a third stage transmission signal
input terminal, and a latch signal output terminal;

the stage transmission signal latch unit further comprising:
a first inverter comprising a first inverted input terminal and a first inverted output terminal, the first inverted input
terminal coupled to the first clock signal input terminal, the first inverted input terminal utilized to receive a first clock
signal;

a second inverter comprising a second inverted input terminal and a second inverted output terminal, the second inverted input
terminal coupled to the first inverted output terminal, the second inverter further coupled to the third stage transmission
signal input terminal and the latch signal output terminal;

a third inverter comprising a third inverted input terminal and a third inverted output terminal, the third inverted input
terminal coupled to the first clock signal input terminal, the third inverter further coupled to the third stage transmission
signal input terminal and the latch signal output terminal, the third inverted input terminal utilized to receive the first
clock signal; and

a fourth inverter comprising a fourth inverted input terminal and a fourth inverted output terminal, the fourth inverted input
terminal coupled to the third inverted output terminal and the second inverted output terminal, the fourth inverted output
terminal coupled to the latch signal output terminal.

US Pat. No. 10,192,933

ORGANIC LIGHT EMITTING DEVICE AND METHOD FOR MANUFACTURING THE SAME

Wuhan China Star Optoelec...

1. A manufacturing method of organic light emitting device, wherein steps hereof comprising:manufacturing a bottom electrode on a base substrate;
manufacturing an organic electro-emitting assembly on the bottom electrode by evaporation techniques and lithography techniques, including
evaporating a hole injection layer on the bottom electrode;
manufacturing hole transport layers corresponding respectively to varies color lights emitted from emitting layers on the hole injection layer by lithography technologies on a needed thickness of resonance mode;
evaporating corresponding emitting layers on the hole transport layers;
evaporating an electron transport layer on the emitting layer;
evaporating an electron injection layer on the electron transport layer; and
manufacturing a top electrode on the organic electro-emitting assembly.

US Pat. No. 10,088,726

ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate, wherein, the array substrate comprises a substrate and a first metal layer, an insulating layer, a P—Si semiconductor layer, a dielectric spacer layer and a second metal layer formed on the substrate, the first metal layer comprises a first zone and a second zone arranged spaced, the first metal layer of the first zone is the gate electrode of the TFT of the array substrate, the second metal layer comprises a third zone and a fourth zone arranged spaced, the second metal layer of the third zone and the fourth zone are the source electrode and the drain electrode of the TFT, respectively, wherein, the P—Si semiconductor layer and the first metal layer of the second zone are arranged insulated and overlapped through the insulating layer sandwiched between the P—Si semiconductor layer and the first metal layer of the second zone, or the P—Si semiconductor layer and the second metal layer of the fourth zone are arranged insulated and overlapped through the dielectric spacer layer sandwiched between the P—Si semiconductor layer and the second metal layer of the fourth zone to form a MIS storage capacitor of the array substrate; andwherein, the gate electrode of the TFT is on the P—Si semiconductor layer, the array substrate further comprises a shading metal layer forming on the substrate and a buffer layer arranged between the shading metal layer and the P—Si semiconductor layer, the shading metal layer comprises a fifth zone and a sixth zone arranged spaced, the fifth zone is under the first zone, the second metal layer further comprises a seventh zone arranged spaced and adjacent with the fourth zone and away from the third zone, the P—Si semiconductor layer connects the shading metal layer of the sixth zone through the second metal layer of the seventh zone, the first metal layer of the second zone connects the second metal layer of the second zone, so that the MIS storage capacitor of the array substrate is formed by the P—Si semiconductor layer, the first metal layer of the second zone and the insulating layer between above.

US Pat. No. 10,043,473

GOA CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit, which comprises: a plurality of cascade GOA units, each GOA unit comprising: a forward-and-reverse scan control module, an output module connected to the forward-and-reverse scan control module, a pull-down module connected to the output module, and a pull-down control module connected to the forward-and-reverse scan control module, the output module and the pull-down module;for a positive integer n and a positive number m, other than the GOA unit in the first and the last stages, in the n-th GOA unit:
the forward-and-reverse scan control module being connected to receive a gate scan drive signal of the (n?1)-th GOA unit, a gate scan drive signal of the (n+1)-th GOA unit, and a first constant voltage, for outputting the first constant voltage to the output module based on the gate scan drive signal of the (n?1)-th GOA unit or the gate scan drive signal of the (n+1)-th GOA unit to control output module to achieve forward scanning or reverse scanning of the GOA circuit;
the output module outputting an n-th gate scan drive signal during an operation duration of the n-th GOA unit;
the pull-down module pulling down the voltage level of the n-th gate scan drive signal during a non-operation duration of the n-th GOA unit; and
the pull-down control module shutting down the pull-down module and maintaining the output module turned on during the operation duration of the n-th GOA unit, and turning on the pull-down module and shutting down the output module during the non-operation duration of the n-th GOA unit;
wherein the forward-and-reverse scan control module comprises: a first thin film transistor (TFT), with the gate connected to the gate scan drive signal of the (n?1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to a first node; and a third TFT, with the gate connected to the gate scan drive signal of the (n+1)-th GOA unit, the source connected to the first constant voltage, and the drain connected to the first node;
the output module comprises: a second TFT, with the gate connected to a second node, the source connected to an m-th clock signal, and the drain connected to the gate scan drive signal of the n-th GOA unit; and a first capacitor, with one end connected to the second node and the other end connected to the gate scan drive signal of the n-th GOA unit;
the pull-down module comprises: a fourth TFT, with the gate connected to a third node, the source connected to the gate scan drive signal of the n-th GOA unit, and the drain connected to a second constant voltage; and a second capacitor, with one end connected to the third node and the other end connected to the second constant voltage; and
the pull-down control module comprises: a sixth TFT, with the gate connected to the third node, the source connected to the first node, and the drain connected to the second constant voltage; a seventh TFT, with the gate connected to the first node, the source connected to the third node, and the drain connected to the second constant voltage; and an eighth TFT, with the gate connected to the (m+2)-th clock signal, the source connected to the first constant voltage, and the drain connected to the third node; and
the GOA unit further comprises a regulator module, which comprising a fifth TFT, with the gate connected to the first constant voltage, the source connected to the first node, and the drain connected to the second node;
wherein the first constant voltage and the second constant voltage having opposite voltage levels.

US Pat. No. 10,032,425

CMOS GOA CIRCUIT OF REDUCING CLOCK SIGNAL LOADING

WUHAN CHINA STAR OPTOELEC...

1. A CMOS GOA circuit of reducing clock signal loading, comprising: GOA units of a plurality of stages, wherein the GOA units of odd stages are cascade coupled, and the GOA units of even stages are cascade coupled;N is set to be positive integer, and except the GOA units of the first, the second, the next to last and the last stages, in the Nth GOA unit comprises: an input control module, a latch module electrically coupled to the input control module, a reset module electrically coupled to the latch module, a signal process module electrically coupled to the latch module, an output buffer module electrically coupled to the signal process module;
the input control module receives a stage transfer signal and a Mth clock signal of the two former N?2th stage GOA unit, and is employed to invert the stage transfer signal of the two former N?2th stage GOA unit twice to obtain a stage transfer signal and input the stage transfer signal to the latch module;
the latch module receives an inverted scan drive signal of the two former N?2th stage GOA unit to be an input control signal of the stage transfer signal, and is employed to latch the stage transfer signal; meanwhile, the latch module further receives a scan drive signal of the two latter N+2th stage GOA unit or an inverted scan drive signal of the two latter N+2th stage GOA unit to be a pull down control signal of the stage transfer signal;
the reset module is employed to perform clear zero process to the stage transfer signal;
the signal process module is employed to implement NAND logic process to the M+2th clock signal and the stage transfer signal to generate a scan drive signal of the Nth stage GOA unit;
the output buffer module is employed to output the scan driving signal and to increase a driving ability of the scan driving signal.

US Pat. No. 9,935,137

MANUFACTURE METHOD OF LTPS ARRAY SUBSTRATE

WUHAN CHINA STAR OPTOELEC...

1. A manufacture method of a LTPS array substrate, comprising steps of:step 1, providing a substrate, and defining a NMOS region and a PMOS region on the substrate, and depositing a first metal layer on the substrate, and patterning the first metal layer to obtain a light shielding layer in the NMOS region;
step 2, forming a buffer layer on the light shielding layer and the substrate, and depositing an amorphous silicon layer on the buffer layer, and employing a low temperature crystallization process to convert the amorphous silicon layer into the polysilicon layer, and patterning the polysilicon layer to obtain a first polysilicon layer in the NMOS region and a second polysilicon layer in the PMOS region;
step 3, coating a photoresist layer on the first polysilicon layer, the second polysilicon layer and the buffer layer, and after employing a halftone mask to implement exposure, development to the photoresist layer, forming first vias corresponding to two ends of the second polysilicon layer in the photoresist layer to expose the two ends of the second polysilicon layer, and meanwhile, forming first grooves corresponding to two ends of the first polysilicon layer in the photoresist layer; employing the photoresist layer to be a mask to implement P type heavy doping to the two ends of the second polysilicon layer to obtain two P type heavy doping regions, and forming a second channel region on the second polysilicon layer in a region between the two P type heavy doping regions;
employing a dry etching process to implement ashing treatment to the photoresist layer to decrease a thickness of the photoresist layer to make the first grooves converted into second vias to expose the two ends of the first polysilicon layer, and employing the photoresist layer to be a mask to implement N type heavy doping to the two ends of the first polysilicon layer to obtain two N type heavy doping regions;
employing a photoresist stripping process to completely strip the rest photoresist layer to expose the first polysilicon layer and the second polysilicon layer, and implementing P type light doping to the first polysilicon layer and the second polysilicon layer to achieve channel doping to the first polysilicon layer.

US Pat. No. 9,904,115

LIQUID CRYSTAL PANELS

Shenzhen China Star Optoe...

8. A liquid crystal panel, comprising:
a first four-domain structure, a second four-domain structure, a third four-domain structure, and a fourth four-domain structure
repeatedly arranged;

wherein the first four-domain structure and the fourth four-domain structure form a first sub-pixel, and the second four-domain
structure and the third four-domain structure form a second sub-pixel, and the first sub-pixel and the second sub-pixel comprises
sixteen liquid crystal rotation states; and

wherein a reference azimuth of the rotated liquid crystal within the first four-domain structure is the same with the reference
azimuth of the rotated liquid crystal within the second four-domain structure, the reference azimuth of the rotated liquid
crystal within the third four-domain structure is the same with the reference azimuth of the rotated liquid crystal within
the fourth four-domain structure, a difference between the reference azimuth of the rotated liquid crystal within the first
four-domain structure and the reference azimuth of the rotated liquid crystal within the third four-domain structure is in
a range between 40 and 50 degrees, and a pretilt angle of the rotated liquid crystal within the first four-domain structure
is different from the pretilt angle of the rotated liquid crystal within the second four-domain structure, and the pretilt
angle of the rotated liquid crystal within the third four-domain structure is different from the pretilt angle of the rotated
liquid crystal within the fourth four-domain structure.

US Pat. No. 9,904,131

LIQUID CRYSTAL PANEL AND LIQUID CRYSTAL DEVICE

Wuhan China Star Optoelec...

1. A liquid crystal panel, comprising:
a TFT substrate and a color film substrate parallel to each other, and a liquid crystal layer between the TFT substrate and
the color film substrate, wherein the TFT substrate comprises at least one reflective area and at least one transmission area
arranged in an interleaved manner, a surface of the TFT substrate facing away the color film substrate is configured with
a metallic reflective layer of a wedged-shaped structure, the metallic reflective layer is arranged on the reflective area,
a surface of the metallic reflective layer facing toward the liquid crystal layer is a plane, and a surface of the metallic
reflective layer facing away the liquid crystal layer is a slope, a thickness of the metallic reflective layer has been gradually
increased along a direction from the transmission area toward the reflective area, the liquid crystal panel further comprises
a first polarizer and a second polarizer, the first polarizer arranged on the surface of the TFT substrate facing away the
color film substrate, and the second polarizer is arranged on the surface of the color film substrate facing away the TFT
substrate.

US Pat. No. 9,905,182

GOA DRIVING CIRCUITS, TFT DISPLAY PANELS AND DISPLAY DEVICES

Wuhan China Star Optoelec...

1. A display device, comprising:
a thin film transistor (TFT) substrate includes a gate driver on array (GOA) driving circuit, wherein the GOA driving circuit
includes a plurality of driving unit at multiple levels, and wherein each of the driving units comprises:

an input module configured to receive display scanning signals or touch scanning signals, output signals at a previous level,
and output signals at a next level, wherein the input module is configured to output first control signals in accordance with
the received display scanning signals or the touch scanning signals;

an output module configured to receive the first control signals and first clock signals, wherein the output module is configured
to output first output control signals in accordance with the first control signals and the first clock signals;

a pull-down module configured to receive the first control signals, second clock signals, and low level signals, wherein the
pull-down module is configured to output pull-down signals in accordance with the first control signals, the second clock
signals, and the low level signals, wherein the second clock signals and the first clock signals are inversed; and

a pull-down maintaining module configured to receive the pull-down signal, high level signals, and the first clock signals,
and

wherein the pull-down maintaining module is configured to output second output control signals in accordance with the pull-down
signals, the high level signals, and the first clock signals, wherein the first output control signals and the second output
control signals cooperatively operate to obtain the output signals,

wherein the input module comprises a first transistor configured to receive the touch scanning signals, and a second transistor
configured to receive the display scanning signals, the scanning signals are high level scanning signals and low level scanning
signals,

wherein a control end of the first transistor configured to receive the output signals at the previous level, an input end
of the first transistor configured to receive the high level scanning signals or the low level scanning signals, and an output
end of the first transistor configured to output the first control signals; and a control end of the second transistor configured
to receive the output signals at the next level, an input end of the second transistor configured to receive the high level
scanning signals or the low level scanning signals, and the output end of the first transistor configured to output the first
control signals,

wherein the output module comprises a third transistor and a first capacitor, wherein a control end of the third transistor
is connected to the output end of the second transistor to receive the first control signals, an input end of the third transistor
configured to receive the first clock signals, and an output end of the third transistor configured to output the first output
control signals; and two ends of the first capacitor respectively are connected to the control end and the output end of the
third transistor,

wherein the pull-down signals comprises first pull-down signals and second pull-down signals, and
the pull-down module comprises a fourth transistor and a fifth transistor,
wherein a control end of the fourth transistor is connected to the output end of the second transistor to receive the first
control signals, and an input end of the fourth transistor configured to receive the second clock signals, and an output end
of the fourth transistor configured to output the first pull-down signals; and a control end of the fifth transistor configured
to receive the second clock signals, an input end of the fifth transistor configured to receive the low level signals, and
an output end of the fifth transistor configured to output the second pull-down signals,

wherein the pull-down maintaining module comprises a sixth transistor, a seventh transistor, an eighth transistor, and a second
capacitor,

wherein a control end of the sixth transistor configured to receive the first clock signals, an input end of the sixth transistor
is connected to an output end of the seventh transistor, an output end of the sixth transistor is connected to the control
end of the third transistor; and

a control end of the seventh transistor respectively is connected to the output ends of the fourth transistor and the fifth
transistor to receive the pull-down signals, an input end of the seventh transistor configured to receive the high level signals,
an output end of the seventh transistor is connected with the input end of the sixth transistor; a control end of the eighth
transistor respectively is connected with the output ends of the fourth transistor and the fifth transistor to receive the
pull-down signals, an input end of the eighth transistor configured to receive the high level signals, and an output end of
the eighth transistor configured to output the second output control signals; and one end of the second capacitor is connected
with the control ends of the seventh transistor and the eighth transistor, and the other end of the second capacitor configured
to receive the high level signals.

US Pat. No. 9,906,222

GATE DRIVING CIRCUIT AND LIQUID CRYSTAL DISPLAY HAVING THE SAME

Wuhan China Star Optoelec...

1. A gate driving circuit, comprising:
an input and latch circuit, a signal processing circuit electrically connected with the input and latch circuit and an output
buffering circuit electrically connected with the signal processing circuit;

wherein, the input and latch circuit outputs a first control signal according to a scanning driving signal of a previous stage,
a first clock signal and a second clock signal phase-inverted with respect to the first clock signal; the signal processing
circuit outputs a second control signal according to the first control signal and a third clock signal; the output buffering
circuit outputs a scanning driving signal of a current stage according to the second control signal;

wherein, the input and latch circuit or the signal processing circuit includes two switch modules which are disposed in parallel,
wherein each switch module includes two switching tubes disposed in series, control terminals of the two switching tubes of
one of the two switch modules are crosswise connected with control terminals of the two switching tubes of the other of the
two switch modules;

wherein, the input and latch circuit includes: a first clock-controlled inverter, a second clock-controlled inverter and a
first inverter; a positive phase control terminal of the first clock-controlled inverter is inputted with the first clock
signal, a negative phase control terminal of the first clock-controlled inverter is inputted with the second clock signal;
an input terminal of the first clock-controlled inverter is inputted with the scanning driving signal of the previous stage;
an output terminal of the first clock-controlled inverter is connected with an output terminal of the second clock-controlled
inverter; a positive phase control terminal of the second clock-controlled inverter is inputted with the second clock signal;
a negative phase control terminal of the second clock-controlled inverter is inputted with the first clock signal; an input
terminal of the first inverter is connected with the output terminal of the first clock-controlled inverter and the output
terminal of the second clock-controlled inverter; an output terminal of the first inverter is connected with an input terminal
of the second clock-controlled inverter, and outputs the first control signal, wherein, at least one of the first clock-controlled
inverter and the second clock-controlled inverter is disposed with the two switch modules connected between at least one output
terminal of the first clock-controlled inverter and the second clock-controlled inverter and a reference voltage level; and

wherein, the output buffering circuit includes second odd-numbered inverters connected sequentially in series; an input terminal
of the second inverters close to the signal processing circuit is inputted with the second control signal, an output terminal
of the second inverters away from the signal processing circuit outputs the scanning driving signal of the current stage.

US Pat. No. 9,898,986

DISPLAY DEVICE CAPABLE OF PERFORMING BLACK FRAME INSERTION

Shenzhen China Star Optoe...

1. A display device capable of performing black frame insertion, comprising a display screen, and a gate driving circuit and
a source driving circuit coupled to the display screen, a gamma circuit and a time sequence control circuit, wherein the gamma
circuit comprises an either-or multiplex selector, and input data of one input end of the either-or multiplex selector is
a VCOM voltage outputted by the gamma circuit, and input data of the other input end is a voltage converted from a predetermined
value after digital to analog conversion stored in a multi time programmable memory of the gamma circuit, and one general
purpose input output port of the time sequence control circuit is assigned to be a control port of controlling output of the
either-or multiplex selector, and as the either-or multiplex selector selects the VCOM voltage outputted by the gamma circuit
under control of the control port, the outputted VCOM voltage is amplified by an operational amplifier in the gamma circuit
and then outputted to the source driving circuit to be a first gamma reference voltage which is required as the source driving
circuit performs digital to analog conversion, and the time sequence control circuit does not output data as a gamma reference
voltage required when the source driving circuit performs digital to analog conversion is the first gamma reference voltage
for realizing output of black frame insertion and reducing power consumption of the time sequence control circuit and the
source driving circuit.

US Pat. No. 9,897,734

POLARIZING FILM AND DISPLAY DEVICE HAVING THE POLARIZING FILM

WUHAN CHINA STAR OPTOELEC...

1. A polarizing film, comprising:
a transparent substrate;
a linear polarizer disposed on the transparent substrate; and
an optical retardation film disposed on the transparent substrate;
wherein the linear polarizer includes a first dielectric layer disposed on the transparent substrate and a metal layer disposed
on the first dielectric layer; and the optical retardation film c includes a second dielectric layer disposed on the transparent
substrate;

the metal layer of the linear polarizer includes striping metal wires periodically arranged with a period of 20-500 nm, a
duty ratio is 0.1 to 0.9 and a height of the metal wire is 10-500 nm;

the second dielectric layer of the optical retardation film includes striping dielectric lines periodically arranged with
a period of 100-700 nm, a duty ratio is 0.1 to 0.9 and a height of the the dielectric line is 0.1-10 ?m; and

the period of the dielectric lines is less than half wavelength of the incident light.

US Pat. No. 9,875,709

GOA CIRCUIT FOR LTPS-TFT

WUHAN CHINA STAR OPTOELEC...

1. A gate driver on array (GOA) circuit for low temperature poly-silicon (LTPS) thin film transistor (TFT), which comprises:
a plurality of cascade GOA units, each GOA unit comprising: an output control module, an output module, a bootstrap capacitor
and a pull-down module;
for a positive integer n, other than the GOA unit in the first and the last stages, in the n-th GOA unit:
the output control module comprising: a first TFT, with a gate connected to an M-th clock signal, a source connected to an
output end of a (n?1)-th GOA unit, and a drain connected to a third node; a third TFT, with a gate connected to an (M+2)-th
clock signal, a drain connected to the third node, and a source connected to the output end of a (n+1)-th GOA unit; and a
fifth TFT, with a gate connected to a constant high voltage, a source connected to the third node, and a drain connected to
a first node;

the output module comprising: a second TFT, with a gate connected to the first node, a source connected to an (M+1)-th clock
signal, and a drain connected to an output end;

the bootstrap capacitor having one end connected to the first node and the other end connected to the output end;
the pull-down module comprising: a fourth TFT, with a gate connected to an (M+3)-th clock signal, a drain connected to the
output end, and a source connected to a constant low voltage; a sixth TFT, with a gate connected to a second node, a drain
connected to the third node, and a source connected to the constant low voltage; a seventh TFT, with a gate connected to the
second node, a drain connected to the output end, and a source connected to the constant low voltage; an eighth TFT, with
a gate connected to the third node, a drain connected to the second node, and a source connected to the constant low voltage;
a ninth TFT, with a gate connected to a fourth node, a source connected to the (M+1)-th clock signal, a and drain connected
to the second node; a tenth TFT, with a gate connected to the third node, a drain connected to the fourth node, and a source
connected to the constant low voltage; and a resistor, with one end connected to the constant high voltage and the other end
connected to the fourth node.

US Pat. No. 9,865,221

VOLTAGE REGULATION CIRCUIT AND LIQUID CRYSTAL DISPLAY COMPRISING THE SAME

SHENZHEN CHINA STAR OPTOE...

1. A voltage regulation circuit in a liquid crystal display panel, comprising: a common voltage generating module configured
to provide a first initial voltage to a common electrode, the first initial voltage comprising an Alternating current (AC)
voltage and a Direct current (DC) voltage, wherein the common voltage generating module comprises a first output terminal
configured to output the first initial voltage to the common electrode;
an inputting module configured to input a second initial voltage into a pixel, wherein the inputting module comprises a second
output terminal configured to output the second initial voltage;

a reverse processing module configured to process the first initial voltage of the common voltage generating module so as
to obtain a reverse voltage of the AC voltage, wherein the reverse processing module comprises a first input terminal and
a third output terminal,

wherein the first initial voltage is inputted into the first input terminal, wherein the third output terminal is configured
to output the reverse voltage of the AC voltage, wherein the reverse processing module comprises a DC blocking unit, wherein
the DC blocking unit is configured to remove the DC voltage of the first initial voltage inputted by the first input terminal;
and an integration module configured to regulate the first initial voltage according to the reverse voltage of the AC voltage
so as to make a liquid crystal drive voltage equal to a preset value,

wherein the liquid crystal drive voltage is a difference value of between the second initial voltage and the first initial
voltage, wherein the integration module comprises a second input terminal and a fourth output terminal,

wherein the reverse voltage of the AC voltage and the first initial voltage are inputted into the second input terminal, the
fourth output terminal is configured to output the liquid crystal drive voltage, wherein the integration module comprises
a fourth resistance, a fifth resistance, a sixth resistance, a second differential amplifier, and a second capacitor; the
second differential amplifier comprises a second initial input terminal, a second feedback input terminal, and a second differential
output terminal; the first input terminal is further connected with the second input terminal via the sixth resistance, the
second initial input terminal is connected with the second input terminal, the second feedback input terminal is grounded
through the fourth resistance; the second differential output terminal is connected with the second feedback input terminal
via the fifth resistance; the second differential output terminal is connected with the fourth output terminal, the second
differential output terminal is further wounded through the second capacitor; and the first output terminal is connected with
the first input terminal, the second input terminal is connected with the first output terminal and the third output terminal,
the second output terminal is connected with the fourth output terminal; and the liquid crystal display panel comprises a
plurality of pixels and the common electrode, wherein the reverse processing module comprises a first resistance, a second
resistance, a third resistance, a first differential amplifier, and a first capacitor; the first differential amplifier comprises
a first initial input terminal, a first feedback input terminal, and a first differential output terminal; the first input
terminal is connected with a terminal of the first capacitor, and another terminal of the first capacitor is connected with
a terminal of the first resistance, and another terminal of the first resistance is connected with the first initial input
terminal, the first feedback input terminal is grounded; and the first differential output terminal is connected with the
first initial input terminal via the second resistance, and the first differential output terminal is connected with the second
input terminal via the third resistance.

US Pat. No. 9,859,436

MANUFACTURE METHOD OF TFT SUBSTRATE STRUCTURE AND TFT SUBSTRATE STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. A manufacture method of a TFT substrate structure, comprising steps of:
step 1, providing a substrate and deposing a buffer layer on the substrate;
step 2, deposing a polysilicon layer on the buffer layer;
step 3, deposing a gate isolation layer on the polysilicon layer, and deposing a metal layer on the gate isolation layer;
step 4, coating a photoresist layer on the metal layer, which is formed in step 3 before the photoresist layer is coated,
and implementing patterning process to the photoresist layer with one mask to acquire a first photoresist section in the middle
and a plurality of second photoresist sections which are distributed in spaces at two sides of the first photoresist section;

step 5, employing the first photoresist section and the plurality of second photoresist sections to be a mask to implement
etching to the metal layer to acquire a gate under the first photoresist section correspondingly and to respectively acquire
a plurality of metal sections under the plurality of second photoresist sections correspondingly;

step 6, stripping the first photoresist section and the plurality of second photoresist sections, and employing the gate and
the plurality of metal sections to be a mask to implement ion implantation to the polysilicon layer to form a channel area
at the polysilicon layer under the gate correspondingly, and to form a plurality of n-type heavy doping areas at two sides
of the channel area respectively positioned under the gate isolation layer where no metal sections are arranged above, and
to form a plurality of undoped areas among the plurality of n-type heavy doping areas under the plurality of metal sections
correspondingly, wherein the plurality of n-type heavy doping areas and plurality of undoped areas are formed while the gate
and the plurality of metal sections are arranged above the gate isolation layer and utilized as the mask.

US Pat. No. 9,857,653

THIN FILM TRANSISTOR ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY PANEL

Shenzhen China Star Optoe...

1. A thin film transistor array substrate, wherein the thin film transistor array substrate comprises:
a substrate, and the substrate comprises a first surface and a second surface, which are oppositely located;
a thin film transistor array, located on the first surface;
a common electrode layer, and the common electrode layer is isolated from the thin film transistor array, and the common electrode
layer comprises a plurality of first strip holes;

a sensing electrode layer, and the sensing electrode layer is isolated from the common electrode layer, and the sensing electrode
layer comprises a plurality of sensing units and a plurality of sensing wires, and the sensing units are distributed in row
and column, and the sensing wires are electrically coupled to the sensing units of each row or each column respectively, and
the sensing wires are located corresponding to the first strip holes.

US Pat. No. 9,846,329

DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY

Wuhan China Star Optoelec...

9. A liquid crystal display, comprising:
a display panel, including:
an upper polarizer;
a lower polarizer;
a first substrate and a second substrate disposed oppositely between the upper polarizer and the lower polarizer;
a liquid crystal layer disposed between the first substrate and the second substrate;
a quantum dot layer, disposed at a side of the second substrate which is far away from the liquid crystal layer; and
a protection layer for protecting the quantum dot layer, disposed between the quantum dot layer and the lower polarizer;
wherein, the quantum dot layer is disposed at a side of the second substrate far away from the liquid crystal layer, and the
protection layer for protecting the quantum dot layer is disposed between the quantum dot layer and the lower polarizer; and

wherein, the protection layer for protecting the quantum dot layer is used for preventing the quantum dot layer from being
oxidized;

wherein, the quantum dot layer at least covers a projection region on the second substrate projected by the first substrate;
and

wherein, an area covered by the quantum dot layer is less than an area of the side of the second substrate far away from the
liquid crystal layer, and is greater than or equal to an area of a projection region on the second substrate projected by
the upper polarizer or the lower polarizer, and an area covered by the protection layer is equal to the area of the side of
the second substrate far away from the liquid crystal layer.

US Pat. No. 9,830,876

CMOS GOA CIRCUIT

SHENZHEN CHINA STAR OPTOE...

1. A CMOS GOA circuit, comprising a plurality of GOA units which are cascade connected;
N is set to be positive integer, and the Nth GOA unit comprises: an input control module, a latch module electrically coupled
to the input control module, a signal process module electrically coupled to the latch module, an output buffer module electrically
coupled to the signal process module and a storage capacitor electrically coupled to the latch module and the signal process
module;

the input control module receives a stage transfer signal of the GOA unit circuit of the former N?1th stage, a first clock
signal, a first inverted clock signal, a constant high voltage level signal and a constant low voltage level signal, and is
employed to invert the stage transfer signal of the GOA unit circuit of the N?1th stage to obtain an inverted stage transfer
signal, and inputs the inverted stage transfer signal to the latch module;

the latch module comprises a NOR gate, and a first input end of the NOR gate is inputted with the inverted stage transfer
signal, and a second input end is inputted a global signal, and an output end of the NOR gate outputs the stage transfer signal,
when at least one of the inverted stage transfer signal and the global signal inputted into the NOR gate is high voltage level,
the output end outputs the stage transfer signal of low voltage level; and as stage transfer signal is high voltage level
and the global signal is low voltage level, the latch module latches the stage transfer signal and the stage transfer signal
outputted by the NOR gate remains to be high voltage level;

the signal process module receives the stage transfer signal, a second clock signal, the constant high voltage level signal,
the constant low voltage level signal and the global signal, and is employed to implement NAND logic process to the second
clock signal and the stage transfer signal to generate a scan driving signal of the GOA unit circuit of the Nth stage; implements
NOR Logic process to the global signal with a result of implementing AND logic process to the second clock signal and the
stage transfer signal to realize that the global signal controls all the scan driving signals of the respective stages raised
up to high voltage levels at the same time;

the output buffer module comprises an odd number of first inverters which are sequentially coupled in series, which are employed
to output the scan driving signal and to increase a driving ability of the scan driving signal;

one end of the storage capacitor is directly coupled to the stage transfer signal, and the other end is directly grounded,
and employed to store a voltage level of the stage transfer signal;

the global signal comprises a single pulse, and as the single pulse is high voltage level, all the scan driving signals of
the respective stages are controlled to be raised up to high voltage levels at the same time, and meanwhile, the NOR gate
is controlled to pull down voltage levels of the stage transfer signals of the respective stages to clear and reset the stage
transfer signals of the respective stages and the storage capacitor stores the low voltage level of the stage transfer signal
to prevent continuation of the scan driving signal.

US Pat. No. 9,817,266

POLARIZER AND TRANSPARENT DISPLAY

Wuhan China Star Optoelec...

1. A transparent display, comprising a backlight module, a first polarizer, a liquid crystal layer and a second polarizer,
which are sequentially stacked up in a first direction;
wherein the first polarizer comprises a first polarization layer, and the first polarization layer comprises a plurality of
first polarization regions and a plurality of first transmittance regions, and the plurality of first polarization regions
and the plurality of first transmittance regions are alternately aligned on a plane perpendicular to a first direction, and
the first polarization regions are employed to transmit through linear polarization light in a polarization axis of the first
polarization regions, and the first transmittance regions are employed to transmit through natural light;

the liquid crystal layer comprises a plurality of display regions and a plurality of transparent regions, and the plurality
of display regions and the plurality of transparent regions are alternately aligned on the plane perpendicular to the first
direction;

the second polarizer comprises a second polarization layer, and the second polarization layer comprises a plurality of second
polarization regions and a plurality of second transmittance regions, and the plurality of second polarization regions and
the plurality of second transmittance regions are alternately aligned on the plane perpendicular to the first direction, and
the second polarization regions are employed to transmit through linear polarization light in a polarization axis of the second
polarization regions, and the second transmittance regions are employed to transmit through natural light; and

vertical projections of the plurality of first polarization regions on the liquid crystal layer completely cover the plurality
of display regions correspondingly one to one, and vertical projections of the plurality of second polarization regions on
the liquid crystal layer completely cover the plurality of display regions correspondingly one to one; and

wherein both an area of the first polarization regions of the first polarizer and an area of the second polarization regions
of the second polarizer are larger than an area of the display regions of the liquid crystal layer.

US Pat. No. 9,817,267

LIQUID CRYSTAL DISPLAYS AND THE DISPLAY METHODS THEREOF

Wuhan China Star Optoelec...

1. A liquid crystal display (LCD), comprising:
a light guiding plate, a light source arranged at a light incident side of the light guiding plate, a quantum dot (QD) media
layer, a first polarizer, and an advanced polarization conversion film (APCF) arranged on a surface of the first polarizer
facing away the light guiding plate, the QD media layer is arranged between the light source and the first polarizer, the
first polarizer and the APCF are arranged between the QD media layer and the light guiding plate;

the light beams emitted from the light source pass through the QD media layer and activate the QD media layer to emit lights,
a portion of the light beams from the QD media layer pass through the APCF and the first polarizer to generate the polarized
beams entering the light guiding plate, the other portion of the light beams are reflected by the APCF to arrive the QD media
layer, and activate the QD media layer to emit lights; and

a second polarizer arranged on an non-light-emitting-surface of the light guiding plate, a first substrate arranged on a light
emitting surface of the light guiding plate, a second substrate opposite to the first substrate, a liquid crystal layer between
the first substrate and the second substrate, and a reflective sheet arranged on a surface of the second substrate facing
toward the liquid crystal layer, the non-light-emitting-surface is parallel to the light emitting surface, the light beams
from the light guiding plate emit out from the light emitting surface, pass through the liquid crystal layer, and are reflected
back toward the light guiding plate by the reflective sheet, most of the reflected light beams pass through the second polarizer
and enter human eyes, a small portion of the reflected light beams are absorbed by the second polarizer, and the light beams
emitted from the light source are blue light, and the blue light activate the QD media layer to emit white light.

US Pat. No. 9,798,404

TOUCH PANELS AND THE DRIVING METHOD THEREOF

Shenzhen China Star Optoe...

1. A touch panel, comprising:
a display area and a non-display area, the display area comprising a plurality of pixel electrodes and touch sensors, the
non-display area comprising a chip area, and a fan area, wherein:

the chip area comprising a driving chip having a plurality of pins, at least a portion of the pins outputting first driving
signals for controlling the pixel electrodes, and outputting second driving signals for controlling the touch sensor;

a plurality of wirings corresponding to the pins being arranged within the fan area, and the wirings transmitting the first
driving signals and the second driving signals outputted by the pins;

the plurality of pins comprising at least one first pin and at least one second pin spaced apart from each other, the first
pin only outputting the first driving signals, and the second pin outputting the first driving signals and the second driving
signals in a time-sharing manner;

the wirings comprising a first wiring and a second wiring respectively connecting to the first pin and the second pin for
transmitting the driving signals outputted by the first pin and the second pin;

a gap density between the first pin and the second pin being configured according to a touch sensibility of the touch panel,
and a greater gap density being configured when the touch sensibility of the touch panel is higher;

each of the pixel electrodes comprising a R-subpixel electrode, a G-subpixel electrode, and a B-subpixel electrode, the non-display
area further comprising a multitask demultiplex area, the first wiring and the second wiring passing through the fan area
and entering the multitask demultiplex area, wherein within the multitask demultiplex area:

each of the first wirings comprising three sub-wirings respectively connecting to the R sub-pixel electrode, the G sub-pixel
electrode, and the B sub-pixel electrode so as to transmit the first driving signals to the R sub-pixel electrode, the G sub-pixel
electrode, and the B sub-pixel electrode, respectively;

each of the second wirings comprising four sub-wirings respectively connecting to the R sub-pixel electrode, the G sub-pixel
electrode, the B sub-pixel electrode, and the touch sensor to respectively transmit the first driving signals to the R sub-pixel
electrode, the G sub-pixel electrode, and the B sub-pixel electrode and to transmit the second driving signals to the touch
sensor;

wherein the display area comprises a plurality of scanning lines and data lines, wherein the data lines are arranged above
the scanning lines, a first insulation layer is arranged between the data line and the scanning line, and a second insulation
layer is arranged above the data line;

the sub-wiring transmitting the second driving signals to the touch sensor is configured on the same layer with the scanning
line, the touch panel further comprises a connecting line arranged on the same layer with the data line, the connecting line
passes through a first through hole of the first insulation layer to connect with the sub-wiring transmitting the second driving
signals to the touch sensor, and the connecting line passes through a second through hole of the second insulation layer to
electrically connect with a touch-driving-signals line of the touch sensor.

US Pat. No. 9,792,845

SCAN DRIVING CIRCUIT

WUHAN CHINA STAR OPTOELEC...

1. A scan driving circuit for driving scan lines connected in series, comprising:
a pull-down controlling module for receiving a scan signal from a former stage and generating a scan voltage signal having
a low voltage level with respect to a scan line according to the scan signal from the former stage;

a pull-down module for pulling down the scan signal with respect to the scan line according to the scan voltage signal;
a reset-controlling module for receiving a clock signal from a next stage and generating a reset signal with respect to the
scan line according to the clock signal from the next stage;

a resetting module for pulling up the scan signal with respect to the scan line according to the reset signal;
a downward-transmitting module for generating and transmitting a clock signal of a current stage and a pull-down controlling
signal of the current stage according to the scan signal of the scan line;

a first bootstrap capacitor for generating the scan voltage signal either having the low voltage level or a high voltage level
of the scan line;

a constant low voltage level source for providing a low voltage level signal; and
a constant high voltage level source for providing a high voltage level signal,
wherein either P-type metal-oxide semiconductor transistors or N-type metal-oxide semiconductor transistors are utilized in
the scan driving circuit to control the pull-down controlling module, the pull-down module, the reset-controlling module,
and the resetting module;

the pull-down controlling module is also used for receiving a scan signal from the next stage and generating the scan voltage
signal having the low voltage level with respect to the scan line according to the scan signal from the next stage; and

the reset-controlling module is also used for receiving a clock signal from the former stage and generating the reset signal
with respect to the scan line according to the clock signal from the former stage;

wherein the pull-down controlling module comprises a first transistor; a scan signal having a low voltage level is inputted
into a control end of the first transistor; the scan signal from the former stage is inputted into an input end of the first
transistor; and an output end of the first transistor is connected with the pull-down module;

wherein the pull-down module comprises a second transistor; a control end of the second transistor is connected with the output
end of the first transistor of the pull-down controlling module; an input end of the second transistor is connected with the
output end of the first transistor of the pull-down controlling module; and the scan voltage signal having the low voltage
level of the scan line is outputted by an output end of the second transistor;

wherein the reset-controlling module comprises a third transistor; the scan signal having the low voltage level is inputted
into a control end of the third transistor; the clock signal from the next stage is inputted into an input end of the third
transistor; and the reset signal of the scan line is outputted by an output end of the third transistor;

wherein the resetting module comprises a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor;
a control end of the fourth transistor is connected with the output end of the third transistor; an input end of the fourth
transistor is connected with the constant low voltage level source; and an output end of the fourth transistor is respectively
connected with a control end of the fifth transistor, a control end of the seventh transistor, and an output end of the sixth
transistor;

an input end of the fifth transistor is connected with the constant high voltage level source; and an output end of the fifth
transistor is connected with the output end of the second transistor;

a control end of the sixth transistor is connected with the output end of the second transistor; and an input end of the sixth
transistor is connected with the constant high voltage level source; and

an input end of the seventh transistor is connected with the constant high voltage level source; and the scan signal of the
current stage of the scan line is outputted by an output end of the seventh transistor.

US Pat. No. 9,792,871

GATE DRIVER ON ARRAY CIRCUIT AND LIQUID CRYSTAL DISPLAY ADOPTING THE SAME

Wuhan China Star Optoelec...

1. A gate driver on array (GOA) circuit, comprising:
a plurality of GOA circuit units, connected in cascade, with the GOA circuit unit at each stage outputting a scan signal from
an output terminal based on a scan signal outputted by a previous stage GOA circuit unit, a scan signal outputted by a next
stage GOA circuit unit, a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, a first
enabling signal and a second enabling signal; the GOA circuit unit at each stage comprises:

a scan control module, comprising:
a first transistor, comprising a gate electrically connected to the first enabling signal, a source electrically connected
to the scan signal outputted by a next stage GOA circuit unit;

a second transistor, comprising a gate electrically connected to the second enabling signal, and a source electrically connected
to the scan signal outputted by the previous stage GOA circuit unit;

a third transistor, comprising a gate electrically connected to the first enabling signal, and a source electrically connected
to the fourth clock signal;

a fourth transistor, comprising a gate electrically connected to the second enabling signal, and a source electrically connected
to the second clock signal;

a fifth transistor, comprising a gate electrically connected to scan signals outputted by the next stage GOA circuit unit
or the previous stage GOA circuit unit, and a source electrically connected to a first constant voltage; and

a sixth transistor, comprising a gate electrically connected to scan signals outputted by a previous stage GOA circuit unit
or a next stage GOA circuit unit, and a source electrically connected to a drain of the fifth transistor;

an input control module, electrically connected to drains of the first and second transistors, for turning on the scan signals
outputted by the previous stage GOA circuit unit or next stage GOA circuit unit based on the third clock signal;

an output control module, electrically connected to a control node, for controlling the output of the scan signal based on
a voltage imposed on the control node;

a voltage regulating module, electrically connected to the output control module, for stabilizing the voltage of the control
node to prevent current leakage;

a pull-up holding module, electrically connected to the input control module, scan control module, output control module and
voltage regulating module, for holding the control node at a high level during non-scanning periods, and holding the scan
signal at a high level; and

a pull-up facilitating module, electrically connected to the pull-up holding module, for controlling leakage of the input
control module during the period when the control node is being charged.

US Pat. No. 9,786,721

OLED DISPLAY PANEL

Wuhan China Star Optoelec...

1. An OLED display panel comprising an array substrate and a color filter layer, the color filter layer being disposed on
the array substrate, wherein the array substrate comprises a cathode layer disposed on the top of the array substrate, the
color filter layer is disposed on the cathode layer, a surface of the color filter layer away from the cathode layer is disposed
with a second thin film layer thereon, a first thin film layer is disposed between the cathode layer and the color filter
layer, and the first thin film layer and the second thin film layer each are a plurality of organic and inorganic layers being
alternately stacked.

US Pat. No. 9,784,996

LIQUID CRYSTAL DISPLAY MODULE AND DEVICE

Wuhan China Star Optoelec...

1. A liquid crystal display (LCD) module, comprising parallel and sequentially stacked backlight unit, LCD unit, and view-angle
adjustment unit, wherein the backlight unit is positioned along a back side of the LCD module as a backlight light source;
the LCD unit is sandwiched between the backlight unit and the view-angle adjustment unit; light produced by the backlight
unit propagates through the LCD unit and the view-angle adjustment unit sequentially; the view-angle adjustment unit comprises
a front glass substrate, a back glass substrate, a plurality of electrodes, and a plurality of liquid crystal molecules; the
electrodes and the liquid crystal molecules are sandwiched between the front and back glass substrates; the electrodes are
positioned at intervals between the front and back glass substrates, forming a plurality of chambers between neighboring electrodes;
the liquid crystal molecules are positioned in the chambers; the liquid crystal molecules are positive liquid crystal molecules;
and the liquid crystal molecules are vertically aligned initially.

US Pat. No. 9,778,519

LIQUID-CRYSTAL DISPLAY PANEL AND DEVICE

SHENZHEN CHINA STAR OPTOE...

1. A liquid-crystal display panel, comprising:
a first substrate comprising a first common electrode and a planarization layer;
a second substrate disposed opposite to the first substrate, comprising a second common electrode and a pixel electrode; and
a liquid-crystal layer disposed between the first substrate and the second substrate;
wherein a projection of the pixel electrode on the first substrate does not overlap with a pattern of the first common electrode
on the first substrate;

the pixel electrode is spiral.

US Pat. No. 9,754,554

PIXEL STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. A pixel structure, comprising a plurality of sub-pixels, the plurality of sub-pixels being arranged in the form of a point
lattice exhibiting a honeycomb configuration comprising honeycomb cells each showing a regular hexagon having edges that have
a length a, the sub-pixels being respectively located at vertices of the plurality of regular hexagons;
the plurality of sub-pixels comprising a plurality of first color sub-pixels, a plurality of second color sub-pixels, and
a plurality of third color sub-pixels;

wherein for two rows of the sub-pixels that are adjacent to each other in an up-down direction, the sub-pixels of one of the
rows are arranged in a horizontal direction such that spacing distances therebetween are of an alternate arrangement of a
and 2a, wherein for every two sub-pixels of which the spacing distance therebetween is a, the one of the sub-pixels that is
located at the right-hand side is a first color sub-pixel, while the one of the sub-pixels that is located at the left-hand
side is a second color sub-pixel; and, the sub-pixels of the other one of the rows are arranged in a horizontal direction
such that spacing distances therebetween are of an alternate arrangement of 2a and a, wherein for every two sub-pixels of
which the spacing distance therebetween is a, the one of the sub-pixels that is located at the right-hand side is a first
color sub-pixel, while the one of the sub-pixels that is located at the left-hand side is a third color sub-pixel; and

for each column of the sub-pixels, multiple ones of the sub-pixels having the same color are arranged in a straight line in
a vertical direction, while two columns that are adjacent to each other in a left-right direction comprise sub-pixels of different
colors.

US Pat. No. 9,720,150

COLOR-FILM SUBSTRATES AND LIQUID CRYSTAL DEVICES

Wuhan China Star Optoelec...

1. A color-film substrate, comprising:
a substrate body and a color filter layer on the substrate body, the color filter layer comprises color filter elements having
at least one of red color filter element, green color filter element, and blue color filter element arranged in a sequence,
the color filter layer comprises a first display area and a second display area arranged in a rim of the first display area;
and

wherein a thickness of the color filter elements of the second display area is larger than a thickness of the color filter
element of the first display area such that a transmission rate of the display panel corresponding to the second display area
is smaller than the transmission rate of the display panel corresponding to the first display area;

wherein the thickness of the color filter elements in the second display area gradually decreases along a direction from the
second display area toward the first display area.

US Pat. No. 9,713,918

EVAPORATION DEVICE AND EVAPORATION METHOD

Wuhan China Star Optoelec...

1. An evaporation device, wherein the evaporation device comprises: a carrier stage, a base and a light source; the carrier
stage is placed on the base; the base is also provided with multiple vacuum pins; the multiple vacuum pins can move with respect
to the base; the carrier stage is provided with multiple pin holes; the multiple vacuum pins can pass through the multiple
pin holes in order to absorb a substrate; a side of the carrier stage away from the base is coated with a photosensitive adhesive
for directly bonding the substrate such that the substrate and the carrier stage are detachably connected through the photosensitive
adhesive, the light source is used to irradiate the photosensitive adhesive between carrier stage and the substrate in order
to decrease the adhesiveness of the photosensitive adhesive;
wherein, the carrier stage is capable of moving and rotating to realize an evaporation process for the substrate.

US Pat. No. 9,647,009

TFT ARRAY SUBSTRATE STRUCTURE

WUHAN CHINA STAR OPTOELEC...

1. A thin-film transistor (TFT) array substrate structure, comprising: a backing plate, a patterned metal light-shielding
layer formed on the backing plate, a first insulation layer covering on the patterned metal light-shielding layer, a plurality
of TFTs formed on the first insulation layer and arranged in an array, a planarization layer covering the TFTs, a common electrode
formed on the planarization layer, a protection layer covering on the common electrode, and a patterned pixel electrode formed
on the protection layer;
the TFTs each comprising a semiconductor layer formed on the first insulation layer, a gate insulation layer covering on the
semiconductor layer, a gate electrode arranged on the gate insulation layer and located above the semiconductor layer, an
interlayer dielectric layer formed on the gate electrode and the gate insulation layer, and a source electrode and a drain
electrode formed on the interlayer dielectric layer;

the patterned metal light-shielding layer comprising a plurality of metal light-shielding blocks arranged in an array and
a narrowed metal strip connected between two adjacent ones of the metal light-shielding blocks, each of the metal light-shielding
blocks being arranged to correspond to and located under one of the semiconductor layers;

the metal light-shielding layer and the common electrode being both connected to and receiving a common voltage signal, the
pixel electrode being set in engagement with the drain electrode of the TFT;

wherein for each of the TFTs, the pixel electrode has a portion overlapping the common electrode to form first storage capacitor
and the metal light-shielding layer has a portion overlapping the drain electrode and the pixel electrode to form a second
storage capacitor, the first storage capacitor and the second storage capacitor being connected in parallel.

US Pat. No. 10,121,804

TFT SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A manufacturing method of a thin-film transistor (TFT) substrate, comprising the following steps:step 1, providing a backing plate, forming a first insulation layer on the backing plate, depositing and patterning a second metal layer on the first insulation layer, and forming a second insulation layer on the second metal layer,
wherein the second metal layer comprises a plurality of peripheral signal wiring traces;
step 2, forming, in the second insulation layer at locations corresponding to each of the peripheral signal wiring traces, a plurality of vias that is arranged in an extension direction of each of the peripheral signal wiring traces and extends through the second insulation layer;
step 3, depositing and patterning a third metal layer on the second insulation layer such that the third metal layer is formed at a location corresponding to each of the peripheral signal wiring traces and is electrically connected, through the plurality of vias, with each of the peripheral signal wiring traces; and
step 4, depositing a third insulation layer on the second insulation layer and the third metal layer to complete the manufacture of the TFT substrate;
wherein the plurality of peripheral signal wiring traces comprises high level direct-current (DC) signal lines, low level DC signal lines, and clock signal lines of a gate-driver-on-array (GOA) circuit and grounding lines of the TFT substrate.

US Pat. No. 10,048,550

DRIVER CHIP STRUCTURE AND LIQUID CRYSTAL DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A driver chip structure, wherein the driver chip structure comprises a substrate and a plurality of connection bumps which are located on the substrate and equal in size, and the substrate comprises a surface, and the plurality of connection bumps are spaced and aligned on the surface in array, and sectional appearances of the connection bumps parallel with the surface are trapezoids, wherein the surface comprises two lateral sides which are opposite and parallel with each other, and the sectional appearances of the connection bumps are trapezoids, and the trapezoids comprise upper base sides and lower base sides, and one column of the connection bumps adjacent to one of the lateral sides are alternately aligned in form of normal trapezoids and obtrapezoids, wherein the lower base sides of the normal trapezoids face the lateral side adjacent to the connection bumps, and the upper base sides of the obtrapezoids face the lateral side adjacent to the connection bumps to increase an amount of the connection bumps and a connection area of the connection bumps.

US Pat. No. 10,042,223

TFT ARRAYS, DISPLAY PANELS, AND DISPLAY DEVICES

Shenzhen China Star Optoe...

11. A display panel, comprising:an array substrate comprising GND wiring and GOA areas, GND wirings and GOA areas, the GND wirings being configured at outer sides of the GOA areas, the GOA area comprising a variety of GOA signal lines and N-th stage GOA circuits electrically connected by the GOA signal lines, a first ESD protection circuit being configured in a middle area between a 1-th stage GOA circuit and the N-th stage GOA circuit to discharge abnormal electrical charges of the GOA signal lines within the middle area.

US Pat. No. 10,043,474

GATE DRIVING CIRCUIT ON ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY (LCD) USING THE SAME

WUHAN CHINA STAR OPTOELEC...

1. A gate driving circuit which is disposed on an array substrate of a liquid crystal display (LCD), wherein the gate driving circuit on the array substrate comprises a plurality of sequentially connected gate driving units, the gate driving circuit unit comprising:an input module, for receiving a previous stage-transmitting signal Q(N?1), a previous inverse stage-transmitting signal XQ(N?1) and a low voltage signal to generate a current stage transition signal TP(N) and a current stage-transmitting signal Q(N) wherein the serial number “N” is a positive integer;
a reset module connected to the input module, for receiving a reset signal, a high voltage signal and the low voltage signal to allow the current stage transition signal TP(N) and the current stage-transmitting signal Q(N) to be reset by the reset signal in an initial status, wherein the reset module generates a control signal based on the high voltage signal and the current stage transition signal;
a latch module connected to the reset module, for receiving the control signal, a first clock signal and the high voltage signal, wherein the latch module generates a current inverse stage-transmitting signal XQ(N) according to the control signal and the first clock signal; and
a signal processing module connected to the latch module, for receiving the current inverse stage-transmitting signal XQ(N), the low voltage signal, a second clock signal and a third clock signal to control on/off statuses of two transistors by the current stage-transmitting signal Q(N) so that the two transistors forms Nth gate signal G(N) and gate signal (N+1)th based on the second clock signal and the third clock signal.

US Pat. No. 9,935,127

CONTROL CIRCUIT OF THIN FILM TRANSISTOR

Wuhan China Star Optoelec...

1. A control circuit for reducing leakage current of a common gate device, comprising:a substrate;
a silicon nitride layer disposed on the substrate;
a silicon dioxide layer disposed on the silicon nitride layer;
a light shielding layer disposed inside the silicon nitride layer, the light shielding layer comprising a first light shielding region and a second light shielding region;
at least one N type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the first light shielding region; and
at least one P type metal oxide semiconductor disposed on the silicon dioxide layer at a position corresponding to the second light shielding region;
wherein each of the N type metal oxide semiconductor and the P type metal oxide semiconductor has a gate electrode layer, a first control signal received by voltage pulses of the gate electrode layer is synchronized with a second control signal received by the light shielding layer according to voltage variations of the first and second control signals;
wherein the control circuit further comprises an N type control circuit or a P type control circuit;
wherein the N type control circuit, comprises:
a gate line connected to the gate electrode layer of each N type metal oxide semiconductor to provide the first control signal;
a light shielding layer control line used for connecting each first light shielding region to provide the second control signal;
an N type light shielding layer control signal generating unit connected with the light shielding layer control line to generate the second control signal; and
at least one data line, respectively connected to a source/drain electrode of the N type metal oxide semiconductor;
the respective connected gate electrode layer voltage pulse synchronized controlled by the gate line and the respective connected light shielding layer voltage pulse synchronized controlled by the N type light shielding layer control signal generating unit;
wherein the P type control circuit, comprises:
a gate line connected to the gate electrode layer of each P type metal oxide semiconductor to provide the first control signal;
a light shielding layer control line used for connecting with each the second light shielding region to provide the second control signal;
a P type light shielding layer control signal generating unit, connected with the light shielding layer control line to generate the second control signal; and
at leak one data line, respectively connected to the source/drain electrode of the P type metal oxide semiconductor;
the respective connected gate electrode layer voltage pulse synchronized controlled by the gate line and the respective connected light shielding layer voltage pulse synchronized controlled by the P type light shielding layer control signal generating unit.

US Pat. No. 9,933,756

SMART WATCH

WUHAN CHINA STAR OPTOELEC...

1. A smart watch, which comprises: a dial (10), a first strap (20) and a second strap (24), connected respectively to both sides of the dial (10);the dial (10) comprising a shell body (11), a first display (12) disposed on a front of the shell body (11), a second display (13) disposed on a back of the shell body (11), and a control circuit disposed inside the shell body (11) to electrically connect the first display (12) and the second display (13);
wherein the first display (12) and the second display (13) are monolithically made from a display motherboard (100), and are controlled by the same control circuit; and
wherein the display motherboard (100) is a flexible organic light-emitting diode (OLED) display motherboard;
the display motherboard (100) comprises: a substrate (110), a light-emitting layer (120) disposed on the substrate (110), an encapsulation layer (130) disposed on the substrate (110) surrounding the light-emitting layer (120), and a control circuit connection area (140) disposed on the substrate (110) outside of the layer encapsulation layer (130);
the substrate (110) being a flexible substrate, comprising a first light-emitting area (111), a first bending area (112), a connection area (113), a second bending area (114), and a second light-emitting area (115) disposed consecutively;
the light-emitting layer (120) covering the first light-emitting area (111) and the second light-emitting area (115), and being disposed with a trench corresponding to the locations of the first bending area (112), the connection area (113) and the second bending area (114);
the light-emitting layer (120) covering the first light-emitting area (111) and the second light-emitting area (115) being electrically connected through metal wires of the trench;
the display motherboard (100) having a bend at the first bending area (112) and a second bending area (114) respectively, so that the first light-emitting area (111) and the second light-emitting area (115) of the substrate (110) located respectively on the front and the back of the shell body (11), and being connected to a control circuit through the control circuit connection area (140) to form the first display (12) and the second display (13).

US Pat. No. 9,921,673

IN-CELL TOUCH DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. An in-cell touch display panel, comprising a thin-film transistor (TFT) substrate, a color filter (CF) substrate opposite
to the TFT substrate, and a liquid crystal layer between the TFT substrate and the CF substrate;
wherein the TFT substrate comprises a first base plate, a light-shielding layer formed on the first base plate, a first insulation
layer formed on the first base plate and the light-shielding layer, a TFT layer formed on the first insulation layer, a first
planarization layer formed on the TFT layer, a pixel electrode formed on the first planarization layer, a first passivation
layer formed on the pixel electrode, a touch detection electrode layer formed on the first passivation layer, a second passivation
layer formed on the first passivation layer and the touch detection electrode layer, and a common electrode formed on the
second passivation layer; and

the second passivation layer comprises a first via formed therein and corresponding to the touch detection electrode layer,
the common electrode being connected, through the first via, to the touch detection electrode layer; and the TFT layer comprises
source/drain electrodes, and the first planarization layer comprises a second via formed therein and corresponding to the
source/drain electrodes, the pixel electrode being connected, through the second via, to the source/drain electrodes;

wherein the CF substrate is spaced from the TFT substrate in a predetermined direction and the first planarization layer,
the first passivation layer, and the second passivation layer are stacked in order on each other in the predetermined direction,
the pixel electrode being interposed between the first passivation layer and the first planarization layer and connected through
the second via to the source/drain electrodes, the touch detection electrode layer being interposed between the first passivation
layer and the second passivation layer and connected through the first via to the common electrode, wherein the touch detection
electrode layer is located under the common electrode and above the pixel electrode in the predetermined direction and is
isolated from the pixel electrode and the source/drain electrodes by the first passivation layer.

US Pat. No. 9,904,102

COLOR FILM SUBSTRATES AND THE TRANSFLECTIVE LIQUID CRYSTAL DEVICES (LCDS) HAVING WIDE VIEWING ANGLE

Wuhan China Star Optoelec...

1. A transflective liquid crystal device (LCD) having wide viewing angle, comprising:
a transmission area, and a reflective area;
a first substrate, a second substrate opposite to the first substrate, a liquid crystal layer between the first substrate
and the second substrate, and a reflective layer between the second substrate and the liquid crystal layer;

a first polarizer, a second polarizer, and a half-wave plate;
wherein the first polarizer is arranged on one side of the first substrate facing away the liquid crystal layer, the second
polarizer is arranged on one side of the second substrate facing away the liquid crystal layer, and an optical axis direction
of the first polarizer and the second polarizer are respectively zero and 90 degree(s);

the half-wave plate is arranged on one side of the first substrate facing toward the liquid crystal layer and the first substrate
is within the transmission area; and

the half-wave plate comprises a first half-wave plate and a second half-wave plate adjacent to each other, the optical axis
direction of the first half-wave plate is perpendicular to that of the second half-wave plate, the optical axis direction
of the first half-wave plate is 45 degrees, the optical axis direction of the second half-wave plate is 45 degrees, and a
dimension of the first half-wave plate equals to the dimension of the second half-wave plate.

US Pat. No. 9,905,804

FLEXIBLE DISPLAY AND METHOD OF FORMING THE SAME

Wuhan China Star Optoelec...

1. A flexible display, comprising:
a flexible base;
an organic light-emitting diode (OLED) element, disposing on the flexible base;
an encapsulation layer, disposed on the OLED element, with the flexible base and/or the encapsulation layer comprising one
or more patterned inorganic layers and two or more organic layers, the two or more organic layers are configured to wrap the
inorganic layers,

wherein the flexible base and the encapsulation layer comprise a plurality of patterned inorganic layers,
wherein the inorganic layers comprise a plurality of patterned areas, with gaps formed between the plurality of patterned
areas; the two or more organic layers are disposed above and below the patterned inorganic layers, and are connected through
the gaps.

US Pat. No. 9,905,590

MANUFACTURING METHOD OF A LTPS ARRAY SUBSTRATE

Shenzhen China Star Optoe...

1. A manufacturing method of a LTPS array substrate, wherein it comprises:
forming a source electrode and a drain electrode of a TFT of said LTPS array substrate on a substrate;
forming polysilicon layers of a first region and a second region on said substrate including said source electrode and said
drain electrode, and the width of said polysilicon layer of said first region being greater than said second region, said
polysilicon layer of said first region except said second region partially covering said source electrode and said drain electrode;

passivating the surface of said polysilicon layer, in order to transform the portion adjacent to the surface of said polysilicon
layer of said second region and said polysillicon layer of said first region into insulating layer, wherein said passivation
comprises at least one of an oxidation treatment and the nitriding treatment;

forming a gate electrode of said TFT on said insulating layer between said source electrode and said drain electrode;
injecting P-type impurity ions into the both ends where said polysilicon layer of said first region directly contacts with
said source electrode and said drain electrode, in order to form a LDD structure;

forming a planar layer on said substrate including said gate electrode, and forming a contact hole in said planar layer in
order to expose the surface of said drain electrode;

forming a common electrode layer of said LTPS array substrate on said planar layer except for corresponding to said TFT;
forming a passivation layer on said planar layer and said common electrode, and said passivation layer being not covered with
said contact hole;

forming a pixel electrode on said passivation layer, and said pixel electrode could be electrically connected with said drain
electrode through said contact hole.

US Pat. No. 9,897,837

MOBILE TERMINAL

Wuhan China Star Optoelec...

1. A mobile terminal, comprising:
a middle frame;
a plastic frame;
a backplane; and
a display module including a display panel and a backlight module;
wherein the plastic frame includes a first frame and a second frame, two opposite sides of the backlight module respectively
abut the first frame and the second frame such that the backlight module is received in the plastic frame;

wherein the backplane carry the backlight module and plastic frame;
wherein the middle frame surrounds the plastic frame and the display module;
wherein the middle frame, the plastic frame and the backplane are formed integrally as a case, and the case is formed by a
plastic injection molding; and

wherein the case includes a bottom plate and a side wall connected with an edge of the bottom plate, the side wall includes
two ladder portions, an upper stage of the two ladder portions carry the display panel, and a lower stage of the two ladder
portions carry the backlight module;

wherein a surface of the display panel away from the backlight module is aligned with a terminal surface of the side wall
of the case;

wherein, the case is a metal case;
wherein the mobile terminal further includes a back cover, and the back cover is disposed at a side of the case away from
the display module;

wherein the display panel is attached to the backlight module through a glue;
wherein a protection glass is provided to cover the surface of the display panel away from the backlight module in order to
protect the display panel from breaking; and

wherein a recess is formed between the side of the case away from the display module and a side of the back cover for receiving
a battery and a circuit board.

US Pat. No. 9,897,853

BACKLIGHT MODULE AND DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A backlight module, comprising a glue frame, a light guide plate and a backlight source, wherein the glue frame comprises
two opposite side walls and end walls connecting with the two opposite side walls, and a loading plate is located at an inner
side of one of the end walls, and a limiting plate is connected between the two opposite side walls, and the limiting plate
and the loading plate are respectively located at two opposite sides of the light guide plate, and the light guide plate comprises
an incident surface, a limiting block and a limiting slot, and the limiting block and the limiting slot are respectively located
on two opposite surfaces of the light guide plate and close to one end of the light guide plate provided with the incident
surface, and the glue frame is installed at periphery of the light guide plate, and the backlight source is installed on the
loading plate and between the glue frame and the light guide plate, and the limiting slot is hold with the loading plate,
and the limiting block is located between the end wall and the limiting plate, and is supported with the limiting plate, and
wherein the limiting plate and the loading plate are misaligned and oppositely located, and an end surface of the limiting
plate toward the end wall is a first end surface, and an end surface of the loading plate toward the limiting plate is a second
end surface, and the first end surface and the second end surface are oppositely located and positioned on the same plane.

US Pat. No. 9,897,864

CURVED DISPLAY PANEL COMPRISING A SUBSTRATE EDGE HAVING RECESSES AT POSITIONS CORRESPONDING TO A PLURALITY OF SPACERS AND ELECTRONIC APPARATUS

Shenzhen China Star Optoe...

1. A curved display panel, comprising a color filter substrate, an array substrate and a plurality of spacers, and the color
filter substrate and the array substrate are curved, and the plurality of spacers is positioned between the color filter substrate
and the array substrate, and an edge of one of the color filter substrate and the array substrate comprises recesses at positions
corresponding to the spacers, a center of one of the color filter substrate and the array substrate comprises bulges at positions
corresponding to the spacers.

US Pat. No. 9,897,873

BLUE PHASE LIQUID CRYSTAL DISPLAY DEVICE AND DISPLAY MODULE OF THE SAME

Wuhan China Star Optoelec...

1. A blue phase liquid crystal display module, comprising:
an upper substrate having multiple upper sawtooth-shaped electrodes;
a lower substrate disposed oppositely to the upper substrate, the lower substrate is provided with multiple lower sawtooth-shaped
electrodes which are alternately disposed with the multiple upper sawtooth-shaped electrodes, convex portions of the multiple
upper sawtooth-shaped electrodes are corresponding to concave portions of the multiple lower sawtooth-shaped electrodes, wherein,
the multiple upper sawtooth-shaped electrodes are connected with a portion of the multiple lower sawtooth-shaped electrodes
in order to form a first pixel electrode and a second pixel electrode which are separated from each other, and pixel electrode
signals having opposite polarities are respectively applied on the first pixel electrode and the second pixel electrode; an
elastic material is filled between the upper sawtooth-shaped electrodes and the upper substrate, and an elastic material is
filled between the lower sawtooth-shaped electrodes and the lower substrate; the lower sawtooth-shaped electrodes includes
a first lower-sawtooth-electrode portion and a second lower-sawtooth-electrode portion which are separated from each other,
the multiple upper sawtooth-shaped electrodes is connected with the first lower-sawtooth-electrode portion; the second pixel
electrode includes the first lower-sawtooth-electrode portion and the multiple upper sawtooth-shaped electrodes, and the first
pixel electrode is the second lower-sawtooth-electrode portion; and

blue phase liquid crystals disposed between multiple the upper sawtooth-shaped electrodes and the multiple lower sawtooth-shaped
electrodes, wherein an electric field is formed between the multiple upper sawtooth-shaped electrodes and the multiple lower
sawtooth-shaped electrodes in order to drive the blue phase liquid crystals.

US Pat. No. 9,897,875

TRANSPARENT DISPLAY

Wuhan China Star Optoelec...

1. A transparent display, comprising a backlight module, a lower polarizer, a phase delay thin film, a liquid crystal layer
and an upper polarizer, which are sequentially stacked up in an image display direction, and
the transparent display alternately comprises a plurality of transparent regions and a plurality of display regions in a first
direction perpendicular with the image display direction, and

the phase delay thin film comprises a plurality of first phase delay thin films located in the plurality of transparent regions
and a plurality of second phase delay thin films located in the plurality of display regions, and

the plurality of first phase delay thin films provide a first phase delay, and the plurality of second phase delay thin films
provide a second phase delay, and a difference of the first phase delay and the second phase delay is ?/2; and

wherein a polarization axis of the upper polarizer is parallel with a polarization axis of the lower polarizer, and a phase
delay value of the first phase delay thin film is 0, and the second phase delay thin film delays a phase of light with ?/2,
and an extension direction of the polarization axis of the lower polarizer and an extension axis of a fast axis of the second
phase delay thin film form a 45° included angle.

US Pat. No. 9,898,943

LIQUID CRYSTAL DISPLAY MODULE

Wuhan China Star Optoelec...

1. A liquid crystal display module, comprising a liquid crystal display panel and a driver integrated circuit, wherein the
liquid crystal display panel comprises a testing pad, a first pad and a second pad, the first pad comprises a first sub pad
and a second sub pad which are separately disposed, the second sub pad is electrically connected to the testing pad, the driver
integrated circuit comprises at least two third pads, the third pads are respectively bonded to the first pad and the second
pad; the first sub pad and the second sub pad are commonly bonded to one of the third pads, so as to achieve a short circuit
between the first sub pad and the second sub pad; and
wherein the liquid crystal display panel comprises a plurality of liquid crystal cells, the testing pad is electrically connected
to the liquid crystal cells through a first testing signal line, and the first pad and the second pad are electrically connected
to the liquid crystal cells through a display signal line.

US Pat. No. 9,886,930

CONTROL CIRCUIT AND DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A drive control circuit, comprising a single data driver, a pixel array and at least one first resistor and at least one
second resistor, and the pixel array comprises M×N pixels aligned in a form M rows×N columns, and M is a natural number larger
than 1, and N is a natural number, and the single data driver is coupled to the N columns pixels of the pixel array through
the at least one first resistor and the at least one second resistor to charge the N columns pixels, wherein the at least
one first resistor and the at least one second resistor are coupled in parallel between the single data driver and one column
pixels and a resistance of the first resistor is larger than a resistance of the second resistor, and an area surrounded by
the pixel array is divided into a first area and a second area, and both the first area and the second area comprise at least
one row pixels, and a length of a connection line of the single data driver with any row pixels in the first area is smaller
than a length of a connection line of the single data driver with any row pixels in the second area, and when the single data
driver determines that it is required to sequentially supply power to each row pixels of the first area, the first resistor
is selected and activated by the single data driver to make a power supply signal outputted by the single data driver pass
through the first resistor and be sequentially outputted to each row pixels of the first area for sequentially supplying power
to the each row pixels of the first area, and when the single data driver determines that it is required to sequentially supply
power to each row pixels of the second area, the second resistor is selected and activated by the single data driver to make
the power supply signal outputted by the single data driver pass through the second resistor and be sequentially outputted
to each row pixels of the second area for sequentially supplying power to the each row pixels of the second area to balance
charge quantity of the each row pixels.

US Pat. No. 9,885,933

TFT ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A thin-film transistor (TFT) array substrate, comprising: a backing plate, a light-shielding layer arranged on the backing
plate, a buffer layer set on and covering the light-shielding layer and the backing plate, a poly-silicon semiconductor layer
arranged on the buffer layer and corresponding to the light-shielding layer, a gate insulation layer set on and covering the
poly-silicon semiconductor layer and the buffer layer, a gate electrode arranged on the gate insulation layer and corresponding
to the poly-silicon semiconductor layer, an interlayer insulation layer set on and covering the gate electrode and the gate
insulation layer, a source electrode and a drain electrode arranged on the interlayer insulation layer, a planarization layer
set on and covering the source electrode, the drain electrode, and the interlayer insulation layer, a common electrode arranged
on the planarization layer, a protection layer arranged on the common electrode, and a pixel electrode arranged on the protection
layer;
wherein the source electrode and the drain electrode each comprise a first molybdenum layer, a first aluminum layer, a second
aluminum layer, and a second molybdenum layer that are stacked on each other in sequence from bottom to top, wherein the first
molybdenum layer has a surface that is smooth; the first aluminum layer and the second aluminum layer each have a surface
on which a plurality of sharp spikes are formed and distributed such that the spikes of the second aluminum layer have a height
that is greater than a height of the spikes of the first aluminum layer; and the second molybdenum layer has a surface that
is substantially smooth and covers on the spikes of the second aluminum layer to reduce the sharpness of the spikes of the
second aluminum layer so that an upper surface of each of the source electrode and the drain electrode exhibits a rough surface
having irregularity comprising raised and recessed portions; and

the pixel electrode is set in contact engagement with the upper surface of the drain electrode by means of a via extending
through the protection layer, the common electrode, and the planarization layer.

US Pat. No. 9,887,254

DOUBLE-SIDE OLED DISPLAY

Wuhan China Star Optoelec...

1. A double-side OLED display, comprising:
a base layer having a first end and a second end; and
an OLED layer disposed on the base layer, wherein the OLED layer includes a first display region and a second display region;
and

a folding region disposed between the first display region and the second display region of the OLED layer;
wherein, the base layer and the OLED layer are folded such that the first display region and the second display region respectively
face toward opposite directions; the base layer is located at an outside;

wherein, a terminal of the double-side OLED display opposite to the folding region is fixed with a packaging material for
performing a packaging to the double-side OLED display;

wherein, the packaging material is disposed at a terminal of the first display region away from the folding region and is
disposed at a terminal of the second display region away from the folding region; and

wherein, the packaging material is disposed between the first end and the second end of the base layer.

US Pat. No. 9,829,758

LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A liquid crystal display panel, comprising a first substrate and a second substrate spaced to each other, and liquid crystal
molecules filled between the first substrate and the second substrate;
wherein, a first projection and a first conductive layer are provided on the side of the first substrate facing the second
substrate, the first conductive layer is located at the side of the first projection facing the second substrate;

wherein, when the first substrate and the second substrate are in a natural state, the first conductive layer and the second
substrate are provided with an interval; when the first substrate and the second substrate are close to each other due to
external compression, the first conductive layer contacts with the second substrate and thereby electrically connects with
a charge storage area on the second substrate, which eliminates the accumulated charge thereon;

wherein, the first conductive layer electrically connects with at least two charge storage areas with different electrical
properties when contacting with the second substrate;

wherein, on the side of the second substrate facing the first substrate is provided with a second projection, a second conductive
layer, a third projection, and a third conductive layer, the second conductive layer is located at the side of the second
projection facing the first substrate and electrically connects with a first charge storage area, the third conductive layer
is located at the side of the third projection facing the first substrate and electrically connects with a second charge storage
area, when the first substrate and the second substrate are close to each other due to external compression, the first conductive
layer contacts with the second conductive layer and the third conductive layer simultaneously;

wherein, the first substrate is a color filter substrate, the second substrate is an array substrate, the first charge storage
area and the second charge storage area are respectively a pixel electrode and a common electrode provided on the array substrate.

US Pat. No. 9,799,294

LIQUID CRYSTAL DISPLAY DEVICE AND GOA SCANNING CIRCUIT OF THE SAME

Shenzhen China Star Optoe...

1. A Gate Driver on Array (GOA) scanning circuit, wherein the GOA scanning circuit includes multiple cascaded GOA circuit
units, and an n-th stage (N?n?1, and n is a positive integer, N is a positive integer and greater than or equal to 2) GOA
circuit unit comprises:
a forward and backward scanning module including a first thin-film transistor and a second thin-film transistor, wherein,
two current path terminals of the first thin-film transistor are respectively connected with a first clock signal and a first
node; two current path terminals of the second thin-film transistor are respectively connected with a second clock signal
and the first node; a control terminal of the first thin-film transistor is connected with a stage-transferring signal of
a previous stage GOA circuit unit; a control terminal of the second thin-film transistor is connected with a stage-transferring
signal of a next stage GOA circuit unit; wherein, a control terminal of a first thin-film of a first stage GOA circuit unit
is connected with a forward scanning trigger signal, and a control terminal of a second thin-film transistor of a Nth stage
GOA circuit unit is connected with a backward scanning trigger signal; and

an output module connected with the first node, and used for outputting a stage-transferring signal and a scanning signal
of a present stage GOA circuit unit according to a voltage level of the first node; the output module includes a third transistor,
a fourth transistor and a first capacitor; a control terminal of the third transistor and a control terminal of the fourth
transistor are both connected with the first node; a first current path terminal of the third transistor is connected with
the second clock signal; a second current path terminal of the third transistor is used for outputting the stage-transferring
signal of the present stage GOA circuit unit; a first current path terminal of the fourth transistor is connected with the
second clock signal, and the second current path terminal of the fourth transistor is used for outputting the scanning signal
of the present stage GOA circuit unit; two terminals of the first capacitor are respectively connected with the first node
and the second current path terminal of the third transistor; the first clock signal and the second clock signal are opposite
in phase.

US Pat. No. 9,799,258

DRIVING CIRCUIT ACCORDING TO RGBW AND FLAT PANEL DISPLAY

Shenzhen China Star Optoe...

1. A driving circuit for driving a RGBW pixel of a display, the driving circuit comprising:
a first driving line, a second driving line, a first voltage-level switch, a second voltage-level switch, a third voltage-level
switch, a fourth voltage-level switch, a first non-voltage-level switch, a second non-voltage-level switch, a third non-voltage-level
switch and a fourth non-voltage-level switch, wherein a voltage-level switch is a switch, which is turned on when a first
voltage level is inputted to a control terminal thereof, and a non-voltage-level switch is a switch, which is turned on when
a second voltage level is inputted to a control terminal thereof;

a control terminal of the first voltage-level switch connected to the first driving line, an input terminal of the first voltage-level
switch connected to a driving signal source, an output terminal of the first voltage-level switch connected to an input terminal
of the third non-voltage level switch, a control terminal of the third non-voltage-level switch connected to the second driving
line and an input terminal of the third non-voltage-level switch used to connect to a first sub-pixel;

a control terminal of the second voltage-level switch connected to the first driving line, an input terminal of the second
voltage-level switch connected to the driving signal source, an output terminal of the second voltage-level switch connected
to an input terminal of the third voltage-level switch, a control terminal of the third voltage-level switch connected to
the second driving line, an output terminal of the third voltage-level switch used to connect to a second sub-pixel;

a control terminal of the first non-voltage-level switch connected to the first driving line, an input terminal of the first
non-voltage level switch connected to the driving signal source, an output terminal of the first non-voltage level switch
connected to an input terminal of the fourth voltage-level switch, a control terminal of the fourth voltage-level switch connected
to the second driving line, an output terminal of the fourth voltage-level switch used to connect to a third sub-pixel;

a control terminal of the second non-voltage-level switch connected to the first driving line, an input terminal of the second
non-voltage level switch connected to the driving signal source, an output terminal of the second non-voltage level switch
connected to an input terminal of the fourth non-voltage-level switch, a control terminal of the fourth non-voltage-level
switch connected to the second driving line, an output terminal of the fourth non-voltage-level switch used to connect to
a fourth sub-pixel;

when the first driving line outputs a first voltage level, the second driving line outputs the second voltage level, the first
voltage-level switch and the third non-voltage-level switch are turned on, a driving signal outputted from the driving signal
source outputted to the first sub-pixel through the first voltage-level switch and the third non-voltage-level switch;

when the first driving line outputs the first voltage level, the second driving line outputs the first voltage level, the
second voltage-level switch and the third voltage-level switch are turned on, the driving signal outputted from the driving
signal source outputted to the second sub-pixel through the second voltage-level switch and the third voltage-level switch;

when the first driving line outputs the second voltage level, the second driving line outputs the first voltage level, the
first non-voltage-level switch and the fourth voltage-level switch are turned on, the driving signal outputted from the driving
signal source outputted to the third sub-pixel through the first non-voltage-level switch and the fourth voltage-level switch;

when the first driving line outputs the second voltage level, the second driving line outputs the second voltage level, the
second non-voltage-level switch and the fourth non-voltage-level switch are turned on, the driving signal outputted from the
driving signal source outputted to the fourth sub-pixel through the second non-voltage-level switch and the fourth non-voltage-level
switch.

US Pat. No. 9,733,421

DISPLAY DEVICE AND BACKLIGHT MODULE THEREOF

WUHAN CHINA STAR OPTOELEC...

1. A backlight module, comprising:
a light guide plate,
a reflecting sheet disposed along the plate lower surface of the light guide plate,
an optical assembly disposed on a plate upper surface of the light guide plate,
a light shielding tape, wherein the light guide plate comprises a light guide plate body and a reinforcement member integrally
formed with and disposed about a non-light incidence side of the light guide plate body, and the light shielding tape is adhered
to a portion of an assembly upper surface of the optical assembly and a lower surface of the reflection sheet and extends
therebetween along the non-light incidence side to cover the reinforcement member, and

wherein the reinforcement member comprises a first bent portion in contact with a body upper surface of the light guide plate
body and a second bent portion in contact with a body lower surface of the light guide plate body, and each of the bent portions
is flush with the corresponding surface of the light guide plate body.

US Pat. No. 9,759,941

ARRAY SUBSTRATE USED IN LIQUID CRYSTAL PANEL AND MANUFACTURING METHOD FOR THE SAME

Shenzhen China Star Optoe...

1. An array substrate used in a liquid crystal panel, comprising:
a substrate;
a low-temperature poly-silicon thin-film transistor (LTPS TFT) disposed above the substrate;
a planarization layer which covers the LTPS TFT;
a via hole formed in the planarization layer, wherein, the via hole reveals a drain electrode of the LTPS TFT;
multiple common electrodes and multiple receiving electrodes which are disposed separately on the planarization layer, wherein,
the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are
disposed separately are connected with each other;

a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization
layer; and

a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through
the via hole.

US Pat. No. 9,721,520

GOA CIRCUIT AND A LIQUID CRYSTAL DISPLAY

Shenzhen China Star Optoe...

1. A GOA circuit for liquid crystal display, the GOA circuit comprising a plurality of GOA unit connected in series, wherein
a Nth level GOA unit including a pull-up control module, a pull-down module, a pull-up module, a pull-down holding module
and a leakage control module;
wherein the pull-up control module including a first transistor, a gate terminal of the first transistor is connected to a
N?1th level pull-down signal, a drain terminal of the first transistor is connected to the first leakage control signal and
the source terminal of the first transistor is connected to the Nth levelgate terminal signal;

wherein the pull-down module including a second transistor, the gate terminal of the second transistor is connected to the
Nth levelgate terminal signal, the drain terminal of the second transistor is connected to the Nth level clock signal line,
and the source terminal of the second transistor output the Nth level pull-down signal;

wherein the pull-up module including a third transistor, the gate terminal of the third transistor is connected to the Nth
levelgate terminal signal, the drain terminal of the third transistor is connected to the Nth level clock signal line, and
the source terminal of the third transistor output the Nth level scanning signal;

wherein the pull-down holding module including a fifth transistor and a eighth transistor, the gate terminal of the fifth
transistor is connected to the Nth level common signal, the drain terminal of the fifth transistor is connected to the Nth
level pull-down signal, the source terminal of the fifth transistor is connected to a first low direct current voltage source;
and the gate terminal of the eighth transistor is connected to the Nth level common signal, the source terminal of the eighth
transistor is connected to the first low direct current voltage source and the drain terminal of the eighth transistor is
connected to the Nth levelgate terminal signal;

wherein the leakage control module is connected in series between the Nth level gate terminal signal and the eighth transistor
and/or between the Nth level pull-down signal and the fifth transistor; in the valid period of the Nth level scanning signal,
a second leakage control signal is to block the Nth level gate terminal signal through the leakage pathway of the eighth transistor
and/or to block the Nth level pull-down signal through the leakage pathway of the fifth transistor;

wherein the leakage control module further including a fourth transistor and a seventh transistor, the gate terminal of the
fourth transistor is connected to the second leakage control signal, the drain terminal of the fourth transistor is connected
to the direct current signaling source, the source terminal of the fourth transistor is connected to the drain terminal of
the eighth transistor; the seventh transistor is connected between the Nth levelgate terminal signal and the drain terminal
of the eighth transistor, the gate terminal of the seventh transistor is connected to the Nth level common signal, the drain
terminal of the seventh transistor is connected to the Nth levelgate terminal signal and the source terminal of the seventh
transistor is connected to the drain terminal of the eighth transistor to block the Nth levelgate terminal signal through
the leakage pathway of the eighth transistor in the valid period of the Nth level scanning signal;

wherein the first leakage control signal is the N?1th level gate terminal signal and to block the Nth levelgate terminal signal
through the leakage pathway of the first transistor in the valid period of the Nth level scanning signal.

US Pat. No. 9,648,306

METHOD FOR ALIGNING AND ASSEMBLING STEREOSCOPIC DISPLAY AND MANUFACTURING EQUIPMENT FOR THE SAME

Wuhan China Star Optoelec...

1. A method for aligning and assembling a stereoscopic display, comprising:
using an alignment imaging device to search alignment marks at non-display regions of a display panel and a cylindrical lens
sheet;

determining a center coordinate of the display panel, a center coordinate of the cylindrical lens sheet, and an angle offset
of the display panel and the cylindrical lens sheet;

using the center coordinate of the display panel and the center coordinate of the cylindrical lens sheet to perform a central
assembling and aligning for the display panel and the cylindrical lens sheet; and

respectively rotating the display panel and the cylindrical lens sheet according to the angle offset in order to finish assembling
and aligning of the display panel and the cylindrical lens sheet.

US Pat. No. 10,073,299

FFS MODE LIQUID CRYSTAL DISPLAY PANEL AND LIQUID CRYSTAL DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A fringe field switching (FFS) mode liquid crystal display panel, comprising:a color film substrate comprising:
a first substrate;
a first planar layer disposed below the first substrate;
an array substrate opposite the color film substrate, the array substrate comprising:
a common electrode;
a pixel electrode disposed on the common electrode; and
a second planar layer disposed on the pixel electrode,
a liquid crystal layer sandwiched between the color film substrate and the array substrate;
wherein an inner surface of the first planar layer corresponding to non-overlapping regions has a plurality of wedge structures, and the non-overlapping regions are regions located above the common electrode that do not overlap with projected areas of the pixel electrode projected on the common electrode; the inner surface of the first planar layer corresponding to overlapping regions does not have a plurality of wedge structures, and the overlapping regions are regions located above the common electrode that overlap with projected areas of the pixel electrode projected on the common electrode; the inner surface is a surface adjacent to the liquid crystal layer.

US Pat. No. 10,000,047

METHOD FOR MANUFACTURING CURVED LIQUID CRYSTAL DISPLAY PANEL

WUHAN CHINA STAR OPTOELEC...

1. A method for manufacturing a curved liquid crystal display panel, wherein:the curved liquid crystal display panel comprises:
a first substrate having a first frame sealing region; the first substrate comprises a first set of frame bodies and a second set of frame bodies; the length of the first set of frame bodies is greater than that of the second set of frame bodies; a region formed by the first set of frame bodies and the second set of frame bodies is located outside a first projection region; the first frame sealing region is located inside the region formed by the first set of frame bodies and the second set of frame bodies; the first projection region is a projection of a display region on the first substrate;
a second substrate opposite to the first substrate, having a second frame sealing region; the second substrate comprises a third set of frame bodies and a fourth set of frame bodies; the length of the third set of frame bodies is greater than that of the fourth set of frame bodies; a region formed by the third set of frame bodies and the fourth set of frame bodies is located outside a second projection region; the second frame sealing region is located inside the region formed by the third set of frame bodies and the fourth set of frame bodies; the second projection region is a projection of the display region on the second substrate;
wherein initial structures of the first substrate and the second substrate are planar structures; the liquid crystal display panel with the planar structure has the display region;
the method for manufacturing the curved liquid crystal display panel comprises:
coating a sealing gum on the first frame sealing region or the second frame sealing region;
filling liquid crystals between the first substrate and the second substrate;
performing a vacuum lamination on the first substrate and the second substrate;
performing a first curing on partial sealing gum on the first set of frame bodies or partial sealing gum on the third set of frame bodies such that the first substrate and the second substrate is adhered to each other in a bending process;
bending the first set of frame bodies obtained after the first curing along an extension direction of the first set of frame bodies or along the extension direction of the third set of frame bodies; and bending the third set of frame bodies obtained after the first curing along the extension direction of the first set of frame bodies or along the extension direction of the third set of frame bodies;
performing a second curing on uncured sealing gum on the bended first substrate or uncured sealing gum on the bended second substrate so as to form the curved liquid crystal display panel.

US Pat. No. 9,933,562

DISPLAY DEVICE

Wuhan China Star Optoelec...

1. A display device, comprising:a base comprising a front case and a back case oppositely joined together to provide a slot in between;
a heat dissipation element housed in the slot;
a backlight source housed in the slot; and
a display unit having a bottom portion plugged into the slot;
wherein
top ends of the front and back cases at the slot's opening are basically at a same height;
the heat dissipation element comprises a first vertical section, a first parallel section, and a slant section between the first parallel and vertical sections slanting towards inside of the slot;
the first vertical section is parallel to a bottom side of the slot;
the backlight source is configured on the first vertical section below the bottom portion of the display unit;
the first parallel section is attached to a back side of the display unit;
an inner wall of the back case has a first bulging piece extended from the top end of the back case into the slot and immediately above the first parallel section's top end of the heat dissipation element, and a slope in a middle section slanting towards inside of the slot;the slant section of the heat dissipation element tightly attaches to the slope of the back case.

US Pat. No. 9,933,653

LIQUID CRYSTAL PANEL AND FABRICATING METHOD THEREOF

Wuhan China Star Optoelec...

1. A liquid crystal panel, wherein the characteristic is in that the liquid crystal panel comprises an array substrate, a color film substrate and a liquid crystal layer mounted between the array substrate and the color film substrate; wherein:the color film substrate forms multiple color resists thereon to form multiple color filter units, wherein the multiple color resists includes a first color resist, a second color resist and a third color resist, a thickness of the third color resist is thicker than a thickness of the first color resist and a thickness of the second color resist;
the array substrate at least forms multiple first spacers and multiple second spacers, wherein the multiple first spacers and the multiple second spacers are disposed on the array substrate such that a gap is existed between the multiple color resists and each of the multiple first spacers and the multiple second spacers, a height of the first spacer is equal to a height of the second spacer; and
a thickness of the color resist corresponding to the first spacer is different from a thickness of the color resist corresponding to the second spacer wherein the first spacer is corresponding to the third color resist, the second spacer is corresponding to the first or the second color resist, a third gap existed between the first spacer and the third color resist is smaller than a first gap existed between the second spacer and the first color resist, or is smaller than a second gap existed between the second spacer and the second color resist;
wherein a portion of the third color resist is disposed on and overlapped with the first color resist or the second color resist.

US Pat. No. 9,928,787

LIQUID CRYSTAL DISPLAY DEVICE

WUHAN CHINA STAR OPTOELEC...

1. A liquid crystal display device, comprising:a liquid crystal panel;
at least one source driving unit disposed on the liquid crystal panel and comprising at least one first fan-out line and at least one second fan-out line which are disposed alternately, wherein the at least one first fan-out line is configured to output a first polarity signal, and the second fan-out line is configured to output a second polarity signal;
at least one demultiplexer disposed on the liquid crystal panel and electrically coupled to the first fan-out line and the second fan-out line, the demultiplexer comprising a plurality of buses, a plurality of first output lines, and a plurality of second output lines, the first output lines and the second output lines alternately disposed, each of the buses electrically coupled to one of the first output lines and one of the second output lines; and
a plurality of pixel units, each of the pixel units comprising four sub-pixels,
in the four sub-pixels of each of the pixel units in an N column, a first and a fourth of the sub-pixels respectively and electrically coupled to a first and a fourth of the first output lines, and a second and a third of the sub-pixels respectively and electrically coupled to a second and a third of the second output lines,
in the four sub-pixels of each of the pixel units in an N+1 column, a first and a fourth of the sub-pixels respectively and electrically coupled to a first and a fourth of the second output lines, a second and a third of the sub-pixels respectively and electrically coupled to a second and a third of the first output lines, and N is an odd number greater than or equal to 1,
wherein frames are made in sets of four, the first polarity signal has the same polarity in a first and fourth frames in each of the sets, and the first polarity signal has the same polarity in a second and a third frames in each of the sets.

US Pat. No. 9,904,101

DISPLAY PANEL AND DISPLAY APPARATUS

SHENZHEN CHINA STAR OPTOE...

1. A display panel comprising:
a color film substrate, which includes a first substrate, a color film layer, and a common electrode layer;
a liquid crystal layer; and
a TFT array substrate, which comprises:
a second substrate including at least a first region and at least a second region;
a pixel electrode layer disposed on a first surface of the second substrate;
a carrier layer including at least one carrier platform disposed on the pixel electrode layer, wherein a position of the carrier
platform corresponds with the second region; and

a reflective layer including at least one reflection sheet disposed on the carrier platform, wherein the reflection sheet
has a first reflective surface and a second reflective surface, wherein the first reflective surface and the second reflective
surface are flat,

wherein the reflection sheet is a double-sided lens including a first transparent dielectric layer, a first reflective coating
layer, and a second transparent dielectric layer, the first reflective coating layer being disposed between the first transparent
dielectric layer and the second transparent dielectric layer;

wherein the first transparent dielectric layer and the first reflective coating layer constitute a first lens and the first
reflective surface associates with the first lens, and the second transparent dielectric layer and the first a reflective
coating constitute the second lens and the second reflective surface associates with the second lens; and

the first transparent dielectric layer faces the liquid crystal layer and the second transparent dielectric layer faces the
carrier platform.

US Pat. No. 9,904,120

LIQUID CRYSTAL TOUCH PANEL AND LIQUID CRYSTAL DISPLAY

Wuhan China Star Optoelec...

11. A liquid crystal display comprising a liquid crystal panel and a backlight module, wherein the liquid crystal panel and
the backlight module are disposed oppositely, the backlight module provides a display light source to the liquid crystal panel
such that the liquid crystal panel can display an image;
wherein, the liquid crystal panel is a liquid crystal touch panel comprising an array substrate and a color filter substrate
which are disposed oppositely, and a liquid crystal layer disposed between the array substrate and the color filter substrate,
wherein,

on the array substrate, a common electrode layer and a planarization layer are disposed sequentially; the common electrode
layer is divided into multiple self-capacitance electrodes which are isolated with each other; on the planarization layer,
multiple electrode leads are provided; the multiple electrode leads and the multiple self-capacitance electrodes are electrically
connected one by one, and the multiple electrode leads are covered with an insulation protective layer; and

between the array substrate and the color filter substrate, a main post spacer and an auxiliary post spacer having a same
height are provided; first terminals of the main post spacer and the auxiliary post spacer are connected with the color filter
substrate; a second terminal of the main post spacer abuts on the insulation protective layer, and is right opposite to the
electrode lead; a second terminal of the auxiliary post space is floating above the insulation protective layer and is right
opposite to a region without providing the electrode lead.

US Pat. No. 9,904,389

TOUCH PANEL WIRE ARRANGEMENT CIRCUIT, DISPLAY PANEL AND DISPLAY DEVICE

Shenzhen China Star Optoe...

1. A touch panel wire arrangement circuit, the touch panel wire arrangement circuit comprises: an ITO region, metal wires,
a touch control hole and an integrated circuit in common Indium Tin Oxide com ITO; wherein the touch panel wire arrangement
circuit further comprises:
a rear end switch set, and the rear end switch set comprises: a plurality of switches, and a G electrode of each switch in
the plurality of switches is inputted with a switch signal, and D electrodes of the plurality of switches are sequentially
coupled to rear ends of the metal wires, and S electrodes of the plurality of switches are inputted with at least one voltage
signals;

the switch signal is: a signal at high voltage level as a touch panel TP signal does not function; the voltage signal is a
common voltage V-com signal as the touch panel is in a display state, wherein the rear end switch set comprises: a plurality
of rear end switch sub sets divided in order, and the rear end switch sub set comprises: n switches, and S electrodes of the
n switches are respectively inputted with n voltage signals through n metal wires, and the n voltage signals are: voltage
signals of n various voltage signal values as the touch panel is in a front section detection; the n is a natural number larger
than or equal to 2.

US Pat. No. 9,904,135

ARRAY SUBSTRATE AND LIQUID CRYSTAL DISPLAY DEVICE

Wuhan China Star Optoelec...

1. An array substrate including multiple low-temperature polysilicon thin film transistors arranged as a matrix, wherein each
low-temperature polysilicon thin film transistor comprises:
a substrate; and
a low-temperature polysilicon layer, a first insulation layer, a gate electrode, a second insulation layer, a source electrode,
a drain electrode, a planarization layer, a first transparent conductive layer, a third insulation layer, a second transparent
conductive layer and a connection metal layer which are disposed at a same side of the array substrate;

wherein, the low-temperature polysilicon layer is disposed adjacent to a surface of the substrate; the first insulation layer
covers the low-temperature polysilicon layer; the gate electrode is disposed at a surface of the first insulation layer away
from the low-temperature polysilicon layer; the second insulation layer covers the gate electrode; the second insulation layer
is provided with a first through hole and a second through hole; the source electrode and the drain electrode are disposed
on the second insulation layer; the source electrode is connected with one terminal of the low-temperature polysilicon layer
through the first through hole; the drain electrode is connected with the other terminal of the low-temperature polysilicon
layer through the second through hole; the planarization layer covers the source electrode and the drain electrode; the planarization
layer is provided with a third through hole corresponding to the drain electrode; the first transparent conductive layer is
disposed at a surface of the planarization layer away from the source electrode and the drain electrode; the third insulation
layer covers the first transparent conductive layer, and the third insulation layer fills the third through hole; the third
insulation layer is provided with a fourth through hole that reveals the drain electrode; the second transparent conductive
layer is disposed on the third insulation layer; the connection metal layer connects with the second transparent conductive
layer and the drain electrode through the fourth through hole; and the first transparent conductive layer is a common electrode,
the second transparent conductive layer is a pixel electrode.

US Pat. No. 9,905,183

GATE DRIVER CIRCUIT AND DISPLAY DEVICE APPLY CIRCUIT THEREOF

Wuhan China Star Optoelec...

1. A gate driver circuit, wherein it includes:
a plurality of GOA circuits, wherein each of the odd-numbered stage GOA circuit cascades, each even-numbered stage GOA circuit
cascades; corresponding to said odd-numbered stage GOA being used to provide signal lines of an odd-numbered stage first scan
signal, an odd-numbered stage second scan signal, and odd-numbered stage startup signal, an odd-numbered stage first timing
signal, an odd-numbered stage second timing signal; corresponding to said even-numbered stage GOA circuit being used to provide
signal lines of an even-numbered stage first scan signal, an even-numbered stage second scan signal, an even-numbered stage
startup signal, an even-numbered stage first timing signal, an even-numbered stage second timing signal;

wherein each GOA circuit includes:
a startup module, said startup module including a first scan signal terminal in order to receive a first scan signal, a second
scan signal terminal in order to receive a second scan signal, a first transistor and a second transistor, wherein first terminal
of said first transistor receives a first transmission signal, second terminal of said first transistor receives said first
scan signal, first terminal of said second transistor receives a second transmission signal, second terminal of said second
transistor receives a second scan signal, third terminals of said first transistor and said transistor are connect with a
first node;

a driving module, said driving module including a first capacitor, a second capacitor, a third transistor, a fourth transistor,
a fifth transistor and a sixth transistor, also including a first timing signal terminal in order to receive a first timing
signal, first terminal of said third transistor being connected with said first timing signal terminal, second terminal of
said third transistor being connected with said first node, third terminal of said third transistor being connected with second
terminal of said fourth transistor, first terminal of said fourth transistor being connected with a second node, third terminal
of said fourth transistor being connected with a high voltage input terminal to receive a high voltage signal, said second
node being connected with said high voltage input terminal through said second capacitor, said second node being also connected
with

first terminal of said sixth transistor, second terminal of said sixth transistor being connected with a third node, third
terminal of said sixth transistor being connected with said high voltage input terminal to receive said high voltage signal,
said third node being connected with said first node through said first capacitor, first terminal of said fifth transistor
being connected with said first node, second terminal of said fifth transistor being connected with said first timing signal
terminal, third terminal of said transistor being connected with said third node;

a control module, said control module including a second timing signal terminal, a seventh transistor and a eighth transistor,
said second timing signal terminal being used to provide a second timing signal, first terminal of said eighth transistor
being connected with a first node, second terminal of said eighth transistor being connected with said second timing signal
terminal, third terminal of said eighth transistor being connected with said second node; first terminal of said seventh transistor
being connected with said second timing signal terminal, second terminal of said seventh transistor being connected with a
low voltage input terminal to receive a low voltage signal, third terminal of said seventh transistor being connected with
said second node; when said gate driver circuit carrying on forward scanning, said first scan signal being low, said second
scan signal being high, when said first transmission signal being low, said first transistor turning on, said first scan signal
pulling down said first node to low potential, said first transistor transmitting said first scan signal to said first node;
while said seventh transistor and said eighth transistor turning on, pulling down said second node to low potential; said
first timing signal being low at this time, being controlled by said first node, said fifth transistor turning on, being controlled
by said second node, said fourth transistor and said sixth transistor turning on, said third node being high;

when said gate driver circuit carrying on reverse scanning, said first scan signal being high, said second scan signal being
low, said second transistor turning on, said first scan signal pulling down said first node to low potential, said first transistor
transmitting said first scan signal to said first node; while said seventh transistor and said eighth transistor turning on,
pulling down said second node to low potential; said first timing signal being low at this time, being controlled by said
first node, said fifth transistor turning on, being controlled by said second node, said fourth transistor and said sixth
transistor turning on, said third node being high.

US Pat. No. 9,898,984

GOA CIRCUIT, DISPLAY DEVICE AND DRIVE METHOD OF GOA CIRCUIT

Shenzhen China Star Optoe...

1. A GOA circuit, applied to drive a display device, wherein the GOA circuit comprises a plurality of levels of GOA units,
a N level of the GOA units is applied to charge a N leveled scanning line of a display region of the display device, the N
leveled scanning line is connected to a first gate all on signal and a second gate all on signal, which is applied to guarantee
scanning lines corresponding to all the GOA units are being charged under control of the first gate all on signal and the
second gate all on signal, where N is a positive integer that is larger than or equal to 1;
wherein the N leveled GOA unit comprises a N leveled pull-up control module, a N leveled pull-up module, a N leveled pull-down
module and a N leveled pull-down maintenance module;

an output terminal of the N leveled pull-up control module is connected to a N leveled grid signal location;
an input terminal of the N leveled pull-up module is connected to the N leveled grid signal location, a control terminal of
the N leveled pull-up module receives a first clock signal, an output terminal of the N leveled pull-up module is connected
to the N leveled scanning line;

an input terminal of the N leveled pull-down module and a N leveled pull-down gate all on signal location are connected, a
control terminal of the N leveled pull-down module receives a first voltage signal, an output terminal of a N leveled pull-down
module is connected to the N leveled grid signal location and the N leveled scanning line respectively;

a control terminal of the N leveled pull-down maintenance module receives a second clock signal or a third clock signal, an
output terminal of the N leveled pull-down maintenance module is connected to the N leveled pull-down gate all on signal location;

wherein the N leveled pull-up control module outputs a pull-up gate all on signal to the N leveled grid signal location, which
leads to the pull-up module outputs the first clock signal to the N leveled scanning line responding to the pull-up gate all
on signal, after charging the N leveled scanning line responding to the first clock signal, the N leveled pull-down maintenance
module outputs the second clock signal or the third clock signal to the N leveled pull-down gate all on signal location, hence
the pull-down module transmits the first voltage signal to the N leveled grid signal location and the N leveled scanning line
respectively, which can turn off the N leveled scanning line, and the N leveled pull-down maintenance module continues to
respond to the second clock signal or the third clock signal and maintain the N leveled scanning line turned off.