US Pat. No. 9,282,646

INTERPOSED SUBSTRATE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. An interposed substrate comprising:
an insulating material layer having an upper surface and a lower surface opposite to each other, and a plurality of first
through holes and a plurality of second through holes, wherein the first through holes and the second through holes penetrate
through the insulating material layer, and a diameter of each of the first through holes is smaller than a diameter of each
of the second through holes;

a plurality of conductive pillars respectively disposed within the first through holes of the insulating material layer, wherein
each conductive pillar has a top surface and a bottom surface opposite to each other, and the top surface of each conductive
pillar and the upper surface of the insulating material layer are coplanar;

a patterned conductor layer disposed within the second through holes of the insulating material layer, wherein the conductive
pillars are separated from each other and stacked on the patterned conductor layer, and a bottom surface of the patterned
conductor layer and the lower surface of the insulating material layer are not aligned; and

a dielectric layer disposed on the upper surface of the insulating material layer, wherein the dielectric layer directly covers
the upper surface of the insulating material layer and the top surfaces of the conductive pillars.

US Pat. No. 9,161,454

ELECTRICAL DEVICE PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME

Unimicron Technology Corp...

1. An electrical device package structure comprising:
a dielectric layer having a first surface, a second surface opposite to the first surface, a first caving pattern disposed
on the first surface and caved into the first surface, at least one second caving pattern disposed on the second surface and
caved into the second surface and at least one through hole extended from the first caving pattern to the second caving pattern;

an electrical device embedded in the dielectric layer and having at least one electrode and the electrode exposing the second
caving pattern;

a first conductive pattern filled in the first caving pattern;
a second conductive pattern filled in the second caving pattern and connected with the electrode of the electrical device;
a conductive via filled in the through hole and connected with the first conductive pattern and the second conductive pattern;
a first solder mask disposed on the first surface and the first conductive pattern of the dielectric layer, and exposing portions
of the first conductive pattern, wherein a surface of the electrical device directly contacted with the first solder mask
and a surface of the first conductive pattern directly contacted with the first solder mask are located in a single plane;
and

a second solder mask disposed on the second surface and the second conductive pattern of the dielectric layer, and exposing
portions of the second conductive pattern.

US Pat. No. 9,131,614

METHOD OF MANUFACTURING AN EMBEDDED WIRING BOARD

UNIMICRON TECHNOLOGY CORP...

1. A method for manufacturing an embedded wiring board, comprising:
providing an activating insulation layer (210) comprising a plurality of catalyst particles (216) substantially evenly distributed in a high molecular weight compound (218), wherein the activating insulating layer has a first wiring layer (220a) exposedly embedded in a lower surface thereof;

forming an intaglio pattern on a upper surface of the activating insulating layer and at least one blind via that partially
exposes the first wiring layer through the intaglio pattern, wherein some of the catalyst particles are activated and exposed
in the intaglio pattern and the blind via;

dipping the activating insulation layer in a first chemical plating solution for forming a solid conductive pillar in the
blind via through electroless plating; and

dipping the activating insulation layer in a second chemical plating solution after forming the solid conductive pillar for
forming a second wiring layer (230) in the intaglio pattern through electroless plating,

wherein solutes of the first chemical plating solution and the second chemical plating solution are different.

US Pat. No. 9,370,099

MANUFACTURING METHOD OF CONNECTOR

UNIMICRON TECHNOLOGY CORP...

1. A manufacturing method of connector, comprising the following steps:
providing a substrate layer and forming a first metal layer on the substrate layer;
patterning the first metal layer to form a wiring layer;
forming a dielectric layer on the wiring layer, wherein the dielectric layer is formed with at least one via hole to partially
expose the wiring layer and a conductive structure arranged on the inner wall of the at least one via hole and electrically
connected to the wiring layer;

forming a first protective layer on the dielectric layer and at least one cantilever structure between the first protective
layer and the dielectric layer, wherein the at least one cantilever structure is electrically connected to the wiring layer
via the conductive structure; and

removing the substrate layer.

US Pat. No. 9,237,643

CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A circuit board structure, comprising:
a core layer with surface material thereof being dielectric material, having a first surface and a corresponding second surface;
a fine circuit pattern, embedded in the first surface of the core layer;
a patterned conductive layer, disposed on the second surface of the core layer and protrudes from the second surface of the
core layer;

at least a conductive through via penetrating the core layer and connecting the fine circuit pattern to the patterned conductive
layer, wherein the conductive through via has a shape of hollow cylinder or solid cylinder; and

a first solder mask, disposed on the first surface of the dielectric layer and the fine circuit pattern, wherein the fine
circuit pattern has at least a first joint pad, and the first solder mask exposes the first joint pad.

US Pat. No. 9,084,379

PROCESS FOR FABRICATING WIRING BOARD

UNIMICRON TECHNOLOGY CORP...

1. A process for fabricating a wiring board, comprising:
forming a first wiring carrying substrate including a first carry substrate and a first wiring layer disposed on the first
carry substrate;

forming at least a first blind via in the first wiring carrying substrate, wherein the first blind via extends from the first
wiring layer into the first carry substrate;

laminating the first wiring carrying substrate to a second wiring carrying substrate via an insulation layer, wherein the
second wiring carrying substrate includes a second carry substrate and a second wiring layer disposed on the second carry
substrate, the insulation layer is disposed between the first wiring layer and the second wiring layer, and full fills the
first blind via;

removing a part of the first carry substrate and a part of the second carry substrate to expose the insulation layer in the
first blind via;

removing a part of the insulation layer in the first blind via to form a hole extending from the first wiring layer to the
second wiring layer;

forming a conductive pillar in the hole, wherein the conductive pillar is connected between the first wiring layer and the
second wiring layer; and

removing the remained first carry substrate and the remained second carry substrate.

US Pat. No. 9,408,313

PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A packaging substrate, comprising:
a substrate body having a first surface and a second surface opposite to the first surface, the first surface having a plurality
of first conductive pads thereon, and the second surface having a die attach area and a peripheral area surrounding the die
attach area, the die attach area having a plurality of second conductive pads embedded therein, wherein top surfaces of the
second conductive pads are exposed from the second surface, and the die attach area of the second surface is fully exposed;
and

a plurality of conductive pillars correspondingly disposed on the second conductive pads and having first ends and opposite
second ends, wherein the first ends are level with the second surface of the substrate body, and the first ends have a width
bigger than a width of the second ends.

US Pat. No. 9,074,051

DIANHYDRIDE MONOMER HAVING SIDE CHAIN, POLYIMIDE COMPOUND HAVING SIDE CHAIN AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A dianhydride monomer having side chain, comprising the formula is listed as formula (I) below:

wherein R is a cycloalkane group with at least one tertiary carbon atom.

US Pat. No. 9,179,549

PACKAGING SUBSTRATE HAVING EMBEDDED PASSIVE COMPONENT AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A packaging substrate having at least an embedded passive component, comprising:
a core board having at least a cavity;
a single-material dielectric layer unit having an upper surface and a lower surface, and encapsulating the core board and
filling the cavity of the core board;

a plurality of positioning pads embedded in the lower surface of the dielectric layer unit;
at least a passive component having upper and lower surfaces each having a plurality of electrode pads disposed thereon, the
passive component being embedded in the dielectric layer unit so as to be received in the cavity of the core board at a position
corresponding to the positioning pads;

a first wiring layer disposed on the upper surface of the dielectric layer unit and electrically connected to the electrode
pads of the upper surface of the passive component through a plurality of first conductive vias; and

a second wiring layer disposed on the lower surface of the dielectric layer unit and electrically connected to the electrode
pads of the lower surface of the passive component through a plurality of second conductive vias,

wherein the second conductive vias penetrate the positioning pads, respectively, and
the dielectric layer unit encapsulates the positioning pads and the passive component.

US Pat. No. 9,095,083

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method for a multi-layer circuit board, comprising:
providing a substrate having a first via penetrating the substrate;
forming a first patterned circuit layer on a surface of the substrate by using the first via as an alignment target, and the
first patterned circuit layer including a first concentric-circle pattern surrounding the first via;

forming a first stacking layer on the surface and covering the first patterned circuit layer, and the first stacking layer
including a first dielectric layer and a first circuit layer covering the first dielectric layer;

forming a first through hole, and the first through hole penetrating regions where an inner diameter of a first concentric
circle from a center of the first concentric-circle pattern is orthogonally projected on the first stacking layer and the
substrate;

forming a second stacking layer on the first stacking layer, and the second stacking layer including a second dielectric layer
and a second circuit layer covering the second dielectric layer; and

forming a second through hole, and the second through hole penetrating regions where an inner diameter of a second concentric
circle from the center of the first concentric-circle pattern is orthogonally projected on the second stacking layer, the
first stacking layer and the substrate.

US Pat. No. 9,510,464

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:
providing a circuit substrate having a first surface and at least a first circuit;
forming a dielectric layer on the circuit substrate, the dielectric layer having a second surface and covering the first surface
and the at least a first circuit;

irradiating the dielectric layer by a laser beam to form a first intaglio pattern, a second intaglio pattern, and at least
a blind via extending from the second surface of the dielectric layer to the at least a first circuit of the circuit substrate;

forming a first conductive layer in the first intaglio pattern, the second intaglio pattern, and the at least a blind via,
wherein the first conductive layer fills the first intaglio pattern and is disposed on an inner wall of the second intaglio
pattern and an inner wall of the at least a blind via, and an entire volume of the first intaglio pattern is full of the first
conductive layer;

forming a barrier layer in the second intaglio pattern and the at least a blind via, the barrier layer covering the first
conductive layer;

forming a second conductive layer in the second intaglio pattern and the at least a blind via, the second conductive layer
covering the barrier layer; and

removing parts of the second conductive layer, parts of the barrier layer, and parts of the first conductive layer until the
second surface of the dielectric layer is exposed to form a patterned circuit structure, the patterned circuit structure being
located in the first intaglio pattern, the second intaglio pattern, and the at least a blind via and being electrically connected
to the at least a first circuit of the circuit substrate.

US Pat. No. 9,320,143

TOUCH MEMBER AND METHOD OF MANUFACTURING THE SAME

Unimicron Technology Corp...

1. A wiring board comprising:
a substrate having opposing first and second surfaces, the substrate having at least one through-via passing through the substrate
from the first surface to the second surface;

a first conductor layer formed on the first surface;
a second conductor layer formed on the second surface; and
a through-via conductor formed in the through-via for electrically connecting to the first conductor layer and the second
conductor layer;

wherein the through-via has a first depressed portion exposed in the first surface, a second depressed portion exposed in
the second surface, and a cylindrical tunnel portion having a substantially constant internal diameter between the first depressed
portion and the second depressed portion for connecting the first depressed portion and the second depressed portion,

wherein the first depressed portion and the second depressed portion are non-coaxial, and the internal diameter of the tunnel
portion is less than a diameter of the first depressed portion in the first surface and a diameter of the second depressed
portion in the second surface;

wherein a bore axis of the first depressed portion and a bore axis of the second depressed portion slant toward each other
at an angle, which is in a range of 5 to 70 degrees, said bore axis of the second depressed portion is substantially perpendicular
to said second surface of said substrate; and

wherein the first depressed portion has a first opening in the first surface, the second depressed portion has a second opening
in the second surface, and a vertical projection of a center point of the first opening on the second surface and a center
point of the second opening are offset from each other by a distance in a range of 5 micrometer to 40 micrometers.

US Pat. No. 9,045,597

POLYIMIDE COMPOUND HAVING SIDE CHAIN AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of polyimide compound having side chain, comprising:
(A) dissolving diamine monomer (a) and dianhydride monomer (b) into cresol by stirring under anhydrous condition to form polyamic
acid compound (c) solution,

wherein the general formula of diamine monomer (a) is shown as formula (V) below:

wherein the general formula of dianhydride monomer (b) is shown as formula (X) below:

wherein the general formula of polyamic acid compound (c) is shown as formula(XII) below

wherein R and R? comprises aromatic hydrocarbon or alicyclic hydrocarbon,
wherein the reaction temperature is 20 to 30, the reaction time is 6 to 7 hours;
(B) adding 5-10 drops of isoquinoline into polyamic acid compound solution, and heating refluxing the solution to form polyimide
compound solution,

wherein the reaction temperature is 100 to 200, the reaction time is 8 to 12 hours; and
(C) cooling polyimide compound (d) solution and adding polyimide compound solution (d) into ethanol to precipitate out solid
polyimide compound (d),

wherein the general formula of polyimide compound (d) is shown as formula (I) below:

(D) heating refluxing solid polyimide compound (d) and ethanol,
wherein the reaction temperature is 70 to 80, the reaction time is 4 to 6 hours.

US Pat. No. 9,380,706

METHOD OF MANUFACTURING A SUBSTRATE STRIP WITH WIRING

Unimicron Technology Corp...

1. A manufacturing method for a substrate strip with a wiring, comprising:
cutting a substrate panel to form a plurality of separated wiring blocks, wherein each of the wiring blocks comprises at least
one wiring board unit, and each of the wiring board units comprises an insulating layer and a wiring layer disposed on the
insulating layer;

testing the wiring blocks to determine whether the wiring blocks are normal or abnormal;
establishing an adhesive layer on a carrying substrate, the adhesive layer having a composition that generates an stronger
adhesion force with respect to the carrying substrate than with respect to the insulating layer; and

after the step of testing the wiring blocks, selectively disposing the normal wiring blocks on the adhesive layer, wherein
the adhesive layer is arranged between the disposed normal wiring blocks and the carrying substrate, wherein the adhesive
layer adheres to and directly contacts the wiring layer of each of the normal wiring blocks so that the wiring layer is embedded
in the adhesive layer and when the adhesive layer is separated from the normal wiring blocks, the adhesive layer is maintained
in contact with on the carrying substrate.

US Pat. No. 9,084,342

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:
providing a substrate, wherein the substrate has a pre-removing area, and the substrate comprises:
a first dielectric layer;
a first laser resistant structure, disposed on a first surface of the first dielectric layer and located at a periphery of
the pre-removing area;

a second dielectric layer, disposed on the first dielectric layer and covering the first laser resistant structure;
a circuit layer, disposed on a second surface of the second dielectric layer, wherein a portion of the circuit layer is extended
from outside of the pre-removing area into the pre-removing area;

a second laser resistant structure, disposed on the second surface, located at the periphery of the pre-removing area, and
insulated from the circuit layer, wherein there is at least one gap between the second laser resistant structure and the circuit
layer, and a vertical projection of the gap on the first surface overlaps the first laser resistant structure;

a third dielectric layer, disposed on the second dielectric layer, and covering the circuit layer and the second laser resistant
structure;

performing a laser machining process to etch the third dielectric layer located at the periphery of the pre-removing area;
removing a portion of the third dielectric layer located within the pre-removing area; and
performing an etching process or a mechanical processing to remove the second laser resistant structure.

US Pat. No. 9,288,917

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD

Unimicron Technology Corp...

1. A method for manufacturing a multi-layer circuit board, comprising:
providing a substrate, the substrate comprising two surfaces opposite to each other and a first via connecting the surfaces;
forming a first patterned circuit layer on each of the surfaces by using the first via as an alignment target, wherein each
of the first patterned circuit layers comprises a first concentric-circle pattern surrounding the first via;

forming a first stacking layer on each of the surfaces, the first stacking layer comprising a first dielectric layer and a
first circuit layer covering the first dielectric layer;

forming a first through hole, the first through hole penetrating regions of the first stacking layers and the substrate where
an inner diameter of a first concentric circle from a center of the first concentric-circle pattern is orthogonally projected
on;

forming a second stacking layer on each of the first stacking layers, each of the second stacking layers comprising a second
dielectric layer and a second circuit layer covering the second dielectric layer; and

forming a second through hole penetrating regions of the second stacking layers, the first stacking layers, and the substrate
where an inner diameter of a second concentric circle from the center of the first concentric-circle pattern is orthogonally
projected.

US Pat. No. 9,485,874

PACKAGE SUBSTRATE HAVING PHOTO-SENSITIVE DIELECTRIC LAYER AND METHOD OF FABRICATING THE SAME

Industrial Technology Res...

1. A package substrate, comprising:
an interposer having a first side and a second side opposite to the first side;
at least one conductive through via penetrating from the first side to the second side;
a redistribution layer formed on the first side and electrically connected to the conductive through via;
a photo-sensitive dielectric layer formed on the second side of the interposer;
a molding layer formed to encapsulate the interposer, wherein a bottom surface of the molding layer is aligned with an end
of the conductive through via, and the photo-sensitive dielectric layer directly covers the molding layer and the interposer;
and

at least one conductive via formed in the photo-sensitive dielectric layer and electrically connected to the conductive through
via, wherein the conductive via is in direct physical and electrical contact with the conductive through via,

wherein the photo-sensitive dielectric layer is photo-sensitive polyimide (PSPI).

US Pat. No. 9,460,992

PACKAGING SUBSTRATE HAVING A THROUGH-HOLED INTERPOSER

Unimicron Technology Corp...

1. A packaging substrate, comprising:
an interposer having opposing first and second surfaces and a plurality of conductive gels interconnecting the first surface
and the second surface, wherein each of the conductive gels has opposing first and second ends, such that the first end protrudes
from the first surface of the interposer, and a circuit redistribution structure is disposed on the second surface of the
interposer and electrically connected to the second ends of the conductive gels;

an encapsulating layer that encapsulates and is in direct contact with side surfaces and the first surface of the interposer;
and

a circuit built-up structure disposed on the encapsulating layer above the first surface of the interposer and electrically
connected to the first ends of the conductive gels.

US Pat. No. 9,374,896

PACKAGING CARRIER AND MANUFACTURING METHOD THEREOF AND CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A packaging carrier, comprising: an interposer, having a first surface and a second surface opposite to each other, and
a plurality of first pads and second pads located on the first surface and the second surface, respectively;
a dielectric layer, having a third surface and a fourth surface opposite to each other, wherein the interposer is embedded
in the dielectric layer, the second surface of the interposer is not covered by the fourth surface of the dielectric layer
and has a height difference with the fourth surface; and

a built-up structure, disposed on the third surface of the dielectric layer and electrically connected to the first pads of
the interposer, wherein the built-up structure only comprises a first circuit layer, at least an insulating layer, at least
a second circuit layer, a plurality of first conductive vias and a plurality of second conductive vias, the first circuit
layer is disposed on the third surface of the dielectric layer, and the first circuit layer is electrically connected to the
first pads of the interposer through the first conductive vias, the insulating layer covers the first circuit layer and the
third surface of the dielectric layer, the second circuit layer is disposed on a surface of the insulating lager relatively
away from the third surface, the second conductive vias penetrate the insulating layer and electrically connect the first
circuit layer and the second circuit layer, and the dielectric layer only covers a portion of the built-up structure by the
third surface of the dielectric layer; wherein the interposer comprises a plurality of through vias, and each through via
is filled with a conductive material and electrically connects the corresponding first pad and the corresponding second pad;
and wherein the interposer comprises a first interposer layer, a second interposer layer and a third interposer layer, the
first interposer layer is located between the second interposer layer and the third interposer layer, and the through vias
at least comprises a plurality of first through vias passing through the first interposer layer and filled with the conductive
material, two surfaces opposite to each other of the first interposer layer are aligned with two ends of each of the first
through vias filled with the conductive material, and the second interposer layer and the third interposer layer respectively
have the first surface and the second surface, and a material of the first interposer layer comprises silicon, glass or ceramic;

materials of the second interposer layer and the third interposer layer are selected from glass, ceramic, polyimide (PI),
polybenzoxazole (PBO) fiber, bis-benzocyclobuten (BCB), silicones, acrylates or epoxy.

US Pat. No. 9,247,631

METHOD FOR FABRICATING HEAT DISSIPATION SUBSTRATE

Unimicron Technology Corp...

1. A method for fabricating a heat dissipation substrate comprising:
providing a first composite board, wherein the first composite board comprises two metal conductive layers and a resin carrier,
wherein the resin carrier is positioned between the two metal conductive layers;

laminating second and third composite boards outside the two metal conductive layers, wherein each of the second and third
composite boards comprises an insulation layer and a thin metal layer, wherein the insulation layers are positioned between
the two metal conductive layers and the thin metal layers of the second and third composite boards;

thickening each of the thin metal layers; and
removing the resin carrier for forming first and second substrates, wherein each of said metal conductive layer forms a first
conductive layer and each of said thin metal layers becomes thicker to form a metal layer in each of the first and second
substrates, and wherein the metal layer is thicker than the first conductive layer in each of the first and second substrates;
and

in each of the first and second substrates, removing part of the metal layer for forming a metal bulk;
providing an adhesive layer, wherein the adhesive layer comprises an opening, and wherein the opening corresponds to the metal
bulk;

providing a second conductive layer;
laminating the second conductive layer, the adhesive layer, and the substrate, wherein the adhesive layer is positioned above
the substrate, and wherein the second conductive layer is above the adhesive layer;

forming a hole in the insulation layer and the first conductive layer, wherein the hole is positioned under the metal bulk;
and

forming a third conductive layer in the hole.

US Pat. No. 9,159,713

OPTO-ELECTRONIC CIRCUIT BOARD AND METHOD FOR ASSEMBLING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. An optical component, comprising:
a base comprising a first via, a second via, a first surface, and a second surface opposite the first surface, wherein the
first via and the second via respectively penetrate the base from the first surface to the second surface;

a waveguide layer disposed on the first surface and comprising a bottom cladding layer, a top cladding layer, and a core layer
which is clad between the bottom cladding layer and the top cladding layer;

an emitting portion disposed at a side of the waveguide layer;
the emitting portion comprising:
a first inserting portion inserting into the first via;
a first light-guide hole aligning with the core layer of the waveguide layer, wherein the first inserting portion and the
first light-guide hole are one integral unit;

a first reflective layer disposed on an inner surface of the first light-guide hole; and
a light emitter aligning with the first light-guide hole and providing an optical signal entering to the core layer through
the first light-guide hole; and

a receiving portion disposed at the other side of the waveguide layer the receiving portion comprising:
a second inserting portion inserting into the second via;
a second light-guide hole aligning with the core layer of the waveguide layer, wherein the second inserting portion and the
second light-guide hole are one integral unit;

a second reflective layer disposed on an inner surface of the second light-guide hole; and
a light receiver aligning with the second light-guide hole, wherein the optical signal passes through the core layer and enters
the light receiver via the second light-guide hole.

US Pat. No. 9,253,898

RIGID FLEX BOARD MODULE AND THE MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A rigid flex board module, comprising:
a rigid flex circuit board, comprising:
a flexible circuit board including a bending portion and a jointing portion connected to the bending portion;
a first rigid circuit board disposed on the jointing portion and exposing the bending portion, and the first rigid circuit
board electrically connected to the flexible circuit board; and

a first adhesive layer connected between the first rigid circuit board and the jointing portion;
a high-density interconnected circuit board arranged in and electrically connected to the first rigid circuit board, wherein
the total number of layers of high-density interconnected circuit board is larger than the total number of layers of the flexible
circuit board;

at least one pair of multi-layer circuit layers respectively configured at two sides of the rigid flex circuit board and two
sides of the high-density interconnected circuit board; and

a plurality of conductive posts electrically connected to the pair of multi-layer circuit layers, the high-density interconnected
circuit board, and the first rigid circuit board.

US Pat. No. 9,484,223

CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A method of fabricating a coreless packaging substrate, comprising the steps of:
providing a carrier board having a plurality of electrical pads formed thereon;
forming a circuit buildup structure on the carrier board and the electrical pads, the circuit buildup structure having at
least a dielectric layer, at least a wiring layer formed on the at least a dielectric layer, and a plurality of conductive
elements formed in the dielectric layer and electrically connected to the at least a wiring layer, wherein the electrical
pads are embedded in a lowermost one of the at least a dielectric layer, so as for part of the conductive elements to be electrically
connected with the electrical pads;

forming a plurality of metal bumps on an uppermost one of the at least a wiring layer;
forming a dielectric passivation layer on an uppermost one of the at least a dielectric layer and the uppermost one of the
at least a wiring layer for covering the metal bumps;

removing a part of the dielectric passivation layer and a part of each of the metal bumps for each of the metal bumps to be
formed by a metal column portion and a wing portion integrally connected to the metal column portion, and for an entire top
surface of the wing portion of each of the metal bumps to be exposed from the dielectric passivation layer, so as for a semiconductor
chip to be electrically connected to the exposed wing portions of the metal bumps; and

removing the carrier board for exposing the electrical pads from the lowermost one of the at least a dielectric layer.

US Pat. No. 9,484,224

METHOD OF FABRICATING A CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A fabrication method of a circuit board structure, comprising the steps of:
providing a carrying board having a first and an opposite second surface and having at least one through cavity formed therein;
placing a semiconductor chip in the through cavity of the carrying board, wherein the semiconductor chip has an active surface
and an opposite inactive surface, and the active surface has a plurality of electrode pads thereon;

filling with an adhesive material in a gap between the through cavity of the carrying board and the semiconductor chip to
fix in position the semiconductor chip in the through cavity, wherein a surface of the adhesive material is flush with the
inactive surface of the semiconductor chip and the second surface;

forming a reinforcing layer on the second surface of the carrying board and the inactive surface of the semiconductor chip,
wherein the reinforcing layer is made of a thermoplastic resin different from a material of the carrying board; and

forming an opening in the reinforcing layer to expose a portion of the inactive surface of the semiconductor chip, wherein
a portion of the reinforcing layer is formed on the inactive surface of the semiconductor chip.

US Pat. No. 9,491,865

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board with a heat-recovery function, comprising:
a substrate having a top surface and a bottom surface which are opposite to each other;
a heat-storing device embedded in the substrate and connected to a processor for performing heat exchange with the processor;
and

a thermoelectric device embedded in the substrate, comprising:
a first metal-junction surface connected to the heat-storing device for performing heat exchange with the heat-storing device;
and

a second metal-junction surface joined with the first metal-junction surface, wherein the thermoelectric device generates
an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface,
wherein the substrate further comprises:

a first recess disposed at the top surface of the substrate, wherein the thermoelectric device is located in the first recess;
a second recess disposed at the bottom surface of the substrate, wherein the heat-storing device is located in the second
recess, the first recess and the second recess are opposite to each other, and at least one portion of the substrate is located
between the heat-storing device and the thermoelectric device;

at least one first via disposed at the portion of the substrate between the heat-storing device and the thermoelectric device;
and

a first heat-conducting pillar disposed in the first via, wherein the heat-storing device performs heat exchange with the
thermoelectric device through the first heat-conducting pillar.

US Pat. No. 9,258,908

SUBSTRATE STRUCTURE HAVING COMPONENT-DISPOSING AREA AND MANUFACTURING PROCESS THEREOF

Unimicron Technology Corp...

1. A substrate structure having a component-disposing area, comprising:
a core layer, comprising a first surface, a patterned metallic layer and a component-disposing area, wherein the patterned
metallic layer is disposed on the first surface and comprises a plurality of pads and the pads are located within the component-disposing
area;

a first dielectric-layer, disposed on the core layer and comprising a plurality of openings respectively exposing the pads;
a laser-resistant metallic pattern, disposed on and directly contacting the first dielectric layer and surrounding a projection
area of the first dielectric-layer which the component-disposing area orthogonally projected on; and

a second dielectric layer, disposed on the first dielectric layer and covering the laser-resistant metallic pattern, wherein
the second dielectric layer comprises a component-disposing cavity corresponding to the projection area, penetrating through
the second dielectric layer and communicated with the openings to expose the pads, and the component-disposing cavity exposing
a part of the laser-resistant metallic pattern surrounding the projection area.

US Pat. No. 9,198,303

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method for a multi-layer circuit board, comprising:
compressing two core layers to form a substrate having two surfaces opposite to each other;
forming a first via connecting through the two surfaces;
forming a first patterned circuit layer on each of the two surfaces by using the first via as an alignment target, and the
first patterned circuit layer including a first concentric-circle pattern surrounding the first via;

forming a first stacking layer on each of the two surfaces, and the first stacking layer including a first dielectric layer
and a first circuit layer covering the first dielectric layer;

forming a first through hole, and the first through hole penetrating regions where an inner diameter of a first concentric
circle from a center of the first concentric-circle pattern is orthogonally projected on the first stacking layers and the
substrate;

forming a second stacking layer on each of the first stacking layers, and the second stacking layer including a second dielectric
layer and a second circuit layer covering the second dielectric layer; and

forming a second through hole, and the second through hole penetrating regions where an inner diameter of a second concentric
circle from the center of the first concentric-circle pattern is orthogonally projected on the second stacking layers, the
first stacking layers and the substrate.

US Pat. No. 9,247,654

CARRIER SUBSTRATE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A carrier substrate, comprising:
a dielectric layer having a first surface and a second surface opposite to each other and a plurality of blind vias;
a first circuit layer embedded in the first surface of the dielectric layer and having an upper surface and a lower surface
opposite to each other, the upper surface exposed from the first surface of the dielectric layer, wherein the blind vias extend
from the second surface to the first circuit layer and expose a portion of the lower surface of the first circuit layer;

an insulation layer having a third surface and a fourth surface opposite to each other and disposed on the first surface of
the dielectric layer through the fourth surface and covers a portion of the upper surface of the first circuit layer, the
insulation layer having a plurality of first openings extending from the third surface to the fourth surface, wherein the
first openings expose another portion of the upper surface of the first circuit layer, an aperture of each first opening is
increased gradually from the third surface to the fourth surface, and the apertures of the first openings on the fourth surface
are greater than a width of the exposed first circuit layer;

a plurality of conductive blocks respectively disposed in the first openings of the insulation layer and connected with another
portion of the upper surface of the first circuit layer exposed by the first openings; and

a first conductive structure disposed on the second surface of the dielectric layer and comprising a plurality of conductive
vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

US Pat. No. 9,485,863

CARRIER AND METHOD FOR FABRICATING CORELESS PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A carrier, comprising:
a metal board; and
a metal layer formed on at least one surface of the metal board, wherein a bonding force between the metal layer and the metal
board in a central region is less than that in a peripheral region.

US Pat. No. 9,370,107

EMBEDDED COMPONENT STRUCTURE AND PROCESS THEREOF

Unimicron Technology Corp...

1. An embedded component structure, comprising: a wiring board having a front side, a reverse side opposite to the front side,
an opening and an interconnection layer, wherein the opening penetrates the wiring board and connects the front side and the
reverse side, and the interconnection layer is located on the front side and extends toward the opening; a component having
an active surface, a back surface opposite to the active surface, and a working area located on the active surface, wherein
the active surface is bonded to the interconnection layer, wherein the interconnection layer has a plurality of leads extending
to the opening, the component has a plurality of bonding pads located on the active surface, and the bonding pads are connected
to the leads through a plurality of conductive bumps respectively, wherein the component is located in the opening, and the
active surface and the front side of the wiring board face in a same direction; and an encapsulant filled inside the opening,
covering the component and exposing the working area.

US Pat. No. 9,491,871

CARRIER SUBSTRATE

Unimicron Technology Corp...

1. A carrier substrate, comprising:
a dielectric layer having a first surface and a second surface opposite to each other and a plurality of blind vias;
a first circuit layer embedded in the first surface of the dielectric layer and having an upper surface and a lower surface
opposite to each other, the upper surface exposed from the first surface of the dielectric layer, wherein the blind vias extend
from the second surface to the first circuit layer and expose a portion of the lower surface of the first circuit layer;

an insulation layer having a third surface and a fourth surface opposite to each other and disposed on the first surface of
the dielectric layer through the fourth surface and covers a portion of the upper surface of the first circuit layer, the
insulation layer having a plurality of first openings extending from the third surface to the fourth surface, wherein the
first openings expose another portion of the upper surface of the first circuit layer, an aperture of each first opening is
increased gradually from the third surface to the fourth surface, and the apertures of the first openings on the fourth surface
are greater than a width of the exposed first circuit layer;

a plurality of conductive blocks respectively disposed in the first openings of the insulation layer and connected with another
portion of the upper surface of the first circuit layer exposed by the first openings, wherein a top surface of each of the
conductive blocks is higher than the third surface of the insulation layer; and

a first conductive structure disposed on the second surface of the dielectric layer and comprising a plurality of conductive
vias filling the blind vias and a second circuit layer disposed on a portion of the second surface.

US Pat. No. 9,420,690

CONNECTOR

Unimicron Technology Corp...

1. A connector comprising:
a wiring layer;
a dielectric layer disposed on the wiring layer, wherein the dielectric layer has at least one via hole to partially expose
the wiring layer;

a conductive structure disposed on the inner wall of the via hole of the dielectric layer and electrically connected to the
wiring layer;

a first protective layer disposed on the dielectric layer; and
at least one cantilever structure disposed between the first protective layer and the dielectric layer, wherein the cantilever
structure is electrically connected to the wiring layer through the conductive structure.

US Pat. No. 9,184,520

ELECTRICAL CONNECTOR

Unimicron Technology Corp...

1. An electrical connector, suitable for contacting a contact and comprising:
a base, having a recess;
an elastic terminal, connected to the base and extending to the recess, wherein the elastic terminal has a fixed end and a
free end, the fixed end is connected to the base, and the free end is located at the recess and is curved; and

a contact protrusion, connected to the elastic terminal and located at the free end, wherein when the contact moves towards
the recess, the contact is capable of pushing the elastic terminal to bend towards a bottom surface of the recess so that
the free end leans against the bottom surface of the recess.

US Pat. No. 9,348,433

OPTICAL TOUCH SENSING STRUCTURE

Unimicron Technology Corp...

1. An optical touch sensing structure, comprising:
a transparent substrate; and
a plurality of optical particles with metallic composition, disposed on the transparent substrate, wherein when an infrared
is incident on each of the optical particles with metallic composition, the infrared is reflected by each of the optical particles
with metallic composition;

a transparent adhesive layer, disposed on the transparent substrate, wherein a refractive index of the transparent adhesive
layer is identical or similar to a refractive index of the transparent substrate, and the optical particles with metallic
composition are fixed on the transparent substrate by the transparent adhesive layer, the transparent adhesive layer completely
covers the transparent substrate and the optical particles with metallic composition are distributed in the transparent adhesive
layer;

a plurality of light absorbing portions, disposed on the transparent adhesive layer and exposing a portion of the transparent
adhesive layer; and

a transparent protective layer, disposed on the transparent adhesive layer and covering the light absorbing portions and the
portion of the transparent adhesive layer exposed by light absorbing portions, wherein a refractive index of the transparent
protective layer is identical or similar to the refractive index of the transparent substrate and identical or similar to
the refractive index of the transparent adhesive layer.

US Pat. No. 9,377,596

OPTICAL-ELECTRO CIRCUIT BOARD, OPTICAL COMPONENT AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. An optical component comprising:
a multi-layer substrate comprising at least one dielectric layer, at least two circuit layers, and two through holes passing
through the at least one dielectric layer, the at least two circuit layers being located on two opposite surfaces of the at
least one dielectric layer;

an optical waveguide element located on a surface of the multi-layer substrate and between the through holes; and
two optical-electro assemblies respectively inserted into the corresponding through holes and correspondingly located at two
opposite ends of the optical waveguide element, each of the optical-electro assemblies comprises an insertion element comprising
an insertion portion, and the insertion portion is inserted into the corresponding through hole, wherein one of the optical-electro
assemblies transforms an electrical signal into a light beam and provides the light beam to the optical waveguide element,
and other one of the optical-electro assemblies receives the light beam transmitted from the optical waveguide element and
transforms the light beam into another electrical signal.

US Pat. No. 9,368,442

METHOD FOR MANUFACTURING AN INTERPOSER, INTERPOSER AND CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A method of manufacturing an interposer, comprising:
providing a substrate, wherein the substrate has a first surface, a second surface opposite to the first surface, and a plurality
of blind vias recessed into the first surface;

filling the blind vias with a plurality of conductive beads, so that each of the blind vias has the plurality of conductive
beads, wherein each of the conductive beads comprises a metal ball and a solder layer enclosing the metal ball;

melting the solder layers, so as to form a plurality of solder posts in the blind vias, wherein the metal balls are inlaid
in the corresponding solder posts, and each of the solder posts and the metal balls inlaid therein construct a conductive
through via;

planarizing the first surface of the substrate, such that a first end, close to the first surface, of each of the conductive
through vias is flush with the first surface of the substrate;

removing a portion of the substrate from the second surface of the substrate till a second end, close to the second surface,
of each of the conductive through vias is exposed to the second surface of the substrate and is flush with the second surface
of the substrate;

after the first surface of the substrate is planarized, manufacturing a first redistribution layer at the first surface of
the substrate, wherein the first redistribution layer is electrically connected to the first end of each of the conductive
through vias; and

after the portion of the substrate is removed from the second surface of the substrate, manufacturing a second redistribution
layer at the second surface of the substrate, wherein the second redistribution layer is electrically connected to the second
end of each of the conductive through vias.

US Pat. No. 9,307,651

FABRICATING PROCESS OF EMBEDDED CIRCUIT STRUCTURE

Unimicron Technology Corp...

1. A fabricating process for an embedded circuit structure, comprising:
providing a core panel;
forming at least one through hole in the core panel, the through hole penetrating the entire thickness of the core panel;
forming a first indent pattern on a first major surface of the core panel;
forming a second indent pattern on a second major surface of the core panel, the second major surface being opposite to the
first major surface of the core panel;

electroplating a conductive material into the through hole, the first indent pattern and the second indent pattern, so as
to form a conductive channel in the through hole, a first circuit pattern in the first indent pattern, and a second circuit
pattern in the second indent pattern, wherein portions of the first circuit pattern exceed the first major surface, portions
of the second circuit pattern exceed the second major surface, and the electroplating process includes performing a chemical
electroplating process at first and then performing an electrolysis electroplating process; and

removing the portions of the first circuit pattern, which exceed the first major surface, for planarizing the first circuit
pattern to be level with the first major surface of the core panel, and removing the portions of the second circuit pattern,
which exceed the second major surface, for planarizing the second circuit pattern to be level with the second major surface
of the core panel.

US Pat. No. 9,324,664

EMBEDDED CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. An embedded chip package structure, comprising:
a core layer, wherein the core layer includes a first surface, a second surface opposite to the first surface and a chip container
passing through the first surface and the second surface;

a chip, disposed in the chip container, wherein the chip includes an active surface and a protrusion and a top surface of
the protrusion is a portion of the active surface;

a first circuit layer, disposed on the first surface and electrically connected to the core layer and the chip, wherein the
first circuit layer has a through hole, and a width of the through hole is smaller than a width of the chip container, so
that the first circuit layer covers the chip except the protrusion, wherein the protrusion of the chip extends into the through
hole and is located within the through hole, and the top surface of the protrusion is exposed to receive an external signal,
and a size of a projection of the through hole on the first surface is substantially equivalent to a size of a projection
of the protrusion on the first surface; and

a second circuit layer, disposed on the second surface and electrically connected to the core layer.

US Pat. No. 9,609,746

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:
providing an inner circuit structure, wherein the inner circuit structure comprises a core layer having an upper surface and
a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned
circuit layer disposed on the lower surface, and a conductive through hole connecting the first patterned circuit layer and
the second patterned circuit layer;

forming a metal pillar on a portion of the first patterned circuit layer;
performing a build-up process to press a first build-up circuit structure on the first patterned circuit layer, wherein the
first build-up circuit structure at least comprises an inner dielectric layer, and the inner dielectric layer directly covers
the upper surface of the core layer and the first patterned circuit layer;

using a contact distance detector to detect an upper surface of the metal pillar relatively far away the first patterned circuit
layer; and

using the upper surface of the metal pillar to serve as a depth reference surface, performing a hole drilling process on the
first build-up circuit structure to remove a portion of the first build-up circuit structure and at least a portion of the
metal pillar so as to form a cavity extending from a first surface of the first build-up circuit structure relatively far
way the inner circuit structure to a portion of the inner dielectric layer, wherein the cavity exposes an inner surface of
the inner dielectric layer, and the inner dielectric layer has an opening connecting the cavity and exposing a portion of
the first patterned circuit layer, a hole diameter of the opening is smaller than a hole diameter of the cavity, and a height
difference is in between an inner surface of the inner dielectric layer exposed by the cavity and a top surface of the first
patterned circuit layer exposed by the opening.

US Pat. No. 9,111,818

PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A packaging substrate, comprising:
a substrate body having a plurality of conductive pads disposed on a surface thereof;
an insulating protective layer formed on the surface of the substrate body and having openings for the conductive pads to
be exposed therefrom; and

conductive pillars disposed on end surfaces of the conductive pads exposed from the openings and having first ends, opposite
second ends, and side surfaces adjacent to the first ends and the second ends, the first ends being closer than the second
ends from the conductive pads, and the first ends having a width bigger than a width of the second ends, wherein the side
surfaces are arc concave toward centers of the conductive pillars.

US Pat. No. 9,385,056

PACKAGING SUBSTRATE HAVING EMBEDDED INTERPOSER AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A fabrication method of a packaging substrate having an embedded interposer, comprising the steps of:
preparing a multi-layer interconnect base plate having opposite third and fourth surfaces, wherein the third surface has a
plurality of first conductive terminals disposed thereon;

forming a built-up structure on the third surface of the multi-layer interconnect base plate;
removing a portion of the built-up structure through a laser so as to form a cavity and expose the plurality of first conductive
terminals from the cavity, thereby providing a carrier having opposite top and bottom surfaces, wherein the carrier comprises
the multi-layer interconnect base plate and the built-up structure having a recess, the recess is formed on the top surface
of the carrier and the plurality of first conductive terminals are formed on the recess, and a plurality of second conductive
terminals are formed on the bottom surface of the carrier for electrically connecting the carrier and an external electronic
device; and

disposing in the recess an interposer having opposite first and second surfaces and a plurality of conductive through vias
penetrating the first and second surfaces, wherein a first conductive pad is formed on an end of each of the conductive through
vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through
vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals.

US Pat. No. 9,070,616

METHOD OF FABRICATING PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate, comprising:
providing a carrier board having two opposite surfaces, on which a plurality of first conductive pads disposed for semiconductor
chips to be disposed on the first respective conductive pads;

forming first metal bumps on the first conductive pads, each of the first metal bumps having a first end and an opposite second
end, wherein the second end is disposed on one of the first conductive pads;

covering the surfaces of the carrier board, the first conductive pads and the first metal bumps with a first dielectric layer
that has a plurality of first intaglios for exposing top and side surfaces of the first ends of the first metal bumps, respectively;

forming a conductive seedlayer on the first dielectric layer and the first ends of the first metal bumps;
forming a metal layer on the conductive seedlayer;
removing a portion of the metal layer and the conductive seedlayer that is over a top surface of the first dielectric layer,
and forming a first circuit layer in the first intaglios;

forming a built-up structure on the first circuit layer and the first dielectric layer, an outermost layer of the built-up
structure having second conductive pads for an external electronic device to be disposed on the second conductive pads; and

removing the carrier board.

US Pat. No. 9,210,815

METHOD OF MANUFACTURING EMBEDDED WIRING BOARD

Unimicron Technology Corp...

1. A manufacturing method of an embedded wiring board, comprising:
providing an insulation layer and a lower wiring layer, wherein the insulation layer includes a polymeric material, the insulation
layer is provided with an upper surface and a lower surface opposite to the upper surface, the lower wiring layer is located
at the lower surface and includes a lower pad which is embedded in the lower surface;

distributing a plural catalyst grains in the polymeric material;
forming a groove and an engraved pattern on the upper surface, wherein a depth of the groove relative to the upper surface
is larger than a depth of the engraved pattern relative to the upper surface;

fondling a blind via on a bottom surface of the groove to expose the lower pad;
exposing and activating some catalyst grains in the groove, the engraved pattern, and the blind via;
forming an upper wiring layer in the engraved pattern;
forming a first conductive pillar in the groove; and forming a second conductive pillar in the blind via, wherein the second
conductive pillar is connected between the first conductive pillar and the lower pad.

US Pat. No. 9,257,379

CORELESS PACKAGING SUBSTRATE AND METHOD OF FABRICATING THE SAME

Unimicron Technology Corp...

1. A coreless packaging substrate, comprising:
a circuit buildup structure having at least a dielectric layer, at least a wiring layer formed on the at least a dielectric
layer, and a plurality of conductive elements formed in the dielectric layer and electrically connected to the at least a
wiring layer;

a plurality of electrical pads embedded in a lowermost one of the at least a dielectric layer for electrically connecting
part of the conductive elements, wherein the electrical pads are exposed from a surface of the lowermost one of the at least
a dielectric layer;

a plurality of copper bumps formed on an uppermost one of the at least a wiring layer, and each having a copper column portion
and a copper wing portion integrally formed on the copper column portion, wherein the copper wing portion of each of the copper
bumps is greater in diameter than the copper column portion; and

a dielectric passivation layer formed on an uppermost one of the at least a dielectric layer, the uppermost one of the at
least a wiring layer, and the copper bumps, with an entire top surface of the copper wing portion of each of the copper bumps
exposed from the dielectric passivation layer,

wherein the exposed top surface of the copper wing portion of each of the copper bumps directly contacts and is electrically
connected with solder bumps of a semiconductor chip,

the dielectric passivation layer is the same in width as the uppermost one of the at least a dielectric layer, and
the copper bumps are free from protruding from the dielectric passivation layer.

US Pat. No. 9,230,899

PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A packaging substrate, comprising:
a holder including an insulating layer, copper layers formed on opposite sides of the insulating layer, a dielectric layer
formed on one of the copper layers, a first metal stripping layer formed on the dielectric layer, and a second metal stripping
layer attached to the first metal stripping layer, wherein the first metal stripping layer and the second metal stripping
layer are full-sheeted and separable from each other;

a plurality of first conductive pads formed on the second metal stripping layer;
a core layer formed on the second metal stripping layer and the first conductive pads and having a first surface and a second
surface opposite to the first surface, wherein the first conductive pads are embedded in the first surface of the core layer;

a circuit layer formed on the second surface of the core layer and having a plurality of conductive vias formed in the core
layer and electrically connected to the first conductive pads, the circuit layer having a plurality of second conductive pads;
and

an insulating protection layer formed on and being in direct contact with the second surface of the core layer and the circuit
layer and having a plurality of openings, from which the second conductive pads are correspondingly exposed.

US Pat. No. 9,514,629

VEHICLE DOOR OPENING WARNING SYSTEM AND VEHICLE DOOR OPENING WARNING METHOD

Unimicron Technology Corp...

1. A vehicle door opening warning system, comprising:
a control unit, disposed at a door of a vehicle;
a projection unit, disposed at the door and electrically coupled to the control unit; and
a detection unit, disposed outside of the vehicle, electrically coupled to the control unit, and producing a signal when the
detection unit detects a moving object existing within 5 to 30 meters of the vehicle, wherein the control unit receives the
signal and controls the projection unit to project a warning message according to the signal, wherein the projection unit
comprises:

a steering element; and
a projection lens, rotatably disposed at the door through the steering element, to turn the projection lens towards a predetermined
projection area for projecting the warning message onto the predetermined projection area.

US Pat. No. 9,433,108

METHOD OF FABRICATING A CIRCUIT BOARD STRUCTURE HAVING AN EMBEDDED ELECTRONIC ELEMENT

Unimicron Technology Corp...

1. A method for fabricating a circuit board structure having at least an embedded electronic element, comprising the steps
of:
providing a substrate having opposite first and second surfaces and embedding at least an electronic element in the substrate,
wherein the electronic element has a first active surface having a plurality of first electrode pads and a second active surface
opposite to the first active surface and having a plurality of second electrode pads, the first active surface and the first
electrode pads of the electronic element being exposed from the first surface of the substrate;

forming a plurality of first conductive bumps on the first electrode pads of the electronic element; and
after the plurality of first conductive bumps are formed on the first electrode pads of the electronic element, covering the
first surface of the substrate and the first active surface of the electronic element with a first dielectric layer and a
first metal layer stacked on the first dielectric layer, wherein the first conductive bumps penetrate the first dielectric
layer so as to be in contact with the first metal layer.

US Pat. No. 9,129,870

PACKAGE STRUCTURE HAVING EMBEDDED ELECTRONIC COMPONENT

Unimicron Technology Corp...

1. A package structure having an embedded electronic component, comprising:
a carrier having a cavity penetrating therethrough and a metal layer disposed at one side of the carrier for covering one
end of the cavity;

a semiconductor chip having opposite active and non-active surfaces and received in the cavity of the carrier with its non-active
surface attached to the metal layer, wherein the active surface of the semiconductor chip has a plurality of electrode pads
formed thereon, and each of the electrode pads has a solder bump disposed thereon;

a dielectric layer formed on the carrier and the semiconductor chip for encapsulating the solder bumps and filling up a spacing
between the semiconductor chip and the cavity of the carrier;

a wiring layer formed on the dielectric layer and having a plurality of conductive pads and a plurality of conductive vias
formed in the dielectric layer for electrically connecting the solder bumps; and

an insulating protection layer formed on the dielectric layer and the wiring layer and having a plurality of openings formed
therein for exposing the conductive pads.

US Pat. No. 9,230,895

PACKAGE SUBSTRATE AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A fabrication method of a plurality of single-wiring-layer package substrates, comprising the steps of:
providing a carrier board having two opposite surfaces each having a first metal layer and a second metal layer sequentially
formed thereon;

forming a separate wiring layer on each of the second metal layers by electroplating, wherein each of the formed wiring layers
comprises solder pads, conductive pads, and circuit wires electrically connecting the solder pads and the conductive pads;

forming dielectric layers on the second metal layers and the wiring layers;
removing portions of the dielectric layers on the wiring layers so as to expose one surface of each of the wiring layers;
removing the carrier board and the first metal layers;
removing the second metal layers so as to expose the other surfaces of the wiring layers;
after the carrier board, the first metal layers, and the second metal layers are removed, forming on one surface of each of
the dielectric layers a first insulating protection layer to cover the dielectric layer and the corresponding wiring layer
to form the plurality of single-wiring-layer package substrates, and forming a plurality of first openings in the first insulating
protection layer for exposing the conductive pads, respectively; and

forming on the other surface of each of the dielectric layers a second insulating protection layer to cover the dielectric
layer and the corresponding wiring layer, and forming a plurality of second openings in the second insulating protection layer
for exposing the solder pads, respectively.

US Pat. No. 9,340,003

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:
providing a first core layer, a second core material layer, and a central dielectric material layer, wherein the first core
layer comprises a core dielectric layer and a core circuit layer, the core circuit layer is disposed on the core dielectric
layer and has a laser resistant pattern, the laser resistant pattern is located at a boundary of the pre-removing area, the
laser resistant pattern is a portion of the core circuit layer and is physically independent from the rest of the core circuit
layer, the second core material layer is disposed on the first core layer, and the central dielectric material layer is disposed
between the first core layer and the second core material layer;

pressing the first core layer, the second core material layer, and the central dielectric material layer to form a composite
circuit structure, wherein a pre-removing area is defined on the composite circuit structure, and at least a portion of the
core circuit layer is located within the pre-removing area;

removing a portion of the central dielectric material layer located at the boundary of the pre-removing area and a portion
of the second core material layer located at the boundary of the pre-removing area by laser etching; and

removing a portion of the central dielectric material layer located within the pre-removing area and a portion of the second
core material layer located within the pre-removing area to form a central dielectric layer and a second core layer.

US Pat. No. 9,335,470

OPTO-ELECTRONIC CIRCUIT BOARD AND METHOD FOR ASSEMBLING THE SAME

UNIMICRON TECHNOLOGY CORP...

5. An opto-electronic circuit board, comprising:
a circuit substrate comprising:
a first circuit layer;
a first cavity disposed on the first circuit layer;
a second cavity disposed on the first circuit layer and at a side of the first cavity; and
a third cavity disposed on the first circuit layer and at a side of the first cavity opposite the second cavity;
a waveguide disposed in the first cavity and comprising:
a base disposed on the first circuit layer;
a bottom cladding layer disposed on the base;
a top cladding layer disposed on the bottom cladding layer; and
a core layer which is clad between the bottom cladding layer and the top cladding layer;
an emitting component disposed in the second cavity, wherein the emitting component comprises:
a first inserting portion inserting into the second cavity;
a first light-guide hole aligning with the core layer of the waveguide;
a first conductive layer disposed on a surface of the emitting component and opposite the waveguide with connecting to the
first circuit layer; and

a light emitter disposed on the first circuit layer, wherein the light emitter provides an optic signal aligning with the
first light-guide such that the optic signal enters to the core layer through the first light-guide hole; and

a receiving component disposed in the third cavity, wherein the receiving component comprises:
a second inserting portion inserting into the third cavity;
a second light-guide hole aligning with the core layer of the waveguide;
a second conductive layer disposed on a surface of the receiving component and opposite the waveguide with connecting to the
first circuit layer; and

a light receiver disposed on the second conductive layer and aligning with the second light-guide hole for receiving the optic
signal, wherein the optic signal passes through the core layer and enters the light receiver via the second light-guide hole.

US Pat. No. 9,295,159

METHOD FOR FABRICATING PACKAGING SUBSTRATE WITH EMBEDDED SEMICONDUCTOR COMPONENT

Unimicron Technology Corp...

1. A method for fabricating a packaging substrate with an embedded semiconductor chip, comprising the steps of:
providing a carrier board and forming an assisting layer with a plurality of apertures on the carrier board, the apertures
being filled with a filling material;

providing the semiconductor chip having an active surface with a plurality of electrode pads thereon and an opposite inactive
surface;

forming a plurality of bumps on the electrode pads, respectively, wherein the bumps correspond in position to the apertures,
respectively, and are attached to the filling material in the apertures, thereby allowing the semiconductor chip to be coupled
to the assisting layer;

filling an adhesive member between the assisting layer and the semiconductor chip so as to encapsulate the bumps and the electrode
pads;

forming a first dielectric layer on the assisting layer so as to encapsulate the semiconductor chip, the first dielectric
layer having a first surface for coupling to the assisting layer and an opposite second surface;

removing the carrier board for exposing the assisting layer;
removing the filling material and the bumps so as to form vias; and
forming in each of the vias a first conductive via for electrical connection with a corresponding one of the electrode pads.

US Pat. No. 9,232,665

METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A PASSIVE ELEMENT EMBEDDED THEREIN

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate having a passive element embedded therein, comprising:
providing a carrier board having two surfaces, each of which has a release film and a metal layer sequentially;
forming positioning pads on the metal layers;
encapsulating the metal layers disposed on the two surfaces of the carrier board with a first thermalplastic dielectric layer;
providing at least a passive element having a plurality of electrode pads formed on an upper surface and a lower surface of
the passive element, and disposing the at least a passive element on the first thermalplastic dielectric layer, with the positioning
pads as positioning sites;

providing a second thermalplastic dielectric layer that is stacked above the first thermalplastic dielectric layer and the
at least a passive element;

heating and compressing the first and second thermalplastic dielectric layers, to form two dielectric layer units, each of
which has top and bottom surfaces, wherein the at least a passive element is embedded in the dielectric layer unit, and the
positioning pads are embedded in the bottom surface of the dielectric layer unit;

removing the carrier board and the release film, so as to separate the two dielectric layer units; and
forming first and second circuit layers on the top and bottom surfaces of the dielectric layer units, wherein the first circuit
layer is formed with a plurality of first conductive vias electrically connected to the electrode pads formed on the upper
surface of the at least a passive element, and the second circuit layer is formed with a plurality of second conductive vias
electrically connected to the electrode pads disposed on the lower surface of the at least a passive element.

US Pat. No. 9,093,459

PACKAGE STRUCTURE HAVING A SEMICONDUCTOR COMPONENT EMBEDDED THEREIN AND METHOD OF FABRICATING THE SAME

Unimicron Technology Corp...

1. A package structure having a semiconductor component embedded therein, comprising:
a first dielectric layer having a first surface and a second surface opposing the first surface;
a semiconductor chip embedded in the first dielectric layer in a manner that the semiconductor chip protrudes from the second
surface of the first dielectric layer, and having an active surface and an inactive surface opposing the active surface, in
which electrode pads are formed on the active surface and in the first dielectric layer, the inactive surface and a part of
a side surface adjacent the inactive surface protrude from the second surface of the first dielectric layer and are exposed
from the second surface of the first dielectric layer, and the inactive surface is higher than the second surface of the first
dielectric layer and exposed to outside;

a first circuit layer formed on the first surface of the first dielectric layer, with a plurality of first conductive vias
formed in the first dielectric layer for electrically connecting to the first circuit layer to the electrode pads;

a built-up structure formed on the first surface of the first dielectric layer and the first circuit layer; and
an insulating protective layer formed on the built-up structure, with a plurality of through holes formed in the insulating
protective layer for exposing a part of a surface of the built-up structure.

US Pat. No. 9,357,659

PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER

Unimicron Technology Corp...

1. A packaging substrate having an embedded through-via interposer, comprising:
an encapsulant layer having opposite first and second surfaces;
a through-via interposer embedded in the encapsulant layer and having opposite first and second sides and a plurality of conductive
through-vias in communication with the first and second sides, wherein each of the conductive through-vias has a first end
surface on the first side of the through-via interposer and a second end surface on the second side of the through-via interposer,
and the second side of the through-via interposer is flush with the second end surfaces of the conductive through-vias and
the second surface of the encapsulant layer;

a redistribution layer embedded in the encapsulant layer and formed on the first side of the through-via interposer and the
first end surfaces of the conductive through-vias so as to electrically connect with the first end surfaces of the conductive
through-vias, wherein the outermost layer of the redistribution layer has electrode pads, and wherein the encapsulant layer
covers the electrode pads; and

a built-up structure formed on the second surface of the encapsulant layer, the second side of the through-via interposer
and the second end surfaces of the conductive through-vias, and having at least a dielectric layer, a circuit layer embedded
in the dielectric layer and a plurality of conductive vias formed in the dielectric layer for electrically connecting with
the circuit layer, wherein portions of the conductive vias electrically connect with the second end surfaces of the conductive
through-vias, respectively.

US Pat. No. 9,224,683

METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING A THROUGH-HOLED INTERPOSER

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate, comprising:
providing at least a board body having opposing first and second surfaces and a protection layer formed on the first surface;
forming a plurality of through holes interconnecting the first surface and the second surface of the board body and extending
to the protection layer;

forming in the through holes a plurality of conductive gels each having opposing first and second ends;
forming on the second surface of the board body a circuit redistribution structure electrically connected to the second ends
of the conductive gels, so as to form an interposer plate including a plurality of interposers;

separating the interposer plate to obtain the plurality of interposers and removing the protection layer, to allow the first
ends of the conductive gels to protrude from the first surface of each of the interposers;

forming a encapsulating layer that encapsulates a periphery and the first surface of each of the interposers; and
forming on the encapsulating layer above the first surfaces of the interposers a circuit built-up structure electrically connected
to the first ends of the conductive gels.

US Pat. No. 9,337,136

METHOD OF FABRICATING A THROUGH-HOLED INTERPOSER

Unimicron Technology Corp...

1. A method of fabricating a through-holed interposer, comprising:
providing a board body having opposing first and second surfaces and first and second protection layers formed on the first
and second surfaces, respectively;

forming a plurality of through holes connecting the first surface and the second surface of the board body and extending to
the first protection layer;

forming in each of the through holes a conductive gel having opposing first and second ends;
removing the first protection layer, to allow the first end of the conductive gel to protrude from the first surface of the
board body;

forming a surface treatment layer on the first end of the conductive gel, wherein the surface treatment layer is in direct
contact with the first end of the conductive gel;

forming on the first surface of the board body and the first end of the conductive gel a first circuit redistribution structure
electrically connected to the first end of the conductive gel; and

removing the second protection layer to expose the second end of the conductive gel from the second surface of the board body.

US Pat. No. 9,581,774

OPTICAL-ELECTRO CIRCUIT BOARD

Unimicron Technology Corp...

1. An optical-electro circuit board comprising:
a multi-layer circuit board comprising a plurality of circuit layers and a plurality of dielectric layers between the circuit
layers and having a groove extending from a surface of the multi-layer circuit board into the circuit layers;

an optical component arranged in an upside down manner and assembled into the groove of the multi-layer circuit board, the
optical component comprising:

a multi-layer substrate comprising at least one dielectric layer, at least two circuit layers, and two through holes passing
through the at least one dielectric layer, the at least two circuit layers being located on two opposite surfaces of the at
least one dielectric layer;

an optical waveguide element located on a surface of the multi-layer substrate and between the through holes, the optical
waveguide element facing a bottom of the groove; and

two optical-electro assemblies respectively inserted into the corresponding through holes and correspondingly located at two
opposite ends of the optical waveguide element, wherein one of the optical-electro assemblies transforms an electrical signal
into a light beam and provides the light beam to the optical waveguide element, and the other one of the optical-electro assemblies
receives the light beam transmitted from the optical waveguide element and transforms the light beam into another electrical
signal; and

two chips located outside the groove and electrically connected to the corresponding optical-electro assemblies, respectively,
wherein one of the chips provides the electrical signal to the corresponding optical-electro assembly, and the other one of
the chips receives the electrical signal transmitted from the other corresponding optical-electro assembly.

US Pat. No. 9,362,140

PACKAGE STACK DEVICE AND FABRICATION METHOD THEREOF

Unimicron Technology Corp...

1. A package stack device, comprising:
a first package structure, comprising:
a first substrate having a first surface with a plurality of first metal posts formed thereon and a second surface opposite
to the first surface, wherein the first metal posts are copper posts, and the second surface of the first substrate has a
plurality of ball pads for mounting solder balls; and

a first electronic element disposed on the first surface of the first substrate and electrically connected to the first substrate,
wherein the first electronic element is an active component and/or a passive component, and the first electronic element is
electrically connected to the first substrate through wire bonding or in a flip-chip manner; a second package structure, comprising:

a second substrate having a third surface and a fourth surface opposite to the third surface, wherein the fourth surface has
a plurality of second metal posts which are connected to the first metal posts, respectively, so as for the second package
structure to be stacked on the first package structure, and wherein a width of end surfaces of the first metal posts is different
from a width of end surfaces of the second metal posts, the second metal posts are copper posts, and a solder material is
formed between each of the first metal posts and the corresponding second metal post; and

a second electronic element disposed on the third surface of the second substrate and electrically connected to the second
substrate; and

an encapsulant formed between the first surface of the first substrate and the fourth surface of the second substrate to encapsulate
the first electronic element, the first metal posts, and the second metal posts.

US Pat. No. 9,111,948

METHOD OF FABRICATING SEMICONDUCTOR PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A fabrication method of a semiconductor package structure, comprising:
providing a carrier board having a first adhesive layer formed on a surface thereof, and, a plurality of semiconductor chips,
each of which has an active surface and an opposite inactive surface, a plurality of electrode pads formed on the active surface,
and a plurality of metal humps disposed on the electrode pads, respectively;

adhering the semiconductor chips to the first adhesive layer through the active surfaces thereof;
forming an encapsulant on the first adhesive layer to encapsulate the semiconductor chips;
providing a metal foil having a plurality of metal posts disposed on a surface thereof, and attaching the metal foil to the
encapsulant through the surface thereof such that the metal posts penetrate the encapsulant and extend to the inactive surfaces
of the semiconductor chips;

removing the carrier board and the first adhesive layer;
forming a dielectric layer on the encapsulant and the semiconductor chips, wherein the dielectric layer has a plurality of
patterned intaglios for exposing the metal bumps, respectively;

forming a wiring layer in the patterned intaglios of the dielectric layer such that the wiring layer is electrically connected
to the metal bumps;

forming an insulating protective layer on the dielectric layer and the wiring layer, wherein the insulating protective layer
has a plurality of openings for exposing portions of the wiring layer;

removing portions of the metal foil to form dicing lines such that the metal foil is separated corresponding to the semiconductor
chips; and

cutting the encapsulant, the dielectric layer and the insulating protective layer along the dicing lines of the metal foil
such that a plurality of semiconductor package structures are formed.

US Pat. No. 9,578,742

CIRCUIT BOARD STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board structure, comprising:
a first circuit layer;
a first dielectric layer disposed on the first circuit layer, wherein the first dielectric layer has at least one first hole
exposing a portion of the first circuit layer;

a second dielectric layer disposed on the first circuit layer and the first dielectric layer, wherein the second dielectric
layer has at least one trench and at least one second hole disposed in the first hole, the second hole exposing the first
circuit layer, the trench exposing the first dielectric layer;

a second circuit layer disposed in the trench; and
a conductive via disposed in the second hole without contacting the first hole, wherein a diameter of the second hole is smaller
than a diameter of the first hole, and the conductive via has a bottom surface, a top surface, and a side surface connecting
the bottom surface and the top surface.

US Pat. No. 9,635,757

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board, comprising:
a dielectric substrate;
a circuit pattern disposed on the dielectric substrate; and
a dielectric layer, disposed on the dielectric substrate, covering the circuit pattern, and comprising a dielectric matrix
and a mesh-shaped fiber structure disposed in the dielectric matrix, wherein there is no mesh-shaped fiber structure on a
portion of the dielectric substrate exposed by the circuit pattern.

US Pat. No. 9,661,761

CARRIER SUBSTRATE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A carrier substrate, comprising:
an insulation layer having a first surface and a second surface relative to each other and a plurality of first openings extending
from the first surface to the second surface, wherein an aperture of each of the first openings gradually increases from the
first surface of the insulation layer towards the second surface;

a plurality of conductive towers disposed on the first surface of the insulation layer, each of the conductive towers having
a top surface and a bottom surface relative to each other, and a diameter of each of the conductive towers gradually increasing
from the top surface towards the bottom surface, wherein the conductive towers comprise a plurality of first conductive towers
and a plurality of second conductive towers surrounding the first conductive towers, and a diameter of the second conductive
towers is greater than a diameter of the first conductive towers, wherein all portions of a side surface of each of the conductive
towers are completely exposed; and

a circuit structure layer disposed on the second surface of the insulation layer and comprising at least one dielectric layer,
at least two circuit layers and a plurality of conductive vias, wherein the dielectric layer and the circuit layers are alternately
stacked, one of the circuit layers is disposed on the second surface of the insulation layer, the conductive vias comprise
a plurality of first conductive vias extending from the circuit layers, disposed in the first openings and extending to the
conductive towers, the conductive vias further comprise a plurality of second conductive vias passing through the dielectric
layer and electrically connecting the circuit layers, a diameter of the first conductive vias gradually increases from the
first surface of the insulation ayer towards the second surface, each of the second conductive towers correspondingly connects
to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the
first conductive vias, wherein an interface exists between the first conductive vias and the first conductive towers as well
as the second conductive towers, and cross-sectional profiles of the first conductive towers and the second conductive towers
are concave shaped, and cross-sectional profiles of the first conductive vias are flat shaped.

US Pat. No. 9,559,045

PACKAGE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Unimicron Technology Corp...

1. A package structure, comprising:
a circuit board, wherein the circuit board comprises a build-up structure, second contact pads and a solder mask layer, and
the second contact pads are disposed between the build-up structure and the solder mask layer;

a supporting structure, disposed in the circuit board, wherein the supporting structure comprises a vertical supporting structure;
a first heat dissipation structure, disposed in the circuit board and between the build-up structure and the second contact
pads, wherein the first heat dissipation structure is electrically connected to the vertical supporting structure to form
an inverted U-shape structure;

a plurality of first contact pads, disposed on the circuit board;
at least one chip, disposed on one portion of the first contact pads; and
a plurality of metal pillars, disposed on the other portion of the first contact pads, wherein the metal pillars surround
the chip.

US Pat. No. 9,860,980

CIRCUIT BOARD ELEMENT

UNIMICRON TECHNOLOGY CORP...

1. A circuit board element, comprising:
a glass substrate having an edge;
a first dielectric layer disposed on the glass substrate and having a central region and an edge region, wherein the edge
region is in contact with the edge of the glass substrate, and a thickness of the central region is greater than a thickness
of the edge region;

a first patterned metal layer disposed on the glass substrate and in the central region of the first dielectric layer; and
an insulating protective layer disposed on the first patterned metal layer and the central region of the first dielectric
layer, wherein the central region of the first dielectric layer has a first side surface, the insulating protective layer
has a second side surface, and the first side surface is connected to the second side surface, and an extending line of the
first side surface and the second side surface intersects the glass substrate.

US Pat. No. 9,686,866

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A package structure comprising:
a circuit substrate comprising:
at least one core layer having a disposition area, a bent area surrounding the disposition area, and an upper surface and
a lower surface opposite to each other;

a build-up structure arranged on the core layer and located in the disposition area, the build-up structure comprising at
least three patterned circuit layers, at least two dielectric layers and a plurality of conductive through holes, wherein
the patterned circuit layers and the dielectric layers are alternately stacked, and the conductive through holes are electrically
connected to every two adjacent patterned circuit layers; and

a plurality of circuit pads arranged on the lower surface of the core layer and located in the bent area;
at least one electronic component embedded in at least one of the dielectric layers and located in the disposition area, wherein
the electronic component is electrically connected to one of the patterned circuit layers through a portion of the conductive
through holes; and

a connecting slot having a bottom portion, a plurality of sidewall portions connecting the bottom portion, and a plurality
of connecting pads located on the sidewall portions, wherein the circuit substrate is assembled to the bottom portion, and
the circuit pads are electrically connected to the connecting pads through the bent area of the core layer bent relative to
the disposition area.

US Pat. No. 9,646,852

MANUFACTURING PROCESS FOR SUBSTRATE STRUCTURE HAVING COMPONENT-DISPOSING AREA

Unimicron Technology Corp...

1. A process for a substrate having a component-disposing area, comprising:
providing a core layer, which comprises a first surface, a metallic layer and a component-disposing area, wherein the metallic
layer is disposed on the first surface;

patterning the metallic layer to form a patterned metallic layer, wherein the patterned metallic layer comprises a plurality
of pads located in the component-disposing area;

forming a first dielectric layer on the first surface, wherein the first dielectric layer covers the patterned metallic layer;
forming a laser-resistant metallic pattern on the first dielectric layer, wherein the laser-resistant metallic pattern surrounds
a projection area of the first dielectric layer which the component-disposing area is orthogonally projected on;

disposing a release film on the projection area of the first dielectric layer, wherein the release film covers a portion of
the laser-resistant metallic pattern within the projection area;

forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer covers the release film
and the laser-resistant metallic pattern;

forming a first open hole and a plurality of second open holes, wherein the first open hole surrounds the projection area
and penetrates through the second dielectric layer and extends to the laser-resistant metallic pattern, and the second open
holes respectively penetrate through the second dielectric layer and extend to the pads; and

making the release film separated from the first dielectric layer to form a component-disposing cavity.

US Pat. No. 9,860,984

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:
providing an inner circuit structure, the inner circuit structure comprises a core layer having an upper surface and a lower
surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit
layer disposed on the lower surface and a conductive through hole connecting the first patterned circuit layer and the second
patterned circuit layer;

forming a metal pillar on a pad of the first patterned circuit layer;
performing a build-up process, to press a first build-up circuit structure on the first patterned circuit layer, wherein the
first build-up circuit structure at least comprises an inner dielectric layer, and the inner dielectric layer directly covers
the upper surface of the core layer and the first patterned circuit layer;

using a contact distance detector to detect an upper surface of the metal pillar relatively far away from the first patterned
circuit layer; and

using the upper surface of the metal pillar to serve as a depth reference surface, performing a hole drilling process on the
first build-up circuit structure, to remove a portion of the first build-up circuit structure and the whole metal pillar,
or remove a portion of the first build-up circuit structure and a portion of the metal pillar, so as to form a cavity extending
from a first surface of the first build-up circuit structure relatively far away from the inner circuit structure to a portion
of the inner dielectric, wherein the cavity exposes an inner surface of the inner dielectric layer, and the inner dielectric
layer has an opening connecting to the cavity, the pad is located in the opening, and a hole diameter of the opening is smaller
than a hole diameter of the cavity, and an inner surface of the inner dielectric layer exposed by the cavity and a top surface
of the pad are coplanar or have a height difference.

US Pat. No. 9,913,418

PROCESS OF AN EMBEDDED COMPONENT STRUCTURE

Unimicron Technology Corp...

1. A process of an embedded component structure, comprising:
providing a wiring board, wherein electrical function of the wiring board is normal, the wiring board has a front side, a
reverse side opposite to the front side, an opening and an interconnection layer, the opening penetrates the wiring board
and connects the front side and the reverse side, and the interconnection layer is located on the front side and extends toward
the opening;

bonding a component to the wiring board, wherein electrical function of the component is normal, the component has an active
surface, a back surface opposite to the active surface, and a working area located on the active surface, the active surface
is bonded to the interconnection layer, the component is located in the opening, and the active surface and the front side
of the wiring board face in a same direction; and

filling an encapsulant into the opening, so as to cover at least the back surface and a portion of the active surface of the
component and expose the working area, wherein a portion of the encapsulant located on the back surface of the component is
flush with the reverse side of the wiring board.

US Pat. No. 9,883,598

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A method for a circuit board having a heat-recovery function, comprising:
forming at least one first via at a single-layer dielectric layer and disposing at least one first heat-conducting pillar
in the first via;

building up a plurality of buildup-dielectric layers from the single-layer dielectric layer to form a substrate;
respectively forming a first recess and a second recess on two opposite surfaces of the substrate, wherein the single-layer
dielectric layer is between the first recess and the second recess;

disposing a thermoelectric device into the first recess for embedding the thermoelectric device in the substrate, wherein
the thermoelectric device is connected to the first heat-conducting pillar;

forming at least one second via at a heat-storing device and filling the second via with at least one second heat-conducting
pillar such that the heat-storing device is penetrated by the second heat-conducting pillar;

disposing a processor on the heat-storing device, wherein the processor is connected to and in contact with the second heat-conducting
pillar; and

disposing the heat-storing device and the processor into the second recess for embedding the heat-storing device in the substrate,
wherein the heat-storing device is between the processor and the thermoelectric device.

US Pat. No. 9,854,671

CIRCUIT BOARD AND METHOD OF MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board, comprising:
a substrate having a top surface and a bottom surface;
a first magnetic structure disposed on the top surface of the substrate;
a first dielectric layer covering the substrate and the first magnetic structure; and
an inductive coil comprising:
a first interconnect disposed on the first dielectric layer;
a second interconnect disposed on the bottom surface of the substrate; and
a plurality of conductive pillars connecting the first interconnect and the second interconnect, wherein the first interconnect,
the second interconnect and the conductive pillars form a helical structure surrounding the first magnetic structure.

US Pat. No. 9,806,050

METHOD OF FABRICATING PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A method of fabricating a package structure having a semiconductor component embedded therein, comprising:
providing a core board having two opposing surfaces on which two carrier layers are formed;
forming on the carrier layers two metal layers having openings for exposing a part of surfaces of the carrier layers;
disposing on the carrier layers in the openings semiconductor chips having active surfaces and inactive surfaces opposing
the active surfaces, with electrode pads disposed on the active surfaces, the semiconductor chips combining with the carrier
layers in the openings by means of the inactive surfaces;

forming on the metal layers and the semiconductor chips first dielectric layers that have exposed first surfaces and second
surfaces combined with the metal layers;

forming first circuit layers on the first surfaces of the first dielectric layers, and forming in the first dielectric layers
a plurality of first conductive vias electrically connected to the first circuit layers and the electrode pads;

forming built-up structures on the first surfaces of the first dielectric layers and the first circuit layers;
forming insulating protective layers on the built-up structures, and forming in the insulating protective layers a plurality
of cavities for exposing a part of surfaces of the built-up structures; and

removing the core board, so as to expose the carrier layers.

US Pat. No. 9,739,963

MANUFACTURING METHOD OF OPTICAL COMPONENT

Unimicron Technology Corp...

1. A manufacturing method of an optical component, comprising:
providing a multi-layer substrate comprising at least one dielectric layer, at least two circuit layers, and two through holes
passing through the at least one dielectric layer, the at least two circuit layers being located on two opposite surfaces
of the at least one dielectric layer;

forming an optical waveguide element on a surface of the multi-layer substrate and between the through holes; and
forming two optical-electro assemblies in the corresponding through holes, the optical-electro assemblies being correspondingly
located at two opposite ends of the optical waveguide element, each of the optical-electro assemblies being formed with an
optical-electro element and an insertion element having a conductive layer disposed thereon, and the conductive layer of each
optical-electro assembly being located between a sidewall of the corresponding through hole and the insertion element of each
optical-electro assembly and being electrically connected to the optical-electro element of each optical-electro assembly.

US Pat. No. 9,781,843

METHOD OF FABRICATING PACKAGING SUBSTRATE HAVING EMBEDDED THROUGH-VIA INTERPOSER

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate having an embedded through-via interposer, comprising the steps of:
providing a through-via interposer having opposite first and second sides and a plurality of conductive through-vias in communication
with the first and second sides, wherein each of the conductive through-vias has a first end surface on the first side of
the through-via interposer and a second end surface on the second side of the through-via interposer, and the second end surfaces
of the conductive through-vias protrude below the second side of the through-via interposer to serve as conductive bumps;

forming a redistribution layer on the first side of the through-via interposer and the first end surfaces of the conductive
through-vias such that the redistribution layer electrically connect with the first end surfaces of the conductive through-vias,
wherein an outermost layer of the redistribution layer has electrode pads;

forming an encapsulant layer to encapsulate and embed the through-via interposer, wherein the encapsulant layer has opposite
first and second surfaces, the second side of the through-via interposer is exposed from the second surface of the encapsulant
layer, the conductive bumps protrude below the second surface of the encapsulant layer, and the encapsulant layer covers the
redistribution layer and the electrode pads;

forming a built-up structure on the second surface of the encapsulant layer, the second side of the through-via interposer
and the conductive bumps, wherein the built-up structure has at least a dielectric layer, a circuit layer formed on the dielectric
layer, and a plurality of conductive vias formed in the dielectric layer for electrically connecting with the circuit layer,
wherein portions of the conductive vias electrically connect with the conductive bumps, respectively, and

decreasing a thickness of the encapsulant layer from the first surface of the encapsulant layer so as to expose the electrode
pads from the first surface of the encapsulant layer.

US Pat. No. 9,805,875

CAPACITOR AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A capacitor, comprising:
a porous substrate having a plurality of holes;
an electrolyte composition located in the holes of the porous substrate, the electrolyte composition comprising an electrolyte
solution and a nano carbon material dispersed in the electrolyte solution; and

a pair of electrodes respectively located on two opposite surfaces of the porous substrate.

US Pat. No. 9,859,130

MANUFACTURING METHOD OF INTERPOSED SUBSTRATE

Unimicron Technology Corp...

1. A manufacturing method of an interposed substrate comprising:
providing a metal carrier;
forming a photoresist layer on the metal carrier, wherein the photoresist layer has a plurality of openings, and a portion
of the metal carrier is exposed by the openings;

forming a plurality of metal passivation pads in the plurality of openings of the photoresist layer, wherein the plurality
of metal passivation pads cover the portion of the metal carrier exposed by the plurality of openings;

forming a plurality of conductive pillars in the plurality of openings of the photoresist layer, wherein the plurality of
conductive pillars are respectively stacked on the plurality of metal passivation pads, and a thickness of each of the plurality
of conductive pillars is at least twice the thickness of each of the plurality of metal passivation pads;

removing the photoresist layer to expose another portion of the metal carrier;
forming an insulating material layer on the metal carrier, wherein the insulating material layer covers the another portion
of the metal carrier and encapsulates the plurality of conductive pillars and the plurality of metal passivation pads; and

removing the metal carrier to expose a lower surface opposite to an upper surface of the insulating material layer.

US Pat. No. 9,831,103

MANUFACTURING METHOD OF INTERPOSED SUBSTRATE

Unimicron Technology Corp...

1. A manufacturing method of an interposed substrate comprising:
forming a metal-stacked layer, wherein the metal-stacked layer comprises a first metal layer, an etching stop layer and a
second metal layer, the etching stop layer is disposed between the first metal layer and the second metal layer, and a thickness
of the second metal layer is greater than a thickness of the first metal layer;

forming a patterned conductor layer on the first metal layer, wherein the patterned conductor layer exposes a portion of the
first metal layer;

forming a plurality of conductive pillars on the patterned conductor layer, wherein the conductive pillars are separated from
each other and stacked on a portion of the patterned conductor layer;

forming an insulating material layer on the metal-stacked layer, the insulating material layer having an upper surface and
a lower surface opposite to each other, wherein the insulating material layer covers the portion of the first metal layer
and encapsulates the conductive pillars and the other portion of the patterned conductor layer;

forming a dielectric layer on the insulating material layer, wherein the dielectric layer covers the upper surface of the
insulating material layer and a top surface of each conductive pillar; and

removing the metal-stacked layer to expose the lower surface of the insulating material layer and a bottom surface of the
patterned conductor layer.

US Pat. No. 9,775,246

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board, comprising:
a substrate, having a first surface and a first circuit layer, wherein the first surface has a chip disposing area and an
electrical connection area, and the first circuit layer is embedded in the first surface;

a photo imageable dielectric layer, disposed on the electrical connection area and having a plurality of openings, wherein
the openings expose parts of the first circuit layer, and the photo imageable dielectric layer exposes the chip disposing
area; and

a plurality of conductive bumps, respectively disposed at the openings, and connected to the first circuit layer, wherein
the photo imageable dielectric layer covers at least a part of a side surface of each of the conductive bumps.

US Pat. No. 9,883,579

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A package structure, comprising:
a circuit substrate, comprising:
a core layer having a first surface and a second surface opposite to each other;
a plurality of electronic devices embedded in the core layer, wherein each of the electronic devices has an active surface
and a back surface opposite to each other, and the active surfaces of two adjacent electronic devices respectively face the
first surface and the second surface of the core layer; and

a conducting unit disposed on the first surface and the second surface of the core layer and extended to the electronic devices
and electrically connected to the electronic devices;

a first build-up circuit structure disposed on the first surface of the core layer and having at least one first opening;
a second build-up circuit structure disposed on the second surface of the core layer and having at least one second opening,
wherein the first opening and the second opening expose a portion of the conducting unit; and

a plurality of piezoelectric heat dissipation units disposed on the conducting unit exposed by the first opening and the second
opening and respectively corresponding to the active surfaces of the electronic devices, wherein the piezoelectric heat dissipation
units are electrically connected to the conducting unit exposed by the first opening and the second opening.

US Pat. No. 9,832,873

CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A circuit board structure, comprising:
an inner circuit structure, comprising a core layer having an upper surface and a lower surface opposite to each other, a
first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface,
and a conductive through hole connecting the first patterned circuit layer and the second patterned circuit layer; and

a first build-up circuit structure, disposed on the upper surface of the core layer and covering the first patterned circuit
layer, wherein the first build-up circuit structure at least has a cavity and an inner dielectric layer, the cavity exposes
a portion of the inner dielectric layer, and the inner dielectric layer directly covers the upper surface of the core layer
and the first patterned circuit layer, the inner dielectric layer has a first portion with a first thickness, and a second
portion with a second thickness exposed by the cavity, wherein the second thickness is thinner than the first thickness, the
inner dielectric layer has an opening connecting the cavity and exposing a portion of the first patterned circuit layer, a
hole diameter of the opening is smaller than a hole diameter of the cavity, and a top surface of the first patterned circuit
layer exposed by the opening is not higher than an inner surface of the inner dielectric layer exposed by the cavity.

US Pat. No. 9,691,699

CIRCUIT STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

Unimicron Technology Corp...

1. A method for manufacturing a circuit structure, comprising:
forming two patterned circuit layers on a core layer, wherein the patterned circuit layers are located respectively on two
opposite surfaces of the core layer;

forming a patterned insulating layer respectively on each of the patterned circuit layers, wherein the patterned insulating
layers respectively expose a portion of the patterned circuit layers;

providing two support plates respectively bonded on the patterned insulating layers wherein each of the support plates, each
of the patterned insulating layers and each of the patterned circuit layers define a plurality of air gaps; and

after providing the two support plates, removing the core layer so as to expose an upper surface of each of the patterned
circuit layers and a top surface of each of the patterned insulating layers, wherein the upper surface of each of the patterned
circuit layers is aligned with the top surface of each of the patterned insulating layers.

US Pat. No. 9,859,159

INTERCONNECTION STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. An interconnection structure, comprising:
a substrate having a first surface and a second surface opposite to each other;
a conductive through via disposed in the substrate and extended from the first surface beyond the second surface;
a dielectric layer disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive
through via, and a top surface of the conductive through via protrudes from a bottom surface of the opening; and

a conductive layer disposed in the opening and in contact with the top surface and a portion of a side surface of the conductive
through via, wherein the conductive layer comprises a seed layer and a conductive material layer, and top surfaces of the
seed layer and the conductive material layer are respectively aligned with a top surface of the dielectric layer.

US Pat. No. 9,974,166

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board, comprising:a substrate, having a first surface and a second surface opposite to each other;
a patterned circuit layer, embedded in the first surface, and a line width of the patterned circuit layer gradually reducing from the first surface towards the second surface;
a patterned photo-imaginable dielectric layer, embedded in the substrate corresponding to the patterned circuit layer; and
a first surface finish layer, exposed on the second surface and only covering a bottom surface of a part of the patterned circuit layer.

US Pat. No. 10,123,418

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board structure, comprising:an insulating layer, comprising a first conductive through hole, a first surface, and a second surface opposite to the first surface, the first conductive through hole penetrating the insulating layer to connect the first surface and the second surface;
a first dielectric layer, disposed on the first surface;
a first inductor, disposed on the first surface of the insulating layer and electrically connecting the first conductive through hole, the first inductor comprising a first conductive coil and a first magnetic flux axis, wherein the first conductive coil in a solenoid form penetrates the first dielectric layer, and a direction of the first magnetic flux axis is substantially parallel to the first surface;
a second dielectric layer disposed on the second surface; and
a second inductor, located on the second surface of the insulating layer and electrically connecting the first conductive through hole, the second inductor comprising a second conductive coil and a second magnetic flux axis, wherein the second conductive coil in a solenoid form penetrates the second dielectric layer, and a direction of the second magnetic flux axis is substantially parallel to the second surface.

US Pat. No. 9,900,997

MANUFACTURING METHOD OF A RIGID FLEX BOARD MODULE

Unimicron Technology Corp...

1. A manufacturing method for a rigid flex board module, comprising:
providing a rigid flex initial substrate including a flexible circuit board, a pair of release layers, a first rigid substrate,
and a first insulating layer;

wherein the flexible circuit board having a bending portion and a jointing portion connected to the bending portion, the pair
of release layers respectively disposed on two sides of the flexible circuit board covering the bending portion, the first
rigid substrate arranged above the flexible circuit board and the pair of release layers, the first rigid substrate covering
the bending portion and the jointing portion, and the first insulating layer connected between the first rigid substrate and
the flexible circuit board;

forming a pair of first openings on the rigid flex initial substrate to expose the bending portion;
forming a second opening through the rigid flex initial substrate, the first rigid substrate and the first insulating layer;
disposing a high-density interconnected circuit layer in the second opening;
forming a pair of multi-layer circuit layers on two sides of the rigid flex initial substrate and covering two sides of the
high-density interconnected circuit layer and the rigid flex initial substrate; and

forming a plurality of conductive posts such that the multi-layer circuit layers, the high-density interconnected circuit
layer, and the rigid flex initial substrate are electrically connected to each other.

US Pat. No. 10,039,184

CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board structure, comprising:an inner circuit structure, comprising a core layer having an upper surface and a lower surface opposite to each other, a first patterned circuit layer disposed on the upper surface, a second patterned circuit layer disposed on the lower surface, and a conductive via connecting the first patterned circuit layer and the second patterned circuit layer; and
a first build-up circuit structure, disposed on the upper surface of the core layer and covering the first patterned circuit layer, wherein the first build-up circuit structure at least has a cavity, the cavity exposes a portion of the first patterned circuit layer, and a cross-sectional profile of an edge of a top surface of the portion of the first patterned circuit layer exposed by the cavity is a curved surface,
wherein the first build-up circuit structure further comprises an inner dielectric layer, at least a first dielectric layer, at least a first patterned conductive layer, and at least a first conductive via structure penetrating through the inner dielectric and the first dielectric layer, the first patterned conductive layer and the first dielectric layer are sequentially stacked on the inner dielectric layer, the first patterned conductive layer is electrically connected to the first patterned circuit layer via the first conductive via structure,
wherein the cavity further exposes a portion of the inner dielectric layer, the inner dielectric layer comprises a first inner surface and a second inner surface, the first inner surface is higher than the second inner surface, the cavity exposes the second inner surface, and the top surface of the portion of the first patterned circuit layer exposed by the cavity is higher than the second inner surface.

US Pat. No. 10,076,039

METHOD OF FABRICATING PACKAGING SUBSTRATE

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate, comprising the steps of:providing a carrier board having two opposite surfaces, forming on each of the two opposite surfaces a plurality of first metal bumps having a first end and an opposite second end, and connecting the second end to the two opposite surfaces of the carrier board for a semiconductor chip to be disposed on the plurality of first metal bumps;
covering the two opposite surfaces of the carrier board and the plurality of first metal bumps with a first dielectric layer that has a plurality of first intaglios which exposes a top surface and side surface of the first end of the plurality of first metal bumps;
forming a conductive seedlayer on the first dielectric layer and the first end of the plurality of first metal bumps;
forming a metal layer on the conductive seedlayer;
removing a portion of the metal layer and the conductive seedlayer such that the top surface is co-planar with a top surface of the first dielectric layer which is opposite the carrier board, and the result of the removal of the portion of the metal layer and the conductive seed layer, forming a first circuit layer in the plurality of first intaglios;
forming a built-up structure on the first circuit layer and the first dielectric layer, forming a pair of upper and lower entire packaging substrates, and having a plurality of conductive pads on an outmost layer of the built-up structure for an external electronic device to be disposed on the plurality of conductive pads; and
removing the carrier board results in the pair of upper and lower entire packaging substrates.

US Pat. No. 10,051,748

CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A circuit board structure, comprising:an inner circuit structure, comprising a core layer having an upper surface and an opposite lower surface, a first patterned circuit layer disposed on the upper surface and a second patterned circuit layer disposed on the lower surface;
a first build-up circuit structure, disposed on the upper surface of the core layer and covering the first patterned circuit layer, wherein the first build-up circuit structure has a cavity, the cavity exposes a portion of the first patterned circuit layer and a portion of the upper surface of the core layer, and the cavity comprises a plurality of side walls, and the side walls have a concave-and-convex profile, or a combination of concave-and-convex and plane profiles, wherein a diameter of the cavity varies from an outermost portion of a first patterned conductive layer of the first build-up circuit structure to the first patterned circuit layer, and a portion of the first patterned conductive layer is adjacent to the cavity; and
a second build-up circuit structure, disposed on the lower surface of the core layer and covering the second patterned circuit layer.

US Pat. No. 10,070,536

MANUFACTURING METHOD OF CIRCUIT BOARD STRUCTURE

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:providing a glass film having an upper surface and a lower surface, and the lower surface of the glass film being disposed on an electrostatic chuck;
performing a dicing process, such that at least one slit is formed in the upper surface of the glass film, wherein a surface of the electrostatic chuck is not exposed by the slit and a depth of the slit is at least more than two-thirds of a thickness of the glass film;
forming a plurality of first conductive vias in the upper surface of the glass film;
forming a first circuit layer on the upper surface of the glass film, such that the first circuit layer is electrically connected with the first conductive vias;
forming a polymer layer on the first circuit layer, and the polymer layer covering surfaces of the first circuit layer and the glass film;
forming a plurality of second conductive vias in the polymer layer, wherein the second conductive vias are electrically connected with the first circuit layer;
forming a second circuit layer on the polymer layer, such that the second circuit layer is electrically connected with the second conductive vias, so as to form a first circuit board structure; and
performing a singulation process, such that the first circuit board structure is divided into a plurality of second circuit board structures.

US Pat. No. 10,219,390

FABRICATION METHOD OF PACKAGING SUBSTRATE HAVING EMBEDDED PASSIVE COMPONENT

Unimicron Technology Corp...

1. A fabrication method of a packaging substrate having at least an embedded passive component, comprising:providing a carrier board having two opposite surfaces and sequentially forming a releasing film and a metal layer on each of the opposite surfaces of the carrier board;
forming a plurality of positioning pads on each of the metal layer on each of the opposite surfaces;
covering each of the metal layer on each of the opposite surfaces with a first hot-melt dielectric layer;
disposing at least a passive component on each of the first hot-melt dielectric layer on each of the metal layer at a position corresponding to the positioning pads, wherein the passive component has upper and lower surfaces each having a plurality of electrode pads disposed thereon;
disposing on each of the first hot-melt dielectric layer on each of the metal layer a core board having at least a cavity so as to receive the passive component on the first hot-melt dielectric layer in the cavity;
stacking a second hot-melt dielectric layer on each of the core on each of the first hot-melt dielectric layer;
heat pressing the first hot-melt dielectric layer and the second hot-melt dielectric layer so as to form two dielectric layer units each having an upper surface and a lower surface and each having the core board corresponding and the passive component embedded therein and the positioning pads corresponding embedded in the lower surface thereof;
removing the carrier board and the releasing film on each of the opposite surfaces so as to separate the two dielectric layer units; and
forming a first wiring layer on the upper surface of each of the dielectric layer units and forming a second wiring layer on the lower surface of each of the dielectric layer units, wherein the first wiring layer is electrically connected to the electrode pads of the upper surface of the passive component through a plurality of first conductive vias, and the second wiring layer is electrically connected to the electrode pads of the lower surface of the passive component through a plurality of second conductive vias.

US Pat. No. 9,955,578

CIRCUIT STRUCTURE

Unimicron Technology Corp...

1. A circuit structure, comprising:a patterned circuit layer;
a patterned insulating layer, covering a portion of the patterned circuit layer, wherein an upper surface of the patterned circuit layer is aligned with a top surface of the patterned insulating layer; and
a support plate, disposed on a bottom surface of the patterned insulating layer, wherein the support plate, the patterned insulating layer and the patterned circuit layer define a plurality of air gaps.

US Pat. No. 9,935,046

PACKAGE DEVICE AND MANUFACTURING METHOD THEREOF

UNIMICRON TECHNOLOGY CORP...

7. A package device comprising:at least one redistribution structure, comprising:
a first dielectric layer; and
a plurality of first metal lines disposed in the first dielectric layer;
a circuit board structure disposed on a first side of the redistribution structure, the circuit board structure comprising:
a second dielectric layer, wherein the second dielectric layer has a plurality of protrusions embedded in the redistribution structure; and
a plurality of second metal lines located in the second dielectric layer and electrically connected to the redistribution structure;
a first electronic component disposed on a second side, opposite to the first side, of the redistribution structure; and
a plurality of first connectors disposed between the redistribution structure and the first electronic component, and the first connectors electrically connect the redistribution structure and the first electronic component.

US Pat. No. 10,098,234

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:providing a dielectric substrate;
forming a circuit pattern on the dielectric substrate;
forming a dielectric layer on the dielectric substrate, and the dielectric layer covers the circuit pattern and has a hole or a conductive via in the dielectric layer, wherein the hole exposes a portion of the circuit pattern and the conductive via is electrically connected to the circuit pattern;
forming a conductive seed layer in the hole and on the dielectric layer;
forming a photoresist layer on the conductive seed layer;
performing imprinting on the photoresist layer via a piezochromic stamp, wherein when a pressing side of the piezochromic stamp facing the conductive seed layer is in contact with the conductive seed layer in the imprinting process, a light transmittance effect of the pressing side is changed from allowing a light having a specific wavelength to pass through to blocking the light having the specific wavelength, or the light transmittance effect of the pressing side is changed from blocking the light having the specific wavelength to allowing the light having the specific wavelength to pass through;
performing exposure on the photoresist layer by using the piezochromic stamp as a mask;
removing the piezochromic stamp and performing development on the photoresist layer to form a patterned photoresist layer;
forming a patterned metal layer on the conductive seed layer exposed by the patterned photoresist layer; and
removing the patterned photoresist layer and the conductive seed layer located under the patterned photoresist layer.

US Pat. No. 9,916,990

PACKAGING SUBSTRATE HAVING A HOLDER, METHOD OF FABRICATING THE PACKAGING SUBSTRATE, PACKAGE STRUCTURE HAVING A HOLDER, AND METHOD OF FABRICATING THE PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A method of fabricating a packaging substrate having a holder, comprising:
providing two stacked copper clad laminates, each of which has an insulating layer and copper layers disposed on opposite
sides of the insulating layer;

forming a strengthened board for embedding the stacked copper clad laminates therein, wherein the strengthened board has a
dielectric layer covering the two copper clad laminates, two first metal stripping layers formed on opposite surfaces of the
dielectric layer, and two second metal stripping layers formed on the first metal stripping layers respectively;

forming a plurality of first conductive pads on the second metal stripping layers;
forming on each one of the second metal stripping layers and the first conductive pads a core layer having a first surface
and a second surface opposite to the first surface, in a manner that the first conductive pads are embedded in the first surface
of each one of the core layers;

forming a circuit layer on the second surface of each one of the core layers;
forming in each one of the core layers a plurality of conductive vias for electrically connecting the first conductive pads
and the circuit layer, wherein each one of the circuit layers has a plurality of second conductive pads;

forming an insulating protection layer on the second surface of each one of the core layers and each one of the circuit layers;
forming in each one of the insulating protection layer a plurality of openings for exposing the second conductive pads; and
cutting through the two stacked copper clad laminates along a predetermined line approximate to sides of the two copper clad
laminates such that the two stacked copper clad laminates are allowed to be separated from each other from the two attached
copper layers so as to be separated into two individual packaging substrates each having the holder.

US Pat. No. 9,917,046

MANUFACTURING METHOD OF A CIRCUIT BOARD HAVING A GLASS FILM

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:
providing a glass film having an upper surface and a lower surface, and the lower surface of the glass film being directly
disposed on an electrostatic chuck;

forming a plurality of first conductive vias in the glass film, and the plurality of the first conductive vias penetrate the
upper surface and the lower surface of the glass film;

forming a first circuit layer on the upper surface of the glass film, such that the first circuit layer is electrically connected
with the first conductive vias;

forming a first polymer layer on the first circuit layer, and the first polymer layer covering a surface of the first circuit
layer and the upper surface of the glass film;

forming a plurality of second conductive vias in the first polymer layer, wherein the second conductive vias are electrically
connected with the first circuit layer;

forming a second circuit layer on the first polymer layer, such that the second circuit layer is electrically connected with
the second conductive vias; and

removing the electrostatic chuck, so as to form a first circuit board structure.

US Pat. No. 9,887,153

CIRCUIT REDISTRIBUTION STRUCTURE UNIT AND METHOD FOR MANUFACTURING CIRCUIT REDISTRIBUTION STRUCTURE

UNIMICRON TECHNOLOGY CORP...

1. A circuit redistribution structure unit, comprising:
a first dielectric layer;
a plurality of first conductive vias disposed in the first dielectric layer;
a first circuit redistribution layer disposed on the first dielectric layer and electrically connected to the first conductive
vias;

a second dielectric layer disposed on the first dielectric layer and the first circuit redistribution layer;
a plurality of second conductive vias disposed in the second dielectric layer and electrically connected to the first circuit
redistribution layer;

a second circuit redistribution layer disposed on the second dielectric layer and electrically connected to the second conductive
vias;

an encapsulation layer disposed on the second dielectric layer and the second circuit distribution layer, wherein the second
dielectric layer has a first surface, a second surface opposite to the first surface, and a side surface connecting the first
surface and the second surface, the second circuit redistribution layer is disposed on the first surface, and the encapsulation
layer covers the first surface and the side surface;

a plurality of third conductive vias disposed in the encapsulation layer and electrically connected to the second circuit
redistribution layer;

a plurality of conductive bumps disposed on the encapsulation layer and electrically connected to the third conductive vias;
and

a plurality of micro bumps disposed on one side of the first dielectric layer opposite to the second dielectric layer and
respectively electrically connected to the first conductive vias.

US Pat. No. 10,068,847

PACKAGE SUBSTRATE AND METHOD OF FABRICATING THE SAME

Industrial Technology Res...

1. A package substrate, comprising:a substrate having a first surface and a second surface opposing to the first surface, the first surface including a plurality of conductive pads;
an insulating protective layer formed on the first surface of the substrate;
an interposer embedded in the insulating protective layer and electrically connected to the substrate, the interposer including a plurality of penetrating conductive vias and a wiring redistribution layer, the interposer exposed from the insulating protective layer, wherein the insulating protective layer is the outmost layer above the first surface of the substrate; and
at least a passive component provided on the first surface of the substrate, wherein the insulating protective layer includes at least an opening for exposing at least one of the conductive pads, and the at least the passive component is directly provided on the conductive pad exposed from the opening, the insulating protective layer is free from covering the wiring redistribution layer and a surface away from the substrate of the passive component.

US Pat. No. 10,056,356

CHIP PACKAGE CIRCUIT BOARD MODULE

Unimicron Technology Corp...

1. A chip package circuit board module, comprising:a circuit board, comprising:
a first pad; and
a second pad, disposed besides the first pad, and separated from the first pad;
an original chip, connected to the first pad and the second pad, wherein a width of the original chip is W1, a total width of the first pad is P1, and a total width of the second pad is P2, the total width P1 of the first pad is larger than twice of the width W1 of the original chip, and the total width P2 of the second pad is larger than twice of the width W1 of the original chip.

US Pat. No. 10,121,757

PILLAR STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A pillar structure disposed on a substrate and comprising:a pad disposed on the substrate;
a metal wire bump disposed on the pad;
a metal wire connected to the metal wire bump, the metal wire and the metal wire bump being integrally formed, wherein the metal wire extends in a first extension direction having a consistent diameter, the substrate extends in a second extension direction, and the first extension direction is perpendicular to the second extension direction, wherein a diameter of the metal wire is less than a width of the metal wire bump; and
a metal plating layer covering the pad and completely encapsulating the metal wire bump and the metal wire, wherein a length of the metal wire is ? a length of the metal plating layer, and the metal plating layer covers an upper surface of the pad and encapsulates a side surface of the pad connecting the upper surface.

US Pat. No. 10,103,104

PACKAGE CARRIER AND MANUFACTURING METHOD OF PACKAGE CARRIER

Unimicron Technology Corp...

1. A package carrier, comprising:a flexible substrate, having a first surface and a second surface opposite to each other, and having a first opening connected between the first surface and the second surface;
a first build-up structure, disposed on the first surface and covering the first opening;
a second build-up structure, disposed on the second surface and having a second opening, wherein the first opening and the second opening are connected to each other to form a chip accommodating cavity together; and
a patterned barrier layer, disposed on the first surface and extended to a bottom surface of the chip accommodating cavity, wherein the patterned barrier layer is embedded in the first build-up structure.

US Pat. No. 10,083,901

METHOD FOR MANUFACTURING CIRCUIT REDISTRIBUTION STRUCTURE

Unimicron Technology Corp...

1. A method for manufacturing a circuit redistribution structure, the method comprising:forming a first dielectric layer on a carrier;
forming a plurality of first holes and a plurality of second holes in the first dielectric layer;
respectively forming a plurality of first conductive vias and a plurality of second conductive vias in the first holes and the second holes, and forming a first circuit redistribution layer on the first dielectric layer, wherein a first portion of the first circuit redistribution layer is electrically connected to the first conductive vias, and a second portion of the first circuit redistribution layer is electrically connected to the second conductive vias;
forming a second dielectric layer on the first dielectric layer and the first circuit redistribution layer;
forming a plurality of third holes and a plurality of fourth holes in the second dielectric layer to respectively expose the first portion and the second portion of the first circuit redistribution layer, and forming a trench in the second dielectric layer to expose the first dielectric layer and divide the second dielectric layer into a first portion and a second portion, wherein the first portion of the first circuit redistribution layer and the third holes are disposed in the first portion of the second dielectric layer, and the second portion of the first circuit redistribution layer and the fourth holes are disposed in the second portion of the second dielectric layer; and
respectively forming a plurality of third conductive vias and a plurality of fourth conductive vias in the third holes and the fourth holes, and forming a first portion of a second circuit redistribution layer on the first portion of the second dielectric layer and forming a second portion of the second circuit redistribution layer on the second portion of the second dielectric layer, wherein the first portion of the second circuit redistribution layer is electrically connected to the third conductive vias, and the second portion of the second circuit redistribution layer is electrically connected to the fourth conductive vias.

US Pat. No. 10,211,139

CHIP PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A chip package structure, comprising:at least one carrier board comprising a substrate and a redistribution layer, wherein the substrate has a first surface and a second surface opposite to each other, and the redistribution layer is disposed on the first surface of the substrate;
at least one chip disposed on the redistribution layer;
at least one conductive pillar disposed on the redistribution layer, wherein the at least one conductive pillar is located at a periphery of the at least one chip;
at least one molding compound disposed on the redistribution layer and covering the at least one chip, the at least one conductive pillar, and the redistribution layer, wherein the at least one conductive pillar passes through the at least one molding compound;
a circuit board disposed on the at least one molding compound, wherein the circuit board is connected with the at least one carrier board through the at least one conductive pillar, such that the at least one chip is located between the substrate and the circuit board, and the at least one chip and the redistribution layer are electrically connected with the circuit board through the at least one conductive pillar; and
a heat sink disposed on the second surface of the substrate, wherein a size of the heat sink is larger than a size of the substrate,
wherein the at least one carrier board further comprises conductive vias that pass through the substrate and connect the first surface with the second surface,
wherein each of the conductive vias comprises a first end and a second end, and the first end is exposed on the first surface of the substrate to be even with the first surface and connected with the redistribution layer while the second end is exposed on the second surface of the substrate to be even with the second surface.

US Pat. No. 10,141,224

MANUFACTURING METHOD OF INTERCONNECTION STRUCTURE

Unimicron Technology Corp...

1. A manufacturing method of an interconnection structure, comprising:providing a substrate;
forming a conductive through via in the substrate, wherein the substrate has a first surface and a second surface opposite to each other, and the conductive through via is extended from the first surface to the second surface;
removing a portion of the substrate from the first surface to expose a portion of the conductive through via;
forming a dielectric layer on the substrate, wherein the dielectric layer covers the exposed conductive through via;
forming an opening in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and a top surface of the conductive through via protrudes from a bottom surface of the opening; and
forming a conductive layer in the opening, wherein the conductive layer comprises a seed layer and a conductive material layer and top surfaces of the seed layer and the conductive material layer are respectively aligned with a top surface of the dielectric layer,
wherein a method of forming the conductive layer comprises:
forming the seed layer on the dielectric layer;
performing an electroplating process to form the conductive material layer on the seed layer, wherein the opening is completely filled with the conductive material layer; and
removing a portion of the conductive material layer and keeping the conductive material layer located in the opening to form the conductive layer.

US Pat. No. 10,433,426

CIRCUIT BOARD AND METHOD FOR MANUFACTURING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board, comprising:a substrate;
a first dielectric layer disposed on the substrate;
an adhesive layer bonded to the first dielectric layer and having a top surface opposite to the substrate;
a second dielectric layer disposed on the adhesive layer and having at least one first through hole;
a first conductive line located in the first through hole of the second dielectric layer, wherein a lowermost surface of the first conductive line is in contact with the top surface of the adhesive layer and the first conductive line is above an entirety of the adhesive layer; and
a plurality of second conductive lines penetrating through the adhesive layer and the second dielectric layer and being in contact with the first dielectric layer, wherein the first conductive line is located between adjacent two of the second conductive lines.

US Pat. No. 10,314,179

MANUFACTURING METHOD OF CIRCUIT STRUCTURE

Unimicron Technology Corp...

1. A manufacturing method of a circuit board structure, comprising:providing an inner circuit structure, the inner circuit structure comprising a core layer having an upper surface and an opposite lower surface, a first patterned circuit layer disposed on the upper surface and a second patterned circuit layer disposed on the lower surface;
forming an insulating material layer on a portion of the first patterned circuit layer, wherein the insulating material layer covers a portion of the upper surface;
forming a laser resisting layer on at least a portion of the insulating material layer after forming the insulating material layer;
adhering a release layer to the laser resisting layer;
performing a build-up process so as to laminate a first build-up circuit structure and a second build-up circuit structure on the first patterned circuit layer and the second patterned circuit layer, respectively, wherein the first build-up circuit structure covers the release layer; and
performing a laser ablation process on the first build-up circuit structure to irradiate a laser beam on the laser resisting layer so as to remove a portion of the first build-up circuit structure and the release layer, thereby forming a cavity at least exposing a portion of the upper surface of the core layer.

US Pat. No. 10,178,755

CIRCUIT BOARD STACKED STRUCTURE AND METHOD FOR FORMING THE SAME

UNIMICRON TECHNOLOGY CORP...

1. A circuit board, comprising:a first dielectric layer;
a first circuit layer disposed in the first dielectric layer;
a second circuit layer disposed on the first dielectric layer;
a plurality of conductive vias disposed in the first dielectric layer and connecting the first circuit layer to the second circuit layer;
a second dielectric layer disposed on the first dielectric layer and the second circuit layer and having a plurality of openings to expose a plurality of parts of the second circuit layer;
a patterned seed layer disposed on the exposed parts of the second circuit layer and sidewalls of the openings; and
a plurality of bonding layers respectively disposed on the patterned seed layer, wherein the bonding layers and the patterned seed layer are made of copper, and the bonding layers are porous.

US Pat. No. 10,433,413

MANUFACTURING METHOD OF CIRCUIT STRUCTURE EMBEDDED WITH HEAT-DISSIPATION BLOCK

Unimicron Technology Corp...

1. A manufacturing method of circuit structure embedded with heat-dissipation block, comprising:providing a core board, wherein the core board comprises a first dielectric layer and two first conductive layers, and the two first conductive layers are located on two opposite sides of the first dielectric layer, respectively;
forming two inner-layer circuits on two opposite sides of the core board;
bonding two build-up structures on two opposite sides of the core board, wherein each of the build-up structures comprises a second dielectric layer and a second conductive layer, and the second dielectric layer is located between the second conductive layer and the core board;
forming a cavity on a predetermined region of each of the two build-up structures, wherein the cavity is communicated with the corresponding inner-layer circuit;
forming a through hole penetrated the core board after forming the cavity and bonding the build-up structures, wherein a dimension of the cavity is greater than a dimension of the through hole, and the through hole is communicated with the cavity, and wherein the cavities of the two build-up structures have an overlapping area, the through hole is formed at the overlapping area and communicated with the cavities; and
disposing a heat-dissipation block into the through hole, wherein the through hole is corresponding to the heat-dissipation block, an upper surface and a lower surface of the heat-dissipation block are aligned with two opening ends of the through hole, respectively.

US Pat. No. 10,426,038

MANUFACTURING METHOD OF CIRCUIT BOARD

Unimicron Technology Corp...

1. A manufacturing method of a circuit board, comprising:providing a dielectric substrate, wherein a circuit pattern, a dielectric layer covering the circuit pattern, and a conductive via located in the dielectric layer and connected to the circuit pattern are disposed on the dielectric substrate;
forming a thermal-sensitive adhesive layer on the dielectric layer;
forming a photoresist material layer on the thermal-sensitive adhesive layer;
performing imprinting on the photoresist material layer via a stamp, wherein a first conductive layer is disposed on a surface of a pressing side of the stamp facing the circuit pattern, a second conductive layer is disposed on a surface of other portions of the stamp, and a resistance of the first conductive layer is greater than a resistance of the second conductive layer;
applying a current to the stamp;
removing the stamp and the photoresist material layer and the thermal-sensitive adhesive layer below the pressing side to form a patterned photoresist layer and a patterned thermal-sensitive adhesive layer;
forming a patterned metal layer on a region exposed by the patterned photoresist layer;
removing the patterned photoresist layer;
heating the patterned thermal-sensitive adhesive layer to reduce the adhesion of the patterned thermal-sensitive adhesive layer; and
after heating the patterned thermal-sensitive adhesive layer, removing the patterned thermal-sensitive adhesive layer.

US Pat. No. 10,383,226

MULTI-LAYER CIRCUIT STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A multi-layer circuit structure, comprising:a core layer, having a first surface and a second surface opposite to each other;
a first circuit structure, disposed on the first surface;
a second circuit structure, disposed on the second surface and electrically connected to the first circuit structure; and
a build-up circuit structure, comprising:
a first dielectric layer, disposed on the first circuit structure;
a plurality of first conductive blind holes, penetrating through the first dielectric layer and electrically contacting the first circuit structure, wherein a top surface of each of the first conductive blind holes is coplanar with a top surface of the first dielectric layer;
a second dielectric layer, disposed on the first dielectric layer, wherein the top surface of each of the first conductive blind holes is coplanar with a bottom surface of the second dielectric layer, and there are only the plurality of first conductive blind holes between the first dielectric layer and the second dielectric layer, wherein each of the first conductive blind holes comprises:
a first conductive layer; and
a seed layer, wherein a top surface of the seed layer, a top surface of the first conductive layer, the top surface of the first dielectric layer, and the bottom surface of the second dielectric layer are coplanar, wherein the bottom surface of the second dielectric layer directly and only contacts the top surface of the seed layer, the top surface of the first conductive layer, and the top surface of the first dielectric layer;
a plurality of second conductive blind holes, penetrating through the second dielectric layer and electrically contacting the first conductive blind holes respectively; and
a patterned circuit layer, disposed on the second dielectric layer and electrically contacting the second conductive blind holes.

US Pat. No. 10,271,433

METHOD OF FABRICATING AN ELECTRICAL DEVICE PACKAGE STRUCTURE

Unimicron Technology Corp...

1. A method of packaging an electrical device comprising:providing a circuit board, wherein the circuit board comprises a substrate and a first conductive pattern disposed on the substrate;
patterning the first conductive pattern to form a first caving pattern;
disposing an electrical device on the first conductive pattern of the circuit board, wherein the electrical device has at least one electrode;
forming a dielectric layer on the circuit board to cover the electrical device, the at least one electrode and the first conductive pattern, wherein the dielectric layer is on the first caving pattern;
patterning the dielectric layer to form a through hole extended to the first conductive pattern and forming a second caving pattern in the dielectric layer, the second caving pattern connecting with the through hole and exposing the at least one electrode;
filling a conductive material in the through hole and the second caving pattern to form a conductive via in the through hole and a second conductive pattern in the second caving pattern;
removing the substrate from the first conductive pattern; and
forming a first solder mask and a second solder mask on the first conductive pattern and the second conductive pattern, respectively, wherein the first solder mask exposes portions of the first conductive pattern and the second solder mask exposes portions of the second conductive pattern.

US Pat. No. 10,324,370

MANUFACTURING METHOD OF CIRCUIT SUBSTRATE AND MASK STRUCTURE AND MANUFACTURING METHOD THEREOF

Unimicron Technology Corp...

1. A manufacturing method of a circuit substrate, comprising:providing a substrate;
coating a positive photoresist layer on the substrate; and
performing once exposure process on the positive photoresist layer disposed on the substrate so as to simultaneously form concaves with at least two different depths,
wherein before performing once exposure process on the positive photoresist layer disposed on the substrate, inputting a program data to a direct imaging exposure machine, the program data comprises a desired forming position and an adjustable exposure energy of each of the concaves.