US Pat. No. 9,788,463

SEMICONDUCTOR MEMORY DEVICE HAVING A HEAT INSULATING MECHANISM

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a semiconductor memory unit;
a memory controller;
a cover unit having a first portion covering the semiconductor memory unit and a second portion covering the memory controller;
a first heat conduction member disposed between the semiconductor memory unit and the first portion of the cover unit; and
a second heat conduction member disposed between the memory controller and the second portion of the cover unit, wherein
the cover unit has a gap formed between the first and second portions.

US Pat. No. 9,883,615

SEMICONDUCTOR MEMORY DEVICE HAVING A HEAT CONDUCTION MEMBER

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a substrate having a conductive region on a surface thereof;
a semiconductor memory unit;
a memory controller, at least one of the semiconductor memory unit and the memory controller being disposed on the substrate;
a housing enclosing the substrate; and
a heat conduction member in contact with and pressed between the conductive region and a portion of the housing, wherein the
heat conduction member is made of an electrically-insulating material.

US Pat. No. 10,076,063

ELECTRONIC APPARATUS

Toshiba Memory Corporatio...

1. An electronic apparatus comprising:a first substrate comprising a first face and a second face on an opposite side of the first face and provided with an opening;
a second substrate comprising a third face configured to face the second face and a fourth face on an opposite side of the third face and configured to be electrically connected to the first substrate;
at least one first electronic component configured to be mounted on at least one of the first and second substrates and store information;
a second electronic component configured to be mounted on the third face of the second substrate, control the first electronic components, and be disposed at a position overlapping the opening in a direction in which the third face faces;
a housing configured to accommodate the first and second substrates and comprising a first cover configured to cover the first face of the first substrate;
a first protruding portion provided on the first cover and configured to protrude toward the second electronic component and pass through the opening; and
a first heat transfer member configured to be interposed between the first protruding portion and the second electronic component and connect the first protruding portion and the second electronic component thermally, wherein
the first cover includes a first portion, a second portion, and a fin, the first portion that covers the at least one first electronic component, the second portion that is separate from the first portion and covers the second electronic component, the fin provided on the second portion,
the first protruding portion is provided on the second portion and protrudes in an opposite direction to a direction where the fin protrudes,
the opening is a cutout that is open in an end face of the first substrate,
the end face faces in a first direction,
the second portion includes a first heat radiating portion and a second heat radiating portion,
the first heat radiating portion extends in a second direction intersecting with the first direction,
the second heat radiating portion extends from the first portion in the first direction and covers the second electronic component, and
the first protruding portion is provided on the second heat radiating portion.

US Pat. No. 9,918,385

ELECTRONIC DEVICE

TOSHIBA MEMORY CORPORATIO...

1. An electronic device, comprising:
a substrate;
first conductors complied with a first USB standard on the substrate;
second conductors complied with a second USB standard on the substrate;
a connector connectable to an external connector, the connector mounted on the first conductors or the second conductors;
third conductors on the substrate;
an electronic component electrically connected to the third conductors; and
a first wiring on the substrate, the first wiring connecting one of the first conductors, one of the second conductors, and
one of the third conductors.

US Pat. No. 9,761,466

APPARATUS AND METHOD FOR CLEANING SEMICONDUCTOR SUBSTRATE

TOSHIBA MEMORY CORPORATIO...

1. A cleaning apparatus for a semiconductor substrate, comprising:
a belt conveyor which feeds a semiconductor substrate;
a treatment head which defines a cleaning space through which the semiconductor substrate is fed by the belt conveyor, the
treatment head executing a cleaning treatment, a rinsing treatment and a drying treatment for the semiconductor substrate
passed through the cleaning space;

a rinse water supplying mechanism which supplies rinse water adjusted to a predetermined pH value indicative of acidity to
the treatment head and applies heat to the rinse water thereby to set a temperature of the rinse water to 70° C. or above;
and

an optical mechanism configured to recognize a pattern on the semiconductor substrate so that the semiconductor substrate
can be automatically placed on the belt conveyor with a direction of the pattern recognized by the optical mechanism and a
feeding direction of the belt conveyor having a predetermined relationship,

wherein in the rinsing treatment, the treatment head is configured to rinse the semiconductor substrate for a first treating
time set to not more than 10 seconds and in the drying treatment, the treatment head is configured to dry the semiconductor
substrate for a second treating time set to not more than 10 seconds and to depressurize a part of the semiconductor substrate,
which part is under the drying treatment,

wherein the rinse water supplying mechanism includes a deionized water supplying section, a hydrochloric acid supplying section,
a rinse water mixing section which stores and mixes the deionized water delivered from the deionized water supplying section
and the hydrochloric acid delivered from the hydrochloric acid supplying section, and a control section which controls the
deionized water supplying section and the hydrochloric acid supplying section;

wherein the rinse water mixing section includes a pH sensor which detects a pH value of the rinse water stored in the rinse
water mixing section, a temperature sensor which detects a temperature of the rinse water stored in the rinse water mixing
section, and a heater which applies heat to the rinse water stored in the rinse water mixing section,

wherein the control section is configured to receive detection signals from the pH sensor and the temperature sensor and to
control the heater;

wherein the treatment head includes an upper head and a lower head and is configured to insert the semiconductor substrate
into the cleaning space located between the upper and lower heads of the treatment head and to cause the semiconductor substrate
to pass through the cleaning space while being fed by the belt conveyor;

wherein the treatment head includes a chemical treatment section, a rinse treatment section and a drying treatment section,
all the sections being disposed sequentially from a side of the semiconductor substrate that is firstly inserted into the
cleaning space;

wherein the chemical treatment section is configured to discharge a cleaning chemical onto a surface of the semiconductor
substrate thereby to chemically clean the semiconductor substrate and retrieve the used chemical;

wherein the rinse treatment section is configured to discharge the rinse water onto a surface of the semiconductor substrate
thereby to rinse the semiconductor substrate and retrieve the used rinse water;

wherein the drying treatment section includes a drying treatment mechanism configured to execute both a drying treatment with
use of a drying solvent and lamp annealing in execution of a drying treatment, the drying treatment section being configured
to form a pressure-reduced space above a region of the semiconductor substrate corresponding to the drying treatment section;
and

wherein the semiconductor substrate is aligned on the belt conveyor so that a line-and-space pattern formed thereon extends
in a direction substantially parallel to a direction in which the semiconductor substrate is fed.

US Pat. No. 9,865,345

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY HAVING MEMORY ARRAYS WITH VARIABLE RESISTANCE STORAGE ELEMENTS AND A BIAS VOLTAGE GENERATOR ARRANGED BETWEEN THE ARRAYS

SK hynix Inc., Gyeonggi-...

1. An electronic device including a semiconductor memory unit, wherein the semiconductor memory unit comprises:
a first circuit area including a plurality of first storage cells, each having a variable resistance element and being selected
when a corresponding word line is activated, a first reference resistance element having a first resistance value, and a first
read control unit for reading data of a storage cell selected among the plurality of first storage cells based on a bias voltage;

a second circuit area including a plurality of second storage cells, each having a variable resistance element and being selected
when a corresponding word line is activated, a second reference resistance element having a second resistance value, and a
second read control unit for reading data of a storage cell selected among the plurality of second storage cells based on
the bias voltage, the second circuit area being arranged spaced apart from the first circuit area; and

a third circuit area arranged between the first circuit area and the second circuit area, wherein the third circuit area includes
a word line driving unit for driving a plurality of word lines, and a bias voltage generation unit for generating the bias
voltage based on currents flowing through the first reference resistance element and the second reference resistance element,

wherein the first reference resistance element and the second reference resistance element are arranged adjacent to the third
circuit area.

US Pat. No. 9,785,494

INFORMATION PROCESSING DEVICE, EXTERNAL STORAGE DEVICE, HOST DEVICE, RELAY DEVICE, CONTROL PROGRAM, AND CONTROL METHOD OF INFORMATION PROCESSING DEVICE

TOSHIBA MEMORY CORPORATIO...

1. An information processing system comprising:
a host device and a storage device coupled with the host device;
the storage device including:
a nonvolatile memory including a plurality of blocks; and
a first controller configured to
control the nonvolatile memory,
determine whether a data write operation to the nonvolatile memory is prohibited based on a first value and a first threshold
value, the first value being a value of a number of free blocks, the first threshold value corresponding to the first value,
and

send, when determining the data write operation to the nonvolatile memory is prohibited, information indicating that data
write operation to the nonvolatile memory is prohibited;

the host device being connectable to a display, the host device including a second controller, the second controller configured
to

acquire a second value and a second threshold value from the storage device, the second value being a value of a number of
bad blocks, the second threshold value corresponding to the second value,

cause the display to show a certain message when the acquired second value exceeds the acquired second threshold value, and
recognize the storage device as a read only device that supports only a read operation of read and write operations of the
nonvolatile memory when receiving the information.

US Pat. No. 9,754,888

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:
a plurality of lower electrode films stacked separated from each other;
an upper electrode film provided above the plurality of lower electrode films;
a semiconductor pillar extending in an arrangement direction of the plurality of lower electrode films and the upper electrode
film;

a memory film provided between the semiconductor pillar and one of the plurality of lower electrode films and between the
semiconductor pillar and the upper electrode film; and

a metal-containing layer provided at at least one of on a lower surface and an upper surface of the one of the plurality of
lower electrode films and between the one of the plurality of lower electrode films and the memory film, the metal-containing
layer having a composition different from a composition of the plurality of lower electrode films,

the upper electrode film being in contact with the memory film, and the one of the plurality of lower electrode films not
being in contact with the memory film.

US Pat. No. 9,858,973

VARIABLE CHANGE MEMORY AND THE WRITING METHOD OF THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A writing method of a memory having a memory cell including an MTJ element, comprising:
applying a voltage which oscillates at a predetermined period to the MTJ element; and
applying, to the MTJ element, a predetermined voltage higher than a peak voltage of the voltage which oscillates at the predetermined
period after the voltage which oscillates at the predetermined period is applied to the MTJ element.

US Pat. No. 9,786,380

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a memory cell that includes a charge storage layer;
a word line connected to a gate of the memory cell; and
a controller configured to perform a write operation on the memory cell by applying a write voltage to the word line to shift
a threshold voltage of the memory cell, the write operation including a verify operation on the memory cell after the applying
of the write voltage to verify that the threshold voltage of the memory cell is at least a target value after the write operation,

wherein the verify operation includes a first verify operation using a first verify voltage applied to the word line and a
second verify operation after the first verify operation using a second verify voltage applied to the word line, the second
verify voltage being higher than the first verify voltage, and the controller is configured to increase the write voltage
when the first verify operation fails and the second verify operation passes.

US Pat. No. 9,786,556

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A manufacturing method of a semiconductor device, comprising:
forming, on a film to be processed, a plurality of first core material patterns extending in parallel in a first direction,
and a plurality of second core material patterns, each of the second core material patterns being drawn from an end portion
of the corresponding first core material pattern, the second core material patterns extending in parallel in a second direction
crossing the first direction, a width of the second core material pattern being wider than a width of the first core material
pattern;

forming an opening pattern having one or a plurality of openings in the second core material pattern so that a first distance
and a second distance are less than a predetermined distance, the first distance being a distance between an edge of the second
core material pattern at a side of an adjacent first core material pattern and the opening pattern, the second distance being
a distance between an edge of the second core material pattern at a side of an adjacent second core material pattern and the
opening pattern;

forming a first side wall pattern along external peripheries of the first core material pattern and the second core material
pattern and along an inner periphery of the opening;

removing the first core material pattern and the second core material pattern after forming the first side wall pattern; and
etching the film after removing the first and second core material patterns.

US Pat. No. 9,901,009

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

12. A semiconductor memory device comprising:
a case;
a first substrate which is provided in the case and which includes a first face;
a first element provided on the first face; and
a first heat conduction member disposed between the first element and the case,
wherein the first element includes a control unit, and
the second substrate includes a second face attached to the first face and a third face opposite to the second face,
the control unit is provided on the third face of the second substrate;
the first heat conduction member covers the control unit and is disposed in a state in which the first heat conduction member
is held among the third face, the control unit, and the case and is in thermally close contact with the third face, the control
unit, and the case,

the first heat conduction member is in contact with a part of the third face, and
a first width is greater than a second width, the first width representing a width of the first heat conduction member in
a first direction along the first face at a first position in contact with the case, the second width representing a width
of the first heat conduction member in the first direction at a second position farther away from the case than the first
position.

US Pat. No. 9,792,983

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A memory device, comprising:
a nonvolatile semiconductor memory cell array;
a plurality of terminals through which control signals are received to control the memory device, the plurality of terminals
including a first terminal to receive data, a second terminal to receive a clock signal, and a third terminal to receive a
read enable signal;

an on-die termination circuit connected to at least one of the first, second, and third terminals and having a variable resistor;
and

a control circuit configured to enable the on-die termination circuit in response to an enabling signal to enable the on-die
termination circuit, a resistance of the variable resistor of the on-die termination circuit being set at different values
depending on whether a control signal is asserted or deasserted when the enabling signal is received.

US Pat. No. 9,792,996

SEMICONDUCTOR MEMORY DEVICE WHICH APPLIES MULTIPLE VOLTAGES TO THE WORD LINE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a first word line coupled to a first memory cell; and
a driver configured to apply a voltage to the first word line to read data in page units,
wherein a first page data associated with the first word line is read by a first reading using a first voltage and by a second
reading using a second voltage,

wherein the driver is further configured to:
apply a third voltage to the first word line during a first phase of the first reading, wherein a potential of the first word
line is a fourth voltage before applying the third voltage, and the third voltage is higher than the first voltage by an amount
which is based on a first difference, the first difference being a difference between the fourth voltage and the first voltage,

apply the first voltage to the first word line during a second phase of the first reading after the first phase of the first
reading,

apply a fifth voltage to the first word line during a first phase of the second reading, wherein the fifth voltage is higher
than the second voltage by an amount which is based on a second difference, the second difference being a difference between
the first voltage and the second voltage, and

apply the second voltage to the first word line during a second phase of the second reading after the first phase of the second
reading,

wherein the second difference is greater than the first difference, and a difference between the fifth voltage and the second
voltage is greater than a difference between the third voltage and the first voltage, and

wherein the first page data is sensed in the second phases of the first and second readings, respectively.

US Pat. No. 9,997,533

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A method for manufacturing a semiconductor device, comprising:making a first through-portion in a stacked body, the first through-portion extending in a stacking direction, the stacked body including a first layer, a second layer, and a sacrificial layer provided between the first layer and the second layer;
making a first gap while causing one portion of the sacrificial layer to remain between the first layer and the second layer by etching the sacrificial layer through the first through-portion, the first gap communicating with the first through-portion;
forming a first film and causing a second gap to remain on an inner side of the first film, the first film being formed along a surface of the first layer adjacent to the first through-portion, along a surface of the first layer adjacent to the first gap, along a surface of the one portion of the sacrificial layer adjacent to the first gap, along a surface of the second layer adjacent to the first gap, and along a surface of the second layer adjacent to the first through-portion, the second gap communicating with the first through-portion;
forming a second film in the second gap and on a side surface of the first film adjacent to the first through-portion;
making a second through-portion in a region of the stacked body where the one portion of the sacrificial layer remains, the second through-portion extending in the stacking direction;
exposing a first portion of the second film by etching the first film through the second through-portion, the first portion being formed in the second gap; and
dividing the second film in the stacking direction by causing etching of at least a portion of the first portion of the second film to progress from an exposed portion of the first portion through the second through-portion.
US Pat. No. 9,772,566

MASK ALIGNMENT MARK, PHOTOMASK, EXPOSURE APPARATUS, EXPOSURE METHOD, AND MANUFACTURING METHOD OF DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A mask alignment mark disposed on a photomask irradiated by an illumination optical system with illumination light from
a direction inclined with respect to an optical axis and used to form a latent image on a substrate through a projection optical
system, the mask alignment mark comprising:
a plurality of patterns arranged in a predetermined direction at a pitch of substantially
P=?/{2×(1??)×(LNA)}

where ? is a ratio of a numerical aperture INA of illumination light incident on the photomask from the illumination optical
system to a numerical aperture LNA of an object side of the projection optical system (INA)/(LNA), and ? is a wavelength of
light.

US Pat. No. 9,773,697

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method of manufacturing a semiconductor device, comprising:
forming a first insulating layer on a first surface of a semiconductor substrate comprising silicon;
forming a conductive layer on the first insulating layer;
forming a first opening that extends from a second surface of the semiconductor substrate opposite to the first surface toward
the first surface, the first opening extending in the semiconductor substrate to the first insulating layer;

performing a first annealing process in a first gas atmosphere that contains hydrogen after formation of the first opening;
forming a second insulating layer on a side wall of the semiconductor substrate in the first opening;
performing a second annealing process after formation of the second insulating layer;
forming a second opening that extends in the first insulating layer to the conductive layer through the first opening; and
forming a through-via in the first and second openings that is connected to the conductive layer.

US Pat. No. 9,733,690

COMMUNICATION DEVICE WHICH DECREASES POWER COMSUMPTION BY POWERING OFF UNUSED FUNCTIONS WHEN DEVICE IS INACTIVE

TOSHIBA MEMORY CORPORATIO...

1. A communication device comprising:
a register to receive data via an input data line; and
a selector to select either a signal in the input data line or a synchronization signal from a synchronization signal generator,
wherein

the communication device
in a first state in which the selector selects the synchronization signal, when a condition in which data is not sent to the
input data line continues for a certain period of time, controls the selector to select the signal in the input data line,
controls an electrical power controller, which controls supply of electrical power to the communication device, to stop the
supply of the electrical power to the synchronization signal generator and the register, and switches the first state of the
communication device to a second state; and

in the second state, when a wake-up signal from the input data line is sent via the selector, controls the selector to select
the synchronization signal, controls the electrical power controller to resume the supply of the electrical power to the synchronization
signal generator and the register, and switches the second state of the communication device to the first state.

US Pat. No. 9,793,102

SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD

Toshiba Memory Corporatio...

1. A semiconductor manufacturing apparatus comprising:
a stage provided in a chamber;
a conveying module configured to convey a plurality of wafers into the chamber and to set the plurality of wafers on the stage;
a controller configured to divide treatment time for simultaneously treating the plurality of wafers on the stage into first
to K-th treatment periods where K is an integer of two or more, and to change positions of one or more of the plurality of
wafers on the stage by the conveying module according to the treatment periods.

US Pat. No. 9,858,998

SEMICONDUCTOR STORAGE DEVICE AND CONTROL METHOD OF SEMICONDUCTOR STORAGE DEVICE WITH DETECTING LEVELS OF A MULTI-ARY SIGNAL

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device, comprising:
N word lines, N being an integer of four or greater;
M bit lines that intersect with the word lines, M being an integer of two or greater;
multiple memory cells placed at positions where the word lines and the bit lines intersect, the memory cell storing binary
data; and

a read circuit connected to the M bit lines, the read circuit detecting levels of a multi-ary signal,
wherein the read circuit detects levels of a quarternary signal on a bit line selected from the M bit lines, and
the semiconductor storage device performs an error operation if data based on the detection results for signal levels is determined
to be incorrect.

US Pat. No. 9,786,377

MEMORY DEVICE

Toshiba Memory Corporatio...

1. A memory device comprising:
a memory cell array including a plurality of memory cell groups; and
a decoder circuit configured to control selection of the memory cell groups, the decoder circuit including:
an address decoder circuit including a plurality of first transistors of which channels are connected in series, and configured
to activate the decoder circuit based on an input address, wherein the number of the first transistors corresponds to a number
of bits of the input address, and signals corresponding to the input address are input to gates of the first transistors,

a plurality of information retention circuits, each of which corresponds to one of the memory cell groups and outputs a signal
that indicates whether or not the corresponding memory cell group is defective,

a second transistor having a gate connected to each of the outputs of the information retention circuits and a channel connected
in series to the channels of the first transistors, and

a signal output circuit configured to output a control signal for selecting or not selecting the memory cell groups based
on an on/off state of the second transistor.

US Pat. No. 9,786,678

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device, comprising:
a plurality of conductive layers stacked in a first direction via an inter-layer insulating layer;
a semiconductor layer having the first direction as a longer direction;
a tunnel insulating layer contacting a side surface of the semiconductor layer;
a charge accumulation layer contacting a side surface of the tunnel insulating layer; and
a block insulating layer contacting a portion facing the conductive layer, of a side surface of the charge accumulation layer,
the charge accumulation layer including:
a first portion facing the conductive layer and extending in the first direction, and
a second portion facing the inter-layer insulating layer and extending in the first direction,
the first portion being thinner than the second portion, and
a film thickness of the second portion of the charge accumulation layer in a second direction crossing the first direction
being approximately constant.

US Pat. No. 9,786,679

METHOD FOR MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor memory device comprising:
forming a stacked body on a substrate, the stacked body including a plurality of first layers and a plurality of second layers
respectively provided between the first layers;

forming a mask layer on the stacked body;
forming a stopper film of a different material from a material of the stacked body in a part of the mask layer;
forming a plurality of mask holes in the mask layer, the mask holes including a first mask hole overlapping on the stopper
film;

by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the
stopper film, but not forming holes in the stacked body under the stopper film; and

forming memory films and channel bodies in the holes.

US Pat. No. 9,784,573

POSITIONAL DEVIATION MEASURING DEVICE, NON-TRANSITORY COMPUTER-READABLE RECORDING MEDIUM CONTAINING A POSITIONAL DEVIATION MEASURING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A positional deviation measuring device comprising:
an adjusting unit configured to adjust a refracting angle of incident light with respect to a substrate;
a detector configured to detect reflected lights from the substrate; and
a calculating unit configured to calculate positional deviation of a pattern based on patterns respectively reflected in the
reflected lights obtained from incident light generating N number of refracting angles with respect to the substrate, where
N is an integer of two or greater.

US Pat. No. 9,780,105

SEMICONDUCTOR MEMORY DEVICE INCLUDING A PLURALITY OF COLUMNAR STRUCTURES AND A PLURALITY OF ELECTRODE FILMS

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a stacked body including a plurality of electrode films stacked along a first direction and separated from each other;
a plurality of columnar structures extending in the first direction, piercing the stacked body, and including a semiconductor
layer;

a charge storage portion provided between one of the columnar structures and one of the electrode films; and
an insulating film dividing one of the electrode films disposed in an upper portion of the stacked body and not dividing other
one of the electrode films disposed in a lower portion of the stacked body, wherein

a shortest distance between the columnar structures disposed on one side of the insulating film being shorter than a shortest
distance between the columnar structures disposed with the insulating film interposed between the columnar structures,

the insulating film extends in a second direction crossing the first direction,
as viewed from the first direction, the plurality of columnar structures is not disposed at first lattice points and is disposed
at second lattice points except for the first lattice points, among lattice points of a lattice, the first lattice points
being located in the insulating film and being arranged in a row along the second direction,

the lattice being configured of a plurality of first imaginary straight lines and a plurality of second imaginary straight
lines,

the plurality of first imaginary straight lines extending in a third direction crossing the first direction and arranged at
equal intervals, and

the plurality of second imaginary straight lines extending in a fourth direction crossing the third direction and arranged
at equal intervals.

US Pat. No. 9,761,307

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a first memory cell capable of storing data of n bits (n is a natural number equal to 2 or more);
a control circuit configured to receive a first data of n bits and write the first data into the first memory cell in a first
program sequence, and receive a second data smaller than the first data and write the first data into the first memory cell
by using the second data in a second program sequence,

wherein the second data is acquired by executing an arithmetic operation of exclusive NOR with respect to the first data.

US Pat. No. 9,754,676

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a first semiconductor chip which outputs data, the first semiconductor chip including a first via which conducts from the
upper surface to the lower surface thereof;

a second semiconductor chip which is connected to the first via by a first bump;
a first FIFO which is formed on the second semiconductor chip and receives the data outputted from the first semiconductor
chip through the first via and the first bump; and

an input/output circuit which outputs the data from the first FIFO and is formed on the second semiconductor chip,
wherein the first FIFO is located closer to the input/output circuit than a middle point of an interconnect line connected
between the first bump and the input/output circuit.

US Pat. No. 9,793,293

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a stacked body including a plurality of electrode layers stacked with an insulator interposed;
a columnar portion provided in the stacked body and extending in a stacking direction of the electrode layers; and
a first separation region provided in the stacked body and extending in a first direction,
the stacked body including a memory cell array and a staircase portion arranged in the first direction, the memory cell array
including memory cells provided along the columnar portion, and the staircase portion including a plurality of terraces arranged
along the first direction, and

the first separation region including a first portion and a second portion in the staircase portion, the first portion having
a first width in a second direction crossing the first direction, and the second portion having a second width in the second
direction, the second width being narrower than the first width.

US Pat. No. 9,780,111

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor device comprising:
a substrate;
a stacked body including a plurality of metal layers, a plurality of insulating layers, and a plurality of intermediate layers
stacked on a major surface of the substrate;

a film having semi-conductivity or conductivity extending in the stacked body in a stacking direction of the stacked body;
and

a memory film provided between the film and the metal layers,
the metal layers being tungsten layers and the intermediate layers being tungsten nitride layers, or the metal layers being
molybdenum layers and the intermediate layers being molybdenum nitride layers,

the intermediate layer being provided between a lower surface of the metal layer and the insulating layer, the intermediate
layer being not provided between an upper surface of the metal layer and the insulating layer, and the intermediate layer
being in contact with the metal layer.

US Pat. No. 9,785,384

SEMICONDUCTOR STORAGE DEVICE AND METHOD FOR CONTROLLING NONVOLATILE SEMICONDUCTOR MEMORY

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:
a nonvolatile semiconductor memory; and
a controller configured to
when receiving a write instruction and first data specified by a write instruction from a host, and in a case where a first
amount does not exceed a current storage capacity of the nonvolatile semiconductor memory, write the first data to the nonvolatile
semiconductor memory based on the received write instruction, the first amount being a sum of current amount of valid data
in the nonvolatile semiconductor memory and data amount corresponding to addresses which are unwritten in the nonvolatile
semiconductor memory among logical addresses contained in the received write instruction.

US Pat. No. 9,748,075

APPARATUS FOR MANUFACTURING TEMPLATE AND METHOD FOR MANUFACTURING TEMPLATE

Toshiba Memory Corporatio...

1. An apparatus for manufacturing a template, comprising:
a vacuum chamber including an inlet and an exhaust port of a reactive gas, the vacuum chamber being capable of maintaining
an atmosphere depressurized below an atmospheric pressure;

an electrode, provided in an interior of the vacuum chamber, for receiving a high frequency voltage to be applied thereto,
a substrate to form the template being placed on the electrode, the substrate having a back surface on a side of the electrode,
a recess being provided in the back surface;

an adjustor being configured to be inserted into the recess, the adjustor being an insulator; and
a guide plate provided in a peripheral portion of an upper surface of the electrode to guide the substrate, the guide plate
being insulative;

wherein
a side surface of the adjustor conforms to an inner surface of the recess.

US Pat. No. 9,773,859

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A non-volatile memory device comprising:
a memory area including a memory cell; and
a peripheral area including a circuit that drives the memory cell, the circuit including a first resistance element,
the first resistance element including:
a first conductive layer extending in a first direction,
a second conductive layer provided on the first conductive layer, the second conductive layer having a first opening and a
second opening aligned in the first direction with the first opening, and the first conductive layer having a first end close
to the first opening and a second end close to the second opening,

a first insulating layer extending between the first conductive layer and the second conductive layer, the first opening and
the second opening of the second conductive layer being in communication with the first insulating layer, and the second conductive
layer having an end portion in contact with the first conductive layer at the first end,

a first contact plug provided in the first opening and extending through the first insulating layer to contact the first conductive
layer, and

a second contact plug provided in the second opening and extending through the first insulating layer to contact the first
conductive layer,

the first resistance element having a first distance from the first contact plug to the second contact plug, a second distance
from the first contact plug to the first end, and a third distance from the second contact plug to the second end, and the
first distance being larger than the second distance and the third distance.

US Pat. No. 9,773,797

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device comprising:
a plurality of memory cells stacked in a first direction and electrically connected in series; and
a selection transistor provided above the memory cells,
at least one of the memory cells including:
a control gate electrode;
a first channel extending in the first direction through the control gate electrode;
a first insulating core film provided inside the first channel;
a conductive layer provided between the control gate electrode and the first channel;
a first insulating film provided between the conductive layer and the first channel; and
a second insulating film provided between the control gate electrode and the conductive layer,
a width of the conductive layer in the first direction being narrower than a width of the second insulating film in the first
direction, and the control gate electrode surrounding an outer periphery of the conductive layer via the second insulating
film in a plane perpendicular to the first direction, and

the selection transistor including:
a selection gate electrode; and
a second channel extending in the first direction through the selection gate electrode, the second channel being connected
to one end of the first channel and not overlapping with the control gate electrode when projected from the first direction.

US Pat. No. 9,773,803

NON-VOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A non-volatile memory device comprising:
a first conductive layer;
an interconnection layer including a first interconnection and a second interconnection;
electrodes between the first conductive layer and the interconnection layer, the electrodes being arranged in a first direction
perpendicular to the first conductive layer;

at least one semiconductor layer extending through the electrodes in the first direction, one end of the semiconductor layer
being electrically connected to the first conductive layer, and the other end of the semiconductor layer being electrically
connected to the first interconnection;

a charge storage portion provided between respective electrodes and the semiconductor layer; and
a conductive body extending in the first direction between the first conductive layer and the second interconnection, the
conductive body electrically connecting the first conductive layer and the second interconnection, and including a first portion
and a second portion,

the first portion being connected to the first conductive layer, and the second portion being electrically connected to the
second interconnection and having a width in a second direction orthogonal to the first direction that is wider than a width
of the first portion in the second direction, and

the first portion has a length in the first direction shorter than an interval between the first conductive layer and one
of the electrodes closest to the first conductive layer among the electrodes.

US Pat. No. 9,867,297

STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A storage device comprising:
an enclosure; and
a circuit board assembly accommodated in the enclosure,
the circuit board assembly comprising:
a first circuit board on which a memory device is mounted,
a second circuit board opposed to the first circuit board, on which a memory device is mounted,
a third circuit board opposed to the second circuit board, on which a memory device is mounted,
a first board-to-board connector provided between the first circuit board and the second circuit board, to connect the first
circuit board and the second circuit board to each other,

a second board-to-board connector provided between the second circuit board and the third circuit board to connect the second
circuit board and the third circuit board to each other, and shifted with respect to the first board-to-board connector in
a plane direction of the second circuit board,

a frame-shaped first spacer sandwiched between the first circuit board and the second circuit board, and
a frame-shaped second spacer sandwiched between the second circuit board and the third circuit board,
the first spacer comprising a support body provided at a position opposed to the second board-to-board connector and brought
into contact with the first circuit board and the second circuit board.

US Pat. No. 9,865,616

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a stacked body including a plurality of electrode films and air gaps, the plurality of electrode films being disposed to be
separated from each other along a first direction, each of the air gaps being made between the electrode films;

a semiconductor pillar extending in the first direction and piercing the stacked body;
a plurality of charge storage films provided between the semiconductor pillar and the plurality of electrode films, the plurality
of charge storage films being partitioned every electrode film;

a substrate disposed on the first-direction side of the stacked body;
a plurality of conductive members piercing the stacked body and being connected to the substrate;
a plurality of capping films disposed between the conductive member and the plurality of electrode films; and
an insulating film disposed between the charge storage films, between the electrode films, between the capping films, and
between the capping film and the conductive member, the insulating film being formed of an insulating material different from
a material of the capping film,

the air gaps being made inside the insulating film.

US Pat. No. 9,793,111

SPIN COATING METHOD AND MANUFACTURING METHOD OF ELECTRONIC COMPONENT

Toshiba Memory Corporatio...

1. A spin coating method comprising:
forming a first material film on an underlying material;
rotating the underlying material while a solution of a second material film is supplied onto an upper surface of the first
material film, to make the solution stay on the upper surface of the first material film;

stopping the rotating of the underlying material or reducing a rotational speed of the underlying material to 10 rpm or less;
and

spinning off the solution from the upper surface of the first material film by rotating the underlying material after a first
period elapses after the stopping of the rotating of the underlying material, or by increasing the rotational speed of the
underlying material after the first period elapses after the reducing of the rotational speed of the underlying material,

wherein when the solution is spun off, the solution is supplied onto the upper surface of the first material film, the supplying
of the solution is stopped and rotation is then performed for a certain period of time, and thereafter the solution is spun
off.

US Pat. No. 9,785,383

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:
a nonvolatile memory including a memory cell configured to store two or more bit data; and
a controller circuit configured to receive a read request from a host, and perform processing according to the read request,
wherein

the controller circuit includes:
a command issuing circuit configured to issue a first command for single read of first data from the nonvolatile memory,
a decoder configured to perform first error correction on the read first data,
a counter configured to count a number of times of multiple reads, and
a statistical processor configured to perform statistical processing of results of the multiple reads, and output second data
obtained by the statistical processing,

the command issuing circuit issuing a second command for multiple reads of the first data, each read of the multiple reads
using an identical read voltage, when the decoder detects an uncorrectable error in the first error correction on the read
first data.

US Pat. No. 9,786,680

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a semiconductor substrate, a first portion and a second portion of an upper layer portion of the semiconductor substrate being
conductive;

an insulating member provided on the semiconductor substrate, the insulating member electrically isolating the first portion
from the second portion;

a first stacked body provided in a region directly above the second portion of the semiconductor substrate, the first stacked
body including a plurality of first insulating films and a plurality of electrode films, each of the first insulating films
and each of the electrode films being stacked alternately;

a semiconductor pillar provided inside the first stacked body, the semiconductor pillar extending in a stacking direction
of the first insulating films and the electrode films;

a charge storage film provided between the semiconductor pillar and the electrode films;
a second stacked body provided in a region directly above the first portion of the semiconductor substrate, the second stacked
body including a plurality of second insulating films and a plurality of third insulating films, each of the second insulating
films and each of the third insulating films being stacked alternately;

two first conductive pillars provided inside the second stacked body, the two first conductive pillars extending in the stacking
direction, lower ends of the two first conductive pillars being connected to the first portion;

two second conductive pillars provided inside the second stacked body, the two second conductive pillars extending in the
stacking direction; and

an interconnect provided on the second stacked body and connected between one of the two first conductive pillars and one
of the two second conductive pillars,

the insulating member electrically isolating a third portion of the upper layer portion of the semiconductor substrate from
the first portion and the second portion, the third portion being conductive,

lower ends of the two second conductive pillars being connected to the third portion.

US Pat. No. 9,767,908

SEMICONDUCTOR MEMORY DEVICE THAT APPLIES AN INITIAL PASS VOLTAGE FOLLOWED BY A FINAL PASS VOLTAGE TO NON-SELECTED WORD LINES DURING A WRITE OPERATION

Toshiba Memory Corporatio...

1. A non-volatile semiconductor memory device comprising:
a first memory cell above a substrate and electrically connected to a first word line;
a second memory cell above the first memory cell and electrically connected to a second word line; and
a controller configured to execute a write operation that includes a first step, a second step after the first step, and a
third step after the second step, wherein

in the first step, a first voltage is applied to the first word line and to a first non-selected word line when the first
memory cell is being written, and a second voltage that is lower than the first voltage is applied to the second word line
and to a second non-selected word line when the second memory cell is being written;

in the second step, a first program voltage is applied to the first word line when the first memory cell is being written,
and a second program voltage is applied to the second word line when the second memory cell is being written;

in the third step, a third voltage higher than the first and second voltages is applied to the first non-selected word line
when the first memory cell is being written and to the second non-selected word line when the second memory cell is being
written; and

a time period between a start of the second step and a start of the third step is different depending on whether the first
memory cell is being written or the second memory cell is being written.

US Pat. No. 9,756,033

INFORMATION RECORDING APPARATUS WITH SHADOW BOOT PROGRAM FOR AUTHENTICATION WITH A SERVER

TOSHIBA MEMORY CORPORATIO...

1. An information apparatus to be coupled to a server, comprising:
a storage device to store data; and
a host device coupled to the storage device,
the storage device comprising,
a first storage that stores a first program, the first program including a program for authentication with the server, the
authentication using authentication information input by a user,

a second storage that stores a second program,
a third storage that stores an operating system,
a fourth storage that stores arbitrary data, and
a fifth storage that stores first information indicating whether or not at least one of the third storage and the fourth storage
is locked;

the host device comprising,
a processor programmed to execute the first program, the second program, and the operating system;
wherein when the information apparatus is started up,
the processor is programmed to cause the storage device to transmit at least the first program to the host device,
the processor is programmed to execute at least the first program before executing the operating system, and
pursuant to which the authentication is performed, if the authentication succeeds, the storage device permits the host device
to access at least one of the third storage and the fourth storage, and the processor is programmed to execute the operating
system.

US Pat. No. 9,786,381

SEMICONDUCTOR MEMORY DEVICE THAT DETERMINES A DETERIORATION LEVEL OF MEMORY CELLS AND AN OPERATION METHOD THEREOF

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a memory cell unit including a plurality of blocks, each of the blocks including a plurality of pages; and
a circuit configured to
count a number of activated or non-activated memory cells in one or more pages when a first voltage is applied to gates of
memory cells of said one or more pages to read data therefrom,

count a number of activated or non-activated memory cells in said one or more pages when a second voltage different from the
first voltage is applied to the gates of the memory cells of said one or more pages to read data therefrom,

compare the counted numbers, and
store, in a register, data about deterioration of the memory cells of said one or more pages depending on a comparison result.

US Pat. No. 9,863,764

STORAGE MEDIUM, SHAPE CALCULATION DEVICE, AND SHAPE MEASUREMENT METHOD

Toshiba Memory Corporatio...

1. A non-transitory computer readable medium that records a shape calculation program which causes a computer to calculate
a shape of a periodic structure and to perform:
extracting, from a first scattering profile of electromagnetic waves obtained when the electromagnetic waves are incident
on a first periodic structure on a substrate, a second scattering profile, on the basis of a certain condition;

extracting, from a third scattering profile calculated using a second periodic structure that is virtually set, a fourth scattering
profile, on the basis of the certain condition;

fitting the second scattering profile and the fourth scattering profile; and
calculating a shape of the first periodic structure on the basis of the result of the fitting.

US Pat. No. 9,818,487

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a memory block including a plurality of memory strings, the plurality of memory strings including a first memory string and
a second memory string, the first memory string including a first transistor, a second transistor and a plurality of first
memory cells, the second memory string including a third transistor, a fourth transistor and a plurality of second memory
cells;

a first bit line connected to a node of the first transistor and a node of the third transistor;
a first select gate line connected to a gate of the first transistor;
a second select gate line connected to a gate of the third transistor;
a source line connected to a node of the second transistor and a node of the fourth transistor;
a plurality of word lines, each of the word lines connected to one of gates of the first memory cells and one of gates of
the second memory cells;

a controller configured to control an erase verify operation of the memory block, wherein the erase verify operation includes:
applying a first selection voltage to the first select gate line at a first time;
while applying the first selection voltage to the first select gate line, applying an erase verify voltage to the plurality
of word lines; and

applying a second selection voltage to the second select gate line at a second time after the first time without making the
voltage applied to the plurality of word lines zero voltage at any time between the first time and the second time.

US Pat. No. 9,792,214

CACHE MEMORY FOR PARTICULAR DATA

Toshiba Memory Corporatio...

1. A cache unit comprising:
a first memory configured to temporarily hold data and an address of the data;
a second memory configured to temporarily hold an address of a particular data set in advance, the particular data being not
held by the first memory; and

a controller comprising a first comparison/control module that includes a data comparing module configured to judge whether
arbitrary data is the particular data or not and an address comparing module configured to search for a storage destination
of an arbitrary address,

wherein, when an instruction to load first data is made for a first specified address, the controller searches for a storage
destination of the first specified address, outputs the data of the first specified address if the storage destination is
the first memory, and outputs the particular data if the storage destination is the second memory, and

wherein, when an instruction to store a specified data at a second specified address is made, the controller judges whether
the specified data is the particular data or not, stores the second specified address and the specified data into the first
memory if the specified data is not the particular data, and stores the second specified address into the second memory if
the specified data is the particular data.

US Pat. No. 9,779,808

RESISTANCE RANDOM ACCESS MEMORY DEVICE AND METHOD FOR OPERATING SAME

TOSHIBA MEMORY CORPORATIO...

1. A resistance random access memory device, comprising:
a first interconnect layer including a plurality of first interconnects, the plurality of first interconnects extending in
a first direction and being arranged along a second direction, the second direction crossing the first direction;

a second interconnect layer including a plurality of second interconnects and being arranged in a third direction with the
first interconnect layer, the third direction being orthogonal to both the first direction and the second direction, the plurality
of second interconnects extending in the second direction and being arranged along the first direction;

variable resistance members connected between the first interconnects and the second interconnects; and
a control circuit applying a first voltage between the plurality of second interconnects and one of the first interconnects
for a first time when switching resistance states of the variable resistance members from a first state to a second state,
and the control circuit applying a second voltage between the plurality of second interconnects and the one of the first interconnects
for a second time after applying the first voltage when the resistance state of one or more of the variable resistance members
of a plurality of the variable resistance members connected to the one of the first interconnects is in the first state, the
second voltage having the same polarity as the first voltage and being lower than the first voltage, the second time being
longer than the first time.

US Pat. No. 9,780,147

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising a memory cell array and a control circuit,
the memory cell array including:
a plurality of first conductive layers that are stacked in a first direction perpendicular to a substrate and extend in a
second direction parallel to the substrate;

a memory layer provided on a side surface of the plurality of the first conductive layers; and
a second conductive layer that extends in the first direction and includes a first side surface that contacts the side surface
of the plurality of the first conductive layers via the memory layer,

a first width in the second direction of the first side surface of the second conductive layer at a first position in the
first direction being larger than a second width in the second direction of the first side surface of the second conductive
layer at a second position in the first direction nearer to the substrate than the first position, and a third width in the
second direction of the first side surface of the second conductive layer at a third position in the first direction between
the first position and the second position being smaller than the first width and larger than the second width,

a first thickness in the first direction of the first conductive layer disposed at the first position being smaller than a
second thickness in the first direction of the first conductive layer disposed at the second position, and a third thickness
in the first direction of the first conductive layer disposed at the third position being larger than the first thickness
and smaller than the second thickness,

the control circuit being configured to apply a first voltage to a selected first conductive layer of the first conductive
layers and provide a second voltage to the second conductive layer, and

the control circuit being configured to, when the control circuit applies the first voltage to the selected first conductive
layer, change a value of the first voltage based on a relative position in the first direction of the selected first conductive
layer.

US Pat. No. 9,748,091

SUBSTRATE TREATMENT APPARATUS AND SUBSTRATE TREATMENT METHOD

TOSHIBA MEMORY CORPORATIO...

1. A substrate treatment method comprising:
housing a substrate in a housing;
supplying chemicals including a first chemical that contains a silylation agent in a gas state to the substrate in the housing,
the chemicals including a chemical having a first boiling point and a chemical having a second boiling point lower than the
first boiling point; and

cooling the substrate in the housing while supplying any of the chemicals to the substrate in the housing,
the method further comprising
supplying the chemical having the first boiling point to the substrate after supplying the chemical having the second boiling
point to the substrate; and

supplying the chemical having the second boiling point to the substrate again after supplying the chemical having the first
boiling point to the substrate.

US Pat. No. 9,773,563

MEMORY CONTROLLER, MEMORY CONTROL METHOD, AND COEFFICIENT DECISION METHOD

TOSHIBA MEMORY CORPORATIO...

1. A memory controller comprising:
circuitry configured to
acquire a distribution of threshold voltages of a plurality of memory cells from a nonvolatile memory, the nonvolatile memory
including the plurality of memory cells;

compare a characteristic value and a condition, and identify a malfunction state occurring in the nonvolatile memory based
on a result of the comparison, the characteristic value indicating a shape characteristic of the distribution, the condition
defining a range of an obtainable characteristic value in plural types of the malfunction states; and

set a read voltage when data is read out of the nonvolatile memory to a voltage value corresponding to a type of the malfunction
state.

US Pat. No. 9,755,000

MEMORY DEVICE

Toshiba Memory Corporatio...

1. A memory device comprising:
a substrate;
a first contact extending in a first direction that crosses a surface of the substrate;
a second contact extending in the first direction, the first and second contacts being aligned in a second direction along
the surface of the substrate;

a first conductive layer above the substrate and extending in a third direction that is along the surface of the substrate
and crosses the second direction, the first conductive layer being formed between the first contact and the second contact
in the second direction, and electrically connected to and in direct contact with the first contact and the second contact;

a second conductive layer above the first conductive layer in the first direction and extending in the third direction, the
second conductive layer being formed between the first contact and the second contact in the second direction, and electrically
insulated and physical separated from the first contact and the second contact.

US Pat. No. 9,816,004

LITHOGRAPHY PATTERN FORMING METHOD USING SELF-ORGANIZING BLOCK COPOLYMER

Toshiba Memory Corporatio...

1. A pattern forming method, comprising:
forming a guide mask layer on a first material layer, the guide mask layer including a first pattern feature having a first
opening width, a second pattern feature having a second opening width, and a third pattern feature with a third opening width,
the first opening width being less than the second opening width and greater than the third opening width;

disposing a self-organizing material having a phase-separation period on the guide mask layer to at least partially fill the
first, second, and third pattern features in the guide mask layer;

processing the self-organizing material disposed on the guide mask layer to cause the self-organizing material to phase separate
into first and second polymer portions, the first opening width being greater than or equal to the phase-separation period
and the third opening width being less than the phase-separation period;

forming a masking pattern on the first material layer by removing the second polymer portions and leaving the first polymer
portions; and

transferring the masking pattern to the first material layer, wherein
a thickness of the self-organizing material formed in the second pattern feature is less than a thickness of the guide mask
layer on the first material layer, and

a thickness of the self-organizing material formed in the third pattern feature is greater than the thickness of the guide
mask layer.

US Pat. No. 9,778,978

MEMORY DEVICE AND MEMORY SYSTEM WITH SENSOR

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:
memory cells;
an error correction circuit; and
a controller,
wherein, in a write operation:
the error correction circuit receives data to be written to the memory cells, and uses the data and a first matrix to generate
a parity, and

the controller writes the data and the parity to the memory cells;
wherein, in a read operation:
the controller reads, from the memory cells, data and parity previously written, and supplies the read data and parity to
the error correction circuit,

the error correction circuit receives the read data and parity, and uses the read data and parity and a second matrix to generate
a syndrome, and

the error correction circuit uses the syndrome to detect an error of the read data and parity, and to correct an error of
the read data when the read data and parity include one-bit or two-bit errors,

wherein the second matrix includes a first and a second portion, the first portion being identical to the first matrix, and
the second portion being a unit matrix, and

wherein an XOR of any two columns of the second matrix is different from an XOR of any other two columns of the second matrix
and any column of the second matrix.

US Pat. No. 9,780,170

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a memory cell, and
a control unit that performs a write operation and an erase operation to the memory cell,
the memory cell comprising: an oxide semiconductor layer; a gate electrode; and a charge accumulation layer disposed between
the oxide semiconductor layer and the gate electrode,

the oxide semiconductor layer including a stacked structure of an n type oxide semiconductor layer and a p type oxide semiconductor
layer,

wherein the control unit, during the erase operation, provides a higher voltage to the oxide semiconductor layer than to the
gate electrode.

US Pat. No. 9,773,555

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:
a first block of memory cells including a first word line above a substrate, a second word line above the first word line,
and a third word line above the second word line;

a first control gate line electrically connected to the first word line;
a second control gate line electrically connected to the second word line and between the first control gate line and the
first block;

a third control gate line electrically connected to the third word line and between the second control gate line and the first
block; and

a fourth control gate line between the second and third control gate lines and electrically connected to a fourth word line
that is between the first and second word lines.

US Pat. No. 9,865,612

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a semiconductor substrate;
a stacked body having a plurality of first insulating layers and conductive layers stacked alternately on the semiconductor
substrate;

a columnar semiconductor layer being provided above the semiconductor substrate in the stacked body, being provided extending
in a stacking direction of the stacked body and including a first portion and a second portion which is provided above the
first portion;

a memory layer provided on a side surface of the columnar semiconductor layer facing the stacked conductive layers and extending
along the columnar semiconductor layer; and

a second insulating layer provided between one of the first insulating layers of the stacked body and the conductive layer,
the columnar semiconductor layer having a boundary of the first portion and the second portion, the boundary being close to
the second insulating layer,

an average value of an outer diameter of the memory layer facing a side surface of the second insulating layer being larger
than that of the memory layer facing a side surface of a lowermost layer of the first insulating layers in the second portion,
and

a diameter of an inner sidewall of the second insulating layer facing a side surface of the memory layer increasing downwardly.

US Pat. No. 9,865,618

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

Toshiba Memory Corporatio...

1. A semiconductor device comprising:
first memory cells provided in a first stacked body including first electrode layers alternately stacked with a plurality
of insulating layers therebetween, the first memory cells having the first electrode layers as control gates and a first semiconductor
portion as channels extending inside the first stacked body;

second memory cells provided in a second stacked body including second electrode layers alternately stacked with a plurality
of insulating layers therebetween, the second memory cells having the second electrode layers as control gates and a second
semiconductor portion as channels extending inside the second stacked body; and

an interlayer cell having a conductive layer and a third semiconductor portion, the second stacked body being stacked above
the first stacked body via the conductive layer, the third semiconductor portion being provided between the first semiconductor
portion and the second semiconductor portion, a central axis of the first semiconductor portion and a central axis of the
second semiconductor portion being shifted in a direction perpendicular to a stacking direction of the first and second stacked
bodies, and the interlayer cell and the first and second memory cells being connected in series via the first to third semiconductor
portions, wherein

the interlayer cell is not used for storing data.

US Pat. No. 9,779,809

RESISTIVE SEMICONDUCTOR MEMORY DEVICE AND OPERATION METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a memory cell array including,
a plurality of first lines disposed above a substrate,
a plurality of second lines disposed intersecting the first lines, and
variable resistance elements disposed at each of intersections of the first lines and the second lines; and
a control circuit configured to apply a first voltage to a selected first line, apply a second voltage having a voltage value
which is smaller than that of the first voltage to a selected second line, and apply a third voltage and a fourth voltage
to a non-selected first line and a non-selected second line in a setting operation, respectively, such that a first potential
difference is applied to a selected variable resistance element disposed at the intersection of the selected first line and
the selected second line,

the control circuit including a detection circuit configured to, during the setting operation, detect a transition of a resistance
state of the selected variable resistance element using a reference voltage, and

the control circuit being configured to, before the setting operation, execute a read operation in which the control circuit
applies the third voltage to the selected first line and the non-selected first line, and applies the second voltage to the
selected second line, and set the reference voltage based on a voltage value of the selected second line during the read operation.

US Pat. No. 9,747,966

SEMICONDUCTOR MEMORY DEVICE FOR SENSING MEMORY CELL WITH VARIABLE RESISTANCE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a memory cell which includes a variable resistance element;
a reference signal generation circuit configured to generate a reference signal;
a sense amplifier including a first input terminal and a second input terminal;
a first transistor configured to electrically couple the memory cell and the first input terminal of the sense amplifier;
a second transistor configured to electrically couple the reference signal generation circuit and the second input terminal
of the sense amplifier;

a first control circuit configured to supply a voltage to gates of the first transistor and the second transistor;
a second control circuit configured to supply a first voltage except 0V to a back gate of the first transistor;
a third control circuit configured to supply a second voltage except 0V to a back gate of the second transistor; and
a functional circuit including a third transistor,
wherein threshold voltages of the first transistor and the second transistor are greater than a threshold voltage of the third
transistor.

US Pat. No. 9,741,564

METHOD OF FORMING MARK PATTERN, RECORDING MEDIUM AND METHOD OF GENERATING MARK DATA

TOSHIBA MEMORY CORPORATIO...

1. A method of forming a mark pattern comprising:
coating a film to be processed on a substrate with a photosensitive film;
irradiating the photosensitive film with exposure light via a mask, the mask including a first mask pattern region and a second
mask pattern region, the first mask pattern region being a region in which a first circuit pattern is arranged, the first
circuit pattern having a first transmittance, the second mask pattern region being a region in which the mark pattern to be
used to measure a superposition between films is arranged, the mark having a second transmittance;

developing the photosensitive film so that the first circuit pattern and the mark pattern are transferred to the photosensitive
film, the transferred first circuit pattern having a first film thickness, the transferred mark pattern having a second film
thickness, the second film thickness being thinner than the first film thickness.

US Pat. No. 9,773,769

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a substrate;
a semiconductor package including a semiconductor chip; and
a first connector between the substrate and the semiconductor package, the first connector having opposing first and second
planar surfaces, the first planar surface in contact with the substrate and the second planar surface in contact with the
semiconductor package,

the first connector also including a plurality of wires extending between the first and second planar surfaces to electrically
connect electrodes of the substrate to electrodes of the semiconductor package, wherein the first connector has concavities
along the first and second planar surfaces, the concavities along the first planar surface causing the substrate and the first
connector to be adhered to each other by suction force and the concavities along the second planar surface causing the semiconductor
package and the connector to be adhered to each other by suction force.

US Pat. No. 9,773,527

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
stacked M semiconductor chips, M being an integer of 2 or more;
electrodes that are provided in the semiconductor chips to electrically connect the semiconductor chips in a direction of
stacking; and

transmission units that are provided for the semiconductor chips and, based on a chip identification information of a semiconductor
chip in a present stage, transmit the chip identification information to a semiconductor chip in a next stage through the
electrodes, or transmit a data for setting the chip identification information, wherein

a direction in which an external signal is sent through the electrodes is opposite to a direction in which the chip identification
information is transmitted through the electrodes,

the external signal is outputted to the semiconductor chips, and
the chip identification information is outputted from the semiconductor chips,
wherein, at a corresponding transmission unit, the semiconductor chip in the present stage counts up its chip identification
information upon detection of power-on and then transmits it to the semiconductor chip in the next stage,

wherein a number of electrodes equal to or more than a number of bits by which the semiconductor chips can be identified are
provided for each of the semiconductor chips,

wherein the corresponding transmission unit inverts bit information corresponding to an electrode in N-th stage according
to transmission of bit information for 2N-1 layers between the semiconductor chips, N being an integer of 2 or more,

wherein the corresponding transmission unit includes a decode unit that, based on first bit information sent from a semiconductor
chip in a previous stage to an electrode in the previous stage of the semiconductor chip in the present stage and second bit
information sent from the semiconductor chip in the previous stage to an electrode in the present stage of the semiconductor
chip in the present stage, generates third bit information to be sent to the electrode in the present stage of the semiconductor
chip in the next stage,

wherein the decode unit includes
an EXOR circuit that generates the third bit information based on an exclusive OR of the first bit information and the second
bit information, and

a drive circuit that sets the second bit information to a reset state upon detection of power-off,
wherein the drive circuit cancels the reset state upon detection of power-on and transmits the second bit information, and
wherein drive circuit includes
a NAND circuit that generates the second bit information based on a negative AND of the third bit information and a power-on
detection signal, and

a MOS transistor that, when an output from the NAND circuit is applied to a gate, pulls down an input potential of the NAND
circuit into which the third bit information is input.

US Pat. No. 9,780,104

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a semiconductor substrate;
a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction
on the semiconductor substrate, the plurality of conductive layers having a first stepped structure;

a peripheral region including a transistor on the semiconductor substrate;
a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and
a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor,
wherein a first layer of the plurality of first layers includes a different material than a second layer of the plurality
of second layers, and

the second layer includes a first portion disposed between the plurality of first contacts and a second portion that includes
a different material from that of the first portion and is disposed in a portion other than between the plurality of first
contacts.

US Pat. No. 9,780,116

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor device, the method comprising:
forming a stacked body, the stacked body including a first insulating film, a first silicon containing film provided on the
first insulating film, a filing film provided on the first silicon containing film, and a second silicon containing film provided
on the filing film, the first silicon containing film containing silicon and nitride, the filing film containing silicon and
nitride, a silicon concentration in the filing film being lower than a silicon concentration in the first silicon containing
film, the second silicon containing film containing silicon and nitride, a silicon concentration in the second silicon containing
film being higher than the silicon concentration of the filing film;

forming a memory hole penetrating the stacked body in a stacking direction of the first insulating film, the first silicon
containing film, the filing film, and the second silicon containing film;

forming a charge storage film on a surface of the memory hole;
forming a second insulating film on a surface of the charge storage film;
forming a semiconductor pillar on a surface of the second insulating film;
forming a slit in the stacked body, the slit extending along a plane including the stacking direction;
removing the filing film through the slit;
forming a third insulating film on the first insulating film, the first silicon containing film, the second silicon containing
film and the charge storage film through the slit;

depositing a conductive material on the third insulating film and in a space through the slit to form an electrode film, the
space being formed after the filing film being removed; and

removing a portion of the electrode film adjacent to the slit to divide the electrode film along the stacking direction.

US Pat. No. 9,773,838

MAGNETORESISTIVE MEMORY DEVICE AND MANUFACTURING METHOD OF THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A magnetoresistive memory device, comprising:
active areas arranged and spaced apart at first intervals, on a semiconductor substrate, each of the active areas being provided
along an X direction;

resistance change elements arrayed in a matrix, in an X direction and a Y direction perpendicular to the X direction, above
the substrate; and

selective transistors provided to correspond to the resistance change elements, in the active areas,
wherein:
gate electrodes of the selective transistors are spaced apart at second intervals in the X direction and arranged along the
Y direction,

each of the active areas is provided to cross one of the gate electrodes, and each of the active areas includes a source region,
a drain region, and a channel region of one of the selective transistors,

in two of the active areas adjacent to each other and crossing different gate electrodes, a part of side surfaces of one of
the active areas is connected to a part of side surfaces of the other of the active areas to share the source region of one
of the selective transistors.

US Pat. No. 9,773,845

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a cell array unit; and
a connection unit that is provided adjacently to the cell array unit and is electrically connected to a peripheral circuit
unit disposed below the cell array unit,

the cell array unit including:
a plurality of word lines that extend in a first direction and are respectively disposed with a certain spacing in a second
direction and a third direction, the second direction intersecting the first direction, and the third direction being a stacking
direction that intersects the first direction and the second direction;

a plurality of bit lines that extend in the third direction and are respectively disposed with a certain spacing in the first
direction and the second direction;

a variable resistance layer that is provided on a side surface of the bit line, the side surface facing the word line, and
functions as a storage element at an intersection of the bit line and the word line;

a plurality of select gate lines that are provided in a layer upward of the plurality of word lines and that function as a
control gate for selecting the bit line; and

a plurality of global bit lines that are provided in a layer upward of the plurality of select gate lines and that are electrically
connected to the plurality of bit lines via the control gate, and

the connection unit including:
a lower wiring line layer that includes a plurality of connection lines that are electrically connected to the plurality of
word lines, the plurality of connection lines being provided at a same height as the plurality of the word lines;

a middle wiring line layer that is provided on the lower wiring line layer and in which the plurality of select gate lines
extending from the cell array unit are formed;

an upper wiring line layer that is provided on the middle wiring line layer and in which the same wiring line layer as the
plurality of global bit lines is formed; and

a first penetrating electrode that connects the lower wiring layer and the peripheral circuit unit.

US Pat. No. 9,767,913

MEMORY SYSTEM PERFORMING READ OF NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:
a nonvolatile semiconductor memory device including a memory cell array having a first block including a memory cell; and
a control unit configured to set a voltage supplied to the memory cell array in a read,
wherein
the control unit is configured to set a first voltage supplied to the memory cell of the first block in a first read in a
first operation, and

the control unit is configured to set a second voltage supplied to the memory cell of the first block in a second read after
a lapse of a first standing time from the first operation, the second voltage different from the first voltage.

US Pat. No. 9,768,189

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a semiconductor layer;
a first semiconductor pillar above the semiconductor layer;
a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor
layer and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar;
and

conductive layers and second insulating layers stacked one by one above the semiconductor layer and covering the second section
of the first insulating layer.

US Pat. No. 9,812,398

SEMICONDUCTOR MEMORY DEVICE HAVING MEMORY CELLS PROVIDED IN A HEIGHT DIRECTION

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a memory string comprising a plurality of memory cells connected in series therein;
a first wiring electrically connected to one end of the memory string; and
a contact electrically connected between the memory string and the first wiring,
the memory string comprising:
a plurality of control gate electrodes as first conductive layers stacked above a substrate; and
a semiconductor layer having one end electrically connected to the contact and having as its longer direction a direction
perpendicular to the substrate, the semiconductor layer facing the plurality of control gate electrodes, and

the contact comprising a contact layer, the contact layer having a plate-like shape whose longer direction is a first direction
parallel to the substrate, and the contact layer having its lower surface electrically connected to the one end of the semiconductor
layer, and

the contact layer comprising:
a metal layer that includes tungsten;
a silicon based layer that includes a material including silicon; and
a second conductive layer that covers side surfaces of the metal layer and the silicon based layer.

US Pat. No. 9,779,797

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A non-volatile memory device, comprising:
a first conductive layer;
a second conductive layer including metal nitride, the metal nitride absorbing oxygen;
a paraelectric layer disposed between the first conductive layer and the second conductive layer;
a ferroelectric layer disposed between the paraelectric layer and the second conductive layer, the ferroelectric layer including
hafnium oxide;

at least one third conductive layer disposed on opposite side of at least one of the first conductive layer and the second
conductive layer to the ferroelectric layer, the at least one third conductive layer including metal oxide, the metal oxide
having oxygen ratio larger than stoichiometric ratio; and

a sense circuit configured to read data based on tunneling current flow between the first conductive layer and the second
conductive layer through the paraelectric layer and the ferroelectric layer.

US Pat. No. 9,779,812

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a first electrode;
a second electrode;
a memory cell provided between the first electrode and the second electrode, the memory cell including a metal containing
film and a resistance change film; and

a control circuit that applies a voltage between the first electrode and the second electrode to perform transition of a resistive
state of the memory cell, wherein

the control circuit performs a first reset operation, a verify operation and a second reset operation,
the first reset operation is performed by applying a first pulse having a voltage of a first polarity to the memory cell,
and applying a second pulse having a voltage of a second polarity that is an inverse of the first polarity to the memory cell
after applying the first pulse,

the verify operation confirms whether the memory cell is in a desired state, performed by applying the memory cell with a
verify pulse having the first polarity,

the second reset operation is performed by applying a sixth pulse having a larger voltage than a voltage of the second pulse
and a second polarity, and

the control circuit performs the verify operation every time the first reset operation terminates and performs the second
reset operation when the memory cell is out of a desired state after performing the verify operation.

US Pat. No. 9,805,808

SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a memory cell array,
the memory cell array including a plurality of memory strings,
the plurality of memory strings including a plurality of memory cells connected in series,
each of the plurality of memory cells storing information according to a threshold voltage;
a plurality of word lines,
each word line being connected to a gate electrode of the plurality of memory cells,
the plurality of memory cells connected to one of the word lines being included in a unit of a page;
a plurality of bit lines,
each bit line being connected to one end of the plurality of memory strings;
a source line being connected to one other end of the plurality of memory strings; and
a circuit controlling a read operation of the information, applying a pre-charge voltage to the plurality of bit lines in
the read operation and changing the pre-charge voltage according to at least one of a number of used pages, or a position
of the page.

US Pat. No. 9,773,539

LOGICAL OPERATION CIRCUIT AND MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A logical operation circuit comprising:
a magnetic tunnel junction (MTJ) element comprising a first magnetic layer, a second magnetic layer, and an intermediate layer
between the first and second magnetic layers, wherein the MTJ element transitions to a first state from a second state by
a first voltage being applied to the MTJ element, and the MTJ element transitions to the second state from the first state
by the first voltage being applied to the MTJ element; and

a driver which is coupled to the first magnetic layer without a magnetic layer interposed and coupled to the second magnetic
layer, and outputs the first voltage.

US Pat. No. 10,104,806

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:a substrate that comprises a plurality of wirings, a first end portion, and a second end portion;
a terminal portion that is connected to the substrate at the first end portion and comprises a terminal connected to the wirings;
a connector to connect to a host device, the connector comprises a holder that surrounds the terminal portion;
a first semiconductor memory that is disposed on a first principal surface of the substrate, is disposed between the first end portion and the second end portion, and is connected to the wirings;
a controller that is disposed on the first principal surface of the substrate, is disposed between the first end portion and the first semiconductor memory, and is connected to the wirings and controls the first semiconductor memory;
a case that houses part of the holder, the substrate, the first semiconductor memory and the controller; and
a first plate-shaped member that is disposed between the first principal surface and a first wall portion of the case facing the first principal surface separated from the first semiconductor memory, the controller, and the case, is connected to the holder at a first end of the first plate-shaped member, is connected to the second end portion at a second end of the first plate-shaped member, and comprises thermal conductivity, wherein
the first plate-shaped member comprises electrical conductivity and is connected to a ground wiring of the wirings on the first principal surface on the second end portion side,
the first plate-shaped member is larger than the ground wiring in a direction vertical to a direction from the first end portion to the second end portion,
the direction from the first end portion to the second end portion is along a direction from the first end of the first plate-shaped member to the second end of the first plate-shaped member, and
the first end of the first plate-shaped member and the second end of the first plate-shaped member do not overlap the first semiconductor memory and the controller in a direction vertical to the first principal surface of the substrate.

US Pat. No. 9,748,090

SEMICONDUCTOR MANUFACTURING APPARATUS AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:
a first cleaner cleaning a top face of a semiconductor substrate or of a polishing target material while the semiconductor
substrate is rotated, after polishing the semiconductor substrate or the polishing target material on the semiconductor substrate
with an abrasive; and

a second cleaner rubbing an end portion of the semiconductor substrate with a physical contact according to rotation of the
semiconductor substrate, wherein

the second cleaner comprises a first portion configured to be in contact with the semiconductor substrate and a third portion
facing the first portion,

the first portion comprises a foamed resin, and
the first portion and the third portion rub an end portion of the semiconductor substrate in a state of sandwiching the end
portion therebetween.

US Pat. No. 9,830,079

MEMORY SYSTEM FOR CONTROLLING NONVOLATILE MEMORY

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:
a nonvolatile memory including a plurality of physical blocks; and
a controller electrically connected to the nonvolatile memory and configured to manage a plurality of namespaces, the plurality
of namespaces including at least a first namespace for storing a first type of data, and a second namespace for storing a
second type of data having a lower update frequency than the first type of data, wherein

the controller is configured to:
receive a first request for the first namespace and a second request for the second namespace from a host device, the first
request specifying a first number of logical block addresses and a first number of physical blocks, the second request specifying
a second number of logical block addresses and a second number of physical blocks;

allocate the first number of physical blocks for the first namespace;
allocate the second number of physical blocks for the second namespace,
allocate a first over-provision area for the first namespace, wherein a remainder which is obtained when a capacity corresponding
to the first number of logical block addresses is subtracted from a capacity corresponding to the first number of physical
blocks serves as the first over-provision area; and

allocate a second over-provision area for the second namespace, wherein a remainder which is obtained when a capacity corresponding
to the second number of logical block addresses is subtracted from a capacity corresponding to the second number of physical
blocks serves as the second over-provision area.

US Pat. No. 9,768,233

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;
a first conductive body facing the stacked body to extend in a stacking direction;
a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive
body and the first conductive films,

the first conductive body including a projecting part that projects along tops of one of the first insulating films and one
of the first conductive films, and a lower surface of the projecting part contacting an upper surface of the one of the first
conductive films; and

a second insulating film configured from a material different from that of the first insulating film, disposed on the one
of the first conductive films of the stacked body, and disposed in the same layer as the projecting part of the first conductive
body.

US Pat. No. 9,754,793

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor device, comprising:
forming a mask layer on a layer to be etched, the mask layer containing tungsten and boron, a composition ratio of the tungsten
being not less than 30%;

patterning the mask layer; and
performing a dry etching to the layer to be etched using the mask layer being patterned, and forming a hole or a slit in the
layer to be etched.

US Pat. No. 9,859,002

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a first electrode;
a second electrode;
a memory cell provided between the first electrode and the second electrode, the memory cell including a metal film and a
resistance change film; and

a control circuit that applies a voltage between the first electrode and the second electrode to perform transition of a resistive
state of the memory cell, wherein

the control circuit performs a first writing operation by
applying a first pulse having a voltage of a first polarity to the memory cell, and
applying a second pulse having a voltage of the first polarity smaller than the voltage of the first pulse to the memory cell
continuously after applying the first pulse.

US Pat. No. 9,806,092

SEMICONDUCTOR MEMORY DEVICE AND METHODS FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

16. A method for manufacturing a semiconductor memory device, comprising:
forming a stacked film by alternately stacking a first film and a second film on a base semiconductor layer, the stacked film
including a plurality of the first films and a plurality of the second films;

forming a first pillar-shaped structure body and a second pillar-shaped structure body, the first pillar-shaped structure
body including a first semiconductor body and a first memory layer, the first semiconductor body extending through the stacked
film along a stacking direction of the stacked film, the first memory layer being provided between the first semiconductor
body and the stacked film, the second pillar-shaped structure body including a second semiconductor body and a second memory
layer, the second semiconductor body extending through the stacked film along the stacking direction, the second memory layer
being provided between the second semiconductor body and the stacked film;

forming a hole in the stacked film;
causing a third portion of the plurality of first films to remain while removing a first portion and a second portion of the
plurality of first films via the hole, the third portion being positioned between the first pillar-shaped structure body and
the second pillar-shaped structure body, the first portion being positioned between the third portion and the first pillar-shaped
structure body, the second portion being positioned between the third portion and the second pillar-shaped structure body;

forming a plurality of conductive layers from a conductive material by introducing the conductive material to at least a portion
of a space formed by the removing of the first portion and the second portion; and

forming an interconnect electrically connected to the first semiconductor body and the second semiconductor body.

US Pat. No. 9,761,463

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
an insulation layer provided on a surface of a substrate;
an electrode buried in the insulation layer and having a first end surface exposed from the insulation layer;
a groove formed on the surface of the substrate around the electrode;
a different substrate stuck to the substrate via the insulation layer;
an insulation layer provided on a sticking surface of the different substrate; and
a corresponding electrode buried in the insulation layer of the different substrate in a position corresponding to the electrode
and having a first end surface exposed from a surface of the insulation layer of the different substrate, wherein

the electrode and the corresponding electrode are connected in a state in which the electrode and the corresponding electrode
are deviated in a surface direction of the joining surface, and

there is an air gap between an unconnected portion of the electrode surface and a surface of the insulation layer in which
the corresponding electrode is provided and between an unconnected portion of the corresponding electrode surface and a surface
of the insulation layer in which the electrode is provided.

US Pat. No. 9,865,323

MEMORY DEVICE INCLUDING VOLATILE MEMORY, NONVOLATILE MEMORY AND CONTROLLER

TOSHIBA MEMORY CORPORATIO...

1. A memory device connectable to a host, the memory device comprising:
a nonvolatile memory;
a volatile memory which is used as a cache of the nonvolatile memory and has a higher access speed than the nonvolatile memory;
and

a controller which controls access to the nonvolatile memory and the volatile memory, wherein
the controller increments, when the controller receives a refresh command for the volatile memory from the host, a value of
a refresh counter, and executes, when the value of the refresh counter exceeds a threshold, no refresh operation corresponding
to the refresh command.

US Pat. No. 9,865,338

MEMORY SYSTEM AND METHOD OF CONTROLLING NONVOLATILE MEMORY BY CONVERTING WRITE DATA WRITTEN TO A PAGE

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:
a nonvolatile memory including a plurality of memory cells and a word line connected to the plurality of memory cells, each
of the plurality of memory cells being configured to store m-bit data in correspondence with one of first to n-th threshold
areas, the first to n-th threshold areas being defined in order of lowest to highest threshold voltage, m being a natural
number of two or more, n being a natural number of m-th power of two, the data being written in units of pages, the data of
m pages being configured to be written into the plurality of memory cells connected to the word line, a value corresponding
to each of the plurality of memory cells among data of each of first to m-th pages being x or y, x being a value of one of
“1” and “0”, and y being a value of one of “1” and “0” and being different from x; and

a controller configured to:
associate data stored in a certain memory cell of the plurality of memory cells with the first threshold area in a case where
all of a first to m-th values are x, the first to m-th values corresponding to the certain memory cell among each of the data
of first to m-th pages, the first to m-th values respectively corresponding to the first to m-th pages, and associate the
data stored in the certain memory cell with the second threshold area in a case where the first value is y, and the second
to m-th values are x;

execute a first data conversion on first data and write the converted first data into the first page, the first data being
target data to be written into the first page, the first data conversion including increasing a ratio of y for a plurality
of values included in the first data and respectively corresponding to the plurality of memory cells; and

execute a second data conversion on second data and write the converted second data into the second page, the second data
being target data to be written into the second page, the second data conversion including increasing a ratio of x for a plurality
of values included in the second data and respectively corresponding to the plurality of memory cells.

US Pat. No. 9,857,991

MEMORY CARD AND HOST DEVICE THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A storage device couplable to a host, comprising:
a command line;
a plurality of data lines;
a clock line;
a nonvolatile memory; and
a controller coupled to the command line, the data lines and the clock line, wherein:
the controller is configured to receive a clock signal through the clock line;
the controller is configured to receive first data and output a first response through at least one of the data lines, in
accordance with a single edge transfer based on either one of a rise edge and a fall edge of the clock signal, in a first
transfer mode of the storage device;

the controller is configured to receive second data and output a second response through at least one of the data lines, in
accordance with a double edge transfer based on both the rise edge and the fall edge of the clock signal, in a second transfer
mode of the storage device;

the controller is configured to receive a first command and output a third response through the command line, in accordance
with the single edge transfer, in the first transfer mode of the storage device;

the controller is configured to receive a second command and output a fourth response through the command line, in accordance
with the single edge transfer, in the second transfer mode of the storage device;

the controller is configured to switch a transfer mode of the storage device from the first transfer mode to the second transfer
mode in response to the first command; and

a transfer rate of the double edge transfer is higher than a transfer rate of the single edge transfer.

US Pat. No. 9,853,040

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a semiconductor substrate;
a plurality of first insulating layers and first conductive layers stacked alternately in a first direction above the semiconductor
substrate;

a first semiconductor layer extending in the first direction; and
a memory layer disposed between one of the first insulating layers and the first semiconductor layer and between one of the
first conductive layers and the first semiconductor layer, the memory layer including a charge accumulation layer and a second
insulating layer, the second insulating layer being between the charge accumulation layer and the first semiconductor layer,

the first semiconductor layer and the memory layer having a gap in which the first semiconductor layer and the second insulating
layer are exposed, between one of the first insulating layers and the first semiconductor layer, and

the first semiconductor layer and the memory layer being contacted each other, between one of the first conductive layers
and the first semiconductor layer.

US Pat. No. 9,857,866

CARD AND HOST APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A host apparatus into which a card including a nonvolatile semiconductor memory is inserted, the host apparatus configured
to:
transmit a first command to the card, the first command instructing the card to send back a response of status data that is
used to determine whether the card supports a termination process in which the card shifts into a state ready for a stop of
power supply from the host apparatus;

issue a function stop command which instructs the card to carry out the termination process and receive a first signal subsequent
to the issuance of the function stop command, the first signal being indicative of a busy state and having a first level;
and

stop supplying power to the card in response to the host apparatus having learned of completion of the busy state by receiving
a first signal being indicative of a ready state and having a second level.

US Pat. No. 9,852,786

SEMICONDUCTOR MEMORY DEVICE THAT VARIES VOLTAGE LEVELS DEPENDING ON WHICH OF DIFFERENT MEMORY REGIONS THEREOF IS ACCESSED

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a semiconductor memory chip including a plurality of regions of memory cells, including a first memory region and a second
memory region; and

a memory controller configured to
set a first voltage based on a first number of times the first memory region has been accessed since a predetermined point
of time and carry out an operation on memory cells of the first memory region by applying the first voltage, when the first
number is more than a threshold number, and

set a second voltage that is different from the first voltage based on a period of time that has passed since a last access
to the second memory region and carry out the operation on memory cells of the second memory region by applying the second
voltage, when a second number of times the second memory region has been accessed since the predetermined point of time is
less than the threshold number.

US Pat. No. 9,847,301

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a semiconductor substrate including an element region having a semiconductor element;
a guard ring provided on an outer periphery of the element region and including a first interconnect and a first plug which
electrically couples the first interconnect and a first well region, a ground voltage being applied to the guard ring;

a second interconnect provided above the first interconnect via a first insulating layer and non-electrically coupling to
the first interconnect; and

a first circuit coupled to the second interconnect,
wherein the first circuit detects one of a crack and a peeling of the guard ring in accordance with a break in the second
interconnect or a short circuit between the second interconnect and the first interconnect.

US Pat. No. 9,847,342

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a first structural body and a second structural body separated in a first direction and extending in a second direction intersecting
with the first direction; and

a plurality of interconnections, provided between the first structural body and the second structural body, extending in the
second direction, and separated from each other along a third direction intersecting with a plane including the first direction
and the second direction,

the first structural body and the second structural body each including:
an insulating member and a column-shaped body disposed in an alternating manner along the second direction and extending in
the third direction; and

an insulating film provided between the column-shaped body and the plurality of interconnections,
the column-shaped body including:
a first semiconductor member and a second semiconductor member separated from each other along the first direction and extending
in the third direction; and

an electrode provided between the first semiconductor member and each of the plurality of interconnections, and
the insulating member of the first structural body and the insulating member of the second structural body making contact
with the plurality of interconnections.

US Pat. No. 9,837,279

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING APPARATUS

Toshiba Memory Corporatio...

1. A manufacturing method of a semiconductor device, the method comprising:
bringing a first catalyst into contact with a workpiece to form an oxide film on a surface of the workpiece; and
bringing a second catalyst different from the first catalyst and the oxide film into contact with each other or moving the
second catalyst and the oxide film closer to each other to elute the oxide film into a treatment liquid,

wherein the first catalyst is a solid catalyst.

US Pat. No. 9,824,738

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:
a first memory area;
a first selection circuit which selects a bit line of the first memory area, the bit line of the first memory area extending
in a first direction;

a second memory area;
a second selection circuit which selects a bit line of the second memory area, the bit line of the second memory area extending
in the first direction; and

a third selection circuit arranged between the first selection circuit and the second selection circuit, and configured to
select the first selection circuit or the second selection circuit,

wherein:
the first memory area, the first selection circuit, the third selection circuit, the second selection circuit, and the second
memory area are aligned in this order in the first direction,

the first selection circuit includes at least a first transistor group and a second transistor group, wherein the first transistor
group and the second transistor group are configured to select the bit line of the first memory area,

the second selection circuit includes at least a third transistor group and a fourth transistor group, wherein the third transistor
group and the fourth transistor group are configured to select the bit line of the second memory area, and

the third selection circuit selects the first transistor group and the third transistor group, or the second transistor group
and fourth transistor group.

US Pat. No. 9,768,188

SEMICONDUCTOR MEMORY

TOSHIBA MEMORY CORPORATIO...

1. A memory comprising:
a plurality of memory cells including a first memory cell above a semiconductor substrate and a second memory cell above the
first memory cell;

a first interconnection including a first part and a second part and surrounding the plurality of memory cells such that the
plurality of memory cells are between the first part and the second part; and

a second interconnection above the plurality of memory cells, the first part, and the second part, and electrically connected
to at least one of the first memory cell and the second memory cell.

US Pat. No. 9,768,191

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a stacked body provided on a major surface of a substrate, the stacked body including a plurality of electrode layers stacked
from the major surface of the substrate with an insulator interposed;

a columnar portion provided in the stacked body, the columnar portion extending along a stacking direction of the stacked
body, the columnar portion including a semiconductor body and a charge storage film, the charge storage film provided between
the semiconductor body and the electrode layers;

a plate portion provided in the stacked body, the plate portion extending along the stacking direction of the stacked body
and a first direction crossing the stacking direction, the plate portion including a conductor and a sidewall insulating film,
the sidewall insulating film provided between the conductor and the insulator and between the conductor and the electrode
layers, the sidewall insulating film contacting the major surface of the substrate, the conductor contacting the major surface
of the substrate; and

a blocking insulating film provided in the stacked body, the blocking insulating film provided between the sidewall insulating
film and the insulator, between the insulator and the electrode layers, and between the charge storage film and the electrode
layers, the blocking insulating film including a first blocking insulating layer and a second blocking insulating layer, the
second blocking insulating layer being different from the first blocking insulating layer.

US Pat. No. 9,768,117

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a substrate including a first portion and a second portion, the first portion having a columnar configuration, the second
portion having an upper surface continuous with a side surface of the first portion via a corner;

a stacked body provided above the substrate, the stacked body including a plurality of electrode layers stacked with an insulator
interposed, the electrode layers including a lowermost electrode layer opposing the side surface of the first portion above
the second portion of the substrate;

an insulating film provided between the side surface of the first portion of the substrate and a side surface of the lowermost
electrode layer, and between the upper surface of the second portion of the substrate and a lower surface of the lowermost
electrode layer;

a semiconductor body extending in a stacking direction through the stacked body and contacting the first portion of the substrate;
and

a charge storage portion provided between the semiconductor body and the electrode layers upper than the lowermost electrode
layer,

an angle formed between the upper surface of the second portion of the substrate and the corner of the substrate on the insulating
film side being greater than 90°.

US Pat. No. 9,767,863

REDUNDANCY MEMORY DEVICE COMPRISING A PLURALITY OF SELECTING CIRCUITS

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:
a first storage area configured to store data;
a first sense amplifier;
a first data latch;
a first selector configured to selectively switch between a first connection and a second connection, the first connection
being between the first data latch and the first sense amplifier, and the second connection being between the first data latch
and another sense amplifier; and

a second selector configured to selectively switch between a third connection and a fourth connection, the third connection
being between the first storage area and the first sense amplifier, and the fourth connection being between another storage
area and the first sense amplifier.

US Pat. No. 9,859,012

BOOSTER CIRCUIT

Toshiba Memory Corporatio...

1. A booster circuit comprising:
a charge pump circuit including a plurality of transistors connected in series in each of which a gate and a channel electrode
are connected, and a plurality of capacitors each of which is connected to the channel electrode of a corresponding one of
the transistors; and

a clock processing circuit including
a first transistor of a first conductivity type and a second transistor of a second conductivity type that are connected in
series between a high-voltage node and a low-voltage node, gates of the first and second transistors being connected to each
other, and

a third transistor of the second conductivity type connected in parallel with the first transistor between the high-voltage
node and a first output terminal of the clock processing circuit that is connected to a node between the first transistor
and the second transistor and to at least one of the capacitors of the charge pump circuit.

US Pat. No. 9,853,052

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a substrate:
a first stacked portion provided above the substrate, the first stacked portion including a plurality of electrode layers
stacked with an insulator interposed,

a semiconductor body extending through the first stacked portion in a stacking direction of the first stacked portion;
a charge storage portion provided between the semiconductor body and one of the electrode layers;
a circuit portion including a transistor provided at a region separated from the first stacked portion in the substrate;
a second stacked portion provided above the circuit portion, the second stacked portion including a plurality of first layers
and a plurality of second layers, the first layers and the second layers including a first layer and a second layer stacked
alternately; and

an insulating layer provided above the circuit portion and provided above the substrate between the first stacked portion
and the second stacked portion;

a height of an uppermost first layer of the second stacked portion from a surface of the substrate being substantially equal
to a height of an uppermost electrode layer of the first stacked portion from the surface of the substrate, or being higher
than the height of the uppermost electrode layer;

wherein a height of a lowermost electrode layer of the first stacked portion from the surface of the substrate is lower than
a height of a lowermost first layer of the second stacked portion from the surface of the substrate.

US Pat. No. 9,846,541

MEMORY SYSTEM FOR CONTROLLING PERFORAMCE BY ADJUSTING AMOUNT OF PARALLEL OPERATIONS

Toshiba Memory Corporatio...

1. A memory system comprising:
a non-volatile memory; and
a controller configured to control the non-volatile memory,
wherein the controller includes:
an interface configured to receive from a host, a first instruction as a performance control instruction, the first instruction
including information and being an instruction that changes a performance of the memory system;

a control unit configured to control the memory system on the basis of the performance control instruction received from the
host such that a number of parallel operations of parallel operating units that are able to operate in parallel in the memory
system is changed; and

a table module configured to store corresponding information in which a control method corresponding to the performance control
instruction is set, the corresponding information being set for the memory system,

wherein the control unit selects the control method corresponding to the received performance control instruction on the basis
of the received performance control instruction and the corresponding information stored in the table module, and changes
the number of parallel operations of the parallel operating units according to the selected control method.

US Pat. No. 9,823,691

SEMICONDUCTOR STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor storage device comprising:
a first substrate comprising a first face and a second face on the side opposite to the first face;
a casing housing the first substrate;
a first non-volatile memory mounted on the first face;
a controller mounted on the first face or the second face, the controller configured to control the first non-volatile memory;
and

a first member mounted on the first face or the second face, the first member including an elastically deformable part and
at least a portion of the first member being positioned between the first non-volatile memory and the controller,

wherein the first member is configured to be brought into contact with the casing by an elastic deformation of the elastically
deformable part to thermally connect the first substrate and the casing.

US Pat. No. 9,825,096

RESISTANCE CHANGE MEMORY, METHOD OF MANUFACTURING RESISTANCE CHANGE MEMORY, AND FET

TOSHIBA MEMORY CORPORATIO...

1. A resistance change memory comprising:
a substrate having a surface
a first conductive line provided above the surface of the substrate;
a second conductive line provided above the first conductive line, and extending in a first direction along the surface of
the substrate;

a third conductive line provided above the surface of the substrate and extending in a second direction, the second direction
intersecting the first direction and the surface of the substrate;

a select transistor provided between the first and third conductive lines; and
a resistance change layer provided between the second and third conductive lines,
wherein the select transistor includes:
a first conductive layer provided on the first conductive line;
a first semiconductor layer as a channel including crystal grains, the first semiconductor layer being provided on the first
conductive layer;

a second conductive layer provided on the first semiconductor layer, and connected to the third conductive line; and
a fourth conductive line as a gate extending in the first direction, the fourth conductive line facing to the first semiconductor
layer,

wherein the first conductive layer and the first semiconductor layer include a predetermined impurity with a first impurity
concentration and the second conductive layer includes no predetermined impurity or the predetermined impurity with a second
impurity concentration less than the first impurity concentration, and

wherein the crystal grains in the first semiconductor layer include first crystal grains and second crystal grains in a first
plane extending in a direction along the surface of the substrate, a crystal orientation of the first crystal grains in the
first plane is {001}-plane, a crystal orientation of the second crystal grains in the first plane is {101}-plane, and a number
of the first crystal grains is larger than a number of the second crystal grains.

US Pat. No. 9,812,207

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a first string comprising a first transistor coupled to a bit line, a second transistor coupled to a source line, and first
cell transistors serially-coupled between the first transistor and the second transistor;

a second string comprising a third transistor coupled to the bit line, a fourth transistor coupled to the source line, and
second cell transistors serially-coupled between the third transistor and the fourth transistor, a gate of the first transistor
being separate from a gate of the third transistor, a gate of the second transistor being coupled to a gate of the fourth
transistor; and

a control circuit configured to apply a first voltage to the source line, a second voltage to the bit line, a third voltage
to the gate of the second transistor, a fourth voltage to a gate of a first one of the first cell transistors, and a fifth
voltage to a gate of a second one of the first cell transistors during a read, the first voltage being higher than the second
voltage, the first voltage being substantially the same as the third voltage, and the fifth voltage being higher than the
fourth voltage.

US Pat. No. 9,804,503

RESIST PLACING METHOD AND RESIST PLACING PROGRAM

Toshiba Memory Corporatio...

1. A resist placing method comprising:
setting, based on information about a grid, first and second grating vectors of a drop grating so that the first and second
grating vectors have directions different from both first and second minimum grating vectors of the grid, the grid being a
minimum grating unit for which a resist drop is dropped onto a substrate, the drop grating being a grating onto which the
resist drop is placed;

placing the drop grating in accordance with a predetermined rule; and
placing a plurality of resist drops using the drop grating formed by the set first and second grating vectors,
wherein the first grating vector is the same in component in a first direction as, and different in component in a second
direction perpendicular to the first direction from, the first minimum grating vector,

wherein the second grating vector is the same in component in the second direction as, and different in component in the first
direction from, the second minimum grating vector, and

wherein a first grating length corresponding to a smaller angle from among a first angle made by the first grating vector
and the first minimum grating vector and a second angle made by the second grating vector and the second minimum grating vector,
is longer than a second grating length corresponding to the larger angle.

US Pat. No. 9,799,546

SEMICONDUCTOR MANUFACTURING APPARATUS AND METHOD OF OPERATING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:
an electrostatic chuck that includes a base and a first electrode provided on the base and is configured to electrostatically
adsorb a wafer on the first electrode;

a measurement module configured to measure potential of the wafer; and
a controller configured to adjust potential of the base based on the potential of the wafer and to adjust potential of the
first electrode based on the potential of the wafer or the base, when the potential of the wafer measured by the measurement
module changes,

wherein
the controller changes the potential of the first electrode from a third value to a fourth value, when the potential of the
wafer measured by the measurement module changes from a first value to a second value, and

the controller changes the potential of the first electrode from the fourth value back to the third value, when the potential
of the wafer measured by the measurement module changes from the second value back to the first value.

US Pat. No. 9,748,240

SEMICONDUCTOR DEVICE INCLUDING A BOUNDARY OF CONDUCTIVITY IN A SUBSTRATE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a semiconductor substrate;
a first semiconductor region of a first conductivity type located in the semiconductor substrate;
a second semiconductor region of a second conductivity type located in the semiconductor substrate and adjacent to the first
semiconductor region at a boundary;

a plurality of first contacts located in the first semiconductor region along the boundary and electrically connected to the
first semiconductor region; and

a plurality of second contacts located in the second semiconductor region along the boundary and electrically connected to
the second semiconductor region, wherein

the second contacts are not located in parts of the second semiconductor region on an opposite side to the first contacts
across the boundary, the parts of the second semiconductor region being adjacent to the first contacts in a first direction
substantially perpendicular to an arranging direction of the first and second contacts, and

the first contacts are not located in parts of the first semiconductor region on an opposite side to the second contacts across
the boundary, the parts of the first semiconductor region being adjacent to second contacts in the first direction.

US Pat. No. 9,773,712

ION IMPLANTATION APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. An ion implantation apparatus comprising:
an implantation part implanting ions into an implantation region located at a bottom of a concave portion formed in a laminated
film provided on a semiconductor substrate;

a measuring part measuring an amount of detected ions corresponding to an aspect ratio of the concave portion based on ions
emitted from the implantation part thereinto, at a first position at which the semiconductor substrate is arranged when the
ions are implanted into the implantation region or a second position close to the first position; and

a controller controlling the implantation part to stop emission of the ions into the measuring part when an accumulated amount
of the amount of detected ions has reached a predetermined amount according to a target accumulation amount of the implantation
region, wherein

the measuring part comprises:
an introduction path introducing ions from the implantation part, an adjusting part adjusting a ratio of a frontage and a
depth of the introduction path to correspond to the aspect ratio, and

a measuring unit measuring an amount of detected ions introduced from the introduction path comprising the adjusted ratio
of the frontage and the depth, to measure the amount of detected ions corresponding to the aspect ratio of the concave portions.

US Pat. No. 9,741,730

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A semiconductor device, comprising:
a control electrode extending a first direction;
a first insulating layer provided on the control electrode, the first insulating layer containing a metal oxide;
a charge storage layer provided on the first insulating layer;
an intermediate insulating layer provided on the charge storage layer;
a floating electrode layer provided on the intermediate insulating layer;
a second insulating layer provided on the floating electrode layer;
a semiconductor layer provided on the second insulating layer;
a first separation film separating the control electrode, the first insulating layer, the charge storage layer, the intermediate
insulating layer, the floating electrode layer, and the second insulating layer in the first direction; and

a second separation film separating a first stacked unit in a second direction, the first stacked unit including the charge
storage layer, the intermediate insulating layer, the floating electrode layer, the second insulating layer, and the semiconductor
layer, the second direction intersecting the first direction, the second separation film containing silicon,

the semiconductor layer containing an n-type impurity and a p-type impurity, and
a concentration of the p-type impurity having a peak on the second insulating layer side of a center position in a thickness
direction of the semiconductor layer.

US Pat. No. 9,768,185

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
an insulating layer;
a conductive layer provided above the insulating layer, the conductive layer having a first film and a second film provided
on an upper part of the first film, the first film including silicon and metal;

a stacked body provided above the conductive layer and including a plurality of electrode layers separately stacked in a first
direction;

a first semiconductor body provided in the stacked body and extending in the first direction, the first semiconductor body
being electrically connected to the conductive layer, the second film being provided between the first semiconductor body
and the first film;

a memory portion provided between the first semiconductor body and one of the plurality of electrode layers; and
a source layer extending in the first direction and in contact with the conductive layer.

US Pat. No. 9,761,415

SEMICONDUCTOR MANUFACTURING APPARATUS AND SEMICONDUCTOR MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:
a housing configured to house a substrate;
a first temperature regulator configured to regulate a temperature of a fluid;
first, second and third flow channels configured to divide the fluid supplied from the first temperature regulator;
a second temperature regulator configured to regulate a temperature of the fluid in the second channel;
a third temperature regulator configured to regulate a temperature of the fluid in the third flow channel;
a fluid supply channel configured to join the fluid in the first flow channel and the fluid in the second flow channel and
to supply the joined fluids to the housing; and

a flow rate regulator configured to regulate a flow rate of the fluid in the first flow channel and a flow rate of the fluid
in the second flow channel;

wherein the fluid in the first flow channel, the fluid in the second flow channel, and the fluid in the third flow channel
flow into the fluid supply channel.

US Pat. No. 9,865,351

MEMORY SYSTEM WITH NON-VOLATILE MEMORY DEVICE THAT IS CAPABLE OF SINGLE OR SIMULATANEOUS MULTIPLE WORD LINE SELECTION

Toshiba Memory Corporatio...

1. A memory system comprising:
a memory device that includes
a memory cell array having a plurality of memory string units including a first memory string unit and a second memory string
unit, each of the memory string units including a plurality of memory strings, each memory string having a first transistor,
a second transistor, and a plurality of memory cells connected between the first transistor and the second transistor, the
plurality of memory cells including a first memory cell and a second memory cell,

a first word line connected to gates of the first memory cells in the first and second memory string units,
a second word line connected to gates of the second memory cells in the first and second memory string units,
a first select gate line connected to the first transistors in the first memory string unit, and
a second select gate line connected to the first transistors in the second memory string unit; and
a controller configured to control an operation of the memory device,
wherein during reading from or writing to the first memory string unit, the memory device selects the first select gate line,
does not select the second select gate line, and while the first select gate line is selected and the second select gate line
is not selected, simultaneously reads from or writes to the first and second memory cells in the memory strings of the first
memory string unit.

US Pat. No. 9,859,103

PROCESS CONTROL DEVICE, RECORDING MEDIUM, AND PROCESS CONTROL METHOD

TOSHIBA MEMORY CORPORATIO...

1. A process control device, comprising:
an emission amount calculation unit configured to select light of a selected wavelength among light generated by a dry etching
process using plasma is being executed on a substrate, calculate an integral value which is obtained by integrating an emission
intensity of the selected light over a period of time during which the selected light is detected, and calculate a total value
of the integral value as a total emission amount at the substrate; and

a process control unit configured to output an instruction to stop the dry etching process when the total emission amount
reaches a predetermined reference value.

US Pat. No. 9,852,987

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a substrate;
a first interconnect which includes a first layer provided on the substrate and formed of a first interconnect material, and
a second layer provided on the first layer, formed of a second interconnect material different from the first interconnect
material, and having a first lower face, and has a first width; and

a second interconnect which includes a third layer provided on the substrate and formed of the first interconnect material,
a fourth layer provided on the third layer, formed of the second interconnect material, and having a second lower face lower
than the first lower face, and has a second width greater than the first width,

wherein
the first layer includes a first metal layer and a second metal layer provided on the first metal layer, the first metal layer
being provided on a lower face of the second metal layer,

the second layer includes a third metal layer and a fourth metal layer provided on the third metal layer, the third metal
layer being provided on a lower face and a side face of the fourth metal layer,

the third layer includes a fifth metal layer and a sixth metal layer provided on the fifth metal layer, the fifth metal layer
being provided on a lower face of the sixth metal layer,

the fourth layer includes a seventh metal layer and an eighth metal layer provided on the seventh metal layer, the seventh
metal layer being provided on a lower face and a side face of the eighth metal layer.

US Pat. No. 9,853,050

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A method for manufacturing a semiconductor memory device, comprising:
forming a stacked body on a substrate by alternately stacking a first insulating layer and a first layer;
forming a first trench in the stacked body, the first trench surrounding a part of the stacked body;
forming a protection film and a first film in the first trench;
removing a first portion of the first film by etching in a first direction opposite to a stacking direction of the stacked
body;

removing a part of the first layer by etching in a second direction crossing the stacking direction, the first layer being
exposed by the removal of the first portion of the first film;

removing a second portion of the first film by etching in the first direction;
further removing a part of the first layer and a part of another first layer by etching in the second direction, the another
first layer being exposed by the removal of the second portion of the first film; and

embedding an insulating film in hollow spaces provided by the removal of the parts of the first layer and the another first
layer,

the first trench having a first portion and a second portion, the first portion extending in a third direction crossing the
second direction with a first width in the second direction, the second portion extending in the second direction with a second
width in the third direction,

the second width being smaller than the first width,
the first width being not less than 3 times a thickness of the protection film, and
the second width being not more than 2 times the thickness of the protection film.

US Pat. No. 9,852,797

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A method of controlling a memory device,
the memory device comprising a plurality of memory strings including first to fourth memory strings, the first memory string
including a plurality of memory cells electrically connected in series between a first selection transistor and a second selection
transistor, the memory cells including a first memory cell and a second memory cell, the first memory string further including
a first transistor provided between the first selection transistor and the first memory cell, a second transistor provided
between the first memory cell and the second memory cell, and a third transistor provided between the second memory cell and
the second selection transistor, a gate of the first selection transistor in the first memory string being coupled to a gate
of a first selection transistor in the second memory string, a gate of a first selection transistor in the third memory string
being coupled to a gate of a first selection transistor in the fourth memory string, gates of memory cells in the first to
third memory strings being coupled to a gate of a memory cell in the fourth memory string,

the method comprising selectively erasing data stored in either a first group including the first and second memory strings
or the second group including the third and fourth memory strings.

US Pat. No. 9,837,264

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device, comprising:
a substrate;
a memory cell disposed within a memory cell region on the substrate, the memory cell accumulating a charge as data; and
a cover layer covering the memory cell, the cover layer having a structure in which a first silicon nitride layer, an intermediate
layer, and a second silicon nitride layer are stacked sequentially from a side of the memory cell, the intermediate layer
being amorphous silicon; wherein

the memory cell comprises: a gate insulating film disposed on the substrate; a floating gate electrode disposed on the gate
insulating film; a block insulating film disposed above the floating gate electrode; and a control gate electrode disposed
on the block insulating film;

a select transistor is disposed in a periphery of the memory cell within a memory cell region;
a peripheral transistor is disposed within a peripheral region, the peripheral region being in a periphery of the memory cell
array region; and a contact is disposed in a periphery of said peripheral transistor;

the cover layer covers an upper portion of the peripheral transistor and has an end of the cover layer contacting the contact;
a spacer configured from an insulator is disposed on the upper portion of the peripheral transistor;
the cover layer is disposed curved toward a substrate surface direction in the portion shifting from the memory cell array
region to the peripheral region, so as to cover upper portions of the memory cell and the select transistor and face part
of a side surface of the select transistor; and

the cover layer is divided by the spacer.

US Pat. No. 9,831,269

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a stacked body including a plurality of electrode layers stacked with an insulator interposed, a hole extending in a stacking
direction of the stacked body through the stacked body and having a central axis along the stacking direction; and

a semiconductor body extending in the stacking direction in the hole, a plurality of memory cells being provided at crossing
portions of the semiconductor body and the electrode layers;

the electrode layers including a first electrode layer and a second electrode layer,
the insulator including a first insulator contiguous above the first electrode layer, a second insulator contiguous below
the first electrode layer, a third insulator contiguous above the second electrode layer, and a fourth insulator contiguous
below the second electrode layer, the first electrode layer being interposed between the first insulator and the second insulator,
the second electrode layer being interposed between the third insulator and the fourth insulator,

an outer periphery of the semiconductor body having a first outer periphery facing to the first insulator, a second outer
periphery facing to the second insulator, a first base surface facing to the first electrode layer, a third outer periphery
facing to the third insulator, a fourth outer periphery facing to the fourth insulator, and a second base surface facing to
the second electrode layer, the first base surface being disposed between the first outer periphery and the second outer periphery
and being defined by a surface substantially aligned in the stacking direction with the first outer periphery and the second
outer periphery, the second base surface being disposed between the third outer periphery and the fourth outer periphery and
being defined by a surface substantially aligned in the stacking direction with the third outer periphery and the fourth outer
periphery,

a distance from the central axis to the first base surface being larger than a distance from the central axis to the second
base surface,

a distance between the first base surface and the first electrode layer being larger than a distance between the second base
surface and the second electrode layer,

an insulating layer being provided between the first electrode layer and the semiconductor body, the insulating layer including
a center portion, an upper side portion connected to the center portion, and a lower side portion connected to the center
portion, the center portion extending along a surface of the first electrode layer facing to the first base surface, the upper
side portion extending in a direction from the surface of the first electrode layer toward the first base surface on an upper
side of the center portion in the stacking direction, and the lower side portion extending in a direction from the surface
of the first electrode layer toward the first base surface on a lower side of the center portion in the stacking direction.

US Pat. No. 9,811,489

STORAGE DEVICE AND SERVER DEVICE

Toshiba Memory Corporatio...

16. A storage device comprising:
a memory that stores data;
a controller configured to control writing of data to the memory and reading of data from the memory;
an interface unit that includes a first terminal, a second terminal, and a third terminal,
the first terminal having an electrical status different between a case where the first terminal is connected to the first
device, and a case where the first terminal is connected to the second device,

the second terminal being a terminal to which a control signal is input from the second device,
the third terminal being a terminal through which power is supplied from the second device to the storage device;
a switch configured to switch a connection status and a disconnection status based on the control signal, the connection status
representing a status in which the third terminal and the controller are electrically connected, the disconnection status
representing a status in which the third terminal and the controller are electrically disconnected; and

a switch control unit configured to control the switch to switch the connection status and the disconnection status based
on electrical statuses of the first terminal and the second terminal.

US Pat. No. 9,813,096

PLAYBACK OF VISUAL OR AUDIO CONTENT RELATED TO A CAPTURED IMAGE

Toshiba Memory Corporatio...

1. A wireless communication system including a storage apparatus and a computing device, the storage apparatus comprising:
a connector through which the storage apparatus communicates with an electronic apparatus and receives power from the electronic
apparatus;

a wireless antenna through which the storage apparatus communicates with the computing device;
a nonvolatile first memory having stored therein visual or audio content to be output through the electronic apparatus when
the connector is electrically coupled to the electronic apparatus, each item of the visual or audio content being associated
with a content ID;

a communication controller that is powered from an induction current generated when a wireless signal is received through
the wireless antenna, the communication controller including a second memory in which the communication controller stores
a content ID transmitted from the computing device via the wireless signal; and

a controller that is powered using the power supplied from the electronic apparatus through the connector when the connector
is electrically coupled to the electronic apparatus, wherein the controller is configured to retrieve the visual or audio
content from the first memory based on the content ID transmitted from the computing device and transmits the retrieved visual
or audio content to the electronic apparatus through the connector for playback by the electronic apparatus,

wherein the computing device comprises an image capturing unit and is configured to extract a set of feature values from data
of an image captured by the image capturing unit and transmit the wireless signal containing the content ID to the storage
apparatus, the content ID being determined based on the extracted set of feature values and geographical or temporal information
relating to the computing device.

US Pat. No. 9,805,804

SEMICONDUCTOR MEMORY DEVICE AND DATA ERASING METHOD

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:
a memory cell array including a first memory string and a second memory string, the first memory string including memory cells
that are disposed in a first layer, the second memory string including memory cells that are disposed in a second layer above
the first layer; and

a controller configured to perform an erasing operation on the memory cells, the erasing operation including a first period
during which an erasing pulse is applied to the memory cells of the second memory string, and the erasing pulse is not applied
to the memory cells of the first memory string, and a second period directly after the first period during which the erasing
pulse is applied to both the memory cells of the first memory string and the memory cells of the second memory string.

US Pat. No. 9,769,944

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a substrate including a main surface and an end surface adjacent to the main surface;
a conductor layer including a first terminal mounted on the main surface and extended toward the end surface;
a first insulating layer mounted on the main surface and covering a part of the conductor layer, the first insulating layer
including a first opening that exposes at least part of the first terminal;

an electronic component mounted on the substrate; and
a USB connector that includes the substrate, the conductor layer, the first insulating layer, and a front end portion in a
first direction,

wherein the first opening includes a first edge separated from the first terminal in the first direction in which the first
terminal is extended, and a second edge separated from the first terminal in a second direction perpendicular to the first
direction, a distance between the second edge and the first terminal in the second direction being larger than a distance
between the first edge and the first terminal in the first direction,

the first terminal includes a side edge that is extended in the first direction,
the second edge includes a third edge and a fourth edge that are separated from the first terminal in the second direction
and face the side edge,

the third edge is closer to the end surface than the fourth edge is,
a distance between the third edge and the first terminal is smaller than a distance between the fourth edge and the first
terminal,

a distance between the front end portion and an end of the third edge in a direction of being more distant from the front
end portion in the first direction is smaller than 3.90 mm, and

the conductor layer includes a second terminal that is extended toward the end surface, a third terminal that is extended
toward the end surface, and a wiring that is extended from the second terminal in a direction intersecting with the first
direction and connects the second terminal and the electronic component to each other.

US Pat. No. 9,888,451

METHOD OF DYNAMICALLY ASSOCIATING AN ACCESSORY ID WITH A PORTABLE MEMORY DEVICE AND DISPLAYING CONFIRMATION OF THE ASSOCIATION

Toshiba Memory Corporatio...

1. In a system where data generated in connection with an accessory ID may be stored in one of a plurality of portable memory
devices including a first portable memory device, a method of dynamically associating the accessory ID with the first portable
memory device and displaying confirmation of the association, comprising:
when an accessory having the accessory ID and the first portable memory device are coupled with a host apparatus, detecting
the accessory ID and storing the accessory ID in the first portable memory device;

wirelessly transmitting the accessory ID and a device ID of the first portable memory device to a user computing device for
registration of the accessory ID and the device ID of the first portable memory device in association with one another; and

subsequent to the registration, upon determining that a code that is captured from a portable memory device uniquely corresponds
to that of the first portable memory device, retrieving an image corresponding to the accessory ID that is registered in association
with the device ID of the first portable memory device, and displaying the image on a display device for visual confirmation
that the portable memory device contains the data generated in connection with the accessory ID.

US Pat. No. 9,865,656

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, including a memory cell array, the memory cell array including a plurality of memory cells,
the memory cell array comprising:
a plurality of first conductive layers that are stacked in a first direction above a substrate and extend in a second direction
intersecting the first direction;

a plurality of second conductive layers that are stacked in the first direction above the substrate and extend in the second
direction, the plurality of second conductive layers being adjacent to the plurality of the first conductive layers in a third
direction intersecting the first direction and the second direction;

a third conductive layer extending in the first direction;
a first variable resistance film provided at intersections of the plurality of first conductive layers and the third conductive
layer;

a second variable resistance film provided at intersections of the plurality of second conductive layers and the third conductive
layer;

a first select transistor disposed closer to the substrate than a lowermost layer of the plurality of first conductive layers,
the first select transistor including a first select gate line intersecting the third conductive layer;

a fourth conductive layer that extends in the third direction and is connected to a lower end of the third conductive layer
via the first select transistor; and

a second select transistor disposed between at least one pair of the plurality of first conductive layers adjacent in the
first direction, the second select transistor including a second select gate line intersecting the third conductive layer.

US Pat. No. 9,858,992

SEMICONDUCTOR MEMORY DEVICE WHICH STORES PLURAL DATA IN A CELL

TOSHIBA MEMORY CORPORATIO...

1. A method for controlling a semiconductor memory device comprising a memory cell array configured to have a plurality of
memory cells arranged in a matrix, each of the plurality of memory cells being connected to a word line and a bit line and
being capable of storing n values (n is a natural number equal to or larger than 3), the method comprising:
controlling potentials of the word line and the bit line according to input data to write data into a memory cell;
writing data into the memory cell to an a1-valued (a1?n) threshold voltage in a first write operation, to an a2-valued (a2?n)
threshold voltage in a second write operation, and to an ak-valued (ak?n) threshold voltage in a k-th write operation (k is
a natural number equal to or larger than 2: k?n), in the first to k-th write operations; and

performing write operations by repeating program and verify operations while raising a program voltage in increments of ?Vpgm,
wherein ?Vpgm in the first to k-th write operations fulfill the following expression:
?Vpgm in the first write operation>?Vpgm in the second write operation> . . . >?Vpgm in the kth write operation.

US Pat. No. 9,859,954

FILE TRANSMISSION/RECEPTION DEVICE AND CONTROL METHOD OF FILE TRANSMISSION/RECEPTION DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A file transmission/reception device comprising:
a communication direction managing unit that, if in near field communication a conflict occurs in a connection at a second
communication layer higher than a first communication layer with an opposing device, cuts off the connection at the second
communication layer with the opposing device, decides a mode of the file transmission/reception device when performing a re-connection
at the second communication layer via the connection at the first communication layer with the opposing device as any one
mode of a master mode and a slave mode, and switches the file transmission/reception device to the decided mode; and

an application unit that performs transmission, reception, or transmission/reception of a file with the opposing device and
the file transmission/reception device in the decided mode, wherein

the communication direction managing unit determines whether the opposing device is compliant with a bidirectional communication
operation,

if the opposing device is compliant with the bidirectional communication operation, the communication direction managing unit
decides the mode such that the file transmission/reception device performs a bidirectional communication process, and

if the opposing device is not compliant with the bidirectional communication operation, the communication direction managing
unit decides the mode such that the file transmission/reception device performs an unidirectional communication process.

US Pat. No. 9,849,558

POLISHING PAD DRESSER, POLISHING APPARATUS AND POLISHING PAD DRESSING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A polishing pad dresser comprising:
a first base portion;
first convex portions provided in a first region of the first base portion;
a second base portion adjacent to the first base portion; and
second convex portions provided in a second region of the second base portion,
wherein
a width of the first convex portions is 1 to 10 ?m,
a height of the first convex portions is 0.5 to 10 ?m,
a density of the first convex portions in the first region is 0.1 to 50%,
a width of the second convex portions is greater than 10 ?m, and
a height of the second convex portions is greater than 10 ?m.
US Pat. No. 9,841,674

PATTERNING METHOD, AND TEMPLATE FOR NANOIMPRINT AND PRODUCING METHOD THEREOF

Toshiba Memory Corporatio...

1. A patterning method comprising:
forming a ground layer on a processing target layer, the ground layer having higher affinity for one of a first segment and
a second segment contained in a self-assembly material than for the other segment;

forming and patterning a neutral layer neutral to the first segment and the second segment on the ground layer;
irradiating exposed surfaces of the ground layer and the neutral layer with an energy ray;
applying the self-assembly material onto the irradiated ground layer and the irradiated neutral layer;
phase-separating the self-assembly material into a first domain including the first segment and a second domain including
the second segment by annealing the self-assembly material; and

selectively removing one of the first domain and the second domain.

US Pat. No. 9,842,990

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a semiconductor layer including a first region and a second region, the second region including at least one of a region being
amorphous or a region having a crystallinity lower than a crystallinity of the first region;

a gate electrode apart from the first region in a first direction, the first direction crossing a second direction connecting
the first region and the second region;

a metal containing portion apart from the second region in the first direction, at least a part of the metal containing portion
overlapping the gate electrode in the second direction; and

an insulating portion provided between the gate electrode and the first region and between the metal containing portion and
the second region.

US Pat. No. 9,831,180

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:
a substrate;
a stacked body provided on the substrate,
the stacked body including a plurality of electrode layers stacked with an insulator interposed,
the stacked body including a stacked portion and a staircase portion,
the staircase portion provided outside the stacked portion,
the plurality of electrode layers including a first portion and a second portion,
the first portion provided in the stacked portion,
the second portion provided in the staircase portion,
the second portion stacked in a staircase pattern in the staircase portion; and
a plurality of columnar portions provided in the stacked portion of the stacked body,
the plurality of columnar portions extending in a stacking direction of the stacked body,
the plurality of columnar portions including a semiconductor body extending in the stacking direction, and a charge storage
film,

the charge storage film provided between the semiconductor body and the plurality of electrode layers, wherein
the second portion of the electrode layers includes a third portion, and
a thickness of the third portion of the electrode layers along the stacking direction of the stacked body is thinner than
a thickness of the first portion of the electrode layers along the stacking direction of the stacked body.

US Pat. No. 9,818,523

ELECTROMAGNET, TESTER AND METHOD OF MANUFACTURING MAGNETIC MEMORY

TOSHIBA MEMORY CORPORATIO...

1. An electromagnet comprising:
a first electromagnet coil having a first portion and a second portion,
wherein:
the first portion of the first electromagnet coil includes sub-portions which are parallel with a first plane and which extend
in different directions that intersect with each other within the first plane,

the second portion of the first electromagnet coil includes sub-portions which are parallel with a second plane and which
extend in different directions that intersect with each other within the second plane, and

the first and second planes intersect at a predetermined angle.

US Pat. No. 9,812,215

MEMORY DEVICE THAT EXECUTES AN ERASE OPERATION FOR A NONVOLATILE MEMORY

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:
a controller; and
a nonvolatile memory in which an erase operation is controlled by the controller, the nonvolatile memory including blocks,
each of the blocks being a unit for the erase operation, the nonvolatile memory transferring a first reply showing a completion
of the erase operation and first information based on a number of memory cells in which a data erase is uncompleted after
the completion of the erase operation to the controller.

US Pat. No. 9,811,462

MEMORY SYSTEM EXECUTING GARBAGE COLLECTION

Toshiba Memory Corporatio...

1. A memory system comprising:
a nonvolatile memory including first and second memory areas; and
a controller controlling the nonvolatile memory, the controller configured to:
detect data amounts of valid data written to the first memory area and data amounts of valid data written to the second memory
area;

update, if writing for the second memory area is executed after writing for the first memory area, at least one of first and
second thresholds such that the first threshold corresponding to the first memory area is greater than the second threshold
corresponding to the second memory area;

select the first memory area as a memory area of a garbage collection target if the data amounts of the first memory area
are smaller than the first threshold, and select the second memory area as the memory area of the garbage collection target
if the data amounts of the second memory area are smaller than the second threshold; and

execute garbage collection on the selected memory area of the garbage collection target.

US Pat. No. 9,811,493

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a memory:
a data register coupled to the memory;
an input/output circuit coupled to the data register and configured to input and output data to and from an external controller
which issues and transmits a command to the device,

wherein the input/output circuit includes:
a first clock generator configured to generate a first clock signal and transmit the first clock signal to a first signal
line,

a first selector configured to receive first data from a first bus, receive second data from a second bus, and transmit one
of the first and second data to a third bus,

a second selector configured to receive the one of the first and second data from the third bus, receive third data from a
fourth bus, receive the first clock signal corresponding to the first and second data from the first signal line, receive
a second clock signal corresponding to the third data from a second signal line, transmit one of the first to third data to
a fifth bus, and transmit one of the first and second clock signals to a third signal line; and

a first-in-first-out (FIFO) circuit configured to receive the one of the first to third data from the fifth bus and receive
the one of the first and second clock signals from the third signal line,

when a read operation of the one of the first and second data is executed, the FIFO circuit receives the one of the first
and second data in response to the first clock signal within a period from when a read command and address data are received
until a read enable signal is received from the external controller, and

when a read operation of the third data is executed, the FIFO circuit receives the third data in response to the second clock
signal within the period.

US Pat. No. 9,811,270

SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER

Toshiba Memory Corporatio...

1. A storage device comprising:
a first memory string including a first memory cell, a second memory cell, and a first selection transistor;
a second memory string including a third memory cell, a fourth memory cell, and a second selection transistor;
a third memory string including a fifth memory cell, a sixth memory cell, and a third selection transistor;
a bit line coupled to the first, second, and third memory strings;
a first word line coupled to gates of the first memory cell, the third memory cell, and the fifth memory cell; and
a second word line coupled to gates of the second memory cell, the fourth memory cell, and the sixth memory cell,
wherein a first page address is allocated to a page associated with the first memory cell, a second page address is allocated
to a page associated with the third memory cell, a third page address is allocated to a page associated with the fifth memory
cell, a fourth page address is allocated to a page associated with the second memory cell, a fifth page address is allocated
to a page associated with the fourth memory cell, and a sixth page address is allocated to a page associated with the sixth
memory cell.

US Pat. No. 9,805,797

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
more than three first memory units each comprising a first select gate transistor; a second select gate transistor; and memory
cell transistors serially coupled in series between the first select gate transistor and the second select gate transistor;

a plurality of first lines coupled to the first select gate transistors such that one respective first line is connected to
one respective first select gate transistor;

a plurality of second lines coupled to the second select gate transistors such that one respective second line is connected
to one respective second select gate transistor;

a plurality of third lines coupled to the memory cell transistors such that one respective third line is connected to one
respective memory cell transistor;

a plurality of drivers including (i) only two first drivers configured to be connected to the first select gate transistors
and only two second drivers configured to be connected to the second select gate transistors, the only two first drivers including
(ia) a first drain select driver that outputs only a selecting voltage that selects the first select gate transistors and
(ib) a first drain unselect driver that outputs only an unselecting voltage that unselects the first select gate transistors,
and the plurality of drivers further including (ii) drivers for the memory cell transistors; and

a plurality of first drive transistors coupled to the first lines and a second common signal line such that one respective
first drive transistor is coupled to either one respective first line or one respective second line, gates of the first drive
transistors connected to a third common signal line.

US Pat. No. 9,805,798

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device, comprising
a memory cell array configured as an arrangement of NAND cell units each including a memory string and select transistors
connected to both ends of the memory string respectively, the memory string including a plurality of nonvolatile memory cells
connected in series, the nonvolatile memory cells including dummy cells which are not used for data storage provided at the
both ends of the memory string and memory cells for data storage which are capable of storing multi-bit data provided between
the dummy cells in the memory string;

word lines connected to control gate electrodes of the memory cells for data storage;
dummy word lines connected to control gate electrodes of the dummy cells;
bit lines connected to first ends of the NAND cell units;
a source line connected to second ends of the NAND cell units; and
a control circuit configured to perform an erasing operation by applying an erasing voltage to the NAND cell units arranged
in a block, the NAND cell units that share the word lines forming the block,

before the erasing operation for the NAND cell units, the control circuit being configured to execute a pre-program operation
in which a certain pre-program voltage is applied to the memory cells for data storage in the NAND cell units and a voltage
different from the certain pre-program voltage is applied to the dummy cells in the NAND cell units, and after the pre-program
operation is finished, the control circuit being configured to start the erasing operation without performing a verify operation,
and

after the erasing operation for the NAND cell units, the control circuit being configured to execute an erasing verify operation
to check whether the memory cells for data storage in the NAND cell units are in an erased state or not in which a certain
voltage is applied to the word lines as well that are connected to the control gate electrodes of the memory cells for data
storage to be checked in the erased state or not in the NAND cell units.

US Pat. No. 9,793,120

DEVICE SUBSTRATE, METHOD OF MANUFACTURING DEVICE SUBSTRATE, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A device substrate comprising a multilayer film that is disposed on a semiconductor wafer, wherein
a main face of the device substrate on which the multilayer film is disposed includes
a patterning region on which a resist is to be applied, and
a bevel region provided as a region from a peripheral edge portion of the patterning region to an end portion of the device
substrate,

the multilayer film on the patterning region includes a mask film that is an uppermost layer film of the multilayer film,
the multilayer film on the bevel region does not include the mask film that is the uppermost layer film of the multilayer
film which presents on the patterning region,

the bevel region includes the region where an upper surface of the bevel region becomes lower toward the end portion of the
device substrate relative to an upper surface of the patterning region, and

the upper surface of the multilayer film that does not include the mask film on the bevel region has an inclination angle
of 10° or more and 90° or less with respect to the upper surface of the multilayer film in which the uppermost layer film
is the mask film on the patterning region, at a boundary between the patterning region and the bevel region.

US Pat. No. 9,768,265

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a semiconductor layer;
a first electrode;
a first oxide layer provided between the semiconductor layer and the first electrode;
a second oxide layer provided between the first oxide layer and the first electrode; and
a storage layer provided between the first oxide layer and the second oxide layer, the storage layer including:
a first region including silicon nitride;
a second region provided between the first region and the second oxide layer and including silicon nitride; and
a third region provided between the first region and the second region and including a plurality of first metal atoms,
a first density of bond of the first metal atoms in the third region being lower than a second density of bond of the first
metal atom and a nitrogen atom in the third region.

US Pat. No. 9,754,781

SEMICONDUCTOR MANUFACTURING METHOD

Toshiba Memory Corporatio...

1. A semiconductor manufacturing method comprising:
feeding a first gas to a reaction chamber, the first gas comprises a component of a first film;
feeding a high-frequency electric power to the reaction chamber for forming a first film over a semiconductor substrate provided
in the reaction chamber using plasma CVD method, the reaction chamber being deaerated;

feeding a second gas to the deaerated reaction chamber for forming a second film over the surface of the first film after
forming the first film without suspending the feeding of the high-frequency electric power, allowing the first gas in the
reaction chamber to react on the second gas, the second film comprises a composition different from that of the first film;

suspending the feeding of the high-frequency electric power for stopping the forming of the second film; and
selectively removing the second film.

US Pat. No. 9,985,044

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:a first stacked body including a plurality of first conductive layers arranged in a first direction;
a second stacked body being arranged in the first direction with the first stacked body and including a plurality of second conductive layers arranged in the first direction;
an intermediate conductive layer provided between the first stacked body and the second stacked body;
an intermediate insulating layer provided between the intermediate conductive layer and the second stacked body;
a semiconductor pillar including a first part, a second part, and a third part, the first part extending in the first direction through the first stacked body and through the intermediate conductive layer, the second part extending in the first direction through the second stacked body, the third part being provided inside the intermediate insulating layer and being continuous with the first part and the second part, a central axis of the first part being shifted from a central axis of the second part in a second direction intersecting the first direction;
a charge storage film including a first charge storage portion and a second charge storage portion, the first charge storage portion being provided between the first stacked body and the first part, the second charge storage portion being provided between the second stacked body and the second part and between the intermediate insulating layer and the third part, the charge storage film including at least one first element selected from the group consisting of nitrogen, hafnium, and aluminum; and
an insulating film provided in at least a portion between the intermediate conductive layer and the first part, the insulating film not including the first element, or the insulating film having a concentration of the first element lower than a concentration of the first element of the charge storage film,
wherein the insulating film includes at least a portion not overlapping the charge storage film in the second direction.

US Pat. No. 9,857,984

MEMORY SYSTEM WITH GARBAGE COLLECTION

Toshiba Memory Corporatio...

1. A memory system comprising:
a nonvolatile memory; and
a controller configured to control the nonvolatile memory,
wherein the controller includes:
an access controller configured to control access to the nonvolatile memory, based on a first request which is issued from
a host;

a processor configured to execute garbage collection for securing, on the nonvolatile memory, a free area for writing data
in the nonvolatile memory, based on a second request which is issued from the host before the first request is issued; and

a scheduler configured to schedule the garbage collection by controlling the processor,
wherein the first request is a first command which requests write to the nonvolatile memory, and
the second request is a second command to execute the garbage collection before the first command is issued, the second command
including a size of write data of the first command.

US Pat. No. 9,859,011

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:
a memory cell array including first memory cells and second memory cells;
a first word line connected to gates of the first memory cells;
a second word line connected to gates of the second memory cells; and
a control circuit that executes a first read operation in response to a first command set, and a second read operation in
response to a second command set following the first command set, wherein

the first read operation includes a first read sequence, in which the control circuit reads data from the first memory cells
by applying at least first to third voltages which are different from each other, to the first word line, and a second read
sequence, in which the control circuit reads the data from the first memory cells by applying a first read voltage that is
set based on the result of the first read sequence, to the first word line, and

in the second read operation, the control circuit reads data from the second memory cells by applying a second read voltage
that is set based on the result of the first read sequence of the first read operation, to the second word line.

US Pat. No. 9,852,063

MEMORY DEVICE AND NON-TRANSITORY COMPUTER READABLE RECORDING MEDIUM

Toshiba Memory Corporatio...

1. A memory device communicating with an information processing device, the memory device comprising:
a nonvolatile memory including a plurality of erase unit areas, each of the erase unit areas including a plurality of write
unit areas;

an address translation unit which generates address translation information relating a logical address of write data written
to the nonvolatile memory to a physical address indicative of a write position of the write data in the nonvolatile memory;

a write unit which writes the write data to the write position indicated by the physical address;
a generation unit which generates, based on the address translation information, valid/invalid information indicating whether
data written to the plurality of erase unit areas is valid data or invalid data, the valid/invalid information including information
relating identification information of the erase unit area to a logical address indicative of the valid data or the invalid
data written to the erase unit area;

a selection unit which selects an erase unit area to be subjected to garbage collection from the plurality of erase unit areas;
a transmission unit which generates, based on the valid/invalid information, area information including a logical address
indicative of valid data written to the erase unit area to be subjected to garbage collection, and transmits the area information
to the information processing device;

a reception unit which receives deletion information including a logical address indicative of data to be deleted amongst
the valid data in the erase unit area to be subjected to garbage collection from the information processing device; and
a garbage collection unit which performs garbage collection of the valid data written to the erase unit area to be subjected
to garbage collection excluding the data to be deleted.

US Pat. No. 9,847,345

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a stacked body, the stacked body including a plurality of control gate electrodes stacked above a substrate;
a memory columnar body that extends in a first direction above the substrate and configures a memory string along with the
stacked body; and

a source contact extending in the first direction and being electrically connected to one end of the memory string,
the source contact being adjacent to the stacked body via a spacer insulating layer, and
a spacer protective layer being provided between the source contact and the spacer insulating layer and including a nitride
or a metal oxide.

US Pat. No. 9,831,150

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Toshiba Memory Corporatio...

1. A semiconductor device comprising:
a first substrate having a first face;
a second substrate disposed on the first face, the second substrate having a second face that faces the first face and a third
face that is opposite to the second face;

a first electronic component disposed on the third face, the first electronic component having a fourth face that faces the
third face and a fifth face that is opposite to the fourth face;

a heat-conducting layer covering the third face and the fifth face;
a covering portion on top of the heat-conducting layer, which is on the second substrate, the covering portion covering at
least the heat-conducting layer; and

a heat-transporting portion thermally connecting the heat-conducting layer and the first substrate, the heat-transporting
portion being located outside the second substrate and outside the covering portion.

US Pat. No. 9,818,627

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MANUFACTURING APPARATUS

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing apparatus comprising:
a cleaning-liquid supply part supplying a cleaning liquid cleaning a semiconductor substrate to a surface of the semiconductor
substrate; and

a chemical-liquid supply part supplying a first chemical liquid for forming a water-repellent protection film and a second
chemical liquid coating the first chemical liquid on the surface of the semiconductor substrate without mixing with the first
chemical liquid, wherein

the chemical-liquid supply part has a double piping structure comprising a first pipe supplying the first chemical liquid
and a second pipe supplying the second chemical liquid, wherein the second pipe is provided to surround an outer circumference
of the first pipe.

US Pat. No. 9,812,195

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device, comprising:
a cell array including a plurality of unit cell arrays arranged in a matrix, one of the unit cell arrays including a plurality
of bit lines, a plurality of word lines intersecting the bit lines, and a plurality of electrically rewritable memory cells
connected at intersections of the bit lines and the word lines between both lines and each including a variable resistance
element; and

a control circuit corresponding to one of the unit cell arrays configured to control voltages applied to the bit lines and
the word lines, the control circuit including a row control circuit to select the word lines, and a column control circuit
to select the bit lines, at least a part of the control circuit being provided beneath the corresponding unit cell array,

the control circuit, during data write to the cell array, simultaneously writing a part of data having a plurality of bits
to at least one of the memory cells belonging to one of the unit cell arrays, and another part of the data to at least one
of the memory cells belonging another of the unit cell arrays, the memory cells written simultaneously being physically separated
apart more than one memory cell from each other.

US Pat. No. 9,804,795

MEMORY SYSTEM AND CONTROLLER

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:
a non-volatile memory that stores user data received from a host;
a controller that controls data transfer between the host and the non-volatile memory; and
a power supply that supplies a voltage to the controller,
wherein the controller includes:
a power supply control unit that determines the voltage supplied to a module in the controller on the basis of an operation
condition determined with the host, the operation condition being a PCIe interface speed that is determined with the host,
and

a PCIe controller that performs data communication with the host using a communication interface based on PCIe specification,
wherein the power supply unit adjusts the voltage supplied to the module in accordance with a command from the power supply
control unit.

US Pat. No. 9,741,739

SEMICONDUCTOR MANUFACTURING METHOD AND SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing method comprising:
alternately stacking first films and second films to form a stack film;
forming a plurality of recessed portions in a stack direction of the stack film at an interval in a first direction substantially
perpendicular to the stack direction;

forming third films in the recessed portions, respectively;
forming a mask material on the stack film and the third films and diminishing the mask material in the first direction to
expose the stack film in a first range between an end of a stepped portion to be formed on the stack film and one of the third
films and to position an end of the mask material on the third film; and

removing a predetermined number of layers of films from the stack film in the first range using the diminished mask material
as a mask to form the stepped portion on the stack film.

US Pat. No. 9,761,318

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device, comprising:
a plurality of word lines;
a plurality of bit lines;
a plurality of memory cells at intersections of the word lines and the bit lines;
a word line driver configured to apply a voltage to a selected word line among the plurality of word lines;
a sense amplifier circuit configured to detect the data of at least one of the memory cells; and
a controller configured to control the word line driver and the sense amplifier,
wherein a write sequence for writing first data to a selected memory cell connected to the selected word line includes a write
loop that includes a write operation in which a write voltage is applied to the selected word line by the word line driver,
and a verify operation during which, when a threshold voltage of the selected memory cell reaches a reference voltage, writing
to the selected memory cell is completed by the controller,

based on second data to be written to a memory cell adjacent to the selected memory cell at a time later than the first data,
the controller changes the reference voltage used for the verify operation of the selected memory cell, and

the adjacent memory cell is connected to a word line adjacent to the selected word line.

US Pat. No. 10,032,790

SEMICONDUCTOR DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device, comprising:a substrate having a major surface;
a stacked body provided on the major surface of the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed, the plurality of electrode layers including a first electrode layer, a second electrode layer, and a third electrode layer, the first electrode layer being most proximal to the major surface of the substrate, the second electrode layer being most distal to the major surface of the substrate, the third electrode layer being provided between the first electrode layer and the second electrode layer;
a columnar portion provided inside the stacked body, the columnar portion extending along a stacking direction of the stacked body, the columnar portion including a semiconductor body and a memory film, the memory film being provided between the semiconductor body and the third electrode layer, the memory film including a charge storage portion; and
a plate portion provided inside the stacked body, the plate portion extending along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction, the plate portion including a plate conductor and a sidewall insulating film, the sidewall insulating film being provided between the plate conductor and the stacked body, the plate portion including a first portion, a second portion, and a third portion along the stacking direction of the stacked body, the third portion being provided between the first portion and the second portion,
a width of the first portion along a second direction being narrower than a width of the third portion along the second direction, the second direction being orthogonal to the first direction and being along the major surface of the substrate,
a width of the second portion along the second direction being narrower than the width of the third portion along the second direction.

US Pat. No. 9,865,809

NONVOLATILE RESISTANCE CHANGE ELEMENT

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile resistance change element comprising:
a first electrode comprising a metal element;
a second electrode comprising an n type semiconductor;
a first layer provided between the first electrode and the second electrode, the first layer including a conductor portion
made of the metal element, and the conductor portion and the second electrode being spaced apart; and

a second layer provided between the first layer and the second electrode, and which is in contact with the first layer and
the second electrode,

wherein the first layer and the second layer are made of silicon oxide, or the first layer and the second layer are made of
silicon nitride, or the first layer and the second layer are made of silicon oxynitride, and

wherein the second layer differs from the first layer in one of a density, a number of dangling bonds, or a number of defects.

US Pat. No. 9,857,978

OPTIMIZATION OF MEMORY REFRESH RATES USING ESTIMATION OF DIE TEMPERATURE

Toshiba Memory Corporatio...

1. A memory system comprising:
a memory configured to have stored data periodically rewritten by a refresh command, the memory having an input/output (“I/O”)
terminal;

a memory controller communicatively coupled by a channel to the I/O terminal and configured to transmit a first plurality
of commands over the channel to the memory, the memory controller further configured to:

estimate a first total energy consumed based on the first plurality of commands during a first sampling period;
determine a first temperature of the memory based on the first total energy consumed in the first sampling period;
determine a first refresh cycle rate corresponding to the first temperature of the memory, and
transmit a refresh command to the memory according to the first refresh cycle rate.

US Pat. No. 9,853,013

SEMICONDUCTOR DEVICE HAVING STACKED CHIPS

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a first chip having a first via and a second via through the first chip; and
a second chip provided on the first chip and having a third via and a fourth via through the second chip;
wherein the first chip includes:
a first inversion circuit, the first inversion circuit being configured to invert a first address signal to an first inverted
address signal and supply the first inverted address signal to the second chip through the first via;

a first logical operation circuit connected to the first inversion circuit, the first logical operation circuit being configured
to perform a logical operation on a second address signal and the first inverted address signal, and supply a first arithmetic
operation output signal to the second chip through the second via; and

a first selection circuit connected to the first logical operation circuit, the first selection circuit being configured to
select a chip based on at least the first arithmetic operation output signal.

US Pat. No. 9,846,552

MEMORY DEVICE AND STORAGE SYSTEM HAVING THE SAME

Toshiba Memory Corporatio...

1. A memory device comprising:
a nonvolatile memory including a plurality of memory chips; and
a memory controller configured to:
upon receiving an access command including a size of data to be accessed and a logical address corresponding to a part of
the data to be accessed, translate the logical address to a physical address of the nonvolatile memory, by referring to a
first table storing a correspondence between physical addresses of the nonvolatile memory and logical addresses,

identify remaining physical addresses corresponding to the data to be accessed in accordance with the access command, other
than the translated physical address, based on the size of the data to be accessed and the translated physical address, and
by referring to a second table indicating a sequence of accessing the memory chips of the nonvolatile memory, and

access the nonvolatile memory at the translated and identified physical addresses.

US Pat. No. 9,831,256

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

TOSHIBA MEMORY CORPORATIO...

12. A semiconductor device, comprising:
a base member;
a stacked body provided above the base member, the stacked body including a plurality of electrode layers stacked in a first
direction with an insulator interposed, the first direction being a direction in which the base member and the stacked body
are arranged, an end portion in a second direction of the stacked body including a staircase portion, the second direction
crossing the first direction, a plurality of terraces and a plurality of level differences being arranged alternately in the
second direction in the staircase portion, the plurality of terraces respectively being upper surfaces of the plurality of
electrode layers, the plurality of level differences respectively including side surfaces of the plurality of electrode layers;

a plurality of contact portions provided in regions directly above the plurality of terraces, the plurality of contact portions
being electrically connected respectively to the plurality of electrode layers; and

a plurality of posts extending through the staircase portion in the first direction and respectively crossing the plurality
of level differences, each of the plurality of posts contacting the base member,

the plurality of contact portions and the plurality of posts being arranged along the second direction,
the plurality of posts extending outside the plurality of contact portions on two sides in a third direction crossing the
first direction and the second direction.

US Pat. No. 9,831,261

SEMICONDUCTOR MEMORY DEVICE WITH FIRST AND SECOND SEMICONDUCTOR FILMS IN FIRST AND SECOND COLUMNAR BODIES

TOSHIBA MEMORY CORPORATIO...

13. A semiconductor memory device, comprising:
a plurality of conductive layers stacked in a vertical direction on a semiconductor substrate; and
a first columnar body and a second columnar body that extend in the vertical direction and have a side surface facing a side
surface of the plurality of conductive layers,

the first columnar body and the second columnar body each comprising:
a first insulating film;
a first semiconductor film disposed on the first insulating film; and
a multi-layer film including a second semiconductor film disposed between the plurality of conductive layers and the first
insulating film, and

the first semiconductor film of the first columnar body having a lower end terminating at an upper surface of the first insulating
film in the first columnar body,

the first semiconductor film of the second columnar body having a lower end penetrating into the first insulating film in
the second columnar body to lower than the upper surface of the first insulating film in the second columnar body, and

the second columnar body having a cross-section which is larger than that of the first columnar body at the same position
in the vertical direction.

US Pat. No. 9,831,290

SEMICONDUCTOR MEMORY DEVICE HAVING LOCAL BIT LINE WITH INSULATION LAYER FORMED THEREIN

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
first conductive layers extending in a first direction and stacked in a second direction intersecting the first direction;
a first semiconductor layer, extending in the second direction and including a material having one of a first conductivity
type and a second conductivity type;

a first insulation layer disposed inside the first semiconductor layer;
a second conductive layer disposed inside the first insulation layer;
a variable resistance layer disposed between the first conductive layers and the first semiconductor layer;
a second semiconductor layer which is in contact with a lower end of the first semiconductor layer; and
a third conductive layer which is in contact with a lower end of the second semiconductor layer, and extends in a third direction
intersecting the first direction and the second direction.

US Pat. No. 9,824,905

SEMICONDUCTOR MANUFACTURING DEVICE AND SEMICONDUCTOR MANUFACTURING METHOD

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor manufacturing device comprising:
an upper cover configured to be arranged above top surfaces of unshielded semiconductor devices which are mounted on a tray
placed on a carrier to go through electromagnetic shielding; and

a displacement detector configured to detect an abnormality when the upper cover is raised, by at least one of the semiconductor
devices which are brought into contact with a bottom surface of the upper cover.

US Pat. No. 9,812,639

NON-VOLATILE MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A non-volatile memory device comprising:
a first interconnection;
a second interconnection closest to the first interconnection in a first direction;
a first rectifying portion disposed between the first interconnection and the second interconnection, the first rectifying
portion including a first metal oxide layer and a second metal oxide layer stacked in the first direction;

a second rectifying portion provided between the first rectifying portion and the second interconnection, the second rectifying
portion including another first metal oxide layer and another second metal oxide layer stacked in the first direction; and

a first resistance change portion disposed between the first rectifying portion and the second rectifying portion; and
a second resistance change portion disposed between the second interconnection and the second rectifying portion,
the first metal oxide layer and the another second metal oxide layer being in contact with the first resistance change portion.

US Pat. No. 9,811,417

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:
an encoder configured to generate an error correction code with respect to data;
a first processor configured to perform interleaving with respect to the data from the encoder after the generation of the
error correction code;

a memory configured to store a process result from the first processor;
a detector configured to detect a credibility value indicative of credibility of the data read from the memory; and
a controller configured to determine whether or not the credibility value of the data read from a predetermined area of the
memory is equal to or greater than a predetermined value based on a detection result from the detector, the controller configured
to perform the interleaving with respect to the data read from the predetermined area if the credibility value is equal to
or greater than the predetermined value and to withhold the interleaving with respect to the data read from the predetermined
area if the credibility value is less than the predetermined value.

US Pat. No. 9,811,275

MEMORY SYSTEM AND DATA CONTROL METHOD

TOSHIBA MEMORY CORPORATIO...

1. A memory system comprising:
a non-volatile memory configured to include a plurality of blocks and to store first information, the plurality of blocks
including a plurality of word lines, each word line being connected to a plurality of memory cells, the plurality of memory
cells connected to one word line having a storage capacity of two or more pages, the first information being used to manage
a correspondence between logical addresses and physical addresses, the physical addresses specifying storage locations in
the non-volatile memory; and

a controller configured to
receive a first write request from a host, the first write request designating a first logical address,
write first data in a first storage location in the non-volatile memory in response to the first write request, the first
storage location corresponding to a first physical address,

register the first physical address as a physical address corresponding to the first logical address in the first information,
receive a second write request from the host, the second write request designating the first logical address,
write second data in a second storage location in the non-volatile memory in response to the second write request, the second
storage location corresponding to a second physical address,

perform a first process of changing a physical address corresponding to the first logical address in the first information
from the first physical address to the second physical address,

store in the non-volatile memory second information in which the first physical address and the second physical address are
associated, and

perform a second process of changing a physical address corresponding to the first logical address in the first information
from the second physical address to the first physical address, with using the second information.

US Pat. No. 9,786,683

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

TOSHIBA MEMORY CORPORATIO...

1. A nonvolatile semiconductor memory device, comprising:
a memory cell array including a memory cell;
a wiring part connecting the memory cell array to an external circuit; and
a transistor that connects the wiring part and the external circuit,
the transistor comprising:
a first insulating layer including a first region, a second region, and a third region, the second and third regions being
disposed on both sides of the first region, and a height of an upper surface of the first region being lower than those of
the second region and the third region;

a semiconductor layer disposed along upper surfaces of the first region, the second region, and the third region; and
a gate electrode layer disposed via the semiconductor layer and a gate insulating film, on an upper part of the second region.

US Pat. No. 9,761,798

STORAGE DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A storage device comprising:
a first conductive layer containing a first element selected from the group consisting of Si, Ge, and a metal element;
a second conductive layer including a first region containing a first metal element and at least one of carbon and nitrogen,
a second region containing a second metal element and at least one of carbon and nitrogen, and a third region provided between
the first region and the second region, the third region containing a third metal element, a standard free energy of formation
of an oxide of the third metal element being smaller than a standard free energy of formation of an oxide of the first element;

a ferroelectric layer provided between the first conductive layer and the second conductive layer; and
a paraelectric layer provided between the first conductive layer and the ferroelectric layer.

US Pat. No. 9,754,632

SEMICONDUCTOR MEMORY SYSTEM

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor device comprising:
a substrate; and
a plurality of nonvolatile semiconductor memories mounted on the substrate, wherein the substrate includes:
a first main surface and a second main surface, the second main surface facing a direction opposite to a direction in which
the first main surface is facing;

a first wiring layer provided on the first main surface, the nonvolatile semiconductor memories being mounted on the first
wiring layer;

a second wiring layer provided on the second main surface;
a plurality of wiring layers disposed as an inner layer; and
a plurality of insulating layers provided between the first wiring layer, the plurality of wiring layers, and the second wiring
layer, wherein

an average value of a wiring density of the wiring layers and the second wiring layer that are disposed on the second main
surface side with respect to a center line of a layer structure of the substrate is equal to or greater than an average value
of a wiring density of the wiring layers and the first wiring layer that are disposed on the first main surface side with
respect to the center line of the layer structure of the substrate, and a difference between these average values is 7.5%
or less, and

a wiring density of at least one of the plurality of wiring layers is 80% or greater.

US Pat. No. 9,858,379

MASK DATA GENERATION SYSTEM, MASK DATA GENERATION METHOD, AND RECORDING MEDIUM

TOSHIBA MEMORY CORPORATIO...

1. A mask data generation system that generates data of a mask, the mask generation system being realized in a computer and
comprising:
a first acquisition part configured to acquire pattern contour data included in each of a plurality of layout candidate data
for a first layer;

a second acquisition part configured to acquire pattern contour data included in layout data for a second layer;
a third acquisition part configured to acquire pattern contour data included in layout data for a third layer;
a superimposing part configured to superimpose the contour data acquired by the first acquisition part and the contour data
acquired by the second acquisition part with each other to obtain a first superimposed data for each of the plurality of layout
candidate data, and to superimpose the contour data acquired by the first acquisition part and the contour data acquired by
the third acquisition part with each other to obtain a second superimposed data for each of the plurality of layout candidate
data;

an area calculation part configured to calculate an overlap area between a first pattern in the contour data acquired by the
first acquisition part and a second pattern in the contour data acquired by the second acquisition part, based on the first
superimposed data, for each of the plurality of layout candidate data;

a distance calculation part configured to calculate a proximity distance between a first pattern in the contour data acquired
by the first acquisition part and a third pattern in the contour data acquired by the third acquisition part, based on the
second superimposed data, for each of the plurality of layout candidate data;

a selection part configured to select proper layout data for the first layer from the plurality of layout candidate data,
based on an overlap area between the first pattern and the second pattern and a proximity distance between the first pattern
and the third pattern; and

forming a latent image on a photosensitive material on a substrate by using the selected proper layout data and illumination
light from a projection optical system.

US Pat. No. 9,831,125

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Toshiba Memory Corporatio...

1. A method for manufacturing a semiconductor device, comprising:
forming a stacked body above a substrate, the stacked body including a plurality of first layers and a plurality of second
layers, the first and second layers including a first layer and a second layer alternately stacked;

forming a slit extending in a stacking direction in the stacked body;
removing the first layers which are alternately stacked and exposed to the slit by etching through the slit to form an air
gap between the second layers, the air gap communicating with the slit;

forming a silicon film on an upper surface side of the air gap, a lower surface side of the air gap, and a side surface side
of the air gap, the side surface side being different from the slit side, while leaving part of the air gap between the silicon
film formed on the upper surface side of the air gap and the silicon film formed on the lower surface side of the air gap;

after the forming the silicon film, forming a metal film on a side surface of the slit;
forming a plurality of metal silicide layers between the second layers by causing reaction between the metal film and the
silicon film; and

removing unreacted part of the metal film formed on the side surface of the slit.

US Pat. No. 9,824,736

MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A memory device comprising:
a memory cell array including memory cells;
a generation circuit generating a reference current;
a sense amplifier comparing a cell current flowing through a memory cell with the reference current and sensing data stored
in the memory cell;

a first clamp transistor connected between a first input terminal of the sense amplifier and the memory cell;
a second clamp transistor connected between a second input terminal of the sense amplifier and the generation circuit;
a first interconnect layer connected to a gate of the first clamp transistor and extending in a first direction;
a second interconnect layer connected to a gate of the second clamp transistor, extending in the first direction, and arranged
adjacent to the first interconnect layer; and

a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer and extending
in the first direction, a fixed voltage being applied to the first shield line,

wherein a first interval between the first interconnect layer and the second interconnect layer is narrower than a second
interval between the one of the first interconnect layer and the second interconnect layer and the first shield layer.

US Pat. No. 9,824,762

SEMICONDUCTOR MEMORY DEVICE

Toshiba Memory Corporatio...

1. A semiconductor memory device comprising:
a first block including a first memory string and a second memory string, the first memory string including a first memory
cell transistor and a first select transistor, the second memory string including a second memory cell transistor and a second
select transistor;

a first select gate line that is electrically connected to a gate of the first select transistor;
a second select gate line that is electrically connected to a gate of the second select transistor; and
a first bit line electrically connected to a first end of the first memory string and a first end of the second memory string,
wherein during writing of data to a first memory cell transistor in the first block,
a first voltage is applied to the first select gate line during a first time period,
a second voltage is applied to the second select gate line and a non-zero voltage is applied to the first bit line, during
a second time period, and

a third voltage lower than the second voltage is applied to the second select gate line and a zero voltage is applied to the
first bit line during a third time period that begins after the second time period.

US Pat. No. 9,824,764

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a memory cell array including a plurality of memory cells that are NAND-connected; and
a control circuit that executes a write sequence, the write sequence writing data to the memory cells,
the write sequence including a plurality of write stages, one of the write stages applying to the memory cells a plurality
of program pulses whose amplitudes increase by a certain increment, the write stages including 1st to Nth, where N is an integer
of 2 or more, write stages, and

an initial amplitude and the increment of the program pulse applied in the N?1th write stage being the same as an initial
amplitude and the increment of the program pulse applied in the Nth write stage, and

the number of the program pulses applied in the N?1th write stage being fewer than the number of the program pulses applied
in the Nth write stage.

US Pat. No. 9,825,184

NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

13. A non-volatile semiconductor memory device comprising:
a tunnel insulating film disposed on a semiconductor substrate;
a floating gate electrode disposed on the tunnel insulating film, and containing a metal element;
an inter-electrode insulating film disposed on the floating gate electrode; and
a control gate electrode disposed on the inter-electrode insulating film,
wherein the inter-electrode insulating film includes
a first layer insulating film disposed on a side closer to the floating gate electrode,
a second layer insulating film disposed on a side closer to the control gate electrode, and
an intermediate insulating film interposed between the first layer insulating film and the second layer insulating film,
wherein the first layer insulating film is arranged such that a part on a side closer to the intermediate insulating film
has a lattice constant closer to that of the intermediate insulating film as compared with a part on a side closer to the
floating gate electrode,

wherein a diffusion constant of the metal element in a part of the first layer insulating film closer to the intermediate
insulating film is smaller than a diffusion constant of the metal element in a part of the first layer insulating film closer
to the floating gate electrode,

wherein the first layer insulating film and the second layer insulating film respectively have dielectric constants higher
than that of the intermediate insulating film,

wherein the floating gate electrode includes
a first layer film disposed on a side closer to the tunnel insulating film,
a second layer film disposed on a side closer to the inter-electrode insulating film, and containing the metal element, and
an intermediate film interposed between the first layer film and the second layer film, and
wherein the second layer film has a larger potential depth with respect to a charge accumulated in the floating gate electrode,
as compared with the first layer film, and

a diffusion constant of the metal element in the intermediate film is smaller than a diffusion constant of the metal element
in the first layer film.

US Pat. No. 9,817,777

MULTI-OPERATING STATE SERIAL ATA DEVICES AND METHODS OF OPERATION THEREFOR

Toshiba Memory Corporatio...

1. A Serial Advanced Technology Attachment (SATA) device for communicating with a host, the host sending commands to the SATA
device and the SATA device sending data to the host in response to the commands being received by the SATA device, the SATA
device having a queue of commands received from the host, wherein only one of either the commands from the host and the data
from the SATA device is sent at a time, the SATA device comprising:
a first operating state wherein the commands are received by the SATA device and the data are not sent to the host; and
a second operating state wherein the commands are received by the SATA device and the data are sent to the host, wherein data
being sent by the SATA device to the host has priority over commands being received by the SATA device from the host,

wherein, during the first operating state, the SATA device is configured to determine an occurrence of one or more conditions
at which to transition from the first operating state to the second operating state, wherein at least one condition of the
one or more conditions is based on if any commands are received by the SATA device.

US Pat. No. 9,818,467

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device comprising:
a first bit line extending in a first direction;
a first source line extending in the first direction;
a first word line extending in a second direction crossing the first direction;
a first control line extending in the second direction;
a first memory cell comprising a first variable resistance element and a first transistor, the first transistor including
a gate coupled to the first word line, the first memory cell including one end coupled to the first bit line and another end
coupled to the first source line;

a second transistor including one end coupled to the first bit line; and
a third transistor including a gate coupled to the first control line, one end coupled to the first bit line, and another
end coupled to the first source line.

US Pat. No. 9,811,410

DATA TRANSFER DEVICE, DATA TRANSFER METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM

TOSHIBA MEMORY CORPORATIO...

1. A data transfer device that communicates with a communication device via a network, comprising:
circuitry configured to implement:
a storage controller to control reading data from and writing data to a plurality of storages;
a correspondence information manager to manage correspondence information between data written by the storage controller and
a storage to which the data is written;

a storage manager to manage an invalid storage, the invalid storage being a storage that the storage controller failed to
read or write data;

a communicator to receive a data storage request message to store data;
a response message generator to generate a response message that contains the data requested by the data storage request message
to be stored, the response message being generated in response to receiving the data storage request message to store the
data, wherein the storage controller writes the response message containing the data to a storage in response to receiving
the data storage request message, and the correspondence information manager manages correspondence information between the
response message and the storage to which the response message is written, and wherein the response message containing the
data is generated and stored for output responsive to a subsequent acquisition request message to retrieve the data contained
in the response message;

a specifier to specify the storage storing the response message containing the data in response to the subsequent acquisition
request message according to the correspondence information between the response message and the storage to which the response
message is written, the subsequent acquisition request message for the data contained in the response message being received
by the communicator from the communication device; and

a reader to request the storage controller to read the response message containing the data from the storage specified by
the specifier when the storage is not the invalid storage, and not to request the storage controller to read the response
message containing the data when the storage is the invalid storage.

US Pat. No. 9,812,507

SEMICONDUCTOR MEMORY DEVICE

TOSHIBA MEMORY CORPORATIO...

1. A semiconductor memory device, comprising:
a semiconductor substrate which extends in first and second directions that intersect each other;
a plurality of first wiring lines which are arranged in a third direction that intersects the first direction and the second
direction, and which extend in the first direction;

a plurality of second wiring lines which are arranged in the first direction and extend in the third direction; and
a plurality of memory cells disposed at intersections of the first wiring lines and the second wiring lines,
one of the memory cells including a first film and a second film whose permittivity is different from that of the first film
which are stacked in the second direction between one of the first wiring lines and one of the second wiring lines,

the second films of two of the memory cells adjacent in the third direction being separated between the two memory cells,
and

the second films of two of the memory cells adjacent in the first direction being separated between the two memory cells.

US Pat. No. 9,754,672

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE WHICH PERFORMS IMPROVED ERASE OPERATION

TOSHIBA MEMORY CORPORATIO...

1. A method of controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of
blocks, each of the blocks including a plurality of memory cells, the method comprising:
performing an erase operation to a selected block, the erase operation including a first phase, a second phase, a third phase,
a fourth phase, a fifth phase, and a sixth phase;

performing a first operation supplying a first erase voltage to the selected block and performing a first verify operation
supplying a first verify voltage to the selected block, in the first phase;

performing a second operation supplying a second erase voltage to the selected block and performing a second verify operation
supplying a second verify voltage to the selected block, in the second phase after the first phase, the second erase voltage
being higher than the first erase voltage;

performing a third operation supplying a third erase voltage to the selected block, in the third phase after the second phase
and interrupting the erase operation when receiving a first command for interrupting the erase operation during the third
operation, the third erase voltage being higher than the second erase voltage;

performing a third verify operation supplying a third verify voltage to the selected block when receiving a second command
for resuming the erase operation after the third phase, in the fourth phase after the third phase;

performing a fourth operation supplying a fourth erase voltage to the selected block and performing a fourth verify operation
supplying a fourth verify voltage to the selected block, in the fifth phase after the fourth phase; and

performing a fifth operation supplying a fifth erase voltage to the selected block and performing a fifth verify operation
supplying a fifth verify voltage to the selected block, in the sixth phase after the fifth phase, the fourth erase voltage
and the fifth erase voltage being equal to or higher than the third erase voltage.

US Pat. No. 9,847,135

MEMORY DEVICE AND METHOD OF READING DATA

TOSHIBA MEMORY CORPORATIO...

1. A memory device, comprising:
a memory cell array in which data is written per page unit and data is erased per block, the block being a multiple of the
page unit of a natural number of two or more, and comprising memory strings,

each of the memory strings comprising memory cells configured to store data of one or more bits with a plurality of threshold
voltages, the plurality of threshold voltages being a threshold voltage indicative of an erase state in which data is erased
and one or more threshold voltages that are higher than the voltage indicative of the erase state and indicate written states
in which data is written; and

a controller configured to:
select one of adjustment values of positive and negative values based on a combination of first read data read from a first
memory cell of the memory cells, second read data read from a third memory cell of the memory cells, and a read voltage,

read data from a second memory cell of the memory cells using the selected adjustment value and the read voltage,
select a first adjustment value as the adjustment value when the read voltage is a first voltage, and
select a second adjustment value as the adjustment value when the read voltage is a second voltage, wherein
the first voltage corresponds to a first threshold voltage of the plurality of threshold voltages,
the second voltage corresponds to a second threshold voltage of the plurality of threshold voltages and is different from
the first threshold voltage, and

the second adjustment value is different from the first adjustment value.

US Pat. No. 9,831,270

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Toshiba Memory Corporatio...

1. A nonvolatile semiconductor memory device, comprising:
a first connector extending in a first direction;
a first conductive layer electrically connected to the first connector, the first conductive layer including
a first planar region spreading to cross the first direction,
a first overlap region overlapping the first connector in the first direction and being continuous with the first planar region,
a first side surface region extending along the first planar region and being continuous with the first planar region and
the first overlap region, the first side surface region including a first side surface extension end portion and a first side
surface middle portion, the first side surface middle portion being positioned between the first side surface extension end
portion and the first overlap region, and

a first crossing side surface region extending along the first planar region and being continuous with the first planar region
and the first overlap region, the first crossing side surface region including a first crossing side surface extension end
portion and a first crossing side surface middle portion, the first crossing side surface middle portion being positioned
between the first crossing side surface extension end portion and the first overlap region,

wherein a distance between the first side surface extension end portion and the first crossing side surface extension end
portion is longer than a distance between the first side surface middle portion and the first crossing side surface middle
portion;

a second connector extending in the first direction;
a second conductive layer electrically connected to the second connector, the second conductive layer including
a second planar region spreading along the first planar region,
a second overlap region overlapping the second connector in the first direction and being continuous with the second planar
region, at least a portion of the second overlap region being disposed between the second connector and the first planar region,

a second side surface region continuous with the second planar region and the second overlap region and aligned with an extension
direction of the first side surface region, the second side surface region including a second side surface extension end portion
and a second side surface middle portion, the second side surface middle portion being positioned between the second side
surface extension end portion and the second overlap region, and

a second crossing side surface region continuous with the second planar region and the second overlap region and aligned with
an extension direction of the first crossing side surface region, the second crossing side surface region including a second
crossing side surface extension end portion and a second crossing side surface middle portion, the second crossing side surface
middle portion being positioned between the second crossing side surface extension end portion and the second overlap region,

wherein a distance between the second side surface extension end portion and the second crossing sloe surface extension end
portion is longer than a distance between the second side surface middle portion and the second crossing side surface middle
portion;

a first insulating region provided between the first conductive layer and the second conductive layer; and
a memory portion connected to the first planar region and the second planar region.