US Pat. No. 9,056,767

DYNAMIC ACCESS POINT BASED POSITIONING

TEXAS INSTRUMENTS INCORPO...

1. A wireless device, comprising:
an access point (AP) scanner configured to scan wireless network channels utilized by one or more APs to transmit data packets,
probe responses, and beacons;

a transceiver configured to transmit one or more probe requests to the one or more APs and receive one or more probe responses
and beacons from the one or more APs; and

a controller coupled to the AP scanner and transceiver configured to:
determine a proximate geographic position of the wireless device based on a signal strength of the one or more probe responses
and beacons received from the one or more APs;

determine a ratio of probe responses received from the one or more APs to probe requests transmitted to the one or more APs;
and

cause the transceiver to lower the frequency of probe requests based on the ratio being higher than a preset threshold value
and raise the frequency of probe requests based on the ratio being lower than a preset threshold value,

wherein the controller dynamically adapts a parameter utilized in determining the proximate geographic position of the wireless
device.

US Pat. No. 9,197,898

SIGNALING SIGNED BAND OFFSET VALUES FOR SAMPLE ADAPTIVE OFFSET (SAO) FILTERING IN VIDEO CODING

TEXAS INSTRUMENTS INCORPO...

1. A method for sample adaptive offset (SAO) filtering in a video decoder, the method comprising:
receiving an entropy encoded bit stream;
decoding the entropy encoded bit stream;
extracting from the decoded bit stream SAO band parameters for a first non-overlapping region wherein the SAO band parameters
comprises a sequence of values of magnitudes of SAO band offsets without sign followed by signs of only the non-zero values
of magnitudes of the SAO band offset values in the decoded bit stream; and

performing SAO filtering of the first non-overlapping region using the extracted SAO band parameters.

US Pat. No. 9,450,487

DC TO DC CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A DC to DC converter comprising:
an input terminal for receiving an input DC voltage;
an output terminal for supplying an output DC voltage;
a first inductor terminal and a second inductor terminal, the first inductor terminal coupled to the input terminal, and the
second inductor terminal coupled to the output terminal;

a first switch operative to control an inductor current flowing from the second inductor terminal to the output terminal;
a current sensor for measuring the inductor current and generating an inductor current signal;
a slope generator for generating a slope compensation signal;
a first mixer having an output, the first mixer for adding the slope compensation signal to the inductor current signal;
a sample and hold circuit for sampling a portion of the slope compensation signal; and
a second mixer having an output, the second mixer for subtracting the sampled portion of the slope compensation signal from
the output of the first mixer, the first switch at least partially controlled in response to the output of the second mixer.

US Pat. No. 9,075,477

TOUCH PANEL APPARATUS AND METHODS

TEXAS INSTRUMENTS INCORPO...

1. An apparatus for improving touch panel accuracy, comprising:
a calibration sampling controller to command an X-Y coordinate positioning apparatus to position a touch-emulating stylus
at a known X-Y coordinate position relative to a touch panel and to depress the stylus;

a touch sampling module communicatively coupled to the calibration sampling controller to receive, sample and store a plurality
of calibration sample values, each calibration sample value corresponding to a signal amplitude associated with a touch panel
node, each node corresponding to an X-Y coordinate position associated with a touch panel row/column cross point, the signal
amplitude corresponding to a physical proximity of a node to the X-Y coordinate position of the depressed stylus; and

a touch panel characteristic modeler communicatively coupled to the calibration sampling controller to receive the plurality
of node calibration sample values and to generate a characteristic model of the plurality of node calibration sample values
as a function of a path of the touch-emulating stylus across the touch panel,

a peak detection module communicatively coupled to the run-time buffer to compare the plurality of sample values and to retain
a selected number of the largest-signal sample values; and

a sample sorting module communicatively coupled to the peak detection module to order the largest-signal X-Y node sample values
according to magnitude.

US Pat. No. 9,408,302

HIGH VOLTAGE POLYMER DIELECTRIC CAPACITOR ISOLATION DEVICE

TEXAS INSTRUMENTS INCORPO...

1. An isolation device, comprising:
a pre-metal dielectric (PMD) layer disposed over a substrate;
a first metal level disposed over the PMD layer;
a dielectric layer disposed over the first metal layer;
a second metal level disposed over the dielectric layer;
a polymer dielectric layer disposed over the second metal level, the polymer dielectric layer comprising primarily a layer
of polymer selected from the group consisting of polyimide and poly(p-phenylene-2,6-benzobisoxazole) (PBO), said polymer being
at least 20 microns thick;

a third metal level disposed over said polymer dielectric layer, said third metal level extending into upper via holes in
said polymer dielectric layer to form upper vias which make electrical connections to said second metal level;

bondpads disposed over said third metal level; and
a dielectric overcoat dielectric layer disposed over said third metal level, said dielectric overcoat dielectric layer exposing
said bondpads;

said isolation device containing a plurality of isolation components selected from the group consisting of a capacitor and
a transformer, said isolation components being formed in at least said second metal level and said third metal level.

US Pat. No. 9,230,852

INTEGRATED CIRCUIT (IC) HAVING ELECTRICALLY CONDUCTIVE CORROSION PROTECTING CAP OVER BOND PADS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) die, comprising:
a substrate having a top side surface providing circuitry including active circuitry configured to provide a function, having
at least one bond pad comprising a bond pad metal coupled to a node in said circuitry, and a dielectric passivation layer
over said top side surface providing a contact area which exposes said bond pad, and

a metal capping layer and having a first portion over at least said contact area in electrical contact with said bond pad
metal and a second portion over the dielectric passivation layer not in electrical contact with any bond pad metal.

US Pat. No. 9,496,024

AUTOMATIC LATCH-UP PREVENTION IN SRAM

TEXAS INSTRUMENTS INCORPO...

1. A system on a chip (SOC), comprising:
a processor; and
a memory system coupled to the processor, the memory system including a static random access memory (SRAM) bank and a memory
controller, the SRAM bank including a first switch coupled to a SRAM array power supply and a source of a transistor of an
SRAM storage cell in an SRAM array and a second switch coupled to a NWELL power supply and a bulk of the transistor of the
SRAM storage cell;

wherein the second switch is configured to close prior to the first switch closing during power up of the SRAM array.

US Pat. No. 9,468,107

INTERDIGITATED CHIP CAPACITOR ASSEMBLY

TEXAS INSTRUMENTS INCORPO...

1. A method of creating an interdigitated chip capacitor (“IDC”) assembly comprising:
forming at least one vertically extending nonconductive abutment surface between adjacent ones of the contact pads, each contact
pad having a top;

forming on the substrate top portion a plurality of grooves projecting outwardly from a central recess;
urging at least one sidewall portion of the IDC into abutting engagement with the at least one abutment surface on a substrate;
providing a plurality of solder paste strips on the top of the contact pads; and
forming a plurality of solder bead strips from the plurality of solder paste strips.

US Pat. No. 9,449,137

BUFFERED CONDUITS FOR HIGH THROUGHPUT CHANNEL IMPLEMENTATION, CROSSTALK DE-SENSITIZATION AND LATE TIMING FIXES ON SKEW SENSITIVE BUSES

TEXAS INSTRUMENTS INCORPO...

1. A method of manufacturing a system on a chip comprising the steps of:
selecting a set of pre-designed modules for the system on a chip;
placing said selected modules on a semiconductor; and
connecting said set of pre-designed modules via a plurality of buses formed according to a set of design rules specifying
tracks having a minimum size of conductors and a minimum spacing between conductors, said connecting including

routing each bus on a preferred direction,
placing minimum size conductors of a first set of alternating conductors of each bus at twice the minimum spacing within corresponding
first tracks of a selected metal layer of the semiconductor,

placing minimum size conductors of a second set of alternating conductors of each bus at twice the minimum spacing within
corresponding second tracks of a metal layer different than said selected metal layer,

connecting the alternating track conductors to corresponding conductors in said selected metal layer by vias.

US Pat. No. 9,391,635

BLOCK SCANNER AND RUN-LEVEL ENCODER FROM AC TO DC VALUES

Texas Instruments Incorpo...

1. A block encode circuit for use with information from multiple coding tables corresponding to different respective values
of Level, comprising:
a scanner operable to scan a block having data values spaced apart in the block by run-lengths to produce a succession of
pairs of values of Level and Run representing each data value and run-length, and in which the Level values include one or
more AC values succeeded by a DC value in the succession; and

a Run-Level encoder responsive to said scanner to encode the values of Level and Run in a same AC to DC order as in the succession
of pairs of values from the scanner to deliver an encoded output, the Run-Level encoder including a memory space for only
a single such coding table of the multiple coding tables at a time in response to a current Level to be encoded, and further
including a symbol encoder to encode the succession of pairs of values, the symbol encoder coupled to directly access only
the memory space to obtain coding table information, so that coding table memory space is reduced.

US Pat. No. 9,179,492

ELECTRONIC DEVICE, METHOD AND SYSTEM FOR HALF DUPLEX DATA TRANSMISSION

Texas Instruments Deutsch...

1. An electronic device for half-duplex near field transmission of radio signals comprising:
a first coil, a second coil and a third coil, being arranged as a three-dimensional antenna each of the coils operating independently
of the other;

a first capacitor, a second capacitor and a third capacitor coupleable in parallel to the first coil, the second coil and
the third coil, respectively, for selectively forming a first, a second and a third parallel-resonant circuit for transmitting
and receiving radio signals;

first, second, third series-resonant circuits for transmitting near field radio signals formed by fourth, fifth and sixth
capacitors in series with the first, second and third coils, respectively; and

a control stage configured to either use one of the first, second or third parallel-resonant circuits for receiving radio
signals and for charging a capacitor to power the electronic device and utilizing a corresponding one of the first, second,
third series-resonant circuits for transmitting near field signals.

US Pat. No. 9,455,720

UNIVERSAL OSCILLATOR

TEXAS INSTRUMENTS INCORPO...

1. An oscillator comprising:
an amplifier array comprising one or more amplifiers;
a control logic unit coupled to the amplifier array and configured to activate the one or more amplifiers;
a self-clock generating circuit coupled to the control logic unit and configured to generate a fixed clock; and
a counter configured to receive the fixed clock from the self-clock generating circuit and configured to provide a controlled
clock to the control logic unit;

wherein the control logic unit is configured to provide an enable signal to the self-clock generating circuit, wherein the
enable signal is configured to activate the self-clock generating circuit;

wherein the self-clock generating circuit is configured to provide the fixed clock to the counter after being activated; and
wherein the counter is configured to provide the controlled clock to the control logic unit after receiving the fixed clock.

US Pat. No. 9,287,875

LOAD SWITCH FOR CONTROLLING ELECTRICAL COUPLING BETWEEN POWER SUPPLY AND LOAD

TEXAS INSTRUMENTS INCORPO...

1. A load switch comprising:
a pass element comprising a first node and a second node, the pass element configured to be coupled to a power supply and
a load, and the pass element further configured to electrically couple the power supply with the load during an ON-state of
the pass element and electrically decouple the power supply from the load during an OFF-state of the pass element, the first
node positioned to be coupled to the power supply and the second node positioned to be coupled to the load;

a level-shift circuit comprising a first transistor and a pull-up resistor, the first transistor comprising a first terminal,
a second terminal and a third terminal, the pull-up resistor coupled between the first node and the first terminal, the first
transistor and the pull-up resistor configured to generate a level-shifted signal at the first terminal in response to an
enable signal at the third terminal, and to enable the ON-state and the OFF-state of the pass element based on the level-shifted
signal; and

a low-resistance active path coupled in parallel with the pull-up resistor for shunting the pull-up resistor in the OFF-state
by providing a path for a leakage current of the first transistor in the OFF-state.

US Pat. No. 9,224,854

TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:
a substrate comprising a semiconductor having a first conductivity type; and
a vertical drain extended metal oxide semiconductor (MOS) transistor, including:
a plurality of deep trench structures disposed in said substrate, at least one micron deep, having a dielectric liner abutting
said substrate;

a vertically oriented drift region having a second conductivity type opposite from said first conductivity type, disposed
in said substrate, abutting and being bounded on at least two opposite sides by said deep trench structures;

at least one trench gate on a gate dielectric layer disposed in a gate trench in said substrate over said vertically oriented
drift region between two adjacent deep trench structures of said plurality of deep trench structures; and

a body region having said first conductivity type disposed over said vertically oriented drift region and contacting said
gate dielectric layer.

US Pat. No. 9,148,166

ADDING PREDEFINED OFFSET TO COARSE ADC RESIDUE OUTPUT TO SAR

TEXAS INSTRUMENTS INCORPO...

1. A successive approximation register analog to digital converter (SAR ADC), configured to receive an input voltage and a
set of reference voltages, comprising:
a charge sharing DAC comprising an array of MSB (most significant bit) capacitors and an array of LSB (least significant bit)
capacitors;

a zero crossing detector coupled to the charge sharing DAC, the zero crossing detector configured to generate a digital output;
a coarse ADC (analog to digital converter) configured to receive the input voltage and configured to generate a coarse output,
wherein a predefined offset is added to a residue of the coarse ADC; and

a successive approximation register (SAR) state machine, coupled to the coarse ADC and the zero crossing detector and, configured
to generate a plurality of control signals, wherein the plurality of control signals is configured to operate the charge sharing
DAC in a sampling mode, an error-correction mode and a conversion mode.

US Pat. No. 9,374,112

CAPTURE SELECTION FOR DIGITAL PRE-DISTORTION ADAPTATION AND CAPTURE CONCATENATION FOR FREQUENCY HOPPING PRE-DISTORTION ADAPTATION

TEXAS INSTRUMENTS INCORPO...

1. A method of training a digital pre-distortion component comprising:
capturing, via a first capturing component, a first sample set of received data;
generating, via a first generating component, a first change matrix associated with a portion of the first sample set of received
data;

storing, into a first memory component, the first change matrix;
capturing, via a second capturing component, a second sample set of received data;
generating, via a second generating component, a second change matrix associated with a portion of the second sample set of
received data;

storing, into a second memory component, the second change matrix;
capturing, via a third capturing component, a third sample set of received data;
generating, via a third generating component, a third change matrix associated with a portion of the third sample set of received
data;

comparing, via a comparing component, the third change matrix with the first change matrix to obtain a first comparison;
comparing, via the comparing component, the third change matrix with the second change matrix to obtain a second comparison;
and

adapting, via an adapting component, a digital pre-distortion component with the third sample set of data based on one of
the first comparison and the second comparison.

US Pat. No. 9,091,736

SYSTEMS AND METHODS OF BATTERY CELL ANOMALY DETECTION

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:
a plurality of voltage to current (V-to-I) converters each being couplable to one of a respective plurality of cells;
a cell detector circuit coupled to each of the plurality of V-to-I converters to receive a current generated by its respective
V-to-I converter, wherein the cell detector circuit compares each of the respective plurality of cells with other cells in
the plurality of cells by determining a maximum current input to the converters and which cell provides that maximum current
to determine if any of the plurality of V-to-I converters provides an anomalous input current and determines which of the
plurality of V-to-I converters provides the anomalous input current whereby relative performance between the cells is determined,
wherein the cell detector circuit further comprises a plurality of multi-input current detectors, wherein each of the plurality
of multi-input current detectors is coupled to each of the plurality of V-to-I converters, and wherein each multi-input current
detector compares at least one of the V-to-I converter outputs to a threshold value to determine an anomalous current; and
wherein each multi-input detector outputs a logic signal for each of the inputs, each output of the multi-input current detector
is coupled to the input of an OR gate.

US Pat. No. 9,357,222

VIDEO DEVICE FINISHING ENCODING WITHIN THE DESIRED LENGTH OF TIME

Texas Instruments Incorpo...

1. A video encoding device comprising:
(A) processor circuitry having a video input receiving frames of video data, a video output, a monitor input, and a control
output controlling precision levels of a scalable motion estimation encoding algorithm;

(B) memory circuitry having an input coupled to the video output and having an output, the memory circuitry storing the frames
of video data;

(C) compression circuitry having a video input coupled to the output of the memory circuitry, a video output coupled to the
monitor input, and a control input coupled to the control output, the compression circuitry performing motion estimation with
a precision level and finishing encoding on each frame of video data in accordance with the scalable motion estimation encoding
algorithm and in response to a precision level output on the control output;

(D) for a certain frame of video data, the compression circuitry performing the motion estimation encoding algorithm with
a precision level and finishing encoding on that certain frame of video data in other than a desired length of time; and

(E) for a frame of video data subsequent to the certain frame of video data, the processor circuitry monitoring the video
output and changing the precision level of the motion estimation encoding algorithm to maintain the performing motion estimation
and finishing encoding within the desired length of time.

US Pat. No. 9,329,615

TRIMMED THERMAL SENSING

TEXAS INSTRUMENTS INCORPO...

1. A trimmed thermal sensing system comprising:
a temperature sensing circuit configured to provide an output that varies as a function of temperature and in response to
a bandgap reference signal generated by a bandgap reference circuit that is trimmed by a first amount to compensate for Vbe
variation; and

a trim network linked to the trimmed bandgap reference and configured to always trim the temperature sensing circuit dependent
on the bandgap trimming and by a an amount substantially equal to the first amount but in an opposite direction of trimming
implemented to provide the trimmed bandgap reference signal, whereby temperature calibration of the temperature sensing circuit
is automatically provided.

US Pat. No. 9,510,391

NETWORK CONFIGURATION FOR DEVICES WITH CONSTRAINED RESOURCES

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:
receiving a wireless beacon from a local configuration device over an ad hoc network at a wireless device, wherein the wireless
beacon includes a data structure that encodes at least a portion of a wireless identifier of an access point;

configuring the wireless device for communication with the access point according to the at least the portion of the wireless
identifier of the access point;

establishing a connection between the wireless device and the access point utilizing a wireless network established based
on the at least a portion of the wireless identifier;

receiving another wireless beacon at the wireless device, wherein the other wireless beacon comprises a next-time data structure,
wherein the next-time data structure comprises updated security information; and

reconfiguring the already configured wireless device for communication with the access point according to the updated security
information.

US Pat. No. 9,362,939

REDUCTION OF INPUT DEPENDENT CAPACITOR DAC SWITCHING CURRENT IN FLASH-SAR ANALOG-TO-DIGITAL CONVERTERS

TEXAS INSTRUMENTS INCORPO...

1. An analog-to-digital converter (ADC) for converting an analog input signal into N-bits of digital output code, the ADC
comprising:
an M-bit flash ADC configured to receive a sampled analog signal and to output a digital signal comprising most significant
M-bits of the N-bits of digital output code in a flash conversion phase, the sampled analog signal being a stored signal of
the analog input signal, M and N being integers; and

an N-bit successive approximation register (SAR) ADC comprising:
a capacitor digital-to-analog converter (DAC) comprising a first set of capacitors and a second set of capacitors, each of
the first set of capacitors and the second set of capacitors being weighted capacitors such that the capacitors of the first
set of capacitors all have respectively different capacitance values and the capacitors of the second set of capacitors all
have respectively different capacitance values, first ends of each capacitor of the first set of capacitors and the second
set of capacitors coupled to a common terminal; and

a digital engine coupled to the M-bit flash ADC and the capacitor DAC for providing the N-bits of digital output code in a
SAR conversion phase based on the digital signal and a voltage (Vcom) at the common terminal, the digital engine configured
to:

in the flash conversion phase, generate the most significant M-bits of the N-bits of digital output code based on the digital
signal received from the M-bit flash ADC, connect second ends of the first set of capacitors to a reference signal (Vref),
and connect second ends of the second set of capacitors to a ground reference signal (Vgnd);

in a first cycle of the SAR conversion phase, connect second ends of one or more capacitors of the first set of capacitors
to the Vgnd if a voltage level corresponding to the digital signal is less than Vref/2, and connect second ends of one or
more capacitors of the second set of capacitors to the Vref if the voltage level corresponding to the digital signal is greater
than Vref/2 so as to generate the voltage level corresponding to the digital signal as the Vcom; and

in subsequent cycles of the first cycle of the SAR conversion phase, control voltage levels at the second ends of the second
set of capacitors to perform successive approximation of least significant N-M bits of the N-bits of digital output code based
on a SAR conversion algorithm.

US Pat. No. 9,357,564

SIGNALING OF RANDOM ACCESS PREAMBLE PARAMETERS IN WIRELESS NETWORKS

TEXAS INSTRUMENTS INCORPO...

1. A method for transmitting from user equipment (UE) to base stations (nodeB) in a cellular network, comprising:
maintaining a fixed set of preamble parameter configurations for use across a complete range of cell sizes within the cellular
network;

receiving at a UE located in a cell a configuration number transmitted from a nodeB serving the cell;
selecting a preamble parameter configuration specified by the received configuration number from the fixed set of preamble
parameter configurations; and

transmitting a preamble from the UE to the nodeB using the preamble parameter configuration indicated by the configuration
number.

US Pat. No. 9,397,085

BI-DIRECTIONAL ESD PROTECTION DEVICE

TEXAS INSTRUMENTS INCORPO...

17. An integrated circuit with a bidirectional ESD bipolar transistor comprising:
an isolated well with a first dopant type forming a base diffusion;
an emitter diffusion with a second dopant type in the isolated well wherein the emitter diffusion forms a first pn junction
on a first lateral side of the base diffusion;

a collector diffusion with the second dopant type in the isolated well wherein the collector diffusion forms a second pn junction
on a second lateral side of the base diffusion and wherein the emitter diffusion and the collector diffusion are identical,
wherein the base diffusion laterally separates the collector diffusion from the emitter diffusion;

silicide blocked from the base diffusion;
silicide blocked from the first pn junction, and from the second pn junction;
silicide blocked from equal top surface portions of the emitter and the collector diffusions;
the emitter diffusion coupled to Vss; and
the collector diffusion coupled to an input pin.

US Pat. No. 9,106,533

SOURCE AND DIVERSITY RATE EQUAL TO A FIRST TRANSMISSION RATE

TEXAS INSTRUMENTS INCORPO...

1. A process of sending packets on a network, comprising:
A. sending source packets of real-time, voice information from a sender to a receiver on the network at a first source rate
that is equal to a first transmission rate;

B. receiving at the sender packet loss information based on a loss of source packets at the receiver;
C. comparing in the sender the packet loss information with a threshold number; and
D. when the packet loss information is greater than the threshold number, sending the source packets at a second source rate
and sending at least one of time and path diversity of the real-time, voice information at a first diversity rate, the sum
of the second source rate and the first diversity rate being equal to the first transmission rate.

US Pat. No. 9,468,065

COMBINED HYBRID AND LOCAL DIMMING CONTROL OF LIGHT EMITTING DIODES

TEXAS INSTRUMENTS INCORPO...

1. A method comprising:
performing global hybrid dimming control of a plurality of strings of backlight light emitting diodes making up a backlight
system as a hybrid of digital modulation dimming and current dimming, comprising:

performing hybrid digital modulation dimming to control brightness up to a specified maximum digital modulation setting; and
performing hybrid current dimming control, with hybrid digital modulation fixed at the maximum digital modulation setting,
to adjust a string current for each of the strings of backlight light emitting diodes; and

performing local dimming control of one or more of the strings of backlight light emitting diodes by introducing a local digital
modulation signal into a hybrid digital modulation control path for each of the one or more strings of backlight light emitting
diodes, correspondingly changing digital modulation for the string to be a combination of hybrid digital modulation and local
digital modulation.

US Pat. No. 9,147,013

WIRELESS SENSOR WITH FRAM

TEXAS INSTRUMENTS INCORPO...

1. A method for operating a wireless sensor module, the method comprising:
collecting sensor data in a periodic manner with a first time period;
logging the sensor data in a non-volatile ferroelectric random access memory (FRAM) within the sensor module;
placing the sensor module in a reduced power idle mode between sensor data collection periods, wherein the logged sensor data
is preserved by the FRAM during the idle mode; and

transmitting a representation of the logged sensor data over a radio channel to a remote receiver in a periodic manner with
a second time period, wherein the second time period is longer than the first time period;

aggregating the logged sensor data during the second time period to form the representation of the logged sensor data, wherein
aggregating comprises processing the logged sensor data in the FRAM by using the FRAM as a scratchpad memory during the processing;

wherein aggregating the logged sensor data further comprises using a hash table stored in the FRAM to perform duplicate packet
suppression.

US Pat. No. 9,432,654

MODIFYING FUSION OFFSET DATA IN SEQUENTIAL STEREOSCOPIC IMAGE FRAMES

Texas Instruments Incorpo...

1. A process of operating a stereoscopic correcting device comprising:
(a) receiving in a memory stereoscopic data in the form of a series of stereoscopic image frames with each frame including
a left image and a right image and with each frame including convergence data that includes plane of convergence data and
fusion offset data, the fusion offset data representing the distance between a plane of convergence and a display screen,
and the sequential frames having different planes of convergence;

(b) comparing the fusion offset data for a current frame, a first next sequential frame, and at least a second next sequential
frame; and

(c) modifying the fusion offset data of the first next sequential frame to reduce a difference between the planes of convergence
of the current frame and at least the second sequential frame.

US Pat. No. 9,629,294

PACKAGED DEVICE FOR DETECTING FACTORY ESD EVENTS

TEXAS INSTRUMENTS INCORPO...

1. An electrostatic discharge (ESD) monitor device, comprising:
an ESD bus comprising metal interconnects above a substrate of said ESD monitor device, said substrate comprising a semiconductor;
a plurality of input/output (I/O) sites; and
a plurality of monitor components disposed at each of said I/O sites, each of said monitor components comprising a scalable
physical structure which provides ESD robustness, each of said monitor components being electrically connected to said ESD
bus.

US Pat. No. 9,571,163

METHODS AND APPARATUS FOR DETERMINING NEARFIELD LOCALIZATION USING PHASE AND RSSI DIVERSITY

TEXAS INSTRUMENTS INCORPO...

1. A receiver comprising:
a received signal strength indication (RSSI) determiner to determine a first strength of an electric field and a second strength
of a magnetic field, the electric field and the magnetic field associated with an electromagnetic signal sent from a transmitter;

an RSSI difference determiner to determine a difference between the first strength and the second strength; and
a weight applier to determine a first estimated distance of the transmitter from the receiver based on the difference between
the first strength and the second strength;

a phase determiner to determine a first phase associated with the electric field and a second phase associated with the magnetic
field; and

a phase difference determiner to determine a difference between the first phase and the second phase, wherein the weight applier
is structured to determine a second estimated distance of the transmitter from the receiver based on the difference between
the first phase and the second phase;

wherein the weight applier is structured to determine a third estimated distance and a fourth estimated distance of the transmitter
from the receiver based on the first strength and the second strength respectively;

wherein the weight applier is structured to determine a set of weights based on the estimated distances, the set of weights
including a first weight corresponding to the first difference, a second weight corresponding to the second difference, a
third weight corresponding to the first strength, and a fourth weight corresponding to the second strength.

US Pat. No. 9,372,796

OPTIMUM CACHE ACCESS SCHEME FOR MULTI ENDPOINT ATOMIC ACCESS IN A MULTICORE SYSTEM

TEXAS INSTRUMENTS INCORPO...

1. A Multicore Shared Memory Controller (MSMC) comprising:
a plurality of slave interfaces, each operable for connection to a corresponding one of a plurality of central processing
units for receiving access requests;

a plurality of master interfaces operable for connection to an external memory interface (EMIF);
datapath module connected to each slave interface and to each master interface, said datapath module including an arbitration
unit operable to arbitrate access of a center processing unit to a memory by unifying all accesses to a particular master
interface before access requests are arbitrated.

US Pat. No. 9,369,042

MULTIPHASE DC-TO-DC SWITCHING POWER CONVERTER WITH LEADING EDGE AND CROSS CHANNEL BLANKING

TEXAS INSTRUMENTS INCORPO...

11. A power converter comprising:
a plurality of channels, each channel having:
a first MOS transistor;
a second MOS transistor connected to the first MOS transistor;
an inductor connected to the first and second MOS transistors;
a current sense circuit connected to the second MOS transistor, the current sense circuit to sense a current that flows through
the second MOS transistor, and output a current sense signal in response; and

a blanking circuit connected to the current sense circuit, the blanking circuit to receive the current sense signal; and
a controller connected to each channel, the controller to select a channel from the plurality of channels as a selected channel
and output:

a gate signal to the second MOS transistor in the selected channel to turn off the second MOS transistor in the selected channel;
a gate signal to the first MOS transistor in the selected channel to turn on the first MOS transistor in the selected channel;
and

a first cross blanking pulse to the blanking circuit in each non-selected channel of the plurality of channels, each blanking
circuit in a non-selected channel to blank the current sense signal in the non-selected channel in response to the first cross
blanking pulse for a first cross blanking period of time that begins before the second MOS transistor in the selected channel
turns off and ends after the first MOS transistor in the selected channel turns on.

US Pat. No. 9,300,361

ENABLING CO-EXISTENCE AMONG POWER LINE COMMUNICATION (PLC) TECHNOLOGIES

TEXAS INSTRUMENTS INCORPO...

1. A method comprising:
performing, by a power line communication (PLC) device,
detecting a co-existence preamble on a PLC network having at least one native PLC device and at least one foreign PLC device;
not receiving a native preamble;
terminating transmissions to the PLC network for a network-specific time period; and
resuming transmissions to the PLC network after expiration of the network-specific time period.

US Pat. No. 9,103,886

DELAY TESTING CAPTURING SECOND RESPONSE TO FIRST RESPONSE AS STIMULUS

TEXAS INSTRUMENTS INCORPO...

1. A process of delay testing logic circuitry, comprising:
A. enabling shifting of parallel connected, equal length subdivisions of a divided scan path;
B. shifting sequentially and separately respective portions of a test pattern of stimulus bits, originally produced for a
contiguous scan path, from a single lead through each of the parallel connected, equal length subdivisions of a divided scan
path;

C. applying the stimulus bits from each subdivision of the divided scan path to only a part of the logic circuitry connected
to that subdivision while shifting the stimulus bits, the applying causing the logic circuitry to produce binary state response
bits, and the shifting of stimulus bits through the subdivisions causing the response bits from the logic circuitry to change
binary states;

D. capturing simultaneously in all subdivisions of the scan path from all of the parts of the logic circuitry first response
bits occurring in response to a previous shift of stimulus bits in each subdivision;

E. capturing simultaneously in all subdivisions of the scan path from all of the parts of the logic circuitry second response
bits occurring in response to applying the first response bits as stimulus bits to the logic circuitry; and

F. separately and sequentially shifting the captured second response bits from the subdivisions to a single lead of the scan
path.

US Pat. No. 9,468,087

POWER MODULE WITH IMPROVED COOLING AND METHOD FOR MAKING

TEXAS INSTRUMENTS INCORPO...

1. A power module, comprising:
a first device die, including: a first side, a second side, and a switching device with a plurality of switch terminals;
a second device die including a first side, a second side, and at least one electrical circuit component;
an interconnect structure formed of a thermally and electrically conductive material, the interconnect structure including
a first side contacting at least a portion of the first side of the first device die, the first side of the interconnect structure
contacting at least a portion of the first side of the second device die, the first side of the interconnect structure forming
electrical contacts to at least one of the switch terminals of the switching device of the first device die and forming at
least one electrical contact to the electrical circuit component of the second device die;

a substrate structure formed of a thermally conductive material, the substrate structure including a first side contacting
at least a portion of a second side of the interconnect structure, and a second side, the substrate structure providing a
thermally conductive path to draw heat away from the first side of the first device die; and

a body structure formed of an electrically insulating material, the body structure extending around portions of the power
module, the body structure including:

a first opening exposing at least a portion of the second side of the substrate structure to provide an externally accessible
first exposed surface of the substrate structure along a top of the power module providing a thermally conductive path through
the substrate structure to draw heat away from the first side of the first device die, and

a second opening exposing at least a portion of the second side of the first device die to provide an externally accessible
second exposed surface of the first device die along a bottom of the power module providing a thermally conductive path to
draw heat away from the second side of the first device die.

US Pat. No. 9,372,665

METHOD AND APPARATUS FOR MULTIPLYING BINARY OPERANDS

TEXAS INSTRUMENTS INCORPO...

1. A method for multiplying a signed first operand na bits and a signed second operand nb bits, wherein na and nb are different
positive integer numbers, the method comprising:
generating single bit products of pairs of a single bit from the signed first operand and a single bit from the signed second
operand with a logical AND function implemented via corresponding AND gates to produce na times nb single bit products;

selectively inverting for the signed first operand and the signed second operands the single bit products of the first operand
bit na?1 multiplied with the second operand bits 0 to nb?2 implemented via corresponding XOR gates;

selectively inverting the single bit products of the signed first operand bits 0 to na?2 multiplied with the signed second
operand bit nb?1, implemented via corresponding XOR gates;

adding the single bit products in accordance with their respective order for producing an intermediate product after both
the steps of selectively inverting; and

adding a ‘1’ bit value at bit positions nb?1, na?1 and na+nb?1 for receiving a final product.

US Pat. No. 9,374,831

NETWORK COEXISTENCE THROUGH ACTIVE SUPERFRAME INTERLEAVING

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:
detecting, at a first body area network (BAN) device in a first body area network (BAN1), a second device in a second body area network (BAN2), the second BAN device transmitting and receiving signals on a selected channel during the second body area network's active
superframes;

wherein the superframe is operating in a beacon mode as a beacon period;
determining, at the first BAN device, whether the second BAN device supports coexistence of independent body area networks
through active superframe interleaving between body area networks on the selected channel;

sending an interleaving request from the first BAN device in the first body area network to the second BAN device in the second
body area network if the second BAN device supports coexistence through active superframe interleaving between body area networks;

receiving an interleaving response at the first device from the second BAN device, the response identifying one or more inactive
superframes of the second BAN device; and

adapting active superframes at the first BAN device to fit within the inactive superframes of the second BAN device.

US Pat. No. 9,223,545

MODIFIED FIXED-POINT ALGORITHM FOR IMPLEMENTING INFRARED SENSOR RADIATION EQUATION

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:
an integrated circuit chip; comprising:
a microcontroller; and
a memory coupled to the microcontroller, and storing program code that, when executed by the microcontroller, causes the microcontroller
to:

perform a plurality of addition operations, a plurality of subtraction operations, a plurality of multiplication operations,
a plurality of shift-left operations, and a plurality of shift-right operations, the plurality of addition, subtraction, multiplication,
shift-left and shift-right operations being configured so as to solve a particular group of equations,

solve the particular group of equations for a plurality of input numbers, each of the input numbers having a value within
a predetermined range associated with the respective input number, and

perform the shift-left and shift-right operations for the input numbers so as to automatically establish a resolution of each
of a plurality of one or more generated numbers that are generated by one or more of the addition, subtraction, multiplication,
shift-left and shift-right operations such that the respective generated number fits within a register of a predetermined
number of bits.

US Pat. No. 9,064,726

LOW-COST CMOS STRUCTURE WITH DUAL GATE DIELECTRICS AND METHOD OF FORMING THE CMOS STRUCTURE

TEXAS INSTRUMENTS INCORPO...

1. A method of forming a semiconductor structure comprising:
forming a first mask that exposes a first well and a first gate to a first implant, and protects a second well and a second
gate from the first implant, the first well and the second well being formed in a semiconductor substrate, a thin gate dielectric
touching and lying between the first well and the first gate, a thick gate dielectric touching and lying between the second
well and the second gate, the first and second wells including a first type of impurity atoms, being substantially free of
a second type of impurity atoms, and having substantially identical dopant profiles when the first mask is formed;

implanting the second type of impurity atoms through the first mask into the first well to form a first source extension region
and a first drain extension region that lies spaced apart from the first source extension region, the first well including
a first channel region that lies between the first source extension region and the first drain extension region, the first
channel region having a first middle point that lies mid-way between the first source extension region and the first drain
extension region, the first channel region at the first middle point including the first type of impurity atoms, being substantially
free of the second type of impurity atoms, and having an average dopant concentration; and

implanting the first type of impurity atoms through the first mask, the first gate, and the thin gate dielectric into the
first channel region to raise the average dopant concentration of the first channel region.

US Pat. No. 9,374,009

CIRCUITS AND METHODS FOR CONSTANT OUTPUT CURRENT IN A FLYBACK CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A flyback converter comprising:
a transformer having a primary side and a secondary side, wherein the primary side is connectable to a voltage source;
a first switch connected to the primary side of the transformer, the first switch controlling the current in the primary side
of the transformer;

a current sensor resistance connected between the first switch and a common node;
a comparator having a first input and a second, the first input being connected between the switch and the current sensor;
driver logic that controls the state of the first switch, wherein the output of the comparator is coupled to the driver logic;
a first voltage source being connected to the second input of the comparator;
an error amplifier that is coupled to the voltage at the inverting input of the comparator to an adjustment voltage, the output
of the error amplifier being coupled to the driver logic, wherein the adjustment voltage compensates for a propagation delay
time between the time the controller generates a control signal for the switch and the time in which current in the primary
side of the transformer ceases to flow, wherein output from the converter is regulated to achieve high current accuracy, wherein
an open loop adjustment voltage is generated by a circuit comprising:

a voltage source referenced to the common node;
a second switch connected between the voltage source and a node; and
a third switch connected between the node and the common node;
wherein the node is coupled to the error amplifier.

US Pat. No. 9,281,269

INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit (IC) package comprising:
a substrate having a top surface with an IC die mounting area and a peripheral area surrounding said mounting area;
a plurality of generally parallel conductor layers;
a plurality of plated through holes (PTHs) extending through said conductor layers in a direction transverse to said conductor
layers, said plurality of PTHs comprising a first portion of said plurality selectively positioned beneath said IC die mounting
area and filled with a filler material having a first filler coefficient of thermal expansion (CTE) and a second portion of
said plurality selectively positioned beneath said peripheral area and filled with a material having a second filler CTE different
than said first filler CTE; and

a die attached to said die mounting area.

US Pat. No. 9,402,248

METHOD FOR DETERMINING THE LOCATION OF CONTROL CHANNELS IN THE UPLINK OF COMMUNICATION SYSTEMS

TEXAS INSTRUMENTS INCORPO...

1. A method for a User Equipment (UE) to determine a resource for transmitting an acknowledgement signal to a Node B, said
acknowledgement signal being generated in response to receiving by said UE a scheduling assignment transmitted by said Node
B, the method comprising the steps of:
receiving a control channel from the Node B using a modulation and coding scheme (MCS) determined from CQI feedback for said
UE, wherein the Node B communicates a number of downlink (DL) and uplink (UL) scheduling assignments in each MCS region, of
a set of MCS regions, through a field that is separately transmitted prior to a remaining part of the control channel carrying
the DL and UL scheduling assignments;

determining a maximum number (M) of scheduling assignment resources that could be received prior to a target resource for
receiving said UE scheduling assignment;

applying a one-to-one mapping between scheduling assignment resources and resources for transmitting acknowledgement signal;
identifying the first mapped resource after said M resources as said target resource for transmitting said acknowledgement
signal; and

transmitting said acknowledgement signal.

US Pat. No. 9,184,784

METHOD AND APPARATUS FOR DIGITAL PREDISTORTION FOR A SWITCHED MODE POWER AMPLIFIER

TEXAS INSTRUMENTS INCORPO...

2. An apparatus comprising:
a digital predistortion block comprising:
a first processing unit configured to receive an input signal and predistort a baseband representation of the input signal
at a carrier frequency; and

second processing units configured to receive the input signal and predistort a baseband representation of the input signal
at one or more harmonic frequencies;

the digital predistortion block configured to generate an output signal based on the predistorted baseband representation
of the input signal and transmit the output signal to a power amplifier;

wherein the second processing units are configured to predistort based on an m-th power of the baseband representation of
the input signal and predistort based on an m-th power of a conjugate of the baseband representation of the input signal,
wherein m is a positive integer.

US Pat. No. 9,280,524

COMBINING A HANDWRITTEN MARKING WITH A RENDERED SYMBOL TO MODIFY THE RENDERED SYMBOL

TEXAS INSTRUMENTS INCORPO...

1. A method performed by at least one device for editing a rendering of symbols, the method comprising:
generating a first rendering of the symbols with typeset font;
causing a display device to display the first rendering;
from a user, receiving a selection of at least a portion of the symbols;
generating a second rendering of the selection with ink font;
causing the display device to display the second rendering;
from the user, receiving at least one handwritten edit to the second rendering, wherein the at least one handwritten edit
includes a handwritten marking on an ink font rendered symbol for combining with the ink font rendered symbol to modify the
ink font rendered symbol;

performing recognition of the handwritten edit, including recognition of how the handwritten marking combines with the ink
font rendered symbol to modify the ink font rendered symbol;

updating the selection to incorporate the recognized handwritten edit;
generating a third rendering of the updated selection with typeset font; and
causing the display device to display the third rendering for replacing at least a portion of the first rendering.

US Pat. No. 9,439,220

MULTIPLE NFC CARD APPLICATIONS IN MULTIPLE EXECUTION ENVIRONMENTS

TEXAS INSTRUMENTS INCORPO...

1. A method performed by a communications device for granting access to a plurality of near field communication execution
environments, the method comprising:
receiving periodic polling sessions, wherein each polling session includes one or more request commands to use a respective
one or more of a plurality of communication protocols;

granting access, in response to a request command during one of the polling sessions, to one type of the plurality of near
field communication execution environments assigned to the requested communication protocol; and

performing an arbitration in response to each polling session such that a same combination of communication protocol and execution
environment is not activated for adjacent polling sessions.

US Pat. No. 9,298,665

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

TEXAS INSTRUMENTS INCORPO...

1. A data processing system comprising:
a plurality of processing cores, at least one processing core including cache memory for temporarily storing data;
a plurality of memory endpoints storing data; and
a plurality of coherence controllers, one corresponding to each of said plurality of memory endpoints, each of said plurality
of coherence controllers includes

a coherence maintenance address queue having a plurality of entries, each entry storing an address of an access request committed
to a shared memory at said corresponding memory endpoint and an assigned ID tag,

an ID allocation block coupled to said coherence maintenance address queue assigning an available ID tag from a set of ID
tags to an access committed to the shared memory for storage in said coherence maintenance address queue and retiring a coherence
maintenance address queue entry upon receipt of a completion signal from the shared memory indicating completion of the corresponding
access, and

a comparator coupled to said plurality of processing cores and said coherence maintenance address queue and receiving an address
of a memory access request from said plurality of processing cores, said comparator comparing the address of the memory access
request with all addresses stored in said coherence maintenance address queue and generating a hazard stall signal if the
address of the memory access request matches any address stored in said coherence maintenance address queue.

US Pat. No. 9,412,437

SRAM WITH BUFFERED-READ BIT CELLS AND ITS TESTING

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a functional memory having an array of memory cells arranged in rows and columns and operable through row and column peripheral
circuitry for write and read operations, each memory cell having a latch portion and a buffer portion;

a first memory cell of the plurality of memory cells arranged to store a data signal in the latch portion in response to a
write signal and also to output the stored data signal to either the latch portion or the buffer portion in response to a
read signal, the latch portion coupled between a bit line and a complementary bit line of the first memory cell, the buffer
portion directly connected to a read word line and a storage node of the latch portion of the first memory cell; and

a selection circuit coupled to receive a mode control signal,
wherein the selection circuit is arranged to receive the data signal from only the buffer portion of the first memory cell
in response to a first state of the mode control signal, and

wherein the selection circuit is arranged to receive the data signal from only the latch portion of the first memory cell
in response to a second state of the mode control signal.

US Pat. No. 9,369,147

ADJUSTABLE AND BUFFERED REFERENCE FOR ADC RESOLUTION AND ACCURACY ENHANCEMENTS

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:
an analog to digital converter (ADC) core;
a reference voltage generator coupled to an input of the ADC core;
a bandgap reference coupled to the reference voltage generator; and
a window comparator configured to control a selected reference voltage range generated by the reference voltage generator
and received by the ADC core.

US Pat. No. 9,270,293

SYSTEM AND METHOD FOR MULTI CHANNEL SAMPLING SAR ADC

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:
a successive approximation register operable to generate first successive approximation instructions and second successive
approximation instructions;

a comparator operable to provide a compared output to said successive approximation register;
a digital to analog converter connected to said comparator and operable to receive the first successive approximation instructions
and to receive the second successive approximation instructions;

a reference voltage line operable to provide a reference voltage;
a first input line operable to provide a first analog input voltage;
a second input line operable to provide a second analog input voltage;
a conversion line connected to said digital to analog converter and to said comparator; and
a passive sample-and-hold component operable to receive the reference voltage from said reference voltage line, to sample
and hold the first analog input voltage from said first input line during a first time period, to sample and hold the second
analog input voltage from said second input line during the first time period, to output the sampled and held first analog
input voltage to said conversion line to said digital to analog converter at a second time period, and to output the sampled
and held second analog input voltage to said conversion line to said digital to analog converter at a third time period;

wherein said digital to analog converter and said comparator are operable to convert the sampled and held first analog input
voltage to a first digital representation during the second time period based on the first successive approximation instructions,

wherein said digital to analog converter and said comparator are further operable to convert the sampled and held second analog
input voltage to a second digital representation during the third time period based on the second successive approximation
instructions, and

wherein said passive sample-and-hold component and said digital to analog converter are operable to share a charge associated
with the first analog input voltage.

US Pat. No. 9,363,901

MAKING A PLURALITY OF INTEGRATED CIRCUIT PACKAGES

TEXAS INSTRUMENTS INCORPO...

1. A method of making a plurality of integrated circuit packages comprising:
providing a metal strip;
on the metal strip, forming a first leadframe having a first die pad having first and second lateral sides, a first plurality
of leads with proximal ends adjacent to the first die pad and free distal ends positioned outwardly from the first die pad
and a first laterally extending leadframe dam bar intersecting the proximal ends of the first plurality of leads; and

on the metal strip, forming a second leadframe having a second die pad having first and second lateral sides, a second plurality
of leads with proximal ends adjacent to the second die pad and free distal ends positioned outwardly from the second die pad
and a second laterally extending leadframe dam bar intersecting the proximal ends of the second plurality of leads, said free
distal ends of said second plurality of leads are positioned being aligned adjacent and non-touching relationship with corresponding
said free distal ends of said first plurality of leads.

US Pat. No. 9,281,304

TRANSISTOR ASSISTED ESD DIODE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a first nwell formed in a p-type substrate;
a first pwell formed in said p-type substrate where a doping of said first pwell is higher than a doping of said p-type substrate;
a gate dielectric formed on said p-type substrate said first nwell and said first pwell;
an NMOS transistor with an NMOS transistor gate on said gate dielectric over said first pwell;
a PMOS transistor with a PMOS transistor gate on said gate dielectric over said first nwell; and
a diode/bipolar ESD device located in the p-type substrate outside of said first nwell and said first pwell further comprising:
a gate spaced ESD diode with an ESD diode gate on said gate dielectric where said ESD diode gate separates a first doping
type diffusion from a second doping type diffusion and where said first doping type diffusion is coupled to a fixed voltage
and where said second doping type diffusion is coupled to an input/output pin of said integrated circuit;

a gate spaced ESD bipolar transistor with an ESD bipolar gate on said gate dielectric where said ESD bipolar gate overlies
a base of said ESD bipolar transistor with a second doping type and where said ESD bipolar gate separates an emitter diffusion
of said ESD bipolar transistor with said first doping type from a collector diffusion of said ESD bipolar transistor with
said first doping type;

said gate spaced ESD diode and said gate spaced ESD bipolar transistor are coupled in parallel;
said emitter is coupled to said I/O pin;
said base diffusion is coupled to said fixed voltage;
said collector is coupled to said fixed voltage;
said ESD diode gate is coupled to said fixed voltage;
said ESD bipolar gate is coupled to said fixed voltage; and wherein a single continuous section of gate material forms both
the ESD diode gate and the ESD bipolar gate.

US Pat. No. 9,299,830

MULTIPLE SHIELDING TRENCH GATE FET

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:
a substrate comprising a semiconductor material;
a drain region of a vertical metal oxide semiconductor (MOS) transistor disposed in the semiconductor material of the substrate;
a vertical drift region of the vertical MOS transistor disposed in the semiconductor material above the drain region;
trenches disposed in the substrate in the vertical drift region;
a dielectric liner disposed in the trenches;
a gate dielectric layer of the vertical MOS transistor disposed in the trenches above the dielectric liner;
a trench gate of the vertical MOS transistor disposed in the trenches contacting the gate dielectric layer;
a body of the vertical MOS transistor disposed in the substrate above the vertical drift region; and
a plurality of field plate segments disposed in the trenches, separated from the substrate by the dielectric liner, comprising:
a lower field plate segment at bottoms of the trenches; and
an upper field plate segment disposed above the lower field plate segment and below the trench gate;
wherein the dielectric liner disposed on sidewalls of the trenches between the lower field plate segment and the substrate
is thicker than the dielectric liner disposed on the sidewalls of the trenches between the upper field plate segment and the
substrate, and the dielectric liner disposed on the sidewalls of the trenches between the upper field plate segment and the
substrate is thicker than the gate dielectric layer disposed on the sidewalls of the trenches between the trench gate and
the substrate.

US Pat. No. 9,231,476

TRACKING ENERGY CONSUMPTION USING A BOOST-BUCK TECHNIQUE

TEXAS INSTRUMENTS INCORPO...

1. An electronic device comprising an energy tracking system, the energy tracking system including a boost circuit, an energy
transfer circuit and a control circuit, the control circuit to control switching of energy in the boost circuit and the energy
transfer circuit in order to transfer energy from a primary voltage applied at an input of the energy tracking system into
a secondary voltage at an output of the energy tracking system;
a first compare circuit to make a first comparison between an output of the boost circuit and a first reference, the first
compare circuit to generate a first output signal based on the first comparison;

a second compare circuit to make a second comparison between the output of the energy tracking system and a second reference,
the second compare circuit to generate a second output signal based on the second comparison;

the control circuit including an ON-time and OFF-time generator responsive to the second output signal, the control circuit
further including first control logic, second control logic, and an accumulator, the first control logic responsive to the
first output signal to generate switching signals for the boost circuit, the second control logic responsive to a signal from
the ON-time and OFF-time generator and to the second output signal to generate ON-time pulses with a constant width ON-time,
the accumulator to collect the ON-time pulses for determining consumed energy based on a number of ON-time pulses per time;

the boost circuit including:
a first inductor having a first terminal and a second terminal, the first terminal of the inductor connected to an input of
the boost circuit;

a first switch, the first switch connected to the second terminal of the first inductor, to ground, and to the control circuit;
a first diode having a cathode and an anode, the anode connected to the second terminal of the first inductor and the cathode
connected to an output of the boost circuit;

a second switch, the second switch connected to the second terminal of the first inductor, to the output of the boost circuit,
and to the control circuit; and

a capacitor having a first terminal and a second terminal, the first terminal of the capacitor connected to the cathode of
the first diode and the second terminal of the capacitor connected to ground,

the energy transfer circuit including:
a third switch, the third switch connected to the control circuit and to the input of the energy transfer circuit;
a second inductor having a first terminal and a second terminal, the first terminal is connected to the third switch and the
second terminal connected to an output of the energy transfer circuit;

a second diode having a cathode and an anode, the anode connected to ground and the cathode connected to the first terminal
of the second inductor; and

a fourth switch, the fourth switch connected to the control circuit, to the cathode of the second diode, and the anode of
the second diode.

US Pat. No. 9,384,003

DETERMINING WHETHER A BRANCH INSTRUCTION IS PREDICTED BASED ON A CAPTURE RANGE OF A SECOND INSTRUCTION

TEXAS INSTRUMENTS INCORPO...

1. An electronic processor for use with a memory having selectable memory areas, the processor comprising:
a memory area selection circuit operable to select one of the selectable memory areas at a time;
an instruction fetch circuit operable to fetch a target instruction at an address from the selected one of the selectable
memory areas;

an execution circuit coupled to execute instructions from said instruction fetch circuit and operable to execute a first instruction
for changing the selection by said memory area selection circuit from a first one of the selectable memory areas to a second
one of the selectable memory areas, said execution circuit further operable to execute a branch instruction which points to
an address;

a branch predictor circuitry for predicting branch behavior of the branch instruction to predict a target address of the branch
instruction, the branch predictor circuitry connected to the instruction fetch circuit to cause the instruction fetch circuit
to early fetch an instruction from the predicted target address, the branch predictor circuitry operable to be updated in
response to a prior prediction and execution of a branch instruction; and

a logic circuit connected to the instruction fetch circuit and the branch predictor circuitry, said logic circuit operable
to

detect the first instruction for changing the selection by said memory area selection circuit,
detect whether a branch instruction is within a capture range of the detected first instruction, disable said branch prediction
circuitry in response to a branch instruction being detected to be within the capture range of the detected first instruction,
and suppress update of the branch predictor circuitry in response to a branch instruction being detected to be within the
capture range of the detected first instruction.

US Pat. No. 9,281,881

4TX CODEBOOK ENHANCEMENT IN LTE

TEXAS INSTRUMENTS INCORPO...

1. A method of channel state information (CSI) feedback in a wireless communication system, comprising:
receiving one or more precoding matrix indicator (PMI) signals from a remote transceiver; and
generating a precoding matrix W derived from a matrix multiplication of two matrices W1 and W2, where said precoding matrix W is applicable to precoding one or more layers of data streams, matrix W1 selected from a first codebook C1 based on a first group of bits in the PMI signals, arid matrix W2 selected from a second codebook C2 based on a second group of bits in the PMI signals, wherein the first codebook C1 comprises the following W1 matrices constructed by non-adjacent Discrete Fourier Transform (DFT) vectors:


Nt?4 is the number of transmit antennas corresponding to W,

N is the maximum number of layers, an integer number greater than or equal to Nt ,

m is the beam index,
n is the layer index,
k is the codebook index and
X(k) is the block diagonal sub-matrix of W(k).

US Pat. No. 9,222,980

IC TEST CIRCUITRY AND ADAPTER WITH DATA TRANSPORT CONTROL REGISTER

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
A. functional logic;
B. test circuitry having a test clock in lead, a test mode select in lead, a test data in lead, and a test data out lead,
the test circuitry including a test access port controller, which includes a state machine, that is connected to the test
clock in lead and the test mode select in lead and that has control outputs, an instruction register having an input connected
to the test data in lead, an output coupled to the test data out lead and a control input connected to the control outputs
of the controller, and a data register having a serial input connected to the test data in lead, a serial output coupled to
the test data out lead, and inputs and outputs coupled to the functional logic; and

C. adapter circuitry including:
i. a first set of leads including: a. a clock input lead, b. a mode input and output lead, c. a test in data lead, and d.
a test out data lead,

ii. a second set of leads having:
a. a test clock out lead carrying a test clock signal coupled to the test clock in lead of the test circuitry,
b. a test mode select out lead carrying a test mode select signal coupled to the test mode select in lead of the test circuitry,
c. a test in data output lead carrying a test in data signal coupled to the test data in lead of the test circuitry, and
d. a test out data input lead carrying a test out data signal coupled to the test data out lead of the test circuitry; and
iii. a transport control register coupled to the first set of leads, the transport control register having bit locations for:
a. background data transfer format,
b. background data transfer enable,
c. custom data transfer enable, and
d. background data transfer selection.

US Pat. No. 9,118,239

POWER SUPPLY CONTROL METHOD FOR CONSTANT CURRENT CONSTANT POWER CONTROL

TEXAS INSTRUMENTS INCORPO...

11. A switching power supply, comprising:
an input configured to receive input power from a connected source;
an output operative to provide output power to a connected load;
at least one switch operative according to a switching control signal to selectively convert the input power from the input
to provide the output power to the output; and

a power supply controller operative to provide the switching control signal to the at least one switch, the power supply controller
comprising:

a voltage control circuit, including:
a voltage error circuit providing a voltage error signal or value representing a difference between a reference voltage signal
or value and an output voltage of the switching power supply, and

a voltage compensator circuit with a digital adder circuit providing an integrator signal or value based at least partially
on a current error value and previous error samples, the voltage compensator circuit providing a voltage control duty cycle
signal or value based at least partially on the voltage error signal or value and on the integrator signal or value, the voltage
compensator circuit comprising a digital proportional integral derivative (PID) circuit operative to compute a proportional
compensation value based on the digital voltage error value and a proportional constant, to compute an integral compensation
value based on a current sample of the digital voltage error value, the integrator value, and an integral constant, to compute
a derivative compensation value based on a difference between a current sample of the digital voltage error value and a preceding
sample of the digital voltage error value, and a derivative constant, and to compute a digital voltage control duty cycle
value as a sum of the proportional compensation value, the integral compensation value, and the derivative compensation value,
and

a presetting circuit operative to provide the voltage control duty cycle signal or value as either the digital voltage control
duty cycle value or as the predetermined duty cycle signal or value based on a preset control signal,

a current control circuit, including:
a current error circuit providing a current error signal or value based at least partially on a reference current signal or
value and an output current of the switching power supply, and

a current compensator circuit providing a current control duty cycle signal or value based at least partially on the current
error signal or value,

a pulse width modulation circuit operative to pulse width modulate at least one switch of the switching power supply at least
partially according to a duty cycle input signal or value, and

a control circuit selectively operative in a first mode to provide the voltage control duty cycle signal or value as the duty
cycle input signal or value, and in a second mode to provide the current control duty cycle signal or value as the duty cycle
input signal or value, the control circuit comprising a logic circuit operative to switch the control circuit from the first
mode to the second mode if a sum of the voltage control duty cycle signal or value plus a predetermined non-zero hysteresis
value is greater than the current control duty cycle signal or value, to selectively preset the voltage control duty cycle
signal or value to a predetermined duty cycle signal or value by providing the preset control signal to the presetting circuit
if the current control duty cycle signal or value is less than the voltage control duty cycle signal or value and then switch
the control circuit from the second mode to the first mode if the voltage control duty cycle signal or value is less than
the current control duty cycle signal or value, and to selectively prevent increase of the integrator signal or value of the
voltage compensator circuit while the control circuit is in the second mode.

US Pat. No. 9,236,107

FRAM CELL WITH CROSS POINT ACCESS

TEXAS INSTRUMENTS INCORPO...

1. A system on chip (SoC) comprising an array of bit cells, wherein the array comprises:
a plurality of bit cells organized into a plurality of rows and columns;
a plurality of word lines, wherein each row of bit cells has one of the plurality of word lines connected to each bit cell
in the row of bit cells;

a plurality of platelines, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell
in the column of bit cells; and

a plurality of bitlines, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell
in the column of bit cells;

wherein each bit cell of the plurality of bits cells comprises a non-volatile storage device connected in series with a pass
gate, wherein a terminal of the non-volatile storage device is coupled to one of the plurality of bitlines, a terminal of
the pass gate is coupled to one of the plurality of platelines, and a control terminal of the pass gate is coupled to one
of the plurality of word lines.

US Pat. No. 9,113,470

SYSTEMS AND METHODS FOR NETWORK CODING USING MAXIMUM DISTANCE SEPARABLE (MDS) LINEAR NETWORK CODES

TEXAS INSTRUMENTS INCORPO...

1. A method for network coding, comprising:
generating, by a processor, a message matrix wherein each column of the message matrix corresponds to one of K message packets
and each element in a column of the message matrix corresponds to one of the symbols of the corresponding message packet;

generating, by the processor, a network code matrix to map the K message packets to N encoded packets, wherein any combination
of K columns of the network code matrix is linearly independent and N is greater than K; and

multiplying, by the processor, the message matrix by the network code matrix to generate a transmission matrix, wherein each
column of the transmission matrix corresponds to an encoded packet for wireless transmission;

sending by the processor the resulting encoded packets to a physical layer of a wireless transmitter for transmission using
an existing underlying wireless communication protocol without modification.

US Pat. No. 9,281,275

BOND PAD HAVING RUTHENIUM DIRECTLY ON PASSIVATION SIDEWALL

TEXAS INSTRUMENTS INCORPO...

1. A method of forming bond pads, the method comprising:
providing a substrate including at least one integrated circuit (IC) device formed thereon having an oxidizable uppermost
metal interconnect layer which provides a plurality of bond pads coupled to circuit nodes on said IC device, said plurality
of bond pads including a metal bond pad area, and at least one passivation layer that provides a trench including dielectric
sidewalls above said metal bond pad area;

depositing a ruthenium (Ru) layer directly on said dielectric sidewalls and directly on said metal bond pad area, and
patterning said Ru layer to provide a bond pad surface for said plurality of bond pads.

US Pat. No. 9,282,333

METHODS AND SYSTEMS FOR MASKING MULTIMEDIA DATA

TEXAS INSTRUMENTS INCORPO...

1. A computer implemented method of masking multimedia data, the method comprising:
performing, with one or more processors, a prediction for at least one multimedia data block based on a prediction mode of
a plurality of prediction modes, the at least one multimedia data block being associated with a region of interest (ROI),
wherein the prediction mode is selected from the plurality of prediction modes by determining a plurality of values of sum
of absolute differences (SAD) associated with the plurality of prediction modes, and selecting the prediction mode from the
plurality of prediction modes that is associated with a highest value of SAD from the plurality of values of SAD, the prediction
mode associated with the highest value of SAD being configured to provide a worst prediction mode to mask the ROI;

generating, with the one or more processors, residual multimedia data associated with the at least one multimedia data block
based on the prediction; and

performing, with the one or more processors, a quantization of the residual multimedia data based on a quantization parameter
(QP) value, the QP value being variable such that varying the QP value controls a degree of masking of the ROI.

US Pat. No. 9,281,213

HIGH PRECISION CAPACITOR DIELECTRIC

TEXAS INSTRUMENTS INCORPO...

1. A process of forming an integrated circuit, comprising the steps:
providing a partially processed integrated circuit;
forming a high precision capacitor bottom plate with a metallic surface on the partially processed integrated circuit;
performing a plasma treatment of the metallic surface in a nitrogen plus ammonia ambient;
forming a high precision capacitor dielectric by:
depositing a first layer of a high precision capacitor dielectric on the high precision capacitor bottom plate wherein the
first layer is silicon nitride;

depositing a second layer of the high precision capacitor dielectric on the first layer wherein the second portion is silicon
dioxide; and

depositing a third layer of the high precision capacitor dielectric on the second portion wherein the third layer is silicon
nitride; and

forming a metallic high precision capacitor top plate on the high precision capacitor dielectric.

US Pat. No. 9,178,525

MISMATCH CORRECTOR

TEXAS INSTRUMENTS INCORPO...

1. A mismatch corrector comprising:
a correction path comprising a plurality of parallel branches that each comprises a correction filter that applies a respective
one of a plurality of time domain filter coefficients that corresponds to a function of a mismatch profile of an interleaved
analog-to-digital (IADC) signal on the IADC signal;

a delay path that delays the IADC signal by a predetermined number of samples to provide a delayed version of the IADC signal;
and

a summer to subtract an output of each correction filter from the delayed version of the IADC signal to generate a corrected
IADC signal.

US Pat. No. 9,306,743

ONE-WAY KEY FOB AND VEHICLE PAIRING VERIFICATION, RETENTION, AND REVOCATION

TEXAS INSTRUMENTS INCORPO...

1. A one way paired key fob device, comprising:
a transmitter configured to transmit signals to a control unit but not receive signals from the control unit; a memory configured
to store a key fob counter and an operation key (OpKey); and a processor coupled to said transmitter and memory, the processor
configured to:

generate an AES-128 OpKey-encrypted value of the key fob counter; transmit a message comprising a predetermined number of
lowest-order bits of the key fob counter and a predetermined number of bits of the AES-128 OpKey-encrypted value of the key
fob counter to the control unit; and

transmitting to the control unit a command to enter a revocation procedure, wherein OpKeys stored in the control unit that
were not recorded during a period are deleted.

US Pat. No. 9,110,111

METHODS AND SYSTEMS TO DETERMINE A FINAL VALUE OF RANDOM TELEGRAPH NOISE TIME CONSTANT AND MAGNITUDE

TEXAS INSTRUMENTS INCORPO...

15. A system, comprising:
an analyzer to measure a parameter of a device to generate a plurality of signals, each signal representing a time series
of values of the parameter; and

a computing resource coupled to the analyzer, comprising:
a processor configured to execute a plurality of modules to;
for the device at each of a plurality of sampling frequencies, cause the analyzer to apply a condition on the device to be
measured and generate a plurality of signals over time using a first integration time, each signals representing a time series
of values of the parameter;

identify at least two stable states in the time series for each signal;
determine a time constant associated with each stable state of each signal;
determine a relationship between the time constants of each stable state and sampling frequency; and
compute a final time constant value for each steady state by computing a derivative of the time constants as a function of
sampling frequency relationship and comparing the derivative to a threshold.

US Pat. No. 9,048,918

ANTENNA GROUPING AND GROUP-BASED ENHANCEMENTS FOR MIMO SYSTEMS

TEXAS INSTRUMENTS INCORPO...

13. A method of operating a receiver, comprising:
receiving a transmission layer mapping;
decoding to separate and demultiplex transmission layers corresponding to the transmission layer mapping; and
feeding back at least one group-based channel quality indicator to a transmitter transmitting the transmission layer mapping,
wherein each group-based channel quality indicator corresponds to one of a set of transmission layer mappings.

US Pat. No. 9,184,779

DYNAMIC MEDIUM SWITCH IN CO-LOCATED PLC AND RF NETWORKS

TEXAS INSTRUMENTS INCORPO...

1. An electronic communication device comprising:
a first transceiver capable of a bi-directional communication session on a first communication medium;
a second transceiver capable of a bi-directional communication session on a second communication medium;
a convergence layer; and
a control logic coupled to the first transceiver and the second transceiver and capable of implementing the convergence layer,
wherein the control logic is configured to

receive, from the first transceiver, a first signal; and
cause, through the convergence layer, in response to the first signal, data received and transmitted by the first transceiver
on the first communication medium as part of a communication session to be received and transmitted instead by the second
transceiver on the second communication medium;

wherein the convergence layer is configured to conceal from a routing layer at least one of
information related to the first signal, and
information related to the data being received and transmitted on the second communication medium.

US Pat. No. 9,310,823

VOLTAGE REFERENCE

TEXAS INSTRUMENTS INCORPO...

1. A voltage reference circuit having an output voltage, the circuit comprising:
a bipolar transistor having a base and an emitter;
a circuit configured to measure the ratio of emitter current to base current of the bipolar transistor;
the output voltage being compensated as a function of the measured ratio;
the bipolar transistor being a third bipolar transistor, the circuit further comprising:
first and second bipolar junction transistors having different current densities;
where the third bipolar junction transistor is driven with the same current density as one of the first and second bipolar
junction transistors;

where the third bipolar transistor is alternately driven with the current density of the first bipolar transistor and the
current density of the second bipolar transistor.

US Pat. No. 9,293,460

ESD PROTECTION DEVICE WITH IMPROVED BIPOLAR GAIN USING CUTOUT IN THE BODY WELL

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a substrate comprising a p-type semiconductor;
a symmetric p-channel metal oxide semiconductor (PMOS) transistor disposed in said substrate;
a p-type n-channel metal oxide semiconductor (NMOS) body well disposed in said substrate;
source and drain regions of a symmetric NMOS transistor disposed in said p-type NMOS body well; and
an NMOS silicon controlled rectifier (SCR), including:
a p-type body well disposed in said substrate, said p-type body well having a lateral cutout portion with a lower doping density
than the p-type body well outside of and laterally surrounding the lateral cutout portion;

an n-type source region disposed in said p-type body well over said lateral cutout portion;
an n-type region disposed in said substrate under said lateral cutout portion, said n-type region being connected to an n-type
drain region; and

a p-type body contact region, disposed in said p-type body well over said lateral cutout portion.

US Pat. No. 9,323,071

LASER SPECKLE REDUCTION FOR UNIFORM ILLUMINATION

TEXAS INSTRUMENTS INCORPO...

1. A diffuser for reducing laser speckle, comprising:
a colloid disposed in a container that is transparent to a selected light frequency and configured for placement in a light
path of a coherent light source, wherein a thickness of the colloid in the diffuser is in a range of 1 nanometer to 5 microns.

US Pat. No. 9,310,434

SCAN TOPOLOGY DISCOVERY IN TARGET SYSTEMS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
(A) a test clock lead, a test mode select lead, a test data in lead, and a test data out lead;
(B); a first test access port having a clock input connected to the test clock lead, having a mode input connected to the
test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data
out lead, the second test access port including topology selection logic, being coupled in a series branch, and having class
T0-T3, T4(W), T5(W) capabilities; and

(C) a second test access port having a clock input connected to the test clock lead, having a mode input connected to the
test mode select lead, having a data input connected to the test data in lead, and a data output connected to the test data
out lead, the second test access port including topology selection logic, being coupled in a Star-4 branch, having no class
T0-T2 capabilities, and having class T3, T4(W), and T5(W) capabilities.

US Pat. No. 9,305,688

SINGLE PHOTOMASK HIGH PRECISION THIN FILM RESISTOR

TEXAS INSTRUMENTS INCORPO...

1. A method of forming an integrated circuit, comprising the steps of:
forming a lower dielectric layer above active components of said integrated circuit;
forming electrodes in said lower dielectric layer, such that top surfaces of said electrodes are substantially coplanar with
a top surface of said lower dielectric layer between said electrodes;

forming a layer of resistor material over said lower dielectric layer and over said electrodes;
forming a resistor mask over said layer of resistor material which overlaps said electrodes;
removing said layer of resistor material in areas exposed by said resistor mask to form a thin film resistor, said thin film
resistor making electrical connections to said top surfaces of said electrodes at a bottom surface of said thin film resistor;
and

forming an upper dielectric layer over said thin film resistor and said lower dielectric layer, so that a top surface of said
thin film resistor is free of electrical connections.

US Pat. No. 9,305,812

DIE EJECT ASSEMBLY FOR DIE BONDER

TEXAS INSTRUMENTS INCORPO...

1. A die eject assembly for a die bonder comprising:
a reciprocating member having a first end;
a poker pin holder positioned at said first end of said reciprocating member
a poker pin being supported by said poker in holder, said poker pin comprising:
an elongate shaft portion having a first shaft end and a second shaft end;
a base portion having a first base end and a second base end, said first base end having a truncated cone shaped upper surface;
said first shaft end of said elongate shaft portion being fixedly attached to said second base end of said base portion; and
a poker pin lock member displaceably mounted on said poker pin holder and having a locked state in which said poker pin lock
member holds said poker pin in fixed relationship with said poker pin holder.

US Pat. No. 9,134,369

TAP, DATA INPUT, OUTPUT CIRCUITRY COUPLED TO MODE SELECT LEAD

TEXAS INSTRUMENTS INCORPO...

1. Communication circuitry comprising:
A. interface leads including a data input lead, a mode select lead, a clock lead, and a data output lead;
B. access port circuitry coupled to the interface leads and including controller circuitry connected to the mode select lead
and the clock lead and having control outputs, an instruction register connected to the data input lead and the control outputs,
and a data register connected to the data input lead and the control outputs; and

C. serial communication circuitry separate from the access port circuitry, the serial communication circuitry including data
input circuitry and data output circuitry coupled to the mode select lead and to the control outputs to input data and to
output data on the mode select lead.

US Pat. No. 9,454,437

NON-VOLATILE LOGIC BASED PROCESSING DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A method of booting or waking a computing device, the method comprising:
executing a standard boot sequence to determine at least a first portion of data for operation of a processing device configured
to store in one or more non-volatile logic arrays a machine state of the processing device in response to the processing device's
entering a backup mode;

restoring, in parallel with the executing of the standard boot sequence to determine the at least the first portion of data,
at least a second portion of data from the one or more non-volatile logic arrays for operation of the processing device, the
second portion of data being different from the first portion of data;

executing a data corruption check for the at least the second portion of data to confirm validity of the at least the second
portion of data;

then:
in response to the data corruption check confirming validity of the at least the second portion of data, executing a standard
boot sequence to determine at least a third portion of data for operation of the processing device, the third portion of data
being different from the first portion of data and different from the second portion of data,

or
in response to the data corruption check detecting invalid data, executing a standard boot sequence to determine at least
the second portion of data for operation of the processing device and the third portion of data for operation of the processing
device.

US Pat. No. 9,291,675

BOUNDARY CONTROL SCAN CELLS, DATA CELLS, RESYNCHRONIZATION MEMORIES, AND MULTIPLEXERS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
A. a first circuit having data input leads connected to the inputs of input data buffers, control output leads connected to
the outputs of control output buffers, and a first scan path coupled between a test data input lead and a test data output
lead, the first scan path including:

i. a first control scan cell having a functional data input, a functional data output connected to an input of a first control
output buffer, a test data input coupled to the test data input lead, and a test data output separate from the functional
data output;

ii. first data scan cells, each first data scan cell having a functional data input connected to a data output of one data
input buffer, a test data input, a functional data output, and a test data output, the first data scan cells being connected
in a series, the test data input of the initial first data scan cell in the series being connected to the test data output
of the first control scan cell, and the test data input of each successive first data scan cell in the series being connected
to the test data output of the previous first data scan cell;

iii. a resynchronization memory having a test data input connected to the test data output of the first control scan cell
and a test data output;

iv. multiplexer circuitry having one input connected to the test data output of the last first data scan cell in the series,
another input connected to the test data output of the resynchronization memory, and an output; and

v. a second control scan cell having a functional data input, a functional data output connected to the input of a second
control output buffer, a test data input coupled to the output of the multiplexer, and a test data output separate from the
functional data output coupled to the test data output lead;

B. a second circuit having data output leads coupled to respective data input leads of the first circuit and having a control
input lead coupled to a control output lead of the first circuit, the data output leads being connected to the outputs of
tri-state data output buffers, each tri-state data output buffer having a tri-state control input for, when active, placing
the output of the tri-state data output buffer in a high impedance output state, the control input lead being connected to
the input of a control input buffer, and a second scan path coupled between the test data input lead and the test data output
lead, the second scan path including:

i. a third control scan cell having a functional data input connected to the output of the control input buffer, a functional
data output connected to the tri-state control inputs of all the data output tri-state buffers, a test data input coupled
to the test data input lead, and a test data output separate from the functional data output;

ii. second data scan cells, each second data scan cell having a functional data input, a test data input, a functional data
output, and a test data output, the second data scan cells being connected in series, the test data input of the initial second
data scan cell in the series being connected to the test data output of the third control scan cell, and the test data input
of each successive second data scan cell being connected to the test data output of the previous second data scan cell, the
functional data output of each second data scan cell being connected to the data input of one tri-state data output buffer;

iii. a resynchronization memory having a test data input connected to the test data output of the third control scan cell
and a test data output; and

iv. multiplexer circuitry having one input connected to the test data output of the last second data scan cell in the series,
another input connected to the test data output of the resynchronization memory, and an output coupled to the test data output
lead; and

C. leads coupling the first and second scan paths between the test data input lead and the test data output lead.

US Pat. No. 9,287,858

LOW LEAKAGE SHADOW LATCH-BASED MULTI-THRESHOLD CMOS SEQUENTIAL CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A multi-threshold CMOS sequential circuit, comprising:
a first latch circuit formed of transistors having threshold voltages in a first range and powered from a switchable voltage
node to provide a primary data path storing at least one data bit during active mode operation of the sequential circuit;
and

a second latch circuit, comprising:
inverters formed of transistors selectively powered from a continuous voltage node and having threshold voltages in a second
range higher than the first range, the inverters of the second latch circuit selectively operative for low-power retention
mode operation of the sequential circuit to latch the at least one data bit transferred from the first latch circuit,

a transfer gate formed of transistors having threshold voltages in the second range and providing a data transfer path between
the first and second latch circuits during transitions from active to low-power retention mode and vice versa, the transmission
gate operative to disconnect the first and second latch circuits from one another during both active mode and low-power retention
mode operation of the sequential circuit, and

a second switching circuit selectively operative to disconnect the inverters of the second latch circuit from the continuous
voltage node during active mode operation of the sequential circuit.

US Pat. No. 9,883,603

ELECTRONIC PULL TAB FOR BATTERY PROTECTION

TEXAS INSTRUMENTS INCORPO...

1. A battery powered device, comprising:
a battery positioned within a housing of the device;
processing logic configured to perform functions of the device;
an electronic switch coupled between the battery and the processing logic;
a bias circuit coupled to the electronic switch, wherein the bias circuit is configured to hold the electronic switch off
to block current flow from the battery while the device is in a storage state; and

an override circuit coupled to the bias circuit and to a start signal generated by an ON switch, wherein the override circuit
is configured to override the bias circuit in response to activation of the start signal such that the electronic switch is
turned on and allows current to flow to the processing logic in an operational state.

US Pat. No. 9,253,850

LED BYPASS AND CONTROL CIRCUIT FOR FAULT TOLERANT LED SYSTEMS

Texas Instruments Incorpo...

1. A light system, comprising:
a plurality of switching devices having respective current paths connected in series, each switching device having a respective
control terminal, and each switching device arranged to receive a respective light emitting diode (LED) in parallel with the
respective current path; and

a plurality of fault detector circuits, each fault detector circuit coupled to the respective current path and having a first
comparator arranged to compare a voltage across the respective current path to a respective first reference voltage, wherein
each fault detector circuit indicates a short circuit fault when a voltage across the respective current path is less than
the respective first reference voltage.

US Pat. No. 10,008,450

OXIDATION RESISTANT BARRIER METAL PROCESS FOR SEMICONDUCTOR DEVICES

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:an underlying metal geometry;
a dielectric layer on the underlying metal geometry;
a contact opening through the dielectric layer wherein the contact opening stops on the underlying metal geometry;
an overlying metal geometry wherein a portion of the overlying metal geometry fills a portion of the contact opening;
an oxidation resistant barrier layer wherein the oxidation resistant barrier layer is disposed between the underlying metal geometry and overlying metal geometry and wherein the oxidation resistant barrier layer is formed of tantalum-nitride (TaN) or titanium-nitride (TiN) with a nitrogen content of at least 20 atomic % and a thickness of at least 5 nm; and
an interdiffusion barrier layer disposed between the underlying metal geometry and the oxidation resistant barrier layer, wherein the interdiffusion barrier layer is TaN or TiN with a thickness between 60 nm and 90 nm and a nitrogen content between 0 and 12 atomic percent.

US Pat. No. 9,213,048

SYSTEM AND METHOD FOR TESTING AN ELECTRONIC DEVICE

TEXAS INSTRUMENTS INCORPO...

1. An adapter for an electrostatic discharge probe, the probe having a conductive tip that is connectable with a lead of a
device under test, the adapter comprising:
an attachment device that is attachable to the tip of the probe, the attachment device including an inner surface structured
to contact and snug around the tip when the attachment device is attached to the tip;

a first conductor affixed to a portion of the inner surface of the attachment device without completely covering the inner
surface, the first conductor configured to contact the tip when the inner surface of the attachment device contacts and snugs
around the tip; and

a second conductor extending between the first conductor and a point external to the attachment device.

US Pat. No. 9,355,942

GANG CLIPS HAVING DISTRIBUTED-FUNCTION TIE BARS

TEXAS INSTRUMENTS INCORPO...

1. A gang clip comprising:
a metallic clip including a flat area and a ridge bending away from the flat area at an angle; and
a plurality of tie bars extending from the flat area, the end portions of the tie bars aligned in a common orientation, wherein
at least one surface of the gang clip has a metallurgical configuration suitable for solder attachment.

US Pat. No. 9,263,973

MEMS ELECTROSTATIC ACTUATOR

TEXAS INSTRUMENTS INCORPO...

1. A MEMS electrostatic actuator device comprising an array of MEMS actuators, each MEMS actuator comprising:
a bottom plate affixed to a substrate, wherein the bottom plate is a signal electrode;
a top plate suspended above the bottom plate; the top plate comprising a parallel plate center section and two rotating drive
members electrically connected to the center section, wherein the center section has openings to reduce stiction;

each rotating drive member is attached to a set of anchor posts, wherein the rotating drive members enable vertical movement
of the center section; and

electrostatic pull-down electrodes underneath each rotating drive member.

US Pat. No. 9,066,110

PARSING FRIENDLY AND ERROR RESILIENT MERGE FLAG CODING IN VIDEO CODING

TEXAS INSTRUMENTS INCORPO...

1. A method for decoding an encoded bit stream for a picture in a video decoder, the method comprising:
decoding a merge flag for a non skip mode inter-predicted prediction unit (PU) from the encoded bit stream;
constructing a merge mode motion data vector (merging candidate) list for the non skip mode inter-predicted PU for a first
value of the merge flag;

adding a zero motion vector merging candidate to the merging candidate list comprising determining a content of the zero motion
vector merging candidate based on a prediction type of a slice containing the non skip mode inter-predicted PU wherein the
zero motion vector merging candidate comprises a motion vector with a value of zero if the slice is a forward predicted slice,
and the zero motion vector merging candidate comprises two motion vectors with values of zero if the slice is a bi-directionally
predicted slice ; and

reconstructing the non skip mode inter-predicted PU based on the merging candidate list.

US Pat. No. 9,379,176

WELL RESISTORS AND POLYSILICON RESISTORS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a substrate comprising semiconductor material at a top surface of the substrate;
field oxide formed by a shallow trench isolation (STI) process disposed at the top surface of the substrate;
a well resistor disposed in the semiconductor material under the field oxide;
resistor head active areas disposed through the field oxide proximate to ends of the well resistor; and
resistor dummy active areas disposed through the field oxide in an area for the well resistor, the resistor dummy active areas
being free of electrical connections above the substrate, the resistor dummy active areas having a density of 10 percent to
80 percent.

US Pat. No. 9,360,693

LCD PANEL WITH NEW CONTROL LINE TOPOLOGY

TEXAS INSTRUMENTS INCORPO...

1. A liquid crystal display (LCD), comprising:
a plurality of segments; and
a plurality of control lines to activate the plurality of segments, wherein each of the plurality of segments is associated
with an intersection of two of the control lines;

wherein each of the plurality of control lines intersects with each of the other plurality of control lines only once; and
wherein a LCD waveform generator to activate the plurality of segments uses a duty cycle inversely proportional the number
of control lines of the LCD.

US Pat. No. 9,263,444

DEVICES HAVING INHOMOGENEOUS SILICIDE SCHOTTKY BARRIER CONTACTS

TEXAS INSTRUMENTS INCORPO...

1. A method of fabricating Schottky barrier contacts for a complementary metal-oxide-semiconductor (CMOS) integrated circuit
(IC), comprising:
providing a substrate including a silicon comprising surface having at least one PMOS region including a first gate stack
including a first gate electrode on a first gate dielectric therein and exposed p-type surface regions including a p-type
source and p-type drain on opposing sides of said first gate stack

and at least one NMOS region including a second gate stack including a second gate electrode on a second gate dielectric therein
and an exposed n-type surface regions including an n-type source and n-type drain on opposing sides of said second gate stack,

depositing a plurality of metals including Yb and Pt to form at least one metal layer on said substrate, and
heating said metal layer to induce formation of an inhomogeneous silicide layer including both Pt silicide and Yb silicide
on both of said exposed p-type surface regions and said exposed n-type surface regions.

US Pat. No. 9,123,802

VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:
a substrate comprising a semiconductor having a first conductivity type; and
a vertical drain extended metal oxide semiconductor (MOS) transistor, including:
a plurality of deep trench structures disposed in said substrate, at least one micron deep, each having a dielectric liner
abutting said substrate, said deep trench structures having substantially equal depths;

a vertical drain contact region having a second conductivity type opposite from said first conductivity type disposed in said
substrate, said vertical drain contact region abutting and being bounded on at least two opposite sides by a portion of said
deep trench structures;

a vertically oriented drift region having said second conductivity type disposed in said substrate, abutting and being bounded
on at least two opposite sides by a portion of said deep trench structures, in which said vertically oriented drift region
makes electrical connection to said vertical drain contact region proximate to a bottom of a first deep trench structure of
said plurality of said deep trench structures, said first deep trench structure separating said vertically oriented drift
region from said vertical drain contact region;

a vertical gate on a gate dielectric layer disposed in a vertically oriented gate trench in said dielectric liner of a first
deep trench structure of said plurality of deep trench structures; and

a body region having said first conductivity type disposed over said vertically oriented drift region and contacting said
gate dielectric layer, such that said vertical gate extends below said body region.

US Pat. No. 9,118,315

SCHEME TO IMPROVE THE PERFORMANCE AND RELIABILITY IN HIGH VOLTAGE IO CIRCUITS DESIGNED USING LOW VOLTAGE DEVICES

TEXAS INSTRUMENTS INCORPO...

1. An input/output (IO) circuit comprising:
a pre-reverse switch configured to receive a pair of input voltages, the pre-reverse switch comprising a first capacitor and
a second capacitor;

a main-driver, coupled to the pre-reverse switch and a pad, configured to receive a first bias voltage and a second bias voltage
and configured to generate a main-driver output voltage, the main-driver having a first parasitic capacitance and a second
parasitic capacitance, wherein the first parasitic capacitance is configured to couple the main-driver output voltage to the
first bias voltage and the second parasitic capacitance is configured to couple the main-driver output voltage to the second
bias voltage; and

a post-reverse switch coupled to the main-driver, the post-reverse switch comprising a third capacitor and a fourth capacitor,
wherein the first capacitor and the third capacitor counter an effect of coupling by the first parasitic capacitance on the
first bias voltage and the second capacitor and the fourth capacitor counter an effect of coupling by the second parasitic
capacitance on the second bias voltage.

US Pat. No. 9,596,724

METHOD AND APPARATUS FOR CALCULATING AN AVERAGE VALUE OF AN INACCESSIBLE CURRENT FROM AN ACCESSIBLE CURRENT

Texas Instruments Incorpo...

1. A buck converter having a regulated output current comprising:
a current measuring device measuring an input current to the converter;
a switch coupled to the current measuring device;
a pulse width modulation (PWM) circuit coupled to receive an output voltage from the measuring device;
an analog multiplier coupled to an output of the pulse width modulation (PWM) circuit to receive a signal (D) related to the
duty cycle of the regulator and a signal 1?D related to the duty cycle of a rectifier or synchronous switch and to a voltage
representative of a predetermined value of output current from the converter.

US Pat. No. 9,384,850

OTP READ SENSOR ARCHITECTURE WITH IMPROVED RELIABILITY

TEXAS INSTRUMENTS INCORPO...

1. A one-time programmable (OTP) memory cell read circuit comprising:
an OTP bit memory element operable to store a data bit;
a programmed-on OTP reference cell operable to generate a first reference current;
a first current mirror having a first input coupled to receive the first reference current, and having a second input coupled
to a current output of the OTP bit memory element and operable to sink current from the OTP bit memory element, wherein the
amount of current the first current mirror sinks from the OTP bit memory element is proportional to the first reference current;

a programmed-off OTP reference cell operable to generate a second reference current;
a second current mirror having a first input coupled to receive the second reference current, and having a second input coupled
to the current output of the OTP bit memory element and operable to sink current from the OTP bit memory element, wherein
the amount of current the second current mirror sinks from the OTP bit memory element is proportional to the second reference
current; and

a comparator operable to compare the voltage at the current output of the OTP bit memory element to a threshold voltage, and
operable to output a logical “1” if the voltage is higher than the threshold voltage, and operable to output a logical “0”
if the voltage is lower than the threshold voltage.

US Pat. No. 9,308,620

PERMEATED GROOVING IN CMP POLISHING PADS

TEXAS INSTRUMENTS INCORPO...

4. A polishing pad, comprising:
a polishing layer configured to polish a surface of at least one of a magnetic, optical or semiconductor substrate in the
presence of a polishing medium, the polishing layer including:

a rotational axis;
an outer periphery;
an annular polishing track concentric with the rotational axis; and
a peripheral region located between the annular polishing track and the outer periphery; and
a plurality of grooves formed in the polishing layer, having top and bottom surfaces, and comprising:
the plurality of grooves formed in the polishing pad comprising first, second and third sets of grooves located entirely within
the polishing pad;

the first set of grooves located on the top surface of the polishing pad, has a pattern and vertically penetrates into the
top surface of polishing pad to at least 37% of the polishing pad thickness;

the second set of grooves is located on the bottom surface of the polishing pad, has a pattern identical to the pattern of
the first set of grooves and vertically penetrates into the bottom surface of polishing pad towards the top surface to at
least 37% of the polishing pad thickness; and

wherein the first set of grooves is located in direct alignment at the interior ends, with the first set of grooves; and
the third set of grooves is centered between the top surface of the polishing pad and the bottom surface of the polishing
pad and located between and interlaced with the aligned interior ends of the first and second groves, and are configured to
present a continuous groove to the material being polished from the top of the pad to within 6 percent of the bottom of the
polishing pad.

US Pat. No. 9,246,450

APPARATUS AND METHOD FOR TESTING OF SUCCESSFUL OPERATION OF TRANSIMPEDANCE AMPLIFIERS

TEXAS INSTRUMENTS INCORPO...

1. Apparatus comprising:
at least two operational amplifiers;
a first and a second current input;
at least one voltage output; and
at least two feedback resistors, wherein:
a first current source is connectable to the first current input, and a test current source is connectable to the second current
input, and wherein

the first current input is connected to an inverting input of the first operational amplifier and
the second current input is connected to an inverting input of the second operational amplifier, and
a first feedback resistor is connected between the output and the inverting input of the first operational amplifier and a
second feedback resistor is connected between the output and the inverting input of the second operational amplifier, and
wherein

the at least one voltage output is connected to the outputs of the first and the second operational amplifier, and
a current mirror, wherein the current mirror is connected between the second current input and the inverting input of the
second operational amplifier, wherein a current mirror input of the current mirror is connected to the second current input
and a current mirror output is connected to the inverting input of the second operational amplifier.

US Pat. No. 9,188,641

IC TAP/SCAN SELECTING BETWEEN TDI/SI AND A TEST PATTERN SOURCE

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
A. a substrate carrying a serial data input lead, a serial data output lead, a select lead, and a clock lead;
B. functional circuitry on the substrate having data input leads and data output leads;
C. test access port circuitry on the substrate having a test data input lead connected to the serial data input lead, a test
data output lead selectively connected to the serial data output lead, scan circuitry control output leads, a TAP controller
having a test mode select input lead selectively coupled to the select lead, a test clock input lead connected to the clock
lead, and a buffer enable output lead, and a data register having an input connected to the test data input lead and having
an output selectively coupled to the test data output lead;

D. scan test port circuitry on the substrate having a scan input lead, a scan output lead selectively coupled to the serial
data output lead, a capture select input lead, a scan clock input lead, and a scan register connected between the scan input
lead and the scan output lead, the scan register having functional data output and input leads connected to the functional
circuitry data input leads and data output leads;

E. connection circuitry on the substrate coupling the scan test port circuitry to the test access port circuitry, the connection
circuitry having control inputs connected to the scan circuitry control output leads, the select lead, and the clock lead,
and the connection circuitry having control outputs connected to the capture select input lead, and the scan clock input lead;
and

F. selection circuitry having an input connected to the serial data input lead, an input connected to a test pattern source
lead, a control input coupled to the scan circuitry control output leads, and an output connected to the scan input lead.

US Pat. No. 9,516,663

DATA AND CONTROL MULTIPLEXING IN PUSCH IN WIRELESS NETWORKS

TEXAS INSTRUMENTS INCORPO...

22. An apparatus for use in a wireless network, comprising:
circuitry for mapping a Rank Indicator (RI) control signal to a first symbol;
circuitry for mapping an ACK/NACK control signal to a second symbol;
circuitry for mapping a reference signal (RS) control signal to a third symbol, wherein the first, second and third modulation
symbols are consecutive in time; and

circuitry for transmitting a sequence of symbols wherein the Rank Indicator (RI) control signal is mapped to the first symbol,
the ACK/NACK control signal is mapped to the second symbol and the reference signal (RS) control signal is mapped to the third
symbol.

US Pat. No. 9,450,546

SYSTEM, METHOD AND DEVICE FOR POWER AMPLIFICATION OF A SIGNAL IN AN INTEGRATED CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
a first power amplifier and a second power amplifier;
a first primary winding configured to directly receive first power solely from the first power amplifier and a second primary
winding configured to directly receive second power solely from the second power amplifier wherein, both the first primary
winding and the second primary winding are commonly electromagnetically coupled to a secondary winding such that the power
transferred from the first primary winding and the second primary winding are additive on the secondary winding; and

a current path connected between the first primary winding and the second primary winding enabling a flow of a first current
induced on at least one of first primary winding and second primary winding when one of first power amplifier and second power
amplifier is in “off” state.

US Pat. No. 9,246,489

INTEGRATED CLOCK GATING CELL USING A LOW AREA AND A LOW POWER LATCH

TEXAS INSTRUMENTS INCORPO...

13. An ICG (integrated clock gating) cell comprising:
a first logic gate configured to receive an enable signal and configured to generate a latch input;
a latch coupled to the first logic gate and configured to receive the latch input and a clock input, the latch comprising
a tri-state inverter and an inverting logic gate, the tri-state inverter is configured to be activated by a control signal
generated by the inverting logic gate; and

a second logic gate configured to receive the control signal and configured to generate a gated clock.

US Pat. No. 10,111,285

ADAPTIVE TURN-OFF DELAY TIME COMPENSATION FOR LED CONTROLLER

Texas Instruments Incorpo...

1. A light emitting diode controller integrated circuit comprising:(a) detector circuitry having a sense input adapted to be coupled to a sense resistor connected in series with a light emitting diode, a reference voltage input, and a comparator output;
(b) compensation timer circuitry having an input coupled to the comparator output, a pulse width modulated input, a clock signal input, and a count output, the compensation timer circuitry having an increment input coupled with the comparator input and the pulse width modulated input and a decrement input coupled with the pulse width modulated input;
(c) driver control circuitry having an input coupled to the count output, an input coupled to the pulse width modulated input, and a driver output; and
(d) driver circuitry having an input coupled with the driver output and having a control output adapted to be coupled to a control input of a power transistor connected in series with the light emitting diode.

US Pat. No. 9,397,824

GEAR SHIFTING FROM BINARY PHASE DETECTOR TO PAM PHASE DETECTOR IN CDR ARCHITECTURE

TEXAS INSTRUMENTS INCORPO...

1. A method for providing clock data recovery (CDR) in a receiver, the method comprising:
receiving a Phase Amplitude Modulation (PAM) signal;
on startup, using a non-return-to-zero (NRZ)-based phase frequency detector (PFD) to acquire a frequency from the received
PAM signal; and

responsive to a determination, switching to a PAM phase detector (PD) for steady state operation of the CDR module;
receiving at the NRZ-based PFD a first signal that comprises the received PAM signal after amplification and equalization
using a continuous time linear filter;

receiving at the PAM PD a second signal that comprises the first signal summed with a correction provided by a Decision Feedback
Equalizer (DFE); and

receiving at the PAM PD a third signal that comprises PAM data output from the DFE.

US Pat. No. 9,209,700

MAGNETIC SENSING TECHNIQUE FOR POWER SUPPLY SYSTEMS

Texas Instruments Incorpo...

1. A power supply system comprising:
a transformer comprising a primary winding, a secondary winding, and an auxiliary winding that are magnetically coupled;
a switch stage configured to generate a current through the primary winding in response to activation of a switch based on
a control signal that is generated based on a feedback voltage associated with the auxiliary winding, the current being induced
in the secondary winding;

an output stage coupled to the secondary winding and configured to generate an output voltage based on the current induced
in the secondary winding; and

a feedback stage coupled to the auxiliary winding and comprising a discriminator configured to determine a zero-current condition
associated with the current induced in the secondary winding based on monitoring a change in slope of the feedback voltage
and to measure the feedback voltage during the zero-current condition, wherein the discriminator further comprises a window
comparator that is configured to establish a window of acceptable magnitudes for the change in the slope of the feedback voltage
to qualify the feedback voltage for a predetermined duration of time before the feedback voltage is measured.

US Pat. No. 9,083,571

SYMBOL-WISE CHANNEL TRACKING FOR SMART UTILITY NETWORKS (SUN) ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING (OFDM)

TEXAS INSTRUMENTS INCORPO...

1. A device for updating channel gain estimates for orthogonal frequency division multiplexed (OFDM) symbols, comprising:
a receiver to receive a plurality of OFDM symbols, wherein each OFDM symbol includes a plurality of pilot tones at a subset
of odd positions; and

a finite impulse response (FIR) filter configured to:
filter a plurality of channel estimates of odd tones of an OFDM symbol using a first set of coefficients to generate an updated
estimate of the channel estimates of the plurality of odd tones for that OFDM symbol, and

filter the plurality of the channel estimates of the odd tones of the OFDM symbol using a second set of coefficients to generate
estimates for a plurality of initial channel estimates of even tones for that OFDM symbol.

US Pat. No. 9,054,027

III-NITRIDE DEVICE AND METHOD HAVING A GATE ISOLATING STRUCTURE

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:
a substrate comprising III-N semiconductor material;
an low-defect layer of III-N semiconductor material disposed on said substrate;
a barrier layer of III-N semiconductor material disposed on said low-defect layer;
a gallium nitride field effect transistor (GaN FET), comprising:
a gate disposed over said barrier layer;
a drain contact disposed over said low-defect layer; and
a source contact disposed over said low-defect layer; and
a gate isolating structure disposed over said barrier layer having a same structure as said gate, said gate isolating structure
being operable to electrically isolate a first region of said semiconductor device from a second regions of said semiconductor
device.

US Pat. No. 9,236,809

AUTOMATIC TIMING ADJUSTMENT FOR SYNCHRONOUS RECTIFIER CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:
a conduction detector configured to monitor conduction of a body diode of a synchronous rectifier switch relative to a predetermined
threshold and to generate a detector output that indicates conduction or non-conduction of the body diode; and

a window analyzer configured to generate a timing signal based on the detector output from the conduction detector, the timing
signal indicating if the synchronous rectifier switch is turned off prematurely or is turned off late relative to an on-time
turn off; and

a controller configured to adjust timing of the synchronous rectifier switch based on whether the timing signal indicates
that the synchronous rectifier switch is turned off prematurely or turned off late relative to the on-time turn off.

US Pat. No. 9,082,905

PHOTODIODE EMPLOYING SURFACE GRATING TO ENHANCE SENSITIVITY

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:
a substrate comprising a semiconductor material extending to a top surface of said substrate;
a photodiode disposed in said substrate;
a surface grating disposed at said top surface of said substrate over the photodiode, said surface grating comprising a plurality
of alternating spaced apart field oxide elements disposed in the top surface of the substrate over the photodiode and a plurality
of alternating spaced apart gate structures disposed on the top surface of the substrate over the photodiode therebetween,
wherein only one gate structure is disposed between each pair of field oxide elements so that said surface grating covers
more than half of said photodiode and a pitch length of said surface grating is no more than 3 microns.

US Pat. No. 9,543,437

INTEGRATED CIRCUIT WITH DUAL STRESS LINER BOUNDARY

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a substrate including:
an nwell surrounded by an nwell perimeter;
a p-active region in the nwell; and
an n-active region outside of the nwell; and
a tensile contact etch stop layer formed over the n-active region and patterned with an opening defined by:
a perpendicular stress liner border aligned substantially within the nwell parameter; and
a parallel stress liner border aligned between the p-active region and n-active region and outside of the nwell perimeter.

US Pat. No. 9,501,074

DYNAMIC CURRENT PULL-DOWN FOR VOLTAGE REGULATOR

TEXAS INSTRUMENTS INCORPO...

1. A circuit comprising:
a comparator to monitor a transient with respect to a predetermined threshold at the output of a voltage regulator and to
generate a compensation signal if the transient exceeds the predetermined threshold; and

a dynamic current pull-down block that is triggered from the compensation signal of the comparator and operative with an output
stage of the voltage regulator to mitigate the transient at the output of the voltage regulator by concurrently activating
a plurality of current pull-down switches during the transient and sequentially deactivating each current pull-down switch
of the plurality of current pull-down switches after its predetermined deactivation delay for each current pull-down switch;

further comprising an error amplifier to generate an error output voltage with respect to an input reference voltage of the
voltage regulator and an output stage to receive the error output voltage of the error amplifier and to generate a control
signal for the voltage regulator.

US Pat. No. 9,300,024

INTERFACE BETWEEN AN INTEGRATED CIRCUIT AND A DIELECTRIC WAVEGUIDE USING A DIPOLE ANTENNA, A REFLECTOR AND A PLURALITY OF DIRECTOR ELEMENTS

TEXAS INSTRUMENTS INCORPO...

1. A system comprising an electronic device coupled to a mating end of a dielectric wave guide (DWG), wherein the electronic
device comprises:
a multilayer substrate, wherein the multilayer substrate comprises:
an interface surface configured for interfacing to the mating end of the DWG;
a conductive layer etched to form a dipole antenna disposed adjacent the interface surface, the dipole antenna configured
to provide coupling to the DWG; and

a reflector structure formed in the substrate adjacent the dipole antenna opposite from the interface surface; and
wherein the DWG includes a plurality of director elements embedded in the mating end of the DWG, in which the plurality of
director elements are arranged side-by-side.

US Pat. No. 9,270,410

MIMO PGRC SYSTEM AND METHOD

TEXAS INSTRUMENTS INCORPO...

1. A method of transmitting a wireless signal from a wireless transmitter, comprising the steps of:
receiving a data stream;
dividing the data stream into a first data stream and a second data stream;
encoding the first data stream in response to a first channel quality indication;
encoding the second data stream separately from the first data stream in response to a second channel quality indication;
converting a first part of the encoded first data stream to a first symbol;
converting a second part of the encoded first data stream to a second symbol;
multiplying the encoded first and second symbols by a linear basis matrix to produce first and second product symbols; and
transmitting the product symbols from at least two transmit antennas of the wireless transmitter.

US Pat. No. 9,202,912

LOW COST DEMOS TRANSISTOR WITH IMPROVED CHC IMMUNITY

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a DEMOS transistor further including:
a body of the DEMOS transistor formed by a well in a substrate of the integrated circuit wherein a doping type of the well
is opposite a doping type of the substrate;

a lightly doped extended drain of the DEMOS transistor wherein the lightly doped extended drain is the same doping type as
the substrate and wherein the lightly doped extended drain is electrically isolated from the substrate on the sides by the
well and on the bottom by an underlying buried layer of the opposite doping type;

a gate of the DEMOS transistor wherein a first portion of the gate overlies the body of the DEMOS transistor and a second
portion of the gate overlies a portion of the lightly doped extended drain adjacent to the body;

a reduced resistance surface channel in the lightly doped extended drain under the gate;
a reduced resistance subsurface channel in the lightly doped extended drain that is not under the gate; and
a reduced resistance transition channel that couples the reduced resistance surface channel to the reduced resistance subsurface
channel.

US Pat. No. 9,113,460

MAPPING BETWEEN LOGICAL AND PHYSICAL UPLINK CONTROL RESOURCE BLOCKS IN WIRELESS NETWORKS

TEXAS INSTRUMENTS INCORPO...

1. A base station for use in a wireless network, comprising:
processing circuitry connected to receiver circuitry and to transmitter circuitry, the receiver circuitry being operable to
receive an uplink control information in a subframe using one of the plurality of uplink physical resource blocks indexed
by nPRB,1;

wherein a first uplink physical resource block index nPRB,1 of a plurality of uplink physical resource blocks is given by nPRB,1=nLRB/2 if nLRB is even and nPRB,1=NPRB?ceil(nLRB/2) if nLRB is odd;

wherein N PRB is the total number of the plurality of uplink physical resource blocks;

wherein the logical uplink control resource block index nLRB is based on information transmitted by the transmitter circuitry; and

wherein cell denotes the ceiling operation.

US Pat. No. 9,543,430

SEGMENTED POWER TRANSISTOR

TEXAS INSTRUMENTS INCORPO...

9. An electronic device comprising:
multiple power transistors, each power transistor comprising:
multiple substantially parallel transistor fingers, each finger including a conductive source stripe and a conductive drain
stripe along a first direction; and

multiple substantially parallel conductive connection lines, each connection line connecting at least one source stripe to
a common source connection or at least one drain stripe to a common drain connection, the conductive connection lines disposed
along a second direction substantially perpendicular to the transistor fingers;

wherein at least one of the source or drain stripes is segmented into multiple portions, wherein adjacent portions are separated
by a cut location having a higher electrical resistance than remaining portions of the at least one segmented source or drain
stripe, and wherein a current path between the adjacent multiple portions is discouraged along the first direction.

US Pat. No. 9,432,576

METHOD AND APPARATUS FOR FUSING IMAGES FROM AN ARRAY OF CAMERAS

TEXAS INSTRUMENTS INCORPO...

1. An image fusing method for fusing images from an array of cameras, comprising:
retrieving, with a digital processor, input images from the array of cameras;
selecting, with the digital processor, a camera from the array of cameras as a reference camera;
estimating, with the digital processor, misalignment between retrieved input images from the reference camera and retrieved
input images from other cameras in the array of cameras;

estimating, with the digital processor, misalignment parameters between the reference camera and the other cameras in the
array of cameras;

correcting, with the digitial processor, the retrieved input images from the other cameras based on the estimated misalignment
parameters to generate corrected image data;

estimating, with the digital processor, local disparity between image data from the reference camera and the corrected image
data from the other cameras in the array of cameras;

using, with the digital processor, the estimated misalignment parameters and the estimated local disparity to map image data
from the other cameras onto a reference camera grid corresponding to the reference camera, wherein the retrieved input image
data from the other cameras in the array of cameras is fused in the reference camera grid utilizing fractional offsets from
integer coordinates;

producing, with the digitial processor, an output image grid on the reference camera grid; and
interpolating, with the digitial processor, output pixels using processed data for producing a high-resolution image.

US Pat. No. 9,281,232

DEVICE HAVING IMPROVED RADIATION HARDNESS AND HIGH BREAKDOWN VOLTAGES

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:
a silicon substrate having a top surface, a moat region along the top surface, a channel region positioned within the moat
region, and a diffusion region positioned within the moat region and adjacent to the channel region along a length direction
of the device;

a field oxide layer formed above the silicon substrate and surrounding the moat region, the field oxide layer having a tapered
edge to interface with the moat region; and

a gate layer formed above the substrate, the gate layer extending across the moat region along the length direction of the
device, and the gate layer abutting the tapered edge of the field oxide layer to surround the diffusion region.

US Pat. No. 9,356,352

WAVEGUIDE COUPLER

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:
an integrated circuit (IC); and
an antenna package having:
a circuit trace assembly that is secured to the IC; and
a coupler that is secured to the circuit trace assembly, the coupler including:
an antenna assembly having:
a window region;
a conductive region that substantially surrounds the window region;
a circular patch antenna that is in communication with the IC; and
an elliptical patch antenna that is located within the window region, that extends over at least a portion of the circular
patch antenna, and that is in communication with the circular patch antenna; and

a high impedance surface (HIS) that substantially surrounds the antenna assembly.

US Pat. No. 9,356,133

MEDIUM VOLTAGE MOSFET DEVICE

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device, comprising:
a substrate;
a drain drift region of a first conductivity type disposed in said substrate;
transistor RESURF trenches defined in said drain drift region, said transistor RESURF trenches each having a trench liner
of dielectric material and a RESURF field plate disposed on said trench liner;

a split gate disposed over said drain drift region between said transistor RESURF trenches, said split gate having a central
opening;

a body region of a second conductivity type, opposite from said first conductivity type, disposed in said substrate abutting
said transistor RESURF trenches;

a source region formed in said body region;
a two-level lightly doped drain (LDD) region of said first conductivity type disposed in said substrate under said central
openings in said split gate;

source-contact trenches defined into said transistor RESURF trenches from a top surface of said substrate, said source-contact
trenches exposing said source region; and

a contact metal stack disposed in said source-contact trenches, said contact metal stack making contact with said source region
and said RESURF field plate in each of said transistor RESURF trenches.

US Pat. No. 9,356,650

CIRCUITS, DEVICES, AND PROCESSES FOR IMPROVED POSITIONING SATELLITE RECEPTION AND OTHER SPREAD SPECTRUM RECEPTION

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit for spread spectrum reception, comprising:
an hypothesis search circuit operable to search hypothesis frequencies and code lags to produce correlation results; and
a processor circuit operable to combine the correlation results for at least two hypothesis frequencies at a given code lag,
the at least two hypothesis frequencies separated by a predetermined frequency difference, and to identify a peak in the combined
correlation results;

wherein said hypothesis search circuit is operable to switch to a bit edge aligned search to issue a plurality of repetitions
of pseudonoise (PN) code free of negation per coherent integration window with a Doppler wipeoff at two frequencies equally
offset plus/minus from the Doppler frequency and correlate with a received signal to electronically determine whether the
correlation results combined is greater than zero or less than zero, whereby to deliver a latest signal bit.

US Pat. No. 9,300,247

RC OSCILLATOR WITH ADDITIONAL INVERTER IN SERIES WITH CAPACITOR

TEXAS INSTRUMENTS INCORPO...

1. A local power supply circuit comprising:
a supply voltage input and a supply voltage return lead;
a current source having an input coupled to the supply voltage input and an output;
a current mirror having a first input coupled to the supply voltage input, a second input coupled to the output of the current
source, a first output, and a local power supply output; and

a first self-biased inverter having a third input coupled to the first output and an output coupled to the supply voltage
return lead, the first self-biased inverter including a third transistor having a control node, a first node, and a second
node and a fourth transistor having a control node, a first node, and a second node, the first and second nodes of the third
and fourth transistors being coupled in series between the third input and the supply voltage return lead, the control node
of the third transistor being connected to the local power supply output, and the control node of the fourth transistor being
connected to the supply voltage return lead, and including a capacitor coupled between the local power supply output and the
supply voltage return lead.

US Pat. No. 9,153,228

WIRELESS TELEPHONE SENDING SPEECH DATA IN SECOND PACKET SECONDARY STAGE

TEXAS INSTRUMENTS INCORPO...

1. A wireless telephone comprising:
A. an antenna;
B. a voice transducer;
C. an integrated circuit processor circuit coupled to the antenna and the voice transducer; and
D. a memory coupled to the processor circuit holding bits defining a process of:
i. converting audible speech from the voice transducer into digital data representing the audible speech in each of successive
frames, for each frame the converting including forming Linear Prediction Coding data, Long Term Prediction lag data, parity
check data, adaptive and fixed codebook gain data, and fixed codebook pulse data;

ii. placing the digital data representing the audible speech for the frames into sequential packets, with each packet having
a primary stage and a secondary stage, the placing including:

a. arranging data from a first frame of speech in the primary stage of a first packet; and
b. arranging data from the first frame of speech in the secondary stage of a second packet, which follows immediately after
the first packet, the data in the secondary stage including only Linear Prediction Coding data, Long Term Prediction lag data,
parity check data, and adaptive and fixed codebook gain data; and

iii. sending the first and second packets of data sequentially over the antenna.

US Pat. No. 9,130,904

EXTERNALLY AND INTERNALLY ACCESSING LOCAL NAS DATA THROUGH NSFV3 AND 4 INTERFACES

TEXAS INSTRUMENTS INCORPO...

1. A process comprising:
(A) assigning from an active directory/Kerberos server to an external user of a collaborative design system a unique external
user identification, a unique group identification, and a unique virtual private network identification;

(B) receiving from an external user computer a request to establish a virtual private network between the external user computer
and a local engagement virtual machine that the external user is authorized to access, the receiving including identifying
a particular local engagement virtual machine by the external user's group identification;

(C) establishing a virtual private network tunnel between the external user computer and the particular local engagement virtual
machine through a firewall separating the external computer user and the particular local engagement virtual machine;

(D) receiving the external user identification in a local active directory/Kerberos server to authorize and log the external
user computer onto the particular local engagement virtual machine;

(E) issuing a Kerberos ticket from the active directory/Kerberos server to the external user computer in response to authorization;
(F) accessing project files and data of the collaborative design system stored on a local network attached storage server
by the external user computer through an NSFv4 interface of the local network attached storage server, including presenting
the Kerberos ticket from the external user computer through the NFSv4 interface to the local network attached storage server
for authenticating the external user computer to access the project files and data of the a collaborative design system stored
on the local network attached storage server;

(G) receiving log in information from an internal user computer in a local computer system coupled to the local network attached
storage server and authenticating the log in information using a network information service; and

(H) accessing the project files and data of the collaborative design system stored on the local network attached storage server
by the internal user computer through an NSFv3 interface of the network attached server without a Kerberos ticket.

US Pat. No. 9,103,885

INTEGRATED CIRCUIT WITH PLURAL COMPARATORS RECEIVING EXPECTED DATA AND MASK DATA FROM DIFFERENT PADS

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
A. input pads and output pads;
B. core circuitry having inputs coupled to the input pads and outputs coupled to the output pads, the core circuitry including
a first core output coupled to a first output pad, and the core circuitry including a second core output coupled to a second
output pad;

C. first comparator circuitry having an input coupled to the first core output, an expected data input coupled to the first
output pad, a mask data input coupled to a third output pad, a compare strobe input coupled to a compare strobe lead, a scan
data input, a scan data output, and a scan control input coupled to a scan control lead; and

D. second comparator circuitry having an input coupled to the second core output, an expected data input coupled to the second
output pad, a mask data input coupled to a fourth output pad, a compare strobe input coupled to the compare strobe lead, a
scan data input coupled to the scan data output of the first comparator circuitry, a scan data output, and a scan control
input coupled to the scan control lead.

US Pat. No. 9,554,435

LED DRIVE APPARATUS, SYSTEMS AND METHODS

TEXAS INSTRUMENTS INCORPO...

1. An apparatus for controlling a level of luminance produced by a color light-emitting diode (LED) array, comprising:
a parallel array of LEDs consisting of at least one LED corresponding to each of three primary colors;
a light flux sensor flux-coupled to the LED array to sense a magnitude of light flux output from a selected LED;
a pulse width modulation (PWM) selector communicatively coupled to the LED array to select a predetermined light flux magnitude
set-point signal associated with a predetermined primary color for a predetermined flux bit-slice period;

a flux comparator coupled to the PWM selector and to the light flux sensor to compare the sensed magnitude of light flux output
to the light flux magnitude set-point signal; and

a current drive circuit communicatively coupled to the flux comparator to selectively charge an energy storage device used
to supply current to the LED array when the sensed magnitude of light flux output is less than the light flux magnitude set-point,
the energy storage device coupled between the current drive circuit and a common anode terminal of the LED array.

US Pat. No. 9,274,201

AUTOMATIC CALIBRATION METHOD FOR ACTIVE AND REACTIVE POWER MEASUREMENT

TEXAS INSTRUMENTS INCORPO...

1. A method of calibrating a device, said method comprising:
providing, via a reference component, a reference power signal based on a voltage instruction and a current instruction;
sampling, via a sampling component, a voltage signal to obtain a sampled voltage value;
sampling, via the sampling component, a current signal to obtain a sampled current value;
generating, via a calibration component, a calibrated power signal based on the sampled voltage value and the sampled current
value;

generating, via a comparing component, an error signal based on the reference power signal and the calibrated power signal;
and

calibrating, via a feedback system including a proportional integral component and the calibration component, the gain of
the sampled voltage and the sampled current based on the error signal.

US Pat. No. 9,269,703

ESD PROTECTION USING DIODE-ISOLATED GATE-GROUNDED NMOS WITH DIODE STRING

TEXAS INSTRUMENTS INCORPO...

1. A method of forming an integrated circuit, comprising:
forming a gate-grounded NMOS ESD device;
forming an isolation diode in series with and coupled to a source of the gate-grounded NMOS transistor, wherein the isolation
diode is segmented and placed in close proximity to, and on opposite sides of, a body of the gate-grounded NMOS ESD device;
and

forming a diode string coupled to the gate-grounded NMOS ESD device in a forward biased configuration, wherein diodes of the
diode string are segmented and placed on multiple sides of the body of the gate-grounded NMOS ESD device.

US Pat. No. 9,201,121

SYSTEM AND METHOD FOR SENSING BATTERY CAPACITY

Texas Instruments Incorpo...

1. A battery sense system comprising:
a temperature sensor configured to measure a temperature of a battery;
a memory configured to store predetermined data associated with steady-state and transient behaviors of the battery relative
to a depth of discharge (DOD) of the battery; and

a controller configured to obtain samples of a voltage of the battery at each of a plurality of sampling intervals, to estimate,
without requiring an additional current sensor, a corresponding current generated by the battery at a given sampling interval
k of the plurality of sample intervals wherein battery current can be determined both under operating conditions and passive
conditions based only on the voltage at a respective one of the sampling intervals, the predetermined data, and the temperature,
and to calculate a state of charge (SOC) of the battery based on based on the estimated current through the battery at the
respective one of the sampling intervals and based on the DOD of the battery at an immediately preceding sampling interval
k-1.

US Pat. No. 9,461,439

OPTOELECTRONIC PACKAGES HAVING MAGNETIC FIELD CANCELATION

TEXAS INSTRUMENTS INCORPO...

1. A stacked optoelectronic packaged device (packaged device), comprising:
a plurality of stacked components within a package including:
a bottom die;
a first cavity die on bottom die;
at least one optics die on said first cavity die;
a second cavity die on said optics die;
a mounting substrate on said second cavity die; and
a photodetector (PD) die optically coupled to receive said light originating from a light source die on the bottom die,
wherein:
at least one of said bottom die and said mounting substrates includes a first set of traces and a second set of traces, the
first and second sets of traces being positioned substantially symmetrically on a first side and a second side of a mirror
plane, respectively;

the first set of traces includes a first inner trace of a first width, a first middle trace of a second width, and a first
outer trace of a third width on the first side of the mirror plane, the first width being greater than the second and third
widths and the first outer trace being closer to a center of the packaged device; and

the second set of traces includes a second inner trace of a fourth width, a second middle trace of a fifth width, and a second
outer trace of a sixth width on the second side of the mirror plane, the fourth width being greater than the fifth and sixth
widths and the second outer trace being closer to a center of the packaged device.

US Pat. No. 9,369,116

LEADING-EDGE PHASE-CUT DIMMER DETECTOR

TEXAS INSTRUMENTS INCORPO...

16. A circuit for detecting a leading-edge phase-cut dimmer, comprising:
a light-emitting diode driven by an LED driver signal;
an edge detector operable to receive the LED driver signal, detect whether the LED driver signal has a rapidly rising edge,
and provide an edge detector output signal, wherein the edge detector output signal comprises a signal pulse if a rapidly
rising edge is detected in the LED driver signal;

a pulse stretcher operable to receive the edge detector output signal and provide a pulse stretcher output signal, wherein
if the edge detector output signal comprises a signal pulse, the pulse stretcher output signal comprises a stretched pulse
having a duration that is longer than the signal pulse received from the edge detector;

a filter operable to receive the pulse stretcher output signal and generate an indicator signal, wherein the filter comprises:
a filter switch coupled to receive the pulse stretcher output signal at a first terminal, wherein a voltage at said first
terminal controls current flow from a second terminal of the filter switch to a third terminal of the filter switch;

a first filter current source supplying a fixed current to the first terminal of the filter switch;
a second filter current source connected to the third terminal of the filter switch and providing a fixed current flowing
away from said third terminal, wherein

a magnitude of the second filter current source is lower than a magnitude of the first filter current source; and
a filter comparator coupled to receive the signal present at the third terminal of the filter switch, compare it with a reference
voltage level, and output a logical “1” if the signal present at the third terminal of the filter switch is greater than the
reference voltage and wherein if the pulse stretcher output signal comprises at least a predetermined number of stretched
pulses within a predetermined amount of time, the indicator signal indicates the presence of a leading-edge phase-cut dimmer
in a circuit generating the LED driver signal; and

a loading circuit configured to receive the indicator signal and, if the indicator signal indicates the presence of a leading-edge
phase-cut dimmer, provide a constant current load to the light-emitting diode, and, if the indicator signal indicates the
absence of a leading-edge phase-cut dimmer, provide a high power factor load to the light-emitting diode.

US Pat. No. 9,305,871

HIGH PIN COUNT, SMALL PACKAGES HAVING HEAT-DISSIPATING PAD

TEXAS INSTRUMENTS INCORPO...

1. An encapsulated semiconductor device package comprising:
a metallic leadframe with a chip assembly pad;
a semiconductor chip mounted on the chip assembly pad;
an encapsulant encapsulating the leadframe and the semiconductor chip;
a first pair of oblong metal pins exposed from a surface of the encapsulant, the pins straddling a corner of the package;
each pin having a long axis, the long axes of the pair forming a non-orthogonal angle.

US Pat. No. 9,300,975

CONCURRENT ACCESS SHARED BUFFER IN A VIDEO ENCODER

TEXAS INSTRUMENTS INCORPO...

1. An apparatus, comprising:
a buffer comprising four pages in which macroblocks of video are stored;
a direct memory access (DMA) engine comprising a plurality of channels, each DMA channel to write encoded macroblocks to the
buffer;

a motion estimator to generate a motion vector for a given macroblock stored in the buffer; and
a motion compensator to use the motion vectors generated by the motion estimator to perform interpolation;
wherein, for a given time slot
a first channel of the DMA engine stores luminance and chrominance data of a first set of a predetermined number of macroblocks
of a current frame and luminance data of corresponding set of macroblocks of a reference frame in a first page of the buffer,
the predetermined number of macroblocks being less than a number of macroblocks in a frame,

the motion estimator accesses data of a second set of the predetermined number of macroblocks of the current frame stored
in a second page of the buffer, for each macroblock stored in the second page of the buffer generates a motion vector based
on a closest match for a corresponding macroblock in the reference frame from only luminance data and stores the motion vector
for each macroblock in the second page of the buffer,

a second channel of the DMA engine stores chrominance data for a set of macroblocks of a reference frame corresponding to
a third set of the predetermined number of macroblocks in a third page of the buffer overwriting luminance data of the third
set of macroblocks of the current frame stored in the third page of the buffer, and

the motion compensator accesses data of a set of macroblocks of a reference frame corresponding to a fourth set of the predetermined
number of macroblocks and motion vectors for each macroblock stored in a fourth page of the buffer, and performs interpolation
for each macroblock of the current frame from luminance and chrominance data of a corresponding macroblock of the reference
frame and a corresponding motion vector;

wherein for each following time slot the first channel of the DMA engine, the motion estimator, the second channel of the
DMA engine and the motion compensator access a next page of the buffer in a circular sequence of pages.

US Pat. No. 9,276,475

SWITCHED MODE ASSISTED LINEAR REGULATOR WITH DECOUPLED OUTPUT IMPEDANCE AND SIGNAL PATH BANDWIDTH

Texas Instruments Incorpo...

1. A switch modes assisted (SMAL) regulator for supplying a regulated load voltage and associated load current to a dynamic
load characterized by a signal bandwidth, comprising:
an amplifier circuit; and
a switched mode converter (switcher) circuit coupled in parallel at a supply node coupled to the dynamic load;
the SMAL regulator is configured to supply the regulated load voltage and the associated load current based on a signal path
bandwidth, wherein:

the amplifier circuit, in response to a dynamic input signal, supplies the regulated load voltage;
the switcher circuit, in response to a switching control signal with a switcher bandwidth that is less than the signal path
bandwidth, supplies a switcher load current based on the switcher bandwidth; and

the amplifier circuit supplies an amplifier load current corresponding to the associated load current not supplied by the
switcher load current; and

the amplifier circuit is configured with first and second negative feedback loops such that the first feedback loop is a higher
speed than the second negative feedback loop, and wherein:

the first negative feedback loop is configured to control an output impedance bandwidth of the amplifier circuit; and
the second negative feedback loop is configured to control the signal path bandwidth substantially independently of the output
impedance bandwidth;

thereby decoupling the configuration of the output impedance bandwidth from the signal path bandwidth.

US Pat. No. 9,116,769

ASIP WITH RECONFIGURABLE CIRCUITRY IMPLEMENTING ATOMIC OPERATIONS OF A PLL

TEXAS INSTRUMENTS INCORPO...

1. An application specific instruction-set processor comprising:
A. an instruction memory containing atomic application specific instructions for implementing phase locked loop computations,
the instruction memory having instruction outputs;

B. decoding circuitry having inputs coupled to the instruction memory outputs and having control outputs carrying control
signals;

C. computational circuitry having control inputs receiving control signals coupled with the decoding circuitry control outputs
and having data bus connections, the computational circuitry including arithmetic circuitry, logic circuitry, data storage
circuitry, and reconfigurable circuitry, the reconfigurable circuitry implementing an atomic operation of the phase locked
loop operation in response to control signals decoded from an atomic application specific instruction;

D. a data bus coupled to the data bus connections;
E. a register file and data memory having connections coupled to the data bus; and
F. interface circuitry having first connections coupled to the data bus and a tuning word output.

US Pat. No. 9,083,328

POSITIVE EDGE FLIP-FLOP WITH DUAL-PORT SLAVE LATCH

TEXAS INSTRUMENTS INCORPO...

1. A flip-flop circuit comprising:
a first inverter configured to receive a first data bit and output a binary logical compliment of the first data bit;
a pass gate configured to transfer the binary logical compliment of the first data bit to a master latch when a first clock
signal is a logical low value and a second clock signal is a logical high value and wherein the pass gate is configured to
not transfer the binary logical compliment of the first data bit to the master latch when the first clock signal is a logical
high value and the second clock signal is a logical low value;

the master latch configured to receive the binary logical compliment of the first data bit, the first clock signal, the second
clock signal , a first retain control signal and a second retain control signal, wherein the first clock signal, the second
clock signal, the first retain control signal, and the second retain control signal determine when a binary logical value
of the first data bit is presented on a data output of the master latch and when the data output of the master latch is latched
in the master latch;

a transfer gate wherein the transfer gate transfers data from the data output of the master latch to an output of the transfer
gate when the first clock signal transitions from a low logical value to a logical high value;

a slave latch configured to receive the output of the transfer gate, a second data bit, the first clock signal, the second
clock signal, the first retain control signal, the second retain control signal, a first slave control signal and a second
slave control signal wherein the first clock signal, the second clock signal, the first retain control signal, the second
retain control signal, the first slave control signal, and the second slave control signal determine whether the output of
the transfer gate or the second data bit is latched in the slave latch.

US Pat. No. 9,053,799

OPTIMIZING FUSEROM USAGE FOR MEMORY REPAIR

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit comprising:
a plurality of memory wrappers, each memory wrapper comprising a memory block with a fuse register and a bypass register,
the bypass register having a bypass data that is configured to indicate a defective memory wrapper of the plurality of memory
wrappers;

a fuseROM controller coupled to the plurality of memory wrappers;
a memory bypass chain configured to link the bypass registers in the plurality of memory wrappers with the fuseROM controller,
wherein the fuseROM controller is configured to load the bypass data in the memory bypass chain; and

a memory data chain configured to link the fuse registers in the plurality of memory wrappers with the fuseROM controller,
wherein the memory data chain is re-configured to link the fuse registers in a set of defective memory wrappers of the plurality
of memory wrappers responsive to the bypass data loaded in the memory bypass chain.

US Pat. No. 9,306,259

HORN ANTENNA FOR LAUNCHING ELECTROMAGNETIC SIGNAL FROM MICROSTRIP TO DIELECTRIC WAVEGUIDE

TEXAS INSTRUMENTS INCORPO...

1. A system comprising:
a multilayer substrate having multiple conductive layers separated by layers of insulation, the substrate including a horn
antenna with a narrow, waveguide portion, input end and a wider output end, the horn antenna being formed of the conductive
layers and the layers of insulation and including a top plate conductive layer, a bottom plate conductive layer, and densely
spaced vias forming vertical sidewalls of the horn antenna and waveguide portion by coupling adjacent edges of the top plate
and bottom plate, the horn antenna being trapezoidal and the waveguide portion being rectangular;

a microstrip line formed in one of the conductive layers adjacent the waveguide portion input end, the microstrip line having
a tapered portion that increases in width as it approaches the waveguide portion input end and the tapered portion not extending
into the waveguide portion; and

a ground plane formed in another one of the conductive layers at the waveguide portion input end.

US Pat. No. 9,298,643

PERFORMANCE AND POWER IMPROVEMENT ON DMA WRITES TO LEVEL TWO COMBINED CACHE/SRAM THAT IS CACHED IN LEVEL ONE DATA CACHE AND LINE IS VALID AND DIRTY

TEXAS INSTRUMENTS INCORPO...

1. A method of data processing comprising the steps of:
temporarily storing in a plurality of first level cache lines data for manipulation by a central processing unit;
storing for each first level each cache line a tag indicating a valid and a dirty status of corresponding data;
temporarily storing in a plurality of second level cache lines data for manipulation by the central processing unit;
storing for the second level cache a set of shadow tags corresponding to the tags of the first level cache;
storing data in a second level memory directly addressable by the central processing unit;
transferring data including transferring data into the second level directly addressable memory;
determining from the shadow tags if the address of a data transfer into the second level directly addressable memory is cached
in the first level cache;

if said address of said data transfer into the second level directly addressable memory is cached in the first level cache,
determining from said shadow tags if said data is valid and dirty in the first level cache, and

if said address of said data transfer into the second level directly addressable memory is cached in the first level cache
as valid and dirty, then transferring said data into a corresponding cache line in the first level cache and not into the
second level directly addressable memory.

US Pat. No. 9,299,697

HIGH BREAKDOWN VOLTAGE MICROELECTRONIC DEVICE ISOLATION STRUCTURE WITH IMPROVED RELIABILITY

TEXAS INSTRUMENTS INCORPO...

1. A microelectronic device, comprising:
a low voltage node of a high voltage component of the microelectronic device;
a high voltage node of the high voltage component;
a main dielectric at least 2 microns thick disposed between the low voltage node and the high voltage node; and
a lower-bandgap dielectric layer disposed between the main dielectric and the high voltage node, wherein:
the lower-bandgap dielectric layer comprises:
at least a first sub-layer having a bandgap energy less than a bandgap energy of a portion of the main dielectric adjacent
to the lower-bandgap dielectric layer; and

a second sub-layer disposed between the first sub-layer and the high voltage node, the second sub-layer having a bandgap energy
less than the bandgap energy of the first sub-layer;

the lower-bandgap dielectric layer extends past the high voltage node continuously around the high voltage node, by a distance
which is at least twice a thickness of the lower-bandgap dielectric layer;

an isolation break in the lower-bandgap dielectric layer so that the lower-bandgap dielectric layer is not continuous at the
isolation break, and the isolation break surrounds the high voltage node.

US Pat. No. 9,231,054

DRAIN EXTENDED CMOS WITH COUNTER-DOPED DRAIN EXTENSION

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a pn junction;
a drift region on one side of said pn junction;
where at least 10 percent of the width of said drift region consists of a concentration of a first dopant type plus a concentration
of scattering centers; and

where said concentration of said scattering centers is greater than said concentration of said first dopant type divided by
5.

US Pat. No. 9,202,883

SILICIDE FORMATION DUE TO IMPROVED SIGE FACETING

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a substrate comprising semiconductor material extending to a top surface of said substrate;
field oxide disposed in said substrate;
a first gate structure over said semiconductor material proximate to said field oxide, said first gate structure comprising:
a gate dielectric layer over said semiconductor material; and
a gate on said gate dielectric layer of said first gate structure;
a second gate structure over said field oxide, said second gate structure comprising a gate on said gate dielectric layer
of said second gate structure, such that said gate of said second gate structure does not overlap a sidewall of said field
oxide facing the first gate structure;

a silicon-germanium source/drain region in said substrate between said first gate structure and said second gate structure,
such that a top edge of a boundary between said silicon-germanium source/drain region and said field oxide does not extend
more than one third of a depth of said silicon-germanium source/drain region from a top surface of said semiconductor material;

dielectric spacers adjacent to lateral surfaces of said gate of said second gate structure, extending onto said silicon-germanium
source/drain region;

metal silicide on said silicon-germanium source/drain region; and
a contact between said first gate structure and said second gate structure, such that at least half of a bottom of said contact
directly contacts said metal silicide on said silicon-germanium source/drain region.

US Pat. No. 9,201,807

METHOD AND SYSTEM FOR MANAGING VIRTUAL MEMORY

TEXAS INSTRUMENTS INCORPO...

1. A non-transitory computer-readable medium storing a software program that, when executed by a processor, performs a method
for virtual memory management comprising:
creating a representation of a page table for a process by instantiating a page table object using a JAVA programming language
class representing a system level page table, wherein each entry of the page table representation comprises a representation
of a page descriptor and the JAVA programming language class comprises a JAVA programming language method for updating the
system level page table; and

changing a field of a page descriptor representation in the page table representation and a corresponding field in a page
descriptor of the system level page table during execution of the process when a virtual page corresponding to the page descriptors
is removed from memory and when the virtual page is placed in memory,

wherein the JAVA programming language method is executed to change the corresponding field using contents of the field in
the page descriptor representation.

US Pat. No. 9,148,580

TRANSFORMING WIDE DYNAMIC RANGE IMAGES TO REDUCED DYNAMIC RANGE IMAGES

TEXAS INSTRUMENTS INCORPO...

1. A method of transforming by a digital system an N-bit raw wide dynamic range (WDR) Bayer image to a K-bit raw red-green-blue
(RGB) image wherein N>K, the method comprising:
converting the N-bit raw WDR Bayer image to an N-bit raw RGB image;
computing a luminance image from the N-bit raw RGB image;
computing a pixel gain value for each luminance pixel in the luminance image to generate a gain map;
applying a hierarchical noise filter to the gain map to generate a filtered gain map;
applying the filtered gain map to the N-bit raw RGB image to generated a gain mapped N-bit RGB image; and
downshifting the gain mapped N-bit RGB image by (N?K) to generate the K-bit RGB image.

US Pat. No. 9,124,177

SYSTEMS AND METHODS OF SMOOTH LIGHT LOAD OPERATION IN A DC/DC CONVERTER

TEXAS INSTRUMENTS INCORPO...

1. A DC-DC converter, comprising:
a switch; and
a voltage mode controller, the controller comprising:
a rising ramp signal generator;
a falling ramp signal generator;
a falling ramp clamp configured to clamp an output of the falling ramp signal generator;
a first comparator configured to compare a rising ramp signal to an output of an error amplifier (COMP signal) for generating
an on time for controlling the switch;

a second comparator configured to compare a falling ramp signal to the COMP signal for generating an off time for controlling
the switch; and

an RS flip flop configured to receive outputs of the first comparator and the second comparator to generate a pulse width
modulation signal, wherein an output voltage from the error amplifier will be substantially constant during continuous conduction
mode and discontinuous conduction mode and wherein an output voltage is proportional to a clamp voltage during discontinuous
conduction mode.

US Pat. No. 9,419,750

NLOS WIRELESS BACKHAUL UPLINK COMMUNICATION

TEXAS INSTRUMENTS INCORPO...

1. A method for uplink (UL) wireless backhaul communication at as wireless backhaul remote unit in a radio access network
(RAN), comprising:
receiving a configuration for radio frames and a transmission schedule through a downlink (DL) physical-layer (PHY) broadcast
channel wherein each radio frame comprises a plurality of UL time slots and a plurality of DL time slots, wherein the transmission
schedule comprises a transmission allocation for the wireless backhaul remote unit, and wherein each UL time slot comprises
a plurality of symbols in time and a plurality of sub-carriers in a system bandwidth;

receiving a UL control channel parameter associated with frequency resource mapping;
selecting a first set of the sub-carriers located near a lower frequency edge of the system bandwidth and a second set of
the sub-carriers located near a higher frequency edge of the system bandwidth according to the frequency resource mapping
received in the UL control channel parameter, wherein the first set of sub-carriers and the second set of sub-carriers are
located at about a same number of sub-carriers away from a direct current (DC) sub-carrier;

generating a UL control frame, wherein generating the UL control frame comprises:
mapping a first portion of the UL control frame to the first set of sub-carriers in a first of the plurality of symbols; and
mapping a second portion of the UL control frame to the second set of sub-carriers in the first symbol; and
generating a UL data frame, wherein generating the UL data frame comprises:
performing forward error correction (FEC) encoding on a data bit stream to generate a plurality of FEC codewords, wherein
performing the FEC encoding comprises:

performing Reed Solomon (RS) encoding on the data bit stream to generate a plurality of RS codewords;
performing byte interleaving on the RS codewords;
performing Turbo encoding on the byte interleaved RS codewords to generate one or more Turbo codewords, wherein each Turbo
codeword is encoded from more than one RS codeword; and

transmitting the UL control frame and the UL data frame according to the transmission allocation.

US Pat. No. 9,397,180

LOW RESISTANCE SINKER CONTACT

TEXAS INSTRUMENTS INCORPO...

1. A method of forming a semiconductor device, comprising the steps:
providing substrate with a transistor covered by a pre-metal dielectric layer;
forming a contact pattern on the pre-metal dielectric layer with openings where contacts are to be formed;
etching contact openings through the pre-metal dielectric and forming a contact opening to a first node of the transistor;
removing the contact pattern;
forming a sinker contact pattern on the pre-metal dielectric layer with an opening where the low resistance sinker contact
is to be formed;

etching a sinker contact through the pre-metal dielectric and etching the sinker contact through a first doped layer and into
a second doped layer wherein the first doped layer and the second doped layer have the same doping type and wherein the second
doped layer is more heavily doped than the first doped layer and wherein the first doped layer and the second doped layer
form a second node of the transistor;

removing the sinker contact pattern;
depositing a barrier layer into the contact openings and into the low resistance sinker contact opening;
depositing a metallic material into and filling the contact openings and into and filling the low resistance sinker contact
opening; and

removing metallic material overfill to form contact plugs and to form a low resistance sinker contact plug.

US Pat. No. 9,379,087

METHOD OF MAKING A QFN PACKAGE

TEXAS INSTRUMENTS INCORPO...

1. A method of making a plated leadframe comprising:
providing a first film layer on a first side of a metal plate;
providing a second film layer on a second side of the metal plate opposite the first side;
photo etching the first film layer in a predetermined pattern that exposes portions of the first side of the metal plate;
chemical etching the exposed portions of the first side of the metal plate to produce a plurality of leads;
removing the first film layer from the plurality of leads;
plating first side surfaces of the plurality of leads;
applying an adhesive tape to the plated first side surfaces of the plurality of leads;
removing the second film layer from the second side surface of the plurality of leads;
masking the second side surfaces of the plurality of leads; and
plating the second side surfaces of the plurality of leads.

US Pat. No. 9,356,117

METHOD FOR FORMING AVALANCHE ENERGY HANDLING CAPABLE III-NITRIDE TRANSISTORS

TEXAS INSTRUMENTS INCORPO...

1. A method of forming a semiconductor device, comprising the steps of:
forming a GaN FET by a process comprising the steps of:
providing a substrate;
forming an low-defect layer comprising gallium nitride over said substrate;
forming a barrier layer comprising AlxGa1?xN on said low-defect layer, so that a two-dimensional electron gas is generated in said low-defect layer just below said barrier
layer, said two-dimensional electron gas providing a conductive channel of said GaN FET;

forming a gate over said barrier layer; and
forming source and drain contacts to make tunneling connections to said two-dimensional electron gas;
forming an overvoltage clamping component, and electrically coupling a first end of said overvoltage clamping component to
a drain node of said GaN FET, said overvoltage clamping component being configured to conduct insignificant current when a
voltage at said drain node is less than a safe voltage limit which is less than a breakdown voltage of said GaN FET; said
overvoltage clamping component being further configured to conduct significant current when said voltage at said drain node
of said GaN FET rises above said safe voltage limit;

forming a voltage dropping component, electrically coupling a first end of said voltage dropping component to a second end
of said overvoltage clamping component, and electrically coupling a second end of said voltage dropping component to a terminal
for a bias potential which provides an off-state bias for said GaN FET, said voltage dropping component being configured to
provide a voltage drop which increases as current from said overvoltage clamping component increases; and

configuring said semiconductor device to turn on said GaN FET when said voltage drop across said voltage dropping component
reaches a threshold value.

US Pat. No. 9,325,241

DEAD-TIME COMPENSATION IN A POWER SUPPLY SYSTEM

TEXAS INSTRUMENTS INCORPO...

1. A power supply circuit comprising:
a pulse-width modulation (PWM) circuit configured to generate a PWM signal including a first PWM pulse during a first time
period and a second PWM pulse during a second time period after the first time period, the first PWM pulse having a first
PWM pulse width, the second PWM pulse having a second PWM pulse width;

a power stage coupled with the PWM circuit, the power stage configured to generate an activation signal for switching an output
signal corresponding to the first PWM pulse during the first time period; and

a delay circuit coupled between the PWM circuit and the power stage, the delay circuit configured to:
measure an activation dead-time by comparing the first PWM pulse with the output signal during the first time period; and
generate a control signal having an adjusted pulse width based on the second PWM pulse width and the measured activation dead-time,
the control signal causing the power stage to prolong the activation signal during the second time period.

US Pat. No. 9,245,755

DEEP COLLECTOR VERTICAL BIPOLAR TRANSISTOR WITH ENHANCED GAIN

TEXAS INSTRUMENTS INCORPO...

1. A process of forming an integrated circuit, comprising the steps:
providing a substrate wafer with a first doping type;
implanting a first implant of a second doping type to form a deep well in the substrate wafer wherein the deep well forms
a collector of a deep collector vertical bipolar transistor;

implanting a second implant of the second doping type to form a first well in the substrate wafer wherein the first well contacts
the deep well and electrically isolates a base region of the deep collector vertical bipolar transistor from the substrate;

implanting the second implant to form a second well in the substrate wherein the second well forms a body of a MOS transistor;
forming a MOS transistor gate dielectric;
forming a MOS transistor gate on the MOS transistor gate dielectric;
implanting a third implant of the second doping type to form source and drain diffusions self aligned to the MOS transistor
gate;

implanting the third implant to form an emitter of the deep collector vertical bipolar transistor;
implanting a fourth implant of the first doping type to form a first base tuning diffusion within the base of the deep collector
vertical bipolar transistor; and

implanting the fourth implant to form a second base tuning diffusion under the gate of the MOS transistor gate and under the
source and drain diffusions.

US Pat. No. 9,169,974

MULTIPLE-CAVITY VAPOR CELL STRUCTURE FOR MICRO-FABRICATED ATOMIC CLOCKS, MAGNETOMETERS, AND OTHER DEVICES

TEXAS INSTRUMENTS INCORPO...

1. An apparatus comprising:
a vapor cell having:
a first cavity configured to receive a first material;
a second cavity fluidly connected to the first cavity by a first channel, the second cavity configured to receive one or more
gases dissociated from the first material and allow radiation to pass through; and

a third cavity fluidly connected to one of the first cavity or the second cavity by a second channel, the third cavity configured
to receive a second material for absorbing a portion of the one or more gases dissociated from the first material.

US Pat. No. 9,160,330

BOOST CAPACITOR SHARING ARCHITECTURE FOR POWER SUPPLY ACTIVE BALANCING SYSTEMS

TEXAS INSTRUMENTS INCORPO...

8. A system comprising:
a first boost capacitor;
a second boost capacitor; and
boost capacitor sharing circuitry that includes multiple first channels coupled to the first boost capacitor and multiple
second channels coupled to the second boost capacitor;

wherein each channel includes a transistor switch and a gate driver configured to drive the transistor switch;
wherein the gate drivers in the first channels include switch sub-arrays configured to control which transistor switch in
the first channels is driven using a voltage from the first boost capacitor; and

wherein the gate drivers in the second channels include switch sub-arrays configured to control which transistor switch in
the second channels is driven using a voltage from the second boost capacitor.

US Pat. No. 9,152,520

PROGRAMMABLE INTERFACE-BASED VALIDATION AND DEBUG

TEXAS INSTRUMENTS INCORPO...

1. A test fixture, comprising:
a test connector that is arranged to communicatively couple a design under test to the test fixture, said test connector including
a shared test bus coupled to a first set of selected pins; and

a programmable logic interface that is communicatively coupled to the test connector and is arranged to receive a downloadable
test bench, wherein the downloadable test bench is arranged to apply test vectors from a first set of test vectors to a first
test control bus;

a multiplexer that is arranged to selectively couple one of the first test control bus and a second test control bus to the
shared test bus, wherein the second test control bus is arranged to apply test vectors from a second set of test vectors.

US Pat. No. 9,104,217

ELECTRONIC DEVICE AND METHOD FOR GENERATING A CURVATURE COMPENSATED BANDGAP REFERENCE VOLTAGE

TEXAS INSTRUMENTS INCORPO...

1. An electronic device having a bandgap reference generator comprising:
a first bipolar transistor having a base coupled to ground, a first collector-emitter channel terminal and a second collector-emitter
channel terminal coupled to ground;

a first resistor having a first terminal connected to said first collector-emitter channel terminal of said first bipolar
transistor and a second terminal connected to a first common resistor node;

a second resistor having a third terminal connected to said first common resistor terminal and a fourth terminal connected
to a second common resistor node;

a second bipolar transistor having a base coupled to ground, a third collector-emitter channel terminal and a fourth collector-emitter
channel terminal coupled to ground;

a third resistor having a fifth terminal connected to said third collector-emitter channel terminal of said second bipolar
transistor and a sixth terminal connected to said second common resistor node;

a fourth resistor having a seventh terminal connected to said second common resistor node, said seventh terminal being an
output of the bandgap reference generator, and an eighth terminal;

a MOS transistor having a ninth terminal of a source-drain channel connected to a power supply, a tenth terminal of said source-drain
channel connected to said eighth terminal of said fourth resistor and a gate;

an amplifier having a inverting input connected to said first common resistor node, a noninverting input connected to said
third collector-emitter channel terminal of said second bipolar transistor and to said fifth terminal of said third resistor,
and an output connected to said gate of said MOS transistor; and

a curvature compensation stage having an input connected to said second common resistor node drawing a compensation current
into said input and out of said second common resistor node in an amount compensating for a variation of base emitter voltage
variation of said first and second bipolar transistors.

US Pat. No. 9,603,141

PHYSICAL DOWNLINK CONTROL CHANNEL AND PHYSICAL HYBRID AUTOMATIC REPEAT REQUEST INDICATOR CHANNEL ENHANCEMENTS

TEXAS INSTRUMENTS INCORPO...

1. A method of operating a user equipment (UE), comprising:
receiving a downlink (DL) assignment on a Demodulation Reference Signal (DMRS)-based physical downlink control channel (D-PDCCH)
and if the user equipment (UE) detects via physical control format indicator channel (PCFICH) on its legacy control region
that the number of OFDM symbols is strictly smaller than the starting symbol for D-PDCCH, then the user equipment (UE) shall
assume one of the two following embodiments for determining the resources on which its PDSCH is mapped:

when the DL-assignment on D-PDCCH overlaps with the DL assignment for PDSCH, the user equipment (UE) assumes that in the overlapping
PRBs, the PDSCH is also present on the OFDM symbols between the last symbol of the legacy PDCCH region and the first symbol
of the D-PDCCH; and

when the DL-assignment on D-PDCCH overlaps with the DL assignment for PDSCH, the user equipment (UE) assumes that its PDSCH
is also present on the OFDM symbols between the last symbol of the legacy PDCCH region and the first symbol of the D-PDCCH.

US Pat. No. 9,450,651

INDUCTIVE STRUCTURES WITH IMPROVED COMMON MODE TRANSIENT IMMUNITY

TEXAS INSTRUMENTS INCORPO...

1. A device, comprising:
a first inductive structure including a first data coil, wherein: a first portion of the first data coil is for conducting
a first common mode current in a first direction; a second portion of the first data coil is for conducting a second common
mode current in a second direction opposite the first direction; the first portion of the first data coil is connected at
a first node to the second portion of the first data coil; and the first node is coupled to a first ground; and

a second inductive structure including a second data coil, wherein: a first portion of the second data coil is aligned with
the first portion of the first data coil for conducting a third common mode current in the first direction; a second portion
of the second data coil is aligned with the second portion of the first data coil for conducting a fourth common mode current
in the second direction; the first portion of the second data coil is connected at a second node to the second portion of
the second data coil; the second node is coupled to a second ground galvanically isolated from the first ground; and the first,
second, third and fourth common mode currents are induced by a common mode transient that occurs with respect to the first
and second grounds;

wherein the first and second portions of the first data coil are coupled to: receive data from a transmitter; and output the
data by inductive coupling to the second data coil; and

wherein the first and second portions of the second data coil are coupled to: receive data by inductive coupling from the
first data coil; and output the data to a receiver.

US Pat. No. 9,414,104

GRAPHICS INITIALIZATION FOR WIRELESS DISPLAY DEVICES

TEXAS INSTRUMENTS INCORPO...

1. A wireless display device operable to receive image data from a player programmed to transform image data in accordance
with display device parameters, the display device comprising
a transmitter operable to transmit information describing a rendering capability of the display device to the player via a
wireless link;

a receiver operable to receive image data transformed using the transmitted information from the player via the wireless link;
a processing system operable to interpret the received image data, thereby generating pixel data;
a frame buffer operable to store the generated pixel data; and
a display engine operable to receive the stored pixel data from the frame buffer and to render a display on the basis of the
stored pixel data.

US Pat. No. 9,368,355

SYSTEM AND METHOD FOR MITIGATING OXIDE GROWTH IN A GATE DIELECTRIC

TEXAS INSTRUMENTS INCORPO...

21. A method for forming a device structure on a substrate, comprising:
introducing the substrate to a processing system by transferring the substrate through a load lock to a distinct transfer
chamber, the transfer chamber having a gas distribution system in fluid communication with the transfer chamber and a first
pumping element connected to the transfer chamber;

transferring the substrate from the transfer chamber to a first process chamber having a distinct, second pumping element;
forming a dielectric layer on the substrate in the first process chamber;
transferring the substrate from the first process chamber to a second process chamber through the transfer chamber while maintaining
the transfer chamber at a pressure of 3 Torr to 200 Torr while actively purging the transfer chamber with N2 at a flow rate of 2 liters per minute to 7 liters per minute using the gas distribution system and the first pumping element,
the second process chamber having a distinct third pumping element;

introducing nitrogen atoms in a top surface of the dielectric layer in the second process chamber while the third pumping
element provides a pressure of 5 mTorr to 50 Torr in the second process chamber;

transferring the substrate from the second process chamber to a third process chamber through the transfer chamber while maintaining
the transfer chamber at a pressure less than 760 Torr while actively purging the transfer chamber with N2 at a flow rate of 2 liters per minute to 7 liters per minute using the gas distribution system and the first pumping element,
the third process chamber having a distinct fourth pumping element; and

performing a thermal process in the third process chamber while the fourth pumping element provides a pressure of 0.5 Torr
to 50 Torr in the third process chamber.

US Pat. No. 9,331,680

LOW POWER CLOCK GATED FLIP-FLOPS

TEXAS INSTRUMENTS INCORPO...

1. A flip-flop comprising:
a multiplexer configured to generate a multiplexer output to a transmission gate, in response to at least one input and a
scan enable;

a master latch configured to receive an output of the transmission gate;
a tri-state inverter configured to receive an output of the master latch;
a slave latch configured to receive an output of the tri-state inverter and the multiplexer output;
a data inverter coupled to an output of the slave latch, configured to generate a flip-flop output; and
a half clock gating inverter configured to generate an inverted clock input in response to a clock input and the multiplexer
output.

US Pat. No. 9,303,953

DIGITAL SYSTEM FOR THE DETECTION OF VARIATIONS IN OPERATING CONDITIONS OF AN INTEGRATED CIRCUIT

TEXAS INSTRUMENTS INCORPO...

1. A tamper detection system comprising:
a launch clock replica circuit receiving a clock signal at an input and generating a launch clock signal at an output;
a waveform generator register having a latch input connected to said output of said launch clock replica, an input and an
output;

an inverter having an input connected to said output of said waveform generator and an output connected to said input of said
waveform generator;

a critical path replica circuit having an input connected to said output of said waveform generator and an output, said critical
path replica circuit having a delay corresponding to a delay of a critical path of a circuit to be protected;

a variable delay circuit having an input connected to said output of said critical path replica circuit and an output, said
variable delay circuit having a specified delay;

a capture clock replica circuit receiving a clock signal at an input and generating a capture clock signal at an output;
a register having a latch input connected to said output of said capture clock replica circuit, an input connected to said
output of said variable delay circuit and an output;

an exclusive NOR gate having a first input connected to said output of said waveform generator, a second input connected to
said output of said register and an output;

a counter having an enable input connected to said output of said exclusive NOR gate, a clock input connected to said output
of said capture clock replica circuit and an overflow output, said counter counting clock signals at said clock input when
said exclusive NOR indicates said output of said waveform generator does not match said output of said register and generating
an overflow signal at said overflow output indicating tampering upon overflow.

US Pat. No. 9,287,876

FULLY AUTOMATED. HIGH THROUGHPUT, CONFIGURABLE DIGITAL DESIGN INTERNAL FUNCTIONAL NODE PROBING MECHANISM AND METHOD

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:
a first functional logic block having a first functional block first output line and a first function block second output
line;

a second functional logic block having a second functional block first output line and a second function block second output
line;

a third functional logic block having a third functional block first output line and a third function block second output
line;

a fourth functional logic block having a fourth functional block first output line and a fourth function block second output
line;

a first level of multiplexers comprising a first first-level multiplexer, a second first-level multiplexer, a third first-level
multiplexer and a fourth first-level multiplexer, the first first-level multiplexer comprising a first two selectable inputs
and a first output, the second first-level multiplexer comprising a second two selectable inputs and a second output, the
third first-level multiplexer comprising a third two selectable inputs and a third output, the fourth first-level multiplexer
comprising a fourth two selectable inputs and a fourth output, one of the first two selectable inputs being connected to the
first functional block first output line, the other of the first two selectable inputs being connected to the first function
block second output line, one of the second two selectable inputs being connected to the second functional block first output
line, the other of the second two selectable inputs being connected to the second function block second output line, one of
the third two selectable inputs being connected to the third functional block first output line, the other of the third two
selectable inputs being connected to the third function block second output line, one of the fourth two selectable inputs
being connected to the fourth functional block first output line, the other of the fourth two selectable inputs being connected
to the fourth function block second output line,

a second level of multiplexers comprising a first second-level multiplexer and a second second-level multiplexer, the first
second-level multiplexer comprising a fifth two selectable inputs and a fifth output, the second first-level multiplexer comprising
a sixth two selectable inputs and a sixth output; and

a digital counter comprising a first select output and a second select output, the first select output being operable to provide
a first select signal to the first first-level multiplexer, to the second first-level multiplexer, to the third first-level
multiplexer and to the fourth first-level multiplexer, the second select output being operable to provide a second select
signal to the first second-level multiplexer and to the second second-level multiplexer.

US Pat. No. 9,264,217

CLOCK DRIFT COMPENSATION APPLYING PAIRED CLOCK COMPENSATION VALUES TO BUFFER

TEXAS INSTRUMENTS INCORPO...

1. A process for clock drift compensation comprising:
storing data in a buffer circuit based on a clock rate for the buffer circuit,
the clock rate for the buffer circuit regulating the amount of data stored in the buffer circuit to prevent overflow or underflow
of the data stored in the buffer circuit;

monitoring the buffer circuit for a buffer fullness status that indicates an amount of data stored in the buffer circuit;
when the monitored buffer fullness status is above a certain threshold, applying a first of two paired clock drift compensation
values to the clock rate for the buffer circuit;

when the monitored buffer fullness status is below the certain threshold, applying a second of the two paired clock drift
compensation values to the clock rate for the buffer circuit: and

determining a difference between a buffer read clock value and a buffer write clock value; and
adjusting the two paired clock drift compensation values applied to the clock rate for the buffer circuit based on the difference.

US Pat. No. 9,257,341

METHOD AND STRUCTURE OF PACKAGING SEMICONDUCTOR DEVICES

TEXAS INSTRUMENTS INCORPO...

1. A semiconductor device comprising:
a semiconductor chip having a first chip surface with metallized terminals, and a parallel second surface;
a frame of insulating material adhering to the sidewalls of the semiconductor chip, the frame having a first surface planar
with the first chip surface and a parallel second surface planar with the second chip surface, the first frame surface including
one or more embedded metallic fiducials extending from the first frame surface into the insulating material; and

at least one film of sputtered metal extending from the terminals across the surface of a polymeric layer to the fiducials,
the film patterned to form extended contact pads over the frame and rerouting traces between the chip terminals and the extended
contact pads, the film adhering to the surfaces;

wherein the metallic fiducials extend from the first frame surface to the parallel second frame surface planar with the second
chip surface, conductively connecting the first and the second surface.

US Pat. No. 9,252,792

TUNABLE FREQUENCY-TO-VOLTAGE CONTROLLED OSCILLATION

TEXAS INSTRUMENTS INCORPO...

1. An oscillator, comprising:
a digital-to-analog converter that is arranged to receive a tuning code, to select one or more individual capacitors in a
capacitor bank in response to the received tuning code, and to generate a frequency control signal in response to the selected
one or more individual capacitors in the capacitor bank and in response to one or more phase control signals;

an amplifier that is arranged to generate an integrated control signal in response to the frequency control signal and in
response to a selected current;

an oscillator that is arranged to generate an output frequency signal in response to the integrated control signal; and
a clock generator that is arranged to generate the one or more phase control signals in response to the output frequency signal;
wherein the capacitor bank is a split capacitor bank that includes a higher-weight capacitor bank, a bridge capacitor, and
a lower-weight capacitor bank, wherein a first terminal of the bridge capacitor is coupled to a first terminal of each of
the individual capacitors of the higher-weight capacitor bank, and wherein a second terminal of the bridge capacitor is coupled
to a first terminal of each of the individual capacitors of the lower-weight capacitor bank;

wherein the split capacitor bank is arranged to couple a voltage reference signal to the first terminal and a second terminal
of each individual capacitor in the higher-weight capacitor bank during a first phase that is determined by the one or more
phase control signals, to couple the voltage reference signal to the first terminal of the bridge capacitor during the first
phase, and to couple the voltage reference signal to a second terminal of each individual capacitor in the lower-weight capacitor
bank during the first phase.

US Pat. No. 9,176,203

APPARATUS AND METHOD FOR IN SITU CURRENT MEASUREMENT IN A CONDUCTOR

TEXAS INSTRUMENTS INCORPO...

1. A conductor apparatus, comprising:
a conductive structure operative to conduct current along a longitudinal direction, the conductive structure comprising an
outer periphery extending between first and second longitudinal ends; and

a magnetometer, comprising:
an array of at least two magnetic sensors located on a single integrated circuit at least partially within the outer periphery
of the conductive structure, the array of at least two magnetic sensors including:

first and second circular magnetic sensors, the first and second circular sensors individually having an associated circular
sensing direction transverse to the longitudinal direction of the conductive structure and individually surrounding the point
along the first side of the magnetometer, wherein the first and second circular sensors are concentric of different diameters,

a sensor interface circuit operatively coupled to the magnetic sensors to generate at least one output signal or value representing
longitudinal current flow in the conductive structure based at least partially on at least one signal from the magnetic sensors,
and

a plurality of wires electrically connected to the sensor interface circuit and extending outside the outer periphery of the
conductive structure.

US Pat. No. 9,137,862

SLEW RATE CONTROLLED TRANSISTOR DRIVER

TEXAS INSTRUMENTS INCORPO...

1. An electronic circuit comprising:
a slew rate controlled transistor driver circuit operable to drive a transistor and configured to generate a transistor driver
signal that rises substantially in step fashion until reaching a first threshold voltage level, whereupon the transistor driver
signal rises at a controlled slew rate, comprising a slew rate controlled gate driver circuit operable to drive a gate of
a field effect transistor and configured to generate a gate control signal that rises substantially in step fashion until
reaching a first threshold voltage level, whereupon the gate control signal rises at a controlled slew rate;

further comprising an LED dimmer circuit comprising:
a field effect transistor whose gate is coupled to receive the gate control signal from the slew rate controlled gate driver
circuit;

a light emitting diode whose anode is coupled to the drain of the field effect transistor and whose cathode is coupled to
the source of the field effect transistor; and

a current source coupled to supply current to the drain of the field effect transistor and the anode of the light emitting
diode.

US Pat. No. 9,112,916

SYSTEMS AND METHODS FOR CONSTRUCTION OF AND NETWORK CODING USING NEAR-MAXIMUM DISTANCE SEPARABLE (MDS) LINEAR NETWORK CODES

TEXAS INSTRUMENTS INCORPO...

1. A method for network coding using a near-maximum distance separable linear network code, comprising:
generating, by a processor, a message matrix wherein each column of the message matrix corresponds to one of K message packets
and each element in a column of the message matrix corresponds to one of the symbols of the corresponding message packet;

generating, by the processor, a network code matrix to map the K message packets to N encoded packets, wherein any combination
of K+1 columns of the network code contains at least K columns that are linearly independent; and

multiplying, by the processor, the message matrix by the network code matrix to generate a transmission matrix, wherein each
column of the transmission matrix corresponds to an encoded packet for wireless transmission;

sending by the processor the resulting encoded packets to a physical layer of a wireless transmitter for transmission using
an existing underlying wireless communication protocol without modification.

US Pat. No. 9,099,998

POSITIVE EDGE PRESET RESET FLIP-FLOP WITH DUAL-PORT SLAVE LATCH

TEXAS INSTRUMENTS INCORPO...

1. A flip-flop circuit comprising:
a multiplexer configured to receive a first data bit (D1), a scan data bit (SD), a scan enable control signal (SE) and a binary logical compliment signal (SEN) of the scan enable
control signal (SE), wherein the scan enable control signals (SE) and (SEN) determine whether a data output (MXO) of the multiplexer
is the binary compliment of data bit (D1) or the binary compliment of scan data bit (SD);

a master latch configured to receive the data output (MXO) of the multiplexer, a first clock signal (CKT), a second clock
signal (CLKZ), a retain control signal (RET), a binary logical compliment signal (RETN) of the retain control signal (RET),
a reset signal (RE) and a preset signal (PREN), wherein the signals (CKT), (CLKZ), (RET), (RETN), (RE) and (PREN) determine
when the binary logical value of the data output (MXO) is presented on an output (MLO) of the master latch and when the output
(MLO) of the master latch is latched in the mater latch;

a transfer gate wherein the transfer gate transfers data from the output (MLO) of the master latch to an output of the transfer
gate when the first clock signal (CKT) transitions from a low logical value to a logical high value; wherein the transfer
gate transfers data from the output (MLO) of the master latch to the output of the transfer gate when signal PREN transitions
from an logical one to a logical zero; wherein the transfer gate transfers data from the output (MLO) of the master latch
to the output of the transfer gate when the signal RE transitions from an logical zero to a logical one;

a slave latch configured to receive the output of the transfer gate, a second data bit (D2), the first clock signal (CKT), the second clock signal (CLKZ), the retain control signal (RET), the binary logical compliment
signal (RETN) of the retain control signal (RET), a slave control signal (SS) and a binary logical compliment signal (SSN)
of the slave control signal (SS) wherein the signals (CKT), (CLKZ), (RET), (RETN), (SS) and (SSN) determine whether the output
of the transfer gate or the second data bit (D2) is latched in the slave latch; wherein the output of the transfer gate is (QN).

US Pat. No. 9,392,662

SYSTEMS AND METHODS OF LED COLOR OVERLAP

TEXAS INSTRUMENTS INCORPO...

1. A device comprising:
a controller module configured to control a single switching regulator, to be connected to a single inductor, and to be connected
to a plurality of light emitting diodes (LEDs), the LEDs emitting a plurality of individual colors, the controller further
configured to drive at least two of the plurality of LEDs simultaneously to achieve a color not supplied by an individual
LED of the plurality of LEDs, wherein the controller comprises a switching regulator configured to supply power to the plurality
of LEDs and further comprising a green LED and a blue LED configured in parallel, the green LED and blue LED configured in
series with a red LED.

US Pat. No. 9,347,991

SCAN THROUGHPUT ENHANCEMENT IN SCAN TESTING OF A DEVICE-UNDER-TEST

Texas Instruments Incorpo...

1. A test system for scan testing a device-under-test (DUT), the DUT comprising P scan input ports and Q scan output ports,
the test system comprising:
a tester configured to operate at a clock frequency F1, the tester comprising:

M tester Input/Output (I/O) ports for providing M scan inputs at the clock frequency F1; and

N tester I/O ports for receiving N scan outputs at the clock frequency F1; and

an adapter module coupled to the tester, the adapter module configured to:
receive the M scan inputs at the clock frequency F1 and provide P scan inputs at a clock frequency F2 to the P scan input ports of the DUT, the P scan inputs provided in response to the M scan inputs; and

receive Q scan outputs at the clock frequency F2 from the Q scan output ports of the DUT and provide the N scan outputs at the clock frequency F1 to the N tester I/O ports of the tester, the N scan outputs provided in response to the Q scan outputs,

wherein a ratio of M to P is equal to a ratio of N to Q, and wherein each of M, N, P and Q is a positive integer.

US Pat. No. 9,185,421

SYSTEM AND METHOD FOR VIDEO TRANSCODING

TEXAS INSTRUMENTS INCORPO...

1. A video transcoding system, comprising:
a video decoder configured to decode a received video signal;
a video encoder configured to encode video data decoded from the received video signal by the video decoder;
a video interface coupling an output of the video decoder to an input of the video encoder, the video interface configured
to transfer video data having a first chroma subsampling ratio;

wherein the video decoder is further configured to:
provide video data to the video interface at a second chroma subsampling ratio that includes fewer chrominance samples than
specified by the first chroma sampling ratio; and

provide non-video information generated from decoding the received video signal to the video interface using video interface
bandwidth usable based on a difference between the first chroma subsampling ratio and the second chroma subsampling ratio.

US Pat. No. 9,170,956

SYSTEM AND METHOD FOR VIRTUAL HARDWARE MEMORY PROTECTION

TEXAS INSTRUMENTS INCORPO...

1. A memory protection unit, comprising:
hardware logic to:
receive a transaction from a virtual central processing unit (CPU) directed at a bus slave, the transaction being associated
with a virtual CPU identification (ID) indicating a safety level of the transaction, wherein the virtual CPU is implemented
on a physical CPU; and

determine whether to grant or deny access to the bus slave based on the safety level indicated by the virtual CPU ID;
wherein the virtual CPU ID is different than an ID of the physical CPU on which the virtual CPU is implemented.

US Pat. No. 9,860,876

BEST-EFFORT SCHEDULED ACCESS

TEXAS INSTRUMENTS INCORPO...

1. A method, comprising:
sending a bilink request from a first device to a second device, the bilink request specifying the first device's bilink allocation
requirements;

receiving a bilink assignment at the first device from the second device, the bilink assignment specifying a tentative assignment
of a bilink allocation to the first device, wherein the tentative assignment of the bilink allocation will be available if
the network of the hub still has enough bandwidth when the scheduled time arrives and will be shifted or reduced if the network
of the hub does not have enough bandwidth when the scheduled time arrives;

monitoring transmissions from the second device on a channel at the first device in preparation for being provided by the
second device with bilink allocation intervals of the bilink allocation; and

receiving a first frame from the second device at the first device for each bilink allocation interval of the bilink allocation,
the first frame starting a bilink allocation interval provided to the first device.

US Pat. No. 9,460,720

POWERING-UP AFE AND MICROCONTROLLER AFTER COMPARING ANALOG AND TRUNCATED SOUNDS

TEXAS INSTRUMENTS INCORPO...

1. A process of operating a sound recognition system comprising:
(a) placing an analog front end channel and a microcontroller in a low power mode;
(b) receiving analog sound signals in signal trigger logic;
(c) comparing the analog sound signals to a reference voltage and producing a sound detected control signal from the signal
trigger logic when an analog sound signal exceeds the reference voltage;

(d) powering up the analog front end channel in response to the sound detected control signal while maintaining the microcontroller
in a low power mode;

(e) pre-screening the analog sound signals in the analog front end channel including comparing a truncated version of the
analog sound signals to stored truncated sound signatures and producing an event trigger signal from the analog front end
upon detecting a match of a truncated version of the analog sound signal and a stored truncated sound signature; and

(f) powering up the microcontroller in response to the event trigger signal.

US Pat. No. 9,407,249

SYSTEM AND METHOD FOR PULSE WIDTH MODULATION

TEXAS INSTRUMENTS INCORPO...

1. A circuit for use with a pulse width modulated signal having first pulse and a second pulse, the first pulse having a period
and first duty cycle, the second pulse having the period and a second duty cycle, the period having clock information therein,
the first duty cycle having first data information therein, the second duty cycle having second data information therein,
said circuit comprising:
a first integrating component operable to generate a first voltage corresponding to the first duty cycle and a second voltage
corresponding to the first duty cycle;

a second integrating component operable to generate a third voltage corresponding to the second duty cycle and a fourth voltage
corresponding to the second duty cycle;

an output component operable to output a first data bit corresponding to the first voltage and the second voltage and to output
a second data bit corresponding to the third voltage and the fourth voltage; and

a controlling component operable to control said first integrating component to eliminate the first voltage and the second
voltage when said second integrating component generates the third and fourth voltage.

US Pat. No. 9,258,107

LOCAL OSCILLATOR PHASE NOISE TRACKING FOR SINGLE CARRIER TRANSMISSION

TEXAS INSTRUMENTS INCORPO...

1. A decision-directed phase lock loop for correcting phase error in a received signal, comprising:
a first buffer configured to store a block of input symbols, the block of input symbols starting with a first pilot symbol
and ending with a last pilot symbol;

a phase rotator configured to apply a phase-noise compensation to the block of input symbols on a symbol-by-symbol basis;
a feedback loop coupled to the phase rotator, the feedback loop providing a phase-noise compensation signal to the phase rotator;
a first output buffer configured to store a first block of phase-noise-compensated symbols output from the phase-rotator,
where the symbols in the first block of phase-noise-compensated symbols are sequentially received from the phase rotator starting
with the first pilot symbol;

a second output buffer configured to store a second block of phase-noise-compensated symbols output from the phase-rotator,
where the symbols in the second block of phase-noise-compensated symbols are sequentially received from the phase rotator
starting with the last pilot symbol; and

a combiner configured to combine associated symbols from the first and second blocks of phase-noise-compensated symbols to
create output symbols, wherein the associated symbols from the first and second blocks of phase-noise-compensated symbols
are combined using a process selected from the group consisting of:

weighted symbol-by-symbol combining using a Log-Likelihood Ratio (LLR) metric; and
weighted symbol-by-symbol combining using a Minimum-Mean-Square Error (MMSE) error metric.

US Pat. No. 9,184,226

EMBEDDED TUNGSTEN RESISTOR

TEXAS INSTRUMENTS INCORPO...

1. An integrated circuit, comprising:
a well;
a silicide active geometry in said well where said silicide active geometry forms a Schottky diode to said well;
a tungsten resistor formed on said silicide active geometry;
two parallel polysilicon leads whose length is equal to or greater than a body of said tungsten resistor; and
sidewall dielectric on vertical sidewalls of said parallel polysilicon leads;
where said body of said tungsten resistor lies between said parallel polysilicon leads, where a width of said tungsten resistor
is defined by a spacing between said parallel polysilicon leads and where said sidewall dielectric prevents said tungsten
resistor from shorting to said parallel polysilicon leads.

US Pat. No. 9,088,158

REVERSE VOLTAGE CONDITION PROTECTION IN A POWER SUPPLY SYSTEM

TEXAS INSTRUMENTS INCORPO...

1. A power supply system comprising:
a power switch device that is activated to provide an output voltage to a load in response to an input voltage, the power
switch device comprising a control terminal and a bulk connection;

a reverse voltage control circuit configured to couple the input voltage to one of the control terminal and the bulk connection
in response to a reverse voltage condition in which an amplitude of the input voltage becomes negative; and

an output shutoff circuit configured to couple the output voltage to a neutral-voltage rail during the reverse voltage condition.

US Pat. No. 9,331,520

INDUCTIVELY COUPLED CHARGER

TEXAS INSTRUMENTS INCORPO...

1. A device, comprising:
a charge controller to regulate an output voltage for charging a battery based on an input voltage and an input current received
from an inductively coupled charging circuit, the charge controller regulating the output voltage based on a selected one
of a plurality of references;

a loop controller that monitors at least one of the input voltage or the input current to generate a feedback signal to the
inductively coupled charging circuit to adjust the input voltage;

wherein the loop controller is a first loop controller that provides a first feedback signal to the inductively coupled charging
circuit based on the input voltage relative to a voltage reference, the device further comprising a second loop controller
configured to provide a second feedback signal to the inductively coupled charging circuit to regulate the input current based
on the input current relative to the selected reference;
wherein the inductively coupled charging circuit is configured to execute a control algorithm to process the first feedback
signal and the second feedback signal to adjust the input voltage to the charge controller; andfurther comprising a selection controller configured to select at least one of the plurality of references that is utilized
by the charge controller and the second loop controller.

US Pat. No. 9,395,412

INVERTED TCK CONTROLLER, UPDATE REGISTER ADDRESS/SELECT OUTPUT TO SHIFT REGISTER

Texas Instruments Incorpo...

1. A falling edge controller comprising:
A. a controller having an inverted TCK (Test Clock) input, a TMS (Test Mode Select) input, a shift register control output,
an update register control output, and a shift output;

B. a shift register having a TDI (Test Data In) input, a shift register control input coupled to the shift register control
output, address inputs, a select input, address and select outputs, and a TDO (Test Data Out) output;

C. an update register having address and select inputs coupled to the address and select outputs, an update register control
input coupled to the update register control output, address outputs coupled to the address inputs of the shift register,
and a select output coupled to the select input of the shift register; and

D. address circuitry having address inputs coupled to the address outputs, and having an enable output.