US Pat. No. 9,129,918

SYSTEMS AND METHODS FOR ANNEALING SEMICONDUCTOR STRUCTURES

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor structure, the method comprising:
providing a semiconductor structure;
providing an energy-converting material capable of increasing the semiconductor structure's absorption of microwave radiation;
providing a heat reflector between the energy-converting material and the semiconductor structure, the heat reflector being
capable of reflecting thermal radiation from the semiconductor structure; and

applying microwave radiation to the energy-converting material and the semiconductor structure to anneal the semiconductor
structure for fabricating semiconductor devices.

US Pat. No. 9,397,129

DIELECTRIC FILM FOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array comprising one or more photodiodes configured to detect light;
a calibration region configured to define a color level for image reproduction, the calibration region formed laterally spaced
apart from the photodiode array;

a dielectric layer formed over and in direct contact with the photodiode array; and
a dielectric film formed over the photodiode array and the calibration region and in contact with the dielectric layer, the
dielectric film having a substantially planar bottom surface extending over the photodiode array and the calibration region.

US Pat. No. 9,147,702

IMAGE SENSOR FOR MITIGATING DARK CURRENT

Taiwan Semiconductor Manu...

16. An image sensor for mitigating dark current, comprising:
a first region comprising a first doping type;
a second region comprising a second doping type, the second doping type opposite of the first doping type, the first region
surrounded by the second region;

a third region at least one of above the first region or below the first region, the third region comprising:
a first sub-region adjacent to the second region and comprising the first doping type; and
a second sub-region adjacent to the first sub-region and comprising the first doping type; and
a first surface protect region comprising the first doping type, the first surface protect region adjacent to the second sub-region.

US Pat. No. 9,054,004

PIXEL ISOLATION STRUCTURES IN BACKSIDE ILLUMINATED IMAGE SENSORS

Taiwan Semiconductor Manu...

1. A backside illuminated image sensor including an array of pixels, comprising:
a first pixel disposed in a front side of a substrate and configured to generate charged carriers in response to light incident
upon a backside of the substrate;

a second pixel disposed in the front side of the substrate and configured to generate charged carriers in response to light
incident upon the backside of the substrate; and
an anti-reflective layer on the backside of the substrate; and
a first isolation structure disposed to separate the second pixel from the first pixel, the first isolation structure extending
from the backside of the substrate toward the front side of the substrate, wherein the first isolation structure includes
a first sidewall substantially vertically to the front side of the substrate,

wherein the first isolation structure separates a region of the anti-reflective layer corresponding to the first pixel and
another region of the anti-reflective layer corresponding to the second pixel.

US Pat. No. 9,281,221

ULTRA-HIGH VACUUM (UHV) WAFER PROCESSING

Taiwan Semiconductor Manu...

11. A vacuum system for ultra-high vacuum (UHV) wafer processing, comprising:
a remote load lock (RLL) module configured to:
receive a wafer from a load port; and
pump down the RLL module to a first pressure;
a first bridge configured to connect the RLL module to a first cluster tool, the first bridge comprising:
a second bypass module;
a first buffer module configured to at least one of:
receive the wafer from the second bypass module;
receive the wafer from the RLL module; or
pump down the first buffer module to a second pressure, the second pressure less than the first pressure; and
a first bypass module configured to receive the wafer from the first buffer module, the first bypass module connected to the
first cluster tool; and

a second bridge configured to connect the first cluster tool to a second cluster tool, the second bridge associated with the
second pressure, the second bridge comprising:

a fourth bypass module configured to receive the wafer from the first cluster tool;
a second buffer module configured to receive the wafer from the fourth bypass module; and
a third bypass module configured to receive the wafer from the second buffer module, the third bypass module connected to
the second cluster tool.

US Pat. No. 9,093,299

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first active region;
a second active region;
a shallow trench isolation (STI) region between the first active region and the second active region; and
a metal connect over the first active region, the STI region and the second active region, and connected to the first active
region and the second active region, such that a first unrecessed portion of the metal connect over the first active region
has a first height, a recessed portion of the metal connect over the STI region has a second height and a second unrecessed
portion of the metal connect over the second active region has a third height, the first height and the third height greater
than the second height.

US Pat. No. 9,455,169

ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM

Taiwan Semiconductor Manu...

1. A pod comprising:
a storage chamber having a sidewall surface defining an opening at one side thereof; and
a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber, the pod
door comprising:

a door body;
a first door locking mechanism on the door body, the first door locking mechanism comprising:
a first pressure applicator;
a first key assembly; and
a first connector-rod coupling the first key assembly to the first pressure applicator; and
a seal band, wherein:
the first key assembly is movable between a locked position and an unlocked position,
the seal band is configured to engage the sidewall surface of the storage chamber while the first key assembly is in the locked
position,

an angle defined by a face of the first connector-rod and a face of the first pressure applicator is different when the first
key assembly is in the locked position than when the first key assembly is in the unlocked position, and

the seal band is spaced apart from the first pressure applicator to define a gap when the first key assembly is in the unlocked
position.

US Pat. No. 9,076,553

SPSRAM WRAPPER

Taiwan Semiconductor Manu...

1. A system for facilitating access operations to a single port memory device, comprising:
a wrapper controller configured to:
initiate a first access operation from a first port of a wrapper address component to a single port memory device during a
first clock period;

receive a clock reset signal from the single port memory device, the clock reset signal indicative of a completion of the
first access operation; and

initiate a second access operation from a second port of the wrapper address component to the single port memory device during
the first clock period responsive to receiving the clock reset signal.

US Pat. No. 9,472,618

NANOWIRE FIELD EFFECT TRANSISTOR DEVICE HAVING A REPLACEMENT GATE

Taiwan Semiconductor Manu...

1. A transistor device, comprising:
a semiconductor substrate;
a buffer layer formed over the semiconductor substrate;
a nanowire formed over the buffer layer and having a pair of distal portions, the nanowire including
source and drain regions respectively defined at the distal portions of the nanowire and
a channel region connecting the source and drain regions of the nanowire;
a gate structure surrounding the nanowire; and
a remnant of a sacrificial layer between the buffer layer and the nanowire, wherein the gate structure and the remnant of
the sacrificial layer define a distance L therebetween and the distance L determines a degree to which areas of the source
region or the drain region are electrically isolated from the buffer layer.

US Pat. No. 9,287,372

METHOD OF FORMING TRENCH ON FINFET AND FINFET THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a trench on a fin field effect transistor (FinFET), comprising:
forming a first inter-layer dielectric layer over a first gate and a second gate of the FinFET;
forming a second inter-layer dielectric layer above the first inter-layer dielectric layer, the first gate of the FinFET,
and the second gate of the FinFET;

patterning a photoresist layer over the second inter-layer dielectric layer;
etching part of the second inter-layer dielectric layer that is not below the photoresist layer to expose the first gate and
the second gate;

forming a first polysilicon layer over the first gate and the second gate and in the second inter-layer dielectric layer;
and

removing the first gate and the second gate and the first polysilicon layer to form a first trench and a second trench through
the first inter-layer dielectric layer and the second inter-layer dielectric layer.

US Pat. No. 9,281,741

START-UP CIRCUIT FOR VOLTAGE REGULATION CIRCUIT

Taiwan Semiconductor Manu...

1. A start-up circuit configured to apply a voltage to a pre-charge node of a primary circuit to alter a wake-up time of the
primary circuit, comprising:
a reset transistor coupled to at least one of ground or a first voltage source and configured to discharge the pre-charge
node to at least one of ground or the first voltage source when the reset transistor is turned-on;

a recharge transistor coupled to a second voltage source and configured to apply the voltage to the pre-charge node when the
recharge transistor is turned-on; and

a control transistor coupled to a third voltage source and configured to control application of a second voltage to a gate
of the recharge transistor.

US Pat. No. 9,064,797

SYSTEMS AND METHODS FOR DOPANT ACTIVATION USING PRE-AMORPHIZATION IMPLANTATION AND MICROWAVE RADIATION

Taiwan Semiconductor Manu...

1. A method for dopant activation in a semiconductor structure for fabricating semiconductor devices, the method comprising:
providing a substrate;
forming a semiconductor structure on the substrate;
performing pre-amorphization implantation on the semiconductor structure;
providing one or more microwave-absorption materials capable of increasing an electric field density associated with the semiconductor
structure; and

applying microwave radiation to the semiconductor structure and the microwave-absorption materials to activate dopants in
the semiconductor structure for fabricating semiconductor devices;

wherein the microwave-absorption materials are configured to increase the electric field density in response to the microwave
radiation so as to increase the semiconductor structure's absorption of the microwave radiation.

US Pat. No. 9,054,686

DELAY PATH SELECTION FOR DIGITAL CONTROL OSCILLATOR

Taiwan Semiconductor Manu...

1. A system for delay path selection, comprising:
a delay path selection multiplexer; and a digitally controlled oscillator comprising: a first inverter structure configured
to be selectively enabled by the delay path selection multiplexer to establish a first delay path within the digitally controlled
oscillator; and a second inverter structure configured to be selectively enabled by the delay path selection multiplexer to
establish a second delay path within the digitally controlled oscillator, the second delay path and the first delay path having
at least one inverter structure in common, and wherein: the delay path selection multiplexer is configured to selectively
enable the first inverter structure and the second inverter structure based upon a selected frequency output of the digitally
controlled oscillator.

US Pat. No. 9,123,839

IMAGE SENSOR WITH STACKED GRID STRUCTURE

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a metal grid formed over a photodiode array, the metal grid comprising:
a first metal grid portion comprising a first interface configured to guide light towards a first photodiode and deflect the
light away from a second photodiode; and

a second metal grid portion comprising a second interface configured to guide the light towards the first photodiode;
a dielectric extending between the first metal grid portion and the second metal grid portion, the dielectric comprising a
first material;

a dielectric grid formed over the metal grid, the dielectric grid comprising:
a first dielectric grid portion; and
a second dielectric grid portion; and
a filler material extending between the first dielectric grid portion and the second dielectric grid portion, the filler material
different than the first material.

US Pat. No. 9,425,257

NON-PLANAR SIGE CHANNEL PFET

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:
a semiconductor substrate having a Germanium concentration and including a top surface;
a metal gate including a bottom surface;
a channel layer formed of a Germanium compound having a Germanium concentration and including a top surface and a bottom surface
that is in contact with the top surface of the semiconductor substrate, wherein the top surface of the channel layer is at
higher elevation than the bottom surface of the metal gate from a bottom surface of the semiconductor substrate, the Germanium
concentration of the semiconductor substrate being less than the Germanium concentration of the channel layer; and

a capping layer a portion of which is formed between the top and bottom surfaces of the channel layer to separate the channel
layer from the metal gate, the capping layer having a Germanium concentration, the Germanium concentration of the channel
layer being greater than the Germanium concentration of the capping layer.

US Pat. No. 9,275,752

READ-ONLY MEMORY

Taiwan Semiconductor Manu...

1. A multi-layer bit-1 read-only memory (ROM) cell, comprising:
a first circuit comprising a first transistor; and
a second circuit comprising a second transistor, wherein:
a gate of the second transistor is coupled to a YMUX connection;
the YMUX connection is coupled to a first multiplexer;
a source of the second transistor is coupled to a word-line bar;
the second circuit is configured to control a voltage in the first circuit;
the second transistor is configured to maintain a disconnection between a source of the first transistor and the word-line
bar when a voltage at the YMUX connection is within a low voltage state voltage range; and

the second circuit is located on a different physical layer than the first circuit.

US Pat. No. 9,275,181

CELL DESIGN

Taiwan Semiconductor Manu...

1. A transistor array of a cell, comprising:
a first transistor comprising:
a first gate, and
a first region having a first length, the first region comprising at least one of a first source or a first drain; and
a second transistor comprising:
a second gate, and
a second region abutting the first region, the second region having a second length different than the first length, the second
region comprising at least one of a second source or a second drain, wherein:

a ratio of the first length to the second length is a function of at least one of a desired alpha ratio for the transistor
array or a desired beta ratio for the transistor array.

US Pat. No. 9,166,035

DELTA DOPING LAYER IN MOSFET SOURCE/DRAIN REGION

Taiwan Semiconductor Manu...

1. A transistor comprising:
a gate terminal;
a source terminal; and
a drain terminal;
wherein at least one of the source and drain terminals has a layered configuration including
a terminal layer having a top surface and a bottom surface, and
an intervening layer that is located within the terminal layer, between and spaced from the top and bottom surfaces, and that
is oriented to be substantially perpendicular to current flow, and that is less than one tenth the thickness of the terminal
layer; and

wherein the terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a
concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal
layer, and

wherein the intervening layer is spaced at least twice as far from the bottom surface as from the top surface.

US Pat. No. 9,153,452

SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTO-CURRENT DETECTION

Taiwan Semiconductor Manu...

1. A system for performing chemical-mechanical planarization on an article, comprising:
a polishing head configured to perform chemical-mechanical planarization (CMP) on an article;
a polishing pad configured to support the article;
a light source configured to emit an incident light;
a polishing fluid configured to perform CMP including a plurality of light-absorption particles capable of transferring charges
to a stop layer in the article in response the incident light;

a current detector configured to detect a current in response to the light-absorption particles transferring charges to the
stop layer; and

one or more processors configured to control the polishing head based on the detected current.

US Pat. No. 9,325,310

HIGH-SWING VOLTAGE MODE DRIVER

TAIWAN SEMICONDUCTOR MANU...

1. A high-swing voltage mode driver, comprising:
a first circuit comprising a first transistor, a second transistor and an inverter, a drain of the first transistor coupled
to a first side of the inverter and a drain of the second transistor coupled to a second side of the inverter;

a second circuit comprising a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, a drain of
the third transistor coupled to a drain of the fifth transistor, a drain of the fourth transistor coupled to a drain of the
sixth transistor, the drain of the first transistor coupled to a source of the fifth transistor and the drain of the second
transistor coupled to a source of the sixth transistor; and

a third circuit comprising a seventh transistor and an eighth transistor, a source of the third transistor coupled to a drain
of the seventh transistor and a source of the fourth transistor coupled to a drain of the eighth transistor.

US Pat. No. 9,299,810

FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a fin-type field effect transistor comprising:
forming a first semiconductor region;
forming a second semiconductor region;
forming a first fin over the first semiconductor region, the first fin comprising a first source, a first drain, and a first
channel;

forming a second fin over the second semiconductor region, the second fin comprising a second source, a second drain, and
a second channel;

masking a portion of the second semiconductor region for a first period of time;
forming a first portion of a first reacted region from the first semiconductor region during the first period of time;
removing the mask after the first period of time; and
forming a second portion of the first reacted region and a second reacted region from the portion of the second semiconductor
region during a second period of time after the first period of time, the first reacted region having a first dimension causing
a first strain in the first channel, and the second reacted region having a second dimension causing a second strain in the
second channel, the first strain substantially equal to the second strain.

US Pat. No. 9,287,122

METHOD FOR GROWING EPITAXIES OF A CHEMICAL COMPOUND SEMICONDUCTOR

Taiwan Semiconductor Manu...

1. A method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication
process, the method comprising:
providing a prelayer over a substrate;
providing a barrier layer over the prelayer; and
selectively forming an InAs epitaxy layer with low-growth-temperature growth and depositing at least one pair of Al(In)Sb/InAs/Al(in)Sb
at a temperature of about 300 to about 600° C. over the barrier layer to provide a chemical compound semiconductor channel
layer.

US Pat. No. 9,454,684

EDGE CRACK DETECTION SYSTEM

Taiwan Semiconductor Manu...

9. An edge crack detection system, comprising:
a radio frequency identification (RFID) reader providing a command signal; and
an RFID tag wirelessly connected to the RFID reader, the RFID tag comprising an antenna completely encircling a die under
test, the antenna disposed outside a seal ring surrounding the entire periphery of the die under test, wherein the antenna
receives the command signal, produces power from the command signal, and provides a response signal based on the command signal,

wherein the RFID reader receives the response signal from the RFID tag and provides the command signal regarding the RFID
tag's self-destruction based on the response signal from the RFID tag, and the RFID tag receives the command signal and self-destructs
based on the command signal.

US Pat. No. 9,350,372

ARRANGEMENT FOR DIGITAL-TO-ANALOG CONVERTER

Taiwan Semiconductor Manu...

1. An arrangement for a digital-to-analog converter (DAC), comprising:
a current source configured to supply a current and comprising a first supply transistor, the first supply transistor comprising:
a first source;
a first drain; and
a first gate between the first source and the first drain, the first supply transistor having a horizontal gate layout; and
a switching element configured to switch a current of the current source between a first terminal and a second terminal, the
switching element comprising a first switching transistor, the first switching transistor comprising:

a second source;
a second drain; and
a second gate between the second source and the second drain, the first switching transistor having a vertical gate layout,
wherein a channel length of a first channel of the first supply transistor is at least three times larger than a channel length
of a second channel of the first switching transistor.

US Pat. No. 9,147,766

SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device having a fin-type channel, comprising:
a substrate;
a first buffer layer above at least a portion of the substrate;
a barrier layer above at least a portion of the first buffer layer;
a fin-type channel layer over the barrier layer; wherein a width of the fin-type channel layer is smaller than a width of
the first buffer layer; and

a first dielectric layer surrounding at least a portion of the fin-type channel layer,
wherein at least a portion of the fin-type channel layer protrudes from a top surface of the first dielectric layer.

US Pat. No. 9,393,668

POLISHING HEAD WITH ALIGNMENT GEAR

TAIWAN SEMICONDUCTOR MANU...

1. An arrangement for driving a rolling seal clamp of a polishing head, comprising:
a body configured to be selectively pressurized; and
a first alignment gear extending from an outer circumference of a housing of the polishing head configured for polishing a
semiconductor wafer, the first alignment gear configured to be selectively mated with a first channel of a rolling seal clamp
to which the body is attached, the first alignment gear mated with the first channel when the body is in a pressurized state
and not mated with the first channel when the body is in a depressurized state.

US Pat. No. 9,391,350

RF CHOKE DEVICE FOR INTEGRATED CIRCUITS

Taiwan Semiconductor Manu...

10. A system for selectively filtering a radio frequency (RF) bandwidth, comprising:
a 3D RF choke configured to selectively filter the RF bandwidth, the 3D RF choke comprising:
a metal connection line configured as an inductive element, the metal connection line connecting to a DC power source at a
first location of the metal connection line, the metal connection line connecting to a metal RF line at a second location
of the metal connection line, the metal RF line connecting an RF input port to an RF output port; and

a capacitive element comprising:
a first ground through via connected to a ground point; and
a first signal through via connected to the metal connection line at a third location of the metal connection line.

US Pat. No. 9,276,108

MEMORY CELL ARRAY AND CELL STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor read-only memory (ROM) unit cell structure comprising:
a cell base region defining a cell boundary, comprising a blanket OD layer having a wide-block profile disposed on a substrate
and defining a continuous common source node, arranged in selective connection with a ground (Vss);

a drain pad disposed above the OD layer selectively connected with a bit line;
a vertical channel structure bridging the drain pad and the OD layer; and
a gate structure disposed vertically between the drain pad and the OD layer and connected with a word-line;
wherein the cell boundary is defined within the coverage of the OD layer.

US Pat. No. 9,317,650

DOUBLE PATTERNING TECHNOLOGY (DPT) LAYOUT ROUTING

TAIWAN SEMICONDUCTOR MANU...

1. A system for determining double patterning technology (DPT) layout routing compliance, comprising:
a layout routing component configured to:
create a first pin group comprising a first set of one or more pre-colored pins that are linked together by a first set of
internal conflict spaces;

associate the first pin group with a first phantom assisted feature (AF) mask polygon, the associating comprising:
selecting a first pre-colored pin from the first set of one or more pre-colored pins;
determining a first mask assignment associated with the first pre-colored pin; and
assigning the first phantom AF mask polygon to a different mask than a mask for the first pre-colored pin according to the
first mask assignment;

create a pin loop based on the first pre-colored pin and the phantom AF mask polygon;
assign a pin loop value to the pin loop; and
determine whether a double patterning technology (DPT) violation is present for the pin loop based on the pin loop value.

US Pat. No. 9,263,330

SEMICONDUCTOR DEVICE, METHOD FOR FORMING CONTACT AND METHOD FOR ETCHING CONTINUOUS RECESS

Taiwan Semiconductor Manu...

1. A method for forming a continuous contact plug, comprising:
forming a first dielectric layer over a substrate;
forming a second dielectric layer over the first dielectric layer;
patterning the second dielectric layer to form a first recess;
patterning the first dielectric layer by a first etchant through the first recess to form a second recess,
wherein the first etchant has a higher etching rate with respect to the first dielectric layer than with respect to the second
dielectric layer and further wherein the second recess is aligned with the first recess; and

forming the continuous contact plug in the first recess and the second recess.

US Pat. No. 9,169,117

MEMS DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a Micro Electro Mechanical System (MEMS) device, comprising:
providing a substrate;
forming a catalyst layer over the substrate;
patterning the catalyst layer;
forming a carbon nanotube based on the catalyst layer;
forming a getter layer over the carbon nanotube and the substrate; and
etching back the getter layer to expose the carbon nanotube.

US Pat. No. 9,461,069

SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE TRANSISTOR LAYERS

Taiwan Semiconductor Manu...

1. A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region
and different transistor types fabricated using different channel material, the semiconductor structure comprising:
a first transistor layer comprising a first type of channel material in the first region but no channel material in the second
region;

a second transistor layer comprising a second type of channel material in the second region but no channel material in the
first region, the second transistor layer vertically elevated above the first transistor layer;

a first transistor fabricated on the first transistor layer; and
a second transistor fabricated on the second transistor layer, wherein the first transistor is interconnected with the second
transistor to form a circuit.

US Pat. No. 9,397,040

SEMICONDUCTOR DEVICE COMPRISING METAL PLUG HAVING SUBSTANTIALLY CONVEX BOTTOM SURFACE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a dielectric layer;
a metal plug over a substrate, the metal plug having a contact bottom surface that is substantially convex;
a metal layer in contact with sidewalls of the dielectric layer and between the dielectric layer and the metal plug; and
a silicide layer between the substrate and the metal plug, wherein:
the silicide layer has a silicide layer top surface that is substantially concave to interface with the substantially convex
contact bottom surface of the metal plug; and

the metal layer terminates at an edge of the silicide layer.

US Pat. No. 9,391,023

METHOD FOR PRODUCING SALICIDE AND A CARBON NANOTUBE METAL CONTACT

Taiwan Semiconductor Manu...

1. A method of producing a metal contact in a semiconductor device comprising:
depositing a catalyst material layer in a via hole;
forming a catalyst from the catalyst material layer;
growing a carbon nanotube structure using the catalyst in the via hole;
forming a portion of salicide from the catalyst after the growth of the carbon nanotube structure;
applying a chemical mechanical polishing (CMP) process to the carbon nanotube structure to remove top layers of catalyst and
nanotube material; and

depositing metal material above the carbon nanotube structure.

US Pat. No. 9,305,837

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor arrangement, the method comprising:
forming a first metal trace in a first dielectric opening in a dielectric layer, the first metal trace having a first metal
trace width between about 30 nm to about 60 nm and a first metal trace length; and

forming a second metal trace in a second dielectric opening in the dielectric layer, the second metal trace having a second
metal trace width between about 10 nm to about 20 nm and second metal trace length, the first metal trace length different
than the second metal trace length, such that the dielectric layer has a dielectric layer width between the first metal trace
and the second metal trace between about 10 nm to about 20 nm.

US Pat. No. 9,338,834

SYSTEMS AND METHODS FOR MICROWAVE-RADIATION ANNEALING

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor structure using microwave radiation, the semiconductor structure including a top
portion and a bottom portion, the method comprising:
providing a semiconductor structure;
providing one or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave
radiation;

applying microwave radiation to the energy-converting materials and the semiconductor structure to anneal the semiconductor
structure for fabricating semiconductor devices;

detecting first local temperatures associated with one or more first zones of the semiconductor structure, wherein the first
zones are disposed in the top portion;

adjusting the microwave radiation applied to the energy-converting materials and the semiconductor structure based at least
in part on the detected first local temperatures;

detecting second local temperatures associated with one or more second zones of the semiconductor structure, wherein the second
zones are disposed in the bottom portion; and

adjusting the microwave radiation applied to the energy-converting material and the semiconductor structure based at least
in part on the detected second local temperatures.

US Pat. No. 9,425,091

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor structure, comprising:
forming a first etch stop layer (ESL);
forming an oxide region above the first ESL;
forming a low-k (LK) dielectric region above the oxide region;
forming a first metal line through at least one of the first ESL, the oxide region, or the LK dielectric region;
forming a second metal line through at least one of the first ESL, the oxide region, or the LK dielectric region;
forming a second ESL over at least one of the first metal line, the second metal line, or the LK dielectric region;
removing at least a portion of the second ESL at least one of:
over at least one of the first metal line or the second metal line; or
between the first metal line and the second metal line;
forming a gap by removing at least one of:
at least a portion of the oxide region between the first metal line and the second metal line; or
at least a portion of the LK dielectric region between the first metal line and the second metal line; and
forming an ESL seal region over at least one of the second ESL, the first metal line, the second metal line, or the gap.

US Pat. No. 9,281,475

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) WITH MULTI-LAYER DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A resistive memory comprising:
a first electrode and a second electrode; and
a multi-layer resistance-switching network disposed between the first electrode and the second electrode, the multi-layer
resistance-switching network comprising:

a group-IV element doping layer;
a first carbon doping layer disposed between the group-IV element doping layer and the first electrode; and
a second carbon doping layer disposed between the group-IV element doping layer and the second electrode.

US Pat. No. 9,252,217

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

11. A method of forming a semiconductor arrangement, comprising:
forming a first opening having a first opening width in a first dielectric layer, the first dielectric layer over a substrate;
forming a first portion of a semiconductor column in the first opening, the first portion comprising a first material, the
first portion having a first portion width substantially equal to the first opening width;

forming a second dielectric layer around the first portion, such that a top surface of the second dielectric layer is above
a top surface of the first portion and a second opening is defined in the second dielectric layer above the first portion,
where the second opening has a second opening width substantially equal to the first opening width; and

forming a second portion of the semiconductor column over the first portion in the second opening, the second portion comprising
a second material different than the first material, the second portion having a second portion width substantially equal
to the first opening width.

US Pat. No. 9,238,578

SEMICONDUCTOR ARRANGEMENT WITH STRESS RELEASE AND THERMAL INSULATION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer;
a microelectromechanical systems (MEMS) wafer formed over the CMOS wafer, the MEMS wafer comprising a high vacuum chamber
configured as a sensing gap between a membrane of the MEMS wafer and a poly layer of the MEMS wafer;

a cap wafer formed over the MEMS wafer; and
an ambient pressure chamber formed between the MEMS wafer and the cap wafer.

US Pat. No. 9,490,288

IMAGE SENSOR WITH TRENCHED FILLER GRID WITHIN A DIELECTRIC GRID INCLUDING A REFLECTIVE PORTION, A BUFFER AND A HIGH-K DIELECTRIC

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array over a substrate;
a dielectric grid over the photodiode array and comprising a first dielectric structure and a second dielectric structure;
a reflective portion between the first dielectric structure and the second dielectric structure;
a filler grid comprising a first filler structure between the first dielectric structure and the second dielectric structure,
the first filler structure over a first photodiode of the photodiode array;

a buffer laterally between the reflective portion and the first dielectric structure, the buffer in direct physical contact
with the first filler structure and the buffer comprising a different material composition than the first dielectric structure
and the second dielectric structure; and

a high-k dielectric laterally between the buffer and the first dielectric structure.

US Pat. No. 9,449,886

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method, comprising:
etching a substrate to define a set of fins;
masking a top surface of a first subset of the set of fins;
etching a second subset of the set of fins while the top surface of the first subset is masked to reduce a fin height of fins
that are members of the second subset;

etching a portion of the substrate between a first fin of the second subset and a second fin of the second subset to define
a trench;

forming a shallow trench isolation (STI) region within a first portion of the trench and a second portion of the trench; and
depositing a conductive material within a third portion of the trench, over the first subset, and over the second subset to
form a metal connect, wherein:

the third portion of the trench is between the first portion of the trench and the second portion of the trench, and
the metal connect is in contact with the first subset and the second subset.

US Pat. No. 9,425,085

STRUCTURES, DEVICES AND METHODS FOR MEMORY DEVICES

Taiwan Semiconductor Manu...

1. A static random access memory (SRAM) device comprising:
first, second, and third conductive layers;
a first word line disposed in the first conductive layer;
a first landing pad disposed in the first conductive layer;
a second word line disposed in the second conductive layer and coupled to the first landing pad;
a second landing pad disposed in the first conductive layer;
a third word line disposed in the third conductive layer and coupled to the second landing pad; and
an SRAM cell coupled to the first word line and the first and second landing pads, wherein at least two of the second conductive
layer, the third conductive layer, and the first conductive layer are disposed one above the other.

US Pat. No. 9,177,924

VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

Taiwan Semiconductor Manu...

1. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:
an input terminal for receiving an input signal;
an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including
one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes:

a well of a first conductivity type that is formed in a semiconductor substrate,
a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire
that is opposite the first end, the source region further including a portion formed in the well, wherein the source region
and the drain region are of a second conductivity type such that a PN junction is formed between the well and the portion
of the source region formed in the well, and

a gate region surrounding a portion of the nanowire, wherein the gate region is separated from the drain region by a first
distance, the separation of the gate region and the drain region providing a resistance in series between the drain region
and the source region; and

an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage
in the input signal is attenuated by the resistance and the PN junction.

US Pat. No. 9,123,563

METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE

Taiwan Semiconductor Manu...

7. A method of forming a contact structure of a gate structure, comprising:
etching an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate to expose
an underlying silicon substrate;

depositing a silicide portion defined by a contact profile in the exposed portion of the silicon substrate;
depositing a metal glue layer around the first metal gate and the second metal gate defining a trench above the silicide portion;
and

depositing a metal plug within the trench.

US Pat. No. 9,349,690

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor arrangement, comprising:
forming a first metal layer in a first opening of a dielectric, a second opening of the dielectric and over the dielectric,
the first metal layer comprising titanium nitride;

forming a first interconnect over the first metal layer in the first opening;
forming a second interconnect over the first metal layer in the second opening;
forming a first dielectric layer over the first metal layer, the first interconnect and the second interconnect;
performing a first etch to remove a first portion of the first dielectric layer over the first interconnect, the second interconnect
and a first portion of the first metal layer and to remove the first portion of the first metal layer from a first top portion
of a top surface of the dielectric, such that a first metal layer first portion remains in the first opening and a first metal
layer second portion remains in the second opening;

performing a second etch to form a first air gap on first side of the first metal layer first portion and to form a second
air gap on a second side of the first metal layer first portion, such that the second air gap is between the first metal layer
first portion and the first metal layer second portion;

performing a third etch to remove first sidewalls of the first metal layer first portion, such that a first bottom portion
of the first metal layer remains under the first interconnect, and to remove second sidewalls of the first metal layer second
portion, such that a second bottom portion of the first metal layer remains under the second interconnect; and

forming a protective barrier over the first interconnect and the second interconnect.

US Pat. No. 9,261,534

SHIELD PIN ARRANGEMENT

Taiwan Semiconductor Manu...

1. A probe card for testing an electronic device comprising:
a signal pin configured to carry a signal;
a first set of one or more shield pins lying within a first plane; and
a second set of one or more shield pins lying within a second plane different than the first plane, the first set and the
second set of one or more shield pins configured to shield the signal pin from an interference signal.

US Pat. No. 9,130,531

SEMICONDUCTOR ARRANGEMENT WITH THERMAL INSULATION CONFIGURATION

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor arrangement, comprising:
forming a microelectromechanical systems (MEMS) wafer comprising a thermal insulator air gap between a sensing layer and a
membrane;

bonding the MEMS wafer to a complementary metal-oxide-semiconductor (CMOS) wafer;
forming an ambient pressure chamber between the CMOS wafer and the membrane of the MEMS wafer, the ambient pressure chamber
exposed to ambient air; and

bonding a cap wafer to the MEMS wafer, the cap wafer comprising a pressurized chamber having a pressure different than an
ambient air pressure.

US Pat. No. 9,425,324

SEMICONDUCTOR DEVICE AND CHANNEL STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a composite structure that comprises
an inner core strut that comprises a gate stack; and
an outer sleeve layer that is sleeved on the gate stack of the inner core strut and that comprises a two-dimensional (2-D)
layered material, wherein the inner core strut mechanically supports the outer sleeve layer and wherein the outer sleeve layer
has a central portion that defines a channel region and a pair of opposing end portions that respectively define source and
drain regions.

US Pat. No. 9,406,626

SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a main circuit;
an assembly isolation region that surrounds the main circuit, the assembly isolation region comprising a first circuit that
includes a first capacitor and a first inductor connected in series; and

a first seal ring that surrounds the assembly isolation region, the first capacitor and the first inductor (i) being connected
between the first seal ring and a ground, and (ii) being disposed laterally between the first seal ring and the main circuit.

US Pat. No. 9,230,961

SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a well region;
a first region disposed within the well region, the first region comprising a first conductivity type;
a first gate disposed above the well region on a first side of the first region, the first gate comprising a first top surface
facing away from the well region, the first top surface having a first top surface area;

a first gate contact disposed above the first gate, the first gate contact comprising a first bottom surface facing towards
the well region, the first bottom surface having a first bottom surface area, the first bottom surface area covering at least
about two thirds of the first top surface area;

a first region contact disposed above the first region; and
a first multi-gate contact in direct physical contact with the first gate contact and the first region contact.

US Pat. No. 9,093,455

BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

15. An interconnect structure, the interconnect structure comprising:
a dielectric layer, the dielectric layer having a recess therein;
a silicon (Si) layer that is deposited in the recess; and
an interconnect including a barrier layer and a conductive layer that are provided in the recess over the Si layer, wherein
the Si layer has a density that substantially prevents the barrier layer from moving away from the conductive layer and towards
the dielectric layer during subsequent processing of the interconnect structure,

wherein the interconnect structure is planarized to cause portions of the Si layer, the barrier layer, and the conductive
layer to be coplanar with a top surface of the dielectric layer, the interconnect structure further comprising:

a nitride layer that is formed in a first portion of the Si layer that is adjacent to the top surface; and
an oxide layer that is formed in a second portion of the Si layer that is adjacent to the first portion.

US Pat. No. 9,550,270

TEMPERATURE MODIFICATION FOR CHEMICAL MECHANICAL POLISHING

Taiwan Semiconductor Manu...

1. A system, comprising:
a fluid reservoir for storing a liquid;
a nozzle for dispensing the liquid onto a polishing pad of a chemical mechanical polishing (CMP) system;
a first fluid pathway from the fluid reservoir to the nozzle;
a second fluid pathway from the fluid reservoir to the nozzle;
a first valve disposed within the first fluid pathway;
a second valve disposed within the second fluid pathway;
a liquid heater component disposed within the second fluid pathway between the fluid reservoir and the second valve, the liquid
heater component comprising a quartz heater configured to heat the liquid to generate heated liquid, wherein the heated liquid
is supplied to the polishing pad upon which a semiconductor wafer is to be polished to generate a heated polishing pad having
a heated polishing pad temperature; and

a polishing component configured to:
responsive to the heated polishing pad temperature exceeding a threshold, polish the semiconductor wafer utilizing the heated
polishing pad during a CMP stage.

US Pat. No. 9,219,471

CIRCUITRY FOR PHASE DETECTOR

Taiwan Semiconductor Manu...

1. A circuit for a phase detector, comprising:
a first buffer configured to:
receive a data signal; and
apply a first delay to the data signal, using a first delay signal, to generate a first modified data signal;
a notifier configured to:
receive the data signal; and
determine whether a violation exists in at least one of a setup timing margin or a hold timing margin;
a first multiplexer configured to:
receive the first modified data signal from the buffer at a 0-input of the first multiplexer;
receive a random value at a 1-input of the first multiplexer; and
transmit a first multiplexer data signal, comprising:
responsive to the notifier determining that the violation exists in at least one of the setup timing margin or the hold timing
margin, transmitting the random value as the first multiplexer data signal; and

responsive to the notifier determining that the violation does not exist in at least one of the setup timing margin or the
hold timing margin, transmitting the first modified data signal from the buffer as the first multiplexer data signal; and

a second multiplexer configured to:
receive the first modified data signal from the buffer at a 0-input of the second multiplexer;
receive the first multiplexer data signal from the first multiplexer at a 1-input of the second multiplexer;
receive a random value turn on control signal; and
transmit a second multiplexer data signal to a D-pin of a flip-flop of the phase detector, comprising:
responsive to the random value turn on control signal comprising 1, transmitting the first multiplexer data signal as the
second multiplexer data signal; and

responsive to the random value turn on control signal comprising 0, transmitting the first modified data signal from the buffer
as the second multiplexer data signal.

US Pat. No. 9,124,086

FAILSAFE ESD PROTECTION

Taiwan Semiconductor Manu...

1. A method for providing failsafe electrostatic discharge (ESD) protection, comprising:
connecting a voltage source (VDDA) to a source of a transistor;
connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface of an NWELL body of the transistor; and
connecting a PAD to the VFS supply voltage via a first diode, the PAD operably connected to circuitry to be protected from
ESD.

US Pat. No. 9,269,812

SEMICONDUCTOR DEVICE HAVING V-SHAPED REGION

Taiwan Semiconductor Manu...

1. A transistor, comprising:
a source/drain region having a height-to-length ratio exceeding at least 1.5 when a poly spacing between the transistor and
a second transistor is less than about 75 nm and having a height-to-length ratio exceeding at least 1.6 when the poly spacing
between the transistor and the second transistor is less than about 60 nm.

US Pat. No. 9,233,839

MEMS DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a microelectromechanical systems (MEMS) device, comprising:
providing a substrate having a first portion and a second portion;
fabricating a membrane type sensor on the first portion of the substrate; and
fabricating a bulk silicon sensor on the second portion of the substrate,
wherein fabricating the membrane type sensor further comprises:
providing a conductive base over the substrate;
providing a sacrificial layer over the conductive base;
providing a reference element over the sacrificial layer;
providing a dielectric layer over the reference element;
removing a portion of the sacrificial layer between the reference element and the conductive base using a plurality of holes
extending through the dielectric layer and the reference element to the sacrificial layer to form a first cavity of the membrane
type sensor between the reference element and the conductive base;

forming a sealing layer above the dielectric layer to seal the first cavity of the membrane type sensor by using Titanium
as the sealing layer; and

patterning the sealing layer over the reference element.

US Pat. No. 9,263,295

NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN

Taiwan Semiconductor Manu...

1. A method for forming a nanowire field effect transistor (FET) device, the method comprising:
forming a device layer including a source region and a drain region being connected by a nanowire channel to be suspended,
the nanowire channel being provided over a sacrificial material;
forming first and second etch stop layers respectively beneath the source region and the drain region,
each of the etch stop layers forming a support structure over a semiconductor substrate; and
suspending the nanowire channel by
etching the sacrificial material beneath the nanowire channel, the etching being selective to the sacrificial material to
substantially prevent the removal of the etch stop layers beneath the source region and the drain region.

US Pat. No. 9,257,559

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a fin having a first wall extending along a first plane, the fin comprising:
a doped region, the doped region defining a first furrow on a first side of the first plane; and
a dielectric disposed within the first furrow, wherein:
the dielectric is contact with the first furrow between a first end of the dielectric and a second end of the dielectric,
the first end is separated a first distance from the first plane; and
the dielectric is convex such that an outer most protruding point is at least one of even with the first plane, on the first
side of the first plane or on a second side of the first plane.

US Pat. No. 9,177,785

THIN OXIDE FORMATION BY WET CHEMICAL OXIDATION OF SEMICONDUCTOR SURFACE WHEN THE ONE COMPONENT OF THE OXIDE IS WATER SOLUBLE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor structure comprising:
forming a solvent mixture by mixing a water soluble substance with an aprotic solvent; and
forming a thin layer of oxide over a semiconductor surface by performing wet chemical oxidation operations on the semiconductor
surface with the solvent mixture.

US Pat. No. 9,123,546

MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURES WITH DIFFERENT CHANNEL MATERIALS

Taiwan Semiconductor Manu...

15. A method for fabricating a semiconductor device structure, the method comprising:
selecting a first material capable of sustaining a first processing temperature and a second material capable of sustaining
a second processing temperature equal to or lower than the first processing temperature;

forming a first device layer on a substrate, the first device layer including a first channel structure for conducting a first
current, the first channel structure including the first material; and

forming a second device layer on the first device layer, the second device layer including a second channel structure for
conducting a second current, the second channel structure including the second material,

wherein the selection of the first material further comprises selecting the first material further capable of sustaining a
first thermal budget proportional to a first processing duration, a second thermal budget proportional to a second processing
duration, and a third thermal budget associated with consolidation of a bonding interface between the first device layer and
the second device layer.

US Pat. No. 9,337,263

SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substrate extending in a substantially horizontal direction;
a source unit including a plurality of sources;
a drain unit including a plurality of drains, wherein one of the source unit and the drain unit is formed on the substrate;
a semiconductor sheet unit extending in a substantially vertical direction and interconnecting the source unit and the drain
unit; and

a nanowire unit extending in the substantially vertical direction, interconnecting the source unit and the drain unit, and
having a cross-sectional shape of a dot in a top view.

US Pat. No. 9,318,447

SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE

Taiwan Semiconductor Manu...

1. A method of forming a vertical structure with at least two barrier layers, comprising:
providing a substrate;
providing a vertical structure over the substrate;
providing a first barrier layer over a source, a channel, and a drain of the vertical structure;
forming a first interlayer dielectric over the first barrier layer corresponding to the source of the vertical structure;
and

providing a second barrier layer over a gate and the drain of the vertical structure.

US Pat. No. 9,059,259

HARD MASK FOR BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

1. A method of fabricating an interconnect structure on a wafer, the method comprising:
providing a dielectric layer on the wafer;
forming an interconnect by-etching a recess into the dielectric layer, the etching utilizing a hard mask that includes a first
layer deposited on the dielectric layer;

planarizing the interconnect and the hard mask using a chemical mechanical polishing (CMP) process, wherein the first layer
of the hard mask substantially remains on the dielectric layer at a completion of the CMP process; and

performing a converting process by selectively converting at least a portion of the first layer into at least one of a nitride-containing
layer and an oxide-containing layer after the CMP process.

US Pat. No. 9,413,140

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a three dimensional (3D) integrated circuit (IC) structure comprising:
a first layer comprising:
a gate of a transistor; and
a first optical transmitter, wherein a first source/drain region of the transistor is coupled to a first serializer and a
second source/drain region of the transistor is coupled to the first optical transmitter, the transistor configured to selectively
couple the first optical transmitter to the first serializer; and

a second layer comprising a second optical transmitter over the first layer, the first optical transmitter configured to transmit
data from the first layer to the second layer and the second optical transmitter configured to transmit data from the second
layer to the first layer.

US Pat. No. 9,368,487

SEMICONDUCTOR DEVICE WITH DYNAMIC LOW VOLTAGE TRIGGERING MECHANISM

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a substrate of a first dopant type;
a well region of the first dopant type disposed in the substrate; and
a depletion inducing structure of a second dopant type having a gap defined therein at least partially arranged in the well
region;

wherein the well region is connected to the substrate through the gap in the depletion inducing structure.

US Pat. No. 9,312,186

METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device having a horizontal gate all around structure on a substrate, the method comprising:
forming a plurality of fins on the substrate, each fin comprising a top channel layer, a bottom channel layer below the top
channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial
layer between the substrate and the bottom channel layer;

forming a shallow trench isolation between the fins;
etching the shallow trench isolation to expose a portion of the fins above a first level;
etching the shallow trench isolation to expose the portion of the fins above a second level which is lower than the first
level; and

removing the top sacrificial layer and the bottom sacrificial layer above the second level.

US Pat. No. 9,472,545

SEMICONDUCTOR ARRANGEMENT WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first substrate comprising:
a first PMOS device comprising a first source/drain region coupled to a first power supply supplying a first voltage; and
a first NMOS device comprising a first source/drain region coupled to a second power supply supplying a second voltage different
than the first voltage;

a second substrate comprising:
a first device coupled to a second source/drain region of the first PMOS device; and
a second device coupled to a second source/drain region of the first NMOS device;
an electrostatic discharge (ESD) pad coupled between the first device and the second device, wherein there is no current path
between the ESD pad and a gate of the first PMOS device or a gate of the first NMOS device; and

a first interlayer via coupling the first substrate and the second substrate.

US Pat. No. 9,378,990

ADJUSTING INTENSITY OF LASER BEAM DURING LASER OPERATION ON A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A system for treating a semiconductor device, comprising:
a laser configured to emit a laser beam that performs an anneal operation on the semiconductor device;
a sensor configured to measure a reflection intensity of the laser beam, the reflection intensity indicative of a magnitude
at which the laser beam is reflected from the semiconductor device; and

a controller configured to control thermal absorption of the laser beam by the semiconductor device by adjusting an applied
intensity of the laser beam as a function of the reflection intensity and a specified thermal absorption rate for the anneal
operation, the applied intensity indicative of a magnitude at which the laser beam is emitted from the laser.

US Pat. No. 9,331,075

SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AT DIFFERENT LEVELS

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a substrate including a first region and a second region;
a first semiconductor device structure formed on the first region;
a semiconductor fin grown in the second region; and
a second semiconductor device structure formed on the semiconductor fin, wherein a top surface of the semiconductor fin is
higher than a top surface of the first semiconductor device structure.

US Pat. No. 9,331,018

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first active area output in a substrate adjacent an active area input;
a second active area output in the substrate adjacent the first active area output; and
a power divider comprising a transmission line and a resistor, the transmission line over the active area input, the first
active area output and the second active area output, the transmission line connected to the active area input, the first
active area output and the second active area output.

US Pat. No. 9,276,084

TRANSISTOR AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A transistor, comprising:
a channel layer over a substrate, having a recess;
a source layer comprising highly doped III-V compounds in the recess; and
a barrier layer between the channel layer and the substrate,
wherein the recess extends from the channel layer into the barrier layer,
wherein a depth between a bottom surface of the channel layer and a base of the recess is more than about 1.4 times a width
of a section of the recess intersecting the bottom surface of the channel layer, wherein a defect starting from the base of
the recess does not extend above the bottom surface of the channel layer if the defect exists in the source.

US Pat. No. 9,310,332

SEMICONDUCTOR DEVICE AND SELECTIVE HEATING THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
an ion sensing device, comprising:
an active region comprising a source, a drain and a channel situated between the source and the drain;
a gate situated over a first surface of the active region;
an ion sensing film situated over a second surface of the active region diametrically opposing the first surface; and
an ion sensing region situated over the ion sensing film, wherein the active region and the gate are embedded within a dielectric
layer; and

a heating element proximate the ion sensing device.

US Pat. No. 9,306,012

STRIP-GROUND FIELD PLATE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a channel between a source region and a drain region of a semiconductor device;
a gate region formed over the channel, the channel comprising an access region formed between the gate region and the drain
region;

a strip-ground field plate formed over the access region, the strip-ground field plate connected to at least one of the source
region or a ground plane;

a first dielectric layer formed between the strip-ground field plate and the access region;
a second dielectric layer formed over the gate region and the strip-ground field plate; and
a source field plate formed over the second dielectric layer.

US Pat. No. 9,305,851

SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH FLUORESCENCE DETECTION

Taiwan Semiconductor Manu...

9. A method comprising:
providing an incident light;
performing a chemical-mechanical planarization (CMP) on an article using a polishing fluid, the polishing fluid including
a plurality of emitter particles that are capable of emitting a fluorescent light in response to an incident light and a plurality
of surfactant particles that attach the emitter particles, wherein the surfactant particles are capable of detaching from
the emitter particles and attaching to a CMP stop material of the article when the CMP stop material is exposed to the polishing
fluid;

detecting the fluorescent light; and
adjusting the performing of the CMP in response to the detected fluorescent light, wherein the fluorescent light is detected
to have a first intensity when the surfactant particles attach the emitter particles and the fluorescent light is detected
to have a second intensity when the surfactant particles detach the emitter particles.

US Pat. No. 9,184,289

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, comprising:
forming an active region adjacent a channel of the semiconductor device, comprising:
implanting a first dopant adjacent the channel to form a doped region;
increasing, after the implanting, a temperature from a first temperature to a second temperature while applying a protective
agent to the doped region, and increasing the temperature from the second temperature to a third temperature while applying
the protective agent to the doped region and while exposing the doped region to a second dopant and a growth agent to form
a growth region over the doped region; and

annealing the doped region and the growth region to activate a dopant within the doped region and to form a first repaired
lattice structure in the doped region to form a repaired doped region, the annealing performed while applying the protective
agent to the doped region and to the growth region and while exposing the doped region and the growth region to the second
dopant and the growth agent at the third temperature, the active region comprising the repaired doped region and the growth
region over the repaired doped region.

US Pat. No. 9,299,657

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

11. A semiconductor device, comprising:
a first conductive portion over a substrate;
a second conductive portion over the substrate;
a third conductive portion over the substrate;
a dielectric layer over the first conductive portion
a first high-resistance portion over the dielectric layer; and
a first plug portion over the first high-resistance portion, the second conductive portion, and the third conductive portion,
wherein the first plug portion electrically connects the second conductive portion and the third conductive portion,

wherein the first high-resistance portion comprises a titanium nitride layer or an aluminum nitride layer.

US Pat. No. 9,299,784

SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a first channel disposed over a substrate and having a first linear surface and a first non-linear surface, wherein the first
non-linear surface defines a first angle relative to the first linear surface and a second angle relative to a second linear
surface of the first channel, the first angle about 40 degrees to about 50 degrees, the second angle about 40 degrees to about
50 degrees;

a first dielectric region surrounding the first channel;
a second channel disposed over the first channel and having a third linear surface and a third non-linear surface;
a second dielectric region surrounding the second channel; and
a gate electrode surrounding the first dielectric region and the second dielectric region.

US Pat. No. 9,286,973

DEVICE AND METHOD FOR FORMING RESISTIVE RANDOM ACCESS MEMORY CELL

Taiwan Semiconductor Manu...

1. A method for forming a resistive random access memory (RRAM) cell, comprising:
providing a first voltage to a first word line connected to a first RRAM cell to form the first RRAM cell; and
providing a negative voltage to a second word line connected to a second RRAM cell that shares a first source line and a first
bit line with the first RRAM cell during the formation of the first RRAM cell.

US Pat. No. 9,343,151

RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF RESETTING A RESISTIVE RANDOM ACCESS MEMORY

Taiwan Semiconductor Manu...

1. A resistive random access memory (RRAM), comprising:
a resistor comprising a cap side electrode and a dielectric side electrode;
a transistor, a drain of the transistor electrically connected to the dielectric side electrode;
a first voltage source electrically connected to a source of the transistor; and
a second voltage source electrically connected to a gate of the transistor, wherein for a reset operation comprising at least
two loops, the first voltage source provides a lower voltage in a second loop than the first voltage source does in a first
loop, and the second voltage source provides a higher voltage in the second loop than the second voltage source does in the
first loop.

US Pat. No. 9,176,388

MULTI-LINE WIDTH PATTERN CREATED USING PHOTOLITHOGRAPHY

Taiwan Semiconductor Manu...

19. A method comprising:
forming a polymer layer over a substrate;
patterning the polymer layer to form a first feature and a second feature, the first feature and the second feature being
separated at a first distance;

applying a rinse material to the polymer layer including the first feature and the second feature;
removing the rinse material from the polymer layer including the first feature and the second feature to cause the first feature
and the second feature to come into contact with each other; and

forming a third feature based on the first feature and the second feature being in contact with each other,
wherein the patterning the polymer layer to form the first feature and the second feature includes: patterning the polymer
layer to form a fourth feature and a fifth feature, the fourth feature and the fifth feature being separated at a second distance
larger than the first distance.

US Pat. No. 9,087,773

IMPLANT REGION DEFINITION

Taiwan Semiconductor Manu...

1. A method for defining one or more implant regions, comprising:
applying a first implant mask to a semiconductor arrangement, the first implant mask covering a first active region and a
second active region, the first implant mask defining a first implant region corresponding to the first active region; and

applying a second implant mask to the semiconductor arrangement, the second implant mask covering a third active region and
the second active region, the second implant mask and the first implant mask defining a second implant region corresponding
to an overlap between the first implant mask and the second implant mask over the second active region, the second implant
mask defining a third implant region corresponding to the third active region.

US Pat. No. 9,202,792

STRUCTURE AND METHOD OF PROVIDING A RE-DISTRIBUTION LAYER (RDL) AND A THROUGH-SILICON VIA (TSV)

Taiwan Semiconductor Manu...

1. A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package, the method
comprising:
preparing a wafer for bonding to a semiconductor package, the wafer comprising a low resistance substrate containing the RDL
and the TSV for making an input/output (I/O) connection point of the semiconductor package available at another location,
wherein the RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation
trench, and wherein the TSV is bounded by the isolation trench and the RDL; and

bonding the wafer to the semiconductor package.

US Pat. No. 9,213,353

BAND GAP REFERENCE CIRCUIT

Taiwan Semiconductor Manu...

1. A band gap reference circuit, comprising:
a first resistor (R1), a second resistor (R2), a third resistor (R3), a fourth resistor (Ra), and a fifth resistor (Rb);

a first operational amplifier (A) comprising a first input, a second input, and an amplifier output, the second input of amplifier
A connected to R2 and R3;

a first field effect transistor (FET) (P1) comprising a first gate, a first source, and a first drain, the first drain of P1 connected to R1 and R2;

a second FET (P2) comprising a second gate, a second source, and a second drain;

a third FET (P3) comprising a third gate, a third source, and a third drain, the first gate, the second gate, and the third gate connected
to the amplifier output of amplifier A;

a fourth FET (Pa) comprising a fourth gate, a fourth source, and a fourth drain, the fourth source connected to the second
drain and Ra, the fourth gate connected to the third drain and Rb, the fourth drain connected to a first capacitor (Ca);

a first bipolar junction transistor (BJT) (Q1) comprising a first base, a first emitter, and a first collector, the first emitter connected to the first input of amplifier
A and R1;

a second BJT (Q2) comprising a second base, a second emitter, and a second collector, the second emitter connected to R3; and

a third BJT (Q3) comprising a third base, a third emitter, and a third collector, the third emitter connected to Ra.

US Pat. No. 9,306,024

METHOD OF FORMING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device comprising at least one of:
a first cycle, the first cycle comprising:
forming a first zirconium layer over a dielectric layer of the semiconductor device;
doping the first zirconium layer using nitrogen plasma to generate a first nitrogen doped zirconium layer; and
applying remote oxygen plasma to the first nitrogen doped zirconium layer to generate a first nitrogen doped zirconium oxide
layer; or

a second cycle, the second cycle comprising:
applying remote oxygen plasma to the dielectric layer to form a first oxide layer over the dielectric layer;
doping the first oxide layer using the nitrogen plasma to generate a first nitrogen doped oxide layer; and
applying zirconium to the first nitrogen doped oxide layer to generate a first nitrogen doped zirconium oxide layer; and
annealing the semiconductor device to form a dielectric film from the first nitrogen doped zirconium oxide layer, the dielectric
film comprising a crystalline structure, the crystalline structure comprising a substantially uniform composition of zirconium,
nitrogen and oxygen.

US Pat. No. 9,177,953

CIRCULAR SEMICONDUCTOR DEVICE WITH ELECTROSTATIC DISCHARGE (ESD) DEVICE AND FUNCTIONAL DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a first circular sector defined by a first radius, a second radius and a first arc connected there between, the first circular
sector comprising:

a first electrostatic discharge (ESD) device comprising:
a first source region; and
a first central drain region;
a second circular sector defined by a third radius, a fourth radius and a second arc connected there between, the second circular
sector comprising:

a first functional device comprising:
a second source region; and
a second central drain region in contact with the first central drain region; and
a first disconnect region disposed between the first source region and the second source region.

US Pat. No. 9,323,244

SEMICONDUCTOR FABRICATION COMPONENT RETUNING

Taiwan Semiconductor Manu...

1. A method for retuning a parameter of a semiconductor fabrication component, comprising:
evaluating processing data associated with a semiconductor fabrication component to formulate performance indices;
performing one or more fabrication process change simulations based upon the performance indices to generate a component operating
behavior data structure;

identifying a first tuning value for a first parameter used by the semiconductor fabrication component based upon the component
operating behavior data structure indicating the first tuning value retunes the semiconductor fabrication component with respect
to a first current value for the first parameter specified within the processing data;

identifying a second tuning value for a second parameter used by the semiconductor fabrication component based upon the component
operating behavior data structure indicating the second tuning value retunes the semiconductor fabrication component with
respect to a second current value for the second parameter specified within the processing data; and

retuning the first parameter from the first current value to the first tuning value and the second parameter from the second
current value to the second tuning value, wherein:

the component operating behavior data structure comprises a characteristic surface for the first parameter and the second
parameter; and

the characteristic surface comprises a surface comprising a retuning point that correlates a selected retuning cost to a tuning
parameter pairing value corresponding to the first tuning value for the first parameter and the second tuning value for the
second parameter, the first tuning value and the second tuning value selected based upon the tuning parameter pairing value
being correlated to the selected retuning cost.

US Pat. No. 9,287,170

CONTACT STRUCTURE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

16. A method of forming a semiconductor device comprising:
lining an opening with metal, the opening at least partially defined by a dielectric;
performing a first annealing operation to form a silicide from the metal;
forming a second dielectric in the opening after forming the silicide;
etching the second dielectric to form a second opening over the silicide;
forming a cobalt plug in the second opening over the silicide; and
performing a second annealing operation on the cobalt plug at a first temperature while exposing the cobalt plug to a first
gas to form an annealed cobalt plug.

US Pat. No. 9,252,271

SEMICONDUCTOR DEVICE AND METHOD OF MAKING

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a channel region disposed between a source region and a drain region;
a gate structure over the channel region;
an interlayer dielectric (ILD) layer proximate the gate structure and not reaching a to surface of the gate structure; and
an ILD stress layer extending in a direction perpendicular to a sidewall of the gate structure and over the ILD layer.

US Pat. No. 9,466,663

SEMICONDUCTOR ARRANGEMENT HAVING CAPACITOR SEPARATED FROM ACTIVE REGION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
an active region comprising a semiconductor device;
a first dielectric layer overlying the active region;
a second dielectric layer overlying the active region and in direct contact with the first dielectric layer; and
a capacitor extending through the first dielectric layer and the second dielectric layer, the capacitor having a first electrode
layer, a second electrode layer, and an insulating layer between the first electrode layer and the second electrode layer,
wherein at least three additional dielectric layers are between a bottom surface of the capacitor and the active region.

US Pat. No. 9,099,421

SURFACE PROFILE FOR SEMICONDUCTOR REGION

Taiwan Semiconductor Manu...

1. A method for controlling a surface profile for a region of a semiconductor, comprising:
applying a first concentration of a first material to a region while an etching to deposition (E/D) ratio is set to a first
number less than one and greater than zero to expand the region; and

applying a second concentration of the first material to the region while the E/D ratio is set to a second number greater
than one to trim at least a portion of the region, wherein trimming the at least a portion of the region is configured to
control a surface profile for the region and wherein the first concentration is different than the second concentration.

US Pat. No. 9,379,718

ALL-DIGITAL PHASE-LOCKED LOOP (ADPLL)

Taiwan Semiconductor Manu...

1. An all-digital phase-locked loop (ADPLL), comprising:
a first circuit, configured to:
monitor a first signal, the first signal comprising a code of fine-tuning;
output a second signal, the second signal having a voltage within a first voltage range when the code of fine-tuning is equal
to a first specified value; and

output a third signal, the third signal having a voltage within a second voltage range when the code of fine-tuning is equal
to a second specified value;

a second circuit, configured to:
output a fourth signal, the fourth signal comprising a code of coarse-tuning;
increase the code of coarse-tuning when the voltage of the second signal is within the first voltage range; and
decrease the code of coarse-tuning when the voltage of the third signal is within the second voltage range; and
a third circuit, configured to:
output a frequency divider signal to the second circuit, wherein:
the frequency divider signal is generated based upon the second signal and the third signal, and
the second circuit generates the fourth signal based upon the frequency divider signal.

US Pat. No. 9,367,654

VARIATION MODELING

Taiwan Semiconductor Manu...

1. A method for back-end-of-line variation modeling, comprising:
defining a bounding box for a device within a design layout of a semiconductor arrangement, wherein a size of the bounding
box is a function of patterns surrounding the device;

determining a back-end-of-line variation parameter for the bounding box;
applying, using a computing device, the back-end-of-line variation parameter as a back-end-of-line constraint for simulation
of the design layout; and

modifying a physical feature of the design layout based upon a result of the simulation, wherein the design layout is implemented
in fabrication of the device.

US Pat. No. 9,202,866

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a column extending through a dielectric;
a first conductor in contact with the dielectric and in contact with a bottom surface of the column;
an insulator concentrically surrounding the column; and
a second conductor concentrically surrounding the insulator,
the column configured as at least one of a column source, a column drain, a column channel, and
the second conductor configured as a conductor gate.

US Pat. No. 9,356,069

PHOTO DIODE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a photo diode, comprising:
forming a first pair of electrodes and a second pair of electrodes over a substrate by using a conductive layer;
forming a dielectric layer over the substrate;
patterning the dielectric layer over the substrate;
forming a photo conversion layer over the substrate; and
forming a color filter layer over the photo conversion layer,
wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a
first pixel from a second portion of the color filter layer corresponding to a second pixel, and a refractive index of the
dielectric layer is lower than a refractive index of the color filter layer,

wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second
pixel, and

wherein at least a portion of the dielectric layer separates a first portion of the photo conversion layer corresponding to
the first pixel from a second portion of the photo conversion layer corresponding to the second pixel, and a refractive index
of the dielectric layer is lower than a refractive index of the photo conversion layer.

US Pat. No. 9,607,942

SEMICONDUCTOR DEVICE WITH PATTERNED GROUND SHIELDING

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a first inductor;
a patterned ground shielding (PGS) underlying the first inductor, the PGS comprising a first portion and a second portion;
a first switch for electrically coupling the first portion of the PGS to the second portion of the PGS, wherein the first
switch underlies the PGS and the first portion of the PGS is electrically coupled to the second portion of the PGS when the
first switch is in a first state;

a conductive element coupling the first switch to the first portion of the PGS, wherein the conductive element is situated
between the PGS and the first switch;

a glue oxide layer underlying the first switch;
a first dielectric layer underlying the glue oxide layer; and
a second inductor underlying the first dielectric layer.

US Pat. No. 9,209,201

SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE TRANSISTOR LAYERS

Taiwan Semiconductor Manu...

1. A method of fabricating a multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping
second region and different transistor types fabricated using different channel material, the method comprising:
providing a wafer with first channel material above a buried oxide layer;
transforming the first channel material in the second region to an oxidation layer;
bonding a second buried oxide layer with a second channel material above the second buried oxide layer to the top surface
of the first channel material in the first region and the oxidation layer in the second region;

removing the second channel material and the second buried oxide layer from the first region; and
fabricating a first transistor type in the first region and a second transistor type in the second region.

US Pat. No. 9,064,986

PHOTO DIODE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a photo diode, comprising:
forming a first bottom electrode corresponding to a first pixel and a second bottom electrode
corresponding to a second pixel over a substrate;
forming a dielectric layer over the substrate;
patterning the dielectric layer over the substrate;
forming a photo conversion layer over the substrate;
forming a top electrode over the photo conversion layer; and
forming a color filter layer over the top electrode,
wherein at least a portion of the dielectric layer separates a first portion of the color filter layer corresponding to a
first pixel from a second portion of the color filer layer corresponding to a second pixel, and a refractive index of the
dielectric layer is lower than a refractive index of the color filter layer.

US Pat. No. 9,466,495

CHEMICAL DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICE FABRICATION

Taiwan Semiconductor Manu...

1. A method for fabricating semiconductor devices, the method comprising:
providing a substrate, depositing an interlayer dielectric on the substrate, forming trenches in the interlayer dielectric
to expose a first region of the substrate, and then providing a polymer layer on the first region on the substrate;

applying an oxygen-based plasma to remove the polymer layer from the first region;
applying an oxidizing solution to generate a dielectric layer on the first region after the removal of the polymer layer;
and

forming a conductive layer on the dielectric layer.

US Pat. No. 9,257,178

DEVICES AND METHODS FOR WRITING TO A MEMORY CELL OF A MEMORY

Taiwan Semiconductor Manu...

1. A device for writing to a memory cell of a memory, the device comprising:
a voltage-generating circuit configured to generate a write voltage;
a current mirror circuit configured to generate a mirror current that mirrors a write current flowing through the memory cell
of the memory, and including

a first transistor having a source terminal, and a gate terminal and a drain terminal coupled to each other and to one of
a bit line and a source line of the memory, and

a second transistor having a source terminal and a gate terminal coupled to the source terminal and the gate terminal of the
first transistor, respectively, and a drain terminal coupled to a node;

a current source circuit coupled to the node and configured to generate a compliance current; and
a switch circuit coupled to the node and between the voltage-generating circuit and the source terminals of the first and
second transistors, and configured to detect a voltage at the node, to permit application of the write voltage to the memory
cell of the memory when the voltage detected thereby is less or greater than a threshold value, and to inhibit the application
of the write voltage to the memory cell of the memory when the voltage detected thereby increases or decreases to the threshold
value.

US Pat. No. 9,214,513

FIN STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A fin structure, comprising:
a fin core protruding from a substrate, comprising:
a first core portion; and
a second core portion over the first core portion; and
a fin shell covering a portion of a sidewall of the fin core,
wherein a material of the second core portion has a lattice constant between a material of the first core portion and a material
of the fin shell.

US Pat. No. 9,214,540

N-TYPE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTOR FOR ELECTROSTATIC DISCHARGE (ESD)

Taiwan Semiconductor Manu...

1. An n-type metal oxide semiconductor (NMOS) transistor for electrostatic discharge (ESD), comprising:
a first region comprising a p-type well (PW) region, a first native NMOS blocked implant (NTN) region, and a second NTN region;
a first n-type plus (NP) region above at least some of the first NTN region;
a first p-type plus (PP) region above at least some of at least one of the first NTN region or the PW region;
a dummy gate stack between the first NP region and the first PP region;
a second NP region above at least some of the PW region;
a second PP region above at least some of the second NTN region;
a shallow trench isolation (STI) region above at least some of at least one of the PW region or the second NTN region; and
a gate stack above at least some of the PW region:
the first PP region between the first NP region and the second NP region;
the second NP region between the first PP region and the second PP region; and
the STI region between the second NP region and the second PP region.

US Pat. No. 9,472,666

ULTRA HIGH VOLTAGE DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device having a first region and a second region, the second region having a greater curvature than the
first region, the device comprising:
an N-type epitaxy layer in the first region and the second region;
a P-well in the N-type epitaxy layer;
a first N+ diffusion layer in the N-type epitaxy layer;
a second N+ diffusion layer in the P-well; and
a P+ diffusion layer in the P-well and in contact with the second N+ diffusion layer, wherein the P+ diffusion layer has a
greater area in the second region than in the first region, and (ii) comprises a greater extension in the second region than
in the first region.

US Pat. No. 9,437,699

METHOD OF FORMING NANOWIRES

Taiwan Semiconductor Manu...

11. A method of forming nanowires, comprising:
providing a substrate;
forming a protrusion comprising a sacrificial material on the substrate;
performing an epitaxial growth process to form a nanowire material symmetric with respect to the protrusion, the nanowire
material including L-shaped portions that coat sidewalls of the protrusion and portions of the substrate; and

removing (i) the sacrificial material, and (ii) portions of the nanowire material coating the substrate to provide two symmetric
nanowires made of the nanowire material, wherein the removal of the sacrificial material exposes inner sidewalls of the nanowires.

US Pat. No. 9,318,488

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a first active region adjacent a first side of a shallow trench isolation (STI) region, the first active region comprising:
a first proximal fin adjacent the STI region and having a first proximal fin height, the first proximal fin being a first
projection of a substrate; and

a first distal fin adjacent the first proximal fin and having a first distal fin height, the first distal fin being a second
projection of the substrate, the first proximal fin height less than the first distal fin height, the first proximal fin disposed
between the STI region and the first distal fin.

US Pat. No. 9,361,980

RRAM ARRAY USING MULTIPLE RESET VOLTAGES AND METHOD OF RESETTING RRAM ARRAY USING MULTIPLE RESET VOLTAGES

Taiwan Semiconductor Manu...

1. A resistive random access memory (RRAM) array, comprising:
a word line voltage source configured to produce a first voltage and a second voltage, wherein in a first operation loop the
first voltage is lower than the second voltage;

a first RRAM connected to a first word line and the word line voltage source;
a second RRAM connected to a second word line and the word line voltage source, wherein a first electrical resistance between
the first word line and the word line voltage source is lower than a second electrical resistance between the second word
line and the word line voltage source, the word line voltage source is configured to provide the first voltage for resetting
the first RRAM, the word line voltage source is configured to provide the second voltage for resetting the second RRAM; and

a verifier configured to determine whether the first and second RRAM were successfully reset, the word line voltage source
being configured to provide, in a second operation loop, first and second voltages that are higher than the respective first
and second voltages provided in the first operation loop, the word line voltage source providing the higher first and second
voltages based on a determination by the verifier that the first and second RRAM were not successfully reset.

US Pat. No. 9,356,020

SEMICONDUCTOR ARRANGEMENT

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first semiconductor device comprising:
a first type region having a first conductivity type, a second type region having a second conductivity type, and a first
channel region between the first type region and the second type region;

a second semiconductor device adjacent the first semiconductor device, the second semiconductor device comprising:
a third type region having a third conductivity type, a fourth type region having a fourth conductivity type, and a second
channel region between the first type region and the second type region;

a first insulator layer comprising a first insulator portion having a first sidewall in contact with the first semiconductor
device and a second insulator portion having a second sidewall in contact with the second semiconductor device, the first
sidewall having a first insulator height and the second sidewall having a second insulator height, wherein the first insulator
height is different than the second insulator height; and

a dielectric layer over a top surface of the first insulator layer, the dielectric layer having a first sidewall in contact
with the first channel region and a second sidewall in contact with the second channel region.

US Pat. No. 9,318,504

DENSITY GRADIENT CELL ARRAY

TAIWAN SEMICONDUCTOR MANU...

1. An array of cells for mitigating density gradients between regions, comprising:
an array of gates comprising:
a first set of gates associated with a first gate dimension; and
a second set of gates associated with a second gate dimension, at least one of a number of gates associated with the first
set of gates or a number of gates associated with the second set of gates based on a first gate density of a first region;
and

an array of oxide defined (OD) regions comprising:
a first set of OD regions associated with a first OD dimension; and
a second set of OD regions associated with a second OD dimension, at least one of a number of OD regions associated with the
first set of OD regions or a number of OD regions associated with the second set of OD regions based on a first OD density
of the first region.

US Pat. No. 9,184,250

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first gate having a first gate height and a first gate length, the first gate adjacent a first contact having a first contact
width, a first bottom contact length and a first top contact length lying within a first top contact length plane, the first
top contact length plane a first critical contact distance from a bottom surface of the first contact; and

a second gate having a second gate height and a second gate length a first pitch distance from the first gate, the second
gate adjacent the first contact, such that the first contact is between the first gate and the second gate, where dimensions
of the semiconductor arrangement conform to

where
k2 is a second constant of about 0.26 to about 0.30,
H is at least one of the first gate height or the second gate height,
k3 is a third constant of about 0.70 to about 0.74,
L is at least one of the first gate length or the second gate length,
P is the first pitch distance,
k4 is a fourth constant of about 48 to about 52,
k5 is a fifth constant of about 0.18 to about 0.22, and
k6 is a sixth constant of about 0.78 to about 0.82.

US Pat. No. 9,343,412

METHOD OF FORMING MOSFET STRUCTURE

Taiwan Semiconductor Manu...

1. A method of forming a MOSFET structure, comprising:
forming an epitaxial layer;
forming a cap layer above the epitaxial layer;
forming a first trench above the epitaxial layer, wherein the forming the first trench above the epitaxial layer comprises
patterning an inter-layer dielectric (ILD) layer of the MOSFET structure to form the first trench;

depositing a protection layer within the first trench; and
forming a bottom photoresist layer above the protection layer and the ILD layer;
forming a first photoresist layer above the bottom photoresist layer; and
forming a second photoresist layer above the first photoresist layer,
wherein the protection layer is a material selected from the group consisting of germanium and silicon-germanium.

US Pat. No. 9,324,578

HARD MASK RESHAPING

Taiwan Semiconductor Manu...

1. A method for reshaping a hard mask, comprising:
forming a hard mask over a layer of a semiconductor arrangement, the hard mask comprising a first hard mask portion;
evaluating whether a dimension of the first hard mask portion corresponds to a target dimension;
when the dimension of the first hard mask portion is less than the target dimension, applying a coating material over the
first hard mask portion to create a coated hard mask comprising a coated first hard mask portion; and

responsive to a coated dimension of the coated first hard mask portion corresponding to the target dimension, performing an
etch through the coated hard mask to etch the layer to create an etched layer.

US Pat. No. 9,319,053

PHASE-LOCKED LOOP (PLL)

TAIWAN SEMICONDUCTOR MANU...

1. A phase-locked loop (PLL), comprising:
a dithering circuit configured to:
receive a first tuning signal; and
dither the first tuning signal to generate a dither signal;
a tuning circuit comprising an adder configured to generate a digitally controlled oscillator (DCO) input signal based upon
a combination of the dither signal and a second tuning signal; and

a DCO configured to:
receive the DCO input signal generated based on the dither signal and the second tuning signal; and
generate an output signal having an output frequency based on the DCO input signal.

US Pat. No. 9,484,460

SEMICONDUCTOR DEVICE HAVING GATE DIELECTRIC SURROUNDING AT LEAST SOME OF CHANNEL REGION AND GATE ELECTRODE SURROUNDING AT LEAST SOME OF GATE DIELECTRIC

Taiwan Semiconductor Manu...

18. A semiconductor device, comprising:
a first type region comprising a first conductivity type;
a second type region comprising a second conductivity type;
a channel region extending between the first type region and the second type region, the first type region in contact with
the channel region;

a drift region extending between the second type region and the channel region;
a gate dielectric surrounding at least some of the channel region;
a gate electrode surrounding at least some of the gate dielectric; and
a dielectric in contact with the drift region, the dielectric different than the gate dielectric.

US Pat. No. 9,478,287

CIRCUITS AND METHODS FOR DETECTING WRITE OPERATION IN RESISTIVE RANDOM ACCESS MEMORY (RRAM) CELLS

Taiwan Semiconductor Manu...

1. A memory cell, comprising:
a resistive random access memory (RRAM) cell, comprising:
a select transistor; and
a programmable resistor, coupled to a source or a drain of the select transistor,
wherein the programmable resistor is configured to change between a relatively high resistance and a relatively low resistance
responsive to changes in a cell current through the RRAM cell, a dynamic voltage being based on the resistance of the programmable
resistor of the RRAM cell; and

a write detection circuit coupled to the RRAM cell and configured to receive the dynamic voltage therefrom, the write detection
circuit comprising:

a voltage shifting circuit configured to receive the dynamic voltage and a first voltage and to provide as output a second
voltage approximately equal to the first voltage divided by approximately two, minus the dynamic voltage; and

an inverter comparator circuit comprising a master circuit and a slave circuit,
wherein the master circuit is coupled to the voltage shifting circuit and is configured to provide as output a first bias
voltage,

wherein the slave circuit is coupled to the voltage shifting circuit and to the master circuit and is configured to provide
as output a write detection voltage based on the second voltage and the first bias voltage.

US Pat. No. 9,425,157

SUBSTRATE AND PACKAGE STRUCTURE

Taiwan Semiconductor Manu...

1. A package structure, comprising:
a chip, comprising a plurality of pillar bumps, each of the plurality of pillar bumps having a bump size;
a substrate, having a first area and a second area, and comprising a plurality of pads, each of the plurality of pads having
a pad size, wherein a ratio of the pad size to the bump size in the first area is larger than a ratio of the pad size to the
bump size in the second area; and

a plurality of solders, electrically connecting the plurality of pillar bumps and the plurality of pads.

US Pat. No. 9,325,296

BUFFER OFFSET MODULATION

TAIWAN SEMICONDUCTOR MANU...

1. A method for buffer offset modulation, comprising:
determining an offset rotation for at least one of a first chop-able buffer (FB) or a second chop-able buffer (SB) based at
least in part on at least one of a first output of a sigma-delta analog digital converter (ADC) or a reference clock; and

generating a second output of the ADC based at least in part on the offset rotation, the second output comprising a modulated
ADC offset.

US Pat. No. 9,315,892

METHOD AND APPARATUS FOR CONTROLLING BEAM ANGLE DURING ION IMPLANTATION OF A SEMICONDUCTOR WAFER BASED UPON PRESSURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of ion implantation, comprising:
determining a set of implant parameters for an implant layer of a wafer being implanted with ions;
accelerating one or more ions to a first energy level based on the set of implant parameters;
implanting, within a process chamber, at least some of the one or more ions into the implant layer of the wafer; and
measuring a pressure within the process chamber, wherein:
the implanting comprises controlling a beam angle, associated with at least some of the one or more ions, via an electroplate
based upon the pressure within the process chamber.

US Pat. No. 9,070,591

ADJUSTING INTENSITY OF LASER BEAM DURING LASER OPERATION ON A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method for adjusting an intensity of a laser beam applied to a semiconductor device, wherein an applied intensity of
the laser beam is indicative of a magnitude at which the laser beam is emitted and wherein a reflection intensity of the laser
beam is indicative of a magnitude at which the laser beam is reflected from the semiconductor device, comprising:
measuring the reflection intensity of the laser beam, and
adjusting the applied intensity of the laser beam as a function of the reflection intensity.

US Pat. No. 9,064,989

PHOTO DIODE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A photo diode, comprising:
a substrate;
a first pair of electrodes and a second pair of electrodes over the substrate, formed by a conductive layer;
a photo conversion layer over the substrate;
a color filter layer over the photo conversion layer; and
a dielectric layer for separating a first portion of the color filter layer corresponding to a first pixel from a second portion
of the color filter layer corresponding to a second pixel, wherein a refractive index of the dielectric layer is lower than
a refractive index of the color filter layer,

wherein the first pair of electrodes corresponds to the first pixel and the second pair of electrodes corresponds to the second
pixel,

wherein at least a portion of the dielectric layer separates a first portion of the photo conversion layer corresponding to
the first pixel from a second portion of the photo conversion layer corresponding to the second pixel, and a refractive index
of the dielectric layer is lower than a refractive index of the photo conversion layer.

US Pat. No. 9,576,896

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement, comprising:
a dielectric layer;
a first metal layer overlying a first portion of the dielectric layer, wherein:
a first void is defined by a first sidewall of the first metal layer and a first sidewall of the dielectric layer, and
the first sidewall of the first metal layer is spaced apart from the first sidewall of the dielectric layer by a first distance;
and

a first interconnect overlying the first metal layer and comprising:
a first interconnect metal plug; and
a first interconnect metal layer surrounding sidewalls and a bottom surface of the first interconnect metal plug, wherein:
a second void is defined by a first sidewall of the first interconnect metal layer and a second sidewall of the dielectric
layer, and

the first sidewall of the first interconnect metal layer is spaced apart from the second sidewall of the dielectric layer
by a second distance different than the first distance.

US Pat. No. 9,443,869

SYSTEMS AND METHODS FOR A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE SEMICONDUCTOR-DEVICE LAYERS

Taiwan Semiconductor Manu...

1. A method of fabricating a multilayer semiconductor device structure, comprising:
providing a first wafer comprising first channel material bonded to a first buried oxide layer;
fabricating a first semiconductor device layer from the first channel material, the first semiconductor device layer comprising
a patterned top surface, the patterned top surface comprising insulator material and conductor material, wherein a pattern
density of the insulator material is greater than 40 percent;

providing a second wafer comprising second channel material bonded to a second buried oxide layer;
bonding the second buried oxide layer to the patterned top surface of the first semiconductor device layer;
fabricating a second semiconductor device layer from the second channel material; and
interconnecting a feature of the first semiconductor device layer with a feature of the second semiconductor device layer.

US Pat. No. 9,343,140

BOOSTED READ WRITE WORD LINE

Taiwan Semiconductor Manu...

1. A boosted control block, comprising:
a delay module coupled to at least one of a boosted read enabled pulse (RENP) line or a boosted write enabled pulse (WENP)
line;

a first NAND gate comprising a first NAND input, a second NAND input, and a first NAND output, wherein:
the first NAND input is coupled to the delay module; and
the second NAND input is coupled to the at least one of the RENP line or the WENP line;
a first inverter comprising a first inverter input and a first inverter output, wherein:
the first inverter input is coupled to the first NAND output, and
the first inverter output is configured to generate a first word line signal at the first inverter output;
a second inverter comprising a second inverter input and a second inverter output, wherein the second inverter input is coupled
to the first inverter output;

a third inverter comprising a third inverter input and a third inverter output, wherein the third inverter input is coupled
to the second inverter output; and

a coupled capacitor coupled to the third inverter output, wherein the coupled capacitor is configured to generate a second
boosted word line signal.

US Pat. No. 9,213,795

MULTIPLE VIA CONNECTIONS USING CONNECTIVITY RINGS

Taiwan Semiconductor Manu...

1. A method, comprising:
generating a first connectivity ring to connect one or more ring one vias, the first connectivity ring comprising mandrel
and the one or more ring one vias extending through the mandrel;

generating a second connectivity ring to connect one or more ring two vias, the second connectivity ring comprising a passive
pattern and at least partially surrounded by the first connectivity ring, the one or more ring two vias extending through
the passive pattern; and

generating one or more cuts within the first connectivity ring to isolate a first ring one via of the one or more ring ones
vias from a second ring one via of the one or more ring ones vias, wherein the method is implemented by a processing unit
that executes processor-executable instructions stored on a non-transitory computer-readable medium.

US Pat. No. 9,209,252

FORMATION OF NICKEL SILICON AND NICKEL GERMANIUM STRUCTURE AT STAGGERED TIMES

Taiwan Semiconductor Manu...

1. A method of generating a semiconductor device on a single semiconductor substrate, comprising:
providing a substrate having a silicon material portion;
forming a first set of source/drain contacts from a first metal on a substrate surface that includes the Silicon material
portion;

annealing the first metal with the Silicon material portion at a first temperature to form the first set of source/drain contacts;
subsequent to forming the first set of source/drain contacts, disposing a germanium material portion on the substrate surface
on which the first set of source/drain contacts are formed proximate the silicon material portion;

forming a second set of source/drain contacts from a second metal on the Germanium material portion; and
annealing the second metal with the Germanium material portion at a second temperature to form the second set of source/drain
contacts, wherein the second temperature is less than the first temperature.

US Pat. No. 9,159,573

SYSTEMS AND METHODS FOR MONITORING AND CONTROLLING PARTICLE SIZES IN SLURRIES

Taiwan Semiconductor Manu...

1. A system for preparing a plurality of slurry particles, the system comprising:
a source tank configured to store and provide a stock slurry containing the slurry particles;
a mixing tank coupled downstream of the source tank;
a sampling module coupled between the source tank and the mixing tank configured to sample the slurry particles and obtain
at least one particle size parameter associated with the slurry particles;

an ultrasonic vibrator arranged in a circulation path to the source tank; and
a controller coupled to the ultrasonic vibrator and the sampling module, controlling the ultrasonic vibrator to vibrate the
slurry particles based on the at least one particle size parameter.

US Pat. No. 9,507,897

CIRCUIT ARRANGEMENT FOR MODELING TRANSISTOR LAYOUT CHARACTERISTICS

Taiwan Semiconductor Manu...

1. A circuit arrangement comprising:
a first current source having a first current input and a first current output;
a second current source having a second current input and a second current output;
a first diode having a first input node and a first output node;
a switching component having a first switching component node, a second switching component node, and a third switching component
node; and

a second diode having a second input node and a second output node;
a first node electrically connected to the first current source, the first diode, and the switching component;
a second node directly electrically connected to the first diode, the switching component, and the second diode; and
a third node electrically connected to the switching component, the second current source and the second diode.

US Pat. No. 9,425,042

HYBRID SILICON GERMANIUM SUBSTRATE FOR DEVICE FABRICATION

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:
a substrate;
a first buffer layer having a first germanium concentration formed on the substrate and formed with a recessed region thereinto;
a second buffer layer having a second germanium concentration formed in the recessed region in the first buffer laver, the
second germanium concentration being larger than the first germanium concentration;

a n-type transistor structure formed on the first buffer layer; and
a p-type transistor structure formed on the second buffer layer.

US Pat. No. 9,406,749

METHOD OF MANUFACTURING A HORIZONTAL GATE-ALL-AROUND TRANSISTOR HAVING A FIN

Taiwan Semiconductor Manu...

1. A method for fabricating a semiconductor structure, the method comprising:
providing a substrate;
forming a plurality of trenches, each of which extends into the substrate, wherein the substrate that is between a pair of
the trenches forms a semiconductor strip;

forming a middle semiconductor strip over the semiconductor strip;
forming a top semiconductor strip over the middle semiconductor strip, wherein the semiconductor strip, the middle semiconductor
strip, and the top semiconductor strip constitute a fin;

forming a groove that extends into the fin and that is defined by a groove-defining wall;
removing the groove-defining wall of the fin to form a hole that extends through the fin and that is defined by a hole-defining
wall;

enlarging the hole in the fin; and
cleaning the hole-defining wall of the fin.

US Pat. No. 9,172,376

CONTROLLING VOLTAGE AT PAD

Taiwan Semiconductor Manu...

1. A method for applying a first voltage at a pad, comprising:
activating a pull-up driver situated between a power supply outputting the first voltage and a node to pull the node to a
second voltage, the second voltage less than the first voltage by about a voltage threshold of the pull-up driver;

triggering, responsive to the node being pulled to the second voltage, a cross control circuit to activate one or more transistors
situated between the pull-up driver and the pad, comprising:

applying the first voltage to a first gate of a first transistor of the one or more transistors; and
pulling the pad to the first voltage responsive to activating the one or more transistors situated between the pull-up driver
and the pad.

US Pat. No. 9,142,404

SYSTEMS AND METHODS FOR ANNEALING SEMICONDUCTOR DEVICE STRUCTURES USING MICROWAVE RADIATION

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor device structure using microwave radiation, the method comprising:
providing a semiconductor device structure;
forming an interfacial layer on the semiconductor device structure;
forming a high-k dielectric layer on the interfacial layer;
performing pre-amorphization implantation on the semiconductor device structure before application of microwave radiation;
and

applying microwave radiation to anneal the semiconductor device structure for fabricating semiconductor devices.

US Pat. No. 9,111,996

SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a layer of semiconductor material, the method comprising:
providing a substrate;
forming an amorphous layer over the substrate, the amorphous layer including a semiconductor or a semiconductor alloy;
bonding a seed wafer to the amorphous layer, the seed wafer including a crystalline semiconductor structure;
performing a solid-phase epitaxial (SPE) growth process to crystallize the amorphous layer, the SPE growth process using the
crystalline semiconductor structure of the seed wafer as a crystal template; and

debonding the seed wafer.

US Pat. No. 9,812,395

METHODS OF FORMING AN INTERCONNECT STRUCTURE USING A SELF-ENDING ANODIC OXIDATION

1. A method of forming an interconnect structure, comprising:
forming a protruding structure on a substrate traversing between a first connection region and a second connection region
defined in the substrate, wherein the protruding structure is formed of a single material or a single compound material; and

oxidizing the protruding structure, wherein the oxidizing of the protruding structure forms a nanowire interconnect inside
the protruding structure, the protruding structure being oxidized by performing a self-ending anodic oxidation on the substrate
having the protruding structure,

the nanowire interconnect (i) being substantially surrounded by a dielectric layer formed by the anodic oxidation, the forming
of the dielectric layer reaching a termination point without external interference, and (ii) traversing between the first
connection region and the second connection region.

US Pat. No. 9,613,174

COMMON TEMPLATE FOR ELECTRONIC ARTICLE

Taiwan Semiconductor Manu...

1. A method for incorporating a common template into an electronic article design, comprising:
receiving a first set of polygon positions defining locations for forming polygons to interface with a first part;
receiving a second set of polygon positions defining locations for forming polygons to interface with a second part;
generating a common template mask set based on commonalities between the first set of polygon positions and the second set
of polygon positions;

generating a first under bump metallization (UBM) mask for the first set of polygon positions based upon differences between
the first set of polygon positions and the second set of polygon positions;

using a common template mask of the common template mask set to fabricate a first polygon at a first location defined by the
first set of polygon positions and a second polygon at a second location defined by the second set of polygon positions; and

using the first UBM mask to fabricate a third polygon at a third location defined by the first set of polygon positions.

US Pat. No. 9,528,194

SYSTEMS AND METHODS FOR FORMING NANOWIRES USING ANODIC OXIDATION

1. A method for forming one or more nanowires on a substrate, the method comprising:
forming a first protruding structure on the substrate;
placing the substrate including the first protruding structure in an electrolytic solution; and
forming the one or more nanowires inside the first protruding structure by oxidizing the first protruding structure, wherein
the first protruding structure is oxidized via an anodic oxidation that uses the substrate as part of an anode electrode,
the one or more nanowires being surrounded by a first dielectric material formed during the anodic oxidation, and wherein
the oxidizing of the first protruding structure comprises oxidizing a bottom portion of the first protruding structure at
a higher rate than a top portion of the first protruding structure.

US Pat. No. 9,508,603

FORMATION OF NICKEL SILICON AND NICKEL GERMANIUM STRUCTURE AT STAGGERED TIMES

Taiwan Semiconductor Manu...

1. A method comprising:
forming in a first region of a substrate a semiconductor material layer that includes a material different from a material
of the substrate;

providing a first source/drain contact, wherein providing the first source/drain contact includes forming first metal on the
semiconductor material layer;

providing a second source/drain contact, wherein providing the second source/drain contact includes forming second metal in
a second region of the substrate, wherein providing the first source/drain contact and providing the second source/drain contact
are performed one after the other; and

surrounding the first and second source/drain contacts with a dielectric material layer.

US Pat. No. 9,502,364

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor package comprising a chip and a component, comprising:
providing a temporary bonding layer over a carrier;
forming an insulator layer over the temporary bonding layer;
forming a backside redistribution layer over the insulator layer;
providing a pre-solder over a portion of the backside redistribution layer;
providing the chip and the component over the backside redistribution layer and contacting the component to the pre-solder;
and

providing a molding compound over the component and adjacent to the chip, wherein forming the backside redistribution layer
over the insulator layer further comprises forming a u-shape pad having an open structure in the backside redistribution layer.

US Pat. No. 9,502,122

SYSTEMS, DEVICES AND METHODS FOR MEMORY OPERATIONS

Taiwan Semiconductor Manu...

15. A memory device comprising:
a plurality of memory blocks;
a common source line shared by the plurality of memory blocks;
a sector driver circuit shared by the plurality of memory blocks, the sector driver circuit being configured to provide a
source line voltage to the common source line and provide a plurality of drive signals to the plurality of memory blocks for
a memory operation; and

a control signal generator configured to provide one or more control signals to the sector driver circuit;
wherein the sector driver circuit is configured to provide the source line voltage and the plurality of drive signals based
at least in part on the one or more control signals; and

wherein the sector driver circuit includes:
a latch circuit shared by the plurality of memory blocks and configured to provide one or more regulation signals based at
least in part on the one or more control signals; and

a source line circuit shared by the plurality of memory blocks and configured to provide the source line voltage based at
least in part on the one or more regulation signals.

US Pat. No. 9,275,910

SEMICONDUCTOR-ON-INSULATOR STRUCTURE AND METHOD OF FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a layer of semiconductor material, the method comprising:
providing a substrate including one or more devices or features formed therein;
bonding a seed layer to the substrate, the seed layer including a crystalline semiconductor structure;
amorphizing a portion of the seed layer that is adjacent to an interface between the seed layer and the substrate;
performing dopant implantation to form an N-type conductivity region or a P-type conductivity region in the seed layer; and
after the dopant implantation, performing a solid-phase epitaxial (SPE) growth process to crystallize the seed layer by using
the crystalline semiconductor structure.

US Pat. No. 9,135,971

BOOSTED READ WRITE WORD LINE

Taiwan Semiconductor Manu...

1. A boosted control block comprising:
a first logic gate configured to generate a first word line signal, the first word line signal configured to operate a header
of a two port synchronous random access memory (SRAM) bit cell array to apply, via a second boosted word line signal, a first
stage voltage level during a first stage of at least one of a read or a write;

a capacitor coupled to the first logic gate and configured to apply a voltage to the second boosted word line signal during
a second stage of the at least one of a read or a write, the voltage increasing the second boosted word line signal to a second
stage voltage level; and

a delay module configured to control a boosted timing delay between the first stage and the second stage, the second boosted
word line signal configured to operate a read write word line (RWWL) driver of the two port SRAM bit cell array.

US Pat. No. 9,478,443

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor package, comprising:
a chip having a plurality of joint pads;
a pillar formed on the chip, the pillar having a thickness that is greater than that of the joint pads;
a component having a plurality of metal caps in physical contact with the joint pads of the chip; and
a redistribution layer formed in an insulator layer and including a conductive material that is electrically connected to
the chip through the pillar, wherein a distance between the insulator layer and the chip is equal to the thickness of the
pillar.

US Pat. No. 9,349,719

SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a first conductive portion on a first side of a shallow trench isolation (STI) region, the first conductive portion formed
within a well having a first conductivity type, the first conductive portion having a second conductivity type and connected
to a first nanowire and at least one of an input output (I/O) port, a first voltage supply (VDD), or a second voltage supply
(VSS); and

a second conductive portion on a second side of the STI region, the second conductive portion formed within the well and having
the second conductivity type, the second conductive portion connected to a second nanowire and at least one of:

the VSS or the VDD when the first conductive portion is connected to the I/O port;
the VSS when the first conductive portion is connected to the VDD; or
the VDD when the first conductive portion is connected to the VSS.

US Pat. No. 9,111,765

INTEGRATED CIRCUIT (IC) STRUCTURE

Taiwan Semiconductor Manu...

1. An integrated circuit (IC), comprising:
a junction gate field effect transistor (JFET) comprising:
one or more JFET gates;
a JFET source; and
a JFET drain;
a first-type well region; and
a lateral vertical bipolar junction transistor (LVBJT) comprising:
one or more LVBJT gates, at least one of the LVBJT gates connected to at least one of a gate control circuit or at least one
of the JFET gates;

a LVBJT base;
a LVBJT emitter;
a LVBJT collector, the LVBJT collector connected to at least one of a common node control circuit or the JFET source;
a second first-type well region abutting the LVBJT base, the LVBJT emitter, and the LVBJT collector;
a second-type well region abutting the first-type well region and the second first-type well region, the second-type well
region doped with a different dopant than the first-type well region and the second first-type well region; and

a second-type deep well region abutting the second first-type well region and the second-type well region.

US Pat. No. 9,812,416

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor arrangement, comprising:
depositing a metal over an initial dielectric layer to form a metal trace;
depositing a first dielectric material over the metal trace to form a first dielectric layer;
etching the first dielectric layer to form a first opening within which a first via is formed, wherein the first via is coupled
to the metal trace;

depositing a second dielectric material over the first via and the first dielectric layer to form a second dielectric layer;
etching the second dielectric layer to form a second opening within which a second via is formed, wherein the second via is
coupled to the first via;

etching the first dielectric layer and the second dielectric layer to form a third opening;
depositing upper test metal material to form an upper test metal layer overlying the first dielectric layer and the second
dielectric layer; and

plating the third opening to form a test pad metal layer lining the third opening and extending from the upper test metal
layer through the first dielectric layer and the second dielectric layer, wherein the metal trace is in contact with a sidewall
of the test pad metal layer.

US Pat. No. 9,520,327

METHODS OF FORMING LOW RESISTANCE CONTACTS

Taiwan Semiconductor Manu...

1. A method for forming electrical contacts, the method comprising:
forming first and second field effect transistors (FETs) over a semiconductor substrate;
forming a dielectric layer over the semiconductor substrate;
etching openings in the dielectric layer that extend to i) source and drain regions of the first FET, and ii) source and drain
regions of the second FET;

forming a hard mask over the source and drain regions of the first and second FETs;
removing a first portion of the hard mask, wherein the first portion is formed over the source and drain regions of the first
FET;

forming first silicide layers over the source and drain regions of the first FET by depositing a first metal layer over the
source and drain regions of the first FET, and annealing the first metal layer to cause the first metal layer to react and
form the first silicide layers;

removing a second portion of the hard mask, wherein the second portion is formed over the source and drain regions of the
second FET;

forming second silicide layers over the source and drain regions of the second FET, wherein the second silicide layers are
formed by depositing a second metal layer over the source and drain regions of the second FET, and annealing the second metal
layer to cause the second metal layer to react and form the second silicide layers; and

depositing a third metal layer within the openings to fill the openings.

US Pat. No. 9,390,985

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor arrangement comprising:
determining a first photoresist height of a first area of a first photoresist adjacent a first dummy gate after a first photoresist
etch;

determining a second photoresist height of a second area of the first photoresist after the first photoresist etch;
responsive to a first difference between the first photoresist height and the second photoresist height being less than a
first threshold difference, performing a hard mask etch, where the hard mask etch removes a first hard mask of the first dummy
gate, a portion of a first sidewall spacer above the first photoresist and a portion of a second sidewall spacer above the
first photoresist, where a first spacer height of the first sidewall spacer is correlated to a mean of the first photoresist
height and the second photoresist height and a second spacer height of the second sidewall spacer is correlated to the mean
of the first photoresist height and the second photoresist height;

removing a first dummy material of the first dummy gate from between the first sidewall spacer and the second sidewall spacer;
and

forming a first gate by forming a first gate electrode between the first sidewall spacer and the second sidewall spacer, where
a first gate height of the first gate is correlated to at least one of the first spacer height or the second spacer height.

US Pat. No. 9,379,069

SEMICONDUCTOR ARRANGEMENT COMPRISING TRANSMISSION LINE SURROUNDED BY MAGNETIC LAYER

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first transmission line having a first thickness and a first width, wherein:
the first thickness is different than the first width,
the first thickness is measured between a bottom wall of the first transmission line and a top wall of the first transmission
line, and

the first width is measured between a first sidewall of the first transmission line and a second sidewall of the first transmission
line;

a first dielectric layer surrounding the first transmission line and in contact with the top wall, the bottom wall, the first
sidewall and the second sidewall of the first transmission line;

a magnetic layer surrounding the first dielectric layer; and
a second dielectric layer surrounding the magnetic layer and in contact with a top wall of the magnetic layer.

US Pat. No. 9,330,967

METHOD OF FABRICATING A SEMICONDUCTOR DEVICE WITH REDUCED LEAK PATHS

Taiwan Semiconductor Manu...

8. A semiconductor device comprising:
a first conductive material;
a transistor including a second conductive material;
a first conductive item disposed between the first and second conductive materials, having opposite first and second ends,
and including a material the same as the second conductive material;

a first non-conductive oxide surface layer interconnecting the first end of the first conductive item and the first conductive
material; and

a spacer surrounding the second conductive material, wherein the second end of the first conductive item extends through the
spacer and is connected to the second conductive material.

US Pat. No. 9,299,768

SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a channel having a first linear surface, a second linear surface, a first non-linear surface, and a second non-linear surface,
the first non-linear surface comprising:

a first surface portion defining a first external angle of about 80 degrees to about 100 degrees;
a second surface portion defining a second external angle of about 80 degrees to about 100 degrees; and
a third surface portion having a linear sidewall, the third surface portion between the first surface portion and the second
surface portion;

a dielectric region abutting the first linear surface, the first non-linear surface, and the second non-linear surface; and
a gate electrode covering the dielectric region.

US Pat. No. 9,270,908

IMAGE SENSOR CONFIGURED TO REDUCE BLOOMING DURING IDLE PERIOD

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a control circuit configured to drive a pixel of the image sensor, where the pixel is associated with an integration period
and an idle period, the control circuit comprising:

a drive component configured to drive the pixel and to maintain the pixel in a reset state during at least a portion of the
idle period to mitigate a buildup of electrical charge at a photosensitive sensor of the pixel; and

a flagging component configured to identify when the pixel is in the integration period and when the pixel is in the idle
period.

US Pat. No. 9,184,269

SILICON AND SILICON GERMANIUM NANOWIRE FORMATION

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor arrangement, comprising:
forming a first silicon and silicon germanium stack over a substrate, the first silicon and silicon germanium stack comprising
a first silicon layer and a first silicon germanium layer;

forming a first source region adjacent to a first side of the first silicon and silicon germanium stack;
forming a first drain region adjacent to a second side of the first silicon and silicon germanium stack;
oxidizing the first silicon and silicon germanium stack forming a first germanium nanowire channel, the oxidizing comprising
transforming the first silicon layer and silicon of the first silicon germanium layer into a silicon oxide region, the first
germanium nanowire channel formed between the first source region and the first drain region;

removing the silicon oxide region;
forming a first gate structure around the first germanium nanowire channel forming a first nanowire transistor; and
forming a second nanowire transistor comprising a first silicon nanowire channel.

US Pat. No. 9,159,577

METHOD OF FORMING SUBSTRATE PATTERN

Taiwan Semiconductor Manu...

1. A method of forming a substrate pattern having an isolated region and a dense region, comprising:
forming a first photoresist layer over the substrate;
exposing the first photoresist layer through a first mask corresponding to the isolated region;
developing the first photoresist layer to form a first pattern;
forming a second photoresist layer over the substrate and the first pattern;
exposing the second photoresist layer through a second mask corresponding to the substrate pattern;
developing the second photoresist layer to form a second pattern; and
etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.

US Pat. No. 9,082,770

DAMASCENE GAP STRUCTURE

Taiwan Semiconductor Manu...

1. A damascene gap structure, comprising:
a first etch stop layer (ESL);
an oxide region above the first ESL;
a low-k (LK) dielectric region above the oxide region;
a second ESL above the LK dielectric region;
a first ESL seal region above the second ESL;
a second ESL seal region flush with the second ESL and below the first ESL seal region;
a gap between the first ESL and the second ESL seal region;
a first metal line on a first side of the gap, the first metal line formed under at least one of the second ESL or the second
ESL seal region, the first metal line formed through the first ESL; and

a second metal line on a second side of the gap, the second metal line formed under at least one of the second ESL or the
second ESL seal region, the second metal line formed through the first ESL.

US Pat. No. 9,519,015

RISE TIME AND FALL TIME MEASUREMENT

Taiwan Semiconductor Manu...

1. A timing measurement system for determining a transition time of a circuit, comprising:
a comparator configured to:
receive a circuit signal from a circuit;
evaluate the circuit signal based upon a first control voltage to create a first output waveform; and
evaluate the circuit signal based upon a second control voltage to create a second output waveform; and
a time converter component; and
a buffer component configured to:
receive the circuit signal from the circuit;
generate a reference waveform based upon the circuit signal; and
provide the reference waveform to the time converter component,
wherein:
the time converter component is configured to evaluate the first output waveform and the second output waveform using the
reference waveform to determine a transition time of the circuit; and

wherein an input terminal of the buffer component and an input terminal of the comparator are coupled to the circuit at a
common node.

US Pat. No. 9,490,163

TAPERED SIDEWALL CONDUCTIVE LINES AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor arrangement comprising:
forming a first dielectric layer;
forming a skeleton layer over the first dielectric layer;
etching through the skeleton layer to define a first trench and etching through a portion of the first dielectric layer exposed
through the first trench to define a first via opening;

forming a first conductive line within the first trench and a first via within the first via opening, the first conductive
line having a sidewall that is at a first angle of at least 45° and less than 90° relative to a first plane in which a bottom
surface of the first conductive line lies; and

replacing the skeleton layer, comprising:
removing the skeleton layer to expose the sidewall of the first conductive line;
forming a second dielectric layer on the exposed sidewall and surrounding the first conductive line, the second dielectric
layer extending over a top surface of the first conductive line from a first edge of the top surface of the first conductive
line to a second edge of the top surface of the first conductive line; and

forming a third dielectric layer over the second dielectric layer, a first air gap defined within the third dielectric layer,
where the first air gap is adjacent the first conductive line.

US Pat. No. 9,404,884

BIOSENSOR DEVICE AND RELATED METHOD

Taiwan Semiconductor Manu...

1. A circuit arrangement comprising:
an ion sensitive sensor;
a differentiator electrically connected to the ion sensitive sensor, wherein the differentiator comprises:
a first capacitor; and
an amplifier;
an AC signal level comparator electrically connected to the differentiator; and
a decision circuit electrically connected to the AC signal level comparator.

US Pat. No. 9,195,792

CIRCUIT DESIGN PORTING BETWEEN PROCESS DESIGN TYPES

Taiwan Semiconductor Manu...

1. A method, comprising:
partitioning a circuit design into a first topology category and a second topology category, the circuit design specified
according to a first process design type;

determining a first ordered set of parameters for the first topology category and a second ordered set of parameters for the
second topology category;

simulating circuit topology behavior of the first topology category to identify first performance characteristics for the
first ordered set of parameters;

normalizing the first ordered set of parameters based upon the first performance characteristics, a normalized parameter corresponding
to a new parameter value of a second process design type satisfying an older parameter value of the first process design type;
and

resizing one or more components within the circuit design based upon the first ordered set of parameters and the second ordered
set of parameters to generate a ported circuit design specified according to the second process design type for the circuit
design, the method implemented at least in part via a processing unit.

US Pat. No. 9,129,082

VARIATION FACTOR ASSIGNMENT

Taiwan Semiconductor Manu...

1. A method for variation factor assignment, comprising:
determining a first peripheral environment for a first device within a die, the first peripheral environment corresponding
to a neighborhood around the first device and comprising at least one of a first layout structure or a first instance; and

assigning a first variation factor to the first device, the first variation factor indicative of an expected variance in at
least one electrical characteristic of the first device and determined based on the first peripheral environment, the assigning
comprising at least one of:

determining the first variation factor based on a first architecture associated with the first layout structure within the
first peripheral environment; or

determining the first variation factor based on a first bounding window associated with the first instance within the first
peripheral environment, at least one of the determining or the assigning implemented by a processing unit.

US Pat. No. 9,502,886

MIM CAPACITOR

Taiwan Semiconductor Manu...

1. A method for managing one or more capacitors, comprising:
determining that a first capacitor in a set of one or more capacitors has a defect when a first signal at a node to which
the first capacitor is coupled has a first logic state; and

responsive to the determination:
disabling the first capacitor; and
applying the first signal having the first logic state to a first logic gate to toggle a first gate signal that is output
by the first logic gate from a first non-enabling logic state to a first enabling logic state, wherein the first enabling
logic state turns on a first transistor to enable a second capacitor.

US Pat. No. 9,502,647

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) WITH A LOW-K POROUS LAYER

Taiwan Semiconductor Manu...

1. A method of fabricating a resistive memory, comprising: forming a first conductive film as a first electrode; forming a
group-IV element, a dielectric material, and a porous low-k layer together using sputtering to form a resistance-switching
network on the first electrode, wherein forming the group-IV element, the dielectric material, and the porous low-k layer
together using sputtering comprises forming the porous low-k layer using inductively coupled plasma (ICP) treatment, and forming
the group-IV element by co-depositing on the porous low-k layer the dielectric material and the group-IV element using sputtering
so that the dielectric material is doped with the group-IV element; and forming a second conductive film as a second electrode
on the resistance-switching network using sputtering.

US Pat. No. 9,460,956

METHOD OF FORMING SHALLOW TRENCH ISOLATION AND SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of forming a shallow trench isolation between a first vertical structure and a second vertical structure in a
substrate, comprising:
providing the substrate;
providing the first vertical structure and the second vertical structure over the substrate;
conformally forming a dielectric layer over the substrate, the first vertical structure, and the second vertical structure;
etching the dielectric layer to expose a portion of the substrate corresponding to the shallow trench isolation;
etching the exposed portion of the substrate to form a recess corresponding to the shallow trench isolation;
removing the dielectric layer; and
forming an oxide layer in the recess as the shallow trench isolation by:
forming the oxide layer over the substrate, the first vertical structure, and the second vertical structure using flowable
CVD;

performing CMP on the oxide layer and stopping on the first vertical structure and the second vertical structure, and
etching the oxide layer to expose the substrate and to form the shallow trench isolation.

US Pat. No. 9,373,623

MULTI-LAYER SEMICONDUCTOR STRUCTURES FOR FABRICATING INVERTER CHAINS

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a first device layer formed on a substrate and including one or more first inverter structures;
a second device layer formed on the first device layer and including one or more second inverter structures; and
one or more inter-layer connection structures configured to electrically connect to the first inverter structures and the
second inverter structures,

wherein the one or more first inverter structures include a first input terminal and a first output terminal, the one or more
second inverter structures include a second input terminal and a second output terminal, and the inter-layer connection structures
are configured to connect the first input terminal with the second output terminal and connect the first output terminal with
the second input terminal.

US Pat. No. 9,059,092

CHEMICAL DIELECTRIC FORMATION FOR SEMICONDUCTOR DEVICE FABRICATION

Taiwan Semiconductor Manu...

1. A method for fabricating semiconductor devices, the method comprising:
providing a substrate including a first region and a second region;
forming a first polymer layer on the first region and the second region;
forming a second polymer layer on the first polymer layer;
removing the second polymer layer on the first region;
applying an oxygen-based plasma to remove the first polymer layer on the first region;
applying an oxidizing solution to generate a first dielectric layer on the first region and to remove the second polymer layer
and the first polymer layer on the second region; and

forming a first conductive layer on the first dielectric layer for fabricating one or more first devices.

US Pat. No. 9,520,296

SEMICONDUCTOR DEVICE HAVING A LOW DIVOT OF ALIGNMENT BETWEEN A SUBSTRATE AND AN ISOLATION THEREOF AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming vertical structures, comprising:
providing a substrate;
forming a first oxide layer over the substrate;
forming a shallow trench isolation to divide the substrate into a first region and a second region;
forming a first dummy layer over the first oxide layer and the shallow trench isolation;
etching the first oxide layer and the first dummy layer to form a first recess in the first region and a second recess in
the second region;

forming a second dummy layer in the first recess and the second recess;
removing the first dummy layer;
removing the first oxide layer;
etching a portion of the shallow trench isolation; and
etching the substrate to make the substrate aligned with a top of the shallow trench isolation and to form a first vertical
structure in the first region and a second vertical structure in the second region.

US Pat. No. 9,502,315

ELECTRICAL COMPONENT TESTING IN STACKED SEMICONDUCTOR ARRANGEMENT

Taiwan Semiconductor Manu...

1. A stacked semiconductor arrangement, comprising:
a dynamic pattern generator layer comprising an electrical component operatively coupled to a pad configured to:
refract an electron beam based upon the pad being placed into a first voltage state by the electrical component; and
not refract the electron beam based upon the pad being placed into a second voltage state, different than the first voltage
state, by the electrical component; and

a monitoring layer comprising a monitoring component configured to evaluate electrical performance of the electrical component.

US Pat. No. 9,395,326

FET SENSING CELL AND METHOD OF IMPROVING SENSITIVITY OF THE SAME

Taiwan Semiconductor Manu...

1. A device, comprising:
a first dielectric layer over a substrate;
an active layer over the first dielectric layer;
a source region in the active layer;
a drain region in the active layer;
a channel region in the active layer situated between the source region and the drain region;
a sensing film over the channel region;
a second dielectric layer over the active layer;
an electrode located within the second dielectric layer; and
a fluidic gate region located over the second dielectric layer and the sensing film, wherein the fluidic gate region is a
cavity, the electrode defines a portion of a sidewall of the cavity, and the sensing film defines a portion of a bottom of
the cavity.

US Pat. No. 9,385,735

ANALOG-TO-DIGITAL CONVERTER FOR IMAGE PIXELS

Taiwan Semiconductor Manu...

1. A method for analog-to-digital conversion, comprising:
applying a first portion of a ramp voltage waveform to a comparator;
making a first determination regarding an output of the comparator responsive to the applying a first portion of a ramp voltage
waveform;

when, based upon the first determination, the output corresponds to a first output:
applying a second portion of the ramp voltage waveform to the comparator; and
when, based upon the first determination, the output corresponds to a second output different than the first output:
adjusting a voltage of a direct current (DC) voltage waveform applied to the comparator.

US Pat. No. 9,460,949

ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM

Taiwan Semiconductor Manu...

1. An apparatus comprising:
a pod, comprising:
a storage chamber comprising a set of walls defining an interior region in which wafers are held, wherein a first wall of
the set of walls defines a first opening;

a receptacle disposed within the interior region and defining a second opening overlying the first opening; and
a constraining ring disposed within the interior region and surrounding a portion of the receptacle defining the second opening
and applying pressure on the receptacle to seal the second opening; and

a pipeline comprising:
a pipe;
a diffuser attached to a first end of the pipe and dimensioned for insertion into the storage chamber through the first opening
and the second opening; and

a controller attached to a second end of the pipe.

US Pat. No. 9,425,228

IMAGE SENSOR WITH REDUCED OPTICAL PATH

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array overlapping a substrate;
a first oxide layer overlapping the photodiode array;
a metal grid comprising a first metal grid structure and a second metal grid structure in contact with a top surface of the
first oxide layer;

an oxide grid comprising a first oxide grid structure in contact with a top surface of the first metal grid structure and
a second oxide grid structure in contact with a top surface of the second metal grid structure;

a filler grid comprising a first filler grid structure overlapping the first oxide layer and between the first metal grid
structure and the second metal grid structure; and

a capping layer in contact with the top surface of the first oxide layer, wherein there is no metal between a top surface
of the first oxide grid structure and a lens structure overlapping the first oxide grid structure.

US Pat. No. 9,211,568

CLEAN FUNCTION FOR SEMICONDUCTOR WAFER SCRUBBER

Taiwan Semiconductor Manu...

1. A system for cleaning a scrub brush of a scrubber utilized in semiconductor fabrication, comprising:
a brush pot into which a scrub brush of a scrubber is deposited comprising:
an inlet connected to a source of a base pH material for modifying a charge of a particle on the scrub brush to a modified
charge corresponding to a scrub brush charge of the scrub brush; and

a rotatable cleaning bar configured to contact the scrub brush and rotate relative to the scrub brush to detach the particle
from the scrub brush.

US Pat. No. 9,202,788

MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device structure, the method comprising:
fabricating a first transistor layer on a substrate, the fabricating of the first transistor layer including:
patterning the substrate to define a first active region, the first active region including a first alignment structure,
doping the first active region to define a conductivity type of the first transistor layer, and
forming a first gate region that is coupled to the first active region, the first gate region including a second alignment
structure;

providing a bounding layer over the first transistor layer;
patterning the bounding layer to include an opening over the first alignment structure and the second alignment structure;
filling the opening of the bounding layer with a transparent or semi-transparent material; and
fabricating a second transistor layer over the bounding layer, the fabricating of the second transistor layer including:
patterning the second transistor layer to define a second active region, wherein patterning the second active region includes
aligning a mask layer relative to the first and the second alignment structures, and wherein the first and the second alignment
structures are detectable via the opening during the patterning of the second transistor layer, and

forming a second gate region that is coupled to the second active region.

US Pat. No. 9,166,001

VERTICAL STRUCTURE AND METHOD OF FORMING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, comprising:
providing a vertical structure over a substrate;
forming an etch stop layer over the vertical structure;
forming an oxide layer over the etch stop layer;
performing chemical mechanical polishing on the oxide layer and stopping on the etch stop layer;
etching back the oxide layer and the etch stop layer to expose a sidewall of the vertical structure and to form an isolation
layer; and

oxidizing the sidewall of the vertical structure and doping oxygen into the isolation layer by using a cluster oxygen doping
treatment.

US Pat. No. 9,147,694

DENSITY GRADIENT CELL ARRAY

Taiwan Semiconductor Manu...

1. A method for forming an array of dummy cells for mitigating density gradients between an active region comprising a plurality
of active cells and a dummy region adjacent the active region and comprising a plurality of dummy cells, the method comprising:
laying out the array of dummy cells, the array of dummy cells comprising:
a plurality of empty cell spaces; and
a first set of dummy cells, comprising:
a first set of gates having a first gate dimension; and
a first set of oxide defined (OD) regions having a first OD dimension;
inserting at least one of:
a first subset of gates having the first gate dimension into at least some of the plurality of empty cell spaces; or
a first subset of OD regions having the first OD dimension into at least some of the plurality of empty cell spaces; and
inserting at least one of:
a second set of gates having a second gate dimension into at least some remaining empty cell spaces of the plurality of empty
cell spaces; or

a second set of OD regions having a second OD dimension into at least some remaining empty cell spaces of the plurality of
empty cell spaces.

US Pat. No. 9,136,332

METHOD FOR FORMING A NANOWIRE FIELD EFFECT TRANSISTOR DEVICE HAVING A REPLACEMENT GATE

Taiwan Semiconductor Manu...

1. A method for forming a nanowire field effect transistor (FET) device, the method comprising:
growing a sacrificial layer, a nanowire, and a buffer layer in a fin structure over a semiconductor substrate using an epitaxial
process, wherein the buffer layer interposes between the semiconductor substrate and the sacrificial layer;

forming a dummy gate around at least a portion of the nanowire, wherein the portion of the nanowire comprises a channel region
of a lateral nanowire FET, the channel region connecting source and drain regions of the FET; and

replacing the dummy gate with a replacement gate, wherein the replacing includes:
removing the dummy gate to expose the portion and the sacrificial layer thereunder,
etching the sacrificial layer after the removal of the dummy gate, the etching being selective to the sacrificial layer to
prevent the removal of the nanowire, and the etching causing the portion of the nanowire to be suspended over the semiconductor
substrate, and

forming the replacement gate that surrounds at least the portion of the nanowire, wherein the replacement gate is deposited
over all sides of the portion, such that the portion is no longer suspended over the semiconductor substrate.

US Pat. No. 9,331,173

SEMICONDUCTOR DEVICE HAVING A CARBON CONTAINING INSULATION LAYER FORMED UNDER THE SOURCE/DRAIN

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor arrangement comprising:
forming a first opening over a first active region, a shallow trench isolation (STI) region and a second active region, such
that the first opening exposes a portion of the first active region and the second active region;

forming a metal connect in the first opening, such that the metal connect is connected to the first active region and the
second active region and the metal connect has an initial height; and

recessing the initial height of the metal connect in the STI region to form a recessed portion of the metal connect having
a second height, such that the second height is less than a first height of a first unrecessed portion of the metal connect
over the first active region and a third height of a second unrecessed portion of the metal connect over the second active
region, the first height substantially equal to the third height.

US Pat. No. 9,165,623

MEMORY ARRANGEMENT

Taiwan Semiconductor Manu...

1. A memory arrangement, comprising:
a first single-port memory cell configured to store content; and
a first word-line driver operably coupled to a first decoder and a second decoder, the first word-line driver configured to
control activation of the first single-port memory cell as a function of a first voltage signal applied to the first word-line
driver via the first decoder and a second voltage signal applied to the first word-line driver via the second decoder, a first
element of the first word-line driver situated on a first physical layer of the memory arrangement and a second element of
the first word-line driver situated on a second physical layer of the memory arrangement.