US Pat. No. 9,318,528

IMAGE SENSOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:
forming a pixel within an image sensor;
bonding the image sensor to a semiconductor device, the semiconductor device comprising a substrate and a heat sink at least
partially located in a first metallization layer between the pixel and the substrate; and

forming a thermal via extending through the image sensor and in thermal connection with the heat sink.

US Pat. No. 9,331,277

ONE TRANSISTOR AND ONE RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH SPACER

Taiwan Semiconductor Manu...

1. A resistive random access memory (RRAM) cell, comprising:
a transistor;
an RRAM structure electrically coupled to the transistor, the RRAM structure having
a bottom electrode having a via portion and a top portion, wherein said via portion of the bottom electrode is embedded in
a first RRAM stop layer;

a resistive material layer on the bottom electrode having a width that is substantially the same as a width of the top portion
of the bottom electrode;

a capping layer on and physically contacting the resistive material layer having a smaller width than the resistive material
layer;

a spacer surrounding the capping layer;
a top electrode on the resistive material layer having a width that is same as the capping layer and a thickness larger than
the capping layer;

a second RRAM stop layer having a first portion disposed over the first RRAM stop layer, the second RRAM stop layer having
a second portion laterally surrounding the top electrode, the spacer, the resistive material layer, and the bottom electrode;
and

a dielectric layer over the first portion of the second RRAM stop layer and laterally surrounding the second portion of the
second RRAM stop layer, the dielectric layer and the second RRAM stop layer differing in composition; and

a conductive material connecting the top electrode of the RRAM structure to a metal layer.

US Pat. No. 9,589,857

INTERPOSER TEST STRUCTURES AND METHODS

Taiwan Semiconductor Manu...

1. A structure comprising:
an interposer having a test structure extending along a periphery of the interposer, at least a portion of the test structure
being in a first redistribution element, the first redistribution element being on a first surface of a substrate of the interposer,
the test structure being intermediate and electrically coupled to at least two probe pads.

US Pat. No. 9,396,953

CONFORMITY CONTROL FOR METAL GATE STACK

Taiwan Semiconductor Manu...

1. A method comprising:
forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer;
removing the dummy gate stack to form a recess;
forming a gate dielectric layer in the recess;
forming a metal layer in the recess, wherein the metal layer is over the gate dielectric layer, and wherein the forming the
metal layer comprises:

placing the wafer against a target;
applying a DC power to the target, wherein a negative end of the DC power is connected to the target, and a positive end of
the DC power is connected to a pedestal underlying the wafer; and

applying an RF power to the target, wherein the DC power and the RF power are applied simultaneously; and
filling a remaining portion of the recess with metallic materials, wherein the metallic materials overlie the metal layer.

US Pat. No. 9,230,795

DIRECTIONAL PRE-CLEAN IN SILICIDE AND CONTACT FORMATION

Taiwan Semiconductor Manu...

9. A method comprising:
etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening;
reacting a surface region of the underlying region with a process gas to form a reaction layer, wherein the reaction layer
comprises a first portion at a bottom of the opening and overlying the underlying region, and a second portion on a top surface
of the dielectric layer, with substantially no reaction layer formed on sidewalls of the opening; and

performing an anneal to remove the reaction layer.

US Pat. No. 9,466,488

METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER

Taiwan Semiconductor Manu...

1. A method of forming a device, comprising:
forming an insulating layer on a top surface of a semiconductor substrate, a target region disposed at the top surface of
the semiconductor substrate;

etching an opening through the insulating layer, the opening exposing a top surface of a portion of the target region, the
etching comprising generating an etching byproduct disposed on surfaces of the opening;

without removing the etching byproduct, forming a doped metal oxide interlayer in the opening and contacting the top surface
of the target region; and

filling a remainder of the opening with a metal plug, the doped metal oxide interlayer disposed between the metal plug and
the substrate.

US Pat. No. 9,373,603

REFLOW PROCESS AND TOOL

Taiwan Semiconductor Manu...

1. A method comprising:
moving a package workpiece into a chamber of a reflow tool, an exhaust system set at a first pressure removing gas from the
chamber during the moving the package workpiece into the chamber;

enclosing the package workpiece in an enclosed environment of the chamber;
causing an oxygen content of the enclosed environment of the chamber to be less than 40 parts per million (ppm), the causing
the oxygen content to be less than 40 ppm comprising setting the exhaust system at a second pressure less than the first pressure;
and

performing a reflow process in the enclosed environment of the chamber while the oxygen content is less than 40 ppm, the reflow
process reflowing a reflowable material of the package workpiece.

US Pat. No. 9,129,918

SYSTEMS AND METHODS FOR ANNEALING SEMICONDUCTOR STRUCTURES

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor structure, the method comprising:
providing a semiconductor structure;
providing an energy-converting material capable of increasing the semiconductor structure's absorption of microwave radiation;
providing a heat reflector between the energy-converting material and the semiconductor structure, the heat reflector being
capable of reflecting thermal radiation from the semiconductor structure; and

applying microwave radiation to the energy-converting material and the semiconductor structure to anneal the semiconductor
structure for fabricating semiconductor devices.

US Pat. No. 9,461,170

FINFET WITH ESD PROTECTION

TAIWAN SEMICONDUCTOR MANU...

1. A field effect transistor (FET) structure, comprising:
a substrate;
a fin structure formed over the substrate, wherein the fin structure comprises:
a first channel region;
a first source or drain region and a second source or drain region formed on and abutting opposite ends of the first channel
region, respectively; and

a well region formed of the same conductivity type as the second source or drain region, connected to the second source or
drain region, and extended to the substrate; and

a first gate structure wrapping around the first channel region in the fin structure;
wherein the first source or drain region and the second source or drain region are more heavily doped than the well region.

US Pat. No. 9,462,692

TEST STRUCTURE AND METHOD OF TESTING ELECTRICAL CHARACTERISTICS OF THROUGH VIAS

Taiwan Semiconductor Manu...

1. An apparatus comprising:
a substrate having a first side and a second side;
a first plurality of electrical connections on the first side of the substrate;
a second plurality of electrical connections on the second side of the substrate; and
a plurality of through vias (TVs), each of the plurality of TVs electrically coupling respective ones of the first plurality
of electrical connections and the second plurality of electrical connections; and

a conductive layer over the second plurality of electrical connections, the conductive layer directly electrically coupling
a first electrical connection of the second plurality of electrical connections to one or more other electrical connections
of the second plurality of electrical connections to electrically couple respective ones of the plurality of TVs to each other.

US Pat. No. 9,397,129

DIELECTRIC FILM FOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array comprising one or more photodiodes configured to detect light;
a calibration region configured to define a color level for image reproduction, the calibration region formed laterally spaced
apart from the photodiode array;

a dielectric layer formed over and in direct contact with the photodiode array; and
a dielectric film formed over the photodiode array and the calibration region and in contact with the dielectric layer, the
dielectric film having a substantially planar bottom surface extending over the photodiode array and the calibration region.

US Pat. No. 9,343,556

METHODS AND APPARATUS FOR ESD PROTECTION CIRCUITS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substrate;
an n type buried layer (NBL) on the substrate;
a first region on the NBL comprising a first n type material;
a second region on the NBL comprising a first p type material and adjacent to and not overlapping with the first region;
a third region on the NBL comprising a second n type material and adjacent to and not overlapping with the second region;
a fourth region comprising a second p type material formed within the first region;
a fifth region comprising a third n type material formed within the second region, and separated from the fourth region by
a first isolation area; and

a sixth region comprising a third p type material formed within the third region, and separated from the fifth region by a
second isolation area.

US Pat. No. 9,293,437

FUNCTIONAL BLOCK STACKED 3DIC AND METHOD OF MAKING SAME

Taiwan Semiconductor Manu...

1. A device package comprising:
a fan-out redistribution layer (RDL);
a device bonded to the fan-out RDL, the device comprising:
a first functional tier comprising:
a first substrate;
first active devices on the first substrate; and
a first metallization layer electrically connecting the first active devices;
a second functional tier bonded to the first function tier, wherein the second functional tier comprises:
a second substrate;
second active devices on the second substrate; and
a second metallization layer electrically connecting the second active devices; and
an interconnect structure electrically connecting the first metallization layer to the second metallization layer, wherein
the interconnect structure comprises an inter-tier via (ITV) at least partially disposed in both the first functional tier
and the second functional tier, and wherein the ITV contacts the first metallization layer; and

a molding compound over the fan-out RDL and extending along sidewalls of the device.

US Pat. No. 9,395,739

COMMON WELL BIAS DESIGN FOR A DRIVING CIRCUIT AND METHOD OF USING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A driving circuit comprising:
a common well;
a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured
to receive a first signal, and having a second terminal connected to the common well; and

a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured
to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well.

US Pat. No. 9,490,176

METHOD AND STRUCTURE FOR FINFET ISOLATION

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, comprising:
receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and
first dielectric features over the substrate and between the dummy gate stacks;

removing the dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose
first and second portions of the active fin respectively;

removing the first portion of the active fin; and
forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin.

US Pat. No. 9,293,992

VOLTAGE REGULATOR

TAIWAN SEMICONDUCTOR MANU...

1. A voltage regulator circuit comprising:
an amplifier having an inverting input and a non-inverting input, the amplifier being configured to generate a control signal
based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the
amplifier;

an output node;
a first power node;
a second power node;
a driver configured to generate a driving current flowing toward the output node in response to the control signal, the driver
being coupled between the first power node and the output node;

a first transistor having a gate, the first transistor being coupled between the output node and the second power node; and
a bias circuit outside the amplifier configured to supply a bias signal to the gate of the first transistor, the first transistor
being configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

US Pat. No. 9,379,076

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:
receiving a substrate including a die pad disposed thereon;
disposing a passivation over the substrate and around the die pad;
disposing a polymer over the passivation;
forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad;
depositing a metallic paste on the elongated portion of the PPI by a stencil including an aperture corresponding to a predetermined
position of the elongated portion of the PPI;

disposing a conductive bump over the metallic paste; and
disposing a molding over the PPI and around the metallic paste and the conductive bump.

US Pat. No. 9,497,861

METHODS AND APPARATUS FOR PACKAGE WITH INTERPOSERS

Taiwan Semiconductor Manu...

1. A device, comprising:
a substrate;
a metal layer above the substrate;
a first contact pad and a second contact pad above the metal layer; and
a first dam above the metal layer, the first dam comprising a first layer of conductive material and a second layer of non-conductive
material above the first layer of conductive material, wherein the first dam surrounds an area, the first contact pad being
within the area, and the second contact pad being outside the area.

US Pat. No. 9,330,947

METHODS FOR FORMING PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS

Taiwan Semiconductor Manu...

1. A method comprising:
placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier;
forming a plurality of through-assembly vias (TAVs) over the release layer;
forming a dam member between the device die and the plurality of TAVs;
molding the device die, the dam member, and the plurality of TAVs in a molding compound; and
grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a
top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and the exposed
ends of the plurality of TAVs.

US Pat. No. 9,632,426

IN-SITU IMMERSION HOOD CLEANING

Taiwan Semiconductor Manu...

15. An apparatus comprising:
a wafer stage configured to secure a wafer;
a cleaning module positioned outside a region occupied by a wafer when a wafer is secured by the wafer stage, wherein the
cleaning module comprises a water reservoir adjacent the wafer stage, the water reservoir configured to hold water having
a top surface of the water being level with a top surface of the wafer when a wafer is secured on a surface of the wafer stage,
wherein the water reservoir extends over a topmost surface of the wafer stage, the water reservoir comprising:

a first exterior wall, a second exterior wall, and an interior wall, the interior wall disposed between the first exterior
wall and the second exterior wall;

a first partition and a second partition, the first partition disposed between the first exterior wall and the interior wall,
the second partition disposed between the interior wall and the second exterior wall;

a first upper extent of the first exterior wall and a second upper extent of the second exterior wall and a third upper extent
of the interior wall above the surface of the wafer stage;

a first lower extent of the first exterior wall and a second lower extent of the second exterior wall and a third lower extent
of the interior wall below the surface of the wafer stage;

the first lower extent, the second lower extent, the third lower extent, a fourth lower extent of the first partition, and
a fifth lower extent of the second partition are coincident with a bottom of the water reservoir; and

a fourth upper extent of the first partition and a fifth upper extent of the second partition are above the bottom of the
water reservoir; and

wherein the cleaning module comprises:
a first portion of the water reservoir defined by the first exterior wall and the interior wall;
a second portion of the water reservoir defined by the interior wall and the second exterior wall;
a first inlet disposed in the first portion of the water reservoir, the first inlet configured to provide water into the first
portion of the water reservoir;

a first outlet disposed in the first portion of the water reservoir at the bottom of the water reservoir, the first outlet
configured to extract water from the second portion of the water reservoir;

a second inlet disposed in the second portion of the water reservoir, the second inlet configured to provide water into the
second portion of the water reservoir; and

a second outlet disposed in the second portion of the water reservoir at the bottom of the water reservoir, the second outlet
configured to extract water from the second portion of the water reservoir.

US Pat. No. 9,240,401

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substrate;
a first region over the substrate, the first region comprising a first n type material;
a second region laterally adjacent to the first region, the second region comprising a first p type material;
a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region,
the third region comprising a second n type material;

a fourth region disposed within a portion of the first region proximate the second region, the fourth region comprising a
second p type material;

a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the
fifth region are separated by a first isolation area;

a sixth region disposed within a portion of the third region proximate the second region, the sixth region comprising a third
p type material; and

a seventh region disposed within the second region and below the fifth region.

US Pat. No. 9,054,004

PIXEL ISOLATION STRUCTURES IN BACKSIDE ILLUMINATED IMAGE SENSORS

Taiwan Semiconductor Manu...

1. A backside illuminated image sensor including an array of pixels, comprising:
a first pixel disposed in a front side of a substrate and configured to generate charged carriers in response to light incident
upon a backside of the substrate;

a second pixel disposed in the front side of the substrate and configured to generate charged carriers in response to light
incident upon the backside of the substrate; and
an anti-reflective layer on the backside of the substrate; and
a first isolation structure disposed to separate the second pixel from the first pixel, the first isolation structure extending
from the backside of the substrate toward the front side of the substrate, wherein the first isolation structure includes
a first sidewall substantially vertically to the front side of the substrate,

wherein the first isolation structure separates a region of the anti-reflective layer corresponding to the first pixel and
another region of the anti-reflective layer corresponding to the second pixel.

US Pat. No. 9,312,229

HYBRID BONDING WITH AIR-GAP STRUCTURE

Taiwan Semiconductor Manu...

1. A package comprising:
a first package component comprising:
a first surface dielectric layer comprising a first planar surface; and
a first metal pad in the first surface dielectric layer, wherein the first metal pad comprises:
a first diffusion barrier layer comprising sidewall portions;
a first metallic material encircled by the sidewall portions of the first diffusion barrier layer, wherein the first metallic
material comprises a second planar surface level with the first planar surface; and

an air gap extending from the second planar surface of the first metallic material into the first metallic material; and
a second package component overlapping the first package component, wherein the second package component comprises:
a second surface dielectric layer comprising a third planar surface bonded to the first planar surface; and
a second metal pad in the second surface dielectric layer, wherein the second metal pad has a fourth planar surface bonded
to the second planar surface, and the air gap is overlapped by the second metal pad.

US Pat. No. 9,281,221

ULTRA-HIGH VACUUM (UHV) WAFER PROCESSING

Taiwan Semiconductor Manu...

11. A vacuum system for ultra-high vacuum (UHV) wafer processing, comprising:
a remote load lock (RLL) module configured to:
receive a wafer from a load port; and
pump down the RLL module to a first pressure;
a first bridge configured to connect the RLL module to a first cluster tool, the first bridge comprising:
a second bypass module;
a first buffer module configured to at least one of:
receive the wafer from the second bypass module;
receive the wafer from the RLL module; or
pump down the first buffer module to a second pressure, the second pressure less than the first pressure; and
a first bypass module configured to receive the wafer from the first buffer module, the first bypass module connected to the
first cluster tool; and

a second bridge configured to connect the first cluster tool to a second cluster tool, the second bridge associated with the
second pressure, the second bridge comprising:

a fourth bypass module configured to receive the wafer from the first cluster tool;
a second buffer module configured to receive the wafer from the fourth bypass module; and
a third bypass module configured to receive the wafer from the second buffer module, the third bypass module connected to
the second cluster tool.

US Pat. No. 9,252,491

EMBEDDING LOW-K MATERIALS IN ANTENNAS

Taiwan Semiconductor Manu...

1. A device comprising:
a patch antenna comprising:
a feeding line;
a ground panel over the feeding line, wherein the ground panel comprises an aperture therein;
a low-k dielectric module over and aligned to the aperture; and
a patch over the low-k dielectric module.

US Pat. No. 9,147,702

IMAGE SENSOR FOR MITIGATING DARK CURRENT

Taiwan Semiconductor Manu...

16. An image sensor for mitigating dark current, comprising:
a first region comprising a first doping type;
a second region comprising a second doping type, the second doping type opposite of the first doping type, the first region
surrounded by the second region;

a third region at least one of above the first region or below the first region, the third region comprising:
a first sub-region adjacent to the second region and comprising the first doping type; and
a second sub-region adjacent to the first sub-region and comprising the first doping type; and
a first surface protect region comprising the first doping type, the first surface protect region adjacent to the second sub-region.

US Pat. No. 9,129,818

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:
a substrate;
a plurality of conductive pads formed in consecutive conductive layers, the plurality of conductive pads aligned and arranged
one above another over the substrate, wherein the plurality of conductive pads comprises a first conductive pad and a second
conductive pad, the first conductive pad is above the second conductive pad, a redistribution layer extends the second conductive
pad, and the first conductive pad is not extended by a redistribution layer;

a bump structure formed on the first conductive pad and electrically coupled to the plurality of conductive pads; and
a dielectric layer extending into a gap between peripheral parts of the first and second conductive pads,
wherein middle parts of the first and second conductive pads are in direct contact with each other, and
wherein the redistribution layer and the second conductive pad comprise different conductive materials.

US Pat. No. 9,443,806

CHIP PACKAGES AND METHODS OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A chip package, comprising:
a chip having a contact pad disposed at a first side of the chip;
a passivation layer over the first side of the chip, the passivation layer having an opening disposed over the contact pad;
a polymer layer over the passivation layer, the polymer layer having an edge disposed over the contact pad, wherein the edge
of the polymer layer is distal from a perimeter of the opening of the passivation layer;

a conductive structure formed atop the contact pad, the conductive structure filling the opening of the passivation layer
and covering the edge of the polymer layer; and

a fan-out structure disposed over the conductive structure, the fan-out structure having a first portion electrically connected
to the conductive structure and a second portion electrically connected to the first portion and extending laterally away
from the first portion and the conductive structure.

US Pat. No. 9,293,392

3DIC INTERCONNECT APPARATUS AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:
bonding a first surface of a first semiconductor chip to a surface of a second semiconductor chip;
after the bonding, forming a first opening extending from a second surface of the first semiconductor chip partially to a
conductive feature in the first semiconductor chip;

forming a liner in the first opening;
forming a second opening extending from a bottom of the first opening to a conductive feature in the second semiconductor
chip, the second opening exposing at least a portion of a sidewall and an adjoining horizontal surface of the conductive feature
of the first semiconductor chip; and

forming a conductive material in the first opening and the second opening.

US Pat. No. 9,093,299

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first active region;
a second active region;
a shallow trench isolation (STI) region between the first active region and the second active region; and
a metal connect over the first active region, the STI region and the second active region, and connected to the first active
region and the second active region, such that a first unrecessed portion of the metal connect over the first active region
has a first height, a recessed portion of the metal connect over the STI region has a second height and a second unrecessed
portion of the metal connect over the second active region has a third height, the first height and the third height greater
than the second height.

US Pat. No. 9,081,289

SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method, comprising:
providing a layout of a device having a pattern of features;
identifying a first portion of at least one feature of the plurality of features;
assigning an image criteria for the first portion;
determining a lithography optimization parameter based on the assigned image criteria for the first portion; and
imaging the first portion of the at least one feature onto a semiconductor substrate using the determined lithography optimization
parameter;

wherein the at least one feature is symmetrical as defined by a layout file, wherein the imaging provides an imaged first
feature on the semiconductor substrate, and wherein the imaged first feature is asymmetrical.

US Pat. No. 9,252,076

3D PACKAGES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a molding material having a thickness over a first substrate, the first substrate comprising a first edge region, a middle
region next to the first edge region, and a second edge region next to the middle region and opposite the first edge region;

a first opening in the molding material in the first edge region, the first opening having a first width;
a first connector in the first opening;
a second opening in the molding material in the middle region, the second opening having a second width, the second width
being greater than the first width;

a second connector in the second opening;
a third opening in the molding material in the second edge region, the third opening having a third width, the third width
being greater than the second width;

a third connector in the third opening; and
a second package bonded to the first connector, the second connector, and the third connector, a first surface of the second
package being physically separated from a first surface of the molding material by a first gap in the first edge region, a
second gap in the middle region, and a third gap in the second edge region, the first gap being greater than the second gap,
and the second gap being greater than the third gap.

US Pat. No. 9,425,250

TRANSISTOR WITH WURTZITE CHANNEL

Taiwan Semiconductor Manu...

1. A device comprising:
a source region;
a drain region;
a wurtzite semiconductor between the source region and the drain region, wherein a source-drain direction is parallel to a
[01-10] direction or a [?2110] direction of the wurtzite semiconductor;

a gate dielectric over the wurtzite semiconductor; and
a gate electrode over the gate dielectric.

US Pat. No. 9,377,401

BIOLOGICAL SENSING STRUCTURES

Taiwan Semiconductor Manu...

1. A biological sensing structure, comprising:
a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to
the top surface;

a first light reflecting layer disposed over the top surface and the sidewall surface of the mesa;
a filling material surrounding the mesa, wherein the mesa protrudes from a top surface of the filling material;
a stop layer disposed over the filling material and a portion of the first light reflecting layer;
a sacrificial layer disposed over a first portion of the stop layer and exposing a second portion of the stop layer;
a second light reflecting layer disposed over the second portion of the stop layer and a portion of the top surface of the
mesa; and

an opening disposed in the second light reflecting layer to partially expose the top surface of the mesa.

US Pat. No. 9,287,413

JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET) AND SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. An n-type junction gate field-effect transistor (NJFET), comprising:
a substrate;
a source region formed in the substrate, wherein the source region is an n-doped region;
a drain region formed in the substrate, wherein the drain region comprises an n-well;
a channel region formed in the substrate, the channel region connecting the source and drain regions, wherein the channel
region is an n-doped region, and the n-well contacts the channel region;

a deep n-well below the channel region, the deep n-well contacting the n-well of the drain region;
at least one gate region formed in the substrate, the at least one gate region configured to cause a depletion in at least
one of the source region or the drain region, wherein the at least one gate region is a p-doped region.

US Pat. No. 9,455,169

ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM

Taiwan Semiconductor Manu...

1. A pod comprising:
a storage chamber having a sidewall surface defining an opening at one side thereof; and
a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber, the pod
door comprising:

a door body;
a first door locking mechanism on the door body, the first door locking mechanism comprising:
a first pressure applicator;
a first key assembly; and
a first connector-rod coupling the first key assembly to the first pressure applicator; and
a seal band, wherein:
the first key assembly is movable between a locked position and an unlocked position,
the seal band is configured to engage the sidewall surface of the storage chamber while the first key assembly is in the locked
position,

an angle defined by a face of the first connector-rod and a face of the first pressure applicator is different when the first
key assembly is in the locked position than when the first key assembly is in the unlocked position, and

the seal band is spaced apart from the first pressure applicator to define a gap when the first key assembly is in the unlocked
position.

US Pat. No. 9,354,510

EUV MASK AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A mask comprising:
a reflective multilayer over a substrate;
an absorption layer disposed over the reflective multilayer; and
an antireflection layer disposed over the absorption layer, wherein a trench extends through the antireflection layer and
terminates in the absorption layer.

US Pat. No. 9,076,553

SPSRAM WRAPPER

Taiwan Semiconductor Manu...

1. A system for facilitating access operations to a single port memory device, comprising:
a wrapper controller configured to:
initiate a first access operation from a first port of a wrapper address component to a single port memory device during a
first clock period;

receive a clock reset signal from the single port memory device, the clock reset signal indicative of a completion of the
first access operation; and

initiate a second access operation from a second port of the wrapper address component to the single port memory device during
the first clock period responsive to receiving the clock reset signal.

US Pat. No. 9,064,797

SYSTEMS AND METHODS FOR DOPANT ACTIVATION USING PRE-AMORPHIZATION IMPLANTATION AND MICROWAVE RADIATION

Taiwan Semiconductor Manu...

1. A method for dopant activation in a semiconductor structure for fabricating semiconductor devices, the method comprising:
providing a substrate;
forming a semiconductor structure on the substrate;
performing pre-amorphization implantation on the semiconductor structure;
providing one or more microwave-absorption materials capable of increasing an electric field density associated with the semiconductor
structure; and

applying microwave radiation to the semiconductor structure and the microwave-absorption materials to activate dopants in
the semiconductor structure for fabricating semiconductor devices;

wherein the microwave-absorption materials are configured to increase the electric field density in response to the microwave
radiation so as to increase the semiconductor structure's absorption of the microwave radiation.

US Pat. No. 9,472,618

NANOWIRE FIELD EFFECT TRANSISTOR DEVICE HAVING A REPLACEMENT GATE

Taiwan Semiconductor Manu...

1. A transistor device, comprising:
a semiconductor substrate;
a buffer layer formed over the semiconductor substrate;
a nanowire formed over the buffer layer and having a pair of distal portions, the nanowire including
source and drain regions respectively defined at the distal portions of the nanowire and
a channel region connecting the source and drain regions of the nanowire;
a gate structure surrounding the nanowire; and
a remnant of a sacrificial layer between the buffer layer and the nanowire, wherein the gate structure and the remnant of
the sacrificial layer define a distance L therebetween and the distance L determines a degree to which areas of the source
region or the drain region are electrically isolated from the buffer layer.

US Pat. No. 9,287,282

METHOD OF FORMING A LOGIC COMPATIBLE FLASH MEMORY

Taiwan Semiconductor Manu...

1. A method comprising:
forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively,
of a semiconductor substrate;

forming a dielectric protection layer overlapping the first pad oxide layer;
removing the second pad oxide layer;
forming a floating gate dielectric over the second active region;
forming a floating gate layer, wherein the floating gate layer comprises a first portion over the dielectric protection layer,
and a second portion over the floating gate dielectric;

performing a planarization on the first portion and the second portion of the floating gate layer;
forming a blocking layer, a control gate layer, and a hard mask layer over the second portion of the floating gate layer;
and

patterning the hard mask layer, the control gate layer, and the blocking layer, wherein a remaining portion of the control
gate layer forms a control gate.

US Pat. No. 9,287,372

METHOD OF FORMING TRENCH ON FINFET AND FINFET THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a trench on a fin field effect transistor (FinFET), comprising:
forming a first inter-layer dielectric layer over a first gate and a second gate of the FinFET;
forming a second inter-layer dielectric layer above the first inter-layer dielectric layer, the first gate of the FinFET,
and the second gate of the FinFET;

patterning a photoresist layer over the second inter-layer dielectric layer;
etching part of the second inter-layer dielectric layer that is not below the photoresist layer to expose the first gate and
the second gate;

forming a first polysilicon layer over the first gate and the second gate and in the second inter-layer dielectric layer;
and

removing the first gate and the second gate and the first polysilicon layer to form a first trench and a second trench through
the first inter-layer dielectric layer and the second inter-layer dielectric layer.

US Pat. No. 9,281,741

START-UP CIRCUIT FOR VOLTAGE REGULATION CIRCUIT

Taiwan Semiconductor Manu...

1. A start-up circuit configured to apply a voltage to a pre-charge node of a primary circuit to alter a wake-up time of the
primary circuit, comprising:
a reset transistor coupled to at least one of ground or a first voltage source and configured to discharge the pre-charge
node to at least one of ground or the first voltage source when the reset transistor is turned-on;

a recharge transistor coupled to a second voltage source and configured to apply the voltage to the pre-charge node when the
recharge transistor is turned-on; and

a control transistor coupled to a third voltage source and configured to control application of a second voltage to a gate
of the recharge transistor.

US Pat. No. 9,064,705

METHODS AND APPARATUS OF PACKAGING WITH INTERPOSERS

Taiwan Semiconductor Manu...

1. A device, comprising:
an interposer with a surface formed by an insulator layer, and a first contact pad covering an opening of the insulator layer
and in contact with a metal layer within the interposer;

a first die and a second die above the interposer, wherein the first die is disposed laterally adjacent the second die; and
a micro-bump layer comprising:
a first micro-bump line above the insulator layer of the interposer, wherein electrical signals between the first die and
the second die are transmitted through the first micro-bump line, and wherein the electrical signals transmitted between the
first die and the second die through the first micro-bump line are not transmitted through the interposer; and

a micro-bump above the first contact pad of the interposer, wherein the micro-bump electrically connects the first die to
the metal layer within interposer.

US Pat. No. 9,054,686

DELAY PATH SELECTION FOR DIGITAL CONTROL OSCILLATOR

Taiwan Semiconductor Manu...

1. A system for delay path selection, comprising:
a delay path selection multiplexer; and a digitally controlled oscillator comprising: a first inverter structure configured
to be selectively enabled by the delay path selection multiplexer to establish a first delay path within the digitally controlled
oscillator; and a second inverter structure configured to be selectively enabled by the delay path selection multiplexer to
establish a second delay path within the digitally controlled oscillator, the second delay path and the first delay path having
at least one inverter structure in common, and wherein: the delay path selection multiplexer is configured to selectively
enable the first inverter structure and the second inverter structure based upon a selected frequency output of the digitally
controlled oscillator.

US Pat. No. 9,282,592

ROTATABLE HEATING-COOLING PLATE AND ELEMENT IN PROXIMITY THERETO

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus for selectively heating or cooling one or more substrates and establishing an approximately uniform temperature
distribution in the one or more substrates during a heating or cooling event, the apparatus comprising:
a rotatable hot-cold plate onto which the one or more substrates are placed, wherein the rotatable hot-cold plate comprises
a plurality of sub-plates for receiving the one or more substrates, and each sub-plate of the plurality of sub-plates is independently
rotatable bi-directionally; and

a heating-cooling element disposed in close proximity to the rotatable hot-cold plate for selectively elevating or lowering
the temperature of the one or more substrates, wherein the rotatable hot-cold plate is configured to rotate relative to the
heating-cooling element.

US Pat. No. 9,275,181

CELL DESIGN

Taiwan Semiconductor Manu...

1. A transistor array of a cell, comprising:
a first transistor comprising:
a first gate, and
a first region having a first length, the first region comprising at least one of a first source or a first drain; and
a second transistor comprising:
a second gate, and
a second region abutting the first region, the second region having a second length different than the first length, the second
region comprising at least one of a second source or a second drain, wherein:

a ratio of the first length to the second length is a function of at least one of a desired alpha ratio for the transistor
array or a desired beta ratio for the transistor array.

US Pat. No. 9,153,452

SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTO-CURRENT DETECTION

Taiwan Semiconductor Manu...

1. A system for performing chemical-mechanical planarization on an article, comprising:
a polishing head configured to perform chemical-mechanical planarization (CMP) on an article;
a polishing pad configured to support the article;
a light source configured to emit an incident light;
a polishing fluid configured to perform CMP including a plurality of light-absorption particles capable of transferring charges
to a stop layer in the article in response the incident light;

a current detector configured to detect a current in response to the light-absorption particles transferring charges to the
stop layer; and

one or more processors configured to control the polishing head based on the detected current.

US Pat. No. 9,123,839

IMAGE SENSOR WITH STACKED GRID STRUCTURE

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a metal grid formed over a photodiode array, the metal grid comprising:
a first metal grid portion comprising a first interface configured to guide light towards a first photodiode and deflect the
light away from a second photodiode; and

a second metal grid portion comprising a second interface configured to guide the light towards the first photodiode;
a dielectric extending between the first metal grid portion and the second metal grid portion, the dielectric comprising a
first material;

a dielectric grid formed over the metal grid, the dielectric grid comprising:
a first dielectric grid portion; and
a second dielectric grid portion; and
a filler material extending between the first dielectric grid portion and the second dielectric grid portion, the filler material
different than the first material.

US Pat. No. 9,425,257

NON-PLANAR SIGE CHANNEL PFET

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:
a semiconductor substrate having a Germanium concentration and including a top surface;
a metal gate including a bottom surface;
a channel layer formed of a Germanium compound having a Germanium concentration and including a top surface and a bottom surface
that is in contact with the top surface of the semiconductor substrate, wherein the top surface of the channel layer is at
higher elevation than the bottom surface of the metal gate from a bottom surface of the semiconductor substrate, the Germanium
concentration of the semiconductor substrate being less than the Germanium concentration of the channel layer; and

a capping layer a portion of which is formed between the top and bottom surfaces of the channel layer to separate the channel
layer from the metal gate, the capping layer having a Germanium concentration, the Germanium concentration of the channel
layer being greater than the Germanium concentration of the capping layer.

US Pat. No. 9,275,752

READ-ONLY MEMORY

Taiwan Semiconductor Manu...

1. A multi-layer bit-1 read-only memory (ROM) cell, comprising:
a first circuit comprising a first transistor; and
a second circuit comprising a second transistor, wherein:
a gate of the second transistor is coupled to a YMUX connection;
the YMUX connection is coupled to a first multiplexer;
a source of the second transistor is coupled to a word-line bar;
the second circuit is configured to control a voltage in the first circuit;
the second transistor is configured to maintain a disconnection between a source of the first transistor and the word-line
bar when a voltage at the YMUX connection is within a low voltage state voltage range; and

the second circuit is located on a different physical layer than the first circuit.

US Pat. No. 9,166,035

DELTA DOPING LAYER IN MOSFET SOURCE/DRAIN REGION

Taiwan Semiconductor Manu...

1. A transistor comprising:
a gate terminal;
a source terminal; and
a drain terminal;
wherein at least one of the source and drain terminals has a layered configuration including
a terminal layer having a top surface and a bottom surface, and
an intervening layer that is located within the terminal layer, between and spaced from the top and bottom surfaces, and that
is oriented to be substantially perpendicular to current flow, and that is less than one tenth the thickness of the terminal
layer; and

wherein the terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a
concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal
layer, and

wherein the intervening layer is spaced at least twice as far from the bottom surface as from the top surface.

US Pat. No. 9,325,310

HIGH-SWING VOLTAGE MODE DRIVER

TAIWAN SEMICONDUCTOR MANU...

1. A high-swing voltage mode driver, comprising:
a first circuit comprising a first transistor, a second transistor and an inverter, a drain of the first transistor coupled
to a first side of the inverter and a drain of the second transistor coupled to a second side of the inverter;

a second circuit comprising a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, a drain of
the third transistor coupled to a drain of the fifth transistor, a drain of the fourth transistor coupled to a drain of the
sixth transistor, the drain of the first transistor coupled to a source of the fifth transistor and the drain of the second
transistor coupled to a source of the sixth transistor; and

a third circuit comprising a seventh transistor and an eighth transistor, a source of the third transistor coupled to a drain
of the seventh transistor and a source of the fourth transistor coupled to a drain of the eighth transistor.

US Pat. No. 9,287,122

METHOD FOR GROWING EPITAXIES OF A CHEMICAL COMPOUND SEMICONDUCTOR

Taiwan Semiconductor Manu...

1. A method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication
process, the method comprising:
providing a prelayer over a substrate;
providing a barrier layer over the prelayer; and
selectively forming an InAs epitaxy layer with low-growth-temperature growth and depositing at least one pair of Al(In)Sb/InAs/Al(in)Sb
at a temperature of about 300 to about 600° C. over the barrier layer to provide a chemical compound semiconductor channel
layer.

US Pat. No. 9,299,810

FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a fin-type field effect transistor comprising:
forming a first semiconductor region;
forming a second semiconductor region;
forming a first fin over the first semiconductor region, the first fin comprising a first source, a first drain, and a first
channel;

forming a second fin over the second semiconductor region, the second fin comprising a second source, a second drain, and
a second channel;

masking a portion of the second semiconductor region for a first period of time;
forming a first portion of a first reacted region from the first semiconductor region during the first period of time;
removing the mask after the first period of time; and
forming a second portion of the first reacted region and a second reacted region from the portion of the second semiconductor
region during a second period of time after the first period of time, the first reacted region having a first dimension causing
a first strain in the first channel, and the second reacted region having a second dimension causing a second strain in the
second channel, the first strain substantially equal to the second strain.

US Pat. No. 9,454,684

EDGE CRACK DETECTION SYSTEM

Taiwan Semiconductor Manu...

9. An edge crack detection system, comprising:
a radio frequency identification (RFID) reader providing a command signal; and
an RFID tag wirelessly connected to the RFID reader, the RFID tag comprising an antenna completely encircling a die under
test, the antenna disposed outside a seal ring surrounding the entire periphery of the die under test, wherein the antenna
receives the command signal, produces power from the command signal, and provides a response signal based on the command signal,

wherein the RFID reader receives the response signal from the RFID tag and provides the command signal regarding the RFID
tag's self-destruction based on the response signal from the RFID tag, and the RFID tag receives the command signal and self-destructs
based on the command signal.

US Pat. No. 9,350,372

ARRANGEMENT FOR DIGITAL-TO-ANALOG CONVERTER

Taiwan Semiconductor Manu...

1. An arrangement for a digital-to-analog converter (DAC), comprising:
a current source configured to supply a current and comprising a first supply transistor, the first supply transistor comprising:
a first source;
a first drain; and
a first gate between the first source and the first drain, the first supply transistor having a horizontal gate layout; and
a switching element configured to switch a current of the current source between a first terminal and a second terminal, the
switching element comprising a first switching transistor, the first switching transistor comprising:

a second source;
a second drain; and
a second gate between the second source and the second drain, the first switching transistor having a vertical gate layout,
wherein a channel length of a first channel of the first supply transistor is at least three times larger than a channel length
of a second channel of the first switching transistor.

US Pat. No. 9,147,766

SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device having a fin-type channel, comprising:
a substrate;
a first buffer layer above at least a portion of the substrate;
a barrier layer above at least a portion of the first buffer layer;
a fin-type channel layer over the barrier layer; wherein a width of the fin-type channel layer is smaller than a width of
the first buffer layer; and

a first dielectric layer surrounding at least a portion of the fin-type channel layer,
wherein at least a portion of the fin-type channel layer protrudes from a top surface of the first dielectric layer.

US Pat. No. 9,393,668

POLISHING HEAD WITH ALIGNMENT GEAR

TAIWAN SEMICONDUCTOR MANU...

1. An arrangement for driving a rolling seal clamp of a polishing head, comprising:
a body configured to be selectively pressurized; and
a first alignment gear extending from an outer circumference of a housing of the polishing head configured for polishing a
semiconductor wafer, the first alignment gear configured to be selectively mated with a first channel of a rolling seal clamp
to which the body is attached, the first alignment gear mated with the first channel when the body is in a pressurized state
and not mated with the first channel when the body is in a depressurized state.

US Pat. No. 9,287,125

MULTIPLE EDGE ENABLED PATTERNING

Taiwan Semiconductor Manu...

1. A method, comprising:
forming a first pattern on a wafer, the first pattern extending in a first direction;
forming a second pattern on the wafer, the second pattern extending in the first direction and being separated from the first
pattern by a first distance measured in a second direction perpendicular to the first direction; and

forming a third pattern on the wafer, the third pattern being separated from the first pattern by a second distance measured
in the first direction, the third pattern being separated from the second pattern by a third distance measured in the first
direction;

wherein the first distance is approximately equal to the third distance; and
wherein the second distance is less than twice the first distance.

US Pat. No. 9,276,108

MEMORY CELL ARRAY AND CELL STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor read-only memory (ROM) unit cell structure comprising:
a cell base region defining a cell boundary, comprising a blanket OD layer having a wide-block profile disposed on a substrate
and defining a continuous common source node, arranged in selective connection with a ground (Vss);

a drain pad disposed above the OD layer selectively connected with a bit line;
a vertical channel structure bridging the drain pad and the OD layer; and
a gate structure disposed vertically between the drain pad and the OD layer and connected with a word-line;
wherein the cell boundary is defined within the coverage of the OD layer.

US Pat. No. 9,391,350

RF CHOKE DEVICE FOR INTEGRATED CIRCUITS

Taiwan Semiconductor Manu...

10. A system for selectively filtering a radio frequency (RF) bandwidth, comprising:
a 3D RF choke configured to selectively filter the RF bandwidth, the 3D RF choke comprising:
a metal connection line configured as an inductive element, the metal connection line connecting to a DC power source at a
first location of the metal connection line, the metal connection line connecting to a metal RF line at a second location
of the metal connection line, the metal RF line connecting an RF input port to an RF output port; and

a capacitive element comprising:
a first ground through via connected to a ground point; and
a first signal through via connected to the metal connection line at a third location of the metal connection line.

US Pat. No. 9,305,837

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor arrangement, the method comprising:
forming a first metal trace in a first dielectric opening in a dielectric layer, the first metal trace having a first metal
trace width between about 30 nm to about 60 nm and a first metal trace length; and

forming a second metal trace in a second dielectric opening in the dielectric layer, the second metal trace having a second
metal trace width between about 10 nm to about 20 nm and second metal trace length, the first metal trace length different
than the second metal trace length, such that the dielectric layer has a dielectric layer width between the first metal trace
and the second metal trace between about 10 nm to about 20 nm.

US Pat. No. 9,461,069

SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE TRANSISTOR LAYERS

Taiwan Semiconductor Manu...

1. A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region
and different transistor types fabricated using different channel material, the semiconductor structure comprising:
a first transistor layer comprising a first type of channel material in the first region but no channel material in the second
region;

a second transistor layer comprising a second type of channel material in the second region but no channel material in the
first region, the second transistor layer vertically elevated above the first transistor layer;

a first transistor fabricated on the first transistor layer; and
a second transistor fabricated on the second transistor layer, wherein the first transistor is interconnected with the second
transistor to form a circuit.

US Pat. No. 9,305,135

GENERATING A SEMICONDUCTOR COMPONENT LAYOUT

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:
generating, by a processor, a first set of configurations of a layout of semiconductor components, the configurations of the
first set of configurations each satisfying a first sub-set of a set of design rules, the first sub-set of the set of design
rules comprising a first quantity of design rules, the first quantity of design rules being less than a second quantity of
design rules included in the set of design rules;

generating, by the processor, a second set of configurations of the layout of semiconductor components, the second set of
configurations being generated by eliminating one or more configurations of the first set of configurations based on a determination
that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the
set of design rules, the second sub-set of the set of design rules comprising one or more of the design rules included in
the set of design rules other than the design rules included in the first sub-set of the set of design rules; and

manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second
set of configurations.

US Pat. No. 9,263,330

SEMICONDUCTOR DEVICE, METHOD FOR FORMING CONTACT AND METHOD FOR ETCHING CONTINUOUS RECESS

Taiwan Semiconductor Manu...

1. A method for forming a continuous contact plug, comprising:
forming a first dielectric layer over a substrate;
forming a second dielectric layer over the first dielectric layer;
patterning the second dielectric layer to form a first recess;
patterning the first dielectric layer by a first etchant through the first recess to form a second recess,
wherein the first etchant has a higher etching rate with respect to the first dielectric layer than with respect to the second
dielectric layer and further wherein the second recess is aligned with the first recess; and

forming the continuous contact plug in the first recess and the second recess.

US Pat. No. 9,169,117

MEMS DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a Micro Electro Mechanical System (MEMS) device, comprising:
providing a substrate;
forming a catalyst layer over the substrate;
patterning the catalyst layer;
forming a carbon nanotube based on the catalyst layer;
forming a getter layer over the carbon nanotube and the substrate; and
etching back the getter layer to expose the carbon nanotube.

US Pat. No. 9,397,040

SEMICONDUCTOR DEVICE COMPRISING METAL PLUG HAVING SUBSTANTIALLY CONVEX BOTTOM SURFACE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a dielectric layer;
a metal plug over a substrate, the metal plug having a contact bottom surface that is substantially convex;
a metal layer in contact with sidewalls of the dielectric layer and between the dielectric layer and the metal plug; and
a silicide layer between the substrate and the metal plug, wherein:
the silicide layer has a silicide layer top surface that is substantially concave to interface with the substantially convex
contact bottom surface of the metal plug; and

the metal layer terminates at an edge of the silicide layer.

US Pat. No. 9,317,650

DOUBLE PATTERNING TECHNOLOGY (DPT) LAYOUT ROUTING

TAIWAN SEMICONDUCTOR MANU...

1. A system for determining double patterning technology (DPT) layout routing compliance, comprising:
a layout routing component configured to:
create a first pin group comprising a first set of one or more pre-colored pins that are linked together by a first set of
internal conflict spaces;

associate the first pin group with a first phantom assisted feature (AF) mask polygon, the associating comprising:
selecting a first pre-colored pin from the first set of one or more pre-colored pins;
determining a first mask assignment associated with the first pre-colored pin; and
assigning the first phantom AF mask polygon to a different mask than a mask for the first pre-colored pin according to the
first mask assignment;

create a pin loop based on the first pre-colored pin and the phantom AF mask polygon;
assign a pin loop value to the pin loop; and
determine whether a double patterning technology (DPT) violation is present for the pin loop based on the pin loop value.

US Pat. No. 9,425,085

STRUCTURES, DEVICES AND METHODS FOR MEMORY DEVICES

Taiwan Semiconductor Manu...

1. A static random access memory (SRAM) device comprising:
first, second, and third conductive layers;
a first word line disposed in the first conductive layer;
a first landing pad disposed in the first conductive layer;
a second word line disposed in the second conductive layer and coupled to the first landing pad;
a second landing pad disposed in the first conductive layer;
a third word line disposed in the third conductive layer and coupled to the second landing pad; and
an SRAM cell coupled to the first word line and the first and second landing pads, wherein at least two of the second conductive
layer, the third conductive layer, and the first conductive layer are disposed one above the other.

US Pat. No. 9,338,834

SYSTEMS AND METHODS FOR MICROWAVE-RADIATION ANNEALING

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor structure using microwave radiation, the semiconductor structure including a top
portion and a bottom portion, the method comprising:
providing a semiconductor structure;
providing one or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave
radiation;

applying microwave radiation to the energy-converting materials and the semiconductor structure to anneal the semiconductor
structure for fabricating semiconductor devices;

detecting first local temperatures associated with one or more first zones of the semiconductor structure, wherein the first
zones are disposed in the top portion;

adjusting the microwave radiation applied to the energy-converting materials and the semiconductor structure based at least
in part on the detected first local temperatures;

detecting second local temperatures associated with one or more second zones of the semiconductor structure, wherein the second
zones are disposed in the bottom portion; and

adjusting the microwave radiation applied to the energy-converting material and the semiconductor structure based at least
in part on the detected second local temperatures.

US Pat. No. 9,281,287

SEMICONDUCTOR BONDING STRUCTURE AND PROCESS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a passivation layer on a substrate;
a first eutectic bonding material at least partially over the passivation layer, the first eutectic bonding material further
comprising:

an initiating portion with a first composition; and
a halting portion surrounding the initiating portion, the halting portion having a second composition different from the first
composition; and

a block laterally separated from the first eutectic bonding material, wherein the block comprises a first material, wherein
the halting portion comprises the first material.

US Pat. No. 9,281,297

SOLUTION FOR REDUCING POOR CONTACT IN INFO PACKAGES

Taiwan Semiconductor Manu...

1. A method comprising:
forming a first package, wherein the first package comprises:
a dielectric layer;
a plurality of redistribution lines in the dielectric layer;
a device die over and electrically coupled to the plurality of redistribution lines;
a molding material molding the device die therein; and
a through-via penetrating through the molding material;
disposing a spacer to attach to a first one of the first package and a second package;
disposing an additional spacer attached to a second one of the first package and the second package; and
bonding the first package to the second package, with the spacer aligned to the additional spacer, wherein the spacer is located
between the first package and the second package.

US Pat. No. 9,281,475

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) WITH MULTI-LAYER DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A resistive memory comprising:
a first electrode and a second electrode; and
a multi-layer resistance-switching network disposed between the first electrode and the second electrode, the multi-layer
resistance-switching network comprising:

a group-IV element doping layer;
a first carbon doping layer disposed between the group-IV element doping layer and the first electrode; and
a second carbon doping layer disposed between the group-IV element doping layer and the second electrode.

US Pat. No. 9,252,217

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

11. A method of forming a semiconductor arrangement, comprising:
forming a first opening having a first opening width in a first dielectric layer, the first dielectric layer over a substrate;
forming a first portion of a semiconductor column in the first opening, the first portion comprising a first material, the
first portion having a first portion width substantially equal to the first opening width;

forming a second dielectric layer around the first portion, such that a top surface of the second dielectric layer is above
a top surface of the first portion and a second opening is defined in the second dielectric layer above the first portion,
where the second opening has a second opening width substantially equal to the first opening width; and

forming a second portion of the semiconductor column over the first portion in the second opening, the second portion comprising
a second material different than the first material, the second portion having a second portion width substantially equal
to the first opening width.

US Pat. No. 9,238,578

SEMICONDUCTOR ARRANGEMENT WITH STRESS RELEASE AND THERMAL INSULATION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer;
a microelectromechanical systems (MEMS) wafer formed over the CMOS wafer, the MEMS wafer comprising a high vacuum chamber
configured as a sensing gap between a membrane of the MEMS wafer and a poly layer of the MEMS wafer;

a cap wafer formed over the MEMS wafer; and
an ambient pressure chamber formed between the MEMS wafer and the cap wafer.

US Pat. No. 9,425,091

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor structure, comprising:
forming a first etch stop layer (ESL);
forming an oxide region above the first ESL;
forming a low-k (LK) dielectric region above the oxide region;
forming a first metal line through at least one of the first ESL, the oxide region, or the LK dielectric region;
forming a second metal line through at least one of the first ESL, the oxide region, or the LK dielectric region;
forming a second ESL over at least one of the first metal line, the second metal line, or the LK dielectric region;
removing at least a portion of the second ESL at least one of:
over at least one of the first metal line or the second metal line; or
between the first metal line and the second metal line;
forming a gap by removing at least one of:
at least a portion of the oxide region between the first metal line and the second metal line; or
at least a portion of the LK dielectric region between the first metal line and the second metal line; and
forming an ESL seal region over at least one of the second ESL, the first metal line, the second metal line, or the gap.

US Pat. No. 9,291,913

PATTERN GENERATOR FOR A LITHOGRAPHY SYSTEM

Taiwan Semiconductor Manu...

14. A method for fabricating a resist pattern, the method comprising:
receiving a substrate;
depositing a resist film on the substrate;
exposing the resist film deposited on the substrate according to a pattern generator (PG), wherein the pattern generator includes:
a mirror array plate having a mirror;
an insulator layer disposed over the mirror array plate;
an electrode plate disposed over the insulator plate, where in the electrode plate includes a first conducting layer and a
second conducting layer; and

a lens let formed over the mirror, wherein the lens let includes a non-straight sidewall formed in the electrode plate; and
forming the resist pattern on the substrate by developing the exposed resist film.

US Pat. No. 9,292,030

ELECTRONIC CIRCUIT HAVING BAND-GAP REFERENCE CIRCUIT AND START-UP CIRCUIT, AND METHOD OF STARTING-UP BAND-GAP REFERENCE CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A circuit, comprising:
a band-gap reference circuit comprising:
an operational amplifier having an output, a first input, and a second input;
a first current path between a power supply node and a reference node, the first input of the operational amplifier being
coupled to the first current path;

a second current path between the power supply node and the reference node, the second input of the operational amplifier
being coupled to the second current path; and

a feedback path between the output of the operational amplifier and the first current path and the second current path; and
a start-up circuit comprising:
a current source; and
at least one switch coupled between the current source and the band-gap reference circuit, the at least one switch being configured
to electrically couple the current source with the first current path and the second current path during a start-up phase,
and to electrically decouple the current source from the first current path and the second current path after the start-up
phase.

US Pat. No. 9,287,171

METHOD OF MAKING A CONDUCTIVE PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of making a semiconductor device, the method comprising:
forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region;
forming a conductive pillar over the UBM layer, the conductive pillar comprising sidewalls, wherein the conductive pillar
exposes the surface region of the UBM layer;

forming a barrier layer over the conductive pillar; and
forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure
contacts the surface region of the UBM layer, the barrier layer is between the non-metal protective structure and the conductive
pillar, and the non-metal protective structure exposes the sidewalls of the UBM layer.

US Pat. No. 9,286,979

METHOD AND STRUCTURE FOR RESISTIVE SWITCHING RANDOM ACCESS MEMORY WITH HIGH RELIABLE AND HIGH DENSITY

Taiwan Semiconductor Manu...

1. An apparatus comprising:
a memory device that includes a resistive material layer having filament features with a filament ratio that is equal to or
greater than about 0.5, wherein the filament features has a size distribution with a characteristic size Sm, wherein the filament features includes a first subset features each with a radius less than Sm and a second subset features each with a radius greater than Sm, and wherein the filament ratio is defined as As/(As+Al), wherein As is a first sum of sectional areas of the first subset features and Al is a second sum of sectional areas of the second subset features.

US Pat. No. 9,280,046

METHOD OF FABRICATING MASK

Taiwan Semiconductor Manu...

1. A method for fabricating an extreme ultraviolet (EUV) mask, the method comprising:
providing a low thermal expansion material (LTEM) layer;
forming a reflective multiple-layer (ML) over the LTEM layer;
forming a conductive layer over an opposite surface of the LTEM layer;
spin-coating a flowable-photosensitive-absorption-layer (FPhAL) over the reflective ML, wherein the FPhAL contains at least
one of HfO2 and Al2O3; and

patterning the FPhAL by a lithography process to form a patterned absorption layer having a first region and a second region,
wherein the FPhAL is removed in the first region and remains in the second region.

US Pat. No. 9,490,288

IMAGE SENSOR WITH TRENCHED FILLER GRID WITHIN A DIELECTRIC GRID INCLUDING A REFLECTIVE PORTION, A BUFFER AND A HIGH-K DIELECTRIC

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array over a substrate;
a dielectric grid over the photodiode array and comprising a first dielectric structure and a second dielectric structure;
a reflective portion between the first dielectric structure and the second dielectric structure;
a filler grid comprising a first filler structure between the first dielectric structure and the second dielectric structure,
the first filler structure over a first photodiode of the photodiode array;

a buffer laterally between the reflective portion and the first dielectric structure, the buffer in direct physical contact
with the first filler structure and the buffer comprising a different material composition than the first dielectric structure
and the second dielectric structure; and

a high-k dielectric laterally between the buffer and the first dielectric structure.

US Pat. No. 9,449,886

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method, comprising:
etching a substrate to define a set of fins;
masking a top surface of a first subset of the set of fins;
etching a second subset of the set of fins while the top surface of the first subset is masked to reduce a fin height of fins
that are members of the second subset;

etching a portion of the substrate between a first fin of the second subset and a second fin of the second subset to define
a trench;

forming a shallow trench isolation (STI) region within a first portion of the trench and a second portion of the trench; and
depositing a conductive material within a third portion of the trench, over the first subset, and over the second subset to
form a metal connect, wherein:

the third portion of the trench is between the first portion of the trench and the second portion of the trench, and
the metal connect is in contact with the first subset and the second subset.

US Pat. No. 9,391,023

METHOD FOR PRODUCING SALICIDE AND A CARBON NANOTUBE METAL CONTACT

Taiwan Semiconductor Manu...

1. A method of producing a metal contact in a semiconductor device comprising:
depositing a catalyst material layer in a via hole;
forming a catalyst from the catalyst material layer;
growing a carbon nanotube structure using the catalyst in the via hole;
forming a portion of salicide from the catalyst after the growth of the carbon nanotube structure;
applying a chemical mechanical polishing (CMP) process to the carbon nanotube structure to remove top layers of catalyst and
nanotube material; and

depositing metal material above the carbon nanotube structure.

US Pat. No. 9,287,172

INTERPOSER-ON-GLASS PACKAGE METHOD

Taiwan Semiconductor Manu...

1. A method comprising:
providing an interposer comprising:
a substrate; and
a first through-substrate via (TSV) penetrating through the substrate;
forming a first oxide layer on a surface of the interposer;
bonding a glass substrate to the interposer through a fusion bonding, with the first oxide layer being between the interposer
and the glass substrate; and

forming a second TSV in the glass substrate and electrically coupled to the first TSV.

US Pat. No. 9,177,924

VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

Taiwan Semiconductor Manu...

1. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:
an input terminal for receiving an input signal;
an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including
one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes:

a well of a first conductivity type that is formed in a semiconductor substrate,
a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire
that is opposite the first end, the source region further including a portion formed in the well, wherein the source region
and the drain region are of a second conductivity type such that a PN junction is formed between the well and the portion
of the source region formed in the well, and

a gate region surrounding a portion of the nanowire, wherein the gate region is separated from the drain region by a first
distance, the separation of the gate region and the drain region providing a resistance in series between the drain region
and the source region; and

an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage
in the input signal is attenuated by the resistance and the PN junction.

US Pat. No. 9,123,563

METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE

Taiwan Semiconductor Manu...

7. A method of forming a contact structure of a gate structure, comprising:
etching an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate to expose
an underlying silicon substrate;

depositing a silicide portion defined by a contact profile in the exposed portion of the silicon substrate;
depositing a metal glue layer around the first metal gate and the second metal gate defining a trench above the silicide portion;
and

depositing a metal plug within the trench.

US Pat. No. 9,261,534

SHIELD PIN ARRANGEMENT

Taiwan Semiconductor Manu...

1. A probe card for testing an electronic device comprising:
a signal pin configured to carry a signal;
a first set of one or more shield pins lying within a first plane; and
a second set of one or more shield pins lying within a second plane different than the first plane, the first set and the
second set of one or more shield pins configured to shield the signal pin from an interference signal.

US Pat. No. 9,130,531

SEMICONDUCTOR ARRANGEMENT WITH THERMAL INSULATION CONFIGURATION

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor arrangement, comprising:
forming a microelectromechanical systems (MEMS) wafer comprising a thermal insulator air gap between a sensing layer and a
membrane;

bonding the MEMS wafer to a complementary metal-oxide-semiconductor (CMOS) wafer;
forming an ambient pressure chamber between the CMOS wafer and the membrane of the MEMS wafer, the ambient pressure chamber
exposed to ambient air; and

bonding a cap wafer to the MEMS wafer, the cap wafer comprising a pressurized chamber having a pressure different than an
ambient air pressure.

US Pat. No. 9,425,324

SEMICONDUCTOR DEVICE AND CHANNEL STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a composite structure that comprises
an inner core strut that comprises a gate stack; and
an outer sleeve layer that is sleeved on the gate stack of the inner core strut and that comprises a two-dimensional (2-D)
layered material, wherein the inner core strut mechanically supports the outer sleeve layer and wherein the outer sleeve layer
has a central portion that defines a channel region and a pair of opposing end portions that respectively define source and
drain regions.

US Pat. No. 9,406,626

SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a main circuit;
an assembly isolation region that surrounds the main circuit, the assembly isolation region comprising a first circuit that
includes a first capacitor and a first inductor connected in series; and

a first seal ring that surrounds the assembly isolation region, the first capacitor and the first inductor (i) being connected
between the first seal ring and a ground, and (ii) being disposed laterally between the first seal ring and the main circuit.

US Pat. No. 9,349,690

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor arrangement, comprising:
forming a first metal layer in a first opening of a dielectric, a second opening of the dielectric and over the dielectric,
the first metal layer comprising titanium nitride;

forming a first interconnect over the first metal layer in the first opening;
forming a second interconnect over the first metal layer in the second opening;
forming a first dielectric layer over the first metal layer, the first interconnect and the second interconnect;
performing a first etch to remove a first portion of the first dielectric layer over the first interconnect, the second interconnect
and a first portion of the first metal layer and to remove the first portion of the first metal layer from a first top portion
of a top surface of the dielectric, such that a first metal layer first portion remains in the first opening and a first metal
layer second portion remains in the second opening;

performing a second etch to form a first air gap on first side of the first metal layer first portion and to form a second
air gap on a second side of the first metal layer first portion, such that the second air gap is between the first metal layer
first portion and the first metal layer second portion;

performing a third etch to remove first sidewalls of the first metal layer first portion, such that a first bottom portion
of the first metal layer remains under the first interconnect, and to remove second sidewalls of the first metal layer second
portion, such that a second bottom portion of the first metal layer remains under the second interconnect; and

forming a protective barrier over the first interconnect and the second interconnect.

US Pat. No. 9,287,856

TRACKING CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A circuit comprising:
a switching circuit having a first terminal, a second terminal, and a third terminal, the first terminal configured to have
a supply voltage value;

a node electrically coupled with the second terminal of the switching circuit, the node having a node voltage, the node voltage
having a first voltage value higher than the supply voltage value; and

a tracking circuit electrically coupled to the third terminal of the switching circuit and the node, and configured to selectively
turn on or turn off the switching circuit by generating a control voltage at the third terminal of the switching circuit based
on the node voltage.

US Pat. No. 9,293,294

FREQUENCY DEPENDENT CLOCK APPARATUS AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A method for operating a dynamic pattern generator (DPG), the method comprising:
receiving a first clock having a frequency and a period;
determining a toggling rate based on the frequency of the first clock;
comparing the toggling rate with a threshold; and
providing a signal including information on a delay for the first clock based on the period of the first clock in response
to a result of the comparing.

US Pat. No. 9,293,585

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

17. A semiconductor device comprising:
a gate structure over a substrate including a gate electrode and gate spacers on opposing sides of the gate electrode;
a first etch stop layer (ESL) over the substrate and at least the gate spacers;
a first inter-layer dielectric over the first ESL;
a second ESL over the first ILD and directly adjoining the first ESL; and
a second ILD over the second ESL, wherein the gate electrode, the first ESL, the second ESL, and the second ILD each have
surfaces which are substantially coplanar.

US Pat. No. 9,281,338

SEMICONDUCTOR IMAGE SENSOR DEVICE HAVING BACK SIDE ILLUMINATED IMAGE SENSORS WITH EMBEDDED COLOR FILTERS

Taiwan Semiconductor Manu...

1. A semiconductor image sensor device, comprising:
a substrate having a first side and a second side that is opposite the first side;
an interconnect structure disposed over the first side of the substrate;
radiation-sensing regions located in the substrate, the radiation-sensing regions being configured to sense radiation that
enters the substrate from the second side, wherein the radiation-sensing regions are separated by gaps;

radiation-blocking structures disposed over the second side of the substrate, wherein each of the radiation-blocking structures
is aligned with a respective one of the gaps;

color filters, each of the color filters being embedded in a space between two adjacent radiation-blocking structures; and
a passivation layer, portions of the passivation layer being disposed between the color filters and the radiation-blocking
structures.

US Pat. No. 9,230,961

SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a well region;
a first region disposed within the well region, the first region comprising a first conductivity type;
a first gate disposed above the well region on a first side of the first region, the first gate comprising a first top surface
facing away from the well region, the first top surface having a first top surface area;

a first gate contact disposed above the first gate, the first gate contact comprising a first bottom surface facing towards
the well region, the first bottom surface having a first bottom surface area, the first bottom surface area covering at least
about two thirds of the first top surface area;

a first region contact disposed above the first region; and
a first multi-gate contact in direct physical contact with the first gate contact and the first region contact.

US Pat. No. 9,281,376

SEMICONDUCTOR STRUCTURES EMPLOYING STRAINED MATERIAL LAYERS WITH DEFINED IMPURITY GRADIENTS AND METHODS FOR FABRICATING SAME

Taiwan Semiconductor Manu...

1. A method comprising:
forming a dummy gate structure on a channel area of a substrate;
forming a source region and a drain region on opposing sides of the channel area in the substrate;
after forming the source region and the drain region, removing the dummy gate structure;
after removing the dummy gate structure, forming a semiconductor layer on the channel area of the substrate, wherein the semiconductor
layer comprises a first concentration of an impurity in a first portion adjacent an interface with the substrate, a second
concentration of the impurity in a second portion distal from the interface, and a third concentration in a third portion
disposed between the first portion and the second portion, the first concentration being greater than the second concentration,
the third concentration being greater than the second concentration; and

forming a gate electrode structure over the semiconductor layer.

US Pat. No. 9,093,455

BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

15. An interconnect structure, the interconnect structure comprising:
a dielectric layer, the dielectric layer having a recess therein;
a silicon (Si) layer that is deposited in the recess; and
an interconnect including a barrier layer and a conductive layer that are provided in the recess over the Si layer, wherein
the Si layer has a density that substantially prevents the barrier layer from moving away from the conductive layer and towards
the dielectric layer during subsequent processing of the interconnect structure,

wherein the interconnect structure is planarized to cause portions of the Si layer, the barrier layer, and the conductive
layer to be coplanar with a top surface of the dielectric layer, the interconnect structure further comprising:

a nitride layer that is formed in a first portion of the Si layer that is adjacent to the top surface; and
an oxide layer that is formed in a second portion of the Si layer that is adjacent to the first portion.

US Pat. No. 9,550,270

TEMPERATURE MODIFICATION FOR CHEMICAL MECHANICAL POLISHING

Taiwan Semiconductor Manu...

1. A system, comprising:
a fluid reservoir for storing a liquid;
a nozzle for dispensing the liquid onto a polishing pad of a chemical mechanical polishing (CMP) system;
a first fluid pathway from the fluid reservoir to the nozzle;
a second fluid pathway from the fluid reservoir to the nozzle;
a first valve disposed within the first fluid pathway;
a second valve disposed within the second fluid pathway;
a liquid heater component disposed within the second fluid pathway between the fluid reservoir and the second valve, the liquid
heater component comprising a quartz heater configured to heat the liquid to generate heated liquid, wherein the heated liquid
is supplied to the polishing pad upon which a semiconductor wafer is to be polished to generate a heated polishing pad having
a heated polishing pad temperature; and

a polishing component configured to:
responsive to the heated polishing pad temperature exceeding a threshold, polish the semiconductor wafer utilizing the heated
polishing pad during a CMP stage.

US Pat. No. 9,219,471

CIRCUITRY FOR PHASE DETECTOR

Taiwan Semiconductor Manu...

1. A circuit for a phase detector, comprising:
a first buffer configured to:
receive a data signal; and
apply a first delay to the data signal, using a first delay signal, to generate a first modified data signal;
a notifier configured to:
receive the data signal; and
determine whether a violation exists in at least one of a setup timing margin or a hold timing margin;
a first multiplexer configured to:
receive the first modified data signal from the buffer at a 0-input of the first multiplexer;
receive a random value at a 1-input of the first multiplexer; and
transmit a first multiplexer data signal, comprising:
responsive to the notifier determining that the violation exists in at least one of the setup timing margin or the hold timing
margin, transmitting the random value as the first multiplexer data signal; and

responsive to the notifier determining that the violation does not exist in at least one of the setup timing margin or the
hold timing margin, transmitting the first modified data signal from the buffer as the first multiplexer data signal; and

a second multiplexer configured to:
receive the first modified data signal from the buffer at a 0-input of the second multiplexer;
receive the first multiplexer data signal from the first multiplexer at a 1-input of the second multiplexer;
receive a random value turn on control signal; and
transmit a second multiplexer data signal to a D-pin of a flip-flop of the phase detector, comprising:
responsive to the random value turn on control signal comprising 1, transmitting the first multiplexer data signal as the
second multiplexer data signal; and

responsive to the random value turn on control signal comprising 0, transmitting the first modified data signal from the buffer
as the second multiplexer data signal.

US Pat. No. 9,124,086

FAILSAFE ESD PROTECTION

Taiwan Semiconductor Manu...

1. A method for providing failsafe electrostatic discharge (ESD) protection, comprising:
connecting a voltage source (VDDA) to a source of a transistor;
connecting a voltage fail safe (VFS) supply voltage to an NWELL circuit interface of an NWELL body of the transistor; and
connecting a PAD to the VFS supply voltage via a first diode, the PAD operably connected to circuitry to be protected from
ESD.

US Pat. No. 9,337,263

SEMICONDUCTOR DEVICE INCLUDING A SEMICONDUCTOR SHEET UNIT INTERCONNECTING A SOURCE AND A DRAIN

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substrate extending in a substantially horizontal direction;
a source unit including a plurality of sources;
a drain unit including a plurality of drains, wherein one of the source unit and the drain unit is formed on the substrate;
a semiconductor sheet unit extending in a substantially vertical direction and interconnecting the source unit and the drain
unit; and

a nanowire unit extending in the substantially vertical direction, interconnecting the source unit and the drain unit, and
having a cross-sectional shape of a dot in a top view.

US Pat. No. 9,287,440

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING THROUGH SILICON PLUGS

Taiwan Semiconductor Manu...

14. A method of making a semiconductor device, the method comprising:
etching a top surface of a substrate to form a first opening and a second opening;
forming an isolation layer in the first opening and the second opening, the isolation layer having a higher thermal resistance
than the substrate;

forming a continuous conductive material in both of the first opening and the second opening, wherein the isolation layer
is located between conductive material and the substrate;

forming a metal pad over the top surface of the substrate, wherein the metal pad is electrically and thermally connected to
the conductive material in the first opening and the conductive material in the second opening; and

bonding a device to the metal pad, wherein the metal pad is electrically and thermally connected to the device.

US Pat. No. 9,269,812

SEMICONDUCTOR DEVICE HAVING V-SHAPED REGION

Taiwan Semiconductor Manu...

1. A transistor, comprising:
a source/drain region having a height-to-length ratio exceeding at least 1.5 when a poly spacing between the transistor and
a second transistor is less than about 75 nm and having a height-to-length ratio exceeding at least 1.6 when the poly spacing
between the transistor and the second transistor is less than about 60 nm.

US Pat. No. 9,263,295

NANOWIRE MOSFET WITH SUPPORT STRUCTURES FOR SOURCE AND DRAIN

Taiwan Semiconductor Manu...

1. A method for forming a nanowire field effect transistor (FET) device, the method comprising:
forming a device layer including a source region and a drain region being connected by a nanowire channel to be suspended,
the nanowire channel being provided over a sacrificial material;
forming first and second etch stop layers respectively beneath the source region and the drain region,
each of the etch stop layers forming a support structure over a semiconductor substrate; and
suspending the nanowire channel by
etching the sacrificial material beneath the nanowire channel, the etching being selective to the sacrificial material to
substantially prevent the removal of the etch stop layers beneath the source region and the drain region.

US Pat. No. 9,257,559

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a fin having a first wall extending along a first plane, the fin comprising:
a doped region, the doped region defining a first furrow on a first side of the first plane; and
a dielectric disposed within the first furrow, wherein:
the dielectric is contact with the first furrow between a first end of the dielectric and a second end of the dielectric,
the first end is separated a first distance from the first plane; and
the dielectric is convex such that an outer most protruding point is at least one of even with the first plane, on the first
side of the first plane or on a second side of the first plane.

US Pat. No. 9,233,839

MEMS DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method for forming a microelectromechanical systems (MEMS) device, comprising:
providing a substrate having a first portion and a second portion;
fabricating a membrane type sensor on the first portion of the substrate; and
fabricating a bulk silicon sensor on the second portion of the substrate,
wherein fabricating the membrane type sensor further comprises:
providing a conductive base over the substrate;
providing a sacrificial layer over the conductive base;
providing a reference element over the sacrificial layer;
providing a dielectric layer over the reference element;
removing a portion of the sacrificial layer between the reference element and the conductive base using a plurality of holes
extending through the dielectric layer and the reference element to the sacrificial layer to form a first cavity of the membrane
type sensor between the reference element and the conductive base;

forming a sealing layer above the dielectric layer to seal the first cavity of the membrane type sensor by using Titanium
as the sealing layer; and

patterning the sealing layer over the reference element.

US Pat. No. 9,177,785

THIN OXIDE FORMATION BY WET CHEMICAL OXIDATION OF SEMICONDUCTOR SURFACE WHEN THE ONE COMPONENT OF THE OXIDE IS WATER SOLUBLE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor structure comprising:
forming a solvent mixture by mixing a water soluble substance with an aprotic solvent; and
forming a thin layer of oxide over a semiconductor surface by performing wet chemical oxidation operations on the semiconductor
surface with the solvent mixture.

US Pat. No. 9,123,546

MULTI-LAYER SEMICONDUCTOR DEVICE STRUCTURES WITH DIFFERENT CHANNEL MATERIALS

Taiwan Semiconductor Manu...

15. A method for fabricating a semiconductor device structure, the method comprising:
selecting a first material capable of sustaining a first processing temperature and a second material capable of sustaining
a second processing temperature equal to or lower than the first processing temperature;

forming a first device layer on a substrate, the first device layer including a first channel structure for conducting a first
current, the first channel structure including the first material; and

forming a second device layer on the first device layer, the second device layer including a second channel structure for
conducting a second current, the second channel structure including the second material,

wherein the selection of the first material further comprises selecting the first material further capable of sustaining a
first thermal budget proportional to a first processing duration, a second thermal budget proportional to a second processing
duration, and a third thermal budget associated with consolidation of a bonding interface between the first device layer and
the second device layer.

US Pat. No. 9,422,151

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:
a cavity;
a membrane in the cavity;
a substrate on one side of the cavity; and
a mesa protruded from a surface of the substrate and toward the membrane, wherein the mesa comprises:
a material proximal to the membrane;
a first buffer layer between the substrate and the material, and at least partially covered by the material; and
a second buffer layer between the substrate and the first buffer layer, and partially covered by the first buffer layer, wherein
the material contacts the second buffer layer, and the second buffer layer includes a hardness greater than a hardness of
the first buffer layer.

US Pat. No. 9,413,140

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a three dimensional (3D) integrated circuit (IC) structure comprising:
a first layer comprising:
a gate of a transistor; and
a first optical transmitter, wherein a first source/drain region of the transistor is coupled to a first serializer and a
second source/drain region of the transistor is coupled to the first optical transmitter, the transistor configured to selectively
couple the first optical transmitter to the first serializer; and

a second layer comprising a second optical transmitter over the first layer, the first optical transmitter configured to transmit
data from the first layer to the second layer and the second optical transmitter configured to transmit data from the second
layer to the first layer.

US Pat. No. 9,318,447

SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL STRUCTURE

Taiwan Semiconductor Manu...

1. A method of forming a vertical structure with at least two barrier layers, comprising:
providing a substrate;
providing a vertical structure over the substrate;
providing a first barrier layer over a source, a channel, and a drain of the vertical structure;
forming a first interlayer dielectric over the first barrier layer corresponding to the source of the vertical structure;
and

providing a second barrier layer over a gate and the drain of the vertical structure.

US Pat. No. 9,312,186

METHOD OF FORMING HORIZONTAL GATE ALL AROUND STRUCTURE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device having a horizontal gate all around structure on a substrate, the method comprising:
forming a plurality of fins on the substrate, each fin comprising a top channel layer, a bottom channel layer below the top
channel layer, a top sacrificial layer between the top channel layer and the bottom channel layer, and a bottom sacrificial
layer between the substrate and the bottom channel layer;

forming a shallow trench isolation between the fins;
etching the shallow trench isolation to expose a portion of the fins above a first level;
etching the shallow trench isolation to expose the portion of the fins above a second level which is lower than the first
level; and

removing the top sacrificial layer and the bottom sacrificial layer above the second level.

US Pat. No. 9,281,363

CIRCUITS USING GATE-ALL-AROUND TECHNOLOGY

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:
a first gate-all-around (GAA) structure configured to form a first circuit;
a second GAA structure configured to form a second circuit similar to the first circuit;
wherein
each of the first GAA structure and the second GAA structure comprises:
at least one GAA device, each GAA device comprising:
at least one nanowire;
a first oxide diffusion (OD) region and a second OD region connected to opposite ends of the at least one nanowire; and
a gate region wrapping all around a portion of each of the at least one nanowire;
at least one first OD region contact element, each first OD region contact element electrically coupled to a corresponding
first OD region of the at least one GAA device; and

at least one second OD region contact element, each second OD region contact element electrically coupled to a corresponding
second OD region of the at least one GAA device; and

the first GAA structure and the second GAA structure have substantially a same of at least one of the following features:
a number of GAA devices in the at least one GAA device configured to have current flows from the first OD region to the second
OD region;

a number of GAA devices in the at least one GAA device configured to have current flows from the second OD region to the first
OD region;

a number of integral first OD region of the at least one GAA device;
a number of integral second OD region of the at least one GAA device;
an orientation of and a corresponding direction of current flow through the first GAA structure or the second GAA structure;
a number of the at least one first OD region contact element;
an orientation of the at least one first OD region contact element;
a number of the at least one second OD region contact element;
an orientation of the at least one second OD region contact element;
a number of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure;
a number of rows of the at least one nanowire arranged in an array for each corresponding GAA devices of the first GAA structure
and the second GAA structure;

a number of nanowires in a row of the at least one nanowire arranged in the array for each corresponding GAA devices of the
first GAA structure and the second GAA structure;

a number of columns of the at least one nanowire arranged in the array for each corresponding GAA devices of the first GAA
structure and the second GAA structure;

a number of nanowires in a column of the at least one nanowire arranged in the array for each corresponding GAA devices of
the first GAA structure and the second GAA structure; and

a shape of the at least one nanowire for each corresponding GAA devices of the first GAA structure and the second GAA structure.

US Pat. No. 9,059,259

HARD MASK FOR BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

1. A method of fabricating an interconnect structure on a wafer, the method comprising:
providing a dielectric layer on the wafer;
forming an interconnect by-etching a recess into the dielectric layer, the etching utilizing a hard mask that includes a first
layer deposited on the dielectric layer;

planarizing the interconnect and the hard mask using a chemical mechanical polishing (CMP) process, wherein the first layer
of the hard mask substantially remains on the dielectric layer at a completion of the CMP process; and

performing a converting process by selectively converting at least a portion of the first layer into at least one of a nitride-containing
layer and an oxide-containing layer after the CMP process.

US Pat. No. 9,472,545

SEMICONDUCTOR ARRANGEMENT WITH ELECTROSTATIC DISCHARGE (ESD) PROTECTION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first substrate comprising:
a first PMOS device comprising a first source/drain region coupled to a first power supply supplying a first voltage; and
a first NMOS device comprising a first source/drain region coupled to a second power supply supplying a second voltage different
than the first voltage;

a second substrate comprising:
a first device coupled to a second source/drain region of the first PMOS device; and
a second device coupled to a second source/drain region of the first NMOS device;
an electrostatic discharge (ESD) pad coupled between the first device and the second device, wherein there is no current path
between the ESD pad and a gate of the first PMOS device or a gate of the first NMOS device; and

a first interlayer via coupling the first substrate and the second substrate.

US Pat. No. 9,368,487

SEMICONDUCTOR DEVICE WITH DYNAMIC LOW VOLTAGE TRIGGERING MECHANISM

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a substrate of a first dopant type;
a well region of the first dopant type disposed in the substrate; and
a depletion inducing structure of a second dopant type having a gap defined therein at least partially arranged in the well
region;

wherein the well region is connected to the substrate through the gap in the depletion inducing structure.

US Pat. No. 9,331,075

SYSTEMS AND METHODS FOR FABRICATING SEMICONDUCTOR DEVICES AT DIFFERENT LEVELS

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a substrate including a first region and a second region;
a first semiconductor device structure formed on the first region;
a semiconductor fin grown in the second region; and
a second semiconductor device structure formed on the semiconductor fin, wherein a top surface of the semiconductor fin is
higher than a top surface of the first semiconductor device structure.

US Pat. No. 9,331,018

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first active area output in a substrate adjacent an active area input;
a second active area output in the substrate adjacent the first active area output; and
a power divider comprising a transmission line and a resistor, the transmission line over the active area input, the first
active area output and the second active area output, the transmission line connected to the active area input, the first
active area output and the second active area output.

US Pat. No. 9,305,851

SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH FLUORESCENCE DETECTION

Taiwan Semiconductor Manu...

9. A method comprising:
providing an incident light;
performing a chemical-mechanical planarization (CMP) on an article using a polishing fluid, the polishing fluid including
a plurality of emitter particles that are capable of emitting a fluorescent light in response to an incident light and a plurality
of surfactant particles that attach the emitter particles, wherein the surfactant particles are capable of detaching from
the emitter particles and attaching to a CMP stop material of the article when the CMP stop material is exposed to the polishing
fluid;

detecting the fluorescent light; and
adjusting the performing of the CMP in response to the detected fluorescent light, wherein the fluorescent light is detected
to have a first intensity when the surfactant particles attach the emitter particles and the fluorescent light is detected
to have a second intensity when the surfactant particles detach the emitter particles.

US Pat. No. 9,276,084

TRANSISTOR AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A transistor, comprising:
a channel layer over a substrate, having a recess;
a source layer comprising highly doped III-V compounds in the recess; and
a barrier layer between the channel layer and the substrate,
wherein the recess extends from the channel layer into the barrier layer,
wherein a depth between a bottom surface of the channel layer and a base of the recess is more than about 1.4 times a width
of a section of the recess intersecting the bottom surface of the channel layer, wherein a defect starting from the base of
the recess does not extend above the bottom surface of the channel layer if the defect exists in the source.

US Pat. No. 9,147,767

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a silicide region on the substrate;
disposing a first dielectric on the substrate;
forming a metal gate structure on the substrate;
disposing a second dielectric over the metal gate structure and the substrate;
performing a first etch in the second dielectric thereby forming a first opening to expose a top surface of a metallic material
in the metal gate structure;

performing a second etch in the first dielectric thereby forming a second opening to expose the silicide region of the substrate;
and

performing a wet etch in the first opening to remove a portion of the metallic material from the top surface thereby forming
a lateral recess under the second dielectric.

US Pat. No. 9,378,990

ADJUSTING INTENSITY OF LASER BEAM DURING LASER OPERATION ON A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A system for treating a semiconductor device, comprising:
a laser configured to emit a laser beam that performs an anneal operation on the semiconductor device;
a sensor configured to measure a reflection intensity of the laser beam, the reflection intensity indicative of a magnitude
at which the laser beam is reflected from the semiconductor device; and

a controller configured to control thermal absorption of the laser beam by the semiconductor device by adjusting an applied
intensity of the laser beam as a function of the reflection intensity and a specified thermal absorption rate for the anneal
operation, the applied intensity indicative of a magnitude at which the laser beam is emitted from the laser.

US Pat. No. 9,362,385

METHOD FOR TUNING THRESHOLD VOLTAGE OF SEMICONDUCTOR DEVICE WITH METAL GATE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for tuning a threshold voltage of a semiconductor device with a metal gate structure, comprising:
forming a high-k dielectric layer in a gate trench;
forming an etch stop over the high-k dielectric layer;
forming a work function adjusting layer over the etch stop by forming a tri-layer with a sequence of a grain boundary engineering
layer configured to allow a dopant atom to penetrate there through, a doping layer configured to provide the dopant atom to
the grain boundary engineering layer, and a capping layer configured to prevent the doping layer from oxidation; and

filling a metal in the gate trench,
wherein a degree of penetration of the dopant atom is controlled by adjusting a growth temperature within a range of from
about 200 to about 350 degrees Celsius during forming the grain boundary engineering layer.

US Pat. No. 9,310,332

SEMICONDUCTOR DEVICE AND SELECTIVE HEATING THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
an ion sensing device, comprising:
an active region comprising a source, a drain and a channel situated between the source and the drain;
a gate situated over a first surface of the active region;
an ion sensing film situated over a second surface of the active region diametrically opposing the first surface; and
an ion sensing region situated over the ion sensing film, wherein the active region and the gate are embedded within a dielectric
layer; and

a heating element proximate the ion sensing device.

US Pat. No. 9,286,973

DEVICE AND METHOD FOR FORMING RESISTIVE RANDOM ACCESS MEMORY CELL

Taiwan Semiconductor Manu...

1. A method for forming a resistive random access memory (RRAM) cell, comprising:
providing a first voltage to a first word line connected to a first RRAM cell to form the first RRAM cell; and
providing a negative voltage to a second word line connected to a second RRAM cell that shares a first source line and a first
bit line with the first RRAM cell during the formation of the first RRAM cell.

US Pat. No. 9,184,289

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device, comprising:
forming an active region adjacent a channel of the semiconductor device, comprising:
implanting a first dopant adjacent the channel to form a doped region;
increasing, after the implanting, a temperature from a first temperature to a second temperature while applying a protective
agent to the doped region, and increasing the temperature from the second temperature to a third temperature while applying
the protective agent to the doped region and while exposing the doped region to a second dopant and a growth agent to form
a growth region over the doped region; and

annealing the doped region and the growth region to activate a dopant within the doped region and to form a first repaired
lattice structure in the doped region to form a repaired doped region, the annealing performed while applying the protective
agent to the doped region and to the growth region and while exposing the doped region and the growth region to the second
dopant and the growth agent at the third temperature, the active region comprising the repaired doped region and the growth
region over the repaired doped region.

US Pat. No. 9,306,012

STRIP-GROUND FIELD PLATE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a channel between a source region and a drain region of a semiconductor device;
a gate region formed over the channel, the channel comprising an access region formed between the gate region and the drain
region;

a strip-ground field plate formed over the access region, the strip-ground field plate connected to at least one of the source
region or a ground plane;

a first dielectric layer formed between the strip-ground field plate and the access region;
a second dielectric layer formed over the gate region and the strip-ground field plate; and
a source field plate formed over the second dielectric layer.

US Pat. No. 9,299,784

SEMICONDUCTOR DEVICE WITH NON-LINEAR SURFACE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a first channel disposed over a substrate and having a first linear surface and a first non-linear surface, wherein the first
non-linear surface defines a first angle relative to the first linear surface and a second angle relative to a second linear
surface of the first channel, the first angle about 40 degrees to about 50 degrees, the second angle about 40 degrees to about
50 degrees;

a first dielectric region surrounding the first channel;
a second channel disposed over the first channel and having a third linear surface and a third non-linear surface;
a second dielectric region surrounding the second channel; and
a gate electrode surrounding the first dielectric region and the second dielectric region.

US Pat. No. 9,369,313

PRE-AMPLIFIER AND A DECISION FEEDBACK EQUALIZER USING THE SAME FOR REDUCING TAP WEIGHT VARIATIONS

Global Unichip Corp., Hs...

1. A pre-amplifier circuit, comprising:
a first differential amplifier having a first output node and a second output node, the first differential amplifier comprising
a first differential transistor pair configured to provide a first differential current signal at the first output node and
the second output node in accordance with a first pair of differential signals coupled to two control terminals of the first
differential transistor pair, respectively, wherein the first differential transistor pair is biased by a first current source;
and

a second differential amplifier having a third output node and a fourth output node, the second differential amplifier comprising
a second differential transistor pair configured to provide a second differential current signal at the third output node
and the fourth output node in accordance with a voltage difference between two control terminals of the second differential
transistor pair, wherein the second differential transistor pair is biased by a second current source, and at least one adjustable
reference voltage circuit is coupled to at least one of the two control terminals of the second differential transistor pair
to generate the voltage difference between the two control terminals of the second differential transistor pair;

wherein the first output node and the third output node are coupled at a fifth output node and the second output node and
the fourth output node are coupled at a sixth output node, wherein the fifth output node is coupled to a first supply voltage
via a first resistive element and the sixth output node is coupled to a second supply voltage via a second resistive element.

US Pat. No. 9,325,318

POST DRIVER

TAIWAN SEMICONDUCTOR MANU...

1. A post driver, comprising:
a source follower including an input to receive a first voltage from a pad, and an output to provide a second voltage; and
a first sub-unit, comprising:
a first transistor coupled between the pad and a first power rail, the first transistor configured to operate in a sub-threshold
region in response to the second voltage and a first range of the first voltage; and

a second transistor coupled in parallel with the first transistor between the pad and the first power rail, the second transistor
configured to electrically connect the pad to the first power rail in response to a second range of the first voltage.

US Pat. No. 9,299,657

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

11. A semiconductor device, comprising:
a first conductive portion over a substrate;
a second conductive portion over the substrate;
a third conductive portion over the substrate;
a dielectric layer over the first conductive portion
a first high-resistance portion over the dielectric layer; and
a first plug portion over the first high-resistance portion, the second conductive portion, and the third conductive portion,
wherein the first plug portion electrically connects the second conductive portion and the third conductive portion,

wherein the first high-resistance portion comprises a titanium nitride layer or an aluminum nitride layer.

US Pat. No. 9,343,151

RESISTIVE RANDOM ACCESS MEMORY AND METHOD OF RESETTING A RESISTIVE RANDOM ACCESS MEMORY

Taiwan Semiconductor Manu...

1. A resistive random access memory (RRAM), comprising:
a resistor comprising a cap side electrode and a dielectric side electrode;
a transistor, a drain of the transistor electrically connected to the dielectric side electrode;
a first voltage source electrically connected to a source of the transistor; and
a second voltage source electrically connected to a gate of the transistor, wherein for a reset operation comprising at least
two loops, the first voltage source provides a lower voltage in a second loop than the first voltage source does in a first
loop, and the second voltage source provides a higher voltage in the second loop than the second voltage source does in the
first loop.

US Pat. No. 9,291,890

METHOD FOR REPAIRING A MASK

Taiwan Semiconductor Manu...

1. A method for repairing a mask, comprising:
receiving a mask having first and second defective regions;
performing a first pre-repair-passivation-treatment (PRPT) to form a first passivation membrane over the mask;
after forming the first passivation membrane, performing a first repair process on the mask, wherein the first defective region
is repaired to form a first repaired defective region;

performing a second PRPT to form a second passivation membrane over the mask, including the first repaired defective region;
and

after forming the second passivation membrane, performing a second repair process on the mask, wherein the second defective
region is repaired to form a second repaired defective region.

US Pat. No. 9,276,117

STRUCTURE AND METHOD AND FINFET DEVICE

Taiwan Semiconductor Manu...

1. A device comprising:
a strain-relaxed buffer (SRB) stack over a substrate, the SRB stack including:
a first SRB layer over the substrate;
a dislocation-trap (DisT) layer disposed over the first SRB layer; and
a second SRB layer disposed over the DisT layer;
a first fin structure disposed over the SRB stack, the first fin structure including:
a portion of the second SRB layer;
a first semiconductor material layer disposed over the portion of the second SRB layer; and
a second semiconductor material layer disposed over the first semiconductor material layer; and
a liner layer extending along the portion of the second SRB layer and the first semiconductor material layer of the first
fin structure.

US Pat. No. 9,176,388

MULTI-LINE WIDTH PATTERN CREATED USING PHOTOLITHOGRAPHY

Taiwan Semiconductor Manu...

19. A method comprising:
forming a polymer layer over a substrate;
patterning the polymer layer to form a first feature and a second feature, the first feature and the second feature being
separated at a first distance;

applying a rinse material to the polymer layer including the first feature and the second feature;
removing the rinse material from the polymer layer including the first feature and the second feature to cause the first feature
and the second feature to come into contact with each other; and

forming a third feature based on the first feature and the second feature being in contact with each other,
wherein the patterning the polymer layer to form the first feature and the second feature includes: patterning the polymer
layer to form a fourth feature and a fifth feature, the fourth feature and the fifth feature being separated at a second distance
larger than the first distance.

US Pat. No. 9,087,773

IMPLANT REGION DEFINITION

Taiwan Semiconductor Manu...

1. A method for defining one or more implant regions, comprising:
applying a first implant mask to a semiconductor arrangement, the first implant mask covering a first active region and a
second active region, the first implant mask defining a first implant region corresponding to the first active region; and

applying a second implant mask to the semiconductor arrangement, the second implant mask covering a third active region and
the second active region, the second implant mask and the first implant mask defining a second implant region corresponding
to an overlap between the first implant mask and the second implant mask over the second active region, the second implant
mask defining a third implant region corresponding to the third active region.

US Pat. No. 9,576,910

SEMICONDUCTOR PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:
a plurality of devices;
a molding surrounding the plurality of devices and including a first surface adjacent to an active component of at least one
of the plurality of devices and a second surface opposite to the first surface; and

a shielding structure disposed within the molding and between two or more of the plurality of devices;
wherein the shielding structure includes a first surface adjacent to the first surface of the molding and a second surface
adjacent to the second surface of the molding, and the second surface of the shielding structure includes a recessed portion
recessed towards the first surface of the molding, and

a metallic coating disposed over the molding and the shielding structure, wherein the metallic coating extends substantially
conformally and continuously within the recessed portion of the second surface of the shielding structure.

US Pat. No. 9,304,959

METHOD OF OPTIMIZING THE WIDTH OF TRANSACTION ID FOR AN INTERCONNECTING BUS

Global Unichip Corp., Hs...

1. A method of generating transaction ID(s) for an interconnecting bus, comprising the steps of:
(a) providing a plurality of masters and a plurality of slaves, wherein the plurality of masters and the plurality of slaves
are connected through the interconnecting bus;

(b) for each slave of the plurality of slaves, generating a transaction ID for each transaction received by the slave, comprising
the sub-steps of:

b1. determining a total number of transactions which are to be received by the slave from the plurality of masters;
b2. determining the smallest integer n such that 2n is greater than or equal to the total number of transactions;

b3. assigning each transaction of the total number of transactions a unique transaction ID to identify the transaction, respectively,
wherein each of the assigned transaction ID is an integer and selected from the range: zero to (2n?1).

US Pat. No. 9,275,925

SYSTEM AND METHOD FOR AN IMPROVED INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

1. An interconnect structure, comprising:
a connector disposed over a substrate and at a second level below a first level, the substrate having a major surface;
an insulating layer disposed over the substrate and over the connector;
a mounting pad disposed over the insulating layer and at the first level, the mounting pad electrically connected to the connector;
a trace disposed over the insulating layer and at the first level and having a major axis extending in a direction parallel
to the major surface of the substrate, the trace electrically connected to the connector and electrically connected to the
mounting pad by way of the connector, the trace spaced apart from the mounting pad in a direction parallel to the major surface
of the substrate;

a contact pad disposed over the substrate and at the second level, the contact pad electrically connected to and in physical
contact with the trace; and

a mounting structure disposed on the mounting pad.

US Pat. No. 9,095,995

METHOD OF FORMING MULTIPLE PATTERNING SPACER STRUCTURES

Taiwan Semiconductor Manu...

1. A method of forming a structure, comprising:
forming a mandrel layer over a substrate;
etching the mandrel layer at least once with a polymerizing etchant, the polymerizing etchant forming a protective layer on
an exposed portion of the substrate during the etching;

forming one or more spacers on sidewalls of the mandrel layer; and
etching the substrate using the one or more spacers as a mask.

US Pat. No. 9,379,220

FINFET DEVICE STRUCTURE AND METHODS OF MAKING SAME

Taiwan Semiconductor Manu...

1. A method comprising:
forming mandrels on a substrate;
conformally depositing a first dielectric layer on the mandrels, the first dielectric layer having horizontal portions on
upper surfaces of the mandrels and vertical portions on sidewall surfaces of the mandrels;

forming a second dielectric layer on the first dielectric layer by treating the first dielectric layer; and
etching the second dielectric layer and the horizontal portions of the first dielectric layer, the etching removing the horizontal
portions of the first dielectric layer, the vertical portions of the first dielectric layer remaining after the etching to
form a pattern.

US Pat. No. 9,292,645

LAYOUT OPTIMIZATION FOR INTEGRATED CIRCUIT DESIGN

Taiwan Semiconductor Manu...

1. A method for laying out a target pattern, the method comprising:
positioning a first feature in a main pattern, the first feature including a first end and a first cut pattern;
assigning a keep-out zone to an end of the first feature and the first cut pattern, the keep-out zone defining a region in
which other features of the main pattern are permitted to pass through and in which corners of the other features are prohibited;

positioning a second feature in the target pattern such that a second end of the second feature does not lie within the keep-out
zone;

determining that an end of a third feature within the target pattern is within the keep-out zone; and
modifying the target pattern such that the end of the third feature is not within the keep-out zone.

US Pat. No. 9,280,041

CROSS QUADRUPOLE DOUBLE LITHOGRAPHY METHOD USING TWO COMPLEMENTARY APERTURES

Taiwan Semiconductor Manu...

10. A method for semiconductor device fabrication, comprising:
providing a first metal aperture, having a first pair of radiation-transmitting regions positioned along a first diametrical
axis, and having a second pair of radiation-transmitting regions positioned along a second diametrical axis substantially
perpendicular to the first diametrical axis, wherein the first pair of radiation-transmitting regions have a greater open
angle than the second pair of radiation-transmitting regions, wherein each radiation-transmitting region of the first and
second pairs has a shape filled with a first material and defined by four edges, the four edges including a first linear edge
and an opposing second linear edge, and a third edge having a curvature and an opposing fourth edge having a curvature, the
fourth edge being shorter than the third edge;

using an imaging system, directing a radiation beam through a photomask and through the first metal aperture to expose a first
pattern onto a layer of a target substrate, wherein the first pattern has horizontally oriented line features, wherein the
first pattern is defined by the photomask and wherein directing the radiation beam through the first and second pairs of radiation-transmitting
regions of the first metal aperture does not change a polarization of the radiation beam;

automatically replacing the first metal aperture with a second metal aperture, having a third pair of radiation-transmitting
regions positioned along the first diametrical axis, and having a fourth pair of radiation-transmitting regions positioned
along the second diametrical axis, wherein the fourth pair of radiation-transmitting regions has a greater open angle than
the third pair of radiation-transmitting regions, wherein each radiation-transmitting region of the third and fourth pairs
has a shape defined by four edges, the four edges including a first linear edge and an opposing second linear edge, and a
third edge having a curvature and an opposing fourth edge having a curvature, the fourth edge being shorter than the third
edge, and wherein the first and second metal apertures are interchangeable in the imaging system; and

directing a second radiation beam through the photomask and through the second metal aperture to expose a second pattern onto
the layer of the target substrate, wherein the second pattern is defined by the photomask and wherein the second pattern has
vertically oriented line features and wherein directing the radiation beam through the third and fourth pairs of radiation-transmitting
regions of the second metal aperture does not change a polarization of the radiation beam; and

using an aggregate of the first pattern and the second pattern as a masking element to etch a feature on the substrate.

US Pat. No. 9,368,394

DRY ETCHING GAS AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming a conductive region at least partially in the semiconductor substrate;
forming a dielectric layer over the substrate;
forming a hard mask over the dielectric layer, the hard mask having an opening over the conductive region;
dry etching the dielectric layer by a first etching gas to form a recessed feature, wherein a surface of the conductive region
is therefore exposed at a bottom of the recessed feature, and a byproduct film is formed at an inner surface of the recessed
feature; and

dry etching the dielectric layer by a second etching gas, wherein the second etching gas chemically reacts with the byproduct
film and the conductive region, and a sacrificial layer is therefore built up around the bottom of the recessed feature.

US Pat. No. 9,324,587

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:
providing a substrate including a first surface and a second surface;
heating the substrate and a transparent film to attach the transparent film on the first surface, wherein a first coefficient
of a thermal expansion (CTE) mismatch is between the substrate and the transparent film;

cooling the substrate and the transparent film; and
disposing a polymeric material on the second surface, wherein a second CTE mismatch is between the substrate and the polymeric
material and the second CTE mismatch is counteracted by the first CTE mismatch.

US Pat. No. 9,287,385

MULTI-FIN DEVICE AND METHOD OF MAKING SAME

Taiwan Semiconductor Manu...

1. A device comprising:
a substrate;
a plurality of fins formed on the substrate, each fin of the plurality of fins having a sidewall, an upper portion of the
sidewall being substantially orthogonal to a major surface of the substrate, and a lower portion of the sidewall being non-orthogonal
to the major surface of the substrate;

source and drain regions formed in each fin of the plurality of fins;
a dielectric layer formed on the substrate, the dielectric layer having a first region having a first thickness, the first
region having a top surface extending to a top surface of a first fin of the plurality of fins, the first region adjacent
one side of the first fin and the dielectric layer further having a second region having a second thickness, different from
the first thickness, adjacent an opposite side of the first fin, the second region having a top surface below the top surface
of the first region;

a continuous gate structure overlying the plurality of fins, the continuous gate structure being adjacent a top surface of
each fin, including the top surface of the first fin, and at least one sidewall surface of at least one fin; and

a first continuous metal layer overlying the source regions of each of the plurality of fins and forming a single source region
of a single transistor that comprises the plurality of fins.

US Pat. No. 9,281,254

METHODS OF FORMING INTEGRATED CIRCUIT PACKAGE

Taiwan Semiconductor Manu...

1. A method for forming integrated circuit packages, the method comprising:
mounting a plurality of first tier stacks to a substrate, wherein the substrate has one or more contact pads corresponding
to each of the first tier stacks and has one or more probing pads associated with each of the first tier stacks;

electrically testing each of the first tier stacks and identifying known good first tier stacks and known bad first tier stacks;
mounting a first plurality of stacking substrates to the known good first tier stacks, thereby forming a plurality of second
tier stacks; and

electrically testing each of the second tier stacks, and identifying known good second tier stacks and known bad second tier
stacks.

US Pat. No. 9,244,118

TESTING SYSTEM WITH AN ISOLATED SWITCHING MODULE

Global Unichip Corp., Hs...

1. A system for testing a DUT having a first ground and a plurality of I/O pins, comprising:
a switching module having a second ground, comprising a conductive path configured to conduct a first pin out of the plurality
of I/O pins of the DUT to a second pin of the switching module;

a tester having a third ground, connected to the conductive path;
a first rectifying device having a first positive terminal and a first negative terminal;
a second rectifying device having a second positive terminal and a second negative terminal, wherein the second positive terminal
is electrically coupled to the first ground of the DUT; and the second negative terminal is electrically coupled to the first
pin of the DUT; and

a third rectifying device having a third positive terminal and a third negative terminal, wherein the third positive terminal
is electrically coupled to the second ground of the switching module; and the third negative terminal is electrically coupled
to the second pin of the switching module,

wherein the first ground of the DUT and the third ground of the tester are electrically coupled to each other; the first positive
terminal of the first rectifying device is electrically coupled to the second ground of the switching module; and the first
negative terminal of the first rectifying device is electrically coupled to the first ground of the DUT, wherein the first
ground of the DUT and the second ground of the switching module are separated by the first rectifying device.

US Pat. No. 9,419,114

TUNNEL FIELD-EFFECT TRANSISTOR

IMEC VZW, Leuven (BE) Ta...

1. A tunnel field-effect transistor device, comprising:
a semiconductor substrate;
a fin structure contacting the semiconductor substrate on a major surface of the semiconductor substrate, wherein the fin
structure is an elevated structure with respect to the semiconductor substrate, wherein the fin structure has a height measured
in a direction orthogonal to the major surface of the semiconductor substrate, wherein the fin structure has a length measured
in a longitudinal direction parallel to the major surface, wherein the fin structure has a width measured in a direction orthogonal
to both the direction of the height and the longitudinal direction, the fin structure comprising a channel region, a drain
region, and a source region, wherein the source region is disposed on the channel region, wherein the source region comprises
a gate interface portion wherein the channel region is disposed on the drain region, and wherein the source region and the
drain region are of opposite conductivity type;

a pocket layer covering the gate interface portion of the source region, the pocket layer contacting at least part of the
channel region, wherein the gate interface portion of the source region comprises at least three mutually non-coplanar surface
segments;

a gate dielectric layer covering the pocket layer, the gate dielectric layer electrically isolating the gate electrode and
the source region: and

a gate electrode covering the gate dielectric layer, wherein the gate electrode is substantially parallel to the at least
three non-coplanar surface segments, wherein the pocket layer comprises an intrinsic semiconductor material or is doped with
a species opposite a conductivity type of the source region, wherein the pocket layer is configured to capture charge carriers
tunneling from the source region in a direction of the gate electrode, and wherein the pocket layer is configured to divert
the charge carriers via the channel region to a portion of the drain region which is in contact with the channel region but
which is electrically insulated from the source region.

US Pat. No. 9,331,066

METHOD AND COMPUTER-READABLE MEDIUM FOR DETECTING PARASITIC TRANSISTORS BY UTILIZING EQUIVALENT CIRCUIT AND THRESHOLD DISTANCE

TAIWAN SEMICONDUCTOR MANU...

1. A method of detecting a parasitic transistor, the method comprising:
using a computer to convert a layout of a selected area to an equivalent circuit having a plurality of diodes;
tracing signals coupled to the diodes to determine at least one diode pair from the diodes; and
filtering the at least one diode pair in accordance with a threshold distance to determine whether at least one parasitic
transistor is obtained;

wherein each diode pair comprises two diodes coupled, and has a common terminal and two I/O terminals, wherein the two I/O
terminals are coupled to different I/O signals, and the at least one diode pair is filtered by comparing a minimum distance
between the two I/O terminals of the diode pair and the threshold distance, and if the minimum distance is smaller than the
threshold distance, the parasitic transistor comprising the diode pair is obtained.

US Pat. No. 9,202,792

STRUCTURE AND METHOD OF PROVIDING A RE-DISTRIBUTION LAYER (RDL) AND A THROUGH-SILICON VIA (TSV)

Taiwan Semiconductor Manu...

1. A method of providing a redistribution layer (RDL) and a through-silicon via (TSV) for a semiconductor package, the method
comprising:
preparing a wafer for bonding to a semiconductor package, the wafer comprising a low resistance substrate containing the RDL
and the TSV for making an input/output (I/O) connection point of the semiconductor package available at another location,
wherein the RDL comprises a conduction path through the low resistance substrate that is bounded on two sides by an isolation
trench, and wherein the TSV is bounded by the isolation trench and the RDL; and

bonding the wafer to the semiconductor package.

US Pat. No. 9,064,873

SINGULATED SEMICONDUCTOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A singulated semiconductor structure, comprising:
a molding compound;
a first conductive post in the molding compound having a first geometric shape in a top view;
a second conductive post in the molding compound having a second geometric shape in a top view, wherein the second geometric
shape is different from the first geometric shape.

US Pat. No. 9,385,156

METHOD OF MANUFACTURING A BACK SIDE ILLUMINATED (BSI) IMAGE SENSOR

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a back side illuminated (BSI) image sensor, comprising:
receiving a semiconductive substrate;
forming a transistor coupled to a photosensitive element at a front side of the semiconductive substrate;
forming a deep trench isolation (DTI) at a back side of the semiconductive substrate;
forming a doped layer conformally over the DTI;
performing a microwave anneal over the back side;
forming a non-transparent material inside the DTI; and
forming a color filter over the doped layer;
wherein the operation of performing the microwave anneal includes forming the doped layer to a predetermined vertical thickness.

US Pat. No. 9,244,122

METHOD OF DETERMINING PERFORMANCE OF A CHIP OF AN INTEGRATED-CIRCUIT DESIGN AND AN APPARATUS AND AN INTEGRATED CIRCUIT USING THE SAME

Global Unichip Corp., Hs...

1. An apparatus for determining the performance of an integrated circuit, comprising:
a plurality of HPM(s) (hardware performance monitor) in the integrated circuit, wherein each HPM generates a value for generating
the performance of the integrated circuit;

a storage unit for storing a plurality of coefficients of a polynomial that defines a performance function of the integrated
circuit, wherein each term of the polynomial comprises a corresponding one of the plurality of coefficients and an exponent
of a value generated by a corresponding one of the plurality of HPM(s); and

a BIST module for determining the performance of the integrated circuit by obtaining a value of the performance function according
to the values of the HPM(s) in the integrated circuit and the plurality of coefficients in the storage unit.

US Pat. No. 9,712,145

DELAY LINE CIRCUIT WITH VARIABLE DELAY LINE UNIT

TAIWAN SEMICONDUCTOR MANU...

1. A delay line circuit comprising:
a plurality of delay circuits configured to receive an input signal and to generate a first output signal, the first output
signal corresponding to a delayed input signal or an inverted input signal; and

a variable delay line circuit configured to receive the first output signal, the variable delay line circuit comprising:
an input end configured to receive the first output signal;
an output end configured to output a second output signal;
a first path between the input end and the output end, the first path comprising a first plurality of inverters and a first
circuit; and

a second path between the input end and the output end, the second path comprising a second plurality of inverters and a second
circuit,

wherein the received first output signal is selectively transmitted through one of the first path or the second path based
on a control signal received from a delay line controller.

US Pat. No. 9,406,588

SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:
a first redistribution layer (RDL), comprising at least one pattern electrically isolated from any component of the semiconductor
structure;

a semiconductor die over the first RDL, at least one contact pad being positioned on a front side of the semiconductor die;
an adhesive layer between a back side of the semiconductor die and the first RDL, the back side is opposite to the front side;
and

a molding compound, encapsulating the first RDL, the semiconductor die, and the adhesive layer, and
a through package via (TPV) penetrating the molding compound and electrically connecting the front side and the first RDL.

US Pat. No. 9,406,629

SEMICONDUCTOR PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor package structure, comprising:
a first semiconductor substrate comprising a conductive pad, the conductive pad comprises a plurality of recesses,
wherein the conductive pad is coupled with a circuitry of the first semiconductor substrate;
a conductive pillar on the conductive pad and disposed between the first semiconductor substrate and a second semiconductor
substrate, wherein the conductive pillar: extends along a longitudinal axis and toward the second semiconductor substrate,
and includes a sidewall with a rough surface notching toward the longitudinal axis, and wherein the rough surface comprises
a width greater than about 2 ?m, and

wherein a bottom surface of the conductive pillar interfaces with the plurality of recesses of the conductive pad.

US Pat. No. 9,349,610

ASSEMBLY STRUCTURE FOR CONNECTING MULTIPLE DIES INTO A SYSTEM-IN-PACKAGE CHIP AND THE METHOD THEREOF

Global Unichip Corp., Hs...

1. A method for assembling multiple integrated circuit dies into a system-in-package chip, the method comprising:
(a) providing a plurality of integrated circuit dies;
(b) disposing at least one redistribution layer on at least one of the plurality of integrated circuit dies for making wire
connections among the plurality of integrated circuit dies without using a substrate underneath the plurality of integrated
circuit dies;

(c) establishing wire connections among the plurality of integrated circuit dies and verifying the plurality of wire connections;
and

(d) packaging the plurality of integrated circuit dies and the verified wire connections into a system-in-package chip.

US Pat. No. 9,331,081

SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:
forming a first mask on a substrate;
defining a first doped region through an opening of the first mask;
forming a second mask on the first mask and filling in the opening of the first mask with the second mask;
defining a second doped region through an opening of the second mask, the opening of the second mask simultaneously exposing
the underlying first mask; and

stripping the first mask and the second mask from the substrate.

US Pat. No. 9,735,129

SEMICONDUCTOR PACKAGES AND METHODS OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method comprising:
forming a first redistribution layer over a first carrier substrate, the first redistribution layer having a first side, the
first side having a first area and a second area surrounding the first area;

forming an alignment structure on the first side of the first redistribution layer in the second area;
forming an electrical connector on the first side of the first redistribution layer in the second area;
after forming the alignment structure and the electrical connector, aligning a first die over the first side of the first
redistribution layer in the first area using the alignment structure as an alignment mark, the alignment structure being located
at a first distance from the first die, the electrical connector being located at a second distance from the first die, the
second distance being greater than the first distance;

bonding the first die to the first side of the first redistribution layer in the first area;
forming a second redistribution layer; and
after forming the second redistribution layer, bonding the second redistribution layer to the first die using a set of bonding
structures to form a set of bonding joints, at least one of the set of bonding joints being bonded to the first die.

US Pat. No. 9,367,660

ELECTROMIGRATION-AWARE LAYOUT GENERATION

TAIWAN SEMICONDUCTOR MANU...

1. A method, performed by at least one processor, comprising:
receiving, by the at least one processor, cell layouts of a plurality of cells; and
for each cell of the plurality of cells and with respect to each first geometric characteristic of a plurality of first geometric
characteristics considered for a first interconnect coupled to an output pin of the cell in the cell layout,

obtaining, by the at least one processor, a respective relationship of a plurality of pairs of second geometric characteristic
and output behaviors,

each second geometric characteristic and each output behavior of the plurality of pairs of second geometric characteristic
and output behavior being considered for the first interconnect and being of the cell, respectively, and

the first geometric characteristic being orthogonal to each second geometric characteristic of the plurality of pairs of second
geometric characteristic and output behavior;

determining, by the at least one processor, respective electromigration susceptibility (EMS) of the first interconnect having
the first geometric characteristic; and

determining, by the at least one processor, a respective geometric constraint of the first interconnect using a first pair
of second geometric characteristic and output behavior in the respective relationship,

the output behavior in the first pair of second geometric characteristic and output behavior causing the respective EMS of
the first interconnect.

US Pat. No. 9,269,675

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device, comprising:
providing a carrier including a substrate layer, a second layer, a first surface of the substrate layer and a second surface
of the second layer;

disposing a plurality of solder bumps on the second surface;
disposing a molding on the second surface and between the plurality of solder bumps;
cutting the substrate layer from the first surface to form a first recess in the substrate layer, wherein the first recess
is above a position between at least two of the plurality of solder bumps; and

cutting the molding from a bottom surface of the first recess to form a second recess in the molding between the at least
two of the plurality of solder bumps.

US Pat. No. 9,263,542

SEMICONDUCTOR DEVICE HAVING A CHARGED INSULATING LAYER

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:
a substrate;
an active layer over the substrate; and
an insulating layer between the substrate and the active layer, the insulating layer being doped with one of positive charge
and negative charge and configured to establish an electric field across the active layer when the semiconductor device is
powered;

wherein the active layer includes a source region, a drain region, and a channel region between the source region and the
drain region; and

wherein the source and drain regions have a same dopant type as the insulating layer, and the channel region has a different
dopant type from the insulating layer.

US Pat. No. 9,406,499

SEMICONDUCTOR WAFER STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor structure, comprising:
a first wafer including a plurality of protrusions protruded from and elongated across the first wafer;
a second wafer including a second surface attached with the plurality of protrusions,
wherein a plurality of passages are intervally configured between the plurality of protrusions and elongated across the first
wafer and the second surface of the second wafer.

US Pat. No. 9,330,731

CIRCUITS IN STRAP CELL REGIONS

TAIWAN SEMICONDUCTOR MANU...

1. A circuit, comprising:
a first transistor in a strap cell region between a first memory array and a second memory array of a memory device, the first
transistor including a first node connected to a first data line, and a second node connected to a second data line, the first
node and the second node of the first transistor being complementary to each other in voltage level;

a second transistor, in the strap cell region, including a first node connected to the second data line, and a second node
connected to the first data line, the first node and the second node of the second transistor being complementary to each
other in voltage level;

an access transistor biased at a controlled voltage, the access transistor including a first terminal connected to the second
data line; and

a third transistor including a gate connected to the first data line, and a terminal connected to a second terminal of the
access transistor.

US Pat. No. 9,407,184

ENERGY HARVESTING DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. An energy harvesting device, comprising:
a semiconductor device, disposed in a housing, comprising:
first sensors; and
second sensors;
a first magnet core, disposed over the semiconductor device, configured to establish a magnetic field for interaction with
the first sensors in a direction and move with respect to the semiconductor device in the direction; and

a second magnet core configured to establish another magnetic field for interaction with the second sensors in another direction
and move with respect to the semiconductor device in the other direction.

US Pat. No. 9,369,134

PLL WITH ACROSS-STAGE CONTROLLED DCO

TAIWAN SEMICONDUCTOR MANU...

1. A phase lock loop (PLL), comprising:
an across-stage digital controlled oscillator (DCO) controller comprising:
a first detector configured to receive a first tuning code in a current stage in which an output frequency of a DCO is tuned
by a first step size and generate a first detect signal which indicates whether the first tuning code exceeds a first range
that the DCO can be correspondingly tuned in the current stage; and

a second tuning code adjustor configured to adjust a second tuning code from a previous stage from which the output frequency
of the DCO is tuned by a second step size in response to the first detect signal, the second step size being larger than the
first step size; and

the DCO configured to generate the output frequency in response to codes comprising the adjusted second tuning code from the
across-stage DCO controller.

US Pat. No. 9,345,132

SUBSTRATE STRUCTURE AND THE PROCESS MANUFACTURING THE SAME

Global Unichip Corp., Hs...

1. A substrate structure comprising:
a plurality of conductive regions, wherein each two adjacent conductive regions are separated by an isolation border; and
a connection structure along at least one side of the substrate structure, wherein the connection structure is electrically
connected with at least two conductive regions of the plurality of conductive regions and is in contact with at least one
isolation border, each of the at least one isolation border being adjacent to at least one of the at least two conductive
regions, wherein when the connection structure along the at least one side of the substrate structure is not present, the
at least two conductive regions of the plurality of conductive regions are not electrically connected to each other, wherein
the connection structure comprises a first pattern and a second pattern, wherein the first pattern is electrically connected
with a first group of conductive regions of the plurality of conductive regions along a first side of the substrate and is
electrically connected with a second group of conductive regions of the plurality of conductive regions along a second side
of the substrate, wherein the first group of conductive regions and the second group of conductive regions are electrically
connected by the second pattern along a same side of the substrate.

US Pat. No. 9,275,732

WRITE BUFFER FOR RESISTIVE RANDOM ACCESS MEMORY

TAIWAN SEMICONDUCTOR MANU...

1. A circuit, comprising:
a current generator configured to generate a predetermined current flowing toward a selected cell in a memory array via a
node during a write operation;

a voltage generator configured to generate a predetermined voltage; and
a first transistor configured to shunt the predetermined current at the node,
wherein the voltage level at the node is clamped at a predetermined value associated with the predetermined voltage and the
predetermined current is shunted through the first transistor as the selected cell is switched between a low resistance state
and a high resistance state during the write operation.

US Pat. No. 9,450,093

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor device comprising:
receiving a FinFET precursor comprising:
a fin structure formed between isolation regions; and
a gate structure formed over a portion of the fin structure such that a sidewall of the fin structure is in contact with a
gate spacer of the gate structure;

patterning the fin structure to form a plurality of upward steps rising from the isolation region, wherein each of the plurality
of upward steps comprises a top surface and a side surface connected to the top surface, and the top surfaces of the plurality
of upward steps are located at different levels;

forming a capping layer over the fin structure, the isolation region, and the gate structure;
performing an annealing process on the FinFET precursor to form at least two dislocations along the upward step; and
removing the capping layer.

US Pat. No. 9,484,318

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:
a substrate including a first layer and a second layer over the first layer;
a bump disposed over the second layer;
a molding disposed over the second layer and surrounding the bump, wherein the second layer includes a protruded portion protruding
from a sidewall of the molding adjacent to a periphery of the substrate; and

a retainer disposed on the second layer, wherein the retainer is disposed between the molding and the periphery of the substrate,
and the retainer includes silicon nitride (SiN), silicon dioxide (SiO2), or silicon oxynitride (SiON);

wherein an included angle of the sidewall of the molding and an upper surface of the molding is smaller than ninety degrees;
wherein the retainer has a trapezoidal cross-section, a bottom base of the trapezoidal cross-section is in contact with the
second layer, an upper base of the trapezoidal cross-section is coplanar with a portion of a too surface of the molding immediately
adjacent to the retainer, and the bottom base of the trapezoidal cross-section is longer than the upper base of the trapezoidal
cross-section.

US Pat. No. 9,337,225

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A backside illumination (BSI) semiconductor image sensing device, comprising:
a semiconductor substrate including an image sensing pixel region and an adjacent peripheral region, wherein the peripheral
region is proximal to a sidewall of the backside illumination semiconductor image sensing device;

a first anti reflective coating (ARC) on a backside of the semiconductor substrate;
a dielectric layer on the first anti reflective coating;
a radiation shielding layer on the dielectric layer in the peripheral region; and
a photon blocking layer on the sidewall of the backside illumination semiconductor image sensing device and covering a portion
of a sidewall of the radiation shielding layer while contacting with the sidewall of the radiation shielding layer, the sidewall
of the radiation shielding layer not abutting the dielectric layer and forming a corner with the dielectric layer, and the
photon blocking layer being configured to block photons penetrating into the semiconductor substrate;

wherein an end of the photon blocking layer includes an arc.