US Pat. No. 9,318,528

IMAGE SENSOR DEVICE AND METHOD

Taiwan Semiconductor Manu...

1. A method of manufacturing a semiconductor device, the method comprising:
forming a pixel within an image sensor;
bonding the image sensor to a semiconductor device, the semiconductor device comprising a substrate and a heat sink at least
partially located in a first metallization layer between the pixel and the substrate; and

forming a thermal via extending through the image sensor and in thermal connection with the heat sink.

US Pat. No. 9,331,277

ONE TRANSISTOR AND ONE RESISTIVE RANDOM ACCESS MEMORY (RRAM) STRUCTURE WITH SPACER

Taiwan Semiconductor Manu...

1. A resistive random access memory (RRAM) cell, comprising:
a transistor;
an RRAM structure electrically coupled to the transistor, the RRAM structure having
a bottom electrode having a via portion and a top portion, wherein said via portion of the bottom electrode is embedded in
a first RRAM stop layer;

a resistive material layer on the bottom electrode having a width that is substantially the same as a width of the top portion
of the bottom electrode;

a capping layer on and physically contacting the resistive material layer having a smaller width than the resistive material
layer;

a spacer surrounding the capping layer;
a top electrode on the resistive material layer having a width that is same as the capping layer and a thickness larger than
the capping layer;

a second RRAM stop layer having a first portion disposed over the first RRAM stop layer, the second RRAM stop layer having
a second portion laterally surrounding the top electrode, the spacer, the resistive material layer, and the bottom electrode;
and

a dielectric layer over the first portion of the second RRAM stop layer and laterally surrounding the second portion of the
second RRAM stop layer, the dielectric layer and the second RRAM stop layer differing in composition; and

a conductive material connecting the top electrode of the RRAM structure to a metal layer.

US Pat. No. 9,589,857

INTERPOSER TEST STRUCTURES AND METHODS

Taiwan Semiconductor Manu...

1. A structure comprising:
an interposer having a test structure extending along a periphery of the interposer, at least a portion of the test structure
being in a first redistribution element, the first redistribution element being on a first surface of a substrate of the interposer,
the test structure being intermediate and electrically coupled to at least two probe pads.

US Pat. No. 9,269,591

HANDLE WAFER FOR HIGH RESISTIVITY TRAP-RICH SOI

Taiwan Semiconductor Manu...

1. A substrate, comprising:
a handle wafer;
a trap-rich layer disposed within the handle wafer at a position abutting a top surface of the handle wafer, wherein the trap
rich layer comprises a re-crystallized material having a plurality of oxidation induced stacking faults configured to trap
carriers;

an insulating layer having a first side abutting the top surface of the handle wafer at an interface with the trap-rich layer,
wherein the top surface of the handle wafer has a scratched top surface with depressions extending in lines across the top
surface of the handle wafer and forming protrusions extending into the insulating layer; and

a thin layer of active silicon abutting a second side of the insulating layer that opposes the first side.

US Pat. No. 9,396,953

CONFORMITY CONTROL FOR METAL GATE STACK

Taiwan Semiconductor Manu...

1. A method comprising:
forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer;
removing the dummy gate stack to form a recess;
forming a gate dielectric layer in the recess;
forming a metal layer in the recess, wherein the metal layer is over the gate dielectric layer, and wherein the forming the
metal layer comprises:

placing the wafer against a target;
applying a DC power to the target, wherein a negative end of the DC power is connected to the target, and a positive end of
the DC power is connected to a pedestal underlying the wafer; and

applying an RF power to the target, wherein the DC power and the RF power are applied simultaneously; and
filling a remaining portion of the recess with metallic materials, wherein the metallic materials overlie the metal layer.

US Pat. No. 9,230,795

DIRECTIONAL PRE-CLEAN IN SILICIDE AND CONTACT FORMATION

Taiwan Semiconductor Manu...

9. A method comprising:
etching a dielectric layer to form an opening, with an underlying region underlying the dielectric layer exposed to the opening;
reacting a surface region of the underlying region with a process gas to form a reaction layer, wherein the reaction layer
comprises a first portion at a bottom of the opening and overlying the underlying region, and a second portion on a top surface
of the dielectric layer, with substantially no reaction layer formed on sidewalls of the opening; and

performing an anneal to remove the reaction layer.

US Pat. No. 9,466,488

METAL-SEMICONDUCTOR CONTACT STRUCTURE WITH DOPED INTERLAYER

Taiwan Semiconductor Manu...

1. A method of forming a device, comprising:
forming an insulating layer on a top surface of a semiconductor substrate, a target region disposed at the top surface of
the semiconductor substrate;

etching an opening through the insulating layer, the opening exposing a top surface of a portion of the target region, the
etching comprising generating an etching byproduct disposed on surfaces of the opening;

without removing the etching byproduct, forming a doped metal oxide interlayer in the opening and contacting the top surface
of the target region; and

filling a remainder of the opening with a metal plug, the doped metal oxide interlayer disposed between the metal plug and
the substrate.

US Pat. No. 9,129,918

SYSTEMS AND METHODS FOR ANNEALING SEMICONDUCTOR STRUCTURES

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor structure, the method comprising:
providing a semiconductor structure;
providing an energy-converting material capable of increasing the semiconductor structure's absorption of microwave radiation;
providing a heat reflector between the energy-converting material and the semiconductor structure, the heat reflector being
capable of reflecting thermal radiation from the semiconductor structure; and

applying microwave radiation to the energy-converting material and the semiconductor structure to anneal the semiconductor
structure for fabricating semiconductor devices.

US Pat. No. 9,461,170

FINFET WITH ESD PROTECTION

TAIWAN SEMICONDUCTOR MANU...

1. A field effect transistor (FET) structure, comprising:
a substrate;
a fin structure formed over the substrate, wherein the fin structure comprises:
a first channel region;
a first source or drain region and a second source or drain region formed on and abutting opposite ends of the first channel
region, respectively; and

a well region formed of the same conductivity type as the second source or drain region, connected to the second source or
drain region, and extended to the substrate; and

a first gate structure wrapping around the first channel region in the fin structure;
wherein the first source or drain region and the second source or drain region are more heavily doped than the well region.

US Pat. No. 9,373,603

REFLOW PROCESS AND TOOL

Taiwan Semiconductor Manu...

1. A method comprising:
moving a package workpiece into a chamber of a reflow tool, an exhaust system set at a first pressure removing gas from the
chamber during the moving the package workpiece into the chamber;

enclosing the package workpiece in an enclosed environment of the chamber;
causing an oxygen content of the enclosed environment of the chamber to be less than 40 parts per million (ppm), the causing
the oxygen content to be less than 40 ppm comprising setting the exhaust system at a second pressure less than the first pressure;
and

performing a reflow process in the enclosed environment of the chamber while the oxygen content is less than 40 ppm, the reflow
process reflowing a reflowable material of the package workpiece.

US Pat. No. 9,397,129

DIELECTRIC FILM FOR IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array comprising one or more photodiodes configured to detect light;
a calibration region configured to define a color level for image reproduction, the calibration region formed laterally spaced
apart from the photodiode array;

a dielectric layer formed over and in direct contact with the photodiode array; and
a dielectric film formed over the photodiode array and the calibration region and in contact with the dielectric layer, the
dielectric film having a substantially planar bottom surface extending over the photodiode array and the calibration region.

US Pat. No. 9,343,556

METHODS AND APPARATUS FOR ESD PROTECTION CIRCUITS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substrate;
an n type buried layer (NBL) on the substrate;
a first region on the NBL comprising a first n type material;
a second region on the NBL comprising a first p type material and adjacent to and not overlapping with the first region;
a third region on the NBL comprising a second n type material and adjacent to and not overlapping with the second region;
a fourth region comprising a second p type material formed within the first region;
a fifth region comprising a third n type material formed within the second region, and separated from the fourth region by
a first isolation area; and

a sixth region comprising a third p type material formed within the third region, and separated from the fifth region by a
second isolation area.

US Pat. No. 9,462,692

TEST STRUCTURE AND METHOD OF TESTING ELECTRICAL CHARACTERISTICS OF THROUGH VIAS

Taiwan Semiconductor Manu...

1. An apparatus comprising:
a substrate having a first side and a second side;
a first plurality of electrical connections on the first side of the substrate;
a second plurality of electrical connections on the second side of the substrate; and
a plurality of through vias (TVs), each of the plurality of TVs electrically coupling respective ones of the first plurality
of electrical connections and the second plurality of electrical connections; and

a conductive layer over the second plurality of electrical connections, the conductive layer directly electrically coupling
a first electrical connection of the second plurality of electrical connections to one or more other electrical connections
of the second plurality of electrical connections to electrically couple respective ones of the plurality of TVs to each other.

US Pat. No. 9,395,739

COMMON WELL BIAS DESIGN FOR A DRIVING CIRCUIT AND METHOD OF USING SAME

TAIWAN SEMICONDUCTOR MANU...

1. A driving circuit comprising:
a common well;
a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured
to receive a first signal, and having a second terminal connected to the common well; and

a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured
to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well.

US Pat. No. 9,293,437

FUNCTIONAL BLOCK STACKED 3DIC AND METHOD OF MAKING SAME

Taiwan Semiconductor Manu...

1. A device package comprising:
a fan-out redistribution layer (RDL);
a device bonded to the fan-out RDL, the device comprising:
a first functional tier comprising:
a first substrate;
first active devices on the first substrate; and
a first metallization layer electrically connecting the first active devices;
a second functional tier bonded to the first function tier, wherein the second functional tier comprises:
a second substrate;
second active devices on the second substrate; and
a second metallization layer electrically connecting the second active devices; and
an interconnect structure electrically connecting the first metallization layer to the second metallization layer, wherein
the interconnect structure comprises an inter-tier via (ITV) at least partially disposed in both the first functional tier
and the second functional tier, and wherein the ITV contacts the first metallization layer; and

a molding compound over the fan-out RDL and extending along sidewalls of the device.

US Pat. No. 9,490,176

METHOD AND STRUCTURE FOR FINFET ISOLATION

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor device, comprising:
receiving a substrate having an active fin, a plurality of dummy gate stacks over the substrate and engaging the fin, and
first dielectric features over the substrate and between the dummy gate stacks;

removing the dummy gate stacks thereby forming a first trench and a second trench, wherein the first and second trenches expose
first and second portions of the active fin respectively;

removing the first portion of the active fin; and
forming a gate stack in the second trench, the gate stack engaging the second portion of the active fin.

US Pat. No. 9,293,992

VOLTAGE REGULATOR

TAIWAN SEMICONDUCTOR MANU...

1. A voltage regulator circuit comprising:
an amplifier having an inverting input and a non-inverting input, the amplifier being configured to generate a control signal
based on a reference signal at the inverting input of the amplifier and a feedback signal at the non-inverting input of the
amplifier;

an output node;
a first power node;
a second power node;
a driver configured to generate a driving current flowing toward the output node in response to the control signal, the driver
being coupled between the first power node and the output node;

a first transistor having a gate, the first transistor being coupled between the output node and the second power node; and
a bias circuit outside the amplifier configured to supply a bias signal to the gate of the first transistor, the first transistor
being configured to operate in a saturation mode based on the bias signal supplied by the bias circuit.

US Pat. No. 9,337,103

METHOD FOR REMOVING HARD MASK OXIDE AND MAKING GATE STRUCTURE OF SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method, comprising:
forming a first gate above a semiconductor substrate;
forming a hard mask having a first composition on the first gate;
forming a contact etch stop layer (CESL) having a second composition, the second composition being different than the first
composition, the CESL formed directly on the hard mask without removal of the hard mask between forming the hard mask and
forming the CESL;

forming an interlayer dielectric (ILD) layer, the ILD layer being formed over the CESL; and
performing two CMP processes, the two CMP processes including
a first CMP process with a first slurry to remove the ILD layer above a top surface of the CESL, wherein the first CMP process
stops when the top surface of the CESL is exposed, and wherein the top surface of the CESL absorbs the first slurry to increase
its selectivity to the first CMP process, and

a second CMP process with a second slurry to selectively remove the CESL and remove the hard mask, wherein the second CMP
process stops when a top surface of polysilicon of the first gate is exposed, and wherein the second slurry comprises silica
particles and provides a removal rate of the hard mask having the first composition to the polysilicon of the first gate of
approximately 20:1 to approximately 40:1.

US Pat. No. 9,379,076

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of manufacturing a semiconductor structure, comprising:
receiving a substrate including a die pad disposed thereon;
disposing a passivation over the substrate and around the die pad;
disposing a polymer over the passivation;
forming a post passivation interconnect (PPI) including an elongated portion and a via portion contacting with the die pad;
depositing a metallic paste on the elongated portion of the PPI by a stencil including an aperture corresponding to a predetermined
position of the elongated portion of the PPI;

disposing a conductive bump over the metallic paste; and
disposing a molding over the PPI and around the metallic paste and the conductive bump.

US Pat. No. 9,497,861

METHODS AND APPARATUS FOR PACKAGE WITH INTERPOSERS

Taiwan Semiconductor Manu...

1. A device, comprising:
a substrate;
a metal layer above the substrate;
a first contact pad and a second contact pad above the metal layer; and
a first dam above the metal layer, the first dam comprising a first layer of conductive material and a second layer of non-conductive
material above the first layer of conductive material, wherein the first dam surrounds an area, the first contact pad being
within the area, and the second contact pad being outside the area.

US Pat. No. 9,330,947

METHODS FOR FORMING PACKAGE-ON-PACKAGE STRUCTURES HAVING BUFFER DAMS

Taiwan Semiconductor Manu...

1. A method comprising:
placing a device die having a plurality of metal posts over a release layer, wherein the release layer is over a first carrier;
forming a plurality of through-assembly vias (TAVs) over the release layer;
forming a dam member between the device die and the plurality of TAVs;
molding the device die, the dam member, and the plurality of TAVs in a molding compound; and
grinding the molding compound to expose ends of the plurality of metal posts and ends of the plurality of TAVs, wherein a
top surface of the molding compound is substantially level with the exposed ends of the plurality of metal posts and the exposed
ends of the plurality of TAVs.

US Pat. No. 9,632,426

IN-SITU IMMERSION HOOD CLEANING

Taiwan Semiconductor Manu...

15. An apparatus comprising:
a wafer stage configured to secure a wafer;
a cleaning module positioned outside a region occupied by a wafer when a wafer is secured by the wafer stage, wherein the
cleaning module comprises a water reservoir adjacent the wafer stage, the water reservoir configured to hold water having
a top surface of the water being level with a top surface of the wafer when a wafer is secured on a surface of the wafer stage,
wherein the water reservoir extends over a topmost surface of the wafer stage, the water reservoir comprising:

a first exterior wall, a second exterior wall, and an interior wall, the interior wall disposed between the first exterior
wall and the second exterior wall;

a first partition and a second partition, the first partition disposed between the first exterior wall and the interior wall,
the second partition disposed between the interior wall and the second exterior wall;

a first upper extent of the first exterior wall and a second upper extent of the second exterior wall and a third upper extent
of the interior wall above the surface of the wafer stage;

a first lower extent of the first exterior wall and a second lower extent of the second exterior wall and a third lower extent
of the interior wall below the surface of the wafer stage;

the first lower extent, the second lower extent, the third lower extent, a fourth lower extent of the first partition, and
a fifth lower extent of the second partition are coincident with a bottom of the water reservoir; and

a fourth upper extent of the first partition and a fifth upper extent of the second partition are above the bottom of the
water reservoir; and

wherein the cleaning module comprises:
a first portion of the water reservoir defined by the first exterior wall and the interior wall;
a second portion of the water reservoir defined by the interior wall and the second exterior wall;
a first inlet disposed in the first portion of the water reservoir, the first inlet configured to provide water into the first
portion of the water reservoir;

a first outlet disposed in the first portion of the water reservoir at the bottom of the water reservoir, the first outlet
configured to extract water from the second portion of the water reservoir;

a second inlet disposed in the second portion of the water reservoir, the second inlet configured to provide water into the
second portion of the water reservoir; and

a second outlet disposed in the second portion of the water reservoir at the bottom of the water reservoir, the second outlet
configured to extract water from the second portion of the water reservoir.

US Pat. No. 9,071,477

METHOD AND ASSOCIATED PROCESSING MODULE FOR INTERCONNECTION SYSTEM

GLOBAL UNICHIP CORPORATIO...

1. A method for an interconnection system, the interconnection system comprising a transmitter filter and a receiver equalizer,
the transmitter filter arranged to filter a first signal based on a pre-tap and a post-tap, and accordingly provide a second
signals; the receiver equalizer arranged to equalize the second signal based on an equalizer tap and accordingly provide a
third signal, and the method comprising:
performing, by a hardware processor a pattern comparison step for forming an indicative pattern according to a plurality of
data samples of the third signal and a transition sample of the third signal, comparing if the indicative pattern matches
a predetermined pattern, and accordingly providing a comparison result, wherein the transition sample is sampled between two
of the plurality of data samples; and

performing a pre-tap tuning directing step for, according to the comparison result, directing whether the pre-tap is incremented
or decremented; and

performing a post-tap tuning directing step for, according to a sign of the equalizer tap, directing whether the post-tap
is incremented or decremented.

US Pat. No. 9,281,221

ULTRA-HIGH VACUUM (UHV) WAFER PROCESSING

Taiwan Semiconductor Manu...

11. A vacuum system for ultra-high vacuum (UHV) wafer processing, comprising:
a remote load lock (RLL) module configured to:
receive a wafer from a load port; and
pump down the RLL module to a first pressure;
a first bridge configured to connect the RLL module to a first cluster tool, the first bridge comprising:
a second bypass module;
a first buffer module configured to at least one of:
receive the wafer from the second bypass module;
receive the wafer from the RLL module; or
pump down the first buffer module to a second pressure, the second pressure less than the first pressure; and
a first bypass module configured to receive the wafer from the first buffer module, the first bypass module connected to the
first cluster tool; and

a second bridge configured to connect the first cluster tool to a second cluster tool, the second bridge associated with the
second pressure, the second bridge comprising:

a fourth bypass module configured to receive the wafer from the first cluster tool;
a second buffer module configured to receive the wafer from the fourth bypass module; and
a third bypass module configured to receive the wafer from the second buffer module, the third bypass module connected to
the second cluster tool.

US Pat. No. 9,054,004

PIXEL ISOLATION STRUCTURES IN BACKSIDE ILLUMINATED IMAGE SENSORS

Taiwan Semiconductor Manu...

1. A backside illuminated image sensor including an array of pixels, comprising:
a first pixel disposed in a front side of a substrate and configured to generate charged carriers in response to light incident
upon a backside of the substrate;

a second pixel disposed in the front side of the substrate and configured to generate charged carriers in response to light
incident upon the backside of the substrate; and
an anti-reflective layer on the backside of the substrate; and
a first isolation structure disposed to separate the second pixel from the first pixel, the first isolation structure extending
from the backside of the substrate toward the front side of the substrate, wherein the first isolation structure includes
a first sidewall substantially vertically to the front side of the substrate,

wherein the first isolation structure separates a region of the anti-reflective layer corresponding to the first pixel and
another region of the anti-reflective layer corresponding to the second pixel.

US Pat. No. 9,318,456

SELF-ALIGNMENT STRUCTURE FOR WAFER LEVEL CHIP SCALE PACKAGE

TAIWAN SEMICONDUCTOR MANU...

1. A method, comprising:
depositing a metal layer over a semiconductor substrate;
patterning the metal layer to form a metal pad and a metal base on the semiconductor substrate;
forming a polymer insulating layer over the semiconductor substrate, the metal pad and the metal base;
forming a first opening passing through the polymer insulating layer to expose a portion of the metal pad;
depositing a copper-containing layer over the polymer insulating layer;
patterning the copper-containing layer to form a support structure with a second opening and a post-passivation interconnect
(PPI) line extending through the second opening, wherein patterning the copper-containing layer forms the support structure
of which a top is elevated higher than a top of the PPI line by a thickness of the metal pad; and

forming a conductive bump on the support structure.

US Pat. No. 9,312,229

HYBRID BONDING WITH AIR-GAP STRUCTURE

Taiwan Semiconductor Manu...

1. A package comprising:
a first package component comprising:
a first surface dielectric layer comprising a first planar surface; and
a first metal pad in the first surface dielectric layer, wherein the first metal pad comprises:
a first diffusion barrier layer comprising sidewall portions;
a first metallic material encircled by the sidewall portions of the first diffusion barrier layer, wherein the first metallic
material comprises a second planar surface level with the first planar surface; and

an air gap extending from the second planar surface of the first metallic material into the first metallic material; and
a second package component overlapping the first package component, wherein the second package component comprises:
a second surface dielectric layer comprising a third planar surface bonded to the first planar surface; and
a second metal pad in the second surface dielectric layer, wherein the second metal pad has a fourth planar surface bonded
to the second planar surface, and the air gap is overlapped by the second metal pad.

US Pat. No. 9,240,401

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substrate;
a first region over the substrate, the first region comprising a first n type material;
a second region laterally adjacent to the first region, the second region comprising a first p type material;
a third region disposed laterally adjacent to the second region on a side of the second region opposite the first region,
the third region comprising a second n type material;

a fourth region disposed within a portion of the first region proximate the second region, the fourth region comprising a
second p type material;

a fifth region disposed within a portion of the second region proximate the first region, wherein the fourth region and the
fifth region are separated by a first isolation area;

a sixth region disposed within a portion of the third region proximate the second region, the sixth region comprising a third
p type material; and

a seventh region disposed within the second region and below the fifth region.

US Pat. No. 9,147,702

IMAGE SENSOR FOR MITIGATING DARK CURRENT

Taiwan Semiconductor Manu...

16. An image sensor for mitigating dark current, comprising:
a first region comprising a first doping type;
a second region comprising a second doping type, the second doping type opposite of the first doping type, the first region
surrounded by the second region;

a third region at least one of above the first region or below the first region, the third region comprising:
a first sub-region adjacent to the second region and comprising the first doping type; and
a second sub-region adjacent to the first sub-region and comprising the first doping type; and
a first surface protect region comprising the first doping type, the first surface protect region adjacent to the second sub-region.

US Pat. No. 9,129,818

SEMICONDUCTOR DEVICE HAVING CONDUCTIVE PADS AND A METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device, comprising:
a substrate;
a plurality of conductive pads formed in consecutive conductive layers, the plurality of conductive pads aligned and arranged
one above another over the substrate, wherein the plurality of conductive pads comprises a first conductive pad and a second
conductive pad, the first conductive pad is above the second conductive pad, a redistribution layer extends the second conductive
pad, and the first conductive pad is not extended by a redistribution layer;

a bump structure formed on the first conductive pad and electrically coupled to the plurality of conductive pads; and
a dielectric layer extending into a gap between peripheral parts of the first and second conductive pads,
wherein middle parts of the first and second conductive pads are in direct contact with each other, and
wherein the redistribution layer and the second conductive pad comprise different conductive materials.

US Pat. No. 9,081,289

SYSTEM AND METHOD FOR OPTIMIZATION OF AN IMAGED PATTERN OF A SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. A method, comprising:
providing a layout of a device having a pattern of features;
identifying a first portion of at least one feature of the plurality of features;
assigning an image criteria for the first portion;
determining a lithography optimization parameter based on the assigned image criteria for the first portion; and
imaging the first portion of the at least one feature onto a semiconductor substrate using the determined lithography optimization
parameter;

wherein the at least one feature is symmetrical as defined by a layout file, wherein the imaging provides an imaged first
feature on the semiconductor substrate, and wherein the imaged first feature is asymmetrical.

US Pat. No. 9,293,392

3DIC INTERCONNECT APPARATUS AND METHOD

Taiwan Semiconductor Manu...

1. A method comprising:
bonding a first surface of a first semiconductor chip to a surface of a second semiconductor chip;
after the bonding, forming a first opening extending from a second surface of the first semiconductor chip partially to a
conductive feature in the first semiconductor chip;

forming a liner in the first opening;
forming a second opening extending from a bottom of the first opening to a conductive feature in the second semiconductor
chip, the second opening exposing at least a portion of a sidewall and an adjoining horizontal surface of the conductive feature
of the first semiconductor chip; and

forming a conductive material in the first opening and the second opening.

US Pat. No. 9,252,491

EMBEDDING LOW-K MATERIALS IN ANTENNAS

Taiwan Semiconductor Manu...

1. A device comprising:
a patch antenna comprising:
a feeding line;
a ground panel over the feeding line, wherein the ground panel comprises an aperture therein;
a low-k dielectric module over and aligned to the aperture; and
a patch over the low-k dielectric module.

US Pat. No. 9,093,299

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a first active region;
a second active region;
a shallow trench isolation (STI) region between the first active region and the second active region; and
a metal connect over the first active region, the STI region and the second active region, and connected to the first active
region and the second active region, such that a first unrecessed portion of the metal connect over the first active region
has a first height, a recessed portion of the metal connect over the STI region has a second height and a second unrecessed
portion of the metal connect over the second active region has a third height, the first height and the third height greater
than the second height.

US Pat. No. 9,443,806

CHIP PACKAGES AND METHODS OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A chip package, comprising:
a chip having a contact pad disposed at a first side of the chip;
a passivation layer over the first side of the chip, the passivation layer having an opening disposed over the contact pad;
a polymer layer over the passivation layer, the polymer layer having an edge disposed over the contact pad, wherein the edge
of the polymer layer is distal from a perimeter of the opening of the passivation layer;

a conductive structure formed atop the contact pad, the conductive structure filling the opening of the passivation layer
and covering the edge of the polymer layer; and

a fan-out structure disposed over the conductive structure, the fan-out structure having a first portion electrically connected
to the conductive structure and a second portion electrically connected to the first portion and extending laterally away
from the first portion and the conductive structure.

US Pat. No. 9,252,076

3D PACKAGES AND METHODS FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a molding material having a thickness over a first substrate, the first substrate comprising a first edge region, a middle
region next to the first edge region, and a second edge region next to the middle region and opposite the first edge region;

a first opening in the molding material in the first edge region, the first opening having a first width;
a first connector in the first opening;
a second opening in the molding material in the middle region, the second opening having a second width, the second width
being greater than the first width;

a second connector in the second opening;
a third opening in the molding material in the second edge region, the third opening having a third width, the third width
being greater than the second width;

a third connector in the third opening; and
a second package bonded to the first connector, the second connector, and the third connector, a first surface of the second
package being physically separated from a first surface of the molding material by a first gap in the first edge region, a
second gap in the middle region, and a third gap in the second edge region, the first gap being greater than the second gap,
and the second gap being greater than the third gap.

US Pat. No. 9,380,709

METHOD OF CUTTING CONDUCTIVE PATTERNS

Taiwan Semiconductor Manu...

1. A method comprising
(a) patterning a layer over a substrate using a first photomask, to create a first metal line pattern;
(b) using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material
from a first region within the first metal line pattern; and

(c) patterning the layer over the substrate with a second photomask in a double patterning process to form a second metal
line pattern having a second region;

(d) after step (c), using the cut mask to perform a second cut patterning while in a second position relative to the layer
over the substrate, for removing material from the second region.

US Pat. No. 9,425,250

TRANSISTOR WITH WURTZITE CHANNEL

Taiwan Semiconductor Manu...

1. A device comprising:
a source region;
a drain region;
a wurtzite semiconductor between the source region and the drain region, wherein a source-drain direction is parallel to a
[01-10] direction or a [?2110] direction of the wurtzite semiconductor;

a gate dielectric over the wurtzite semiconductor; and
a gate electrode over the gate dielectric.
US Pat. No. 9,134,604

EXTREME ULTRAVIOLET (EUV) MASK AND METHOD OF FABRICATING THE EUV MASK

TAIWAN SEMICONDUCTOR MANU...

1. An extreme ultraviolet (EUV) mask, comprising:
a substrate;
a reflective multilayer (ML) coating over the substrate; and
an absorber layer over the reflective ML coating,
wherein the absorber layer is a dual-layer stack having a first layer and a second layer over the first layer, and the first
layer is made of Ag—Pd—Cu (APC) or Cu and the second layer is made of Indium Tin Oxide (ITO).

US Pat. No. 9,093,373

CONDUCTIVE DIFFUSION BARRIER STRUCTURE FOR OHMIC CONTACTS

Taiwan Semiconductor Manu...

1. An integrated circuit (IC), comprising:
a p-type region formed beneath a surface of a semiconductor substrate;
an n-type region formed beneath the surface of the semiconductor substrate and meeting the p-type region at a p-n junction;
and

a diffusion barrier structure, which is formed in the semiconductor substrate and extends along a side of the p-n junction,
to limit lateral diffusion of dopants between the p-type region and n-type region.

US Pat. No. 9,437,281

NEGATIVE BITLINE BOOST SCHEME FOR SRAM WRITE-ASSIST

Taiwan Semiconductor Manu...

1. A device comprising:
a switch coupled between a bit line voltage node and a low voltage supply node;
a boost signal circuit coupled to a control node of the switch, the boost signal circuit providing a boost signal responsive
to a write enable signal;

a plurality of delay elements;
a first capacitor having a first end coupled to the bit line voltage node and a second end coupled to the control node; and
a second capacitor having a first end coupled to the bit line voltage node and a second end coupled to the second end of the
first capacitor.

US Pat. No. 9,305,880

INTERCONNECTS FOR SEMICONDUCTOR DEVICES

Taiwan Semiconductor Manu...

1. A method for forming an interconnect structure, comprising:
providing a dielectric layer above a semiconductor substrate, the dielectric layer having a recess formed therein;
forming an interconnect structure comprising a metal liner and a conductive fill within said recess;
applying an electron beam treatment to said interconnect structure by focusing a beam of electrons on the interconnect structure;
and

planarizing said interconnect structure, wherein said planarizing step and said applying step are performed under vacuum in
a chamber without releasing the vacuum therebetween.

US Pat. No. 9,287,413

JUNCTION GATE FIELD-EFFECT TRANSISTOR (JFET) AND SEMICONDUCTOR DEVICE

Taiwan Semiconductor Manu...

1. An n-type junction gate field-effect transistor (NJFET), comprising:
a substrate;
a source region formed in the substrate, wherein the source region is an n-doped region;
a drain region formed in the substrate, wherein the drain region comprises an n-well;
a channel region formed in the substrate, the channel region connecting the source and drain regions, wherein the channel
region is an n-doped region, and the n-well contacts the channel region;

a deep n-well below the channel region, the deep n-well contacting the n-well of the drain region;
at least one gate region formed in the substrate, the at least one gate region configured to cause a depletion in at least
one of the source region or the drain region, wherein the at least one gate region is a p-doped region.

US Pat. No. 9,455,169

ULTRA-LOW OXYGEN AND HUMILITY LOADPORT AND STOCKER SYSTEM

Taiwan Semiconductor Manu...

1. A pod comprising:
a storage chamber having a sidewall surface defining an opening at one side thereof; and
a pod door fitted to the storage chamber at the opening so as to provide ingress and egress to the storage chamber, the pod
door comprising:

a door body;
a first door locking mechanism on the door body, the first door locking mechanism comprising:
a first pressure applicator;
a first key assembly; and
a first connector-rod coupling the first key assembly to the first pressure applicator; and
a seal band, wherein:
the first key assembly is movable between a locked position and an unlocked position,
the seal band is configured to engage the sidewall surface of the storage chamber while the first key assembly is in the locked
position,

an angle defined by a face of the first connector-rod and a face of the first pressure applicator is different when the first
key assembly is in the locked position than when the first key assembly is in the unlocked position, and

the seal band is spaced apart from the first pressure applicator to define a gap when the first key assembly is in the unlocked
position.

US Pat. No. 9,354,510

EUV MASK AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A mask comprising:
a reflective multilayer over a substrate;
an absorption layer disposed over the reflective multilayer; and
an antireflection layer disposed over the absorption layer, wherein a trench extends through the antireflection layer and
terminates in the absorption layer.

US Pat. No. 9,377,401

BIOLOGICAL SENSING STRUCTURES

Taiwan Semiconductor Manu...

1. A biological sensing structure, comprising:
a mesa integrally connected a portion of a substrate, wherein the mesa has a top surface and a sidewall surface adjacent to
the top surface;

a first light reflecting layer disposed over the top surface and the sidewall surface of the mesa;
a filling material surrounding the mesa, wherein the mesa protrudes from a top surface of the filling material;
a stop layer disposed over the filling material and a portion of the first light reflecting layer;
a sacrificial layer disposed over a first portion of the stop layer and exposing a second portion of the stop layer;
a second light reflecting layer disposed over the second portion of the stop layer and a portion of the top surface of the
mesa; and

an opening disposed in the second light reflecting layer to partially expose the top surface of the mesa.

US Pat. No. 9,287,372

METHOD OF FORMING TRENCH ON FINFET AND FINFET THEREOF

Taiwan Semiconductor Manu...

1. A method of forming a trench on a fin field effect transistor (FinFET), comprising:
forming a first inter-layer dielectric layer over a first gate and a second gate of the FinFET;
forming a second inter-layer dielectric layer above the first inter-layer dielectric layer, the first gate of the FinFET,
and the second gate of the FinFET;

patterning a photoresist layer over the second inter-layer dielectric layer;
etching part of the second inter-layer dielectric layer that is not below the photoresist layer to expose the first gate and
the second gate;

forming a first polysilicon layer over the first gate and the second gate and in the second inter-layer dielectric layer;
and

removing the first gate and the second gate and the first polysilicon layer to form a first trench and a second trench through
the first inter-layer dielectric layer and the second inter-layer dielectric layer.

US Pat. No. 9,287,153

SEMICONDUCTOR BAKING APPARATUS AND OPERATION METHOD THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor baking apparatus comprising:
a load lock chamber;
a process chamber having a first accommodating space therein;
a transfer chamber having a second accommodating space therein and connected to the load lock chamber and the process chamber;
a first interior door between the process chamber and the transfer chamber, wherein when the first interior door is opened,
the first accommodating space is communicated with the second accommodating space; and

a controller programmed to open the first interior door when the semiconductor baking apparatus idles.

US Pat. No. 9,282,631

CIRCUIT WITH FLAT ELECTROMAGNETIC BAND GAP RESONANCE STRUCTURE

GLOBAL UNICHIP CORPORATIO...

1. A circuit with electromagnetic band gap resonance structure, comprising:
a first conductor layer;
a second conductor layer comprising a predetermined quantity of flat units; each of the flat units spirally revolving inward
from an end to an internal point, and spirally revolving outward from the internal point to an other end; and

a predetermined number of conductive stands, each of the conductive stands associated with one of the predetermined quantity
of flat units, for connecting the associated flat unit to the first conductor layer;

wherein the predetermined quantity of flat units are arranged to suppress a response of at least a frequency, each said frequency
associates with a stub length of each of the flat units; each of the flat units are connected to the associated conductive
stand at a connection point, and the stub length of each of the flat units associated with a route length from the connection
point to one of the two ends of each of the flat units.

US Pat. No. 9,240,348

METHOD OF MAKING A SEMICONDUCTOR DEVICE PACKAGE

Taiwan Semiconductor Manu...

1. A method of forming a semiconductor device package, the method comprising:
bonding a front surface of a first substrate to a second substrate;
thinning a back surface of the first substrate;
depositing and patterning a dielectric layer on the thinned back surface of the first substrate;
etching the first substrate after the depositing and the patterning of the dielectric layer are performed to form a through
silicon via to enable making an electrical connection with a first level metal of the first substrate;

depositing an isolation layer to line the through silicon via;
etching the isolation layer at the bottom of the through silicon via; and
depositing a conductive layer to line the through silicon via after the isolation layer at the bottom of the through silicon
via is etched; and

depositing a copper film over the conductive layer.

US Pat. No. 9,076,553

SPSRAM WRAPPER

Taiwan Semiconductor Manu...

1. A system for facilitating access operations to a single port memory device, comprising:
a wrapper controller configured to:
initiate a first access operation from a first port of a wrapper address component to a single port memory device during a
first clock period;

receive a clock reset signal from the single port memory device, the clock reset signal indicative of a completion of the
first access operation; and

initiate a second access operation from a second port of the wrapper address component to the single port memory device during
the first clock period responsive to receiving the clock reset signal.

US Pat. No. 9,064,705

METHODS AND APPARATUS OF PACKAGING WITH INTERPOSERS

Taiwan Semiconductor Manu...

1. A device, comprising:
an interposer with a surface formed by an insulator layer, and a first contact pad covering an opening of the insulator layer
and in contact with a metal layer within the interposer;

a first die and a second die above the interposer, wherein the first die is disposed laterally adjacent the second die; and
a micro-bump layer comprising:
a first micro-bump line above the insulator layer of the interposer, wherein electrical signals between the first die and
the second die are transmitted through the first micro-bump line, and wherein the electrical signals transmitted between the
first die and the second die through the first micro-bump line are not transmitted through the interposer; and

a micro-bump above the first contact pad of the interposer, wherein the micro-bump electrically connects the first die to
the metal layer within interposer.

US Pat. No. 9,064,797

SYSTEMS AND METHODS FOR DOPANT ACTIVATION USING PRE-AMORPHIZATION IMPLANTATION AND MICROWAVE RADIATION

Taiwan Semiconductor Manu...

1. A method for dopant activation in a semiconductor structure for fabricating semiconductor devices, the method comprising:
providing a substrate;
forming a semiconductor structure on the substrate;
performing pre-amorphization implantation on the semiconductor structure;
providing one or more microwave-absorption materials capable of increasing an electric field density associated with the semiconductor
structure; and

applying microwave radiation to the semiconductor structure and the microwave-absorption materials to activate dopants in
the semiconductor structure for fabricating semiconductor devices;

wherein the microwave-absorption materials are configured to increase the electric field density in response to the microwave
radiation so as to increase the semiconductor structure's absorption of the microwave radiation.

US Pat. No. 9,287,282

METHOD OF FORMING A LOGIC COMPATIBLE FLASH MEMORY

Taiwan Semiconductor Manu...

1. A method comprising:
forming a first pad oxide layer and a second pad oxide layer over a first active region and a second active region, respectively,
of a semiconductor substrate;

forming a dielectric protection layer overlapping the first pad oxide layer;
removing the second pad oxide layer;
forming a floating gate dielectric over the second active region;
forming a floating gate layer, wherein the floating gate layer comprises a first portion over the dielectric protection layer,
and a second portion over the floating gate dielectric;

performing a planarization on the first portion and the second portion of the floating gate layer;
forming a blocking layer, a control gate layer, and a hard mask layer over the second portion of the floating gate layer;
and

patterning the hard mask layer, the control gate layer, and the blocking layer, wherein a remaining portion of the control
gate layer forms a control gate.

US Pat. No. 9,282,592

ROTATABLE HEATING-COOLING PLATE AND ELEMENT IN PROXIMITY THERETO

TAIWAN SEMICONDUCTOR MANU...

1. An apparatus for selectively heating or cooling one or more substrates and establishing an approximately uniform temperature
distribution in the one or more substrates during a heating or cooling event, the apparatus comprising:
a rotatable hot-cold plate onto which the one or more substrates are placed, wherein the rotatable hot-cold plate comprises
a plurality of sub-plates for receiving the one or more substrates, and each sub-plate of the plurality of sub-plates is independently
rotatable bi-directionally; and

a heating-cooling element disposed in close proximity to the rotatable hot-cold plate for selectively elevating or lowering
the temperature of the one or more substrates, wherein the rotatable hot-cold plate is configured to rotate relative to the
heating-cooling element.

US Pat. No. 9,275,181

CELL DESIGN

Taiwan Semiconductor Manu...

1. A transistor array of a cell, comprising:
a first transistor comprising:
a first gate, and
a first region having a first length, the first region comprising at least one of a first source or a first drain; and
a second transistor comprising:
a second gate, and
a second region abutting the first region, the second region having a second length different than the first length, the second
region comprising at least one of a second source or a second drain, wherein:

a ratio of the first length to the second length is a function of at least one of a desired alpha ratio for the transistor
array or a desired beta ratio for the transistor array.

US Pat. No. 9,153,452

SYSTEMS AND METHODS FOR CHEMICAL MECHANICAL PLANARIZATION WITH PHOTO-CURRENT DETECTION

Taiwan Semiconductor Manu...

1. A system for performing chemical-mechanical planarization on an article, comprising:
a polishing head configured to perform chemical-mechanical planarization (CMP) on an article;
a polishing pad configured to support the article;
a light source configured to emit an incident light;
a polishing fluid configured to perform CMP including a plurality of light-absorption particles capable of transferring charges
to a stop layer in the article in response the incident light;

a current detector configured to detect a current in response to the light-absorption particles transferring charges to the
stop layer; and

one or more processors configured to control the polishing head based on the detected current.

US Pat. No. 9,472,618

NANOWIRE FIELD EFFECT TRANSISTOR DEVICE HAVING A REPLACEMENT GATE

Taiwan Semiconductor Manu...

1. A transistor device, comprising:
a semiconductor substrate;
a buffer layer formed over the semiconductor substrate;
a nanowire formed over the buffer layer and having a pair of distal portions, the nanowire including
source and drain regions respectively defined at the distal portions of the nanowire and
a channel region connecting the source and drain regions of the nanowire;
a gate structure surrounding the nanowire; and
a remnant of a sacrificial layer between the buffer layer and the nanowire, wherein the gate structure and the remnant of
the sacrificial layer define a distance L therebetween and the distance L determines a degree to which areas of the source
region or the drain region are electrically isolated from the buffer layer.

US Pat. No. 9,281,741

START-UP CIRCUIT FOR VOLTAGE REGULATION CIRCUIT

Taiwan Semiconductor Manu...

1. A start-up circuit configured to apply a voltage to a pre-charge node of a primary circuit to alter a wake-up time of the
primary circuit, comprising:
a reset transistor coupled to at least one of ground or a first voltage source and configured to discharge the pre-charge
node to at least one of ground or the first voltage source when the reset transistor is turned-on;

a recharge transistor coupled to a second voltage source and configured to apply the voltage to the pre-charge node when the
recharge transistor is turned-on; and

a control transistor coupled to a third voltage source and configured to control application of a second voltage to a gate
of the recharge transistor.

US Pat. No. 9,281,263

INTERCONNECT STRUCTURE INCLUDING A CONTINUOUS CONDUCTIVE BODY

Taiwan Semiconductor Manu...

1. An interconnect structure for connecting devices of a semiconductor substrate, comprising:
a dielectric layer over the substrate;
a continuous conductive body passing through the dielectric layer and made up of a lower body region and an upper body region,
wherein the lower body region is an interconnect line region and the upper body region is a via region which is continuous
with the interconnect line region, wherein the lower body region has a first width defined between opposing lower sidewalls
of the continuous conductive body, and wherein the upper body region has a second width defined between opposing upper sidewalls
of the continuous conductive body, wherein the second width is less than the first width; and

a barrier layer separating the continuous conductive body from the dielectric layer, wherein the barrier layer comprises:
a first barrier layer extending along sidewalls of the via region and along sidewalls of the interconnect line region and
extending under a lower surface of the interconnect line region to separate the conductive body from the dielectric layer;
and

a second barrier layer overlying an upper surface of the via region, wherein the first barrier layer and second barrier layer
are continuous.

US Pat. No. 9,123,839

IMAGE SENSOR WITH STACKED GRID STRUCTURE

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a metal grid formed over a photodiode array, the metal grid comprising:
a first metal grid portion comprising a first interface configured to guide light towards a first photodiode and deflect the
light away from a second photodiode; and

a second metal grid portion comprising a second interface configured to guide the light towards the first photodiode;
a dielectric extending between the first metal grid portion and the second metal grid portion, the dielectric comprising a
first material;

a dielectric grid formed over the metal grid, the dielectric grid comprising:
a first dielectric grid portion; and
a second dielectric grid portion; and
a filler material extending between the first dielectric grid portion and the second dielectric grid portion, the filler material
different than the first material.

US Pat. No. 9,054,686

DELAY PATH SELECTION FOR DIGITAL CONTROL OSCILLATOR

Taiwan Semiconductor Manu...

1. A system for delay path selection, comprising:
a delay path selection multiplexer; and a digitally controlled oscillator comprising: a first inverter structure configured
to be selectively enabled by the delay path selection multiplexer to establish a first delay path within the digitally controlled
oscillator; and a second inverter structure configured to be selectively enabled by the delay path selection multiplexer to
establish a second delay path within the digitally controlled oscillator, the second delay path and the first delay path having
at least one inverter structure in common, and wherein: the delay path selection multiplexer is configured to selectively
enable the first inverter structure and the second inverter structure based upon a selected frequency output of the digitally
controlled oscillator.

US Pat. No. 9,425,257

NON-PLANAR SIGE CHANNEL PFET

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:
a semiconductor substrate having a Germanium concentration and including a top surface;
a metal gate including a bottom surface;
a channel layer formed of a Germanium compound having a Germanium concentration and including a top surface and a bottom surface
that is in contact with the top surface of the semiconductor substrate, wherein the top surface of the channel layer is at
higher elevation than the bottom surface of the metal gate from a bottom surface of the semiconductor substrate, the Germanium
concentration of the semiconductor substrate being less than the Germanium concentration of the channel layer; and

a capping layer a portion of which is formed between the top and bottom surfaces of the channel layer to separate the channel
layer from the metal gate, the capping layer having a Germanium concentration, the Germanium concentration of the channel
layer being greater than the Germanium concentration of the capping layer.

US Pat. No. 9,287,313

ACTIVE PIXEL SENSOR HAVING A RAISED SOURCE/DRAIN

Taiwan Semiconductor Manu...

1. A device, comprising:
an integrated circuit comprising an array of active pixel sensor cells formed on a semiconductor body;
the active pixel sensor cells each having a transistor that has a channel region and a raised source or drain region;
the channel region being a doped region of the semiconductor body;
the raised source or drain region comprising doped polysilicon positioned over and in contact with the semiconductor body
and a region of the semiconductor body that is doped to an opposite doping type of the channel region by diffusion of dopants
into the semiconductor body from the doped polysilicon; and

wherein the doped polysilicon of the raised source or drain region extends to overlay a gate of a source follower transistor
of the active pixel sensor cells.

US Pat. No. 9,287,233

ADHESIVE PATTERN FOR ADVANCE PACKAGE RELIABILITY IMPROVEMENT

Taiwan Semiconductor Manu...

1. An integrated chip (IC) package, comprising:
an integrated chip (IC) die coupled to an underlying substrate by a plurality of electrically conductive bonding structures;
a first adhesive layer having a first Young's modulus and disposed onto the substrate at a first plurality of positions surrounding
the IC die;

a second adhesive layer, having a second Young's modulus less than the first Young's modulus, disposed onto the substrate
at a second plurality of positions surrounding the IC die, wherein the second adhesive layer has an “L ” shape comprising
two connected orthogonal legs separated from the first adhesive layer by spaces having different sizes; and

a lid affixed to the substrate by the first and second adhesive layers and configured to extend to a position overlying the
IC die.

US Pat. No. 9,275,752

READ-ONLY MEMORY

Taiwan Semiconductor Manu...

1. A multi-layer bit-1 read-only memory (ROM) cell, comprising:
a first circuit comprising a first transistor; and
a second circuit comprising a second transistor, wherein:
a gate of the second transistor is coupled to a YMUX connection;
the YMUX connection is coupled to a first multiplexer;
a source of the second transistor is coupled to a word-line bar;
the second circuit is configured to control a voltage in the first circuit;
the second transistor is configured to maintain a disconnection between a source of the first transistor and the word-line
bar when a voltage at the YMUX connection is within a low voltage state voltage range; and

the second circuit is located on a different physical layer than the first circuit.

US Pat. No. 9,262,558

RC EXTRACTION FOR SINGLE PATTERNING SPACER TECHNIQUE

Taiwan Semiconductor Manu...

1. An integrated circuit design method, comprising:
performing a place and route operation using a computer implemented place and route tool to generate a preliminary layout
for a photomask to be used to form a circuit pattern of a semiconductor device, the place and route operation being constrained
by a plurality of single patterning spacer technique (SPST) routing rules, wherein the SPST routing rules cause first and
second patterns to be laid out , such that the first patterns are to be included in the photomask, and the second patterns
are to be excluded from the photomask but defined between spacers, the spacers to be formed adjacent the circuit pattern formed
using the first patterns of the photomask;

predicting locations and sizes of dummy conductive fill patterns within the computer implemented place and route tool, the
dummy conductive fill patterns to be added to the preliminary layout of the photomask; and

performing RC timing analysis of the circuit pattern within the computer implemented place and route tool, the RC timing analysis
being performed based on the preliminary layout and the predicted locations and sizes of dummy conductive fill patterns.

US Pat. No. 9,263,345

SOI TRANSISTORS WITH IMPROVED SOURCE/DRAIN STRUCTURES WITH ENHANCED STRAIN

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a substructure including a substrate that is silicon, a buried oxide layer formed over said silicon substrate and a crystalline
silicon material formed over said buried oxide layer, the substructure including openings extending from a top surface of
the crystalline silicon material through the buried oxide layer and into the substrate;

a plurality of gate structures formed over said crystalline silicon material, a gate structure of the plurality of gate structures
having a pair of sidewall spacers with a gate electrode therebetween;

source/drain structures disposed adjacent said gate electrode, said source/drain structures comprising a strain material that
is a different material than said silicon substrate, the strain material filling the openings, the strain material having
an upper portion extending above said crystalline silicon material; and

graded dopant impurity regions in said silicon substrate entirely below the strain material in a region entirely between sidewall
spacers of two adjacent gate structures of the plurality of gate structures, the graded dopant impurity regions formed of
silicon doped with impurities, the graded dopant impurity regions located beneath respective bottom surfaces of said strain
material.

US Pat. No. 9,166,035

DELTA DOPING LAYER IN MOSFET SOURCE/DRAIN REGION

Taiwan Semiconductor Manu...

1. A transistor comprising:
a gate terminal;
a source terminal; and
a drain terminal;
wherein at least one of the source and drain terminals has a layered configuration including
a terminal layer having a top surface and a bottom surface, and
an intervening layer that is located within the terminal layer, between and spaced from the top and bottom surfaces, and that
is oriented to be substantially perpendicular to current flow, and that is less than one tenth the thickness of the terminal
layer; and

wherein the terminal layer and the intervening layer include a common semiconductive compound and a common dopant, with a
concentration of the dopant in the intervening layer being over ten times an average concentration of the dopant in the terminal
layer, and

wherein the intervening layer is spaced at least twice as far from the bottom surface as from the top surface.

US Pat. No. 9,472,665

MOS TRANSISTOR AND METHOD FOR MANUFACTURING MOS TRANSISTOR

Taiwan Semiconductor Manu...

1. A MOS transistor in a semiconductor substrate, the MOS transistor comprising:
a source region of a first conductivity type and a drain region of the first conductivity type in the semiconductor substrate;
a channel region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate between
the source region and the drain region;

an isolation region adjacent to the drain region;
a drift region of the first conductivity type laterally adjacent to the channel region and beneath the isolation region and
the drain region;

a gate dielectric layer over the channel region and extending over the drift region;
a gate electrode over the gate dielectric layer having a first portion and a second portion, wherein the first portion of
the first conductivity type has a uniform or substantially uniform dopant concentration and is over the channel region and
further extends over a portion of the drift region and a portion of the isolation region, the second portion is un-doped and
over the isolation region, an interface between the first portion and the second portion is directly overlying the isolation
region, and the first portion has a width less than a width of the second portion; and

a field plate contacting an upper surface of the gate electrode, wherein the field plate comprises polycide.

US Pat. No. 9,412,656

REVERSE TONE SELF-ALIGNED CONTACT

Taiwan Semiconductor Manu...

1. A method, comprising:
forming a sacrificial material around and above a pair of gate structures, wherein a source/drain region is arranged between
the pair of gate structures;

removing the pair of gate structures to form a pair of cavities within the sacrificial material;
filling the pair of cavities with a gate material to form a pair of replacement gate structures;
forming a sacrificial source/drain contact between the pair of replacement gate structures;
forming a dielectric layer over the sacrificial source/drain contact and over the pair of replacement gate structures;
sequentially etching both the sacrificial source/drain contact and the dielectric layer to form a recess that extends through
the sacrificial material; and

filling the recess with a conductive material to form a source/drain contact that is electrically coupled to the source/drain
region.

US Pat. No. 9,287,122

METHOD FOR GROWING EPITAXIES OF A CHEMICAL COMPOUND SEMICONDUCTOR

Taiwan Semiconductor Manu...

1. A method of providing a chemical compound semiconductor channel layer on a substrate for use in a semiconductor fabrication
process, the method comprising:
providing a prelayer over a substrate;
providing a barrier layer over the prelayer; and
selectively forming an InAs epitaxy layer with low-growth-temperature growth and depositing at least one pair of Al(In)Sb/InAs/Al(in)Sb
at a temperature of about 300 to about 600° C. over the barrier layer to provide a chemical compound semiconductor channel
layer.

US Pat. No. 9,287,133

HARD MASK REMOVAL SCHEME

TAIWAN SEMICONDUCTOR MANU...

1. A method for hard mask layer removal, the method comprising:
dispensing a chemical on a hard mask layer, wherein the chemical comprises an acidic chemical; and
draining the chemical from a chamber,
wherein the chemical drained from the chamber is not recycled for hard mask removal.

US Pat. No. 9,281,331

HIGH DIELECTRIC CONSTANT STRUCTURE FOR THE VERTICAL TRANSFER GATES OF A COMPLEMENTARY METAL-OXIDE SEMICONDUCTOR (CMOS) IMAGE SENSOR

Taiwan Semiconductor Manu...

1. An active pixel sensor (APS) comprising:
a photodiode arranged in a semiconductor substrate, laterally adjacent to a vertical trench, wherein the photodiode is configured
to convert incident radiation to electrical charge and to accumulate the electrical charge;

a vertical-gate transfer transistor configured to selectively transfer the accumulated charge to a charge storage node for
read-out, wherein the vertical-gate transfer transistor includes a dielectric layer lining the vertical trench and a vertical
gate filling the vertical trench over the dielectric layer, wherein the dielectric layer has a dielectric constant exceeding
that of silicon dioxide, and wherein the vertical gate extends from a point over the photodiode to a point below the photodiode;

a shallow trench isolation (STI) region extending into the semiconductor substrate to a first depth, and laterally surrounding
the photodiode and the vertical-gate transfer transistor; and

a deep trench isolation (DTI) region extending into the semiconductor substrate to a second depth greater than the first depth,
laterally surrounding the STI region, and restricted to a periphery of a multi-pixel sensor array to which the APS belongs;

wherein the dielectric layer covers the STI and DTI regions and comprises an opening exposing the photodiode and source and
drain regions on opposing sides of the vertical trench.

US Pat. No. 9,275,950

BEAD FOR 2.5D/3D CHIP PACKAGING APPLICATION

Taiwan Semiconductor Manu...

1. An integrated circuit package comprising:
a multilayer interposer having one or more integrated devices mounted thereon, the interposer comprising multiple layers of
wiring structures; and

one or more metal wiring beads provided in the interposer, each of the one or more metal wiring beads comprising:
a convoluted wiring pattern that is formed in one of the multiple layers of wiring structures in the interposer; and
two terminal end segments connected to power lines in the integrated circuit package, wherein the one or more metal wiring
beads operate as power noise filters,

wherein the convoluted wiring pattern further comprises a plurality of vias, provided in a via layer between each of the multiple
layers of wiring structures, establishing electrical connection between the layers of wiring structures.

US Pat. No. 9,350,372

ARRANGEMENT FOR DIGITAL-TO-ANALOG CONVERTER

Taiwan Semiconductor Manu...

1. An arrangement for a digital-to-analog converter (DAC), comprising:
a current source configured to supply a current and comprising a first supply transistor, the first supply transistor comprising:
a first source;
a first drain; and
a first gate between the first source and the first drain, the first supply transistor having a horizontal gate layout; and
a switching element configured to switch a current of the current source between a first terminal and a second terminal, the
switching element comprising a first switching transistor, the first switching transistor comprising:

a second source;
a second drain; and
a second gate between the second source and the second drain, the first switching transistor having a vertical gate layout,
wherein a channel length of a first channel of the first supply transistor is at least three times larger than a channel length
of a second channel of the first switching transistor.

US Pat. No. 9,325,310

HIGH-SWING VOLTAGE MODE DRIVER

TAIWAN SEMICONDUCTOR MANU...

1. A high-swing voltage mode driver, comprising:
a first circuit comprising a first transistor, a second transistor and an inverter, a drain of the first transistor coupled
to a first side of the inverter and a drain of the second transistor coupled to a second side of the inverter;

a second circuit comprising a third transistor, a fourth transistor, a fifth transistor and a sixth transistor, a drain of
the third transistor coupled to a drain of the fifth transistor, a drain of the fourth transistor coupled to a drain of the
sixth transistor, the drain of the first transistor coupled to a source of the fifth transistor and the drain of the second
transistor coupled to a source of the sixth transistor; and

a third circuit comprising a seventh transistor and an eighth transistor, a source of the third transistor coupled to a drain
of the seventh transistor and a source of the fourth transistor coupled to a drain of the eighth transistor.

US Pat. No. 9,299,810

FIN-TYPE FIELD EFFECT TRANSISTOR AND METHOD OF FABRICATING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A method of fabricating a fin-type field effect transistor comprising:
forming a first semiconductor region;
forming a second semiconductor region;
forming a first fin over the first semiconductor region, the first fin comprising a first source, a first drain, and a first
channel;

forming a second fin over the second semiconductor region, the second fin comprising a second source, a second drain, and
a second channel;

masking a portion of the second semiconductor region for a first period of time;
forming a first portion of a first reacted region from the first semiconductor region during the first period of time;
removing the mask after the first period of time; and
forming a second portion of the first reacted region and a second reacted region from the portion of the second semiconductor
region during a second period of time after the first period of time, the first reacted region having a first dimension causing
a first strain in the first channel, and the second reacted region having a second dimension causing a second strain in the
second channel, the first strain substantially equal to the second strain.

US Pat. No. 9,287,350

METAL-INSULATOR-METAL CAPACITOR

TAIWAN SEMICONDUCTOR MANU...

1. A metal-insulator-metal capacitor comprising:
a bottom metal line;
a top metal line; and
an insulating material layer disposed between the bottom metal line and the top metal line, the insulating material layer
being an inter-metal-dielectric layer, wherein the top metal line comprises a first portion and a second portion, the first
portion being buried in the inter-metal-dielectric layer, and the second portion being on the inter-metal-dielectric layer.

US Pat. No. 9,287,414

INTEGRATED CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. An integrated circuit including a Schottky diode, the diode comprising:
an active region bordered by an isolation region in a semiconductor substrate of the integrated circuit, wherein a portion
of the surface of the active region is covered by a protection layer;

a first electrode comprising a first metal contact directly in contact with a surface of the active region such that an intervening
silicide contact is not connected between the first metal contact and the active region, wherein the first metal contact extends
through the protection layer to meet the surface of the active region; and

a second electrode comprising a second metal contact and a silicide contact in direct contact therewith, the silicide contact
of the second electrode being in direct contact with the surface of the active region, wherein the silicide contact is provided
on an exposed portion of the surface of the active region not covered by the protection layer.

US Pat. No. 9,275,905

METHOD OF FORMING SEMICONDUCTOR STRUCTURE WITH ANTI-PUNCH THROUGH STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor structure, comprising:
implanting a first type of dopants in a first region and a second region of a substrate;
implanting a second type of dopants in the second region of the substrate;
forming an un-doped silicon layer over the first region and the second region of the substrate;
patterning the un-doped silicon layer, the first region of the substrate, and the second region of the substrate to form a
first fin structure and a second fin structure;

forming a shallow trench isolation structure around the first fin structure and the second fin structure; and
forming a gate structure across the first fin structure and the second fin structure,
wherein the first fin structure comprises a first type of anti-punch through structure implanted with the first type of dopants
and a first un-doped silicon structure over the first type of anti-punch through structure, and the second fin structure comprises
a second type of anti-punch through structure implanted with the second type of dopants and a second un-doped silicon structure
formed over the second type of anti-punch through structure.

US Pat. No. 9,324,577

MODIFIED SELF-ALIGNED CONTACT PROCESS AND SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A method of modifying a self-aligned contact process in a semiconductor fabrication, comprising:
forming a transistor over a substrate, comprising:
depositing a high-k dielectric layer over the substrate;
depositing a work function metal layer over the high-k dielectric layer;
forming a metal gate over the work function metal layer;
forming two spacers sandwiching the work function metal layer and the metal gate; and
forming a doped region in the substrate;
etching a portion of the work function metal layer and the metal gate to leave a metal residue over inner walls of the two
spacers and over the top surface of the work function metal layer and the metal gate;

modifying the metal residue to form a metal compound;
depositing an insulator covering the metal compound; and
forming contact pads respectively electrically connected to the metal gate and the doped region.

US Pat. No. 9,305,635

HIGH DENSITY MEMORY STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor memory, comprising:
a plurality of sub banks, each sub bank comprising a row of a plurality of memory bit cells, each memory cell coupled to a
corresponding local bit line of a plurality of local bit lines, each local bit line coupled to a respective global bit line
of a plurality of global bit lines for reading/writing data from/to the plurality of memory bit cells of each sub bank;

a plurality of switch elements for each of the sub banks, wherein each switch element couples a local bit line to a corresponding
global bit line for data transmission between the local bit line and the global bit line;

a plurality of bank selection signal lines, each bank selection signal line coupled to a plurality of switch elements in a
corresponding one of the plurality of sub banks, wherein each bank selection signal line is configured to carry a bank selection
signal to select one of the plurality of the sub banks for data transmission between the local bit lines coupled to the selected
sub bank and the plurality of global bit lines.

US Pat. No. 9,287,398

TRANSISTOR STRAIN-INDUCING SCHEME

Taiwan Semiconductor Manu...

1. A transistor device, comprising:
a gate structure disposed on a semiconductor substrate;
a substantially v-shaped source/drain recess arranged in the semiconductor substrate alongside the gate structure, the source/drain
recess having a bottom tip spaced beneath an upper surface of the semiconductor substrate and having outermost edges spaced
beneath the upper surface of the semiconductor substrate on opposite sides of the bottom tip;

a doped strain-inducing region disposed within the source/drain recess, wherein the doped strain-inducing region comprises
a compound semiconductor material that is doped with n-type or p-type dopant impurities; and

an un-doped strain-inducing region disposed within the source/drain recess under the doped strain-inducing region, wherein
the un-doped strain-inducing region comprises the compound semiconductor material at a first stoichiometry near the bottom
tip of the source/drain recess, and comprises the compound semiconductor material at a second, different stoichiometry near
an outermost edge of the source/drain recess.

US Pat. No. 9,287,154

UV CURING SYSTEM FOR SEMICONDUCTORS

Taiwan Semiconductor Manu...

1. A semiconductor wafer curing system comprising:
a processing chamber;
a belt conveyor disposed in the processing chamber, the belt conveyor being configured for holding a wafer and operable to
transport the wafer through the processing chamber;

an ultraviolet (UV) radiation source disposed above the processing chamber, the UV radiation source being operable to emit
UV radiation to irradiate a wafer disposed on the belt conveyor for UV curing;

the processing chamber provided with a UV transparent window that is positioned between the belt conveyor and the UV radiation
source, wherein the UV radiation impinges on higher and lower intensity regions on a side of the UV transparent window with
higher and lower intensities of UV radiation, respectively;

wherein the UV transparent window is configured to pass at least some of the UV radiation from the UV radiation source, through
the lower intensity region, and onto the wafer on the belt conveyor;

the UV transparent window includes a UV radiation modifying section;
wherein the UV radiation modifying section has a surface area less than the surface area of the side of the UV transparent
window and is localized to the higher intensity region of the UV transparent window, and reduces the intensity of the UV radiation
passing through the radiation modifying section to the wafer on the belt conveyor; and

wherein all portions of the wafer are irradiated substantially uniformly with relatively uniform UV intensity.

US Pat. No. 9,277,195

PIXEL ARRAY WITH CLEAR AND COLOR PIXELS EXHIBITING IMPROVED BLOOMING PERFORMANCE

Taiwan Semiconductor Manu...

1. An integrated circuit (IC), comprising:
a color pixel including: a first photo-detecting element, and a color pixel access transistor to selectively couple the first
photo-detecting element to a first charge-storage node; and

a clear pixel including: a second photo-detecting element, and a clear pixel access transistor to selectively couple the second
photo-detecting element to a second charge-storage node;

wherein the color pixel access transistor is configured to transfer a first charge per unit time between the first photo-detecting
element and the first charge-storage node, and wherein the clear pixel access transistor is configured to transfer a second
charge per unit time between the clear pixel access transistor and the second charge-storage node, wherein the second charge
per unit time is greater than the first charge per unit time; and

wherein the color pixel access transistor and clear pixel access transistor have different width-to-length ratios or different
voltage thresholds from one another.

US Pat. No. 9,263,437

MECHANISMS FOR FORMING METAL-INSULATOR-METAL (MIM) CAPACITOR STRUCTURE

Taiwan Semiconductor Manu...

1. A device, comprising:
a substrate; and
a metal-insulator-metal (MIM) capacitor formed on the substrate,
wherein the MIM capacitor comprises:
a capacitor top metal (CTM) layer;
a capacitor bottom metal (CBM) layer; and
an insulator formed between the CTM layer and the CBM layer,
wherein the insulator comprises an insulating layer and a first high-k dielectric layer, and wherein the first high-k dielectric
layer is formed between the CBM layer and the insulating layer, or between the CTM layer and the insulating layer, and a thickness
of the insulating layer is larger than a thickness of the first high-k dielectric layer.

US Pat. No. 9,147,766

SEMICONDUCTOR DEVICE HAVING FIN-TYPE CHANNEL AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device having a fin-type channel, comprising:
a substrate;
a first buffer layer above at least a portion of the substrate;
a barrier layer above at least a portion of the first buffer layer;
a fin-type channel layer over the barrier layer; wherein a width of the fin-type channel layer is smaller than a width of
the first buffer layer; and

a first dielectric layer surrounding at least a portion of the fin-type channel layer,
wherein at least a portion of the fin-type channel layer protrudes from a top surface of the first dielectric layer.

US Pat. No. 9,454,684

EDGE CRACK DETECTION SYSTEM

Taiwan Semiconductor Manu...

9. An edge crack detection system, comprising:
a radio frequency identification (RFID) reader providing a command signal; and
an RFID tag wirelessly connected to the RFID reader, the RFID tag comprising an antenna completely encircling a die under
test, the antenna disposed outside a seal ring surrounding the entire periphery of the die under test, wherein the antenna
receives the command signal, produces power from the command signal, and provides a response signal based on the command signal,

wherein the RFID reader receives the response signal from the RFID tag and provides the command signal regarding the RFID
tag's self-destruction based on the response signal from the RFID tag, and the RFID tag receives the command signal and self-destructs
based on the command signal.

US Pat. No. 9,393,668

POLISHING HEAD WITH ALIGNMENT GEAR

TAIWAN SEMICONDUCTOR MANU...

1. An arrangement for driving a rolling seal clamp of a polishing head, comprising:
a body configured to be selectively pressurized; and
a first alignment gear extending from an outer circumference of a housing of the polishing head configured for polishing a
semiconductor wafer, the first alignment gear configured to be selectively mated with a first channel of a rolling seal clamp
to which the body is attached, the first alignment gear mated with the first channel when the body is in a pressurized state
and not mated with the first channel when the body is in a depressurized state.

US Pat. No. 9,391,350

RF CHOKE DEVICE FOR INTEGRATED CIRCUITS

Taiwan Semiconductor Manu...

10. A system for selectively filtering a radio frequency (RF) bandwidth, comprising:
a 3D RF choke configured to selectively filter the RF bandwidth, the 3D RF choke comprising:
a metal connection line configured as an inductive element, the metal connection line connecting to a DC power source at a
first location of the metal connection line, the metal connection line connecting to a metal RF line at a second location
of the metal connection line, the metal RF line connecting an RF input port to an RF output port; and

a capacitive element comprising:
a first ground through via connected to a ground point; and
a first signal through via connected to the metal connection line at a third location of the metal connection line.

US Pat. No. 9,372,205

UNIVERSAL PROBE CARD PCB DESIGN

Taiwan Semiconductor Manu...

16. A method comprising:
selectively transmitting first testing signals to a membrane core through a portion of a plurality of signal channels on a
printed circuit board (PCB), and transmitting second testing signals to the membrane core through a portion of the signal
channels on the PCB,

wherein the signal channels through which the first testing signals are transmitted are different from the signal channels
through which the second testing signals are transmitted,

wherein the membrane core is inserted into an opening defined by a plurality of first signal pads on the PCB.
US Pat. No. 9,287,125

MULTIPLE EDGE ENABLED PATTERNING

Taiwan Semiconductor Manu...

1. A method, comprising:
forming a first pattern on a wafer, the first pattern extending in a first direction;
forming a second pattern on the wafer, the second pattern extending in the first direction and being separated from the first
pattern by a first distance measured in a second direction perpendicular to the first direction; and

forming a third pattern on the wafer, the third pattern being separated from the first pattern by a second distance measured
in the first direction, the third pattern being separated from the second pattern by a third distance measured in the first
direction;

wherein the first distance is approximately equal to the third distance; and
wherein the second distance is less than twice the first distance.

US Pat. No. 9,281,311

MEMORY CELL ARRAY INCLUDING A WRITE-ASSIST CIRCUIT AND EMBEDDED COUPLING CAPACITOR AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

17. A method of forming a memory cell array, the method comprising:
forming a plurality of bit lines of the memory cell array in a first metal layer;
forming a plurality of word lines of the memory cell array in a second metal layer; and
forming the at least one embedded coupling capacitor from at least two conductive traces disposed in a third metal layer,
wherein forming the at least one embedded coupling capacitor includes:

coupling a first conductive trace of the at least two conductive traces to a driving source node of a write-assist circuit
and

coupling a second conductive trace of the at least two conductive traces to an enable input of the write-assist circuit, wherein
the write-assist circuit comprises at least two serially coupled inverters, a capacitor having a first node coupled to an
output of the at least two serially coupled inverters and a second node coupled to the driving source node, and a metal oxide
semiconductor transistor having a source coupled to the driving source node and a drain coupled to at least one of the plurality
of bit lines.

US Pat. No. 9,276,108

MEMORY CELL ARRAY AND CELL STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor read-only memory (ROM) unit cell structure comprising:
a cell base region defining a cell boundary, comprising a blanket OD layer having a wide-block profile disposed on a substrate
and defining a continuous common source node, arranged in selective connection with a ground (Vss);

a drain pad disposed above the OD layer selectively connected with a bit line;
a vertical channel structure bridging the drain pad and the OD layer; and
a gate structure disposed vertically between the drain pad and the OD layer and connected with a word-line;
wherein the cell boundary is defined within the coverage of the OD layer.

US Pat. No. 9,269,485

METHOD OF CREATING SPIRAL INDUCTOR HAVING HIGH Q VALUE

TAIWAN SEMICONDUCTOR MANU...

1. An inductor structure, comprising:
a silicon wafer;
a dielectric layer formed on the silicon wafer;
a spirally patterned conductor layer formed over and in the silicon wafer and in the dielectric layer to form metal-containing
layers, the spirally patterned conductor layer forming a planar spiral inductor;

a via hole formed over and in the silicon wafer and in the metal-containing layers within the spirally patterned conductor
layer, wherein the via hole is formed by a through silicon via (TSV) process and is formed through the silicon wafer; and

a core layer filling the via hole, wherein the core layer extends from a bottom surface of the silicon wafer to a top surface
of the metal-containing layers, and the core layer is insulated from the spirally patterned conductor layer and surrounded
by the spirally patterned conductor layer.

US Pat. No. 9,263,316

METHOD FOR FORMING A SEMICONDUCTOR DEVICE WITH VOID-FREE SHALLOW TRENCH ISOLATION

Taiwan Semiconductor Manu...

1. A method of fabricating a semiconductor device, the method comprising:
providing a semiconductor substrate;
forming a barrier layer over the semiconductor substrate;
forming a trench by etching through the barrier layer and a portion of the semiconductor substrate;
partially filling the trench with an isolation oxide, wherein the remaining portion of the trench comprises an opening and
an empty space below the opening, and an overhang is formed at a top portion of the trench after the isolation oxide is formed
partially filling the trench to shrink the opening; and

filling the remaining portion of the trench with a spin coating material.

US Pat. No. 9,257,636

PERPENDICULAR MAGNETIC RANDOM-ACCESS MEMORY (MRAM) FORMATION BY DIRECT SELF-ASSEMBLY METHOD

Taiwan Semiconductor Manu...

1. A method of forming a magnetic memory cell, comprising:
forming a heterostructure over a layer of dielectric material disposed over a substrate, wherein the heterostructure comprises
first and second ferromagnetic layers which are separated by an insulating layer;

forming a pattern of polymer pillars over the heterostructure, wherein a pillar comprises a cylindrical shape;
etching through the heterostructure by utilizing the pattern of polymer pillars as a hardmask, thereby forming a pattern of
magnetic memory cells within the heterostructure;

depositing a sidewall material over the etched heterostructure; and
etching the sidewall material to remove portions of the sidewall material horizontally-disposed on a surface of the first
ferromagnetic layer or the second ferromagnetic layer, while leaving portions of the sidewall material vertically-disposed
adjacent to sidewalls of the first ferromagnetic layer or the second ferromagnetic layer and the insulating layer substantially
intact.

US Pat. No. 9,305,837

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor arrangement, the method comprising:
forming a first metal trace in a first dielectric opening in a dielectric layer, the first metal trace having a first metal
trace width between about 30 nm to about 60 nm and a first metal trace length; and

forming a second metal trace in a second dielectric opening in the dielectric layer, the second metal trace having a second
metal trace width between about 10 nm to about 20 nm and second metal trace length, the first metal trace length different
than the second metal trace length, such that the dielectric layer has a dielectric layer width between the first metal trace
and the second metal trace between about 10 nm to about 20 nm.

US Pat. No. 9,287,280

METHOD TO IMPROVE MEMORY CELL ERASURE

Taiwan Semiconductor Manu...

1. A semiconductor structure of a split gate flash memory cell, said semiconductor structure comprising:
a semiconductor substrate including a first source/drain region and a second source/drain region;
an erase gate located over the first source/drain region; and
a floating gate and a word line located over the semiconductor substrate between the first and second source/drain regions,
wherein the floating gate is arranged between the word line and the erase gate, and wherein the floating gate includes a pair
of protrusions extending vertically up from a top surface of the floating gate and arranged on opposing sides, respectively,
of the floating gate.

US Pat. No. 9,285,394

TESTING APPARATUS AND METHOD

Taiwan Semiconductor Manu...

17. A method for testing a device under test (DUT), the method comprising:
disposing the DUT on at least one probe; and
moving a plurality of variable-length pushers to push against the DUT, such that the variable-length pushers are individually
compressed by different zones of the DUT to fit a shape of the DUT, and the DUT is forced to be in electrical contact with
the probe.

US Pat. No. 9,281,192

CMP-FRIENDLY COATINGS FOR PLANAR RECESSING OR REMOVING OF VARIABLE-HEIGHT LAYERS

Taiwan Semiconductor Manu...

1. A method of manufacturing an integrated circuit device, comprising:
processing a wafer through a series of operations to form a topographically variable layer of a material on the wafer, wherein
the topographically variable layer varies in height across the wafer;

spin coating a monomer-containing solvent solution over a surface of the topographically variable layer;
heating the wafer to within a first temperature range;
maintaining the wafer within the first temperature range while a majority of the solvent evaporates from the solution;
heating the wafer to within a second temperature range that is above the first temperature range;
maintaining the wafer within the second temperature range until the monomers have polymerized to form a polymer coating and
the polymers in the coating have cross-linked;

performing chemical mechanical polishing (CMP) to remove a first portion of the polymer coating; and
etching to effectuate a top-down recessing of the polymer coating.

US Pat. No. 9,269,733

IMAGE SENSOR DEVICE WITH IMPROVED QUANTUM EFFICIENCY

TAIWAN SEMICONDUCTOR MANU...

10. A method for fabricating a semiconductor device, the method comprising:
providing a substrate;
forming a wiring layer on the substrate;
forming a first semiconductor layer on the wiring layer, the first semiconductor layer having a light-sensing portion;
forming a switching element on the first semiconductor layer, wherein the switching element and the light-sensing portion
are staggered;

forming a plurality of microstructures at a side face area of the first semiconductor layer corresponding to the light-sensing
portion; and

forming a second semiconductor layer on the microstructures and the switching element.

US Pat. No. 9,267,988

ON-CHIP EYE DIAGRAM CAPTURE

Taiwan Semiconductor Manu...

1. An eye diagram capture device, which comprises:
a delay line arranged to receive a digital signal and output a time delayed version of the digital signal;
an edge detection circuit arranged to receive the digital signal and the time delayed version of the digital signal, the edge
detection circuit operating to output a signal corresponding to a voltage of the digital signal received, which is stable
before a leading edge of the time delayed version of the digital signal; and,

a voltage comparator arranged to receive the digital signal and a reference voltage, the voltage comparator operating to output
a first signal when the voltage of the digital signal and the reference voltage are equal to each other.

US Pat. No. 9,169,117

MEMS DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method of forming a Micro Electro Mechanical System (MEMS) device, comprising:
providing a substrate;
forming a catalyst layer over the substrate;
patterning the catalyst layer;
forming a carbon nanotube based on the catalyst layer;
forming a getter layer over the carbon nanotube and the substrate; and
etching back the getter layer to expose the carbon nanotube.

US Pat. No. 9,461,069

SYSTEMS AND METHODS FOR INTEGRATING DIFFERENT CHANNEL MATERIALS INTO A CMOS CIRCUIT BY USING A SEMICONDUCTOR STRUCTURE HAVING MULTIPLE TRANSISTOR LAYERS

Taiwan Semiconductor Manu...

1. A multilayer semiconductor structure having a layout footprint with a first region and a non-overlapping second region
and different transistor types fabricated using different channel material, the semiconductor structure comprising:
a first transistor layer comprising a first type of channel material in the first region but no channel material in the second
region;

a second transistor layer comprising a second type of channel material in the second region but no channel material in the
first region, the second transistor layer vertically elevated above the first transistor layer;

a first transistor fabricated on the first transistor layer; and
a second transistor fabricated on the second transistor layer, wherein the first transistor is interconnected with the second
transistor to form a circuit.

US Pat. No. 9,263,330

SEMICONDUCTOR DEVICE, METHOD FOR FORMING CONTACT AND METHOD FOR ETCHING CONTINUOUS RECESS

Taiwan Semiconductor Manu...

1. A method for forming a continuous contact plug, comprising:
forming a first dielectric layer over a substrate;
forming a second dielectric layer over the first dielectric layer;
patterning the second dielectric layer to form a first recess;
patterning the first dielectric layer by a first etchant through the first recess to form a second recess,
wherein the first etchant has a higher etching rate with respect to the first dielectric layer than with respect to the second
dielectric layer and further wherein the second recess is aligned with the first recess; and

forming the continuous contact plug in the first recess and the second recess.

US Pat. No. 9,153,343

MEMORY DEVICE HAVING RRAM-BASED NON-VOLATILE STORAGE ARRAY

TAIWAN SEMICONDUCTOR MANU...

1. A device comprising:
a storage region comprising:
a first storage array comprising a plurality of first storage cells; and
a second storage array comprising a plurality of second storage cells configured to be in place of the first storage cells;
and

a resistive-read-access-memory-based (RRAM-based or ReRAM-based) non-volatile storage array configured to record at least
one corresponding relationship between the first storage cells and the second storage cells.

US Pat. No. 9,087,759

METHOD OF FORMING AN IMAGE SENSOR DEVICE AND METHOD OF FORMING THE SAME

Taiwan Semiconductor Manu...

1. A method, comprising:
providing a carrier wafer having a pixel area and a peripheral area;
stacking a first image sensing structure on the carrier wafer, the first image sensing structure having a first portion in
the pixel area for sensing incident light in a red color wavelength band and a second portion in the peripheral area;

forming a first conductive through-silicon via (TSV) in the second portion of the first image sensing structure;
forming a first conductive bump structure on the first conductive TSV;
stacking a second image sensing structure above the first image sensing structure and on the first conductive bump structure,
the second image sensing structure having a third portion in the pixel area for sensing incident light in a green color wavelength
band and a fourth portion in the peripheral area;

forming a second conductive TSV in the fourth portion of the second image sensing structure;
forming a second conductive bump structure on the second conductive TSV; and
stacking a third image sensing structure above the second image sensing structure and on the second conductive bump structure,
the third image sensing structure having a fifth portion in the pixel area for sensing incident light in a blue color wavelength
band and a sixth portion in the peripheral area.

US Pat. No. 9,397,040

SEMICONDUCTOR DEVICE COMPRISING METAL PLUG HAVING SUBSTANTIALLY CONVEX BOTTOM SURFACE

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a dielectric layer;
a metal plug over a substrate, the metal plug having a contact bottom surface that is substantially convex;
a metal layer in contact with sidewalls of the dielectric layer and between the dielectric layer and the metal plug; and
a silicide layer between the substrate and the metal plug, wherein:
the silicide layer has a silicide layer top surface that is substantially concave to interface with the substantially convex
contact bottom surface of the metal plug; and

the metal layer terminates at an edge of the silicide layer.

US Pat. No. 9,317,650

DOUBLE PATTERNING TECHNOLOGY (DPT) LAYOUT ROUTING

TAIWAN SEMICONDUCTOR MANU...

1. A system for determining double patterning technology (DPT) layout routing compliance, comprising:
a layout routing component configured to:
create a first pin group comprising a first set of one or more pre-colored pins that are linked together by a first set of
internal conflict spaces;

associate the first pin group with a first phantom assisted feature (AF) mask polygon, the associating comprising:
selecting a first pre-colored pin from the first set of one or more pre-colored pins;
determining a first mask assignment associated with the first pre-colored pin; and
assigning the first phantom AF mask polygon to a different mask than a mask for the first pre-colored pin according to the
first mask assignment;

create a pin loop based on the first pre-colored pin and the phantom AF mask polygon;
assign a pin loop value to the pin loop; and
determine whether a double patterning technology (DPT) violation is present for the pin loop based on the pin loop value.

US Pat. No. 9,305,135

GENERATING A SEMICONDUCTOR COMPONENT LAYOUT

TAIWAN SEMICONDUCTOR MANU...

1. A method comprising:
generating, by a processor, a first set of configurations of a layout of semiconductor components, the configurations of the
first set of configurations each satisfying a first sub-set of a set of design rules, the first sub-set of the set of design
rules comprising a first quantity of design rules, the first quantity of design rules being less than a second quantity of
design rules included in the set of design rules;

generating, by the processor, a second set of configurations of the layout of semiconductor components, the second set of
configurations being generated by eliminating one or more configurations of the first set of configurations based on a determination
that the eliminated one or more configurations of the first set of configurations fail to satisfy a second sub-set of the
set of design rules, the second sub-set of the set of design rules comprising one or more of the design rules included in
the set of design rules other than the design rules included in the first sub-set of the set of design rules; and

manufacturing a semiconductor device having semiconductor components arranged based on one of the configurations of the second
set of configurations.

US Pat. No. 9,281,273

DESIGNED-BASED INTERCONNECT STRUCTURE IN SEMICONDUCTOR STRUCTURE

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a plurality of gate structures extending in a first direction formed over a substrate;
a contact formed adjacent to the gate structures over the substrate; and
a plurality of metal layers formed over the gate structures, wherein some of the metal layers comprise metal lines extending
in the first direction, and some of the metal layers comprise metal lines extending in a second direction substantially perpendicular
to the first direction,

wherein the gate structures follow the following equation:

wherein Pgate min is the minimum value among gate pitches of the gate structures;

Lgate min is the minimum value among gate lengths of the gate structures; and

Hgate min is the minimum value among gate heights of the gate structures.

US Pat. No. 9,238,578

SEMICONDUCTOR ARRANGEMENT WITH STRESS RELEASE AND THERMAL INSULATION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement, comprising:
a complementary metal-oxide-semiconductor (CMOS) wafer;
a microelectromechanical systems (MEMS) wafer formed over the CMOS wafer, the MEMS wafer comprising a high vacuum chamber
configured as a sensing gap between a membrane of the MEMS wafer and a poly layer of the MEMS wafer;

a cap wafer formed over the MEMS wafer; and
an ambient pressure chamber formed between the MEMS wafer and the cap wafer.

US Pat. No. 9,236,273

UV PROTECTION FOR LIGHTLY DOPED REGIONS

Taiwan Semiconductor Manu...

1. An integrated circuit device, comprising:
a semiconductor body;
a bipolar junction transistor comprising a lightly doped region within the semiconductor body;
a plurality of metal interconnect layers disposed over the bipolar junction transistor; and
a UV barrier layer disposed over the metal interconnect layers.

US Pat. No. 9,287,276

MEMORY CELL ARRAY

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor memory cell array comprising:
a memory cell unit comprising:
an active region;
a first transistor formed on the active region;
a second transistor formed on the active region;
a gate structure formed on the active region and between the first transistor and the second transistor, and configured to
be biased by a power line to electrically isolate the first transistor from the second transistor; and

an interconnect connecting the gate structure and at least one of sources of the first transistor and the second transistor
to the power line.

US Pat. No. 9,287,403

FINFET AND METHOD FOR MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

1. A FinFET, comprising:
a fin structure over a substrate;
a gate stack across the fin structure;
a pair of first spacers on sidewalls of the gate stack; and
a source/drain region in the fin structure not covered by the gate stack;
a doped region in the fin structure and adjacent to the source/drain region;
a contact etch stop layer over the source/drain region; and
an interlayer dielectric layer over the contact etch stop layer,
wherein the gate stack covers top surfaces of the first spacers.

US Pat. No. 9,281,287

SEMICONDUCTOR BONDING STRUCTURE AND PROCESS

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
a passivation layer on a substrate;
a first eutectic bonding material at least partially over the passivation layer, the first eutectic bonding material further
comprising:

an initiating portion with a first composition; and
a halting portion surrounding the initiating portion, the halting portion having a second composition different from the first
composition; and

a block laterally separated from the first eutectic bonding material, wherein the block comprises a first material, wherein
the halting portion comprises the first material.

US Pat. No. 9,281,196

METHOD TO REDUCE ETCH VARIATION USING ION IMPLANTATION

Taiwan Semiconductor Manu...

1. A method of forming a transistor device, comprising:
forming first and second well regions within a semiconductor substrate, the first and second well regions having first and
second etch rates, respectively, which are different from one another for a pre-determined etch;

selectively implanting dopants into the first well region to alter the first etch rate to make the first etch rate substantially
equal to the second etch rate; and

concurrently etching both the first, selectively implanted well region and the second well region using the pre-determined
etch to form channel recesses having equal recess depths.

US Pat. No. 9,281,475

RESISTIVE RANDOM-ACCESS MEMORY (RRAM) WITH MULTI-LAYER DEVICE STRUCTURE

Taiwan Semiconductor Manu...

1. A resistive memory comprising:
a first electrode and a second electrode; and
a multi-layer resistance-switching network disposed between the first electrode and the second electrode, the multi-layer
resistance-switching network comprising:

a group-IV element doping layer;
a first carbon doping layer disposed between the group-IV element doping layer and the first electrode; and
a second carbon doping layer disposed between the group-IV element doping layer and the second electrode.

US Pat. No. 9,275,923

BAND PASS FILTER FOR 2.5D/3D INTEGRATED CIRCUIT APPLICATIONS

Taiwan Semiconductor Manu...

1. A filter, comprising:
a polymer package and common molding compound that collectively form a body;
a passive device chip disposed within the body, and comprising a plurality of capacitors;
a transceiver chip disposed within the body, and comprising a plurality of active devices; and
a plurality of transmission lines, which electrically connect the passive device chip and the transceiver chip to a solder
bump or pin arranged on an outer surface of the body;

wherein the polymer package is arranged over respective upper surfaces of the passive device chip, the transceiver chip, and
the common molding compound;

wherein a first subset of the plurality of capacitors are connected in series along a path extending continuously between
an input and an output of the filter, and wherein respective capacitors are coupled by respective nodes on the path; and

wherein a second subset of the plurality of capacitors are connected in parallel between the respective nodes and a ground
terminal.

US Pat. No. 9,252,217

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

Taiwan Semiconductor Manu...

11. A method of forming a semiconductor arrangement, comprising:
forming a first opening having a first opening width in a first dielectric layer, the first dielectric layer over a substrate;
forming a first portion of a semiconductor column in the first opening, the first portion comprising a first material, the
first portion having a first portion width substantially equal to the first opening width;

forming a second dielectric layer around the first portion, such that a top surface of the second dielectric layer is above
a top surface of the first portion and a second opening is defined in the second dielectric layer above the first portion,
where the second opening has a second opening width substantially equal to the first opening width; and

forming a second portion of the semiconductor column over the first portion in the second opening, the second portion comprising
a second material different than the first material, the second portion having a second portion width substantially equal
to the first opening width.

US Pat. No. 9,490,288

IMAGE SENSOR WITH TRENCHED FILLER GRID WITHIN A DIELECTRIC GRID INCLUDING A REFLECTIVE PORTION, A BUFFER AND A HIGH-K DIELECTRIC

Taiwan Semiconductor Manu...

1. An image sensor, comprising:
a photodiode array over a substrate;
a dielectric grid over the photodiode array and comprising a first dielectric structure and a second dielectric structure;
a reflective portion between the first dielectric structure and the second dielectric structure;
a filler grid comprising a first filler structure between the first dielectric structure and the second dielectric structure,
the first filler structure over a first photodiode of the photodiode array;

a buffer laterally between the reflective portion and the first dielectric structure, the buffer in direct physical contact
with the first filler structure and the buffer comprising a different material composition than the first dielectric structure
and the second dielectric structure; and

a high-k dielectric laterally between the buffer and the first dielectric structure.

US Pat. No. 9,425,085

STRUCTURES, DEVICES AND METHODS FOR MEMORY DEVICES

Taiwan Semiconductor Manu...

1. A static random access memory (SRAM) device comprising:
first, second, and third conductive layers;
a first word line disposed in the first conductive layer;
a first landing pad disposed in the first conductive layer;
a second word line disposed in the second conductive layer and coupled to the first landing pad;
a second landing pad disposed in the first conductive layer;
a third word line disposed in the third conductive layer and coupled to the second landing pad; and
an SRAM cell coupled to the first word line and the first and second landing pads, wherein at least two of the second conductive
layer, the third conductive layer, and the first conductive layer are disposed one above the other.

US Pat. No. 9,425,091

METHOD FOR FORMING SEMICONDUCTOR STRUCTURE

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor structure, comprising:
forming a first etch stop layer (ESL);
forming an oxide region above the first ESL;
forming a low-k (LK) dielectric region above the oxide region;
forming a first metal line through at least one of the first ESL, the oxide region, or the LK dielectric region;
forming a second metal line through at least one of the first ESL, the oxide region, or the LK dielectric region;
forming a second ESL over at least one of the first metal line, the second metal line, or the LK dielectric region;
removing at least a portion of the second ESL at least one of:
over at least one of the first metal line or the second metal line; or
between the first metal line and the second metal line;
forming a gap by removing at least one of:
at least a portion of the oxide region between the first metal line and the second metal line; or
at least a portion of the LK dielectric region between the first metal line and the second metal line; and
forming an ESL seal region over at least one of the second ESL, the first metal line, the second metal line, or the gap.

US Pat. No. 9,338,834

SYSTEMS AND METHODS FOR MICROWAVE-RADIATION ANNEALING

Taiwan Semiconductor Manu...

1. A method for annealing a semiconductor structure using microwave radiation, the semiconductor structure including a top
portion and a bottom portion, the method comprising:
providing a semiconductor structure;
providing one or more energy-converting materials capable of increasing the semiconductor structure's absorption of microwave
radiation;

applying microwave radiation to the energy-converting materials and the semiconductor structure to anneal the semiconductor
structure for fabricating semiconductor devices;

detecting first local temperatures associated with one or more first zones of the semiconductor structure, wherein the first
zones are disposed in the top portion;

adjusting the microwave radiation applied to the energy-converting materials and the semiconductor structure based at least
in part on the detected first local temperatures;

detecting second local temperatures associated with one or more second zones of the semiconductor structure, wherein the second
zones are disposed in the bottom portion; and

adjusting the microwave radiation applied to the energy-converting material and the semiconductor structure based at least
in part on the detected second local temperatures.

US Pat. No. 9,290,376

MEMS PACKAGING TECHNIQUES

Taiwan Semiconductor Manu...

1. A microelectromechanical systems (MEMS) package comprising:
a MEMS IC comprising a MEMS substrate, a dielectric layer disposed over the MEMS substrate, and a piezoelectric layer disposed
over the dielectric layer, wherein the dielectric layer includes a flexible diaphragm made of dielectric material and wherein
the piezoelectric layer includes a piezoelectric layer opening over the flexible diaphragm;

a CMOS IC comprising a CMOS substrate and an electrical interconnect structure, wherein the CMOS IC is bonded to the MEMS
IC so the electrical interconnect structure is proximate to the piezoelectric layer and so the CMOS IC encloses a back cavity
over the flexible diaphragm; and

a support layer disposed between the electrical interconnect structure and the piezoelectric layer, the support layer having
a support layer opening which is disposed at a position vertically aligned with the flexible diaphragm and which is a part
of the back cavity.

US Pat. No. 9,291,913

PATTERN GENERATOR FOR A LITHOGRAPHY SYSTEM

Taiwan Semiconductor Manu...

14. A method for fabricating a resist pattern, the method comprising:
receiving a substrate;
depositing a resist film on the substrate;
exposing the resist film deposited on the substrate according to a pattern generator (PG), wherein the pattern generator includes:
a mirror array plate having a mirror;
an insulator layer disposed over the mirror array plate;
an electrode plate disposed over the insulator plate, where in the electrode plate includes a first conducting layer and a
second conducting layer; and

a lens let formed over the mirror, wherein the lens let includes a non-straight sidewall formed in the electrode plate; and
forming the resist pattern on the substrate by developing the exposed resist film.

US Pat. No. 9,292,030

ELECTRONIC CIRCUIT HAVING BAND-GAP REFERENCE CIRCUIT AND START-UP CIRCUIT, AND METHOD OF STARTING-UP BAND-GAP REFERENCE CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A circuit, comprising:
a band-gap reference circuit comprising:
an operational amplifier having an output, a first input, and a second input;
a first current path between a power supply node and a reference node, the first input of the operational amplifier being
coupled to the first current path;

a second current path between the power supply node and the reference node, the second input of the operational amplifier
being coupled to the second current path; and

a feedback path between the output of the operational amplifier and the first current path and the second current path; and
a start-up circuit comprising:
a current source; and
at least one switch coupled between the current source and the band-gap reference circuit, the at least one switch being configured
to electrically couple the current source with the first current path and the second current path during a start-up phase,
and to electrically decouple the current source from the first current path and the second current path after the start-up
phase.

US Pat. No. 9,287,171

METHOD OF MAKING A CONDUCTIVE PILLAR BUMP WITH NON-METAL SIDEWALL PROTECTION STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method of making a semiconductor device, the method comprising:
forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region;
forming a conductive pillar over the UBM layer, the conductive pillar comprising sidewalls, wherein the conductive pillar
exposes the surface region of the UBM layer;

forming a barrier layer over the conductive pillar; and
forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure
contacts the surface region of the UBM layer, the barrier layer is between the non-metal protective structure and the conductive
pillar, and the non-metal protective structure exposes the sidewalls of the UBM layer.

US Pat. No. 9,286,979

METHOD AND STRUCTURE FOR RESISTIVE SWITCHING RANDOM ACCESS MEMORY WITH HIGH RELIABLE AND HIGH DENSITY

Taiwan Semiconductor Manu...

1. An apparatus comprising:
a memory device that includes a resistive material layer having filament features with a filament ratio that is equal to or
greater than about 0.5, wherein the filament features has a size distribution with a characteristic size Sm, wherein the filament features includes a first subset features each with a radius less than Sm and a second subset features each with a radius greater than Sm, and wherein the filament ratio is defined as As/(As+Al), wherein As is a first sum of sectional areas of the first subset features and Al is a second sum of sectional areas of the second subset features.

US Pat. No. 9,281,297

SOLUTION FOR REDUCING POOR CONTACT IN INFO PACKAGES

Taiwan Semiconductor Manu...

1. A method comprising:
forming a first package, wherein the first package comprises:
a dielectric layer;
a plurality of redistribution lines in the dielectric layer;
a device die over and electrically coupled to the plurality of redistribution lines;
a molding material molding the device die therein; and
a through-via penetrating through the molding material;
disposing a spacer to attach to a first one of the first package and a second package;
disposing an additional spacer attached to a second one of the first package and the second package; and
bonding the first package to the second package, with the spacer aligned to the additional spacer, wherein the spacer is located
between the first package and the second package.

US Pat. No. 9,281,968

DIFFERENTIAL CIRCUIT SYSTEM

GLOBAL UNICHIP CORPORATIO...

1. A differential circuit system in an integrated circuit, connected to an external power source for receiving an external
voltage and a ground voltage, the differential circuit system comprising:
a differential circuit set, comprising a plurality of differential circuits connected between a first node and a second node,
wherein each of the plurality of the differential circuits generates a current flowing from the first node to the second node,
wherein the first node supplies a high voltage and the second node supplies a low voltage and the first node receives the
external voltage;

a voltage regulator, for generating the low voltage according to a first voltage and supplying the low voltage to the second
node; and

a current drainage circuit set, connected between the second node and the ground voltage, for generating a drainage current,
wherein a superposed current flowing to the voltage regulator is equivalent to summation of a plurality currents outputted
by the plurality of differential circuits minuses the drainage current.

US Pat. No. 9,281,203

SILICON DOT FORMATION BY DIRECT SELF-ASSEMBLY METHOD FOR FLASH MEMORY

Taiwan Semiconductor Manu...

15. A method, comprising:
providing a copolymer solution comprising first and second polymer species over a substrate;
annealing the substrate and the copolymer solution, which results in a self-assembly of the copolymer solution into a phase-separated
material, wherein the first polymer species forms a polymer matrix, and the second polymer species forms a second polymer
pattern within the polymer matrix;

removing the second polymer species from the polymer matrix, which replaces the second polymer pattern with a substantially
identical pattern of holes within the polymer matrix; and

implanting a dopant into the substrate using the polymer matrix having the holes therein as a hard mask to block the dopant
and to form a plurality of discrete data storage elements within the substrate.

US Pat. No. 9,264,219

CLOCK AND DATA RECOVERY CIRCUIT AND METHOD

GLOBAL UNICHIP CORPORATIO...

1. A clock and data recovery circuit, comprising:
a data analysis module configured to generate an error signal according to an input data, a first clock signal, and a second
clock signal;

a loop filter module configured to generate a first corrective signal according to the error signal, a phase threshold value,
and a frequency threshold value; and

a phase adjust module configured to generate the first clock signal and the second clock signal according to the first corrective
signal,

wherein the loop filter module is further configured to accumulate the error signal to generate an accumulated value, and
to compare the accumulated value with an accumulated threshold value to dynamically adjust the accumulated threshold value,
the phase threshold value, and the frequency threshold value.

US Pat. No. 9,263,293

FLASH MEMORY STRUCTURE AND METHOD FOR FORMING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor structure, comprising:
a substrate;
a floating gate having a first sidewall and a second sidewall formed over the substrate;
an insulating layer formed over the substrate to cover the first sidewall and an upper portion of the second sidewall of the
floating gate;

a control gate formed over the insulating layer;
a first spacer formed on a first sidewall of the control gate over the floating gate, wherein a bottom surface of the first
spacer directly contacts the second sidewall of the floating gate; and

a second spacer formed on a second sidewall of the control gate,
wherein the floating gate is formed in a shark's fin shape, and a top surface of the control gate connecting the first sidewall
and the second sidewall of the control gate has a step-like profile.

US Pat. No. 9,287,172

INTERPOSER-ON-GLASS PACKAGE METHOD

Taiwan Semiconductor Manu...

1. A method comprising:
providing an interposer comprising:
a substrate; and
a first through-substrate via (TSV) penetrating through the substrate;
forming a first oxide layer on a surface of the interposer;
bonding a glass substrate to the interposer through a fusion bonding, with the first oxide layer being between the interposer
and the glass substrate; and

forming a second TSV in the glass substrate and electrically coupled to the first TSV.

US Pat. No. 9,280,046

METHOD OF FABRICATING MASK

Taiwan Semiconductor Manu...

1. A method for fabricating an extreme ultraviolet (EUV) mask, the method comprising:
providing a low thermal expansion material (LTEM) layer;
forming a reflective multiple-layer (ML) over the LTEM layer;
forming a conductive layer over an opposite surface of the LTEM layer;
spin-coating a flowable-photosensitive-absorption-layer (FPhAL) over the reflective ML, wherein the FPhAL contains at least
one of HfO2 and Al2O3; and

patterning the FPhAL by a lithography process to form a patterned absorption layer having a first region and a second region,
wherein the FPhAL is removed in the first region and remains in the second region.

US Pat. No. 9,275,710

THREE DIMENSIONAL CROSS-ACCESS DUAL-PORT BIT CELL DESIGN

Taiwan Semiconductor Manu...

1. A semiconductor memory, comprising:
a dual-port memory array having a plurality of cross-access dual-port bit cells arranged in a plurality of rows and a plurality
of columns, wherein each of the plurality of cross-access dual-port bit cells has two cross-access ports for reading and writing
one or more bits of data to the cross-access dual port bit cell;

a pair of word lines associated with at least one of the plurality of rows of the dual-port memory array, wherein the pair
of word lines is configured to carry a pair of row selection signals for enabling one or more read and write operations on
one or more cross-access dual-port bit cells in the row;

a pair of column selection lines associated with at least one of the plurality of columns of the dual port memory array, wherein
the pair of column selection lines is configured to carry a pair of column selection signals for enabling the cross-access
dual-port bit cells in the column during the read and write operations;

a PMOS transistor and an NMOS transistor for each of the cross-access ports of the cross-access dual-port bit cell, wherein
the PMOS transistor is configured to have its source coupled to one of the word lines and its drain coupled to an output node
of the cross-access port, wherein the NMOS transistor is configured to have its source coupled to a low-voltage source and
its drain coupled to the output node, wherein gates of the transistors are configured to be coupled together and controlled
by one of the column selection lines so that only one of the cross-access ports of the cross-access dual-port bit cell is
enabled during a read and/or a write operation.

US Pat. No. 9,276,010

DUAL SILICIDE FORMATION METHOD TO EMBED SPLIT GATE FLASH MEMORY IN HIGH-K METAL GATE (HKMG) TECHNOLOGY

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) comprising:
a semiconductor substrate including a periphery region and a memory cell region;
a high-k metal gate (HKMG) gate electrode disposed on the periphery region;
a first memory cell disposed on the memory cell region, comprising a select gate (SG) and a memory gate (MG);
a silicide layer disposed on a SG top surface or a MG top surface of the first memory cell;
a hard mask layer in contact with an upper surface of the HKMG gate electrode; and
metal contacts extending into the silicide layer on the SG top surface or the MG top surface.

US Pat. No. 9,257,438

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device structure, comprising:
a substrate, wherein the substrate has a cell region and a logic region;
an isolation feature formed in the substrate;
a first gate stack structure formed on the isolation feature and at the cell region;
a second gate stack structure formed on the isolation feature and at the cell region, wherein the first gate stack structure
is adjacent to the second gate stack structure; and

a capping layer formed on the isolation feature between the first gate stack structure and the second gate stack structure,
wherein the entire capping layer has a height that is less than half the height of the first gate stack structure, and a lateral
external sidewall of the entire capping layer is in direct contact with a lateral sidewall of the first gate stack structure,
and a top of the lateral external sidewall of the entire capping layer is below a top of the lateral sidewall of the first
gate stack structure,

wherein the isolation feature between the first gate stack structure and the second gate stack structure has a substantially
planar topography.

US Pat. No. 9,177,924

VERTICAL NANOWIRE TRANSISTOR FOR INPUT/OUTPUT STRUCTURE

Taiwan Semiconductor Manu...

1. A system for protecting a circuit from an electrostatic discharge (ESD) voltage, the system comprising:
an input terminal for receiving an input signal;
an ESD protection circuit configured to receive the input signal from the input terminal, the ESD protection circuit including
one or more vertical nanowire field effect transistors (FETs), wherein each of the one or more vertical nanowire FETs includes:

a well of a first conductivity type that is formed in a semiconductor substrate,
a nanowire having i) a source region at a first end of the nanowire, and ii) a drain region at a second end of the nanowire
that is opposite the first end, the source region further including a portion formed in the well, wherein the source region
and the drain region are of a second conductivity type such that a PN junction is formed between the well and the portion
of the source region formed in the well, and

a gate region surrounding a portion of the nanowire, wherein the gate region is separated from the drain region by a first
distance, the separation of the gate region and the drain region providing a resistance in series between the drain region
and the source region; and

an output terminal configured to receive the input signal from the ESD protection circuit, wherein an ESD-induced voltage
in the input signal is attenuated by the resistance and the PN junction.

US Pat. No. 9,130,531

SEMICONDUCTOR ARRANGEMENT WITH THERMAL INSULATION CONFIGURATION

Taiwan Semiconductor Manu...

1. A method for forming a semiconductor arrangement, comprising:
forming a microelectromechanical systems (MEMS) wafer comprising a thermal insulator air gap between a sensing layer and a
membrane;

bonding the MEMS wafer to a complementary metal-oxide-semiconductor (CMOS) wafer;
forming an ambient pressure chamber between the CMOS wafer and the membrane of the MEMS wafer, the ambient pressure chamber
exposed to ambient air; and

bonding a cap wafer to the MEMS wafer, the cap wafer comprising a pressurized chamber having a pressure different than an
ambient air pressure.

US Pat. No. 9,123,563

METHOD OF FORMING CONTACT STRUCTURE OF GATE STRUCTURE

Taiwan Semiconductor Manu...

7. A method of forming a contact structure of a gate structure, comprising:
etching an oxidation layer and a first sidewall layer disposed between a first metal gate and a second metal gate to expose
an underlying silicon substrate;

depositing a silicide portion defined by a contact profile in the exposed portion of the silicon substrate;
depositing a metal glue layer around the first metal gate and the second metal gate defining a trench above the silicide portion;
and

depositing a metal plug within the trench.

US Pat. No. 9,455,346

CHANNEL STRAIN INDUCING ARCHITECTURE AND DOPING TECHNIQUE AT REPLACEMENT POLY GATE (RPG) STAGE

Taiwan Semiconductor Manu...

1. A method of forming a strain inducing layer overlaying a channel in a finFET (fin field-effect transistor) device, comprising:
forming a dummy gate over an upper surface of a fin of semiconductor material and along sidewalls of the fin, wherein the
fin corresponds to channel region of the finFET device;

forming source/drain regions for the finFET device on opposite edges of the dummy gate while the dummy gate is in place over
the channel region;

removing the dummy gate after the source/drain regions have been formed and leaving a remaining portion of fin in place after
the dummy gate has been removed; and

forming a strain inducing layer over an upper surface of the remaining portion of the fin and along sidewalls of the remaining
portion of the fin.

US Pat. No. 9,449,886

SEMICONDUCTOR DEVICE AND FORMATION THEREOF

Taiwan Semiconductor Manu...

1. A method, comprising:
etching a substrate to define a set of fins;
masking a top surface of a first subset of the set of fins;
etching a second subset of the set of fins while the top surface of the first subset is masked to reduce a fin height of fins
that are members of the second subset;

etching a portion of the substrate between a first fin of the second subset and a second fin of the second subset to define
a trench;

forming a shallow trench isolation (STI) region within a first portion of the trench and a second portion of the trench; and
depositing a conductive material within a third portion of the trench, over the first subset, and over the second subset to
form a metal connect, wherein:

the third portion of the trench is between the first portion of the trench and the second portion of the trench, and
the metal connect is in contact with the first subset and the second subset.

US Pat. No. 9,391,023

METHOD FOR PRODUCING SALICIDE AND A CARBON NANOTUBE METAL CONTACT

Taiwan Semiconductor Manu...

1. A method of producing a metal contact in a semiconductor device comprising:
depositing a catalyst material layer in a via hole;
forming a catalyst from the catalyst material layer;
growing a carbon nanotube structure using the catalyst in the via hole;
forming a portion of salicide from the catalyst after the growth of the carbon nanotube structure;
applying a chemical mechanical polishing (CMP) process to the carbon nanotube structure to remove top layers of catalyst and
nanotube material; and

depositing metal material above the carbon nanotube structure.

US Pat. No. 9,287,127

WAFER BACK-SIDE POLISHING SYSTEM AND METHOD FOR INTEGRATED CIRCUIT DEVICE MANUFACTURING PROCESSES

Taiwan Semiconductor Manu...

1. A wafer polishing process, comprising:
forming integrated circuit component devices on a front side of a wafer;
polishing a first region of the wafer that comprises a central area on a back side of the wafer;
polishing a second region of the wafer that comprises a peripheral area on the back side of the wafer;
after polishing the first region, buffing the first region; and
after polishing the second region, buffing the second region;
wherein the polishing of the first region and the polishing of the second region are done after the forming of integrated
circuit component devices on the front side of the wafer;

the first region comprises an area on the back side of the wafer that is not within the second region;
the second region comprises an area on the back side of the wafer that is not within the first region;
polishing comprises polishing with an abrasive pad having a first grit; and
buffing comprises buffing with an abrasive pad having a second grit that is finer than the first grit or buffing with a non-abrasive
pad.

US Pat. No. 9,278,860

METHOD AND APPARATUS FOR RECYCLING WASTE SULFURIC ACID

Taiwan Semiconductor Manu...

1. A method for recycling waste sulfuric acid solution, comprising:
providing a reaction tank;
introducing a waste sulfuric acid (H2SO4) solution into the reaction tank, wherein the waste sulfuric acid solution comprises hydrogen peroxide (H2O2) and;

supplying a compound containing chlorine into the reaction tank;
mixing the compound containing chlorine with the waste sulfuric acid solution to promote a chemical reaction that decomposes
the hydrogen peroxide (H2O2); and

collecting a waste gas generated from the reaction tank after mixing the waste sulfuric acid solution and the compound containing
chlorine, wherein the waste gas comprises Cl2 and O2.

US Pat. No. 9,281,681

ESD PROTECTION CIRCUITS AND METHODS

Taiwan Semiconductor Manu...

1. An electrostatic discharge protection circuit, comprising:
a first LC resonator circuit coupled to an input node and disposed in parallel with an internal circuit that is also coupled
to the input node, the first LC resonator including

a first portion of a single planar inductor coupled to the input node and to the first node, and
a first capacitor coupled to the input node and to the first node such that the first capacitor is disposed in parallel with
the first portion of the single planar inductor; and

a second LC resonator circuit coupled in series with the first LC resonator circuit at a first node, the second LC resonator
including

a second portion of the single planar inductor coupled to the first node and to a second node, and
a second capacitor coupled to the first node and to the second node such that the second capacitor is disposed in parallel
with the second portion of the single planar inductor,

wherein the first LC resonator circuit is configured to resonate at a different frequency than a frequency at which the second
LC resonator circuit is configured to resonate, and a first connecting end portion of the first portion of the single planar
inductor is disposed in a first metal layer and second connecting end portion of the second portion of the single planar inductor
is disposed in a second metal layer, wherein the first connecting end portion does not contact the second metal layer and
the second connecting end portion does not contact the first metal layer.

US Pat. No. 9,281,215

MECHANISM FOR FORMING GATE

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a semiconductor substrate;
an isolation structure in the semiconductor substrate and surrounding an active region of the semiconductor substrate;
a gate over the semiconductor substrate, wherein the gate has an intermediate portion over the active region and two end portions
connected to the intermediate portion, the end portions are located over the isolation structure, each of the end portions
has a first gate length longer than a second gate length of the intermediate portion, and each of the end portions has a first
edge facing the active region and aligned with a second edge of the isolation structure; and

a spacer layer surrounding and covering an entire lateral outer sidewall of the intermediate portion of the gate and an entire
lateral outer side wall of the two end portions of the gate, wherein the spacer layer that covers the entire lateral outer
side wall of the two end portions of the gate has a first portion located directly above the active region and a second portion
located directly above the isolation structure.

US Pat. No. 9,275,894

METHOD FOR FORMING SEMICONDUCTOR DEVICE STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for forming a semiconductor device structure, comprising:
forming a dielectric layer on a semiconductor substrate, wherein the dielectric layer has at least one first trench in the
dielectric layer;

forming a seed layer on a sidewall and a bottom surface of the first trench;
forming a first conductive layer on the seed layer, wherein a bottom deposition rate of the first conductive layer is greater
than a sidewall deposition rate of the first conductive layer;

performing a thermal treatment process to melt and transform the seed layer and the first conductive layer into a second conductive
layer; and

forming a third conductive layer on the second conductive layer to fill the first trench.

US Pat. No. 9,261,534

SHIELD PIN ARRANGEMENT

Taiwan Semiconductor Manu...

1. A probe card for testing an electronic device comprising:
a signal pin configured to carry a signal;
a first set of one or more shield pins lying within a first plane; and
a second set of one or more shield pins lying within a second plane different than the first plane, the first set and the
second set of one or more shield pins configured to shield the signal pin from an interference signal.

US Pat. No. 9,087,821

HYBRID BONDING WITH THROUGH SUBSTRATE VIA (TSV)

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device structure, comprising:
a first semiconductor wafer bonded to a second semiconductor wafer via a hybrid bonding structure, wherein the hybrid bonding
structure comprises:

a first conductive material embedded in a first polymer material; and
a second conductive material embedded in a second polymer material, wherein the first conductive material is bonded to the
second conductive material and the first polymer material of the first semiconductor wafer is bonded to the second polymer
material of the second semiconductor wafer; and

at least one through substrate via (TSV) extending from a bottom surface of the first semiconductor wafer to a metallization
structure of the first semiconductor wafer; and

an interconnect structure formed over the bottom surface of the first semiconductor wafer, wherein the interconnect structure
is electrically connected to the metallization structure via the TSV.

US Pat. No. 9,305,864

THROUGH SILICON VIA (TSV) ISOLATION STRUCTURES FOR NOISE REDUCTION IN 3D INTEGRATED CIRCUIT

Taiwan Semiconductor Manu...

1. A semiconductor device comprising:
an active semiconductor device formed on a surface of a semiconductor substrate;
an isolation through silicon via (TSV) extending through said semiconductor substrate and laterally spaced from said active
semiconductor device and next to a surface dopant impurity region of a first dopant impurity type disposed in said surface
between said isolation TSV and said active semiconductor device, said surface dopant impurity region having a dopant concentration
different from said substrate; and

said isolation TSV surrounded laterally by a surrounding dopant impurity region along part of a length of said isolation TSV,
wherein said surrounding dopant impurity region extends from said surface to a termination location above a bottom surface
of said semiconductor substrate.

US Pat. No. 9,269,814

SACRIFICIAL LAYER FIN ISOLATION FOR FIN HEIGHT AND LEAKAGE CONTROL OF BULK FINFETS

Taiwan Semiconductor Manu...

1. An integrated circuit (IC) including one or more FinFET devices formed on a semiconductor substrate, the IC comprising:
a gate electrode which overlies the semiconductor substrate and which has a gate dielectric on an underside of the gate electrode;
a fin of semiconductor material suspended from the gate dielectric, wherein a cavity separates a lower surface of the suspended
fin from a region of the semiconductor substrate aligned under the fin; and

a pair of sidewall spacers on opposing sidewalls of the suspended fin, wherein the pair of sidewall spacers have upper surfaces
below an upper surface of the gate electrode and lower surfaces below the lower surface of the suspended fin.

US Pat. No. 9,268,375

POWER DISTRIBUTION IN SEMICONDUCTOR DEVICE

TAIWAN SEMICONDUCTOR MANU...

1. A semiconductor device comprising:
a clock signal distribution network configured to receive a first power; and
a logic circuitry configured to receive a second power independent from the first power;
wherein the clock signal distribution network comprises:
a first clock spine comprising a plurality of outputs; and
a plurality of second clock spines, wherein each second clock spine of the plurality of second clock spines comprises an input
connected to an output of the plurality of outputs.

US Pat. No. 9,257,498

PROCESS TO IMPROVE PERFORMANCE FOR METAL-INSULATOR-METAL (MIM) CAPACITORS

Taiwan Semiconductor Manu...

1. A metal-insulator-metal (MIM) capacitor, comprising:
a capacitor bottom metal (CBM) electrode;
a high k dielectric layer arranged over the CBM electrode;
a capacitor top metal (CTM) electrode arranged over the high k dielectric layer; and
CTM protective sidewall regions, which extend along sidewall surfaces of the CTM electrode, wherein top and bottom surfaces
of the CTM electrode are substantially aligned with top and bottom surfaces of the CTM protective sidewall regions.

US Pat. No. 9,425,324

SEMICONDUCTOR DEVICE AND CHANNEL STRUCTURE THEREOF

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a composite structure that comprises
an inner core strut that comprises a gate stack; and
an outer sleeve layer that is sleeved on the gate stack of the inner core strut and that comprises a two-dimensional (2-D)
layered material, wherein the inner core strut mechanically supports the outer sleeve layer and wherein the outer sleeve layer
has a central portion that defines a channel region and a pair of opposing end portions that respectively define source and
drain regions.

US Pat. No. 9,406,626

SEMICONDUCTOR DEVICE AND METHOD FABRICATING THE SAME

Taiwan Semiconductor Manu...

1. A semiconductor device, comprising:
a main circuit;
an assembly isolation region that surrounds the main circuit, the assembly isolation region comprising a first circuit that
includes a first capacitor and a first inductor connected in series; and

a first seal ring that surrounds the assembly isolation region, the first capacitor and the first inductor (i) being connected
between the first seal ring and a ground, and (ii) being disposed laterally between the first seal ring and the main circuit.

US Pat. No. 9,349,690

SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF

TAIWAN SEMICONDUCTOR MANU...

1. A method of forming a semiconductor arrangement, comprising:
forming a first metal layer in a first opening of a dielectric, a second opening of the dielectric and over the dielectric,
the first metal layer comprising titanium nitride;

forming a first interconnect over the first metal layer in the first opening;
forming a second interconnect over the first metal layer in the second opening;
forming a first dielectric layer over the first metal layer, the first interconnect and the second interconnect;
performing a first etch to remove a first portion of the first dielectric layer over the first interconnect, the second interconnect
and a first portion of the first metal layer and to remove the first portion of the first metal layer from a first top portion
of a top surface of the dielectric, such that a first metal layer first portion remains in the first opening and a first metal
layer second portion remains in the second opening;

performing a second etch to form a first air gap on first side of the first metal layer first portion and to form a second
air gap on a second side of the first metal layer first portion, such that the second air gap is between the first metal layer
first portion and the first metal layer second portion;

performing a third etch to remove first sidewalls of the first metal layer first portion, such that a first bottom portion
of the first metal layer remains under the first interconnect, and to remove second sidewalls of the first metal layer second
portion, such that a second bottom portion of the first metal layer remains under the second interconnect; and

forming a protective barrier over the first interconnect and the second interconnect.

US Pat. No. 9,293,585

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FORMING SAME

Taiwan Semiconductor Manu...

17. A semiconductor device comprising:
a gate structure over a substrate including a gate electrode and gate spacers on opposing sides of the gate electrode;
a first etch stop layer (ESL) over the substrate and at least the gate spacers;
a first inter-layer dielectric over the first ESL;
a second ESL over the first ILD and directly adjoining the first ESL; and
a second ILD over the second ESL, wherein the gate electrode, the first ESL, the second ESL, and the second ILD each have
surfaces which are substantially coplanar.

US Pat. No. 9,287,856

TRACKING CIRCUIT

TAIWAN SEMICONDUCTOR MANU...

1. A circuit comprising:
a switching circuit having a first terminal, a second terminal, and a third terminal, the first terminal configured to have
a supply voltage value;

a node electrically coupled with the second terminal of the switching circuit, the node having a node voltage, the node voltage
having a first voltage value higher than the supply voltage value; and

a tracking circuit electrically coupled to the third terminal of the switching circuit and the node, and configured to selectively
turn on or turn off the switching circuit by generating a control voltage at the third terminal of the switching circuit based
on the node voltage.

US Pat. No. 9,272,386

POLISHING HEAD, AND CHEMICAL-MECHANICAL POLISHING SYSTEM FOR POLISHING SUBSTRATE

TAIWAN SEMICONDUCTOR MANU...

1. A polishing head for a chemical-mechanical polishing system, the polishing head comprising:
a carrier head;
at least one electromagnetism actuated pressure sector disposed on the carrier head, wherein the electromagnetism actuated
pressure sector comprises:

a stator being stationary with respect to the carrier head;
an active cell linearly movable with respect to the carrier head and in electromagnetic cooperation with the stator: and
a sector plate connected to the active cell; and
a membrane covering the electromagnetism actuated pressure sector.

US Pat. No. 9,129,988

FINFET AND METHOD OF MANUFACTURING THE SAME

TAIWAN SEMICONDUCTOR MANU...

12. A method of manufacturing a FinFET, comprising:
forming a fin structure over a substrate;
forming a dummy gate that crosses over the fin structure;
forming a doped region through the fin structure;
forming a source-drain region in the doped region;
removing the dummy gate and a portion of the fin structure beneath the dummy gate to form a cavity; and
forming a gate in the cavity.

US Pat. No. 9,281,338

SEMICONDUCTOR IMAGE SENSOR DEVICE HAVING BACK SIDE ILLUMINATED IMAGE SENSORS WITH EMBEDDED COLOR FILTERS

Taiwan Semiconductor Manu...

1. A semiconductor image sensor device, comprising:
a substrate having a first side and a second side that is opposite the first side;
an interconnect structure disposed over the first side of the substrate;
radiation-sensing regions located in the substrate, the radiation-sensing regions being configured to sense radiation that
enters the substrate from the second side, wherein the radiation-sensing regions are separated by gaps;

radiation-blocking structures disposed over the second side of the substrate, wherein each of the radiation-blocking structures
is aligned with a respective one of the gaps;

color filters, each of the color filters being embedded in a space between two adjacent radiation-blocking structures; and
a passivation layer, portions of the passivation layer being disposed between the color filters and the radiation-blocking
structures.

US Pat. No. 9,263,511

PACKAGE WITH METAL-INSULATOR-METAL CAPACITOR AND METHOD OF MANUFACTURING THE SAME

Taiwan Semiconductor Manu...

1. A package comprising:
a chip comprising:
a metal-insulator-metal (MIM) capacitor formed in a first polymer layer wherein the MIM capacitor comprises a lower metal
layer, an upper metal layer, and a capacitor dielectric layer formed between the lower metal layer and the upper metal layer,
and the upper metal layer substantially covers the capacitor dielectric layer; and

a metallic pillar formed on the MIM capacitor;
a molding compound surrounding the chip;
a second polymer layer formed on the chip and the molding compound;
a third polymer layer formed on the second polymer layer;
an interconnect structure formed between the second polymer layer and the third polymer layer and electrically coupled to
the metallic pillar and the MIM capacitor; and

a bump formed over and electrically coupled to the interconnect structure.

US Pat. No. 9,230,961

SEMICONDUCTOR ARRANGEMENT FACILITATING ENHANCED THERMO-CONDUCTION

Taiwan Semiconductor Manu...

1. A semiconductor arrangement comprising:
a well region;
a first region disposed within the well region, the first region comprising a first conductivity type;
a first gate disposed above the well region on a first side of the first region, the first gate comprising a first top surface
facing away from the well region, the first top surface having a first top surface area;

a first gate contact disposed above the first gate, the first gate contact comprising a first bottom surface facing towards
the well region, the first bottom surface having a first bottom surface area, the first bottom surface area covering at least
about two thirds of the first top surface area;

a first region contact disposed above the first region; and
a first multi-gate contact in direct physical contact with the first gate contact and the first region contact.

US Pat. No. 9,293,294

FREQUENCY DEPENDENT CLOCK APPARATUS AND METHOD

TAIWAN SEMICONDUCTOR MANU...

1. A method for operating a dynamic pattern generator (DPG), the method comprising:
receiving a first clock having a frequency and a period;
determining a toggling rate based on the frequency of the first clock;
comparing the toggling rate with a threshold; and
providing a signal including information on a delay for the first clock based on the period of the first clock in response
to a result of the comparing.

US Pat. No. 9,287,303

CMOS IMAGE SENSOR STRUCTURE

TAIWAN SEMICONDUCTOR MANU...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a substrate;
forming a logic gate structure and a photosensitive gate structure on a surface of the substrate;
forming a hard mask layer to cover the logic gate structure, the photosensitive gate structure and the surface of the substrate;
forming a spacer material layer to cover the hard mask layer;
removing a first portion of the spacer material layer to expose a portion of the hard mask layer, wherein a second portion
of the spacer material layer remains for forming a first spacer overlying the hard mask layer conformal to a sidewall of the
logic gate structure and a second spacer overlying the hard mask layer conformal to a sidewall of the photosensitive gate
structure; and

forming a first source and a first drain respectively in the substrate at two opposite sides of the logic gate structure,
and a second source and a second drain respectively in the substrate at two opposite sides of the photosensitive gate structure.

US Pat. No. 9,281,336

MECHANISMS FOR FORMING BACKSIDE ILLUMINATED IMAGE SENSOR DEVICE STRUCTURE

Taiwan Semiconductor Manu...

11. A method for manufacturing a backside illuminated image sensor device structure comprising:
providing a substrate having a front side and a back side;
forming a polysilicon layer over the front side of the substrate;
forming a buffer layer over the polysilicon layer;
forming an etch stop layer over the buffer layer;
forming a hard mask layer over the etch stop layer;
patterning the hard mask layer;
performing an implant process from the front side of the substrate through the etch stop layer to form a radiation sensing
region that is in the substrate and directly below the etch stop layer;

removing the hard mask layer by a first removing process;
removing the etch stop layer by a second removing process; and
removing the buffer layer by a third removing process.

US Pat. No. 9,275,598

DAC ARCHITECTURE FOR LCD SOURCE DRIVER

Taiwan Semiconductor Manu...

1. A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code, comprising:
a two-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving
a high reference voltage and a low reference voltage input node for receiving a low reference voltage; and

a voltage selector, the voltage selector setting the high reference voltage and low reference voltage to selected levels depending
on at least a portion of the M-bit digital input code;

wherein the two-bit serial charge redistribution digital-to-analog converter includes:
an output operational amplifier having a first operational amplifier input coupled to an output of the output operational
amplifier and a second operational amplifier input coupled to a charge collection node;

a termination capacitor coupled between the charge collection node and the low reference voltage input node;
a first capacitor coupled between the low reference voltage input node and a first capacitor charging node;
a second capacitor coupled between the low reference voltage input node and a second capacitor charging node;
a first switching circuit for coupling the first capacitor charging node to one of the low reference voltage input node and
the high reference voltage input node during capacitor charge cycles in response to instances of a two-bit control code from
a sequence of two-bit control codes derived from the M-bit digital input code;

a second switching circuit for coupling the second capacitor charging node to one of the low reference voltage input node
and the high reference voltage input node during the capacitor charge cycles in response to the instances of the two-bit control
code; and

a third switching circuit for coupling the first and second capacitor charging nodes to the charge collection node during
charge redistribution cycles following the capacitor charge cycles,

wherein the first and second capacitors are binary weighted with respect to one another.

US Pat. No. 9,093,455

BACK-END-OF-LINE (BEOL) INTERCONNECT STRUCTURE

Taiwan Semiconductor Manu...

15. An interconnect structure, the interconnect structure comprising:
a dielectric layer, the dielectric layer having a recess therein;
a silicon (Si) layer that is deposited in the recess; and
an interconnect including a barrier layer and a conductive layer that are provided in the recess over the Si layer, wherein
the Si layer has a density that substantially prevents the barrier layer from moving away from the conductive layer and towards
the dielectric layer during subsequent processing of the interconnect structure,

wherein the interconnect structure is planarized to cause portions of the Si layer, the barrier layer, and the conductive
layer to be coplanar with a top surface of the dielectric layer, the interconnect structure further comprising:

a nitride layer that is formed in a first portion of the Si layer that is adjacent to the top surface; and
an oxide layer that is formed in a second portion of the Si layer that is adjacent to the first portion.

US Pat. No. 9,550,270

TEMPERATURE MODIFICATION FOR CHEMICAL MECHANICAL POLISHING

Taiwan Semiconductor Manu...

1. A system, comprising:
a fluid reservoir for storing a liquid;
a nozzle for dispensing the liquid onto a polishing pad of a chemical mechanical polishing (CMP) system;
a first fluid pathway from the fluid reservoir to the nozzle;
a second fluid pathway from the fluid reservoir to the nozzle;
a first valve disposed within the first fluid pathway;
a second valve disposed within the second fluid pathway;
a liquid heater component disposed within the second fluid pathway between the fluid reservoir and the second valve, the liquid
heater component comprising a quartz heater configured to heat the liquid to generate heated liquid, wherein the heated liquid
is supplied to the polishing pad upon which a semiconductor wafer is to be polished to generate a heated polishing pad having
a heated polishing pad temperature; and

a polishing component configured to:
responsive to the heated polishing pad temperature exceeding a threshold, polish the semiconductor wafer utilizing the heated
polishing pad during a CMP stage.

US Pat. No. 9,281,376

SEMICONDUCTOR STRUCTURES EMPLOYING STRAINED MATERIAL LAYERS WITH DEFINED IMPURITY GRADIENTS AND METHODS FOR FABRICATING SAME

Taiwan Semiconductor Manu...

1. A method comprising:
forming a dummy gate structure on a channel area of a substrate;
forming a source region and a drain region on opposing sides of the channel area in the substrate;
after forming the source region and the drain region, removing the dummy gate structure;
after removing the dummy gate structure, forming a semiconductor layer on the channel area of the substrate, wherein the semiconductor
layer comprises a first concentration of an impurity in a first portion adjacent an interface with the substrate, a second
concentration of the impurity in a second portion distal from the interface, and a third concentration in a third portion
disposed between the first portion and the second portion, the first concentration being greater than the second concentration,
the third concentration being greater than the second concentration; and

forming a gate electrode structure over the semiconductor layer.