US Pat. No. 9,489,478

SIMPLIFYING MODES OF AN ELECTRONIC CIRCUIT BY REDUCING CONSTRAINTS

Synopsys, Inc., Mountain...

1. A computer-implemented method for simplifying modes of a circuit design, the method using a computer processor to execute
steps including:
receiving, by the computer processor, a description of a mode of a circuit, the description comprising a netlist and timing
constraints associated with the netlist, the netlist comprising timing nodes connected by timing paths, and the timing constraints
comprising one or more clocks and corresponding timing exceptions associated with one or more timing paths;

identifying, by the computer processor, a set of timing nodes of the circuit, each timing node in the identified set of timing
nodes associated with timing paths reaching the timing node;

selecting, by the computer processor, critical clock pairs, the selecting comprising, for each timing node in the identified
set of timing nodes:

determining a set of clock pairs, each clock pair from the determined set of clock pairs associated with a particular timing
path reaching the timing node, each clock pair including a launch clock and a capture clock associated with the particular
timing path;

for each clock pair from the determined set of clock pairs, determining a time interval between an edge of the launch clock
and an edge of the capture clock;

identifying a clock pair with a smallest time interval in the determined set of clock pairs; and
marking the identified clock pair as a selected critical clock pair;
modifying, by the computer processor, the description of the mode by eliminating one or more clocks that do not occur in the
selected critical clock pairs; and

performing a timing analysis of the circuit using the modified description of the mode.

US Pat. No. 9,216,590

EXTREME ULTRAVIOLET/SOFT X-RAY LASER NANO-SCALE PATTERNING USING THE DEMAGNIFIED TALBOT EFFECT

COLORADO STATE UNIVERSITY...

1. A method for producing nanometer-scale patterning on the surface of a sample, comprising:
directing a coherent light beam having a chosen wavelength onto a focusing optic such that the light beam emerging therefrom
converges

placing a Talbot mask having a periodic pattern of nanometer-scale unit cells formed thereon in the converging light beam
at a first chosen distance from the focusing optic, wherein the converging light beam passes through the Talbot mask; and

placing a sample disposed at a second chosen distance from the Talbot mask, having a photosensitive surface thereon responsive
to the light beam passing through the Talbot mask, for generating a nanostructure having the pattern of unit cells of the
Talbot mask on the sample.

US Pat. No. 9,424,380

AUGMENTED SIMULATION METHOD FOR WAVEFORM PROPAGATION IN DELAY CALCULATION

Synopsys, Inc., Mountain...

1. A non-transitory computer readable storage medium storing instructions for performing static timing analysis of an integrated
circuit design for manufacturing, the instructions for:
receiving, by a static timing analyzer, information describing a distorted input waveform, the distorted input waveform received
as input to a cell of the integrated circuit design for performing timing analysis of the integrated circuit design, the integrated
circuit design for manufacturing;

determining, by the static timing analyzer, a transition time of the distorted input waveform;
receiving, by the static timing analyzer, information describing a nominal input waveform based on the determined transition
time and a corresponding nominal output waveform, the nominal output waveform representing output of the cell of the integrated
circuit design;

computing, by the static timing analyzer, an input waveform distortion as a difference between the distorted input waveform
and the nominal input waveform;

generating, by the static timing analyzer, an augmented circuit based on the nominal input waveform and the input waveform
distortion; and

computing an output waveform distortion for the output of the cell of the integrated circuit design based on the augmented
circuit.

US Pat. No. 9,201,708

DIRECT MEMORY INTERFACE ACCESS IN A MULTI-THREAD SAFE SYSTEM LEVEL MODELING SIMULATION

Synopsys, Inc., Mountain...

1. A computer implemented method for multi-threaded system level modeling simulation (SLMS) of a target system on a host system,
the method comprising:
beginning parallel execution of a plurality of SLMS processes via a plurality of threads, the SLMS processes representing
functional behaviors of components within the target system that access a memory of the target system through an interconnect
of the target system;

during the parallel execution, detecting a request for direct memory interface (DMI) access to a region of the memory, wherein
the DMI access is direct access to the region of the memory of the target system that bypasses the interconnect of the target
system, the request for DMI access initiated by a requesting SLMS process of the SLMS processes;

responsive to the request for DMI access, executing the requesting SLMS process in an exclusive execution mode that prevents
the requesting SLMS process from executing in parallel with other SLMS processes of the SLMS processes; and

granting the DMI access to the requesting SLMS process responsive to executing the requesting SLMS process in the exclusive
execution mode.

US Pat. No. 9,075,666

DEFERRED EXECUTION IN A MULTI-THREAD SAFE SYSTEM LEVEL MODELING SIMULATION

Synopsys, Inc., Mountain...

1. A computer implemented method for multi-threaded system level modeling simulation (SLMS) of a target system on a host system,
the method comprising:
beginning parallel execution of a plurality of SLMS processes via a plurality of threads, the SLMS processes representing
functional behaviors of components within the target system;

during the parallel execution of the SLMS processes, detecting operations within the SLMS processes that access at least one
shared resource within the host system; and

during the parallel execution, deferring execution of one or more of the operations within the SLMS processes that access
the at least one shared resource within the host system until after the parallel execution is completed, wherein deferring
execution comprises:

deferring a first set of the operations that access a first set of the at least one shared resource until after the parallel
execution is completed; and

executing a second set of the operations that access a second set of the at least one shared resource during the parallel
execution.

US Pat. No. 9,053,264

WHAT-IF SIMULATION METHODS AND SYSTEMS

Synopsys, Inc., Mountain...

1. A method comprising:
receiving, at one or more computer systems, a design coding in HDL (Hardware Description Language);
receiving, at the one or more computer systems, a simulation result corresponding to a simulation performed with the design,
wherein the simulation result comprises signal values of signals, a changed time of the respective signal value, and an event
sequence order for the changed time of the respective signal value;

receiving, at the one or more computer systems, a what-if design scope and a what-if time window;
extracting, with one or more processors associated with the one or more computer systems, a portion of the design according
to the what-if design scope to generate a sub-design;

determining, with the one or more processors associated with the one or more computer systems, primary input signals of the
sub-design;

extracting, with the one or more processors associated with the one or more computer systems, what-if simulation data from
the simulation result according to the primary input signals and the what-if time window, wherein the what-if simulation data
comprises the signal values of the primary input signals within the what-if time window, the changed time of the respective
signal value, and the event sequence order for the changed time of the respective signal value; and

generating, with the one or more processors associated with the one or more computer systems, a what-if test bench according
to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are input to a simulator
according to the what-if test bench.

US Pat. No. 9,367,648

SPECIFICATION-GUIDED USER INTERFACE FOR OPTICAL DESIGN SYSTEMS

Synopsys, Inc., Mountain...

1. A method for designing an optical system using a optical design system implemented on a computer system, the method comprising
the optical design system performing the steps of:
generating a design state overview of the design of the optical system, the design state overview summarizing a current state
and a target state of the design by describing a plurality of specifications for the optical system, the specification descriptions
including target ranges for the specifications based on the target state of the design and further including current values
for the specifications based on the current state of the design, and the specification descriptions include a comparison condition
between a combination of a target range, a target state and a current value associated with the specification;

displaying the design state overview; and
updating, by a processor, the design state overview in response to the optical design system changing the current design for
the optical system and visually emphasizing one or more specifications based in part on a comparison condition.

US Pat. No. 9,064,076

USER INTERFACE FOR FACILITATION OF HIGH LEVEL GENERATION OF PROCESSOR EXTENSIONS

Synopsys, Inc., Mountain...

1. A computer implemented method comprising:
receiving a request to generate a processor extension from a high level description, the processor extension for extending
an instruction set of a processor, the processor extension for executing an extension instruction;

generating a first window on a graphical user interface comprising a plurality of instruction formats representing available
instruction types, wherein the instruction formats specify a number of operands and type of operands of the extension instruction,
the first window operable to allow user selection of a selected instruction format, wherein the selected instruction format
specifies characteristics of the extension instruction to be implemented by a hardware of the processor extension;

generating a second window on a graphical user interface comprising editable instruction fields for defining the extension
instruction, the extension instruction extending the instruction set of the processor based on the selected instruction format;

generating a third window on a graphical user interface operable to display an editable description of the extension instruction,
the editable description of the extension instruction describing the execution of the extension instruction to be implemented
by the hardware of the processor extension, the editable description written in a programming language other than a hardware
description language (HDL); and

generating, by a computer, a representation of a hardware design of the processor extension based on the extension instruction
and the description of the extension instruction, the hardware design of the processor extension implementing the editable
description of the extension instruction written in the programming language, the processor extension comprising the instruction
format and a computational element that implements the extension instruction.

US Pat. No. 9,298,084

PREVENTING DOUBLE PATTERNING ODD CYCLES

Synopsys Inc., Mountain ...

1. A method of preventing odd cycles caused by design modifications to a double patterning layout including a plurality of
partitions comprising:
utilizing a processor to identify a set of potential double patterning cycles in a partition of the layout, the set of potential
double patterning cycles including a cross-partition subset of double patterning cycles that include cross-partition edges
that extend from vertices in the partition to closely proximate vertices in adjoining partitions, for storage in a memory;

receiving a set of design modifications to the partition;
utilizing the processor to identify from the set of potential double patterning cycles a subset of double patterning cycles
affected by the set of design modifications to the partition;

utilizing the processor to identify from the set of design modifications a subset of design modifications to the partition
which may cause odd cycles in the subset of double patterning cycles; and

providing a notification of the subset of design modifications to the partition.

US Pat. No. 9,239,897

HIERARCHICAL TESTING ARCHITECTURE USING CORE CIRCUIT WITH PSEUDO-INTERFACES

Synopsys, Inc., Mountain...

1. A core circuit in a test circuit comprising:
at least one real input configured to receive scan-in data and control data for controlling operation of the core circuit
from a source external to the test circuit;

an input register chain coupled to the at least one real input and configured to store the scan-in data and the control data;
at least one scan chain coupled to a subset of registers in the register chain to receive the scan-in data and configured
to generate a scan-out data representing presence of faults in an associated circuit responsive to receiving the scan-in data;

a pseudo-output coupled to the input register chain and configured to send at least a subset of the scan-in data and the control
data to another input register chain in the core circuit or to another core circuit; and

a pseudo-input coupled to the input register chain, the pseudo input coupled directly to a pseudo output of the core circuit
or the other core circuit.

US Pat. No. 9,285,796

APPROXIMATE FUNCTIONAL MATCHING IN ELECTRONIC SYSTEMS

Synopsys, Inc., Mountain...

1. A method to update a description of an integrated circuit design or software program, the method comprising:
determining, using a processor, whether an input of one or more subsets of the description or software program is a control
input by

assigning combinations of logic values to one or more side inputs of the one or more subsets of the description or software
program

determining a first number of outputs sensitized by a logic transition of the input for each combination of values of the
one or more side inputs,

determining if the first number is greater than a predetermined number, and identifying the input as a control input if the
first number of outputs sensitized by the input is greater than the predetermined number;

determining a first plurality of co-factors for the one or more subsets of the description or software program, each co-factor
determined by toggling combinations of values for the control inputs;

identifying matches in the description or software program or a template by a comparison of co-factors;
determining one or more updated subsets based on one or more matches; and
updating the description or software program with the updated subset.

US Pat. No. 9,449,138

PROTOTYPE AND EMULATION SYSTEM FOR MULTIPLE CUSTOM PROTOTYPE BOARDS

Synopsys, Inc., Mountain...

1. A system for emulating a circuit design, the system comprising:
a host workstation coupled by an emulation interface to a field programmable gate array (FPGA) configured to emulate and verify
the circuit design when the host workstation is invoked to verify the circuit design, wherein the emulation interface is configured
to provide timing and control information for at least the verify; and

a non-transitory computer readable storage medium comprising instructions, which when executed cause the host workstation
to:

compile a portion of the circuit design and an associated verification module adapted to configure the FPGA, wherein a compilation
is performed in accordance with a description file.

US Pat. No. 9,292,641

TIMING BOTTLENECK ANALYSIS ACROSS PIPELINES TO GUIDE OPTIMIZATION WITH USEFUL SKEW

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool in a computer, a method for guiding circuit optimization, the method comprising:
the EDA tool in the computer computing a set of aggregate slacks for a set of chains of logic paths in a circuit design, wherein
each aggregate slack in the set of aggregate slacks corresponds to a chain of logic paths in the set of chains of logic paths,
wherein each logic path in each chain of logic paths (1) begins at a primary input or an output of a sequential circuit element
and (2) ends at a primary output or an input of a sequential circuit element, wherein each aggregate slack in the set of aggregate
slacks is equal to a sum of slacks of individual logic paths in the corresponding chain of logic paths in the set of chains
of logic paths;

the EDA tool in the computer determining an optimization guidance based on the set of aggregate slacks, wherein the optimization
guidance comprises one or more of: (1) a specification of one or more timing violations that are not to be resolved, (2) a
specification of one or more timing violations that are to be resolved, (3) a specification of one or more aggregate slacks
that are to be increased, (4) a specification of an order in which chains of logic paths are to be optimized, (5) a specification
of an order in which logic paths are to be optimized, and (6) a specification of a termination condition for terminating a
circuit optimization; and

the EDA tool in the computer optimizing the circuit design based on the optimization guidance.

US Pat. No. 9,431,085

MOST ACTIVATED MEMORY PORTION HANDLING

Synopsys, Inc., Mountain...

1. An apparatus for activation tracking comprising:
calculating logic configured to determine a number of times that a portion of a memory has been accessed;
storage memory, coupled to the calculating logic, configured to store the number of times that the portion of a memory has
been accessed as well as an address for the portion, wherein the number of times and the address are cast out in response
to where sufficient other portions have been accessed more times;

an others register configured to store a value representing a maximum number of times that any address which is not stored
in the storage memory has been accessed;

threshold logic, coupled to the calculating logic, configured to determine that the number of times that the portion is accessed
exceeds a certain threshold; and

marking logic, coupled to the calculating logic, configured to define that a second portion of the memory needs refresh, based
on the number of times exceeding the certain threshold.

US Pat. No. 9,286,433

METHOD OF FAST ANALOG LAYOUT MIGRATION

Synopsys Taiwan Co., Ltd....

1. A computer implemented method of forming an integrated circuit (IC) layout, the method comprising:
using the computer, automatically forming a constraint tree when the computer is invoked to receive a first layout of the
IC, the constraint tree comprising a plurality of constraint nodes describing placement constraints based on the first layout,
wherein the placement constraints comprise:

one or more matching constraints,
one or more symmetry constraints, and
one or more other constraints; and
generating, using the computer, a second layout of the IC, the second layout of the IC conforming with the constraints of
the constraint tree, wherein:

device modules of the second layout subject to the matching constraints are placed with a placement pattern extracted from
the corresponding device modules of the first layout without exploring other placement patterns,

device modules of the second layout subject to the symmetry constraints are placed with a placement pattern extracted from
the corresponding device modules of the first layout without exploring other placement patterns, and

device modules of the second layout subject to the other constraints are placed with a placement pattern which is generated
as a result of exploring alternative placement patterns, and is different from the placement pattern of the corresponding
device modules of the first layout.

US Pat. No. 9,280,629

GENERATING A CIRCUIT DESCRIPTION FOR A MULTI-DIE FIELD-PROGRAMMABLE GATE ARRAY

Synopsys, Inc., Mountain...

1. A method for generating a circuit description for a multi-die field-programmable gate array (FPGA) comprising a first FPGA
die and at least one further FPGA die, the method being performed in an FPGA design tool and comprising:
evaluating, automatically, a first partition and a second partition of a partitioned circuit description, the first partition
being associated with the first FPGA die and the second partition being associated with the at least one further FPGA die;
and

inserting at least one multiplexing element into the first partition and a corresponding de-multiplexing element into the
second partition based on the automated evaluation.

US Pat. No. 9,244,795

METHOD AND APPARATUS FOR EMULATION AND PROTOTYPING WITH VARIABLE CYCLE SPEED

Synopsys, Inc., Mountain...

1. A hardware verification system comprising a plurality of programmable devices and a system clock, the hardware verification
system configured to:
identify a first propagation delay associated with a first signal path corresponding to propagation of a first clock signal
derived from a variable period clock signal;

identify a second propagation delay associated with a second signal path, the second propagation delay being smaller than
the first propagation delay;

generate the variable period clock signal from the system clock, the variable period clock signal having a first period and
a second period greater than the first period, said first period occurring in each N cycles of the system clock and said second
period occurring in each M cycles of the system clock, wherein N and M are integer values greater than zero,

wherein the variable period clock signal has the second period when a change in value of the first clock signal is expected
at a next edge of the system clock, wherein the second period of the variable period clock signal is defined in accordance
with the first propagation delay, and

wherein the variable period clock signal has the first period when a change in value of the first clock signal is not expected
at the next edge of the system clock, wherein the first period of the variable period clock signal is defined in accordance
with the second propagation delay; and

apply the variable period clock signal to at least a first subset of the plurality of programmable devices.

US Pat. No. 9,069,699

IDENTIFYING INCONSISTENT CONSTRAINTS

SYNOPSYS, INC., Mountain...

1. A method for identifying inconsistent constraints, the method comprising:
receiving a set of constraints, wherein each constraint is defined over one or more random variables from a set of random
variables;

while solving the set of constraints by using a constraint solver executing on a computer, identifying a phase in a series
of phases of the constraint solver where an inconsistency in the set of constraints is detected, wherein detecting an inconsistency
in the set of constraints implies that no value assignment can simultaneously satisfy all of the constraints in the set of
constraints;

receiving a subset of the set of constraints;
and while solving the subset of the set of constraints by using the constraint solver executing on the computer, processing
only up to the identified phase in the series of phases of the constraint solver.

US Pat. No. 9,152,750

METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE

Synopsys, Inc., Mountain...

1. A method for simulating the manufacturing a structure, the method comprising:
simulating on a computer the formation of a line of crystalline phase material, the line having first and second opposite
sidewall surfaces; and

simulating on the computer the processing of the line to straighten at least one of the sidewall surfaces.

US Pat. No. 9,178,508

HIGH VOLTAGE SWITCH WITH TWO OR MORE OUTPUTS

Synopsys, Inc., Mountain...

1. A high-voltage (HV) switch with multiple outputs, comprising:
a first output branch configured to provide a first voltage output switching between a first voltage level and a second voltage
level lower than the first voltage level based on a first bias voltage and a first control signal;

a second output branch configured to provide a second voltage output based on the first bias voltage, a second bias voltage,
and a second control signal, the second voltage output switched between the first voltage level and the second voltage level
according to the second bias voltage and the second control signal in response to placing the first voltage output at the
first voltage level; and

a common branch coupled to the first and second output branches to provide the first bias voltage to the first output branch
and the second output branch in response to receiving the first control signal.

US Pat. No. 9,164,953

SCHEDULING IN A MULTICORE ARCHITECTURE

Synopsys, Inc., Mountain...

1. A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein
at least one processor element comprises reconfigurable logic, the method comprising:
providing a first configuration queue of executable transactions corresponding to a first configuration of the reconfigurable
logic and a second configuration queue of executable transactions corresponding to a second configuration of the reconfigurable
logic, the reconfigurable logic comprising one of a field programmable gate array (FPGA) or a memory, the executable transactions
allocated to and ready for execution by the reconfigurable logic;

providing a plurality of executable transaction schedulers, each executable transaction scheduler comprising a scheduling
algorithm for determining a most eligible executable transaction for execution from a number of candidate executable transactions;

linking the executable transaction schedulers together into a multilevel scheduler;
outputting the most eligible executable transaction from the multilevel scheduler to one of the first configuration queue
and the second configuration queue;

outputting the executable transactions of the first configuration queue to the reconfigurable processor element for execution
when the reconfigurable logic is configured according to the first configuration;

reconfiguring the reconfigurable logic according to a second configuration when a pre-determined threshold is reached; and
outputting the executable transactions of the second configuration queue to the configurable processor element for execution
when the reconfigurable logic is configured according to the second configuration.

US Pat. No. 9,157,961

TWO-LEVEL COMPRESSION THROUGH SELECTIVE RESEEDING

Synopsys, Inc, Mountain ...

1. A scan test system for testing a design implemented in an integrated circuit (IC), the design including a plurality of
blocks and a plurality of scan chains, the system comprising:
a plurality of compressor and decompressor structures (CODECs);
an instruction decode unit (IDU) configured to receive scan inputs from a tester, to determine whether a seed extracted from
the scan inputs is broadcast loaded in the plurality of CODECs, multicast loaded in a subset of the plurality of CODECs, or
individual loaded in a single CODEC, and to transmit one or more CODEC enable signals to said the plurality of CODECs,

wherein said plurality of CODECs are connected in parallel to the tester such that each said CODEC receives said seed, and
wherein said block includes at least one CODEC, each CODEC including:

a set of the plurality of scan chains;
a first pseudo-random pattern generator (PRPG) processing chain configured to use the seed to generate patterns for identifying
faults of the design, the patterns being applied to the set of the plurality of scan chains;

a second PRPG processing chain configured to generate X-tolerant (XTOL) control bits, the XTOL control bits determining a
level of observability of the set of the plurality of scan chains;

a PRPG shadow configured to receive the scan inputs and to selectively load the seed, when enabled by an associated said CODEC
enable signal transmitted from the IDU, to one of the first PRPG processing chain and the second PRPG processing chain; and

an unload block configured to receive scan outputs from the set of the plurality of scan chains and the XTOL control bits,
and to generate test outputs for analyzing the design.

US Pat. No. 9,134,378

LINEAR DECOMPRESSOR WITH TWO-STEP DYNAMIC ENCODING

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for calculating static seeds and dynamic seeds to enable generation
of care bits for detecting faults in a circuit under test (CUT), the method comprising:
receiving an integrated circuit (IC) design that includes a set of registers, a linear expander, and the CUT, wherein the
linear expander is capable of generating the care bits based on data stored in the set of registers and scanning the care
bits into a set of scan chains in the CUT, wherein the care bits comprise a set of static care bits and a set of dynamic care
bits, wherein the static care bits are capable of being encoded by using a first system of linear equations based on static
seeds, wherein the dynamic care bits are capable of being encoded by using a second system of linear equations based on dynamic
seeds, and wherein the first system of linear equations includes an augmented equation for each static care bit which is capable
of being determined by superposing linear equations of the static care bit and at least one corresponding dynamic care bit;

calculating the static seeds based on the static care bits and the first system of linear equations; and
calculating the dynamic seeds based on the dynamic care bits and the second system of linear equations.

US Pat. No. 9,047,257

CONCURRENT HOST OPERATION AND DEVICE DEBUG OPERATION WITH SINGLE PORT EXTENSIBLE HOST INTERFACE (XHCI) HOST CONTROLLER

Synopsys, Inc., Mountain...

1. A universal serial bus (USB) host controller conforming to a first universal serial bus (USB) Specification, the USB host
controller including an extensible host interface (xHCI), the USB host controller further comprising:
a host;
a first data path component coupled to the host;
a debug device; and
a second data path component coupled to the debug device, wherein the host and debug device are configured to simultaneously
operate during their respective host and device debug operations using a single port of the USB host controller.

US Pat. No. 9,355,728

VERY DENSE NONVOLATILE MEMORY BITCELL

Synopsys, Inc., Mountain...

1. A bitcell design for use with a complementary metal-oxide-semiconductor (CMOS) manufacturing process, the bitcell design
specifying components of a bitcell comprising:
a source region of a second conductivity type in a well of a first conductivity type;
a drain region of the second conductivity type in the well, the drain region implanted with a halo region of the first conductivity
type, a first boundary between the drain region and the halo region having a first doping gradient;

a channel region in the well between the drain region and the source region;
a capacitive region formed in the source region and comprising a dopant of the second conductivity type, the dopant implanted
to a depth within the well shallower than or equal to a deepest portion of the source region, a second boundary between the
source region and the channel region having a second doping gradient that changes more gradually than the first doping gradient;

a floating gate above the well and covering the channel region, at least a portion of the drain region and the capacitive
region, a gate-source capacitance between the floating gate and the source region increased relative to a gate-drain capacitance
between the floating gate and the drain region by the capacitive region; and

wherein the bitcell does not comprise a control gate.

US Pat. No. 9,361,418

NANOWIRE OR 2D MATERIAL STRIPS INTERCONNECTS IN AN INTEGRATED CIRCUIT CELL

SYNOPSYS, INC., Mountain...

1. A computer system adapted to process a computer implemented representation of a circuit design, comprising:
a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause
the processor to select cells from a cell library;

the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular
cells in a computer executable language; and

at least one entry in the cell library comprising a specification of physical structures and timing parameters of a circuit
including:

a first transistor,
a second transistor, and
an interconnect connecting a terminal of the first transistor to a terminal of the second transistor, the interconnect comprising
one or more nanowires or 2D material strips arranged in parallel,

wherein said one or more nanowires or 2D material strips of the interconnect includes/include a set of nanowires or 2D material
strips disposed in a plurality of stacks.

US Pat. No. 9,471,745

CHIP CROSS-SECTION IDENTIFICATION AND RENDERING ANALYSIS

Synopsys, Inc., Mountain...

1. A computer-implemented method for circuit analysis comprising:
identifying a portion of a semiconductor chip based on a layout for a design for the semiconductor chip;
generating virtual cuts for a cross section of the layout; and
rendering, using one or more processors, the layout into a three-dimensional view of the portion that was identified using
the virtual cuts that were generated, wherein the rendering is based on a three-dimensional simulation that includes structural
generation.

US Pat. No. 9,465,616

INSTRUCTION CACHE WITH WAY PREDICTION

Synopsys, Inc., Mountain...

1. An integrated circuit comprising:
an instruction cache comprising a plurality of fetch blocks, each fetch block of the plurality of fetch blocks associated
with a location in the instruction cache and a cache tag identifying a location of the fetch block in memory;

a branch prediction module, configured to generate a way prediction identifying a location in the instruction cache associated
with a predicted fetch block and a cache tag associated with the predicted fetch block; and

an instruction fetch unit configured to:
retrieve, based on the way prediction, a first fetch block from the instruction cache located at the location identified by
the way prediction;

compare the cache tag associated with the retrieved first fetch block with the cache tag associated with the predicted fetch
block; and

validate, based on the comparison, that the retrieved first fetch block is the predicted fetch block predicted by the way
prediction.

US Pat. No. 9,342,645

METHOD FOR TESTING A COMPUTER PROGRAM

Synopsys, Inc., Mountain...

1. A method for testing a circuit specification after changing a first version of the circuit specification into a second
version of the circuit specification due to a revision of the circuit specification, the method comprising:
receiving, at one or more computer systems, a first set of mutations associated with the first version of the circuit specification
and a second set of mutations associated with the second version of the circuit specification;

identifying, with the one or more processors associated with one or more computer systems, changed and unchanged mutations
in the first set of mutations and in the second set of mutations based on a comparison between the second version of the circuit
specification and the first version of the circuit specification, wherein

mutations that can be inserted only in the first version of the circuit specification or only in the second version of the
circuit specification are identified as changed mutations, and mutations that can be inserted in the first version of the
circuit specification and the second version of the circuit specification are identified as unchanged mutations; and

generating, with the one or more processor associated with the one or more computer systems, information configured to test
the second version of the circuit specification using at least a portion of the identified mutations classified as the changed
mutations.

US Pat. No. 9,338,463

VISUAL QUALITY MEASURE FOR REAL-TIME VIDEO PROCESSING

Synopsys, Inc., Mountain...

1. A method of measuring a visual quality of a processed image, comprising:
receiving a first image and a second image, wherein the second image is a processed version of the first image;
for each block in the first image, estimating a mean square error between the block in the first image and a block in the
second image corresponding to the block in the first image based on quantization thresholds and quantization invariants used
by an encoder;

determining a first set of variances of pixel values in a pixel domain or transform coefficients in a transform domain for
each block in the first image;

estimating a second set of variances of pixel values or transform coefficients for each block in the second image based on
the quantization thresholds and quantization invariants used by the encoder; and

computing a measure of the visual quality of the second image based at least in part on the estimated mean square errors,
the first set of variances and the second set of variances.

US Pat. No. 9,317,636

SYSTEM AND METHOD FOR STOPPING INTEGRATED CIRCUIT SIMULATION

Synopsys, Inc., Mountain...

1. A method for debugging an electronic hardware design, the electronic hardware design comprising a plurality of simulated
hardware modules configured to operate in parallel and having a simulated state, the method comprising:
receiving, during execution of a simulation of the simulated hardware modules, a plurality of simulation stop requests requesting
stoppage of the simulation from a plurality of simulation stoppers associated with a plurality of debuggers for the simulated
hardware modules, the simulation stop requests including a first simulation stop request corresponding to a first simulated
hardware module and generated in response to hitting of a breakpoint during execution of the simulation, the simulation stop
requests including a second simulated stop request corresponding to a second simulated hardware module and generated during
execution of the simulation;

responsive to receiving the simulation stop requests including the first simulation stop request and the second simulation
stop request, creating a plurality of active simulation stopper entries for the plurality of simulation stoppers in a list
of active simulation stoppers;

reaching a synchronization point of the simulation that is subsequent to the simulation stop requests, the simulated state
of the simulation hardware modules being synchronized at the synchronization point;

at the synchronization point of the simulation, stopping the simulation and repeatedly performing the following steps until
the list of active simulation stoppers is empty:

executing a corresponding investigative agent for the corresponding active simulation stopper entry;
removing the corresponding active simulation stopper entry from the list of active simulation stoppers; and
continuing the simulation responsive to the list of active simulation stoppers being empty.

US Pat. No. 9,280,326

COMPILER RETARGETING BASED ON INSTRUCTION SEMANTIC MODELS

Synopsys, Inc., Mountain...

1. A computer implemented method for generating a description of compiler code selector rules from an architecture description,
the compiler code selector rules for use in a compiler that translates source code into machine instructions of a target processor,
the method comprising:
accessing a target processor architecture model of the target processor, the target processor architecture model described
in a processor architecture description language, the target processor architecture model comprising semantic information
and syntax information for the machine instructions, and description of non-terminals of the target processor;

generating a plurality of semantic statements from semantic information included in the processor architecture model;
applying, to said semantic information, at least one semantic transformation from a library of pre-defined semantic transformations
to generate a single semantic statement from a sequence of at least two of said plurality of semantic statements;

generating a plurality of basic rules that map from source code operations to machine instructions comprising:
accessing rules that map from source code operations to semantic patterns,
searching said semantic statements for matches to said semantic patterns, and
mapping a sequence of two or more source code operations to a single machine instruction based on the accessed rules that
matches from semantic statements to semantic patterns; and

permuting said basic rules with non-terminals to generate a plurality of mappings that serve as said description of said compiler
code selector rules.

US Pat. No. 9,275,177

SEMI-LOCAL BALLISTIC MOBILITY MODEL

Synopsys, Inc., Mountain...

1. A computer-implemented method of simulating a semiconductor device, the method comprising:
establishing a maximum energy associated with a carrier entering a region of the semiconductor device;
defining a maximum kinetic energy associated with the carrier in accordance with the maximum energy and further in accordance
with a position of the carrier within the region; and

computing a velocity of the carrier in accordance with the maximum kinetic energy and further in accordance with one or more
scatterings, said maximum kinetic energy establishing an upper bound for a velocity of the carrier.

US Pat. No. 9,460,034

STRUCTURED BLOCK TRANSFER MODULE, SYSTEM ARCHITECTURE, AND METHOD FOR TRANSFERRING

Synopsys, Inc., Mountain...

1. A method for transferring data from a source processing unit to a destination processing unit, the method comprising:
selecting a first source processing unit comprising a source processor and a source memory configured to store data, the source
memory being a private memory of the source processor;

selecting a first destination processing unit comprising a destination processor and a destination memory configured to store
data, the destination memory being a private memory of the destination processor;

marking, by a connection manager, the destination memory in the selected first destination processing unit as no longer available;
copying, by a copy engine controlled by the connection manager, a block of data from the source memory into the destination
memory, wherein copying comprises:

altering a portion of the block of data by passing replacement data through a multiplexer of the copy engine to the destination
memory responsive to receiving a first signal at the multiplexer, and

passing unaltered data for another portion of the block of data through the multiplexer to the destination memory responsive
to receiving a second signal at the multiplexer; and

marking the source memory in the selected first source processing unit as available in response to copying the block of data.

US Pat. No. 9,390,222

DETERMINING A SET OF TIMING PATHS FOR CREATING A CIRCUIT ABSTRACTION

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool in a computer, a method for determining a set of timing paths for creating
a circuit abstraction, the method comprising:
receiving, by the EDA tool in the computer, a circuit element in the circuit design that is a candidate for optimization;
identifying, by the EDA tool in the computer, critical timing paths in the circuit design whose delay is affected by a change
in an input capacitance of the circuit element, wherein said identifying includes identifying at least one critical timing
path that does not pass through the circuit element, but whose delay is affected by a change in an input capacitance of the
circuit element; and

creating, by the EDA tool in the computer, a circuit abstraction based at least on the identified critical timing paths.

US Pat. No. 9,384,309

GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool in a computer, a method for determining margin values, the method comprising:
determining, by the EDA tool in the computer, an arrival time at an output pin of a logic gate;
determining, by the EDA tool in the computer, a set of required times at the output pin of the logic gate, wherein each required
time in the set of required times is determined by propagating required times from timing endpoints backward to the output
pin of the logic gate, and wherein each required time in the set of required times is associated with a timing end-point in
a path-group;

determining, by the EDA tool in the computer, a first set of slack values at the output pin of the logic gate by computing
a difference between each required time in the set of required times and the arrival time;

determining, by the EDA tool in the computer, a second set of slack values for a set of timing end-points, wherein the set
of timing end-points does not include the output pin of the logic gate, wherein each slack value in the second set of slack
values is determined by computing a difference between a required time at a timing end-point in the set of timing end-points
and an arrival time at the timing end-point that was propagated forward to the timing end-point;

determining, by the EDA tool in the computer, a set of margin values at the output pin of the logic gate, wherein each margin
value is determined by computing a difference between a first slack value in the first set of slack values and a second slack
value in the second set of slack values; and

optimizing, by the EDA tool in the computer, the logic gate based on the set of margin values.

US Pat. No. 9,361,417

PLACEMENT OF SINGLE-BIT AND MULTI-BIT FLIP-FLOPS

Synopsys, Inc., Mountain...

1. A method of circuit design in an integrated circuit EDA flow for lithographic masks for production of integrated circuits
with a computer system, comprising:
generating with the computer system a placed, routed, and optimized circuit design in the integrated circuit EDA flow for
lithographic masks for production of integrated circuits, including:

with the computer system, performing a first placement for a netlist of the circuit design according to a first set of circuit
element positioning rules;

with the computer system, identifying a plurality of single-bit flip-flops in the circuit design including at least a first
set of single-bit flip-flops and a second set of single-bit flip-flops;

with the computer system, grouping the second set of single-bit flip-flops together as a first relative placement set of single-bit
flip-flops, and replacing the first set of single-bit flip-flops in the circuit design with at least a first set of multi-bit
flip-flops in the circuit design;

with the computer system, creating a second set of circuit element positioning rules for the first relative placement set
of single-bit flip-flops based on a result of the first placement, the second set of circuit element positioning rules specifying
positioning of the first relative placement set of single-bit flip-flops;

responsive to a design success with the first relative placement set of single-bit flip-flops in the circuit design, replacing
the first relative placement set of single-bit flip-flops in the circuit design, with at least a second set of multi-bit flip-flops
in the circuit design; and

with the computer system, completing placement, routing, and optimization of the netlist of the circuit design according to
the second set of circuit element positioning rules.

US Pat. No. 9,348,964

MASK3D MODEL ACCURACY ENHANCEMENT FOR SMALL FEATURE COUPLING EFFECT

Synopsys, Inc., Mountain...

1. A method of performing mask topography effect modeling on a mask design layout for integrated circuit design, the method
comprising, upon receiving the mask design layout:
generating scaling parameters for edge coupling effects, each scaling parameter having an associated combination of feature
width and space, wherein a sum of feature width and space associated with at least one scaling parameter is less than a minimum
pitch; and

using a computing device, applying a thick mask model comprising a plurality of edge-based kernels to the mask design layout
to create a mask 3D residual, comprising updating the plurality of edge-based kernels with the scaling parameters.

US Pat. No. 9,336,342

MEMORY HARD MACRO PARTITION OPTIMIZATION FOR TESTING EMBEDDED MEMORIES

Synopsys, Inc., Mountain...

1. A circuit included in an embedded memory, the circuit comprising:
a functional input port, a functional output port, and a functional memory data path from the functional input port to the
functional output port, the functional memory data path comprising:

an array of data buffer circuits including input latches located in peripheral memory circuitry included in a memory instance
instantiated on a die,

an array of memory cells, and
an array of sense amplifiers included in the memory instance, the array of sense amplifiers including output latches located
in the peripheral memory circuitry included in the memory instance;

a scan input port, a scan output port, and a scan data path from the scan input port to the scan output port, the scan data
path comprising:

an array of scan flops, at least one scan flop in the array of scan flops comprising:
an input latch located in the peripheral memory circuitry, and
an additional output latch located in the in test logic separate from the memory instance, the additional output latch having
an input coupled to the memory array and coupled to receive the output from the input latch located in the peripheral memory
circuitry, the additional output latch having an output coupled to the scan output port;

wherein the scan output port of the scan data path bypasses the array of memory cells; and
a built-in self-test (BIST) input port, a BIST output port, and a BIST data path from the BIST input port to the BIST output
port, the BIST input port operating as the functional input port when a BIST enable signal is set to a first logic level to
enable transmission of functional data through BIST data path and operating in BIST mode when the BIST enable signal is set
to a second logic level to enable transmission of BIST test data through the BIST data path, the BIST data path comprising:

at least one input latch from the input latches located in the peripheral memory circuitry;
the array of memory cells, and
at least one output latch from the output latches located in the peripheral memory circuitry included in the memory instance.

US Pat. No. 9,286,262

SCHEDULING IN A MULTICORE ARCHITECTURE

Synopsys, Inc., Mountain...

1. A method of scheduling threads, the method comprising:
analyzing, by a parent scheduler, an application to identify an application thread for execution, the parent scheduler associated
with a plurality of associated child schedulers, the parent scheduler configured to store a pointer to a most eligible child
scheduler;

providing, by the parent scheduler, the application thread to the most eligible child scheduler based on the stored pointer,
the most eligible child scheduler determined based on priority metrics received from each child scheduler; and

scheduling, by the most eligible child scheduler, the application thread for execution by a processor core of a multicore
processor associated with the most eligible child scheduler.

US Pat. No. 9,189,591

PATH-BASED FLOORPLAN ANALYSIS

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for computing a timing effort metric, the method comprising:
upon receipt of a circuit design layout that includes two circuit objects, computing a physical distance between the two circuit
objects;

computing a timing distance of a timing path between the two circuit objects, wherein the timing distance of the timing path
is equal to an intrinsic path slack of the timing path multiplied by a scaling factor, wherein the intrinsic path slack is
based on an intrinsic delay of the timing path between the two circuit objects, wherein the intrinsic delay of the timing
path is a sum of intrinsic delays of circuit elements along the timing path, and wherein the scaling factor is based on a
physical distance that corresponds to a unit delay; and

computing, by using one or more processors, the timing effort metric based on the physical distance and the timing distance,
wherein the timing effort metric indicates a level of difficulty of fixing a timing violation associated with the timing path
between the two circuit objects in the circuit design layout.

US Pat. No. 9,171,112

SEMICONDUCTOR HOLD TIME FIXING

Synopsys, Inc., Mountain...

1. A computer-implemented method for design analysis and modification comprising:
evaluating a semiconductor design based on ideal clocks;
estimating hold-time requirements for the design based on the ideal clocks;
allocating, using one or more processors, placement regions for the design wherein the placement regions are to be used during
hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins
on blocks within the design;

wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than
wiring of nets without hold-time violations; and

modifying the design by performing hold-time fixing on the design.

US Pat. No. 9,286,424

EFFICIENT WAVEFORM GENERATION FOR EMULATION

Synopsys, Inc., Mountain...

1. A non-transitory computer readable medium storing instructions, the instructions when executed by one or more processors
cause the one or more processors to:
receive a request for a design signal of a design under test (DUT);
identify one or more partitions of the DUT to be emulated based on the request for the design signal, the one or more partitions
selected to minimize a number of emulation signals traced during emulation;

store information indicating signals obtainable from the one or more partitions of the DUT, describing designs of a plurality
of sections of the DUT, indicating signals obtainable from the plurality of sections, and indicating signals used in simulating
each of the plurality of sections;

receive, from an emulator, an emulation signal of the DUT traced by the emulator based on emulation of the one or more partitions
of the DUT;

determine, from the plurality of sections of the DUT, a subset of sections to simulate to produce the design signal, based
on the stored information;

simulate the subset of sections based on the emulation signal; and
produce the design signal based on the simulation of the subset of sections.

US Pat. No. 9,280,632

METHODS AND APPARATUSES FOR CIRCUIT DESIGN AND OPTIMIZATION

Synopsys, Inc., Mountain...

1. A method implemented on a data processing system comprising a processor and a memory, the method, upon receipt of at least
a portion of an integrated circuit design comprising:
determining timing critical nets for the integrated circuit design using the processor;
identifying a set of elements and nets for each of the timing critical nets;
determining one or more islands from the union of timing critical nets having one or more common elements or nets;
identifying one or more sub-portions of the integrated circuit design corresponding to the islands;
executing a placer which places the one or more sub-portions of the integrated circuit design on a transformed representation
of the integrated circuit design, wherein at least one of the determining timing critical nets, identifying a set of elements
and nets, determining one or more islands, identifying one or more sub-portions, and executing a placer is performed using
the processor; and

storing the transformed representation of the design in the memory, wherein the stored transformed representation of the design
is used in the creation of an integrated circuit.

US Pat. No. 9,086,989

EXTENDING PROCESSOR MMU FOR SHARED ADDRESS SPACES

Synopsys, Inc., Mountain...

1. A method for accessing shared code on a system, wherein the system comprises a memory, a memory management unit (MMU) with
a shared address space identifier (SASID) register, and a translation lookaside buffer (TLB) entry with a shared bit, the
method comprising:
requesting a contents of a memory address in the memory, the request comprising a virtual address entry and an address space
identifier (ASID) entry;

responsive to the request, accessing the TLB entry, the TLB entry comprising the virtual address entry and a physical address
entry;

determining a state corresponding to a shared bit in the TLB entry;
responsive to the state of the shared bit, accessing the contents of the SASID register; and
responsive to a comparison of the contents of the SASID register and the ASID entry, accessing an address in the memory corresponding
to the physical address entry the comparison of the contents of the SASID register and the ASID entry comprising:

accessing the contents of the SASID register; and
accessing a bit in the contents of the SASID register denoted by the value of the ASID entry.

US Pat. No. 9,342,226

CYCLE-TAPPING TECHNIQUE FOR SELECTING OBJECTS

SYNOPSYS, INC., Mountain...

1. A computer-implemented method, comprising:
receiving a cursor location in an electronic design automation (EDA) environment, wherein the EDA environment includes multiple
objects;

determining a subset of the multiple objects based on the cursor location;
selecting a first object from the subset of multiple objects;
creating a first new object and populating at least one property of the first new object based on a corresponding property
of the first object, wherein creating the first new object comprises performing a first sequence of operations, and wherein
the first new object is a different type of object than the first object; and

in response to receiving error information that indicates that the first new object has an error,
removing the first new object,
receiving a selection of a second object from the subset of multiple objects, wherein the second object is selected by cycle-tapping
through the subset of the multiple objects, and

responsive to receiving the selection of the second object, creating a second new object by reapplying the first sequence
of operations and populating at least one property of the second new object based on a corresponding property of the second
object,

wherein the second new object is a different type of object than the second object.

US Pat. No. 9,281,030

CONTROLLING TIMING OF NEGATIVE CHARGE INJECTION TO GENERATE RELIABLE NEGATIVE BITLINE VOLTAGE

Synopsys, Inc., Mountain...

1. A memory device, comprising:
a plurality of memory bitcells arranged in columns and rows, each column of the bitcells connected by a pair of bitlines;
a write assist circuit connected to at least one pair of the bitlines and configured to inject negative charge to a bitline
of the pair of the bitlines to place the bitline in a negative voltage level in a write operation;

a column decoder configured to generate a column select signal indicating a column of the bitcells for the write operation,
delay of the column select signal changing at a first rate responsive to change in a supply voltage level of the memory device;
and

a trigger signal generator configured to generate a trigger signal to set time for injecting negative charge into the bitline
to place the bitline in the negative voltage level, delay of the trigger signal changing at a second rate higher than the
first rate responsive to change in the supply voltage level.

US Pat. No. 9,189,580

ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE

Synopsys, Inc., Mountain...

1. A method for developing an integrated circuit device simulation model for an integrated circuit in which a property of
a transistor of the circuit will be modified by effects of stress in a channel of the transistor, comprising the steps of:
providing a circuit layout for at least a portion of an integrated circuit device, the layout identifying a first transistor
for the device, the first transistor having a channel;

approximating a first stress, oriented in a longitudinal direction of the channel, induced in at least a portion of the channel;
approximating a second stress, induced in the channel portion and oriented laterally across the channel portion and perpendicular
to the longitudinal direction;

approximating stress-induced variation of a transistor property of the first transistor, in dependence upon both the first
and second stress approximations;

including in the simulation model transistor property variation information obtained in dependence upon the approximated stress-induced
variation of a transistor property of the first transistor; and

providing the simulation model for simulating the integrated circuit.

US Pat. No. 9,360,926

MEMORY POWER SUPPLY LOAD MANAGEMENT

Synopsys, Inc., Mountain...

1. A method of storing data, the method comprising:
receiving electronic data to be stored;
partitioning the data into multiple segments;
storing each segment in a memory during a separate write cycle;
determining, for each segment, a number of memory cells required for storing the respective segment; and
programming a compensation load, based on the determined number of memory cells, to cause power provided by a power supply
to remain substantially constant during the storing of each segment.

US Pat. No. 9,202,005

DEVELOPMENT AND DEBUG ENVIRONMENT IN A CONSTRAINED RANDOM VERIFICATION

SYNOPSYS, INC., Mountain...

1. A system to debug constraints in a design simulation, comprising:
a processor configured to execute modules; and
a memory storing the modules, the modules comprising:
a design verification environment configured to:
pause the design simulation and execute a constraint solver in response to reaching a breakpoint in the design simulation,
the design simulation including constraint information that includes a plurality of constraints,

extract a portion of the design simulation associated with a portion of the plurality of constraints,
present constraint static information that describes an organization of the portion of the plurality of constraints,
present constraint dynamic information that describes an activity level of the portion of the plurality of constraints,
receive a modification of the constraint information within the extracted portion of the design simulation,
execute a call to solve the portion of the plurality of constraints using the modified constraint information and the constraint
solver to generate one or more results, the one or more results including solutions for the portion of the plurality of constraints,

present the solutions, and
resume the design simulation using the modified constraint information without re-starting the design simulation.

US Pat. No. 9,317,298

GENERATION OF INSTRUCTION SET FROM ARCHITECTURE DESCRIPTION

Synopsys, Inc., Mountain...

1. A computer implemented method of generating an instruction set for an architecture, comprising:
accessing a hierarchical description of an architecture of node groups, wherein each node in a node group is associated with
at least one operation;

selecting a leaf node group within the architecture of node groups;
resolving path-split ambiguities for a node associated with a plurality of parent nodes associated with a path split from
a path within the architecture from the node to the selected leaf node group into a plurality of paths each associated with
a different parent node of the plurality of parent nodes by assigning a unique encoding for each operation associated with
a parent node of the plurality of parent nodes above the path split within the architecture based on a sum of encoding widths
associated with operations above the parent node within the architecture of node groups, each encoded operation associated
with an encoding width;

propagating the encoding widths associated with the encoded operations to the selected leaf node group; and
generating an instruction set associated with the leaf node group for each unique path from a root node group to the leaf
node group, each instruction set based on the propagated encoding widths associated with a unique path.

US Pat. No. 9,189,581

EQUIVALENCE CHECKING BETWEEN TWO OR MORE CIRCUIT DESIGNS THAT INCLUDE DIVISION CIRCUITS

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) software tool in a computer, a method for proving equivalence between a first
circuit design and a second circuit design, wherein the first circuit design includes a first division circuit and the second
circuit design includes a second division circuit, the method comprising:
the EDA software tool in the computer analyzing the first and second circuit designs to determine an input relationship between
a set of inputs of the first division circuit and a set of inputs of the second division circuit, wherein the set of inputs
of the first division circuit is different from the set of inputs of the second division circuit;

the EDA software tool in the computer determining an output relationship between a set of outputs of the first division circuit
and a set of outputs of the second division circuit based on the input relationship, wherein the input relationship is different
from the output relationship; and

the EDA software tool in the computer proving equivalence between the first and second circuit designs, wherein said proving
involves using the output relationship as an assumption.

US Pat. No. 9,379,183

METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE

SYNOPSYS, INC., Mountain...

1. A structure comprising a layer of crystalline phase material, the layer having a line of the crystalline phase material
formed therein, the line having first and second opposite sidewall surfaces,
wherein the line has a line width roughness between the first sidewall surface and the second sidewall surface that is less
than or equal to 1.5 nm.

US Pat. No. 9,258,320

SYSTEM FOR TESTING COMPUTER APPLICATION

SYNOPSYS, INC., Mountain...

1. A method for testing a computer program application in a server computer, the method comprising:
having a library database comprising library reference strings that distinguish each library from other libraries, the library
database further storing known suspicious features of libraries;

upon receiving a test request requesting the server computer to test suspicious behaviour associated with the computer program
application, performing the method by:

acquiring the computer program application on a basis of the test request;
applying at least one test routine to the computer program application and testing for suspicious behaviour associated with
the computer program application, wherein said testing comprises installing the computer program application to the server
computer, executing the computer program application, searching a computer program code of the computer program application
for the library reference strings, determining one or more libraries invoked by the computer program application on the basis
of the library reference strings found in the computer program code of the computer program application, cross-referencing
the library database with the libraries invoked by the computer program application and determining, on the basis of the comparison,
whether or not the computer program application comprises one or more of the suspicious features, monitoring an operation
of the computer program application and comparing behaviour;

creating a test report specifying at least some of the suspicious features, if any found during the at least one test routine,
and inserting results of said monitoring into the test report; and

communicating the test report.

US Pat. No. 9,081,924

METHOD AND APPARATUS FOR TRANSACTION RECORDING AND VISUALIZATION

Synopsys, Inc., Mountain...

1. A method, comprising:
receiving, at one or more computer systems, information generated in response to a simulation comprising transactions on a
device under test between multiple test bench components;

generating, with one or more processors associated with the one or more computer systems, a transaction database as a response
to the simulation;

generating, with the one or more processors associated with the one or more computer systems, an element of a sequence diagram
that visually represents both a temporal sequence between two or more data elements of a transaction between at least two
test bench components and a transaction passing sequence between each of the two or more data elements; and

generating, with the one or more processors associated with the one or more computer systems, information configured to display
the sequence diagram based on the element and storing the information configured to display the sequence diagram in a storage
device associated with the one or more computer systems;

wherein a transaction represented by an element in the sequence diagram is selected from data passed between two sequencers
and data passed between a sequencer and a driver.

US Pat. No. 9,058,447

MODIFYING A VIRTUAL PROCESSOR MODEL FOR HARDWARE/SOFTWARE SIMULATION

Synopsys, Inc., Mountain...

1. A method to transform a transformable virtual processor model to a user virtual processor model to simulate a user target
processor, the method comprising:
receiving a transformable virtual processor model, the transformable virtual processor model configured to perform, on a host
processor system, a behavior and timing accurate simulation of a seed target processor, the transformable virtual processor
model having a transformable instruction set and a transformable pipeline;

receiving one or more user-provided descriptions of the user target processor; and
transforming the received transformable virtual processor model to the user virtual processor model, wherein the user virtual
processor model is configured to perform, on the host processor system, a behavior and timing accurate simulation of the user
target processor according to the user-provided descriptions, wherein the transforming includes at least one of the following:

adding a new instruction associated with the user virtual processor model to the transformable instruction set of the transformable
virtual processor model;

modifying a definition of one or more instructions in the transformable instruction set of the transformable virtual processor
model according to the user virtual processor model; and

modifying a processor structure of the transformable virtual processor model by performing at least one of:
adding an additional pipeline associated with the user virtual processor model to the transformable virtual processor model;
and

modifying the transformable pipeline of the transformable virtual processor model according to the user virtual processor
model;

wherein at least one of the receiving, and transforming is performed by a processor.

US Pat. No. 9,208,278

CLUSTERING USING N-DIMENSIONAL PLACEMENT

Synopsys, Inc., Mountain...

1. A method of partitioning a design into smaller components upon receiving the design represented by a hypergraph with a
plurality of nodes, the method comprising:
by using a computing device, placing the plurality of nodes of the hypergraph into an N-dimensional space, wherein N is an
integer that is greater than 2;

identifying a set of hyperedges of the hypergraph based on a first set of criteria;
for each identified hyperedge, identifying pairs of nodes connected by the hyperedge based on a second set of criteria;
adding the identified pairs of nodes into a sorted list, wherein the sorted list is sorted based on a function of locations
for each identified pair of nodes; and

clustering identified pairs of nodes of the hypergraph;
wherein the clustering is used in the generation of an integrated circuit; andwherein the clustering of the identified pairs of nodes of the hypergraph comprises iteratively: selecting a pair of nodes
from the sorted list according to a sorted order, and merging the two nodes of the selected pair.

US Pat. No. 9,471,727

SIMULATION WITH DYNAMIC RUN-TIME ACCURACY ADJUSTMENT

Synopsys, Inc., Mountain...

1. A computer implemented simulation method comprising:
during a simulation, simulating a first portion of a sequence of instructions by a first simulation model of a processor;
during the simulation, receiving an accuracy control input from a debugger and switching from the first simulation model of
the processor to a second simulation model of the processor responsive to the accuracy control input from the debugger, the
second simulation model providing a different simulation speed and accuracy than the first simulation model; and

during the simulation, simulating a second portion of the sequence of instructions by the second simulation model of the processor
upon switching from the first simulation model to the second simulation model.

US Pat. No. 9,448,706

LOOP REMOVAL IN ELECTRONIC DESIGN AUTOMATION

SYNOPSYS, INC., Mountain...

1. A computer-implemented method for facilitating graphical object creation in an integrated circuit design layout by using
an electronic design automation (EDA) application, comprising:
obtaining a new point, the new point being a current position of a cursor, for inclusion in a sequence of points to create
a graphical object in the integrated circuit design layout;

determining a last rectilinear line segment between the new point and the last point in the sequence of points;
examining, in order from the first point in the sequence of points to the last point in the sequence of points, line segments
between consecutive points in the sequence of points to detect an intersection with the last rectilinear line segment;

in response to detecting an intersection between a line segment corresponding to two consecutive points and the last rectilinear
line segment,

removing, from the sequence of points, all points added after the earlier of the two consecutive points, and
appending the intersection point to the sequence of points;
appending the new point to the sequence of points; and
displaying a visual representation of the graphical object using the sequence of points including the intersection point and
the new point.

US Pat. No. 9,209,129

SELF-ALIGNED VIA INTERCONNECT USING RELAXED PATTERNING EXPOSURE

Synopsys, Inc., Mountain...

1. An integrated circuit comprising:
a first metal layer comprising a first metal trace having a first width;
a second metal layer above and immediately adjacent to said first metal layer, the second metal layer comprising a second
metal trace that is perpendicular to the first metal trace and has a second width;

a via coupling the first metal trace on said first metal layer to the second metal trace on said second metal layer;
said via extending in a first horizontal dimension to a width greater than the first width of said first metal trace; and
said via extending in a second horizontal dimension, perpendicular to said first horizontal dimension, to a length substantially
equal to the second width of said second metal trace.

US Pat. No. 9,459,992

SYSTEM AND METHOD OF DEBUGGING MULTI-THREADED PROCESSES

Synopsys, Inc., Mountain...

1. A method of debugging a platform, said method comprising:
detecting a breakpoint event of a simulator that is communicatively coupled to a debugger, the simulator comprising a first
thread simulating the platform, a second thread implementing a first interprocess communication channel between the simulator
and an embedded software debugger that is different than the debugger and a third thread implementing a second interprocess
communication channel between the simulator and a component that is different than the debugger and different than the embedded
software debugger and external to the simulator;

blocking, using the debugger and responsive to detecting the breakpoint event, the first thread simulating the platform while
allowing the second thread implementing the first interprocess communication channel to operate and allowing the third thread
implementing the second interprocess communication channel to operate; and

communicating using the second thread implementing the first interprocess communication channel and the third thread implementing
the second interprocess communication channel while the first thread simulating the platform is blocked, the embedded software
debugger accessing a state of the platform using the second thread during the communicating.

US Pat. No. 9,430,595

MANAGING MODEL CHECKS OF SEQUENTIAL DESIGNS

Synopsys, Inc., Mountain...

1. A method of model checking a first circuit model of a first circuit design comprising:
receiving a request from a user for a model check of the first circuit model including a set of test parameters of the model
check to verify the first circuit model meets a set of specifications thereby verifying the circuit design meets specifications;

responsive to receiving the user request, utilizing a processor to generate a first signature of the requested first circuit
model and a subset of the test parameters to verify the first circuit model meets the set of specifications;

utilizing the generated first signature to identify a potentially equivalent subset of prior circuit models from a database
of signatures of previously tested prior circuit models stored in memory with corresponding prior test parameters and test
results for each of the previously tested prior circuit models;

utilizing the processor to determine whether the requested first circuit model is functionally equivalent to one of the identified
subset of prior circuit models; and

in response to determining functional equivalence, utilizing the processor to provide the corresponding prior test results
for the functionally equivalent prior circuit model to the user for use as model check results of the first circuit model.

US Pat. No. 9,430,427

STRUCTURED BLOCK TRANSFER MODULE, SYSTEM ARCHITECTURE, AND METHOD FOR TRANSFERRING

Synopsys, Inc., Mountain...

1. A system for copying data, the system comprising:
a source processing unit comprising a source processor and a source memory configured to store a plurality of blocks of data,
the source memory being a private memory of the source processor;

a first destination processing unit comprising a first destination processor and a first destination memory that is a private
memory of the first destination processor;

a structured block transfer module (SBTM) comprising:
a connection manager coupled to the source processing unit and the first destination processing unit, the connection manager
configured to:

receive a request to copy a block of data of the plurality of blocks of data, the block of data stored at a source memory
location of the source memory,

obtain the source memory location of the block of data, and
select a destination memory location of the first destination memory available to store the block of data; and
a first copy engine configured to copy the block of data from the source memory location to the destination memory location
in response to receiving a signal from the connection manager; and

a replacement engine coupled to the first copy engine and at least one of the source processing unit and the first destination
processing unit, the replacement engine configured to modify at least a portion of the copied data block, the replacement
engine comprising:

a value loader outputting a replacement data signal,
a replace controller outputting a replace signal in response to a start counter greater than or equal to a threshold and a
length counter less than a threshold, and

a multiplexing unit configured to replace data from the source processing unit with data from the replacement data signal
in response to the replace signal.

US Pat. No. 9,418,042

MEMORY INTERFACE AND METHOD OF INTERFACING BETWEEN FUNCTIONAL ENTITIES

Synopsys, Inc., Mountain...

1. A processing device, comprising:
a reduced instruction set computer (RISC) processor core having an instruction decode stage;
a memory interface having:
one or more first ports to couple to a memory array,
one or more second ports, and
data transfer fabric for data communication between the one or more first ports and the one or more second ports; and
a processor coupled to the one or more second ports of the memory interface, the processor operating under control of least
one of (1) the instruction decode stage of the RISC processor core and (2) an auxiliary register associated with the RISC
processor core,

the memory interface further comprising a function controller associated with the one or more second ports and having a plurality
of registers, the function controller controlling a function of the processor.

US Pat. No. 9,378,320

ARRAY WITH INTERCELL CONDUCTORS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS

SYNOPSYS, INC., Mountain...

1. A computer system adapted to process a computer implemented representation of a circuit design, comprising:
a processor and a memory coupled to the processor, the memory storing instructions that, when executed by the processor, cause
the processor to select cells from a cell library;

the cell library including entries for a plurality of cells, the entries in the cell library including specifications of particular
cells in a computer executable language; and

at least one entry in the cell library comprising a specification of physical structures and timing parameters of
an array of circuit cells, wherein one or more circuit cells in the array each including one or more transistors and one or
more cell interconnect terminals; and

a conductor configured to connect cell interconnect terminals of a plurality of the circuit cells in the array, the conductor
comprising one or more nanowires or 2D material strips arranged in parallel.

US Pat. No. 9,280,668

METHODS AND SYSTEMS OF DETECTING AND ANALYZING CORRELATED OPERATIONS IN A COMMON STORAGE

Synopsys, Inc., Mountain...

1. A method of detecting correlated operations in a common storage, comprising:
triggering a series of input operations which are performed by a plurality of application components of a network application
to induce the writing of uniquely identifiable data to a storage location of a memory unit of said network application;

monitoring a plurality of output operations of said application, each said output operation includes data read from said memory
unit;

identifying a group of input and output operations from a plurality of different application components of said network application
according to at least one correlation between at least some of said plurality of input operations and at least some of said
plurality of output operations, said at least one correlation is identified when said at least some output operations includes
reading said uniquely identifiable data from said storage location of said memory unit, wherein said storage location is a
common storage location for said uniquely identifiable data which has been written and read; and

outputting an indication of a sharing of said common storage location by input and output operations of said plurality of
application components.

US Pat. No. 9,135,386

MULTI-MODE SCHEDULER FOR CLOCK TREE SYNTHESIS

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for performing clock tree synthesis (CTS) in a circuit design,
the method comprising:
traversing one or more clock trees from a root of each clock tree to a set of sinks of the clock tree, wherein said traversing
is performed across different clocks and modes;

wherein while performing said traversing, marking each gate in the one or more clock trees with a traversal level, and marking
each sink with one or more clocks and one or more modes that are associated with the sink;

creating a task queue for a CTS engine, wherein each task is associated with a gate in the one or more clock trees, wherein
each task specifies instructions for synthesizing or modifying a clock tree, and wherein tasks are scheduled in the task queue
in decreasing traversal level of the associated gate; and

providing the task queue to the CTS engine, wherein the CTS engine synthesizes and optimizes the one or more clock trees based
on the tasks in the task queue, and wherein the circuit design is subsequently provided to a semiconductor fabrication facility
for producing integrated circuit chips.

US Pat. No. 9,454,635

VIRTUAL LAYER GENERATION DURING FAILURE ANALYSIS

Synopsys, Inc., Mountain...

1. A computer-implemented method for design analysis comprising:
selecting, from a layout design for a semiconductor chip design, a plurality of shapes from the layout design;
manipulating the plurality of shapes by performing an operation on the plurality of shapes;
generating, using one or more processors, a new shape based on the manipulating, wherein the new shape substantially matches
a manufactured shape or a defect overlaying a physical chip image with the new shape wherein the overlaying includes using
an operation on multiple shapes to create the new shape and wherein the new shape shows an intended semiconductor design after
fabrication processes; and

using the new shape in failure analysis of a semiconductor chip based on the semiconductor chip design.

US Pat. No. 9,503,255

CRYPTOGRAPHIC SEQUENCING SYSTEM AND METHOD

Synopsys, Inc., Mountain...

1. A method for leak resistant ciphering comprising:
providing a first stream of data and an associated first secret key;
expanding the associated first secret key to form a first associated expanded secret key;
providing a second simultaneous stream of data and an associated second secret key;
expanding the associated second secret key to form a second associated expanded secret;
intermixing the first stream of data and the second stream of data to form a combined stream of data;
ciphering the combined stream of data in accordance with the first and second associated expanded secret keys by interleaving
rounds to form a ciphered combined stream wherein ciphering of the combined stream of data is performed within a fixed window
of time such that Gpre+Gpost is equal to a constant, the fixed window of time filled with ciphering of the combined stream of data and other data;

de-multiplexing the ciphered combined stream of data to form de-multiplexed streams of data;
providing the de-multiplexed streams of data at an output port;
combining the processing of multiple simultaneous streams of data affords the opportunity to obfuscate the power signatures
of each individual stream; and

determining Gpre by a scheduling system, Gpre varying between different intermixed streams of data.

US Pat. No. 9,430,442

SOLVING A GATE-SIZING OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER

SYNOPSYS, INC., Mountain...

1. A method for using a constraints solver to solve a gate optimization problem for a portion of a circuit design, the method
comprising:
creating a constraints problem based on the gate-sizing optimization problem for the portion of the circuit design, wherein
the constraints problem comprises: (1) a constraint for each equation in the gate-sizing optimization problem, (2) a set of
upper bound constraints that impose an upper bound on one or more variables that are used in the objective function of the
gate-sizing optimization problem, (3) constraints that impose upper bounds, lower bounds, or both upper bounds and lower bounds
on capacitance variables based on one or more of (i) estimated capacitance values, (ii) maximum capacitance values of gates
in a technology library, and (iii) minimum capacitance values of gates in the technology library, and (4) a task definition
that computes the value of the objective function of the gate-sizing optimization problem; and

solving the gate-sizing optimization problem by repeatedly solving the constraints problem using a constraints solver that
is executing on a processor, wherein prior to each invocation of the constraints solver the upper bound is increased or decreased
based at least on a result returned by a previous invocation of the constraint solver.

US Pat. No. 10,510,402

MITIGATING WRITE DISTURBANCE IN DUAL PORT 8T SRAM

Synopsys, Inc., Mountain...

1. A static random access memory (SRAM) device, the SRAM device comprising a plurality of dual-port SRAM cells arranged in rows and columns, each SRAM cell comprising:a pair of cross-coupled inverters having a first data port coupled to a first word line, a first bit line, and a first bit-complement line, and further having a second data port coupled to a second word line, a second bit line, and a second bit-complement line,
wherein the first bit line is connected to a first data terminal through a first data transmission switch responsive to a first port write signal, and to a second data terminal through, in series, a second data transmission switch responsive to a second port write signal and a first cross-connect switch responsive to a write disturb enable signal,
wherein the second bit line is connected to the second data terminal through a third data transmission switch responsive to the second port write signal, and to the first data terminal through, in series, a fourth data transmission switch responsive to the first port write signal and a second cross-connect switch responsive to the write disturb enable signal,
wherein the first bit-complement line is connected to a first data-complement terminal through a fifth data transmission switch responsive to the first port write signal, and to a second data-complement terminal through, in series, a sixth data transmission switch responsive to the second port write signal and a third cross-connect switch responsive to the write disturb enable signal, and
wherein the second bit-complement line is connected to the second data-complement terminal through a seventh data transmission switch responsive to the second port write signal, and to the first data-complement terminal through, in series, an eighth data transmission switch responsive to the first port write signal and a fourth cross-connect switch responsive to the write disturb enable signal.

US Pat. No. 9,195,789

INCREMENTAL FUNCTIONAL VERIFICATION OF A CIRCUIT DESIGN

Synopsys, Inc., Mountain...

1. A method for incrementally verifying a circuit design, the method comprising:
(a) representing a first subset of modules in the circuit design by one or more interpretive computer programming modules,
wherein the circuit design is used to manufacture integrated circuits;

(b) representing a second subset of modules in the circuit design by one or more hardware descriptive language (HDL) modules;
(c) performing simulation of a mixed design which represents the first subset of the circuit design by the one or more interpretive
computer programming modules and represents the second subset of the circuit design by the one or more HDL modules;

(d) translating a part of the first subset of modules into a HDL module to include the part of the first subset in the second
subset of modules and remove the part from the first subset of modules, responsive to the simulation of the mixed design being
successful; and

(e) repeating (a) through (d) at least once until no module for translation remain in the first subset of modules.

US Pat. No. 9,141,807

SECURITY REMEDIATION

Synopsys, Inc., Mountain...

1. A method to remediate a defect in first computer program code used to configure a first computer to produce code in response
to a request from a different computer configured using second computer program code, to use the produced code to parse one
or more contexts within the produced code, each context corresponding to one or more parser states and to generate output
information, the method comprising:
configuring a computer to perform static analysis of the first computer program code that includes,
simulating the first computer configured, to produce, in a non-transitory computer readable storage device, at least a portion
of the produced code that includes one or more contexts;

simulating the different computer configured, to identify one or more parser states that correspond to the one or more contexts
in the at least a portion of the produced code;

producing a first information structure in a non-transitory computer readable storage device that associates a respective
code statement of the first computer program code with at least one context that corresponds to at least one identified parser
state; and

configuring a computer to perform a static analysis of the first computer program code that includes,
running multiple checkers to identify one or more defect types in the first computer program code;
producing a second information structure in a non-transitory computer readable storage device that associates the respective
code statement of the first computer program code with the one or more identified defect types;

identifying a technology used by the first computer program code to represent the respective code statement; and
determining a remediation for an identified defect type that is associated by the second information structure with the respective
code statement, based upon at least, the at least one context that is associated by the first information structure with the
respective code statement, and the identified technology.

US Pat. No. 9,275,182

PLACING TRANSISTORS IN PROXIMITY TO THROUGH-SILICON VIAS

Synopsys, Inc., Mountain...

17. An EDA tool on a computer readable medium executable by the computer system to transform a hardware description language
circuit representation into a physical circuit representation, comprising:
a layout tool on a computer readable medium making a circuit design comprising a TSV causing stress in a substrate and a first
transistor,

the layout tool permitting rotation of the first transistor to cause a longitudinal axis of the first transistor and a tangential
direction of the TSV to coincide.

US Pat. No. 9,417,951

METHOD AND APPARATUS FOR CIPHER FAULT DETECTION

Synopsys, Inc., Mountain...

1. A method comprising:
providing data for ciphering thereof; and;
ciphering the data in a plurality of cipher rounds, each round comprising:
determining an encoding for error detection of data for being processed within the round,
determining an output error detection encoding for the round,
processing the data for being processed within the round to provide output error detection encoding,
verifying the output error detection encoding against the determined output error detection encoding, and
when the output error detection encoding is other than same as the determined error detection encoding, providing a signal
indicative of an error within the cipher process.

US Pat. No. 9,405,878

GENERATING A CIRCUIT DESCRIPTION FOR A MULTI-DIE FIELD-PROGRAMMABLE GATE ARRAY

Synopsys, Inc., Mountain...

1. A system for generating a circuit description for a multi-die field-programmable gate array (FPGA) comprising a first FPGA
die and at least one further FPGA die, the system comprising:
a processor; and
a memory storing instructions executable by the processor, the instructions when executed cause the processor to:
evaluate, automatically, a first partition and a second partition of a partitioned circuit description, the first partition
being associated with the first FPGA die and the second partition being associated with the at least one further FPGA die;

insert at least one multiplexing element into the first partition and a corresponding de-multiplexing element into the second
partition based on the automated evaluation; and

perform one of:
execute, in response to direct physical connections between the first partition and the second partition with the first FPGA
die and second FPGA die located adjacent within the multi-die FPGA, direct signal transmission between the first partition
and the second partition; and

execute, in response to indirect inter-die connections between the first partition and the second partition with at least
a third FPGA die inserted between the first FPGA die and the second FPGA die, insertion of at least one intermediate register
in the third FPGA die, the third FPGA die being associated with a third partition of the partitioned circuit description.

US Pat. No. 9,201,992

METHOD AND APPARATUS USING FORMAL METHODS FOR CHECKING GENERATED-CLOCK TIMING DEFINITIONS

Synopsys, Inc., Mountain...

1. A method implemented as a generated-clock checker tool in a programmable computing system for checking timing definitions
of generated-clocks against a register-level design for an integrated circuit, the method comprising:
constructing waveform models from both user-specified timing definitions and a register-level design for each generated clock,
by considering all logic paths from a master clock to each generated-clock, and keeping track of any inversions in a logic
path, while ignoring any combinational logic unrelated to clock generation, and generating finite state machines to represent
the waveform models;

comparing, using formal methods, the two sets of constructed waveform models obtained from the timing definitions and the
register-level design, by using a satisfiability checker to compare the finite state machines; and

reporting, by using the programmable computing system, any discrepancies found between the two sets of waveforms.

US Pat. No. 9,400,862

CELLS HAVING TRANSISTORS AND INTERCONNECTS INCLUDING NANOWIRES OR 2D MATERIAL STRIPS

SYNOPSYS, INC., Mountain...

1. A computer system adapted to process a computer implemented representation of a circuit design, comprising:
a processor and memory coupled to the processor, the memory storing instructions executable by the processor, including instructions
to select cells from a cell library;

the cell library including entries for a plurality of cells, entries in the cell library including specifications of particular
cells in a computer executable language; and

at least one entry in the cell library comprising a specification of a cell including
a plurality of transistors and an interconnect; wherein
a transistor in the plurality has a channel comprising one or more nanowires or 2D material strips arranged in parallel, and
the interconnect comprises one or more nanowires or 2D material strips arranged in parallel and connected to terminals of
more than one of the transistors in the plurality of transistors.

US Pat. No. 9,390,221

LINEAR COMPLEXITY PRIORITIZATION OF TIMING ENGINEERING CHANGE ORDER FAILURES

Synopsys, Inc., Mountain...

1. A computer-implemented method for displaying an output of a timing violation fixing in a circuit design for manufacturing
of an integrated circuit, the method comprising:
determining, by an analysis tool a plurality of timing violations in the circuit design of the integrated circuit, each timing
violation associated with a timing path, each timing path including a plurality of cells, the plurality of timing violations
comprising a first timing violation and a second timing violation, wherein the plurality of timing violations are identified
responsive to determining that the plurality of timing violations cannot be fixed by replacing one or more cells of the timing
path associated with the timing violation;

determining, for a first timing path associated with the first timing violation, a reason why one or more cells of the first
timing path cannot be automatically replaced by the analysis tool;

determining a priority for fixing, in the circuit design, each of the plurality of timing violations; and
outputting information describing the plurality of timing violations, the outputting comprising:
outputting information for the first timing violation and information for the second timing violation, and an indication of
the priority of the first timing violation compared to the priority of the second timing violation, and

outputting an indication of the reason why the one or more cells of the first timing path associated with the first timing
violation cannot be automatically replaced by the analysis tool.

US Pat. No. 9,355,860

METHOD FOR ACHIEVING UNIFORM ETCH DEPTH USING ION IMPLANTATION AND A TIMED ETCH

Synopsys, Inc., Mountain...

1. A wafer comprising:
ridged semiconductor material subjected to a first ion implantation, thereby damaging the ridged semiconductor material;
an isolation material formed between ridges of the ridged semiconductor material, the isolation material subjected to the
first ion implantation, thereby damaging the isolation material, and then etched to a precise depth having a variation less
than 10% across the wafer; and

a dielectric layer disposed on a top surface of each said ridge, and extending down each side surface of each said ridge to
said isolation material.

US Pat. No. 10,032,521

PUF VALUE GENERATION USING AN ANTI-FUSE MEMORY ARRAY

Synopsys, Inc., Mountain...

13. A method of Physical Unclonable Function (PUF) value generation, comprising:applying a first voltage to first terminals of a pair of anti-fuse memory cells that are electrically coupled to each other;
applying a second voltage to second terminals of the pair of anti-fuse memory cells that are electrically coupled to each other, the first voltage and the second voltage being effective for programming an anti-fuse memory cell;
forming a conductive link in a first anti-fuse memory cell of the pair of anti-fuse memory cells in response to the first voltage and the second voltage, to conduct current from the first terminals to the second terminals; and
changing a voltage level of the first terminals in response to the current conducted from the first terminals to the second terminals, that is effective for inhibiting programming a second anti-fuse memory cell of the pair of anti-fuse memory cells.

US Pat. No. 9,292,650

IDENTIFYING LAYOUT PATTERN CANDIDATES

Synopsys Inc., Mountain ...

1. A method of automatically identifying layout pattern candidates in selected regions for use in analyzing semiconductor
device performance issues comprising:
identifying a set of target regions and a set of reference regions from a design layout;
identifying individual clips in the set of reference regions and the set of target regions;
clustering the individual clips by layout pattern similarity to generate a reference baseline of layout patterns from the
set of reference regions including determining a first frequency of reference layout patterns in the set of reference regions;

clustering the individual clips by layout pattern similarity from the set of target regions to determine a second frequency
of target layout patterns in the set of target regions;

comparing the second frequency of target layout patterns in the set of target regions to the first frequency of reference
layout patterns in the reference baseline;

based on the comparison, identifying candidate layout patterns from the set of target regions for further analysis;
determining whether any of the candidate clip patterns caused a performance issue in the target region; and
upon a positive determination, correcting the candidate layout pattern to correct the performance issue.

US Pat. No. 9,311,437

MODELING A BUS FOR A SYSTEM DESIGN INCORPORATING ONE OR MORE PROGRAMMABLE PROCESSORS

Synopsys, Inc., Mountain...

1. A method for processing data in a transaction through a virtual bus structure model after inclusion of the virtual bus
structure model in one or more system designs including one or more programmable processors, the virtual bus structure model
in the system designs located between a sender of data and a receiver of data, wherein the sender of data is configured to
write data through the transaction and the receiver of data is configured to read data through the transaction, the method
comprising:
determining a number of data beats to commit to supply from a sender of data to a receiver of data;
marking a data channel as busy;
indicating a simulated time at which the first of the committed data beats will be available from the sender of data;
signaling the receiver of data that the number of data beats is available;
determining a number of data payloads needed to transfer the number of data beats;
determining the point in simulated time at which the last of the data beats will be accepted by the receiver of data; and
signaling the sender of data the acceptance of a data payload by the receiver of data, wherein the sender of data sends the
data within the committed data beats ahead of simulation time to a receiver of data without compromising cycle accuracy of
the data.

US Pat. No. 9,170,481

SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION USING SHOT OPTIMIZATION

Synopsys, Inc., Mountain...

1. A computer-implemented method for shape analysis comprising:
determining a desired fabricated shape based on a semiconductor chip design layout corresponding to a physical chip, wherein
the desired fabricated shape corresponds to the semiconductor design layout;

evaluating the semiconductor design layout to determine mask shapes, wherein the mask shapes include an assist feature which
is determined comprising:

analyzing the semiconductor design layout to evaluate desired fabricated shapes using the assist feature to aid in fabrication
of the desired fabricated shapes;

selecting a glyph that approximates the assist feature; and placing the glyph within the mask shapes;
establishing a shot density for shots used to generate mask shapes;
approximating, using one or more processors, mask shapes using shots based on the shot density;
estimating a resulting fabricated semiconductor layout based on the shots;
modifying the shots to make the resulting fabricated semiconductor layout to be closer to the desired fabricated shape; and
storing information on the shots onto computer storage media.

US Pat. No. 9,342,439

COMMAND COVERAGE ANALYZER

Synopsys, Inc., Mountain...

1. A dynamic code analysis tool comprising:
a first extractor for extracting a set of software product configurations upon receipt of a software product;
a second extractor for extracting a set of test suite configurations upon receipt of a test suite for the software product;
a CCA engine for analyzing a set of commands within the set of test suite configurations to a set of commands within the set
of software product configurations; and

a report generator for communicating the relationship between the commands within the set of test suite configurations (test
suite commands) to the commands within the set of software product configurations (software product commands).

US Pat. No. 9,189,583

LOOK-UP BASED BUFFER TREE SYNTHESIS

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) software tool, a method for synthesizing a buffer tree, the method comprising:
receiving a source node and a set of sink nodes; and
constructing the buffer tree by recursively performing at least the following operations by starting from the set of sink
nodes and progressively moving toward the source node:

forming one or more clusters by grouping one or more sink nodes together;
determining a capacitive load for each cluster;
performing a table lookup on a lookup table based on the capacitive load to obtain an optimal size of a buffer or an inverter
and an optimal spacing, wherein the lookup table associates capacitive load values with corresponding optimal buffer or inverter
sizes and optimal spacing values; and

placing the buffer or the inverter of the optimal size at one or more locations in the buffer tree based on the optimal spacing.

US Pat. No. 9,141,737

ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE

SYNOPSYS, INC., Mountain...

1. A system for developing an integrated circuit device simulation model for an integrated circuit in which a property of
a transistor of the circuit will be modified by effects of stress in a channel of the transistor, wherein:
the system is configured to determine, for the simulation model, an approximation of the stress in each of a plurality of
sites in the channel;

the system is configured to convert each of the stress approximations to a respective transistor property adjustment value;
and

the system is configured to include in the simulation model a combined transistor property adjustment value for the transistor
obtained in dependence upon a combination of the transistor property adjustment values developed in the act of converting,

the simulation model being provided for simulating the circuit.

US Pat. No. 9,171,123

DIAGNOSIS AND DEBUG USING TRUNCATED SIMULATION

Synopsys, Inc., Mountain...

1. A computer-implemented method for design analysis comprising:
determining one or more of the patterns, from patterns used to test a semiconductor design, which cause a physical semiconductor
chip, based on the semiconductor design, to fail in operation;

identifying a subset of logic within the design where the fail occurred based on the one or more patterns which cause the
physical semiconductor chip to fail in operation;

generating a truncated rank-ordered list of nodes and logic based on the subset of logic, wherein the truncated rank-ordered
list includes a list of observe nodes and pass-through cells, where the list of pass-through cells includes state elements
which data passes through during application of the one or more patterns; and

performing good-machine simulation on the subset of logic using the one or more patterns and the truncated rank-ordered list.

US Pat. No. 9,684,743

ISOLATED DEBUGGING IN AN FPGA BASED EMULATION ENVIRONMENT

Synopsys, Inc., Mountain...

1. A non-transitory computer readable storage medium storing instructions, the instructions when executed by one or more processors
cause the one or more processors to:
receive, from an emulator, a plurality of interface signals, the emulator including a plurality of field-programmable gate
arrays (FPGAs), the plurality of interface signals generated by tracing interfaces from the plurality of FPGAs during a first
emulation of a design under test (DUT);

after the first emulation of the DUT, transmit to the emulator instructions to run a second emulation of at least a portion
of the DUT using a subset of FPGAs from the plurality of FPGAs and one or more interface signals from the plurality of interface
signals; and

receive from the emulator traced signals traced during the second emulation by running of the subset of FPGAs based on the
one or more interface signals from the plurality of interface signals.

US Pat. No. 9,684,755

ISOLATION OF IP UNITS DURING EMULATION OF A SYSTEM ON A CHIP

Synopsys, Inc., Mountain...

1. A non-transitory computer readable medium storing instructions for isolating emulated units, the instructions to configure
a host system to:
identify a first set of field programmable gate arrays (FPGAs) included in an emulator and selected to emulate a first unit
in a design under test (DUT);

identify a second set of FPGAs included in the emulator and selected to emulate a second unit in the DUT, the second set of
FPGAs different than the first set of FPGAs;

designate an FPGA included in the emulator for routing connections between units of the DUT, the designated FPGA not part
of the first and the second set of FPGAs; and

determine a route for a connection between the first unit and the second unit through the designated FPGA.

US Pat. No. 9,472,423

METHOD FOR SUPPRESSING LATTICE DEFECTS IN A SEMICONDUCTOR SUBSTRATE

SYNOPSYS, INC., Mountain...

1. During fabrication of a semiconductor device on a crystal substrate, the semiconductor device having source and drain regions,
with a channel between the source and drain regions and a gate conductor positioned above the channel, a method for suppressing
the formation of leakage-promoting defects in a crystal lattice due to dopant implantation in the lattice, comprising:
providing impurity atoms within the substrate, more deeply than the source and drain regions within the lattice, the impurity
atoms being selected to impose a compressive stress on the crystal lattice, at least some of the impurity atoms being directly
below at least part of the gate conductor;

implanting dopant atoms into the lattice; and
after implanting the dopant atoms into the lattice, annealing the lattice to thereby cause compressive stress exerted by the
impurity atoms on the lattice, including those of the impurity atoms directly below at least part of the gate conductor, to
emit interstitial defect atoms from a region containing the impurity atoms.

US Pat. No. 9,417,287

SCHEME FOR MASKING OUTPUT OF SCAN CHAINS IN TEST CIRCUIT

Synopsys, Inc., Mountain...

12. A test circuit in an integrated circuit comprising:
a plurality of scan chains, each scan chain configured to generate scan chain outputs representing test responses of a subset
of sub-circuits of the integrated circuit;

a compressor configured to compress the scan chain outputs of the plurality of scan chains; and
a fanout circuit between at least one of the plurality of the scan chains and the compressor, the fanout circuit configured
to set a fanout of the scan chain based on a fanout control signal, the fanout circuit configured to send a scan chain output
of the at least one scan chain to one input of the compressor for compression responsive to the fanout control signal indicating
configuring of the at least one scan chain as a single fanout, and send the scan chain output of the at least one scan chain
to three or more inputs of the compressor for compression responsive to the fanout control signal indicating configuring of
the scan chain as a multiple fanout.

US Pat. No. 9,287,253

METHOD AND APPARATUS FOR FLOATING OR APPLYING VOLTAGE TO A WELL OF AN INTEGRATED CIRCUIT

Synopsys, Inc., Mountain...

1. An integrated circuit, comprising:
a semiconductor substrate;
an n-well in the substrate having a range of n-well depths relative to a surface plane including a deepest n-well depth relative
to the surface plane;

a device in the n-well having at least one terminal with a range of n-well terminal depths relative to the surface plane including
a deepest n-well terminal depth relative to the surface plane shallower, relative to the surface plane, than the deepest n-well
depth relative to the surface plane;

a p-well in the substrate having a range of p-well depths relative to the surface plane including a deepest p-well depth relative
to the surface plane;

a device in the p-well having at least one terminal with a range of p-well terminal depths relative to the surface plane including
a deepest p-well terminal depth relative to the surface plane shallower, relative to the surface plane, than the deepest p-well
depth relative to the surface plane; and

biasing circuitry providing all bias voltages required by the device in the n-well and the device in the p-well for operation,
wherein during operation of the device in the n-well and the device in the p-well: (i) the biasing circuitry applies a bias
voltage arrangement to the device in the n-well and the device in the p-well, (ii) no well bias voltage is applied by the
biasing circuitry to the n-well, and (iii) no well bias voltage is applied by the biasing circuitry to the p-well,

wherein the n-well and the p-well are physically connected directly to each other along a range of shared well depths from
the surface plane to an intermediate plane in the substrate deeper than the surface plane.

US Pat. No. 9,257,429

N-CHANNEL AND P-CHANNEL END-TO-END FINFET CELL ARCHITECTURE WITH RELAXED GATE PITCH

Synopsys, Inc., Mountain...

1. An integrated circuit, comprising:
a substrate;
a first set of semiconductor fins aligned in a first direction on the substrate, one or more of the semiconductor fins in
the first set including at least one channel region and at least two source/drain regions of finFETs;

a second set of semiconductor fins aligned in the first direction on the substrate one or more of the semiconductor fins in
the second set including at least one channel region and at least two source/drain regions of finFETs;

a third set of semiconductor fins aligned in the first direction on the substrate, one or more of the semiconductor fins in
the third set including at least one channel region and at least two source/drain regions of finFETs;

a first power conductor over semiconductor fins in the first set and the third set between the first set and the third set;
a patterned gate conductor layer including a plurality of gate elements on corresponding fins in the first and second sets
of semiconductor fins, the gate elements being disposed over channel regions of the corresponding semiconductor fins;

at least one patterned conductor layer overlying the patterned gate conductor layer; and
a plurality of interlayer connectors, including interlayer connectors aligned over corresponding semiconductor fins in the
first and second sets and connected to the gate elements of particular finFETs on the corresponding fins.

US Pat. No. 9,183,329

DEBUGGING SIMULATION WITH PARTIAL DESIGN REPLAY

Synopsys, Inc., Mountain...

1. A method for simulating and re-simulating behavior of a circuit comprising at least one high-level circuit module and at
least one low-level circuit module, wherein each high-level circuit module is represented by a high-level design model and
each low-level circuit module is represented by a low-level design model, wherein the low-level circuit module has a plurality
of output driving port signals capable of outputting data from the low-level circuit module and a plurality of input receiving
port signals capable of inputting data to the low-level circuit module, the method comprising the steps of:
a. compiling each high-level design model into a corresponding high-level executable model for simulating behavior of the
at least one high-level circuit module and compiling each low-level design model into a corresponding low-level executable
model for simulating behavior of the at least one low-level circuit module;

b. generating a first replay engine for a first low-level circuit module of the at least one low-level circuit module according
to the output driving port signals of the first low-level circuit module, wherein the first replay engine for the first low-level
circuit module is generated without using any simulated data and without using any emulated data;

c. performing an initial simulation of circuit behavior, comprising executing the high-level executable models and the low-level
executable models and recording data representing behavior of the output driving port signals of the first low-level circuit
module in response to the input receiving port signals of the first low-level circuit module; and

d. performing a replay simulation of circuit behavior, comprising executing the high-level executable models, the first replay
engine to replace the low-level executable model corresponding to the first low-level circuit module, and the low-level executable
models which are not replaced, wherein the first replay engine simulates behavior of the output driving port signals of the
first low-level circuit module in response to the data recorded during the initial simulation that represents the behavior
of the output driving port signals of the first low-level circuit module.

US Pat. No. 9,507,896

QUASI-DYNAMIC SCHEDULING AND DYNAMIC SCHEDULING FOR EFFICIENT PARALLEL SIMULATION

Synopsys, Inc., Mountain...

1. A method for simulating a circuit design, the method comprising:
identifying a specified region of a circuit design for manufacturing, the circuit design comprising a set of logic elements
having common inputs corresponding to one or more inputs of the specified region of the circuit design;

identifying one or more inputs of the specified region of the circuit design having a state change;
selecting a subset of the identified one or more inputs of the specified region of the circuit design that have an input change;
for each input of the selected subset of the identified one or more inputs of the specified region of the circuit design:
computing a logic level depth associated with the input, the logic level depth corresponding to a number of logic elements
included in a signal path from an input of a first logic element included in the signal path to an input of a register included
in the signal path;

determining a maximum logic level depth of the one or more logic elements coupled to the selected subset of inputs of the
identified one or more inputs of the specified region of the circuit design from the computed logic level depths;

scheduling for simulation, by one or more processors, one or more logic elements coupled to the selected subset of the identified
one or more inputs of the specified region of the circuit design; and

simulating in parallel, in accordance with the scheduled simulation of the simulation range of logic levels, the one or more
logic elements coupled to the selected subset of the identified one or more inputs of the specified region of the circuit
design.

US Pat. No. 9,477,801

MULTI-THREADED TRACK ASSIGNMENT

SYNOPSYS, INC., Mountain...

1. A computer-implemented method for performing multi-threaded track assignment in a circuit design, the method comprising:
a global routing process in a computer system determining paths for a first set of wires and a second set of wires;
a first thread in the computer system assigning horizontal tracks in a first horizontal partition to the first set of wires
that passes through the first horizontal partition;

a second thread in the computer system assigning horizontal tracks in a second horizontal partition to a second set of wires
that passes through the second horizontal partition; and

wherein the first thread and the second thread execute in parallel in the computer system, wherein the first horizontal partition
and the second horizontal partition do not overlap with each other, wherein the first horizontal partition extends across
an entire length of the circuit design along a horizontal direction, wherein the second horizontal partition extends across
the entire length of the circuit design along the horizontal direction, and wherein the first thread and the second thread
obtain a lock for a net associated with a wire before assigning a track to the wire.

US Pat. No. 9,471,285

IDENTIFYING SOFTWARE COMPONENTS IN A SOFTWARE CODEBASE

SYNOPSYS, INC., Mountain...

1. A method for detecting third party software components in a source file, comprising:
receiving a source file containing source code at a server;
generating a code signature for the source file, the generating comprising:
determining a language of the source file;
identifying a list of language reserved keywords and key phrases associated with the programing language;
removing from the source file text that does not match a language reserved keyword or key phrase of the identified list;
removing from the source file language-specific control characters and control character sequences;
replacing each language reserved keyword and key phrase of the source file with a corresponding compact byte representation
to produce an encoded sequence; and

hashing the encoded sequence to produce the code signature;
comparing the generated code signature to signatures stored in a reference database to identify matching third Party software
files, the reference database storing a plurality of code signatures corresponding to the third party software files;

creating a list of the identified third party software files; and
presenting the list of identified third party to a user.

US Pat. No. 9,471,746

SUB-RESOLUTION ASSIST FEATURE IMPLEMENTATION WITH SHOT OPTIMIZATION

Synopsys, Inc., Mountain...

1. A computer-implemented method for shape analysis comprising:
determining a desired fabricated shape based on a semiconductor design layout corresponding to a physical chip, wherein the
desired fabricated shape corresponds to the semiconductor design layout;

evaluating the semiconductor design layout to determine mask shapes, wherein the mask shapes are determined comprising analyzing
the semiconductor design layout to evaluate desired fabricated shapes;

establishing a shot density for shots used to generate the mask shapes;
approximating, using one or more processors, the mask shapes using shots based on the shot density;
estimating a resulting fabricated semiconductor layout based on the shots;
modifying the shots used to generate the mask shapes to make the resulting fabricated semiconductor layout to be closer to
the desired fabricated shape; and

storing information on the shots onto computer storage media.

US Pat. No. 9,430,606

FAILURE ANALYSIS AND INLINE DEFECT CHARACTERIZATION

Synopsys, Inc., Mountain...

1. A computer implemented method for performing semiconductor failure analysis comprising:
having a set of rules wherein each rule of the set of rules describes a design rule check for a semiconductor layout;
selecting a rule from the set of rules to apply to the semiconductor layout wherein the rule describes a two-dimensional Boolean
operation on shapes where the rule further describes shapes of one or more layers and shapes of potential defects derived
from defect scanning tools or yield managements systems, wherein the Boolean operation on shapes further includes shapes of
electrical traces identified from electrical analysis of a netlist representing circuitry in the semiconductor layout;

identifying a portion of the semiconductor layout by searching through the semiconductor layout for a match to the rule which
was selected; and

displaying the portion of the semiconductor layout.

US Pat. No. 9,404,972

DIAGNOSIS AND DEBUG WITH TRUNCATED SIMULATION

Synopsys, Inc., Mountain...

1. A computer-implemented method for design analysis comprising:
determining one or more patterns, from patterns used to test a semiconductor design, which cause a physical semiconductor
chip, based on the semiconductor design, to fail in operation;

identifying a subset of logic within the design where the fail occurred based on the one or more patterns which cause the
physical semiconductor chip to fail in operation;

generating a truncated list of nodes and logic based on the subset of logic, wherein the truncated list includes a list of
observe nodes and a list of pass-through cells; and

performing simulation on the subset of logic using the one or more patterns and the truncated list.

US Pat. No. 9,390,208

FORMAL VERIFICATION OF TEMPORAL PROPERTIES EXPRESSED USING LOCAL VARIABLES

Synopsys, Inc., Mountain...

1. A method for verifying whether a hardware design satisfies a temporal property, the method comprising a processor executing
the steps of:
accessing a hardware description language (HDL) description of the hardware design;
accessing the temporal property, the temporal property expressed using a local variable;
creating a parse tree for the temporal property;
determining whether the temporal property is a member of a practical subset of temporal properties based on analyzing the
parse tree, wherein every member of the practical subset possesses an alternating automaton with no conflicts; and

(a) formally verifying whether the hardware design satisfies the temporal property for all such temporal properties that are
determined to be members of the practical subset; or (b) not formally verifying whether the hardware design satisfies the
temporal property for all such temporal properties that are determined not to be members of the practical subset.

US Pat. No. 9,069,920

AUTOMATED CIRCUIT DESIGN

Synopsys, Inc., Mountain...

1. A method implemented on a data processing system for circuit synthesis, the method comprising, upon receiving a circuit
design:
determining, using a processor, a net of the circuit design, the net including a first driver driving one or more control
loads via a first routing resource and one or more non-control loads via a second routing resource; and

purifying the net into a first net and a second net, the first net including the first driver driving the one or more control
loads via the first routing resource, the second net having a second driver driving the one or more non-control loads via
the second routing resource;

the first driver and the second driver having the same inputs;
wherein the first net and the first routing resource are optimized during a placement and routing phase for routing the control
loads;

wherein the first net and the second net, and the first driver and the second driver are used in the implementation of a resulting
circuit design in a vendor's technology/architecture dependent integrated circuit.

US Pat. No. 9,379,018

INCREASING ION/IOFF RATIO IN FINFETS AND NANO-WIRES

SYNOPSYS, INC., Mountain...

1. A method for fabricating an integrated circuit transistor structure comprising steps of:
providing an intermediate structure comprising:
a body of material, the body having an adjustment layer comprising adjustment volume material, and an upper layer of semiconductor
material, the upper layer overlying the adjustment layer,

a gate conductor outside the body, the gate conductor having portions facing the body on at least three sides of the body
and defining a channel volume of the body, the body having first and second longitudinally opposite end surfaces, the gate
conductor extending beyond the body in both longitudinal directions, and

a dielectric material between the gate conductor and the body;
forming first and second additional semiconductor material on respectively the first and second end surfaces of the body;
and

forming source and drain volumes longitudinally adjacent to respectively the first and second additional semiconductor material,
wherein the adjustment volume material has, at each longitudinal position, an electrical conductivity which differs from that
of the upper layer of semiconductor material at the same longitudinal position, at least while the transistor is in an off-state,

wherein the first additional material is less conductive than the source material, at least when the transistor is in the
off state,

and wherein the second additional material is less conductive than the drain material, at least when the transistor is in
the off state.

US Pat. No. 9,177,894

LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

SYNOPSYS, INC., Mountain...

5. A method for making an integrated circuit device, comprising:
providing a first semiconductor substrate having opposite topside and backside surfaces, the first semiconductor substrate
having a transistor therein;

forming a first conductor extending entirely through the first substrate, the first conductor being electrically connected
on a first end to a first point on the first substrate topside surface and on a second end to a second point on the first
substrate backside surface;

forming an additional TSV passing through the first substrate;
forming a plurality of RDL conductors on the backside of the first substrate;
electrically connecting the additional TSV to one of the RDL conductors; and
insulating the first conductor from all RDL conductors on the backside of the first substrate.

US Pat. No. 9,147,027

CHIP CROSS-SECTION IDENTIFICATION AND RENDERING DURING FAILURE ANALYSIS

Synopsys, Inc., Mountain...

1. A computer program product embodied in a non-transitory computer readable medium for circuit failure analysis comprising:
code for identifying a physical portion of a physical chip based on a semiconductor chip design corresponding to the physical
chip to be failure analyzed;

code for rendering a three-dimensional view of the physical portion that was identified, wherein the rendering includes generating
two or more cuts on planes that intersect a surface of the semiconductor chip and intersect two or more points within the
semiconductor chip where the two or more cuts form adjacent edges of the three-dimensional view; and

code for navigating to the physical portion of the physical chip.

US Pat. No. 9,098,665

PRIORITIZED SOFT CONSTRAINT SOLVING

Synopsys, Inc., Mountain...

5. A computer-implemented method for semiconductor design implementation comprising:
recognizing a plurality of soft constraints within a set of constraints, that define a semiconductor design problem wherein
solving the semiconductor design problem provides a specific chip operation, wherein the plurality of soft constraints provide
preferred but not absolute needs for a semiconductor chip;

prioritizing one or more of the plurality of soft constraints;
solving the semiconductor design problem;
determining a soft constraint which is not honored by the solving; and
debugging the soft constraint which is not honored.

US Pat. No. 9,064,808

INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE AND METHODS FOR MANUFACTURING THE SAME

Synopsys, Inc., Mountain...

1. A method for manufacturing a structure, the method comprising:
providing a first layer of crystalline phase material having crystallographic planes with differing epitaxial growth rates,
the first layer being oriented such that a first one of the crystallographic planes having the slowest of the epitaxial growth
rates extends vertically with respect to a top surface of the first layer of crystalline phase material;

forming a mask element overlying the first layer of crystalline phase material;
implanting ions into the first layer using the mask element as an implantation mask, thereby converting a region of the first
layer into an amorphous phase, the amorphous phase region having a first interface with crystalline phase material underlying
the mask element;

partially recrystallizing the amorphous phase region into the crystalline phase to form a recrystallized portion adjacent
the first interface and leave a remaining portion in the amorphous phase, the remaining portion having a second interface
with the recrystallized portion; and

selectively removing the remaining portion of the amorphous phase region to leave a first sidewall surface in the first layer
at a location defined by the second interface,

wherein the first sidewall extends parallel to the first one of the crystallographic planes having the slowest of the epitaxial
growth rates.

US Pat. No. 9,053,050

DETERMINING A DESIRABLE NUMBER OF SEGMENTS FOR A MULTI-SEGMENT SINGLE ERROR CORRECTING CODING SCHEME

Synopsys, Inc., Mountain...

1. A computer-implemented method for selecting a minimum number of segments for a multi-segment single error correcting (SEC)
coding scheme, the method comprising:
determining, based on memory scrambling information, a mapping between a logical structure for a representation of a memory
and a physical layout for the representation, the memory scrambling information including information specifying one or more
memory scrambling techniques implemented in the representation to store a data word;

determining a plurality of distances based on the determined mapping, wherein each distance is determined for a pair of storage
locations of the representation;

receiving a masked write segmentation requirement and a multi-bit upset size requirement;
selecting a segmentation value greater than or equal to the masked write segmentation requirement;
dividing one or more data words of the representation into a plurality of segments corresponding to the segmentation value;
determining a set of distances for pairs of bits of the one or more segments;
determining whether a shortest distance in the set of distances is greater than the multi-bit upset size; and
selecting the segmentation value for the representation with the one or more memory scrambling techniques implemented for
the data word to be greater than or equal to the masked write segmentation requirement based on determining that the shortest
distance is greater than the multi-bit upset size.

US Pat. No. 9,601,203

FLOATING GATE NON-VOLATILE MEMORY BIT CELL

Synopsys, Inc., Mountain...

1. A circuit comprising:
a first non-volatile memory cell comprising a first current-carrying terminal coupled to a first bitline;
a second non-volatile memory cell comprising a first current-carrying terminal coupled to a second bitline;
a first select transistor comprising a first current-carrying terminal coupled to a second current-carrying terminal of the
first non-volatile memory cell, and a gate terminal coupled to a select line; and

a second select transistor comprising a first current-carrying terminal coupled to a second current-carrying terminal of the
second non-volatile memory cell, and a gate terminal coupled to the select line.

US Pat. No. 9,519,740

DETERMINING OPTIMAL GATE SIZES BY USING A NUMERICAL SOLVER

SYNOPSYS, INC., Mountain...

1. A method for optimizing a circuit design, the method comprising:
optimizing, in a computer system, a portion of the circuit design that includes a driver gate that drives one or more inputs
of each gate in a set of gates, wherein said optimizing the portion of the circuit design comprises:

modeling a gate optimization problem for the portion of the circuit design based on circuit information that includes generic
logical effort values of each gate in the set of gates, an input capacitance value and a specific logical effort value of
the driver gate, and wire resistance and capacitance values of a net that electrically connects an output of the driver gate
with one or more inputs of each gate in the set of gates, wherein said modeling includes constructing a differentiable objective
function that minimizes a maximum delay from an input of the driver gate to an output of each gate in the set of gates;

executing a conjugate-gradient based numerical solver to solve the gate optimization problem;
incrementally computing a gradient of the differentiable objective function; and
providing the computed gradient to the conjugate-gradient based numerical solver.

US Pat. No. 9,484,186

MODELING AND CORRECTING SHORT-RANGE AND LONG-RANGE EFFECTS IN E-BEAM LITHOGRAPHY

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) software tool in a computer, a method for correcting a mask layout to compensate
for electron-beam (e-beam) proximity effects during e-beam lithography, the method comprising:
receiving a calibrated e-beam model which includes a long-range component which models long-range electron effects and a short-range
component which models short-range electron effects;

receiving a mask layout to be corrected, wherein the mask layout is generated based on a design intent;
the EDA software tool in the computer pre-computing a first resist intensity map based on the long-range component of the
calibrated e-beam model and the mask layout; and

the EDA software tool in the computer correcting a target pattern within the mask layout by, iteratively:
computing a second resist intensity map on the target pattern based on the short-range component of the calibrated e-beam
model and the target pattern;

obtaining a combined resist intensity map on the target pattern by combining the first resist intensity map and the second
resist intensity map; and

adjusting the target pattern based on the combined resist intensity map and the design intent.

US Pat. No. 9,430,601

METHOD AND APPARATUS FOR AUTOMATIC RELATIVE PLACEMENT GENERATION FOR CLOCK TREES

SYNOPSYS, INC., Mountain...

1. A system for circuit design, comprising:
an EDA system performing a transformation of a hardware description language circuit representation into a physical circuit
representation with a clock tree of clock network flip-flops,

wherein the EDA system complies with a plurality of sets of rules created at different times, and
wherein the EDA system adds clock network buffer circuitry, including an instance with the clock network flip-flops having
integrated clock gating,

wherein the system automatically creates the clock network flip-flops after coarse placement and before clock tree synthesis.

US Pat. No. 9,405,872

SYSTEM AND METHOD FOR REDUCING POWER OF A CIRCUIT USING CRITICAL SIGNAL ANALYSIS

Synopsys, Inc., Mountain...

1. A computerized method, implemented in a programmable system having at least a processing unit and a storage, for determination
of signals to be used for achieving power consumption reduction of an integrated circuit (IC), the method comprising:
receiving from storage by the programmable system a description of at least a portion of an IC, the received circuit description
comprising a plurality of circuit modules (CMs);

performing a power consumption simulation of the IC from the received description, by execution of instructions on a processing
unit of the programmable system, so as to generate a power consumption time series for each CM;

performing an analysis of the power consumption time series respective of each CM, by execution of instructions on the processing
unit, so as to identify existence of any one or more idle periods for each CM;

selecting, by execution of instructions on the processing unit, any CM having at least one idle period that is above a predetermined
threshold value; and

performing an analysis on all the input signals of each selected CM, by execution of instructions on the processing unit respective
of each selected CM, so as to determine at least one input signal of all selected CM's input signals that are correlated to
transitions of such selected CM between its idle and non-idle states.

US Pat. No. 9,317,399

POLICY EVALUATION BASED UPON DYNAMIC OBSERVATION, STATIC ANALYSIS AND CODE CHANGE HISTORY

Synopsys, Inc., Mountain...

1. A method to evaluate tests of computer program code comprising:
receiving, in a computer readable storage device, user input to designate a static analysis checker tool to use to identify
a code portion within the computer program code;

receiving, in the computer readable storage device, user input to designate a code range within the computer program code;
configuring a computer to perform one or more dynamic tests of computer program code;
capturing, in a computer readable storage device, test results that indicate portions of the computer program code that have
been tested using the one or more dynamic tests;

configuring a computer to produce, in a computer readable storage device, based at least in part upon the user input, a code
filter to indicate one or more respective portions of the computer program code to respectively either omit from or to include
in a determination of adequacy of the captured test results;

wherein producing the code filter includes configuring the computer to use the checker tool to produce, in the computer readable
storage device, a first filter element to indicate code from the computer program code that corresponds to the code portion
identified using the designated checker tool;

wherein producing the code filter includes configuring the computer to use a code modification history to produce, in the
computer readable storage device, a second filter element to indicate code from the computer program code that corresponds
to the designated code range; and

filtering the computer program code using the produced code filter to produce filtered computer program code; and
generating a test result indication by comparing the captured test results that indicate portions of the computer program
code that have been tested with the filtered computer program code to provide an indication of adequacy of the captured test
results coverage.

US Pat. No. 9,208,281

OPTIMIZING DESIGNS OF INTEGRATED CIRCUITS

Synopsys, Inc., Mountain...

1. A machine-implemented method for load based replication which comprises:
determining, by using a computer, as part of a process of designing a system for implementation into a target architecture,
a routing net from a first load to a driving component;

determining available places for a replicated version of the driving component utilizing information about available wiring
resources within the target architecture;

performing load-based replication in a second representation of the system, wherein the replicated version of the driving
component is created in the second representation of the system based on the routing net and the available places;

creating connections, in the second representation of the system, between the replicated version of the driving component
and the first load; and determining whether a second load in the same routing net from the driving component and in the same
area as the first load is to be connected to the replicated version of the driving component, wherein one or more of the first
load and the second load are critical loads.

US Pat. No. 9,183,333

GENERALIZED MOMENT BASED APPROACH FOR VARIATION AWARE TIMING ANALYSIS

Synopsys, Inc., Mountain...

1. A method of performing statistical timing analysis on a circuit design upon receipt of a signal path in the circuit design,
the method comprising:
by using a computing device, receiving the signal path that traverses a plurality of gates;
for each of the plurality of gates, receiving a gate statistical distribution that represents delay variation at the gate
using a number of statistical moments that comprises a standard deviation and at least one moment that has a higher order
than the standard deviation;

computing statistical moments for a signal path distribution representing delay on the signal path by applying one or more
operations to the gate statistical distributions based on a configuration of the plurality of gates; and

converting statistical moments of the signal path distribution to timing moments;
converting the timing moments to timing parameters by extracting a set of poles and residues from the timing moments;
reconstructing a resulting distribution function based on the computed poles and residues; and
using the reconstructed resulting distribution function in timing analysis for the circuit design.

US Pat. No. 9,151,783

GROUND OFFSET MONITOR AND COMPENSATOR

SYNOPSYS, INC., Mountain...

1. A circuit, comprising:
a first node whose voltage is equal to a first voltage value that is used as a reference voltage in the circuit;
a second node to receive a voltage signal from a remote circuit, wherein a relationship exists between the voltage signal
and a second voltage value that is used as a corresponding reference voltage in the remote circuit;

circuitry to determine the second voltage value from the voltage signal based on the relationship;
circuitry to output an offset value based on a difference between the first voltage value and the second voltage value; and
circuitry to provide the offset value to a receiver, wherein the receiver uses the offset value to adjust a threshold voltage
of a data slicer that is used to interpret information encoded in the voltage signal.

US Pat. No. 9,147,030

MULTIPLE-INSTANTIATED-MODULE (MIM) AWARE PIN ASSIGNMENT

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for performing multiple-instantiated-module (MIM) aware pin assignment,
wherein an MIM is a module that is instantiated at multiple locations in a circuit design, the method comprising:
the EDA tool routing, by using one or more processors, a net of an MIM instance selected from a set of MIM instances in the
circuit design, wherein said routing tries to optimize a cost function that includes a set of cost terms, wherein each MIM
instance in the set of MIM instances corresponds to a cost term in the set of cost terms, and wherein each cost term includes
at least one of: a bounding box cost component, a congestion cost component, a routing blockage cost component, or a pin blockage
cost component; and

the EDA tool placing pins in each MIM instance in the set of MIM instances based on the net that was routed for the selected
MIM instance.

US Pat. No. 9,076,673

FINFET CELL ARCHITECTURE WITH POWER TRACES

SYNOPSYS, INC., Mountain...

1. An integrated circuit, comprising:
a substrate;
a first set of semiconductor fins in a first region of the substrate, including outer fins on opposing outside edges of the
first set;

a first isolation feature parallel to the first set of semiconductor fins;
a second isolation feature located in the first region between the outer fins of the first set of semiconductor fins;
a patterned gate conductor layer including a plurality of first region gate traces overlying the first set, the plurality
of first gate traces including;

a first gate trace extending from a position proximate a first outer fin of the first set and terminating at a position proximate
the second isolation feature; and

a second gate trace extending from a position proximate the first outer fin to a position proximate a second outer fin, opposite
the first outer fin.

US Pat. No. 9,857,409

NEGATIVE BIAS THERMAL INSTABILITY STRESS TESTING OF TRANSISTORS

Synopsys, Inc., Mountain...

1. A circuit comprising:
a transistor for testing, the transistor having a gate-to source voltage Vgs and a drain-to-source voltage Vds;
a sensor circuit connected to the drain of the transistor;
a complementary control circuitry attached to the transistor and the sensor circuit such that the sensor circuit is powered
off during a stress test of the transistor, and the drain-to-source voltage of the transistor for testing is zero during the
stress test, and the sensor circuit is powered through the transistor during an evaluation of the stress test, the complementary
control circuit comprising a pair of transistors coupled to the sensor circuit in parallel, a first transistor to set a voltage
across the sensor circuit to zero during the stress test, and a second transistor to provide ground during the stress test
evaluation.

US Pat. No. 9,652,889

IMAGE PROCESSING METHOD

SYNOPSYS, INC., Mountain...

1. A computer-implemented method of generating a representation of a virtual three-dimensional object in a computer having
a processor and a memory device in order to improve conformance of a slave boundary representation to a master boundary representation,
the method comprising:
obtaining into the memory device the master boundary representation of the virtual three-dimensional object;
sampling by the processor a bounding volume containing the master boundary representation to generate a digitized three-dimensional
representation of the object in the memory device;

generating by the processor the slave boundary representation from the digitized three-dimensional representation of the object,
the slave boundary representation being in the memory device; and

modifying by the processor the slave boundary representation with reference to the master boundary representation, wherein
modifying the slave boundary representation comprises:

comparing the slave boundary representation with the master boundary representation to identify a displaced portion on the
slave boundary representation having a displacement relative to a corresponding portion of the master boundary representation;
and

mapping the displaced portion of the slave boundary representation to a modified position to reduce the displacement relative
to the corresponding portion of the master boundary representation.

US Pat. No. 9,508,868

ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR

Synopsys, Inc., Mountain...

1. A paired non-volatile memory bitcell comprising:
a first active region in a substrate, the first active region comprising a first and second source and a first and second
drain;

a second active region separated from the first active region by a nonconductive region, the second active region comprising
one plate of each of a first and second capacitor;

a third active region separated from the first and second active regions by a second nonconductive region, the third active
region comprising one plate of each of a first and second band to band tunneling (BTBT) capacitor;

a first floating gate located above the second active region and forming another plate of the first capacitor, above the third
active region forming another plate of the first BTBT capacitor, and above the first active region between the first source
and the first drain; and

a second floating gate located above the second active region and forming another plate of the second capacitor, above the
third active region forming another plate of the second BTBT capacitor, and above the first active region between the second
source and the second drain;

wherein the first and second sources of the first active region each comprise at least one of a source-drain extension implant
and a lightly doped drain (LDD) implant, and wherein the first and second sources each comprise a halo implant and the first
and second drains do not comprise a halo implant.

US Pat. No. 9,465,663

ALLOCATING RESOURCES IN A COMPUTE FARM TO INCREASE RESOURCE UTILIZATION BY USING A PRIORITY-BASED ALLOCATION LAYER TO ALLOCATE JOB SLOTS TO PROJECTS

SYNOPSYS, INC., Mountain...

1. A method for allocating resources in a compute farm, wherein the compute farm's resources are represented using a set of
job slots, and wherein the set of job slots are managed by a queuing system, the method comprising:
a priority-based allocation (PBA) layer receiving information about a first job that is pending in the queuing system, wherein
the information indicates that the first job is associated with a first project, and wherein the PBA layer is separate from
the queuing system;

in response to the PBA layer determining that the number of job slots in the compute farm that are allocated to jobs associated
with the first project is less than the number of job slots allocated to the first project, and that no free job slots are
available for executing the first job,

the PBA layer identifying a low-priority job slot that is currently executing a second job associated with a second project,
wherein the number of job slots in the compute farm that are executing jobs associated with the second project is greater
than the number of job slots allocated to the second project,

the PBA layer providing a scheduling instruction to the queuing system via an interface of the queuing system, wherein the
scheduling instruction instructs the queuing system to schedule the first job in the low-priority job slot, and

the PBA layer providing a de-allocation instruction to the queuing system via the interface of the queuing system, wherein
the de-allocation instruction instructs the queuing system to de-allocate the executing second job.

US Pat. No. 9,460,258

SHAPING INTEGRATED WITH POWER NETWORK SYNTHESIS (PNS) FOR POWER GRID (PG) ALIGNMENT

SYNOPSYS, INC., Mountain...

1. A method for performing shaping on a circuit design, the method comprising:
receiving a set of power grid (PG) strategies that specifies a structure of a PG that is to be used in the circuit design;
creating a set of placement constraints based on the set of PG strategies, wherein the set of placement constraints comprises
a placement constraint that requires a physical partition to be aligned with the structure of the PG, and wherein at least
one PG wire passes through the physical partition;

performing, by computer, shaping on the circuit design using the set of placement constraints; and
after performing said shaping on the circuit design, creating the PG in the circuit design based on the set of PG strategies,
wherein said creating the PG in the circuit design comprises pushing the at least one PG wire into the physical partition.

US Pat. No. 9,454,149

EXTRACTING ATTRIBUTE FAIL RATES FROM CONVOLUTED SYSTEMS

Synopsys, Inc., Mountain...

1. A method of extracting attribute fail rates for manufactured devices comprising:
testing manufactured devices having a set of attributes to provide a set of test results stored in memory;
generating a yield model of the manufactured devices based on the set of test results and parsed by the set of attributes;
and
performing, by a processor, a statistical analysis of the generated yield model to extract fail rates of the selected subset
of attributes.

US Pat. No. 9,442,886

SCHEDULING IN A MULTICORE ARCHITECTURE

Synopsys, Inc., Mountain...

1. A method of scheduling executable transactions in a multicore processor comprising a plurality of processor elements, wherein
at least one processor element comprises reconfigurable logic, the method comprising:
providing a first configuration queue of executable transactions allocated for execution by a first configuration of the reconfigurable
logic and a second configuration queue of executable transactions allocated for execution by a second configuration of the
reconfigurable logic;

providing a multilevel scheduler comprising a plurality of executable transaction schedulers each configured to determine
a most eligible executable transaction for execution from a plurality of candidate executable transactions, each candidate
executable transaction associated with the first configuration of the reconfigurable logic or the second configuration of
the reconfigurable logic, the multilevel scheduler configured to:

output a determined most eligible executable transaction to the first configuration queue in response to the determined most
eligible executable transaction being associated with the first configuration of the reconfigurable logic; and

output the determined most eligible executable transaction to the second configuration queue in response to the determined
most eligible executable transaction being associated with the second configuration of the reconfigurable logic; and

when the reconfigurable logic is configured in the first configuration:
outputting executable transactions from the first configuration queue to the reconfiguration logic; and
reconfiguring the reconfigurable logic to the second configuration when a pre-determined threshold is reached.

US Pat. No. 9,424,951

DYNAMIC STATIC RANDOM ACCESS MEMORY (SRAM) ARRAY CHARACTERIZATION USING AN ISOLATED BIT-LINE

Synopsys, Inc., Mountain...

1. A circuit comprising: a static random access memory (SRAM) array including a bit-line;
a current mirror to create a mirrored isolated bit-line (MIBL) current, based on a bit-line read current in an active bit-cell
of the SRAM array, the active bit-cell of the SRAM array having a read path; and

a sensor circuit including an output, the output of the sensor circuit characterizing the SRAM array when powered by the MIBL,
wherein the sensor circuit is not inline with the read path;

wherein the sensor circuit is a ring oscillator.

US Pat. No. 9,246,826

INTEGRATED CIRCUIT ARRANGEMENT FOR BUFFERING SERVICE REQUESTS

Synopsys, Inc., Mountain...

1. An integrated circuit comprising:
a data communication network comprising a plurality of connections;
a plurality of modules coupled to the data communication network via at least one network interface; and
at least one remote service module being coupled to the data communication network via a further network interface, the further
network interface comprising:

terminal connection buffers marking the terminals of the plurality of connections, wherein the terminal connection buffers
in the further network interface being identified by a first identifier, wherein each of said plurality of modules is arranged
to provide its network interface with a service request for the remote service module, said network interface being arranged
to extend said service request with the first identifier for establishing a network connection with a remote service module,
and

a circuit portion comprising a plurality of buffers between the at least one network interface and the remote service module
for storing service requests from the plurality of modules, said circuit portion comprising decoding logic for selecting one
of said buffers by decoding a further identifier embedded in the service request.

US Pat. No. 9,245,075

CONCURRENT OPTIMIZATION OF TIMING, AREA, AND LEAKAGE POWER

SYNOPSYS, INC., Mountain...

1. In a circuit synthesis system comprising an electronic design automation (EDA) tool in a computer, a method for concurrently
optimizing timing, area, and power leakage in a circuit design, the method comprising:
in response to determining that a cell is not timing critical, but a driver cell that drives an input of the cell is timing
critical, the EDA software tool in the computer optimizing the cell based on a first cost metric that combines a first timing
metric and a first area metric;

in response to determining that both the cell and the driver cell are not timing critical, the EDA software tool in the computer
optimizing the cell based on a second cost metric that combines a second area metric and a power leakage metric; and

in response to determining that the cell is timing critical, the EDA software tool in the computer optimizing the cell based
on a second timing metric.

US Pat. No. 9,230,674

NON-VOLATILE MEMORY WITH NEGATIVE BIAS

Synopsys, Inc., Mountain...

1. A non-volatile memory system, comprising:
a plurality of bit cells structured in a row with a control line, a word line, and a plurality of bit lines, each bit line
associated with a corresponding bit cell from the plurality of bit cells, the control line configured to:

couple the word line and a selected bit line from the plurality of bit lines to read a content in a bit cell associated with
the selected bit line responsive to the control line supplied with a first voltage, and

decouple the word line and the plurality of bit lines to not read contents in the plurality of bit cells responsive to the
control line supplied with a second voltage; and

a bit line controller coupled to the plurality of bit lines and to bias the selected bit line from the plurality of bit lines
at a third voltage that is lower than the second voltage to read the content in the bit cell associated with the selected
bit line in a first mode.

US Pat. No. 9,208,272

APPARATUS AND METHOD THEREOF FOR HYBRID TIMING EXCEPTION VERIFICATION OF AN INTEGRATED CIRCUIT DESIGN

Synopsys, Inc., Mountain...

1. A computerized method for verification of timing exceptions of an integrated circuit (IC) design, the method comprising:
performing by a computing device at least a dynamic verification using a test-bench of the IC design to verify correctness
of at least a dynamic timing exception, filtered out from a static verification of at least a static timing exception of the
IC design, that is contained in at least a constraints file of the IC design to identify any dynamic timing exception failures;
and

correcting any timing exception or design bug respective of an identified dynamic timing exception failure caused by simulation
of an assertion for at least one timing exception and updating the IC design and the respective design constraint files respective
of the correction.

US Pat. No. 9,171,122

EFFICIENT TIMING CALCULATIONS IN NUMERICAL SEQUENTIAL CELL SIZING AND INCREMENTAL SLACK MARGIN PROPAGATION

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for optimizing a circuit design, the method comprising:
optimizing, by the EDA tool in a computer, a first sequential cell, wherein said optimizing involves:
computing first timing-related information associated with a source driver, wherein an output of the source driver drives
a data input of the first sequential cell and a data input of a second sequential cell, wherein the first sequential cell
and the second sequential cell each have at least one clock input and at least one data input;

storing the first timing-related information;
evaluating alternative library cells as replacements for the first sequential cell by reusing the first timing-related information;
and

optimizing, by the EDA tool in the computer, the second sequential cell by reusing the first timing-related information;
wherein a representation of the circuit design is subsequently provided to a semiconductor fabrication facility for fabrication.

US Pat. No. 9,171,126

RANGE PATTERN MATCHING IN MASK DATA

Synopsys, Inc., Mountain...

1. An apparatus, comprising:
memory; and
a processor configured to execute instructions stored in the memory to:
search mask data, wherein the mask data describes figures corresponding to features of an optical mask to be generated based
on the mask data, and wherein the mask data is searched for a set of one or more figures corresponding with an electronic
pattern definition, the pattern definition describing at least one geometric figure and having a pattern ID;

identify a match in the mask data, wherein the match comprises a set of one or more figures corresponding with the pattern
definition;

identify a match location in the mask data, the mask location corresponding to a location of the match in the mask data;
identify a match orientation, the match orientation describing an orientation of the match; and
generate a set of coordinates for the match location based on the pattern ID and the match orientation, the set of coordinates
indicating a position in the mask data for further processing.

US Pat. No. 9,058,451

AUTOMATIC SYNTHESIS OF COMPLEX CLOCK SYSTEMS

Synopsys, Inc., Mountain...

1. A method of performing clock network synthesis upon receipt of a non-transitory computer readable circuit design, the method
comprising:
by using a computing device, building a graph representation for a clock network;
determining an optimal clock network balancing solution for the clock network by applying linear programming to the graph,
the applying linear programming comprising generating a set of constraints for the graph and determining a proper insertion
delay for each edge of the graph by solving for a minimal skew based on the set of constraints, the set of constraints comprising
a plurality of Edge Relation, Endpoint Constraint, Skew Limit, Maximum Latency Constraint and Maximum Skew Constraint; and

implementing the optimal clock network balancing solution, wherein the implemented optimal clock network balancing solution
is used to create an integrated circuit.

US Pat. No. 9,459,679

POWER MANAGER AND METHOD FOR MANAGING POWER

Synopsys, Inc., Mountain...

1. An electronic system comprising:
a hardware monitor coupled to an electronic device and configured to monitor a workload of the electronic device and to generate
a signal indicative of the workload of the electronic device during a monitoring time period between a first time and a second
time; and

a power manager coupled to the hardware monitor and configured to:
determine a frequency of a periodicity of the workload based on the signal,
detect a first event in the workload at the first time, the first event represented by at least a first predetermined amount
of change in the signal from a first level in a first predetermined length of time,

detect a second event in the workload at the second time after the first time, the second event represented by at least another
first predetermined amount of change in the signal from the first level in the first predetermined length of time,

predict a third time at which a future event in the workload is expected to occur based on a difference between the first
time and the second time,

predict a fourth time after the third time, the fourth time corresponding to a predicated time when another future event in
the workload is expected to occur based on the difference between the first time and the second time,

select a subsequent monitoring time period between the third time at which the predicted future event is expected to occur
and the fourth time at which said another predicted further event is expected to occur, the difference between the first time
and the second time different from another difference between the third time and the fourth time, and

control an amount of power supplied to the electronic device based on the frequency of the periodicity of the workload,
wherein the hardware monitor is further configured to monitor the workload of the electronic device during the subsequent
monitoring time period.

US Pat. No. 9,430,608

FIXING OF SEMICONDUCTOR HOLD TIME

Synopsys, Inc., Mountain...

1. A computer-implemented method for design analysis and modification comprising:
estimating hold-time requirements for a semiconductor design based on ideal clocks;
allocating, using one or more processors, placement regions for the design wherein the placement regions are to be used during
hold-time fixing, wherein the allocating of placement regions to be used during hold-time fixing allows for access to pins
on blocks within the design;

wiring track routes for the design wherein the wiring of track routes for hold-time critical nets is performed later than
wiring of nets without hold-time violations; and

modifying the design by performing hold-time fixing on the design.

US Pat. No. 9,406,812

ASYMMETRIC DENSE FLOATING GATE NONVOLATILE MEMORY WITH DECOUPLED CAPACITOR

Synopsys, Inc., Mountain...

1. A non-volatile memory bitcell comprising:
a source and a drain formed in an active region and separated by a channel region in the active region;
a gate stack comprising:
a gate formed on an oxide over the channel region;
at least one sidewall spacer formed around the gate; and
a charge trapping layer formed on an opposite side of the sidewall spacer from the gate, at least a portion of the charge
trapping layer acting as a floating gate of the bitcell;

an electrically insulating layer covering the floating gate portion of the charge trapping layer; and
a contact physically contacting the electrically insulating layer above the floating gate portion of the charge trapping layer,
wherein the contact does not make direct electrical contact to either the gate or the active region.

US Pat. No. 9,384,313

SYSTEMS AND METHODS FOR INCREASING DEBUGGING VISIBILITY OF PROTOTYPING SYSTEMS

Synopsys, Inc., Mountain...

1. A method to debug a RTL design in an FPGA-based emulation or co-emulation system, the method comprising the steps of:
a. instrumenting the RTL design by inserting at least one dummy module for correlating a set of signals of the RTL design
to corresponding gate-level signals;

b. synthesizing the instrumented RTL design to generate a gate-level net-list targeting for the emulation or co-emulation
system;

c. fitting the gate-level net-list into the FPGA devices in the emulation or co-emulation system and generating location information
of instances of the gate-level net-list in the FPGA devices; and

d. extracting values of gate-level signals corresponding to the set of signals of the RTL design in an emulation or co-emulation
run according to the location information of the instances that output the gate-level signals in the emulation or co-emulation
system.

US Pat. No. 9,354,511

INTEGRATED MASK-AWARE LITHOGRAPHY MODELING TO SUPPORT OFF-AXIS ILLUMINATION AND MULTI-TONE MASKS

Synopsys, Inc., Mountain...

1. A method of performing optical lithography simulation implemented in a computer upon receipt of a multi-tone mask having
a plurality of mask tones, the method comprising:
generating, using a computing device, a function with polarization having a portion representing a tone mask matrix and a
portion representing a characteristic transmission (CT) function matrix based on the multi-tone mask, wherein the CT function
matrix is a function of light source point information and not a function of mask geometry information; and

generating one or more convolution kernel for the multi-tone mask from the CT function for use in a Hopkins' form for calculating
light intensity for the optical lithography simulation.

US Pat. No. 9,329,235

LOCALIZING FAULT FLOP IN CIRCUIT BY USING MODIFIED TEST PATTERN

Synopsys, Inc., Mountain...

1. A method for localizing at least one scan flop associated with a fault, the method comprising:
generating a first test pattern comprising first scan-in data and first control data, the first control data of the first
test pattern at least identifying a first sequence of compressor outputs used to generate a first fault data, the first sequence
of compressor outputs identifying a sequential combination of outputs of a test circuit for generating the first fault data;

receiving first fault data, the received first fault data generated by applying the first scan-in data to scan flops in the
test circuit of an integrated circuit based at least on the first control data and compressing an output of the test circuit
using the first sequence of compressor outputs;

responsive to determining that the first fault data indicates presence of a fault in the integrated circuit, generating a
second test pattern comprising second scan-in data and second control data, the second control data of the second test pattern
at least identifying a second sequence of compressor outputs used to generate a second fault data, the second sequence of
compressor outputs different than the first sequence of compressor outputs;

receiving second fault data, the received second fault data generated by applying the second scan-in data to the scan flops
in the test circuit based at least on the second control data and compressing the output of the test circuit using the second
sequence of compressor outputs; and

identifying at least one scan flop associated with the fault by identifying at least one scan flop common to first scan flops
and second scan flops, an incorrect output of the first scan flops resulting in the first fault data, and an incorrect output
of the second scan flops resulting in the second fault data.

US Pat. No. 9,190,346

LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

SYNOPSYS, INC., Mountain...

1. A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause a computer
system to perform a method for developing a three-dimensional integrated circuit, the method comprising:
writing to a non-transitory computer-readable storage medium one or more layout files for a plurality of integrated circuit
chips stacked vertically in a fixed structure, the plurality of integrated circuit chips including a first chip having opposite
topside and backside surfaces, the layout files defining mask elements for a transistor in the first chip; and

wherein the layout files further define mask elements for a first conductor extending entirely through the first chip, the
first conductor being electrically connected on a first end to a first point on the first chip topside surface and on a second
end to a second point on the first chip backside surface,

the layout files being provided for fabrication of the plurality of integrated circuit chips.

US Pat. No. 9,183,335

DYNAMIC POWER DRIVEN CLOCK TREE SYNTHESIS (CTS)

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) software tool, method for clock tree synthesis, the method comprising:
the EDA software tool in a computer selecting one or more cells from a cell library based at least on power ratios of cells
in the cell library, wherein a power ratio of a cell is equal to an expected amount of dynamic power consumption of a clock
tree when the clock tree drives a unit capacitive load, and wherein the clock tree is built using the cell; and

the EDA software tool in the computer constructing a clock tree based on the one or more cells.

US Pat. No. 9,112,511

LOW VOLTAGE LEVEL SHIFTER FOR LOW POWER APPLICATIONS

Synopsys, Inc., Mountain...

1. A non-transitory computer readable medium storing a digital representation of level shifter circuit, the level shifter
circuit comprising:
an input stage configured to receive an input signal from an input terminal changing in a first voltage range, and comprising:
a first transistor having a gate receiving the input signal, the first transistor turned on responsive to the input signal
being active and turned off responsive to the input signal being inactive, and

a second transistor having a gate receiving an inverse of the input signal, the second transistor turned on responsive to
the input signal being inactive and turned off responsive to the input signal being active;

an intermediate stage coupled to the input stage and configured to regulate a voltage of an intermediate signal generated
in response to operation of the input stage, the intermediate stage comprising:

a third transistor having a gate receiving a reference voltage and a source coupled to a drain of the first transistor,
a fourth transistor having a gate receiving the reference voltage and a source coupled to a drain of the second transistor,
a fifth transistor coupled to the third transistor,
a first voltage divider configured to bias the fifth transistor by dividing a voltage between a drain of the fifth transistor
and a source of the fifth transistor, an output of the first voltage divider coupled to a gate of the fifth transistor,

an sixth transistor coupled to the forth transistor, and
a second voltage divider configured to bias the sixth transistor by dividing a voltage between a drain of the sixth transistor
and a source of the sixth transistor, an output of the second voltage divider coupled to a gate of the sixth transistor,

wherein a threshold voltage of the fifth transistor and the sixth transistor is larger than first voltage range; and
an output stage coupled to the intermediate stage, the output stage configured to generate an output signal changing at a
second voltage range higher than the first voltage range based on the intermediate signal.

US Pat. No. 9,053,281

DUAL-STRUCTURE CLOCK TREE SYNTHESIS (CTS)

SYNOPSYS, INC., Mountain...

1. A computer-implemented method for clock tree synthesis in an electronic design automation (EDA) tool, the computer-implemented
method comprising:
upon receiving a circuit design in which clock tree synthesis is to be performed, constructing, by using a processor, a set
of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree, wherein
each upper-level clock tree is optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew,
and wherein optimizing each upper-level clock tree includes optimizing at least one of: a topology of said each upper-level
clock tree, buffers in said each upper-level clock tree, routing of said each upper-level clock tree, and a wire width used
in said each upper-level clock tree; and

for each leaf of each upper-level clock tree, constructing a lower-level clock tree, wherein the lower-level clock tree distributes
a clock signal from said each leaf of said each upper-level clock tree to a set of clock sinks, wherein the lower-level clock
tree is optimized to reduce latency, power consumption, and/or area, and wherein optimizing the lower-level clock tree includes
optimizing at least one of: a topology of the lower-level clock tree, buffers in the lower-level clock tree, routing of the
lower-level clock tree, and a wire width used in the lower-level clock tree.

US Pat. No. 10,073,933

AUTOMATIC GENERATION OF PROPERTIES TO ASSIST HARDWARE EMULATION

Synopsys, Inc., Mountain...

1. A system for assisting in generation of a hardware emulation test suite for verifying a design under test by a hardware emulator, the system comprising:a properties database that stores properties automatically detected from previously executed verifications of prior designs of electronic circuitries, the properties declaring conditions in the prior designs; and
an emulation property generator system coupled to the properties database, wherein the emulation property generator system:
accesses the design under test; and
selects from the properties database a set of properties for incorporation into the hardware emulation test suite, the set selected based on a relation of the design under test to the prior designs and also selected based on whether properties are synthesizable for the hardware emulator.

US Pat. No. 10,032,859

METHODS FOR MANUFACTURING INTEGRATED CIRCUIT DEVICES HAVING FEATURES WITH REDUCED EDGE CURVATURE

Synopsys, Inc., Mountain...

1. A method for manufacturing a structure, the method comprising:forming a mask element using nanoimprint lithography, the mask element overlying a layer of crystalline phase material, the mask element having a first sidewall surface;
etching the layer using the mask element as an etch mask, thereby forming a second sidewall surface in the layer at a location defined by the first sidewall surface; and
processing the etched layer to straighten the second sidewall surface.

US Pat. No. 9,691,764

FINFET CELL ARCHITECTURE WITH POWER TRACES

SYNOPSYS, INC., Mountain...

1. An integrated circuit, comprising:
a substrate;
a first set of semiconductor fins in a first region of the substrate;
a plurality of gate traces overlying the first set;
a patterned conductor layer overlying the first set, including;
a first patterned conductor over the first set and connected to source/drain regions of two or more fins in the first set,
and

a second patterned conductor over the first set and connected to source/drain regions of one or more fins in the first set,
wherein the first patterned conductor is connected to more source/drain regions of fins in the first set than the second patterned
conductor.

US Pat. No. 9,583,208

SENSING SCHEME FOR HIGH SPEED MEMORY CIRCUITS WITH SINGLE ENDED SENSING

Synopsys, Inc., Mountain...

11. A circuit, comprising:
a plurality of bit cells connected to a word line, each bit cell configured to store one of a first bit value or a second
bit value, the plurality of bit cells comprising a bit cell coupled to a bitline;

a pre-charger transistor coupled to the bitline, the pre-charger transistor configured to inject charge into the bitline;
and

a level detector receiving an input from the bitline, the level detector configured to output a first voltage level indicating
that the bit value stored in the bit cell is the first bit value, responsive to a voltage level of the bitline staying below
a first threshold voltage level during the injection of the charge into the bitline and output a second voltage level indicating
that the bit value stored in the bit cell is the second bit value, responsive to the voltage level of the bitline exceeding
a second threshold voltage level higher than the first threshold voltage level during the injection of the charge into the
bitline, the level detector comprising:

a first inverter coupled to the bitline, the first inverter receiving the voltage level of the bitline;
a diode coupled to the output of the first inverter, the diode configured to conduct responsive to the voltage level of the
bitline exceeding the second threshold voltage level during the injection of the charge into the bitline;

a first node connected to a first supply voltage via the diode responsive to the diode conducting; and
a positive feedback circuit receiving input from the first node, the positive feedback circuit outputting the first voltage
level responsive to the first node connecting to the first supply voltage via the diode.

US Pat. No. 9,418,189

SRAM LAYOUTS

Synopsys, Inc., Mountain...

1. An article of manufacture, comprising a computer readable storage medium, having stored thereon in a non-transitory manner
a computer readable definition of shapes for a lithographic mask set for defining features to be formed on an integrated circuit
using the mask set, wherein the features define a static random access memory comprising an array of memory cells, each particular
one of the cells comprising:
first and second pass-gate transistors each connected in the cell to perform a pass gate function;
first and second P-channel pull-up transistors each connected in the cell to perform a pull-up function; and
first and second N-channel pull-down transistors, each connected in the cell to perform a pull-down function, each of the
transistors having a respective gate electrode and respective first and second current path terminal,

wherein the gate electrode of a particular one of the transistors of a first one of the functions does not share a layout
track with the gate electrodes of any of the transistors of either of the other two functions.

US Pat. No. 9,390,211

CIRCUIT PLACEMENT BASED ON FUZZY CLUSTERING

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for placing a circuit design, the method comprising:
receiving a netlist for the circuit design, wherein the netlist describes interconnections between a plurality of cells;
representing the netlist as a graph;
performing, using one or more processors, fuzzy clustering on the graph to obtain a set of clusters and a set of probability
values, wherein each probability value corresponds to a probability of a given cell belonging to a given cluster;

partitioning the netlist based on the set of clusters and the set of probability values to obtain a partitioned netlist;
placing the partitioned netlist to obtain a placed circuit design, wherein cells of each partition are placed in a layout
bin corresponding to the partition; and

optimizing the placed circuit design, wherein said optimizing reassigns at least one cell to a different layout bin based
on the set of probability values.

US Pat. No. 9,378,000

DETERMINATION OF UNREACHABLE ELEMENTS IN A DESIGN

SYNOPSYS, INC., Mountain...

1. A computer-implemented method of optimizing a circuit design described by a program code written in hardware description
language (HDL), the method comprising:
receiving a description of the program code;
determining one or more impossible values for a variable in the program code based on a plurality of potential values of the
variable;

propagating the one or more impossible values of the variable to other variables that are dependent on the variable in the
program code;

identifying, using a computing device, a set of unreachable targets in the program code based on the one or more impossible
values for the variable, the propagating, and the description of the program code;

removing objects associated with the set of unreachable targets.

US Pat. No. 9,256,706

KNOWLEDGE-BASED ANALOG LAYOUT GENERATOR

Synopsys Taiwan Co., Ltd....

1. A computer-implemented method for generating a layout of a design, the method comprising:
invoking the computer to receive a schematic representation of the design, the schematic representation comprising a plurality
of devices and associated terminals coupled to one another by a plurality of nets;

generating a connection graph associated with the schematic representation of the design via the computer, said generating
the connection graph comprising:

calculating interconnection codes between pairs of devices;
converting the devices and nets connecting the terminals to respective nodes and edges; and
associating the interconnection codes to the edges of the connection graph;
comparing the connection graph to a plurality of connection graphs stored in a database to identify a match via the computer;
and

selecting a layout associated with the matching connection graph in generating the layout of the design via the computer.

US Pat. No. 9,171,114

MANAGING THE CONFIGURATION AND FUNCTIONALITY OF A SEMICONDUCTOR DESIGN

Synopsys, Inc., Mountain...

1. A computer-implemented method of generating at least a portion of an integrated circuit design, the method comprising:
providing a user with an integrated circuit design for a processor or processor peripheral device, the integrated circuit
design described by a hardware description language model;

assigning default values to a plurality of design parameters from a set of design parameters for the hardware description
language model, the plurality of design parameters including at least a cache size parameter and a parameter indicating either
to include or not include in the integrated circuit design an interface to memory external to the processor or processor peripheral
device;

providing a graphical user interface (GUI) displaying a representation of the cache size parameter and a representation of
the parameter indicating either to include or not include in the integrated circuit design the interface to memory external
to the processor or processor peripheral device;

receiving, via the GUI, one or more inputs from the user for at least one of the set of design parameters to customize the
integrated circuit design responsive to assigning the default values, the received set of design parameters including a cache
size and an indication to include the interface to memory in the integrated circuit design;

displaying, via the GUI, a plurality of memory extensions available to an extension algorithm for inclusion in the integrated
circuit design based on the indication to include the interface to memory in the integrated circuit design, the plurality
of memory extensions including a load and storage memory controller, an instruction fetch memory controller, a host interface
for communication with the processor or processor peripheral device, an arbitration unit for memory access, and a random access
memory sequencer;

receiving, via the GUI, a selection of one or more of the plurality of memory extensions for inclusion in the integrated circuit
design;

determining, using the extension algorithm, the one or more of the plurality of memory extensions that were selected via the
GUI; and

generating, by a computer, an updated hardware description language model for the integrated circuit design based on the received
set of design parameters and the hardware description language model, wherein the processor or processor peripheral device
is fabricated based at least in part on the updated hardware description language model.

US Pat. No. 9,098,649

DISTANCE METRIC FOR ACCURATE LITHOGRAPHIC HOTSPOT CLASSIFICATION USING RADIAL AND ANGULAR FUNCTIONS

Synopsys, Inc., Mountain...

1. A method of characterizing a plurality of clips of an integrated circuit layout for clustering, the method comprising:
determining a total distance metric for a first clip and a second clip; and
performing said determining the total distance metric for multiple transformations of the first clip to determine a minimized
total distance metric for the first and second clips, each transformation being a reflection or a rotation of the first clip,
wherein the minimized total distance metric determines whether the first and second clips should be clustered,

wherein said determining the total distance metric includes integrating differences of radial and angular functions for polygons
in the first and second clips to provide a distance metric, which is compared to a predetermined threshold to determine whether
polygons in the first and second clips are a matched pair,

the method being performed by a computer.

US Pat. No. 9,542,156

AUTOMATIC CONTROL SYSTEM AND METHOD FOR A TRUE RANDOM NUMBER GENERATOR

Synopsys, Inc., Mountain...

1. A system for reseeding a pseudo random number generator to generate pseudo random numbers, said system comprising
a true random number generator generating a true random number,
a storage device storing the generated true random number,
a pseudo random number generator generating pseudo random numbers using the stored true random number as a seed,
a controller coupled to said true random number generator and said pseudo random number generator to
request a new true random number generated by the true random number generator concurrently with the operation of the pseudo
random number generator, and direct storing of the new true random number, and

reseed the pseudo random number generator with the new true random number upon occurrence of a known condition varied pseudo
randomly by the controller.

US Pat. No. 9,501,597

ELIMINATION OF ILLEGAL STATES WITHIN EQUIVALENCE CHECKING

Synopsys, Inc., Mountain...

1. A computer program product embodied in a non-transitory computer readable medium, which when executed by a processor, causes
the processor to perform design analysis, the computer program product comprising instructions that when executed cause the
processor to:
apply a set of inputs to a first representation and the set of inputs to a second representation for a semiconductor design
wherein the semiconductor design is for fabrication in a semiconductor process;

compare outputs of the first representation and outputs of the second representation, based on the set of inputs that were
applied, to look for mismatch between the outputs of the first representation and the outputs of the second representation;

evaluate in response to detecting a mismatch, a starting point for the first representation to determine whether the starting
point for the first representation is reachable; and

generate a generalized constraint for the starting point for the second representation, if the starting point for the second
representation is not reachable, wherein the generalized constraint is based on an invariant that holds in every reachable
state of the semiconductor design.

US Pat. No. 9,465,897

ANALYSIS OF STRESS IMPACT ON TRANSISTOR PERFORMANCE

SYNOPSYS, INC., Mountain...

1. A method for approximating stress-induced mobility variation in an integrated circuit layout during the development of
an integrated circuit, the integrated circuit layout defining a plurality of transistors each having a respective channel,
comprising:
approximating the stress at each of a plurality of sites in the channels of each of more than twelve of the transistors in
the integrated circuit layout;

converting the stress approximation at each of the sites to a respective mobility variation value;
combining the respective mobility variation value at all the sites in the channel of each particular one of the more than
twelve transistors, to develop an overall mobility variation value for that particular transistor; and

providing for circuit simulation a value dependent upon the mobility variation value developed for each of the more than twelve
transistors.

US Pat. No. 9,461,655

PHASE INTERPOLATOR WITH PHASE TRAVERSING FOR DELAY-LOCKED LOOP

Synopsys, Inc., Mountain...

1. A method for phase-traversing from an initial clock signal to a final output clock signal, comprising:
providing the initial clock signal having a phase comprising weighted phases of a first and second component clock signal,
each component clock signal originating from a common clock source, the phase of the first component clock signal weighted
by weight1, and the phase of the second component clock signal weighted by (1-weight1);

providing a third component clock signal originating from the common clock source, and having a phase that is opposite to
the phase of the first component clock signal relative to the phase of the second component clock when the phases of the component
clock signals are mapped onto a unit circle;

generating an intermediate clock signal having a phase comprising the phase of the second component clock signal; and
generating the final output clock signal having a phase comprising the weighted phases of the second and third component clock
signal, the phase of the second component clock signal weighted by weight2, and the phase of the third component clock signal
weighted by (1-weight2).

US Pat. No. 9,411,014

REORDERING OR REMOVAL OF TEST PATTERNS FOR DETECTING FAULTS IN INTEGRATED CIRCUIT

Synopsys, Inc., Mountain...

1. A method for reordering a test pattern set for testing an integrated circuit, comprising:
computing a productivity index for each test pattern in the test pattern set, the productivity index indicating a number of
faults detectable by a test pattern but not by other test patterns of the test pattern set preceding the test pattern;

comparing a productivity index of a first test pattern and a productivity index of a second test pattern, the second test
pattern appearing later in the test pattern set than the first test pattern; and

swapping locations of the first test pattern and the second test pattern responsive to the productivity index of the second
test pattern being higher than the productivity index of the first test pattern.

US Pat. No. 9,383,977

GENERATION OF COMPILER DESCRIPTION FROM ARCHITECTURE DESCRIPTION

Synopsys, Inc., Mountain...

1. A computer implemented method of generating a compiler description from an architecture description, comprising:
extracting, by a compiler description generator, information from an architecture description describing an architecture of
an application specific instruction set processor (ASIP);

receiving, by the compiler description generator via a source different than the architecture description, definitions for
a plurality of abstract elements of a compiler that have no direct representative in the architecture description, the abstract
elements comprising a non-terminal representing a data path in common with a plurality of compiler instructions;

extracting, by the compiler description generator, a mapping of compiler rules to instructions included in the architecture
description; and

automatically generating, by the compiler description generator, a compiler description of the compiler for the architecture
of the ASIP based on the extracted information, the received definitions for the plurality of abstract elements, and the extracted
mapping, wherein a compiler generator generates the compiler based on the compiler description.

US Pat. No. 9,195,634

OPTIMIZING CONSTRAINT SOLVING BY REWRITING AT LEAST ONE MODULO CONSTRAINT

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) software tool in a computer, a method for assigning random values to a set of
random variables, the method comprising:
the EDA software tool in the computer receiving a set of constraints, wherein each constraint is defined over one or more
random variables from the set of random variables, wherein the set of constraints includes one or more modulo constraints
that use a modulo operator;

the EDA software tool in the computer rewriting the set of constraints to obtain a new set of constraints, wherein said rewriting
includes replacing at least one modulo constraint whose divisor is not equal to a power of two with one or more non-modulo
constraints, wherein the one or more non-modulo constraints use only non-modulo operators, and wherein the one or more non-modulo
constraints use at least one random variable other than those used in the modulo constraint; and

the EDA software tool in the computer assigning random values to the set of random variables based on the new set of constraints,
wherein the EDA software tool in the computer uses the set of random variables to generate one or more random stimuli to perform
functional verification on a circuit design under verification.

US Pat. No. 9,184,110

LATCH-UP SUPPRESSION AND SUBSTRATE NOISE COUPLING REDUCTION THROUGH A SUBSTRATE BACK-TIE FOR 3D INTEGRATED CIRCUITS

SYNOPSYS, INC., Mountain...

5. An integrated circuit device comprising:
a first semiconductor substrate having opposite topside and backside surfaces, the first semiconductor substrate having a
transistor therein;

a first conductor extending entirely through the first substrate, the first conductor being electrically connected on a first
end to a first point on the first substrate topside surface and on a second end to a second point on the first substrate backside
surface;

an additional TSV passing through the first substrate;
an insulating layer on the backside surface of the first substrate; and
a plurality of RDL conductors on the backside of the insulating layer,
wherein the additional TSV is electrically connected to one of the RDL conductors through a via in the insulating layer, and
the first conductor is not connected to any RDL conductors on the backside of the first substrate.

US Pat. No. 9,860,055

FLEXIBLE ARCHITECTURE FOR PROCESSING OF LARGE NUMBERS AND METHOD THEREFOR

Synopsys, Inc., Mountain...

1. A method for performing a cryptographic process, the method comprising:
receiving a security level for processing the cryptographic process;
storing the security level in a control register;
transforming a first cryptographic process into a process rewritten to optimize the use of a plurality of large number operations
supported within a core processor; and

executing the first security process on the core processor based on the security level stored in the control register and
how the core processor is implemented.

US Pat. No. 9,672,317

QUALITY OF RESULTS SYSTEM

Synopsys, Inc., Mountain...

1. A parser apparatus for use in an electronic design automation design flow, the parser apparatus stored in a computer readable
storage device, the parser apparatus comprising:
a parser to parse task output containing data relevant to a quality of results (QoR) decision and identify a pre-defined data
characteristic in the task output; and

a processor to execute the parser upon receipt of the task output,
wherein selected result values obtained from the parser execution are used to make a decision, manually or automatically,
about a next action to be performed in the design flow, and

wherein the design flow process results in a design state representation and the design state representation is used to fabricate
an integrated circuit.

US Pat. No. 9,612,943

PRIORITIZATION OF TESTS OF COMPUTER PROGRAM CODE

Synopsys, Inc., Mountain...

1. A method to prioritized testing of computer program code, the method, comprising:
obtaining a user input, the user input indicating test weighting criteria and test prioritization criteria;
performing a baseline run, wherein performing the baseline run comprises:
performing at least one dynamic test on a baseline source code to produce runtime observations,
performing a static analysis on the baseline source code to produce a first property summary, the first property summary identifying
at least one property associated with a function within the baseline source code, and

storing, in a non-transitory storage device, a history, the history comprising the runtime observations and the first property
summary;

after performing the baseline run, performing a partial run, wherein performing the partial run comprises:
performing a static analysis on a modified source code to produce a second property summary, the second property summary identifying,
in the modified source code, the at least one property associated with the function identified within the baseline source
code and identifying, in the modified source code, at least one property associated with the function identified within the
baseline source code wherein the property has changed relative to the baseline source code version, the modified source code
being a modified version of the baseline source code, and

wherein the function is a first function, and wherein the first property summary or the second property summary indicates
an impact of a change in the first function on a second function, wherein the second function is unchanged from the baseline
source code to the modified source code;

storing a partial run results record, the partial run results record comprising the second property summary;
prioritizing a plurality of tests based at least in part on the user input, information from the history, and information
from the partial run results record; and

executing the plurality of tests according to the priority.

US Pat. No. 9,507,729

METHOD AND PROCESSOR FOR REDUCING CODE AND LATENCY OF TLB MAINTENANCE OPERATIONS IN A CONFIGURABLE PROCESSOR

Synopsys, Inc., Mountain...

1. A memory management unit (MMU) for storing mappings between virtual addresses and physical addresses, the MMU comprising:
a translation look-aside buffer (TLB) configured to store mappings between virtual address and physical address; and
a memory management unit (MMU) controller configured to:
receive a request to insert an entry into the TLB, the request comprising a virtual address and a physical address, and
responsive to receiving the request to insert the entry:
determining whether a stored entry in the TLB matches the virtual address of the requested entry by comparing the virtual
address of the requested entry to a virtual address associated with each stored entry in the TLB;

responsive to determining that the stored entry matches the virtual address of the requested entry, replacing the stored entry
with the requested entry; and

responsive to determining that the stored entry does not match the virtual address of the requested entry determining a location
in the TLB to insert the requested entry.

US Pat. No. 9,454,626

SOLVING AN OPTIMIZATION PROBLEM USING A CONSTRAINTS SOLVER

SYNOPSYS, INC., Mountain...

1. A method for using a constraints solver to determine an optimum value for an objective function of an optimization problem,
the method comprising:
receiving a set of constraints that is defined over a set of variables, wherein the set of constraints corresponds to the
optimization problem, and wherein the set of constraints includes one or more constraints that impose an upper bound on one
or more variables that are used in the objective function of the optimization problem; and

iteratively performing the following set of operations on a computer:
solving the set of constraints using a constraints solver;
responsive to the constraints solver returning a solution, decreasing the upper bound; and
responsive to the constraints solver indicating that no solutions exist or that the constraints solver timed out, increasing
the upper bound.

US Pat. No. 9,384,319

DETECTING AND DISPLAYING MULTI-PATTERNING FIX GUIDANCE

Synopsys, Inc., Mountain...

1. A computer implemented method for validating a design, the method comprising:
generating, using the computer, a graph non-decomposable to a colored graph representative of the design, when the computer
is invoked to validate the design;

identifying, using the computer, at least one guidance to at least one conflict in a mask layout associated with the design,
said conflict causing the graph to be non-decomposable; and

building, using the computer, a first set of conflict edges characterized by an upper bound on a minimum number of the at
least one conflict using a first coloring attempt of one of a plurality of coloring attempts on the graph by a coloring algorithm.

US Pat. No. 9,280,625

INCREMENTAL SLACK MARGIN PROPAGATION

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool in a computer, a method for incrementally propagating slack margins in a
circuit design while optimizing the circuit design by processing gates in the circuit design in a reverse-levelized order,
the method comprising:
after the EDA tool in the computer replaces a first gate with an alternative gate, the EDA tool in the computer marking outputs
of source drivers that drive inputs of the alternative gate as out-of-date;

in response to the EDA tool in the computer determining that an output of a source driver is marked out-of-date, the EDA tool
in the computer performing at least the following operations: (1) computing a new arrival time at the output of the source
driver, (2) propagating the new arrival time to inputs of gates that are driven by the output of the source driver, and (3)
removing an out-of-date mark from the output of the source driver;

in response to the EDA tool in the computer determining that an input of a second gate is marked out-of-date or that a slack
margin was not computed for an output of the second gate, the EDA tool in the computer performing at least the following operations:
(1) propagating arrival times from the input to the output of the second gate, and (2) marking the output of the second gate
as having an out-of-date slack margin; and

in response to the EDA tool in the computer determining that an output of a third gate is marked as having an out-of-date
slack margin, the EDA tool in the computer performing at least the following operations: (1) computing new slack margins for
the output of the third gate based on the old arrival time, new arrival time, and old slack margin at the output of the third
gate, and (2) computing new slack margins for each input of the third gate based on a new margin at the output of the third
gate and an arrival time from each input of the third gate to the output of the third gate.

US Pat. No. 9,152,752

INCREASING PRPG-BASED COMPRESSION BY DELAYED JUSTIFICATION

Synopsys, Inc., Mountain...

1. A method of generating a pseudo-random pattern generator (PRPG) set of bits to increase scan compression, the method comprising:
generating xheadlines for a circuit design, the xheadlines being decision nodes resulting from at least one of gate modification
restrictions, dynamic value considerations, and fanout allowance; and

mapping the xheadlines and any care bits, which are generated for non-xheadlines, to the PRPG set of bits,
wherein the gate modification restrictions include limiting the xheadlines to AND, OR, and XOR logic networks or their inverted
versions.

US Pat. No. 9,064,082

UPDATING PIN LOCATIONS IN A GRAPHICAL USER INTERFACE OF AN ELECTRONIC DESIGN AUTOMATION TOOL

SYNOPSYS, INC., Mountain...

1. In an electronic design automation (EDA) tool, a method for updating pin locations in a graphical user interface (GUI)
of the EDA tool, wherein a set of pins are currently located at a set of pin locations on an edge of a block or partition
in a circuit design layout, the method comprising:
in a computer when the EDA tool modifies the circuit design layout:
responsive to determining that the edge has increased in length, the EDA tool does not change the set of pin locations in
the GUI of the EDA tool;

responsive to determining that the edge has decreased in length but is long enough to preserve the first set of pin locations,
the EDA tool does not change the set of pin locations in the GUI of the EDA tool; and

responsive to determining that the edge has decreased in length and is not long enough to preserve the set of pin locations,
the EDA tool decreases distances between neighboring signal pins in the GUI of the EDA tool while preserving (1) locations
of one or more power pins, (2) relative ordering of signal pins, and (3) locations of one or more fixed pins.

US Pat. No. 9,052,357

PACKET SWITCH BASED LOGIC REPLICATION

Synopsys, Inc., Mountain...

1. A method for debugging a source circuit, the method comprising upon receiving information regarding the source circuit:
compiling representation of a source circuit including one or more source subchannels associated with portions of source logic
driven by a plurality of clock domains, each source subchannel to generate packets carrying signal data from one of the portions
of the source logic;

compiling representation of a destination circuit including one or more destination subchannels associated with portions of
destination logic replicating the source logic, each destination subchannel to forward the signal data via the packets to
one of the portions of the destination logic;

configuring a switching logic mapping the source subchannels to the destination subchannels as virtual channels to forward
the packets from the source subchannels to the destination subchannels, the packets based on a packet format including a header
field and a payload field, the header field to carry channel identifiers identifying the virtual channels and the payload
field to carry the signal data; and

configuring a single queue coupled to the switching logic to record packets from the source subchannels into a packet stream
for a delay period to distribute to the destination subchannels for the destination logic to emulate the source logic synchronous
with the plurality of clock domains with the delay period.

US Pat. No. 9,195,791

CUSTOM MODULE GENERATION

SYNOPSYS, INC., Mountain...

1. A computer-implemented method for creating a layout for a circuit design which includes a circuit module, the method comprising:
receiving a user-defined module generator to generate at least one custom implementation of the circuit module from an existing
implementation of the circuit module; and

creating the layout for the circuit design by:
converting the existing implementation from an internal representation of the existing implementation of the circuit module
to an open representation of the existing implementation of the circuit module, wherein the open representation of the existing
implementation of the circuit module is a standardized data model and interface for representing and accessing the existing
implementation of the circuit module;

executing the user-defined module generator on at least one processor to generate at least one open representation of a custom
implementation of the circuit module from the open representation of the existing implementation of the circuit module, wherein
the user-defined module generator generates the open representation of the custom implementation of the circuit module by
modifying the open representation of the existing implementation of the circuit module to satisfy a set of constraints;

converting the custom implementation of the circuit module from the open representation of the custom implementation of the
circuit module to an internal representation of the custom implementation of the circuit module; and

instantiating the internal representation of the custom implementation of the circuit module in the layout.

US Pat. No. 9,588,179

SCHEME FOR MASKING OUTPUT OF SCAN CHAINS IN TEST CIRCUIT

Synopsys, Inc., Mountain...

1. A computer implemented method for masking scan chains in a test circuit of an integrated circuit, the method comprising:
generating, by a computer, a test pattern including a plurality of input values for detecting a primary fault representing
a fault for which an initial subset of input values in the test pattern is generated, at least one secondary fault representing
a fault detectable by specifying input values other than the initial subset of input values, and at least one tertiary fault
representing a fault detectable by the test pattern specified with the input values for the primary and the at least one secondary
fault;

responsive to a condition not being met, generating first mask data configured to mask a first subset of scan chains to increase
a total number of detectable primary, secondary, and tertiary faults associated with the test pattern; and

responsive to the condition being met, generating second mask data configured to mask a second subset of scan chains to protect
the primary fault associated with the test pattern.