US Pat. No. 9,491,894

MANUFACTURING METHOD OF COVER STRUCTURE

Subtron Technology Co., L...

1. A method of manufacturing a cover structure, the method comprising:
providing a first insulating layer having a first surface and a second surface opposite to each other;
providing a second insulating layer having a third surface and a fourth surface opposite to each other and an opening passing
through the third surface and the fourth surface, wherein a thickness of the second insulating layer is greater than a thickness
of the first insulating layer;

laminating the first insulating layer and the second insulating layer for the third surface of the second insulating layer
to connect to the second surface of the first insulating layer, wherein a cavity is defined by the opening of the second insulating
layer and the first insulating layer;

forming a metal layer on the cavity and on the fourth surface of the second insulating layer; and
patterning a portion of the metal layer formed on the fourth surface of the second insulating layer to form a patterned circuit
layer.

US Pat. No. 9,433,099

PACKAGE CARRIER

Subtron Technology Co., L...

1. A package carrier, comprising:
a removable supporting plate comprising a dielectric layer, a copper foil layer and a releasing layer, wherein the dielectric
layer is disposed between the copper foil layer and the releasing layer; and

a circuit board disposed on the removable supporting plate and directly contacting the releasing layer the circuit board comprising:
a circuit layer comprises a first patterned circuit layer and a second patterned circuit layer; and an insulation layer disposed
between the first patterned circuit layer and the second patterned circuit layer, and having a first surface and a second
surface opposite to each other;

a first patterned solder mask layer disposed on the upper surface of the first patterned circuit layer and exposing a portion
of the upper surface: and

a second patterned solder mask layer disposed between the second pattern circuit layer and the releasing layer and on the
lower surface of the second pattern circuit layer and exposing a portion of the lower surface, wherein the releasing layer
and the second patterned solder mask layer are conformally disposed, a side surface of the second patterned solder mask layer
is covered by the releasing layer, and the lower surface exposed by the second patterned solder mask layer directly contacts
the releasing layer, and wherein a thickness of the circuit board is between 30 ?m to 100 ?m.

US Pat. No. 9,131,635

MANUFACTURING METHOD OF SUBSTRATE STRUCTURE

Subtron Technology Co., L...

1. A manufacturing method of a substrate structure, comprising:
providing a base material, wherein the base material has a core layer, and a first copper foil layer and a second copper foil
layer located at a first surface and a second surface of the core layer, where the first surface and the second surface are
opposite to each other;

performing a surface treatment on the first copper foil layer and the second copper foil layer, so as to form a first roughened
surface and a second roughened surface respectively on the first copper foil layer and the second copper foil layer;

irradiating a laser beam on the first roughened surface of the first copper foil layer, so as to form at least one first blind
hole extending from the first copper foil layer to the second surface of the core layer;

performing an etching process on the second copper foil layer, so as to form at least one second blind hole extending from
the second copper foil layer to the second surface of the core layer, wherein the second blind hole connects with the first
blind hole to constitute of at least one through hole; and

forming a conductive layer on the first copper foil layer and the second copper foil layer, wherein the conductive layer fills
up the through hole and covers the first copper foil layer and the second copper foil layer.

US Pat. No. 9,313,886

SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a substrate structure, comprising:
providing a substrate, the substrate comprising a supporting layer, two release layers and two base metal layers, the two
release layers disposed on two opposite surfaces of the supporting layer respectively, the two base metal layers covering
the two release layers respectively;

forming two etch stop layers on each of the base metal layers;
forming two patterned metal layers on each of the etch stop layers, each of the patterned metal layers comprising a plurality
of openings to expose a corresponding portion of the etch stop layer, wherein each of the etch stop layers is located between
each of the base metal layers and each of the patterned metal layers;

forming two first patterned solder-resist layers on each of the patterned metal layers to cover the exposed portion of the
base metal layer;

laminating a stacking layer on each of the patterned metal layers, each of the stacking layers covering the corresponding
first patterned solder-resist layer, wherein each of the stacking layers comprises a dielectric layer and a metal foil, and
each of the dielectric layers is disposed between the corresponding patterned metal layer and the corresponding metal foil;

separating each of the base metal layers from the release layer to remove the supporting layer;
removing each of the base metal layers by etching to expose each of the etch stop layers; and
removing each of the etch stop layers to expose each of the patterned metal layers and each of the first patterned solder-resist
layers.

US Pat. No. 9,655,254

MANUFACTURING METHOD OF CIRCUIT SUBSTRATE

SUBTRON TECHNOLOGY CO. LT...

1. A method for manufacturing a circuit substrate, comprising:
bonding peripheries of two metal layers directly to form a sealed area;
forming at least a through hole passing through the sealed area, and wherein an area of the through hole is smaller than an
area of the sealed area;

forming two first insulating layers on the two metal layers and forming two inner conductive layers on the two first insulating
layers, wherein an area of each of the two first insulating layers is larger than an area of each of the two metal layers;

laminating the two first insulating layers and the two inner conductive layers and the two metal layers bonded with each other
being embedded in the two first insulating layers, wherein portions of the two first insulating layers fill in the through
hole when the two first insulating lavers are laminated;

patterning the two inner conductive layers, forming two second insulating layers on the two inner conductive layers, and forming
two outer conductive layers on the two second insulating layers;

laminating the second insulating layers and the two outer conductive layers and the two inner conductive layers being embedded
in the second insulating layers; and

separating the sealed area of the two metal layers to form two separated circuit substrates by removing a region of the sealed
area.

US Pat. No. 9,532,494

MANUFACTURING METHOD OF PACKAGE STRUCTURE

Subtron Technology Co., L...

1. A manufacturing method of a package structure, comprising:
providing a substrate, the substrate having an upper surface, a lower surface, and an opening, the upper surface and the lower
surface being opposite to each other, the opening communicating the upper surface and the lower surface;

configuring an electronic device in the opening of the substrate;
laminating an adhesive layer and a patterned metal layer located on the adhesive layer on the lower surface of the substrate,
the adhesive layer and the patterned metal layer exposing a bottom surface of the electronic device;

forming a heat-dissipating column on the bottom surface of the electronic device exposed by the adhesive layer and the patterned
metal layer after laminating the adhesive layer and the patterned metal layer located on the adhesive layer on the lower surface
of the substrate, the heat-dissipating column connecting the patterned metal layer and the bottom surface of the electronic
device; and

respectively laminating a first laminated structure and a second laminated structure on the upper surface of the substrate
and the patterned metal layer after forming the heat-dissipating column, the first laminated structure covering the upper
surface of the substrate and a top surface of the electronic device, the second laminated structure covering the heat-dissipating
column and the patterned metal layer, wherein the first laminated structure comprises at least one first dielectric layer,
at least one first patterned metal layer, and at least one conductive via penetrating the at least one first dielectric layer,
the at least one first dielectric layer and the at least one first patterned metal layer are sequentially stacked on the upper
surface of the substrate, the opening is filled with the at least one first dielectric layer, and the at least one first patterned
metal layer is electrically connected to the electronic device through the at least one conductive via.

US Pat. No. 9,510,453

PACKAGE CARRIER

Subtron Technology Co., L...

1. A package carrier suitable for carrying at least a chip, the package carrier comprising:
an insulating layer having a first surface and a second surface opposite to each other;
a patterned circuit layer, embedded in the second surface of the insulating layer and having a bonding surface, wherein the
second surface of the insulating layer and the bonding surface of the patterned circuit layer are coplanar, and the patterned
circuit layer comprises at least one die pad;

a plurality of conductive connection structures embedded in the insulating layer and connected to the patterned circuit layer;
a plurality of pads disposed on the first surface of the insulating layer and respectively connected to the conductive connection
structures;

a solder resist layer disposed on the second surface of the insulating layer wherein a portion of the bonding surface of the
patterned circuit layer is exposed by the solder resist layer; and

a surface treatment layer disposed on the bonding surface of the patterned circuit layer, wherein a portion of the surface
treatment layer is located between the chip and the die pad, a height difference is formed between a first top surface of
the solder resist layer and a second top surface of the surface treatment layer so as to form a cavity between a sidewall
of the solder resist layer and the second top surface of the surface treatment layer, and portions of the chip is embedded
in the cavity formed by the solder resist layer and surface treatment layer, and a bottom surface of the chip is lower than
the first top surface of the solder resist layer.

US Pat. No. 9,137,899

PROCESS OF ELECTRONIC STRUCTURE AND ELECTRONIC STRUCTURE

Subtron Technology Co., L...

1. A process of an electronic structure, comprising:
providing a carrier board with a first surface;
forming a first release layer on the first surface of the carrier board, wherein the first release layer has property of temporary
adhesion capability and the first release layer entirely or mostly overlays the first surface;

forming a built-up structure on the first release layer, wherein step of forming the built-up structure comprises at least
disposing a conductive layer, a dielectric layer, a conductive blind via passing through the dielectric layer, a core layer
or an electronic device on the first release layer of the carrier board;

after forming the built-up structure on the first release layer, providing another carrier board with another release layer,
wherein the another carrier board is aligned and adhered on the built-up structure;

separating the built-up structure from the carrier board on the edges so as to be transferred onto the another carrier board
by using a physical lift-off process;

turning-over the built-up structure and forming another built-up structure on the built-up structure; and
performing a separating process so that the built-up structure is separated from the carrier board to form an electronic structure.

US Pat. No. 9,204,546

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A circuit board, comprising:
an insulation layer, having an upper surface and a lower surface opposite to each other;
a patterned circuit layer, embedded in the insulation layer, and a surface of the patterned circuit layer aligned with the
upper surface of the insulation layer, wherein the insulation layer has at least one blind via extending from the lower surface
to the patterned circuit layer;

a conductive connecting structure, comprising a conductive pattern layer and at least one conductive pillar, wherein the conductive
pattern layer is disposed on the lower surface of the insulation layer, and the conductive pillar is disposed inside the blind
via and connects the patterned circuit layer and the conductive pattern layer;

a first solder resist layer, disposed on the lower surface of the insulation layer, and having at least one first opening,
wherein the first opening exposes a portion of the conductive pattern layer so as to define at least one first pad;

a second solder resist layer, disposed on the upper surface of the insulation layer, and having at least one second opening,
wherein the second opening exposes a portion of the patterned circuit layer so as to define at least one second pad; and

at least one conductive bump, disposed on the second pad, wherein a top surface of the conductive bump is higher than a second
surface of the second solder resist layer.

US Pat. No. 9,204,560

MANUFACTURING METHOD OF PACKAGE CARRIER

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, comprising:
providing an insulation substrate, the insulation substrate having an upper surface, a lower surface opposite to the upper
surface, a plurality of cavities and a plurality of through holes, wherein the cavities are located at the lower surface,
and the through holes pass through the insulation substrate and respectively communicate with the cavities to define a plurality
of vias, and a diameter of each of the through holes is substantially less than a diameter of each of the cavities;

performing an electroless plating process to form a conductive material on the upper surface, the lower surface and in the
vias of the insulation substrate, wherein the conductive material covers the upper surface and the lower surface of the insulation
substrate and fills up the vias;

removing a portion of the conductive material on the upper surface and the lower surface of the insulation substrate to expose
the upper surface and the lower surface of the insulation substrate, wherein the conductive material fills up the vias to
define a plurality of conductive posts;

forming an insulation layer on the upper surface of the insulation substrate, wherein the insulation layer has a top surface
relatively far from the upper surface of the insulation substrate and a plurality of blind vias extending from the top surface
to the conductive posts;

forming a patterned circuit layer on the top surface of the insulation layer, wherein the patterned circuit layer fills up
the blind vias and is connected to the conductive posts, and the patterned circuit layer exposes a portion of the top surface
of the insulation layer; and

forming a solder mask layer on the patterned circuit layer, the solder mask layer covering the patterned circuit layer and
the exposed portion of the top surface of the insulation layer, the solder mask layer having a plurality of openings, wherein
the openings expose a portion of the patterned circuit layer to define a plurality of pads.

US Pat. No. 9,153,521

METHOD OF MANUFACTURING A PACKAGE CARRIER

Subtron Technology Co., L...

1. A method of manufacturing a package carrier, comprising:
providing an insulation cover, the insulation cover having an inner surface and an outer surface opposite to each other, a
plurality of openings, and a containing space, wherein the insulation cover comprises a plurality of catalyst particles;

irradiating the outer surface of the insulation cover with a laser beam to activate parts of the catalyst particles so as
to form a patterned metal layer on the outer surface of the insulation cover;

forming a surface treatment layer on the patterned metal layer; and
forming a heat dissipation element in the containing space of the insulation cover, the heat dissipation element being structurally
connected to the insulation cover, wherein a thermal-conductive layer is formed on a surface of the heat dissipation element,
and the openings of the insulation cover expose a portion of the thermal-conductive layer.

US Pat. No. 9,418,931

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package structure, comprising:
providing a substrate, the substrate includes a core layer, a first patterned metal layer and a second patterned metal layer,
and the first patterned metal layer and the second patterned metal layer respectively disposed on two opposite surfaces of
the core layer;

forming a through cavity penetrating the substrate;
disposing the substrate on a tape carrier;
disposing a semiconductor component in the through cavity and positioned on the tape carrier, and an inner wall of the through
cavity and a side surface of the semiconductor device jointly defining a groove;

dispensing a filling compound above the groove, wherein a material of the filling compound comprises epoxy;
performing a heating process for the filling compound to flow toward the tape carrier and comprehensively filling the groove;
laminating a first stacked layer onto the substrate towards the first patterned metal layer, and the first stacked layer covering
at least a part of the semiconductor component;

removing the tape carrier; and
laminating a second stacked layer onto the substrate towards the second patterned metal layer, and the second stacked layer
covering at least a part of the semiconductor component.

US Pat. No. 9,603,263

MANUFACTURING METHOD OF CIRCUIT SUBSTRATE

Subtron Technology Co., L...

1. A manufacturing method of a circuit substrate, comprising:
bonding peripheries of two metal layers to form a sealed area, wherein each of the two metal layers comprises a first copper
foil layer and a second copper foil layer, and a thickness of each of the second copper foil layers is substantially greater
than a thickness of each of the first copper foil layers, and the second copper foil layers are bonded to each other;

forming at least a through hole passing through the sealed area;
forming two insulating layers on the two metal layers, and forming two conductive layers on the two insulating layers;
laminating the two insulating layers and the two conductive layers to the two metal layers, wherein the two metal layers bonded
to each other are embedded between the two insulating layers, and the two insulating layers are filled into the through hole;

separating the sealed area of the two metal layers to form two separated circuit substrates; and
removing the second copper foil layers from each of the two separated circuits by a lift-off method, wherein the lift-off
method comprises peeling off the second copper foil layer from the first copper foil layer.

US Pat. No. 9,247,632

COVER STRUCTURE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a cover structure, the manufacturing method comprising:
disposing a metal substrate on a carrier having a surface, and the metal substrate comprising a plurality of openings that
expose a portion of the surface of the carrier, wherein the metal substrate comprises a first metal layer formed thereon which
is disposed conformally with the metal substrate, and the first metal layer covers the portion of the surface of the carrier
exposed by the openings;

laminating an insulating layer and a second metal layer located on the insulating layer on the metal substrate, wherein the
insulating layer is located between the first metal layer and the second metal layer, and covers the first metal layer and
fills the openings; and

removing the metal substrate and the carrier to expose the first metal layer and define a plurality of cavity regions and
a plurality of connecting regions connected with the cavity regions, wherein positions of the cavity regions correspond to
positions of the metal substrate, and positions of the connecting regions correspond to the positions of the openings.

US Pat. No. 9,591,753

CIRCUIT BOARD AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

6. A manufacturing method of a circuit board, comprising:
providing a substrate;
forming a patterned copper layer on the substrate, wherein the patterned copper layer covers the substrate and exposes a portion
of the substrate;

forming a phosphorous-containing electroless plating palladium layer on the patterned copper layer, wherein the phosphorous-containing
electroless plating palladium layer covers the patterned copper layer, and in the phosphorous-containing electroless plating
palladium layer, a weight percentage of phosphorous is in a range from 4% to 6%, and a weight percentage of palladium is in
a range from 94% to 96%;

forming an electroless plating palladium layer on the phosphorous-containing electroless plating palladium layer, wherein
the electroless plating palladium layer covers the phosphorous-containing electroless plating palladium layer, and in the
electroless plating palladium layer, a weight percentage of palladium is at least 99% or more; and

forming an immersion plating gold layer on the electroless plating palladium layer, wherein the immersion plating gold layer
covers the electroless plating palladium layer.

US Pat. No. 9,538,647

SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF

SUBTRON TECHNOLOGY CO., L...

1. A substrate structure, comprising:
a substrate, comprising a dielectric layer, a plurality of pads, a patterned solder mask, a first through hole, a first surface,
and a second surface opposite to the first surface, the plurality of pads being respectively disposed on two opposite surfaces
of the dielectric layer, the patterned solder mask covering the two opposite surfaces and exposing the plurality of pads,
wherein the first through hole penetrates the substrate for connecting the first surface and the second surface and the first
through hole penetrates the dielectric layer and the patterned solder mask; and

a carrier, comprising a second through hole, a release layer, an insulating paste layer, and a metal layer, wherein the insulating
paste layer is disposed between the release layer and the metal layer, the carrier is attached to the second surface by attaching
the release layer to the second surface and contacting the release layer with the patterned solder mask, the second through
hole corresponds to the first through hole and penetrates the carrier for exposing the first through hole, and a smallest
diameter of the second through hole is greater than a largest diameter of the first through hole.

US Pat. No. 9,330,941

PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, comprising:
providing a supporting board having an upper surface;
forming a patterned circuit layer directly on the upper surface of the supporting board, wherein the patterned circuit layer
exposes a portion of the upper surface of the supporting board, and the patterned circuit layer comprises at least one die
pad;

laminating an insulating layer and a conductive layer located at a first surface of the insulating layer directly onto the
patterned circuit layer, wherein the insulating layer covers the patterned circuit layer and the portion of the upper surface
of the supporting board exposed by the patterned circuit layer;

forming a plurality of conductive connection structures directly on the patterned circuit layer;
patterning the conductive layer to define a plurality of pads respectively connected to the conductive connection structures
and to expose a portion of the first surface of the insulating layer;

removing the supporting board to expose a second surface opposite to the first surface of the insulating layer, wherein the
second surface of the insulating layer and a bonding surface of the patterned circuit layer are coplanar;

forming a solder resist layer directly on the second surface of the insulating layer after removing the supporting board,
wherein a portion of the bonding surface of the patterned circuit layer is exposed by the solder resist layer; and

forming a surface treatment layer directly on the bonding surface of the patterned circuit layer after removing the supporting
board, wherein a portion of the surface treatment layer is located between a chip and the die pad, a height difference is
between a first top surface of the solder resist layer and a second top surface of the surface treatment layer so as to form
a cavity between a sidewall of the solder resist layer and the second top surface of the surface treatment layer, and portions
of the chip is embedded in the cavity formed by the solder resist layer and surface treatment layer, and a bottom surface
of the chip is lower than the first top surface of the solder resist layer.

US Pat. No. 9,648,760

SUBSTRATE STRUCTURE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A substrate structure, comprising:
a dielectric layer comprising a first surface and a second surface opposite to the first surface, the first surface having
a plurality of recesses;

a metal foil disposed on the second surface;
a first patterned solder-resist layer filled into each of the recesses, a top surface of the first patterned solder-resist
layer being substantially coplanar with the first surface;

a patterned metal layer disposed on the first surface and having a plurality of openings at least partially exposing the first
patterned solder-resist layer;

a release layer disposed between the first patterned solder-resist layer and the dielectric layer and between the patterned
metal layer and the dielectric layer; and

a second patterned solder-resist layer disposed on the first patterned solder-resist layer and in the openings of the patterned
metal layer, and covering a portion of the patterned metal layer.

US Pat. No. 9,236,364

PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, comprising:
bonding two base metal layers;
laminating two supporting layers onto the base metal layers respectively;
disposing two release metal films on the supporting layers respectively, wherein each of the release metal films comprises
a first metal foil and a second metal foil separable from each other;

forming two patterned metal layers on the release metal films respectively, wherein each of the patterned metal layers is
capable of carrying and electrically connected to a chip; and

separating the two base metal layers from each other to form two package carriers independent from each other.

US Pat. No. 9,282,643

CORE SUBSTRATE AND METHOD FOR FABRICATING CIRCUIT BOARD

Subtron Technology Co., L...

1. A method for fabricating a circuit board, comprising:
providing a core substrate, the core substrate comprising:
a dielectric layer;
two releasing layers disposed on the dielectric layer and respectively and directly covering two side surfaces of the dielectric
layer;

two first copper foil layers respectively disposed on the releasing layers and directly covering the releasing layers; and
two nickel layers respectively disposed on the first copper foil layers and directly covering the first copper foil layers;
forming two patterned circuit layers respectively on the nickel layers, wherein the patterned circuit layers expose portions
of the nickel layers;

forming two insulating layers respectively on the patterned circuit layers, wherein the insulating layers cover the patterned
circuit layers and the portions of the nickel layers;

performing a lift-off step to separate the releasing layers from the dielectric layer;
performing a first etching step using the nickel layers as etching stop layers to remove the first copper foil layers so as
to expose the nickel layers; and

performing a peeling step to remove the nickel layers so as to expose the patterned circuit layers, wherein top surfaces of
the patterned circuit layers are aligned with upper surfaces of the insulating layers.

US Pat. No. 9,578,750

PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, comprising:
bonding two base metal layers to each other;
laminating two supporting layers onto the two base metal layers respectively;
disposing two first metal films and two second metal films on the two supporting layers respectively, wherein each of the
second metal films is disposed between the supporting layer and the first metal film, and the first metal film and the second
metal film are separable from each other;

forming two patterned etch-stop layers respectively on the two first metal films;
forming two first patterned metal layers on the two patterned etch-stop layers respectively, wherein each of the first patterned
metal layers comprises at least one pad pattern, and the two first patterned metal layers are disposed on the two patterned
etch-stop layers respectively;

forming two dielectric layers on the two first patterned metal layers respectively and covering the corresponding first patterned
metal layers, wherein each of the dielectric layers comprises at least one conductive via respectively connecting the corresponding
pad pattern;

forming two second patterned metal layers on the two dielectric layers respectively, wherein each of the second patterned
metal layers at least covers a top surface of the corresponding conductive via;

separating the two base metal layers from each other to form two package carriers independent from each other;
separating the two second metal films, the two supporting layers, and the two base metal layers from the first metal films;
removing the first metal films by an etching process, wherein the etching process is stopped by the patterned etch-stop layers;
and

removing the patterned etch-stop layers from the first patterned metal layers after removing the first metal films.

US Pat. No. 9,458,540

PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package substrate, comprising:
forming a first base;
forming a plurality of metal bumps on the first base by plating, wherein the metal bumps expose parts of the first base;
providing a second base, the second base having an upper surface and a lower surface opposite to each other, a core dielectric
layer, a first copper foil layer, a second copper foil layer, and a plurality of containing cavities, wherein the first copper
foil layer and the second copper foil layer are respectively located on two side surfaces of the core dielectric layer that
are opposite to each other, and the containing cavities extend from the lower surface and pass through the second copper foil
layer and the core dielectric layer to expose parts of the first copper foil layer;

forming an adhesive layer on inner walls of the containing cavities;
laminating the first base and the second base, so as to accommodate the metal bumps in the containing cavities, wherein the
metal bumps are fixed within the containing cavities through the adhesive layer;

removing the first base, wherein a bottom surface of each of the metal bumps substantially flushes with the lower surface
of the second base;

forming a plurality of blind via holes extending from the upper surface of the second base to the metal bumps;
forming a conductive material layer on the first copper foil layer and the second copper foil layer, wherein the conductive
material layer covers the first copper foil layer, the second copper foil layer and the bottom surfaces of the metal bumps,
and the conductive material layer fills the blind via holes to define a plurality of conductive through via holes; and

patterning the conductive material layer to form a first patterned metal layer and a second patterned metal layer, wherein
the first patterned metal layer is located on the first copper foil layer and connected with the conductive through via holes,
the second patterned metal layer is located on the second copper foil layer, and the first patterned metal layer and the second
patterned metal layer respectively expose parts of the two side surfaces of the core dielectric layer.

US Pat. No. 9,589,942

PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A package structure, comprising:
a first substrate,. comprising:
a core layer comprising a first surface and a second surface, a cavity, a third patterned metal layer and a fourth patterned
metal layer, the third patterned metal layer and the fourth patterned metal layer covering two opposite surfaces of the core
layer respectively, and the cavity penetrating the core layer;

a third semiconductor component disposed in the cavity;
a first stacked layer and a second stacked layer disposed on the two opposite surfaces of the core layer respectively, the
first stacked layer comprising a first dielectric layer and a first patterned metal layer, the second stacked layer comprising
a second dielectric layer and a second patterned metal layer, and the first dielectric layer and the second dielectric layer
jointly encapsulating the third semiconductor component and the core layer; and

a plurality of component conducting vias for electrically connecting the third semiconductor component to the first patterned
metal layer and the second patterned metal layer;

a patterned solder mask disposed on the first patterned metal layer and the second patterned metal layer and exposing at least
a part of the first patterned metal layer and the second patterned metal layer;

a plurality of first posts disposed on the exposed part of the first patterned metal layer and thermally coupled to the first
patterned metal layer;

a first semiconductor component disposed on the first surface, and the first semiconductor component electrically connecting
the first patterned metal layer and thermally coupled to the first posts; and

a second substrate, wherein two opposite ends of each of the first posts are connected to the first substrate and the second
substrate respectively, such that the first semiconductor component is located between the first substrate and the second
substrate and the first posts are thermally coupled to the second substrate.

US Pat. No. 9,761,515

SUBSTRATE STRUCTURE

Subtron Technology Co., L...

1. A substrate structure, comprising:
a dielectric layer comprising a first surface and a second surface opposite to the first surface, the first surface having
a plurality of recesses;

a metal foil disposed on the second surface;
a patterned metal layer disposed on the first surface, the patterned metal layer having a plurality of openings, the openings
respectively corresponding to and exposing the recesses;

a first patterned solder-resist layer filled in each of the recesses and corresponding to each of the openings, a top surface
of the first patterned solder-resist layer being substantially coplanar with a top surface of the patterned metal layer;

a release layer disposed between the first patterned solder-resist layer and the dielectric layer and between the patterned
metal layer and the dielectric layer; and

a second patterned solder-resist layer disposed on the first patterned solder-resist layer and in the openings of the patterned
metal layer, and covering a portion of the patterned metal layer.

US Pat. No. 9,668,351

PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A package carrier, comprising:
a carrier, having a connecting surface;
a releasable solder resist layer, disposed on the connecting surface of the carrier and completely covering the connecting
surface, wherein a material of the releasable solder resist layer comprises a thermal-curing solder resist material and a
photo-curing solder resist material, and the releasable solder resist layer is in a semi-cured state;

a substrate, having a upper surface and a lower surface opposite to each other; and
a first patterned solder resist layer, disposed on the lower surface of the substrate and exposing a portion of the lower
surface, wherein the carrier is temporarily bonded to the first patterned solder resist layer through the releasable solder
resist layer.

US Pat. No. 9,883,599

MANUFACTURING METHOD FOR MULTI-LAYER CIRCUIT BOARD HAVING CAVITY

Subtron Technology Co., L...

1. A manufacturing method of a multi-layer circuit board having a cavity, comprising:
providing a core board and forming a through hole that penetrates the core board, wherein the core board comprises a first
dielectric layer and two first conductive layers that are disposed on two opposite surfaces of the first dielectric layer
and conducted with each other;

forming two build-up structures, the step of forming each of the two build-up structures comprises:
providing at least one second conductive layer;
bonding at least one second dielectric layer to the at least one second conductive layer, and bonding a third conductive layer
to the at least one second dielectric layer; and

patterning the third conductive layer to form a stopper layer that exposes a portion of the at least one second dielectric
layer, wherein the at least one second conductive layer, the at least one second dielectric layer, and the stopper layer constitute
each of the two build-up structures;

bonding the two build-up structures to two opposite sides of the core board and each of the two build-up structures facing
the core board with the stopper layer to form the multi-layer circuit board, the two build-up structures cover the through
hole and the stopper layer corresponding to the through hole, wherein each of the two build-up structures comprises the stopper
layer, the at least one second dielectric layer and the at least one second conductive layer which are stacked in sequence
on the stopper layer; and

removing a portion of one of the two build-up structures corresponding to the through hole, such that the through hole communicates
with the removed portion of the one of the two build-up structures outside, to form the cavity.

US Pat. No. 9,693,468

PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package substrate, comprising:
providing a first copper layer and a first plating copper layer formed thereon, a first dielectric layer, a second copper
layer and a second plating copper layer formed thereon, a second dielectric layer, a third copper layer and a third plating
copper layer formed thereon, wherein the first dielectric layer is located between the first copper layer and the second copper
layer, the second dielectric layer is located between the second plating copper layer and the third copper layer, and edges
of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper
layer;

laminating the first copper layer, the first dielectric layer, the second copper layer, the second dielectric layer and the
third copper layer such that the first dielectric layer and the second dielectric layer completely encapsulate the edges of
the second copper layer and the edges of the second plating copper layer thereon so as to form a temporary carrier, and wherein
the edges of the first copper layer and the edges of the third copper layer are substantially aligned to each other;

forming two circuit structures on two opposite surfaces of the temporary carrier, wherein each of the circuit structures include
at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of
conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit
layers;

cutting the temporary carrier and the circuit structures so as to expose the edges of the second copper layer and the edges
of the second plating copper layer; and

separating the temporary carrier and the circuit structures along the exposed edges of the second copper layer and the exposed
edges of the second plating copper layer so as to form two package substrates independent from each other.

US Pat. No. 9,870,931

PACKAGE CARRIER AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, adapted to carry at least one heat generating element, and the manufacturing
method of the package carrier, comprising:
providing a substrate, wherein the substrate has an upper surface and a lower surface opposite to each other, and a through
hole connecting the upper surface and the lower surface;

disposing at least one heat conducting element inside the through hole of the substrate, wherein a thickness of the heat conducting
element is smaller than a thickness of the substrate, the heat conducting element is fixed in the through hole by an insulating
material and the insulating material is located between the heat conducting element and an inner wall of the through hole,
wherein the insulating material has a top surface and a bottom surface opposite to each other, the heat conducting element
has a first surface and a second surface opposite to each other, the top surface of the insulating material and the upper
surface of the substrate are approximately coplanar, and the bottom surface of the insulating material, the lower surface
of the substrate, and the second surface of the heat conducting element are approximately coplanar;

forming a first patterned circuit layer and a second patterned circuit layer, wherein the first patterned circuit layer is
at least formed on the upper surface of the substrate and the top surface of the insulating material and exposes portions
of the substrate and the top surface, and the second patterned circuit layer is formed on the lower surface of the substrate
and the bottom surface of the insulating material, and exposes portions of the substrate and the bottom surface; and

forming at least one cavity having a depth and extending from the top surface of the insulating material to the heat conducting
element, wherein the cavity exposes a portion of the first surface of the heat conducting element, and the first surface of
the heat conducting element is lower than the top surface of the insulating material.

US Pat. No. 9,933,149

ILLUMINATION APPARATUS

Subtron Technology Co., L...

1. An illumination apparatus, comprising:a thermal conductivity substrate having an upper surface;
a package carrier disposed on the upper surface of the thermal conductivity substrate and having an opening, the opening exposing a portion of the upper surface of the thermal conductivity substrate, wherein the package carrier comprises at least one insulating layer, a plurality of conductive layers, and a solder mask layer, the insulating layer and the conductive layers are alternatively stacked up, the solder mask layer exposes a part of one conductive layer to define at least one bonding pad;
at least one light emitting element disposed on the upper surface of the thermal conductivity substrate exposed by the opening of the package carrier;
at least one bonding wire electrically connecting the light emitting element to the package carrier, wherein a terminal of the bonding wire is disposed on the bonding pad;
a light transmission cap disposed above the thermal conductivity substrate, wherein the light emitting element and the package carrier are located between the light transmission cap and the thermal conductivity substrate;
a first seal ring disposed between the light transmission cap and the package carrier; and
a second seal ring disposed between the package carrier and the thermal conductivity substrate, wherein the thermal conductivity substrate, the light transmission cap, the first seal ring, the second seal ring and the package carrier completely seal the light emitting element.

US Pat. No. 9,883,594

SUBSTRATE STRUCTURE FOR PACKAGING CHIP

Subtron Technology Co., L...

1. A manufacturing method of a substrate structure, comprising:
providing a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to
the packaging region and surrounds the packaging region;

forming a plurality of through holes in the packaging region;
providing a carrier, wherein the carrier comprises a release layer, a dielectric layer, and a metal layer, the dielectric
layer being disposed between the release layer and the metal layer;

laminating the substrate to the release layer of the carrier, such that the release layer and the dielectric layer are filled
into the through holes to separably attach the substrate to the carrier;

packaging a chip on the packaging region of the substrate, wherein the chip directly contacts the release layer filled into
the through holes; and

separating the chip and the substrate from the release film and the carrier to expose the back surface of the chip after packaging
the chip on the substrate.

US Pat. No. 9,961,784

MANUFACTURING METHOD OF CIRCUIT SUBSTRATE

Subtron Technology Co., L...

1. A method for manufacturing a circuit substrate, comprising:bonding peripheries of two metal layers directly to form a sealed area;
forming at least a through hole passing through the sealed area, and wherein an area of the through hole is smaller than an area of the sealed area;
forming two insulating layers on the two metal layers, wherein an area of each of the two insulating layers is larger than an area of each of the two metal layers;
forming two conductive layers on the two insulating layers;
laminating the two insulating layers and the two conductive layers and the two metal layers bonded with each other being embedded between the two insulating layers, wherein portions of the two insulating layers fill in the through hole when the two insulating layers are laminated;
removing a part of the two insulating layers and a part of the two conductive layers to form a plurality of blind holes exposing the two metal layers;
forming a conductive material in the blind holes and on remaining portions of the two conductive layer; and
removing the bonded peripheries of the two metal layers to form two separated circuit substrates.

US Pat. No. 10,123,413

PACKAGE SUBSTRATE AND MANUFACTURING METHOD THEREOF

Subtron Technology Co., L...

1. A temporary package substrate, comprising:a first copper layer;
a second copper layer;
a third copper layer, wherein the second copper layer is located between the first copper layer and the third copper layer, and edges of the second copper layer are retracted a distance compared to edges of the first copper layer and edges of the third copper layer;
a first plating copper layer, disposed on the first copper layer, and directly covering the first copper layer;
a second plating copper layer, disposed on the second copper layer, and directly covering the second copper layer;
a third plating copper layer, disposed on the third copper layer, and directly covering the third copper layer;
a first dielectric layer, disposed between the first copper layer and the second copper layer;
a second dielectric layer, disposed between the second plating copper layer and the third copper layer, wherein the first dielectric layer and the second dielectric layer completely encapsulate the edges of the second copper layer and the edges of the second plating copper layer; and
two circuit structures, disposed on two opposite surfaces of the first copper layer and the third copper layer, and the first copper layer and the third copper layer being located between the two circuit structures, wherein each of the circuit structures includes at least two patterned circuit layers, an insulation layer located between the patterned circuit layers, and a plurality of conductive through hole structures penetrating the insulation layer and electrically connected with the patterned circuit layers.

US Pat. No. 10,177,067

MANUFACTURING METHOD OF PACKAGE CARRIER

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, the manufacturing method comprising:providing a substrate, the substrate comprising a core layer, a first conductive layer, and a second conductive layer, the first conductive layer and the second conductive layer being respectively disposed on two opposite sides of the core layer, the core layer having a first thickness;
forming a heat conducting channel passing through the substrate;
forming an adhesion layer on the second conductive layer, the adhesion layer covering a side of the heat conducting channel;
placing a heat conducting element and a buffer layer connected to the heat conducting element into the heat conducting channel, wherein the buffer layer and the adhesion layer are in contact with each other, a gap is between an inner side surface of the core layer in the heat conducting channel and the heat conducting element and between the inner side surface of the core layer in the heat conducting channel and the buffer layer, the heat conducting element having a second thickness less than the first thickness;
filling the gap with a first insulation material surrounding the heat conducting element and the buffer layer;
removing the adhesion layer and the buffer layer, the heat conducting element and the first insulation material defining a cavity exposing the heat conducting element; and
patterning the first conductive layer and the second conductive layer to respectively form a first patterned circuit layer and a second patterned circuit layer.

US Pat. No. 10,319,610

PACKAGE CARRIER

Subtron Technology Co., L...

1. A package carrier, adapted to carry at least one heat generating element, and the package carrier comprising:a substrate, having an upper surface and a lower surface opposite to each other, and a through hole connecting the upper surface and the lower surface;
at least one heat conducting element, disposed inside the through hole and having a first surface and a second surface opposite to each other, wherein a thickness of the heat conducting element is smaller than a thickness of the substrate;
an insulating material, located between the heat conducting element and an inner wall of the through hole, wherein the heat conducting element is fixed in the through hole by the insulating material, the insulating material has a top surface and a bottom surface opposite to each other, the top surface of the insulating material and the upper surface of the substrate are approximately coplanar, and the bottom surface of the insulating material, the lower surface of the substrate and the second surface of the heat conducting element are approximately coplanar, and the insulating material and the heat conducting element define at least one cavity having a depth and extending from the top surface of the insulating material to the heat conducting element and the cavity exposes a portion of the first surface of the heat conducting element, and the first surface of the heat conducting element is lower than the top surface of the insulating material;
a first patterned circuit layer, disposed on the upper surface of the substrate and the top surface of the insulating material, and exposing portions of the substrate and the top surface; and
a second patterned circuit layer, disposed on the lower surface of the substrate and the bottom surface of the insulating material, and exposing portions of the substrate and the bottom surface.

US Pat. No. 10,297,517

MANUFACTURING METHOD OF PACKAGE CARRIER

Subtron Technology Co., L...

1. A manufacturing method of a package carrier, comprising:providing a substrate having a through hole, wherein a profile of the through hole from top view is a first rounded rectangular;
disposing a heat conducting slug inside the through hole of the substrate, wherein the heat conducting slug and an inner wall of the through hole are separated with a gap, and a profile of the heat conducting slug from top view is a second rounded rectangular;
filling the through hole of the substrate with an insulating material so as to fix the heat conducting slug in the through hole via the insulating material;
forming a conductive through hole structure, a first patterned circuit layer and a second patterned circuit layer, wherein the first patterned circuit layer and the second patterned circuit layer are respectively formed on two opposite sides of the substrate and expose a portion of the substrate, the conductive through hole structure penetrates the substrate and connects a portion of the first patterned circuit layer and a portion of the second patterned circuit layer, and
performing a grinding process to remove a portion of the substrate, a portion of the insulating material, and a portion of the heat conducting slug after filling the through hole of the substrate with the insulating material and before forming the conductive through hole structure, the first patterned circuit layer, and the second patterned circuit layer, so that a top surface and a bottom surface opposite to each other of the heat conducting slug are substantially coplanar with a first surface and a second surface opposite to each other of the insulating material respectively, and substantially coplanar with an upper surface and a lower surface opposite to each other of the substrate respectively.

US Pat. No. 10,798,822

METHOD OF MANUFACTURING A COMPONENT EMBEDDED PACKAGE CARRIER

Subtron Technology Co., L...

1. A manufacturing method of a component embedded package carrier, comprising:forming a core layer, the core layer comprising a dielectric layer, an opening of the core layer, a first patterned conductive layer, a second patterned conductive layer and a plurality of conductive through hole structures, the dielectric layer having an upper surface and a lower surface opposite each other, the opening passing through the dielectric layer, the first patterned conductive layer being located on the upper surface, the second patterned conductive layer being located on the lower surface, and the conductive through hole structures passing through the dielectric layer and connecting the first patterned conductive layer with the second patterned conductive layer, wherein forming the core layer comprises:
providing the dielectric layer, a first copper foil layer and a second copper foil layer, the first copper foil layer being disposed on the upper surface of the dielectric layer, and the second copper foil layer being disposed on the lower surface of the dielectric layer;
forming a plurality of through holes, the through holes passing through the dielectric layer, the first copper foil layer and the second copper foil layer;
forming a first conductive material layer on the first copper foil layer and the second copper foil layer, wherein the first conductive material layer fills the through holes and entirely covers the first copper foil layer and the second copper foil layer;
patterning the first conductive material layer, the first copper foil layer and the second copper foil layer, thereby defining the conductive through hole structures, the first patterned conductive layer and the second patterned conductive layer; and
forming the opening of the core layer, after patterning the first conductive material layer, the first copper foil layer and the second copper foil layer;
disposing at least one electronic component inside the opening of the core layer;
laminating a first insulating layer and a first circuit layer located on the first insulating layer onto the first patterned conductive layer, wherein the first insulating layer covers the first patterned conductive layer and the upper surface of the dielectric layer and is filled into the opening of the core layer;
laminating a second insulating layer and a second circuit layer located on the second insulating layer onto the second patterned conductive layer, wherein the second insulating layer covers the second patterned conductive layer and the lower surface of the dielectric layer and is filled into the opening of the core layer, and the first insulating layer and the second insulating layer completely fill the opening of the core layer and completely encapsulate the electronic component;
forming a plurality of conductive blind via structures, a third patterned conductive layer and a fourth patterned conductive layer, the third patterned conductive layer being located on the first insulating layer and comprising the first circuit layer, the fourth patterned conductive layer being located on the second insulating layer and comprising the second circuit layer, and the conductive blind via structures connecting the third patterned conductive layer with the conductive through hole structures, the fourth patterned conductive layer with the conductive through hole structures, the third patterned conductive layer with the electronic component and the fourth patterned conductive layer with the electronic component, wherein forming the conductive blind via structures, the third patterned conductive layer and the fourth patterned conductive layer comprises:
forming a plurality of blind vias, the blind vias extending from the first circuit layer to the first patterned conductive layer and the electronic component and extending from the second circuit layer to the second patterned conductive layer and the electronic component;
forming a second conductive material layer on the first circuit layer and the second circuit layer, wherein the second conductive material layer fills the blind vias and entirely covers the first circuit layer and the second circuit layer; and
patterning the second conductive material layer, the first circuit layer and the second circuit layer, thereby defining the conductive blind via structures, the third patterned conductive layer and the fourth patterned conductive layer; and
forming a first protecting layer and a second protecting layer, the first protecting layer having a first roughness surface and covering the third patterned conductive layer and a portion of the first insulating layer, and the second protecting layer having a second roughness surface and covering the fourth patterned conductive layer and a portion of the second insulating layer.