US Pat. No. 9,465,394

LOW-DROP REGULATOR APPARATUS AND BUFFER STAGE CIRCUIT HAVING HIGHER VOLTAGE TRANSITION RATE

Silicon Motion Inc., Hsi...

1. A low-drop (LDO) regulator apparatus, comprising:
an operational amplifier, for receiving a reference voltage and a feedback voltage to generate a first voltage signal;
a buffer stage circuit, coupled to a power transistor, for buffering the first voltage signal to generate a second voltage
signal, the buffer stage circuit comprises:

a first switch, for receiving the first voltage signal to decide whether to enable an operation of a current mirror;
the current mirror, coupled to the first switch, for mirroring and generating the mirrored current according to the first
voltage signal; and

a second switch, coupled to an output terminal of the current mirror, for providing the second voltage signal to the power
transistor to turn off the power transistor; and

the power transistor, coupled to the buffer stage circuit, for generating an output voltage according to the second voltage
signal, the output voltage being proportional to the feedback voltage;

wherein the buffer stage circuit is arranged to determine whether to mirror and generate a mirrored current according to the
first voltage signal, and to generate the second voltage signal for providing the second voltage signal to the power transistor
to control the power transistor to switch to an on state or an off state according to the first voltage signal in response
to that when the mirrored current is generated; when the second switch is turned on, the current mirror is disabled, and the
second switch is arranged to provide the second voltage signal to the power transistor to turn off the power transistor; and,
when the second switch is turned off, the current mirror is enabled and is arranged to mirror and generate the mirrored current
according to the first voltage signal so as to generate the second voltage signal to turn on the power transistor.

US Pat. No. 9,483,212

NON-VOLATILE MEMORY DEVICES AND CONTROL METHODS THEREFOR

SILICON MOTION, INC., Jh...

1. A non-volatile memory device comprising:
a non-volatile memory divided into a plurality of physical blocks, wherein each physical block is divided into a plurality
of physical pages; and

a connection interface connected to a host; and
a controller connected to the connection interface,
wherein when the controller performs a block-reconfiguration operation, the controller re-adjusts a position where data is
disposed in the physical blocks to obtain a usable physical block, and

wherein movement of a first portion of the data related to the block-reconfiguration operation is performed when the controller
operates an initial operation, and movement of a second portion of the data related to the block-reconfiguration operation
is performed when the controller processes a read command from the host.

US Pat. No. 9,104,546

METHOD FOR PERFORMING BLOCK MANAGEMENT USING DYNAMIC THRESHOLD, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF

Silicon Motion Inc., Jhu...

1. A method for performing block management, the method being applied to a controller of a Flash memory, the Flash memory
comprising a plurality of blocks, the method comprising:
adjusting a dynamic threshold according to at least one condition; and
comparing a valid or invalid page count of a specific block of the plurality of blocks with the dynamic threshold to determine
whether to erase the specific block.

US Pat. No. 9,563,249

DATA STORAGE DEVICE AND POWER-INTERRUPTION DETECTION METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of pages, wherein each of the pages comprises a spare area, and each of the spare areas
stores a power-off-reset count; and

a controller device, determining whether a first page of the pages has been through a power-interruption event by comparing
two of the power-off-reset counts stored in the spare areas.

US Pat. No. 9,116,797

FLASH MEMORY DEVICES INCLUDING RESERVE UNITS OPERATING IN ABNORMAL SITUATIONS AND CONTROLLING METHODS THEREOF

SILICON MOTION, INC., Jh...

1. A flash memory controller comprising:
a read/write unit, coupled to a flash memory, performing a write command or a read command;
a state machine for determining a state of the flash memory controller;
a processing unit, coupled to the read/write unit and the state machine, controlling the read/write unit; and
a reserve unit, coupled to a first data line, a second data line, and the read/write unit,
wherein when the flash memory controller is operating abnormally, the reserve unit receives an external signal via the first
data line and the second data line and controls the read/write unit according to the external signal,

wherein when the flash memory controller is operating normally, the state machine outputs a sleep signal to the reserve unit,
wherein when the reserve unit receives the sleep signal, the reserve unit stops operating.

US Pat. No. 9,417,958

FLASH MEMORY CONTROL METHOD, CONTROLLER AND ELECTRONIC APPARATUS

Silicon Motion Inc., Hsi...

1. A memory control method for controlling a flash memory, the flash memory comprising a first memory component and a second
memory component, the second memory component comprising a plurality of blocks, each block comprising a plurality of data
pages, the memory control method comprising:
writing original data to the first memory component;
reading from the first memory component to obtain input data, the input data comprising a plurality of input data rows;
dividing the plurality of input data rows into a plurality of data groups;
writing each of the input data row corresponding to each of the data groups into one of the data pages in the second memory
component;

writing a parity row corresponding to each of the data groups to one corresponding data page that is distinct from a data
page storing the written input data row in the second memory component, wherein a number of the input data rows corresponding
to each of the data groups is smaller than a number of the data pages for each of the blocks; and

updating the parity row of corresponding data group according to accumulated calculation of content of the input data row
each time before writing an input data row to the second memory component.

US Pat. No. 9,128,643

METHOD AND APPARATUS PERFORMING CLOCK EXTRACTION UTILIZING EDGE ANALYSIS UPON A TRAINING SEQUENCE EQUALIZATION PATTERN

Silicon Motion Inc., Jhu...

1. A method applied to an electronic device for performing clock extraction, comprising:
performing edge analysis upon a training sequence equalization (TSEQ) pattern carried by a set of received signals that are
received via a Universal Serial Bus (USB) port of the electronic device, and accordingly obtain a plurality of estimated edge
numbers;

generating a plurality of analysis results according to the plurality of estimated edge numbers and a predetermined threshold,
wherein the plurality of estimated edge numbers are derived by performing edge number estimation upon the TSEQ pattern corresponding
to a plurality of time intervals respectively; and

performing frequency calibration on a frequency of an output clock of an oscillator according to the plurality of analysis
results, so as to utilize the output clock to act as a reference clock after the frequency calibration is completed.

US Pat. No. 9,268,638

FLASH MEMORY CONTROL METHOD, CONTROLLER AND ELECTRONIC APPARATUS

Silicon Motion Inc., Jhu...

1. A memory control method for controlling a flash memory, the flash memory comprising a memory component, the memory component
comprising a plurality of blocks, each block comprising a plurality of data pages, the memory control method comprising:
reading a data group setting, the data group setting indicating a number of plurality of data rows included in a data group,
each data row being stored in one corresponding data page, and a number of a plurality of input data rows of data groups is
smaller than a number of plurality of data pages included in each block;

reading the plurality of data rows corresponding to one of the data groups and a parity row;
using the parity row to perform error detection and correction on the plurality of data rows.

US Pat. No. 9,256,529

FLASH MEMORY CONTROLLER

Silicon Motion Inc., Jhu...

1. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a read and write
circuit, a first data block, and a second data block, the flash memory controller comprising:
a communication interface for receiving a first data and a second data; and
a processing circuit, coupled with the communication interface and the flash memory module, for dynamically controlling a
data writing mode of the flash memory module according to an amount of stored data in the flash memory module;

wherein if the amount of stored data in the flash memory module is less than a first threshold when the communication interface
receives the first data, the processing circuit controls the flash memory module so that the first data is written into the
first data block under an one-bit-per-cell mode, and if the amount of stored data in the flash memory module is greater than
the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory
module so that the second data is written into the second data block under a two-bit-per-cell mode.

US Pat. No. 9,116,792

DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, comprising a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of
spare blocks, and the data block pool comprises a plurality of data blocks; and

a controller, determining a minimum erase count from the erase counts of the spare blocks and the data blocks, adding a second
difference to the minimum erase count to obtain a jail threshold, comparing the erase counts of the spare blocks with the
jail threshold to obtain a plurality of jail blocks with the erase counts greater than the jail threshold, confining the jail
blocks to a jail pool, and avoiding using the jail blocks as a current data block to be written with data by not retrieving
the jail blocks with the erase counts greater than the jail threshold for storing data;

wherein the controller adds a first difference to the minimum erase count to obtain a hot threshold, compares the erase counts
of the spare blocks with the hot threshold to obtain a plurality of hot blocks with the erase counts greater than the hot
threshold, counts a number of the hot blocks to obtain a hot block number, and performs a wear-leveling process between the
data blocks of the data block pool and the hot blocks when the hot block count is greater than zero;

wherein the second difference is greater than the first difference.

US Pat. No. 9,437,328

APPARATUS AND METHOD FOR APPLYING AT-SPEED FUNCTIONAL TEST WITH LOWER-SPEED TESTER

Silicon Motion Inc., Hsi...

1. A method for testing a device under test, comprising:
generating at least one test pattern;
feeding the at least one test pattern transmitted at a first clock rate into the device under test;
sampling the at least one test pattern by using a second clock rate and accordingly generate at least one sampled test pattern,
wherein the second clock rate is higher than the first clock rate;

performing a designated function upon the at least one sampled test pattern and accordingly generating at least one functional
test result;

outputting the at least one functional test result;
wherein the sampling step comprises:
sampling the at least one test pattern by using the second clock rate to generate a plurality of duplicated test patterns
served as the at least one sampled test pattern.

US Pat. No. 9,384,125

METHOD FOR ACCESSING FLASH MEMORY HAVING PAGES USED FOR DATA BACKUP AND ASSOCIATED MEMORY DEVICE

Silicon Motion Inc., Jhu...

1. A method for accessing a flash memory, wherein a number of entire pages of a block of the flash memory is (2N+M) and is not an integer power of two, last M pages are arranged for backing up data of a portion of first (2N) pages, and both of N and M are positive integers, the method comprising:
reading data of at least one page from the portion of the first (2N) pages of the block; and

selectively reading page(s) arranged for backing up the at least one page from the last M pages of the block to act as data
of the at least one page;

wherein the step of selectively reading the page(s) arranged for backing up the at least one page from the last M pages comprises:
determining whether required time for reading data of the at least one page exceeds a predetermined time period; and
when it is determined that the required time for reading the data of the at least one page exceeds the predetermined time
period, reading the page(s) arranged for backing up the at least one page from the last M pages to act as the data of the
at least one page.

US Pat. No. 9,261,892

LOW-DROPOUT VOLTAGE REGULATOR APPARATUS CAPABLE OF ADAPTIVELY ADJUSTING CURRENT PASSING THROUGH OUTPUT TRANSISTOR TO REDUCE TRANSIENT RESPONSE TIME AND RELATED METHOD THEREOF

Silicon Motion Inc., Jhu...

1. A low-dropout voltage regulator apparatus, comprising:
a voltage source circuit, arranged to generate a reference voltage signal and at least one threshold voltage signal;
an error amplifier, coupled to the voltage source circuit, the error amplifier arranged to receive the reference voltage signal
and a feedback voltage signal to generate an output control signal;

an output transistor, coupled to the error amplifier, the output transistor arranged to receive the output control signal
and provide an output current for the output terminal according to the output control signal;

a resistor-capacitor circuit, coupled to the error amplifier and the output transistor, the resistor-capacitor circuit arranged
to generate the feedback voltage signal by performing voltage dividing according to a voltage corresponding to the output
current;

a detection circuit, coupled to the voltage source circuit, the detection circuit arranged to receive the at least one threshold
voltage signal and an output voltage at the output terminal, and compare the at least one threshold voltage signal with the
output voltage to generate at least one control voltage signal; and

a current adjusting circuit, coupled to the output terminal, the detection circuit and the error amplifier, the current adjusting
circuit arranged to adjust the output control signal generated by the error amplifier and adaptively adjust a current passing
through the output transistor according to the at least one control voltage signal, so as to decrease a transient response
time of the low-dropout voltage regulator.

US Pat. No. 9,141,533

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD FOR PERFORMING GARBAGE COLLECTION

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a Flash memory; and
a controller, controlling the Flash memory in accordance with firmware, wherein when the firmware is available for at least
a predetermined time period without being requested by a host, the controller, driven according to the firmware, performs
a garbage-collection operation on the Flash memory without a request from the host,

wherein:
the Flash memory provides a plurality of blocks for data storage, each block including a plurality of pages;
when the firmware is available for at least the predetermined time period without being requested by the host, the controller
samples a plurality of low-efficiency blocks from the plurality of blocks in the Flash memory, the plurality of low-efficiency
blocks having a smaller amount of valid pages in comparison to the remaining blocks in the Flash memory;

the controller classifies the Flash memory in accordance with the low-efficiency blocks and, when classifying the Flash memory
as dirty, the controller moves valid data contained in the low-efficiency blocks to other blocks;

the controller classifies the Flash memory as clean when average number of valid pages in the low-efficiency blocks is higher
than a threshold number, otherwise, the controller classifies the Flash memory as dirty; and

when the Flash memory is classified as clean and no command requiring firmware operations is transmitted from the host, or
when valid data are all removed from the low-efficiency blocks and no command requiring firmware operations is transmitted
from the host, the controller increases the threshold number and observes a new set of low-efficiency blocks, reclassifies
the Flash memory in accordance with the new set of low-efficiency blocks and the threshold number that has been increased
and, when the Flash memory is reclassified as dirty, the controller moves valid data contained in the new set of low-efficiency
blocks to other blocks.

US Pat. No. 9,436,599

FLASH STORAGE DEVICE AND METHOD INCLUDING SEPARATING WRITE DATA TO CORRESPOND TO PLURAL CHANNELS AND ARRANGING THE DATA IN A SET OF CACHE SPACES

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory, comprising a plurality of blocks each with a plurality of pages, wherein the blocks are further grouped to
be accessed by a plurality of channels separately; and

a controller coupled to the FLASH memory, comprising:
a computing unit;
a read only memory, loaded with programs to be executed by the computing unit to build firmware for the data storage device;
and

a random access memory, allocated according to the computing unit executing the firmware to provide a first set of cache spaces,
wherein different cache spaces within the first set of cache spaces correspond to different ones of the plurality of channels,
respectively, and every channel corresponds to one cache space of the first set of cache spaces,

wherein:
the computing unit separates write data issued from a host to correspond to the plurality of channels and, after data arrangement
that combines non-refreshed data with write data in the first set of cache spaces for every channel is completed, the computing
unit writes data arranged in the first set of cache spaces for every channel to the FLASH memory via the plurality of channels;

the computing unit further allocates the random access memory to provide a second set of cache spaces, and different cache
spaces within the second set of cache spaces correspond to the different ones of the plurality of channels, respectively and
every channel corresponds to one cache space of the second set of cache spaces; and

when writing the data arranged in the first set of cache spaces for every channel to the FLASH memory, the computing unit
uses the second set of cache spaces to perform data arrangement for the write data issued from the host.

US Pat. No. 9,230,673

METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY

Silicon Motion Inc., Jhu...

7. A memory controller for reading data stored in a flash memory, comprising:
a receiving circuit, arranged for obtaining a plurality of bit sequences read from a plurality of memory cells of the flash
memory, respectively; and

a control logic, coupled to the receiving circuit, the control logic arranged for performing a plurality of read operations
upon each of the memory cells, and determining readout information of the memory cells according to binary digit distribution
characteristics of the bit sequences, wherein the read operations utilizes a plurality of control gate voltages to read bits
from each of the memory cells as one of the bit sequences.

US Pat. No. 9,195,539

METHOD FOR READING DATA FROM BLOCK OF FLASH MEMORY AND ASSOCIATED MEMORY DEVICE

Silicon Motion Inc., Hsi...

1. A method for reading data from a block of a flash memory, wherein the block comprises a plurality of pages and at least
one parity page, each of the pages comprises a plurality of sectors used for storing data and associated row parities, and
each of the sectors of the parity page is used to store a column parity which is generated in accordance with a sector of
each of the pages; the method comprising:
reading data from a specific page of the pages;
decoding the data of the specific page; and
when a specific sector of the specific page fails to be decoded successfully, sequentially reading all original data of the
pages and the parity page, and performing error correction upon the specific sector according to at least a portion of the
original data of the pages and the parity page corresponding to the specific sector, comprising:

decoding the sectors of the pages that correspond to the specific sector, and generating a corresponding decoded data when
decoding of the sectors is successful;

recording the specific sector with decoding failure and its original data into a storage unit;
decoding the corresponding decoded data of the sectors or the original data, along with a column parity of the at least one
parity page corresponding to the specific sector, to generate a decoding result; and

using the decoding result to perform error correction upon the specific sector.

US Pat. No. 9,405,619

METHOD FOR PERFORMING ERROR CORRECTION, ASSOCIATED MEMORY APPARATUS AND ASSOCIATED CONTROLLER THEREOF

Silicon Motion Inc., Hsi...

1. A method for use in a controller of a memory apparatus for performing error correction, the memory apparatus having a flash
memory, the method comprising:
performing a read operation at a specific physical address of the flash memory;
after an uncorrectable error of the read operation is detected, performing a first re-read operation at the specific physical
address of the flash memory by configuring a first retry parameter to the flash memory to obtain first data corresponding
to the first retry parameter and temporarily storing the first data into a volatile memory and performing a first hard decoding
operation on the first data; and

after decoding failure of the first hard decoding operation is detected, at least according to the first data read from the
volatile memory, performing a soft decoding operation to perform error correction corresponding to the specific physical address.

US Pat. No. 9,405,620

DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory; and
a controller, configured to perform a first error correction on at least one first data sector of a first page of the flash
memory when a predetermined condition is satisfied, obtain a data-sector read voltage of the first data sector through the
first error correction, retrieve data of a first meta-data sector of the first page by the data-sector read voltage, and perform
a second error correction on the retrieved data of the first meta-data sector read by the data-sector read voltage.

US Pat. No. 9,335,354

PHASE DETECTOR WITH METASTABLE PREVENTION STAGE

Silicon Motion Inc., Tai...

10. A phase detector, arranged for comparing a phase of a first clock, signal with a phase of a second clock signal, comprising:
a phase detection stage, for receiving the first clock signal and the second clock signal, and outputting a phase comparison
result according to the phase of the first clock signal and the phase of the second clock signal; and

a metastable prevention stage, for receiving the phase comparison result, and outputting a stable phase comparison result
according to the phase comparison result;

wherein the stable phase comparison result comprises a first stable comparison signal and a second stable comparison signal,
and the phase detector further comprises:

a synchronization stage, for synchronizing the first stable comparison signal with the second stable comparison signal, and
comprising:

a flip-flop, having a data input terminal, a clock input terminal and a data output terminal, wherein the data input terminal
receives the second stable comparison signal, the clock input signal receives the first clock signal, and the data output
terminal outputs a second synchronized stable comparison signal which is synchronized with the first stable comparison signal.

US Pat. No. 9,286,972

METHOD, MEMORY CONTROLLER AND SYSTEM FOR READING DATA STORED IN FLASH MEMORY

Silicon Motion, Inc., Jh...

1. A method for reading data stored in a flash memory, the method comprises:
controlling the flash memory to perform a read operation upon a first page of the flash memory;
obtaining a first codeword of the first page;
obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping
rule;

performing an error correction operation according to the first set of LLR mapping values;
obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction
operation performed according to the first set of LLR mapping values indicates that a first sector of the first page is uncorrectable
and a second sector neighboring to the first sector is correctable, wherein the second LLR mapping rule is obtained by gathering
a statistics feature of a second codeword of the flash memory and correct data of the flash memory, a statistics feature of
a part of the first codeword and correct data of the part of the first codeword, and a statistics feature of the second codeword
of the second sector and the correct data of the second sector; and

performing the error correction operation according to the second set of LLR mapping values.

US Pat. No. 9,454,430

METHOD FOR CONTROLLING MEMORY APPARATUS, AND ASSOCIATED MEMORY APPARATUS AND CONTROLLER THEREOF

Silicon Motion Inc., Hsi...

1. A method for controlling a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element
each comprising a plurality of blocks, the method applied to a controller in the memory apparatus, the controller arranged
to control the at least one non-volatile memory element, the method comprising following steps:
reading encoded data of a second set of error correction configuring parameters from a system block of a specific non-volatile
memory element within the at least one non-volatile memory element, and utilizing a low-density parity-check (LDPC) engine
in the controller to decode the encoded data to obtain the second set of error correction configuring parameters, wherein
the LDPC engine stores a first set of error correction configuring parameters, and during decoding the encoded data, the LDPC
engine performs decoding corresponding to a first LDPC characteristic matrix based on the first set of error correction configuring
parameters; and

storing the second set of error correction configuring parameters obtained by decoding the encoded data into a random access
memory (RAM) in the LDPC engine, and controlling the LDPC engine to perform operations corresponding to a second LDPC characteristic
matrix based on the second set of error correction configuring parameters in the RAM, in order to make the LDPC engine be
equipped with encoding and decoding capabilities corresponding to the second LDPC characteristic matrix, for allowing the
controller to access data in the at least one non-volatile memory element;

wherein the first LDPC characteristic matrix comprises a plurality of sub-matrices, and each of the plurality of sub-matrices
of the first LDPC characteristic matrix is a square matrix selected from a predetermined set;

the second LDPC characteristic matrix comprises a plurality of sub-matrices, and each of the plurality of sub-matrices of
the second LDPC characteristic matrix is a square matrix selected from the predetermined set;

a size of any sub-matrix within the plurality of sub-matrices of the second LDPC characteristic matrix is equal to a size
of any sub-matrix within the plurality of sub-matrices of the first LDPC characteristic matrix; and

the predetermined set comprises a zero matrix, an identity matrix, and at least one cyclic-shifted matrix of the identity
matrix, wherein any cyclic-shifted matrix within the at least one cyclic-shifted matrix is obtained by cyclically shifting
all column vectors in the identity matrix, or by cyclically shifting all row vectors in the identity matrix.

US Pat. No. 9,411,681

METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY

Silicon Motion Inc., Hsi...

7. A memory controller for reading data stored in a flash memory, comprising:
a receiving circuit, arranged for obtaining a plurality of bit sequences read from a plurality of memory cells of the flash
memory, respectively;

a control logic, coupled to the receiving circuit, the control logic arranged for performing a plurality of read operations
upon each of the memory cells; and

an error correction code (ECC) circuit, coupled to the control logic, for performing an error correction code (ECC) operation
upon the bit sequences to determine whether the bit sequences have uncorrectable error bits;

wherein when the bit sequences have uncorrectable error bits, the control logic updates at least one of the bit sequences,
and determines a readout information of the memory cells according updated bit sequence(s) and non-updated bit sequence(s)
of the bit sequences.

US Pat. No. 9,535,444

DIFFERENTIAL OPERATIONAL AMPLIFIER AND BANDGAP REFERENCE VOLTAGE GENERATING CIRCUIT

Silicon Motion Inc., Hsi...

1. A differential operational amplifier, comprising:
a voltage adjusting module, coupled between a first predetermined voltage source and a second predetermined voltage source,
for adjusting a first voltage via a first voltage adjusting value to generate a first adjusted voltage, and for adjusting
a second voltage via a second voltage adjusting value to generate a second adjusted voltage, wherein the first voltage adjusting
value and the second voltage adjusting value change corresponding to a temperature; and

a differential signal computing module, coupled between the first predetermined voltage source and the second predetermined
voltage source, for generating an output voltage according the first adjusted voltage and the second adjusted voltage;

wherein the voltage adjusting module comprises:
a first transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving
the first voltage, a second terminal outputting the first adjusted voltage, wherein the first voltage adjusting value is a
voltage difference between the control terminal of the first transistor and the second terminal of the first transistor; and

a second transistor, comprising: a first terminal coupled to the first predetermined voltage source, a control terminal receiving
the second voltage, a second terminal outputting the second adjusted voltage, wherein the first voltage adjusting value is
a voltage difference between the control terminal of the first transistor and the second terminal of the first transistor.

US Pat. No. 9,489,143

METHOD FOR ACCESSING FLASH MEMORY AND ASSOCIATED CONTROLLER AND MEMORY DEVICE

Silicon Motion Inc., Hsi...

1. A method for accessing a flash memory, wherein the flash memory is a Triple-Level Cell flash memory and each word line
of the flash memory constitutes a least significant bit (LSB) page, a central significant bit (CSB) page and a most significant
bit (MSB) page, each storage unit of each word line of the flash memory is implemented by a floating-gate transistor, and
each storage unit supports at least eight write voltage levels, the method comprising:
generating dummy data according to data of a first page and a second page corresponding to a specific word line of the flash
memory, wherein the dummy data is going to be written in a third page corresponding to the specific word line, wherein the
first page is one of the LSB page, the CSB page and the MSB page corresponding to the specific word line, the second page
is another one of the LSB page, the CSB page and the MSB page corresponding to the specific word line, and the third page
is the other one of the LSB page, the CSB page and the MSB page corresponding to the specific word line; and

writing the data and the dummy data into the flash memory;
wherein the step of generating the dummy data according to the data of the first page and the second page corresponding to
the specific word line of the flash memory comprising:

for any storage unit of the specific word line, determining a bit value corresponding to the third page according to a combination
of bits of the first page and the second page.

US Pat. No. 9,274,893

DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, capable of operating in a SLC mode and a non-SLC mode; and
a controller, configured to perform a first read operation to read a page corresponding to a first word line of the flash
memory in the SLC mode according to a read command of a host, and perform an adjustable read operation when data read by the
first read operation cannot be recovered by coding, wherein the controller is further configured to enable the flash memory
to operate in the non-SLC mode in the adjustable read operation, and write logic 1 into a most-significant-bit page corresponding
to the first word line in the non-SLC mode to adjust voltage distribution of the first page.

US Pat. No. 9,470,714

TESTING APPARATUS FOR FLASH MEMORY CHIP

SILICON MOTION, INC., Jh...

1. A testing apparatus for testing a first flash memory chip, the testing apparatus comprising:
an interface printed circuit board (PCB);
a separate PCB, disposed over the interface PCB, wherein a second flash memory chip is placed between the interface PCB and
the separate PCB, and the second flash memory chip comprises a first embedded flash memory chip and a dynamic random access
memory (DRAM), wherein the second flash memory chip is connected to the interface PCB through corresponding first pins of
the DRAM; and

a socket device, disposed over the separate PCB and configured to install the first flash memory chip, wherein the first flash
memory chip is connected to the interface PCB through corresponding second pins.

US Pat. No. 9,411,686

METHODS FOR ACCESSING A STORAGE UNIT OF A FLASH MEMORY AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for accessing a storage unit of a flash memory, performed by a processing unit, comprising:
after all messages within a RAID (Redundant Array of Independent Disk) group are programmed, determining whether a vertical
ECC (Error Correction Code) within the RAID group has been generated;

directing a DMA (Direct Memory Access) controller to obtain the vertical ECC from a DRAM (Dynamic Random Access Memory) and
store the vertical ECC to a buffer when the vertical ECC within the RAID group has been generated, thereby enabling the vertical
ECC to be programmed to the storage unit; and

directing a RAID-encoding unit to output the vertical ECC to the buffer when the vertical ECC within the RAID group has not
been generated, thereby enabling the vertical ECC to be programmed to the storage unit.

US Pat. No. 9,239,685

METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF

Silicon Motion Inc., Jhu...

8. A memory device, comprising:
a Flash memory comprising a plurality of blocks; and
a controller, for accessing the Flash memory, managing the plurality of blocks, and performing memory access management of
data accessed by the controller, wherein the controller controls the Flash memory to perform a plurality of sensing operations
with a plurality of different sensing voltages respectively corresponding to the plurality of sensing operations, generate
a first digital value of a Flash cell of the Flash memory according to the plurality of sensing operations, generate at least
a second digital value of the Flash cell according to the plurality of sensing operations and the generated first digital
value, and obtain soft information of the Flash cell according to the at least one second digital value;
wherein the first digital value and the at least one second digital value are used for determining information of a same bit
stored in the Flash cell, a number of possible bit(s) of the Flash cell directly corresponds to a number of possible states
of the Flash cell, and the obtained soft information is used for performing soft decoding.

US Pat. No. 9,110,824

METHOD, CONTROLLER, AND MEMORY DEVICE FOR CORRECTING DATA BIT(S) OF AT LEAST ONE CELL OF FLASH MEMORY

Silicon Motion Inc., Jhu...

1. A method for modifying a data bit of at least a cell of a flash memory, comprising:
(a) determining a contributing factor of level distribution corresponding to an electric level of a first cell to generate
a first determination result, the contributing factor of level distribution comprising potential impact caused by a storage
level of another cell to the electric level of the first level; and

(b) modifying the data bit corresponding to the electric level of the first cell according to the first determination result.

US Pat. No. 9,430,159

NON-VOLATILE MEMORY DEVICES AND CONTROLLERS

SILICON MOTION, INC., Jh...

1. A non-volatile memory device comprising:
a non-volatile memory divided into a plurality of physical blocks, wherein each physical block is divided into a plurality
of physical pages; and

a connection interface connected to a host; and
a controller,
wherein the controller receives a series of write commands from the host through the connection interface, and address of
the write commands correspond to logic pages in a corresponding logic block,

wherein the controller selects one physical block from the plurality of physical block to serve as an operation physical block
and writes the different logic pages of the different logic blocks into the operation physical block, and

wherein when the controller performs a recovery operation after an abnormal status occurs, even though there is remaining
space in the operation physical block, the controller re-selects another physical block to serve as the operation physical
block for following data write operation.

US Pat. No. 9,368,226

DATA STORAGE DEVICE AND METHOD FOR RESTRICTING ACCESS THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, having a plurality of blocks, and each of the blocks has a plurality of pages;
a temperature sensor, arranged to detect surrounding ambient temperature and produce temperature parameters accordingly; and
a controller, configured to sequentially perform a plurality of maintenance procedures at different times during the flash
memory is powered on, and scan the blocks to maintain data stored in the pages of the flash memory in the maintenance procedures,
wherein the controller is configured to perform a first maintenance procedure of the plurality of maintenance procedures after
a predetermined period from the time the data storage device is powered on, read the temperature sensor to obtain a first
temperature parameter in the first maintenance procedure, determine a first time span according to a first predetermined condition,
and perform a second maintenance procedure of the plurality of maintenance procedures after the first time span from the time
the first maintenance procedure has finished, wherein the first predetermined condition comprises the first temperature parameter.

US Pat. No. 9,355,028

DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data-storage device, comprising:
a FLASH memory, allocated to provide data-storage space, a valid page count table, logical-to-physical address mapping information,
and an invalid block record; and

a controller, allocating the data-storage space to store data issued from a host, and establishing and maintaining the valid
page count table, the logical-to-physical address mapping information, and the invalid block record in the FLASH memory to
manage the data-storage space,

wherein:
the controller updates the logical-to-physical address mapping information after an update of the valid page count table is
completed;

the controller maintains the invalid block record based on the valid page count table;
wherein:
every round of updating the valid page count table, the logical-to-physical address mapping information, and the invalid block
record is followed by backing up the valid page count table, the logical-to-physical address mapping information, and the
invalid block record to the FLASH memory as power-restoration information; and

in power restoration, the controller uses the power-restoration information to update the valid page count table, the logical-to-physical
address mapping information, and the invalid block record first and then compares an event record with the logical-to-physical
address mapping information to further update the valid page count table and then continuously maintains the valid page count
table, the logical-to-physical address mapping information, and the invalid block record.

US Pat. No. 9,208,074

UPDATING ADDRESS MAPPING IN SUB-INTERVALS IN A FLASH MEMORY DATA STORAGE DEVICE

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory, providing storage space divided into a plurality of blocks with each block comprising a plurality of pages;
a random access memory; and
a controller, operating the FLASH memory in accordance with commands issued from a host,
wherein:
when a master buffer block selected from the plurality of blocks of the FLASH memory to buffer write data from the host is
full, the controller updates a logical-to-physical address mapping table for the master buffer block based on a master buffer
block physical-to-logical address mapping table in separated update sub-intervals;

the logical-to-physical address mapping table is maintained on the FLASH memory;
the master buffer block physical-to-logical address mapping table is maintained in the random access memory corresponding
to the master buffer block;

between the separated update sub-intervals, the controller responds to commands from the host; and
the controller further selects a slave buffer block from the plurality of blocks of the FLASH memory to buffer write data
between the separated update sub-intervals.

US Pat. No. 9,082,491

DATA WRITING METHOD AND DATA STORAGE DEVICE

SILICON MOTION, INC., Jh...

1. A data writing method for a flash memory, comprising:
obtaining write data to be written to the flash memory;
directing the flash memory to write a data page of the write data to a strong page of a target pair page of a target block;
and

directing the flash memory to write first predetermined data to a weak page of the target pair page for extending the data
duration of the strong page of the target pair page.

US Pat. No. 9,443,604

ELECTRONIC DEVICE AND DATA-MANAGEMENT METHOD THEREOF

SILICON MOTION, INC., Jh...

1. An electronic device, comprising:
a controller;
a first flash memory, storing a first data sector; and
a second flash memory, storing a second data sector, wherein the first data sector and the second data sector are the same,
and the first data sector is stored in a plurality of pages of the first flash memory and the second data sector is stored
in a plurality of pages of the second flash memory;

wherein the controller produces a third data sector according to the first data sector and the second data sector to recover
the first data sector when the first data sector stored in the first flash memory and the second data stored in the second
flash memory are damaged.

US Pat. No. 9,430,030

STATUS SWITCHING METHOD

SILICON MOTION, INC., Jh...

1. A status switching method, applied to a slave device, wherein the status switching method comprises:
receiving a command wrapper from a host device;
receiving a status query command corresponding to the command wrapper form the host device;
transmitting a status wrapper to the host device in response to the status query command; and
refusing to enter a low-power status corresponding to a switch status request when the switch status request is received during
a specific period, wherein the specific period starts when the command wrapper is received and ends when the status wrapper
is transmitted.

US Pat. No. 9,104,549

DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT

SILICON MOTION, INC., Jh...

1. A data storage device, coupled to a host, comprising:
a flash memory, comprising a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of
spare blocks, and the data block pool comprises a plurality of data blocks, wherein a spare block count indicates a total
number of the spare blocks; and

a controller, receiving target data from the host, writing the target data to a current data block, determining whether a
current programming page is the first page of the current data block, determining whether the spare block count is less than
a spare block count threshold when the current programming page is the first page, and setting data move information for a
data merge process when the spare block count is less than the spare block count threshold, wherein when the current page
is not the first page, the controller determines whether the data move information is set, and when the data move information
is set, the controller performs a data merge process according to the data move information within a limited time period,
wherein the limited time period is determined by a standard for data transmission between the data storage device and the
host.

US Pat. No. 9,489,916

PROCESSING METHOD OF AN EXTERNAL-IMAGE DEVICE

SILICON MOTION, INC., Jh...

1. A processing method of an electrical device, comprising:
receiving a first number of basic area-updating requests generated by an operating system of the electrical device, by a processor
circuit operating in the electrical device, wherein each of the basic area-updating requests corresponds to an image-updating
area, and the first number of basic area-updating requests correspond to an updating contents of a displayed image;

calculating the image-updating areas corresponding to the first number of basic area-updating requests by the processor circuit;
using a transmission rate of an external interface to determine a ratio of the first number corresponding to the basic area-updating
requests and a second number corresponding to transmission-image areas by the processor circuit;

integrating the image-updating areas to the second number of the transmission-image areas according to the ratio to reduce
an amount of data transmission between an external-image device and the electronic device by the processor circuit, wherein
a screen update fluency of the external-image device is smoother when a network bandwidth between the external-image device
and the electrical device is limited; and

transmitting the second number of transmission-image areas to the external-image device through the external interface by
the processor circuit.

US Pat. No. 9,361,999

DATA STORAGE DEVICE AND ERROR CORRECTION METHOD CAPABLE OF ADJUSTING VOLTAGE DISTRIBUTION

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory; and
a controller, configured to perform a first read operation to read a first page corresponding to a first word line of the
flash memory according to a read command of a host, and perform a distribution-adjustment procedure when data read by the
first read operation cannot be recovered by coding, wherein the controller is further configured to perform an adjustable
read operation to read a second page corresponding to a second word line of the flash memory in the distribution-adjustment
procedure, wherein the controller is further configured to read the second page by a predetermined number of adjustment times
in the adjustable read operation to adjust the threshold voltage distribution of the first page by a read disturbance effect.

US Pat. No. 9,177,664

METHOD, MEMORY CONTROLLER AND SYSTEM FOR READING DATA STORED IN FLASH MEMORY

Silicon Motion, Inc., Jh...

1. A method for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory cells and
stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of 2N voltage states, the method comprises:
controlling the flash memory to perform a first read operation upon the memory cell with a first threshold voltage to obtain
a first binary digit for representing a bit of the N bits data;

performing an error correction hard decode according to the first binary digit;
controlling the flash memory to perform a second read operation upon the memory cell with a second threshold voltage to obtain
a second binary digit for representing the bit of the N bits data, if the error correction hard decode indicates an uncorrectable
result;

performing an error correction soft decode according to the first binary digit and the second binary digit; and
determining a threshold voltage shifting direction by obtaining a bit flopping phenomenon from comparing the first binary
digit and the second binary digit when the error correction soft decode indicates a correctable result, wherein a bit flopping
number showing bit-flopping phenomenon of all memory cells of a target page containing the memory cell is calculated, and
the smaller the bit flopping number the more the threshold voltage shifting direction inclines to.

US Pat. No. 9,417,959

FLASH DEVICE AND OPERATING METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A flash device, comprising:
a flash memory, comprising a plurality of pages; and
a controller coupled to the flash memory, comprising:
an operating unit, receiving a plurality of bytes of the page which are from the flash memory and corresponding to a read
command, and obtaining an operation result according to a logic level of each bit of each of the bytes;

an error correction code decoder, decoding the bytes of the page according to an error correction code; and
a processing unit coupled to the operating unit and the error correction code decoder, determining whether the page is valid
data according to the decoded bytes, and determining whether the page is an empty page according to the operation result after
determining that the page is not the valid data,

wherein when the operation result indicates that the logic level of at least one bit of the bytes is a low logic level, the
processing unit re-provides the read command to the flash memory.

US Pat. No. 9,170,937

DATA STORAGE DEVICE AND OPERATING METHOD FOR FLASH MEMORY

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory, providing a storage space storing a first storage type system information and a second storage type system
information, wherein, data recognition for the first storage type system information is stricter than that of the second storage
type information; and

a controller, coupled to the FLASH memory, reading the storage space, and performing an error checking and correction process
on data read from the storage space and operating the FLASH memory based on the storage type system information, among the
first and second storage type information, which first passes the error checking and correction process,

wherein:
the FLASH memory further comprises a read/write circuit;
the read/write circuit provides a multi-level programming technique, by which a storage cell is programmed in two stages for
transformation to a multi-level cell, wherein the two stages include a strong page stage and a weak page stage;

the read/write circuit further provides a single level programming technique, by which a storage cell is transformed to a
single level cell;

the first storage type system information is programmed into the storage space by the read/write circuit via the strong page
stage of the multi-level programming technique; and

the second storage type system information is written into the storage space by the read/write circuit through the single
level programming technique.

US Pat. No. 9,134,946

ELECTRONIC APPARATUS AND METHOD FOR DATA TRANSMISSION FROM AN ELECTRONIC APPARATUS TO A DISPLAY DEVICE

SILICON MOTION, INC., Jh...

1. An electronic apparatus, coupled to a display device, comprising:
a memory, comprising a virtual frame buffer for storing data to be transmitted to the display device;
a data transmission interface, performing data transmission between the electronic apparatus and the display device; and
a control module, storing a current character image corresponding to a current character in the virtual frame buffer when
a user inputs the current character to an input device, determining whether a prior image which has not been transmitted to
the display device exists in the virtual frame buffer, determining whether the current character image matches the prior image,
and combining the prior image with the current character image to obtain a combined image in place of the prior image when
the current character image matches the prior image, wherein when an abscissa value of the upper-left corner of the current
character image is equal to the sum of the abscissa value of the upper-left corner of the prior image and the width of the
prior image, the ordinate value of the upper-left corner of the prior image is equal to the ordinate value of the upper-left
corner of the current character image, and the height of the prior image is equal to the height of the current character image,
the control module determines that the current character image matches the prior image.

US Pat. No. 9,400,746

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory, providing a physical storage space comprising a plurality of blocks;
a controller, for management of the plurality of blocks as well as a spare queue and a jail queue for the plurality of blocks
of the FLASH memory, and imprisoning some of the plurality of blocks into the jail queue,

wherein:
the controller further monitors erase counts of the blocks within the jail queue and the spare queue; and
when the jail queue is full and any block within the spare queue has an erase count greater than any block within the jail
queue, the controller releases a first block from the jail queue and pushes a second block selected from the spare queue into
the jail queue.

US Pat. No. 9,244,833

DATA-STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data-storage device, comprising:
a FLASH memory, providing data-storage space and recorded with logical-to-physical address mapping information, wherein:
the logical-to-physical address mapping information includes a group table and a plurality of logical-to-physical address
mapping tables corresponding to different groups;

each entry in the group table corresponds to one group and points to one logical-to-physical address mapping table corresponding
thereto; and

the logical-to-physical address mapping tables show how host addresses are mapped to the data-storage space;
a controller, executing firmware to allocate the data-storage space to store data issued from a host and to maintain the logical-to-physical
address mapping information in the FLASH memory; wherein

when allocating a first new page in the FLASH memory to update a target host page, the controller further corrects the physical-to-logical
address mapping table in a random-access memory to record that the first new page maps to the target host page, copies an
original page of the target host page from the FLASH memory to the random-access memory to be updated in the random-access
memory and then write to the first new page of the FLASH memory in accordance with the physical-to-logical address mapping
table provided by the random-access memory, allocates a second new page in the FLASH memory for update of the logical-to-physical
address mapping table corresponding to the target host page to point to the first new page by one entry therein, and allocates
a third new page in the FLASH memory for update of the group table to point to the second new page by one entry therein.

US Pat. No. 9,459,962

METHODS FOR ACCESSING A STORAGE UNIT OF A FLASH MEMORY AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

5. An apparatus for accessing a storage unit of a flash memory, comprising:
a multiplexer;
a buffer;
a RAID-encoding (Redundant Array of Independent Disk-encoding) unit, generating vertical ECC (Error Correction Code) according
to original data; and

a processing unit, coupled to the multiplexer and the RAID-encoding unit, controlling the multiplexer to couple a DRAM (Dynamic
Random Access Memory) to the buffer; directing a DMA (Direct Memory Access) controller to store a message of the DRAM to the
buffer through the multiplexer and to output the message of the DRAM to the RAID-encoding (Redundant Array of Independent
Disk-encoding) unit in a plurality of batches; and, after a first condition is satisfied, controlling the multiplexer to couple
the RAID-encoding unit to the buffer and directing the RAID-encoding unit to output the vertical ECC to the buffer through
the multiplexer in at least one batch,

wherein the vertical ECC is generated by the RAID-encoding unit according to the message,
wherein the first condition is satisfied when a first counter value reaches a threshold, indicating a total number of message
outputs,

wherein the message, the vertical ECC, and a horizontal ECC associated with one of the message and the vertical ECC form a
RAID group.

US Pat. No. 9,292,432

GARBAGE COLLECTION METHOD FOR FLASH MEMORY

SILICON MOTION, INC., Jh...

1. A data storage device, coupled to a host, the data storage device comprising:
a flash memory, comprising a spare block pool, and a data block pool, wherein the spare block pool comprises a plurality of
spare blocks, and the data block pool comprises a plurality of data blocks; and

a controller, receiving target data from the host and writing the target data to a current data block of the plurality of
data blocks,

wherein when the controller determines that a wear-leveling process is to be performed to write the target data, the controller
sorts an erase count of each data block,

wherein when the controller determines that no two blocks among the data blocks simultaneously have the same smallest erase
count, the controller further determines whether the difference of the erase count corresponding to at least one first block
in the data blocks and the smallest erase count is less than a first threshold value,

wherein when the difference between the erase count corresponding to at least one first block in the data blocks and the smallest
erase count is less than a first threshold value, the controller selects a second block having a smallest valid page number
from the at least one first block to perform a data cleaning process, thereby writing valid pages of the second block to one
of the spare blocks.

US Pat. No. 9,293,203

METHOD FOR READING DATA STORED IN A FLASH MEMORY ACCORDING TO A THRESHOLD VOLTAGE DISTRIBUTION AND MEMORY CONTROLLER AND SYSTEM THEREOF

Silicon Motion, Inc., Jh...

1. A method for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory cells and
each memory cell has a particular threshold voltage, the method comprising:
obtaining a first threshold voltage information representing threshold voltages of a first group of the memory cells;
obtaining a second threshold voltage information representing threshold voltages of a second group of the memory cells, wherein
the second threshold voltage information is different from the first threshold voltage information, and the first group of
the memory cells comprises at least a part of the second group of the memory cells; and

controlling the flash memory to perform at least one read operation upon the first group of the memory cells according to
the second threshold voltage information.

US Pat. No. 9,811,414

METHOD FOR MANAGING DATA STORED IN FLASH MEMORY AND ASSOCIATED MEMORY DEVICE AND CONTROLLER

Silicon Motion Inc., Hsi...

1. A method for managing data stored in a flash memory, wherein the flash memory comprises a plurality of blocks; the method
comprising:
reading a program list from a memory within a memory controller for controlling the flash memory, instead of the flash memory,
wherein the program list records information about programmed blocks of the plurality of blocks and sequence of write times
of the programmed blocks, and the memory within the memory controller is different from the flash memory;

determining a first block of the plurality of blocks according to the program list, wherein the first block is a programmed
block that has an earliest write time in the program list, and the first block is a starting block for a quality detection
operation;

starting the quality detection operation to read the first block to detect quality of the first block to generate a first
detection result;

referring to the first detection result to determine whether to move contents of the first block to a third block and delete
the contents of the first block; and

when the contents of the first block are moved to the third block, deleting records associated with the first block in the
program list, and adding records associated with the third block into the program list stored in the memory within the memory
controller.

US Pat. No. 9,507,708

METHOD FOR MANAGING MEMORY APPARATUS, ASSOCIATED MEMORY APPARATUS THEREOF AND ASSOCIATED CONTROLLER THEREOF

Silicon Motion Inc., Hsi...

1. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element,
each of the at least one NV memory element comprising a plurality of blocks, the method being applied to a controller of the
memory apparatus, the controller arranged to control the at least one NV memory element, the method comprising following steps:
temporarily storing data received from a host device into a volatile memory in the controller and utilizing the data in the
volatile memory as received data, and dynamically monitoring a data amount of the received data to determine whether to immediately
write the received data into the at least one NV memory element, wherein at least one write command received from the host
device indicates that the host device demands to write the data; and

when a specific signal is received and it is detected that specific data having been written into a same location in a specific
block configured to be a multiple level cell (MLC) memory block within a specific NV memory element of the at least one NV
memory element for at least once but less than a predetermined number of times exists in the received data, immediately writing
the specific data into another block in the at least one NV memory element, to prevent the specific data from being lost,
wherein the specific signal indicates that power of the controller is abnormal or the memory apparatus is going to be powered
off, the predetermined number of times is larger than one, and the other block is configured as a single level cell (SLC)
memory block.

US Pat. No. 9,223,691

DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT

SILICON MOTION, INC., Jh...

1. A data storage device, coupled to a host, comprising:
a flash memory, comprising a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of
spare blocks, and the data block pool comprises a plurality of data blocks, wherein the spare blocks with erase counts higher
than a hot threshold are determined as hot spare blocks, and a hot spare block count indicates a total number of the hot spare
blocks; and

a controller, receiving target data from the host, writing the target data to a current data block, determining whether a
current programming page is the first page which is on the first most position of physical arrangement of the current data
block, determining whether the hot spare block count is greater than zero when the current programming page is the first page,
setting data move information for a wear-leveling process when the hot spare block count is greater than zero, determining
whether the data move information is set when the current page is not the first page, and performing a wear-leveling process
according to the data move information when the data move information is set.

US Pat. No. 9,536,602

METHOD FOR WRITING DATA INTO FLASH MEMORY AND RELATED CONTROL APPARATUS

Silicon Motion Inc., Hsi...

1. A method for writing data into a flash memory, wherein the flash memory includes a plurality of multi-level cells, and
each of the plurality of multi-level cells is arranged to store a plurality of bits, the method comprising:
storing a first bit into each of the plurality of multi-level cells respectively, and for each of the plurality of multi-level
cells:

determining a data polarity of a first bit to be written into the multi-level cell;
when the data polarity of the first bit is a first polarity, not injecting a first electrical charge amount into a floating
gate of the multi-level cell; and

when the data polarity of the first bit is a second polarity, injecting the first electrical charge amount into the floating
gate of the multi-level cell;

determining if each of the plurality of multi-level cells stores the first bit respectively; and
when each of the plurality of multi-level cells stores the first bit respectively, storing a second bit into each of the plurality
of multi-level cells respectively.

US Pat. No. 9,514,042

METHOD FOR MANAGING MEMORY APPARATUS TO PERFORM WRITING CONTROL ACCORDING TO MONITORED DATA AMOUNT OF RECEIVED DATA, ASSOCIATED MEMORY APPARATUS THEREOF AND ASSOCIATED CONTROLLER THEREOF

Silicon Motion Inc., Hsi...

1. A method for managing a memory apparatus, the memory apparatus comprising at least one non-volatile (NV) memory element,
each of the at least one NV memory element comprising a plurality of blocks, the method applied to a controller of the memory
apparatus, the controller being used to control the at least one NV element, the method comprising following steps:
temporarily storing data received from a host device into a volatile memory in the controller and utilizing the data in the
volatile memory as received data, and dynamically monitoring a data amount of the received data to determine whether to immediately
write the received data into the at least one NV memory element, wherein at least one write command received from the host
device indicates that the host device requests to write the data; and

when determining to immediately write the received data into the at least one NV memory element, directly writing the received
data into a specific block configured to be a Multiple Level Cell (MLC) memory block within a specific NV memory element of
the at least one NV memory element, rather than indirectly writing the received data into the specific block by first temporarily
writing the received data into any other block configured to be a Single Level Cell (SLC) memory block.

US Pat. No. 9,329,992

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a FLASH memory with a storage space divided into blocks, wherein each block is further divided into pages; and
a controller, coupled to the FLASH memory to manage at least one replay-protected memory block of the FLASH memory,
wherein:
the controller programs two pages into the at least one replay-protected memory block and each page is programmed with a write
count of the at least one replay-protected memory block;

during a power restoration process, the controller checks the at least one replay-protected memory block to recognize whether
a power failure event happened;

during the power restoration process, the controller checks the amount of programmed pages of the at least one replay-protected
memory block; and

during the power restoration process, the controller ignores the last programmed page of the at least one replay-protected
memory block when there is an odd number of programmed pages of the at least one replay-protected memory block.

US Pat. No. 9,288,475

3D IMAGE-CAPTURING METHOD, 3D CAMERA AND LEVEL-ALIGNMENT MACHINE FOR 3D CAMERA

SILICON MOTION, INC., Jh...

1. A 3D image-capturing method, comprising:
using a left-eye camera to capture a left-eye image and using a right-eye camera to capture a right-eye image;
comparing the left- and right-eye images to observe similar columns between the left- and right-eye images and thereby obtain
a first-column range in the left-eye image and a second-column range in the right-eye image which indicate similar columns;

comparing the left-eye image within the first-column range with the right-eye image within the second-column range to observe
similar rows between the left- and right-eye images and thereby obtain a first-row range in the left-eye image and a second-row
range in the right-eye image which indicate similar rows; and

vertically shifting the left- and right-eye images in accordance with the first-row range obtained in the left-eye image and
the second-row range obtained in the right-eye image to horizontally align the left- and right-eye images to generate a 3D
image,

wherein the step of observing the first-column range in the left-eye image and the second-column range in the right-eye image
further comprises:

estimating vertical projections of the left- and right-eye images;
differentiating the vertical projections of the left- and right-eye images to obtain first-order differentiated vertical projections
of the left- and right-eye images; and

shifting the first-order differentiated vertical projections of the left- and right-eye images relative to each other step
by step with comparisons between each shift and thereby the first-column range in the left-eye image and the second-column
range in the right-eye image are obtained.

US Pat. No. 10,049,005

FLASH MEMORY CONTROL APPARATUS UTILIZING BUFFER TO TEMPORARILY STORING VALID DATA STORED IN STORAGE PLANE, AND CONTROL SYSTEM AND CONTROL METHOD THEREOF

Silicon Motion Inc., Hsi...

1. A flash memory control apparatus, comprising:a data read/write interface, arranged for coupling a first flash memory and a second flash memory, wherein the first flash memory comprises a first storage plane and a first buffer, and the second flash memory comprises a second storage plane and a second buffer; and
a controller, coupled to the data read/write interface, the controller arranged for transmitting a plurality of valid data sets stored in the first storage plane to the second buffer through the data read/write interface, wherein each of the plurality of valid data sets has a plurality of data bits; a data size of the plurality of valid data sets stored in the first storage plane is less than or equal to a storage capacity of the second buffer; and after an erase cycle is performed on the first storage plane, the controller further programs the plurality of valid data sets transmitted to the second buffer into the first storage plane.

US Pat. No. 9,666,294

METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY

Silicon Motion Inc., Hsi...

6. A memory controller for reading data stored in a flash memory, comprising:
a receiving circuit, arranged for obtaining a plurality of bit sequences read from a plurality of memory cells of the flash
memory, respectively;

a control logic, coupled to the receiving circuit, the control logic arranged for performing a plurality of read operations
upon each of the memory cells; and

an error correction code (ECC) circuit, coupled to the control logic, for determining whether the bit sequences have uncorrectable
error bits;

wherein when the bit sequences have uncorrectable error bits, the control logic updates the bit sequences, and determines
a readout information of the memory cells according to updated bit sequences.

US Pat. No. 9,601,219

METHOD, MEMORY CONTROLLER, AND MEMORY SYSTEM FOR READING DATA STORED IN FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A method for reading data stored in a flash memory, comprising:
selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options;
controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading
a plurality of bit sequences;

performing a codeword error correction operation upon the plurality of bit sequences, and determining whether the codeword
error correction operation performed upon the plurality of bit sequences is successful;

when the codeword error correction operation performed upon the plurality of bit sequences is not successful, determining
an electric charge distribution parameter corresponding to the initial gate voltage combination;

determining a target gate voltage combination corresponding to the electric charge distribution parameter according a look-up
table (LUT), wherein the target gate voltage combination comprises a plurality of threshold voltage levels; and

controlling the plurality of memory units according to the target gate voltage combination, to read a plurality of updated
bit sequences.

US Pat. No. 9,520,184

METHOD FOR WRITING IN-SYSTEM PROGRAMMING CODE INTO FLASH MEMORY FOR BETTER NOISE MARGIN

Silicon Motion Inc., Hsi...

4. A flash memory, wherein the flash memory is a Triple-Level Cell flash memory, each storage unit of the flash memory is
implemented by a floating-gate transistor and each storage unit supports eight write voltage levels; wherein before the first
time the flash memory is read by a memory controller, data in the flash memory is stored with only two specific voltage levels
of the eight write voltage levels, wherein the data comprises least significant bits (LSBs), central significant bits (CSBs)
and most significant bits (MSBs).

US Pat. No. 10,075,311

CLOCK CORRECTION METHOD AND CIRCUIT UTILIZING TRAINING SEQUENCE TO CORRECT OSCILLATOR OUTPUT, AND REFERENCE CLOCK GENERATION METHOD AND CIRCUIT UTILIZING TRAINING SEQUENCE TO GENERATE REFERENCE CLOCK

Silicon Motion Inc., Hsi...

1. A clock correction method, comprising:receiving a training signal in a communication protocol, wherein the training signal carries a specific signal pattern occurring repeatedly;
performing frequency division on the training signal according to a number of toggles of the specific signal pattern so as to generate an equalization training sequence (TSEQ) clock; and
correcting a frequency of an output clock of an oscillator according to the equalization training sequence clock.

US Pat. No. 10,019,355

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A flash memory apparatus, comprising:a flash memory module comprising a plurality of first blocks and at least one second block; and
a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of first blocks, a cell of the plurality of first blocks being arranged for storing data of two bits;
wherein after completing program of the plurality of first blocks, the flash memory module is arranged for performing an internal copy operation to program the at least one second block by sequentially reading and writing the groups of data and the corresponding parity check code from the plurality of first blocks to the at least one second block, a cell of the second block being arranged for storing data of 2N bits, N being an integer equal to 2 or greater than 2.

US Pat. No. 9,627,085

REFRESH METHOD FOR FLASH MEMORY AND RELATED MEMORY CONTROLLER THEREOF

Silicon Motion Inc., Hsi...

1. A refresh method for a flash memory, comprising:
performing a write operation to store an input data into a storage space in the flash memory, the write operation comprising
an initial program operation, a first reprogram operation, and a second reprogram operation which are sequentially performed;

checking reliability of the storage space with the input data already stored therein, the checking step comprising: detecting
if the storage space with the input data already stored therein suffers from data-retention disturbance; and

when the checking steps indicates that the storage space suffers from the data-retention disturbance, performing a refresh
operation upon the storage space based on the input data, and the refresh operation comprises:

recovering the input data from the storage space; and
programming the input data recovered from the storage space into original storage locations in the storage space, the programming
step being an additional reprogram operation applied to the storage space and different and distinct from the initial program
operation, the first reprogram operation, and the second reprogram operation;

wherein the input data stored in the storage space by the write operation is read based on a first initial setting of reference
threshold voltage values, and the input data stored in the storage space by the refresh operation is read based on a second
initial setting of reference threshold voltage values different from the first initial setting of reference threshold voltage
values; the second initial setting of reference threshold voltage values corresponds to threshold voltage distributions that
are sharper than threshold voltage distributions of the first initial setting of reference threshold voltage values.

US Pat. No. 9,570,183

METHOD AND CONTROLLER FOR MANAGING MEMORY DEVICE

Silicon Motion Inc., Hsi...

9. A memory device, comprising:
at least one non-volatile (NV) memory element, each comprising a plurality of blocks; and
a controller, arranged to control the NV memory element, the controller comprising a processing unit for managing the memory
device according to a program code embedded in the processing unit or a program code received from outside the processing
unit, wherein the controller sends a last writing command to a specific NV memory element within the NV memory element to
write a set of data to a specific block in the specific NV memory element, rather than sending either a first writing command
or a second writing command to the specific NV memory element, wherein the first writing command, the second writing command,
and the last writing command are used to write a same data into a same location in the NV memory element at different times,
respectively, to ensure that the same data is stored correctly;

wherein after the set of data is written to the specific block, the controller sends a read command to the specific NV memory
element to read stored data of the set of data from the specific block, and checks whether the stored data matches the set
of data to determine whether the specific block is a bad block.

US Pat. No. 9,520,185

METHOD FOR PERFORMING MEMORY ACCESS MANAGEMENT, AND ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF

Silicon Motion Inc., Hsi...

9. A memory device, comprising:
a Flash memory comprising a plurality of blocks; and
a controller, for accessing the Flash memory, managing the plurality of blocks, and performing memory access management of
data accessed by the controller, wherein the controller performs a plurality of sensing operations respectively corresponding
to a plurality of different sensing voltages to generate a first digital value of a Flash cell of a Flash memory and a second
digital value of the Flash cell of the Flash memory, uses the first digital value and the second digital value to obtain soft
information of a bit stored in the Flash cell, and uses the soft information to perform soft decoding.

US Pat. No. 9,093,154

METHOD, MEMORY CONTROLLER AND SYSTEM FOR READING DATA STORED IN FLASH MEMORY

SILICON MOTION, INC., Jh...

10. A memory controller for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory
cells and stores N bit(s) data in a memory cell of the memory cells by programming the memory cell to one voltage state of
2N voltage states, the memory controller comprises:
a control logic for controlling the flash memory to perform at least one read operation upon the memory cell to obtain at
least one binary digit for representing a bit of the N bits data;

an encoder, coupled to the control logic, for generating a codeword for representing the bit of the N bits data according
to the at least one binary digit, wherein the codeword is different from the at least one binary digit; and

a memory buffer, coupled to the encoder, for storing the codeword and providing the codeword to an error correction decoder
for performing an error correction operation,

wherein the control logic is further for controlling the flash memory to perform a first read operation with a first threshold
voltage upon the memory cell to obtain a first binary digit of the at least one binary digit; and

wherein the encoder is further for determining the first binary digit as a sign bit of the codeword; and for generating at
least one strength bit for representing a reliability of the sign bit.

US Pat. No. 9,069,978

DATA STORAGE DEVICE AND DATA PROTECTION METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of blocks; and
a memory controller, encrypting a first file to produce a first encrypted file and store the first encrypted file to the flash
memory, wherein the controller further comprises:

a key generation module, producing a first key according to a first write command of a host device, wherein the first key
is arranged to be stored in a first block of the blocks;

an encryption/decryption module, encrypting the first file according to the first key to produce a first encrypted file, wherein
the first encrypted file is arranged to be stored in at least one second block of the blocks; and

a key eliminating module, deleting the first key stored in the first block according to a first eliminating command in order
to invalidate the first encrypted file stored in the second block, wherein the number of the at least one second block is
determined by the first write command and a predetermined length.

US Pat. No. 10,025,662

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A flash memory apparatus, comprising:a flash memory module comprising a plurality of storage blocks, each storage block can be used as a first block or a second block, a cell of the first block being arranged for storing data of 1 bit, a cell of the second block being arranged for storing data of at least 2 bits; and
a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, executing error code encoding to generate a corresponding parity check code to store the groups of data and the corresponding parity check code to at least one block of first blocks;
wherein after completing storing the groups of data, the flash memory module is arranged for performing an internal copy operation upon the groups of data and the corresponding parity check code from the at least one block of the first blocks to at least one second block.

US Pat. No. 9,733,857

FLASH MEMORY CONTROLLER

Silicon Motion Inc., Hsi...

1. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a read and write
circuit and a plurality of blocks supporting a plurality of program threshold voltage intervals, and the flash memory controller
comprising:
a communication interface for receiving data from a host device; and
a processing circuit, coupled with the communication interface and the flash memory module, for dynamically controlling a
data writing mode of the flash memory module according to an amount of stored data in the flash memory module;

wherein if the amount of stored data in the flash memory module is less than a first threshold, the processing circuit controls
the read and write circuit to use only two of the program threshold voltage intervals to write the data into one of the blocks;
and if the amount of stored data in the flash memory module is greater than the first threshold, the processing circuit controls
the read and write circuit to use at least four of the program threshold voltage intervals to write the data into the one
of the blocks.

US Pat. No. 9,218,891

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a FLASH memory with a storage space divided into blocks, wherein each block is further divided into pages; and
a controller coupled to the FLASH memory to manage at least one replay-protected memory block of the FLASH memory,
wherein:
the controller programs a success flag and a write count into a system block of the FLASH memory after the controller programs
two pages into the at least one replay-protected memory block of the FLASH memory;

during a power restoration process, the controller checks the amount of programmed pages of the at least one replay-protected
memory block; and

during the power restoration process, the controller ignores the last programmed page of the at least one replay-protected
memory block when there is an odd number of programmed pages of the at least one replay-protected memory block.

US Pat. No. 9,075,707

DATA WRITING METHOD AND DATA STORAGE DEVICE

SILICON MOTION, INC., Jh...

1. A data writing method for a memory, wherein the memory comprises a data area and a spare area, the data area comprises
a plurality of data blocks storing data, and the spare area comprises a plurality of spare blocks having no data stored therein,
comprising:
receiving a write command for writing a write data to a first data block of the memory from a host;
sorting the plurality of spare blocks of the spare area according to erase counts of the plurality of spare blocks;
calculating a total number of worn-out blocks in the spare area, wherein erase counts of the worn-out blocks are greater than
a first threshold;

checking whether the total number of the worn-out blocks is greater than a specific number, wherein the specific number is
equal to two;

if the total number of the worn-out blocks is greater than the specific number, performing a wear-leveling process to swap
the worn-out blocks in the spare area for the data blocks in the data area;

selecting a first spare block with the least erase counts from the plurality of spare blocks of the spare area;
writing the write data to the first spare block; and
erasing data from the first data block to convert the first data block to a spare block,
wherein the performing of the wear-leveling process comprises:
selecting a second spare block with the largest erase count from the worn-out blocks of the spare area;
obtaining a second data block with an erase count less than a second threshold from the data area;
writing data stored in the second data block to the second spare block; and
erasing data from the second data block to convert the second data block to a spare block,
wherein obtaining of the second data block comprises:
when the data area does not comprise any data blocks with erase counts less than the second threshold, subtracting a predetermined
number from the erase counts of all data blocks of the data area; and

searching the data area for the second data block with an erase count less than the second threshold.

US Pat. No. 9,904,312

FREQUENCY CALIBRATION METHOD APPLICABLE IN UNIVERSAL SERIAL BUS DEVICE AND RELATED UNIVERSAL SERIAL BUS DEVICE

Silicon Motion Inc., Hsi...

1. A frequency calibration method applied to a Universal Serial Bus (USB) device, comprising:
coupling the USB device to a USB host, wherein the USB device comprises at least a programmable oscillator;
utilizing the USB device to extract a low frequency periodic signal (LFPS) from the USB host;
utilizing the programmable oscillator to generate an oscillating signal;
performing a frequency dividing operation upon the oscillating signal, to generate a feedback signal;
generating a specific clock signal according to the oscillating signal; and
utilizing the specific clock signal to detect a second frequency of the feedback signal;
comparing a first frequency of the low frequency periodic signal and the second frequency of the feedback signal, to generate
a comparison result; and

adjusting the programmable oscillator according to the comparison result, to generate the oscillating signal having the predetermined
frequency;

wherein a frequency of the specific clock signal is higher than a frequency of the oscillating signal.

US Pat. No. 9,614,433

SWITCHING-CAPACITOR REGULATOR WITH CHARGE INJECTION MODE FOR HIGH LOADING CURRENT

Silicon Motion Inc., Hsi...

1. A switching-capacitor regulator with a charge injection mode for a high loading current, wherein the switching-capacitor
regulator generates an output voltage at an output node, comprising:
a storage capacitor;
a switch module, coupled between the storage capacitor, a first supply voltage, a second supply voltage and the output node,
and the switch module comprises:

a first switch, coupled to a first node of the storage capacitor, for selectively connecting the first supply voltage to the
first node of the storage capacitor;

a second switch, coupled between the first node of the storage capacitor and the output node, for selectively connecting the
first node of the storage capacitor to the output node;

a third switch, coupled between a second node of the storage capacitor and the output node, for selectively connecting the
second node of the storage capacitor to the output node; and

a fourth switch, coupled to the second node of the storage capacitor, for selectively connecting the second supply voltage
to the second node of the storage capacitor;

a current source, directly connected to the output node, for selectively providing a current to the output node directly;
and

a control unit, coupled to the switch module and the output node, for controlling the switch module to selectively charge
or discharge the storage capacitor, and for controlling the current source to selectively provide the current to the output
node, to adjust a voltage level of the output voltage;

wherein the control unit controls the switch module to selectively charge or discharge the storage capacitor, and controls
the current source to selectively provide the current to the output node directly to adjust the voltage level of the output
voltage according to the voltage level of the output voltage, and the control unit comprises:

a first comparator, for comparing the output voltage and a first reference voltage to generate a first comparison result;
a first control signal generating unit, coupled to the first comparator, for generating a plurality of first control signals
to control the switch module according to the first comparison result;

a second comparator, for comparing the output voltage and a second reference voltage to generate a second comparison result;
and

a second control signal generating unit, coupled to the second comparator, for generating a second control signal to control
the current source according to the second comparison result;

wherein the second reference voltage is lower than the first reference voltage; and when the output voltage is greater than
the first reference voltage, the first control signal generating unit generates the first control signals to disable all of
the first switch, the second switch, the third switch and the fourth switch, and the second control signal generating unit
generates the second control signal to disable the current source; when the output voltage is lower than the first reference
voltage and is greater than the second reference voltage, the first control signal generating unit generates the first control
signals to control the first switch, the second switch, the third switch and the fourth switch to alternately charge and discharge
the storage capacitor, and the second control signal generating unit generates the second control signal to disable the current
source; and when the output voltage is lower than the second reference voltage, the first control signal generating unit generates
the first control signals to control the first switch, the second switch, the third switch and the fourth switch to alternately
charge and discharge the storage capacitor, and the second control signal generating unit generates the second control signal
to enable the current source.

US Pat. No. 9,497,504

METHOD FOR ENHANCING FAST BACKWARD PERFORMANCE AND ASSOCIATED ELECTRONIC DEVICE

Silicon Motion Inc., Hsi...

1. A method for enhancing fast backward performance, the method comprising:
during a playback or fast forward operation, with regard to a plurality of offsets of a multimedia file, temporarily storing
part of a plurality of cluster numbers which respectively correspond to part of the plurality of offsets into a first buffering
region/buffer, rotating each cluster of the plurality of clusters in and out of a second buffering region/buffer according
to capacity of the second buffering region/buffer such that it is replaced by another cluster of the plurality of clusters,
so that each cluster is only stored temporarily in the second buffering region/buffer, and rotating each corresponding cluster
number in and out of the first buffering region/buffer accordingly, wherein the cluster numbers respectively represent a plurality
of clusters belonging to the multimedia file, and the offsets respectively correspond to different playback time points of
the plurality of clusters; and

utilizing at least one portion of the offsets and the cluster numbers to perform a fast backward operation of the multimedia
file, comprising:

determining whether a cluster corresponding to a target offset exists within the second buffering region/buffer; and
in a situation where the cluster corresponding to the target offset does not exist within the second buffering region/buffer,
determining whether the target offset is one of the offsets, when the target offset is not one of the offsets, finding a specific
offset of the offsets that is most close to, but not greater than, the target offset and utilizing the specific offset as
a start offset, and with regard to a plurality of additional offsets of the multimedia file that start from the start offset
through to the target offset, respectively storing corresponding cluster numbers into the first buffering region/buffer and
temporarily storing clusters represented by the cluster numbers corresponding to the additional offsets into the second buffering
region/buffer in turns, and reading at least one portion of data belonging to the clusters within the second buffering region/buffer
and outputting the at least one portion of the data as output data of the fast backward operation;

wherein the offsets are not stored with the cluster numbers.

US Pat. No. 9,312,691

ESD PROTECTION CIRCUIT AND ESD PROTECTION METHOD THEREOF

SILICON MOTION, INC., Jh...

1. An ESD protection circuit, comprising:
a first voltage terminal;
a second voltage terminal;
a discharge transistor, having a first terminal coupled to the first voltage terminal, a second terminal coupled to the second
voltage terminal, a control terminal coupled to a first node, and a substrate coupled to a second node, wherein the discharge
transistor forms a discharge path between the first voltage terminal and the second voltage terminal;

a first switch, coupled between the first voltage terminal and the first node, arranged to selectively provide voltage at
the first voltage terminal to the control terminal of the discharge transistor;

a second switch, coupled between the first node and the second voltage terminal, arranged to selectively provide voltage at
the second voltage terminal to the control terminal of the discharge transistor;

a third switch, coupled between the first voltage terminal and the second node, arranged to selectively provide voltage at
the first voltage terminal to the substrate of the discharge transistor; and

a fourth switch, coupled between the second node and the second voltage terminal, arranged to selectively provide voltage
at the second voltage terminal to the substrate of the discharge transistor.

US Pat. No. 10,050,642

LOW POWER SCHEME FOR BIT FLIPPING LOW DENSITY PARITY CHECK DECODER

Silicon Motion Inc., Hsi...

1. A method of power saving for a low-density parity check (LDPC) decoder, the method comprising:performing a plurality of decoding iterations to decode a received codeword, comprising:
performing an initial decoding iteration at a first clock frequency;
at the end of the initial decoding iteration, determining a syndrome weight indicating a number of error bits of the decoded codeword;
using the determined syndrome weight to update the first clock frequency for a next decoding iteration of the plurality of decoding iterations, the updated clock frequency being the same as or higher than the first clock frequency;
performing the next decoding iteration according to the updated clock frequency; and
repeating these steps until a codeword is determined;
wherein when the syndrome weight of a specific iteration of the plurality of iterations indicates a number of error bits of the decoded codeword has increased, the updated clock frequency will be increased accordingly in order to give a same throughput for a next decoding iteration as for the specific iteration.

US Pat. No. 9,959,165

METHOD, MEMORY CONTROLLER, AND MEMORY SYSTEM FOR READING DATA STORED IN FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A memory controller for reading data stored in a flash memory, comprising:a control logic circuit, arranged to select an initial gate voltage combination from a plurality of predetermined gate voltage combination options and control a plurality of memory units in the flash memory according to the initial gate voltage combination;
a receiving circuit, coupled to the control logic circuit, the receiving circuit arranged to read a plurality of bit sequences when the control logic circuit controls the plurality of memory units in the flash memory according to the initial gate voltage combination;
a data processing circuit, coupled to the receiving circuit and the control logic circuit, the data processing circuit arranged to perform a codeword error correction upon the plurality of bit sequences and determine whether the codeword error correction performed upon the plurality of bit sequences is successful, wherein when the codeword error correction performed upon the plurality of bit sequences is not successful, the data processing circuit determines an electric charge distribution parameter corresponding to the initial gate voltage combination; and
a storage unit, coupled to the data processing circuit and the control logic circuit, the storage unit arranged to store a look-up table (LUT);
wherein the control logic circuit further determines a target gate voltage combination corresponding to the electric charge distribution parameter by using the LUT, and controls the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination; and the target gate voltage combination comprises a plurality of threshold voltage levels.

US Pat. No. 9,627,047

METHOD FOR INCREASING SPEED OF WRITING DATA INTO FLASH MEMORY UNIT AND ASSOCIATED DEVICE

Silicon Motion Inc., Hsi...

1. A method for writing data into a flash memory unit, the method comprising:
when writing data into the flash memory unit for the n-th time, determining a data polarity of an n-th data bit to be written
into the flash memory unit;

selectively injecting an n-th electrical charge amount into a floating gate of the flash memory unit according to the data
polarity of the n-th data bit only;

when writing data into the flash memory unit for the (n+1)-th time, determining the data polarity of an (n+1)-th data bit
to be written into the flash memory unit; and

selectively injecting an (n+1)-th electrical charge amount into the floating gate of the flash memory unit according to the
data polarity of the (n+1)-th data bit only;

wherein the (n+1)-th electrical charge amount is not equal to the n-th electrical charge amount, and n is a positive integer
not less than 1.

US Pat. No. 10,019,314

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A flash memory apparatus, comprising:a flash memory module comprising a plurality of storage blocks, each storage block can be used as a first block or a second block; and
a flash memory controller, configured for classifying data to be programmed into a plurality of groups of data, respectively executing error code encoding to generate a first corresponding parity check code to store the groups of data and the first corresponding parity check code into the flash memory module as first blocks, a cell of the first blocks being arranged for storing data of 1 bit;
wherein the flash memory controller is further arranged for reading out the groups of data from the first blocks, executing error correction and de-randomize operation upon read out data to generate de-randomized data, executing randomize operation upon the de-randomized data according to a set of seeds to generate randomized data, performing error code encoding upon the randomized data to generate a second corresponding parity check code, storing the randomized data and the second corresponding parity check code into the flash memory module as the second block, a cell of the second block being arranged for storing data of at least 2 bits.

US Pat. No. 9,704,543

CHANNEL CONTROLLING DEVICE FOR IMPROVING DATA READING EFFICIENCY

Silicon Motion Inc., Hsi...

1. A channel controlling device, comprising:
a multiplexing circuit, coupled to a plurality of channels, the multiplexing circuit arranged to select a specific channel
from the channels to output a channel data according to a selecting signal, wherein the channels correspond to a plurality
of predetermined digital numbers, respectively;

a sorting circuit, arranged to queue the predetermined digital numbers according to a data output order of the channels, to
form a plurality of queued digital numbers; and

an arbitration circuit, arranged to determine the selecting signal according to the queued digital numbers.

US Pat. No. 9,858,996

MEMORY ACCESS MODULE FOR PERFORMING SENSING OPERATIONS ON STORAGE CELLS OF A STORAGE DEVICE TO OBTAIN SOFT INFORMATION AND EXECUTING A PROGRAM MODE TO CONTROL ACCESS TO THE STORAGE DEVICE

Silicon Motion Inc., Hsi...

1. A memory access module for performing memory access management of a storage device comprising a plurality of storage cells,
the memory access module comprising:
sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing
voltages in order to generate a first digital value and a second digital value of a storage cell;

processing means for using the first digital value and the second digital value to obtain soft information of a same bit stored
in the storage cell;

decoding means for using the soft information to perform soft decoding; and
controlling means for accessing the storage device, wherein the controlling means comprises:
storage means for storing a program code; and
processing means for executing a program code to control access to the storage device and manage the plurality of storage
cells.

US Pat. No. 10,007,460

FLASH MEMORY CONTROLLER

Silicon Motion Inc., Hsi...

1. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a plurality of blocks, and the flash memory controller comprising:a communication interface for receiving data from a host device; and
a processing circuit, coupled with the communication interface and the flash memory module, for dynamically determining a voltage range of a plurality of program threshold voltage intervals according to an amount of stored data in the flash memory module, and using the plurality of program threshold voltage intervals to write the data into one of the blocks.

US Pat. No. 9,910,772

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A flash memory apparatus, comprising:
a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and
a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory
controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing
single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) XOR (exclusive-OR) error code encoding
to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the
plurality of single-level-cell blocks;

wherein when completing program of the plurality of single-level-cell blocks, the flash memory module is arranged for performing
an internal copy operation to program the at least one multiple-level-cell block by sequentially reading and writing the groups
of data and the corresponding parity check code from the plurality of single-level-cell blocks to the at least one multiple-level-cell
block according to an order of storing data in the plurality of single-level-cell blocks.

US Pat. No. 9,780,977

CLOCK CORRECTION METHOD AND CIRCUIT UTILIZING TRAINING SEQUENCE TO CORRECT OSCILLATOR OUTPUT, AND REFERENCE CLOCK GENERATION METHOD AND CIRCUIT UTILIZING TRAINING SEQUENCE TO GENERATE REFERENCE CLOCK

Silicon Motion Inc., Hsi...

1. A clock correction method, comprising:
receiving an equalization training sequence (TSEQ) specified by a communication protocol, wherein the equalization training
sequence comprises a specific pattern occurring repeatedly;

performing frequency division on the equalization training sequence according to a number of toggles of the specific pattern
so as to generate an equalization training sequence clock; and

correcting a frequency of an output clock of an oscillator according to the equalization training sequence clock.

US Pat. No. 9,703,627

ERROR CORRECTION CODE UNIT, SELF-TEST METHOD AND ASSOCIATED CONTROLLER APPLIED TO FLASH MEMORY DEVICE FOR GENERATING SOFT INFORMATION

Silicon Motion Inc., Hsi...

1. An error correction code (ECC) unit of a flash memory device, comprising:
an encoder, for receiving input data and encoding the received input data to generate an error correction code;
a self-test circuit, coupled to the encoder, the self-test circuit arranged for generating the input data to the encoder,
receiving the error correction code from the encoder, and utilizing the input data and the error correction code to simulate
a reading result of a page of a flash memory of the flash memory device to generate soft information; and

a decoder, coupled to the self-test circuit, the decoder arranged for directly receiving the soft information from the self-test
circuit, without accessing the flash memory, and decoding the soft information to generate a decoding result.

US Pat. No. 10,236,908

FLASH MEMORY APPARATUS AND STORAGE MANAGEMENT METHOD FOR FLASH MEMORY

Silicon Motion Inc., Hsi...

1. A flash memory apparatus, comprising:a flash memory module comprising a plurality of single-level-cell blocks and at least one multiple-level-cell block; and
a flash memory controller having a plurality of channels respectively connected to the flash memory module, the flash memory controller being configured for classifying data to be programmed into a plurality of groups of data, respectively executing single-level-cell programming and RAID-like (Redundant Array of Independent Disks-like) RS (Reed-Solomon) error code encoding to generate a corresponding parity check code to program the groups of data and the corresponding parity check code to the plurality of single-level-cell blocks;
wherein when completing program of the plurality of single-level-cell blocks, controlling the flash memory module to perform an internal copy operation to program the at least one multiple-level-cell block of the flash memory module according to the plurality of single-level-cell blocks of the flash memory module.

US Pat. No. 9,656,073

EXTERNAL ELECTRONIC EAR DEVICE AND COCHLEAR IMPLANT DEVICE

KUANG-CHAO CHEN, New Tai...

1. An external electronic ear device in a cochlear system, the external electronic ear device comprising:
a housing;
an external magnet, disposed in the housing and configured to attract a receiver magnet disposed under a scalp of a user;
a microphone, disposed in the housing and configured to receive an external sound and generate a sound signal corresponding
to the external sound;

a processing circuit, disposed in the housing and configured to convert the sound signal into an electrode driving signal;
a wireless signal transmitter circuit, disposed in the housing and configured to transmit the electrode driving signal to
a cochlear implant device in the cochlear system;

a power management circuit, disposed in the housing and configured to generate a plurality of respective voltage levels capable
of being used by the microphone and the processing circuit; and

a charging coil, disposed in the housing and configured to transmit a charging signal generated according to the power management
circuit to the cochlear implant device for charging a power supply of the cochlear implant device,

wherein the cochlear implant device is configured to convert the electrode driving signal into a plurality of electrode currents,
and a plurality of electrical pulses are generated in a cochlear nerve of the user through a plurality of electrodes according
to the electrode currents.

US Pat. No. 9,627,050

MEMORY ACCESS MODULE FOR PERFORMING MEMORY ACCESS MANAGEMENT

Silicon Motion Inc., Hsi...

1. A memory access module for performing memory access management of a storage device comprising a plurality of storage cells,
the memory access module comprising:
sensing means for performing a plurality of sensing operations respectively corresponding to a plurality of different sensing
voltages in order to generate at least a first digital value of a storage cell, wherein each subsequent sensing operation
corresponds to a sensing voltage which is determined according to a result of the previous sensing operation;

processing means for using the first digital value to obtain soft information of a bit stored in the storage cell; and
decoding means for using the soft information to perform soft decoding.

US Pat. No. 9,600,408

DATA STORAGE DEVICE AND METHOD FOR FLASH BLOCK MANAGEMENT

SILICON MOTION, INC., Jh...

1. A data storage device, coupled to a host, comprising:
a flash memory, comprising a spare block pool and a data block pool, wherein the spare block pool comprises a plurality of
spare blocks, and the data block pool comprises a plurality of data blocks; and

a controller, receiving target data from the host, writing the target data to a current programming data block, determining
whether a current programming page is a first page of the current programming data block, wherein the current programming
page is a physical page, determining whether data move information is set when the current page is not the first page, and
when the data move information is set, performing a data move process according to the data move information within a limited
time period, wherein the limited time period is determined by a standard for data transmission between the data storage device
and the host, wherein the data move process is a data merge process.

US Pat. No. 10,153,048

METHOD AND APPARATUS FOR READING DATA STORED IN FLASH MEMORY BY REFERRING TO BINARY DIGIT DISTRIBUTION CHARACTERISTICS OF BIT SEQUENCES READ FROM FLASH MEMORY

Silicon Motion Inc., Hsi...

7. A memory controller for reading data stored in a flash memory, comprising:a receiving circuit, arranged for obtaining codeword read from a plurality of memory cells of the flash memory, respectively;
a control logic, coupled to the receiving circuit, the control logic arranged for performing a plurality of read operations upon each of the memory cells; and
an error correction code (ECC) circuit, coupled to the control logic, for determining whether the codeword have uncorrectable error bits;
wherein when the ECC circuit corrects the codeword successfully, the ECC circuit directly outputs corrected codeword; and when the ECC circuit fails to correct the codeword read from the memory cells, the control logic performs a plurality of read operations upon each of the memory cells of the flash memory to obtain a plurality of bit sequences respectively corresponding the memory cells, and determines readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.

US Pat. No. 10,089,174

FLASH MEMORY CONTROLLER AND MEMORY DEVICE FOR ACCESSING FLASH MEMORY MODULE, AND ASSOCIATED METHOD

Silicon Motion Inc., Hsi...

1. A method for accessing a flash memory module, wherein the flash memory module is a 3D flash memory module, and the method comprises:sequentially writing Nth-(N+K)th data to floating gate transistors of different word line groups of each of a plurality of flash memory chips of the flash memory module, wherein each of the word line groups comprises a plurality of word lines, and encoding the Nth-(N+K)th data to generate Nth-(N+K)th error correction codes (ECCs), respectively, where the Nth-(N+K)th ECCs are used to correct errors of the Nth-(N+K)th data, respectively, and N and K are positive integers;
writing (N+K+1)th data to floating gate transistors of another word line group of each of the plurality of flash memory chips of the flash memory module, and encoding the (N+K+1)th data with at least one of the Nth-(N+K)th ECCs, to generate (N+K+1)th ECC;
writing the (N+K+1)th ECC, or writing the (N+K)th ECC and (N+K+1)th ECC, to a specific block of the flash memory module that is different from block(s) storing the Nth-(N+K+1)th data, and deleting the Nth-(N+K?1)th ECCs from the 3D flash memory module;
reading specific data from the block(s) of the flash memory module, wherein the specific data is not the (N+K)th data or the (N+K+1)th data; and
when an error that is uncorrectable when reading the specific data, reading the (N+K+1)th ECC stored in the specific block, or reading the (N+K)th and the (N+K+1)th ECC stored in the specific block, to perform error correction upon the specific data.

US Pat. No. 9,304,686

DATA STORAGE DEVICE AND DATA TRIMMING METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of blocks, wherein each of the blocks comprises a plurality of pages, and each of the
pages comprises a plurality of data trimming units which is a smallest unit for data modification; and

a controller, after a data trimming process has been performed on an address range of the flash memory, determining a last
page corresponding to an ending address of the address range, determining whether data values stored in the last page with
addresses subsequent to the ending address are all equal to a specific data pattern, and setting the value of a trimming flag
corresponding to the last page to be 1 when the data values stored in the last page with addresses subsequent to the ending
address are all equal to the specific data pattern, wherein the specific data pattern has a predetermined value.

US Pat. No. 9,251,454

STORAGE MEDIUM, TRANSMITTAL SYSTEM AND CONTROL METHOD THEREOF

Silicon Motion, Inc., Jh...

13. A control method for a storage medium comprising a transmittal module comprising a plurality of transmittal pads, comprising:
receiving an operation voltage; and
determining whether a level state of the transmittal module is equal to a pre-determined state, wherein when the level state
is equal to the pre-determined state, a SD mode is entered into, and when the level state is not equal to the pre-determined
state, an eMMC mode is entered into, wherein in the SD mode, the transmittal module is not utilized to communicate with a
processing device, and in the eMMC module, the transmittal module is utilized to communicate with the processing device.

US Pat. No. 10,110,255

METHOD FOR ACCESSING FLASH MEMORY MODULE AND ASSOCIATED FLASH MEMORY CONTROLLER AND MEMORY DEVICE

Silicon Motion Inc., Hsi...

1. A method for accessing a flash memory module, wherein the flash memory module is a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip is a 3D flash memory chip, each flash memory chip includes a plurality of blocks, each block includes a plurality of data pages and includes a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, the floating transistors on each bit line forms at least one page among the plurality of data pages, and the method comprises:configuring the flash memory chips to set at least one first super block and at least one second super block of the flash memory chips;
allocating the at least one second super block to store temporary parity check codes generated by an encoding procedure during programming data into the at least one first super block;
reading a plurality of temporary parity check codes from the second super block;
generating a plurality of final parity check codes according to the temporary parity check codes, wherein each final parity check code is generated by using the temporary parity check codes corresponding to the data stored in nonadjacent word line groups of the first super block, and each word line group has a plurality of word lines; and
writing the plurality of final parity check codes into the first super block.

US Pat. No. 9,940,983

CHANNEL CONTROLLING DEVICE FOR IMPROVING DATA READING EFFICIENCY

Silicon Motion Inc., Hsi...

1. A channel controlling device, comprising:a multiplexing circuit, coupled to multiple channels and arranged to refer to a selection signal to select a particular channel from the channels to output a channel data selection signal, wherein the channels are corresponding to multiple predetermined digital numbers, respectively;
a sorting circuit, arranged to refer to a data output order of the channels to sort the predetermined digital numbers, in order to convert the predetermined digital numbers into multiple sorted digital numbers; and
an arbitration circuit, arranged to refer to the sorted digital numbers to determine the selection signal.

US Pat. No. 9,690,695

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory, providing storage space divided into a plurality of blocks with each block comprising a plurality of pages;
and

a controller, operating the FLASH memory in accordance with commands issued from a host,
wherein:
the controller updates a logical-to-physical address mapping table between the host and the FLASH memory in accordance with
a first group count of a first buffer block selected from the plurality of blocks of the FLASH memory;

the first group count reflects a first logical address distribution of write data buffered in the first buffer block and with
non-updated logical-to-physical address mapping information;

the higher the first group count, the more dispersed the first logical address distribution showing distribution of logical
addresses of the write data buffered in the first buffer block and with non-updated logical-to-physical address mapping information;

the controller divides each page of the logical-to-physical address mapping table into X entries for storage of physical address
information of X logical addresses;

X is a number;
X logical addresses, sharing one page for recording the logical-to-physical address mapping information thereof, are classified
as belonging to one group;

the controller uses 2nd to Nth buffer blocks selected from the plurality of blocks of the FLASH memory as well as the first buffer block to buffer write
data, and N is a number;

the controller further updates the logical-to-physical address mapping table in accordance with the 2nd to Nth group counts of the 2nd to Nth buffer blocks;

the 2nd to Nth group counts reflect the 2nd to Nth logical address distributions showing distribution of logical addresses of write data buffered in the 2nd to Nth buffer blocks and with non-updated logical-to-physical address mapping information;

for the 2nd to Nth group counts a higher count value means that the logical address distribution corresponding thereto is more dispersed; and

when write data issued from the host has a logical address belonging to a group not counted in the first to Nth group counts et and a minimum group count among the first to Nth group counts is less than a threshold value the controller uses the buffer block having the minimum group count to buffer
the write data and adds one to the minimum group count.

US Pat. No. 9,159,451

TESTING SYSTEM AND TESTING METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A testing system for a wafer having a plurality of flash memory dies, comprising:
a testing apparatus, providing a testing requirement; and
a probe card coupled to the testing apparatus via a specific transmission line, comprising:
a plurality of probes, contacting with at least one of the flash memory dies of the wafer; and
a controller, writing a testing data to the flash memory die according to the testing requirement, and reading the testing
data from the flash memory die via the probes,

wherein the controller provides a testing result to the testing apparatus according to the read testing data,
wherein the controller performs an error checking and correcting procedure for the read testing data, to obtain the testing
result.

US Pat. No. 9,847,134

DATA STORAGE DEVICE AND VOLTAGE PROTECTION METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, arranged to store data;
a voltage detection device, arranged to detect a supply voltage received by the data storage device; and
a controller, configured to receive write commands from a host, and operate in a prohibition mode when the supply voltage
is outside a predetermined range, wherein the write command is arranged to enable the controller to write data into the flash
memory, and the controller is configured to disable all of the write commands received from the host while in the prohibition
mode.

US Pat. No. 9,786,379

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of pages and a plurality of word lines, wherein each of the word lines controls at
least two of the pages; and

a controller, reading a first page of the pages in response to a read command, wherein the first page is controlled by a first
word line of the word lines, and the controller closes the first word line when a predetermined condition is satisfied, wherein
the predetermined condition comprises that the first page cannot be successfully read.

US Pat. No. 9,779,022

METHODS FOR CACHING AND READING DATA TO BE PROGRAMMED INTO A STORAGE UNIT AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for caching and reading data to be programmed into a storage unit, performed by a processing unit, comprising:
receiving a write command for programming at least a data page into a first address from a master device via a first access
interface;

determining whether a block of data to be programmed has been collected, wherein the block contains a specified number of
pages; and

storing the data page in a DRAM (Dynamic Random Access Memory) and updating cache information to indicate that the data page
has not been programmed into the storage unit, and to also indicate the location of the DRAM caching the data page when the
block of data to be programmed has not been collected,

wherein the step for updating cache information to indicate that the page of data has not been programmed into the storage
unit, and to also indicate the location of the DRAM caching the page of data further comprises:

inserting a record comprising the first address, and a second address of the DRAM caching the data page.

US Pat. No. 9,760,433

FLASH MEMORY CONTROL APPARATUS UTILIZING BUFFER TO TEMPORARILY STORING VALID DATA STORED IN STORAGE PLANE, AND CONTROL SYSTEM AND CONTROL METHOD THEREOF

Silicon Motion Inc., Hsi...

1. A flash memory control apparatus, comprising:
a data read/write interface, arranged for coupling a first flash memory and a second flash memory, wherein the first flash
memory comprises a first storage plane and a first buffer, and the second flash memory comprises a second storage plane and
a second buffer; and

a controller, coupled to the data read/write interface;
wherein when the read/write interface couples the first flash memory and the second flash memory, the controller is arranged
to temporarily store a plurality of valid data sets stored in the first storage plane into the second buffer through the data
read/write interface; each of the plurality of valid data sets has a plurality of data bits; a data size of the plurality
of valid data sets stored in the first storage plane is less than or equal to a storage capacity of the second buffer; and
after an erase cycle is performed on the first storage plane, the controller further programs the plurality of valid data
sets temporarily stored in the second buffer into the first storage plane.

US Pat. No. 9,508,436

METHOD FOR READING DATA STORED IN A FLASH MEMORY ACCORDING TO A PHYSICAL CHARACTERISTIC AND MEMORY CONTROLLER AND SYSTEM THEREOF

Silicon Motion, Inc., Jh...

1. A method for reading data stored in a flash memory, wherein the flash memory comprises a plurality of memory cells and
each memory cell has a particular threshold voltage, the method comprising:
reading a first group of the memory cells for obtaining a first physical characteristic of the first group of the memory cells;
reading a second group of the memory cells for obtaining a second physical characteristic of the second group of the memory
cells, wherein the second physical characteristic is different from the first physical characteristic, and at least a part
of the first group of the memory cells are the same as at least a part of the second group of the memory cells; and

performing at least one read operation of the flash memory upon the first group of the memory cells according to the second
physical characteristic.

US Pat. No. 9,075,709

FLASH MEMORY CONTROLLER

Silicon Motion, Inc., Zh...

1. A flash memory controller comprising:
a communication interface for receiving a first data, a second data, and a third data;
a recording medium for recording an amount of stored data in a flash memory module, wherein the flash memory module comprising
a read and write circuit, a first data block, a second data block, and a third data block; and

a processing circuit, coupled with the communication interface, the recording medium, and the flash memory module, for controlling
the read and write circuit to configure program threshold voltages of at least one cell in the first data block to be within
a first voltage range so as to write the first data into the first data block when the amount of stored data in a flash memory
module is less than a first threshold, and for controlling the read and write circuit to configure program threshold voltages
of at least one cell in the third data block to be within a second voltage range so as to write the third data into the third
data block when the amount of stored data in the flash memory module is greater than a second threshold;

wherein the second threshold is greater than the first threshold and the first voltage range is less than the second voltage
range.

US Pat. No. 9,069,972

SECURE DIGITAL CARD, AND SECURE DIGITAL CARD SYSTEM AND OPERATING METHOD

Silicon Motion, Inc., Jh...

1. A Secure Digital card, comprising:
a Flash memory, providing a data storage space and a Content Protection Recorded Media Support Space; and
a controller, executing a firmware and providing read/write commands that a host outputs to the Content Protection Recorded
Media support space as security commands such that operate a Content Protection Recorded Media mechanism over the data storage
space, wherein:

the Content Protection Recorded Media support space includes a security command representative space representative of the
security commands, and each space cell of the security command representative space corresponds to one of the security commands;
and

the security command representative space includes:
a first space cell, corresponding to a Get Media Key Block command;
a second space cell, corresponding to a Get Media ID command;
a third space cell, corresponding to a First Random Number Set command in an Authentication and Key Exchange process;
a fourth space cell, corresponding to a Second Random Number Get command in the Authentication and Key Exchange process;
a fifth space cell, corresponding to a Second Response Value Set command in the Authentication and Key Exchange process;
a sixth space cell, corresponding to a First Response Value Get command in the Authentication and Key Exchange process;
a seventh space cell, corresponding to a Change Secure Area command;
an eighth space cell, corresponding to a Secure Erase command;
a ninth space cell, corresponding to a Secure Write Multi-blocks command;
a tenth space cell, corresponding to a Secure Write Media Key Block command; and
an eleventh space cell, corresponding to a Secure Read Multiblocks command.

US Pat. No. 9,588,709

FLASH MEMORY CONTROLLER

Silicon Motion Inc., Hsi...

1. A flash memory controller for controlling a flash memory module, wherein the flash memory module comprises a read and write
circuit and a plurality of data blocks, the flash memory controller comprising:
a communication interface for receiving data from a host device; and
a processing circuit, coupled with the communication interface and the flash memory module, for dynamically determining a
one-bit-per-cell mode or a multiple-bit-per-cell mode according to an amount of stored data in the flash memory module, and
using the determined one-bit-per-cell mode or the determined multiple-bit-per-cell mode to write the data into a target data
block of the plurality of data blocks of the flash memory module.

US Pat. No. 9,552,012

FREQUENCY CALIBRATION METHOD APPLICABLE IN UNIVERSAL SERIAL BUS DEVICE AND RELATED UNIVERSAL SERIAL BUS DEVICE

Silicon Motion Inc., Hsi...

1. A frequency calibration method applicable in a Universal Serial Bus (USB) device, the frequency calibration method comprising:
coupling the USB device to a USB host;
utilizing the USB device to receive a polling low frequency periodic signal from the USB host;
determining a host type of the USB host according to the polling low frequency periodic signal; and
calibrating a programmable oscillator of the USB device according to a specific clock period corresponding to the host type,
to make the programmable oscillator generate a target oscillating signal having a predetermined frequency;

wherein the step of determining the host type of the USB host according to the polling low frequency periodic signal comprises:
extracting a low frequency clock signal corresponding to the polling low frequency periodic signal;
controlling the programmable oscillator to generate an oscillating signal;
adjusting the oscillating signal of the programmable oscillator to serve as a coarsely-adjusted oscillating signal according
to a pulse width time of the low frequency clock signal;

utilizing the coarsely-adjusted oscillating signal of the programmable oscillator to calculate a pulse period of the low frequency
clock signal;

calculating a ratio of the pulse period and the pulse width time; and
determining the host type of the USB host according to the ratio.

US Pat. No. 9,490,022

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of blocks, wherein each of the blocks comprises a plurality of pages;
a voltage source, providing the flash memory an operation voltage; and
a controller, determining whether the operation voltage was lower than a predetermined voltage level during a predetermined
operation after the predetermined operation on the flash memory is finished, and enabling the flash memory to initialize when
the operation voltage was lower than the predetermined voltage level during the predetermined operation.

US Pat. No. 9,778,867

DATA MAINTENANCE METHOD FOR ERROR CORRECTION AND DATA STORAGE DEVICE USING THE SAME

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, having a plurality of single-level-cell units and a plurality of triple-level cell units; and
a controller, performing a predetermined number of read processes on a predetermined number of specific single-level-cell
units of the single-level-cell units to program data of the predetermined number of specific single-level-cell units into
a specific triple-level cell unit of the triple-level cell units, checking whether the specific triple-level cell unit can
be read successfully after the predetermined number of specific single-level-cell units are programmed into the specific triple-level
cell unit, and determining whether any of the predetermined number of specific single-level-cell units has not been read successfully
by any of the read processes when the specific triple-level cell unit cannot be read successfully.

US Pat. No. 9,692,399

DIGITAL DELAY UNIT AND SIGNAL DELAY CIRCUIT

SILICON MOTION, INC., Jh...

1. A digital delay unit, comprising:
an inverter to receive a first signal;
a first signal input terminal coupled to a first input terminal of a first NAND gate;
the first NAND gate having a second input terminal coupled to an output terminal of the inverter;
a second NAND gate, having a first input terminal coupled to an output terminal of the first NAND gate;
a third NAND gate, having a first input terminal coupled to an output terminal of the second NAND gate, and a second input
terminal coupled to a second signal input terminal; and

a fourth NAND gate having a first input terminal to receive the first signal, a second input terminal to receive a second
signal, and an output terminal coupled to a second input terminal of the second NAND gate,

wherein when the first signal input terminal receives an input signal that is a clock signal, a logic level of the first signal
is set to be 0 and the logic level of the second signal input terminal is set to be 1, and when the input signal is sent to
the digital delay unit via the second signal input terminal, the logic level of the first signal is set to be 1, and a logic
level of the second signal is set to be 1.

US Pat. No. 9,690,661

NON-VOLATILE MEMORY DEVICES AND CONTROLLERS

SILICON MOTION, INC., Jh...

1. A non-volatile memory device comprising:
a non-volatile memory divided into a plurality of physical blocks, wherein each physical block is divided into a plurality
of physical pages; and

a connection interface connected to a host; and
a controller,
wherein the controller selects one physical block from the plurality of physical block to serve as an operation physical block,
and when receiving a write command from the host, the controller writes data corresponding to the write command into the operation
physical block,

wherein when the controller performs a data read operation to read the operation physical block, if the data read operation
is failed, the controller enables retry machine by using different potentials,

wherein when the controller performs a recovery operation after an abnormal status occurs, the controller cancels the retry
machine and reads the physical page in the operation physical block which is written finally at the last time, and checks
a verification code of the physical page, and

wherein when check result of the verification code represents that an error occurs, the controller enables the retry machine
by using different potentials to retry to read the physical page and re-programming the physical page.

US Pat. No. 9,606,733

DATA STORAGE DEVICE AND OPERATING METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a FLASH memory, comprising a plurality of blocks wherein each of the blocks comprises a plurality of pages; and
a controller, coupled to the FLASH memory and utilized to execute a garbage-collection process on the FLASH memory according
to a number of spare blocks in the FLASH memory and a number of inefficient blocks where most of the pages are spare in the
FLASH memory, wherein the garbage-collection process is utilized for merging at least two inefficient blocks to release at
least one spare block from the inefficient blocks, and the garbage-collection process is executed according to a number of
threshold values rather than only one threshold value, wherein the controller determines that:

the FLASH memory is in a first state when the number of inefficient blocks is less than a first threshold value;
the FLASH memory is in a second state when the number of spare blocks in the FLASH memory is more than or equal to a second
threshold value; and

the FLASH memory is in a third state when the number of spare blocks in the FLASH memory is more than or equal to a third
threshold value but less than the second threshold value.

US Pat. No. 9,513,995

METHODS FOR ACCESSING A STORAGE UNIT OF A FLASH MEMORY AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for accessing a storage unit of a flash memory, performed by a processing unit, comprising:
after receiving a notification indicating that errors presented in a message of a sector within a RAID (Redundant Array of
Independent Disk) group cannot be fixed by an error correction algorithm with a horizontal ECC (Error Correction Code) of
the sector, determining addresses of the other sectors within the RAID group;

providing a first information to a sector-decoding unit and a RAID-decoding unit, which indicates that a vertical correction
procedure has been activated, wherein the sector-decoding unit, after receiving the first information from the processing
unit, decodes the content read by the storage-unit access interfaces and transmits the decoded results to the RAID-decoding
unit;

directing a plurality of storage-unit access interfaces to read content from the determined addresses of the storage unit,
thereby enabling the RAID-decoding unit to recover the message of the sector by using the read content; and

after the decoded results for the other sectors has been completely transmitted to the RAID-decoding unit, providing a second
information to the RAID-decoding unit, which indicates that the vertical correction procedure ends, wherein the RAID-decoding
unit, after receiving the second information, stores a decoded result corresponding to the previously received data for the
RAID group from the sector-decoding unit to a buffer, and the decoded result corresponding to the previously received data
for the RAID group is considered as the message of the sector.

US Pat. No. 10,004,137

PRINTED CIRCUIT BOARD ASSEMBLY

SILICON MOTION, INC., Jh...

1. A printed circuit board assembly, comprising:a substrate, comprising:
a first cap-insulation layer;
a second cap-insulation layer;
a plurality of conductive layers, vertically sandwiched between the first cap-insulation layer and the second cap-insulation layer, wherein the substrate has a first part, a second part and a third part, and the second part is laterally sandwiched between the first part and the third part along a longitudinal direction, wherein for protecting the conductive layers from moisture, each of the areas of the conductive layers corresponding to the second part is smaller than the area of the first cap-insulation layer corresponding to the second part for at least a first predetermined percentage, and each of the areas of the conductive layers corresponding to the second part is smaller than the area of the second cap-insulation layer corresponding to the second part for at least the first predetermined percentage;
a first connector implemented in the first part; and
a second connector implemented in the third part, wherein the first cap-insulation layer and the second cap-insulation layer has a plurality of vias, wherein the region under the first connector is a first region, the region under the second connector is a second region, and the region except for the first region and the second region in the first part, the second part and the third part is a third region, wherein density of the vias on the first cap-insulation layer corresponding to the second region and density of vias on the second cap-insulation layer corresponding to the second region are larger than density of the vias on the first cap-insulation layer corresponding to the third region and density of vias on the second cap-insulation layer corresponding to the third region.

US Pat. No. 10,002,673

FLASH MEMORY DATA STORAGE DEVICE AND PROGRAMMING METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A detection method for detecting a programming operation of a flash memory, comprising:issuing a program command of the programming operation to the flash memory, by a controller;
issuing a first read status command to the flash memory, by the controller, before a page program time of the flash memory has been reached;
determining whether the programming operation is performed in the flash memory according to a first memory status corresponding to the first read status command provided by the flash memory;
issuing a second read status command to the flash memory after exceeding the page program time of the flash memory when determining that the programming operation is being performed in the flash memory, by the controller; and
determining whether the programming operation has succeeded according to a second memory status provided by the flash memory and corresponding to the second read status command.

US Pat. No. 9,846,643

METHODS FOR MAINTAINING A STORAGE MAPPING TABLE AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for maintaining a storage mapping table, performed by a processing unit, comprising:
directing an access interface to read a group mapping table from the last page of a block of a storage unit, wherein the block
is allocated to store data of a plurality of groups, each group stores information indicating which location in the storage
unit stores data of an LBA (Logical Block Address) range, and the group mapping table stores information indicating which
unit of the block stores the latest data of each group; and

storing the group mapping table to a DRAM (Dynamic Random Access Memory);
directing the access interface to read data of each group from the storage unit according to the group mapping table; and
storing the data of each group in a specified location of a storage mapping table of the DRAM,
wherein, in the step of storing the data of each group in a specified location of a storage mapping table of the DRAM further
comprises:

storing data of the groups of the storage mapping table into the DRAM according to the order of the LBAs.

US Pat. No. 9,747,173

DATA STORAGE DEVICES AND DATA MAINTENANCE METHODS

SILICON MOTION, INC., Jh...

1. A data storage device comprising:
a flash memory comprising a plurality of blocks, wherein each block comprises a plurality of pages; and
a controller, when the data storage device is resumed from a power-off event, selecting a first block which was written last
before the power-off event among the plurality of blocks and writing data of a plurality of first pages of the first block
into a plurality of second pages of the first block.

US Pat. No. 9,684,568

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages; and
a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein:
the microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory
to record mapping information between the host and the flash memory, allocates the blocks of the flash memory to provide a
system block, and records a link table indicator in the system block to indicate a position of the link table;

the link table indicates positions of the plurality of logical-to-physical address mapping tables, each entry in the link
table corresponds to one logical-to-physical address mapping table; and

wherein the microcontroller erases user data of logical addresses corresponding to N logical-to-physical address mapping tables
by downloading the link table from the flash memory to the random access memory, invalidating N entries corresponding to the
N logical-to-physical address mapping tables in the link table on the random access memory, uploading the link table with
the N entries of invalid data back to the flash memory, and updating the system block with an updated link table indicator,
where N is an integer.

US Pat. No. 9,111,586

STORAGE MEDIUM AND TRANSMITTAL SYSTEM UTILIZING THE SAME

Silicon Motion, Inc., Jh...

1. A storage medium comprising:
a processing module receiving test data according to a write command;
a cell array storing the test data, and
wherein the processing module receives verify data according to a comparison command, reads the test data stored in the cell
array to generate access data, and compares the access data with the verify data to generate a compared report,

wherein the processing module comprises:
a logic decoder unit decoding the write command to generate a first control signal and decoding the comparison command to
generate a second control signal;

an accessing unit writing the test data into the cell array according to the first control signal and retrieving the test
data stored in the cell array according to the second control signal;

a comparing unit comparing each bit of the access data and each bit of the verify data one by one to generate the compared
report; and

a register unit storing the compared report.

US Pat. No. 9,996,304

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a flash memory, comprising a plurality of chips, a plurality of channel select lines and a plurality of chip select lines, wherein each of the chips has a plurality of pages, and the chips are arranged in a matrix, the channel select lines are arranged to select columns of the matrix, the chip select lines are arranged to select rows of the matrix, the pages of each of the chips are arranged to be assembled into a super block according to a predetermined order, and each of super blocks comprises the pages of different chips;
a plurality of counting control arrays, wherein each of the counting control arrays comprises a plurality of fields, the counting control arrays corresponds to one of the super blocks, each of the fields corresponds to one of a plurality of combinations of the chip select lines and the channel select lines that arranged to select the chips; and
a controller, reading a first counting control array corresponding to a first super block of the super blocks to obtain value of a first field corresponding to a first chip of the first counting control array when data of the first super block in the first chip is required to be read, wherein the controller keeps the value of the first field and writes a second value into other fields except of the first field of the first counting control array when the value of the first field is a first value, and writes the first value into the first field and maintain values of the other fields except for the first field of the first counting control array when the value of the first field is the second value.

US Pat. No. 9,899,104

RAID DECODING ARCHITECTURE WITH REDUCED BANDWIDTH

Silicon Motion Inc., Hsi...

1. A RAID decoding system for performing a Built in Self-Test (BIST), comprising:
an Error Insertion block for inserting errors into a first Reed-Solomon (RS) codeword and a second RS codeword; and
a RAID decoder, comprising:
a storage, for storing a syndrome of the first RS codeword, a syndrome of the second RS codeword, parity data of the first
RS codeword and parity data of the second RS codeword;

a first RS decoder for storing the first RS codeword and for performing decoding on the first RS codeword according to the
parity data of the first RS codeword to generate an updated syndrome of the first RS codeword;

a second RS decoder for storing the second RS codeword and for performing decoding on the second RS codeword according to
the parity data of the second RS codeword to generate an updated syndrome of the second RS codeword; and

a MUX, coupled between the storage and the first RS decoder and the second RS decoder, for inputting the first RS codeword
to the first RS decoder and inputting the second RS codeword to the second RS decoder in a first iteration, and for inputting
the parity data of the first RS codeword to the first RS decoder and inputting the parity data of the second RS codeword to
the second RS decoder in following iterations for updating the syndrome of the first RS codeword and the syndrome of the second
RS codeword;

wherein when the updated syndrome of the first RS codeword and the updated syndrome of the second RS codeword both equal zero,
the updated syndromes of the first RS codeword and the second RS codeword are used to perform error correction on the first
RS codeword and the second RS codeword to generate an error-corrected first RS codeword and an error-corrected second RS codeword.

US Pat. No. 9,720,820

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory; and
a controller, for management of a spare queue for the FLASH memory, blocks within the spare queue are entirely-erased,
wherein:
the controller further manages a jail queue to freeze blocks whose erase counts are greater than an overused higher threshold;
the controller performs a garbage collection operation with wear leveling when the blocks within the spare queue are less
than a clean threshold, any block within the spare queue has an erase count greater than an overused lower threshold, and
both of the following two specific conditions are; wherein:

one of the two specific conditions shows that the blocks frozen within the jail queue are more than a predetermined amount
and another of the two specific condition shows that the FLASH memory is in a power-cycle routine; and

when performing the garbage collection operation with wear leveling, the controller selects one block from higher erase count
blocks in the spare queue to collect valid data.

US Pat. No. 9,575,885

DATA STORAGE APPARATUS FOR SCRAMBLED DATA AND MANAGEMENT METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage apparatus, comprising:
a transmission interface;
a nonvolatile memory, wherein the nonvolatile memory is a flash memory comprising a plurality of physical blocks, the controller
records a mapping relation for mapping a plurality of logical blocks to the plurality of physical blocks;

a controller for recording a non-completed flag;
wherein when the controller receives a first initialization command via the transmission interface, the controller performs
a first initialization setting to the nonvolatile memory and sets the the non-completed flag as a non-completed status;

wherein when the controller receives a second initialization command via the transmission interface, the controller performs
a second initialization setting to the nonvolatile memory and sets the non-completed flag as a completed status;

wherein when the controller receives a write command via the transmission interface, write data are scrambled and then the
scrambled write data are written to the nonvolatile memory;

wherein when the non-completed flag indicates the non-completed status, if the controller receives a read command to the nonvolatile
memory via the transmission interface, no matter whether data associated to an indicated address of the read command are scrambled,
the controller descrambles the data associated to the indicated address and then provides the descrambled data associated
to the indicated address via the transmission interface;

wherein the controller records whether the physical block associated with each logical block is valid according to a valid
flag;

wherein only when the non-completed flag indicates the completed status, the controller determines whether to return the descrambled
data according to the valid flag.

US Pat. No. 10,048,870

ELECTRONIC SYSTEM AND DATA MAINTENANCE METHOD THEREOF

SILICON MOTION, INC., Jh...

1. An electronic system, comprising:a host; and
a data storage device, comprising:
a flash memory;
a controller, receiving a read command from the host, reading a first data sector from the flash memory according to the read command, and producing a setting signal according to a maintenance time of the flash memory when the flash memory needs to be maintained; and
a delay circuit, receiving the setting signal from the controller, dividing the first data sector into a plurality of first sub-data sectors according to the setting signal, and transmitting at least one of the first sub-data sectors to the host at a predetermined time interval for extending a busy time of the controller.

US Pat. No. 9,996,265

DATA STORAGE DEVICE AND DATA WRITING METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:a flash memory, having a plurality of TLC blocks, wherein each of the TLC blocks comprises a plurality of pages; and
a controller, checking whether any of the TLC blocks was undergoing a write operation which was unfinished at the time that the power-off event occurred when the data storage device resumes operation after a power-off event, wherein when a first TLC block was undergoing a write operation which was unfinished at the time that the power-off event occurred, the controller further checks whether data stored in a page which was the last one being written in the first TLC block can be successfully read, and continues to write the remaining data into the first TLC block when the data of the page which was the last one being written in the first TLC block can be successfully read.

US Pat. No. 10,164,656

BIT FLIPPING ALGORITHM FOR PROVIDING SOFT INFORMATION DURING HARD DECISION HARD DECODING

Silicon Motion Inc., Hsi...

1. A method for performing low-density parity check (LDPC) decoding, the method comprising:generating a look-up table (LUT) containing predetermined values linking a number of failed check nodes to a log-likelihood ratio (LLR) value;
inputting a codeword to a first decoder which operates in a hard decoding mode;
in a first iteration of the first decoder, decoding the codeword using a hard decoding algorithm to generate hard information by determining a number of failed check nodes and generating soft information by inputting the number of failed check nodes to the LUT to generate an LLR value;
performing a successive number of decoding iterations of the codeword in the first decoder using the hard decoding algorithm wherein in each iteration a number of failed check nodes is determined, and the number of failed check nodes is input to the LUT to generate an LLR value;
when a predetermined number of decoding iterations of the hard decoding algorithm is reached without parity check equations for the codeword being satisfied at check nodes, stopping decoding of the codeword using the first decoder, inputting the codeword to the second decoder and starting decoding of the codeword in the second decoder using a soft decoding algorithm and the LLR values generated by the LUT; or
when parity check equations for the codeword are satisfied at the check nodes before the predetermined number of decoding iterations of the hard decoding algorithm is reached, the decoded codeword is directly output without the second decoder being used.

US Pat. No. 10,042,756

METHODS FOR SCHEDULING READ COMMANDS AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for scheduling read commands, performed by a processing unit, comprising:receiving a logical read command from a master device via a first access interface, wherein the logical read command requests to read data of a logical address;
obtaining one of plurality of first physical storage locations of mapping segments that is associated with the logical address from a high-level mapping table, wherein a mapping table is divided into the mapping segments, the mapping segments are distributed to store in a plurality of storage sub-units and the storage sub-units provide non-volatile storage space;
directing a second access interface to read one designated mapping segment from the obtained first physical storage location of a designated storage sub-unit;
obtaining a second physical storage location associated with the logical address from the read mapping segment;
directing the second access interface to read data from the second physical storage location of the designated storage sub-unit; and
directing the first access interface to clock the data read from the obtained second physical storage location out to the master device.

US Pat. No. 9,990,280

METHODS FOR READING DATA FROM A STORAGE UNIT OF A FLASH MEMORY AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for reading data from a storage unit of a flash memory, performed by a processing unit, comprising:receiving a first read command from a master device via a first access interface;
determining whether data requested by the first read command has been cached in a first buffer, where the first buffer caches continuous data obtained from a storage unit; and
when data requested by the first read command has not been cached in the first buffer, directing a second access interface to read the data requested by the first read command from the storage unit and store the read data in a second buffer other than the first buffer to avoid the continuous data cached in the first buffer being overwritten, and directing the first access interface to read the data requested by the first read command from the second buffer and clock the read data out to the master device,
wherein the first and second buffers are physically separated memories or two continuous spaces of a physical memory, which are logically allocated,
wherein the second buffer stores fragment data rather than the continuous data, all blocks of the continuous data are associated with continuous addresses and at least two blocks of the fragment data are associated with discontinuous logical addresses.

US Pat. No. 10,163,499

METHOD FOR INCREASING SPEED OF WRITING DATA INTO FLASH MEMORY UNIT AND ASSOCIATED DEVICE

Silicon Motion Inc., Hsi...

1. A control device, arranged to write data into a flash memory unit, the control device comprising:a determining circuit, arranged to determine a data polarity of an n-th data bit of the flash memory unit when writing data into the flash memory unit for the n-th time; and
a writing circuit, arranged to inject an n-th electrical charge amount to a floating gate of the flash memory unit according to the data polarity of the n-th data bit only;
wherein the determining circuit is further arranged to determine the data polarity of an (n+1)-th data bit of the flash memory unit when writing data into the flash memory unit for the (n+1)-th time, the writing circuit is further arranged to selectively inject an (n+1)-th electrical charge amount to the floating gate of the flash memory unit according to the data polarity of the (n+1)-th data bit only, the (n+1)-th electrical charge amount is not equal to the n-th electrical charge amount, and n is a positive integer not smaller than 1.

US Pat. No. 9,875,032

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory;
a controller, receiving a read command from a host, reading a first data sector from the flash memory according to the read
command, and producing a setting signal according to a maintenance time of the flash memory when the flash memory needs to
be maintained; and

a delay circuit, receiving the setting signal from the controller, dividing the first data sector into a plurality of first
sub-data sectors according to the setting signal, and transmitting at least one of the first sub-data sectors to the host
at a predetermined time interval for extending a busy time of the controller.

US Pat. No. 9,859,792

SWITCHING-CAPACITOR REGULATOR WITH CHARGE INJECTION MODE FOR HIGH LOADING CURRENT

Silicon Motion Inc., Hsi...

1. A switching-capacitor regulator for generating an output voltage at an output node, comprising:
a storage capacitor;
a switch module, coupled between the storage capacitor, a first supply voltage, a second supply voltage and the output node,
and the switch module comprises:

a first switch, coupled to a first node of the storage capacitor, for selectively connecting the first supply voltage to the
first node of the storage capacitor;

a second switch, coupled between the first node of the storage capacitor and the output node, for selectively connecting the
first node of the storage capacitor to the output node;

a third switch, coupled between a second node of the storage capacitor and the output node, for selectively connecting the
second node of the storage capacitor to the output node; and

a fourth switch, coupled to the second node of the storage capacitor, for selectively connecting the second supply voltage
to the second node of the storage capacitor;

a current source, connected to the output node, for selectively providing a current to the output node; and
a control unit, coupled to the switch module and the output node, for referring to a voltage level of the output voltage to
control the switch module to selectively charge or discharge the storage capacitor, and to control the current source to selectively
provide the current to the output node, to adjust the output voltage;

wherein when the output voltage is greater than a first reference voltage, the control unit disables all of the first switch,
the second switch, the third switch, the fourth switch and the current source; when the output voltage is lower than the first
reference voltage and is greater than a second reference voltage, the control unit controls the first switch, the second switch,
the third switch and the fourth switch to alternately charge and discharge the storage capacitor, and the control unit disables
the current source; and when the output voltage is lower than the second reference voltage, the control unit controls the
first switch, the second switch, the third switch and the fourth switch to alternately charge and discharge the storage capacitor,
and the control unit enables the current source.

US Pat. No. 9,852,032

DATA STORAGE DEVICES AND DATA MAINTENANCE METHODS

SILICON MOTION, INC., Jh...

1. An electronic system, comprising:
a host; and
a data storage device, being operated according to a command from the host, wherein the data storage device comprises:
a flash memory comprising a plurality of blocks, wherein each block comprises a plurality of pages; and
a controller, when the data storage device is resumed from a power-off event, selecting a first block which was written last
before the power-off event among the plurality of blocks and writing data of a plurality of first pages of the first block
into a plurality of second pages of the first block.

US Pat. No. 9,766,974

DATA STORAGE DEVICE AND DATA ACCESS-METHOD

SILICON MOTION, INC., Jh...

1. A data-storage device, comprising:
a flash memory, comprising a plurality of blocks, and each of the blocks has a plurality of pages, wherein each of the pages
has a plurality of sub-pages and a plurality of spare areas, each of the spare areas is arranged to store a spare data sector,
and each of the spare data sectors corresponds to one of the sub-pages; and

a controller, arranged to access the sub-pages according to the spare data sectors,
wherein the minimum access unit of the flash memory is the sub-page, each of the spare data sectors comprises a metadata arranged
to record the information of the corresponding sub-page and an ECC parity of the metadata, and each of the sub-pages comprises
a data area and an ECC parity of the data area, wherein the metadata includes properties of data in the blocks, wherein the
properties include a mapping relationship of the physical sub-pages and the logical sub-pages, wherein one of the sub-pages
is directly accessed by an access command of the flash memory, and wherein when the data-storage device is powered on, the
controller reads data from at least one predetermined page stored in the flash memory for obtaining sizes of the blocks, pages,
and sub-pages based on different access modes.

US Pat. No. 9,645,895

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory including multi-level cells and single-level cells, wherein the flash memory is divided into a plurality of
blocks with each block comprising a plurality of pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,
wherein:
the microcontroller is configured to establish a first physical-to-logical address mapping table in the random access memory
for a first run-time write block between the blocks of the flash memory, and the first run-time write block contains multi-level
cells;

the microcontroller is further configured to establish a second physical-to-logical address mapping table in the random access
memory for a second run-time write block between the blocks of the flash memory, and the second run-time write block contains
single-level cells;

in response to data that was previously stored in the first run-time write block with mapping information in the first physical-to-logical
address mapping table, but not yet uploaded to the flash memory, being updated into the second run-time write block, the microcontroller
is configured to update a logical-to-physical address mapping table located in the flash memory in accordance with the first
physical-to-logical address mapping table.

US Pat. No. 9,563,550

FLASH STORAGE DEVICE AND CONTROL METHOD FOR FLASH MEMORY

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a FLASH memory, for data storage and further storing a logical-to-physical address mapping table and an access protection
mapping table, wherein the access protection mapping table shows access protection statuses of different logical addresses;
and

a controller, setting a physical address pointer corresponding to issued logical addresses in the logical-to-physical address
mapping table to zeros or redirecting the physical address pointer corresponding to the issued logical addresses in the logical-to-physical
address mapping table to an invalid physical space in accordance with logical addresses issued via a dynamic capacity management
request from a host to break a logical-to-physical mapping relationship of the issued logical addresses such that total amount
of spare blocks available in the FLASH memory is increased, and, asserting a flag, corresponding to the issued logical addresses,
in the access protection mapping table, to a access protected mode and, accordingly, adjusting an end-of-life judgment value,

wherein the logical addresses issued via the dynamic capacity management request is modified as access-protected and thereby
space allocation thereon is no more required, wherein the end-of-life judgment value is positively related to the total amount
of spare blocks available in the FLASH memory.

US Pat. No. 9,542,278

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, providing a storage space that is divided into a plurality of blocks with each block comprising a plurality
of physical pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,
wherein:
the microcontroller is configured to build a physical-to-logical address mapping table in the random access memory for a run-time
write block between the blocks of the flash memory;

the microcontroller is further configured to allocate the random access memory to provide a collection and update area for
logical-to-physical address mapping tables that correspond to logical addresses recorded into the physical-to-logical address
mapping table; and

when recording a logical address corresponding to a new logical-to-physical address mapping table that has not appeared in
the collection and update area into the physical-to-logical address mapping table, the microcontroller is further configured
to collect the new logical-to-physical address mapping table into the collection and update area and perform an update of
the new logical-to-physical address mapping table within the collection and update area.

US Pat. No. 10,102,904

MEMORY ACCESS MODULE FOR PERFORMING A PLURALITY OF SENSING OPERATIONS TO GENERATE DIGITAL VALUES OF A STORAGE CELL IN ORDER TO PERFORM DECODING OF THE STORAGE CELL

Silicon Motion Inc., Hsi...

1. A memory access module for performing memory access management of a storage device comprising a plurality of storage cells, wherein each storage cell has a number of possible bit(s) which directly corresponds to a number of possible states of the storage cell, the memory access module comprising:a read only memory for storing a program code; and
a microprocessor, coupled to the read only memory, for executing the program code to perform the following steps:
performing a plurality of sensing operations, wherein a first sensing operation corresponds to a first sensing voltage, and each subsequent sensing operation corresponds to a sensing voltage which is determined according to a result of the previous sensing operation;
using the plurality of sensing operations to generate a first digital value and a second digital value of a storage cell;
using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and
using the soft information to perform soft decoding.

US Pat. No. 9,990,996

FLASH MEMORY DATA STORAGE DEVICE AND PROGRAMMING METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a flash memory, comprising a memory array; and
a controller, performing a programming operation for the flash memory,
wherein after the controller issues a program command of the programming operation to the flash memory, the controller issues a first read status command to the flash memory before a page program time of the flash memory has been reached, and before the page program time of the flash memory has been reached, the controller determines whether the programming operation is performed in the flash memory according to a first memory status, wherein the first memory status is provided by the flash memory in response to the first read status command,
wherein when the controller determines that the programming operation is being performed in the flash memory, the controller issues a second read status command to the flash memory after exceeding the page program time of the flash memory, and the controller determines whether the programming operation has succeeded according to a second memory status provided by the flash memory.

US Pat. No. 9,852,062

MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME

SILICON MOTION, INC., Jh...

1. A memory controller comprising:
a first transmittal module transmitting data;
a specific pin coupled to a setting module;
a clock pin receiving a clock signal, wherein the first transmittal module and the clock pin constitute an embedded multimedia
card (eMMC) interface;

a second transmittal module transmitting data, wherein the second transmittal module and the clock pin constitute a universal
flash storage (UFS) interface;

a first control module communicating with an external host via the first transmittal module according to the clock signal
when a level of the specific pin is at a first level; and

a second control module communicating with the external host via the second transmittal module according to the clock signal
when the level of the specific pin is at a second level, wherein the first level exceeds the second level, wherein the clock
pin is shared by the first and second transmittal modules,

wherein when the first control module communicates with the external host via the first transmittal module, simultaneously,
the second control module stops working, and

wherein when the second control module communicates with the external host via the second transmittal module, simultaneously,
the first control module stops working, and

wherein each of the first and the second control modules receives a signal carried on the specific pin, but does not utilize
the specific pin to transmit or receive communications with the external host.

US Pat. No. 9,741,451

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of chips, each of the chips comprises a plurality of pages for storing data, the pages
of the chips are arranged to assemble into a super block according to a predetermined arrangement order, the pages of the
super block are numbered 0˜X from top to bottom, wherein the pages with number 0˜Y?1 constitute a data area and the pages
with numbers Y˜X constitute a RAID parity area, wherein X is an integer greater than 1, and Y is an integer greater than 1
and less than X; and

a controller, storing at least one parity code into the RAID parity area after all of the data is stored into the data area,
and performing an error correction to correct data of the data area of the flash memory by using data of the RAID parity area
when the controller cannot successfully read the data of the data area.

US Pat. No. 9,766,880

ELECTRONIC DEVICE AND METHOD FOR FIRMWARE UPDATING THEREOF

Silicon Motion, Inc., Jh...

1. A firmware update method, applied to a host device and a peripheral device, wherein the peripheral device comprises a memory
device and a controller, the firmware update method comprising:
transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector
has a first mode parameter and a first program code sector, wherein the first mode parameter represents that the first program
code sector has not been written into the memory device;

retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device
after an interruption event has occurred on the memory device during the transmission, wherein the second mode parameter represents
that the first program code sector has been written into the memory device;

replacing, by the host device, the first mode parameter of the first firmware data sector with the second mode parameter of
the first firmware data sector if the interruption event has occurred;

reading at least one parameter sector of the received first firmware data sector by the controller, wherein the parameter
sector of the first firmware data sector comprises one of the first mode parameter and the second mode parameter;

storing to the memory device the first program code sector of the first firmware data sector having the first mode parameter;
and

not storing the first program code sector of the first firmware data sector having the second first mode parameter.

US Pat. No. 9,613,708

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, comprising a plurality of pages and a plurality of word lines, wherein each of the word lines controls at
least two of the pages; and

a controller, reading a first page of the pages in response to a read command, wherein the first page is controlled by a first
word line of the word lines, and the controller further writes dummy data into the pages controlled by the first word line
other than the first page when a predetermined condition is satisfied, wherein the predetermined condition comprises that
the first word line is not close and the first page cannot be successfully read.

US Pat. No. 9,606,911

APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE

SILICON MOTION, INC., Zh...

1. A controller for managing a flash memory module, comprising:
a processing circuit configured for recording a plurality of address groups into a plurality of addressing blocks, wherein
the processing circuit writes each address group into a physical page of one of the plurality of addressing blocks, and each
of the plurality of address groups containing a plurality of address mapping information respectively corresponding to a plurality
of sequential logical addresses; and

a communication interface for coupling with the processing circuit for receiving a write command with respect to a target
logical address from a host device;

wherein the processing circuit writes the target logical address and associated data into a destination page of a target data
block, retrieves the address mapping information for the target logical address from the plurality of address groups, updates
the retrieved address mapping information based on physical location information of the destination page of the target data
block, and writes a target address group containing updated address mapping information for the target logical address into
a target page of a target addressing block,

wherein the processing circuit records N group numberings of N address groups stored in a first addressing block in a physical
page of the first addressing block, and

wherein the processing circuit is further configured for:
setting an initial valid group count of the first addressing block;
comparing recorded allocation information for the N address groups with allocation information for the N address groups obtained
based on the N group numberings; and

adjusting the initial valid group count based on the comparing results to obtain a valid group count of the first addressing
block.

US Pat. No. 9,569,126

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, providing a storage space that is divided into a plurality of physical blocks with each physical block further
divided into a plurality of physical pages; and

a control unit, comprising a microcontroller and a random access memory,
wherein:
the microcontroller is configured to generate command sequence information for write data, and further allocates the random
access memory for temporary storage of the write data and the command sequence information;

the microcontroller is further configured to upload the write data onto a run-time write block between the physical blocks
of the flash memory with the command sequence information corresponding thereto; and

the microcontroller is further configured to check the run-time write block during a power recovery process of the data storage
device and, based on the command sequence information that has been uploaded onto the run-time write block, the write data
in the run-time write block and later in a command sequence than lost data is abandoned.

US Pat. No. 9,563,551

DATA STORAGE DEVICE AND DATA FETCHING METHOD FOR FLASH MEMORY

SILICON MOTION, INC., Jh...

1. A data storage device, coupled to a host, the data storage device comprising:
a flash memory; and
a controller, configured to control accessing of the flash memory;
wherein when the host performs random data accessing of the flash memory, the controller retrieves address information of
a corresponding block and a corresponding page in the flash memory associated with first data to be read based on a global
mapping table of the controller, and pre-fetches the corresponding page from the flash memory based on the address information;

wherein after the controller retrieves the address information, the controller further determines whether the first data to
be read is located in a current buffer block of the flash memory based on a local mapping table of the controller while the
controller is pre-fetching the corresponding page from the memory based on the address information;

wherein the pre-fetched corresponding page is stored in a buffer of the controller,
wherein when the first data is located in the current buffer block, the controller directly reads the first data from the
current buffer block, and

wherein when the first data is not located in the current buffer block, the controller directly obtains the first data from
the pre-fetched corresponding page stored in the buffer of the controller.

US Pat. No. 10,133,664

METHOD, FLASH MEMORY CONTROLLER, MEMORY DEVICE FOR ACCESSING 3D FLASH MEMORY HAVING MULTIPLE MEMORY CHIPS

Silicon Motion Inc., Hsi...

1. A method for accessing a flash memory module, the flash memory module being a 3D NAND-type flash memory module including a plurality of flash memory chips, each flash memory chip including a plurality of blocks which include a plurality of multiple-level cell blocks, each block including a plurality of data pages and including a plurality of word lines respectively disposed on a plurality of different planes and a plurality of floating transistors controlled by a plurality of bit lines, floating transistors on each bit line forming at least one page among the plurality of data pages, and the method comprises:performing encoding upon data to generate at least one set of parity check codes, wherein the data is to be programmed into a super block of the flash memory chips and the super block includes one multiple-level cell block of each flash memory chip among the flash memory chips;
programming the data into the super block;
writing and buffering the at least one set of parity check codes into a buffer memory; and
reading the at least one set of parity check codes from the buffer memory, then encoding the at least one set of parity check codes to generate at least one set of final parity check codes, and then programming the at least one set of final parity check codes into a plurality of data pages of one flash memory chip of the super block;
wherein each flash memory chip of the 3D NAND-type flash memory module has a plurality of 3D stacked planes; all word lines disposed on a same 3D stacked plane are classified into a same word line set all word line sets are classified into a group of multiple odd word line sets and a group of multiple even word line sets; and, the at least one set of parity check codes is generated for data disposed on particular word lines associated with a same order respectively comprised within different non-adjacent word line sets, the different non-adjacent word line sets being the multiple odd word line sets or the multiple even word line sets.

US Pat. No. 9,971,546

METHODS FOR SCHEDULING READ AND WRITE COMMANDS AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for scheduling read and write commands, performed by a processing unit, comprising:configuring a write timer and setting the write timer to a time period for a tolerable waiting time associated with write commands;
obtaining more than one read commands from a read queue successively and executing the obtained read commands for reading data from a storage unit via an access interface until a first condition is met;
after executing each read command, determining whether the write timer has reached the time period;
determining that the first condition is met when the write timer has reached the time period; and
after the first condition is met, obtaining more than one of the write commands from a write queue successively and executing the obtained write commands for programming data into the storage unit via the access interface until a second condition is met.

US Pat. No. 9,901,736

COCHLEA HEARING AID FIXED ON EARDRUM

Kuang-Chao Chen, New Tai...

1. A cochlea hearing aid device for helping user to hear, comprising:
a cochlea electrode, disposed at the cochlea of a user;
a driver circuit, comprising a casing that is configured to be installed at a through hole on the eardrum of the user, and
the driver circuit being electrically connected to cochlea electrode, wherein the driver circuit signal processes a voice
data in order to provide a corresponding driving signal for driving the cochlea electrode; and

a plurality of hand-held electronic apparatuses transmitting different wireless signals to the driver circuit respectively,
and the driver circuit synthesizing received wireless signals, wherein at least one of hand-held electronic apparatuses stores
a plurality of scenario parameters, and transmits a controlling signal to the driver circuit based on a selected scenario
parameter, wherein the driver circuit adjusts an output parameter of the cochlea electrode according to the controlling signal
transmitted by the hand-held electronic apparatus.

US Pat. No. 9,747,206

METHODS FOR REPROGRAMMING DATA AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for reprogramming data, performed by a processing unit, comprising:
after inspecting that a page of data has failed to be programmed into a first block of a storage unit, determining, by the
processing unit, whether the failed page is an upper page or a first lower page of the first block;

determining, by the processing unit, whether the page of data has failed to be programmed into the first block of the storage
unit;

when the failed page is the upper page of the first block, obtaining, by the processing unit, a host page number associated
with a second lower page of a plurality of memory cells of the first block of a wordline, wherein the memory cells comprises
the failed page;

when the failed page is the upper page of the first block, selecting, by the processing unit, a second block of the storage
unit; and

when the failed page is the upper page of the first block, directing, by the processing unit, an access interface to reprogram
data from the second lower page to the upper page of the first block into the second block of the storage unit, wherein at
least one intermediate page is present between the second lower page and the upper page of the first block, and the second
lower page, the intermediate page and the upper page are associated with consecutive host page numbers,

wherein the step for determining whether the page of data has failed to be programmed into the first block of the storage
unit further comprises

inspecting, by the processing unit, a register through the access interface to determine whether the page of data has failed
to be programmed into the first block of the storage unit, wherein the register is set by control circuits to notify the processing
unit an execution outcome associated with a programming of the page of data.

US Pat. No. 9,697,076

DATA STORAGE DEVICE AND ERROR CORRECTION METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data reading method, applied to a data storage device, wherein the data storage device comprises a flash memory capable
of operating in a SLC mode and a multi-level cell mode, the data reading method comprising:
reading a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host
to obtain a first data segment;

writing a predetermined data into a most-significant-bit page corresponding to the first word line in the multi-level cell
mode when the first data segment has an error;

reading the page corresponding to the first word line in the SLC mode again to obtain a second data segment.

US Pat. No. 10,310,746

METHOD, ASSOCIATED MEMORY DEVICE AND CONTROLLER THEREOF FOR PERFORMING DYNAMIC RESOURCE MANAGEMENT

Silicon Motion Inc., Hsi...

1. A method for performing dynamic resource management in a memory device, the memory device comprising a non-volatile (NV) memory, the NV memory comprising a plurality of NV memory elements, and the method comprising:storing a plurality of sets of physical region descriptor (PRD) information related to a plurality of host commands, respectively, and storing a plurality of intermediate PRDs respectively corresponding to the plurality of sets of PRD information into a first queue, wherein the plurality of host commands are received from outside the memory device, and any of the plurality of intermediate PRDs comprises an identifier (ID) of a set in the plurality of sets of PRD information;
obtaining an intermediate PRD of the plurality of intermediate PRDs from the first queue, and storing the intermediate PRD into a second queue;
sending a command to the NV memory according to the intermediate PRD in the second queue, to access data in at least one NV memory element of the plurality of NV memory elements; and
when an operation of accessing the data is successful, releasing the intermediate PRD from the second queue to the first queue.

US Pat. No. 10,235,075

FLASH MEMORY CONTROLLER

Silicon Motion Inc., Hsi...

1. A method for controlling a flash memory module, wherein the flash memory module comprises a plurality of blocks, and the method comprising:receiving data from a host device; and
determining if the data is cold data;
if it is determined that the data is the cold data, using at least four of program threshold voltage intervals to write the data into one of the blocks;
if it is determined that the data is not the cold data, referring to an amount of stored data in the flash memory module to select at least a portion of the program threshold voltage intervals to write the data into the one of the blocks.

US Pat. No. 9,870,321

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, providing a storage space that is divided into a plurality of physical blocks with each physical block further
divided into a plurality of physical pages; and

a control unit, comprising a microcontroller and a random access memory and coupled between a host and the flash memory,
wherein:
the microcontroller is configured to duplicate a last write page of a run-time write block between the plurality of physical
blocks during a power recovery process and thereby generate a duplicated page in the run-time write block;

the microcontroller is configured to use mapping information accessed from the duplicated page in rebuilding a physical-to-logical
address mapping table rather than mapping information accessed from the last write page;

the microcontroller is configured to maintain the physical-to-logical address mapping table on the random access memory for
the run-time write block;

the microcontroller is configured to update a logical-to-physical address mapping table in accordance with the physical-to-logical
address mapping table, and the logical-to-physical address mapping table is maintained in the flash memory; and

the microcontroller is configured to write dummy data into a next page with respect to the last write page during the power
recovery process to make the next page with respect to the last write page a dummy page.

US Pat. No. 9,852,068

METHOD AND APPARATUS FOR FLASH MEMORY STORAGE MAPPING TABLE MAINTENANCE VIA DRAM TRANSFER

Silicon Motion, Inc., Jh...

1. A method for maintaining a storage mapping table, performed by a processing unit, comprising:
after a total number of logical blocks, which exceeds a specified number, have been programmed into a storage unit, directing
an access interface to program a corresponding group of a storage mapping table of a DRAM (Dynamic Random Access Memory) into
a first block of the storage unit according to a group number of an unsaved group queue;

updating a group mapping table of the DRAM to indicate that the latest data of the group of the storage mapping table is stored
in which location in the storage unit; and

removing the group number from the unsaved group queue.

US Pat. No. 9,842,030

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, divided into a plurality of blocks with each block comprising a plurality of physical pages; and
a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,
wherein:
the microcontroller maintains a plurality of logical-to-physical address mapping tables and a link table on the flash memory
to record mapping information between the host and the flash memory and records a link table indicator on the flash memory
to indicate a position of the link table;

the link table indicates positions of the plurality of logical-to-physical address mapping tables, and each entry in the link
table corresponds to one logical-to-physical address mapping table; and

the microcontroller erases user data of logical addresses corresponding to N logical-to-physical address mapping tables by
downloading the link table from the flash memory to the random access memory, invalidating N entries corresponding to the
N logical-to-physical address mapping tables in the link table on the random access memory, uploading the link table with
the N entries of invalid data back to the flash memory, and records an updated link table indicator on the flash memory to
indicate a position of the uploaded link table on the flash memory, where N is an integer.

US Pat. No. 10,095,614

MEMORY CONTROLLER AND ACCESSING SYSTEM UTILIZING THE SAME

SILICON MOTION, INC., Jh...

1. A memory controller comprising:a first transmittal module transmitting data and comprising a specific pin;
a first clock pin receiving a first clock signal, wherein the first transmittal module and the first clock pin constitute an embedded multimedia card (eMMC) interface;
a second transmittal module comprising a receiving pin and a transmittal pin, wherein the receiving pin and the transmittal pin transmit data according to a serial method;
a first control module communicating with an external host via the first transmittal module when a level of the specific pin is at a first level; and
a second control module communicating with the external host via the second transmittal module when the level of the specific pin is at a second level, wherein the first level exceeds the second level, the first control module operates independently of the second control module, and the second control module operates independently of the first control module.

US Pat. No. 10,073,769

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

SILICON MOTION, INC., Jh...

13. A data storage device, comprising:a random access memory, having a cache area; and
a controller, loading a part of data mapping sets of a data mapping table on a plurality of sectors of the cache area, wherein when all of the sectors of the cache area are filled and a first data mapping set needs to be loaded on the cache area, the controller selects a first sector from the sectors according to an infrequent index set and loads the first data mapping set on the first sector, wherein when the infrequent index set does not correspond to any of the sectors, the controller transforms a frequent index set to the infrequent index set, and selects the first sector according to the transformed infrequent index set.

US Pat. No. 10,013,210

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a flash memory, having a plurality of Single-Level Cell (SLC)-spare blocks, a plurality of TLC-data blocks, and a plurality of Triple-Level Cell (TLC)-spare blocks; and
a controller, equally distributing the TLC-data blocks into three regions, the regions have the same number of TLC-data blocks, the controller further receives a prewrite data sector and a logic address of the prewrite data sector, and obtains a first sub-prewrite data sector, a second sub-prewrite data sector and a third sub-prewrite data sector according to the prewrite data sector and the logic address, wherein in a first stage, the controller further determines a first TLC-data block corresponding to the logic address according to the logic address, defines the region that contains the first TLC-data block as a first region, and determines whether the first TLC-data block has valid data, wherein in a first state, when the first TLC-data block does not have valid data, the controller respectively selects a second TLC-data block and a third TLC-data block from the regions other than the first region according to the first TLC-data block, respectively writes the first sub-prewrite data sector, the second sub-prewrite data sector and the third sub-prewrite data sector into the first TLC-data block, the second TLC-data block and the third TLC-data block by a SLC storage mode, and maps the first TLC-data block, the second TLC-data block and the third TLC-data block to the logic address.

US Pat. No. 9,933,958

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:a flash memory, comprising a plurality of blocks, wherein each of the blocks has a plurality of pages; and
a controller, receiving a write command which is arranged to write a plurality of data sectors into a plurality of first pages of a first block of the blocks, calculating an offset index according to a first erase count of the first block, retrieving a plurality of seeds from a random seed table according to the offset index, encoding the data sectors by using the retrieved seeds to obtain a plurality of encoded data sectors, and writing the encoded data sectors into the first pages.

US Pat. No. 9,727,271

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory including multi-level cells and single-level cells, wherein the flash memory is divided into a plurality of
blocks with each block comprising a plurality of physical pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,
wherein:
the microcontroller is configured to use the random access memory to cache data issued from the host before writing the data
into the flash memory;

the microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block
containing multi-level cells and a second run-time write block containing single-level cells; each physical page of data uploaded
from the random access memory to the first run-time write block contains sequential data;

random data cached in the random access memory to form one physical page is written into the second run-time write block;
and

when determining that a first physical page of data that has been uploaded from the random access memory to the second run-time
write block contains random data, the microcontroller is configured to write a second physical page of data, cached in the
random access memory after the first physical page of data, into the second run-time write block, before checking whether
the second physical page of data contains random or sequential data.

US Pat. No. 9,645,894

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, divided into a plurality of blocks with each block comprising a plurality of pages; and
a control unit, coupling the flash memory to a host and comprising a microcontroller,
wherein the microcontroller is configured to allocate the flash memory to provide a first block from the blocks to work as
a run-time write block for reception of write data and, during a power recovery process due to an unexpected power-off event
that interrupted write operations on the first block, the microcontroller is configured to allocate the flash memory to provide
a second block from the blocks for complete data recovery of the first block and to replace the first block as the run-time
write block, wherein the microcontroller is configured to allocate the flash memory to provide the first block as the run-time
write block when finishing writing of a table-outdated block between the blocks of the flash memory, the control unit further
comprises a random access memory, the microcontroller is configured to establish a physical-to-logical address mapping table
in the random access memory to record logical addresses corresponding to physical addresses of the table-outdated block, and
the microcontroller is configured to update a logical-to-physical address mapping table in accordance with the physical-to-logical
address mapping table at intervals longer than a time-out period between write operations on the run-time write block.

US Pat. No. 9,632,880

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory, divided into a plurality of blocks with each block comprising a plurality of pages; and
a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,
wherein:
the microcontroller is configured to allocate the flash memory to provide a first run-time write block from the blocks;
between a first write operation and a second write operation of the first run-time write block, the microcontroller updates
a logical-to-physical address mapping table in accordance with a first section of physical-to-logical information while a
second section of physical-to-logical information is waiting to be updated to the logical-to-physical address mapping table
in a time interval between another pair of write operations performed on the first run-time write block;

the logical-to-physical address mapping table is provided within the flash memory; and
a first physical-to-logical address mapping table that provides the first and second sections of physical-to-logical information
is established in the random access memory to record logical addresses corresponding to physical addresses of one block.

US Pat. No. 9,570,162

DATA READ METHOD FOR FLASH MEMORY

SILICON MOTION, INC., Jh...

1. A data read method for a flash memory, wherein the flash memory comprises a plurality of pages, and predetermined information
is written into each of the pages of the flash memory, and the predetermined information is a binary code with a predetermined
value, and the binary code is constituted by a plurality of bits, comprising:
reading a target address of the flash memory according to a source read voltage to obtain source data and a source error correction
code;

correcting error bits of the source data according to the source error correction code in a first error correction process;
when the error bits of the source data cannot be corrected in the first error correction process, reading the predetermined
information corresponding to the source data from the flash memory according to the source read voltage;

amending the source data according to the difference between the predetermined value of the predetermined information and
the predetermined information read from the flash memory when the error bits of the source data cannot be corrected to obtain
an amended data;

amending the source error correction code according to the difference between the predetermined value of the predetermined
information and the predetermined information read from the flash memory when the error bits of the source data cannot be
corrected to obtain an amended error correction code;

correcting error bits of the amended data according to the amended error correction code in a second error correction process;
and

when the error bits of the amended data are successfully corrected to obtain second output data in the second error correction
process, sending the second output data to a host.

US Pat. No. 9,529,709

APPARATUSES FOR MANAGING AND ACCESSING FLASH MEMORY MODULE

SILICON MOTION, INC., Zh...

1. A controller for managing a flash memory module, comprising:
a communication interface for coupling with a host device; and
a processing circuit coupled with the communication interface and configured for:
writing a plurality of data and associated logical addresses into multiple physical pages of multiple data blocks,
recording a first address group in a first page of a first addressing block in an order based on an address order of a first
set of M sequential logical addresses, wherein the first address group comprises multiple addresses of a first set of M physical
pages of the multiple data blocks, and the first set of M physical pages corresponds to the first set of M sequential logical
addresses,

recording a second address group in a second page of the first addressing block in an order based on an address order of a
second set of M sequential logical addresses, wherein the second address group comprises multiple addresses of a second set
of M physical pages of the multiple data blocks, and the second set of M physical pages corresponds to the second set of M
sequential logical addresses,

recording a third address group in a first page of a second addressing block in an order based on an address order of a third
set of M sequential logical addresses, wherein the third address group comprises multiple addresses of a third set of M physical
pages of the multiple data blocks, and the third set of M physical pages corresponds to the third set of M sequential logical
addresses, and

recording a fourth address group in a second page of the second addressing block in an order based on an address order of
a fourth set of M sequential logical addresses, wherein the fourth address group comprises multiple addresses of a fourth
set of M physical pages of the multiple data blocks, and the fourth set of M physical pages corresponds to the fourth set
of M sequential logical addresses;

wherein M is an integer larger than one, the second set of M logical addresses is successive to the first set of M logical
addresses, the third set of M logical addresses is successive to the second set of M logical addresses, and the fourth set
of M logical addresses is successive to the third set of M logical addresses,

wherein the multiple data blocks, the first addressing block, and the second addressing block are different, and
wherein the physical pages of the data blocks and the physical pages of the addressing blocks are separate.

US Pat. No. 9,514,843

METHODS FOR ACCESSING A STORAGE UNIT OF A FLASH MEMORY AND APPARATUSES USING THE SAME

SILICON MOTION, INC., Jh...

1. A method for accessing a storage unit of a flash memory, performed by a control unit, comprising:
appending a transaction to a bad-column table each time a bad column of a block within the storage unit is inspected;
determining whether a total number of transactions within the bad-column table is odd when determining that a last column
of the block is a regular column;

appending a transaction to the bad-column table to indicate that the last column of the block is a bad column when determining
that the total number of transactions within the bad-column table is odd;

appending no transaction to the bad-column table when determining that the total number of transactions within the bad-column
table is even;

reading out designated data through a storage-unit access interface after receiving a data-read request through a processing-unit
access interface;

dropping bits of columns according to the transactions within the bad-column table; and
replying with cleaned data through the processing-unit access interface.

US Pat. No. 10,140,026

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a flash memory, comprising a plurality of blocks, each of blocks has a plurality of pages, each of the pages has a logical address and a physical address, the flash memory has a data mapping table arranged to record a plurality of mapping relationships between the logical addresses and the physical addresses, the data mapping table is divided into a plurality of data mapping sets, each of the data mapping sets has at least two of the mapping relationships, and each of the data mapping sets corresponds to a set index;
a random access memory, having a cache area, a sequential-order table, a reverse-order table and a cache-area mapping table, wherein the cache area has a plurality of sectors arranged to store part of the data mapping sets of the data mapping table, the cache-area mapping table has a plurality of sector-mapping columns arranged to record the set indexes of the data mapping sets of the cache area, the sequential-order table is arranged to record the order that the data mapping sets are read from the cache area, and the reverse-order table is arranged to record the opposite order that the data mapping sets are read from the cache area; and
further comprising a controller locating a first data mapping set of a first mapping relationship comprising the page indicated by a read command or a write command, and determining whether the first data mapping set has been uploaded into the cache area according to whether the cache-area mapping table has a first set index of the first data mapping set, wherein the first data mapping set is one of the data mapping sets, the first set index is one of the set indexes, and the first mapping relationship is one of the mapping relationships;
wherein each of the sectors corresponds sequentially to a plurality of common indexes, the sector-mapping columns of the cache-area mapping table correspond sequentially to the sectors of the cache area, the sequential-order table has a plurality of sequential-order columns corresponding sequentially to the sectors of the cache area, the reverse-order table has a plurality of reverse-order columns corresponding sequentially to the sectors of the cache area, and each of the sectors and the sector-mapping column, the sequential-order column, the reverse-order column have the same common index with the corresponding sector.

US Pat. No. 10,007,601

DATA STORAGE DEVICE AND OPERATING METHOD FOR FLASH MEMORY

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:a FLASH memory, comprising a first block and a second block, wherein each of the first block and the second block comprises a plurality of pages;
a controller, electrically communicating with the FLASH memory and having circuitry configured to:
determine whether a first data segment issued from a host is a complete page segment, wherein the controller writes the first data segment into the first block if the first data segment is a complete page segment, and, the controller writes the first data segment into the second block if the first data segment is an incomplete page segment;
classify the first block into a first set of blocks, which stores only complete page segments, responsive to the first block being filled;
classify the second block into a second set of blocks, which stores only incomplete page segments, responsive to the second block being filled;
during a first garbage collection operation, collect valid data only from the first set of blocks to release space of blocks of invalid data from the first set of blocks; and
during a second garbage collection operation, collect valid data only from the second set of blocks to release space of blocks of invalid data from the second set of blocks.

US Pat. No. 9,991,196

PRINTED CIRCUIT BOARD AND METHOD OF FABRICATING AN ELEMENT

SILICON MOTION, INC., Jh...

6. A method of fabricating an element, comprising:applying a non-plating process to fabricate a printed circuit board, wherein the printed circuit board is divided into a plurality of package units, and the non-plating process fabricating the printed circuit board comprises:
performing a first plating through at least one ground pad to form at least one ground line and at least one power line on the surface of each of the package units of the printed circuit board; and
performing a second plating to form a plurality of first signal lines on the surface of each of the package units of the printed circuit board.

US Pat. No. 9,846,578

ELECTRONIC DEVICE AND METHOD FOR FIRMWARE UPDATING THEREOF

Silicon Motion, Inc., Jh...

1. A firmware update method, applied to a host device and a peripheral device, wherein the peripheral device comprises a memory
device, a register and a controller, the firmware update method comprising:
transmitting a first firmware data sector to a peripheral device from the host device, wherein the first firmware data sector
has a first mode parameter and a first program code sector;

temporarily storing the received firmware data sector into the register by the controller;
reading at least one parameter sector of the received first firmware data sector by the controller to determine if the mode
parameter of the firmware data sector is a first mode parameter or a second mode parameter, wherein the first made parameter
represents that the first program code sector has not been written into the memory device, and the second mode parameter represents
that the first program code sector has been written into the memory device;

determining whether or not an interruption event occurs on the memory device during the transmission;
replacing the first mode parameter of the first firmware data sector with the second mode parameter of the first firmware
data sector if the interruption event has occurred on the memory device; and

retransmitting the first firmware data sector having a second mode parameter to the peripheral device from the host device
if the interruption event has occurred.

US Pat. No. 9,830,098

METHOD OF WEAR LEVELING FOR DATA STORAGE DEVICE

Silicon Motion, Inc., Jh...

1. A method of wear leveling for a data storage device, wherein the data storage device comprises a non-volatile memory, the
non-volatile memory comprises a plurality of blocks, a portion of the blocks not having any valid data are defined as spare
blocks and the spare blocks are associated with a spare pool, the method comprising steps of:
maintaining a management table recording a plurality of physical block numbers and a plurality of block statuses corresponding
to the blocks;

selecting a first spare block having one of the block statuses and a first smallest physical block number as a current temporary
block;

receiving a write command from a host;
determining whether data in the write command shall be written into the current temporary block;
if false, selecting a second spare block having the one of the block statuses and a second smallest physical block number
as a next temporary block; and

writing the data into the next temporary block.

US Pat. No. 9,785,546

METHODS FOR SCHEDULING READ COMMANDS AND APPARATUSES USING THE SAME

Silicon Motion, Inc., Jh...

1. A method for scheduling read commands, performed by a processing unit, comprising:
receiving a plurality of logical read commands from a master device via a first access interface, where the logical read commands
request to read data of a plurality of logical addresses;

obtaining a plurality of first physical storage locations of a plurality of mapping segments associated with the logical addresses
from a high-level mapping table;

directing a second access interface to read the mapping segments from the first physical storage locations of a storage unit;
obtaining a plurality of second physical storage locations associated with the logical addresses from the mapping segments;
directing the second access interface to read data from the second physical storage locations of the storage unit; and
directing the first access interface to clock the data of the logical addresses out to the master device,
wherein the storage unit comprising a plurality of storage sub-units and each storage sub-unit is associated with a sub-queue.

US Pat. No. 9,779,017

DATA STORAGE DEVICE AND DATA ACCESSING METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, comprises a plurality of dies, and a bad column table, and each of the dies has a plurality of columns, wherein
each of the columns is constituted by a plurality of sectors; and

a controller, performing a read operation or a write operation from a first column to an Nth column of the columns in response
to a read command or a write command, reading the bad column table during or before the read operation or the write operation
to obtain the first bad column data set, and skipping at least two columns within the range of the first column to the Nth
column according to a first bad column data set during the read operation and the write operation, wherein the first bad column
data set has first data and second data, the first data is a starting address, and the second is a number of columns;

wherein the bad column table further comprises a second bad column data set, the controller skips one column within the range
of the first column to the Nth column during the read operation and the write operation in response to the second bad column
data set, wherein the second bad column data set comprises third data, the third data indicates an address of one of the columns;
and

wherein N is a positive integer and the value of the N is greater than 3.

US Pat. No. 9,645,896

DATA STORAGE DEVICE AND FLASH MEMORY CONTROL METHOD

SILICON MOTION, INC., Jh...

1. A data storage device, comprising:
a flash memory including multi-level cells and single-level cells, wherein the flash memory is divided into a plurality of
blocks with each block comprising a plurality of physical pages; and

a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,
wherein:
the microcontroller is configured to use the random access memory to cache data issued from the host before writing the data
into the flash memory;

the microcontroller is further configured to allocate the blocks of the flash memory to provide a first run-time write block
containing multi-level cells and a second run-time write block containing single-level cells;

each physical page of data uploaded from the random access memory to the first run-time write block contains sequential data;
random data cached in the random access memory to form one physical page is written into the second run-time write block;
and

when determining that a first physical page of data that has been uploaded from the random access memory to the second run-time
write block contains random data, the microcontroller is configured to write a second physical page of data, cached in the
random access memory after the first physical page of data, into the second run-time write block, before determining that
the second physical page of data contains random data.

US Pat. No. 9,620,245

DATA STORAGE DEVICE AND DATA MAINTENANCE METHOD THEREOF

Silicon Motion, Inc., Jh...

1. A data storage device, comprising:
a flash memory, having a plurality of block groups, wherein each of the block groups has a plurality of blocks, and each of
the blocks has a plurality of pages; and

a controller, configured to perform a first read operation on at least one first page of a first block which belongs to a
first block group of the block groups, and perform a maintenance process in background after the first read operation is finished,
wherein in the maintenance process:

the controller is configured to determine whether a first group read count of the first block group is greater than a read
threshold

if yes, that is, if the first group read count is greater than the read threshold, the controller is configured to scan the
pages of each of the blocks of the first block group to obtain a plurality of first error bit numbers corresponding to the
blocks of the first block group, and update the block by moving the data store in the block corresponding to the first error
bit number that is greater than an error-bit threshold, wherein the first group read count indicates a number of times that
all of the pages have been read in the first block group, and the first error bit number indicates a number of error bits
of the data stored in the block.

US Pat. No. 10,140,024

DATA STORAGE DEVICE AND DATA READING METHOD THEREOF

Silicon Motion, Inc., Jh...

11. A data storage device, comprising:a flash memory;
a random access memory; and
a controller, receiving a plurality of read commands from a host to constitute a command queue, and determining an order for execution of the read commands, wherein a data sector indicated by one of the read commands requires one of a plurality of mapping tables to be located, and the read commands correspond to a plurality of read tasks, and each of the read commands is arranged to prepare one of the read tasks that is arranged to transmit the indicated data sector to the host,
wherein the controller selects a first read command where the mapping table required by the first read command has already been loaded on the random access memory from the read commands to be the first of the read tasks executed,
wherein remaining read commands other than the first read command in the read commands in the command queue are prioritized based on whether one of the mapping tables required by one of the remaining read commands is loaded on the random access memory, and one of the remaining read commands that requires one of the mapping tables having not been loaded on the random access memory has a higher priority than another one of the remaining read commands that requires one of the mapping tables having already been loaded on the random access memory.

US Pat. No. 10,140,058

MEMORY CONTROLLER AND MEMORY MODULE

SILICON MOTION, INC., Jh...

1. A memory controller coupled between an external device and a memory, comprising:a first interface to communicate with the memory, the first interface comprising:
a first buffer coupled to the memory; and
a first synchronization unit coupled to the first buffer;
a second interface to communicate with the external device, the second interface comprising:
a second buffer coupled to the external device; and
a second synchronization unit coupled to the second buffer; and
a control logic,
wherein in response to a synchronization debug signal being at a first logic level, the control logic sets the second buffer of the second interface to be at a receiving mode according to the synchronization debug signal to receive test data from the external device and transmit the test data to the first synchronization unit, and the control logic sets the first buffer of the first interface to be at a transmitting mode according to an inverted synchronization debug signal to transmit the test data from the first synchronization unit to the memory, and
wherein after a predetermined time, in response to the synchronization debug signal being at a second logic level, the control logic sets the first buffer of the first interface to be at the receiving mode to receive a test result from the memory and transmit the test result to the second synchronization unit, and the control logic sets the second buffer of the second interface to be at the transmitting mode to transmit the test result from the second synchronization unit to the external device,
wherein the first synchronization unit and the second buffer are operated at a second clock, and the second synchronization unit and the first buffer are operated at a first clock.