US Pat. No. 9,220,050

MESH NETWORK DEFRAGMENTATION

Silicon Laboratories Inc....

1. A method of creating a mesh network having a single leader node, from a plurality of nodes, wherein each of said plurality
of nodes executes said method, said method comprising:
receiving one or more beacon messages at said node, wherein each node sending a beacon message temporarily assumes leader
node status, and wherein each of said beacon messages comprises a unique indicia associated with said sending node;

comparing, at said receiving node, said indicia of each of said received beacon messages;
selecting a leader node based on said comparison; and
retransmitting from said receiving node said beacon message comprising said indicia of said selected leader node,
wherein said method is repeated until all of said plurality of nodes have selected the same leader node.

US Pat. No. 9,196,962

DIFFERENTIAL LOOPSTICK ANTENNA CONFIGURATION

Silicon Laboratories Inc....

8. An apparatus comprising:
a positive antenna input;
a negative antenna input;
a first switch disposed between the positive antenna input and a reference voltage node to selectively couple the positive
antenna input to the reference voltage node and a second switch disposed between the negative antenna input and the reference
voltage node to selectively couple the negative antenna input to the reference voltage node,

wherein one of the first and second switches is configured to couple the positive antenna input or the negative antenna input
to the reference voltage node to operate the apparatus in a single-ended mode with respect to the positive and negative antenna
inputs,

wherein in the single-ended mode, the first and second switches are configured to couple a front end of the receiver to receive
signals from one of a first loopstick antenna coupled at one of the positive and negative antenna inputs and a second loopstick
antenna coupled at the other of the positive and negative antenna inputs.

US Pat. No. 9,369,138

CALIBRATION OF DIGITAL-TO-TIME CONVERTER

Silicon Laboratories Inc....

1. An apparatus comprising:
a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration
signal, the output signal having edges linearly delayed from corresponding edges of the input signal based on the digital
code, the digital code vacillating between an evaluation code and a calibration code;

a reference signal generator configured to provide a delayed version of the input signal, the delay of the reference signal
generator being matched to a delay of the digital-to-time converter; and

a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version
of the input signal.

US Pat. No. 9,713,090

LOW-POWER COMMUNICATION APPARATUS AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus, comprising:
a detector to detect an idle state of a communication link that communicates bursts or packets of information, the detector
comprising:

at least one single-ended receiver to sample signal levels of the communication link; and
a bus idle detector, coupled to the at least one single-ended receiver, to detect the idle state of the communication link;
and

an oscillator having low-power and normal modes of operation, the oscillator to make a transition to the low-power mode during
the idle state of the communication link, the oscillator to leave the low-power mode of operation and to enter the normal
mode of operation during non-idle states of the communication link.

US Pat. No. 9,484,925

PROGRAMMABLE DIVIDER

Silicon Laboratories Inc....

1. A method comprising:
controlling a modulus of a programmable divider, the controlling comprising selectively activating and deactivating a plurality
of cells of the divider, each cell of the plurality of cells being programmable by an associated at least one programming
signal to cause the cell to divide by one of multiple moduli;

wherein the activating comprises, for at least one of the cells, configuring an output signal of the cell to exhibit a predetermined
signal state to override a response of the cell to the associated at least one programming signal when the cell transitions
from a deactivated state to an activated state;

wherein the controlling further comprises retiming a modulus control signal received by the at least one cell from being synchronized
from a first clock signal to being synchronized to a second clock signal other than the first clock signal.

US Pat. No. 9,426,603

SYSTEM AND METHOD FOR USING A DEVICE TO OPERATE ON MULTIPLE NETWORKS

Silicon Laboratories Inc....

1. A device, comprising:
exactly one radio portion, wherein the radio portion comprises:
an antenna;
a radio circuit;
protocol interfacing and processing circuitry; and
one or more configuration registers;
a processing unit; and
a non-transitory computer readable medium, in communication with the processing unit, comprising instructions which, when
executed, allow the device to share the radio portion among a first IEEE802.15.4 network and a second IEEE802.15.4 network
by:

configuring the radio portion to operate as a parent node on the second IEEE802.15.4 network;
setting a timer to a predetermined value; and
upon expiration of the timer, reconfiguring the radio portion to operate as a sleepy end device on the first IEEE802.15.4
network, wherein the device performs a function as a sleepy end device, and

configuring the radio portion to operate on the second IEEE802.15.4 network after the function is performed, and
wherein each time the timer expires, the radio portion is reconfigured to operate as a sleepy end device on the first IEEE802.15.4
network.

US Pat. No. 9,143,112

CIRCUITS AND METHODS FOR PROVIDING AN IMPEDANCE ADJUSTMENT

Silicon Laboratories Inc....

1. An apparatus comprising:
a node configured to couple to a power line to receive direct current (DC) power from a power generator;
a signal generator including a control input and including an output coupled to the node; and
a control circuit including an input coupled to the output and including an control output coupled to the control input of
the signal generator, the control circuit to determine an impedance associated with the power generator based on a signal
at the input and to apply a control signal to the control input of the signal generator to produce an impedance adjustment
signal on the output of the signal generator for communication to the power generator through the power line via the node
in response determining the impedance.

US Pat. No. 9,048,547

AIR LOOP ANTENNA FOR SHARED AM/FM

Silicon Laboratories Inc....

1. Shared AM/FM antenna circuitry configured for coupling to radio circuitry, comprising:
an air loop antenna element formed between first and second antenna element nodes, the air loop antenna element being configured
to receive AM channels within an AM broadcast band;

a first conductor segment coupled to the first node of the air loop antenna element with the first node being between the
air loop antenna element and the first conductor segment; and

a second conductor segment coupled to the second node of the air loop antenna element with the second node being between the
air loop antenna element and the second conductor segment;

at least one of the first and second conductor segments being configured to receive FM channels within an FM broadcast band;
at least one of the first and second conductor segments being coupled between the first or second node of the air loop antenna
element and an AM signal path, the AM signal path being configured for coupling at a third node to provide the received AM
broadcast channels to an AM signal input of the radio circuitry;

at least one of the first and second conductor segments being coupled between the first or second node of the air loop antenna
element and a FM signal path, the FM signal path being configured for coupling at a fourth node to provide the received FM
broadcast channels to an FM signal input of the radio circuitry;

the AM signal path being further configured to at least partially block the received FM broadcast band channels and to at
least partially pass the received AM broadcast band channels to the AM signal input of the radio circuitry; and

the FM signal path being further configured to at least partially pass the received FM broadcast band channels to the FM signal
input of the radio circuitry.

US Pat. No. 9,473,150

PEAK DETECTORS FOR AMPLITUDE CONTROL OF OSCILLATORS

Silicon Laboratories Inc....

1. An apparatus comprising:
an oscillator circuit configured to generate an oscillating signal; and
a feedback circuit configured to control a bias signal of the oscillator circuit to maintain a target peak amplitude of the
oscillating signal based on a current-mode indicator of a peak amplitude of the oscillating signal and a reference current,
the feedback circuit comprising:

a rectifier circuit configured to directly sense current of the oscillator circuit and generate the current-mode indicator
based on the sensed current; and

a summing node configured to provide a bias control signal based on a difference between the current-mode indicator and the
reference current,

wherein the rectifier circuit includes a transistor having a source terminal directly coupled to the oscillator circuit, a
gate terminal directly coupled to a bias node of the oscillator circuit, and a drain terminal coupled to the summing node.

US Pat. No. 9,204,080

MULTI-CHIP MODULES HAVING STACKED TELEVISION DEMODULATORS

Silicon Laboratories Inc....

1. A multi-chip module (MCM) package having multiple television demodulator dies, comprising:
a plurality of pins, the pins comprising:
a plurality of input pins configured to receive two or more tuned broadcast channels associated with at least one of satellite
television broadcasts;

a plurality of input pins configured to receive two or more tuned broadcast channels associated with terrestrial or cable
television broadcasts; and

a plurality of output pins configured to provide two or more demodulated television signals;
at least two stacked demodulator dies coupled to the plurality of pins, each die having at least one pad connected to a shared
pin for the MCM package and each die being configured to provide at least one of the demodulated television signals;

wherein the MCM package has a top surface area of about 64 square millimeters or less.

US Pat. No. 9,253,007

METHODS AND SYSTEMS FOR RAPID DETECTION OF DIGITAL CONTENT WITHIN RF SIGNALS

Silicon Laboratories Inc....

1. A method for detecting digital content in a radio frequency (RF) channel, comprising:
receiving radio frequency (RF) signals;
digitizing signals associated with a channel within the RF signals to generate digital samples having a real component (I)
and an imaginary component (Q);

generating cyclic prefix correlation values based upon the digital samples over a selected number of symbol times associated
with digital content being detected within the channel, the selected number of symbol times being a plurality of symbol times;

accumulating the cyclic prefix correlation values in a plurality of accumulation registers over the selected number of symbol
times to form a plurality of accumulated correlation values;

storing the accumulated correlation values in a dump register after the selected number of symbol times;
utilizing the accumulated correlation values within the dump register to determine whether digital content is present within
the channel; and

outputting a detection signal indicating whether or not digital content is present.

US Pat. No. 9,176,558

OPTIMIZING BIAS POINTS FOR A SEMICONDUCTOR DEVICE

Silicon Laboratories Inc....

1. A method comprising:
determining a corner value for each of a plurality of device types of a semiconductor die based on operation of each of the
device types and storing the corner value for each of the device types in a storage of the semiconductor die

determining environmental conditions at which the semiconductor die is operating using one or more sensors of the semiconductor
die;

using a controller of the semiconductor die to access a table in the storage based on the determined environmental conditions,
the table including a set of bias points, to determine a bias point for each of a plurality of blocks based on the environmental
conditions and heuristics for the semiconductor die, wherein the table is partitioned into a plurality of partitions each
associated with at least one of the blocks and including a plurality of bias points each corresponding to a set of environmental
conditions and based on the determined corner value of each of the plurality of device types; and

dynamically operating the semiconductor die at a bias point accessed from the table based on the determined environmental
conditions.

US Pat. No. 9,407,276

REDUCING DISTORTION IN AN ANALOG-TO-DIGITAL CONVERTER

Silicon Laboratories Inc....

1. An apparatus comprising:
a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first portion of a differential
analog signal and convert the first portion of the differential analog signal into a first digital value;

a second VCO ADC unit to receive a second portion of the differential analog signal and convert the second portion of the
differential analog signal into a second digital value;

a combiner to form a combined digital signal from the first and second digital values;
a decimation filter circuit to receive the combined digital signal and filter the combined digital signal into a filtered
combined digital signal; and

a cancellation circuit to receive the filtered combined digital signal and generate a distortion cancelled digital signal,
based at least in part on a coefficient value.

US Pat. No. 9,307,318

AUDIO PROCESSOR CIRCUITS FOR ACOUSTIC ECHO CANCELLATION AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. An audio processor circuit comprising:
a first digital signal processing circuit having an input for receiving a far-end audio signal, and an output;
a second digital signal processing circuit having an input for receiving a digital near-end audio signal, and an output;
a delay buffer having an input coupled to said output of said first digital signal processing circuit, and an output, a delay
of said delay buffer synchronizing said output of said first digital signal processing circuit to said output of said second
digital signal processing circuit; and

an interleaver having a first input coupled to said output of said delay buffer, a second input coupled to said output of
said second digital signal processing circuit, and an output for alternatively providing signals received from said first
and second inputs to said output.

US Pat. No. 9,264,084

RADIO RECEIVER HAVING ENHANCED AUTOMATIC GAIN CONTROL CIRCUITRY

Silicon Laboratories Inc....

1. An apparatus comprising:
an input terminal to receive a radio frequency (RF) signal and to communicate the RF signal to a low noise amplifier (LNA)
via an input signal path; and

a capacitor attenuator coupled to the input terminal to attenuate the RF signal by a controllable amount and having a first
portion controllable to include a used part configured on the input signal path and an unused part coupled between the input
signal path and an AC reference node, and a second portion coupled between the LNA and the AC reference node, wherein a capacitance
of the first and second portions is responsive to a strength of the RF signal.

US Pat. No. 9,246,500

TIME-TO-VOLTAGE CONVERTER USING A CAPACITOR BASED DIGITAL TO ANALOG CONVERTER FOR QUANTIZATION NOISE CANCELLATION

Silicon Laboratories Inc....

1. A phase-locked loop (PLL) comprising:
a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply
a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage with reduced quantization
noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference
signal and a feedback signal from an oscillator controlled at least in part based on a value of the combined voltage.

US Pat. No. 9,312,972

METHODS AND SYSTEMS FOR BLENDING BETWEEN ANALOG AND DIGITAL BROADCAST SIGNALS

Silicon Laboratories Inc....

1. A method for processing signals, comprising:
performing a digital/analog blending operation between digital demodulated signals obtained from digital modulated signals
contained in a received radio frequency (RF) spectrum and analog demodulated signals obtained from analog modulated signals
contained in the same received RF spectrum to produce a post-blend demodulated left plus right (L+R) signal and a post-blend
demodulated left minus right (L?R) signal; and

then performing stereo-to-mono blending operations on the post-blend demodulated (L+R) and (L?R) signals.

US Pat. No. 9,287,219

RADIATION-BLOCKING STRUCTURES

Silicon Laboratories Inc....

1. A multi-layer semiconductor device, comprising:
a first device layer including one or more non-continuous first radiation-opaque layer structures defining radiation transmissive
areas in the first device layer; and

a second device layer underlying the first device layer, the second device layer including one or more non-continuous second
radiation-opaque layer structures defining radiation transmissive areas in the second device layer;

where the first non-continuous opaque structures of the first device layer are cooperatively spaced in overlapping relationship
with the second non-continuous opaque structures of the second device layer to form a continuous barrier that completely blocks
all radiation that impinges on the first device layer from above the semiconductor device from penetrating through the combination
of the first and second device layers of the multi-layer structure;

where the semiconductor device further comprises a third device layer disposed between the first and second device layers,
the third device layer comprising radiation-transmissive dielectric material; and where each of the first and second non-continuous
opaque structures comprise non-continuous metal structures; and

where the semiconductor comprises a gas sensor device; where the first non-continuous opaque structures of the first device
layer comprise sensor electrodes for the gas sensor device; and where the second non-continuous opaque structures of the second
device layer comprise ground planes.

US Pat. No. 9,274,140

MULTI-PURPOSE INTEGRATED CIRCUIT DEVICE CONTACTOR

Silicon Laboratories Inc....

1. A tester apparatus comprising:
a first printed circuit board;
a pogo block electrically connected to the first printed circuit board on a first side of the pogo block;
wherein in a first configuration the pogo block is configured to be electrically connected to a packaged integrated circuit
under test; and

wherein in a second configuration the pogo block is electrically connected on a second side of the pogo block to a second
printed circuit board, wherein the second printed circuit board provides a translation from the first printed circuit board
to provide for testing in the second configuration of a device with at least one of a different package size or different
electrical contacts than the packaged integrated circuit under test in the first configuration.

US Pat. No. 9,252,707

MEMS MASS BIAS TO TRACK CHANGES IN BIAS CONDITIONS AND REDUCE EFFECTS OF FLICKER NOISE

Silicon Laboratories Inc....

1. A method comprising:
applying an electrode bias signal to an electrode of a microelectromechanical system (MEMS) device;
applying a mass bias signal to a mass of the MEMS device suspended from a substrate of the MEMS device; and
generating the mass bias signal based on a target mass-to-electrode bias signal level and a signal level of the electrode
bias signal,

wherein generating the mass bias signal comprises:
replicating the electrode bias signal to generate a replica electrode bias signal; and
boosting a signal level of the replica electrode bias signal by the target mass-to-electrode bias signal level to generate
the mass bias signal.

US Pat. No. 9,178,451

CONTROLLER FOR BRUSHLESS DC MOTOR WITH FLEXIBLE STARTUP AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. A controller for a brushless direct current (BLDC) motor, comprising:
a pulse width modulator for providing a plurality of phase control signals to control corresponding ones of a plurality of
phases of the BLDC motor; and

a control circuit for controlling said pulse width modulator to provide pulses to said plurality of phases to control a speed
of the BLDC motor by causing said pulse width modulator to adjust widths of said pulses when a measured current in an active
one of a corresponding phase exceeds a threshold in a startup mode, wherein in said startup mode said control circuit controls
said pulse width modulator to provide said pulses at a duty cycle to said plurality of phases, and reduces said duty cycle
of said pulses based on a time when said measured current in said active one of said plurality of phases exceeds said threshold.

US Pat. No. 9,136,824

FREQUENCY MANAGEMENT USING SAMPLE RATE CONVERSION

Silicon Laboratories Inc....

1. An apparatus comprising:
a first analog-to-digital converter (ADC) to receive and sample an analog signal responsive to a first clock signal at a first
clock frequency to output digitized samples, wherein the first clock frequency is dynamically controllable;

a first asynchronous sample rate converter coupled to the first ADC to receive the digitized samples at the first clock frequency
and to output the digitized samples at a second clock frequency, wherein the second clock frequency is a fixed frequency;

a digital datapath coupled to the first asynchronous sample rate converter, and including a plurality of modules to process
the digitized samples and to output processed digitized samples, the digital datapath to operate according to a second clock
signal at the second clock frequency; and

a second asynchronous sample rate converter coupled to the digital datapath to receive the processed digitized samples at
the second clock frequency and to output the processed digitized samples at the first clock frequency.

US Pat. No. 9,048,777

APPARATUS FOR INTEGRATED CIRCUIT INTERFACE AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus, comprising:
an integrated circuit (IC) adapted to be powered by a positive supply voltage, the IC comprising:
a charge pump adapted to convert the positive supply voltage of the IC to a negative bias voltage; and
a bidirectional interface circuit, comprising:
an amplifier coupled to the negative bias voltage to accommodate a bidirectional input voltage of the IC; and
a comparator coupled to the negative bias voltage to accommodate the bidirectional input voltage of the IC.

US Pat. No. 9,236,867

APPARATUS FOR MIXED SIGNAL INTERFACE CIRCUITRY AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An integrated circuit (IC), comprising:
a plurality of pads to send or receive signals; and
a plurality of mixed signal interface blocks to process both analog and digital signals, the plurality of the mixed signal
interface blocks coupled to: (a) a digital core of the IC via a plurality of corresponding digital interfaces, and (b) the
plurality of pads;

wherein each mixed signal interface block in the plurality of mixed signal interface blocks senses an analog input signal
in a plurality of analog signals simultaneously with other mixed signal interface blocks in the plurality of mixed signal
interface blocks, and

wherein processing of analog signals provided to the plurality of mixed signal interface blocks occurs in the plurality of
mixed signal interface blocks rather than the digital core of the IC.

US Pat. No. 9,172,344

STATISTICAL GAIN CONTROL IN A RECEIVER

Silicon Laboratories Inc....

1. A method comprising:
receiving a radio frequency (RF) signal in a receiver;
accumulating a first count of a number of samples of the RF signal greater than a first threshold during an accumulation window
and accumulating a second count of a number of the samples greater than a second threshold during the accumulation window,
the first threshold greater than the second threshold;

processing the first count to produce a first processed count;
determining if the first processed count exceeds a first metric after the accumulation window if so, reducing a gain of an
RF gain element of the receiver;

processing the second count to produce a second processed count;
determining if the second processed count exceeds a second metric after a plurality of accumulation windows; and
if not, increasing the gain of the RF gain element.

US Pat. No. 9,157,937

CAPACITANCE TO DIGITAL CONVERTER AND METHOD

Silicon Laboratories Inc....

1. An integrator circuit comprising:
a switched capacitor bridge including first and second inputs and first and second outputs, the switched capacitor bridge
configured to sample first and second reference voltages twice per unit time interval; and

an integrator coupled to the first and second outputs and configured to integrate charge dumped into the first and second
outputs twice per unit time interval.

US Pat. No. 9,143,373

TRANSPORT OF AN ANALOG SIGNAL ACROSS AN ISOLATION BARRIER

Silicon Laboratories Inc....

1. A method comprising:
receiving an input signal to modulate and a modulation signal to modulate the input signal;
generating a pulse width modulated (PWM) signal using the input signal and the modulation signal in a pulse width modulator
circuit;

converting a rising edge of the pulse width modulated signal to a first pulse having a first width;
converting a falling edge of the pulse width modulated signal to a second pulse having a second width;
transmitting the first and second pulses across a communication channel;
supplying the first and second pulses to an edge demodulator and generating an edge demodulated signal; and
supplying the edge demodulated signal as a feedback signal to the pulse width modulator circuit.

US Pat. No. 9,065,657

POWERED DEVICE INCLUDING A DETECTION SIGNATURE CIRCUIT

Silicon Laboratories Inc....

9. The powered device of claim 1, wherein the impedance is substantially constant across a range of device detection input values.

US Pat. No. 9,058,761

SYSTEM AND METHOD FOR LCD LOOP CONTROL

Silicon Laboratories Inc....

1. An LCD controller, comprising:
a charge pump circuit for generating a charge voltage responsive to an external voltage and a clock signal;
an oscillator for generating the clock signal responsive to an oscillator control signal;
an LCD driver voltage circuit for generating a plurality of LCD driver voltages for driving segments of an LCD display; and
loop control circuit for monitoring an LCD driver voltage from the LCD driver voltage circuit and generating the oscillator
control signal responsive thereto to enable and disable the oscillator by using a latch, the loop control circuit further
comprising:

a comparator for comparing the LCD driver voltage with a reference voltage and generating an output at a first logical level
when the LCD driver voltage exceeds the reference voltage by a first predetermined level and generating the output at a second
logical level when the LCD driver voltage falls below the reference voltage by a second predetermined level;

wherein the latch latches the output at either the first logical level or the second logical level; and
control logic for generating the oscillator control signal to enable the oscillator responsive to the output at the second
logical level and for generating the oscillator control signal to disable the oscillator responsive to the output at the first
logical level.

US Pat. No. 9,438,165

RC OSCILLATOR

Silicon Laboratories Inc....

1. A method comprising:
using a current source to provide a charging current to a capacitor of a resistor-capacitor (RC) tank of an RC oscillator;
using a resistor of the current source as a resistor for the RC tank; and
communicating the charging current to the capacitor using a charging path, wherein using the charging path comprises communicating
the charging current to the capacitor using an amplifier and using the amplifier to amplify the voltage to generate a signal
to turn on a discharge path to discharge the capacitor, wherein using the amplifier to amplify the voltage comprises operating
a first transistor in a linear mode of operation to communicate the charging current to the capacitor and transitioning the
first transistor to an off state near or at the end of a first part of an oscillation cycle for the RC oscillator to increase
the amplification of the signal.

US Pat. No. 9,362,936

DIGITAL-TO-TIME CONVERTER

Silicon Laboratories Inc....

1. An apparatus comprising:
a digital-to-time converter comprising:
a first node;
a second node configured to receive a reference signal;
a digital-to-analog signal converter configured to couple a passive impedance to the first node, the passive impedance being
selected according to a digital code;

a first switch configured to selectively couple the first node to a second reference signal in response to an input signal;
and

a comparator configured to generate the output signal based on a first signal on the first node and the reference signal on
the second node.

US Pat. No. 9,264,754

PACKET SYNCHRONIZATION RECEIVER

Silicon Laboratories Inc....

1. A method comprising:
generating, based on at least one received signal, a first packet stream and a second packet stream, wherein one of the first
and second packet streams includes a packet associated with the other of the first and second packet streams, and wherein
the first and second packet streams contain control information including respective buffer configuration sizes for the first
and second packet streams in a dejitter buffer;

prior to determining the respective buffer configuration sizes based on the control information in the first and second packet
streams, allocating respective first and second portions of the dejitter buffer to the first and second packet streams;

prior to determining the respective buffer configuration sizes indicated by the control information in the first and second
packet streams, writing to the dejitter buffer data associated with the first and second packet streams;

determining the buffer configuration size indicated by the control information in the first packet stream; and
based on the buffer configuration size indicated by the control information in the first packet stream, reallocating the respective
first and second portions of the dejitter buffer to the first and second packet streams.

US Pat. No. 9,166,576

CIRCUITS AND METHODS OF AUTOMATICALLY ADJUSTING A DISCRIMINATOR THRESHOLD

Silicon Laboratories Inc....

1. A circuit comprises:
a discriminator to store a discriminator threshold;
a comparator circuit including a first input to receive a count, a second input to receive the discriminator threshold, and
an output to provide an output signal representing a result of the comparison between the count and the discriminator threshold;
and

a controller to automatically adjust the discriminator threshold when the count exceeds a first threshold or falls below a
second threshold.

US Pat. No. 9,429,468

APPARATUS WITH SENSOR FUNCTIONALITY AND POWER MANAGEMENT AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus, comprising:
a sensor integrated circuit (IC) to sense a stimulus, the sensor integrated circuit (IC) comprising:
an integrated analog-to-digital converter (ADC) to convert at least one signal related to the stimulus to at least one digital
signal; and

an integrated power management unit (PMU) to reduce power dissipation of the sensor integrated circuit (IC) by running at
a low duty cycle the integrated analog-to-digital converter (ADC), and by suspending a controller of the sensor integrated
circuit (IC).

US Pat. No. 9,385,747

CAPACITANCE-TO-DIGITAL CONVERTER UTILIZING DIGITAL FEEDBACK AND AUXILIARY DAC

Silicon Laboratories Inc....

1. A capacitance-to-digital converter circuit comprising:
a capacitor bridge circuit to sense a difference in capacitance between one or more sense capacitors and other capacitors
in the bridge circuit;

auxiliary capacitor digital to analog converters (DACs) coupled to the capacitor bridge circuit to reduce a magnitude of an
error signal corresponding to the sensed difference;

an analog to digital converter (ADC) coupled to the capacitor bridge circuit and the auxiliary capacitor DACs to convert the
error signal whose magnitude is reduced by the auxiliary capacitor DACs to a digital signal;

a digital accumulator coupled to the ADC to accumulate the digital signal from the ADC; and
wherein the auxiliary capacitor DACs are controlled to offset the difference in capacitance between the one or more sense
capacitors and the other capacitors in the bridge circuit based on the accumulated digital signal.

US Pat. No. 9,312,899

RADIO FREQUENCY (RF) RECEIVERS HAVING WHITENED DIGITAL FRAME PROCESSING AND RELATED METHODS

Silicon Laboratories Inc....

11. A receiver system, comprising:
a radio frequency (RF) front-end configured to receive an RF signal spectrum and to output analog signals associated with
the RF signal spectrum;

an analog-to-digital converter (ADC) coupled to receive the analog signals and to output digital samples associated with the
analog signals;

a digital processor coupled to receive the digital samples and to digitally process the digital samples, the digital processor
comprising:

a frame buffer coupled to receive and store the digital samples; and
a frame processor coupled to receive digital frames including blocks of multiple digital samples from the frame buffer and
to initiate digital processing of each frame based upon a frame control signal delayed by a variable time delay;

wherein the RF front-end, the ADC, and the digital processor are integrated within a single integrated circuit.

US Pat. No. 9,250,137

TEMPERATURE MEASUREMENT CIRCUITRY AND SYSTEM

Silicon Laboratories Inc....

1. A temperature measurement circuit comprising:
a modulator including an input terminal and an output terminal, the input terminal configured to receive an input signal corresponding
to a time-varying voltage at a first terminal of a bipolar device, the modulator configured to provide a modulator output
signal on the output terminal in response to receiving the input signal;

a back-end filter coupled to the output terminal and including a filter output terminal, the back-end filter configured to
convolve the modulator output signal with an impulse response to provide a filtered signal to the filter output terminal;
and

a temperature determination circuit coupled to the filter output terminal and configured to determine a temperature in response
to receiving the filtered signal.

US Pat. No. 9,178,549

HIGH PERFORMANCE, LOW COST RECEIVER FRONT END

SILICON LABORATORIES INC....

1. A radio frequency (RF) receiver front end, comprising:
an RF attenuator having an input for receiving an RF input signal, and an output; and
a low noise amplifier (LNA) having an input coupled to said output of said RF attenuator, and an output for providing a differential
RF output signal,

wherein said LNA comprises:
a first polarity amplifier having an input terminal coupled to said output of said RF attenuator, and an output terminal for
providing a first component of said differential RF output signal, said first polarity amplifier having a first input impedance;
and

a plurality of second polarity amplifiers, each having an input terminal coupled to said output of said RF attenuator, and
an output terminal, wherein said output terminals of said plurality of second polarity amplifiers are coupled together and
form a second component of said differential RF output signal, and each of said plurality of second polarity amplifiers has
a second input impedance higher than said first input impedance.

US Pat. No. 9,164,936

SYSTEM AND METHOD FOR REGULATING DIRECT MEMORY ACCESS DESCRIPTOR AMONG MULTIPLE EXECUTION PATHS BY USING A LINK TO DEFINE ORDER OF EXECUTIONS

SILICON LABORATORIES INC....

1. A method comprising:
using execution of descriptors in a processor-based machine to control direct memory access communications; and
using data from a given descriptor of the descriptors to control repeated executions of at least one of the descriptors to
control branching of descriptor execution among execution paths,

wherein using the data comprises:
using a loop counter to regulate a number of the repeated executions of at least one of the descriptors using a first execution
path of the execution paths and using a first interpretation of a linking parameter to define an order in which at least some
of the descriptors are executed using the first execution path; and

using a second interpretation of the linking parameter to cause the descriptor execution along a second execution path of
the execution paths in response to the loop counter indicating expiration of the number of repeated executions.

US Pat. No. 9,077,652

METHODS FOR LIMITING NUMBER OF ROUTERS IN A MESH NETWORK

Silicon Laboratories Inc....

1. A method of limiting the number of routers in a mesh network, said mesh network comprising a plurality of nodes, each node
comprising a processing unit and a network interface, said method comprising:
determining, using a node of said plurality of nodes, a number of routers currently in said mesh network;
enabling routing capability of said node if a number of routers currently in said mesh network is less than a predetermined
threshold;

monitoring network traffic, using said network interface, to identify a connectivity issue, if said number of routers is not
less than said predetermined threshold; and

enabling routing capability of said node if said connectivity issue is detected and said node can resolve said connectivity
issue.

US Pat. No. 9,461,653

FRACTIONAL-N PHASE-LOCKED LOOP

Silicon Laboratories Inc....

1. A phase-locked loop (PLL) comprising:
a capacitor based digital to analog converter (DAC) coupled to receive a digital indication of quantization noise and to supply
a quantization noise correction voltage to adjust a phase error voltage to create a combined voltage signal with reduced quantization
noise, wherein the phase error voltage is indicative of a phase error corresponding to a time difference between a reference
signal and a feedback signal based on an output of a first oscillator, the first oscillator controlled at least in part based
on a value of the combined voltage signal; and

an oscillator-based analog to digital converter (ADC) coupled the capacitor based DAC to convert the combined voltage signal
to a digital value, the oscillator-based ADC having a second oscillator having a frequency responsive to the combined voltage
signal.

US Pat. No. 9,324,701

DIODE CIRCUIT LAYOUT TOPOLOGY WITH REDUCED LATERAL PARASITIC BIPOLAR ACTION

Silicon Laboratories Inc....

1. A semiconductor circuit device, comprising:
a semiconductor substrate; and
at least one diode structure formed in the substrate, the diode structure comprising elongated N+ doped regions alternating
with elongated P+ doped regions that are together surrounded by a P+ doped or N+ doped/Nwell guard ring;

where each of the elongated N+ doped regions extend between first and second ends with no P+ doped region disposed between
the first and second ends of the elongated N+ doped regions and the surrounding guard ring, and each of the elongated P+ doped
regions extend between first and second ends with no N+ doped region disposed between the first and second ends of the elongated
P+ doped regions and the surrounding guard ring; and

where either:
the first and second ends of the elongated P+ doped regions are each recessed inward relative to the first and second ends
of the elongated N+ doped regions such that a lateral distance between each of the first and second ends of the elongated
P+ doped regions and the surrounding guard ring is greater than a lateral distance between each of the first and second ends
of the elongated N+ doped regions and the surrounding guard ring, or

the first and second ends of the elongated N+ doped regions are each recessed inward relative to the first and second ends
of the elongated P+ doped regions such that a lateral distance between each of the first and second ends of the elongated
N+ doped regions and the surrounding guard ring is greater than a lateral distance between each of the first and second ends
of the elongated P+ doped regions and the surrounding guard ring.

US Pat. No. 9,209,912

CIRCUIT DEVICES AND METHODS FOR RE-CLOCKING AN INPUT SIGNAL

Silicon Laboratories Inc....

1. A method of re-clocking an input signal, the method comprising:
receiving a digital data stream having an average data rate corresponding to a first clock rate;
receiving a clock signal having a second clock rate from a timing source;
adjusting edge timing of transitions within the digital data stream based on a selected one of the clock signal and an inverted
version of the clock signal in response to a control signal to produce an output signal re-clocked according to the selected
one of the clock signal and the inverted version of the clock signal and having a power spectrum including a spectral null
at a desired frequency without altering the average data rate;

generating the control signal in response to transitions in the output signal; and
altering the control signal based on the transitions in the output signal using a flip flop circuit having a clock input configured
to receive the output signal, a data input, and a data output coupled to the data input through an inverter, the flip-flop
circuit configured to toggle an output signal to produce the control signal.

US Pat. No. 9,197,510

EFFICIENT NETWORK DATA DISSEMINATION

Silicon Laboratories Inc....

1. A method of disseminating information throughout a mesh network, said mesh network comprising a plurality of nodes and
a leader node which maintains a list of routers, said method comprising:
creating a beacon message at said leader node, said beacon message comprising:
an identity of said leader node;
a sequence number;
a version number associated with quasi-static network information;
a first network topology portion, said first network topology portion comprising entries for each of said routers in said
network, a cost of reaching each of said routers from said leader node, and a next hop to be used when communicating from
said leader node with each of said routers; and

first link information indicating link quality and protocol state of each of said routers that is a neighbor of said leader
node;

transmitting said beacon message from said leader node;
receiving said beacon message by a first router disposed within a listening range of said leader node;
creating a first routing table in a memory device within said first router using said first network topology and first link
information from said received beacon message, and using link information learned about neighbors of said first router;

transmitting a second beacon message from said first router, said second beacon message comprising:
said identity of said leader node;
said sequence number;
said version number associated with quasi-static network information;
a second network topology portion; and
second link information; wherein information from said first routing table is incorporated in said second network topology
portion and said second link information.

US Pat. No. 9,178,592

SYSTEMS AND METHODS USING MULTIPLE INTER-CHIP (IC) LINKS FOR ANTENNA DIVERSITY AND/OR DEBUG

Silicon Laboratories Inc....

1. An antenna diversity system, comprising:
at least two radio frequency (RF) tuner circuits coupled together by at least a first segment of a first inter-chip (IC) communication
link and at least a first segment of a second IC communication link, the two RF tuner circuits being configured to simultaneously
communicate at least one of digital streaming data, non-streaming digital packetized data, or a combination thereof simultaneously
across the first segment of the first IC communication link and across the first segment of the second IC communication link;

where each given one of the two RF tuner circuits has a RF input that is configured to receive RF signals of a RF spectrum
and at least one digital output that is configured to produce at least one digital output signal that is based at least in
part on the RF signals received by the RF input of the given RF tuner circuit, digital streaming data received from the other
RF tuner circuit across at least one of the first segment of the first IC communication link or the first segment of the second
IC communication link, or a combination thereof.

US Pat. No. 9,160,166

CHARGE PUMP FOR LOW POWER CONSUMPTION APPARATUS AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus, comprising:
a first set of circuits adapted to operate in a first mode of operation of the apparatus;
a second set of circuits adapted to operate in a second mode of operation of the apparatus, wherein a power consumption of
the apparatus is lower in the second mode of operation of the apparatus than in the first mode of operation of the apparatus;
and

a charge pump adapted to convert a first supply voltage of the apparatus to a second supply voltage, wherein the second supply
voltage powers the second set of circuits.

US Pat. No. 9,444,406

AMPLIFIER TOPOLOGY ACHIEVING HIGH DC GAIN AND WIDE OUTPUT VOLTAGE RANGE

Silicon Laboratories Inc....

1. An apparatus comprising:
an amplifier including,
an amplifier output stage including a first and a second transistor, the output stage supplying an amplifier output signal
at an amplifier output node;

a sense amplifier having an input coupled to a gate of the first transistor and having an output coupled to a gate of the
second transistor to thereby control current from the second transistor; and

an impedance coupled between the amplifier output node and the gate of the first transistor.

US Pat. No. 9,231,402

CIRCUIT DEVICE AND METHOD OF SUPPRESSING A POWER EVENT

Silicon Laboratories Inc....

1. A circuit device comprising:
a diode bridge including a first power input and a second power input and including a first output terminal and a second output
terminal, the diode bridge comprising a plurality of diodes and a respective plurality of diode bypass elements associated
with the plurality of diodes; and

a logic circuit to detect a power event at the first and second power inputs and to selectively activate one or more of the
respective plurality of diode bypass elements in response to detecting the power event to limit a rectified power supply at
the first and second output terminals.

US Pat. No. 9,166,507

SENSING A BACK ELECTROMOTIVE FORCE OF A MOTOR

SILICON LABORATORIES INC....

1. A method comprising:
using a processing core to regulate at least one characteristic of a first signal used to drive a first stator winding of
a brushless direct current (BLDC) motor;

using a peripheral component to generate a tracking signal in response to the first signal, the tracking signal indicating
times to sense a back electromotive force of a second stator winding of the BLDC motor; and

sensing the back electromotive force in response to the tracking signal, wherein the sensing comprises selectively isolating
a back electromotive force sensor from the second stator winding based on additional non-sensing times indicated by the tracking
signal.

US Pat. No. 9,054,672

SELECTIVE VARIABLE ATTENUATION CIRCUITRY AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. Variable capacitive attenuation circuitry having at least one RF signal input and an RF signal output, and comprising at
least two capacitors, each of the capacitors of the circuitry being selectable within the circuitry as either a shunt capacitor
between the RF signal output and an RF reference or as a series capacitor between the RF signal input and the RF signal output.

US Pat. No. 9,438,290

RECEIVER HAVING A CALIBRATION SOURCE

Silicon Laboratories Inc....

1. A method comprising:
using a signal reception path in a radio frequency (RF) receiver to process an input signal for the receiver for a first mode
of the receiver;

using a harmonic generator of the receiver to generate a harmonic signal; and
using the harmonic signal to replace the input signal with the harmonic signal for a second mode of the receiver, wherein
the act of using the harmonic generator comprises using a square wave generator or a pulse generator.

US Pat. No. 9,379,098

ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT INCLUDING A DISTRIBUTED DIODE STRING

Silicon Laboratories Inc....

1. An integrated circuit comprising:
a first input/output (I/O) pad;
a second I/O pad;
a first plurality of diodes arranged in series between the first I/O pad and a power supply terminal;
a second plurality of diodes arranged in series between the second I/O pad and the power supply terminal;
a conductor configured to couple a first node within the first plurality of diodes to a second node within the second plurality
of diodes such that the first plurality of diodes is electrically coupled to the second plurality of diodes only between the
first node and the second node, the first node is located between a first diode of the first plurality of diodes and a last
diode of the first plurality of diodes, the second node is located between a first diode of the second plurality of diodes
and a last diode of the second plurality of diodes; and

wherein at least one of the first plurality of diodes and the second plurality of diodes comprises a tapered diode string
arranged in series and having decreasing diode sizes along a length of the tapered diode string.

US Pat. No. 9,356,606

CLOCK GENERATOR USING FREE-RUNNING OSCILLATOR AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. A clock generator comprising:
a free-running LC oscillator having an output for providing an oscillator clock signal;
a tunable frequency synthesizer coupled to said free-running oscillator for providing a clock output signal in response to
said oscillator clock signal and a frequency control signal, said frequency control signal corresponding to a measured characteristic
of said free-running oscillator, wherein said tunable frequency synthesizer comprises a compensation processor for providing
said frequency control signal based on said measured characteristic and a frequency select signal; and

a calibration circuit coupled to said tunable frequency synthesizer for providing a frequency offset signal corresponding
to an offset in frequency between said oscillator clock signal and a reference clock signal as said measured characteristic
in response to said compensation processor.

US Pat. No. 9,231,579

HIGHLY LINEAR BUFFER

Silicon Laboratories Inc....

1. A circuit, comprising:
a first transistor having a first terminal, a second terminal, and a control terminal; and
a non-parasitic feed-forward path coupled to the control terminal and the first terminal, wherein the feed-forward path includes
first circuitry configured to:

decouple the feed-forward path from a DC component of an input signal to the control terminal; and
reduce a voltage between the first and second terminals based on the input signal;
wherein the second terminal is coupled to an output of the circuit;
a complementary transistor configured as a source follower, wherein a source terminal of the complementary transistor is coupled
to the source terminal of the first transistor; and

another feed-forward path coupled to a gate terminal of the complementary transistor and a drain terminal of the complementary
transistor, wherein the another feed-forward path includes second circuitry configured to:

decouple the another feed-forward path from a DC component of the input signal to the gate terminals of the first and complementary
transistors; and

reduce a drain-source voltage of the complementary transistor based on the input signal.

US Pat. No. 9,355,870

INTEGRATED CIRCUIT WITH SENSOR AREA AND RESIN DAM

Silicon Laboratories Inc....

1. An sensor structure comprising:
a substrate;
a sensor region of said substrate, said sensor region configured to allow for an ambient access region of an ambient sensor
of said substrate

a first resin dam on said substrate, the first resin dam extending above a surface of the substrate and
a mold resin on the substrate, the first resin dam being located between the sensor region and the mold resin,
wherein the first resin dam provides a barrier between the mold resin and the sensor region.

US Pat. No. 9,252,891

DIE-TO-DIE COMMUNICATION LINKS FOR RECEIVER INTEGRATED CIRCUIT DIES AND RELATED METHODS

Silicon Laboratories Inc....

1. A multi-die system having die-to-die communications, comprising:a first integrated circuit die, comprising:
a radio frequency (RF) input configured to receive an RF input signal;
receive path circuitry coupled to receive the RF input signal and configured to generate a tuned digital signal representing
content of a channel within the RF input signal based upon a channel selection signal, the receive path circuitry including
analog front end circuitry and digital circuitry;

a spur cancellation module within the digital circuitry configured to generate one or more spur cancellation signals for the
receive path circuitry;

a control module configured to provide one or more control signals to the spur cancellation module; and
a first inter-die transmit and receive module configured to receive one or more operating parameters from a second integrated
circuit die;

wherein the control module is further configured to adjust the one or more control signals for the spur cancellation module
based upon the one or more operating parameters; and
a second integrated circuit die, comprising:
a second inter-die transmit and receive module configured to communicate the one or more operating parameters to the first
inter-die transmit and receive module.

US Pat. No. 9,246,494

METERING CIRCUIT INCLUDING A FLOATING COUNT WINDOW TO DETERMINE A COUNT

Silicon Laboratories Inc....

1. A method comprising:
receiving a count corresponding to a number of peaks of a resonant signal that exceed a reference signal;
comparing the count to a floating count window defined by a first count threshold and a second count threshold, the first
count threshold is larger than the second count threshold; and

selectively shifting the floating count window in a direction of the count when the count falls outside of the floating count
window.

US Pat. No. 9,209,838

LOW-COST RECEIVER USING INTEGRATED INDUCTORS

SILICON LABORATORIES INC....

1. A receiver comprising:
a first amplifier having an input for receiving a radio frequency signal, and an output;
a first filter having an input coupled to the output of the first amplifier, a tuning input, and an output, for substantially
passing frequencies below a variable cutoff frequency, the variable cutoff frequency being less than an upper frequency threshold
of the first filter;

a second filter having an input coupled to the output of the first amplifier, a tuning input, and an output, for substantially
passing frequencies within a band above a lower threshold frequency of the second filter and below an upper threshold frequency
of the second filter;

wherein the first filter comprises:
a first variable capacitor having a first terminal coupled to the output of the first amplifier, a second terminal coupled
to a power supply voltage terminal, and a control terminal for receiving a tuning signal; and

an inductance leg having a first terminal coupled to the output of the first amplifier, and a second terminal coupled to the
power supply voltage terminal, the inductance leg including a first inductor and having an effective resistance in series
with the inductor, wherein the effective resistance has a value related to an upper cutoff frequency to be tuned by the first
filter.

US Pat. No. 9,379,879

NOISE-SHAPING TIME-TO-DIGITAL CONVERTER

Silicon Laboratories Inc....

1. An apparatus comprising:
a time-to-digital converter comprising:
a phase detector configured to generate a phase error signal based on a phase-adjusted feedback signal and an input signal;
a loop filter configured to integrate the phase error signal and generate an analog integrated phase error signal; and
an analog-to-digital converter configured to convert the analog integrated phase error signal to a digital phase error code;
a digital-to-time converter configured to convert at least a portion of the digital phase error code to a gating signal based
on a reference clock signal and an enable signal; and

a feedback circuit configured to generate the phase-adjusted feedback signal based on the reference clock signal and the gating
signal.

US Pat. No. 9,300,227

MONOLITHIC BODY MEMS DEVICES

Silicon Laboratories Inc....

1. An apparatus comprising:
a microelectromechanical system (MEMS) device comprising:
a first electrostatic transducer comprising a body suspended from a substrate and a first electrode suspended from the substrate,
the first electrode being electrostatically coupled to the body; and

a second electrostatic transducer comprising the body and a second electrode suspended from the substrate, the second electrode
being electrostatically coupled to the body and electrically isolated from the first electrode, the first and second electrodes
being mechanically coupled to the body.

US Pat. No. 9,264,080

REDUCING SECOND ORDER DISTORTION IN AN AMPLIFIER

Silicon Laboratories Inc....

1. An apparatus comprising:
a differential amplifier including a first transistor and a second transistor, the differential amplifier coupled to receive
an input radio frequency (RF) signal and to output an amplified RF signal, wherein at least one element of the differential
amplifier is controllable based on a DC output of the differential amplifier, to compensate for a second order intermodulation
product of the apparatus.

US Pat. No. 9,190,957

EFFICIENT DUAL CHANNEL CONVERSION IN A MULTI-BAND RADIO RECEIVER

Silicon Laboratories Inc....

1. An apparatus comprising:
a first signal path to receive and process a radio frequency (RF) signal of a first band and including a first programmable
digitizer to convert the RF signal of the first band into a first digitized signal without downconversion to a lower frequency
signal and a second programmable digitizer to convert a second RF signal of the first band into a second digitized signal
without downconversion to a lower frequency signal.

US Pat. No. 9,190,975

RECEIVER CHIP WITH MULTIPLE INDEPENDENT LOOP-THROUGH PATHS

Silicon Laboratories Inc....

1. A radio receiver comprising:
a radio frequency (RF) receive path configured to convey a first radio signal within a first band to a radio tuning circuit,
wherein the RF receive path is controllable using a first automatic gain control (AGC) circuit; and

a loop-through path configured to convey a second radio signal within a second band between an input and an output of the
radio receiver, wherein the second band is different from the first band, and wherein the loop-through path is controllable
using a second AGC control circuit.

US Pat. No. 9,172,361

MULTI-STAGE DELAY-LOCKED LOOP PHASE DETECTOR

Silicon Laboratories Inc....

1. A phase detector comprising:
a phase propagator circuit including a plurality of flip-flops, each flip-flop including a clock input, the plurality of flip-flops
including a first flip-flop and a second flip-flop, the first flip-flop including an input to receive a signal and including
an output, the second flip-flop including an input coupled to the output of the first flip-flop, the phase propagator circuit
further includes an n-th flip-flop of the plurality of flip-flops, the n-th flip-flop includes an output configured to provide
a phase locked output signal;

a phase controller coupled to the clock input of each flip-flop in the plurality of flip-flops, the phase controller configured
to provide a clock signal to the clock input of each of the plurality of flip-flops, the phase controller to apply different
phases of the clock signal to the plurality of flip-flops, the different phases including a first phase applied to the clock
input of the first flip-flop and a second phase applied to the clock input of the second flip-flop, the first phase is shifted
non-linearly relative to the second phase; and

a phase locator configured to receive a first signal at the output of the n-th flip-flop and to receive a second signal from
the phase controller, the phase locator configured to determine a difference between the first signal and the second signal.

US Pat. No. 9,164,052

INTEGRATED GAS SENSOR

Silicon Laboratories Inc....

1. A gas sensor comprising:
an the integrated circuit, the integrated circuit comprising:
electrical circuits formed utilizing a semiconductor substrate;
an external connection layer configured to provide external connection location for the integrated circuit;
a sensor conductive layer formed above at least a portion of the external connection layer;
an insulative passivation layer formed between the external connection layer and the sensor conductive layer; and
at least one sensor pattern formed in the sensor conductive layer, wherein the sensor pattern is formed in a region above
at least some of the electrical circuits of the integrated circuit.

US Pat. No. 9,379,676

CIRCUITRY AND METHODS FOR COMMON-MODE REJECTION CALIBRATION

Silicon Laboratories Inc....

1. Differential signal circuitry having at least one differential input source configured to receive positive and negative
signal components of an analog differential signal pair, the differential circuitry comprising:
a differential amplifier having a positive input coupled to receive the positive signal of the analog differential signal
pair across a positive signal path from the differential input source, and a negative input coupled to receive the negative
signal of the analog differential signal pair across a negative signal path from the differential input source; and

common mode calibration circuitry coupled within at least one of the positive signal path or negative signal path between
the differential input source and the inputs of the differential amplifier, the common mode calibration circuitry being configured
to programmably vary the impedance of at least one of the positive signal path or negative signal path when a difference exists
between an impedance of the positive signal path and an impedance of the negative signal path so as to reduce the existing
difference in signal path impedance between the positive and negative signal paths.

US Pat. No. 9,219,512

INTEGRATED RECEIVER AND INTEGRATED CIRCUIT HAVING INTEGRATED INDUCTORS AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. An integrated receiver comprising:
a tracking bandpass filter having an input for receiving a radio frequency (RF) input signal, and an output, and comprising
a variable capacitor having a capacitance that varies in response to a bandpass frequency control signal, in parallel with
an integrated inductor;

said integrated inductor comprising a plurality of windings formed in a plurality of metal layers;
a tunable lowpass filter having an input coupled to said output of said tracking bandpass filter, and an output and having
a tuning input for receiving a cutoff frequency signal; and

a mixer having a signal input coupled to said output of said tunable lowpass filter, a local oscillator input for receiving
a local oscillator signal, and a signal output for providing a converted RF signal,

wherein said tracking bandpass filter, said integrated inductor, said tunable lowpass filter, and said mixer are formed on
a single integrated circuit.

US Pat. No. 9,502,399

DIODE STRING CIRCUIT CONFIGURATIONS WITH IMPROVED PARASITIC SILICON-CONTROLLED RECTIFIER (SCR) CONDUCTION DURING ELECTROSTATIC DISCHARGE (ESD) EVENTS

Silicon Laboratories Inc....

1. A semiconductor circuit device, comprising:
a semiconductor substrate;
a diode string including two or more nwell diode structures formed in the substrate, each of the nwell diode structures comprising
at least one N+ doped region and at least one P+ doped region, the N+ doped regions and P+ doped regions of the individual
nwell diode structures being electrically coupled together in series to form a diode string having a first nwell diode structure
disposed at a first end of the diode string and a last nwell diode structure disposed at a second and opposite end of the
diode string; and

at least one N+ doped/nwell guard bar formed in the substrate adjacent at least one side of the first nwell diode structure
with no other well structure physically disposed in the substrate between the first nwell diode structure and the N+ doped/nwell
guard bar, the N+ doped/nwell guard bar being electrically coupled to a first power supply rail of the semiconductor device;

where the semiconductor substrate is electrically coupled to a second power supply rail of the semiconductor device that is
different than the first power supply rail; and

where the at least one N+ doped/nwell guard bar is positioned adjacent the first nwell diode structure to create a silicon-controlled
rectifier (SCR) between the first diode structure and the N+ doped/nwell guard bar through the semiconductor substrate.

US Pat. No. 9,378,782

APPARATUS WITH WRITE-BACK BUFFER AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus comprising:
a source to communicate data;
a storage circuit to store data communicated by the source; and
a write-back buffer to store data communicated by the source in a misaligned write operation in order to improve throughput
between the source and the storage circuit.

US Pat. No. 9,350,412

TRANSCEIVER SUITABLE FOR MULTIPLE POWER LEVEL OPERATION AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. A transceiver comprising:
a transmit/receive terminal;
a receiver input terminal;
a scalable impedance network coupled between said transmit/receive terminal and said receiver input terminal and having a
plurality of taps in an order between said transmit/receive terminal and said receiver input terminal in which an impedance
looking into any given tap toward said transmit/receive terminal is smaller than an impedance looking into a subsequent tap
toward said transmit/receive terminal, if any, in said order;

a plurality of power amplifiers arranged in an order and having outputs respectively coupled to said plurality of taps of
said scalable impedance network, wherein a power of any given power amplifier is higher than a power of a subsequent power
amplifier, if any, in said order; and

a receiver coupled to said receiver input terminal.

US Pat. No. 9,343,971

SYNCHRONOUS VCC GENERATOR FOR SWITCHING VOLTAGE REGULATOR

Silicon Laboratories Inc....

1. A method comprising:
charging a capacitor during a beginning of an ON portion of a pulse width modulated signal to generate a voltage across the
capacitor using charging current sourced from a primary inductor on a primary side of a transformer;

supplying the voltage as a supply voltage to control circuitry in an integrated circuit used to generate the pulse width modulated
signal;

turning on a first transistor during the beginning of the ON portion to cause the charging current to flow through the primary
inductor, through the first transistor, and charge the capacitor;

turning on a second transistor during a second portion of the ON portion after the beginning and before an OFF portion of
the pulse width modulated signal to cause current to flow through the primary inductor and to flow through the second transistor;
and

turning off the first transistor during the second portion to stop charging the capacitor.

US Pat. No. 9,319,027

INJECTING A TONE FOR IMAGE REJECTION CALIBRATION

Silicon Laboratories Inc....

1. An apparatus comprising:
a low noise amplifier (LNA) comprising a first transconductor having an input to receive a differential input radio frequency
(RF) signal via a first differential signal line and a second differential signal line and an output to output a differential
amplified RF signal to a RF signal path; and

a second transconductor having an input coupled to a first common mode node and a second common mode node coupled between
the first differential signal line and the second differential signal line to receive a test tone signal and an output to
output an amplified test tone signal to the RF signal path, wherein the first common mode node is coupled between first and
second parallel capacitors and the second common mode node is coupled between third and fourth parallel capacitors.

US Pat. No. 9,258,596

DEMODULATOR AND MULTI-CHIP MODULE FOR A MULTI-MODE RECEIVER AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. A demodulator for a multi-mode receiver comprising:
a demodulator die including:
a first input port receiving a satellite input signal;
a second input port receiving a terrestrial or cable input signal;
a first transport stream port;
a second transport stream port;
a demodulator core responsive to an input from a selected one of said first input port and said second input port for providing
a first transport stream signal to an output thereof; and

a switching circuit responsive to a first mode for coupling said output of said demodulator core to a selected one of said
first and second transport stream ports while keeping another one of said first and second transport stream ports in a high
impedance state.

US Pat. No. 9,256,558

DIRECT MEMORY ACCESS DESCRIPTOR-BASED SYNCHRONIZATION

SILICON LABORATORIES INC....

1. A method comprising:
processing descriptors to control a direct memory access (DMA) channel;
synchronizing at least part of the processing, the synchronizing comprising processing a first descriptor of the descriptors
to cause the processing to selectively pause based on a trigger value; and

controlling the trigger value, the controlling comprising processing at least one other descriptor associated with another
DMA channel.

US Pat. No. 9,270,288

TIME-TO-DIGITAL CONVERTER BASED ON A VOLTAGE CONTROLLED OSCILLATOR

Silicon Laboratories Inc....

1. A phase-locked loop (PLL) comprising:
a time to voltage converter to convert a phase error corresponding to a time difference between a reference signal and a feedback
signal of the PLL to one or more voltage signals; and

an oscillator-based analog to digital converter (ADC) coupled to receive the one or more voltage signals and convert the one
or more voltage signals to a digital value corresponding to the phase error, the oscillator-based ADC having one or more oscillators
having respective frequencies responsive to the one or more voltage signals.

US Pat. No. 9,246,412

SUSPENDED PASSIVE ELEMENT FOR MEMS DEVICES

Silicon Laboratories Inc....

1. An apparatus comprising:
a microelectromechanical system (MEMS) device comprising:
a first electrode and a second electrode; and
a body suspended from a substrate of the MEMS device, the body and the first electrode forming a first electrostatic transducer,
and the body and the second electrode forming a second electrostatic transducer; and

a suspended passive element mechanically coupled to the body and electrically isolated from the body.

US Pat. No. 9,099,994

RELAXATION OSCILLATOR

Silicon Laboratories Inc....

1. An apparatus comprising:
a first capacitor to pre-charge to a first voltage exceeding a first reference voltage by a first delay compensation voltage
during a first portion of a clock period and thereafter to charge to a second voltage exceeding a second reference voltage
by a second delay compensation voltage during a second portion of the clock period;

a second capacitor to charge to the second voltage during the first portion of the clock period and to pre-charge to the first
voltage during the second portion of the clock period;

a first comparator coupled to the first capacitor to compare a first voltage of the first capacitor to the first reference
voltage during the first clock period portion and to compare the first capacitor voltage to the second reference voltage during
the second clock period portion and to provide a first comparison output to a timing logic circuit; and

a second comparator coupled to the second capacitor to compare a voltage of the second capacitor to the second reference voltage
during the first clock period portion and to compare the second capacitor voltage to the first reference voltage during the
second clock period portion and to provide a second comparison output to the timing logic circuit;

wherein the timing logic circuit receives the first comparison output and the second comparison output and generates a clock
signal based thereon.

US Pat. No. 9,094,042

DAC CURRENT SOURCE MATRIX PATTERNS WITH GRADIENT ERROR CANCELLATION

Silicon Laboratories Inc....

1. A digital-to-analog converter (DAC) comprising:
an array of current elements configured to supply current using thermometer decoding of a code corresponding to at least a
portion of a digital signal to be converted;

wherein for a majority of current elements in the array, pairs of consecutive current elements of the array are placed substantially
symmetrically around a center of the array, such that for each of the pairs, a first and second current element are offset
from the center of the array in a substantially equal and opposite direction.

US Pat. No. 9,491,394

CONFIGURABLE BUFFER FOR AN INTEGRATED CIRCUIT

Silicon Laboratories Inc....

1. A method comprising:
reading a configuration register of a tuner to obtain a control value, the tuner comprising a single chip complementary metal
oxide semiconductor (CMOS) tuner;

controlling a plurality of switches of the tuner based on the control value;
receiving and processing a radio frequency (RF) signal in the tuner to output a driven signal from a driver circuit of the
tuner; and

outputting the driven signal directly from the driver circuit to an output pin of the tuner when the tuner is coupled to an
AC-coupled load, and otherwise buffering the driven signal in an internal buffer of the tuner and coupling the buffered signal
to the output pin when the tuner is coupled to a DC-coupled load.

US Pat. No. 9,106,867

MULTI-TUNER USING INTERPOLATIVE DIVIDERS

Silicon Laboratories Inc....

1. An apparatus comprising:
a plurality of channels for receiving a radio frequency (RF) signal, wherein each of the plurality of channels comprises:
a first amplifier to amplify the RF signal;
a mixer to downconvert the amplified RF signal to a second frequency signal using a local oscillator (LO) signal, each of
the plurality of channels configured to receive a different LO signal;

a first filter to filter the downconverted second frequency signal;
a digitizer to digitize the downconverted second frequency signal; and
a clock generation circuit including a frequency synthesizer to generate a reference clock signal and a plurality of interpolative
dividers, each of the plurality of interpolative dividers to receive the reference clock signal and to generate a corresponding
LO signal therefrom and to provide the corresponding LO signal to the mixer of at least one of the plurality of channels.

US Pat. No. 9,118,392

ISOLATED SERIALIZER-DESERIALIZER

Silicon Laboratories Inc....

1. A method comprising:
receiving input data from a plurality of input channels at a first integrated circuit die;
combining the input data from the plurality of input channels into combined data;
transmitting the combined data from the plurality of input channels serially across an isolation communication channel;
decoding the transmitted combined data at a second integrated circuit die coupled to the isolation communication channel;
and

supplying the decoded transmitted combined data to respective output channels corresponding to the input channels.

US Pat. No. 9,401,726

BACKGROUND CALIBRATION OF TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTERS

Silicon Laboratories Inc....

1. A time interleaved analog-to-digital converter (ADC) comprising:
a reference ADC coupled to receive an analog input signal combined with a calibration signal;
a plurality of sub-ADCs coupled to receive the analog input signal combined with the calibration signal, the sub-ADCs configured
to sample the analog input signal combined with the calibration signal using respective sample clock signals; and

a plurality of calibration circuits coupled to the reference ADC and respective ones of the sub-ADCs, each of the calibration
circuits being configured to determine respective timing errors between the reference ADC and the sub-ADCs and to provide
respective timing mismatch estimates; and

wherein each of the calibration circuits are further configured to adjust a gain of an associated sub-ADC to match a gain
of the reference ADC.

US Pat. No. 9,525,440

TRANSMISSION-BASED TEMPERATURE CONTROL FOR AN ELECTRICAL DEVICE

Silicon Laboratories Inc....

7. An apparatus comprising:
a temperature sensor to sense an ambient temperature;
an integrated circuit comprising:
a radio; and
a processing core to:
estimate a temperature change to the integrated circuit in response to a pending transmission by the radio;
control the radio to regulate at least one parameter of the pending transmission based at least in part on the ambient temperature
sensed by the temperature sensor and the estimated temperature change; and

selectively use a back off time period to regulate a timing of the transmission to maintain the ambient temperature below
a predetermined temperature, wherein the back off time period is associated with a transmission protocol to avoid a conflict
due to a transmission by a device other than the integrated circuit.

US Pat. No. 9,099,922

SYSTEM AND METHOD FOR ADAPTIVE CURRENT LIMIT OF A SWITCHING REGULATOR

SILICON LABORATORIES INC....

1. An adaptive current limiter for a switching regulator, wherein the switching regulator develops a pulse control signal
and adjusts a duty cycle of the pulse control signal to control switching of current through an inductor to convert an input
voltage to an output voltage, the adaptive current limiter comprising:
a conversion network which is configured to provide a limit value based on applying the duty cycle of the pulse control signal
to a reference value; and

an amplifier network which is configured to provide an adaptive current limit signal using said limit value, wherein said
adaptive current limit signal is used by the switching regulator to limit peak current through the inductor.

US Pat. No. 9,553,572

SELF CLOCKING COMPARATOR FOR A CHARGE PUMP

SILICON LABORATORIES INC....

1. A self clocking comparator for clocking a charge pump providing a high voltage output, comprising:
a plurality of gain stages having a first input that receives a sense voltage indicative of the high voltage output of the
charge pump, having a second input that receives a reference voltage, having a reset input, and having an output providing
a compare voltage;

wherein said plurality of gain stages assert said compare voltage to a first voltage level in a default state when said sense
voltage is greater than said reference voltage, and wherein said plurality of gain stages assert said compare voltage to a
second voltage level in a reset state when said sense voltage is less than said reference voltage; and

a reset circuit having an input receiving said compare voltage and having an output providing a reset signal to said reset
input of said plurality of gain stages, wherein said reset circuit asserts said reset signal to force said plurality of gain
stages back to said default state in response to said compare voltage transitioning to said second voltage level, and wherein
said reset circuit negates said reset signal when said compare voltage is at said first voltage level.

US Pat. No. 9,509,278

ROTATIONAL MEMS RESONATOR FOR OSCILLATOR APPLICATIONS

Silicon Laboratories Inc....

1. An apparatus comprising:
a microelectromechanical system (MEMS) device comprising:
a resonator suspended from a substrate;
an anchor disposed at a center of the resonator;
a plurality of suspended beams radiating between the anchor and the resonator;
a plurality of first electrodes disposed about the anchor, the plurality of first electrodes and the resonator forming a first
electrostatic transducer; and

a plurality of second electrodes disposed about the anchor, the plurality of second electrodes and the resonator forming a
second electrostatic transducer,

wherein the first electrostatic transducer and the second electrostatic transducer are configured to sustain rotational vibrations
of the resonator at a predetermined frequency about an axis through the center of the resonator and orthogonal to a plane
of the substrate in response to a signal on the plurality of first electrodes,

wherein each electrode of the pluralities of first and second electrodes comprises an electrode anchor to the substrate and
a suspended surface parallel to a suspended surface of the resonator forming a transduction gap having a length that extends
in a direction radiating from the anchor, the suspended surface of the electrode being orthogonal to the plane of the substrate.

US Pat. No. 9,154,084

LOW-NOISE RECEIVER WITH COMPLEX RF ATTENUATOR

Silicon Laboratories Inc....

1. An apparatus comprising:
an integrated circuit comprising:
a low-noise amplifier having a first complex input impedance; and
a complex attenuator coupled to an input terminal of the integrated circuit, the complex attenuator having a second complex
input impedance and a first complex output impedance, the complex attenuator comprising:

a selectable series impedance circuit having a first selectable impedance coupled between the input terminal of the integrated
circuit and an input of the low-noise amplifier; and

a first shunt circuit having a second selectable impedance, the first shunt circuit being coupled between the input terminal
of the integrated circuit and a first reference node.

US Pat. No. 9,531,284

PSEUDO-CONSTANT FREQUENCY CONTROL FOR VOLTAGE CONVERTER

Silicon Laboratories Inc....

1. A voltage converter having a switching cycle with an ON portion and an OFF portion, the voltage converter comprising:
a current control loop to sense a current flowing through an inductor and to compare the sensed current to a threshold current
value to determine when to end the ON portion by turning off a switch, wherein the current flows through the inductor and
the switch during the ON portion;

a voltage control loop to sense an output voltage of the voltage converter and to determine a difference between the sensed
output voltage and a reference voltage and to supply an indication of the difference for use in determining the threshold
current value; and

a timing control loop to compare a switching frequency of the voltage converter with a target switching frequency and to adjust
the OFF portion of the switching cycle based on the compare of the switching frequency with the target switching frequency;

wherein a bandwidth of the timing control loop is lower than a bandwidth of the voltage control loop.

US Pat. No. 9,490,818

CANCELLATION OF DELTA-SIGMA QUANTIZATION NOISE WITHIN A FRACTIONAL-N PLL WITH A NONLINEAR TIME-TO-DIGITAL CONVERTER

Silicon Laboratories Inc....

1. A method comprising:
performing nonlinear quantization noise cancellation to generate a digital representation of a phase error with reduced quantization
noise, the phase error corresponding to a time difference between a feedback signal of a fractional-N phase-locked loop (PLL)
and a reference signal;

performing the nonlinear quantization noise cancellation in an analog domain to generate an analog representation of the phase
error with reduced quantization noise;

converting the analog representation to a digital representation of the phase error with reduced quantization noise; and
performing cancellation on the digital representation based on residual error associated with the cancellation in the analog
domain to generate a second digital representation with further reduced noise.

US Pat. No. 9,369,146

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER WITH SINGLE-ENDED MEASUREMENT

Silicon Laboratories Inc....

1. A circuit comprising:
a comparator including a first input, a second input, and an output; and
a successive approximation register (SAR) circuit coupled to the output of the comparator, the first input, and the second
input, the SAR circuit configured to program one or more capacitors to selectively apply a bias signal to the first input
and to provide a single-ended measurement of a voltage at the second input.

US Pat. No. 9,257,836

SUPPRESSION OF TRANSIENTS IN COMMUNICATIONS ACROSS AN ISOLATION BARRIER

Silicon Laboratories Inc....

1. An apparatus comprising:
an isolation barrier providing electrical isolation between a first domain including a transmit circuit and a second domain
including a receive circuit;

the receive circuit to receive a signal transmitted across the isolation barrier by the transmit circuit and to provide a
receive circuit output signal; and

a common mode transient suppression circuit coupled to the receive circuit to suppress transients in the receive circuit output
signal that are present in the received signal but not in the signal transmitted;

wherein the common mode transient suppression circuit includes a delay circuit; and
wherein the common mode transient suppression circuit suppresses transients in the receive circuit output signal having an
event length below a predetermined length of time, the predetermined length of time corresponding to a delay associated with
the delay circuit.

US Pat. No. 9,813,023

COMMON-MODE IMPEDANCE NETWORK FOR REDUCING SENSITIVITY IN OSCILLATORS

Silicon Laboratories Inc....

1. An oscillator comprising:
a planar conductive loop comprising a first terminal, a second terminal, and a center tap, the planar conductive loop being
formed from a first conductive layer above an integrated circuit substrate; and

a planar conductive structure extending from a first point proximate to the center tap and extending along a line of symmetry
of the planar conductive loop to a second point proximate to the first terminal and the second terminal,

wherein the center tap is capacitively coupled to an AC ground node using the planar conductive structure, the planar conductive
structure is capacitively coupled to the center tap of the planar conductive loop, and the planar conductive structure is
directly coupled to the AC ground node.

US Pat. No. 9,118,374

INTEGRATED CIRCUIT WITH INTER-CHIP LINK FOR BOOT-UP

SILICON LABORATORIES INC....

1. An integrated circuit comprising:
a first port for conducting a first plurality of signals;
a second port for conducting a second plurality of signals;
a data path coupled between said first port and said second port;
a controller comprising a snooper having an input coupled to said data path, and an output;
a processor having an input and an output; and
a memory coupled to said output of said controller,
wherein in a first mode, said controller causes said data path to conduct at least one signal received on said first port
to said second port and stores data received from said data path in said memory; and

wherein in a second mode, said controller controls said processor to output signals to said second port.

US Pat. No. 9,762,250

CANCELLATION OF SPURIOUS TONES WITHIN A PHASE-LOCKED LOOP WITH A TIME-TO-DIGITAL CONVERTER

Silicon Laboratories Inc....

1. A phase-locked loop (PLL) comprising:
a spur cancellation circuit coupled to receive a residue signal indicative of a first spur frequency and to receive a residual
phase error signal and to generate a spur cancellation signal; and

a circuit to combine the spur cancellation signal and a first phase error signal corresponding to a time difference between
a reference signal and a feedback signal in the PLL and to generate a second phase error signal with a reduced spurious tone
at the first spur frequency.

US Pat. No. 9,503,113

APPARATUS FOR OFFSET TRIMMING AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus comprising:
a first circuit comprising a first transconductance stage to generate a first current, the first circuit having an output
offset;

an offset trim circuit, comprising:
a second circuit to provide an output voltage selectable from a plurality of voltage values; and
a second transconductance stage to generate a second current in response to the output voltage of the second circuit;
wherein the output offset of the first circuit is trimmed by adding the second current to the first current.

US Pat. No. 9,489,000

USE OF A THERMISTOR WITHIN A REFERENCE SIGNAL GENERATOR

Silicon Laboratories Inc....

1. An apparatus comprising:
a first device having a first temperature coefficient;
a thermistor having a second temperature coefficient, the thermistor being coupled in series with the first device and the
second temperature coefficient having a sign opposite to a sign of the first temperature coefficient;

a circuit configured to maintain equivalence of a first signal and a second signal to offset a first temperature variation
of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature
coefficient, the first signal being received by the circuit on a first node, and the second signal being received by the circuit
on a second node; and

a resistor coupled to the second node and having a third temperature coefficient, the third temperature coefficient having
a magnitude substantially less than a magnitude of the first temperature coefficient and substantially less than a magnitude
of the second temperature coefficient.

US Pat. No. 9,342,084

BIAS CIRCUIT FOR GENERATING BIAS OUTPUTS

Silicon Laboratories Inc....

1. An apparatus comprising:
a ready circuit to output a ready indicator when a supply voltage provided to the ready circuit and a voltage regulator is
sufficient to operate the voltage regulator;

the voltage regulator to receive the supply voltage and to output a regulated voltage, the voltage regulator to receive a
first current from the ready circuit and to control the regulated voltage based on the first current when the ready indicator
is inactive;

a bias circuit to receive the regulated voltage and including a first circuit to generate a first bandgap bias current and
a second circuit to generate a second bias current; and

an output circuit to receive a selected one of the first bandgap bias current and the second bias current and output one or
more bias outputs to one or more client circuits based on the selected one of the first bandgap bias current and the second
bias current.

US Pat. No. 9,251,107

IMMEDIATE DIRECT MEMORY ACCESS DESCRIPTOR-BASED WRITE OPERATION

SILICON LABORATORIES INC....

1. A method comprising:
processing a direct memory access (DMA) descriptor in a DMA controller, the DMA descriptor including first data and second
data;

storing the first data at an address identified by the second data,
wherein processing the DMA descriptor comprises:
determining, based on third data of the DMA descriptor, to identify the DMA descriptor as being associated with a first descriptor
type; and

in response to the determination, reading the first data from a field of the DMA descriptor, the field being associated with
a memory address and being associated with a second descriptor type.

US Pat. No. 9,106,265

RECEIVE DATA FLOW PATH USING A SINGLE FEC DECODER

Silicon Laboratories Inc....

1. A receiver comprising:
a frequency deinterleaver (FDI) coupled to receive data and control information including transmission parameters associated
with the data and supply frequency deinterleaved cells corresponding to the data and frequency deinterleaved cells corresponding
to the control information;

a time deinterleaver (TDI) to generate forward error correction (FEC) blocks based on the frequency deinterleaved cells;
a forward error correction (FEC) circuit coupled to the time deinterleaver to apply forward error correction to the FEC blocks
and coupled to the frequency deinterleaver to apply forward error correction to the control information; and

control logic to control outputs from the frequency deinterleaver and the time deinterleaver to prioritize processing of the
control information in the FEC circuit over processing of FEC blocks.

US Pat. No. 9,095,041

METHOD AND APPARATUS FOR REDUCING INTERFERENCE

Silicon Laboratories Inc....

1. A method of reducing interference present in a circuit formed on an integrated circuit comprising the steps of:
identifying a conductive trace on the circuit carrying high frequency digital current; and
placing a conductive strip in the proximity of the identified conductive trace to help contain the high frequency current
flowing through the conductive trace to a component of the circuit formed on the integrated circuit, wherein the conductive
strip has first and second opposite ends, the first end making a connection to a reference voltage, and the second end making
no connection, such that a loop area of a current that flows through a route capacitance formed between the conductive trace
and the conductive strip is reduced.

US Pat. No. 9,846,205

MAGNETIC FIELD GENERATING COIL ON SENSOR DIE

Silicon Laboratories Inc....

1. A method comprising:
activating generation of a first magnetic field by a magnetic field generating coil disposed on an integrated circuit responsive
to an activation indication supplied to the integrated circuit;

measuring the first magnetic field using a magnetic sensor disposed on the integrated circuit; and
responsive to a subsequent activation indication, activating the magnetic field generating coil to cause generation of a second
magnetic field different from the first magnetic field; and

measuring the second magnetic field using the magnetic sensor.

US Pat. No. 9,588,497

DIFFERENTIAL VOLTAGE-CONTROLLED OSCILLATOR ANALOG-TO-DIGITAL CONVERTER USING INPUT-REFERRED OFFSET

Silicon Laboratories Inc....

1. A feedback loop comprising:
an oscillator-based analog-to-digital converter configured to convert an analog signal to a first digital value and a second
digital value, the oscillator-based analog-to-digital converter comprising:

a first oscillator having a first oscillation frequency configured to generate the first digital value based on a first signal
component of the analog signal; and

a second oscillator having a second oscillation frequency configured to generate the second digital value based on a second
signal component of the analog signal, the first and second signal components being complementary signal components; and

a combiner configured to generate a digital value based on the first digital value, the second digital value, and an offset
code, the offset code having a value that increases a difference between the first oscillation frequency and the second oscillation
frequency.

US Pat. No. 9,515,671

APPARATUS FOR GAIN SELECTION WITH COMPENSATION FOR PARASITIC ELEMENTS AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus comprising:
a first circuit having a first programmable gain, the first circuit including a first set of components having parasitic elements;
and

a second circuit having a second programmable gain, the second circuit including a second set of components having parasitic
elements,

wherein the apparatus has a gain that is a product of the first and second programmable gains, and wherein a gain error because
of the parasitic elements of the first and second sets of components is canceled by setting the first programmable gain as
a reciprocal of the second programmable gain.

US Pat. No. 9,413,234

SWITCHING REGULATOR SYSTEM WITH LOW POWER OPERATION

SILICON LABORATORIES INC....

1. A regulator controller for coupling to a voltage source, an inductor and an output capacitor, said regulator controller
comprising:
an input terminal for coupling to the voltage source and for coupling to a first end of the inductor, wherein said input terminal
develops an input voltage;

an inductor terminal for coupling to a second end of the inductor;
at least one output terminal including a first output terminal for coupling to the output capacitor, wherein said first output
terminal develops an output voltage;

a switching circuit coupled to the input terminal and the inductor terminal, wherein said switching circuit selectively couples
said inductor terminal to ground during a charging period and to said at least one output terminal during a discharging period
during a switching cycle;

a switch control circuit coupled to said switching circuit, wherein said switch control circuit sets a duration of said charging
period based on said input voltage and sets duration of said discharging period based on a difference between said input voltage
and said output voltage; and

a discontinuous detection circuit that terminates said switching cycle upon detection of a condition indicative of zero current
through the inductor, wherein said condition indicative of zero current through the inductor comprises a voltage of said inductor
terminal reaching a voltage level of said input terminal.

US Pat. No. 9,390,037

PAD DIRECT MEMORY ACCESS INTERFACE

SILICON LABORATORIES INC....

8. An apparatus comprising:
signal pads;
a set of analog circuitry associated with each of the signal pads, the set of analog circuitry comprising at least one of
an analog-digital converter, a digital-to-analog converter and a comparator;

a direct memory access (DMA) interface comprising:
at least one register to assign at least one group of the signal pads to a direct memory access (DMA) channel;
at least one queue associated with the DMA channel to simultaneously store data indicative of DMA requests associated with
more than one pad of the assigned group of pads; and

pad controllers, wherein each pad controller is associated with a given signal pad of the signal pads and is adapted to communicate
data between the DMA interface and a memory when a DMA channel is assigned to the given pad.

US Pat. No. 9,260,290

TECHNIQUE FOR FORMING A MEMS DEVICE

Silicon Laboratories Inc....

1. An apparatus formed on a substrate including at least one semiconductor device, the apparatus comprising:
a microelectromechanical system (MEMS) device comprising a portion of a first structural layer and a portion of a second structural
layer formed above the first structural layer, the second structural layer having a thickness greater than a thickness of
the first structural layer,

wherein the MEMS device comprises a member comprising the portion of the first structural layer and the portion of the second
structural layer,

wherein the portion of the second structural layer is an attachment attached to the first portion of the first structural
layer.

US Pat. No. 9,106,176

APPARATUS FOR MOTOR CONTROL SYSTEM AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. A motor control apparatus to control a motor external to the motor control apparatus, the motor control apparatus comprising
a microcontroller unit (MCU), the MCU comprising mixed signal motor control circuitry adapted to perform back electromotive
force (EMF) motor control in a first mode of operation, the mixed signal motor control circuitry further adapted to perform
field oriented control (FOC) in a second mode of operation.

US Pat. No. 9,742,209

SYSTEM AND APPARATUS FOR IMPROVING THE UTILITY OF REGULATORS AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An integrated circuit (IC), comprising:
a first circuit powered by a first supply voltage;
a second circuit powered by a second supply voltage, the second supply voltage having a lower level than the first supply
voltage; and

a power management circuit, comprising a switch-mode DC-DC regulator coupled to a plurality of pins of the IC in a pre-defined
configuration, wherein the power management circuit provides the first and second supply voltages to power up the IC in a
default configuration without knowledge of the pre-defined configuration.

US Pat. No. 9,658,975

DATA TRANSFER MANAGER

Silicon Laboratories Inc....

1. An apparatus, comprising:
a direct memory access (DMA) controller coupled to a bus;
a data transfer management (DTM) circuit;
a processor configured to execute program instructions to configure the DTM circuit to provide DMA requests to the DMA controller,
wherein the DMA requests cause the DMA controller to perform:

retrieving a data object; and
transmitting the data object to a peripheral circuit via the bus.

US Pat. No. 9,673,833

ALIGNING ASYNCHRONOUS SIGNALS BY TIME SHIFTING INFORMATION

Silicon Laboratories Inc....

1. A method comprising:
generating a count corresponding to a number of cycles of a ring oscillator;
generating a phase of the ring oscillator corresponding to a fractional cycle of the ring oscillator;
generating a delayed count that is a delayed version of the count corresponding to full cycles of the ring oscillator; and
using the count, the phase, and the delayed count to determine an aligned count that is aligned with the phase.

US Pat. No. 9,590,630

APPARATUS FOR MIXED SIGNAL INTERFACE CIRCUITRY AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An integrated circuit (IC), comprising:
a plurality of pads to communicate with a plurality of sensors external to the IC; and
a plurality of mixed signal interface blocks to process both analog and digital signals, the plurality of the mixed signal
interface blocks coupled to a digital core of the IC via a plurality of corresponding digital interfaces, and coupled to the
plurality of sensors via the plurality of pads;

wherein each mixed signal interface block in the plurality of mixed signal interface blocks receives an analog input signal
from a corresponding sensor in the plurality of sensors and converts the analog input signal to a digital signal in a plurality
of digital signals simultaneously with other mixed signal interface blocks in the plurality of mixed signal interface blocks,
and wherein the plurality of digital signals are provided to the digital core of the IC for processing.

US Pat. No. 9,582,016

BOOST CONVERTER WITH CAPACITIVE BOOST STAGES

Silicon Laboratories Inc....

1. An apparatus comprising:
an inductor coupled between an input voltage node and a switching node;
a switch configured to selectively enable the inductor to generate a voltage on the switching node based on a voltage on the
input voltage node;

a passive circuit configured to receive the voltage on the switching node and a reference voltage on a reference node and
configured to generate an intermediate voltage on an intermediate node with respect to the reference voltage based on the
voltage on the switching node, the passive circuit comprising:

a first capacitor coupled between the switching node and a first node;
a first diode coupled to conduct current from the first node to the reference node;
a second diode coupled to conduct current from the intermediate node to the first node; and
a second capacitor coupled between the intermediate node and the reference node; and
a boost circuit configured to receive the voltage on the switching node and the intermediate voltage and configured to generate
an output voltage on an output node referenced to the intermediate voltage, the output voltage having a magnitude with respect
to the reference voltage greater than a magnitude of the intermediate voltage with respect to the reference voltage.

US Pat. No. 9,048,821

LOW POWER RELAXATION OSCILLATOR

Silicon Laboratories Inc....

1. A relaxation oscillator circuit comprising:
a first comparator including a first input, a second input, a bias input, and an output, the first input coupled to a charging
node, and the second input configured to receive a reference signal; and

a first bias circuit configured to provide a bias signal to the bias input of the first comparator when a first node voltage
on the charging node exceeds a first reference, the first bias circuit comprises a second comparator including:

a first input coupled to the charging node;
a second input configured to receive the first reference; and
an output coupled to the bias input of the first comparator and configured to provide the bias signal.

US Pat. No. 9,705,514

HYBRID ANALOG AND DIGITAL CONTROL OF OSCILLATOR FREQUENCY

Silicon Laboratories Inc....

1. A phase-locked loop comprising:
a digital control path to control a first plurality of varactors within a tank circuit of an oscillator; and
an analog control path to control a second plurality of varactors within the tank circuit to control frequency of the oscillator.

US Pat. No. 9,689,724

RESONANT SIGNAL SENSING CIRCUIT HAVING A LOW POWER MODE

Silicon Laboratories Inc....

10. A metering circuit comprising:
a sensor circuit connected to an input that is coupled to the input to receive the resonant signal corresponding to the usage
of the resource from an external circuit;

a timer circuit to generate a timer signal at selected intervals;
a microcontroller unit configured to remain in a low power mode and to transition to a higher power mode in response to a
wakeup signal; and

a controller coupled to the timer circuit and the sensor circuit, the controller having a first power mode and a second power
mode, the first power mode having a lower power consumption than the second power mode, the controller configured to enter
the second power mode and enable the sensor circuit to capture measurements of the resonant signal in response to receiving
the timer signal, the controller configured to selectively provide the wakeup signal to the microcontroller unit based on
the measurements of the resonant signal.

US Pat. No. 9,627,424

PHOTODIODES FOR AMBIENT LIGHT SENSING AND PROXIMITY SENSING

Silicon Laboratories Inc....

1. A method comprising:
performing ambient light sensing using a first plurality of photodiodes, the ambient light sensing including,
filtering light in a magenta filter that substantially blocks green light and supplying first filtered light from the magenta
filter to a first diode of the first plurality of photodiodes;

filtering light in a cyan filter that substantially blocks red light and supplying second filtered light to a second diode
of the first plurality of photodiodes;

filtering light in a yellow filter than substantially blocks blue light and supplying third filtered light to a third diode
of the first plurality of photodiodes;

supplying broad spectrum light to a fourth diode of the first plurality of photodiodes;
determining an estimate of green light, which includes subtracting light sensed by the first diode from light sensed by the
fourth diode;

determining an estimate of red light, which includes subtracting light sensed by the second diode from light sensed by the
fourth diode;

determining an estimate of blue light, which includes subtracting light sensed by the third diode from light sensed by the
fourth diode; and

performing proximity detection using a second plurality of photodiodes having a deeper junction depth with respect to the
cyan, magenta, and yellow filters than the first plurality of photodiodes.

US Pat. No. 9,602,026

TEMPERATURE COMPENSATION FOR MEMS DEVICES

Silicon Laboratories Inc....

1. An apparatus comprising:
a microelectromechanical system (MEMS) device comprising:
a first electrode and a second electrode; and
a body suspended from a substrate, the body and the first electrode forming a first electrostatic transducer, and the body
and the second electrode forming a second electrostatic transducer, wherein the body comprises:

a temperature compensating structure comprising:
a first beam suspended from the substrate, the first beam being formed from a first material having a first Young's modulus
temperature coefficient;

a second beam suspended from the substrate, the second beam being formed from a second material having a second Young's modulus
temperature coefficient; and

a routing spring suspended from the substrate, the routing spring being coupled to the first beam and the second beam.

US Pat. No. 9,590,644

MANAGING SPURS IN A RADIO FREQUENCY CIRCUIT

Silicon Laboratories Inc....

1. An integrated circuit comprising:
a radio frequency synthesizer configured to provide a local oscillator (LO) signal at a selected frequency related to a channel
of interest within an radio frequency (RF) input signal; and

a re-clocking circuit including a first input to receive a clock signal, a second input to receive a local re-clocking signal
related to the LO signal, and an output to provide a timing output signal, the timing output signal being a selected one of
the clock signal and a local timing output signal corresponding to a frequency adjusted version of the clock signal based
upon the local re-clocking signal;

a control circuit configured to determine a mode and to selectively control the re-clocking circuit to provide the selected
one of the local timing output signal and the clock signal to the output as the local timing output signal; and

a digital circuit including an input to receive the selected one of the local timing output signal and the clock signal as
a digital clock signal.

US Pat. No. 9,565,065

METHODS FOR LIMITING NUMBER OF ROUTERS IN A MESH NETWORK

Silicon Laboratories Inc....

1. A method of creating a mesh network having biconnectivity, said mesh network comprising a plurality of nodes, each node
comprising a processing unit and a network interface, said method comprising:
monitoring network traffic, using a network interface of a node of said plurality of nodes, to determine neighbors of said
node;

querying, using said network interface, each of said neighbors to determine neighbors of said neighbors;
determining, using said node, that at least one of said neighbors is part of a first group and at least a second of said neighbors
is part of a second group, where there are no nodes common to said first group and said second group;

sending a request from said node to find another node in said mesh network which is in communication with said first group
and said second group;

receiving, at a second node, said request from said node, where said second node is not currently a router;
determining said second node can communicate with said first group and said second group; and
enabling routing capability of said second node to create said biconnectivity.

US Pat. No. 9,178,452

CONTROLLER FOR BRUSHLESS DC MOTOR WITH LOW TORQUE RIPPLE AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. A controller for a BLDC motor, comprising:
a pulse width modulator for providing at least one phase control signal for a corresponding phase of the BLDC motor with a
pulse width determined by a duty cycle signal; and

a duty cycle adjustment circuit having a first input for receiving said at least one phase control signal, a second input
for receiving a measured current signal, and an output, wherein said duty cycle adjustment circuit integrates said measured
current signal to form an average current signal, and provides a corresponding modified phase control signal by adjusting
widths of pulses of said at least one phase control signal when said average current signal in said corresponding phase exceeds
a threshold.

US Pat. No. 9,118,533

ANTENNA DIVERSITY COMBINING FOR DIFFERENTIALLY MODULATED ORTHOGONAL FREQUENCY DIVISION MULTIPLEXED (OFDM) SIGNALS

Silicon Laboratories Inc....

1. An apparatus comprising:
a first tuner configured to receive a radio frequency (RF) signal from a first antenna and to process the RF signal to generate
a first time-domain quadrature signal;

a second tuner configured to receive the RF signal from a second antenna and to process the RF signal to generate a second
time-domain quadrature signal;

a combiner circuit configured to receive the first and second time-domain quadrature signals, the combiner circuit including:
a first path circuit configured to convert the first time-domain quadrature signal to a first frequency-domain signal and
to differentially decode the first frequency-domain signal;

a second path circuit configured to convert the second time-domain quadrature signal to a second frequency-domain signal and
to differentially decode the second frequency-domain signal; and

a first combiner configured to combine the first and second decoded frequency-domain signals into a combined frequency-domain
signal;

a re-encoder coupled to the first combiner to generate an estimated signal based on the combined frequency-domain signal;
a first filter configured to filter the first time-domain quadrature signal based at least in part on the estimated signal;
a second filter configured to filter the second time-domain quadrature signal based at least in part on the estimated signal;
and

a second combiner configured to combine the filtered first and second time-domain quadrature signals.

US Pat. No. 9,094,634

AMPLIFIER FOR TELEVISION TUNER CHIP AND METHOD THEREFOR

SILICON LABORATORIES INC....

1. An amplifier, comprising:
a negative gain amplifier having an input and an output;
a load element having a first terminal coupled to a power supply voltage terminal, and a second terminal; and
a transconductance device having a first current electrode coupled to said second terminal of said load element, a control
electrode coupled to said output of said negative gain amplifier, and a second current electrode coupled to said input of
said negative gain amplifier,

wherein said load element comprises a resonant network, said resonant network comprising:
an inductor having a first terminal coupled to said power supply voltage terminal, and a second terminal coupled to said first
current electrode of said transconductance device, and

a capacitor having a first terminal coupled to said power supply voltage terminal, a second terminal coupled to said first
current electrode of said transconductance device.

US Pat. No. 9,742,397

APPARATUS FOR OFFSET CORRECTION IN ELECTRONIC CIRCUITRY AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus comprising:
a first field effect transistor (FET) coupled in a circuit, the first FET having a body;
a second FET coupled in the circuit, the second FET having a body, wherein the circuit has an offset because of a mismatch;
and

an offset correction circuit coupled to the body of the first FET and to the body of the second FET to provide a first offset
correction signal to the body of the first FET and a second offset correction signal to the body of the second FET, wherein
the offset correction circuit comprises a third FET and a fourth FET coupled in a source follower configuration.

US Pat. No. 9,531,253

SOFT-START FOR ISOLATED POWER CONVERTER

Silicon Laboratories Inc....

1. A voltage converter having a switching cycle with an ON portion and an OFF portion, the voltage converter comprising:
a current control loop to sense current flowing through an inductor on a primary side of the voltage converter and to compare
sensed current to a threshold peak current value to determine when to end the ON portion by turning off a switch, the current
flowing through the inductor and the switch during the ON portion; and

a start-up circuit to detect when a secondary side of the voltage converter is supplying an indication of output voltage to
the primary side;

a soft start threshold peak current generator coupled to supply a soft start threshold peak current value to the current control
loop as the threshold peak current value prior to the start-up circuit detecting that the indication of output voltage is
being provided by the secondary side; and

wherein the indication of output voltage from the secondary side is used to generate the threshold peak current value after
detection that the indication is being provided by the secondary side.

US Pat. No. 9,083,354

CLOCK SIGNAL TIMING-BASED NOISE SUPPRESSION

SILICON LABORATORIES INC....

7. An apparatus comprising:
an analog system adapted to synchronize at least one operation to a first clock signal;
a digital system adapted to synchronize at least one operation to a second clock signal, wherein the first and second clock
signals are electrically coupled together; and

a clock regulation circuit adapted to regulate a timing of the first clock signal relative to the second clock signal to control
a noise contained in the first clock signal, the clock regulation circuit comprising:

a phase detector disposed in the analog system to measure a timing of the first clock signal relative to the second clock
signal;

a controllable delay element disposed in the digital system; and
a controller to regulate a delay of the delay element to regulate the timing based on the measurement of the timing by the
phase detector.

US Pat. No. 9,860,392

DIRECT-CURRENT TO ALTERNATING-CURRENT POWER CONVERSION

Silicon Laboratories Inc....

1. A power converter circuit comprises:
a first power converter coupled between a direct-current (DC) node and a first pair of output nodes, the first power converter
configured to convert a DC signal at the DC node into a first power signal and to provide the first power signal having a
first phase to the first pair of output nodes; and

a second power converter coupled between the DC node and a second pair of output nodes, the second power converter configured
to convert the DC signal at the DC node into a second power signal and to provide the second power signal having a second
phase to the second pair of output nodes, the second phase and the first phase differ by an odd multiple of ninety degrees.

US Pat. No. 9,748,963

REDUCING DISTORTION IN AN ANALOG-TO-DIGITAL CONVERTER

Silicon Laboratories Inc....

1. An apparatus comprising:
a first voltage controlled oscillator (VCO) analog-to-digital converter (ADC) unit to receive a first analog signal and convert
the first analog signal into a first digital signal;

a decimation filter circuit to receive the first digital signal and filter the first digital signal into a filtered first
digital signal; and

a cancellation circuit feed forward coupled to receive the filtered first digital signal and generate an output first digital
signal based at least in part on a coefficient value, to reduce third-order distortion.

US Pat. No. 9,710,031

ANALOG INTERFACE FOR A MICROPROCESSOR-BASED DEVICE

Silicon Laboratories Inc....

1. An apparatus comprising:
an integrated circuit comprising a processor and a driver, the integrated circuit being fabricated by a process establishing
a nominal maximum voltage for components of the integrated circuit,

wherein the driver is adapted to selectively electrically couple a voltage higher than the nominal maximum voltage to an external
terminal of the integrated circuit,

wherein the processor is adapted to control the driver to selectively couple together power supply rails, at least one of
the power supply rails being external to the integrated circuit.

US Pat. No. 9,599,643

PEAK DETECTOR

Silicon Laboratories Inc....

1. An apparatus comprising:
a comparator to compare a first signal to a threshold to generate a second signal indicative of the comparison;
an output circuit to receive the second signal and generate at least one third signal indicative of whether a magnitude of
the first signal is within predetermined boundaries; and

a controller to control the threshold for the comparator based at least in part on whether the at least one third signal indicates
that the first signal is within a region defined by the predetermined boundaries.

US Pat. No. 9,588,190

RESONANT MEMS LORENTZ-FORCE MAGNETOMETER USING FORCE-FEEDBACK AND FREQUENCY-LOCKED COIL EXCITATION

Silicon Laboratories Inc....

1. A method comprising:
supplying a current to at least one conductive path integral with a proof mass of a microelectromechanical system (MEMS) device
to thereby exert a Lorentz force on the MEMS device in the presence of a magnetic field; and

determining the magnetic field based on a control value in a control loop configured to apply a feedback force to the proof
mass that opposes the Lorentz force to compensate for a displacement of the proof mass from a nominally stationary position.

US Pat. No. 9,572,109

REDUCED POWER CONSUMPTION IN A WIRELESS NETWORK DEVICE

Silicon Laboratories Inc....

1. A method for reducing power consumption in a device, said device comprising circuitry for transmitting and receiving packets,
and a processing unit, said method comprising:
sending a data request packet from said device to a second device;
receiving an acknowledgement packet from said second device in response to said data request packet, said acknowledgement
packet having an indication regarding whether additional data will be transmitted by said second device;

parsing said acknowledgement packet, using said processing unit, as said acknowledgement packet is received;
disabling said circuitry upon receipt of said indication before receipt of entire acknowledgement packet, if said indication
denotes that additional data will not be transmitted by said second device; and

disabling said circuitry for a predetermined time period after receipt of said acknowledgement packet, if said indication
denotes that additional data will be transmitted by said second device, wherein said acknowledgement packet further comprises
an indication of a minimum time before said second device transmits said additional data, and said predetermined time period
is determined based on said indication of the minimum time.

US Pat. No. 9,812,989

ISOLATED POWER TRANSFER DEVICE

Silicon Laboratories Inc....

1. An apparatus comprising:
an integrated circuit package comprising:
a multi-layer substrate;
a first conductive coil formed using the multi-layer substrate; and
a second conductive coil formed using the multi-layer substrate, the second conductive coil being inductively coupled to the
first conductive coil and electrically isolated from the first conductive coil;

a first integrated circuit die held by the integrated circuit package and electrically coupled to the first conductive coil;
and

a second integrated circuit die held by the integrated circuit package, the second integrated circuit die being electrically
coupled to the second conductive coil and electrically isolated from the first integrated circuit die,

wherein the first conductive coil is configured to transfer power via the second conductive coil from the first integrated
circuit die to the second integrated circuit die.

US Pat. No. 9,712,261

APPARATUS AND METHOD OF BACKGROUND TEMPERATURE CALIBRATION

Silicon Laboratories Inc....

1. A circuit comprises: a timer coupled to a controller; and the controller configured to determine a calibration state of
the circuit, to determine an active mode state of the circuit, to select a type of calibration operation based on the calibration
state, and to control timing of the selected type of calibration operation in response to determining the calibration state
to correspond to a time when the circuit is not active, the controller is configured to perform: a first type of calibration
when the timer exceeds a first threshold; a second type of calibration when the timer exceeds a second threshold; and a third
type of calibration when the timer exceeds a third threshold.

US Pat. No. 9,614,528

REFERENCE BUFFER CIRCUITS INCLUDING A NON-LINEAR FEEDBACK FACTOR

Silicon Laboratories Inc....

1. An apparatus comprising:
an amplifier circuit including a first input to receive a signal, a second input to receive a feedback signal, and an output;
a first buffer circuit including an input coupled to the output of the amplifier and including an output coupled to an output
node;

a second buffer circuit including an input coupled to the output of the amplifier circuit and including an output; and
a feedback circuit coupled between the output nodes of the first and second buffer circuits and the second input of the amplifier
circuit, the feedback circuit including at least one non-linear resistor configured to define a feedback ratio that changes
in response to a voltage at the output node, wherein the at least one non-linear resistor comprises:

a first non-linear resistor coupled between the output node of the first buffer circuit and a feedback node that is coupled
to the second input of the amplifier; and

a second non-linear resistor coupled between the output of the second buffer circuit and the feedback node.

US Pat. No. 9,088,948

REDUCED POWER CONSUMPTION IN A WIRELESS NETWORK DEVICE

Silicon Laboratories Inc....

1. A method for reducing power consumption in a device, said device comprising circuitry for transmitting and receiving packets,
and a processing unit, said method comprising:
receiving a packet from a second device;
parsing said packet, using said processing unit, as said packet is received;
disabling said circuitry upon receipt of data of interest before receipt of entire packet; and
using said processing unit to construct an artificial packet in memory, said artificial packet appearing to be a successfully
received packet;

wherein software is executed by said device and said software comprises a low level layer which communicates with hardware,
and a higher level layer, wherein said low level layer disables said circuitry.

US Pat. No. 9,736,777

REDUCED POWER CONSUMPTION IN A WIRELESS NETWORK DEVICE

Silicon Laboratories Inc....

1. A method of reducing power while attempting to transmit a packet over a channel using a device having a radio component,
said radio component comprising analog circuitry for receiving and transmitting packets and digital circuitry, comprising:
performing a check to determine if said channel is available;
transmitting said packet after said check if said channel is available;
waiting a delay time before a second check is performed if said channel is not available;
powering off the analog circuitry during said delay time;
performing said second check after said delay time, wherein said second check is performed while said analog circuitry is
powered off;

receiving, by software executing on said device, an indication that said second check failed;
powering on said analog circuitry after receiving said indication;
waiting a minimum delay time before a third check is to be performed to determine if said channel is available;
performing said third check after said minimum delay time; and
transmitting said packet after said third check if said channel is available.

US Pat. No. 9,608,681

OUTPUT DRIVER ARCHITECTURE WITH LOW SPUR NOISE

Silicon Laboratories Inc....

1. An apparatus comprising:
a filter to receive a digital input signal via a first input signal path and output a driving signal via an output signal
path, the filter having a feedback input coupled to the output signal path;

an output stage coupled to the filter, the output stage comprising:
a first metal oxide semiconductor field effect transistor (MOSFET) having a gate terminal to receive the driving signal and
a second terminal to output a filtered signal; and

a second MOSFET having a gate terminal to receive a control signal and a second terminal coupled to the second terminal of
the first MOSFET; and

a digital output pad coupled to the output signal path to output the filtered signal, the filtered signal comprising a digital
signal.

US Pat. No. 9,584,133

TEMPERATURE COMPENSATED OSCILLATOR WITH IMPROVED NOISE PERFORMANCE

Silicon Laboratories Inc....

1. An apparatus comprising:
a regulator circuit coupled to receive a first voltage and to supply a second voltage as a regulated voltage;
an oscillator circuit coupled to receive the second voltage and supply an oscillator output signal;
a charge pump circuit coupled to receive the second voltage and supply a third voltage larger than the second voltage to the
regulator circuit,

wherein the regulator circuit has a plurality of stages and wherein a first stage of the plurality of stages includes a first
transistor coupled at a first current carrying terminal to an earlier one of the plurality of stages and the first transistor
is coupled at a second current carrying terminal to supply the second voltage, the first stage further including a first stage
operational amplifier coupled to receive the third voltage as a supply voltage and the first stage operational amplifier is
coupled to receive as inputs a reference signal and the second voltage, and an output of the first stage operational amplifier
is coupled to a gate of the first transistor; and

a reference generator circuit coupled to supply as the reference signal a temperature sensitive reference signal to the regulator
circuit, the reference signal corresponding to a voltage value of the second voltage.

US Pat. No. 9,570,908

POWER MANAGEMENT SYSTEM

Silicon Laboratories Inc....

1. An apparatus comprising:
a system comprising a plurality of loads, a plurality of linear regulators, a controller, an adjustable DC power source and
a plurality of switches, wherein:

the adjustable DC power source is one of a plurality of DC power sources;
the linear regulators receive a plurality of DC voltages, each DC voltage being provided by one of the DC power sources and
the number of the DC power sources being less than the number of linear regulators;

the linear regulators are adapted to supply power to the plurality of loads;
the switches couple the DC voltages to the linear regulators according to one of a plurality of switch configurations; and
the controller is adapted to control both the DC output voltage provided by the adjustable DC power source and select the
switch coupling configuration from the plurality of switch coupling configurations to regulate a collective power dissipation
of the linear regulators.

US Pat. No. 10,075,173

DIGITAL FAST LOCK FOR PHASE-LOCKED LOOPS

Silicon Laboratories Inc....

1. A method comprising:detecting a first edge of an input clock signal in an edge detect circuit and generating an edge detect signal based thereon, the input clock signal being supplied to a phase and frequency detector (PFD) of a phase-locked loop;
generating a feedback signal in a feedback divider responsive to assertion of the edge detect signal, the feedback signal having an initial edge that is substantially aligned with a second edge of the input clock signal;
supplying the feedback signal to the PFD, with the initial edge substantially aligned with the second edge of the input clock signal; and
keeping an output path of the phase-locked loop in a reset condition and releasing the output path of the phase-locked loop substantially simultaneously with releasing the feedback divider to supply the feedback signal.

US Pat. No. 9,866,215

HIGH SPEED LOW CURRENT VOLTAGE COMPARATOR

Silicon Laboratories Inc....

1. An apparatus comprising:
a first comparator having a first common gate input stage with a first input terminal to receive a first voltage and a second
input terminal to receive a second voltage, a first capacitor coupled between the first input terminal and a common gate connection
of the first common gate input stage, the first common gate input stage to output a first comparison signal, and a first feedback
circuit to provide a first boost current to the first common gate input stage responsive to a first value of the first comparison
signal and to pull down a level of the first comparison signal responsive to a first value of a second comparison output signal,
the first comparator to output a first comparison output signal based on the first comparison signal; and

a second comparator having a second common gate input stage with a first input terminal to receive the second voltage and
a second input terminal to receive the first voltage, and a second capacitor coupled between the first input terminal of the
second common gate input stage and a common gate connection of the second common gate input stage, the second common gate
input stage to output a second comparison signal, the second comparator to output the second comparison output signal based
on the second comparison signal.

US Pat. No. 9,793,240

MULTIPLE DIE LAYOUT FOR FACILITATING THE COMBINING OF AN INDIVIDUAL DIE INTO A SINGLE DIE

SILICON LABORATORIES INC....

1. An apparatus comprising:
a wafer portion;
a plurality of die fabricated in the wafer portion in a defined pattern such that the die of the plurality die are separated
from each other by a dicing area or a street, the plurality of die comprising a first die adjacent to a second die;

a conductive connection between the first die and the second die, wherein the conductive connection electrically couples circuitry
disposed on the first die to circuitry disposed on the second die, wherein the conductive connection is electrically interfaced
to a power connection on the first die and a power provided to the first die is applied through the conductive connection
to the second die; and

a material to encapsulate the wafer portion.

US Pat. No. 9,641,186

APPARATUS FOR DIGITAL-TO-ANALOG CONVERSION WITH IMPROVED PERFORMANCE AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus comprising:
a digital-to-analog converter (DAC) to convert a digital input signal to an analog output signal, the DAC comprising:
a decoder to decode the digital input signal and to provide first and second sets of control signals;
a resistor DAC (RDAC) to provide first and second voltages in response to the first set of control signals; and
an interpolator coupled to receive the first and second voltages and to provide a first analog signal in response to the second
set of control signals.

US Pat. No. 9,602,110

OSCILLATOR AMPLIFIER BIASING TECHNIQUE TO REDUCE FREQUENCY PULLING

Silicon Laboratories Inc....

1. An apparatus comprising:
an oscillator circuit configured to generate a clock signal in response to an oscillator bias signal received on a bias node;
and

a bias signal generation circuit configured to generate the oscillator bias signal based on a sensed temperature code and
a predetermined parameter describing a relationship between temperature and an oscillator bias signal level corresponding
to a target frequency of oscillation of the clock signal, the target frequency of oscillation being selected based on a rate
of change of clock signal frequency as a function of the oscillator bias signal level.

US Pat. No. 9,584,347

METHODS AND SYSTEMS FOR RAPID DETECTION OF DIGITAL RADIO SIGNALS

Silicon Laboratories Inc....

1. A receiver system for detecting digital content in a radio frequency (RF) channel, comprising:
front-end circuitry configured to receive radio frequency (RF) signals and to output signals associated with a channel within
the RF signals;

analog-to-digital conversion (ADC) circuitry configured to receive the output signals and to output digital samples having
a real component (I) and an imaginary component (Q);

complex magnitude determination circuitry configured to receive the digital samples and to generate complex magnitudes for
the digital samples;

sliding window averaging filter circuitry configured to subsample the complex magnitudes for each of a plurality of symbols,
to apply a sliding window average to the subsampled complex magnitudes to generate a plurality of averaged subsampled magnitude
values for each symbol based upon subsampled complex magnitudes within sliding windows of subsampled complex magnitudes, and
to output the averaged subsampled magnitude values for each symbol; and

shape detection circuitry configured to determine if digital content is present within the channel having a digital content
shaping function, the digital content shaping function being associated with digital content to be detected, the shape detection
circuitry comprising:

buffer circuitry configured to store the averaged subsampled magnitude values for each symbol, each averaged subsampled magnitude
value having an associated index value; and

detection circuitry configured to detect a minimum value within the stored averaged subsampled magnitude values for each symbol,
to output an index value associated with the detected minimum value for each symbol, and to form an index count histogram
based upon index values output for the plurality of symbols;

wherein the index count histogram includes count values associated with the index values output for the plurality of symbols;
and

wherein the shape detection circuitry is further configured to use the count values within the index count histogram to determine
if digital content is present within the channel having the digital content shaping function;

wherein the digital content is included within OFDM (orthogonal frequency division multiplexed) symbols transmitted within
the channel, and wherein the digital content shaping function comprises a pulse shaping function applied to each OFDM symbol.

US Pat. No. 9,553,565

AUTOMATIC FREQUENCY COMPENSATION METHOD AND APPARATUS

Silicon Laboratories Inc....

1. A method comprising:
receiving a radio signal using a radio receiver;
detecting a preamble in the radio signal;
responsive to detecting the preamble, freezing a control voltage of an automatic frequency compensation (AFC) loop of the
radio receiver for a predetermined time interval;

switching, using a multiplexer and responsive to freezing the control voltage, a clock source of the AFC loop from a first
clock circuit configured to provide a first clock signal to a second, different clock circuit configured to provide a second
clock signal; and

subsequently unfreezing the control voltage of the AFC loop responsive to an indication that the predetermined time interval
has elapsed.

US Pat. No. 9,531,394

CALIBRATION OF DIGITAL-TO-TIME CONVERTER

Silicon Laboratories Inc....

1. An apparatus comprising:
a digital-to-time converter configured to generate an output signal based on a digital code, an input signal, and a gain calibration
signal, the output signal having edges linearly delayed from corresponding edges of the input signal based on the digital
code, the digital code vacillating between an evaluation code and a calibration code;

a reference signal generator configured to provide a delayed version of the input signal, a delay of the reference signal
generator being matched to a delay of the digital-to-time converter; and

a calibration circuit configured to generate the gain calibration signal based on the output signal and the delayed version
of the input signal.

US Pat. No. 10,090,674

MAXIMUM SUPPLY VOLTAGE SELECTION

Silicon Laboratories Inc....

15. An apparatus comprising:an integrated circuit adapted to receive multiple source supply voltages, the source supply voltages comprising a first source supply voltage and a second source supply voltage, and the integrated circuit comprising:
a supply voltage switching circuit to control routing of the source supply voltages to power consuming circuitry;
a passive comparator to respond to a magnitude of a difference between the first source supply voltage and the second source supply voltage being above a threshold to couple the greater of the first source supply voltage and the second source supply voltage to the supply voltage switching circuit;
an active comparator to respond to the magnitude of the difference between the first source supply voltage and the second source supply voltage being below the threshold to compare the first source supply voltage to the second source supply voltage; and
at least one switch to respond to a result of the comparison by the active comparator to couple the greater of the first source supply voltage and the second source supply voltage to the supply voltage switching circuit.

US Pat. No. 9,735,145

ELECTROSTATIC DISCHARGE PROTECTION FOR A BALUN

Silicon Laboratories Inc....

1. An apparatus comprising:
a balun circuit including an input coil and an output coil disposed on an integrated circuit die;
a first bond wire coupled to a first terminal of the balun circuit through a first die pad and coupled to a first output terminal
of an integrated circuit package housing the integrated circuit die;

a second bond wire coupled to a second terminal of the balun circuit through a second die pad and coupled to a second output
terminal on the integrated circuit package, the second output terminal for coupling to a first ground, the first ground being
a board ground of a printed circuit board on which the integrated circuit package is mounted; and

a third bond wire coupled to the second output terminal and to an electrostatic discharge (ESD) circuit on the integrated
circuit die through a third die pad, wherein the ESD circuit is coupled to a second ground, the second ground being an integrated
circuit ground on the integrated circuit die; and

wherein voltage swings on the first and second bond wires are approximately an order of magnitude greater than a voltage swing
at the third die pad.

US Pat. No. 9,736,709

RECEIVER WITH FREQUENCY DEVIATION DETECTION CAPABILITY AND METHOD THEREFOR

Silicon Laboratories Inc....

1. A receiver comprising:
an analog receiver having an input for receiving a radio frequency (RF) signal, and an output for providing a digital intermediate
frequency signal; and

a digital processor having an input for receiving said digital intermediate frequency signal, and an output for providing
digital symbols, wherein said digital processor measures a peak-to-peak frequency deviation of said digital intermediate frequency
signal, and performs a digital signal processing function on said digital intermediate frequency signal to provide said digital
symbols based on said peak-to-peak frequency deviation so measured, wherein said digital processor adjusts a plurality of
nominal slicing levels in response to said peak-to-peak frequency deviation so measured and a nominal peak-to-peak frequency
deviation, said digital processor comprising:

a slicing level calculator for receiving said peak-to-peak frequency deviation and a nominal peak-to-peak frequency deviation,
and for providing a plurality of adjusted slicing levels, said slicing level calculator calculating said plurality of adjusted
slicing levels by multiplying each of said plurality of nominal slicing levels by a ratio of said peak-to-peak frequency deviation
to said nominal peak-to-peak frequency deviation; and

a slicer coupled to said slicing level calculator for determining said digital symbols using said plurality of adjusted slicing
levels.

US Pat. No. 9,705,521

NOISE SHAPING SIGNED DIGITAL-TO-ANALOG CONVERTER

Silicon Laboratories Inc....

1. A method comprising:
selectively enabling a first sequence of unit elements of a plurality of unit elements of a digital-to-analog converter to
convert a signed digital code to a plurality of analog signals in response to a plurality of control signals, individual control
signals of the plurality of control signals and individual analog signals of the plurality of analog signals corresponding
to respective unit elements of the plurality of unit elements; and

generating the plurality of control signals based on a pointer, a magnitude of the signed digital code, and a sign of the
signed digital code,

wherein the pointer has a value based on an immediately prior signed digital code,
wherein in response to the immediately prior signed digital code being a positive digital code, the value is an index to a
last-used element in a sequence of modularly adjacent used elements of the plurality of unit elements, and

wherein in response to the immediately prior signed digital code being a negative digital code, the value is an index to an
unused element modularly adjacent to the last-used element.

US Pat. No. 9,698,767

AC POWER CONTROLLER

Silicon Laboratories Inc....

9. An apparatus comprising:
a line coupled capacitor alternating current (AC) to direct current (DC) converter circuit to obtain power from an alternating
current (AC) power line selectively coupled to a load;

a communication circuit supplied with power from the capacitor AC to DC converter circuit to transmit or receive information
associated with one or more aspects related to power supplied to the load; and

an adaptive triac control circuit to supply during a calibration phase an initial triac gate drive signal that successfully
switches on a triac coupled to receive the initial triac gate drive signal as a triac gate drive signal and to supply as the
triac gate drive signal two or more additional triac gate drive signals having successively lower levels of at least one of
pulse width and current magnitude than the initial triac gate drive signal to determine an effective triac gate drive signal
that successfully switches on the triac, the effective triac gate drive signal having a lower level of at least one of pulse
width and current magnitude than the initial triac gate drive signal.

US Pat. No. 9,537,581

ISOLATOR INCLUDING BI-DIRECTIONAL REGULATOR

Silicon Laboratories Inc....

1. An apparatus comprising:
a first terminal;
a second terminal;
a bi-directional regulator circuit configured to generate a voltage across a first power supply node and a second power supply
node in response to an input current flowing through the first terminal into the bi-directional regulator circuit and from
the bi-directional regulator circuit through the second terminal with a first polarity and configured to generate the voltage
across the first power supply node and the second power supply node in response to the input current flowing through the second
terminal into the bi-directional regulator circuit and from the bi-directional regulator circuit through the first terminal
with a second polarity opposite the first polarity; and

functional circuitry, powered by the voltage and configured to generate a signal using the voltage, the signal being indicative
of presence of the input current.

US Pat. No. 9,124,334

DETECTING DIGITAL RADIO SIGNALS

Silicon Laboratories Inc....

1. An apparatus comprising:
a filter to receive a band limited signal downconverted from a radio signal and to filter the band limited signal according
to a pulse shaping function used to encode the radio signal;

a peak detector to detect peaks within the filter output;
a differentiator coupled to the peak detector to determine a pulse period for each of a plurality of pairs of the detected
peaks; and

a controller to detect presence of a valid signal within the radio signal based at least in part on the detected peaks, wherein
the controller is to determine a number of the plurality of pairs having a pulse period within a threshold range of a symbol
period used in encoding the radio signal.

US Pat. No. 9,819,524

IMAGE REJECTION CALIBRATION WITH A PASSIVE NETWORK

Silicon Laboratories Inc....

17. A receiver comprising:
a complex mixer to downconvert a radio frequency (RF) signal to a complex intermediate frequency (IF) signal;
an IF signal path coupled to the complex mixer, the IF signal path comprising:
an in-phase signal path to receive an in-phase IF signal, the in-phase signal path including a phase correction circuit comprising:
a first series admittance element; and
a first plurality of parallel admittance elements to couple between the in- phase signal path and a selected one of a positive
quadrature signal path node, a negative quadrature signal path node, and a first common mode voltage node;

a quadrature signal path to receive a quadrature IF signal, the quadrature signal path including a gain correction circuit
comprising:

a second series admittance element; and
a second plurality of parallel admittance elements to couple between the quadrature signal path and a selected one of the
positive quadrature signal path node, the negative quadrature signal path node, and a second common mode voltage node.

US Pat. No. 9,793,873

CIRCUITS AND METHODS FOR PROVIDING AN IMPEDANCE ADJUSTMENT

Silicon Laboratories Inc....

1. A method comprising:
controlling a signal source, using a control circuit, during a first mode to selectively apply a signal to an input node configurable
to couple to a power line to receive a power supply;

measuring an electrical parameter of the input node during the first mode using a detector circuit;
determining an impedance associated with the power line in response to measuring the electrical parameter using the control
circuit; and

controlling the signal source, using the control circuit, during a second mode to provide an impedance adjustment signal to
the input node for communication to a remote device through the power line.

US Pat. No. 9,787,310

LEVEL-SHIFTER CIRCUIT FOR LOW-INPUT VOLTAGES

Silicon Laboratories Inc....

1. A method comprising:
receiving an input signal at an input stage of a circuit;
amplifying the input signal using an amplifier of the circuit to produce a level-shifted output signal; and
selectively controlling switches of an active load coupled to the input stage based on the level-shifted output signal to
provide current flow to the input stage during transitions of the input signal and to turn off the current flow to the input
stage between the transitions in the input signal to reduce overall current consumption.

US Pat. No. 9,705,668

DUAL PATH TIMING JITTER REMOVAL

Silicon Laboratories Inc....

1. An apparatus comprising:
a phase detector to supply a phase difference between an input clock signal and a feedback signal;
a gap detector coupled to the phase detector to detect when the phase difference is larger than a gap threshold and generate
a detected difference;

a first circuit responsive to the detected difference being larger than the gap threshold to supply a modified phase difference
in which a gap value is subtracted, the first circuit being responsive to the detected difference being smaller than the gap
threshold to supply the phase difference;

a loop filter coupled to an output of the first circuit to filter the output of the first circuit and supply a loop filter
output;

an oscillator controlled to supply an oscillator output signal according to the loop filter output;
an accumulator circuit coupled to the gap detector to accumulate the gap value and supply a phase adjust signal; and
a first phase adjust circuit coupled in a feedback path between the oscillator and the phase detector and coupled to adjust
a phase of a first phase adjust circuit input signal, to thereby cause the feedback signal to have a phase based, at least
in part, on the phase adjust signal.

US Pat. No. 9,698,807

TIME SIGNAL CONVERSION USING DUAL TIME-BASED DIGITAL-TO-ANALOG CONVERTERS

Silicon Laboratories Inc....

1. An apparatus comprising:
a first time-based digital-to-analog converter configured to generate a first clock signal based on a first reference clock
signal and a first digital code, the first clock signal having one of a delay based on the first digital code and a period
based on the first digital code;

a second time-based digital-to-analog converter configured to generate a second clock signal based on a second reference clock
signal and a second digital code, the first reference clock signal having a first frequency and the second reference clock
signal having a second frequency that is harmonically related to the first frequency; and

a time signal converter configured to generate an output signal having a level indicative of a time-of-arrival of a first
edge of the first clock signal relative to a time-of-arrival of a second edge of the second clock signal.

US Pat. No. 9,696,272

SYSTEMS AND METHODS FOR HUMIDITY MEASUREMENT USING DIELECTRIC MATERIAL-BASED RELATIVE HUMIDITY SENSORS

Silicon Laboratories Inc....

1. A method of operating a relative humidity (RH) sensor to measure RH conditions, the method comprising selecting an initial
test measurement frequency as a current selected test measurement frequency for a humidity-sensitive dielectric material of
the RH sensor; and then:
a) exposing a humidity-sensitive dielectric material of the RH sensor to at least one value of RH while applying the current
selected test measurement frequency to the humidity-sensitive dielectric material of the RH sensor;

b) using at least one processing device to measure a humidity-sensitive electrical parameter value of the RH sensor at the
exposed value of RH while applying the current selected test measurement frequency to the humidity-sensitive dielectric material
of the RH sensor;

c) using at least one processing device to determine a value of sensor shift (S) and/or sensor drift (D) at the current selected
test measurement frequency by comparing the measured humidity-sensitive electrical parameter value to a baseline humidity-sensitive
electrical parameter value previously measured at the same value of RH humidity;

d) selecting at least one new and different test measurement frequency as the current selected test measurement frequency
and iteratively repeating steps a) to d) for at least one additional time with the new current selected test measurement frequency;
and then

e) using at least one processing device to determine an operating humidity measurement frequency based at least in part on
the values of S and/or D determined at previously-selected different test frequencies during multiple iterations of steps
a) to d).

US Pat. No. 9,698,674

TIMING BASED APPROACH FOR EFFICIENT SWITCHED MODE POWER CONVERSION

Silicon Laboratories Inc....

1. A method for operating a voltage converter comprising:
operating the voltage converter in a first charging mode until current through an inductor reaches a first current threshold;
after the first charging mode, changing to operate the voltage converter in an intermediate charging mode, in which current
is supplied to a load until an end of a time period;

in response to the end of the time period operating the voltage converter in a third charging mode, the third charging mode
being a discharge mode;

in a timing control loop,
comparing an output voltage of the voltage converter to a ripple voltage reference and supplying a first comparison indication;
determining the time period for operating in the intermediate charging mode based on the first comparison indication;
in a frequency control loop,
comparing a reference voltage to the output voltage and supplying a second comparison indication;
determining a pulse frequency modulation (PFM) frequency of the voltage converter based in part on the second comparison indication
and based in part on the time period determined in the timing control loop.

US Pat. No. 9,647,670

OSCILLATOR WITH DYNAMIC GAIN CONTROL

SILICON LABORATORIES INC....

1. An oscillator comprising:
an oscillator core circuit for connection to a frequency reference element for providing a first clock signal using a negative
gain element having a gain determined by a gain control signal;

a dynamic gain control circuit for providing said gain control signal to set an absolute value of said gain to a first level
during a startup state, and changing said gain control signal to reduce said absolute value of said gain to a second level
lower than said first level after said first clock signal has reached a steady state, wherein said dynamic gain control circuit
comprises:

an amplitude determination circuit for comparing an amplitude of oscillations of said first clock signal to a voltage threshold
signal; and

a digital controller for providing said voltage threshold signal at a first threshold and said gain control signal at a first
gain corresponding to said first level of said absolute value of said gain during said startup state, and changing from said
startup state to said steady state in response to said amplitude determination circuit comparing said amplitude of oscillations
of said first clock signal to said voltage threshold signal,

wherein said digital controller is further programmable to calibrate said gain control signal to a second gain for operation
in said steady state after setting said voltage threshold signal to a second threshold.

US Pat. No. 9,621,170

ACCURATE FREQUENCY CONTROL USING A MEMS-BASED OSCILLATOR

Silicon Laboratories Inc....

1. A method comprising:
selecting one or more attributes of error information through a programming interface, the one or more attributes including
a selectable number of bits of resolution of the error information, the error information indicating a difference between
a first frequency and a target frequency;

generating an oscillator output signal having the first frequency with a micro electro mechanical system (MEMS) oscillator
on a first integrated circuit;

determining temperature in a temperature sensor and providing an indication of sensed temperature;
determining frequency error in the oscillator output signal due to temperature based on the indication of sensed temperature;
determining the error information by combining the frequency error determined based on the indication of sensed temperature
and frequency error due to an initial frequency offset of the MEMS oscillator from the target frequency;

supplying the oscillator output signal and the error information from two or more output terminals of the first integrated
circuit, to a receiving system on a second integrated circuit;

determining a frequency translation ratio of the oscillator output signal in the receiving system based on the error information
and on desired frequency information;

generating a clock signal in a frequency translation circuit in the receiving system based on the oscillator output signal
and the frequency translation ratio; and

supplying the clock signal to functional circuitry of the receiving system.

US Pat. No. 9,612,893

PERIPHERAL WATCHDOG TIMER

Silicon Laboratories Inc....

1. A circuit comprising:
a plurality of peripherals; and
a peripheral watchdog timer circuit coupled to at least one of the plurality of peripherals, the peripheral watchdog timer
circuit configured to count clock cycles and concurrently to detect activity associated with at least one of the plurality
of peripherals, the peripheral watchdog timer circuit configured to reset a count in response to detecting the activity.

US Pat. No. 9,564,915

APPARATUS FOR DATA CONVERTER WITH INTERNAL TRIGGER CIRCUITRY AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An integrated circuit (IC), comprising:
an analog-to-digital converter (ADC), comprising:
an ADC core circuit integrated in the IC to receive an analog signal, to convert the analog signal to a digital signal in
response to a trigger signal, and to provide the digital signal as an output of the ADC; and

internal trigger circuitry integrated in the ADC to provide the trigger signal to the ADC after a prescribed delay period
has expired.

US Pat. No. 9,806,521

ELECTROSTATIC DISCHARGE PROTECTION FOR A TRANSFORMER BALUN

Silicon Laboratories Inc....

1. An apparatus comprising:
an input coil and an output coil having a center point connection, the input coil and the output coil forming a balun; and
an electrostatic discharge (ESD) circuit configured to couple the center point connection to a reference voltage node through
the ESD circuit responsive to a voltage at the center point connection being above a first threshold voltage and the ESD circuit
is responsive to isolate the center point connection from the reference voltage node responsive to the voltage at the center
point connection being below the first threshold voltage and above a second threshold voltage;

wherein ESD circuit is further configured to couple the center point connection to the reference voltage node through a first
circuit responsive to the voltage at the center point connection being below the second threshold voltage;

wherein the voltage at the center point connection varies but is substantially stable during normal operation as compared
to positive and negative outputs of the balun and the voltage at the center point connection remains within several tenths
of volts of zero volts during normal operation.

US Pat. No. 9,787,388

FULLY FLEXIBLE MULTI-TUNER FRONT END ARCHITECTURE FOR A RECEIVER

Silicon Laboratories Inc....

1. An apparatus comprising:
a first low noise amplifier (LNA) to receive and amplify a first radio frequency (RF) signal of a first band, received from
a first antenna;

a first tuner having a first plurality of mixers including a first mixer to selectively be coupled to the first LNA to receive
and downconvert the first RF signal received from the first LNA to a first downconverted signal, the first tuner to process
the first downconverted signal;

a second LNA to receive and amplify a second RF signal of a second band, received from a second antenna; and
a second tuner having a second plurality of mixers including a second mixer to selectively be coupled to the second LNA to
receive and downconvert the second RF signal received from the second LNA to a second downconverted signal and a first mixer
to selectively be coupled to the first LNA to receive and downconvert the first RF signal received from the first antenna
to a third downconverted signal, the second tuner controllable to process a selected one of the second downconverted signal
and the third downconverted signal provided by a selected one of the second mixer and the first mixer of the second tuner.

US Pat. No. 9,674,010

UPDATING A FILTER OF AN EQUALIZER

Silicon Laboratories Inc....

1. A tuner comprising:
an analog front end to receive a radio frequency (RF) signal and to downconvert the RF signal to a second frequency signal;
a digitizer to convert the second frequency signal to a digitized signal;
a channel equalizer including a filter to filter the digitized signal;
a first controller to update the filter according to a frequency response of the filter, the first controller comprising:
a frequency response determination logic to receive a plurality of taps of the filter and determine based thereon a magnitude
value of the frequency response of the filter;

a comparison logic to compare the magnitude value to a reference value to generate an error signal based on a cost function
according to

and
a tap update logic to update one or more taps of the plurality of taps of the filter based on the error signal.

US Pat. No. 10,090,838

OVER VOLTAGE TOLERANT CIRCUIT

Silicon Laboratories Inc....

1. A method comprising:using a first transistor of an input/output (I/O) circuit of an integrated circuit to couple an I/O pad of the integrated circuit to an output terminal of logic to communicate a signal provided by the logic to a driver circuit of the I/O circuit;
coupling a source terminal of an n-channel metal-oxide-semiconductor field effect transistor (NMOSFET) to a control terminal of the first transistor;
coupling a gate terminal of the NMOSFET to the supply voltage;
coupling a drain terminal of the NMOSFET to an enable signal;
controlling the enable signal to control whether the first transistor is activated or deactivated; and
inhibiting a leakage current in the first transistor due to a voltage of the pad exceeding a supply voltage of the integrated circuit when the enable signal causes the first transistor to be deactivated, wherein inhibiting the leakage current comprises:
coupling a control terminal of a switch to the supply voltage;
activating the switch in response to the voltage of the pad exceeding the supply voltage to transition the switch from a first state of the switch in which the switch is deactivated to a second state in which the switch couples the control terminal of the first transistor to the voltage of the pad;
using a comparator to compare the voltage of the pad to the supply voltage; and
coupling the output terminal of the comparator to a substrate associated with the first transistor.

US Pat. No. 10,057,051

DUAL PATH TIMING WANDER REMOVAL

Silicon Laboratories Inc....

1. A method comprising:determining a timing difference between a first signal and a second signal and supplying the timing difference;
detecting in an excursion detector if a magnitude of the timing difference is above a predetermined timing threshold and supplying as an excursion detector output a first adjustment if the magnitude of the timing difference is above the predetermined timing threshold and supplying as the excursion detector output a second adjustment if the magnitude of the timing difference is below the predetermined timing threshold;
supplying the excursion detector output to an arithmetic circuit and adjusting the timing difference by the first or the second adjustment;
supplying a loop filter with an output of the arithmetic circuit and generating a loop filter output;
controlling an oscillator based on the loop filter output and supplying an oscillator output signal; and
low pass filtering the output of the excursion detector and supplying a low pass filtered output.

US Pat. No. 9,823,687

LOW FREQUENCY PRECISION OSCILLATOR

SILICON LABORATORIES INC....

1. A method comprising:
using a first oscillator to clock operations of a radio of an integrated circuit (IC);
intermittently using the first oscillator to frequency tune a second oscillator of the IC, wherein intermittently using the
first oscillator to frequency tune the second oscillator comprises intermittently changing a dithering applied to an oscillation
frequency of an oscillator core of the second oscillator;

using the oscillator core to provide a signal cycling between an upper threshold and a lower threshold at the oscillation
frequency of the oscillator core; and

dithering the upper and lower thresholds,
wherein intermittently changing the dithering applied to the oscillation frequency comprises intermittently adjusting the
dithering of the upper and lower thresholds.

US Pat. No. 9,817,636

GENERATING AN ENTROPY SIGNAL

Silicon Laboratories Inc....

1. A method comprising:
using an analog-to-digital converter (ADC) to provide an entropy signal at an output of the ADC; and
controlling a reference signal to the ADC to cause an internal noise level of the ADC to correspond to more than one least
significant bit (LSB) voltage of the ADC.

US Pat. No. 9,804,573

USE OF REDUNDANCY IN SUB-RANGING TIME-TO-DIGITAL CONVERTERS TO ELIMINATE OFFSET MISMATCH ISSUES

Silicon Laboratories Inc....

1. An apparatus comprising:
a fine time-to-digital converter (TDC) providing fine time information with a first resolution, wherein the fine TDC is configured
to roll over from a maximum value to a minimum value;

a coarse TDC providing coarse time information with a second resolution, the second resolution more coarse than the first
resolution and the second resolution is less than a range of the fine TDC such that a first portion of the fine time information
and a second portion of the coarse time information overlap and provide redundancy;

a compare circuit to compare the first portion of the fine time information and the second portion of the coarse time information
and supply a mismatch indication in response to the first portion and the second portion not matching; and

a correction circuit to correct the second portion responsive to the mismatch indication.

US Pat. No. 9,712,176

APPARATUS FOR LOW POWER SIGNAL GENERATOR AND ASSOCIATED METHODS

Silicon Laboratories Inc....

1. An apparatus comprising:
a signal generator comprising:
a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency; and
an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal having a frequency lower
than the frequency of the output signal of the VCO,

wherein the asymmetric divider presents a balanced load to the VCO.

US Pat. No. 9,647,623

SIGNAL PROCESSOR SUITABLE FOR LOW INTERMEDIATE FREQUENCY (LIF) OR ZERO INTERMEDIATE FREQUENCY (ZIF) OPERATION

Silicon Laboratories Inc....

1. A signal processor for a radio frequency (RF) receiver, comprising:
a first filter having an input for receiving an input signal, and an output;
a first automatic gain control (AGC) loop having an input coupled to said output of said first filter, and an output;
a second filter having an input coupled to said output of said first AGC loop, and an output; and
a second AGC loop having an input coupled to said output of said second filter, and an output;
wherein said first AGC loop and said second AGC loop are independent of each another,
and wherein each of said first and second AGC loops comprises:
a programmable gain amplifier having an input forming an input of a respective AGC loop, a control input, and an output;
a peak detector having an input coupled to said output of said programmable gain amplifier, and an output; and
a controller having an input coupled to said output of said peak detector, and an output coupled to said control input of
said programmable gain amplifier,

wherein said controller of said first and second AGC loops comprises:
a microcontroller having an input coupled to said output of said peak detectors of said first and second AGC loops, and an
output coupled to said control input inputs of said programmable gain amplifiers of said first and second AGC loops; and

firmware coupled to said microcontroller and operable to cause said microcontroller to implement said controller of each of
said first and second AGC loops.