US Pat. No. 9,147,739

METHOD OF FORMING POLYSILICON IN A TRENCH

Silergy Semiconductor Tec...

1. A method for forming polysilicon in a trench, comprising:
providing a substrate;
forming a first dielectric layer on said substrate;
forming an opening in said first dielectric layer by etching;
forming a trench in said substrate by etching through said opening;
forming a second dielectric layer on sidewalls of said trench;
forming polysilicon on a surface of said substrate and on a surface of said second dielectric layer in said trench;
applying a sacrificial layer made of photoresist or spin-on glass on a surface of polysilicon to provide a flat surface; and
removing said sacrificial layer and a portion of polysilicon on said surface of said substrate successively by etching, while
a portion of polysilicon remaining in said trench is etched to a predetermined depth below said surface of said substrate.

US Pat. No. 9,408,265

MULTICHANNEL CONSTANT CURRENT LED DRIVING CIRCUIT, DRIVING METHOD AND LED DRIVING POWER

Silergy Semiconductor Tec...

1. A multichannel constant current light-emitting diode (LED) driving circuit configured to drive a plurality of LED strings,
the LED driving circuit comprising:
a) a power stage circuit having a power switching transistor, an inductor, and a rectifier circuit, wherein said power stage
circuit is configured to receive a DC bus voltage, and to generate a pseudo-constant output signal to drive said plurality
of LED strings;

b) a current control unit configured to control an average current of each of said plurality of LED strings in accordance
with a corresponding one of a plurality of dimming signals; and

c) said current control unit being configured to control said power switching transistor in accordance with a current feedback
signal that represents a current flowing through said LED strings, wherein said plurality of LED strings are coupled in series
to receive said pseudo-constant output signal.

US Pat. No. 9,362,833

CONSTANT VOLTAGE CONSTANT CURRENT CONTROL CIRCUITS AND METHODS WITH IMPROVED LOAD REGULATION

Silergy Semiconductor Tec...

1. A constant voltage/constant current (CVCC) control circuit for regulation of a load of a flyback switch mode power supply
(SMPS), the CVCC control circuit comprising:
a) a voltage feedback circuit configured to generate an output voltage feedback signal;
b) a current feedback circuit configured to generate an output current feedback signal;
c) a control signal generating circuit configured to receive said output voltage feedback signal and said output current feedback
signal, to control whether said flyback SMPS operates in a constant voltage mode or a constant current mode based on a first
control signal and an error signal, and to generate a CVCC control signal;

d) a first enable signal generating circuit configured to compare a first reference voltage and said CVCC control signal to
generate a first enable signal;

e) a pulse-width modulation (PWM) controller configured to generate a PWM control signal based on said CVCC control signal
to control a main switch of said flyback SMPS, wherein said PWM control signal is configured to control operation of said
main switch when said first enable signal is inactive and a second enable signal is active, and wherein said main switch remains
off when said first enable signal is active or said second enable signal is inactive; and

f) a second enable signal generating circuit configured to receive said output voltage feedback signal and a second reference
voltage, and to generate said second enable signal, wherein said PWM control signal is configured to control said operation
of said main switch when said CVCC control signal is higher than said first reference voltage and said output voltage feedback
signal is less than said second reference voltage, and wherein said main switch is controlled to be off when said CVCC control
signal is less than said first reference voltage or said output voltage feedback signal is higher than said second reference
voltage.

US Pat. No. 9,473,034

ISOLATED POWER CONVERTER AND SWITCHING POWER SUPPLY USING THE SAME

Silergy Semiconductor Tec...

1. An isolated power converter, comprising:
a transformer with a primary winding and a secondary winding;
a secondary rectifier coupled with said secondary winding;
a power switch and a current sampling circuit coupled in series between an input power source and a first terminal of said
primary winding, wherein a second terminal of said primary winding is coupled with a ground, wherein said current sampling
circuit is configured to sample a current through said power switch to output a current detection signal;

a voltage feedback circuit coupled in parallel with said primary winding and configured to output a feedback voltage in accordance
with a voltage across said primary winding;

a bias voltage generating circuit coupled with said input power source and configured to provide a bias voltage for said control
circuit; and

a control circuit configured to output switching control signal in accordance with said current detection signal and said
feedback voltage, and said control circuit is powered by said bias voltage;

wherein, both ground terminals of said control circuit and said bias voltage generating circuit are coupled with said first
terminal of said primary winding.

US Pat. No. 9,420,652

LED DRIVER

Silergy Semiconductor Tec...

1. A LED driver comprising a rectifier circuit, a driving current generating circuit, a bus voltage detection circuit, a LED
configuration control circuit, and a LED array,
wherein said rectifier circuit has an input for receiving an AC voltage and an output for providing a DC output voltage which
is obtained by rectifying said AC voltage;

said driving current generating circuit has an input for receiving said DC voltage and an output for providing a driving current
to said LED array;

said bus voltage detection circuit detects a bus voltage in said driving current generating circuit and has an output for
providing a value of said bus voltage;

said LED configuration control circuit controls on and off states of LEDs in said LED array in accordance with said value
of said bus voltage; and

said LED array comprises a plurality of LEDs connected in series with each other and one or more switches each connected in
parallel with at least one of said plurality of LEDs, and said LED configuration control circuit controls on and off states
of said switches,

wherein said driving current generating circuit outputs said driving current which is adjusted in accordance with an actual
operation state of each LED in said LED array,

said driving current generating circuit divides said bus voltage into a plurality of voltage levels, and divides said driving
current into a plurality of current levels,

when said bus voltage detection circuit detects that said level of said bus voltage decreases gradually, the number of said
LEDs connected in series in an on state decreases gradually, and said driving current increases to corresponding one of said
plurality of current levels;

when said bus voltage detection circuit detects that said level of said bus voltage increases gradually, said number of said
LEDs connected in series in an on state increases gradually, and said driving current decreases to corresponding one of said
plurality of current levels.

US Pat. No. 9,351,362

DIMMING CIRCUIT AND METHOD FOR LEDS

Silergy Semiconductor Tec...

1. A dimming circuit for LEDs which obtains a DC voltage from an external AC power supply by using a TRIAC, an electronic
transformer, and a rectifier bridge sequentially, comprising:
a first power stage circuit having an input terminal configured to receive said DC voltage;
a second power stage having an input terminal coupled to an output terminal of said first power stage and an output terminal
coupled to an LED load;

a first control circuit configured to generate a first control signal in accordance with a first output voltage generated
at said output terminal of said first power stage circuit, a first reference voltage and an upper threshold voltage to maintain
an average value of said first output voltage to be consistent with said first reference voltage; and

a second control circuit configured to generate a dimming signal and control an operation of said second power stage circuit
in accordance with said dimming signal to maintain an output current of said second power stage circuit to be consistent with
an expected driving current represented by said dimming signal,

wherein said dimming circuit operates in one of a first operating mode and a second operating mode,
in said first operating mode, an input current of said first power stage circuit is maintained to be a first current which
is no less than a holding current of said electronic transformer, when said first output voltage is in a continuously increasing
state and is less than said upper threshold voltage, in a time period during which said TRIAC is turned on, in each half-sinusoidal
wave period of said AC power supply, and said second control circuit generates said dimming signal in accordance with said
first current,

in said second operating mode, said input current is maintained to be said first current when said first output voltage is
in a continuously increasing state and is less than said upper threshold voltage, and said input current is maintained to
a second current after said first output voltage reaches said upper threshold voltage and then decreases continuously, after
said TRIAC is turned on, in each half-sinusoidal wave period of said AC power supply, and said second control circuit generates
said dimming signal in accordance with said first current and said first output voltage.

US Pat. No. 9,324,633

MULTI-LEVEL PACKAGE ASSEMBLY HAVING CONDUCTIVE VIAS COUPLED TO CHIP CARRIER FOR EACH LEVEL AND METHOD FOR MANUFACTURING THE SAME

SILERGY SEMICONDUCTOR TEC...

1. A package assembly comprising:
a plurality of semiconductor chips stacked in a plurality of levels, including a lowermost level and at least one upper level;
a plurality of encapsulant layers stacked in a plurality of levels, each encapsulating respective one level of said semiconductor
chips and having a respective upper surface; and

a chip carrier for mounting lowermost-level semiconductor chips,
wherein at least one upper-level semiconductor chip is electrically coupled to said chip carrier by conductive traces, said
conductive traces comprising:

extension conductors formed on an upper surface of a lower-level encapsulant layer; and
conductive vias which penetrate said lower-level encapsulant layer and are exposed at a bottom surface of said package assembly.

US Pat. No. 9,491,817

LED DRIVING CIRCUIT

Silergy Semiconductor Tec...

1. An LED driving circuit, comprising:
a) a rectifier circuit configured to receive an AC input power supply through a tri-electrode AC switch (TRIAC), and to generate
a bus voltage;

b) a driving current generator configured to convert said bus voltage to a constant driving current and an output voltage
to drive an LED load; and

c) a current distribution circuit coupled between a positive pole and a negative pole of said bus voltage, wherein said current
distribution circuit is configured to sample an input current to generate a sense signal, and to compare said sense signal
against a voltage reference signal that represents an expected input current, so as to regulate said input current according
to said voltage reference signal.

US Pat. No. 9,491,818

LED DRIVER ADAPTED TO ELECTRONIC TRANSFORMER

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver adapted to an electronic transformer, the LED driver comprising:
a) a rectifier bridge and a power stage circuit coupled between said electronic transformer and an LED load, wherein said
power stage circuit comprises an inductor and a power switch;

b) a first control circuit configured to control said power switch to regulate a current of said inductor and to maintain
an output voltage of said power stage circuit as substantially constant based on a first sense signal and a first voltage
feedback signal, wherein said first sense signal represents said inductor current, and wherein said first voltage feedback
signal represents said output voltage of said power stage circuit;

c) an inductor current clamping circuit in said first control circuit, wherein said inductor current clamping circuit comprises
a voltage source coupled to a diode to provide a clamping voltage that matches a holding current of said electronic transformer,
wherein said inductor current clamping circuit is configured to clamp a voltage control signal to said clamping voltage when
said voltage control signal is less than said clamping voltage such that said inductor current is clamped to said holding
current when said inductor current is less than said holding current;

d) a current stabilizing control circuit configured to detect a current of said LED load to generate a detection signal, and
to maintain said LED load current as substantially constant based on said detection signal; and

e) said first control circuit comprising a voltage control circuit configured to receive said first voltage feedback signal
and a first reference voltage signal, and to generate said voltage control signal, wherein said clamping voltage is provided
to a current control loop as a reference voltage signal when said voltage control signal is less than said clamping voltage,
wherein said voltage control signal is provided to said current control loop as said reference voltage signal when said voltage
control signal is greater than said clamping voltage, and wherein said current control loop is configured to receive said
first sense signal and said reference voltage signal, and to generate a first control signal to control said power switch.

US Pat. No. 9,171,921

TRENCH MOSFET AND METHOD FOR FABRICATING THE SAME

Silergy Semiconductor Tec...

1. A method for fabricating a trench MOSFET, comprising:
providing a substrate having a body of a first conductivity type and an epitaxy layer of said first conductivity type on said
body;

forming a trench by etching said epitaxy layer;
depositing a first insulating layer and a first polysilicon layer successively on said epitaxy layer, said first polysilicon
layer filling said trench;

forming a first gate in said trench by etching said first polysilicon layer;
etching off an exposed portion of said first insulating layer, and depositing a second insulating layer and a second polysilicon
layer successively, said second polysilicon layer filling said trench;

forming a second gate in said trench by etching said second polysilicon layer;
forming a well of a second conductivity type by performing a first ion implanting after etching off an exposed portion of
said second insulting layer to expose said epitaxy layer;

forming a source region of said first conductivity type by performing a second ion implanting at said surface of said well;
depositing a third insulating layer on said source region and over said trench;
forming a gate opening and a source opening by etching, said gate opening extending through said third insulating layer, said
second gate, said second insulating layer and into said first gate, and said source opening extending through said third insulating
layer, said source region and into said well; and

forming metal plugs by filling a metal layer in said gate opening and in said source opening, respectively.

US Pat. No. 9,136,248

MULTI-CHIP STACKED PACKAGE AND METHOD FOR FORMING THE SAME

Silergy Semiconductor Tec...

1. A multi-chip stacked package comprising:
a chip carrier;
multiple levels of chips, with one or more chips being arranged in each level and;
a patterned conductor layer on a back surface of a lower one of two chips in two adjacent levels;
a plurality of first conductive bumps between at least one lowermost chip and said chip carrier,
a plurality of second conductive bumps between two adjacent levels of chips; and
wherein one or more levels of chips, except for topmost chips, have conductive vias,
said plurality of first conductive bumps provide electrical connections with said at least one lowermost chip, and with at
least one upper chip,

said conductive vias of a lower chip are electrically coupled to an upper chip by means of said patterned conductor layer
and said plurality of second conductive bumps.

US Pat. No. 9,379,088

STACKED PACKAGE OF VOLTAGE REGULATOR AND METHOD FOR FABRICATING THE SAME

Silergy Semiconductor Tec...

1. A method for fabricating a stacked package of a voltage regulator, comprising:
forming a first chip by integrating a gate driving circuit with a first power switch, forming a second chip having a second
power switch, arranging a plurality of terminals on a front surface of said first chip and on a front surface of said second
chip, and arranging a plurality of terminals on a back surface of said second chip;

forming a group of bumps corresponding to said plurality of terminals on said front surface of said first chip and on said
front surface of said second chip;

forming a non-conductive layer and conductive layer side by side on said back surface of said second chip, for electrically
insulating said first chip from said second chip and electrically coupling said first chip to said second chip respectively;

providing a first leadframe and a second leadframe each having at least a group of leads, all of said leads of said first
leadframe being electrically coupled to said terminals on said front surface of said first chip by means of said bumps of
said first chip, and some of said leads of said second leadframe being electrically coupled to said terminals on said front
surface of said second chip by means of said bumps of said second chip;

electrically coupling said back surface of said first leadframe to said back surface of said second chip;
electrically coupling said leads of said first leadframe to the corresponding ones of said second leadframe by using a group
of electrical wires so that said leads of said second leadframe may be coupled to an external circuit; and

encapsulating said first chip, said second chip, said conductive layer, said non-conductive layer, said plurality of bumps,
said first leadframe, said second leadframe and said group of electrical wires in a stacked package.

US Pat. No. 9,245,977

VERTICAL DOUBLE-DIFFUSION MOS AND MANUFACTURING TECHNIQUE FOR THE SAME

Silergy Semiconductor Tec...

1. A method of making a vertical double-diffusion MOS (VDMOS) transistor, the method comprising:
a) etching an isolated oxide layer formed on a surface of an epitaxial structure to define an active region of said VDMOS
transistor;

b) injecting a first dopant into said active region, and diffusing said first dopant to form a doping region, wherein said
doping region comprises a body region for said VDMOS transistor;

c) after said body region is formed, forming a gate oxide layer on a surface of said active region;
d) depositing polysilicon on said gate oxide layer, and etching said polysilicon to form a gate;
e) injecting a second dopant at an end of said gate to form a source in said body region, wherein said first and second dopants
have opposite types;

f) forming a contact hole adjacent to said gate, and injecting a third dopant into said contact hole, wherein said first and
third dopants have a same type;

g) depositing and etching aluminum on a chip surface; and
h) coating said aluminum and said chip surface with a passivation layer.

US Pat. No. 9,325,254

SCR DIMMING CIRCUIT AND DIMMING CONTROL METHOD

SILERGY SEMICONDUCTOR TEC...

1. A SCR dimming circuit comprising a SCR element, a rectifier circuit, a filter circuit, a power converter, and a dimming
control circuit, wherein said SCR element, said rectifier circuit and said filter circuit are configured to obtain a bus voltage
from an AC power supply for said power converter, said dimming control circuit comprising:
a phase angle detection circuit for receiving a bus voltage sampling signal indicative of said bus voltage, comparing said
bus voltage sampling signal with a threshold voltage, an outputting a phase angle signal;

an output current feedback control circuit for receiving said phase angle signal and an output current feedback signal indicative
of an output current of said power converter, and generating a first control signal in accordance with said phase angle signal
and said output current feedback signal;

an input current control circuit for receiving an input current sampling signal indicative of an input current of said power
converter, comparing said input current sampling signal with a predetermined value, and outputting a second control signal,
wherein said predetermined value is less than a holding current of said SCR element;

a maximum operation time detection circuit for receiving said phase angle signal, measuring a first time period during which
said phase angle signal is valid, and generating a third control signal which is valid when said first time period reaches
a predetermined time and is valid when said phase angle signal becomes invalid; and

a logic operator for receiving said first control signal, said second control signal and said third control signal, and outputting
a driving signal.

US Pat. No. 9,089,026

DIMMING CIRCUIT AND METHOD FOR LEDS

Silergy Semiconductor Tec...

1. A dimming circuit for LEDs which obtains a DC voltage from an external AC power supply by using a TRIAC, an electronic
transformer, and a rectifier bridge sequentially, comprising:
a first power stage circuit having an input terminal configured to receive said DC voltage;
a second power stage having an input terminal coupled to an output terminal of said first power stage and an output terminal
coupled to an LED load;

a first control circuit configured to generate a first control signal in accordance with a first output voltage generated
at the output terminal of said first power stage circuit, a first reference voltage and an upper threshold voltage to maintain
an average value of said first output voltage to be consistent with said first reference voltage, wherein an input current
of said first power stage circuit is maintained to be consistent with a first current by said first control signal when said
first output voltage is in a continuously increasing state and is lower than said upper threshold voltage, and said first
output voltage is decreased continuously and said input current is maintained to be consistent with a second current after
said first output voltage reaches said upper threshold voltage by said first control signal, and wherein said first current
is no less than a holding current of said electronic transformer; and

a second control circuit configured to generate a dimming signal in accordance with said first current and said first output
voltage to control an operation of said second power stage circuit to maintain an output current of said second power stage
circuit to be consistent with an expected driving current represented by said dimming signal.

US Pat. No. 9,052,728

START-UP CIRCUIT AND METHOD THEREOF

Silergy Semiconductor Tec...

1. A start-up circuit, comprising:
a) a delay circuit comprising a first resistor and a first capacitor, wherein said first capacitor is coupled between ground
and a common node, and a multiplexed pin is connected to said common node;

b) a control chip configured to receive an enable signal at said multiplexed pin, a first reference voltage, and an input
voltage source, and to supply power at an output pin;

c) wherein said start-up circuit is configured to output an electrical signal at said output pin in response to said enable
signal being activated, said electrical signal being output at said output pin based on a comparison of a voltage at said
multiplexed pin against said first reference voltage, and after a delay time that is determined by a value of said capacitor
and said first reference voltage; and

d) wherein a voltage at said output pin is configured to increase continuously with a fixed rising slope that is determined
by input current flowing through said multiplexed pin during a start-up process for said start-up circuit.

US Pat. No. 9,603,211

LED DRIVER

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a rectifier circuit having an input for receiving an AC voltage, and an output for providing a DC output voltage by rectifying
said AC voltage;

b) an LED array comprising N LED units having at least one LED coupled between a first output terminal and a second output
terminal of said DC output voltage;

c) (N?1) groups of switches, each group of switches comprising two switches coupled in series between said first and second
output terminals of said DC output voltage, wherein a common node of said two switches of each group is coupled to a common
node between two adjacent LED units, and wherein the operation of said two switches of each group is complementary such that
when said switch is on, said LED unit coupled in parallel with said switch is out of operation; and

d) an LED configuration control circuit configured to control the on and off states of switches to correspondingly control
operation of said LED units in accordance with a value of said DC output voltage and a current requirement for a current flowing
through said LED units.

US Pat. No. 9,343,965

SWITCHING REGULATOR AND CONTROL CIRCUIT AND CONTROL METHOD THEREFOR

Silergy Semiconductor Tec...

1. A control circuit for controlling a switching regulator, comprising:
a supplementary signal generator configured to generate a supplementary signal;
a superimposing circuit configured to superimpose said supplementary signal with a first signal to generate a superposition;
a state detection circuit configured to generate a state signal in accordance with a second signal and said superposition;
a clock generator configured to generate a clock signal; and
a switching control signal generator configured to generate a switching control signal in accordance with said state signal
and said clock signal;

wherein said supplementary signal generator is configured to generate said supplementary signal varying with a state parameter
of a power stage in a first mode and to impede said supplementary signal from deviating from a value thereof at the moment
of switching from said first mode to said second mode.

US Pat. No. 9,131,562

HIGH EFFICIENCY LED DRIVER AND DRIVING METHOD THEREOF

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a power switch configured to receive a DC bus voltage, and to generate a driving voltage and a driving current for an LED
device;

b) a first comparator configured to generate a first controlling signal by comparison of said DC bus voltage against a sum
of said driving voltage and a first reference voltage;

c) a controlling and driving circuit configured to receive said first controlling signal and an LED current sampling signal,
wherein said controlling and driving circuit is configured to operate in a first operation mode or a second operation mode
according to said first controlling signal;

d) wherein when said DC bus voltage is greater than said sum of said driving voltage and said first reference voltage, said
controlling and driving circuit is configured to operate in said first operation mode, and said power switch is configured
to generate a first output current according to said LED current sampling signal;

e) wherein when said DC bus voltage is greater than said driving voltage and less than said sum of said driving voltage and
said first reference voltage, said controlling and driving circuit is configured to operate in said second operation mode,
and said power switch is configured to generate a second output current; and

f) an output capacitor coupled in parallel with said LED device, and having a first terminal coupled to said DC bus voltage,
and a second terminal coupled to said power switch.

US Pat. No. 9,699,844

MULTICHANNEL CONSTANT CURRENT LED DRIVING CIRCUIT, DRIVING METHOD AND LED DRIVING POWER

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driving circuit configured to drive an LED load having a plurality of LED strings coupled
in series, the LED driving circuit comprising:
a) a power stage circuit configured to receive a DC bus voltage, and to generate an output signal to drive said plurality
of LED strings;

b) a current control unit configured to control an average current of each of said plurality of LED strings in accordance
with a corresponding one of a plurality of dimming signals; and

c) said current control unit being configured to control operation of said power stage circuit to control said output signal
in accordance with a current feedback signal that represents a current flowing through said plurality of LED strings.

US Pat. No. 9,131,582

HIGH EFFICIENCY LED DRIVING CIRCUIT AND DRIVING METHOD

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driving circuit, comprising:
a) a protection control circuit configured to activate a first protection control signal in response to a comparison of a
sense voltage signal against a first reference voltage to indicate an LED device is in a first load state, wherein said sense
voltage signal represents an output voltage of said LED driving circuit;

b) said protection control circuit being configured to activate a second protection control signal in response to a comparison
of said sense voltage signal against a second reference voltage to indicate said LED device is in a second load state;

c) a power stage circuit comprising an inductor coupled to a power switch through a resistor, wherein said sense voltage signal
is determined by a voltage across said inductor; and

d) a pulse-width modulation (PWM) control circuit configured to control said power switch according to said first and second
protection control signals.

US Pat. No. 9,438,108

BIAS VOLTAGE GENERATING CIRCUIT AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A bias voltage generating circuit, comprising:
a) a first control circuit configured to compare a drain-source voltage of a first switch against a bias voltage across a
capacitor;

b) a second control circuit configured to control said first switch, wherein said second control circuit is configured to
be enabled when said bias voltage is at least as high as an expected bias voltage;

c) wherein said first control circuit is configured to control said capacitor to charge when said drain-source voltage of
said first switch is greater than said bias voltage, wherein said first control circuit comprises a first comparator configured
to receive said bias voltage and an overvoltage protection voltage, and to output a first control signal, a second switch
coupled to said first switch and being controllable by said first control signal, and a diode having an anode coupled to said
second switch, and a cathode coupled to said capacitor; and

d) wherein said bias voltage is less than said overvoltage protection voltage when said capacitor charges, and wherein said
overvoltage protection voltage comprises a voltage that is a predetermined amount higher than said expected bias voltage.

US Pat. No. 9,420,408

TIRE STATUS MONITORING-TRANSMISSION SYSTEM AND TRANSMISSION DEVICE THEREOF

Silergy Semiconductor Tec...

1. A tire status monitoring-transmission system comprising
a Bluetooth wireless transceiving host computer having a display interface and sending out a response signal if having detected
an upward Bluetooth broadcasting signal;

a plurality of transmission modules wirelessly linking to said Bluetooth wireless transceiving host computer and each including
a Bluetooth wireless transceiving unit persistently emitting said upward Bluetooth broadcasting signal and receiving said
response signal after said Bluetooth wireless transceiving host computer receives said upward Bluetooth broadcasting signal
and generates said response signal; and

a control unit electrically connected with said Bluetooth wireless transceiving unit and generating a trigger signal according
to said response signal; and

a sensor module electrically connected with said control unit, triggered by said trigger signal to detect a tire status, and
generating detection signals to said control unit, wherein said control unit further transmits said detection signals to said
Bluetooth wireless transceiving host computer through said Bluetooth wireless transceiving unit, and wherein said Bluetooth
wireless transceiving host computer presents said tire status and on said display interface.

US Pat. No. 9,312,785

SYNCHRONOUS RECTIFICATION CONTROLLING CIRCUIT AND SYNCHRONOUS RECTIFICATION CONTROLLING METHOD

Silergy Semiconductor Tec...

1. A synchronous rectification circuit, comprising:
a) a sampling circuit configured to sample a voltage across first and second power terminals of a synchronous rectifier, and
to generate a first sampling voltage;

b) an enable controlling circuit configured to delay said first sampling voltage, and to generate a second sampling voltage,
and to activate a ramp voltage when said first sampling voltage is higher than said second sampling voltage;

c) said enable controlling circuit being configured to generate an enable controlling signal in response to a comparison of
said ramp voltage against a reference voltage that represents a predetermined light load condition; and

d) a driving circuit configured to activate a driving signal to turn on said synchronous rectifier when said enable controlling
signal and a synchronous rectification open signal are active.

US Pat. No. 9,246,328

INTEGRATED EMI FILTER CIRCUIT WITH ESD PROTECTION AND INCORPORATING CAPACITORS

Silergy Semiconductor Tec...

1. An integrated electromagnetic interference (EMI) filter circuit with electrostatic discharge (ESD) protection and incorporating
capacitors, comprising:
a) a first passive element connected between an input terminal and an output terminal;
b) first and second capacitors, wherein said first capacitor is connected between ground and said input terminal, and said
second capacitor is connected between ground and said output terminal;

c) first and second diodes, wherein an anode of said first diode is connected to ground, and a cathode of said first diode
is connected to said input terminal, wherein an anode of said second diode is connected to ground, and a cathode of said second
diode is connected to said output terminal, wherein said first diode comprises a first parasitic capacitance separate from
said first capacitor, and said second diode comprises a second parasitic capacitance separate from said second capacitor;
and

d) a first parallel capacitor connected in parallel to said first passive element, and between said input terminal and said
output terminal for frequency compensation.

US Pat. No. 9,246,394

SYNCHRONOUS RECTIFICATION CONTROL CIRCUIT AND POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A synchronous rectification control circuit in a flyback converter, comprising:
a) a first control circuit configured to receive a drain-source voltage signal of a synchronous rectifier switch and an output
voltage of said flyback converter, and to generate a first control signal based on a conduction time of a primary-side power
switch of said flyback converter, wherein said first control signal, said conduction time of said primary-side power switch,
and a primary-side input voltage of said flyback converter, are directly proportional to each other;

b) a second control circuit configured to receive said drain-source voltage signal, and to generate a second control signal
therefrom;

c) an enable signal generating circuit configured to generate an enable signal based on said first control signal and a threshold
value, wherein said enable signal generating circuit directly receives said first control signal;

d) wherein when said primary-side power switch is turned off, and said first control signal is greater than said threshold
value, said second control signal is enabled by said enable signal to control a switching operation of said synchronous rectifier
switch before said primary-side power switch is turned on again; and

e) wherein when said primary-side power switch is turned off, and said first control signal is less than said threshold value,
said synchronous rectifier switch is configured to stop operation before said primary-side power switch is turned on again.

US Pat. No. 9,129,947

MULTI-CHIP PACKAGING STRUCTURE AND METHOD

Silergy Semiconductor Tec...

1. A multi-chip packaging structure, comprising:
a) N chips, wherein N is an integer of at least two, and wherein an upper surface of each chip comprises a plurality of pads;
b) a lead frame with a chip carrier and a plurality of pins, wherein said N chips are stacked in layers on said chip carrier,
and wherein a first chip of said N chips situated in an upper layer comprises a control and driving circuit and partially
covers a second chip of said N chips situated in a lower layer such that said plurality of pads of said second chip are exposed,
and wherein said second chip comprises a power transistor;

c) a plurality of first bonding leads configured to connect pads on said first chip to pads on said second chip, wherein a
first of said plurality of pins is configured to withstand a high voltage, and wherein a second of said plurality of pins
comprises a no connect pin; and

d) a plurality of second bonding leads configured to connect pads on said first and second chips to said plurality of pins
for external connection to said multi-chip packaging structure, wherein said first pin is directly connected to said chip
carrier without connecting through any of said plurality of second bonding leads, and wherein said first and second pins are
adjacent to each other.

US Pat. No. 9,130,468

CONSTANT VOLTAGE CONSTANT CURRENT CONTROLLER AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A constant voltage constant current (CVCC) controller configured for a flyback converter, said CVCC controller comprising:
a) a current controller configured to generate an error signal by calculating a difference between an output current feedback
signal from a current feedback circuit and a reference current;

b) a voltage controller configured to receive an output voltage feedback signal from a voltage feedback circuit and a reference
voltage, and to generate a control signal;

c) a selector comprising a first switch configured to receive said error signal and being controllable by said control signal,
said selector being configured to control said flyback converter to operate in a first operation mode or a second operation
mode based on said control signal, wherein said selector comprises a second switch coupled to said first switch and being
controllable by an inverted version of said control signal, wherein said selector is configured to generate a constant voltage
control signal based on said error signal when said flyback converter is operating in said first operation mode, and to generate
a constant current control signal based on said error signal when said flyback converter is operating in said second operation
mode, wherein said selector comprises a discharging circuit coupled between said second switch and ground, and a first capacitor
coupled to said first and second switches and ground, wherein a cross voltage on said first capacitor is configured as said
constant voltage control signal or said constant current control signal;

d) a pulse-width modulation (PWM) controller configured to generate a PWM control signal to control a main switch of said
flyback converter, wherein said PWM controller is configured to generate a constant voltage signal based on said constant
voltage control signal to maintain an output voltage of said flyback converter as substantially constant when said flyback
converter operates in said first operation mode, and wherein said PWM controller is configured to generate a constant current
signal based on said constant current control signal to maintain an output current of said flyback converter as substantially
constant when said flyback converter operates in said second operation mode; and

e) a timer configured to measure a discharging time of a secondary winding of said flyback converter, and to generate a timing
signal therefrom.

US Pat. No. 9,385,616

AC/DC POWER CONVERTER

Silergy Semiconductor Tec...

1. An AC/DC power converter, comprising:
a) a rectifier bridge and a filter capacitor configured to convert an external AC voltage to a half-sinusoid DC input voltage;
b) a first power stage having a first converter topology and being configured to receive said half-sinusoid DC input voltage,
said first power stage comprising a first magnetic component, a capacitive component, a controlling and driving circuit, and
a power transistor, wherein said first power stage is configured to provide power factor correction (PFC) of a first current
flowing through said first magnetic component relative to said half-sinusoid DC input voltage;

c) a second power stage having a second converter topology and comprising a second magnetic component, said capacitive component,
and said power transistor, wherein said capacitive component is common to said first and second power stages, and wherein
said second power stage is configured to provide constant current regulation of an output current of said AC/DC power converter;
and

d) a sampling resistor coupled between said power transistor and ground, wherein a voltage across said sampling resistor is
configured to represent a peak current of said second magnetic component.

US Pat. No. 9,331,581

AC-DC VOLTAGE CONVERTER WITH LOW STANDBY POWER CONSUMPTION AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. An AC-DC voltage converter, comprising:
a) a safety capacitor configured to receive an input power supply;
b) a common mode filter inductor configured to process said input power supply with a rectifier bridge and a filter;
c) a switching power supply circuit configured to receive energy from said input power supply as an output from said filter,
wherein said switching power supply circuit comprises a power stage circuit, a control circuit configured to control said
power stage circuit to realize voltage conversion of said input power supply, and a phantom load;

d) wherein said control circuit is configured to disable said phantom load from a supply voltage of said control circuit by
opening a first switch connected to said phantom load when said control circuit detects that said input power supply is operating
in a normal operating state; and

e) wherein when said control circuit detects that said input power supply is operating in an under voltage lock out state,
said control circuit is configured to enable said phantom load, energy stored in said safety capacitor is configured to be
supplied to a load of said switching power supply circuit and said phantom load, and said power stage circuit is configured
to be disabled until a voltage of said safety capacitor is reduced to less than a predetermined threshold value.

US Pat. No. 9,317,019

SINUSOIDAL MODULATION CONTROL METHODS AND CIRCUITS FOR PERMANENT MAGNET SYNCHRONOUS MOTORS

Silergy Semiconductor Tec...

1. A sinusoidal modulation control method for a permanent magnet synchronous motor, the method comprising:
a) detecting rotor position information of said permanent magnet synchronous motor to obtain a plurality of rotor position
signals and a rotor rotating speed measured value, wherein said plurality of rotor position signals comprises three-phase
Hall signals that correspond to three Hall effect sensors;

b) comparing said rotating speed measured value against a reference rotating speed value to generate an error signal, and
generating a first regulating voltage signal based on said error signal using a proportional-integral (PI) regulator;

c) receiving said plurality of rotor position signals and said first regulating voltage signal, and generating a full-wave
U-shaped modulation wave by using said plurality of rotor position signals as a plurality of time references;

d) generating a second U-shaped modulation wave by multiplying said full-wave U— shaped modulation wave with said first regulating
voltage signal;

e) comparing said second U-shaped modulation wave against a triangular wave to generate a pulse-width modulation (PWM) control
signal;

f) controlling a switch of an inverter with said PWM control signal to regulate a current of said permanent magnet synchronous
motor; and

g) regulating a rotor position angle by an external enable signal by using said external enable signal to shift said full-wave
U-shaped modulation wave left or right of one of said plurality of rotor position signals to change said rotor position angle
between a stator magneto-motive force and a rotor magneto-motive force to maximize torque generated at every ampere stator
current.

US Pat. No. 9,131,553

LED DRIVER

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a soft-start control circuit, wherein when a first threshold value is less than a soft-start reference value, said LED
driver is configured to operate in a soft-start process, wherein said soft-start reference value represents a desired output
current of said LED driver, and wherein an inductor current of said LED driver is no greater than a second threshold value;

b) wherein during a first time interval of said soft-start process, an LED driving current is configured to be maintained
at a first current value, and an LED driving voltage rises in a slope-shape, wherein said first threshold value is maintained
at a corresponding initial soft-start value of said first current value, and said second threshold value rises in a slope-shape;

c) wherein during a second time interval of said soft-start process, said LED driving current is configured to rise in a slope-shape,
and said LED driving voltage is configured to be maintained at an end state of said first time interval, wherein said first
threshold value continues to rise in a slope-shape, and reaches a first final value at an end of said second time interval,
and wherein said second threshold value is maintained at a second final value; and

d) when said first threshold value is greater than said soft-start reference value, said LED driver is configured to operate
in a normal operating state, and said LED driving current is substantially consistent with said desired output current.

US Pat. No. 9,444,441

ZERO-CROSSING DETECTION CIRCUIT AND METHOD FOR SYNCHRONOUS STEP-DOWN CONVERTER

Silergy Semiconductor Tec...

1. A zero-crossing detection circuit for a synchronous step-down converter, the zero-crossing detection circuit comprising:
a) a state determination circuit configured to compare a drain voltage of a synchronous transistor of said synchronous step-down
converter against a reference voltage, and to generate a state digital signal indicative of whether a body diode of said synchronous
transistor is turned on;

b) a logic circuit configured to convert said state digital signal into a counting instruction signal;
c) a plus-minus counter configured to generate a numerical signal in response to said counting instruction signal;
d) a digital-analog converter configured to generate a correction analog signal based on said numerical signal;
e) a zero-crossing comparator configured to receive said correction analog signal and said drain voltage of said synchronous
transistor, and to provide a zero-crossing comparison signal to a driving circuit of said synchronous step-down converter;
and

f) a timing logic circuit configured to receive a first timing signal from said driving circuit, and to generate a second
timing signal indicative of an operation time of a comparator, and a third timing signal indicative of an operation time of
said logic circuit, wherein said second and third timing signals are respectively provided to said comparator and said logic
circuit, and said first timing signal is provided to said plus-minus counter.

US Pat. No. 9,369,049

INTEGRATED SWITCH MODE POWER SUPPLY CONTROLLER AND SWITCH MODE POWER SUPPLY USING THE SAME

Silergy Semiconductor Tec...

1. An integrated switch mode power supply controller, comprising:
a) a multiplexing pin configured to receive a detection voltage signal, and a current sample pin configured to receive a current
sample signal;

b) a switch mode power supply configured to receive a DC input voltage, and to operate in a switching cycle having first,
second, and third time intervals, wherein said switch mode power supply comprises a transformer having primary and secondary
windings;

c) wherein during said first time interval, said detection voltage signal is proportional to said DC input voltage, a current
compensation signal is configured to be generated according to said detection voltage signal, and said current compensation
signal is configured to be superimposed with said current sample signal to obtain a peak current flowing through said primary
winding;

d) wherein during said second time interval, said detection voltage signal is proportional to an output voltage of said switch
mode power supply, and a discharging duration of current through said secondary winding is determined based on said detection
voltage signal; and

e) wherein during said third time interval, said detection voltage signal is proportional to a voltage across a power transistor
of said switch mode power supply, said power transistor being turned on at a local minimum according to said detection voltage
signal.

US Pat. No. 9,331,661

IC EMI FILTER WITH ESD PROTECTION INCORPORATING LC RESONANCE TANKS FOR REJECTION ENHANCEMENT

Silergy Semiconductor Tec...

1. An integrated circuit (IC) electromagnetic interference (EMI) filter with electrostatic discharge (ESD) protection incorporating
inductor-capacitor (LC) resonance tanks, said IC EMI filter comprising:
a first diode with a first anode thereof coupled to a ground, wherein said first diode comprises a first parasitic capacitance
between a first cathode of said first diode and said first anode;

a first inductor having a first series resistance, and being coupled to said first cathode;
a second diode with a second anode thereof coupled to said ground, wherein said second diode comprises a second parasitic
capacitance between a second cathode of said second diode and said second anode;

a second inductor having a second series resistance, and being coupled to said second cathode; and
a first passive element coupled between said first and second inductors, wherein a first node between said first passive element
and said first inductor is coupled to a first port, and a second node between said first passive element and said second inductor
is coupled to a second port.

US Pat. No. 9,287,773

SWITCH POWER SUPPLY CONTROLLER AND CONTROL METHOD

Silergy Semiconductor Tec...

1. A switch power supply controller, comprising:
a) a switch configured to operate in a first state and a second state during each switch cycle to convert an input signal
to an output signal as part of a switch mode power supply;

b) a switch time regulating circuit configured to compare a duration of said first state of said switch in a present switch
cycle against an expected first state duration;

c) said switch time regulating circuit being configured to decrease a duration of said second state of said switch in said
present switch cycle when said first state duration is greater than said expected first state duration, wherein a first state
duration for a next switch cycle is decreased due to said second state duration of said present switch cycle being decreased;

d) said switch time regulating circuit being configured to increase said second state duration in said present switch cycle
when said first state duration is less than said expected first state duration, wherein a first state duration for said next
switch cycle is increased due to said second state duration of said present switch cycle being increased;

e) said switch time regulating circuit comprising a reference voltage generating circuit configured to output a reference
voltage signal based on said first state duration and said expected first state duration, and a timing circuit configured
to control said second state duration to substantially match said reference voltage signal; and

f) said timing circuit comprising a ramp signal generating circuit configured to output a ramp signal at a start time of said
second state of said switch, and a comparison circuit configured to compare said ramp signal against said reference voltage
signal, and to output a signal to end said second state of said switch when said ramp signal rises to a level of said reference
voltage signal.

US Pat. No. 9,246,384

CURRENT FEEDBACK METHOD, CURRENT FEEDBACK CIRCUIT, DRIVING CIRCUIT AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A current feedback circuit, comprising:
a) a first current mirror circuit having an input terminal coupled to a source of a main power transistor of a switching power
supply, and a control terminal configured to receive a pulse-width modulation (PWM) control signal, said first current mirror
circuit being configured to generate a first mirror current;

b) said first current mirror circuit and said main power transistor being on such that an output sampling current flows through
said first current mirror circuit and said main power transistor when said PWM control signal is active;

c) a second current mirror circuit configured to generate an output feedback current that is in a predetermined direct proportion
with said output sampling current, and is generated in accordance with said first mirror current;

d) a current follower with input terminals coupled to a charging and discharging circuit and said first current mirror circuit,
and an output terminal coupled to a current detection pin, wherein said current follower comprises an operational amplifier
having input terminals coupled to input and output terminals of said first current mirror circuit, and a first transistor
having a gate coupled to an output terminal of said operation amplifier, a source coupled to an inverting input terminal of
said operational amplifier, and a drain coupled to said current detection pin; and

e) a first switch circuit coupled between said charging and discharging circuit and an input terminal of said operational
amplifier, wherein said first switch circuit is off when said PWM control signal is inactive.

US Pat. No. 9,136,207

CHIP PACKAGING STRUCTURE OF A PLURALITY OF ASSEMBLIES

Silergy Semiconductor Tec...

1. A chip packaging structure, comprising:
a) a first assembly;
b) at least one second assembly located above said first assembly, wherein said at least one second assembly is electrically
connected to said first assembly by a plurality of first protruding structures located under periphery and internal regions
of said at least one second assembly, wherein said at least one second assembly comprises at least one power transistor;

c) at least one third assembly located above said at least one second assembly, wherein said at least one third assembly is
electrically connected to said first assembly by a plurality of second protruding structures located outside of said at least
one second assembly, and wherein said at least one third assembly comprises an inductor having bent portions;

d) wherein a first portion of said inductor and a corresponding of said plurality of second protruding structures form a bent
structure substantially perpendicular to a second portion of said inductor, wherein said plurality of second protruding structures
are connected between said first portion of said inductor and a top surface of said first assembly, and wherein said inductor
is coupled to said at least one transistor in a configuration of a switching voltage regulator; and

e) wherein an enclosure of said at least one second assembly and any remaining of said at least one third assembly into a
single packaging structure comprises said inductor with said bent portions.

US Pat. No. 9,078,381

METHOD OF CONNECTING TO A MONOLITHIC VOLTAGE REGULATOR

Silergy Technology, Sunn...

1. A method of connecting to a monolithic voltage regulator, the method comprising:
a) using a plurality of bumps on said monolithic voltage regulator to form connections to source and drain terminals of a
transistor of said monolithic voltage regulator;

b) using a first surface of a single layer lead frame to connect to said monolithic voltage regulator via said plurality of
bumps, said first surface having a first pattern, said single layer lead frame comprising said first surface and a second
surface, said single layer lead frame having a plurality of interleaving lead fingers for connecting to said plurality of
bumps, wherein each said interleaving lead finger comprises a first portion with a first thickness and a second portion with
a second thickness, wherein said first thickness is greater than said second thickness, and wherein at least one of said interleaving
lead fingers comprises two first portions separated by one second portion;

c) using a flip-chip package to encapsulate said monolithic voltage regulator, said plurality of bumps, and said single layer
lead frame; and

d) using said second surface of said single layer lead frame to provide external connectors to said monolithic voltage regulator
at said flip-chip package, wherein said second surface comprises a second pattern that is different from said first pattern.

US Pat. No. 9,717,133

WIRELESS LED DRIVER

Silergy Semiconductor Tec...

1. A wireless light-emitting diode (LED) driver, comprising:
a) an electrical energy transmitter comprising an inverter circuit coupled to receive an input power supply, and being configured
to convert a received voltage signal to an AC signal;

b) said electrical energy transmitter comprising N transmitter coupling circuits coupled to said inverter circuit, and being
configured to be driven by said AC signal;

c) an electrical energy receiver comprising M receiver coupling circuits coupled to said transmitter coupling circuits in
a contactless mode, and being configured to receive said AC signal; and

d) said electrical energy receiver comprising M rectifier circuits coupled to said receiver coupling circuits one by one,
wherein each said rectifier circuit is configured to convert said AC signal to a DC signal to drive an LED load coupled to
output terminals of said rectifier circuit, and wherein N and M are integers not less than 1.

US Pat. No. 9,438,118

EFFICIENT BOOST-BUCK CONVERTER AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A method of controlling a boost-buck converter, the method comprising:
a) receiving, by a control circuit, an input voltage from an input terminal of said boost-buck converter;
b) receiving, by said control circuit, an output voltage from an output terminal of said boost-buck converter;
c) controlling, by said control circuit, switching operations of first, second, third, and fourth switches of said boost-buck
converter according to said input and output voltages such that said boost-buck converter operates in at least one of: a buck
mode and a boost mode; and

d) wherein said boost-buck converter comprises said first switch directly connected to said input terminal and to a first
node, said second switch directly connected to said first node and to a ground terminal, a first inductor directly connected
to said input terminal and to a second node, said third switch directly connected to said second node and to said ground terminal,
said fourth switch directly connected to said second node and to said output terminal, and a second inductor directly connected
to said first node and to said output terminal.

US Pat. No. 9,413,248

CONTROL METHOD AND AC-DC POWER CONVERTER

Silergy Semiconductor Tec...

4. An AC-DC power converter, comprising:
a) a filter capacitor configured to receive a first branch current from an input current of said AC-DC power converter;
b) a power converting circuit configured to receive a second branch current from said input current;
c) a compensating circuit configured to generate a first compensation signal by compensation of an error between a feedback
signal that represents an output signal of said power converting circuit and a first reference voltage that represents a desired
output value of said output signal;

d) a superposition circuit configured to generate a second compensation signal by adding said first compensation signal with
a triangular wave signal from a triangular wave signal generating circuit;

e) a driving control circuit configured to generate a control signal to control a power switching device of said power converting
circuit based on said second compensation signal; and

f) said power converting circuit being configured to produce a first converting current by a first conduction time that is
generated based on said feedback signal, and a second converting current having a same absolute value as said first branch
current by a second conduction time based on said triangular wave signal, wherein said second branch current comprises a sum
of said first and second converting currents, and a power converting circuit conduction time comprises a sum of said first
and second conduction times.

US Pat. No. 9,246,381

ACTIVE POWER FACTOR CORRECTION CONTROL CIRCUIT, CHIP AND LED DRIVING CIRCUIT THEREOF

Silergy Semiconductor Tec...

1. An active power factor correction (APFC) control circuit, configured to generate a pulse-width modulation (PWM) control
signal to control the operation of a power converter, the APFC control circuit comprising:
a) an inductor current zero crossing detection circuit coupled to a common node between a power switch of said power converter
and a first switch that are coupled in series, wherein said inductor current zero crossing detection circuit is configured
to generate a comparison signal based on a voltage signal at said common node;

b) said comparison signal being activated when an inductor current of said power converter decreases to zero; and
c) said APFC control circuit being configured as a source driver, wherein a control terminal of said power switch is coupled
to a constant voltage supply.

US Pat. No. 9,054,597

BOOST PFC CONTROLLER

Silergy Semiconductor Tec...

1. A boost power factor correction (PFC) controller configured for an AC/DC converter, the boost PFC controller comprising:
a) an off signal generator configured to compare an inductor current sample signal against a first control signal, wherein
said inductor current sample signal increases during an on time of a power switch of said AC/DC converter, and wherein said
off signal generator is configured to generate an off signal when said inductor current sample signal reaches a level of said
first control signal;

b) an on signal generator configured to compare a peak value of a second control signal having a first coefficient of proportionality
to an off time of said power switch against a third control signal having a second coefficient of proportionality to an off
duty cycle of said power switch, wherein said second control signal increases during said off time of said power switch, and
wherein said on signal generator is configured to generate an on signal when said second control signal reaches a level of
said third control signal; and

c) a logic circuit coupled to said on signal generator and said off signal generator, wherein said logic circuit is configured
to turn on said power switch when said on signal is active, and to turn off said power switch when said off signal is active,
wherein each of said second and third control signals is generated using an output of said logic circuit that is used to control
said power switch.

US Pat. No. 9,560,709

LED DRIVER AND LED LIGHTING DEVICE

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a rectifying bridge configured to receive an AC current from an electrical ballast, and to generate a DC current;
b) a rectifying and filtering circuit coupled to said rectifying bridge, and configured to rectify and filter said DC current,
and to drive an LED load;

c) a power switch coupled between an input of said rectifying and filtering circuit and ground, and configured to be controlled
by a switching control signal such that said rectifying and filtering circuit is shorted when said power switch is turned
on by said switching control signal;

d) a first detecting circuit configured to sample a current that flows through said LED load, and to generate a first detection
signal;

e) a second detecting circuit configured to sample an output current of said rectifying bridge, and to generate a second detection
signal; and

f) a control circuit configured to generate said switching control signal according to said first and second detection signals.

US Pat. No. 9,287,782

HIGH EFFICIENCY BI-DIRECTIONAL DC CONVERTER AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A method of controlling a bi-directional DC converter, the method comprising:
a) detecting whether there is an input power supply at an input port, wherein said bi-directional DC converter comprises a
single magnetic element;

b) operating said bi-directional DC converter in a first operation mode to charge a battery when said input power supply is
detected at said input port;

c) operating said bi-directional DC converter in a second operation mode to transfer power from said battery to an output
port for a load when said input power supply is not detected at said input port;

d) transferring power through said single magnetic element in both said first operation mode and said second operation mode;
e) comparing, by a first feedback circuit, a current feedback signal of said battery against a first reference voltage to
generate a first error signal, comparing a voltage feedback signal of said battery against a second reference voltage to generate
a second error signal, and generating a first feedback signal by selecting a lesser of said first and second error signals;

f) comparing, by a second feedback circuit, an output voltage at said output port against a third reference voltage, and generating
a second feedback signal; and

g) providing, by a first selection circuit, one of said first and second feedback signals to a pulse-width modulation (PWM)
control circuit that controls a charging current of said battery according to said first feedback signal, or said output voltage
according to said second feedback signal.

US Pat. No. 9,648,677

LED DRIVING CIRCUIT AND METHOD USING SINGLE INDUCTOR

Silergy Semiconductor Tec...

1. An LED driving circuit using a single inductor, comprising:
a power stage circuit configured to receive a DC bus voltage and output a constant signal for driving an LED load;
a constant current controller configured to receive a feedback signal representing an LED load current, and control operations
of a power transistor and a rectifying transistor in said power stage circuit in accordance with said feedback signal to maintain
an output signal of said power stage circuit to be constant; and

a constant voltage generating circuit configured to be connected in series with said LED load between an output terminal of
said power stage circuit and ground, receive a current signal at said output terminal of said power stage circuit, and generate
a constant voltage signal by charging a capacitor through a first switch in said constant voltage generating circuit with
said current signal, wherein said constant voltage signal is configured as a reserve supply voltage of said LED driving circuit.

US Pat. No. 9,413,222

UNDERVOLTAGE PROTECTION CIRCUIT, UNDERVOLTAGE PROTECTION METHOD AND SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. An undervoltage protection circuit configured for a switching power supply, said undervoltage protection circuit comprising:
a) an undervoltage detection circuit configured to use a first voltage that represents an input voltage of said switching
power supply to determine whether said input voltage is in an undervoltage state, and to output a detection result;

b) a selection circuit configured to select a first or a second control signal to be provided as a main control signal to
a control circuit based on said detection result, wherein said first control signal comprises an output voltage error feedback
signal of said switching power supply, and said second control signal represents a minimum value of said first control signal;

c) said control circuit being configured, in response to said main control signal being said first control signal, to control
a switching operation of a power transistor in said switching power supply such that an output voltage of said switching power
supply is maintained as substantially stable; and

d) said control circuit being configured, in response to said main control signal being said second control signal, to control
said switching operation of said power transistor to reduce an input power of said switching power supply.

US Pat. No. 9,318,911

SELF-ADAPTIVE INPUT POWER CHARGER AND METHOD FOR CONTROLLING INPUT CURRENT OF CHARGER

(A) Silergy Semiconductor...

1. A self-adaptive input power charger, comprising:
a) a power stage circuit configured to receive an input voltage and an input current from an external input power supply for
charging a battery;

b) a comparison circuit comprising a first error amplifier configured to receive said input voltage and a first reference
voltage, and to generate a comparison result indicating that said input power supply has entered a current-limiting state
when said input voltage is less than said first reference voltage;

c) a current regulation circuit configured to generate a first control signal in response to said comparison result, wherein
said current regulation circuit comprises a first diode having a cathode coupled to said comparison result, and an anode coupled
to said first control signal; and

d) a driving control circuit coupled to said anode of said first diode, and being configured to control a duty cycle of a
power switch in said power stage circuit based on said first control signal to limit said input current of said charger.

US Pat. No. 9,287,793

ISOLATED POWER SUPPLY, CONTROL SIGNAL TRANSMISSION CIRCUIT AND METHOD THEREOF

Silergy Semiconductor Tec...

1. A control signal transmission circuit configured in an isolated power supply, the control signal transmission circuit comprising:
a) a first signal converter coupled to a first ground potential having a ground noise signal, and to a second ground potential
of said isolated power supply, wherein said first signal converter is configured to generate a first ground noise component
with a first predetermined proportionality to said ground noise signal;

b) a second signal converter coupled to a first control signal having said ground noise signal, and to said second ground
potential, wherein said second signal converter is configured to generate a first peak signal based on said first control
signal and having a second ground noise component with a second predetermined proportionality to said ground noise signal;
and

c) a control signal generator configured to generate a second control signal based on a difference between said first peak
signal and said first ground noise component, wherein said second control signal is configured to control a switch of said
isolated power supply.

US Pat. No. 9,413,252

TRANSMISSION VOLTAGE LOSS COMPENSATION CIRCUIT, COMPENSATION METHOD, CONTROLLING CHIP AND SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method of compensating for transmission voltage loss from a switching power supply, the method comprising:
a) receiving, in a current feedback circuit, a feedback signal from a feedback terminal that is coupled to an auxiliary winding
of said switching power supply, and a signal from a common node of a sampling resistor and a main switch of said switching
power supply;

b) generating, by said current feedback circuit, a sampling signal that represents an output current of said switching power
supply, wherein said sampling signal is generated from said feedback signal and said common node signal;

c) delaying, by a delay circuit, said sampling signal to generate a delayed sampling signal;
d) converting said delayed sampling signal to generate a compensation signal; and
e) regulating an output voltage of said switching power supply based on said compensation signal to compensate for said transmission
voltage loss from said output voltage transmission to a load such that a voltage at said load is maintained as substantially
consistent with an expected voltage at said load;

wherein said delay circuit comprises:
a) first and second switches coupled in series between said sampling signal and said delayed sampling signal, wherein said
second switch is controllable by a clock signal, and said first switch is controllable by an inverted version of said clock
signal;

b) a first capacitor coupled between a common node of said first and second switches and ground; and
c) a second capacitor a coupled between said delayed sampling signal and ground.

US Pat. No. 9,407,140

VOLTAGE DETECTION METHOD AND CIRCUIT AND ASSOCIATED SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method of detecting a voltage, the method comprising:
a) generating a first current according to a first voltage and a converting resistor;
b) charging a detection capacitor by said first current during a first time period of a switching cycle of a switching power
supply, wherein said first voltage comprises an excitation voltage on an inductor of said switching power supply during said
first time period;

c) charging said detection capacitor by a second current during a second time period of said switching cycle, wherein said
first and second currents flow in opposite directions;

d) detecting a voltage across said detection capacitor to obtain a detection voltage at an end time of said second time period,
wherein said first time period comprises a rising portion of a current flowing through said inductor, and said second time
period comprises a decreasing portion of said inductor current; and

e) determining a state of a present output voltage of said switching power supply according to said detection voltage, wherein
said converting resistor comprises a proportion of a predetermined output voltage of said switching power supply and said
second current;

wherein:
a) said present output voltage of said switching power supply is determined to be greater than said predetermined output voltage
when said detection voltage is greater than an initial voltage of said detection capacitor at a beginning of said switching
cycle;

b) said present output voltage of said switching power supply is determined to be equal to said predetermined output voltage
when said detection voltage is equal to said initial voltage of detection capacitor; and

c) said present output voltage of said switching power supply is determined to be less than said predetermined output voltage
when said detection voltage is less than said initial voltage of detection capacitor.

US Pat. No. 9,331,588

CONTROL CIRCUITS AND CONTROL METHODS FOR FLYBACK CONVERTERS AND AC-DC POWER CONVERTERS THEREOF

Silergy Semiconductor Tec...

1. A control circuit for a flyback converter, the control circuit comprising:
a) a turn-on signal generating circuit that is configured, in each switching cycle, to receive a drain-source voltage of a
power switch of said flyback converter, and to activate a turn-on signal to turn on said power switch when said drain-source
voltage reaches a valley value;

b) a turn-off signal generating circuit that is configured, in each switching cycle, to activate a turn-off signal to turn
off said power switch based on a feedback error signal of said flyback converter after a conducting time interval of said
power switch has elapsed, wherein said conducting time interval is in direct proportion to said feedback error signal, and
in inverse proportion to a conducting duty cycle of said power switch; and

c) said flyback converter being configured to receive an input current and an input voltage, wherein said input current and
said input voltage of said flyback converter are maintained as substantially in phase for power factor correction (PFC) by
activation of said turn-on signal and said turn-off signal, and an output electrical signal of said flyback converter is configured
to be maintained as substantially constant.

US Pat. No. 9,419,511

CAPACITOR DISCHARGING METHOD AND DISCHARGING CIRCUIT THEREOF

Silergy Semiconductor Tec...

4. A capacitor discharging circuit for a switching power supply having an X capacitor coupled between input terminals of said
switching power supply, the capacitor discharging circuit comprising:
a) a detection circuit configured to generate a first voltage signal from a voltage at said X capacitor, wherein said detection
circuit comprises a differential circuit configured to differentiate said voltage at said X capacitor to generate a differential
signal, a clamping circuit configured to clamp said differential signal between an upper limit and a lower limit to generate
a clamping signal, and a voltage converting circuit configured to convert said clamping signal to said first voltage signal;

b) said detection circuit comprising a timing circuit configured to receive a clock signal, and being configured to activate
a detection signal in response to said first voltage signal being inactive for a duration of a predetermined time interval,
wherein said detection signal being activated indicates a cut-off of said input terminals; and

c) a discharging circuit configured to at least partially discharge the X capacitor after the cut-off and in response to activation
of the detection signal.

US Pat. No. 9,385,603

CONTROL METHOD AND CONTROL CIRCUIT FOR SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method of controlling a switching power supply, the method comprising:
a) generating an ideal on time signal according to an input voltage and an output voltage of said switching power supply;
b) generating a ripple voltage signal having a predetermined constant value when a power switch of said switching power supply
is on, and a linearly decreasing value when said power switch is off;

c) generating a regulating voltage signal according to an output voltage sense signal and said ripple voltage signal;
d) generating a regulating control signal by comparing said regulating voltage signal against a first reference signal;
e) generating an on time control signal according to said regulating control signal and said ideal on time signal; and
f) generating a driving signal according to said on time control signal for driving said power switch.

US Pat. No. 9,055,629

SCR DIMMING CIRCUIT AND METHOD

Silergy Semiconductor Tec...

1. A silicon-controlled rectifier (SCR) dimming circuit, comprising:
a) an SCR element configured to generate a lack-phase AC voltage based on a sinusoidal AC supply;
b) a rectifier bridge configured to generate a lack-phase DC voltage based on said lack-phase AC voltage;
c) a conduction angle generator configured to receive said lack-phase DC voltage from said rectifier bridge, and to generate
a controlling signal that represents a conduction angle of said SCR element, a clamping voltage, and an adjustment signal;
and

d) a dimming signal generator configured to generate a dimming signal in response to said controlling signal, said clamping
voltage, and said adjustment signal, wherein said dimming signal is configured to regulate luminance of a light-emitting diode
(LED) load in accordance with said lack-phase DC voltage.

US Pat. No. 9,391,467

STEP-UP BATTERY CHARGING MANAGEMENT SYSTEM AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A battery charger, comprising:
a) a step-up converter configured to generate an output signal by boosting a DC input voltage, wherein a threshold voltage
is greater than said DC input voltage;

b) a charging control circuit configured to receive said output signal from said step-up converter, and to control charging
of a battery;

c) said charging control circuit being configured to regulate said output signal by a power transistor operating in a linear
region to maintain a charging current for said battery charging as a trickle current when a battery voltage is less than said
threshold voltage, wherein said power transistor is coupled between said step-up converter and said battery; and

d) said charging control circuit being configured to charge said battery directly by said output signal by said power transistor
operating in a saturation region when said battery voltage is greater than said threshold voltage.

US Pat. No. 9,373,567

LEAD FRAME, MANUFACTURE METHOD AND PACKAGE STRUCTURE THEREOF

Silergy Semiconductor Tec...

1. A method of making a package structure, the method comprising:
a) forming a horizontal plate and a plurality of first conductive bumps by two separate molds, wherein said horizontal plate
is conductive and arranged at a bottom of a lead frame;

b) stamping said plurality of first conductive bumps on corresponding locations of said horizontal plate;
c) arranging a first component above and electrically connected to said horizontal plate of said lead frame by said plurality
of first conductive bumps;

d) forming a plurality of second conductive bumps on said horizontal plate outside of a region covered by said first component,
wherein each of said plurality of second bumps extends to a height greater than said first component;

e) forming a plurality of third conductive bumps on said plurality of second conductive bumps; and
f) arranging a second component above said first component and electrically connecting said second component to said plurality
of third conductive bumps.

US Pat. No. 9,054,580

REFERENCE VOLTAGE REGULATING METHOD AND CIRCUIT FOR CONSTANT CURRENT DRIVER

Silergy Semiconductor Tec...

1. A reference voltage regulating method for a constant current driver, the method comprising:
a) setting a first resistor of a reference voltage circuit to match an ideal equivalent resistor of a current output channel
of a constant current source in said constant current driver;

b) setting a first current of said reference voltage circuit to match an ideal output current of said current output channel;
c) setting a product of said first current and said first resistor to be a reference voltage of said reference voltage circuit;
and

d) setting a product of said ideal output current and said ideal equivalent resistor to be a threshold voltage of said constant
current source, wherein said reference voltage is no less than said threshold voltage.

US Pat. No. 9,271,366

DIMMABLE LED DRIVER AND DRIVING METHOD

(A) Silergy Semiconductor...

1. A dimmable light-emitting diode (LED) driver, comprising:
a) a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge configured to convert an AC voltage
to a DC voltage signal;

b) a power stage circuitry configured to receive said DC voltage signal, and to output a constant current to drive an LED
load, wherein said power stage circuitry comprises first and second power stage circuits, wherein said first power stage circuit
is configured to receive said DC voltage signal, and to generate a first output voltage to said second power stage;

c) an input current control circuit configured to receive an input current of said first power stage circuit and said first
output voltage, and to generate a first control signal to control said input current as a pseudo square waveform signal, wherein
a high frequency saw-tooth waveform is formed from upper portions of said pseudo square waveform signal during an on time
of said SCR;

d) wherein a peak value of said saw-tooth waveform is configured to satisfy a minimum load current requirement of said electronic
transformer, and lower portions of said pseudo square waveform signal are maintained as substantially zero; and

e) said second power stage circuit being configured to generate a substantially constant output current to drive said LED
load in accordance with said input current.

US Pat. No. 9,190,931

LOAD DRIVING CIRCUIT AND METHOD THEREOF

Silergy Semiconductor Tec...

1. A method of driving a load, the method comprising:
a) monitoring an AC input to a rectifier circuit in real-time, wherein said rectifier circuit comprises first and second rectifier
circuits;

b) turning off a first controllable switch and turning on a second controllable switch when said AC input is in a first state,
wherein said first state comprises said AC input being in a positive half cycle and increasing, or said AC input being in
said positive half cycle and decreasing while being at least as high as a predetermined threshold value;

c) using said AC input to supply power to a load circuit and an output capacitor via said first rectifier circuit when said
AC input is in said first state, wherein said first rectifier circuit comprises a first diode and said second controllable
switch;

d) turning on said first and second controllable switches and using said output capacitor to supply power to said load circuit
when said AC input is in a second state, wherein said second state comprises said AC input being in positive half cycle and
decreasing to less than said threshold value;

e) turning on said first controllable switch and turning off said second controllable switch when said AC input is in a third
state, wherein said third state comprises said AC input being in a negative half cycle and having an absolute value increasing,
or said AC input being in said negative half cycle and having said absolute value decreasing and at least as high as said
threshold value;

f) using said AC input to supply power to said load circuit and said output capacitor via said second rectifier circuit when
said AC input is in said third state, wherein said second rectifier circuit comprises a second diode and said first controllable
switch; and

g) turning on said first and second controllable switches and using said output capacitor to supply power to said load circuit
when said AC input is in a fourth state, wherein said fourth state comprises said AC input being in said negative half cycle
and having an absolute value decreasing to be less than said threshold value.

US Pat. No. 9,167,643

HIGH-PRECISION LED CONTROL CIRCUIT, METHOD AND LED DRIVER THEREOF

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal;
b) a current control circuit configured to generate a control signal to control an output current of said LED driver in response
to said reference voltage signal and an output voltage feedback signal from an LED load;

c) a power switch controllable by said enable signal and said control signal that are received at inputs of a logic gate,
wherein an output of said logic gate is only coupled to a gate of said power switch; and d) said LED driver being configured
to drive said LED load when said enable signal is active.

US Pat. No. 9,488,680

VOLTAGE PEAK DETECTION CIRCUIT AND DETECTION METHOD

Silergy Semiconductor Tec...

1. A voltage peak detection circuit, comprising:
a) a voltage coupling circuit configured to inductively couple an input inductor voltage of a switching power supply, and
to generate a first voltage that represents a DC input voltage of said switching power supply;

b) a voltage conversion circuit configured to receive said first voltage, and to generate a second voltage that is proportional
to said first voltage;

c) a holding circuit configured to hold a peak value of said second voltage to generate a peak voltage signal that represents
a peak value of said DC input voltage, wherein a time constant of said holding circuit is configured to meet a transient response
requirement of said peak value of said DC input voltage;

d) a charging control circuit in said holding circuit, and being configured to receive said second voltage and a micro-current
source, and to generate said peak voltage signal, wherein said charging control circuit is configured to increase said peak
voltage signal through said micro-current source when said peak voltage signal is less than said second voltage; and

e) a discharging circuit in said holding circuit, and being configured to control a discharge rate of said peak voltage signal
according to a clock signal.

US Pat. No. 9,214,852

PRECHARGE CIRCUITS AND METHODS FOR DC-DC BOOST CONVERTERS

Silergy Semiconductor Tec...

1. A precharge method for a DC-DC boost converter comprising a current mirror circuit having a reference transistor and a
power transistor, the method comprising:
a) maintaining a reference current flowing through said reference transistor as substantially constant by comparing a voltage
at a first node in a voltage clamping circuit against a reference voltage to generate an error voltage, and by controlling
said reference transistor by said error voltage;

b) maintaining, by said voltage clamping circuit, a drain-source voltage of said reference transistor and a drain-source voltage
of said power transistor as substantially equal, wherein said voltage clamping circuit comprises a first transistor having
a source directly connected to a drain of said reference transistor, and a drain directly connected to a sampling resistor
at said first node; and

c) obtaining a substantially constant mirror current by reflecting said reference current through said power transistor to
operate as a precharging current of a precharge circuit, wherein said current mirror circuit comprises an inductor coupled
between sources of said reference transistor and said power transistor.

US Pat. No. 9,078,323

HIGH EFFICIENCY LED DRIVER AND DRIVING METHOD THEREOF

Silergy Semiconductor Tec...

1. A method of driving a light-emitting diode (LED) device, the method comprising:
a) generating an absolute value of an AC input voltage;
b) generating a driving voltage and a driving current for said LED device through a power switch;
c) generating a reference voltage based on said driving current and an expected driving current of said LED device;
d) comparing said absolute value of said AC input voltage against a sum of said driving voltage and said reference voltage;
e) turning off said power switch when said absolute value of said AC input voltage is greater than said sum of said driving
voltage and said reference voltage; and

f) turning on said power switch to generate an output current when said absolute value of said AC input voltage is greater
than said driving voltage and less than said sum of said driving voltage and said reference voltage.

US Pat. No. 9,065,331

INDUCTOR CURRENT DETECTION CIRCUIT AND LED DRIVER

Silergy Semiconductor Tec...

1. An inductor current detection circuit configured in a switching mode power supply under discontinuous conduction mode,
the inductor current detection circuit comprising:
a) a voltage detection circuit coupled to a secondary winding of a transformer of said switching mode power supply and configured
to generate a sampling voltage based on a drain-source voltage of a power switch in said switching mode power supply;

b) a voltage holding circuit configured to receive said sampling voltage, and to generate a holding voltage through a sampling
and holding operation; and

c) a comparison circuit coupled to an input and an output of said voltage holding circuit and configured to compare said sampling
voltage against said holding voltage, and to generate a zero-crossing signal when said sampling voltage is less than said
holding voltage, wherein said zero-crossing signal is configured to represent an inductor current ending time of said switching
mode power supply.

US Pat. No. 9,529,373

SWITCHING REGULATOR AND CONTROL CIRCUIT AND CONTROL METHOD THEREFOR

Silergy Semiconductor Tec...

1. A control circuit, comprising:
a first controller configured to generate a first control signal for controlling a power switch in a power stage to accumulate
energy in an inductive element in accordance with a feedback voltage representing an output voltage of said power stage, a
ripple signal and a reference voltage; and

a second controller configured to generate a second control signal with a predetermined frequency for controlling a rectifying
switch in said power stage, wherein, a duty cycle of said second control signal varies with a difference between said feedback
voltage and said reference voltage so that a current through said inductive element is shunted by said rectifying switch in
a lightly loaded or unloaded condition.

US Pat. No. 9,123,629

CHIP PACKAGE AND METHOD FOR FORMING THE SAME

Silergy Semiconductor Tec...

7. The method according to claim 6, wherein a plurality of leads are provided while providing said carrier pad;
said plurality of leads are arranged at edges of said carrier pad and have lead pads at surfaces of said plurality of leads,
wherein said surfaces of said lead pads flush with those of said first conductive bumps.

US Pat. No. 9,559,043

MULTI-LEVEL LEADFRAME WITH INTERCONNECT AREAS FOR SOLDERING CONDUCTIVE BUMPS, MULTI-LEVEL PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

Silergy Semiconductor Tec...

1. A leadframe for stacking a plurality of levels of electronic devices, comprising a plurality of leads each having an interconnect
area,
wherein said plurality of leads are grouped so that interconnect areas of each group of said leads have a height corresponding
to one level of electronic devices and are soldered to conductive bumps of said one level of electronic devices,

leads of different groups are coplanar at bottoms in a plane perpendicular to a first direction along which said electronic
devices are stacked

said leads comprise a first group of leads for a lowermost level of electronic devices, to an m-th group of leads for a topmost
level of electronic devices, where m is a natural number larger than 2, and

interconnect areas of an n-th group of leads surround interconnect areas of said first to an (n?1)-th groups of leads, where
n is any natural number larger than 1 and smaller than m.

US Pat. No. 9,699,918

PACKAGE ASSEMBLY AND METHOD FOR MANUFACTURING THE SAME

Silergy Semiconductor Tec...

1. A package assembly, comprising:
a) first and second electrical components stacked on first and second layers;
b) a lead frame comprising a plurality of leads, and being electrically connected to said first and second electrical components;
c) an encapsulating compound overlapping a portion of said lead frame and said first and second electrical components to expose
portions of said plurality of leads of said lead frame from said encapsulating compound; and

d) a heat sink having a first portion arranged between heat transmission mediums of said first and second electrical components,
a second portion extending from said first portion to a surface of said encapsulating compound, and a third portion extending
from said second portion and being exposed at said surface of said encapsulating compound, wherein said heat sink provides
a common heat dissipation path for said first and second electrical components.

US Pat. No. 9,615,415

LED DRIVING CIRCUIT AND METHOD USING SINGLE INDUCTOR

Silergy Semiconductor Tec...

1. An LED driving circuit using a single inductor, comprising:
a power stage circuit configured to
receive a DC bus voltage and
output a constant signal for driving an LED load;
a constant current controller configured to
receive a feedback signal representing an LED load current, and
control operations of a power transistor and a rectifying transistor in said power stage circuit in accordance with said feedback
signal to maintain an output current of said power stage circuit to be constant; and

a constant voltage generating circuit configured to
be connected in parallel with said LED load between an output terminal of said power stage circuit and ground,
receive a current signal at said output terminal of said power stage circuit, and
generate a constant voltage signal by charging a capacitor in said constant voltage generating circuit with said current signal,
wherein said constant voltage signal is configured as a reserve supply voltage of said LED driving circuit.

US Pat. No. 9,712,078

SYNCHRONOUS RECTIFICATION CIRCUIT ADAPTED TO ELECTRONIC TRANSFORMER AND SWITCHING POWER SUPPLY THEREOF

SILERGY SEMICONDUCTOR TEC...

1. A synchronous rectification circuit adapted to an electronic transformer, which receives a voltage signal having a sine
wave envelope from said electronic transformer, comprising a first transistor switch, a second transistor switch, a third
transistor switch, a fourth transistor switch, and a switching control circuit,
wherein said first transistor switch, said second transistor switch, said third transistor switch and said fourth transistor
switch are configured to be a rectifier bridge;

said synchronous rectification circuit has a first input terminal which is a common node between said third transistor switch
and said fourth transistor switch;

said synchronous rectification circuit has a second input terminal which is a common node between said first transistor switch
and said second transistor switch;

said switching control circuit detects voltages at said first and second input terminals, and controls on and off states of
said first to fourth transistor switches in response to detected voltages, in which

said switching control circuit controls an operation state of said second transistor switch in accordance with a voltage at
said second input terminal;

said switching control circuit controls an operation state of said fourth transistor switch in accordance with a voltage at
said first input terminal; and

said switching control circuit controls an operation state of said first transistor switch in accordance with operation states
of said second and fourth transistor switches; and

said switching control circuit controls an operation state of said third transistor switch in accordance with operation states
of said second and fourth transistor switches,

wherein both said second transistor switch and said fourth transistor switch are inactive in a time interval represented by
a dead time signal,

said switching control circuit comprises a first switching control circuit, a second switching control circuit, a third switching
control circuit, and a fourth switching control circuit,

said second switching control circuit comprises a first voltage judgment circuit and a second logic circuit, in which said
first voltage judgment circuit receives said voltage at said second input terminal, compares said voltage with a first threshold
voltage and a second threshold voltage respectively, and generates a first comparison signal and a second comparison signal,

said second logic circuit receives said first comparison signal, said second comparison signal and said dead time signal,
generates a second on signal for turning on said second transistor switch in a case that said voltage at said second input
terminal is less than said first threshold voltage and said dead time signal is active, and a second off signal for turning
off said second transistor switch in a case that said voltage at said second input terminal is larger than said second threshold
voltage;

said fourth switching control circuit comprises a second voltage judgment circuit and a fourth logic circuit, in which said
second voltage judgment circuit receives said voltage at said first input terminal, compares said voltage with a third threshold
voltage and a fourth threshold voltage respectively, and generates a third comparison signal and a fourth comparison signal,

said fourth logic circuit receives said third comparison signal, said fourth comparison signal and said dead time signal,
generates a fourth on signal for turning on said fourth transistor switch in a case that said voltage at said first input
terminal is less than said third threshold voltage and said dead time signal is active, and a fourth off signal for turning
off said fourth transistor switch in a case that said voltage at said first input terminal is larger than said fourth threshold
voltage;

said first switching control circuit comprises a first logic circuit, said first logic circuit receives said second off signal
and said fourth on signal, performs an AND operation, and generates a first on signal for turning on said first transistor
switch; and

said first logic circuit receives said second on signal and said fourth off signal, performs an OR operation, and generates
a first off signal for turning off said first transistor switch;

said third switching control circuit comprises a third logic circuit, said third logic circuit receives said second on signal
and said fourth off signal, performs an AND operation, and generates a third on signal for turning on said third transistor
switch;

said third logic circuit receives said second off signal and said fourth on signal, performs an OR operation, and generates
a third off signal for turning off said third transistor switch.

US Pat. No. 9,627,513

METHOD FOR MANUFACTURING LATERAL DOUBLE-DIFFUSED METAL OXIDE SEMICONDUCTOR TRANSISTOR

Silergy Semiconductor Tec...

1. A method for manufacturing a lateral double-diffused metal oxide semiconductor transistor, comprising:
forming a semiconductor layer of a first doping type;
forming a high-voltage gate dielectric at a surface of said semiconductor layer;
forming a thin gate dielectric above said semiconductor layer to have at least a portion adjacent to said high-voltage gate
dielectric without using a mask;

forming a gate conductor above said thin gate dielectric and said high-voltage gate dielectric without using a mask;
forming a first sidewall of said gate conductor above said thin gate dielectric, by patterning said gate conductor through
a first mask;

forming a second sidewall of said gate conductor at least partially above said high-voltage gate dielectric, by patterning
said gate conductor through a second mask; and

forming source and drain regions of said first doping type,
wherein said method further comprises forming a body region of a second doping type opposite to said first doping type by
doping through said first mask.

US Pat. No. 9,614,437

SWITCHING REGULATOR AND CONTROL CIRCUIT AND CONTROL METHOD THEREFOR

Silergy Semiconductor Tec...

1. A control circuit for controlling a power switch in a power stage of switching regulator, comprising:
a set pulse generator configured to generate set pulses in accordance with a feedback voltage, a ripple voltage and a reference
voltage, wherein said feedback voltage is obtained from an output voltage of said power stage;

a reset pulse generator configured to generate reset pulses in a one to one correspondence with said set pulses by comparing
a sawtooth wave and a threshold voltage, wherein in a first mode a time interval between each said reset pulse and neighboring
set pulse preceding thereto is constant, and in a second mode said time interval decreases with time; and

a logic circuit configured to generate a switching control signal in accordance with said set pulses and said reset pulses,
wherein said switching control signal turns on said power switch when said set pulse occurs and turns off said power switch
when said reset pulse occurs,

wherein said threshold voltage is constant in said first mode and decreases in a predetermined frequency in said second mode
so that a frequency of said switching control signal increases in said second mode.

US Pat. No. 9,595,453

CHIP PACKAGE METHOD AND PACKAGE ASSEMBLY

Silergy Semiconductor Tec...

1. A chip package method, comprising:
etching a metal plate to form at least one trench at a surface of said metal plate;
forming a metallic conductor at said at least one trench by electroplating, with a bottom of said metallic conductor being
located in said at least one trench;

placing a chip on said metallic conductor and electrically coupling electrode terminals of said chip to said metallic conductor
by electric connectors;

encapsulating said chip, said metallic conductor and said electric connectors by a molding process to form a package body,
with said metal plate being exposed from said package body; and

peeling off said metal plate from said package body to separate said metal plate from said metallic conductor and expose a
bottom of said metallic conductor from said package body,

wherein said at least one trench has a predetermined depth so that said at least one trench locks said metallic conductor
before said metal plate is peeled off from said package body, and said metallic conductor is separated from said at least
one trench when said metal plate is peeled off from said package body.

US Pat. No. 9,729,049

SUPPLY VOLTAGE GENERATING CIRCUIT AND SWITCHING POWER SUPPLY

SILERGY SEMICONDUCTOR TEC...

1. A supply voltage generating circuit for providing a supply voltage to a power terminal of a control circuit in a switching
power supply which has a power stage circuit comprising a main power transistor and a rectifying device, said supply voltage
generating circuit comprising: a switching circuit, a unidirectional conduction circuit and an energy storage circuit,
wherein said switching circuit has a first terminal being electrically coupled to a first terminal of said unidirectional
conduction circuit and a current output terminal of said rectifying device, and a second terminal being coupled to a first
ground,

said unidirectional conduction circuit has a second terminal being coupled to said first ground through said energy storage
circuit,

in a time period during which said main power transistor is turned off, said switching circuit is turned off and a current
provided by said rectifying device flows to said energy storage circuit through said unidirectional conduction circuit, in
a case that said supply voltage is smaller than a predetermined voltage reference, and said switching circuit is turned on
and said current provided by said rectifying device flows to said switching circuit, in a case that said supply voltage is
larger than or equal to said predetermined voltage reference, and

said supply voltage is a voltage produced by said energy storage circuit.

US Pat. No. 9,198,245

DIMMING METHOD AND CIRCUIT AND CONTROLLED-SILICON DIMMING CIRCUIT WITH THE SAME

Silergy Semiconductor Tec...

1. A method of controlling dimming, the method comprising:
a) generating a dimming signal according to a DC input voltage signal;
b) generating a voltage average value signal from said dimming signal;
c) determining whether said dimming signal is in a positive half cycle or a negative half cycle;
d) comparing said voltage average value signal against an output current feedback signal to generate a first comparison signal,
and generating a driving signal according to said first comparison signal when said dimming signal is in said positive half
cycle; and

e) comparing said voltage average value signal against said output current feedback signal to generate a second comparison
signal, and generating said driving signal according to said second comparison signal when said dimming signal is in said
negative half cycle.

US Pat. No. 9,872,355

CONTROL CIRCUIT, CONTROL METHOD AND LED DRIVING CIRCUIT THEREOF

Silergy Semiconductor Tec...

1. A control circuit for a light-emitting diode (LED) driving circuit having a rectifier and a power transistor for driving
an LED load, the control circuit comprising:
a) a control signal regulation circuit configured to control a driving voltage of said power transistor to vary with a rectifier
output voltage to control the variation of a current flowing through said power transistor to be consistent with that of said
rectifier output voltage to decrease a power loss of said power transistor; and

b) said control signal regulation circuit being configured to control said driving voltage of said power transistor to vary
with said rectifier output voltage to control the variation of said current flowing through said power transistor to be opposite
to that of said rectifier output voltage to improve a power factor of said LED driving circuit.

US Pat. No. 9,819,270

SWITCHING POWER CONVERTER, CONTROL CIRCUIT AND INTEGRATED CIRCUIT THEREFOR, AND CONSTANT-CURRENT CONTROL METHOD

SILERGY SEMICONDUCTOR TEC...

1. A control circuit configured to control a power stage circuit comprising a first power transistor, a second power transistor
and an inductor, comprising:
a valley-value obtaining circuit configured to obtain a first voltage representing a valley value of an electric current through
said first power transistor;

a peak-value obtaining circuit configured to obtain a second voltage representing a peak value of an electric current through
said second power transistor;

a compensation signal generating circuit configured to generate a compensation signal representing a difference between a
desirable inductor current and an average value of a peak value and a valley value of an inductor current in accordance with
said first voltage, said second voltage and a reference voltage; and

a control signal generating circuit configured to generate a first control signal for controlling said first power transistor
and a second control signal for controlling said second power transistor in accordance with said compensation signal.

US Pat. No. 9,215,763

PULSE CURRENT LED DRIVING CIRCUIT

Silergy Semiconductor Tec...

1. A pulse current light-emitting diode (LED) driving circuit, comprising:
a) an AC power supply configured to generate an AC input;
b) a rectifier circuit configured to receive said AC input voltage, and to generate a DC input voltage;
c) a sampling circuit configured to receive said DC input voltage, and to generate a DC sense voltage;
d) a comparison circuit configured to receive said DC sense voltage, and to generate a first comparison signal;
e) a feedback compensating circuit configured to sample a current that flows through a transistor, and to generate a compensation
signal;

f) a signal processing circuit configured to receive said first comparison signal and said compensation signal, and to generate
an on signal, wherein said signal processing circuit comprises a filter circuit configured to smooth rising edges and falling
edges of said on signal; and

g) said transistor having a gate configured to receive said on signal, a drain configured to receive said DC input voltage,
and a source coupled to a first terminal of a sampling resistor, wherein a second terminal of said sampling resistor is coupled
to a first terminal of a load, and a second terminal of said load is coupled to ground, and wherein said transistor is turned
on and a drain-source current is generated to drive said load when said on signal is active.

US Pat. No. 9,843,210

METHOD FOR TRANSMITTING DATA AND WIRELESS CHARGER FOR IMPLEMENTING SAME

Silergy Semiconductor Tec...

8. A wireless charger configured to power a load, comprising:
a signal transmitter configured to modulate an electric parameter on a first inductive element by cutting off power from said
first inductive element to said load and providing power from said first inductive element to said load in accordance with
a data signal to be transmitted, thereby obtaining a first signal characterizing said data signal with a pattern of said cutting
off and providing of the power; and

a signal receiver configured to sense said first current signal at a second inductive element to generate a second signal
on the second inductive element and to demodulate said second signal to obtain said data signal transmitted thereto;

wherein during data transmission between said signal transmitter and said signal receiver, output current of said wireless
charger is set at a preset current value, and at the end of data transmission said output current is resumed consistent with
a driving current of said load.

US Pat. No. 9,729,068

SWITCHING MODE CONVERTER

SILERGY SEMICONDUCTOR TEC...

1. A switching mode converter, comprising:
an input circuit having a primary-side winding and a primary-side power switch which are coupled in series between an input
terminal and ground;

at least one first output circuit having a first secondary-side winding which is coupled with said primary-side winding;
at least one second output circuit having a second secondary-side winding which is coupled with said primary-side winding,
and at least one secondary-side power switch;

a first control circuit which controls said primary-side power switch to be turned on and off to adjust an output parameter
of said first output circuit; and

a second control circuit which controls said secondary-side power switch to be turned on and off to adjust an output parameter
of said second output circuit,

wherein said first output circuit and said second output circuit are configured so that said second secondary-side winding
feeds back a voltage to said first secondary-side winding with a value less than an output voltage of said first secondary-side
winding so that said first output circuit is blocked when said secondary-side power switch is turned on.

US Pat. No. 9,837,898

PEAK-VALUE CURRENT MODE CONTROL FOR POWER CONVERTERS

SILERGY SEMICONDUCTOR TEC...

1. A control circuit for a power converter, wherein said power converter comprises a power switch and an inductor being coupled
to said power switch, said control circuit controls operation of said power switch to charge and discharge said inductor for
generating an inductor current and providing an output current, said control circuit controls said power switch to be turned
on when or after an inductor current detection signal is zero, and controls said power switch to be turned off when said inductor
current detection signal reaches a peak reference signal or when said power switch has been turned on for a maximum on time,
wherein said control circuit adjusts said maximum on time in accordance with said inductor current detection signal so that
said power converter provides a constant output current to a load.

US Pat. No. 9,900,941

RIPPLE SUPPRESSION CIRCUIT, SUPPRESSION METHOD AND LED LIGHTING APPARATUS

Silergy Semiconductor Tec...

1. A ripple suppression circuit configured to suppress a current ripple provided to a load by a DC converter, the ripple suppression
circuit comprising:
a) a ripple voltage sampling circuit coupled to output terminals of said DC converter, wherein said ripple voltage sampling
circuit is configured to generate a ripple reference voltage that represents a ripple voltage of an output voltage of said
DC converter; and

b) a voltage regulation circuit coupled to said load and said ripple voltage sampling circuit, wherein said voltage regulation
circuit is controllable by said ripple reference voltage such that a voltage across said voltage regulation circuit is consistent
with said ripple voltage.

US Pat. No. 9,967,517

METHODS OF TRANSMITTING AND RECEIVING AUDIO-VIDEO DATA AND TRANSMISSION SYSTEM THEREOF

Silergy Semiconductor Tec...

1. A method for transmitting an audio-video data, the method comprising:a) receiving a video signal from a video source and an audio signal from an audio source;
b) receiving an audio data of said audio signal, and detecting an audio frame clock signal of said audio signal;
c) converting said audio data to an audio data sequence with a first encoding rule;
d) generating a start data code and an end data code according to said audio data sequence and said audio frame clock signal with a second encoding rule;
e) generating an audio frame clock code with said second encoding rule and according to said audio data sequence and said audio frame clock signal, wherein said first encoding rule is different than said second encoding rule;
f) generating a low speed data frame according to said audio frame clock signal and said audio data sequence;
g) inserting said start data code at the beginning of each audio data sequence, and inserting said end data code at the ending of each audio data sequence;
h) inserting said audio frame clock code to said low speed data frame at the beginning of each audio frame clock signal, wherein said audio frame clock code is between said start data code and said end data code in said low speed data frame;
i) packing said low speed data frame and said video signal to form a high speed data frame; and
j) serializing said high speed data frame to form an audio-video transmission data.

US Pat. No. 9,192,004

HIGH-EFFICIENCY LED DRIVER AND DRIVING METHOD

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a silicon-controller rectifier (SCR) coupled to an AC power supply, and configured to generate a DC voltage through a first
rectifier circuit;

b) a first stage power converter circuit having an isolated topology with a power factor correction function, wherein said
first stage power converter circuit is configured to convert said DC voltage to a first output voltage;

c) said first stage power converter circuit comprising a transformer having a primary winding coupled to said DC voltage,
and a secondary winding coupled to said first output voltage through a second rectifier circuit;

d) a second stage power converter circuit having a non-isolated topology, wherein said second stage power converter circuit
is configured to convert said first output voltage to an output current configured to drive an LED load based on a conduction
angle of said SCR;

e) a dimming circuit coupled to said first stage power converter circuit, and configured to output a dimming signal that represents
said SCR conduction angle, wherein said dimming circuit comprises a square wave signal generating circuit coupled to said
secondary winding of said transformer, and is configured to output a square-wave signal as said dimming signal; and

f) a first control circuit configured to receive an LED current signal and said dimming signal, and to control a second stage
power switch to convert said first output voltage to said output current to drive said LED load.

US Pat. No. 9,245,872

FLIP-CHIP PACKAGE STRUCTURE AND METHOD FOR AN INTEGRATED SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A flip-chip package structure, comprising:
a) a die comprising at least one power device of a switching power supply, wherein a surface of said die comprises at least
two polarities;

b) a redistribution layer comprising a plurality of redistribution layer units, each redistribution layer unit having a first
surface and a second surface with different patterns, wherein said first surface is configured to be electrically coupled
to one polarity, and said second surface is configured to redistribute said polarity;

c) a lead frame having a plurality of pins, wherein a first surface of each said pin is configured to be electrically coupled
to said second surface of said redistribution layer, wherein a length of said first surface of each said pin substantially
spans across a length of said die; and

d) a flip-chip package configured to package said die, said redistribution layer, and said lead frame, wherein a second surface
of said lead frame is configured to provide electrical connectivity to said integrated switching power supply.

US Pat. No. 9,054,705

SELF-POWERED SOURCE DRIVING CIRCUIT AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A source driving circuit configured for a switching power circuit, the source driving circuit comprising:
a) a source transistor coupled between a source of a main power transistor and ground, wherein said source transistor is controllable
by a pulse-width modulation (PWM) control signal;

b) said main power transistor being configured to be on when said source transistor is on and a gate-source voltage of said
main power transistor exceeds a conduction threshold voltage;

c) a source diode having an anode coupled to said main power transistor source, and a cathode coupled to a delay circuit and
to a power supply capacitor, wherein said power supply capacitor is not connected to a gate of said main power transistor;
and

d) said delay circuit being coupled to said power supply capacitor and said main power transistor gate, and being configured
to turn off said main power transistor after a delay time from said source transistor being turned off has elapsed, wherein
said power supply capacitor is charged during said delay time such that a voltage across said power supply capacitor is at
least a level of a reference voltage.

US Pat. No. 9,054,546

PRIMARY-SIDE AND SECONDARY-SIDE FULL-BRIDGE SWITCHING CIRCUIT CONTROLLER FOR A MAGNETIC COUPLING AND CONTACTLESS POWER TRANSMISSION APPARATUS

Silergy Semiconductor Tec...

1. An apparatus, comprising:
a) a sweep generator configured to generate a switching pulse signal to control operation of bottom switches of a primary-side
full-bridge switching circuit during an initial operation process;

b) a primary-side switching current zero-crossing detector configured to generate a primary-side current zero-crossing pulse
signal when a primary-side switching current crosses zero;

c) a primary-side pulse-width modulation (PWM) signal generator configured to generate a primary-side PWM signal in accordance
with an input current to control a shut-off operation of top switches of said primary-side full-bridge switching circuit;

d) wherein when in a first operation condition, a frequency of said switching pulse signal is higher than a frequency of said
primary-side current zero-crossing pulse signal, and said switching pulse signal is configured to control a shut-off operation
of said bottom switches of said primary-side full-bridge switching circuit; and

e) wherein when in a second operation condition, the frequency of said switching pulse signal is lower than the frequency
of said primary-side current zero-crossing pulse signal, and said primary-side current zero-crossing pulse signal is configured
to control said shut-off operation of said bottom switches to maintain a power transmitter in a resonant state and an output
voltage of said primary-side full-bridge switching circuit in phase with a current of a primary-side transmitter winding.

US Pat. No. 9,229,035

CURRENT DETECTION CIRCUIT AND SWITCH REGULATOR USING THE SAME

Silergy Semiconductor Tec...

1. A current detection circuit configured to determine an input current and an output current of a switching regulator, the
current detection circuit comprising:
a) a mirror circuit configured to mirror a current flowing through a main power transistor of said switching regulator to
generate a sampling signal that is in proportion to said main power transistor current;

b) a current generating circuit configured to perform a first average value calculation of said sampling signal based on a
switching cycle of said switching regulator to determine said input current; and

c) said current generating circuit being configured to perform a second average value calculation of said sampling signal
based on a conduction duty cycle of said main power transistor to determine said output current.

US Pat. No. 9,192,007

PWM DIMMING CONTROL METHOD AND CONTROL CIRCUIT AND LED DRIVER THEREFOR

Silergy Semiconductor Tec...

1. A pulse-width modulation (PWM) dimming control method for a light-emitting diode (LED) load, the method comprising:
a) receiving a PWM dimming signal and a clock signal in a control circuit, wherein said clock signal is used to determine
an effective width of said PWM dimming signal;

b) setting a minimum value of said effective width of said PWM dimming signal;
c) using said PWM dimming signal as a dimming control signal when said effective width of said PWM dimming signal is greater
than said minimum value;

d) regulating said effective width of said PWM dimming signal as said minimum value, and using said regulated PWM dimming
signal as said dimming control signal, when said effective width of said PWM dimming signal is less than said minimum value;
and

e) controlling a driving current of said LED load according to said dimming control signal.

US Pat. No. 9,391,505

PFC CIRCUIT

Silergy Semiconductor Tec...

1. A power factor correction (PFC) circuit, comprising:
a) a rectifier bridge and a PFC converter coupled to an input capacitor;
b) a harmonic wave compensation circuit configured to shift a phase of a DC input voltage provided from said rectifier bridge,
wherein said harmonic wave compensation circuit comprises a phase of about ?45° when a corner frequency is about 50 Hz;

c) a PFC control circuit configured to control said PFC converter, wherein said PFC control circuit comprises a voltage sampling
circuit coupled to said harmonic wave compensation circuit, and configured to generate a first sampling voltage, and wherein
said harmonic wave compensation circuit is configured to control a phase of said first sampling voltage to lag a phase of
said DC input voltage by about 45°;

d) said PFC control circuit comprising a current sampling circuit configured to sample an output current of said PFC converter,
and to generate a second sampling voltage, and an error signal amplifier circuit configured to generate an error voltage signal
from said first and second sampling voltages, and a reference voltage that represents an average value of said output current;
and

e) said PFC control circuit comprising a driving signal generation circuit configured to generate a driving signal coupled
to a power switch of said PFC converter based on a comparison of said error voltage signal and a ramp signal.

US Pat. No. 9,508,677

CHIP PACKAGE ASSEMBLY AND MANUFACTURING METHOD THEREOF

Silergy Semiconductor Tec...

1. A chip package assembly, comprising:
a) a first substrate at a bottom layer, the first substrate having a first surface and a second surface opposite to said first
surface, wherein said second surface is provided with a first group of inner leads;

b) at least one chip layer above said first group of inner leads, wherein each of said chip layers comprises a third surface
and a fourth surface opposite to said third surface, wherein electrodes on said third surface that that lie at the lowest
level are electrically coupled to said first group of inner leads through a first connector;

c) a second substrate above said fourth surface on the topmost layer and having a fifth surface, wherein said fifth surface
is provided with a second group of inner leads electrically coupled to the electrodes on said fourth surface on the topmost
layer, and wherein said second substrate comprises a sixth surface opposite to said fifth surface;

d) a plastic package in the space between said first and second substrates, wherein side surfaces of said plastic package
expose said first and second groups of inner leads; and

e) first and second groups of outer leads on the side surfaces of said plastic package, being configured to electrically couple
with said first and second groups of inner leads, and extending to said second surface or said sixth surface.

US Pat. No. 9,999,106

DIMMING CIRCUIT, CONTROL CIRCUIT AND DIMMING METHOD

Silergy Semiconductor Tec...

1. A dimming circuit for adjusting the brightness of an LED load, the dimming circuit comprising:a) a primary controlled flyback converter having a primary-side circuit, a first secondary-side circuit, and a second secondary-side circuit;
b) a DC-DC converter coupled in a cascade arrangement with said second secondary-side circuit, wherein an output node of said DC-DC converter is coupled in series to an output node of said first secondary-side circuit;
c) a control circuit configured to control, according to a dimming signal that represents an expected output current of said dimming circuit, a power switch of said primary controlled flyback converter to adjust output voltages of said first and second secondary-side circuits, in order to adjust a power that is provided to said LED load;
d) a reference voltage adjustment circuit configured to adjust a reference voltage of said primary controlled flyback converter according to said dimming signal, wherein said reference voltage represents an expected output voltage of said primary controlled flyback converter; and
e) said control circuit being configured to control a power switch of said DC-DC converter according to said dimming signal, such that said DC-DC converter operates within a predetermined state range.

US Pat. No. 9,444,321

ZERO-CROSSING DETECTION CIRCUIT

Silergy Semiconductor Tec...

1. A zero-crossing detection circuit, comprising:
a) a first detection circuit configured to detect a current through a main transistor of a main circuit of a switching power
supply, and to generate a voltage sense signal that represents said current through said main transistor, wherein said first
detection circuit comprises a first transistor that is coupled to a source of said main transistor;

b) a second detection circuit configured to detect if quasi-resonance occurs in said main circuit, said second detection circuit
being configured to generate at least one pulse signal when said quasi-resonance is detected; and

c) a control circuit configured to receive said at least one pulse signal and said voltage sense signal, to turn said main
transistor off when said current through said main transistor reaches a predetermined value, and to turn said main transistor
on by turning said first transistor on when said at least one pulse signal is active.

US Pat. No. 9,077,260

BOOST POWER FACTOR CORRECTION CONTROLLER

Silergy Semiconductor Tec...

1. A power factor correction (PFC) controller configured for an AC/DC converter, the PFC controller comprising:
a) a conductive signal generator configured to receive a first sampling signal that represents an inductor current, wherein
said first sampling signal is configured to be compared against a first control signal, wherein said first control signal
is in proportion to and rises during a shutdown time of a power switch of said AC/DC converter, wherein when said first control
signal reaches a level of said first sampling signal, said conductive signal generator is configured to output a conductive
signal;

b) a shutdown signal generator configured to compare a second control signal against a third control signal, wherein said
second control signal is in proportion to and rises during a conductive time of said power switch with a first proportionality
coefficient, wherein said third control signal is in proportion to a duty cycle of said power switch with a second proportionality
coefficient, wherein when said second control signal reaches a level of said third control signal, said shutdown signal generator
is configured to output a shutdown signal; and

c) a logic controller coupled to said conductive signal generator and said shutdown signal generator, wherein when said conductive
signal is activated, said logic controller is configured to turn said power switch on, and wherein when said shutdown signal
is activated, said logic controller is configured to turn said power switch off.

US Pat. No. 9,054,592

SYNCHRONOUS RECTIFYING CONTROL METHOD AND CIRCUIT FOR ISOLATED SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

6. A synchronous rectifying control circuit configured for an isolated switching power supply, said synchronous rectifying
control circuit comprising:
a) a voltage determiner configured to receive a power terminal voltage, wherein said power terminal voltage comprises a voltage
between first and second power terminals of a synchronous rectifier in said isolated switching power supply, wherein said
voltage determiner comprises a sample and hold circuit configured to receive said power terminal voltage, and to generate
a sample and hold output, a first comparator configured to receive said sample and hold output and said power terminal voltage,
and to activate a first comparator output when said power terminal voltage begins to decline, and a single pulse generator
configured to activate a drop signal in response to said first comparator output;

b) a ramp voltage generator configured to generate a ramp voltage that continuously rises according to said power terminal
voltage when said drop signal is inactive, wherein said ramp voltage generator is configured to reduce said ramp voltage in
response to said drop signal being activated; and

c) a conduction signal generator configured to receive said ramp voltage, said drop signal, and a threshold voltage, wherein
said threshold voltage substantially matches a minimum conduction time of said synchronous rectifier, and wherein said conduction
signal generator is configured to generate a conduction signal to turn on said synchronous rectifier when said ramp voltage
is higher than said threshold voltage and said drop signal is activated.

US Pat. No. 9,929,137

METHOD FOR MANUFACTURING ESD PROTECTION DEVICE

SILERGY SEMICONDUCTOR TEC...

1. A method for manufacturing an ESD protection device, comprising:forming a first buried layer on a semiconductor substrate;
forming a first epitaxial layer on said semiconductor substrate;
forming a first doped region in said first epitaxial layer; and
forming a second doped region in said first epitaxial layer which surrounds said first doped region,
wherein said semiconductor substrate and said first doped region are both of a first doping type, said buried layer and said first epitaxial layer are both of a second doping type, said first doping type and said second doping type are opposite,
said first doped region and said second doped region are formed using a same first mask.

US Pat. No. 9,924,569

LED DRIVING CIRCUIT

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driving circuit configured to drive an LED load comprising N LED strings, wherein N is a positive
integer no less than 2, the LED driving circuit comprising:
a) a power converter having a power switch;
b) a constant current control circuit configured to control a switching operation of said power switch such that said power
converter generates a driving current for said LED load;

c) N control switches respectively coupled in series to said N LED strings;
d) a pulse-width modulation (PWM) signal generator configured to generate N color tuning PWM signals; and
e) a color tuning control circuit configured to receive said N color tuning PWM signals, and to generate N switching control
signals to correspondingly control switching operations of said N control switches, in order to regulate a ratio of a current
through each LED string of said LED load to said driving current, and to regulate the color temperature of said LED load.

US Pat. No. 9,055,635

CONTROLLED-SILICON ADAPTING LED DRIVING CIRCUIT, METHOD AND SWITCH MODE POWER SUPPLY

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a silicon-controlled rectifier (SCR) and a rectifier bridge configured to receive an AC voltage, and to generate a phase-loss
half sine wave voltage signal to a transformer for driving an LED load;

b) a threshold voltage control circuit configured to receive a threshold voltage and an input voltage signal derived from
said phase-loss half sine wave voltage signal, and to determine whether to output said threshold voltage based on angle information
of said input voltage signal;

c) a first control circuit configured to compare said input voltage signal against said threshold voltage output by said threshold
voltage control circuit, and to generate a first control signal; and

d) a power switch coupled to said transformer controllable by said first control signal to be off until an absolute value
of said AC voltage is reduced to zero.

US Pat. No. 9,161,407

DIMMABLE LED DRIVER AND DRIVING METHOD

Silergy Semiconductor Tec...

1. A dimmable light-emitting diode (LED) driver, comprising:
a) a silicon-controlled rectifier (SCR), an electronic transformer, and a rectifier bridge configured to convert an AC voltage
to a DC voltage signal;

b) a power stage circuit configured to receive said DC voltage signal, and to output a constant current to drive an LED load,
wherein said power stage circuit comprises first and second power stage circuits, wherein said first power stage circuit is
configured to receive said DC voltage signal, and to generate a first output voltage to said second power stage;

c) an input current control circuit configured to receive an input current of said first power stage circuit and said first
output voltage, and to generate a first control signal to control said input current as a square wave signal during an on
time of said SCR, and said input current is maintained as substantially zero during an off time of said SCR;

d) wherein, during said on time of said SCR, a peak of said input current is a substantially constant value that satisfies
a minimum load current requirement of said electronic transformer, and a valley of said input current is substantially zero;
and

e) wherein said LED driver is configured to drive said LED load in accordance with said input current and said first output
voltage.

US Pat. No. 9,129,065

USB DEVICE AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

10. A universal serial bus (USB) device, comprising:
a) an interface module having a power supply port, a ground port, and first and second data ports, wherein said interface
module is configured to connect to corresponding ports of a USB host at a USB interface;

b) a property identification module coupled to said first and second data ports, wherein said property identification module
comprises a processing unit configured to determine properties of said USB interface according to states of first and second
determination signals, wherein a first determination circuit coupled to said first data port is configured to generate said
first determination signal, and a second determination circuit coupled to said second data port is configured to generate
said second determination signal;

c) a data transmission module configured to exchange data between said USB device and said USB host according to said determined
properties;

d) a charging module coupled to said power supply port and said ground port, wherein said charging module is configured to
charge said USB device based on said determined properties;

e) wherein when said first determination signal is active and said second determination signal is inactive, said processing
unit is configured to determine that said USB interface is in an open state, and said data transmission module and said charging
module are disabled;

f) wherein when said first and second determination signals are inactive, said processing unit is configured to determine
that said USB interface comprises a standard downstream interface, said data transmission module is configured to perform
data exchange, and said charging module is configured to charge said USB device at a first current; and

g) wherein when said first and second determination signals are active, said processing unit is configured to determine that
said USB interface comprises a dedicated charging port, said data transmission module is disabled, and said charging module
is configured to charge said USB device at a second current.

US Pat. No. 9,054,088

MULTI-COMPONENT CHIP PACKAGING STRUCTURE

Silergy Semiconductor Tec...

1. A multiple-component chip packaging structure, comprising:
a) a first component;
b) at least one second component arranged on said first component, wherein said at least one second component is electrically
connected to said first component by a plurality of protruding structures, wherein said at least one second component comprises
at least one power transistor;

c) an inductor on said at least one second component, wherein said inductor is coupled to said at least one power transistor
in a configuration of a switching voltage regulator;

d) at least one extension structure arranged on at least one side of said inductor, wherein said at least one extension structure
leads out electrical polarities of said inductor, and wherein said inductor and said at least one extension structure are
in an upper layer of said chip packaging structure; and

e) a plurality of bonding wires, wherein each bonding wire electrically connects one of said at least one extension structure
to said first component.

US Pat. No. 9,837,516

BI-DIRECTIONAL PUNCH-THROUGH SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Silergy Semiconductor Tec...

1. A method of manufacturing a bi-directional punch-through semiconductor device, the method comprising:
a) forming, in a semiconductor substrate of a first conductivity type, a semiconductor buried layer of a second conductivity
type;

b) forming an epitaxy semiconductor layer on said semiconductor substrate, wherein said epitaxy semiconductor layer comprises
a first epitaxy region and a second epitaxy region of different conductivity types;

c) forming a first doped region of said second conductivity type in said second epitaxy region;
d) forming a second doped region of said first conductivity type in said first epitaxy region; and
e) forming a third doped region of said first conductivity type in said first doped region.

US Pat. No. 9,525,334

CONTROL CIRCUIT WITH MULTIPLE FEEDBACK LOOPS AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A control circuit with multiple feedback loops configured for a switching power supply, the control circuit comprising:
a) a plurality of feedback circuits configured to receive a plurality of feedback signals of a power stage circuit, and to
correspondingly generate a plurality of error signals;

b) a plurality of switching circuits configured to transfer said plurality of error signals to a compensation circuit, wherein
each of said plurality of switching circuits is correspondingly coupled to one of said plurality of feedback circuits, and
wherein only one of said plurality of switching circuits is turned on to correspondingly transfer one of said error signals
to said compensation circuit when in a steady status;

c) said compensation circuit being configured to receive said plurality of error signals, and to generate a compensation signal;
and

d) a pulse-width modulation (PWM) control circuit configured to receive said compensation signal, and to generate a PWM control
signal to control operation of a power switch in said power stage circuit.

US Pat. No. 9,515,550

INDUCTOR CURRENT ZERO-CROSSING DETECTION METHOD AND CIRCUIT AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A method of detecting an inductor current zero-crossing in a switching power supply, the method comprising:
a) determining a present output voltage of said switching power supply;
b) generating a zero-crossing detection threshold voltage with a predetermined fixed value when said output voltage is less
than or equal to a predetermined minimum output voltage; and

c) generating a zero-crossing detection signal according to said zero-crossing detection threshold voltage, wherein said zero-crossing
detection signal is used to turn off a synchronous rectifier switch in said switching power supply, wherein said zero-crossing
detection threshold voltage is generated to vary with said output voltage when said output voltage is greater than said predetermined
minimum output voltage.

US Pat. No. 10,027,174

RESONANCE-TYPE CONTACTLESS POWER SUPPLY AND POWER RECEIVER

SILERGY SEMICONDUCTOR TEC...

1. A resonance-type contactless power supply comprising:a high-frequency power supply configured to provide a high-frequency AC current with a predetermined frequency;
a transmitter-side resonant circuit comprising a transmitting coil for receiving said high-frequency AC current from said high-frequency power supply;
a receiver-side resonant circuit comprising a receiving coil which is separated from but coupled to said transmitting coil in a contactless manner, and configured to receive electric energy from said transmitting coil; and
a receiver-side parallel capacitor which is connected in parallel at an output terminal of said receiver-side resonant circuit,
wherein said transmitting coil and said receiving coil are coupled to each other and each have self-inductance including leakage inductance and mutual inductance,
said predetermined frequency is a leakage-inductance resonance frequency in a case that said transmitting coil and said receiving coil are coupled to each other in a predetermined coupling coefficient, and said receiver-side parallel capacitor has a capacitance value equal to 1/n?12LM, wherein ?1 is said angular frequency of said predetermined frequency, LM is a predetermined mutual inductance between said transmitting coil and said receiving coil, and n has a predetermined value,
wherein said transmitter-side resonant and said receiver-side resonant circuit each have a resonant capacitor, and impedances of said leakage inductances and said resonant capacitors are canceled out at said leakage-inductance resonance frequency, both in said transmitter-side resonant circuit and in said receiver-side resonant circuit.

US Pat. No. 9,960,691

CONTROL CIRCUIT, CONTROL METHOD AND FLYBACK CONVERTER OF PRIMARY-SIDE FEEDBACK CONTROL THEREOF

SILERGY SEMICONDUCTOR TEC...

1. A control circuit for controlling a power stage circuit in a flyback converter of primary-side feedback control, comprising:a current sampling circuit configured to sample a primary-side current and to obtain a current sampling signal;
a voltage sampling circuit configured to sample a voltage across an auxiliary winding after a blanking time and to obtain a voltage sampling signal; and
a control signal generating circuit configured to generate a switching control signal in accordance with said voltage sampling signal and said current sampling signal, in which said switching control signal is generated in a constant on time mode when said current sampling signal is larger than a current threshold at a constant on time point, and is generated in a peak current mode when said current sampling signal is smaller than said current threshold at said constant on time point,
wherein said switching control signal controls a power switch in said power stage circuit, and said constant on time point is a time point at which said switching control signal maintains to be valid for a predetermined constant on time period.

US Pat. No. 9,905,636

SUPER-JUNCTION STRUCTURE AND METHOD FOR MANUFACTURING THE SAME AND SEMICONDUCTOR DEVICE THEREOF

SILERGY SEMICONDUCTOR TEC...

1. A super-junction structure comprising:
an epitaxy layer of a first doping type;
a plurality of first pillar regions of a second doping type, which are formed in said epitaxy layer and separated from each
other, and

a second pillar region, which is a portion of said epitaxy layer between adjacent ones of said plurality of first pillar regions
and arranged alternatively with said plurality of first pillar regions to form said super-junction structure,

wherein each of said plurality of first pillar regions comprises a first sub-pillar region and a second sub-pillar region,
said second sub-pillar region is aligned to and stacked on said first sub-pillar region and has a doping concentration smaller
than that of said first sub-pillar region,

when a high voltage is applied to said super-junction structure, a breakdown point is located at said first sub-pillar region,
so that an avalanche current flows through said plurality of first pillar regions and said plurality of second pillar regions.

US Pat. No. 9,907,130

HIGH-EFFICIENCY LED DRIVER AND DRIVING METHOD

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a silicon-controller rectifier (SCR) coupled to an AC power supply, and configured to generate a DC voltage through a first
rectifier circuit;

b) a first stage power converter circuit having an isolated topology with a power factor correction function, wherein said
first stage power converter circuit is configured to convert said DC voltage to a first output voltage;

c) said first stage power converter circuit comprising a transformer having a primary winding coupled to said DC voltage,
and a secondary winding coupled to said first output voltage through a second rectifier circuit; and

d) a second stage power converter circuit having a non-isolated topology, wherein said second stage power converter circuit
is configured to convert said first output voltage to an output current configured to drive an LED load based on a conduction
angle of said SCR.

US Pat. No. 9,899,880

POWER RECEIVER, RESONANCE-TYPE CONTACTLESS POWER SUPPLY AND CONTROL METHOD THEREFOR

SILERGY SEMICONDUCTOR TEC...

1. A resonance-type contactless power supply comprising:
a power transmitter, comprising:
an AC current generating circuit configured to generate an AC current having a first current strength parameter;
a transmitter-side resonant circuit comprising a transmitting coil for receiving said AC current and transmitting electric
energy; and

a transmitter-side control circuit configured to obtain a first signal representing said first current strength parameter
and a number of power receivers being coupled to said transmitter-side resonant circuit, and to transfer them wirelessly;

at least one power receiver, comprising:
a receiver-side resonant circuit comprising a receiving coil which is separated from but coupled to said transmitting coil
in a contactless manner, and configured to receive electric energy from said transmitting coil;

a rectifier circuit being coupled to said receiver-side resonant circuit;
a power converter being coupled to said rectifier circuit; and
a receiver-side control circuit configured to regulate said power converter for maintaining a second current strength parameter
to be m times larger than said first current parameter,

wherein
said second current strength parameter represents a current strength parameter of an AC current which flows though said receiving
coil, Rs is an equivalent resistance of said transmitting coil, Rd is an equivalent resistance of said receiving coil, n is
a number of said power receivers, and said current strength parameter is a peak or an effective value of a current.

US Pat. No. 9,107,270

HIGH EFFICIENCY LED DRIVERS WITH HIGH POWER FACTOR

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver configured to drive an LED device, the LED driver comprising:
a) a rectifier bridge configured to receive an AC input voltage source, and to provide a first input voltage and a second
input voltage;

b) an LED current detection circuit coupled to said LED device, wherein said LED current detection is configured to generate
a feedback signal that represents an error between a driving current and an expected driving current of said LED device;

c) a power stage circuit configured for a buck topology and having a power switch, wherein a first power switch terminal is
coupled to said first input voltage, and a second power switch terminal is coupled to ground;

d) a control circuit coupled to said LED current detection circuit and said power stage circuit, wherein said control circuit
is configured to generate a control signal according to said feedback signal and a drain-source voltage of said power switch,
wherein said control signal is configured, in each switch period, to turn on said power switch when said drain-source voltage
reaches a low level, and to turn off said power switch after a fixed time interval based on said feedback signal; and

e) a bias power supply generating circuit having a diode and a capacitor, wherein said diode is coupled between a common node
of an inductor of said power stage circuit and said LED device, and wherein a voltage at a common node of said diode and said
capacitor is configured as a bias power supply of said control circuit.

US Pat. No. 10,128,227

ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME

SILERGY SEMICONDUCTOR TEC...

1. An ESD protection device, comprising:a semiconductor substrate with a first doping type;
a buried layer, a surface of which is at least exposed on a surface of said semiconductor substrate, wherein said buried layer is of a second doping type opposite to said first doping type;
an epitaxial semiconductor layer located on said semiconductor substrate and said buried layer, and being spaced apart into a first portion and a second portion, wherein said first portion of said epitaxial semiconductor layer is of one of said first doping type and said second doping type, said second portion is of said second doping type;
a first doped region located in said first portion of said epitaxial semiconductor layer, wherein said first doped region is of said second doping type;
a second doped region located in said second portion of said epitaxial semiconductor layer, wherein said second doped region is of said first doping type; and
a doped layer located around said second doped region, wherein said doped layer is of said second doping type,
said ESD protection device comprises a rectifier diode and an open-base bipolar transistor, said first doped region is an anode of said rectifier diode and said semiconductor substrate is a cathode of said rectifier diode, said second doped region, said epitaxial semiconductor layer and said semiconductor substrate are an emitter region, a base region and a collector region of said open-base bipolar transistor, respectively,
said first doped region and said second doped region extend through said doped layer into said epitaxial semiconductor layer by a predetermined depth.

US Pat. No. 9,966,831

CONTROLLER AND CONTROLLING METHOD OF SWITCHING POWER SUPPLY

SILERGY SEMICONDUCTOR TEC...

1. A controller of a switching power supply having a first output terminal for providing a switching control signal for turning on and off a power transistor so that an inductor current flows through an inductor which is connected in series with said power transistor, comprising:a frequency-jittering signal generating circuit configured to generate a frequency-jittering signal variable over time;
a superimpose circuit configured to superimpose said frequency-jittering signal on a sampling signal of said inductor current to generate a superimposed signal; and
a first comparator configured to compare said superimposed signal with a control voltage to generate an OFF signal for turning off said power transistor,
wherein said frequency-jittering signal generating circuit comprises:
a first current source and a first switch which are connected in series between said first output terminal and ground;
a second current source and a second switch which are connected in series between said first output terminal and ground; and
a capacitor which is connected between said first output terminal and ground,
wherein said first current source and said second current source provide currents flowing in opposite directions, and said first switch and said second switch are turned on alternatively.

US Pat. No. 9,525,283

OUTPUT OVERVOLTAGE PROTECTION METHOD AND CIRCUIT FOR SWITCHING POWER SUPPLY AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. An output overvoltage protection method for a switching power supply, the method comprising:
a) charging a first capacitor by a first current during a first time interval of a switching period of said switching power
supply, wherein said first current is in direct proportion with a first proportionality coefficient to an input voltage of
said switching power supply, and wherein said first time interval is substantially the same as a time coefficient of said
input voltage;

b) charging a second capacitor by a second current during a second time interval of said switching period of said switching
power supply, wherein said second current is in direct proportion with a second proportionality coefficient to an upper limit
voltage of a load of said switching power supply, and wherein said second time interval is substantially the same as a time
coefficient of an output voltage of said switching power supply; and

c) generating an overvoltage protection signal by comparing a first voltage across said first capacitor against a second voltage
across said second capacitor at the end of said second time interval, wherein said overvoltage protection signal is active
when said first voltage is at least as high as said second voltage.

US Pat. No. 9,525,344

CONSTANT TIME CONTROLLER AND CONTROLLING METHOD FOR A SWITCHING REGULATOR

Silergy Semiconductor Tec...

1. A method of controlling a switching regulator, the method comprising:
a) detecting an output voltage and an inductor current of said switching regulator;
b) determining if there is a transient change on a load of said switching regulator by using said output voltage and a first
reference voltage;

c) generating a control signal using said output voltage, said inductor current, and a second reference voltage;
d) controlling, by said control signal having a constant pulse width according to a constant time generator configured to
support a constant on-time control mode and a constant off-time control mode, a switch of said switching regulator to maintain
said output voltage as substantially constant when no transient change is determined on said load; and

e) deactivating said control signal by reducing said constant pulse width for a present switching cycle such that said inductor
current changes along with a variation tendency of an output current of said switching regulator when a transient change whereby
said output voltage transitions from a first voltage to a second voltage is determined on said load, wherein said second voltage
is higher than said first voltage for said constant on-time control mode, and said second voltage is lower than said first
voltage for said constant off-time control mode.

US Pat. No. 9,525,357

CONTROL AND DRIVE CIRCUIT AND METHOD

Silergy Semiconductor Tec...

1. A control and drive circuit configured for a synchronous rectification switching power supply, the control and drive circuit
comprising:
a) a primary side switch controller configured to generate a primary side switch control signal to directly control a primary
side power switch of said synchronous rectification switching power supply;

b) a logic circuit configured to generate a first control signal based on said primary side switch control signal;
c) a converting circuit directly connected to a secondary side ground, and being configured to generate a second control signal
based on said first control signal, wherein said second control signal comprises a positive spike signal that rises instantaneously
and decreases exponentially in response to each low to high transition of said first control signal, and a negative spike
signal that falls instantaneously and increases exponentially in response to each high to low transition of said first control
signal;

d) an isolation circuit configured to isolate a primary side ground that is connected to said primary side power switch from
said secondary side ground, wherein said isolation circuit is directly connected to said primary side ground and to said secondary
side ground with no other devices therebetween; and

e) a synchronous rectifier switch controller configured to generate a synchronous rectifier switch control signal based on
said second control signal such that phases of said primary side switch control signal and said synchronous rectifier switch
control signal are the same or inverse based on a topology of said synchronous rectification switching power supply.

US Pat. No. 9,318,960

HIGH EFFICIENCY AND LOW LOSS AC-DC POWER SUPPLY CIRCUIT AND CONTROL METHOD

Silergy Semiconductor Tec...

1. An AC-DC power supply circuit, comprising:
a) a rectifier configured to rectify an AC power supply to generate a DC input voltage;
b) a first stage voltage converter configured to convert said DC input voltage to a first stage output voltage, and to convert
a control signal to a feedback signal that represents said first stage output voltage without using sampling resistors;

c) a second stage voltage converter configured to convert said first stage output voltage to a constant DC output signal,
and to generate said control signal that represents a duty cycle of said second stage voltage converter; and

d) an output voltage feedback circuit in said first stage voltage converter and being configured to average said control signal,
to compare said control signal against a reference value, and to generate said feedback signal via a compensation circuit
to control a switch to convert said DC input voltage to said first stage output voltage.

US Pat. No. 9,214,850

SOURCE-ELECTRODE DRIVING CONTROL CIRCUIT AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A driving control circuit, comprising:
a) a main power switch having a gate connected to a clamping voltage that is greater than a threshold voltage of said main
power switch;

b) a valley voltage detection circuit configured to activate a valley control signal when a drain-source voltage of said main
power switch is at a resonance valley level; and

c) a source voltage control circuit configured to reduce a voltage of a source of said main power switch to turn on said main
power switch in response to said valley control signal being activated.

US Pat. No. 9,170,588

COMPENSATION CIRCUIT AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A compensation circuit, comprising:
a) a transconductance amplifier configured to receive a reference signal and a feedback signal, and to generate an amplifier
output signal according to a difference between said reference signal and said feedback signal;

b) a switching circuit comprising a first switch having a first power terminal connected to said amplifier output signal,
a second power terminal connected to a charging circuit, and a control terminal configured to receive a control signal from
a switch control circuit; and

c) said charging circuit being configured to be charged by said amplifier output signal in response to said control signal,
and to generate a compensation signal therefrom.

US Pat. No. 9,130,456

CONTROL CIRCUIT OF INTERLEAVED SWITCHING POWER SUPPLY AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A control circuit configured for an interleaved switching power supply, the control circuit comprising:
a) a feedback compensation signal generation circuit configured to sample an output voltage of said interleaved switching
power supply, and to generate a feedback compensation signal;

b) a first switch control circuit configured to compare a first branch voltage signal that represents an inductor current
of a first voltage regulation circuit against said feedback compensation signal, wherein when said first branch voltage signal
is consistent with said feedback compensation signal, a first switch on signal is generated to control a first main power
switch of said first voltage regulation circuit to be on for a predetermined time, and then said first main power switch is
controlled to be off; and

c) a second switch control circuit configured to compare a second branch voltage signal that represents an inductor current
of a second voltage regulation circuit against said feedback compensation signal, wherein when said second branch voltage
signal is consistent with said feedback compensation signal, a second switch on signal is generated to control a second main
power switch of said second voltage regulation circuit to be on, and wherein said second switch control circuit is configured
to detect a phase difference between said first and second switch on signals, and to adjust an on time of said second main
power switch to regulate said phase difference to be 180° in response to said phase difference being detected as other than
180°.

US Pat. No. 9,130,460

MASTER-SLAVE INTERLEAVED BCM PFC CONTROLLER AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A master-slave interleaved boundary conduction mode (BCM) power factor correction (PFC) controller for controlling a PFC
circuit with master and slave channels, said PFC controller comprising:
a) a first switch of said master channel, said first switch being configured to control operation of said master channel;
b) a second switch of said slave channel, said second switch being configured to control operation of said slave channel;
c) a first phase shifter configured to generate a slave channel turn-on controlling signal by phase delaying a turn-on signal
of said first switch by less than 180°;

d) a second phase shifter configured to generate a slave channel turn-off controlling signal by phase delaying a turn-off
signal of said first switch by at least 180°; and

e) a slave channel controller configured to receive said slave channel turn-on controlling signal, said slave channel turn-off
controlling signal, and a slave channel inductor current zero-crossing signal, and to generate a slave channel control signal
therefrom, wherein said second switch is configured to be turned on when said slave channel turn-on controlling signal and
said slave channel inductor current zero-crossing signal are both active, and wherein said second switch is configured to
be turned off when said slave channel turn-off controlling signal is active.

US Pat. No. 10,027,155

POWER MANAGEMENT CIRCUIT AND MOBILE TERMINAL

Silergy Semiconductor Tec...

1. A power management circuit, comprising:a bi-directional DC converter comprising a low-voltage terminal, and a high-voltage terminal, and configured to convert a first voltage at said high-voltage terminal into a second voltage and supply said second voltage at said low-voltage terminal in a buck mode, or to convert said second voltage at said low-voltage terminal into said first voltage and supply said first voltage at said high-voltage terminal in a boost mode;
a supply terminal for being electrically coupled to an external power supply or a first load;
a load terminal for being electrically coupled to a second load;
a capacitor being electrically coupled between said load terminal and a ground terminal;
a first switch being electrically coupled between said supply terminal and said high-voltage terminal, and configured to be turned off in a case that said second load operates in a first mode and said supply terminal is electrically coupled to said external power supply,
wherein said power management circuit is configured to electrically couple said high-voltage terminal to said load terminal and output electric energy to said load terminal by controlling said bi-directional DC converter to operate in said boost mode, in a case that said second load operates in said first mode.

US Pat. No. 9,955,257

CLASS-D AUDIO AMPLIFIER

SILERGY SEMICONDUCTOR TEC...

1. A class-D audio amplifier, comprising:a loop filter configured to receive and filter an audio signal and provide a first audio signal;
a PWM modulation circuit being electrically coupled to said loop filter, and configured to receive said first audio signal and compare said first audio signal with a triangular wave signal and provide an audio PWM signal;
a power amplifier being electrically coupled to said PWM modulation circuit, and configured to receive and amplify power of said audio PWM signal and provide an output voltage;
an auxiliary power amplifier configured to start to operate when said class-D audio amplifier is powered on and stops operating after said class-D audio amplifier is powered off; and
a soft start circuit configured to suppress noise interference from a control loop when said class-D audio amplifier is powered on,
wherein an output voltage of said power amplifier is not fed back to an input terminal of said loop filter, or said power amplifier is disabled, when said auxiliary power amplifier is active.

US Pat. No. 9,654,005

BATTERY CHARGE AND DISCHARGE MANAGEMENT CIRCUIT AND ELECTRONIC DEVICE THEREOF

Silergy Semiconductor Tec...

1. An apparatus, comprising:
a) a first switch coupled to an external interface and an inductor;
b) a second switch coupled to ground and a common node between said first switch and said inductor;
c) a third switch coupled to ground and a common node between said inductor and a fourth switch, wherein said inductor and
first, second, third, and fourth switches form a power converter;

d) a charge and discharge control circuit coupled to said power converter, and being configured to control said first, second,
third, and fourth switches;

e) an internal load coupled to said fourth switch; and
f) a chargeable battery coupled to said fourth switch, wherein said power converter is configured to provide power from an
external power supply to said battery and said internal load when said external interface is coupled to said external power
supply, wherein said battery is configured to provide power to said internal load and via said power converter to an external
load when said external interface is coupled to said external load, and wherein said battery is configured to provide power
to said internal load when said external interface is disconnected from said external power supply and said external load.

US Pat. No. 9,654,013

CONTROL CIRCUIT, CONTROL METHOD AND PRIMARY-CONTROLLED FLYBACK CONVERTER USING THE SAME

Silergy Semiconductor Tec...

1. A control circuit configured to control a power stage circuit of a primary-controlled flyback converter, the control circuit
comprising:
a) a current sense circuit configured to generate a current sense signal by sampling a primary current;
b) a voltage sense circuit configured to generate a voltage sense signal by sampling an auxiliary voltage after a blanking
time has elapsed, wherein said blanking time changes along with a peak of said current sense signal;

c) a control signal generator configured to generate a switch control signal according to said voltage sense signal and said
current sense signal, wherein said control signal generator generates said switch control signal under a constant on time
mode when said current sense signal is greater than a current threshold after a constant on time, and wherein said control
signal generator generates said switch control signal under a peak current mode when said current sense signal is less than
said current threshold after said constant on time; and

d) said switch control signal being configured to control a power switch of said power stage circuit, wherein said switch
control signal is active during said constant on time.

US Pat. No. 9,627,992

CONTROLLING CIRCUIT AND AC/DC CONVERTER THEREOF

Silergy Semiconductor Tec...

1. A controlling circuit configured for an AC/DC converter that receives an AC voltage supply, the controlling circuit comprising:
a) a compensation signal generator configured to generate a compensation signal that is consistent with and follows an error
between an output signal from said AC/DC converter and an expected converter output signal during a first time interval of
a half period of said AC voltage supply, wherein said output signal is lower than a reference level only during said first
time interval;

b) a charging capacitor configured to maintain said compensation signal as substantially constant at a same value as at the
end of said first time interval during a remaining time interval of said half period, wherein said output signal is higher
than said reference level only during said remaining time interval; and

c) a controlling signal generator configured to generate a controlling signal based on said compensation signal to maintain
said output signal as substantially consistent with said expected converter output signal.

US Pat. No. 9,531,281

AC-DC POWER CONVERTER

Silergy Semiconductor Tec...

1. An AC-DC power converter, comprising:
a) a rectifier bridge and filter configured to convert an external AC voltage to a sine half-wave DC input voltage;
b) a first energy storage element configured to store energy from said sine half-wave DC input voltage via a first current
through a first conductive path during a first operation mode, wherein said first current rises during said first operation
mode;

c) a second energy storage element configured to store energy from a second DC voltage via a second current through a second
conductive path during said first operation mode, wherein said second current rises during said first operation mode;

d) a transistor configured to share said first and second conductive paths;
e) said first energy storage element being configured to release energy to a third energy storage element and a load through
a third conductive path during a second operation mode, wherein said third energy storage element is configured to generate
said second DC voltage, and wherein said first current declines during said second operation mode; and

f) said second energy storage element being configured to release energy to said load through a fourth conductive path during
said second operation mode, wherein a peak value of said first current is configured to vary along with said sine half-wave
DC input voltage, and wherein an output of said AC-DC converter is configured to be substantially constant.

US Pat. No. 9,543,828

LOW-NOISE MULTI-OUTPUT POWER SUPPLY CIRCUIT AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A method of controlling a low-noise multi-output power supply circuit, the method comprising:
a) detecting operation states of each of a plurality of switch mode power supplies;
b) generating a frequency modulation signal to control an operating frequency of a switch mode power supply to be substantially
equal to a main frequency signal when said switch mode power supply is detected to operate in a heavy-load steady state;

c) controlling said operating frequency of said switch mode power supply to be independent of said main frequency signal when
said switch mode power supply is detected to operate in a light-load or a dynamic state;

d) shifting a phase of said main frequency signal; and
e) controlling each of said plurality of switch mode power supplies to operate in an interleaved-phase state.

US Pat. No. 9,543,832

CURRENT DETECTION CIRCUIT AND SWITCHING REGULATOR THEREOF

Silergy Semiconductor Tec...

8. A current detection circuit configured for a switching regulator, the current detection circuit comprising:
a feedback controlling circuit configured to control a feedback signal to be consistent with a reference signal, and to generate
a feedback control signal;

a feedback signal generator configured to receive a rise time and a fall time of inductor current of said switching regulator,
and to generate said feedback signal in direct proportion with said feedback control signal;

a comparator configured to receive said feedback signal and said reference signal;
a first switching circuit comprising first and second switches coupled in series between a voltage source and ground, wherein
said first switch is controllable by an output of said comparator, and said second switch is controllable by an inverted version
of said comparator output; and

a first charging capacitor coupled to a common node of said first and second switches, wherein a voltage across said first
charging capacitor is configured as said feedback control signal.

US Pat. No. 9,525,336

HARMONIC CONTROL METHOD AND CIRCUIT FOR FLYBACK SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A harmonic control method for a flyback switching power supply, the method comprising:
a) generating a sense voltage signal based on an output signal of said flyback switching power supply;
b) generating a first compensation signal by determining and compensating an error between said sense voltage signal and a
reference voltage;

c) generating a second compensation signal by regulating said first compensation signal based on a duty cycle of a main power
switch in said flyback switching power supply, wherein said second compensation signal is in direct proportion to said first
compensation signal, and said second compensation signal is in inverse proportion to said duty cycle; and

d) generating a control signal based on said second compensation signal and a triangular wave signal, to control said main
power switch such that said output signal is substantially constant and an input current follows a waveform variation of an
input voltage of said flyback switching power supply.

US Pat. No. 9,444,353

ISOLATED POWER CONVERTER AND ASSOCIATED SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. An isolated power converter, comprising:
a) a transformer having a primary winding and a secondary winding;
b) a secondary rectifier circuit coupled to said secondary winding;
c) a power switch coupled between an input voltage source and a first terminal of said primary winding, wherein a second terminal
of said primary winding is coupled to ground;

d) a feedback circuit coupled between said first and second terminals of said primary winding, and being configured to generate
a voltage feedback signal based on a voltage across said primary winding;

e) a control circuit configured to generate a control signal to control said power switch; and
f) an over voltage protection circuit comprising a comparator configured to compare said voltage feedback signal against a
threshold value, and to activate an over voltage signal when said voltage feedback signal is greater than said threshold value,
and a logic circuit configured to activate a reset signal when said over voltage signal is activated outside of a predetermined
time period, wherein said reset signal is configured to reset said control signal when activated.

US Pat. No. 9,407,138

CONTROL CIRCUIT AND CONTROL METHOD FOR CHARGE PUMP CIRCUIT

Silergy Semiconductor Tec...

1. A method of controlling a charge pump circuit, the method comprising:
a) detecting a difference between an output voltage and an input voltage in real time;
b) generating an error amplifying signal by comparing said difference between said output voltage and said input voltage against
a predetermined difference; and

c) generating a control voltage signal for controlling said charge pump circuit according to said error amplifying signal,
wherein a frequency of said control voltage signal positively changes along with said difference between said output voltage
and said input voltage when said difference between said output voltage and said input voltage is greater than said predetermined
difference.

US Pat. No. 9,144,125

AC-DC POWER CONVERTER

Silergy Semiconductor Tec...

1. An AC-DC power converter, comprising:
a) a rectifier bridge and filter configured to convert an external AC voltage to a sine half-wave DC input voltage;
b) a first energy storage element configured to store energy from said sine half-wave DC input voltage via a first current
through a first conductive path when in a first operation mode, wherein said first current rises during said first operation
mode;

c) a second energy storage element comprising a transformer configured to store energy from a second DC voltage via a second
current through a second conductive path when in said first operation mode, wherein said second current rises during said
first operation mode;

d) a transistor configured to share said first and second conductive paths;
e) said first energy storage element being configured to release energy to a third energy storage element and a load through
a third conductive path when in a second operation mode, wherein said third energy storage element is configured to generate
said second DC voltage, and wherein said first current declines during said second operation mode; and

f) said second energy storage element being configured to release energy to said load through a fourth conductive path during
said second operation mode, wherein a peak value of said first current varies in proportion with said sine half-wave DC input
voltage.

US Pat. No. 10,069,320

ELECTRONIC CIGARETTE WITH MINIATURIZED CHARGING AND DISCHARGING INTEGRATED CIRCUIT THEREFOR

SILERGY SEMICONDUCTOR TEC...

17. An electronic cigarette, comprising: a peripheral circuit and an integrated circuit,wherein said integrated circuit comprises a first connector for being electrically coupled to a rechargeable battery, a second connector for being electrically coupled to an external unit, a third connector for being electrically coupled to a first capacitor, a first voltage regulator and a second voltage regulator,
said first voltage regulator is electrically coupled between said first connector and said third connector, and said second voltage regulator is electrically coupled between said second connector and said third connector;
when said second connector is electrically coupled to an adapter, electric energy from said adapter is converted and supplied to said rechargeable battery through said second voltage regulator and said first voltage regulator successively; and
when said second connector is electrically coupled to an atomizer, electric energy from said rechargeable battery is converted and supplied to said atomizer through said first voltage regulator and said second voltage regulator successively;
wherein said first voltage regulator operates in a bi-directional mode or a parallel mode, and said second voltage regulator operates in a linear mode or a switching mode,
wherein said peripheral circuit comprises said rechargeable battery, a first inductor and a first capacitor, a first terminal of said first inductor is electrically coupled to one end of said rechargeable battery, a second terminal of said first inductor is electrically coupled to said first connector of said integrated circuit, the other end of said rechargeable battery is grounded, a first terminal of said first capacitor is electrically coupled to said third connector of said integrated circuit, a second terminal of said first capacitor is grounded, and said second connector is electrically coupled to said atomizer or said external adapter.

US Pat. No. 9,966,843

SUPPLY VOLTAGE GENERATING METHOD

SILERGY SEMICONDUCTOR TEC...

1. A supply voltage generating method for providing a supply voltage to a control circuit being configured to control a main power transistor in a switching power supply, comprising:in an on time interval of said main power transistor, providing said supply voltage to said control circuit;
in an off time interval of said main power transistor, determining whether the current supply voltage is less than a predetermined voltage reference;
when the current supply voltage is not less than said predetermined voltage reference, providing said supply voltage to said control circuit by controlling a freewheeling current flowing to a first ground through a switching circuit;
when the current supply voltage is less than said predetermined voltage reference, increasing the current supply voltage by controlling said freewheeling current flowing to an energy storage circuit through a unidirectional conduction circuit, until the current supply voltage reaches said predetermined voltage reference, and providing said supply voltage to said control circuit.

US Pat. No. 9,819,176

LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR

Silergy Semiconductor Tec...

1. A low capacitance transient voltage suppressor, comprising:
a first diode having an anode coupled to an I/O port, wherein said first diode induces a first parasitic capacitance;
a resistor having a first terminal coupled to a cathode of said first diode, and a second terminal coupled to a common node;
a second diode having a cathode coupled to said common node, and an anode coupled to a low-voltage terminal, wherein said
second diode induces a second parasitic capacitance, and said first and second diodes are turned on to discharge an electrostatic
discharge (ESD) transient voltage through said resistor during ESD stressing; and

a third diode having an anode coupled to said common node and a cathode coupled to said resistor, wherein said anode of said
third diode comprises a ring structure that laterally surrounds and is separated by a gap from said anode of said first diode,
and wherein said third diode induces a third parasitic capacitance that is smaller than said first and second parasitic capacitances,
and said third parasitic capacitance in series with said first and second parasitic capacitances dominates a small capacitance
in a path during normal operation.

US Pat. No. 9,741,655

INTEGRATED CIRCUIT COMMON-MODE FILTERS WITH ESD PROTECTION AND MANUFACTURING METHOD

Silergy Semiconductor Tec...

1. A common-mode EMI filter IC incorporating ESD protection, comprising:
a primary spiral inductor coil;
a secondary spiral inductor coil disposed corresponding to said primary spiral inductor coil, wherein said secondary spiral
inductor coil has the same layout shape and orientation as said primary spiral inductor coil, and wherein each of said primary
and secondary spiral inductor coils comprises a metal line formed by a fine-pitch thick metal re-distribution layer (RDL)
process technique and having a pitch of less than 5 ?m and a thickness from 10 ?m to 30 ?m for reduced insertion loss;

a dielectric layer electrically separating said primary spiral inductor coil and said secondary spiral inductor coil; and
a high-resistance substrate, wherein said primary spiral inductor coil, said secondary spiral inductor coil, and said dielectric
layer are disposed on top of said high-resistance substrate, and a resistivity of said substrate is greater than 100 ?-cm.

US Pat. No. 9,653,355

FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF

Silergy Semiconductor Tec...

1. A flip chip package structure, comprising:
a) a pad on a die;
b) an isolation layer on said die and said pad, wherein said isolation layer comprises a through hole that exposes a portion
of said pad;

c) a metal layer on said pad, wherein said metal layer fully covers said exposed portion of said pad, and wherein said metal
layer is fully contained within said through hole; and

d) a bump on said metal layer, wherein said bump is separated from said isolation layer by gaps, wherein said bump comprises
a top portion that is wider than a bottom portion, and wherein said bottom portion is the only portion of said bump that is
in contact with said metal layer.

US Pat. No. 9,564,795

RIPPLE FILTER CIRCUIT AND RIPPLE FILTER METHOD

Silergy Semiconductor Tec...

1. A method of filtering a ripple, the method comprising:
a) generating, by a sampling circuit, a sense voltage signal that represents an output current flowing through a load;
b) generating, by a filter circuit, a filter voltage signal by filtering said sense voltage signal, wherein said filter circuit
comprises a switch capacitor circuit and a filter capacitor; and

c) generating, by an error amplifying circuit, an error compensation signal by amplifying a difference between said sense
voltage signal and said filter voltage signal, wherein said error compensation signal is configured to compensate and regulate
said output current flowing through said load by controlling a power switch that is coupled to said load and said sampling
circuit.

US Pat. No. 9,559,542

BATTERY POWERED CIRCUIT AND METHOD

Silergy Semiconductor Tec...

1. An apparatus, comprising:
a) a power converter having an output terminal configured to supply power for a load;
b) a first switch coupled between said power converter and an input voltage;
c) a second switch coupled between a battery and said output terminal of said power converter;
d) a pulse-width modulation (PWM) controller configured to control a switching state of a power transistor in said power converter;
e) a mode-switching circuit configured to select a charging mode or a discharging mode based on a voltage of said battery
and a charging current; and

f) a charging-discharging circuit configured to control said second switch based on said mode selection.

US Pat. No. 9,543,822

OVER VOLTAGE PROTECTION CONTROL METHOD AND CIRCUIT FOR FOUR-SWITCH BUCK-BOOST CONVERTER

Silergy Semiconductor Tec...

5. An apparatus, comprising:
a) a buck-boost converter comprising a first switch coupled to an input terminal and an inductor, a second switch coupled
to ground and a common node of said first switch and said inductor, a third switch coupled to ground and a common node of
a fourth switch and said inductor, wherein said fourth switch is coupled to an output terminal of said buck-boost converter;

b) an over voltage detection circuit comprising a comparator configured to receive a voltage feedback signal indicative of
an output voltage of said buck-boost converter at a first input terminal, and an over voltage threshold signal at a second
input terminal, and to generate an over voltage signal;

c) a first control circuit configured to generate a first PWM control signal according to an operation mode of said buck-boost
converter;

d) a first logic circuit configured to receive said first PWM control signal and said over voltage signal from said comparator,
and to control said first and second switches;

e) a second control circuit configured to generate a second PWM control signal according to said operation mode of said buck-boost
converter; and

f) a second logic circuit configured to receive said second PWM control signal and said over voltage signal from said comparator,
and to control said third and fourth switches, wherein said second and third switches are controlled to be on, and said first
and fourth switches are controlled to be off, when said voltage feedback signal is greater than said over voltage threshold
signal.

US Pat. No. 9,543,824

ACTIVE POWER FACTOR CORRECTION CONTROL CIRCUIT, CHIP AND LED DRIVING CIRCUIT THEREOF

Silergy Semiconductor Tec...

1. An active power factor correction (APFC) control circuit, configured to generate a pulse-width modulation (PWM) control
signal to control the operation of a power converter, the APFC control circuit comprising:
a) an inductor current zero crossing detection circuit coupled to a source of a power switch of said power converter, wherein
said inductor current zero crossing detection circuit is configured to generate a comparison signal based on a voltage at
said source of said power switch;

b) said comparison signal being activated when an inductor current of said power converter decreases to zero; and
c) said APFC control circuit being configured to drive said source of said power switch.

US Pat. No. 9,479,060

CONTROL CIRCUIT, BATTERY POWER SUPPLY DEVICE AND CONTROL METHOD

Silergy Semiconductor Tec...

1. A control circuit, comprising:
a) a boost mode controller configured to control a switch type converter to operate in a boost mode such that an input current
is less than a first input current threshold, wherein said switch type converter comprises a first terminal coupled to a power
supply line from an external power supply to a load, and a second terminal coupled to a battery;

b) a buck mode controller configured to control said switch type converter to operate in a buck mode; and
c) a select circuit configured to select either said boost mode controller or said buck mode controller to control said switch
type converter based on a detected value of said input current of said external power supply and a detected value of a battery
charging/discharging current.

US Pat. No. 10,037,987

SEMICONDUCTOR STRUCTURE OF ESD PROTECTION DEVICE AND METHOD FOR MANUFACTURING THE SAME

SILERGY SEMICONDUCTOR TEC...

1. A method for manufacturing a semiconductor structure of an ESD protection device, comprising:forming a buried layer with a first doping type and a buried layer with a second doping type in a first region and a second region on a top surface of a semiconductor substrate with said first doping type, respectively;
forming an epitaxial layer with said second doping type on said buried layer with said first doping type and said buried layer with said second doping type,
wherein said buried layer with said first doping type and said buried layer with said second doping type are buried between said semiconductor substrate and said epitaxial layer, a first doped region with said first doping type is formed on a top of a third region of said epitaxial layer which is on said buried layer with said second doping type.

US Pat. No. 9,559,591

MULTI-PHASE INTERLEAVED CONVERTER WITH AUTOMATIC CURRENT-SHARING FUNCTION AND CONTROL METHOD THEREFOR

Silergy Semiconductor Tec...

1. A multi-phase interleaved converter, comprising:
a) a plurality of phases, wherein each phase of said multi-phase interleaved converter comprises a buck-type power stage having
a power switch, a freewheeling switch and an inductor, a switching control circuit and a reference signal generator, and wherein
each switching control circuit comprises an adder, a comparator, an on time control circuit, and a logic circuit;

b) said adder being configured to receive a ramp signal and a feedback signal that represents an output voltage of said multi-phase
interleaved converter, and to generate a feedback voltage signal;

c) said comparator being configured to receive said feedback voltage signal and a reference voltage signal, and to generate
a comparator output signal;

d) said logic circuit being configured to receive said comparator output signal and an output from said on time control circuit,
and to control a switching operation of said power switch; and

e) said reference signal generator being configured to provide said reference voltage signal of each phase according to an
inductor current sense signal of each phase, such that current-sharing occurs between each of said plurality of phases.

US Pat. No. 9,391,511

FAST RESPONSE CONTROL CIRCUIT AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A control circuit configured to control a switch mode power supply, said control circuit comprising:
a) a compensation signal generating circuit configured to generate a compensation signal according to an error between an
output voltage feedback signal and a first reference voltage of said switch mode power supply;

b) a switching signal generating circuit configured to control a switching operation of a power switching device of said switch
mode power supply according to said compensation signal;

c) a judge circuit configured to determine an operation state of said switch mode power supply according to said output voltage
feedback signal, wherein said judge circuit comprises a first comparator configured to receive a first threshold signal, a
second comparator configured to receive a second threshold signal, a first diode having an anode coupled to an output of said
first comparator, a second diode having an anode coupled to an output of said second comparator, a first resistor coupled
between a cathode of said first diode and ground, and a second resistor coupled between a cathode of said second diode and
ground; and

d) a loop gain regulating circuit configured to regulate a loop gain of said control circuit according to said operation state.

US Pat. No. 10,084,347

POWER TRANSMITTER, RESONANCE-TYPE CONTACTLESS POWER SUPPLY AND CONTROL METHOD THEREFOR

SILERGY SEMICONDUCTOR TEC...

1. A resonance-type contactless power supply, comprising:an inverter circuit configured to receive electric energy and output an AC current with a self-inductance resonance frequency in accordance with an inverter control signal;
a transmitter-side resonant circuit comprising a transmitting coil for transmitting electric energy;
a receiver-side resonant circuit comprising a receiving coil which is separated from but electrically coupled to said transmitting coil in a contactless manner, and configured to receive electric energy from said transmitting coil;
a rectifier circuit being electrically coupled to said receiver-side resonant circuit for converting an AC current from said receiver-side resonant circuit to a DC current; and
a control circuit configured to adjust a phase difference of said inverter control signal in a current cycle in a manner the same as that in a previous cycle in a case that a power parameter in said current cycle and that in said previous cycle satisfy a predetermined relationship, and adjust said phase difference of said inverter control signal in said current cycle in a manner opposite to that in said previous cycle in a case that said power parameter in said current cycle and that in said previous cycle don't satisfy said predetermined relationship, wherein said power parameter represents a difference between an input power of said inverter circuit and an output power of said rectifier circuit, or a ratio of said input power of said inverter circuit to said output power of said rectifier circuit,
wherein said control circuit comprises an inverter signal generating circuit configured to generate said inverter control signal in accordance with a compensation signal,
said inverter signal generating circuit comprises a comparator configured to compare said compensation signal and a triangular wave signal and to generate a pulse-width modulation signal, and a phase shift control circuit configured to provide said inverter control signal with said phase difference responding to said pulse-width modulation signal.

US Pat. No. 9,742,302

ZERO-CROSSING DETECTION CIRCUIT AND SWITCHING POWER SUPPLY THEREOF

Silergy Semiconductor Tec...

1. A zero-crossing detection circuit, comprising:
a) a state judging circuit configured to generate a judging signal based on whether a body diode of a synchronous power switch
is conducting when said synchronous power switch is off;

b) a regulation voltage generator configured to reduce a regulation voltage when said judging signal indicates that said body
diode is conducting, and to increase said regulation voltage when said judging signal indicates that said body diode is not
conducting, wherein a detection voltage comprises a sum of said regulation voltage and a voltage at a first terminal of said
synchronous power switch; and

c) a first comparison circuit configured to compare said detection voltage against a voltage at a second terminal of said
synchronous power switch, and to generate a zero-crossing detection signal, wherein said zero-crossing detection signal is
activated to turn off said synchronous power switch when said detection voltage equals said voltage at said second terminal
of said synchronous power switch.

US Pat. No. 9,698,693

CONTROL CIRCUIT, CONTROL METHOD AND SWITCH-TYPE CONVERTER

Silergy Semiconductor Tec...

1. A control circuit configured to control a power stage circuit of a switch-type converter, the control circuit comprising:
a) a current detection circuit configured to detect whether an inductor current rises to a first threshold value during an
on time of a first switch, and to detect whether said inductor current is greater than a second threshold value when an on
time of a second switch is greater than or equal to a current detection blanking time, wherein said power stage circuit comprises
said first and second switches and said inductor;

b) a logic circuit configured to deactivate a first switch control signal and to activate a second switch control signal when
said inductor current rises to said first threshold value such that said first switch remains off and said second switch remains
on during a regulation time; and

c) said logic circuit being configured to generate said first and second switch control signals according to a pulse-width
modulation (PWM) signal and a zero-crossing detection signal outside of said regulation time, wherein said regulation time
is a larger of a first time and a second time, wherein said first time comprises a predetermined time, and said second time
comprises a time duration that said inductor current decreases from said first threshold value to said second threshold value.

US Pat. No. 9,641,084

CONTROL METHOD AND CONTROL CIRCUIT FOR SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method of controlling a switching power supply, the method comprising:
a) generating a driving current signal that follows a waveform of a sense voltage signal, wherein said sense voltage signal
is related to a current through a collector of a transistor that is configured as a power switch of said switching power supply,
wherein said collector is coupled to an inductive element of said switching power supply;

b) providing said driving current signal to a base of said transistor, wherein said transistor is in a saturated conduction
state when a pulse-width modulation (PWM) signal is active;

c) releasing charge accumulated on said base when said PWM signal is inactive to turn off said transistor; and
d) generating, prior to said generating said driving current signal, a single pulse signal at a rising edge of said PWM signal,
a superimposing voltage signal by adding said single pulse signal to said sense voltage signal, and said driving current signal
according to said superimposing voltage signal.

US Pat. No. 9,786,521

CHIP PACKAGE METHOD FOR REDUCING CHIP LEAKAGE CURRENT

Silergy Semiconductor Tec...

1. A chip package method, comprising:
a) forming bonding pins on a first region of a first surface of a carrier;
b) forming an insulating layer on an inactive face of a chip, wherein said inactive face of said chip is opposite to an active
face of said chip;

c) pasting said chip on a second region of said first surface of said carrier by said insulating layer;
d) electrically coupling electrodes on said active face of said chip to said bonding pins by conductive wires;
e) forming an enclosure to cover said chip and said bonding pins by a molding process; and
f) peeling away said carrier from said enclosure to expose said bonding pins and said insulating layer on a second surface
of said enclosure.

US Pat. No. 9,787,302

SOURCE DRIVER CIRCUIT AND CONTROL METHOD THEREOF

Silergy Semiconductor Tec...

1. A source driver circuit configured for a power converter comprising a main switching transistor having a control terminal
and first and second power terminals, the source driver circuit comprising:
a) a control transistor having a control terminal and first and second power terminals, wherein said control transistor is
coupled between said second power terminal of said main switching transistor and ground;

b) a power supply capacitor coupled between said control terminal of said main switching transistor and ground, wherein said
power supply capacitor is configured to receive a bias voltage that is substantially constant;

c) a regulation resistor coupled between said bias voltage and said control terminal of said main switching transistor;
d) a freewheeling diode having a cathode coupled to said control terminal of said main switching transistor, and an anode
coupled to said second power terminal of said main switching transistor;

e) said control transistor being controllable to be periodically turned on and off to control said main switching transistor
to correspondingly follow on and off states of said control transistor, wherein when said main switching transistor is on,
a current of a main current path flows from said first power terminal of said main switching transistor to said second power
terminal of said main switching transistor, and flows from said first power terminal of said control transistor to said second
power terminal of said control transistor; and

f) said main switching transistor having an on time interval comprising a first time interval from an end of an off state
to a beginning of a fully on state, and a second time interval when said main switching transistor is fully on, wherein said
control transistor is configured to provide a substantially constant start-up current during said first time interval.

US Pat. No. 9,742,291

CONTROL CIRCUIT AND RELATED INTEGRATED CIRCUIT AND SWITCHING-TYPE CONVERTER

Silergy Semiconductor Tec...

1. A control circuit, comprising:
a) a power supply circuit comprising a bias capacitor coupled between a power terminal and a common node, wherein said power
supply circuit is configured to supply power to said control circuit via said bias capacitor;

b) a detection circuit coupled between said common node and a current output terminal of a main power switch of a power stage
circuit, wherein said detection circuit is configured to detect current flowing through said main power switch;

c) a current feedback circuit configured to generate a feedback signal according to a difference value between a sense value
obtained from a voltage at said power terminal during an off state of said main power switch and a present voltage at said
power terminal, wherein said feedback signal represents an inductor current of said power stage circuit;

d) a control signal generator configured to generate a control signal according to said feedback signal to control said main
power switch; and

e) said current feedback circuit comprising a trigger circuit configured to activate a trigger signal when said control signal
represents an off state of said main power switch in each switching cycle, a sample and hold circuit configured to sample
said voltage at said power terminal according to said trigger signal, and to generate said sense value, and a differential
amplifier configured to generate said feedback signal according to said difference value between said sense value and said
voltage at said power terminal.

US Pat. No. 9,769,888

DRIVING CIRCUIT AND DRIVING METHOD FOR A PLURALITY OF LED STRINGS

Silergy Semiconductor Tec...

1. A constant current driving circuit, comprising:
a) a plurality of light-emitting diode (LED) strings;
b) a voltage regulator configured to provide an output voltage signal as a supply for said plurality of LED strings;
c) a plurality of current regulating circuits corresponding to said plurality of LED strings, and being coupled between said
plurality of LED strings and ground, wherein each of said plurality of current regulating circuits is configured to regulate
a driving current through said LED string according to a reference current signal; and

e) a plurality of signal generating circuits corresponding to said plurality of current regulating circuits, wherein each
signal generating circuit is configured to to increase said reference current signal and to regulate an on duty cycle of said
current regulating circuit when an input voltage signal of said current regulating circuit is greater than a voltage threshold,
in order to regulate said driving current to maintain a brightness of said LED string.

US Pat. No. 9,692,288

HIGH-EFFICIENCY BIAS VOLTAGE GENERATING CIRCUIT

Silergy Semiconductor Tec...

1. A switching power supply, comprising:
a) a driver circuit configured to receive a bias voltage, and to drive a gate of a power transistor in a power stage of said
switching power supply;

b) said driver circuit being enabled in response to said bias voltage being at least as high as an expected bias voltage,
wherein a ratio of an output voltage of said switching power supply to said expected bias voltage of said driver circuit is
configured as a proportionality coefficient;

c) a bias voltage generating circuit configured to generate said bias voltage for said driver circuit based on a first voltage,
wherein said bias voltage generating circuit comprises an auxiliary winding, a resistor directly connected to said auxiliary
winding, and a diode directly connected to said resistor, and wherein said first voltage is configured at a common node of
said auxiliary winding and said resistor; and

d) an H-shaped inductor coupled to an input of said bias voltage generating circuit, wherein said first voltage is configured
to be generated based on a number of turns of said H-shaped inductor and said proportionality coefficient.

US Pat. No. 9,871,452

TRANSFORMER, FLYBACK CONVERTER AND SWITCHING POWER SUPPLY WITH THE SAME

Silergy Semiconductor Tec...

1. A flyback converter, comprising:
a) a power switch being controlled to be turned on and off to control a current through a primary side;
b) a first primary winding coupled between an input terminal and a first terminal of said power switch, wherein a dotted terminal
of said first primary winding is coupled to said first terminal of said power switch;

c) a second primary winding coupled between a second terminal of said power switch and a primary grounding terminal, wherein
a dotted terminal of said second primary winding is coupled to said primary grounding terminal, and wherein said second primary
winding is directly connected to said power switch with no other devices therebetween;

d) a secondary winding configured between said first primary winding and said second primary winding in a radial direction
of a magnetic core, wherein said first primary winding, said second primary winding, and said secondary winding are wound
around said magnetic core;

e) a rectifier bridge directly connected to a non-dotted terminal of said first primary winding, and to said dotted terminal
of said second primary winding;

f) a capacitor coupled in parallel with said rectifier bridge, wherein said non-dotted terminal of said first primary winding
is only connected to said rectifier bridge and said capacitor; and

g) a secondary rectifier and filter circuit coupled with said secondary winding, and being configured to generate a stable
current/voltage.

US Pat. No. 9,825,538

VOLTAGE SAMPLING CONTROL METHOD AND RELATED CONTROL CIRCUIT FOR ISOLATED SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method, comprising:
a) generating a sampling signal by sampling a voltage across a winding of a transformer of an isolated switching power supply;
b) activating a first blanking time signal when said sampling signal is higher than a first reference voltage;
c) activating a second blanking time signal when said sampling signal rises to a level of a second reference voltage, wherein
active portions of said first and second blanking time signals at least partially overlap, and said sampling signal is not
detected during activation of either of said first and second blanking time signals;

d) generating a detection signal from said sampling signal after both of said first and second blanking time signals have
been deactivated; and

e) generating a feedback signal according to said detection signal.

US Pat. No. 9,788,369

LED DRIVER AND LED DRIVING METHOD

Silergy Semiconductor Tec...

7. A light-emitting diode (LED) driver for an LED load, the LED driver comprising:
a) a main power switch and a control circuit, wherein an output terminal of said control circuit is coupled to a gate of said
main power switch for controlling switching states of said main power switch, and wherein said main power switch is coupled
to said LED load;

b) an auxiliary power switch coupled to a DC bus voltage and said main power switch;
c) a capacitor coupled between a supply voltage of said control circuit and a control ground, wherein a voltage across said
capacitor is configured as said supply voltage;

d) a voltage-stabilizing circuit comprising a zener diode coupled to said supply voltage, and being configured to clamp said
supply voltage to a predetermined stable voltage when said supply voltage reaches a level of said predetermined stable voltage,
wherein an anode of said zener diode is directly connected to a common node of said main power switch and an output current
sampling resistor, wherein said output current sampling resistor is directly connected to said LED load; and

e) a supply voltage control circuit coupled between said auxiliary power switch and said supply voltage, wherein said DC bus
voltage is configured to charge said capacitor through said auxiliary power switch and said supply voltage control circuit
when said main power switch is off, and wherein said DC bus voltage is provided to said main power switch through said auxiliary
power switch, and a driving current output from said main power switch is configured to drive said LED load when said main
power switch and said auxiliary power switch are on.

US Pat. No. 9,739,806

VOLTAGE DETECTION METHOD AND CIRCUIT AND ASSOCIATED SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method of detecting a voltage, the method comprising:
a) charging a detection capacitor by a first current during a first time period portion of a switching cycle of a switching
power supply;

b) discharging said detection capacitor by a second current during a second time period of said switching cycle;
c) detecting a voltage across said detection capacitor to obtain a detection voltage at an end time of said second time period;
and

d) determining a state of a present output voltage of said switching power supply according to said detection voltage;wherein, the method further comprising resetting said voltage across said detection capacitor during a third time period,
wherein said third time period comprises a time portion from said end time of said second time period to a start time of a
next switching cycle.

US Pat. No. 9,755,521

INTERLEAVED SWITCHING POWER SUPPLY AND CONTROL METHOD FOR THE SAME

Silergy Semiconductor Tec...

7. A method of controlling an interleaved switching power supply having a plurality of parallel coupled power stage circuits,
the method comprising:
a) generating an output voltage feedback signal from an output voltage of said interleaved switching power supply;
b) receiving a plurality of switching control signals, and generating an AC ripple signal having a frequency that is N times
a switching frequency, wherein N is equal to a number of said plurality of power stage circuits;

c) generating a superposition signal by adding said output voltage feedback signal with said AC ripple signal;
d) generating a comparison signal from said superposition signal and a reference voltage;
e) dividing said comparison signal into a plurality of turn on control signals for controlling turn on of a plurality of main
power switches in said plurality of power stage circuits, wherein at least two of said plurality of turn on control signals
have a predetermined phase angle therebetween;

f) generating a current-sharing signal from sampling inductor currents in said plurality of power stage circuits;
g) generating a plurality of turn off control signals for controlling turn off of said plurality of main power switches in
response to said current-sharing signal and said plurality of turn on control signals; and

h) generating said plurality of switching control signals for controlling said plurality of main power switches in response
to said plurality of turn on and turn off control signals.

US Pat. No. 9,722,496

TRANSMISSION VOLTAGE LOSS COMPENSATION CIRCUIT, COMPENSATION METHOD, CONTROLLING CHIP AND SWITCHING POWER SUPPLY

Silergy Semiconductor Tec...

1. A method of compensating for transmission voltage loss from a switching power supply, the method comprising:
a) receiving, in a current feedback circuit, a feedback signal from a feedback terminal that is coupled to an auxiliary winding
of said switching power supply, and a signal from a common node of a sampling resistor and a main switch of said switching
power supply;

b) generating, by said current feedback circuit, a sampling signal that represents an output current of said switching power
supply, wherein said sampling signal is generated from said feedback signal and said common node signal;

d) converting said sampling signal to a compensation signal; and
e) regulating an output voltage of said switching power supply based on said compensation signal and said feedback signal
to compensate for said transmission voltage loss from said output voltage transmission to a load such that a voltage at said
load is maintained as substantially consistent with an expected voltage at said load.

US Pat. No. 10,128,221

PACKAGE ASSEMBLY HAVING INTERCONNECT FOR STACKED ELECTRONIC DEVICES AND METHOD FOR MANUFACTURING THE SAME

SILERGY SEMICONDUCTOR TEC...

1. A package assembly comprising:a leadframe having at least two groups of leads;
an encapsulant layer for filling trenches between adjacent leads of said at least two groups of leads and exposing top surfaces of said at least two groups of leads, and
a plurality of electronic devices stacked in at least two levels,
wherein each group of leads is electrically coupled to and is used for securing a respective level of electronic devices, and
said package assembly further comprises a contact pad on at least one lead and being soldered to said electronic devices, and an interconnect being formed integrally with said contact pad and extending at least partially on said encapsulant layer for coupling one or more leads of one group of leads to one or more leads of another group of leads.

US Pat. No. 10,084,322

TUNING CIRCUIT, TUNING METHOD AND RESONANCE-TYPE CONTACTLESS POWER SUPPLY

SILERGY SEMICONDUCTOR TEC...

1. A tuning circuit for tuning a resonance-type contactless power supply, comprising:a sampling circuit configured to obtain a sampling value of an inductor current from a resonance-type contactless power supply in each cycle, and to provide a first sampling signal and a second sampling signal, wherein said first sampling signal represents a sampling value in a current cycle, and said second sampling signal represents a sampling value in a previous cycle;
an adjustment instruction circuit configured to generate an adjustment signal the same as that in said previous cycle in a case that said first sampling signal is larger than said second sampling signal, or opposite to that in said previous cycle in a case that said first sampling signal is less than said second sampling signal; and
a control signal adjusting circuit configured to regulate a frequency of a control signal of an inverter circuit in accordance with said adjustment signal,
wherein said adjustment signal instructs said frequency of said control signal to increase or decrease by a predetermined amount.

US Pat. No. 9,780,081

CHIP PACKAGE STRUCTURE AND MANUFACTURING METHOD THEREFOR

Silergy Semiconductor Tec...

1. A chip package structure, comprising:
a) a lead frame having a carrier substrate and a first lead around said carrier substrate;
b) a first conductive post arranged on said first lead and electrically coupled with said first lead;
c) a first chip having an active face and an inactive face opposite to said active face, wherein said inactive face is attached
to said carrier substrate, and electrode pads on said active face are provided with a first electrical connector;

d) a first plastic package configured to fully encapsulate said first chip, and to partly encapsulate said lead frame, wherein
said first plastic package comprises a first surface and a second surface opposite to said first surface, wherein said first
conductive post and said first electrical connector are exposed on said first surface, and wherein said first lead is exposed
on said second surface, and

e) a second lead being arranged on said first surface, wherein said second lead is configured to electrically couple said
first electrical connector with said first conductive post.

US Pat. No. 9,774,264

CONTROL CIRCUIT AND CONTROL METHOD FOR SWITCHING POWER SUPPLY OPERATING IN QUASI RESONANT MODE

Silergy Semiconductor Tec...

1. A control circuit, comprising:
a) an output current sampling circuit configured to sample a current through a power switch of a switching power supply operating
in a quasi-resonant mode, and to generate an output current feedback signal that represents an output current of said switching
power supply; and

b) a valley locking circuit configured to receive said output current feedback signal and a plurality of valley switching
threshold voltages, wherein said valley locking circuit is switched to a corresponding valley from a valley currently being
locked when said output current feedback signal is increased or reduced to one of said plurality of valley switching threshold
voltages.

US Pat. No. 9,774,285

VOLTAGE SENSE CONTROL CIRCUIT, VOLTAGE SENSE CONTROL DRIVING CIRCUIT AND DRIVING METHOD FOR PERMANENT MAGNET SYNCHRONOUS MOTOR

Silergy Semiconductor Tec...

1. A driving circuit of a permanent magnet synchronous motor (PMSM), the driving circuit comprising:
a) a current sampling circuit configured to obtain a current sampling signal by sampling a rotor current of one phase of said
PMSM;

b) a sliding mode estimating circuit configured to receive said current sampling signal and a voltage sampling signal that
represents a rotor voltage of said phase, to estimate a back electromotive force information of said phase, and to generate
a first voltage signal that represents said back electromotive force information;

c) a speed computing circuit configured to receive said first voltage signal, and to generate an angular velocity signal that
represents rotor cycle information; and

d) a pulse-width modulation (PWM) control circuit configured to generate a PWM control signal according to said angular velocity
signal, wherein said PWM control signal is configured to control the turn on and off of switches in a three-phase inverter,
to control an operating current of said PMSM to be a sine wave current.

US Pat. No. 9,735,122

FLIP CHIP PACKAGE STRUCTURE AND FABRICATION PROCESS THEREOF

Silergy Semiconductor Tec...

1. A method of fabricating a flip chip package structure, the method comprising:
a) forming a pad on a die;
b) depositing an isolation layer on said die and said pad;
c) forming a through hole in said isolation layer to selectively expose a portion of said pad;
d) depositing a metal layer on said pad to fully cover said exposed portion of said pad; and
e) forming a bump on said metal layer, wherein said bump is separated from said isolation layer by gaps.

US Pat. No. 9,762,128

CONTROL CIRCUIT OF ISOLATED CONVERTER AND SWITCHING POWER SUPPLY, AND CONTROL METHOD FOR THE SAME

Silergy Semiconductor Tec...

1. A method of controlling an isolated converter comprising a transformer having a primary winding and a secondary winding,
a main power switch coupled with said primary winding, and a freewheeling diode coupled with said secondary winding, the method
comprising:
a) controlling a first voltage signal across said secondary winding according to a wake-up signal to reflect change of an
output voltage of said isolated converter;

b) obtaining a second voltage signal that represents said first voltage signal at said primary side of said isolated converter;
c) detecting said second voltage signal and controlling said main power switch according to a detection result in order to
maintain said output voltage at a predetermined value;

d) generating said wake-up signal according to said output voltage and a first threshold voltage when said isolated converter
is in a dynamic loading state of a normal operating mode;

e) generating said wake-up signal according to said output voltage and a second threshold voltage when said isolated converter
is in a load steady state of a standby operating mode; and

f) generating said wake-up signal according to said output voltage and a third threshold voltage when said isolated converter
is in a dynamic loading state of said standby operating mode.

US Pat. No. 9,756,688

HIGH EFFICIENCY LED DRIVERS WITH HIGH POWER FACTOR

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver configured to drive an LED device, the LED driver comprising:
a) a rectifier bridge configured to receive an AC input voltage source, and to provide a first input voltage and a second
input voltage;

b) an LED current detection circuit coupled to said LED device in series between said second input voltage and a ground, wherein
said LED current detection circuit is configured to generate a feedback signal that represents an error between a driving
current and an expected driving current of said LED device;

c) a power stage circuit having a power switch, wherein a first power switch terminal is coupled to said first input voltage,
and a second power switch terminal is directly connected to said ground; and

d) a control circuit coupled to said LED current detection circuit and said power stage circuit, wherein said control circuit
shares said ground with said power stage circuit, and said control circuit is configured to generate a control signal according
to said feedback signal and a drain-source voltage of said power switch, wherein said control signal is configured, in each
switch period, to turn on said power switch when said drain-source voltage reaches a low level, and to turn off said power
switch after a fixed time interval based on said feedback signal.

US Pat. No. 9,699,838

INDUCTOR CURRENT DETECTION CIRCUIT AND LED DRIVER

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver configured as a switching mode power supply operated in a discontinuous conduction
mode, the LED driver comprising:
a) a power switch with a first power terminal coupled to ground, and a second power terminal coupled to an inductor;
b) an inductor current detection circuit configured to detect an ending time of a current of said inductor, and to generate
a zero-crossing signal;

c) a control circuit configured to receive said zero-crossing signal, and to generate a control signal configured to control
a switching operation of said power switch;

d) wherein said control signal is configured to control said power switch to turn on a delay time after activation of said
zero-crossing signal; and

e) wherein said control signal is configured to control said power switch to turn off after a conduction time interval after
said power switch is turned on, wherein said conduction time interval is constant and regulated in accordance with an error
between a present output current of said LED driver and an expected output current.

US Pat. No. 9,699,839

MULTICHANNEL CONSTANT CURRENT LED CONTROLLING CIRCUIT AND CONTROLLING METHOD

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driving circuit, comprising:
a) a switching power stage circuit configured to generate a pseudo-constant output current to drive an LED load, wherein said
LED load comprises a plurality of LED strings coupled in series between outputs of said switching power stage circuit wherein
said plurality of LED strings are controlled by a plurality of pulse-width modulation (PWM) dimming signals to be enabled
or disabled from a series LED current path to control average currents flowing through said plurality of LED strings;

b) a loop steady state network comprising a plurality of steady state holding components configured to hold a plurality of
steady state control signals that correspond to a plurality of load states of said LED load;

c) a control loop configured to generate a first control signal in accordance with a current feedback signal that represents
said driving current of said LED load and a corresponding one of said plurality of steady state control signals to control
operation of said switching power stage circuit;

d) a switching decoder coupled to said loop steady state network, wherein said switching decoder is configured to generate
a selected steady state signal based on said plurality of PWM dimming signals; and

e) a logic circuit coupled to said control loop and configured to generate a gate control signal to control operation of a
power switching transistor of said switching power stage circuit in accordance with said first control signal and said plurality
of PWM dimming signals.

US Pat. No. 9,699,840

HIGH-PRECISION LED CONTROL CIRCUIT, METHOD AND LED DRIVER THEREOF

Silergy Semiconductor Tec...

1. A light-emitting diode (LED) driver, comprising:
a) a reference voltage control circuit configured to provide a reference voltage signal in response to an enable signal, wherein
said reference voltage signal equals a first voltage value when said enable signal is active, and equals a second voltage
value when said enable signal is inactive, wherein said first voltage value is configured to represent an expected output
current of said LED driver;

b) a current control circuit configured to generate a control signal to control an output current of said LED driver in response
to said reference voltage signal and a feedback signal that represents an output current of said LED driver; and

c) a power switch controllable by said enable signal and said control signal, wherein said power switch is controlled by said
control signal to drive an LED load when said enable signal is active, and said power switch is disabled when said enable
signal is inactive.

US Pat. No. 9,698,677

BROWNOUT RECOVERY CIRCUIT FOR BOOTSTRAP CAPACITOR AND SWITCH POWER SUPPLY CIRCUIT

Silergy Semiconductor Tec...

1. A brownout recovery circuit configured for a switch power supply circuit with a first switch, said brownout recovery circuit
comprising:
a) an under-voltage detection circuit configured to activate a detection signal when a bootstrap capacitor is not in an under-voltage
state, and to deactivate said detection signal when said bootstrap capacitor is in said under-voltage state;

b) a logic circuit configured to, when said detection signal is active, generate a first control signal according to a main
control signal from said switch power supply circuit and a switch state of a second switch, wherein an active duration of
said first control signal is less than a first predetermined time when said detection signal is active, and said active duration
of said first control signal is controlled to be said first predetermined time when said detection signal is inactive;

c) a first control circuit configured to generate a first switch signal according to said detection signal and having a same
state as said first control signal, wherein said first switch signal is configured to control said first switch to be turned
on or off when said detection signal is active, and to turn off said first switch when said detection signal is inactive;
and

d) a second control circuit configured to receive said first control signal, and to generate a second switch signal configured
to turn off said second switch when said detection signal is active, and to turn on said second switch when said first control
signal changes from active to inactive and said detection signal is inactive, wherein an on time of said second switch is
controlled to be a second predetermined time when said detection signal is inactive.

US Pat. No. 9,645,200

BATTERY POWER MEASURING METHOD, MEASURING DEVICE AND BATTERY-POWERED EQUIPMENT

Silergy Semiconductor Tec...

1. A method of measuring a battery power, the method comprising:
a) detecting, by a detection device, a voltage and a temperature at an output terminal of a battery;
b) obtaining, from a storage device coupled to said detection device, a first correction coefficient based on a battery open-circuit
voltage at a previous sample time;

c) obtaining, from said storage device, a second correction coefficient based on said battery temperature;
d) calculating, by a calculation device coupled to said detection device and said storage device, a real-time battery open-circuit
voltage by using said voltage at said output terminal of said battery, said first and second correction coefficients, said
battery open-circuit voltage at said previous sample time, and a time interval between said previous sample time and a present
sample time;

e) converting, by a display device coupled to said calculation device, said real-time battery open-circuit voltage into a
battery power measurement for display;

f) determining, by a calibration circuit coupled to said detection device and said calculation device, if said battery is
in a relaxed state based on a changing rate of said real-time battery open-circuit voltage; and

g) setting, by said calibration circuit, said real-time battery open-circuit voltage to be equal to said voltage at said output
terminal of said battery when said battery is in said relaxed state.