US Pat. No. 9,111,874

SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:
providing a to-be-etched layer for making the semiconductor structure;
forming a hard mask layer on the to-be-etched layer;
forming a photoresist layer on the hard mask layer;
forming a patterned photoresist layer having openings exposing the hard mask layer by exposing and developing the photoresist
layer;

forming sidewall spacers on side surfaces of the openings;
forming a patterned hard mask layer by etching the hard mask layer using the patterned photoresist layer and the sidewall
spacers as an etching mask such that patterns in the hard mask layer have a substantially 90 degree angle at edge,

wherein, while etching the hard mask layer, the patterned photoresist layer and the sidewall spacers are also etched such
that remaining sidewall spacers have a height greater than remaining patterned photoresist layer over the to-be-etched layer;
and

forming to-be-etched patterns by etching the to-be-etched layer based on the patterned hard mask layer.

US Pat. No. 9,332,626

EUV LIGHT SOURCE AND EXPOSURE APPARATUS

SEMICONDUCTOR MANUFACTURI...

1. An extreme ultraviolet (EUV) light source, comprising:
a spray nozzle array having a plurality of spray nozzles configured to spray a plurality of rows of droplets to an irradiating
position;

a laser source having a first reflective mirror and a second reflective mirror configured to generate a first laser beam and
a second laser beam and cause the first laser beam and the second laser beam to sequentially bombard the plurality of droplets
arriving at the irradiating position to generate EUV light with increased output power, and

a light focusing device comprising a first partial focusing mirror and a second partial focusing mirror configured to perform
a rotating scanning to collect EUV light and focus the collected EUV light at a central focusing point.

US Pat. No. 9,331,079

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a plurality of fins on the semiconductor substrate;
forming a plurality of shallow trench isolation (STI) structures on the semiconductor substrate on opposite sides of the fins;
forming a dummy gate on the fins;
forming gate spacers on opposite sides of the dummy gate;
etching a first portion of the STI structures disposed outside a gate region, the first portion having a first predetermined
thickness;

forming an interlayer dielectric over the semiconductor substrate;
removing the dummy gate;
etching a second portion of the STI structures disposed in the gate region, the second portion having a second predetermined
thickness; and

forming a high-k dielectric layer and a metal gate in an area where the dummy gate is removed.

US Pat. No. 9,331,069

RESISTOR MEMORY BIT-CELL AND CIRCUITRY AND METHOD OF MAKING THE SAME

Semiconductor Manufacturi...

1. A semiconductor memory control unit comprising:
a semiconductor substrate having a first surface and a second surface opposite the first surface;
a switching transistor; and
a resistive memory cell;
wherein the switching transistor comprises:
a gate disposed over the first surface of the semiconductor substrate;
a source and a drain each disposed in the semiconductor substrate, the drain comprising a first drain portion in the vicinity
of the first surface and a second drain portion in the vicinity of the second surface;

a gate terminal disposed over the first surface and connected to the gate,
a source terminal disposed over the first surface and connected to the source,
a drain terminal disposed over the second surface of the semiconductor substrate and connected to the drain, and
wherein the resistive memory cell is disposed over the second surface and has a first end connected to the drain terminal.

US Pat. No. 9,331,084

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND ADJUSTING THRESHOLD VOLTAGES IN THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a semiconductor device, comprising:
forming a fin structure on a semiconductor substrate;
forming a well region in the semiconductor substrate by ion implantation so as to form transistors, wherein the transistors
include a pull-up (PU) transistor, a transfer gate (PG) transistor, and a pull-down (PD) transistor of a static random-access
memory (SRAM) cell;

the ion implantation being used to adjust threshold voltages of the transistors, wherein standard threshold voltage (SVt)
ion implantation conditions are used to adjust a first threshold voltage of the PU transistor and a second threshold voltage
of the PG transistor, and low threshold voltage (LVt) ion implantation conditions are used to adjust a third threshold voltage
of the PD transistor;

forming a gate electrode for each transistor; and
performing lightly doped drain (LDD) ion implantation and pocket area (PKT) ion implantation on the PU, PG, and PD transistors
of the SRAM cell,

wherein P-type high-threshold voltage (PHVT) ion implantation conditions are used for the LDD ion implantation and PKT ion
implantation of the PU transistor; N-type standard threshold voltage (NSTV) ion implantation conditions are used for the LDD
ion implantation and PKT ion implantation of the PG transistor; and N-type low-threshold voltage (NLVT) ion implantation conditions
are used for the LDD ion implantation and PKT ion implantation of the PD transistor.

US Pat. No. 9,330,964

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS FOR IMPROVING UNDERCUT BETWEEN POROUS FILM AND HARDMASK FILM

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a to-be-etched layer made of a porous low-K dielectric material including boron nitride on one surface of the substrate;
forming a first hard mask layer made of nitrogen-doped silicon oxycarbide (SiOC(N)) directly on the to-be-etched layer;
etching the first hard mask layer to have same patterns corresponding to positions of subsequently formed a plurality of openings;
forming the plurality of openings through an entire thickness of the to-be-etched layer using the first hard mask layer as
an etching;

etching and cleaning a bottom surface of the openings along with side surfaces of both the to-be-etched layer and the first
hard mask layer in the openings by a wet chemical cleaning process, to level the side surfaces of both the to-be-etched layer
and the first hard mask layer with each other in the openings, wherein an etching rate of a solution of the wet chemical cleaning
process to the first hard mask layer and an etching rate of the solution of the wet chemical cleaning process to the to-be-etched
layer is identical; and

after the wet chemical cleaning process, forming a conductive structure in each of the openings.

US Pat. No. 9,330,924

METHOD FOR FORMING CONTROL GATE SALICIDE

Semiconductor Manufacturi...

1. A method for forming a semiconductor device, comprising:
forming a control gate structure of a silicon material on a substrate;
forming a planarized dielectric layer adjacent the control gate structure;
removing a portion of the dielectric layer to expose a top portion of the control gate structure;
removing an outer portion of the exposed top portion of the control gate structure such that the top portion of the control
gate structure has a narrower width than the unexposed portion;

forming a metal layer over the exposed portion of the control gate structure and a top surface of the dielectric layer; and
forming a silicide layer over the top portion of the control gate structure, such that the width of the silicided top portion
of the control gate structure is substantially the same as the width of the bottom portion of the control gate structure.

US Pat. No. 9,337,104

METHOD FOR CHEMICAL MECHANICAL POLISHING OF HIGH-K METAL GATE STRUCTURES

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a semiconductor substrate containing a front-end device, the front-end device comprising a first type metal gate
transistor region including a first dummy gate, a second type metal gate transistor region including a second dummy gate,
and a polysilicon gate transistor region including a polysilicon gate;

forming an interlayer dielectric layer on the semiconductor substrate;
forming a first hard mask layer on the interlayer dielectric layer;
forming a second hard mask layer on the first hard mask layer;
forming a mask layer having an opening on the second hard mask layer exposing a portion of the second hard mask layer disposed
above the first type metal gate transistor;

removing the exposed portion of the second hard mask layer to expose a portion of the first hard mask layer;
removing the exposed portion of the first hard mask layer using a reactive gas that is not susceptible to cause damage to
the interlayer dielectric layer;

removing the first dummy gate;
forming a first work function metal layer in a location where the first dummy gate has been removed;
forming a metal gate layer on the first work function metal layer;
removing a portion of the first work function metal layer and a portion of the metal gate layer that are over the interlayer
dielectric layer, the second hard mask layer, and the first hard mask layer to form a metal gate.

US Pat. No. 9,330,921

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:
a semiconductor substrate;
a memory cell disposed on the semiconductor substrate, wherein the memory cell includes a selection transistor disposed on
a first region of the semiconductor substrate and a memory transistor disposed on a second region of the semiconductor substrate,
wherein the first region and the second region are spaced apart by a third region of the semiconductor substrate,

the selection transistor including a selection gate, a first source, and a first drain disposed on the third region of the
semiconductor substrate,

the memory transistor including a floating gate, a control gate disposed over the floating gate, a second source disposed
on the third region of the semiconductor substrate, a second drain, and a first insulating layer disposed between the floating
gate and the control gate; and

a selection gate sidewall spacer disposed near an edge of a bit line of the selection gate of the selection transistor, wherein
the selection gate sidewall spacer is separated from the selection gate by a second insulating layer, and wherein the selection
gate sidewall spacer and the control gate are formed of a first material.

US Pat. No. 9,298,103

CYLINDRICAL RETICLE SYSTEM, EXPOSURE APPARATUS AND EXPOSURE METHOD

SEMICONDUCTOR MANUFACTURI...

1. An exposure apparatus, comprising:
a base;
a plurality of wafer stages on the base for loading wafers and successively moving from a first position to a second position
of the base cyclically;

alignment detection units above the first position of the base for detecting alignment marks on the wafer, and aligning the
wafers;

a cylindrical reticle system above the second position of the base;
an illuminator box in the cylindrical reticle system;
an optical projection unit between the cylindrical reticle and the base;
a cylindrical lens unit between the optical projection unit and the cylindrical reticle system,
wherein the cylindrical lens units has a flat surface and a concave surface, the flat surface of the cylindrical lens unit
is toward the cylindrical reticle system, and the radian of the concave is determined according to the radius of the cylindrical
reticle.

US Pat. No. 9,334,157

MEMS DEVICE AND FORMATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a MEMS device, comprising:
providing a first substrate including integrated circuits therein;
forming a first dielectric layer on the first substrate;
forming one or more first metal connections and second metal connections in the first dielectric layer, wherein the first
metal connections and the second metal connections are electrically connected to the integrated circuits;

forming a second dielectric layer on the first dielectric layer;
forming an acceleration sensor in the second dielectric layer, the acceleration sensor being electrically connected to the
one or more first metal connections;

providing a second semiconductor substrate and bonding the second semiconductor substrate to the second dielectric layer;
forming one or more first metal vias in the second semiconductor substrate and in the second dielectric layer, the first metal
vias being electrically connected to the second metal connections; and

forming a pressure sensor directly on the second semiconductor substrate, the pressure sensor being electrically connected
to the first metal vias, wherein the pressure sensor overlaps with the acceleration sensor in a vertical plane, and the second
semiconductor substrate is between the pressure sensor and the acceleration sensor.

US Pat. No. 9,093,508

NANO FIELD-EFFECT VACUUM TUBE

SEMICONDUCTOR MANUFACTURI...

1. A nano field-effect vacuum tube, comprising:
a semiconductor substrate having an insulating layer;
a through channel configured as a vacuum channel region;
a dielectric layer surrounding the through channel;
a source region and a drain region both sealing the through channel;
a metal layer configured as a gate; and
an isolation layer isolating the metal layer from the source region and the drain region,
wherein: the through channel is formed by sequentially forming a sacrificial line and source/drain sacrificial layers connecting
with the sacrificial line; forming a trench in the insulating layer to suspend the sacrificial line; forming the dielectric
layer on a surface of the sacrificial line; forming the metal layer on the dielectric layer to fill up the trench, cover the
sacrificial line and expose the source/drain sacrificial layers; removing the source/drain sacrificial layers to expose opposite
ends of the sacrificial line and the dielectric layer; and removing the sacrificial line.

US Pat. No. 9,613,682

FINFET 6T SRAM CELL STRUCTURE

Semiconductor Manufacturi...

1. A static memory circuit comprising:
a pull-up (PU) transistor comprising a number of Fins;
a pull-down (PD) transistor comprising a number of Fins;
a pass-gate (PG) transistor associated with the PU transistor and the PD transistor; and
first and second word lines electrically insulated from each other, wherein:
the PG transistor comprises a number of Fins, and a gate electrode comprising a number of first gates and a number of second
gates each disposed on one of the Fins of the PG transistor, the first gates being connected to the first word line, and the
second gates being connected to the second word line;

during a read operation, one of the first and second word lines is asserted low, so that a ratio of the number of Fins of
the PD transistor and the number of Fins of the PG transistor is greater than or equal to a first predetermined value; and

during a write operation, one of the first and second word lines is asserted high, so that a ratio of the number of Fins of
the PG transistor and the number of Fins of the PU transistor is greater than or equal to a second predetermined value.

US Pat. No. 9,059,210

ENHANCED STRESS MEMORIZATION TECHNIQUE FOR METAL GATE TRANSISTORS

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device, comprising:
forming a dummy gate structure on a semiconductor substrate, the dummy gate structure including a sacrificial gate electrode
layer over a sacrificial gate dielectric layer;

forming sidewall spacers on both sides of the dummy gate structure;
performing a deep pre-amorphization implant;
performing an ion implantation to form heavily doped source/drain regions in the semiconductor substrate;
removing the sidewall spacers;
after removing the sidewall spacers, forming a stress material layer over the dummy gate structure;
performing an annealing process;
after the annealing process, removing the stress material layer;
forming an interlayer dielectric layer surrounding the dummy gate structure;
removing the dummy gate structure to form a groove in the interlayer dielectric layer;
forming a high-k dielectric layer and a metal gate structure in the groove;
forming contact holes that expose at least part of the heavily doped source/drain regions; and
forming a self-aligned silicide over exposed portions of the heavily doped source/drain regions.

US Pat. No. 9,371,223

MEMS DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method of forming a MEMS device, comprising:
providing a first semiconductor substrate and a second semiconductor substrate, wherein the first semiconductor substrate
includes a CMOS control circuit and the second semiconductor substrate includes a first region and a second region, the second
region being between adjacent first regions;

forming a first dielectric layer on the first semiconductor substrate;
forming a first metal interconnect structure through the first dielectric layer and on the first semiconductor substrate,
the first metal interconnect structure connected to the CMOS control circuit;

forming a sacrificial layer on a surface portion of the first dielectric layer;
forming a bonding layer on the first dielectric layer such that the sacrificial layer is within the bonding layer;
bonding the second semiconductor substrate and the bonding layer together, wherein the second region of the second semiconductor
substrate correspondingly covers the sacrificial layer;

forming a plurality of first through-holes passing through the first region of the second semiconductor substrate and through
the bond layer to expose at least a surface portion of the first metal interconnect structure;

forming an isolation layer on a sidewall surface of each first through-hole and on a top surface of the second semiconductor
substrate;

filling a conductive material in the each first through-hole to form a conductive plug on the first metal interconnect structure;
forming a second metal interconnect structure including a first end formed through the isolation layer and on the first region
of the second semiconductor substrate, and including a second end connected to an upper end of the conductive plug;

forming a plurality of second through-holes through the second region of the second semiconductor substrate and through a
top portion of the bonded layer that is on the sacrificial layer; and

removing the sacrificial layer along the plurality of second through-holes to form a cavity under the top portion of the bonded
layer to leave a movable electrode formed by the top portion of the bonded layer and a remaining portion of the second semiconductor
substrate to form the MEMS device.

US Pat. No. 9,054,193

FIN FIELD-EFFECT TRANSISTORS

SEMICONDUCTOR MANUFACTURI...

1. A fin field-effect transistor device, comprising:
a semiconductor substrate having a plurality of fins and isolation structures between adjacent fins disposed thereon;
a high-K metal gate surrounded by sidewall spacers;
a punch-through stop layer at the bottom of each of the fins;
doping sidewall spacers connecting to ends of the punch-through stop layer on sidewalls of the fins and extended into top
portions of the isolation structures near the fins;

source/drain regions in the fins at both sides of the high-K metal gate; and
a dielectric material layer.

US Pat. No. 9,324,671

METAL PILLAR BUMP PACKAGING STRCTURES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a metal pillar bump packaging structure, comprising:
providing a semiconductor substrate;
forming a metal interconnect structure and a dielectric layer exposing a portion of the metal interconnect structure on the
semiconductor substrate;

forming a photoresist layer having an opening with an undercut at a bottom of the opening to expose the portion of the metal
interconnect structure and to expose a first portion of the dielectric layer that is on the metal interconnect structure and
at the undercut;

forming a metal pillar bump structure having a pillar body and an extension part with an enlarged bottom area in the opening
and the undercut, wherein the extension part with the enlarged bottom area is formed on the exposed portion of the metal interconnect
structure and on the first portion of the dielectric layer that is on the metal interconnect structure and at the undercut;
and

forming a soldering ball on the metal pillar bump structure.

US Pat. No. 9,147,598

DOUBLE-SIDE PROCESS SILICON MOS AND PASSIVE DEVICES FOR RF FRONT-END MODULES

Semiconductor Manufacturi...

1. A method for forming integrated circuit, comprising:
providing a first semiconductor substrate having a front surface and a back surface that is opposite to the front surface;
forming one or more first trenches in the first semiconductor substrate from the front surface side, the first trenches being
characterized by a first depth;

forming one or more second trenches in the first semiconductor substrate from the front surface side, the second trenches
being characterized by a second depth which greater than the first depth;

forming a horizontal isolation layer parallel to the front surface and at a third depth from the front surface;
forming a first recessed region extending in the first semiconductor substrate from the back surface side to the horizontal
isolation layer that results in a thinned semiconductor region having a thickness substantially equal to the third depth;
and

forming a bulk dielectric layer covering the back surface side of the first semiconductor substrate.

US Pat. No. 9,397,116

SEMICONDUCTOR DEVICE HAVING A CLOSED CAVITY STRUCTURE AND METHOD OF MANUFACTURING THE SAME

Semiconductor Manufacturi...

1. A semiconductor device comprising:
a first dielectric layer;
a second dielectric layer overlapping the first dielectric layer and having a closed cavity structure;
a first transistor disposed between the first dielectric layer and the closed cavity structure;
a second transistor disposed between the first dielectric layer and the closed cavity structure;
a trench isolation structure disposed between the first transistor and the second transistor and disposed between the first
dielectric layer and the closed cavity structure; and

an embedded insulating layer disposed between the first transistor and the closed cavity structure.

US Pat. No. 9,324,712

INTEGRATED CIRCUIT AND RELATED MANUFACTURING METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing an integrated circuit, the method comprising:
forming a first transistor comprising a first active region;
forming a second transistor comprising a second active region;
forming a third transistor comprising a gate electrode, wherein the gate electrode is formed to overlap each of the first
active region and the second active region in a configuration that isolates the first transistor from the second transistor
when the third transistor is in an off state; and

providing a predetermined voltage to the gate electrode for turning off the third transistor to isolate the first transistor
from the second transistor.

US Pat. No. 9,416,004

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor fabrication method, comprising:
providing a semiconductor substrate comprising a first electrode layer therein, wherein the first electrode layer has a top
surface coplanar with a top surface of the semiconductor substrate;

forming a sacrificial layer on the semiconductor substrate and the first electrode layer;
forming a first mask layer on the sacrificial layer, wherein the first mask layer is made of a conductive material;
etching the first mask layer and the sacrificial layer, by a first etching process, using a patterned layer as an etch mask
to etch the first mask layer until a surface of the sacrificial layer is exposed, and a second etching process following the
first etching process, using the first mask layer as an etch mask to etch the sacrificial layer, until a surface of the first
electrode layer is exposed to form openings through the first mask layer and the sacrificial layer;

performing a cleaning process to remove etch byproducts adhered to a surface of the first mask layer and adhered to sidewalls
and bottom surfaces of the openings; and

forming conductive plugs in the openings after the cleaning process.

US Pat. No. 9,377,582

SUBSTRATE, RELATED DEVICE, AND RELATED MANUFACTURING METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a substrate, the method comprising:
processing a substrate material member to form a first remaining portion of the substrate material member, wherein the first
remaining portion of the substrate material member has a first cavity, wherein a flat sidewall of the first cavity is oriented
at a first angle with respect to at least one of a horizontal plane, a flat bottom surface of the first cavity, and a flat
bottom side of the first remaining portion of the substrate material member;

providing a sacrificial material member inside the first cavity; and
processing the sacrificial material member when processing the first remaining portion of the substrate material member to
remove the sacrificial material member and to form a second remaining portion of the substrate material member, wherein the
second remaining portion of the substrate material member has a second cavity, wherein a flat sidewall of the second cavity
is resulted from removal of at least the flat sidewall of the first cavity and is oriented at a second angle with respect
to at least one of the horizontal plane, a flat bottom surface of the second cavity, and a flat bottom side of the second
remaining portion of the substrate material member, and wherein the second angle is smaller than the first angle.

US Pat. No. 9,343,435

SEMICONDUCTOR DEVICE AND RELATED MANUFACTURING METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a first dielectric layer and a first set of conductive pads on a first substrate, each conductive pad of the first
set of conductive pads being positioned between portions of the first dielectric layer;

providing a first insulating material layer to cover the first dielectric layer and the first set of conductive pads; and
removing portions of the first insulating material layer to form a first insulating layer, opening of the first insulating
layer exposing the first set of conductive pads.

US Pat. No. 9,236,296

FABRICATION METHOD FOR MIM CAPACITOR

SEMICONDUCTOR MANUFACTURI...

1. A method for forming an MIM capacitor, comprising:
forming a dielectric layer over a substrate containing a conductive layer;
forming a groove through the dielectric layer to expose the conductive layer in the substrate;
forming a first metal layer on a sidewall surface and a bottom surface of the groove and on a top surface of the dielectric
layer;

forming a sacrificial layer in the groove to expose a portion of the first metal layer that is on the top surface of the dielectric
layer and on a top portion of the sidewall surface of the groove;

removing the exposed portion of the first metal layer to leave a remaining portion thereof in the groove as a first electrode
plate of the MIM capacitor;

removing the sacrificial layer from the groove to leave the first electrode plate remaining in the groove;
forming a dielectric material layer on the first electrode plate, on the top portion of the sidewall surface of the groove,
and on the top surface of the dielectric layer;

forming a second metal layer on the dielectric material layer;
forming a third metal layer on the second metal layer to fill the groove in the dielectric layer; and
polishing the third metal layer, the second metal layer, and the dielectric material layer, using the top surface of the dielectric
layer as a stop layer to expose a tip surface area of the dielectric material layer and to expose a tip surface area of the
second metal layer; and

forming a diffusion barrier layer on the third metal layer in the groove, wherein:
the diffusion barrier layer is made of a material including one or more selected from the group consisting of CoWP, CuSiAl,
CuAl, CuAlN, and CuMn, and

the diffusion barrier layer is patterned so as to cover the tip surface area of the second metal layer and to expose a main
portion of the tip surface area of the dielectric material layer.

US Pat. No. 9,293,472

RF SOI SWITCH WITH BACKSIDE CAVITY AND THE METHOD TO FORM IT

Semiconductor Manufacturi...

1. An integrated circuit comprising:
a compound semiconductor substrate having a first semiconductor substrate, an insulating layer on the first semiconductor
substrate, and a second semiconductor substrate on the insulating layer;

a transistor disposed on and in the second semiconductor substrate and having a bottom portion insulated by the insulating
layer;

a plurality of shallow trench isolations disposed on opposite sides of the transistor,
a cavity disposed below the bottom portion of the transistor; and
a plurality of isolation plugs disposed on opposite sides of the cavity;
wherein the cavity is disposed on an upper portion of the first semiconductor substrate and comprises a top surface delineated
by the insulating layer.

US Pat. No. 9,306,587

OSCILLATOR CIRCUIT AND CONFIGURATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. An oscillator circuit, comprising:
a signal selecting unit, configured to select a reference signal or a frequency-divided signal as an input signal;
a control voltage generating unit, configured to generate a control voltage based on the input signal, wherein the control
voltage has a value associated with a frequency of the input signal;

a reference voltage generating unit, configured to generate a reference voltage, wherein the reference voltage has a value
equal to the value of the control voltage when the input signal is the reference signal;

an output adjusting unit, configured to generate an output signal based on the control voltage and the reference voltage,
wherein the output signal has a frequency associated with a voltage difference between the reference voltage and the control
voltage, and the frequency of the output signal maintains unchanged if the voltage difference is zero; and

a frequency-dividing unit, configured to divide the frequency of the output signal and generate the frequency-divided signal.

US Pat. No. 9,298,099

EXPOSURE APPARATUS AND EXPOSURE METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. An exposure apparatus, comprising:
a base;
a wafer stage group having a plurality of wafer stages on the base for holding wafers and successively moving from a first
position to a second position of the base cyclically;

an alignment detection unit above the first position for detecting wafer stage fiducials on the wafer stage at the first position
and alignment marks on a wafer on the wafer stage at the first position to align the wafer;

a reticle stage on the second position for loading a cylindrical reticle and causing the cylindrical reticle to rotate around
a center axis of the reticle stage; and

an optical projection unit between the reticle stage and the base for projecting light passing through the cylindrical reticle
on exposure regions of a wafer on the wafer stage,

wherein a control system is configured to control the wafer stage group such that:
when the wafer stage moves from the first position to the second position, the wafer stage performs a unidirectional scan
along an scanning direction, the cylindrical reticle rotates around the center axis of the reticle stage, the light passing
through the cylindrical reticle is projected onto the wafer on the wafer stage, and a column of exposure regions on the wafer
along the scanning direction are exposed, and

a first column of exposure regions on a first wafer and a corresponding column of exposure regions on a second wafer are each
exposed prior to exposing a second column of the exposure regions on the first wafer.

US Pat. No. 9,293,469

FLASH MEMORY AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. An flash memory fabrication method, comprising:
providing a substrate having a plurality of floating gate structures separated by trenches, including at least a source trench
and a drain trench, wherein source regions are formed in the substrate at bottom of the source trench and drain regions are
formed in the substrate at bottom of the drain trench;

forming a metal film on the substrate and on the floating gate structures;
performing a thermal annealing process on the metal film to diffuse metal ions of the metal film into the substrate to form
a first silicide layer on the source regions and a second silicide layer on the drain regions;

removing portions of the metal film to form a metal layer on the bottom and lower sidewalls of the source trench and contacting
with the first silicide layer;

forming a dielectric layer on the substrate and the floating gate structures, the dielectric layer covering the source trench
and the drain trench; and

forming a first conducting structure and one or more second conducting structures in the dielectric layer, wherein the first
conducting structure is on a surface of the metal layer in the source trench, the second conducting structures are on a surface
of the second silicide layer, and adjacent first conducting structure and second conducting structure have a predetermined
distance.

US Pat. No. 9,287,182

FABRICATION METHOD FOR SEMICONDUCTOR DEVICE WITH THREE OR FOUR-TERMINAL-FINFET

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
providing a semiconductor substrate including a silicon-on-insulator (SOI) substrate including a top silicon layer;
forming a first fin and a second fin on the semiconductor substrate by:
dividing the top silicon layer into a first top silicon layer for forming the first fin and a second top silicon layer for
forming the second fin, according to a pre-defined position for forming each of the first fin and the second fin,

removing a height portion of the second top silicon layer to provide a remaining second top silicon layer; and
patterning the first top silicon layer and the remaining second top silicon layer to form the first fin and the second fin,
wherein the first fin has a top surface higher than the second fin from the semiconductor substrate;

forming a first gate dielectric layer across the first fin, a first gate on the first gate dielectric layer, a second gate
dielectric layer across the second fin, and a second gate on the second gate dielectric layer;

forming an interlayer dielectric layer to cover the first gate, the second gate, and the semiconductor substrate; and
removing a first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate
dielectric layer, over the top surface of the first fin, and a second portion of the interlayer dielectric layer over the
second fin to expose the second gate over the second fin, wherein the second gate remains intact while removing, according
to a height difference between the first fin and the second fin.

US Pat. No. 9,299,788

MULTI-GATE VDMOS TRANSISTOR

SEMICONDUCTOR MANUFACTURI...

1. A multi-gate vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor, comprising:
a substrate having a first surface and a second surface opposite to the first surface;
a drift layer on the first surface of the substrate;
an epitaxial layer on the drift layer;
a plurality of trenches, each trench of the plurality of trenches passing through the epitaxial layer and a thickness portion
of the drift layer;

a plurality of gate structures, each gate structure of the plurality of gate structures substantially entirely filling the
each trench, an arrangement of the plurality of gate structures has a polygonal shape or a concentric circular shape by connecting
centers of the plurality of gate structures;

a plurality of doped regions in the epitaxial layer having a conductivity type opposite to the epitaxial layer, each doped
region of the plurality of doped regions surrounding a top portion of a sidewall of the each gate structure of the plurality
of gate structures, such that each gate structure of two adjacent gate structures has a first half of the top portion of the
sidewall surrounded by each doped region of the plurality of doped regions, and a second half of the top portion of the sidewall
exposed to the epitaxial layer, and two doped regions of the plurality of doped regions are located between the two adjacent
gate structures in a cross section vertical to the first surface or the second surface of the substrate;

a source metal layer on a planar surface of the epitaxial layer, the source metal layer electrically connecting the plurality
of doped regions; and

a drain metal layer on the second surface of the substrate.

US Pat. No. 9,257,287

LASER ANNEALING DEVICE AND METHOD

SEMICONDUCTOR MANUFACTURI...

1. A laser annealing device, comprising:
a pump laser source array including a plurality of pump laser sources, the pump laser sources each emitting a pump laser beam;
an annealing laser source for emitting annealing laser; and
a tunable mask for transmitting at least part of the annealing laser after being irradiated by the pump laser beam,
wherein the tunable mask rotates at a predetermined speed, and
wherein the tunable mask has a band gap Eg, the annealing laser has an optical band gap Eb larger than the Eg, and the pump
laser beam has an optical band gap Ea larger than the band gap Eb.

US Pat. No. 9,287,397

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING SAME

SEMICONDUCTOR MANUFACTURI...

1. A method of fabricating a semiconductor device, comprising:
forming a plurality of gate electrodes at a predetermined interval on a surface of a semiconductor substrate;
forming spacers on sidewalls of the gate electrodes;
depositing an interconnection layer conformally on the surface of the semiconductor substrate over the gate electrodes and
the spacers;

selectively etching the interconnection layer, wherein at least a portion of the interconnection layer that is formed on the
surface of the semiconductor substrate and sidewalls of the spacers and located between adjacent gate electrodes, remains
after the selective etch, and wherein a portion of the gate electrodes is exposed to form an exposed portion of the gate electrodes
after the selective etch of the interconnection layer;

forming a dielectric layer on the semiconductor substrate, the sidewalls of the spacers, and the exposed portion of the gate
electrodes; and

forming an electrical contact on the etched interconnection layer located between the adjacent gate electrodes,
wherein the electrical contact is selectively formed on a portion of the etched interconnection layer located between adjacent
laterally opposite spacers.

US Pat. No. 9,256,703

METHOD OF DETECTING A SCATTERING BAR BY SIMULATION

Semiconductor Manufacturi...

1. A method of testing a scattering bar by simulation, the method comprising:
preparing an OPC mask model including a main pattern and a scattering bar pattern;
forming an image plane of the OPC mask model located at a middle portion of a photoresist layer;
forming a scattering bar OPC model by refocusing the image plane of the OPC mask model located at the middle portion of the
photoresist layer to a top portion of the photoresist layer;

simulating an exposure of the scattering bar OPC model with an exposure dose of about 15% over a normal dose;
simulating a profile of the exposed scattering bar OPC model;
testing the simulated profile;
conducting a real wafer exposure of the OPC mask model to evaluate at least one simulation result; and after testing the simulated
profile:

while simulating an exposure of the scattering bar OPC model, establishing a correlation between the simulated 15% overexposure
dose of the scattering bar pattern and a real exposure dose of a wafer of about 10% over the nominal dose.

US Pat. No. 9,305,833

SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate;
forming a conductive layer in a surface of the substrate;
forming a dielectric layer on the surface of the substrate covering the conductive layer;
forming an opening exposing a portion of the conductive layer in the dielectric layer;
forming a passivation layer using a passivation solution to react with a surface of the portion of the conductive layer on
the bottom of the opening to convert the surface of the conductive layer into a metal complex layer;

cleaning inner surface of the opening using a cleaning solution not reacting with the passivation layer;
after cleaning the opening, removing the passivation layer; and
forming a metal layer connecting with the conductive layer in the opening.

US Pat. No. 9,293,430

SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME

Semiconductor Manufacturi...

1. A chip comprising:
a substrate;
a dielectric layer disposed on the substrate, wherein the dielectric layer includes a first dielectric region and a second
dielectric region surrounding an outer periphery of the first dielectric region, and wherein a top surface of the first dielectric
region is disposed below a top surface of the second dielectric region; and

a metal pad disposed in a through-hole in the first dielectric region and contacting a portion of the substrate.

US Pat. No. 9,312,355

STRIPE STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating stripe structures, comprising:
providing a substrate;
forming a to-be-etched layer on the substrate;
forming a first stripe made of a hard mask pattern on the to-be-etched layer and exposing the to-be-etched layer;
forming a photoresist pattern on the exposed to-be-etched layer and on the first stripe made of the hard mask pattern, the
photoresist pattern including a stripe opening formed on the first stripe and perpendicular to a length direction of the first
stripe;

forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening;
etching through the first stripe made of the hard mask pattern using the photoresist pattern having the polymer layer as an
etching mask to form second stripes made of the hard mask pattern; and

forming the stripe structures by etching the to-be-etched layer using the second stripes made of the hard mask pattern as
an etching mask to remove a portion of the to-be-etched layer to expose a surface portion of the substrate.

US Pat. No. 9,305,823

SEMICONDUCTOR DEVICE INCLUDING STI STRUCTURE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method of forming a transistor device, comprising:
providing a mask layer on a semiconductor substrate;
patterning the mask layer to form an opening in the mask layer to expose a surface portion of the semiconductor substrate;
forming a trench in the semiconductor substrate by etching along the opening;
forming a first dielectric layer in the trench, wherein the first dielectric layer has a top surface lower than a top surface
of the semiconductor substrate to provide an uncovered sidewall surface of the trench in the semiconductor substrate;

forming an epitaxial layer on the uncovered sidewall surface of the trench in the semiconductor substrate and on the first
dielectric layer, wherein the epitaxial layer includes a spacing to expose a surface portion of the first dielectric layer;
and

forming a second dielectric layer on the exposed surface portion of the first dielectric layer to fill the spacing in the
epitaxial layer, wherein:

the first and second dielectric layers form an isolation structure for the transistor device, and
a channel width of the transistor device is a total width including a width of a portion of the semiconductor substrate located
between neighboring isolation structures plus a total width of the epitaxial layer on both sides of the isolation structure.

US Pat. No. 9,269,772

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:
a substrate;
a fin-shaped buffer layer over the substrate;
a Quantum Well (QW) material layer on the fin-shaped buffer layer, the QW material layer being suitable for forming an electron
gas therein;

a barrier material layer on the QW material layer;
a cap layer on the barrier material layer; and
a gate structure,
wherein the QW material layer is suitable for forming an electron gas therein, and
wherein the gate structure comprises a gate insulating layer on at least a portion of the cap layer, a gate on the gate insulating
layer, and a spacer for the gate.

US Pat. No. 9,263,273

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:
preparing a semiconductor substrate that includes a first region for forming an isolated LDNMOS device, a second region for
forming a non-isolated LDNMOS device, and a third region for forming an LDPMOS device;

providing a first mask that overlaps the semiconductor substrate;
etching, using the first mask, the semiconductor substrate to form a first trench in the first region, a second trench in
the second region, and a third trench in the third region;

providing a second mask that overlaps the semiconductor substrate and includes three openings respectively corresponding to
the first region, the second region, and the third region;

performing first ion implantation through the three openings to form a first P-doped region in the first region, a second
P-doped region in the second region, and a third P-doped region in the third region;

performing second ion implantation through the three openings to form a first N-doped region in the first region, a second
N-doped region in the second region, and a third N-doped region in the third region;

performing third ion implantation through the three openings to form a fourth N-doped region in the first region, a fifth
N-doped region in the second region, and a sixth N-doped region in the third region; and

forming a first isolation member in the first trench, a second isolation member in the second trench, and a third isolation
member in the third trench.

US Pat. No. 9,323,163

CYLINDRICAL RETICLE SYSTEM, EXPOSURE APPARATUS AND EXPOSURE METHOD

SEMICONDUCTOR MANUFACTURI...

1. A cylindrical reticle system, comprising:
a center shaft fixed a one side of a base;
a first bearing fixed at the end of the center shaft near to the base;
a second bearing fixed at the other end of the center shaft far from the base; and
a cylindrical reticle,
wherein:
the first bearing and the second bearing have a bearing outer ring, a bearing inner ring, and rolling elements between the
bearing outer ring and the bearing inner ring, respectively;

the first bearing and the second bearing further include: first gripping holders for generating a pressure on an inner surface
of non-imaging regions of the cylindrical reticle to harness the cylindrical reticle on the bearing outer rings tightly;

the bearing inner rings of the first bearing and the second bearing are fixed on the center shaft;
the cylindrical reticle is a hollow cylinder; and
the cylindrical reticle harnesses on the bearing outer rings of the first bearing and the second bearing.

US Pat. No. 9,396,993

DEVICE HAVING REDUCED PAD PEELING DURING TENSILE STRESS TESTING AND A METHOD OF FORMING THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
forming a first aluminum pad layer on a metal layer;
forming an adhesion layer on the first aluminum pad layer;
etching the adhesion layer so as to form a patterned adhesion layer;
forming a second aluminum pad layer on the first aluminum pad layer and the patterned adhesion layer; and
reducing a width of the first aluminum pad layer after a plurality of spaced portions of the patterned adhesion layer has
been formed, wherein the first aluminum pad layer is wider than the patterned adhesion layer after the reducing.

US Pat. No. 9,310,643

METHOD AND STRUCTURE FOR FABRICATING SMOOTH MIRRORS FOR LIQUID CRYSTAL ON SILICON DEVICES

Semiconductor Manufacturi...

1. A liquid crystal on silicon (LCOS) device, the device comprising:
a semiconductor substrate;
a metal-oxide semiconductor (MOS) device layer overlying the semiconductor substrate, the MOS device layer having a plurality
of MOS devices;

a planarized interlayer dielectric layer overlying the MOS device layer;
a plurality of recessed regions formed within a portion of the planarized interlayer dielectric layer;
an aluminum layer filling each of the recessed regions to form a plurality of respective electrode plates corresponding to
each of the recessed regions, the aluminum layer having a smooth surface free from any dimple, each of the electrode plates
being coupled to each one of the MOS devices;

a protective layer of only an aluminum oxide layer directly overlying a surface of each of the plurality of electrode plates,
the protective layer formed by exposing the electrode plates to an oxidizing fluid;

a liquid crystal film directly overlying the protective layer; and
a mirror finish formed on the surface of each of the electrode plates for reflecting light by a chemical mechanical polishing
process, the mirror finish being substantially free from dishes and scratches.

US Pat. No. 9,299,622

ON-CHIP PLASMA CHARGING SENSOR

Semiconductor Manufacturi...

1. A method for making a device for monitoring charging effects, the method comprising:
providing a semiconductor substrate having a surface region;
forming a gate dielectric layer overlying a first portion and a second portion of the surface region of the semiconductor
substrate;

performing an implant to adjust a threshold voltage in the second portion of the surface of the semiconductor substrate;
forming a polysilicon material overlying the first and second portions;
patterning the polysilicon material to form a first gate and a second gate, the first gate being over the first portion and
the second gate being over the second portion;

forming first, second, and third doped regions in the semiconductor substrate using the first and second gates as a protective
mask;

wherein the second doped region has the first gate on one side and the second gate on the other side;
forming an interlayer dielectric layer over the second gate; and
forming a conductive layer over the interlayer dielectric layer, the conductive layer being electrically coupled to the second
gate and configured to collect charges;

wherein the second doped region is interposed between the first and the third doped regions, the second doped region is coupled
to the first doped region through the first portion of the substrate, and the second doped region is coupled to the third
doped region through the second portion of the substrate; and

wherein the second doped region has a positive electric charge on a side to the first gate and a negative electric charge
on an opposite side.

US Pat. No. 9,293,550

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:
a gate insulating layer selectively formed on an inner wall of a silicon substrate recess;
a work function material layer directly formed on the gate insulating layer so as to apply a tensile stress or a compressive
stress to a channel of a MOS field-effect transistor;

a gate metal formed on the work function material layer; and
a barrier layer formed between the work function material layer and the gate metal.

US Pat. No. 9,293,354

APPARATUS AND METHOD FOR CALIBRATING LITHOGRAPHY PROCESS

Semiconductor Manufacturi...

1. A method for calibrating a lithography tool, the method comprising:
providing a calibration wafer bearing a pattern comprising a plurality of first marks delineating a border of an edge bead
removal (EBR) region and a plurality of second marks delineating a border of a wafer ID region;

forming a photoresist material on the calibration wafer to cover the pattern;
removing edge beads disposed in an edge portion of the photoresist material to expose a portion of the first marks;
inspecting the calibration wafer to determine alignment of a remaining portion of the photoresist material with the exposed
portion of the first marks; and

inspecting the wafer ID region to determine alignment of the remaining portion of the photoresist material with the second
marks.

US Pat. No. 9,287,375

TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD

SEMICONDUCTOR MANUFACTURI...

1. A transistor device comprising:
a substrate that has a first recess and a first substrate surface, wherein the first recess is recessed with respect to the
first substrate surface;

a source that overlaps the substrate;
a drain overlaps the substrate; and
a gate structure that has a first gate structure portion and a second gate structure portion, wherein the first gate structure
portion is positioned inside the first recess, wherein the second gate structure portion is connected to the first gate structure
and is positioned outside the first recess, wherein a portion of the source and a portion of the drain extend underneath the
first gate structure portion.

US Pat. No. 9,269,625

METHOD AND SYSTEM FOR CMOS IMAGE SENSING DEVICE

Semiconductor Manufacturi...

1. A method for manufacturing a CMOS image sensor, the CMOS image sensor being characterized by reduced blooming, the method
comprising:
providing a substrate material, the substrate material being characterized by a first dimension and a second dimension, the
first and the second dimensions being determined by a desired size of the image sensor;

defining an active region on the substrate material, the active region being characterized by a third dimension and a fourth
dimension determined by a resolution of the image sensor, the active region extending from an upper surface of the substrate
material into a depth of the substrate material;

defining a non-active region on the substrate material, the non-active region being different from the active region, the
non-active region being characterized by a fifth dimension and a sixth dimension determined for preventing unwanted electron
diffusion, the non-active region including a silicon material, the non-active region extending from the upper surface of the
substrate material into the depth of the substrate material;

forming an n-type region within the active region, a depletion region being formed below the n-type region;
forming a gate region within the active region;
forming a doped region, the doped region extending from an upper region, the substrate material into the depth into the substrate
material within the non-active region, the doped region being characterized by including at least one substance at a predetermined
range of concentration, the doped region being adjacent to the active region and separating at least a portion of the non-active
region from the active region; and

forming a plurality of voids as an electron diffusion barrier region within the doped region in a direction perpendicular
to an upper surface of the substrate material and extending into the depth into the substrate material, the plurality of voids
extending substantially more in the direction perpendicular to the upper surface than in a direction parallel to the upper
surface,

wherein the concentration diffusing electrons is lower in the potion of the non-active region, which extends from the upper
surface into the depth of the substrate material on one side of the electron diffusion barrier region, than the electron concentration
in the active region on an opposite side of the electron diffusion barrier region.

US Pat. No. 9,184,291

FINFET DEVICE AND METHOD OF FORMING FIN IN THE SAME

Semiconductor Manufacturi...

1. A method of manufacturing a fin for a FinFET device, the method comprising:
providing a semiconductor substrate;
forming a plurality of implanted regions in the semiconductor substrate; and
epitaxially forming the fin between two adjacent implanted regions, wherein the fin has a <501> surface orientation.

US Pat. No. 9,224,812

SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES

Semiconductor Manufacturi...

1. A method for fabricating a semiconductor device, comprising:
providing a first insulation layer on a wafer substrate;
forming an elongated semiconductor region overlying the first insulation layer along a first direction, the elongated semiconductor
region including a first end section, a middle section, and a second end section;

forming an undercut structure of the first insulation layer beneath the elongated semiconductor region;
removing the undercut structure selectively beneath the middle section to form a cavity having a first length and a first
height;

forming a channel region by shaping the middle section above the cavity to a substantially cylindrical shape, the channel
region having a channel length substantially equal to the first length;

forming a second insulation layer around the cylindrical channel region, the second insulation layer having a thickness substantially
less than the first height of the cavity;

depositing a conductive layer on the first insulation layer to at least cover the elongated semiconductor region including
the cylindrical channel region surrounded by the second insulation layer;

forming a gate region from the conductive layer along a second direction surrounding the cylindrical channel region including
the cavity beneath the channel region, the second direction being substantially perpendicular to the first direction;

forming a source region in the first end section; and
forming a drain region in the second end section.

US Pat. No. 9,287,387

STATIC MEMORY CELL AND FORMATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of forming a static memory cell, comprising:
providing a semiconductor substrate including a first region,
forming a first fin part on the semiconductor substrate in the first region;
forming an isolation layer on the semiconductor substrate, having a top surface lower than a top surface of the first fin
part to cover a lower portion of a sidewall surface of the first fin part;

forming a first dummy gate structure across a length of the first fin part;
forming a first sidewall spacer on the sidewall surface of the first dummy gate structure and on a surface portion of the
isolation layer;

forming a dielectric layer on the isolation layer and having a top surface coplanar with a top surface of the first dummy
gate structure;

forming a mask layer on the dielectric layer and on the top surface of the first dummy gate structure, wherein the mask layer
contains a first opening to expose the top surface of the first dummy gate structure;

removing the first dummy gate structure through the first opening to form a first trench exposing a portion of a surface of
the first fin part and the sidewall spacer located on both sides of the first fin part;

removing a portion of a thickness of the isolation layer at the bottom of the first trench through the first opening to form
a second trench exposing a portion of sidewalls of the first fin part beneath the top surface of the isolation layer; and

forming a first gate structure by filling up the first trench and the second trench in the first region.

US Pat. No. 9,263,321

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a semiconductor device, comprising:
forming, on a substrate, an active region and at least one groove isolation region adjoining the active region;
forming a gate structure on a first portion of the active region;
forming at least one local interconnection layer on a portion of the substrate, wherein the at least one local interconnection
layer is formed of one single material and is directly contacting a second portion of the active region and a portion of the
groove isolation region adjoining the active region, and does not extending over the gate structure,

wherein the local interconnection layer has a first portion directly contacting the second portion of the active region and
a second portion extending from the first portion along a side wall of the gate structure, height of the second portion being
higher than a top surface of the first portion and lower than a top surface of the gate structure, and

wherein forming the at least one local interconnection layer on the portion of the substrate comprises:
forming a local interconnection material layer conformally over the groove isolation region, the active region, and the gate
structure;

forming a patterned hard mask on the local interconnection material layer, the patterned hard mask covering second portions
of the active regions disposed on both sides of the gate structure and opening a top of the gate structure; and

etching the local interconnection material layer using the patterned hard mask as an etch mask, so as to form the local interconnection
layer.

US Pat. No. 9,184,170

METHOD FOR FINFET SRAM RATIO TUNING

Semiconductor Manufacturi...

1. A method of forming a semiconductor device, the method comprising:
providing a front-end device having a plurality of memory cells, each memory cell including at least two pull-up transistors,
at least two pull-down transistors, and at least two pass-gate transistors, the pull-up transistors, the pull-down transistors,
and the two pass-gate transistors each having a gate and gate sidewalls;

forming a mask over the at least two pull-up transistors;
performing a first lightly doped source and drain ion implantation at a first tilted angle into the at least two pull-down
transistors and the at least two pass-gate transistors; and

performing a second lightly doped source and drain ion implantation at a second tilted angle into a portion of the at least
two pull-down transistors and the at least two pass-gate transistors;

wherein the first tilt angle and the second tilt angle are angles relative to a direction perpendicular to a surface of the
front-end device, and the first tilt angle is smaller than the second tilt angle.

US Pat. No. 9,111,643

METHOD AND APPARATUS FOR REPAIRING DEFECTIVE MEMORY CELLS

Semiconductor Manufacturi...

1. A method for repairing defective memory cells of a memory device, the method comprising:
receiving an access command having an access address and an access operation, the access address including a row address and
a column address;

determining whether the row address and the column address of the access address are the same as a pre-recorded row address
and column address of a defective memory cell;

if the row address and the column address of the access address are the same as the respective row and column addresses of
the defective memory cell, finding a redundant memory cell associated with the defective memory cell in response to the access
address; and

executing the access operation using the redundant memory cell.

US Pat. No. 9,105,477

ESD PROTECTION STRUCTURE AND ESD PROTECTION CIRCUIT

SEMICONDUCTOR MANUFACTURI...

16. An electrostatic discharge (ESD) protection circuit comprising:
a PMOS transistor, having a source region and a gate connected to a power supply terminal, and a drain region connected to
an I/O interface terminal;

an NMOS transistor, having a drain region connected to the I/O interface terminal, and a gate and a source region connected
to a ground terminal;

a first PNP-type parasitic transistor, having an emitter region connected to the power supply terminal, a collector region
connected to the ground terminal, and a base region connected to an external trigger-voltage adjustment circuit, wherein the
external trigger-voltage adjustment circuit pulls down an electric potential of the base region of the first PNP-type parasitic
transistor when the power supply terminal generates an instantaneous electric potential difference;

a second PNP-type parasitic transistor, having an emitter region connected to the I/O interface terminal, a collector region
connected to the ground terminal, and a base region connected to the external trigger-voltage adjustment circuit, wherein
the external trigger-voltage adjustment circuit pulls down an electric potential of the base region of the second PNP-type
parasitic transistor when the power supply terminal generates an instantaneous electric potential difference; and

a first NPN-type parasitic transistor, having an emitter region connected to the ground terminal, a collector region connected
to the I/O interface terminal, and a base region connected to the external trigger-voltage adjustment circuit, wherein the
external trigger-voltage adjustment circuit pulls up an electric potential of the base region of the first NPN-type parasitic
transistor when the power supply terminal generates an instantaneous electric potential difference.

US Pat. No. 9,290,378

MEMS CAPPING METHOD

Semiconductor Manufacturi...

1. A method for fabricating a MEMS device, the method comprising:
providing a substrate having a front surface and a back surface;
forming a protruding engagement member on the front surface of the substrate, the protruding engagement member having an inner
periphery defining a groove;

forming a first trench having a first depth along an outer periphery of the protruding engagement member;
forming a patterned mask layer on the protruding engagement member covering the engagement member including the groove and
exposing a portion of the first trench;

etching the exposed portion of the first trench using the patterned mask layer as a mask to form a second trench having a
second depth;

removing the patterned mask layer; and
bonding the substrate with a MEMS substrate to form the MEMS device.

US Pat. No. 9,147,596

METHOD FOR FORMING SHALLOW TRENCH ISOLATION

Semiconductor Manufacturi...

1. A method of forming shallow trench isolation (STI), comprising:
forming a hard mask layer on a semiconductor substrate;
patterning the hard mask layer to form openings for a plurality of isolation regions;
forming a plurality of shallow trench isolation structures in the semiconductor substrate;
removing a top portion of said hard mask layer, causing top portions of the plurality of shallow trench isolation structures
to protrude above a remaining bottom portion of the hard mask layer;

performing oxygen plasma treatment to the protruding top portions of the plurality of shallow trench isolation structure;
performing an annealing process to form a densified oxide layer on top surfaces and sidewalls of the protruding portions of
the plurality of shallow trench isolation structures; and

removing the remaining bottom portion of the hard mask layer after the annealing process has been performed.

US Pat. No. 9,105,079

METHOD AND SYSTEM FOR OBTAINING OPTICAL PROXIMITY CORRECTION MODEL CALIBRATION DATA

SEMICONDUCTOR MANUFACTURI...

1. A method for obtaining calibration data for use in calibrating an optical proximity correction model, the method comprising:
capturing, using an image-capturing device, an image for each portion of a plurality of portions of a wafer to obtain captured
images, the captured images including a first image and a second image, the first image including an image of a first portion
of the wafer, the second image including an image of a second portion of the wafer, the first portion of the wafer immediately
neighboring the second portion of the wafer;

assembling, using a processor that is connected to the image-capturing device, at least portions of the captured images to
form an assembled image;

mapping layout data of the wafer with the assembled image;
selecting portions of the assembled image based on the layout data of the wafer; and
obtaining data associated with the portions of the assembled image as the calibration data.

US Pat. No. 9,349,729

SEMICONDUCTOR STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:
providing a semiconductor substrate having a first region and a second region;
forming a first dummy gate on a surface of the semiconductor substrate in the first region and a device layer on the surface
of the semiconductor substrate in the second region;

forming a dielectric layer on the first dummy gate and the device layer and with a top surface leveling the top surfaces of
the first dummy gate and the device layer on the semiconductor substrate;

removing the first dummy gate to form a first trench;
forming a first metal layer on the first trench to fill the first trench and on the surface of the dielectric layer and the
surface of the device layer; and

performing a first planarization process on the first metal layer using a first polishing slurry having a first protective
agent to form a first gate electrode in the first trench and a protective layer on the device layer preventing the device
layer being damaged during the first planarization process.

US Pat. No. 9,337,043

METAL GATE TRANSISTOR AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a metal gate transistor, comprising:
providing a substrate having a top surface and a back surface;
forming a dummy gate on the top surface of the substrate;
forming a first interlayer dielectric layer on the top surface of substrate;
planarizing the first interlayer dielectric layer to expose the dummy gate;
removing the dummy gate to form a trench;
forming a metal gate stack to cover the first interlayer dielectric layer and to fill the trench;
planarizing the metal gate stack to remove a portion of the metal gate stack from the first interlayer dielectric layer to
form a metal gate electrode in the trench and to leave a remaining edge portion of the metal gate stack over an annular region
of the substrate; and

performing an edge cleaning process on the top surface of the substrate to remove the remaining edge portion of the metal
gate stack from the annular region of the substrate, wherein the performing of the edge cleaning process includes:

flipping and fixing the substrate such that the back surface of the substrate faces upward and the top surface of the substrate
faces downward; and

spraying a cleaning fluid onto the back surface of the substrate, wherein a part of the sprayed cleaning fluid flows to the
annular region of the substrate on the top surface of the substrate.

US Pat. No. 9,299,619

METHOD FOR MANUFACTURING CMOS DEVICE WITH HIGH-K DIELECTRIC LAYERS AND HIGH-K CAP LAYERS FORMED IN DIFFERENT STEPS

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:
preparing a semiconductor substrate that includes a PMOS region for forming a PMOS structure and includes an NMOS region for
forming an NMOS structure;

forming an interlayer dielectric layer on the semiconductor substrate;
forming a first gate trench in the interlayer dielectric layer and on the PMOS region;
sequentially forming a first high-k dielectric layer and a first high-k cap layer that cover a bottom and sides of the first
gate trench;

forming a second gate trench in the interlayer dielectric layer and on the NMOS region;
sequentially forming a second high-k dielectric layer and a second high-k cap layer that cover a bottom and sides of the second
gate trench;

removing a portion of the first high-k dielectric layer and a portion of the first high-k cap layer, wherein the portion of
the first high-k dielectric layer and the portion of the first high-k cap layer are positioned inside the first gate trench
and overlap a side of the first gate trench, and wherein the side of the first gate trench is not parallel to the top surface
of the semiconductor substrate; and

removing a portion of the second high-k dielectric layer and a portion of the second high-k cap layer, wherein the portion
of the second high-k dielectric layer and the portion of the second high-k cap layer are positioned inside the second gate
trench and overlap a side of the second gate trench, and wherein the side of the second gate trench is not parallel to the
to surface of the semiconductor substrate.

US Pat. No. 9,257,538

FIN-TYPE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a fin-type field effect transistor, the method comprising:
providing a substrate having a fin;
forming a gate structure on the fin;
forming source and drain regions adjacent to the gate structure;
etching a portion of the source and drain regions to form a trench;
forming a first epitaxial layer in the trench, the first epitaxial layer being a carbon-doped silicon layer having a carbon
concentration of less than 4 percent by weight;

forming a second epitaxial layer on the first epitaxial layer, the second epitaxial layer being a barrier metal layer; and
forming a third epitaxial layer on the second epitaxial layer, the third epitaxial layer being a metal layer.

US Pat. No. 9,425,068

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Semiconductor Manufacturi...

1. A method for manufacturing semiconductor device, the method comprising:
performing an etching process to remove a sacrificial layer from a first composite structure, wherein the first composite
structure includes a first substrate structure;

performing a heat treatment to release a gas from the first composite structure;
performing a cleaning process to remove an oxide layer from the first composite structure; and
combining the first composite structure with a second composite structure that includes a second substrate structure and an
electronic component positioned on the second substrate structure, such that the first substrate structure is combined with
the second substrate structure to form an enclosure structure that encloses the electronic component.

US Pat. No. 9,270,283

FREQUENCY GENERATION DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A frequency generation device comprising:
a voltage generation unit configured to generate a first voltage based on a reference frequency and configured to generate
a feedback voltage based on a first feedback frequency;

a reference voltage source configured to provide a reference voltage that is equal to the first voltage, wherein the reference
voltage source comprises a resistive voltage divider unit and a bandgap voltage source; and

a feedback unit connected to the voltage generation unit and the reference voltage source, wherein a first input terminal
of the feedback unit is configured to receive the reference voltage from the reference voltage source, wherein a second input
terminal of the feedback unit is configured to receive the feedback voltage from the voltage generation unit, and wherein
the feedback unit is configured to generate a feedback signal having a second feedback frequency based on both the reference
voltage and the feedback voltage.

US Pat. No. 9,190,331

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Manufacturi...

1. A semiconductor device, comprising:
a substrate;
a fin projecting upwardly from or through an upper surface of the substrate, the fin including a first semiconductor layer
portion formed from a corresponding first semiconductor material, the fin being interposed between and longitudinally extending
between a semiconductive source region portion and a semiconductive drain region portion;

wherein the fin includes a semiconductive channel region joining the source region portion and the drain region portion, the
channel region being of a first conductivity type; and

wherein the fin further includes at least first and second channel control regions adjoining the channel region and configured
for selectively creating charge depletion zones for thereby selectively controlling electrical conduction through the channel
region, the at least two channel control regions being respectively formed along respective and opposed sidewall portions
of the channel region and the channel control regions having a second conductivity type which is opposite to the first conductivity
type; and

a gate adjoining and electrically connecting to the channel control regions from outer sides of the channel control regions.

US Pat. No. 9,153,585

TUNNELING FIELD EFFECT TRANSISTOR DEVICE AND RELATED MANUFACTURING METHOD

Semiconductor Manufacturi...

1. A transistor device comprising:
a first source portion including a first InSb material set and a first first-type dopant set;
a first drain portion including a second InSb material set and a first second-type dopant set;
a first channel portion disposed between the first source portion and the first drain portion and including a third InSb material
set;

a first gate member overlapping the first channel portion;
a second drain portion including a first GaSb material set and a second first-type dopant set;
a second source portion including a second GaSb material set and a second second-type dopant set;
a second channel portion disposed between the second source portion and the second drain portion and including a third GaSb
material set; and

a second gate member overlapping the second channel portion.

US Pat. No. 9,362,276

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor device,
comprising:
providing a semiconductor substrate including a plurality of active regions configured in parallel and an isolation region
between adjacent active regions;

forming isolation structures in the isolation regions;
providing a plurality of dummy gate structures on the isolation structures and the active regions that are in the semiconductor
substrate, wherein each dummy gate structure includes a dummy gate electrode layer and a sidewall spacer on a sidewall surface
of the dummy gate electrode layer;

forming a stress layer in the semiconductor substrate between two adjacent dummy gate structures;
forming a first dielectric layer on the semiconductor substrate, the stress layers, and the sidewall spacers of the plurality
of dummy gate structures, wherein the first dielectric layer exposes the dummy gate electrode layers of the plurality of dummy
gate structures;

removing the dummy gate electrode layers to form first openings in the first dielectric layer;
forming gate structures in the first openings, wherein the gate structures include a plurality of functional gate structures
and at least one non-functional gate structure;

removing the at least one non-functional gate structure to form at least one second opening in the first dielectric layer;
forming at least one third opening in the semiconductor substrate at a bottom of the at least one second opening; and
forming a second dielectric layer to fill up the at least one second opening and the at least one third opening.

US Pat. No. 9,373,694

SYSTEM AND METHOD FOR INTEGRATED CIRCUITS WITH CYLINDRICAL GATE STRUCTURES

Semiconductor Manufacturi...

1. A transistor device comprising:
a semiconductor substrate;
a fin structure protruding from the semiconductor substrate and extending in a first direction, the fin structure having a
first type impurity and including a source region disposed at one end and a drain region disposed at the opposite end and
a channel region disposed between the source region and the drain region; and

a gate structure overlying the channel region;
wherein the fin structure has a rectangular cross-section bottom portion having a width and a height measured in a second
direction perpendicular to the first direction and an arched cross-section top portion,

wherein a maximum distance measured in the second direction between opposite sides of the arched cross-section top portion
is equal to the width of the rectangular cross-section bottom portion, and

wherein the source, drain, and channel regions each are doped with dopants of a same polarity and a same concentration.

US Pat. No. 9,252,010

METHOD FOR PROCESSING STRUCTURE IN MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for processing a structure in manufacturing of a semiconductor device, the method comprising:
polishing the structure to form a polished structure, the polished structure comprising a first metal member, a dielectric
layer that contacts the first metal member, and a particle that contacts at least one of the first metal member and the dielectric
layer;

applying a first organic acid to the polished structure to remove at least a first portion of the particle, and
applying a second organic acid to remove a second portion of the particle,
wherein the first organic acid is applied in a solution polishing process to remove the first portion of the particle, wherein
the second organic acid is used in a chemical cleaning process to remove the second portion of the particle, and wherein the
chemical cleaning process is performed after the solution polishing process.

US Pat. No. 9,557,348

SEMICONDUCTOR TESTING STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor testing structure, comprising:
providing a substrate having a device structure formed on a surface of the substrate, a dielectric layer formed on the surface
of the substrate and a surface of the device structure, and conductive structures and an insulation layer electrically insulating
the conductive structures formed on a first surface of the dielectric layer;

planarizing the conductive structures and the insulation layer to remove the conductive structures and the insulation layer
by a first planarization process until the first surface of the dielectric layer is exposed;

bonding the first surface of the dielectric layer with a dummy wafer by an adhesive layer; and
removing the substrate to expose a second surface relative to the first surface of the dielectric layer and a surface of the
device structure.

US Pat. No. 9,368,497

FIN FIELD-EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating fin-field effect transistors, comprising:
providing a semiconductor substrate;
forming a plurality of fins on a surface of the semiconductor substrate;
forming dummy gates over side and top surfaces of the fins;
forming a precursor material layer to cover the dummy gates and the semiconductor substrate;
performing a thermal annealing process on the precursor material layer to convert the precursor material layer into a dielectric
layer having a plurality of voids;

planarizing the dielectric layer with the plurality of voids to expose top surfaces of the dummy gates;
performing a post-treatment process using oxygen-contained de-ionized water onto the planarized dielectric layer to eliminate
the plurality of voids formed in the dielectric layer;

removing the dummy gates to form trenches in the dielectric layer without voids; and
forming a high-K metal gate structure in each of the trenches.

US Pat. No. 9,368,412

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing one or more semiconductor devices, the method comprising:
providing a dielectric layer on a substrate structure, wherein the substrate structure includes a first electrode and a second
electrode;

providing a first mask on the dielectric layer;
providing a second mask, which overlaps the first mask and has a first designated structure, wherein a portion of the first
mask is positioned between a first portion of the first designated structure and a second portion of the first designated
structure in a layout view of a process structure that includes the substrate structure, the dielectric layer, the first mask,
and the second mask; and

performing a first removal process through the first portion of the first designated structure and through the second portion
of the first designated structure for removing portions of the dielectric layer to form a first contact hole and a second
contact hole in a first remaining dielectric layer, which is a remaining portion of the dielectric layer, wherein the first
contact hole and the second contact hole expose the first electrode and the second electrode, respectively.

US Pat. No. 9,190,330

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
providing a fin protruding upwardly from or through a surface of the substrate, the fin having a first semiconductor layer
portion formed of a corresponding first semiconductive material having a respective first conductivity type;

forming a to-be-sacrificed dummy gate enwrapping a first portion of the fin that corresponds to a channel region to be formed
at that enwrapped first portion;

forming a first insulating material layer so as to at least cover an exposed second portion of the fin that is not enwrapped
by the dummy gate, the formed first insulating material layer leaving exposed a top surface of the dummy gate;

selectively removing the dummy gate to thereby expose the first portion of the first semiconductor layer portion that was
enwrapped by the dummy gate while not exposing the second portion of the fin that is covered by the first insulating material
layer; and

introducing, into the exposed portion of the first semiconductor layer portion, one or more dopants including a conductivity
type reversing dopant that is capable of imparting a second conductivity type to the semiconductive parts of the fin it is
introduced into, so as to thereby form a channel region having the first conductivity type and at least two opposed channel
control regions having the second conductivity type, the at least two opposed channel control regions being disposed for selectively
generating charge depletion zones at and into opposed sides of the channel region for thereby selectively controlling current
conduction through the channel region,

wherein the channel control regions further comprise a portion formed above and adjoining a top of the channel region.

US Pat. No. 9,449,718

METHOD FOR SETTING A FLASH MEMORY FOR HTOL TESTING

SEMICONDUCTOR MANUFACTURI...

1. A method for setting voltages in a flash memory for high temperature operating life (HTOL) testing, the flash memory comprising
a substrate including a source region and a drain region, and a control gate, the method comprising:
setting the voltages that are applied to the source region, the control gate, and the substrate when the flash memory is in
a standby mode, where setting the voltages further comprises:

setting a first voltage that is applied to the source region to a ground voltage,
setting a second voltage that is applied to the control gate to the ground voltage, and
setting a third voltage that is applied to the substrate to a power supply voltage that is higher than the ground voltage,
wherein a charge leakage between the control gate and the substrate is reduced and a charge storage capability of the control
gate is improved by applying the ground voltage to both the control gate and the source region when the flash memory is in
the standby mode.

US Pat. No. 9,391,188

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:
a hybrid orientation substrate, containing a first portion having a first crystal orientation and a second portion having
a second crystal orientation different from the first crystal orientation, the first and second portions being laminated and
formed from the same semiconductor material;

a gate on the substrate;
a source region and a drain region in the substrate on each side of the gate; and
a dielectric wall in the substrate below the gate, the dielectric wall being substantially vertical to a substrate surface
and being located between at least one of the source region and the drain region and a side surface of the gate corresponding
to said at least one of the source region and the drain region, the upper end of the dielectric wall being lower than the
substrate surface;

wherein the crystal orientations of the source and drain regions are the same as one of the first and second crystal orientations,
and the crystal orientation of a channel region below the gate and between the source and drain regions is the same as the
other of the first and second crystal orientations; and wherein the source and drain regions and the channel region are formed
from the same semiconductor material as the substrate.

US Pat. No. 9,316,925

METHODS FOR MONITORING SOURCE SYMMETRY OF PHOTOLITHOGRAPHY SYSTEMS

SEMICONDUCTOR MANUFACTURI...

1. A method for monitoring a source symmetry of a photolithography system, comprising:
providing a first reticle having a plurality of first mark patterns and a plurality of second mark patterns;
providing a second reticle also having a plurality of the first mark patterns and a plurality of the second mark patterns;
forming first bottom overlay alignment marks on a first wafer using the first reticle;
forming first top overlay alignment marks on the first bottom overlay alignment marks using the second reticle;
forming second bottom overlay alignment marks on a second wafer using the second reticle;
forming second top overlay alignment marks on the second bottom overlay alignment marks using the first reticle;
measuring a first overlay shift of the first top overlay alignment marks and the first bottom overlay alignment marks;
measuring a second overlay shift of the second top overlay alignment marks and the second bottom overlay alignment marks;
and

obtaining an overlay shift caused by the source asymmetry based on the first overlay shift and the second overlay shift.

US Pat. No. 9,190,317

INTERCONNECTION STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating an interconnection structure, comprising:
providing a substrate having certain semiconductor devices, a metal layer electrically connecting with the semiconductor devices,
and a barrier layer on the metal layer;

forming a dielectric layer on the substrate;
forming a black diamond hard mask on the dielectric layer;
forming an antireflective coating made of silicon oxynitride (SiON) on the black diamond hard mask that is on the dielectric
layer;

forming a second mask having a first pattern corresponding to a through hole, wherein the antireflective coating significantly
reduces lithographic light reflection to avoid photoresist residue in the first pattern;

forming a through hole by etching the dielectric layer and the antireflective coating covering the dielectric layer using
the second mask as an etching mask; and

forming a via by filling the through hole with a conductive material.

US Pat. No. 9,576,897

SEMICONDUCTOR INTERCONNECT DEVICE

SEMICONDUCTOR MANUFACTURI...

1. An interconnect device, comprising:
a substrate;
a dielectric layer on the substrate;
a metal layer passing through the dielectric layer and on the substrate;
a metal nitride capping layer on the metal layer, wherein the metal nitride capping layer is formed from underlying portions
of the metal layer by a thermal annealing reaction and a nitridation process; and

a semiconductor nitride layer on the dielectric layer and in direct contact with the metal nitride capping layer, wherein
the semiconductor nitride layer and the metal nitride capping layer are from a same semiconductor cover layer after the thermal
annealing reaction and the nitridation process.

US Pat. No. 9,576,828

HEAT RESERVOIR CHAMBER, AND METHOD FOR THERMAL TREATMENT

SEMICONDUCTOR MANUFACTURI...

1. A thermal treatment chamber, comprising:
a wafer holder to hold a to-be-processed wafer;
a heat reservoir located under the wafer holder, but being separated from the wafer holder, for adjusting a temperature of
the wafer holder based on the to-be-processed wafer;

a first driving unit connected to the heat reservoir for adjusting a distance between the wafer holder and the heat reservoir
to adjust the temperature of the wafer holder; and

a frame having a base and sidewalls, wherein the sidewalls are fixed on the base to form space such that the wafer holder,
the heat reservoir, and the first driving unit are positioned in the space, wherein:

the first driving unit includes a driver and a connecting unit, the driver being fixed on the base for driving the heat reservoir
moving up and down, and the connecting unit being connected to the heat reservoir and the driver to guide a movement direction
of the heat reservoir, and

the connecting unit includes a fixed portion and a movable portion, the fixed portion being fixed on a sidewall of the frame,
and the movable portion being connected to the heat reservoir and the driver to guide the movement direction of the heat reservoir
along directions confined by the fixed portion.

US Pat. No. 9,362,331

METHOD AND SYSTEM FOR IMAGE SENSOR AND LENS ON A SILICON BACK PLANE WAFER

Semiconductor Manufacturi...

1. A method for forming image sensors, the method comprising:
providing a substrate;
forming a plurality of photo diode regions, each of the photo diode regions being spatially disposed on the substrate;
forming one or more interconnect layers overlying the plurality of photo diode regions;
forming an interlayer dielectric layer overlying all the interconnect layers;
forming a shielding layer overlying the interlayer dielectric layer, the shielding layer having openings only above the plurality
of photo diode regions to allow light to reach the photo diode regions; and

forming a plurality of lens structures comprising a silicon dioxide bearing material overlying the shielding layer, wherein
the shielding layer comprises openings only underneath the plurality of lens structures and is configured to shield regions
not underneath the lens structures.

US Pat. No. 9,207,138

CAPACITIVE PRESSURE SENSORS AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a capacitive pressure sensor, comprising:
providing a substrate;
forming a trench in a surface of the substrate;
forming a first electrode including a first sub-electrode and a second sub-electrode on a side surface of the trench;
forming a first sacrificial layer on the first electrode;
etching the substrate under the bottom of the trench to form an etching hole in the substrate under the bottom of the trench;
forming a second electrode on a side surface and a bottom surface of the trench, a portion of the bottom of the trench, and
a side surface of the first sacrificial layer;

forming a second sacrificial layer on the second electrode and filling up the trench and the etching hole;
forming a first sealing layer on the second sacrificial layer;
removing the first sacrificial layer to form a first chamber between the first electrode and the second electrode;
planarizing the substrate or etching the substrate to expose the sacrificial layer on the bottom surface of the etching hole;
removing the second sacrificial layer in the trench and the etching hole to form a second chamber in the second electrode;
and

forming a second sealing layer on the other surface of the substrate to seal the second chamber.

US Pat. No. 9,093,317

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
providing a semiconductor substrate including a first region and a second region;
forming a gate dielectric material layer to cover the first region of the semiconductor substrate, and forming a floating
gate dielectric layer on a surface portion of the second region of the semiconductor substrate, a floating gate on the floating
gate dielectric layer, and a control gate dielectric layer on the floating gate, wherein the control gate dielectric layer
has a top surface higher than the gate dielectric material layer in the first region;

conformally forming a gate material layer to cover the gate dielectric material layer of the first region and to cover the
semiconductor substrate, sidewalls of the floating gate dielectric layer and the floating gate and the control gate dielectric
layer, a top surface of the control gate dielectric layer of the second region, the gate material layer on the control gate
dielectric layer of the second region having a top surface higher than a top surface in the first region;

forming a first filling material layer on the gate material layer to provide a first flat surface and forming a first patterned
mask layer on the first filling material layer to cover the second region and to perform a patterning in the first region;

forming a gate on a gate dielectric layer in the first region by etching the gate material layer and the gate dielectric material
layer using the first patterned mask layer as an etch mask, wherein the gate material layer in the second region has the top
surface higher than a top surface of the gate of the first region; and

forming a control gate on the control gate dielectric layer in the second region by etching the gate material layer in the
second region.

US Pat. No. 9,112,025

LDMOS DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for forming an LDMOS device, the method comprising:
providing an N-type buried isolation region in a P-type substrate;
forming a P-type epitaxial layer over the P-type substrate, the P-type epitaxial layer including a first region and a second
region, wherein the first region is positioned above the N-type buried isolation region, and the second region surrounds the
first region;

forming an annular groove in the second region of the P-type epitaxial layer, wherein the annular groove surrounds the first
region of the P-type epitaxial layer and exposes a surface of the N-type buried isolation region at a bottom of the annular
groove;

forming isolation layers on both sidewalls of the annular groove;
forming an annular conductive plug in the annular groove between the isolation layers, wherein the annular conductive plug
is in contact with the N-type buried isolation region at the bottom of the annular conductive plug; and

forming a gate structure of an LDMOS transistor over the first region of the P-type epitaxial layer.

US Pat. No. 9,373,784

SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor memory device, comprising:
a first insulating portion;
a phase-change material element that directly contacts the first insulating portion;
a first electrode, which directly contacts a first side surface of the phase-change material element, the first side surface
of the phase-change material element being not parallel to a top surface of the first electrode;

an insulating layer, wherein a planar surface of the insulating layer directly contacts a planar surface of the phase-change
material element, and wherein the planar surface of the phase-change material element is not parallel to the first side surface
of the phase-change material element; and

a second insulating portion surrounding the phase-change material element, directly contacting each of the planar surface
of the insulating layer, the first side surface of the phase-change material element, and the first insulating portion, and
being asymmetric with reference to the phase-change material element.

US Pat. No. 9,202,885

NANOSCALE SILICON SCHOTTKY DIODE ARRAY FOR LOW POWER PHASE CHANGE MEMORY APPLICATION

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device having a plurality of Schottky diodes, the method comprising:
providing a P-type semiconductor substrate;
defining a diode array region having the plurality of Schottky diodes and a peripheral device region on the P-type semiconductor
substrate;

forming an N+ buried layer in the diode array region;
forming a semiconductor epitaxial layer on a portion of the peripheral device region and on the N+ buried layer;
forming a plurality of deep trench isolations through at least the epitaxial layer and the N+ buried layer along a first direction;
forming a plurality of shallow trench isolations within the diode array region and within the peripheral device region along
a second direction, the shallow trench isolations having a depth equal to or greater than a thickness of the epitaxial layer;

wherein forming a plurality of shallow trench isolations comprises:
forming a plurality of shallow trenches within the epitaxial layer of the diode array region and within the epitaxial layer
of the peripheral device region;

forming a liner layer overlying the shallow trenches;
performing an ion implantation into the liner layer to form a P+ protection layer;
subjecting the P+ protection layer to an annealing treatment;
filling the shallow trenches with an insulation material; and
planarizing the insulation material using a chemical mechanical polishing process;
wherein performing an ion implantation comprises implanting dopants at an energy in a range between 5 KeV and 40 KeV, a dose
in a range between 1.0×1012 to 4.0×1015 atoms per cm2, and an implant angle in a range of 45 degrees and 70degrees relative to a surface of the semiconductor substrate, the dopants
comprising boron, boron fluoride, or indium;

forming an N? doped region within a region of the epitaxial layer disposed between the deep trench isolations and the shallow
trench isolations of the diode array region; and

forming a metal silicide on the N? doped region.

US Pat. No. 9,190,327

CMOS TRANSISTORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating CMOS transistors, comprising:
providing a semiconductor substrate having at least one first region and at least one second region;
forming a first gate on a top surface of the semiconductor substrate in the first region and a second gate on the top surface
of the semiconductor substrate in the second region;

forming first offset spacers made of a first nitrogen-contained material on side surfaces of the first gate and the second
gate;

forming dummy spacers made of a second nitrogen-contained material on surfaces of the first offset spacers and the semiconductor
substrate in the first region and a dummy spacer material layer made of the second nitrogen-contained material to cover the
second gate and the top surface of the semiconductor substrate in the second region;

forming sigma-shape SiGe stress layers in the semiconductor substrate at both sides of the first gate in the first region;
removing the first offset spacers, the dummy spacers and the dummy spacer material layer;
forming second offset spacers on the first gate and the second gate;
forming N-type lightly doped drain regions in the semiconductor substrate in the second region at both sides of the second
gate and the second offset spacers; and

forming main sidewall spacers on the second offset spacers.

US Pat. No. 9,419,090

INTERCONNECT STRUCTURES AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating an interconnect structure, comprising:
providing a substrate;
forming a semiconductor layer having at least a first sub-semiconductor layer and a second sub-semiconductor layer on the
substrate;

forming a first interconnect component having a first contact region on the first sub-semiconductor layer, and forming a second
interconnect component having a second contact region on the second sub-semiconductor layer;

forming an interlayer dielectric layer between the first interconnect component and the second interconnect component; and
forming an interconnect line layer in the interlayer dielectric layer, wherein the interconnect line layer is connected with
the first contact region and the second contact region to realize an electrical interconnection of the first interconnect
component and the second interconnect component.

US Pat. No. 9,123,606

PIXEL STRUCTURES OF CMOS IMAGING SENSORS

Semiconductor Manufacturi...

1. A pixel structure of a CMOS imaging sensor, comprising:
a semiconductor substrate doped with first type doping ions;
a gate structure formed on the semiconductor substrate;
an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type doping
ions formed in the semiconductor substrate at one side of the gate structure; isolation layers formed between side surfaces
of the epitaxial layer and the semiconductor substrate to prevent dark currents from laterally transferring;

a floating diffusion region formed in the semiconductor substrate at the other side of the gate structure; and
a pinning layer formed on the epitaxial layer,
wherein the isolation layers are formed by: forming a hard mask layer having an opening on the semiconductor substrate;
forming a trench in the semiconductor substrate using the hard mask layer as an etching mask;
forming an isolation material layer on side surfaces of the trench, performing a mask-less process onto the isolation material
layer and filling the trench with the epitaxial layer,

wherein a portion of the epitaxial layer is higher than a top surface of the semiconductor substrate, and the portion of the
epitaxial layer higher than the top surface of the semiconductor substrate covers a portion of the top surface of the semiconductor
substrate around the trench and disposed under a sidewall spacer of the gate structure;

wherein a width of the portion of the epitaxial layer covering the portion of the top surface of the semiconductor substrate
around the trench is in a range of approximately 0.1 ?m-1 ?m.

US Pat. No. 9,064,804

METHOD FOR MANUFACTURING TWIN BIT STRUCTURE CELL WITH SILICON NITRIDE LAYER

Semiconductor Manufacturi...

1. A method for forming a twin bit cell structure for a flash memory device, the method comprising:
providing a semiconductor substrate including a surface region;
forming a gate dielectric layer overlying the surface region;
forming a polysilicon gate structure overlying the gate dielectric layer;
forming first and second undercut regions underneath the polysilicon gate structure in first and second portions of the gate
dielectric layer;

exposing the semiconductor substrate, the gate dielectric layer, the undercut regions, and the polysilicon gate structure
to an oxidizing environment to cause:

formation of a first silicon oxide layer overlying a top surface, side surfaces, and bottom surfaces facing the undercut regions
of the polysilicon gate structure, and

formation of a second silicon oxide layer overlying a portion of the surface region of the semiconductor substrate;
depositing a silicon nitride material over the first and second silicon oxide layers and filling the undercut regions;
selectively etching a first portion of the silicon nitride material overlapped by the polysilicon gate structure;
maintaining a second portion the silicon nitride material in an insert region in a portion of each of the undercut regions;
and

forming a sidewall spacer structure, wherein the sidewall spacer structure is formed so as to overlie each of the side surfaces
of the polysilicon gate structure, to overlie exposed surfaces of the silicon nitride material, and to overlie an exposed
surface portion of the second oxide layer,

wherein the sidewall spacer structure contacts the exposed surfaces of the silicon nitride material at a contact interface,
and wherein the contact interface is overlapped by the polysilicon gate structure in the undercut regions underneath the polysilicon
gate structure.

US Pat. No. 9,419,057

RESISTIVE RANDOM ACCESS MEMORY DEVICE AND MANUFACTURING METHODS

SEMICONDUCTOR MANUFACTURI...

1. A resistive memory storage device, comprising:
a lower electrode;
an upper electrode;
a plurality of composite material layers disposed between the lower electrode and the upper electrode, each composite material
layer including a first layer and a second layer, wherein:

the first layer is a metal-based high-K dielectric material layer having a first metal element; and
the second layer is a metal layer including the first metal element.

US Pat. No. 9,142,675

FIN FIELD EFFECT TRANSISTORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a fin field-effect transistor, comprising:
providing a substrate having a first region and a second region;
forming a plurality of fin structures on a surface of the substrate in the first region and the second region;
forming a first mask layer on the fin structures and on the surface of the substrate, wherein the first mask layer has a plurality
of first openings exposing fin structure portions in the first region next to the second region;

removing the fin structure portions exposed in the first region next to the second region;
forming a second mask layer on the first mask layer that is on the fin structures in the second region to cover the fin structures
in the second region and to expose remaining fin structures in the first region;

removing the remaining fin structures in the first region to leave the fin structures in the second region;
forming fins by etching the substrate using the fin structure in the second region as an etching mask; and
forming a gate structure stretching over the fins in the second region and source/drain regions in the fins at both sides
of the gate structures.

US Pat. No. 9,048,413

SEMICONDUCTOR MAGNETORESISTIVE RANDOM-ACCESS MEMORY (MRAM) DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device, comprising:
a magnetic tunnel junction unit; a magnetic shielding material layer covering sidewalls of the magnetic tunnel junction unit;
an isolation dielectric layer disposed between the sidewalls of the magnetic tunnel junction unit and the magnetic shielding
material layer,

wherein a height of the isolation dielectric layer is greater than a height of the magnetic tunnel junction unit in a vertical
direction,

wherein a height of the magnetic shielding material layer is greater than the height of the isolation dielectric layer in
the vertical direction, and a portion of the magnetic shielding material layer extending above the isolation dielectric layer
comprises an oxide of the magnetic shielding material, and

wherein the oxide of the magnetic shielding material includes Al2O3;

a first dielectric layer in which the magnetic tunnel junction unit, the isolation dielectric layer, and the magnetic shielding
material layer are embedded,

wherein a height of the first dielectric layer and the height of the magnetic shielding material layer are substantially the
same;

a second dielectric layer located above the first dielectric layer and the magnetic tunnel junction unit; and
a first conductive contact extending through the second dielectric layer and the isolation dielectric layer so as to electrically
connect with a top portion of the magnetic tunnel junction unit,

wherein an upper portion of the isolation dielectric layer contacts portions of each of the first conductive contact and the
second dielectric layer, and

wherein the first conductive contact and the magnetic shielding material layer are electrically isolated from each other by
the second dielectric material layer and the isolation dielectric layer.

US Pat. No. 9,443,755

METHOD OF FABRICATING MINIATURIZED SEMICONDUCTOR OR OTHER DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method of fabricating a semiconductor device, the method comprising:
forming a frame on a surface of a substrate, wherein an interior is surrounded by one or more interior sidewalls of the frame;
providing a copolymer member comprising a first monomer and a second monomer;
after the providing, processing the copolymer such that the first monomer is disposed at a center region of the interior and
is surrounded by the second monomer, wherein a planar top surface of the second monomer directly abuts a top surface of the
first monomer, is coplanar with the top surface of the first monomer, and covers the frame in a direction perpendicular to
the planar top surface of the second monomer;

after the processing, solidifying the second monomer to produce a solidified monomer member;
after the solidifying, selectively removing the first monomer to produce a void; and
using the void and the solidified monomer member for partially removing the substrate.

US Pat. No. 9,117,053

ENHANCED OPTICAL PROXIMITY CORRECTION (OPC) METHOD AND SYSTEM

Semiconductor Manufacturi...

1. An enhanced optical proximity correction method, comprising:
providing a mask substrate and a substrate;
forming a customer target pattern on the mask substrate;
obtaining a production layout by performing an optical proximity correction process onto the customer target pattern using
the customer target pattern and a pattern formed on the substrate;

obtaining light intensity information of the production layout instead of dimension by:
decomposing sides of the production layout into a plurality of segments, drawing a spatial light intensity distribution curve
of each of a plurality of test points picked up from a line vertical to a segment, and searching for a maximum light intensity
and a minimum light intensity in a first space range using an intersection point of the spatial light intensity distribution
curve and a reference exposure threshold as a center,

wherein the line is through the center point of the segment and the test points are in inner regions and outer regions at
both sides of the segment;

storing the light intensity information of the production layout, storing the production layout, and storing surrounding coherence
radius in an optical proximity correction model database if the light intensity information of the production layout does
not coincide with light intensity information of original modeling patterns already stored in the optical proximity correction
model database; and

generating actual patterns using the stored optical proximity correction model corresponding to the stored light intensity
information of the production layout, the production layout, and surrounding coherence radius.

US Pat. No. 9,059,068

PIXEL STRUCTURES OF CMOS IMAGING SENSORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a pixel structure of a CMOS imaging sensor, comprising:
providing a semiconductor substrate doped with first type doping ions;
forming a hard mask layer having an opening on the semiconductor substrate;
forming a trench in the semiconductor substrate by etching the semiconductor substrate using the hard mask layer as an etching
mask;

etching the hard mask layer to enlarge the opening to form an enlarged opening to expose a surface portion of a top surface
of the semiconductor substrate around the trench;

forming isolation layers on side surfaces of the trench to prevent a dark current from laterally transferring;
forming an epitaxial layer doped with second type doping ions with a doping type opposite to a doping type of the first type
doping ions in the trench by filling up the trench and covering the surface portion of the top surface of the semiconductor
substrate around the trench,

wherein a portion of the epitaxial layer is higher than the top surface of the semiconductor substrate, the portion of the
epitaxial layer higher than the top surface of the semiconductor substrate is filled in the enlarged opening, and the portion
of the epitaxial layer higher than the top surface of the semiconductor substrate covers the surface portion of the top surface
of the semiconductor substrate exposed by the enlarged opening;

forming a pinning layer on the epitaxial layer;
forming a gate structure on the top surface of the semiconductor substrate at one side of the epitaxial layer; and
forming a floating diffusion region in the semiconductor substrate at one side of the gate structure far from the epitaxial
layer.

US Pat. No. 9,112,023

MULTI-GATE VDMOS TRANSISTOR AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a multi-gate vertical double-diffused metal-oxide-semiconductor (VDMOS) transistor, comprising:
providing a substrate having a first surface and a second surface opposite to the first surface;
forming a drift layer on the first surface of the substrate;
forming an epitaxial layer having a first conductivity type on the drift layer;
etching the epitaxial layer and a thickness portion of the drift layer to form a plurality of trenches;
forming a plurality of gate structures, each gate structure of the plurality of gate structures substantially entirely filling
each trench of the plurality of trenches, an arrangement of the plurality of gate structures forms a polygonal shape or a
concentric circular shape by lines connecting centers of the plurality of gate structures;

forming a plurality of doped regions having a second conductivity type opposite to the first conductivity type in the epitaxial
layer, each doped region of the plurality of doped regions partially surrounding a top portion of a sidewall of each gate
structure of the plurality of gate structures such that each gate structure of two adjacent gate structures has a first half
of the top portion of the sidewall surrounded by a doped region of the plurality of doped regions and a second half of the
top portion of the sidewall exposed to the epitaxial layer, and two doped regions of the plurality of doped regions are located
between the two adjacent gate structures in a cross section vertical to the first surface or the second surface of the substrate;

forming a source metal layer on a planar surface of the epitaxial layer, the source metal layer electrically connecting the
plurality of doped regions; and

forming a drain metal layer on the second surface of the substrate.

US Pat. No. 9,515,078

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor structure, comprising:
providing a semiconductor substrate;
forming a first stop layer on the semiconductor substrate, a first sacrificial layer on the first stop layer, a second stop
layer on the first sacrificial layer, and a second sacrificial layer on the second stop layer;

forming a surface-covering layer on the second sacrificial layer, wherein the surface-covering layer is made of a material
layer including silicon oxide, and has a thickness ranging from about 30 Å to about 100 Å;

etching the second sacrificial layer, the second stop layer, the first sacrificial layer, the first stop layer, and the semiconductor
substrate, to form a groove;

filling an insulating dielectric material in the groove to form an isolation structure, a top surface of the isolation structure
being leveled with a surface of the second sacrificial layer;

removing the second sacrificial layer, to expose sidewalls and a top of an exposed portion of the isolation structure;
removing the second stop layer and etching the exposed portion of the isolation structure, to reduce a width of the top of
the exposed portion of the isolation structure;

removing the first sacrificial layer; and
forming a floating gate on the first stop layer.

US Pat. No. 9,406,555

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming an interconnect device, comprising:
providing a dielectric layer on a substrate;
forming openings in the dielectric layer to expose a portion of a surface of the substrate at a bottom of each opening;
forming a metal layer to fill up the openings;
forming a semiconductor cover layer on the metal layer and on the dielectric layer;
performing a thermal annealing reaction on the semiconductor cover layer to convert portions of the semiconductor cover layer
that are on the metal layer into a metal capping layer; and

performing a nitridation process on the metal capping layer and a remaining semiconductor cover layer to convert the metal
capping layer into a metal nitride capping layer and the remaining semiconductor cover layer into a semiconductor nitride
layer.

US Pat. No. 9,524,865

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
providing a substrate; and
forming a dielectric layer on the substrate by a deposition process using reactant gases including a silicon-source gas and
an oxygen-source gas under a radio-frequency (RF) power, wherein:

the deposition process performed for a total deposition time to form the dielectric layer is divided into a first time length,
a second time length and a third time length; and

the RF power of the deposition process in the first time length is a first power, the first power gradually increases from
the first power to a second power in the second time length, the RF power in the third time length is the second power, and
the first power is less than the second power.

US Pat. No. 9,508,609

FIN FIELD EFFECT TRANSISTOR AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a FinFET, comprising:
providing a semiconductor substrate having a plurality of sacrificial layers formed thereon, each sacrificial layer having
two sides;

forming a plurality of first sidewall spacers on the semiconductor substrate and having one first sidewall spacer on each
side of each sacrificial layer of the plurality of sacrificial layers;

forming a plurality of second sidewall spacers on the semiconductor substrate and having one second sidewall spacer on each
first sidewall spacer formed on each sacrificial layer, wherein the plurality of second sidewall spacers is made of a material
different from the plurality of first sidewall spacers;

removing the plurality of sacrificial layers;
measuring a first width as a distance between two adjacent first sidewall spacers of the plurality of first sidewall spacers,
and a second width as a distance between two adjacent second sidewall spacers of the plurality of second sidewall spacers;

when the first width is not substantially equal to the second width, correspondingly etching the plurality of first sidewall
spacers or the plurality of second sidewall spacers such that the first width is substantially equal to the second width;
and

etching the semiconductor substrate, using the plurality of first sidewall spacers and the plurality of second sidewall spacers
as an etch mask, to form a plurality of fins, such that a top of each fin of the plurality of fins has a substantially symmetrical
morphology.

US Pat. No. 9,379,240

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:
a substrate;
a first fin disposed on the substrate and including a first semiconductor member;
a first spacer having a first type of stress and directly contacting the first semiconductor member;
an insulating layer directly contacting the substrate, wherein the first spacer is positioned between the substrate and a
portion of the insulating layer; and

a second spacer having a second type of stress that is different from the first type of stress, wherein the portion of the
insulating layer is positioned between the first spacer and the second spacer, and wherein a side of the first fin directly
contacts each of the first spacer and the second spacer.

US Pat. No. 9,541,463

CAPACITIVE PRESSURE SENSORS

SEMICONDUCTOR MANUFACTURI...

1. A capacitive pressure sensor, comprising:
a substrate having a trench and a through hole connecting a bottom surface of the trench and a first surface of the substrate;
a first electrode formed on a side surface of the trench being vertical to a second surface of the substrate, wherein the
first electrode includes a first sub-electrode and a second sub-electrode;

a second electrode formed in the trench and the through hole, wherein a first portion of the second electrode is formed on
side surfaces of the through hole, and a second portion of the second electrode is formed in the trench, a first chamber being
formed between the first electrode and the second electrode;

a second chamber formed in the second electrode;
a first sealing layer formed on the second electrode such that the second electrode and the first sealing layer are suspended;
and

a second sealing layer formed on the first surface of the substrate to seal the through hole.

US Pat. No. 9,472,422

SEMICONDUCTOR DEVICE STRUCTURE AND MANUFACTURING METHODS

Semiconductor Manufacturi...

1. A method for forming a semiconductor device, comprising:
providing a semiconductor structure, having:
a substrate,
N sub-stack structures numbered from 1 to N overlying the substrate, where N is an integer, and each sub-stack structure includes
two sub-stacks; and

a mask layer overlying the N sub-stack structures;
repeatedly removing a portion of the mask layer and removing exposed portions of the sub-stack structures to form a first
stepped structure;

forming first spacers on sidewalls of the mask layer and the sub-stack structures in the first stepped structure, each spacer
covering a portion of the exposure portions of the sub-stack structures;

using the mask layer and the first spacers as masks, removing exposed portions of an upper sub-stack in the stepped structure;
and

removing the mask layer and the first spacer to form a second stepped structure.

US Pat. No. 9,209,289

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of fabricating a semiconductor device, the method comprising:
forming a substrate structure, wherein the substrate structure includes a substrate and a fin-shaped barrier layer formed
on a surface of the substrate;

forming an insulating part adjacent to the fin-shaped barrier layer on the surface of the substrate, wherein the surface of
the substrate directly contacts each of the fin-shaped barrier and the insulating part and is parallel to a bottom side of
the substrate;

forming a quantum well (QW) material layer on a surface of the fin-shaped barrier layer; and
forming a barrier material layer on the QW material layer.

US Pat. No. 9,634,087

FINFET AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a fin field-effect transistor (FinFET), comprising:
providing a semiconductor substrate;
forming a hard mask layer on the semiconductor substrate, wherein a position of the hard mask layer corresponds to a position
of subsequently formed fin;

forming a doping region in the semiconductor substrate by using the hard mask layer as a mask to perform an anti-punch-through
ion implantation process;

forming an anti-punch-through region by performing an annealing process onto the doping region, such that impurity ions in
the doping region diffuse into the semiconductor substrate under the hard mask layer; and

forming a trench by using the hard mask layer as a mask to etch the semiconductor substrate and the doping region, wherein
the semiconductor substrates between the adjacent trenches constitutes a fin.

US Pat. No. 9,595,585

METHODS FOR HIGH-K METAL GATE CMOS WITH SIC AND SIGE SOURCE/DRAIN REGIONS

Semiconductor Manufacturi...

18. A method of manufacturing a semiconductor device, comprising:
forming a PMOS region and an NMOS region in a semiconductor substrate;
forming a dummy gate structure in each of the PMOS region and NMOS region, a first portion of a hard mask being disposed on
top of the dummy gate structure;

forming a second portion of the hard mask layer on sidewalls of each of the dummy gate structures;
forming a first nitride layer covering the PMOS region and sidewall of NMOS dummy gate;
forming silicon carbon (SiC) regions embedded in the semiconductor substrate on both sides of the dummy gate structure in
the NMOS region;

removing the first nitride layer and the hard mask layer on top of the dummy gate in the NMOS region;
forming a second nitride layer covering the NMOS region and sidewall of PMOS dummy gate;
forming silicon germanium (SiGe) regions embedded in the semiconductor substrate on both sides of the dummy gate structure
in the PMOS region;

removing the second nitride layer from the NMOS region; and
while retaining the hard mask layer on top of the dummy gate in the PMOS region, performing ion implant to form source/drain
regions in the NMOS region and the PMOS region, respectively.

US Pat. No. 9,837,318

METHOD FOR REDUCING N-TYPE FINFET SOURCE AND DRAIN RESISTANCE

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a semiconductor substrate including a first semiconductor region;
a first semiconductor fin on the first semiconductor region;
a first gate structure on a portion of the surface of the first semiconductor fin;
a first mask layer on the first semiconductor fin and the first gate structure;
forming a second mask layer on the substrate structure;
etching the first mask layer and the second mask layer to expose a portion of a first semiconductor fin that is not covered
by the first gate structure;

performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion
of the first semiconductor fin located below the first gate structure;

etching the first semiconductor fin to remove at least a portion of an exposed portion of the first semiconductor fin; and
epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first
source region and a first drain region.

US Pat. No. 9,793,320

MEMORY CELL STRUCTURES

Semiconductor Manufacturi...

16. A memory cell array, comprising:
M rows and N columns of memory cells, M and N being a natural number greater than one, wherein each memory cell comprises:
a first diode;
a second diode; and
a random access memory cell element having a first end and a second end opposite the first end,
wherein the first diode and the random access memory cell element are series connected between a bit line and a word line,
wherein the second diode and the random access memory cell element are series connected in series between the word line and
a reset line,

wherein a set path is formed through the first diode and the random access memory cell element, and
wherein a reset path is formed through the random access memory cell element and the second diode.

US Pat. No. 9,673,322

VERTICAL JUNCTIONLESS TRANSISTOR DEVICE AND MANUFACTURING METHODS

Semiconductor Manufacturi...

1. A method for forming a semiconductor device, comprising:
providing a substrate;
forming a buffer layer including a lower portion extending over the substrate and a fin structure protruding above the lower
portion;

forming a sacrificial layer disposed over a side surface of the fin structure and a top surface of the lower portion of the
buffer;

forming a device semiconductor layer disposed over a surface of the sacrificial layer;
forming a gate dielectric layer disposed over a surface of the device semiconductor layer;
forming a gate electrode layer disposed over a surface of the gate dielectric layer;
removing a portion of the sacrificial layer to form a cavity surrounding the fin structure; and
performing an oxidation process to form a thermal oxide layer in the cavity surrounding the side surface of the fin structure.

US Pat. No. 9,754,680

METHOD AND DEVICE FOR COMPACT EFUSE ARRAY

Semiconductor Manufacturi...

1. An electrical fuse (eFuse) memory device, comprising:
an eFuse array having a plurality of electrical fuse (eFuse) cells arranged in multiple rows and columns, each eFuse cell
having an eFuse, a first diode, and a second diode coupled to an internal node, each eFuse cell further having first, second,
and third terminals, wherein:

the first diode is coupled between the first terminal and the internal node;
the second diode is coupled between the second terminal and the internal node; and
the eFuse is coupled between the third terminal and the internal node;
a shared NMOSFET for each of the multiple rows, with a drain coupled to the third terminal of each of the plurality of eFuse
cells in that row, a source coupled to a ground terminal, and a gate coupled to a word line;

a write bit line for each column, the write bit line coupled to the second terminal of each of the eFuse cells in that column;
and

a read bit line for each column, the read bit line coupled to the first terminal of the eFuse cell.

US Pat. No. 9,606,173

IN-CHIP STATIC-CURRENT DEVICE FAILURE DETECTING METHODS AND APPARATUS

SEMICONDUCTOR MANUFACTURI...

1. A method for detecting a static-current failure device in a chip, comprising:
providing a to-be-tested chip;
determining existence of a static-current failure device in the to-be-tested chip;
detecting positions of a plurality of hotspots in the to-be-tested chip when the existence of the static-current failure devices
is determined;

selecting a common circuit path of the plurality of hotspots according to position information of the plurality of hotspots
in a circuit layout file of the to-be-tested chip;

converting a circuit layout of the common circuit path into a corresponding electrical diagram and marking the hotspot positions
onto corresponding positions on the electrical diagram;

detecting a shared device of the hotspots in the electrical diagram; and
marking a position of the shared device in the circuit layout as a position of a static-current failure device.

US Pat. No. 9,747,999

COMPACT EFUSE ARRAY WITH DIFFERENT MOS SIZES ACCORDING TO PHYSICAL LOCATION IN A WORD LINE

Semiconductor Manufacturi...

1. An array of electrically programmable fuse (eFuse) units, the array comprising:
a first wiring drive unit configured to provide a first wiring;
a plurality of eFuse units connected to the first wiring, each of the eFuse units comprising:
an electrically programmable fuse (eFuse) having a first terminal and a second terminal;
a write switch having a first terminal, a second terminal, and a control terminal, the write switch being configured to pass
through a first portion of a write current;

a read/write switch having a first terminal, a second terminal, and a control terminal, the read/write switch being configured
to pass through a second portion of the write current or a read current;

a common node; wherein:
the first terminal of the eFuse is connected to a second wiring,
the second terminal of the eFuse, the first terminal of the read/write switch, and the first terminal of the write switch
are connected to the common node,

the second terminal of the write switch and the second terminal of the read/write switch is connected to a third wiring,
the control terminal of the write switch is connected to the first wiring,
the control terminal of the read/write switch is connected to a fourth wiring, and
at least one connecting switch having a control terminal connected to the first wiring, the at least one connecting switch
being disposed between two adjacent eFuse units and a first terminal connected to a common node of a first of the two adjacent
eFuse units and a second terminal connected to a common node of a second of the two adjacent eFuse units.

US Pat. No. 9,685,382

METHOD FOR REDUCING LOSS OF SILICON CAP LAYER OVER SIGE SOURCE/DRAIN IN A CMOS DEVICE

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, comprising:
providing a semiconductor substrate, the semiconductor substrate including a PMOS region and an NMOS region, and a plurality
of gate structures forming in the PMOS region and the NMOS region;

depositing a spacer material layer overlying the plurality of gate structures and the surface of the semiconductor substrate;
forming a first photoresist layer to cover the PMOS region and to expose the NMOS region;
etching the exposed portion of the spacer material layer to form first sidewall spacers on the sidewalls of the gate structures
in the NMOS region; removing the first photoresist layer;

depositing a sacrificial surface layer, the sacrificial layer overlying the spacer material layer covering the PMOS region,
the first sidewall spacers, and the exposed surface of the semiconductor substrate;

forming a second photoresist layer to cover the NMOS region and to expose the PMOS region;
etching the sacrificial material layer and the spacer material layer in the exposed PMOS region to form second sidewall spacers
on the sidewalls of the gate structure in the PMOS region;

removing the second photoresist layer; then subsequently
forming stress layers in source/drain regions in the PMOS region;
forming a cover layer on the stress layers; and then subsequently
removing the sacrificial material layer, the first sidewall spacers, and the second sidewall spacer.

US Pat. No. 9,672,899

DUAL-INVERTER MEMORY DEVICE AND OPERATING METHOD THEREOF

Semiconductor Manufacturi...

1. A memory device comprising:
a first inverter;
a second inverter, wherein an output terminal of the second inverter is electrically connected to an input terminal of the
first inverter;

a control transistor electrically connected to each of an output terminal of the first inverter and an input terminal of the
second inverter for controlling an electrical connection between the output terminal of the first inverter and the input terminal
of the second inverter;

a first access transistor, wherein a drain terminal of the first access transistor is electrically connected through the control
transistor to the output terminal of the first inverter; and

a second access transistor, wherein a source terminal of the second access transistor is electrically connected to the output
terminal of the second inverter.

US Pat. No. 9,553,097

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:
a semiconductor substrate;
a first transistor comprising: a first source electrode positioned in the semiconductor substrate, a first drain electrode
positioned in the semiconductor substrate, a first source connecting terminal formed of a first material and electrically
connected to the first source electrode, a first drain connecting terminal formed of the first material and electrically connected
to the first drain electrode, a first gate electrode overlapping a portion of the semiconductor substrate that is positioned
between the first source electrode and the first drain electrode, and a first gate dielectric layer positioned between the
first gate electrode and the semiconductor substrate; and

a second transistor comprising: a doped region positioned in the semiconductor substrate, a second source electrode positioned
in the semiconductor substrate, a second drain electrode positioned in the semiconductor substrate, a control gate electrode
formed of the first material and overlapping a part of the semiconductor substrate that is positioned between the second source
electrode and the second drain electrode, a second gate dielectric layer positioned between the control gate electrode and
the semiconductor substrate and directly contacting the control gate electrode, a floating gate electrode having a first portion
extending through an opening of the second gate dielectric layer to contact the doped region and having a second portion positioned
between the control gate electrode and the second gate dielectric layer, and an insulating member positioned between the control
gate electrode and the floating gate electrode.

US Pat. No. 9,741,573

NAND FLASH MEMORY AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a NAND flash memory, comprising:
providing a semiconductor substrate having an isolation material layer formed on the semiconductor substrate, a selection
gate material layer formed on the isolation material layer, and a plurality of alternately stacked gate dielectric material
layers and control gate material layers formed on the selection gate material layer;

forming a hard mask layer having a plurality of openings on a surface of the uppermost control gate material layer;
forming a stacked gate structure on the semiconductor substrate, wherein the stacked gate structure includes a selection gate
on the semiconductor substrate and control gates on the selection gate, and a width of the stacked gate structure is the same
as a width of the hard mask layer on a top surface of the stacked gate structure;

isolating the selection gate and the control gates by a gate dielectric layer;
forming a notch between the adjacent stacked gate structures;
removing a part of a width of the selection gate and a part of a width of the control gates by using the hard mask layer as
a mask to perform a back-etching process onto the stacked gate structure, such that a spacing between the adjacent selection
gates and a spacing between the adjacent control gates can be larger than a spacing between the adjacent hard mask layers
and a spacing between the adjacent gate dielectric layers; and

performing a deposition process to form a dielectric layer filling the notch, wherein air gaps are formed in the dielectric
layer between the adjacent selection gates and between the adjacent control gates.

US Pat. No. 9,773,739

MARK STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a mark structure, comprising:
providing a substrate having a device region and a mark region including a first mark region and a second mark region surrounded
by the first mark region;

sequentially forming a device layer, a dielectric layer and a mask layer on a surface of the substrate;
forming a first opening in the dielectric layer in the device region, a first mark in the dielectric layer in the first mark
region, and a mark opening in dielectric layer in the second mark region, a bottom of the first opening, a bottom of the first
mark and a bottom of the mark opening being lower than a surface of the dielectric layer, and higher than a surface of the
device layer;

forming a second opening exposing the device layer in the dielectric layer on the bottom of the first opening and a second
mark in the dielectric layer on the bottom of the mark opening; and

forming a conductive structure in the first opening and the second opening.

US Pat. No. 9,123,812

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method of fabricating an semiconductor device, comprising:
providing a semiconductor layer including a first opening therein;
filling the first opening with a stress material;
etching the stress material to form a second opening having a width less than a width of the first opening to leave a stress
material layer in the semiconductor layer and on each sidewall of the second opening;

etching the semiconductor layer to form a fin structure on a sidewall surface of the stress material layer;
forming a main gate structure on the sidewall surface of the fin structure; and
forming a back gate structure on the sidewall surface of the stress material layer.

US Pat. No. 9,660,058

METHOD OF FINFET FORMATION

Semiconductor Manufacturi...

1. A method of fabricating a fin for a FinFET device, the method comprising:
providing a semiconductor substrate;
forming a patterned silicon germanium layer on the semiconductor substrate;
epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer;
forming a sacrificial layer covering the patterned silicon germanium layer;
etching back the sacrificial layer until a portion of the silicon layer disposed on the top surface of the patterned silicon
germanium layer is exposed;

etching back the exposed portion of the silicon layer;
etching back again the sacrificial layer until a top surface of the sacrificial layer is co-planar with the top surface of
the patterned silicon germanium layer;

removing the patterned silicon germanium layer; and
removing the sacrificial layer to form the fin,
wherein etching back the sacrificial layer and etching back the exposed portion of the silicon layer are different etch processes.

US Pat. No. 10,031,516

METHOD AND SYSTEM FOR AUTOMATICALLY COLLECTING SEMICONDUCTOR MANUFACTURING PARAMETERS

SEMICONDUCTOR MANUFACTURI...

1. A method for automatically collecting semiconductor manufacturing parameters of a manufacturing equipment, comprising:reporting semiconductor manufacturing parameters obtained by self-monitoring of the manufacturing equipment, wherein each semiconductor manufacturing parameter has a state variable identifier and a collected event identifier such that each semiconductor manufacturing parameter is reported with the state variable identifier and the collected event identifier to obtain a measurement specification identifier for each semiconductor manufacturing parameter;
obtaining storage locations in an electronic data capture corresponding to reported semiconductor manufacturing parameters and transporting the reported semiconductor manufacturing parameters and corresponding storage locations;
receiving the reported semiconductor manufacturing parameters and the corresponding storage location and storing each reported semiconductor manufacturing parameters automatically into the electronic data capture of a manufacturing execution system according to the corresponding storage location, wherein the electronic data capture storing the storage locations also includes allowable specification for each reported semiconductor manufacturing parameter;
comparing between a reported semiconductor manufacturing parameter and a corresponding allowable specification; and
continuing a normal manufacturing operation of the manufacturing equipment when the reported semiconductor manufacturing parameter does not exceed a range defined by the corresponding allowable specification.

US Pat. No. 9,847,419

SEMICONDUCTOR DEVICE AND FABRICATION METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A fabrication method for forming a semiconductor device, comprising:
forming a substrate, the substrate including first fins, second fins, and a first trench located in the substrate between
a first fin and an adjacent fin, a first fin being parallel to an adjacent second fin;

forming a first mask layer on the substrate, the first fins, and the second fins;
removing portions of the first mask layer neighboring a first trench to expose a portion of a top surface of a first fin and
a portion of a top surface of the adjacent second fin to form a first opening, a portion of the top surface of the first fin
covered by a remaining portion of the first mask layer being a first fin device region, a portion of the top surface of the
second fin covered by a remaining portion of the first mask layer being a second fin device region;

forming first insulating structures, a first insulating structure filling a first trench and a corresponding first opening,
a first insulating structure covering a portion of the top surface of a first fin and a portion of the top surface of the
adjacent second fin;

forming a dummy gate structure on each first insulating structure, and a gate structure on each of the first fin device regions
and the second fin device regions; and

forming a stress layer in a first fin device region between a dummy gate structure and a gate structure and forming a stress
layer in a second fin device region between a dummy gate structure and a gate structure.

US Pat. No. 9,831,308

SEMICONDUCTOR DEVICE HAVING VERTICAL SEMICONDUCTOR PILLARS

Semiconductor Manufacturi...

1. A semiconductor device, comprising:
a plurality of substantially vertical semiconductor pillars on a substrate; and
a mask layer overlying the plurality of semiconductor pillars;
wherein a contiguous portion of the hard mask layer connects two or more of the plurality of semiconductor pillars, and
wherein the plurality of semiconductor pillars form a plurality of nanowires.

US Pat. No. 9,646,865

INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND EXPOSURE ALIGNMENT SYSTEM

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating an interconnection structure, comprising:
providing a wafer, wherein a first conductive layer is formed on a surface of the wafer;
patterning the first conductive layer to form a first to-be-connected member and a plurality of first alignment members in
the first conductive layer;

obtaining reference coordinates and measurement coordinates of the plurality of first alignment members;
forming a first dielectric layer covering the wafer and the first to-be-connected member, and forming a first mask layer on
the first dielectric layer;

pattering the first mask layer to form a first opening and a plurality of second alignment members in the first mask layer,
wherein the first opening is used to define a position of a second to-be-connected member;

obtaining reference coordinates and measurement coordinates of the plurality of second alignment members;
forming a second dielectric layer filling the first opening and covering the first mask layer, and forming a second mask layer
on the second dielectric layer;

based on the reference coordinates and the measurement coordinates of the plurality of first alignment members, as well as
the reference coordinates and the measurement coordinates of the plurality of second alignment members, obtaining wafer coordinates
for characterizing a position deviation of the wafer;

obtaining adjustment compensation values according to stacking offsets between a first to-be-connected member, a second to-be-connected
member and an interconnection structure of a preceding wafer;

adjusting a position of the wafer according to the wafer coordinates and the adjustment compensation values;
after adjusting the position of the wafer, patterning the second mask layer to form a second opening in the second mask layer;
and

using the second opening to form the interconnection structure in the first dielectric layer and the second dielectric layer,
wherein the interconnection structure electrical interconnects the first to-be-connected member and the second to-be-connected
member.

US Pat. No. 9,189,590

METHOD AND DEVICE FOR EXAMINING QUALITY OF DUMMY PATTERN INSERTION PROGRAM USED IN CIRCUIT LAYOUT DESIGN

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:
using a dummy pattern insertion program to generate a dummy-based circuit layout;
determining whether the dummy-based circuit layout complies with a set of circuit layout design rules;
using the dummy pattern insertion program to generate a first dummy-inserted circuit layout;
checking whether the first dummy-inserted circuit layout complies with at least one of a set of dummy pattern check rules
and a set of pattern density rules;

using the dummy pattern insertion program to generate a second dummy-inserted circuit layout;
examining whether the second dummy-inserted circuit layout complies with at least one of the set of circuit layout design
rules, the set of dummy pattern check rules, and the set of pattern density rules;

approving, using a device that includes hardware, the dummy pattern insertion program based on the determining, the checking,
and the examining;

generating a semiconductor device layout design using the dummy pattern insertion program; and
manufacturing the semiconductor device using the semiconductor device layout design and a manufacturing apparatus.

US Pat. No. 9,111,871

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

16. A method for forming a semiconductor structure, comprising:
providing a substrate having a plurality of isolation structures, a top surface of the plurality of isolation structures being
higher than a surface of the substrate;

forming a device layer on the substrate and on the plurality of isolation structures;
polishing the device layer using a polishing process, such that the top surface of the plurality of isolation structures are
exposed, with residue remaining on the device layer and on the plurality of isolation structures, wherein:

the polishing process has a substantially same polishing rate for the device layer and for the plurality of isolation structures,
the polishing process includes a first polishing process and a second polishing process after the first polishing process,
a polishing rate during the first polishing process is higher than a polishing rate during the second polishing process, and
after the first polishing process, a distance between a surface of the device layer and the top surface of the plurality of
isolation structures ranges from about 100 Åto about 800 Å; and

removing the residue from the device layer and from the plurality of isolation structures using a non-polishing-removal process,
such that the top surface of the plurality of isolation structures and a top surface of the device layer are substantially
leveled and smooth.

US Pat. No. 9,099,338

METHOD OF FORMING HIGH K METAL GATE

Semiconductor Manufacturi...

1. A method of forming a semiconductor device, the method comprising:
providing a semiconductor substrate having a NMOS region and a PMOS region;
forming dummy gate structures having a stacked sacrificial gate material layer over a sacrificial dielectric layer in the
NMOS and PMOS regions;

concurrently removing the sacrificial gate material layer and the sacrificial dielectric layer to form a groove in the dummy
gate structure in the NMOS region and a groove in the dummy gate structure in the PMOS region;

forming a first high-K dielectric layer in the grooves of the NMOS and PMOS regions and a first metal gate over the first
high-K dielectric layer;

forming a hard mask over the NMOS region;
removing the first metal gate layer and the first high-K dielectric layer of the dummy gate structure in the PMOS region using
the hard mask as a mask to form a channel groove in the semiconductor substrate;

forming a second high-K dielectric layer in the channel groove;
forming a second metal gate over the second high-K dielectric layer; and
removing the hard mask.

US Pat. No. 9,755,659

ASAR ADC CIRCUIT AND CONVERSION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. An asynchronous successive approximation register analog-to-digital converter (ASAR ADC) circuit, configured to covert
a first analog signal into a first digital signal, the ASAR ADC circuit comprising:
a sample/hold circuit having an input terminal configured as an input terminal of the ASAR ADC to input the first analog signal,
and an output terminal configured to output a second analog signal;

a digital-to-analog converter circuit having an input terminal configured to input the first digital signal, and an output
terminal configured to output a third analog signal;

a first voltage comparison circuit, configured to respond to a valid level of a latch signal, and to compare the second analog
signal with the third analog signal respectively inputted into a positive terminal of the first voltage comparison circuit
and a negative terminal of the first voltage comparison circuit to output a first logic level and a second logic level;

a first logic circuit, configured to respond to a valid level of a flag signal, and to identify a comparison result of the
first voltage comparison circuit according to the first logic level and the second logic level respectively inputted into
the first logic circuit to output the first digit signal; and

a pulse generation circuit configured to generate the latch signal and the flag signal with a generation time of the valid
levels of the latch signal and the flag signal independently from the first logic level and the second logic level.

US Pat. No. 9,368,409

SEMICONDUCTOR STRUCTURE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating semiconductor devices, comprising:
providing a substrate with a gate electrode film on the substrate and a gate electrode pattern film on the gate electrode
film, the gate electrode pattern film including a hard mask material layer and a silicon material layer on the hard mask material
layer;

forming at least one pattern layer on the gate electrode pattern film;
using the at least one pattern layer as the etch mask to etch portions of the gate electrode pattern film to expose portions
of the gate electrode film and form a gate electrode pattern layer on the gate electrode film, the gate electrode pattern
layer including a hard mask layer and a silicon layer on the hard mask layer, and sidewalls of the silicon layer in a direction
perpendicular to a first direction having a first poly line width roughness (Poly LWR); and

performing an etch-repairing treatment on the sidewalls of the silicon layer in the direction perpendicular to the first direction
such that the sidewalls of the silicon layer in the direction perpendicular to the first direction have a second Poly LWR,
the second Poly LWR being lower than the first Poly LWR.

US Pat. No. 9,355,712

ELECTROMECHANICAL NONVOLATILE MEMORY

Semiconductor Manufacturi...

1. A semiconductor device comprising:
a semiconductor substrate;
an insulating layer on the semiconductor substrate;
a bit line comprising a TiAl material and disposed on the insulating layer;
a sidewall layer disposed on opposite sides of the bit line; and
a word line comprising a TiN material and disposed on the sidewall layer intersecting the bit line;
wherein the sidewall layer has a thickness larger than the thickness of the bit line, and
an intersection region of the word line and bit line forms a memory cell.

US Pat. No. 9,337,107

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
providing a substrate;
forming a dielectric layer on the substrate, the dielectric layer having therein six openings including a first opening, a
second opening, a third opening, a fourth opening, a fifth opening, and a sixth opening;

forming a gate dielectric layer on sidewalls and a bottom surface of each opening of the six openings;
forming a cap layer on the gate dielectric layer;
forming a first work function layer on the cap layer in the first opening and in the second opening;
forming a diffusion layer on the first work function layer in the first opening, and on the cap layer in both of the fifth
opening and the six opening;

performing an annealing process to diffuse a material of the diffusion layer into the first work function layer and the cap
layer, to form a doped work function layer in the first opening and form a doped cap layer in the fifth opening and in the
sixth opening;

removing a remaining portion of the diffusion layer after the annealing process, and forming a second work function layer
on the cap layer in the fourth opening and on the doped cap layer in the fifth opening, such that transistors respectively
formed with the first opening, the second opening, and the third opening have threshold voltages different from each other,
and transistors respectively formed with the fourth opening, the fifth opening, and the sixth opening have threshold voltages
different from each other; and

after forming the second work function layer, forming a third work function layer in the each opening; and
forming a metal gate on the third work function layer.

US Pat. No. 9,245,897

FLASH MEMORY DEVICE AND RELATED MANUFACTURING METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a memory device, the method comprising:
obtaining a silicon substrate structure, wherein the silicon substrate structure includes a substrate, a floating gate oxide
material layer positioned on the substrate, a floating gate polysilicon material layer positioned on the floating gate oxide
material layer, a first control gate and a second control gate that are positioned on the floating gate polysilicon material
layer, a first control gate sidewall layer and a second control gate sidewall layer that are respectively positioned on two
opposite sides of the first control gate, and a control gate offset oxide layer that is positioned on the first control gate
sidewall layer and positioned between the first control gate sidewall layer and the second control gate;

removing, using the control gate offset oxide layer as a first mask, a portion of the floating gate polysilicon material layer
for forming a floating gate polysilicon structure that includes a first step structure;

forming a masking oxide layer on the control gate offset oxide layer, such that the masking oxide layer is positioned between
the control gate offset oxide layer and the second control gate;

removing, using the masking oxide layer as a second mask, a portion of the floating gate polysilicon structure for forming
a floating gate polysilicon member that includes the first step structure and a second step structure; and

providing a first polysilicon material set between the first control gate and the second control gate for forming an erase
gate.

US Pat. No. 9,209,387

PHASE CHANGE MEMORY AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a phase change memory, comprising:
providing a substrate containing a bottom electrode structure through the substrate, the bottom electrode structure having
a top surface flushed with a top surface of the substrate;

forming a mask layer on the flushed top surfaces of the substrate and the bottom electrode structure;
forming a first opening in the mask layer to expose the top surface of the bottom electrode structure;
forming a spacer on sidewalls and bottom surface portions of the first opening to expose a surface portion of the bottom electrode
structure, wherein the first opening including the spacer therein has a width at a bottom of the first opening less than a
width at a top of the first opening;

forming a heating layer at least on the surface portion of the bottom electrode structure exposed by the spacer, the heating
layer having a top surface lower than a top surface of the mask layer;

forming a phase change layer on the heating layer to completely fill the first opening, wherein the width at the bottom of
the first opening to expose the bottom electrode structure by the spacer bottom ranges from about 10 nm to about 80 nm; and

forming a top electrode on the phase change layer and the mask layer.

US Pat. No. 9,831,313

METHOD TO THIN DOWN INDIUM PHOSPHIDE LAYER

SEMICONDUCTOR MANUFACTURI...

1. A method for thinning down an InP layer formed on a fin structure, comprising:
providing a fin structure, wherein the fin structure is made of InGaAs;
forming an InP layer to cover the fin structure;
converting a surface portion of the InP layer into a Phosphorus-rich layer; and
removing the Phosphorus-rich layer, wherein a remaining portion of the InP layer becomes a thinned-down InP layer.

US Pat. No. 9,455,318

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a well region on the substrate;
forming at least one first gate structure on the well region, wherein the first gate structure includes a gate insulating
layer and a first gate electrode formed on the gate insulating layer,

wherein the first gate electrode is formed having a first enclosed pattern on a surface of the well region;
wherein an area inside the first enclosed pattern is defined as a first region, and an area outside the first enclosed pattern
is defined as a second region;

performing ion implantation on the first region such that the first region has a first conductivity type,
performing ion implantation on the second region such that the second region has a second conductivity type,
wherein the first conductivity type and the second conductivity type are different,
forming a second gate structure on the well region, wherein the second gate structure is spaced apart from the first gate
structure,

wherein the second gate structure includes the gate insulating layer and a second gate electrode formed on the gate insulating
layer,

wherein the second gate electrode is formed having a second enclosed pattern on the surface of the well region, and the second
enclosed pattern is surrounded by the first region,

wherein an area inside the second enclosed pattern is defined as a third region; and
performing ion implantation on the third region such that the third region has the second conductivity type.

US Pat. No. 9,206,030

MEMS CAPACITIVE PRESSURE SENSORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a MEMS capacitive pressure sensor, comprising:
providing a substrate having a first region and a second region;
forming a first dielectric layer on a surface of the substrate;
forming a second dielectric layer having a step surface profile on the first dielectric layer;
forming a first electrode layer on the second dielectric layer;
forming an insulation layer on the first electrode layer and corresponding the step surface profile;
forming a sacrificial layer on the insulation layer and corresponding the step surface profile;
forming a second electrode layer on the sacrificial layer and corresponding the step surface profile; and
removing the sacrificial layer to form a chamber having a step surface profile between the first electrode layer and the second
electrode layer as a base of the capacitive pressure sensor.

US Pat. No. 9,111,942

LOCAL INTERCONNECT STRUCTURE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method of making a local interconnect structure, comprising:
providing a semiconductor substrate;
forming a dielectric layer on the semiconductor substrate;
forming a first film layer patterned on a first surface portion of the dielectric layer;
forming a sidewall spacer having a thickness only on sidewalls of the first film layer to surround the first film layer on
the dielectric layer by a patterning process;

further patterning the sidewall spacer by removing a portion of the sidewall spacer to expose a second surface portion of
the dielectric layer and to leave a pattern made by remainng sidewall spacer;

forming a second film layer on the exposed second surface portion of the dielectric layer, wherein the second film layer has
a top surface substantially flushed with a top surface of the remaining sidewall spacer;

removing the remaining sidewall spacer to form a first opening such that the first opening has a same pattern as the pattern
of the remaining sidewall spacer;

etching the dielectric layer via the first opening to expose a surface of the semiconductor substrate to form a second opening
through the dielectric layer, the second opening having the same pattern; and

filling the second opening with a conductive material to form a local interconnect structure having the same pattern as the
pattern of the remaining sidewall spacer after the further patterning.

US Pat. No. 9,589,884

INTEGRATED CIRCUIT DEVICE WITH RADIO FREQUENCY (RF) SWITCHES AND CONTROLLER

SEMICONDUCTOR MANUFACTURI...

1. An integrated circuit device comprising:
a first semiconductor substrate;
a first transistor set at least partially positioned in the first semiconductor substrate;
a first dielectric layer overlapping the first semiconductor substrate and covering a gate electrode of the first transistor
set;

a first interconnect member at least partially positioned in the first dielectric layer and electrically connected to a terminal
of the first transistor set;

a second semiconductor substrate;
a second transistor set at least partially positioned in the second semiconductor substrate;
a second dielectric layer connected to the first dielectric layer, positioned between the first dielectric layer and the second
semiconductor substrate, and covering a gate electrode of the second transistor set, wherein the first dielectric layer is
positioned between the second dielectric layer and the first semiconductor substrate;

a second interconnect member at least partially positioned in the second dielectric layer and electrically connected to a
terminal of the second transistor set;

a third dielectric layer, wherein the first semiconductor substrate is positioned between the third dielectric layer and the
first dielectric layer;

a third interconnect member extending through the third dielectric layer and electrically connected to the first interconnect
member;

a fourth interconnect member extending through the third dielectric layer and electrically connected to the second interconnect
member;

a fourth dielectric layer overlapping the third dielectric layer, wherein the third dielectric layer is positioned between
the fourth dielectric layer and the first semiconductor substrate; and

a first passive device at least partially positioned in the fourth dielectric layer.

US Pat. No. 9,419,104

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate;
forming a shallow trench isolation (STI) structure in the semiconductor substrate, wherein the STI structure is disposed in
a location corresponding to where a P-well is to be formed;

performing ion implantation to form the P-well and an N-well in the semiconductor substrate, wherein the P-well is formed
surrounding side and bottom portions of the STI structure;

forming a recess in the STI structure;
forming a gate structure on the semiconductor substrate, wherein a portion of the gate structure extends into the recess;
and

performing ion implantation to form a source in the N-well and a drain in the P-well.

US Pat. No. 9,379,206

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

Semiconductor Manufacturi...

1. A semiconductor device fabrication method comprising:
providing a substrate on which a gate structure is formed;
etching the substrate to form a recess at a source/drain position in the substrate;
forming removable sidewalls on side walls of the recess;
etching the recess to form a Sigma shaped recess;
performing selective epitaxial growth of substantially un-doped SiGe in the Sigma shaped recess;
removing the removable sidewalls;
performing epitaxial growth of SiGe doped with P-type impurities in the Sigma shaped recess.

US Pat. No. 9,190,481

TRANSISTORS AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating transistors, comprising:
providing a substrate;
forming at least one dummy gate structure having a dummy gate dielectric layer formed on the substrate and a dummy gate electrode
layer formed on the dummy gate dielectric layer on the substrate;

forming a dielectric film on a surface of the substrate and a top surface of the dummy gate structure;
increasing the density of the dielectric film by performing a thermal annealing process onto the dielectric film;
planarizing the dielectric film having the increased density until the top surface of the dummy gate structure is exposed;
forming a dense layer having an increased density on the dielectric film;
removing the dummy gate dielectric layer and the dummy gate electrode layer to form an opening; and
forming a gate dielectric layer and a gate electrode layer sequentially in the opening.

US Pat. No. 9,153,480

INTERCONNECT STRUCTURE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating an interconnect structure, comprising:
providing a substrate comprising a semiconductor device disposed therein;
forming a porous dielectric layer on the substrate;
performing a first surface treatment to convert a top portion of the porous dielectric layer into an isolation layer on remaining
porous dielectric layer, such that the isolation layer converted from the top portion of the porous dielectric layer has a
density sufficiently higher than the remaining porous dielectric layer to prevent moisture absorption of the porous dielectric
layer,

wherein, prior to performing the first surface treatment, a pre-treatment is performed on the to portion of the porous dielectric
layer to compact the to-be-formed isolation layer with the remaining porous dielectric layer to prepare the top portion of
the porous dielectric layer for the first surface treatment, wherein the pre-treatment uses ozone; and

forming an interconnect at least passing through the isolation layer and passing through the remaining porous dielectric layer
to provide electrical connection to the semiconductor device in the substrate.

US Pat. No. 9,799,728

THREE-DIMENSIONAL TRANSISTOR AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a three-dimensional (3D) transistor, comprising:
providing a semiconductor substrate;
forming an active region and two isolation structures on the semiconductor substrate, wherein the active region is formed
between the two isolation structures;

forming a photoresist layer on the active region and the isolation structures;
forming an opening in the photoresist layer to expose a top surface of the active region and a first portion of a top surface
of each isolation structure close to the activation region;

forming a trench on each side of the active region by removing a portion of a corresponding isolation structure exposed in
the opening through an etching process performed along the opening using the photoresist layer as an etch mask, wherein a
portion of the active region between the two trenches becomes a three-dimensional fin structure after etching; and

removing the photoresist layer.

US Pat. No. 9,431,516

MOS TRANSISTOR AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method of forming a MOS transistor, comprising:
providing a semiconductor substrate;
forming a gate structure on the semiconductor substrate, the gate structure including a gate dielectric layer and a gate on
the gate dielectric layer;

forming a lightly doped region by a light ion implantation in the semiconductor substrate on both sides of the gate structure;
forming a first halo region by a first halo implantation to substantially cover the formed lightly doped region in the semiconductor
substrate;

forming a groove in the semiconductor substrate on the both sides of the gate structure;
prior to forming a source and a drain in the groove, forming a second halo region in the semiconductor substrate by a second
halo implantation performed into a groove sidewall that is adjacent to the gate structure, wherein the second halo region
covers: substantially the lightly doped region and at least a portion of the first halo region, in the semiconductor substrate
under the gate, and substantially covers the same groove sidewall that is adjacent to the gate structure; and

forming the source and the drain in the groove.

US Pat. No. 9,422,157

METHOD FOR TEMPERATURE COMPENSATION IN MEMS RESONATORS WITH ISOLATED REGIONS OF DISTINCT MATERIAL

SEMICONDUCTOR MANUFACTURI...

1. A method of forming a MEMS resonator comprising:
forming a first structural material on a substrate;
patterning the first structural material;
forming over the first structural material, a second structural material having a different Young's modulus temperature coefficient
than the first structural material;

planarizing the second structural material to expose the first structural material;
patterning a resonator containing both the first and second structural materials; and
anchoring the patterned resonator to an anchor, where the first structural material is confined to a region of the resonator
having a longest dimension that is shorter than a distance between the anchor and a point of the resonator furthest from the
anchor.

US Pat. No. 9,209,299

TRANSISTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a transistor, comprising:
providing a substrate;
forming a gate structure on a surface of the substrate;
forming a first doped region in the substrate by a first ion implantation on both sides of the gate structure;
forming an opening within the first doped region, wherein the opening has a depth in the substrate less than a depth of the
first doted region, and a bottom of the first doped region in the substrate is outside of the opening to surround a bottom
of the opening;

forming a stress layer to fill up the opening within the first doped region on the both sides of the gate structure, wherein
the stress layer has a thickness in the substrate less than the depth of the first doped region, and the bottom of the first
doped region in the substrate is outside of the stress layer to surround a bottom of the stress layer; and

forming a second doped region within the stress layer, wherein the second doped region and the first doped region form a source
region or a drain region.

US Pat. No. 9,176,400

SYSTEM AND METHOD FOR REDUCING CONTAMINATION IN EXTREME ULTRAVIOLET LITHOGRAPHY LIGHT SOURCE

SEMICONDUCTOR MANUFACTURI...

1. A system for extreme ultraviolet (EUV) lithography light source, comprising:
a pulsed laser radiation apparatus configured to provide laser radiation;
an EUV light excitation source material configured to receive the laser radiation to generate an EUV light, wherein the laser
radiation generates droplets from the EUV light excitation source material;

a collector configured to collect the EUV light, comprising: a plurality of reflective mirrors surrounding the EUV light excitation
source material, wherein the plurality of reflective mirrors are movable; and

a mirror control system synchronized with the pulsed laser radiation apparatus and configured to set the plurality of reflective
mirrors to be simultaneously in a reflective state for reflecting the EUV light and configured to set the plurality of reflective
mirrors to be simultaneously in a non-reflective state by rotating the plurality of reflective mirrors to be substantially
parallel to a corresponding flight direction of droplets for preventing contamination by the droplets.

US Pat. No. 9,147,749

TRANSISTORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a transistor, comprising:
providing a semiconductor substrate;
forming a trench in the semiconductor substrate by etching the semiconductor substrate;
forming a threshold-adjusting layer on the semiconductor substrate in the trench;
forming a carrier drifting layer on the threshold-adjusting layer;
performing a plasma treatment process on the carrier drifting layer; and
forming a gate structure on the carrier drifting layer corresponding to the trench, wherein:
the threshold-adjusting layer is a semiconductor layer doped with a certain type of threshold-adjusting ions to adjust the
threshold voltage of the transistor.

US Pat. No. 9,093,354

THREE-DIMENSIONAL QUANTUM WELL TRANSISTOR

SEMICONDUCTOR MANUFACTURI...

1. A transistor comprising:
a semiconductor substrate;
a fin part and an insulating layer each disposed on the semiconductor substrate, the insulating layer having a top surface
lower than a top surface of the fin part;

a quantum well (QW) layer disposed on the fin part;
a barrier layer disposed on the QW layer;
a gate structure disposed on the barrier layer across the fin part and on the insulating layer, the gate structure including
a gate dielectric layer on each of the insulating layer and the barrier layer, and a gate electrode on the gate dielectric
layer;

a source and a drain disposed on both sides of the gate structure and within the fin part, each of the source and the drain
having a side edge aligned with a sidewall edge of the gate structure; and

a sidewall spacer disposed on both sidewalls of the gate electrode and on surface of each of the source and the drain such
that a channel region in the QW layer under the gate structure having a same width with the gate structure and the channel
region does not extend to under the sidewall spacer.

US Pat. No. 9,865,505

METHOD FOR REDUCING N-TYPE FINFET SOURCE AND DRAIN RESISTANCE

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate structure, the substrate structure comprising:
a semiconductor substrate including a first semiconductor region;
a first semiconductor fin on the first semiconductor region;
a first gate structure on a portion of the surface of the first semiconductor fin;
a first mask layer on the first semiconductor fin and the first gate structure;
forming a second mask layer on the substrate structure;
etching the first mask layer and the second mask layer to expose a portion of a first semiconductor fin that is not covered
by the first gate structure;

performing a first ion implantation on an exposed portion of the first semiconductor fin to introduce impurities into a portion
of the first semiconductor fin located below the first gate structure;

etching the first semiconductor fin to remove at least a portion of an exposed portion of the first semiconductor fin; and
epitaxially growing a first semiconductor material on the remaining portions of the first semiconductor fin to form a first
source region and a first drain region.

US Pat. No. 9,706,632

EUV LIGHT SOURCE AND EXPOSURE APPARATUS

SEMICONDUCTOR MANUFACTURI...

1. An extreme ultraviolet (EUV) light source, comprising:
a spray nozzle array having a plurality of spray nozzles configured to spray a plurality of rows of droplets to an irradiating
position;

a laser source configured to generate a first laser beam and a second laser beam and cause the first laser beam and the second
laser beam to alternately bombard the rows of droplets to generate EUV light;

a focusing mirror having at least two first sub-focusing mirrors and at least two second sub-focusing mirrors;
a first driving device having at least two first sub-driving devices and at least two second sub-driving device, each of first
driving devices driving one of the first sub-focusing mirrors and each of the second sub-driving devices driving one of the
second sub-focusing mirrors; and

a control unit configured to synchronously control the spray nozzle array, the laser source and the focusing mirror.

US Pat. No. 9,455,255

FIN-TYPE FIELD EFFECT TRANSISTOR AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method of manufacturing a fin-type field effect transistor, comprising:
sequentially forming a first mask and a second mask on a semiconductor substrate;
patterning the second mask;
forming a third mask on the second mask, and patterning the third mask in accordance with a fin pattern of the fin-type field
effect transistor;

etching the semiconductor substrate, the first mask, and the second mask through the third mask, wherein a first trench is
formed in the semiconductor substrate;

removing the third mask;
etching the first mask through the second mask, and subsequently removing the second mask;
etching the semiconductor substrate through the first mask to form a plurality of fins and a second trench disposed between
adjacent fins, wherein the etching of the semiconductor substrate further deepens the first trench such that a depth of the
first trench is greater than a depth of the second trench; and

forming the fin-type field effect transistor on the semiconductor substrate, wherein a dielectric material is disposed in
the first trench and the second trench.

US Pat. No. 9,450,075

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:
a base dielectric layer;
a semiconductor substrate layer disposed on the base dielectric layer;
an interfacial dopant layer disposed at an interface between the base dielectric layer and the semiconductor substrate layer
without performing a post-doping epitaxial deposition process, and continuously extending between adjacent shallow trench
isolation (STI) structures; and

a transistor disposed within and on a surface of the semiconductor substrate layer, wherein the transistor comprises:
a gate dielectric layer disposed on the semiconductor substrate layer;
a gate electrode disposed on the gate dielectric layer;
a source electrode and a drain electrode disposed within the semiconductor substrate layer on opposite sides of the gate electrode;
and

an undoped channel region, a base dopant region, and a threshold voltage setting region, wherein the undoped channel region,
the base dopant region, and the threshold voltage setting region are disposed within the semiconductor substrate layer,

wherein the undoped channel region is disposed between the source electrode and the drain electrode, and the base dopant region
and the threshold voltage setting region extend beneath the source electrode and the drain electrode, and

wherein the undoped channel region is disposed beneath the gate electrode, the base dopant region is disposed below the undoped
channel region, and the threshold voltage setting region is disposed between the undoped channel region and the base dopant
region.

US Pat. No. 9,449,950

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor device comprising:
a first substrate;
a second substrate;
a dielectric layer that is positioned between the first substrate and the second substrate and has a hole;
a first conductive member that is positioned in the dielectric layer and includes a first conductive material portion and
a first etch-stop layer formed on the first conductive material portion;

a second conductive member that is positioned in the dielectric layer and includes a second conductive material portion and
a second etch-stop layer formed on the second conductive portion, wherein the second conductive member is spaced from the
first conductive member, and is positioned closer to the second substrate than the first conductive member, and wherein the
hole of the dielectric layer exposes a top and side portion of the first etch-stop layer and a lateral portion of the first
conductive material portion of the first conductive member, and a top portion of the second etch-stop layer of the second
conductive member; and

a third conductive member that contacts the top and side of the first etch-stop layer and the lateral portion of the first
conductive material portion of the first conductive member and the top portion of the second etch-stop layer of the second
conductive member through the hole.

US Pat. No. 9,406,527

SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND RELATED SEMICONDUCTOR WAFER

Semiconductor Manufacturi...

1. A method for processing a wafer in a process of manufacturing semiconductor devices, the method comprising:
using a first slurry set to perform a first chemical mechanical polishing process on the wafer, wherein the wafer includes
a plurality of metal gate structures;

using a second slurry set to perform a second chemical mechanical polishing process on the wafer, wherein a concentration
of a slurry material in the second slurry set is less than a concentration of the slurry material in the first slurry set;

providing a set of hydrogen peroxide onto the polishing pad when the second slurry set is being provided onto the polishing
pad, wherein the hydrogen peroxide is provided at a flow rate greater than the flow rate at which the second slurry is provided;

performing a cleaning process on the wafer; and
providing an anti-reflective coating on the wafer.

US Pat. No. 9,196,725

SEMICONDUCTOR STRUCTURE HAVING COMMON GATE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor structure having a common gate, comprising:
providing a semiconductor substrate having a first transistor region, a second transistor region, and an isolation structure
in the semiconductor substrate formed between the first transistor region and the second transistor region;

forming a dummy gate structure on each surface of the first transistor region, the second transistor region, and the isolation
structure of the semiconductor substrate;

forming an interlayer dielectric layer on the semiconductor substrate, wherein the interlayer dielectric layer has a top surface
leveled with the dummy gate structure;

etching a first portion of the dummy gate structure corresponding to the first transistor region to form a first trench, and
forming a first high-K gate dielectric layer on an inner wall of the first trench, and forming a first metal gate electrode
on the first high-K gate dielectric layer, to form a first metal gate;

etching a second portion of the dummy gate structure corresponding to the second transistor region to form a second trench,
and forming a second high-K gate dielectric layer on an inner wall of the second trench, and forming a second metal gate electrode
on the second high-K gate dielectric layer, to form a second metal gate, wherein the first metal gate and the second metal
gate have a boundary located on the surface of the isolation structure;

forming a third trench over the isolation structure by etching at least a portion of the first metal gate and a portion of
the second metal gate at the boundary; and

forming a conductive material layer in the third trench over the isolation structure and connecting the first metal gate electrode
of the first metal gate with the second metal gate electrode of the second metal gate.

US Pat. No. 9,166,050

TRANSISTOR AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a transistor, comprising:
providing a substrate;
forming a gate structure on the substrate;
forming a stress layer in the substrate on both sides of the gate structure;
doping barrier ions in the stress layer to form a barrier layer in the stress layer, wherein the barrier layer has a preset
distance from a surface of the stress layer; and

forming an electrical contact layer using a portion of the stress layer on the barrier layer by a salicide process, the electrical
contact layer containing a first metal element, the first metal element having a resistivity lower than a resistivity of a
silicidation metal, wherein the barrier layer prevents atoms of the first metal element from diffusing to a bottom of the
stress layer.

US Pat. No. 9,147,746

MOS TRANSISTORS AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating an MOS transistor, comprising:
providing a semiconductor substrate;
forming a metal gate structure on the semiconductor substrate, the metal gate structure including a sidewall spacer;
forming a source region and a drain region in the semiconductor substrate at both sides of the metal gate structure;
forming a contact-etch-stop layer on the source region, the drain region and the metal gate structure;
forming an interlayer dielectric layer on the contact-etch-stop layer and the metal gate structure;
forming a first opening in the interlayer dielectric layer with a portion of the sidewall spacer and the contact-etch-stop
layer left on the bottom of the first opening covering the semiconductor substrate and the drain region within the first opening
but without exposing the semiconductor substrate and any of the drain region, wherein a height of the portion of the sidewall
spacer and the contact-etch-stop layer left on the bottom of the first opening is in a range of approximately 50Å-300Å;

forming a first contact hole in the interlayer dielectric layer by removing the portion of the sidewall spacer and contact-etch-stop
layer left on the bottom of the first opening to expose the semiconductor substrate and the drain region on the bottom of
the first opening; and

forming a first conductive via connecting with the metal gate structure and the drain region in the first contact hole.

US Pat. No. 9,823,271

SEMICONDUCTOR TESTING STRUCTURES AND SEMICONDUCTOR TESTING APPARATUS

SEMICONDUCTOR MANUFACTURI...

1. A semiconductor testing structure, comprising:
a dummy wafer;
an adhesive layer on the dummy wafer;
a dielectric layer having a first surface bonded on the adhesive layer; and
a device structure in the dielectric layer and having a testing surface even and smooth with a second surface of the dielectric
layer.

US Pat. No. 9,352,957

SEMICONDUCTOR DEVICE, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for manufacturing a semiconductor device, the method comprising:
providing a first substrate structure that has a trench;
providing a getter in the trench, wherein the getter overlaps a first portion of a bottom surface of the trench; and
after the getter has been provided in the trench, combining the first substrate structure with a second substrate structure
that includes an inductor, wherein the inductor overlaps a second portion of the bottom surface of the trench without overlapping
the getter in a direction perpendicular to the bottom surface of the trench.

US Pat. No. 9,196,697

SEMICONDUCTOR DEVICE WITH AN ALUMINUM ALLOY GATE

Semiconductor Manufacturi...

1. A semiconductor device, comprising:
a semiconductor substrate;
a gate insulating layer over the substrate, the gate insulating layer having a dielectric constant greater than 10;
a first barrier layer on the gate insulating layer;
an aluminum alloy gate on the first barrier layer, the aluminum alloy gate formed as an alloy mixture of aluminum and at least
a second non-alloy metal, and

a layer of the second non-alloy metal formed between the aluminum alloy gate and the first barrier layer.

US Pat. No. 9,136,469

PHASE CHANGE MEMORIES

SEMICONDUCTOR MANUFACTURI...

1. A phase change memory, comprising:
a semiconductor substrate having a bottom electrode connecting with one or more of semiconductor devices;
a first dielectric layer on the semiconductor substrate;
a loop-shape electrode embedded in the first dielectric layer, a top surface of the loop-shape electrode leveling with a top
surface of the first dielectric layer;

a second dielectric layer on the first dielectric layer and the loop-shape electrode;
a phase change layer in the second dielectric layer such that a contact area between the phase change layer and the loop-shape
electrode is controlled by a thickness of the loop-shape electrode; and

a top electrode electrically connecting with the phase change layer, wherein:
a portion of the loop-shape electrode is covered by an isolation structure, the phase change layer is covered by a contact
metal layer, and the contact metal layer is covered by a third dielectric layer.

US Pat. No. 9,136,183

TRANSISTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a complementary junctionless transistor device comprising:
providing a semiconductor substrate, wherein the semiconductor substrate includes an N-field-effect transistor (NFET) portion
and a P-field-effect transistor (PFET) portion neighboring with each other;

forming an isolation layer on the semiconductor substrate and an active layer on the isolation layer, wherein the active layer
and the isolation layer are made of materials having an etching selectivity, and the semiconductor substrate and the isolation
layer are made of materials having an etching selectivity;

forming a P-well in the NFET portion of the semiconductor substrate, and forming an N-well in the PFET portion of the semiconductor
substrate;

forming a P-doped isolation layer by doping a portion of the isolation layer on the NFET portion, and forming an N-doped isolation
layer by doping a portion of the isolation layer on the PFET portion neighboring with the NFET portion;

forming an N-doped active layer by doping a portion of the active layer on the P-doped isolation layer, and forming a P-doped
active layer by doping a portion of the active layer on the N-doped isolation layer;

etching the active layer and the isolation layer to form an opening to expose a surface of the semiconductor substrate covering
an interface portion between the NFET portion and PFET portion;

removing a portion of the P-doped isolation layer to suspend the N-doped active layer from opposing ends of the N-doped active
layer, and removing a portion of the N-doped isolation layer to suspend the P-doped active layer from opposing ends of the
P-doped active layer;

forming a dielectric layer between the N-doped active layer and the semiconductor substrate, between the P-doped active layer
and the semiconductor substrate, and in the opening;

forming a first gate structure on the N-doped active layer disposed on a remaining P-doped isolation layer on the NFET portion,
forming a second gate structure on the P-doped active layer disposed on a remaining N-doped isolation layer on the PFET portion;
and

forming an N-doped source and an N-doped drain in the N-doped active layer on both sides of the first gate structure, and
forming a P-doped source and a P-doped drain in the P-doped active layer on both sides of the second gate structure.

US Pat. No. 9,837,311

CONDUCTIVE PLUG STRUCTURE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a conductive plug structure, comprising:
providing a substrate;
forming a mask layer having an opening on a surface of the substrate;
etching the substrate to form a contact hole using the mask layer as an etching mask;
after forming the contact hole using the mask layer as the etching mask, etching the mask layer to increase a feature size
of the opening;

forming an insulation layer on an inner surface of the opening, an inner surface of the enlarged opening and a surface of
the mask layer to have more edge corners, a thickness of the insulation layer being greater than a thickness of the remaining
mask layer;

forming a conductive layer filling the contact hole on the insulation layer; and
planarizing the conductive layer and the insulation layer until a surface of the mask layer is exposed.

US Pat. No. 9,922,878

HYBRID INTEGRATED SEMICONDUCTOR TRI-GATE AND SPLIT DUAL-GATE FINFET DEVICES AND METHOD FOR MANUFACTURING

Semiconductor Manufacturi...

1. A method for fabricating an integrated circuit having at least a tri-gate FinFET and a dual-gate FinFET, the method comprising:
providing a semiconductor on insulator (SOI) substrate, the SOI substrate comprising a semiconductor layer overlying an insulator
layer, the semiconductor layer having a surface region;

implanting impurities into the semiconductor layer for a threshold voltage adjustment;
forming a hard mask overlying the surface region;
patterning the hard mask to form a first hard mask cap portion and a second hard mask cap portion;
etching the semiconductor layer using the patterned hard mask as an etch mask to form a first fin and a second fin, each of
the first and second fins having side surfaces extending along a longitudinal direction of the fins;

removing the second hard mask cap portion overlying the second fin to expose a top surface of the second fin while keeping
the first hard mask cap portion;

forming a gate dielectric layer completely over the side surfaces of the first fin and the side surfaces and the exposed top
surface of the second fin while exposing the first hard mask cap portion;

forming a conductive layer overlying the gate dielectric layer and in direct contact with the exposed first hard mask cap
portion;

selectively etching the conductive layer to form a first gate structure for the first fin and a second gate structure for
the second fin;

forming an interlayer dielectric layer overlying the first and second gate structures;
planarizing the interlayer dielectric layer by chemical mechanical polishing (CMP) using the first hard mask cap portion as
a polish stop; and

forming elevated source structures overlying source regions and elevated drain structures overlying drain regions,
wherein the gate dielectric layer formed on the side surfaces of the first fin comprises a portion disposed on opposite sides
of the first gate structure.

US Pat. No. 9,825,091

MEMORY CELL STRUCTURES

Semiconductor Manufacturi...

16. A memory cell array, comprising:
M rows and N columns of memory cells, M and N being a natural number greater than one, wherein each memory cell comprises:
a first diode;
a second diode; and
a random access memory cell element having a first end and a second end opposite the first end,
wherein the first diode and the random access memory cell element are series connected between a bit line and a word line,
wherein the second diode and the random access memory cell element are series connected in series between the word line and
a reset line,

wherein a set path is formed through the first diode and the random access memory cell element, and
wherein a reset path is formed through the random access memory cell element and the second diode.

US Pat. No. 9,653,283

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

Semiconductor Manufacturi...

1. A method of manufacturing a semiconductor device, comprising:
providing a semiconductor substrate including a first transistor, a second transistor, a trench disposed between the first
transistor and the second transistor, and a dummy gate disposed on the first transistor, the second transistor, and the trench;

selectively forming a photoresist on a first portion of the dummy gate over the first transistor and exposing a second portion
of the dummy gate over the second transistor;

removing the second portion of the dummy gate on the second transistor using the photoresist, so that an edge surface of the
dummy gate between the first transistor and the second transistor above the trench is exposed while the dummy gate remains
over more than half of the first transistor;

performing a treatment using hydrogen (H2) on a surface of the semiconductor substrate and the edge surface of the dummy gate, so as to remove residue materials left
behind from the removal of the dummy gate; and

forming a metal gate on the second transistor.

US Pat. No. 9,428,377

METHODS AND STRUCTURES FOR THIN-FILM ENCAPSULATION AND CO-INTEGRATION OF SAME WITH MICROELECTRONIC DEVICES AND MICROELECTROMECHANICAL SYSTEMS (MEMS)

SEMICONDUCTOR MANUFACTURI...

1. A microshell structure, comprising:
a lower microshell layer disposed over a MEMS region and an underlying substrate;
one or more lower release holes defined in the lower microshell layer;
an upper microshell layer disposed over the lower microshell layer;
one or more upper release holes defined in the upper microshell layer;
one or more open cavities or open areas defined under the upper microshell layer; and
a sealing layer disposed on the upper microshell layer that seals the upper release holes in the upper microshell layer;
where the lower release holes are laterally offset from the upper release holes such that none of the lower release holes
are aligned with any of the upper release holes.

US Pat. No. 9,514,994

FINFET DEVICE AND FABRICATION METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate having a first region and a second region;
forming a plurality of fins on the substrate;
forming a plurality of doping regions with different doping concentrations in the fins in the first region;
forming a plurality of dummy gate structures over the plurality of fins;
forming source and drain regions in the plurality of fins at both sides of the dummy gate structures;
removing the dummy gate structures to form a plurality of openings to expose the plurality of fins;
forming a plurality of work function layers with different work functions on the exposed fins in the openings in the second
region; and

forming gate structures in the openings.

US Pat. No. 9,508,717

INTEGRATED CIRCUIT DEVICE AND REPAIR METHOD THEREOF

SEMICONDUCTOR MANUFACTURI...

1. An integrated circuit (IC) device, comprising:
a PMOS transistor, including a substrate, a gate dielectric layer on the substrate, and a gate on the gate dielectric layer;
and

a repair circuit, including an NMOS transistor and configured to apply a negative bias voltage to the substrate of the PMOS
transistor, when the PMOS transistor is in an OFF state, to cause injections of electrons in the substrate into the gate dielectric
layer to neutralize holes caused by negative bias temperature instability (NBTI) effect,

wherein:
the repair circuit is further configured to stop applying the negative bias voltage to the substrate of the PMOS transistor
when the PMOS transistor is in an ON state, and

the NMOS transistor has a gate connecting to the gate of the PMOS transistor, has a source connecting to the substrate of
the PMOS transistor, and has a drain configured to receive an input voltage having a negative value as a highest voltage level
provided to the substrate of the PMOS transistor.

US Pat. No. 9,159,785

SEMICONDUCTOR DEVICE HAVING BURIED LAYER AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a buried layer, comprising:
providing a semiconductor substrate including a hard mask layer thereon, wherein the hard mask layer has a plurality of through-openings;
forming a plurality of deep trenches in the semiconductor substrate using the hard mask layer as a mask;
doping a bottom of each of the plurality of deep trenches in the semiconductor substrate to form a plurality of heavily-doped
regions;

connecting one or more of the plurality of heavily-doped regions to form the buried layer in the semiconductor substrate;
after the buried layer is formed, forming an oxide layer on an inner surface of sidewalls and a bottom of each of the plurality
of deep trenches; and

filling the plurality of deep trenches with a filling material on sidewalls and a bottom of the oxide layer in each deep trench
to form isolation structures between adjacent active regions in the semiconductor substrate.

US Pat. No. 9,136,164

SEMICONDUCTOR DEVICE AND FABRICATION METHOD

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
providing a substrate comprising a first region and a second region;
providing first metal layers in the first region and the second region of the substrate, wherein the first metal layers have
a top surface coplanar with a top surface of the substrate;

forming an interlayer dielectric layer over the substrate, wherein the interlayer dielectric layer comprises a trench in the
first region, and the interlayer dielectric layer in the second region has a top surface coplanar with a bottom of the trench
in the first region;

forming through-holes in the interlayer dielectric layer, each through-hole corresponding to one first metal layer in the
first region and the second region;

forming a polymer layer to fill the through-holes and the trench in the interlayer dielectric layer and to cover the top surface
of the interlayer dielectric layer in the first and second regions, wherein the polymer layer has a different solubility in
an exposed area and in a non-exposed area;

exposing and developing the polymer layer to form vias, each including an upper via in the polymer layer and a lower via in
the interlayer dielectric layer, wherein each via is formed on a corresponding first metal layer in the first and second regions;

forming a second metal layer to fill each via and to electrically connect to the corresponding first metal layer; and
removing the polymer layer between adjacent second metal layers to form air gaps between the adjacent second metal layers
in the second region.

US Pat. No. 9,490,260

METHOD FOR FABRICATING A SEMI-FLOATING GATE TRANSISTOR

Semiconductor Manufacturi...

1. A method for manufacturing a semi-floating gate transistor structure, the method comprising:
providing a substrate having a first N-well region and a second N-well region separated from each other;
forming an oxide layer disposed on the first N-well region of the substrate;
forming a groove in the oxide layer to expose a surface region of the substrate;
performing an N-type ion implantation into the substrate to form a heavily doped N-type region in the surface region of the
substrate corresponding to a location of the groove in the oxide layer; and

forming a P-type doped first polysilicon layer on the oxide layer, the P-type doped first polysilicon layer filling the groove
in the oxide layer.

US Pat. No. 9,450,178

MAGNETORESISTIVE SENSOR, RELATED MANUFACTURING METHOD, AND RELATED ELECTRONIC DEVICE

Semiconductor Manufacturi...

1. A method for manufacturing a magnetoresistive sensor, the method comprising:
forming a trench structure in a substrate, wherein the forming the trench structure comprises performing a wet etching process
on a substrate material member, wherein the trench structure has a first side, a second side, and a third side, wherein the
second side is connected through the first side to the third side, wherein the second side is at a first obtuse angle with
respect to a side of the substrate, and wherein the third side is at a second obtuse angle with respect to the side of the
substrate;

forming a first magnetic element on the first side of the trench structure;
forming a second magnetic element on the second side of the trench structure; and
forming a third magnetic element on the third side of the trench structure, wherein the first, the second, and the third magnetic
element are spaced apart from one another.

US Pat. No. 9,431,405

METHOD FOR FORMING FLASH MEMORY DEVICES

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a flash memory device, comprising:
providing a semiconductor substrate;
forming a first polysilicon layer on a surface of the semiconductor substrate;
forming a hard mask layer on the first polysilicon layer;
forming a plurality of first openings to expose the first polysilicon layer in the hard mask layer and first polysilicon silicon
layer by etching the hard mask layer and the first polysilicon, forming a plurality of grooves in the semiconductor substrate
by etching the semiconductor substrate along the first openings;

forming liner oxide layers by oxidizing the first polysilicon layer exposed by the first openings;
forming shallow trench isolation structures covering the liner oxide layers by filling the first openings and the grooves
with an isolation material;

forming second openings by removing the hard mask layer and a non-oxidized first polysilicon layer;
forming a tunnel oxide layer on the surface of the semiconductor substrate at a bottom of each of the second openings; and
forming a floating gate on each of the tunnel oxide layers.

US Pat. No. 9,923,065

FABRICATING METHOD OF FIN-TYPE SEMICONDUCTOR DEVICE

SEMICONDUCTOR MANUFACTURI...

1. A method for forming a semiconductor device, comprising:
providing a semiconductor substrate including a plurality of fins projected on a surface of the semiconductor substrate, wherein
a width of a bottom portion of one fin is larger than or equal to ? of a width of a top portion of the one fin;

forming an insulating film on top portions and side walls of the plurality of fins, wherein the insulating film is located
on the surface of the semiconductor substrate, and a thermal conductivity of the insulating layer is larger than a thermal
conductivity of silicon oxide; and

etching a portion of the insulating film to expose top surfaces and a part of side walls of the plurality of fins and to form
an insulating layer that has a surface lower than the top surfaces of the plurality of fins.

US Pat. No. 9,598,279

SEMICONDUCTOR STRUCTURES AND FABRICATION METHODS THEREOF

SEMICONDUCTOR MANUFACTURI...

1. A method for fabricating a semiconductor structure, comprising:
providing a substrate having a device region;
forming a sacrificial layer on a surface of the substrate in the device region;
forming a device layer having a plurality of openings exposing a portion the sacrificial layer on the sacrificial layer;
removing the sacrificial layer to expose the surface of the substrate in the device region; and
forming a cavity in the substrate in the device region by simultaneously etching the surface of the substrate in the device
region exposed by the removed sacrificial layer and the plurality of openings using an anisotropic etching process.