US Pat. No. 10,658,511

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor device, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate, and
a first fin and a second fin positioned on the substrate;
depositing a first interlayer dielectric layer on the semiconductor structure;
performing first partial etching on the first interlayer dielectric layer to expose a top of the first fin;
after the top of the first fin is exposed, removing a part of the first fin to form a first groove;
epitaxially growing a first electrode in the first groove;
performing second partial etching on the first interlayer dielectric layer to expose a top of the second fin;
after the top of the second fin is exposed, removing a part of the second fin to form a second groove, wherein the second groove is separated from the first groove; and
epitaxially growing a second electrode in the second groove.

US Pat. No. 10,707,117

INTERCONNECTION STRUCTURE AND METHOD FOR MANUFACTURING SAME

Semiconductor Manufacturi...

1. A method for manufacturing an interconnection structure, comprising:providing a substrate structure, wherein the substrate structure comprises:
a substrate,
an interlayer dielectric layer on the substrate,
a plurality of first through holes running through the interlayer dielectric layer, and
a first metal layer filling the plurality of first through holes;
forming a through hole structural layer on the substrate structure, wherein the through hole structural layer comprises a dual-damascene through hole structure, the dual-damascene through hole structure comprising:
a second through hole and a third through hole in the through hole structural layer, and
an opening on the second through hole and the third through hole,
wherein the first metal layer in one of the first through holes of the plurality of first through holes is exposed in the second through hole,
wherein the first metal layer in another one of the plurality of first through holes is exposed in the third through hole, and
wherein the second through hole, the third through hole, and a part of the through hole structural layer between the second through hole and the third through hole are exposed in the opening;
filling a second metal layer in the second through hole and the third through hole, wherein an upper surface of the second metal layer is lower than an upper surface of the part of the through hole structural layer between the second through hole and the third through hole;
etching the part of the through hole structural layer between the second through hole and the third through hole so that the upper surface of the part is lower than the upper surface of the second metal layer; and
after etching the part of the through hole structural layer, forming, in the opening, a third metal layer connected to the second metal layer.

US Pat. No. 10,714,343

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base;
forming a to-be-etched material layer on the base;
forming a mask material layer on the to-be-etched material layer;
performing a first doping treatment on a partial region of the mask material layer, wherein:
the first doping treatment is suitable for increasing an etching selection ratio of the mask material layer that has not undergone the first doping treatment to the mask material layer that has undergone the first doping treatment,
after the first doping treatment is performed, the mask material layer comprises a first mask-material-layer part and a to-be-removed second mask-material-layer part, and
the first mask-material-layer part is a part that has undergone the first doping treatment in the mask material layer, or, the second mask-material-layer part is a part that has undergone the first doping treatment in the mask material layer;
after the first doping treatment is performed, forming, in the mask material layer, a first trench exposing a part of the to-be-etched material layer, wherein the first trench is at least located in the first mask-material-layer part;
after the first trench is formed, removing the second mask-material-layer part, and forming a second trench exposing a part of the to-be-etched material layer in the remaining mask material layer;
removing the to-be-etched material layer exposed from the first trench and the second trench, and forming a target pattern layer; and
after the target pattern layer is formed, removing the remaining mask material layer.

US Pat. No. 10,622,441

SEMICONDUCTOR APPARATUS AND MANUFACTURING METHOD FOR SAME

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor apparatus, comprising:providing a substrate structure, the substrate structure comprising:
a substrate,
a fin located on the substrate and extending along a first direction, and
an isolation region located around the fin, where an upper surface of the isolation region is lower than an upper surface of the fin, the isolation region comprising a first isolation region and a second isolation region, the first isolation region being located on a side surface of the fin that is in the first direction, and the second isolation region being located on a side surface of the fin that is in a second direction that is different from the first direction;
forming, on the substrate structure, a sacrificial layer;
etching the sacrificial layer to form an opening, the opening exposing an upper surface of the first isolation region and exposing a part, which is located above the first isolation region, of the side surface of the fin adjacent to the first isolation region;
filling the opening with an insulating material to form a third isolation region on the first isolation region, an upper surface of the third isolation region being higher than the upper surface of the fin; and
removing the sacrificial layer.

US Pat. No. 10,629,646

IMAGE SENSOR INCLUDING DOPED REGIONS AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A method for manufacturing an image sensor, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises: a semiconductor substrate, and a first active region located on the semiconductor substrate, the first active region comprising a first doped region, a second doped region abutting against the first doped region, a third doped region abutting against the first doped region, and a fourth doped region abutting against the third doped region, wherein the second doped region is located at an upper surface of the first active region;
forming a semiconductor layer on an upper surface of the second doped region; and
forming a contact connected to the semiconductor layer;
wherein the semiconductor structure further comprises a first gate structure located on the first active region, the first gate structure comprising a first gate electrode located above a portion at which the first doped region abuts against the third doped region, and only a portion of an upper surface of the fourth doped region is located below the first gate electrode.

US Pat. No. 10,593,550

METHOD FOR MANUFACTURING SEMICONDUCTOR STRUCTURE

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor structure, comprising:forming a semiconductor layer at a surface of a to-be-etched material layer on a substrate;
after forming the semiconductor layer, forming an amorphous carbon layer on the semiconductor layer;
forming a patterned mask layer on an upper surface of the amorphous carbon layer; and
etching the amorphous carbon layer, the semiconductor layer, and the to-be-etched material layer using the patterned mask layer as a mask.

US Pat. No. 10,600,700

TEST STRUCTURE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A test structure manufacturing method, comprising:providing a top wafer structure, wherein the top wafer structure comprises a top wafer and multiple first pads that are spaced from each other at a bottom of the top wafer;
providing a bottom wafer;
forming a pad material layer on the bottom wafer;
patterning the pad material layer, to form multiple initial second pads in a pad region;
forming an insulation layer on a side surface of each initial second pad;
etching the multiple initial second pads to form trenches, to form multiple second pads that are spaced from each other at a top of the bottom wafer; and
bonding, in an eutectic manner, the multiple first pads with the multiple second pads, wherein each first pad is bonded with a second pad, to form multiple pads.

US Pat. No. 10,764,693

MICROPHONE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A method for manufacturing a microphone, comprising:providing a substrate structure, the substrate structure comprising a substrate and a first insulating layer covering a first part of the substrate;
forming a first electrode plate layer, the first electrode plate layer covering a part of the first insulating layer; and
forming a second insulating layer, the second insulating layer covering a part of a region of the first insulating layer which is not covered by the first electrode plate layer and a part of the first electrode plate layer,
wherein when viewed from the top of the microphone, a border of the first electrode plate layer adjacent to a second part of the substrate not covered by the first insulating layer and a border of the second insulating layer adjacent to the second part of the substrate form an angle, and a degree ? of the angle is larger than or equal to 90° and is smaller than or equal to 180°.

US Pat. No. 10,804,135

SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein a dummy gate structure is formed on the base, a source/drain doping region is formed in the base on both sides of the dummy gate structure, a dielectric layer is formed on the base exposed by the dummy gate structure, and the dielectric layer covers the source/drain doping region;
etching the dielectric layer on both sides of the dummy gate structure to form a contact hole exposing the source/drain doping region;
forming a contact plug in the contact hole, wherein the contact plug is electrically connected to the source/drain doping region and a top of the contact plug is lower than a top of the dummy gate structure;
after forming the contact plug, removing the dummy gate structure, and forming a protective layer on the top of the contact plug;
after forming the protective layer, forming a gate opening in the dielectric layer; and
forming a gate structure in the gate opening.

US Pat. No. 10,872,971

SEMICONDUCTOR STRUCTURE AND FORMATION METHOD THEREOF

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein the base comprises a device region used for forming a device and isolation regions located at both sides of the device region;
patterning the base to form a substrate and discrete fins and pseudo fins protruding from the substrate, wherein the fins are located in the device region, and the pseudo fins are located in the isolation regions;
removing the pseudo fins in the isolation regions;
forming isolation layers on the substrate exposed by the fins, wherein the isolation layers cover part of the side walls of the fins; and
thinning the isolation layers in the isolation regions, wherein the remaining isolation layers in the isolation regions are regarded as target isolation layers, and surfaces of the target isolation layers are lower than surfaces of the isolation layers between the discrete fins.

US Pat. No. 10,804,372

GATE-ALL-AROUND FIELD EFFECT TRANSISTOR AND METHOD FOR MANUFACTURING SAME

Semiconductor Manufacturi...

1. A method for manufacturing a gate-all-around field effect transistor, comprising:forming a first fin structure on a substrate, wherein the first fin structure comprises one first laminated structure or a plurality of first stacked laminated structures, wherein each first laminated structure sequentially comprises a sacrificial layer, a support layer, and a channel layer from bottom to top;
forming a dummy gate structure across the first fin structure, wherein the dummy gate structure comprises a dummy gate dielectric layer on a surface of the first fin structure, a dummy gate on the dummy gate dielectric layer, and a first spacer on a side surface of the dummy gate;
removing parts of the first fin structure located on two sides of the dummy gate structure to form a second fin structure;
performing first etching on a side surface of the sacrificial layer in the second fin structure to form a first space;
forming a second spacer in the first space;
performing second etching on a side surface of the channel layer in the second fin structure to form a second space; and
after the second space is formed, performing selective epitaxy on the side surface of the channel layer in the second fin structure to form a source region and a drain region;
wherein along a direction of a channel, compared with a side surface, distal to the sacrificial layer, of the second spacer, the side surface of the channel layer after the second etching is closer to the sacrificial layer.

US Pat. No. 10,755,075

FINGERPRINT RECOGNITION APPARATUS AND MANUFACTURING METHOD THEREFOR, MOBILE TERMINAL, AND FINGERPRINT LOCK

Semiconductor Manufacturi...

1. A fingerprint recognition apparatus, comprising:a substrate defining a protrusion on a surface of the substrate;
a fingerprint chip, comprising:
a signal processing circuit connected to the protrusion through a through substrate via (TSV) structure;
a plurality of sensing electrodes connected to the signal processing circuit; and
a protection layer covering the plurality of sensing electrodes; and
a touch cover plate located on the protection layer.

US Pat. No. 10,700,281

SEMICONDUCTOR RANDOM ACCESS MEMORY AND MANUFACTURING METHOD THEREOF

Semiconductor Manufacturi...

1. A method for manufacturing a resistive random access memory (RRAM), comprising:providing a metal bottom interconnection layer;
forming a bottom dielectric layer above the metal bottom interconnection layer, the bottom dielectric layer comprising a via through the bottom dielectric layer that exposes a portion of the metal bottom interconnection layer; and
forming a bottom electrode layer in the via, the bottom electrode layer comprising a first electrode being only formed above the metal bottom interconnection layer, wherein the first electrode is selectively grown above the metal bottom interconnection layer using a chemical vapor deposition (CVD) process.

US Pat. No. 10,964,540

SEMICONDUCTOR STRUCTURE FORMING METHOD

Semiconductor Manufacturi...

1. A patterning method, comprising:providing a base, a first mask layer formed on the base, and a second mask layer located at a top of the first mask layer, the second mask layer internally having a first opening, a second opening and a third opening which expose the first mask layer, the first opening, the second opening, the third opening being arrayed in parallel along a first direction;
performing a first cutting treatment on the first mask layer located below the first opening along the first direction;
after performing the first cutting treatment, performing a second cutting treatment on the first mask layer below the second mask layer located between the first opening and the second opening along the first direction;
after performing the second cutting treatment, forming first side wall layers on a side wall of the first opening, a side wall of the second opening and a side wall of the third opening;
forming a first pattern layer filling the first opening, the second opening and the third opening after the first side wall layers are formed, the first pattern layer internally having a first groove that is located right above the second mask layer between the second opening and the third opening;
etching, using the first pattern layer as a mask, to remove the second mask layer located between the second opening and the third opening along the bottom of the first groove, so as to form fourth openings located between adjacent first side wall layers; removing the first pattern layer; and
etching, using the second mask layer and the first side wall layers as masks, the first mask layer below the first opening, the second opening, the third opening and the fourth openings, so as to form a patterned first mask layer.

US Pat. No. 10,804,400

SEMICONDUCTOR STRUCTURE, MANUFACTURING METHOD THEREFOR, AND HIGH-K METAL GATE FIN FIELD-EFFECT TRANSISTOR

Semiconductor Manufacturi...

1. A semiconductor structure, comprising:a substrate structure having a high-dielectric-constant material layer and comprising a first portion for forming a first PMOS device and a second portion for forming a second PMOS device;
a first P-type work function adjustment layer disposed on the high-dielectric-constant material layer of the first portion and a first P-type work function adjustment layer disposed on the high-dielectric-constant material of the second portion, wherein an oxygen vacancy concentration at an interface of the high-dielectric-constant material layer and the first P-type work function adjustment layer of the first portion is higher than an oxygen vacancy concentration at an interface of the high-dielectric-constant material layer and the first P-type work function adjustment layer of the second portion; and
a second P-type work function adjustment layer disposed on the first P-type work function adjustment layer of the first portion, and disposed on the first P-type work function adjustment layer of the second portion.

US Pat. No. 10,749,511

IO CIRCUIT AND ACCESS CONTROL SIGNAL GENERATION CIRCUIT FOR IO CIRCUIT

Semiconductor Manufacturi...

1. An access control signal generation circuit for an IO circuit, comprising:a bias module coupled with an IO port, the bias module configured to generate an access control signal according to an IO port signal and an IO control signal, wherein a first voltage value of the access control signal is equal to a larger value between a second voltage value of an IO port voltage division signal and a voltage value of the IO control signal, and the second voltage value of the IO port voltage division signal is equal to a value of percentage of a third voltage value of the IO port signal, wherein the percentage is greater than 0 and less than 100;
an access control module coupled with the bias module, the access control module configured to cut off or conduct based on the first voltage value of the access control signal and the third voltage value of the IO port signal received and to output a first interface signal, wherein in an open-drain mode, when the IO control signal is in logic low level, the access control module is conducting and a voltage value of the first interface signal varies according to the third voltage value of the IO port signal; and
a higher-selection module coupled with an IO power source and the IO port configured to generate a second interface signal according to an IO power source signal and the IO port signal, wherein a voltage value of the second interface signal is equal to a larger value between a voltage value of the IO power source signal and the third voltage value of the IO port signal.

US Pat. No. 10,685,838

SEMICONDUCTOR STRUCTURE PROVIDING FOR AN INCREASED PATTERN DENSITY ON A SUBSTRATE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, used to form target patterns, wherein the base comprises a first region and a second region, and wherein a pitch between target patterns formed on the first region is greater than a pitch between target patterns formed on the second region;
forming a bottom core material layer on the base;
forming a plurality of discrete first core layers on the bottom core material layer;
forming a first mask sidewall on a sidewall of the first core layer of the first region, and forming a second mask sidewall on a sidewall of the first core layer of the second region, wherein a thickness of the second mask sidewall is greater than a thickness of the first mask sidewall;
removing the first core layers;
after the first core layers are removed, patterning the bottom core material layer using the first mask sidewall and the second mask sidewall as masks, to form a plurality of discrete second core layers;
removing the first mask sidewall and the second mask sidewall;
after the first mask sidewall and the second mask sidewall are removed, forming a third mask sidewall on a sidewall of the second core layer;
removing the second core layers; and
after the second core layers are removed, patterning the base using the third mask sidewall as a mask, to form a plurality of target patterns protruding out of a residual base;
wherein the step of forming the first mask sidewall and the second mask sidewall comprises:
forming a first sidewall film conformally covering the first core layer and the base;
removing the first sidewall film of the first region;
after the first sidewall film of the first region is removed, forming a second sidewall film, to conformally cover the first core layer, the base, and a residual first sidewall film; and
removing a top of the first core layer and the second sidewall film and the first sidewall film on the base using a blanket etching process, reserving a residual second sidewall film on the sidewall of the first core layer as the first mask sidewall, and reserving the residual first sidewall film as a fourth mask sidewall, wherein the fourth mask sidewall is located between the first mask sidewall and the first core layer of the second region, and between the first mask sidewall and the bottom core material layer of the second region, and the fourth mask sidewall and the first mask sidewall of the second region construct the second mask sidewall.

US Pat. No. 11,011,608

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME

Semiconductor Manufacturi...

17. A semiconductor structure, comprising:a base;
a gate structure located on the base;
a source/drain doped layer located within the base on both sides of the gate structure;
an interlayer dielectric layer located on the base exposed from the gate structure, the interlayer dielectric layer exposing a top of the gate structure, the interlayer dielectric layer comprising a first dielectric layer and a second dielectric layer located on the first dielectric layer, the first dielectric layer covering a portion of a side wall of the gate structure, and a top surface of the first dielectric layer being flush with a top surface of the source/drain doped layer;
a contact plug located within the interlayer dielectric layer between side walls of the adjacent gate structures, the contact plug being electrically connected to the source/drain doped layer; and
a self-aligned stop layer located between at least the contact plug and the side wall of the gate structure.

US Pat. No. 10,991,794

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SAME

Semiconductor Manufacturi...

1. A method for manufacturing a semiconductor device, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate,
a gate structure disposed on the substrate,
initial spacer layers on side surfaces of two sides of the gate structure, and
a first inter-layer dielectric layer covering the gate structure and the initial spacer layers,
wherein the substrate comprises a source and a drain respectively located on the two sides of the gate structure;
etching the first inter-layer dielectric layer to form a source contact hole exposing the source and a drain contact hole exposing the drain, wherein the source contact hole and the drain contact hole further expose a part of the initial spacer layer on at least one side of the gate structure;
removing the exposed part of the initial spacer layer to expose the side surface of the at least one side of the gate structure;
forming a spacer structure layer on the exposed side surface of the at least one side of the gate structure, wherein:
the spacer structure layer comprises a first spacer layer, a sacrificial spacer layer, and a second spacer layer,
the first spacer layer is positioned between the gate structure and the sacrificial spacer layer, the sacrificial spacer layer is positioned between the first spacer layer and the second spacer layer, and a bottom end of the second spacer layer is higher than a bottom end of the first spacer layer, and
the first spacer layer is formed on the exposed side surface of the at least one side of the gate structure, the sacrificial spacer layer is formed on a side surface of the first spacer layer, and the second spacer layer is formed on a side surface of the sacrificial spacer layer;
after the spacer structure layer is formed, forming, in the source contact hole, a source contact member connected to the source, and forming, in the drain contact hole, a drain contact member connected to the drain;
after the source contact member and the drain contact member are formed, selectively removing the sacrificial spacer layer to form an air gap and maintaining the first spacer layer and the second spacer layer, wherein a bottom end of the air gap is positioned above the bottom end of the first spacer layer and below the bottom end of the second spacer layer; and
forming a second inter-layer dielectric layer on the first inter-layer dielectric layer, the source contact member, and the drain contact member, wherein the second inter-layer dielectric layer covers the air gap.

US Pat. No. 10,964,813

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate having a first device region and a second device region, the first device region comprising an input/output device region, and the second device region comprising a core device region;
a first trench at the first device region;
a first dummy gate dielectric layer at a side wall of the first trench;
a first spacer layer at the side wall of the first trench, the first spacer layer being positioned on the first dummy gate dielectric layer;
a Lightly Doped Drain (LDD) region below the first trench;
a second trench at the second device region;
a second dummy gate dielectric layer at a side wall of the second trench; and
a second spacer layer at the side wall of the second trench, the second spacer layer being positioned on the second dummy gate dielectric layer,
wherein a thickness of the first spacer layer is smaller than a thickness of the second spacer layer.

US Pat. No. 10,964,585

METHOD FOR FORMING A FIN-BASED SEMICONDUCTOR STRUCTURE

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein the base comprises a substrate and a fin protruding out of the substrate, a fin mask layer is formed on the top of the fin, and the base comprises a graphics-intensive region and a graphics-sparse region;
forming an isolation material layer on the substrate exposed by the fin, wherein the isolation material layer exposes a top of the fin mask layer;
performing first etching processing on the isolation material layer, wherein a residual isolation material layer covers a partial sidewall of the fin mask layer, and a top of the residual isolation material layer located on the graphics-sparse region is lower than a top of the residual isolation material layer located on the graphics-intensive region;
removing the fin mask layer after the first etching processing is performed; and
performing second etching processing on the residual isolation material layer using an isotropic dry etching process after the fin mask layer is removed, wherein the etched isolation material layer is used as an isolation layer, and the isolation layer covers a partial sidewall of the fin.

US Pat. No. 10,957,785

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate;
a semiconductor fin on the substrate;
an isolation region at sides of the semiconductor fin, wherein an upper surface of the isolation region is lower than an upper surface of the semiconductor fin, wherein the isolation region comprises a first region and a second region; and
a gate structure covering a portion of the semiconductor fin and the first region of the isolation region, wherein the second region of the isolation region is located at least one of two sides of the gate structure, and wherein an upper surface of the first region is level with an upper surface of the second region.

US Pat. No. 10,877,543

LEVEL SHIFTER, INTEGRATED CIRCUIT, AND METHOD

Semiconductor Manufacturi...

1. A level shifter (LS), configured to run in a first mode and a second mode alternating with each other, wherein the LS comprises:an input unit that is configured to:
receive a first signal,
be turned on in the first mode to transmit the first signal to a latch unit, and
be turned off in the second mode;
a power supply switch unit that is configured to:
transmit a first power supply voltage to the latch unit in the first mode, and
transmit a second power supply voltage to the latch unit in the second mode,
wherein the first power supply voltage is lower than the second power supply voltage;
the latch unit that is configured to:
latch the first signal in the first mode, wherein a level amplitude of a latched first signal is equal to the first power supply voltage,
change the level amplitude of the first signal from the first power supply voltage to the second power supply voltage in the second mode, and
output, in each of the first mode and the second mode, a second signal whose logic is opposite to that of the first signal to an output unit; and
the output unit that is configured to:
isolate the received second signal and output the second power supply voltage in the first mode, and
output, in the second mode according to the received second signal, a third signal whose logic is opposite to that of the second signal,
wherein a level amplitude of the third signal is equal to the second power supply voltage.

US Pat. No. 10,860,772

METHOD AND APPARATUS FOR DESIGNING INTERCONNECTION STRUCTURE AND METHOD FOR MANUFACTURING INTERCONNECTION STRUCTURE

Semiconductor Manufacturi...

1. A method for manufacturing an interconnection structure comprising:generating, with a processor, a chip design drawing, wherein generating the chip design drawing comprises:
designing n virtual interconnection units according to a number of metal interconnection layers in a circuit area of the chip design drawing, wherein an ith virtual interconnection unit comprises i metal interconnection layers, and adjacent metal interconnection layers in the ith virtual interconnection unit are connected by using vias, and n?, i?n; and
filling an area in the chip design drawing outside the circuit area with virtual interconnection units, wherein an (i+1)th virtual interconnection unit is filled, and the ith virtual interconnection unit is not filled unless there is no space in the area for the (i+1)th virtual interconnection unit; and
manufacturing an interconnection structure according to the chip design drawing with which the virtual interconnection units are filled.

US Pat. No. 10,784,296

IMAGE SENSOR AND MANUFACTURING METHOD THEREFOR

Semiconductor Manufacturi...

1. A method for manufacturing an image sensor, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises: a semiconductor substrate and a first active region located on the semiconductor substrate, the first active region comprising a first doped region;
forming a doped semiconductor layer on the first active region;
annealing to diffuse dopants in the doped semiconductor layer to a surface layer of the first doped region, so as to form a second doped region, wherein the second doped region is located at an upper surface of the first active region; and
forming a contact connected to the doped semiconductor layer.

US Pat. No. 11,011,627

SEMICONDUCTOR STRUCTURE AND METHOD FOR THE FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein the base comprises a device region for forming devices and isolation regions located on two sides of the device region;
patterning the base to form a substrate and fins protruding from the substrate;
forming, on two sides of the device region, first dummy fins protruding from the substrate of the isolation region; and
forming an isolation layer on the substrate exposed by the fins and the first dummy fins, wherein the isolation layer covers a part of side walls of the fin;
wherein in the step of forming the first dummy fins, along a direction perpendicular to side walls of the first dummy fin, a distance between the first dummy fin and an adjacent fin is a first distance, and a distance between adjacent fins on the device region is a second distance, wherein the first distance is greater than 0.5 times the second distance and less than 3 times the second distance.

US Pat. No. 11,011,412

SEMICONDUCTOR STRUCTURE AND METHOD FOR THE FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, where a core layer is formed on the base, a hard mask layer is formed on the core layer, and a first mask opening is formed in the hard mask layer;
forming a first mask trench in the core layer exposed from the first mask opening, along an extending direction of the first mask trench, where the first mask trench comprises a plurality of mask sub-trenches along the extending direction of the first mask trench, and the mask sub-trenches of the plurality of mask sub-trenches are isolated from each other using the core layer exposed from the first mask opening;
forming a first spacer on a side wall of the mask sub-trench;
removing a core layer of a region in which the first mask opening is located, and forming, at a position corresponding to the core layer, a second mask trench enclosed by the first spacer and the base, where the second mask trench and the first mask trench are isolated from each other using the first spacer;
forming a second protective layer on the hard mask layer, the second protective layer being filled in the first mask trench, and the second protective layer exposing a core layer of the region in which the first mask opening is located;
removing the exposed core layer using the second protective layer as a mask;
forming a second spacer on a side wall of the second mask trench, after the second spacer is formed, both the first spacer and the base, and the second spacer and the base, enclose a first target trench; and
after forming the second spacer, removing the second protective layer.

US Pat. No. 11,011,416

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, a bottom dielectric layer formed on the base, and an interconnecting wire located within the bottom dielectric layer being formed on the base, wherein the bottom dielectric layer exposes a top of the interconnecting wire;
etching a portion of a thickness of the bottom dielectric layer, along an extending direction of the interconnecting wire, where adjacent interconnecting wires and a remainder of the bottom dielectric layer form a groove, along the extending direction of the interconnecting wire, an opening width of the groove is a first width, and along a direction perpendicular to the extending direction of the interconnecting wire, the adjacent interconnecting wires and the bottom dielectric layer form a trench, an opening width of the trench is a second width, and the second width is smaller than the first width;
after etching the portion of the thickness of the bottom dielectric layer, forming a side wall layer that covers the bottom and side walls of the groove, as well as the top of the interconnecting wire conformally, the side wall layer sealing the top of the trench;
after forming the side wall layer, forming an etch stop layer at least in the groove, the etch stop layer sealing a top of the groove;
forming a top dielectric layer covering the interconnecting wire, the etch stop layer, and the bottom dielectric layer;
forming a via within top dielectric layers on both sides of the groove, the via exposing the top of the interconnecting wire;
forming a via interconnecting structure filling the via, the via interconnecting structure being electrically connected to the interconnecting wire.

US Pat. No. 10,998,396

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base;
forming a first electrode layer on the base;
forming a capacitance dielectric layer on a top and a sidewall of the first electrode layer;
after forming the capacitance dielectric layer, performing cleaning processing on the capacitance dielectric layer; and
after performing the cleaning processing, forming a second electrode layer conformally covering the capacitance dielectric layer.

US Pat. No. 10,990,000

PHOTOLITHOGRAPHY PLATE AND MASK CORRECTION METHOD

Semiconductor Manufacturi...

1. A mask correction method, comprising:forming a patterned mask having at least one defect with a defect dimension of 10 nm to 25 nm on a substrate;
performing optical imaging simulation on the mask to determine a defective mask pattern within the patterned mask;
determining whether the defect dimension of the defect on the defective mask pattern is within a specified range, where the specified range is 10 nm to 25 nm; and
in response to determining that the defect dimension is within the specified range,
determining a location of a scattering bar to be formed in the substrate according to a shape of the defective mask pattern,
forming a recess at the location in the substrate, and
forming the scattering bar in the recess, where a length of the scattering bar is greater than a length of the defect and a width of the scattering bar is greater than a width of the defect.

US Pat. No. 10,991,572

MANUFACTURING METHOD FOR SEMICONDUCTOR APPARATUS

Semiconductor Manufacturi...

1. A manufacturing method for a semiconductor apparatus, comprising:providing a semiconductor structure, wherein the semiconductor structure comprises:
a substrate and an interlayer dielectric layer on the substrate, wherein the interlayer dielectric layer has an opening for forming a gate;
depositing a gate metal layer on the semiconductor structure to fill the opening entirely, wherein the gate metal layer contains impurity, the gate metal layer comprises a first part in the opening and a second part on the first part, the second part covers a top of the opening, the second part is further formed on the interlayer dielectric layer;
removing a portion of the second part;
after removing the portion of the second part, forming an impurity adsorption layer on the gate metal layer;
performing a first annealing treatment on a semiconductor structure on which the impurity adsorption layer has been formed, to make the impurity in the gate metal layer enter the impurity adsorption layer, wherein a temperature of the first annealing treatment falls within a range of 800° C. to 1000° C.; and
removing the impurity adsorption layer after the first annealing treatment is performed, wherein a remaining portion of the second part, a portion of the interlayer dielectric layer, and a portion of the first part are further removed, a remaining portion of the first part is used as a metal gate.

US Pat. No. 10,991,596

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base;
forming, on the base, a to-be-etched material layer, a core material layer located on the to-be-etched material layer, and a hard mask (HM) material layer located on the core material layer;
patterning the HM material layer to form a plurality of discrete HM layers, wherein after the HM layers are formed, a plurality of openings is formed between adjacent HM layers;
etching the core material layer between adjacent HM layers, forming, in the core material layer, a plurality of first grooves exposing the to-be-etched material layer, and using the remaining core material layer as a core layer, wherein the etching the core material layer between the adjacent HM layers comprises:
forming a flattened layer on the core material layer exposed from the HM layer, wherein the flattened layer covers the top of the HM layer;
forming a second pattern layer on the flattened layer, wherein the second pattern layer has a plurality of opening patterns, a side wall of an opening pattern located between adjacent HM layers is level with a side wall of the opening, or, an opening pattern located between adjacent HM layers exposes the flattened layer that is above the opening and is above a part of the top of HM layers on two sides of the opening; and
sequentially etching the flattened layer and the core material layer along the opening pattern;
forming a side wall layer on a side wall of the first groove and a side wall of the HM layer;
after the side wall layer is formed, removing the HM layer and the core layer at the bottom of the HM layer, and forming, in the core layer, a plurality of second grooves exposing the to-be-etched material layer; and
removing the to-be-etched material layer at the bottom of the first groove and the second groove by using the side wall layer and the remaining core layer as masks, and forming a target pattern in the remaining to-be-etched material layer.

US Pat. No. 10,991,690

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein the base comprises:
a substrate,
a fin protruding from the substrate, and
at least two channel laminates sequentially located on the fin, where each channel laminate of the at least two channel laminates comprises a sacrificial layer and a channel layer located on the sacrificial layer;
forming a gate structure across the channel laminates, wherein the gate structure covers a part of a top and a part of sidewalls of the channel laminates;
etching the channel laminates on two sides of the gate structure to form, in the channel laminates, a groove that exposes the fin and to remove a portion of the sacrificial layer, wherein:
after the groove is formed, a part of the channel layer is exposed on two sides of a remaining sacrificial layer below the gate structure;
the fin, the channel layer adjacent to the fin and the remaining sacrificial layer encircle a first trench;
adjacent channel layers and a remaining sacrificial layer between the channel layers encircle a second trench, wherein the quantity of the channel laminates is two, and along a direction perpendicular to sidewalls of the gate structure, a lateral depth of the second trench measured from an edge of the channel layer is greater than a lateral depth of the first trench measured from the edge of the channel layer, or the quantity of the channel laminates is greater than or equal to three, and along the direction perpendicular to the sidewalls of the gate structure, the lateral depth of the second trench is greater than the lateral depth of the first trench, and lateral depths of second trenches decrease gradually along a direction from a top of the gate structure to a bottom of the gate structure;
forming first spacers in the first trench and the second trench; and
forming a source-drain doping layer in the groove after forming the first spacers.

US Pat. No. 10,964,593

METHOD FOR FORMING A SEMICONDUCTOR STRUCTURE WITH A GATE CONTACT PLUG

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, a gate structure being formed on the base, a source/drain doped layer being formed within the base on both sides of the gate structure, an initial dielectric layer being formed on the base exposed from the gate structure, the initial dielectric layer covering a top of the gate structure, a-source/drain contact plugs being formed within the initial dielectric layer on a top of the source/drain doped layer, the source/drain contact plugs being electrically connected to the source/drain doped layer;
removing a portion of a thickness of the initial dielectric layer to form a dielectric layer and expose a portion of a side wall of each of the source/drain contact plugs;
forming an etch stop layer on at least the side wall of each of the source/drain contact plugs exposed from the dielectric layer;
etching the dielectric layer on the top of the gate structure using the etch stop layer on the side walls of the source/drain contact plugs as lateral etch stop positions, to form a gate contact opening exposing the top of the gate structure;
forming a gate contact plug within the gate contact opening, the gate contact plug being electrically connected to the gate structure.

US Pat. No. 10,964,797

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a base, wherein a dummy gate structure is formed on the base, an interlayer dielectric layer is formed on the base exposed by the dummy gate structure, and the interlayer dielectric layer covers side walls of the dummy gate structure and exposes a top of the dummy gate structure;
forming an isolation structure in the interlayer dielectric layer between adjacent dummy gate structures, wherein the isolation structure further extends into the base;
after forming the isolation structure, removing the dummy gate structure and forming a gate opening in the interlayer dielectric layer;
filling a gate electrode material into the gate opening, wherein the gate electrode material further covers a top of the interlayer dielectric layer; and
performing at least one polishing treatment to remove the gate electrode material above the top of the interlayer dielectric layer and retaining the gate electrode material in the gate opening as a gate electrode layer, wherein the step of the polishing treatment comprises:
performing a first polishing treatment on the gate electrode material using a metal polishing liquid; and
after the first polishing treatment, performing a second polishing treatment on the isolation structure using deionized water.

US Pat. No. 10,964,818

SEMICONDUCTOR DEVICE DOPED FROM A DIFFUSED LAYER

Semiconductor Manufacturi...

1. A semiconductor device, comprising:a substrate;
a source and a drain that are at least partially located in the substrate;
a diffused layer on a surface of at least one of the source or the drain, wherein a conductivity type of the diffused layer is a same conductivity type as the source and the drain, and a doping density of a dopant contained in the diffused layer is separately greater than doping densities of dopants contained in the source and the drain;
a barrier layer on the diffused layer;
an interlayer dielectric layer that is formed on the barrier layer and that covers the source and the drain; and
a source contact and a drain contact that pass through the interlayer dielectric layer, wherein the source contact is connected to the source, and the drain contact is connected to the drain.

US Pat. No. 10,964,823

SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING SAME

Semiconductor Manufacturi...

1. A method for forming a semiconductor structure, comprising:providing a substrate, the substrate comprising a device unit area, wherein at least two fins are formed on the substrate of the device unit area, a channel structure layer is formed on the fins, the channel structure layer comprising a first channel structure layer located on at least one fin, a second channel structure layer located on at least one fin, and a third channel structure layer located on at least one fin, the first channel structure layer comprising multiple channel laminates, each channel laminate comprising a first sacrificial layer and a first channel layer located on the first sacrificial layer, the second channel structure layer is a second channel layer of a single-layer structure, and the third channel structure layer comprises a third channel layer, a second sacrificial layer located on the third channel layer, and a fourth channel layer located on the second sacrificial layer;
forming a dummy gate structure across the channel structure layer of the device unit area, wherein the dummy gate structure covers a part of a top and a part of lateral sides of the channel structure layer;
forming a source-drain doping layer in the channel structure layer on two sides of the dummy gate structure;
after forming the source-drain doping layer, forming an interlayer dielectric layer on the substrate exposed by the dummy gate structure, wherein the interlayer dielectric layer covers lateral sides of the dummy gate structure; and
after forming the interlayer dielectric layer, forming a gate structure at positions of the dummy gate structure, the first sacrificial layer, and the second sacrificial layer.