US Pat. No. 9,087,964

LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a first electrode and a second electrode over an insulating layer;
a partition between the first electrode and the second electrode, the partition positioned over the insulating layer;
a projecting object over the partition;
a first light-emitting unit over the first electrode, the partition, the projecting object, and the second electrode;
an intermediate layer over the first light-emitting unit;
a second light-emitting unit over the intermediate layer; and
a third electrode over the second light-emitting unit,
wherein a recess is formed by a side surface of the projecting object and a side surface of the partition,
wherein a distance between a first point and a second point is greater than a total thickness of the first light-emitting
unit and the intermediate layer which are positioned over the first electrode and is smaller than or equal to a total thickness
of the first light-emitting unit, the intermediate layer, the second light-emitting unit, and the third electrode which are
positioned over the first electrode,

wherein the first point is the most protruded point of the projecting object in a direction parallel to a surface on which
the partition is formed, and

wherein the second point is a point of intersection of a surface of the partition with a first line which is drawn perpendicular
to the surface on which the partition is formed from the first point.

US Pat. No. 9,064,966

SEMICONDUCTOR DEVICE WITH OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a first region and a second region,
wherein the first region has a crystal whose size is less than or equal to 10 nm,
wherein the second region has a crystal part whose c-axis is aligned in a direction parallel to a normal vector of a surface
of the oxide semiconductor layer, and

wherein, in the first region, circumferentially distributed spots are observed in a nanobeam electron diffraction in which
a diameter of an electron beam is 1 nm? or more and 10 nm? or less.

US Pat. No. 9,237,657

WIRING SUBSTRATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THEREOF

SEMICONDUCTOR ENERGY LABO...

1. A method for manufacturing a wiring substrate, comprising the steps of:
forming a first conductive layer;
forming an insulating layer over the first conductive layer;
forming a porous film on the insulating layer;
forming an opening in the insulating layer and the porous film;
discharging a composition including a conductive material into the opening and over the porous film to form a second conductive
layer to be on and in direct contact with the first conductive layer and the a part of porous film by an ink jet method after
forming the opening; and

etching an exposed portion of the porous film using the second conductive layer as a mask after discharging the composition,
wherein an outermost side end portion of the second conductive layer is aligned with a side end portion of the etched porous
film,

wherein an entire top surface of the etched porous film is overlapped with the second conductive layer,
wherein the step of discharging the composition is performed under reduced pressure,
wherein the porous film is formed to have pores, and
wherein at least one pore is filled with the composition including the conductive material.

US Pat. No. 9,159,939

PHOTOELECTRIC CONVERSION DEVICE

Semiconductor Energy Labo...

1. A photoelectric conversion device comprising:
a crystalline silicon substrate;
a first silicon semiconductor layer over the crystalline silicon substrate, the first silicon semiconductor layer partially
covering a surface of the crystalline silicon substrate;

a second silicon semiconductor layer over the first silicon semiconductor layer;
a first electrode over the second silicon semiconductor layer; and
a light-transmitting semiconductor layer covering the crystalline silicon substrate, the first silicon semiconductor layer,
the second silicon semiconductor layer, and the first electrode,

wherein the light-transmitting semiconductor layer comprises an organic compound and an inorganic compound and is in direct
contact with the crystalline silicon substrate.

US Pat. No. 9,461,176

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

9. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode over a substrate;
forming a gate insulating film over the gate electrode;
forming an oxide semiconductor film over the gate insulating film;
forming an oxide film over the oxide semiconductor film;
forming a pair of electrodes electrically connected to the oxide semiconductor film over the oxide film, without performing
heat treatment after the oxide film is formed;

forming a first oxide insulating film over the oxide film and the pair of electrodes by a plasma CVD,
wherein a film formation temperature of the first oxide insulating film is higher than or equal to 280° C. and lower than
or equal to 400° C.;

forming a second oxide insulating film over the first oxide insulating film; and
performing heat treatment at a temperature higher than or equal to 150° C. and lower than or equal to 400° C.

US Pat. No. 9,070,776

SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a power supply control circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor;
and

a signal processing circuit comprising an input terminal and an output terminal,
wherein a gate of the first transistor is electrically connected to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor
and one of a source and a drain of the third transistor,

wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the
fourth transistor and the input terminal,

wherein the other of the source and the drain of the second transistor is electrically connected to a first wiring,
wherein a gate of the third transistor is electrically connected to a gate of the fourth transistor and the output terminal,
wherein the other of the source and the drain of the third transistor and the other of the source and the drain of the fourth
transistor is electrically connected to a second wiring, and

wherein at least one of the second transistor and the fourth transistor comprises a channel included in an oxide semiconductor
layer.

US Pat. No. 9,412,874

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a gate electrode layer;
a first gate insulating layer containing silicon and nitrogen adjacent to the gate electrode layer;
a second gate insulating layer containing silicon and nitrogen over the first gate insulating layer;
a first oxide semiconductor layer containing more indium than gallium adjacent to the second gate insulating layer; and
a second oxide semiconductor layer over the first oxide semiconductor layer.

US Pat. No. 9,240,488

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an oxide semiconductor layer including a channel formation region, a first region, and a second region over a substrate;
a gate insulating layer over the oxide semiconductor layer;
a gate electrode layer over the gate insulating layer;
an insulating layer over the gate electrode layer and the gate insulating layer; and
a source electrode layer and a drain electrode layer over the insulating layer,
wherein the first region is one of a source or drain region,
wherein each of the first region and the second region includes oxygen defects due to oxygen-defect-inducing factors,
wherein the second region is between the channel formation region and the first region,
wherein a concentration of the oxygen-defect-inducing factors of the second region is lower than that of the first region,
wherein the insulating layer includes a first part overlapping with the first region and a second part overlapping with the
second region,

wherein an interface between the first part and the second part is substantially aligned with an interface between the first
region and the second region, and

wherein the gate insulating film is over and in contact with the first region and the second region.

US Pat. No. 9,106,224

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A driving method of a semiconductor device which comprises:
a first circuit comprising a capacitor and a first transistor; and
a second circuit comprising a second transistor,
wherein a gate of the second transistor is connected to the first circuit,
wherein the first transistor has a same conductivity type as the second transistor,
the driving method comprising the steps of:
supplying a first potential to a first electrode of the capacitor;
supplying a second potential to a second electrode of the capacitor through the first transistor, wherein the second potential
is lower than the first potential; and

making the second electrode of the capacitor into a floating state,
wherein a potential supplied to a first terminal of the second transistor and a potential supplied to a second terminal of
the second transistor are distinct from the second potential.

US Pat. No. 9,196,858

METHOD FOR MANUFACTURING LIGHT EMITTING DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a light emitting device, comprising:
forming an anode;
forming a hole transporting layer over the anode;
forming a light emitting layer over the hole transporting layer;
forming an electron transporting layer over the light emitting layer;
forming a mixed layer including a first organic compound, a second organic compound, and metal oxide over the electron transporting
layer by a co-evaporation in vacuum;

after forming the mixed layer step, exposing the mixed layer to a nitrogen gas atmosphere without exposing the mixed layer
to a gas atmosphere including oxygen; and

after exposing step, forming a cathode over the mixed layer without exposing the mixed layer to a gas atmosphere including
oxygen.

US Pat. No. 9,240,425

METHOD FOR MANUFACTURING LIGHT-EMITTING DISPLAY DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a light-emitting display device comprising the steps of:
forming a first conductive film over a substrate having an insulating surface;
performing a first photolithography step on the first conductive film to form a first gate layer and a second gate layer;
forming a first insulating film over the first gate layer and the second gate layer;
forming a semiconductor film over the first insulating film;
forming a second conductive film over the semiconductor film;
performing a second lithography step on the second conductive film to form a first source layer and a first drain layer of
a first transistor comprising the first gate layer, and a second source layer and a second drain layer of a second transistor
comprising the second gate layer;

forming a second insulating film over the first transistor, the second transistor, and the semiconductor film;
performing a third lithography step, after formation of the second insulating film, to form:
a first opening exposing part of one of the first source layer and the first drain layer and a second opening exposing part
of one of the second source layer and the second drain layer by selectively etching the second insulating film; and

a third opening exposing part of the second gate layer and a fourth opening exposing part of the substrate by selectively
etching the second insulating film, the semiconductor film, and the first insulating film,

forming a third conductive film over the second insulating film so as to cover the first opening, the second opening, the
third opening, and the fourth opening; and

performing a fourth lithography step on the third conductive film to form:
a first pixel electrode electrically connected to the one of the second source layer and the second drain layer through the
second opening; and

a connection layer electrically connecting the one of the first source layer and the first drain layer to the second gate
layer through the first opening and the third opening,

wherein the first transistor and the second transistor comprise respectively a first region and a second region of the semiconductor
layer; and

wherein the semiconductor layer is continuously formed in the first region, in the second region, and along a path linking
the first region and the second region.

US Pat. No. 9,112,037

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first insulating layer over a first wiring;
an island-shaped semiconductor layer over the first insulating layer;
a source electrode and a drain electrode over the island-shaped semiconductor layer, wherein one of the source electrode and
the drain electrode is electrically connected to the first wiring through an opening in the island-shaped semiconductor layer
and the first insulating layer;

a second insulating layer over the island-shaped semiconductor layer, the source electrode, and the drain electrode; and
a gate electrode over the second insulating layer,
wherein an entire outer edge of one of the source electrode and the drain electrode is surrounded by the gate electrode in
planar view, and

wherein an outer edge of the gate electrode is surrounded by the other of the source electrode and the drain electrode in
the planar view.

US Pat. No. 9,076,825

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming an oxide semiconductor film over an insulating surface;
forming a hard mask over the oxide semiconductor film, the hard mask containing at least one of Ti, Mo, Ta, and W;
forming a resist over the hard mask;
performing light exposure to form a resist mask;
processing the hard mask using the resist mask to form a processed hard mask;
processing the oxide semiconductor film using the processed hard mask;
removing the resist mask and the processed hard mask;
forming a source electrode and a drain electrode in contact with the oxide semiconductor film;
forming a gate insulating film over the source electrode and the drain electrode; and
forming a gate electrode over the gate insulating film, the gate electrode overlapping with the oxide semiconductor film.

US Pat. No. 9,472,682

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an oxide semiconductor film;
a gate insulating film over the oxide semiconductor film;
a gate electrode layer over the gate insulating film;
a silicon nitride film over the oxide semiconductor film, the gate insulating film, and the gate electrode layer, the silicon
nitride film comprising a first opening; and

a first electrode layer over the silicon nitride film, the first electrode layer being in contact with the oxide semiconductor
film through the first opening,

wherein in the silicon nitride film, a peak of the number of released hydrogen molecules does not appear at a temperature
lower than or equal to 500° C. in thermal desorption spectroscopy.

US Pat. No. 9,236,400

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A liquid crystal display device comprising:
a first pixel over a first substrate, and comprising:
a first TFT comprising:
a first portion of a semiconductor layer;
a first gate insulating film over the first portion of the semiconductor layer; and
a first gate electrode over the first gate insulating film,
a capacitor comprising:
a first layer comprising a second portion of the semiconductor layer;
a second layer over the first layer, and comprising a same layer as the first gate insulating film; and
a third layer over the second layer, and comprising a same layer as the first gate electrode,
wherein a third portion of the semiconductor layer extends to a second pixel next to the first pixel, the third portion of
the semiconductor layer being contiguous with the first portion of the semiconductor layer,

a first insulating film comprising silicon nitride, and over and in contact with the first gate electrode and the first gate
insulating film;

a second insulating film comprising an organic insulating material, and over the first insulating film; and
a wiring over the second insulating film, the wiring being connected to the first portion of the semiconductor layer through
an opening in both the first insulating film and the second insulating film,

wherein the first layer, the third layer, and a fourth layer overlap each other, the fourth layer comprising a same layer
as the wiring.

US Pat. No. 9,262,978

DRIVING CIRCUIT OF A SEMICONDUCTOR DISPLAY DEVICE AND THE SEMICONDUCTOR DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device, comprising:
a pixel matrix circuit; and
a first gate signal line side driving circuit and a second gate signal line side driver circuit, wherein the pixel matrix
circuit is located between the first gate signal line side driving circuit and the second gate signal line side driver circuit,
each of the first gate signal line side driving circuit and the second gate signal line side driver circuit including a shift
register circuit and a buffer circuit electrically connected with the shift register circuit, the buffer circuit comprising
an inverter,

wherein the inverter comprises a plurality of n-channel thin film transistors and at least one p-channel thin film transistor,
wherein each of the plurality of n-channel thin film transistors is connected in parallel with each other, and
wherein a channel region of the plurality of n-channel thin film transistors comprises crystalline silicon.

US Pat. No. 9,356,154

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a substrate;
a first insulating film over the substrate;
an oxide semiconductor film over the first insulating film;
a gate insulating film over the oxide semiconductor film;
a gate electrode which is over the gate insulating film and overlaps with the oxide semiconductor film;
a second insulating film over the gate electrode; and
a source electrode and a drain electrode which are electrically connected to the oxide semiconductor film via the second insulating
film,

wherein the first insulating film contains silicon and oxygen; and
wherein the oxide semiconductor film which overlaps with at least the gate electrode includes a region in which a concentration
of silicon distributed from an interface between the oxide semiconductor film and the first insulating film toward the oxide
semiconductor film is lower than or equal to 1.1 at. %.

US Pat. No. 9,208,717

SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:
a pixel comprising:
an electroluminescent device;
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a capacitor,
wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second
transistor,

wherein the one of the source and the drain of the first transistor is directly connected to one of a source and a drain of
the third transistor,

wherein a gate of the first transistor is directly connected to the other of the source and the drain of the second transistor,
wherein one of a source and a drain of the fourth transistor is directly connected to the other of the source and the drain
of the first transistor,

wherein the other of the source and the drain of the fourth transistor is directly connected to a first line,
wherein one of a source and a drain of the fifth transistor is directly connected to the other of the source and the drain
of the first transistor,

wherein the other of the source and the drain of the fifth transistor is directly connected to a second line,
wherein the other of the source and the drain of the third transistor is directly connected to the electroluminescent device,
wherein a first electrode of the capacitor is directly connected to the gate of the first transistor,
wherein a second electrode of the capacitor is directly connected to the first line,
wherein a gate of the second transistor is directly connected to a third line,
wherein a gate of the fifth transistor is directly connected to the third line, and
wherein a gate of the fourth transistor is directly connected to a fourth line.

US Pat. No. 9,166,019

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising the steps of:
forming a first electrode layer and a second electrode layer;
forming an oxide semiconductor layer over the first electrode layer and the second electrode layer;
forming a gate insulating layer over the oxide semiconductor layer;
forming a gate electrode layer and a first insulating layer over the gate insulating layer to overlap with the oxide semiconductor
layer;

introducing an impurity element into the oxide semiconductor layer using the gate electrode layer and the first insulating
layer as masks so that a first region, a second region and a channel formation region between the first region and the second
region are formed;

forming a second insulating layer over the first insulating layer to cover side surfaces of the gate electrode layer;
forming a conductive film over the oxide semiconductor layer, the gate electrode layer, the second insulating layer, and the
first insulating layer;

forming a first insulating film over the conductive film;
forming a source electrode layer, a drain electrode layer, and a third insulating layer by removing parts of the first insulating
film and the conductive film by a chemical mechanical polishing method until the first insulating layer is exposed so that
the conductive film is divided; and

forming a fourth insulating layer over the first insulating layer, the second insulating layer, the source electrode layer,
the drain electrode layer, and the third insulating layer.

US Pat. No. 9,122,348

TOUCH PANEL

Semiconductor Energy Labo...

1. A touch panel comprising:
a first pixel including a first photosensor portion detecting light with a first color;
a second pixel including a second photosensor portion detecting light with a second color;
a first A/D converter performing A/D conversion on a first output signal of the first photosensor portion; and
a second A/D converter performing A/D conversion on a second output signal of the second photosensor portion,
wherein voltage resolution of the first A/D converter and voltage resolution of the second A/D converter are different,
wherein each of the first A/D converter and the second A/D converter comprises a D/A converter and a comparator being electrically
connected to the D/A converter through a DAC output signal line,

wherein each of the first photosensor portion and the second photosensor portion comprises a transistor and a photodiode,
wherein one of a source and a drain of the transistor is electrically connected to the comparator through a photosensor signal
line,

wherein a gate of the transistor is electrically connected to one electrode of the photodiode, and
wherein the comparator is configured to compare a potential of the DAC output signal line and a potential of the photosensor
signal line.

US Pat. No. 9,159,942

LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC APPLIANCE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:
a hole-transport layer; and
a light-emitting layer over the hole-transport layer,
wherein the light-emitting layer includes a first organic compound having an electron-transport property, a second organic
compound having a hole-transport property, and a third organic compound converting triplet excitation energy into light emission,

wherein a combination of the first organic compound and the second organic compound forms an exciplex, and
wherein the hole-transport layer comprises the second organic compound and an organic compound having a hole-transport property.

US Pat. No. 9,437,824

LIGHT-EMITTING ELEMENT, LIGHT EMITTING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:
a first light-emitting layer between an anode and a cathode; and
a second light-emitting layer between the anode and the cathode, the second light-emitting layer being in contact with a cathode
side of the first light-emitting layer,

wherein the first light-emitting layer includes a first layer provided on an anode side and a second layer provided on a cathode
side,

wherein the first layer provided on the anode side contains a first light-emitting substance and a first organic compound,
wherein the second layer provided on the cathode side contains a second organic compound and the first light-emitting substance,
wherein an amount of the second organic compound in the second layer provided on the cathode side is greater than or equal
to 50 wt % and less than or equal to 99.9 wt %,

wherein the second light-emitting layer contains a third organic compound and a second light-emitting substance,
wherein an amount of the third organic compound in the second light-emitting layer is greater than or equal to 50 wt % and
less than or equal to 99.9 wt %, and

wherein the first organic compound is a compound different from the second organic compound.

US Pat. No. 9,123,581

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an antenna portion;
a first circuit configured to rectify an output of the antenna portion and configured to output a direct current voltage,
the output of the first circuit being used as a first power supply potential;

a second circuit configured to receive an output of the first circuit and configured to output a specific voltage, the output
of the second circuit being used as a second power supply potential;

a third circuit configured to receive the output of the first circuit and configured to boost the first power supply potential,
the third circuit comprising a first booster circuit configured to boost the first power supply potential and a second booster
circuit configured to boost an output of the first booster circuit; and

a memory configured to receive an output of the second booster circuit.

US Pat. No. 9,287,511

ANTHRACENE DERIVATIVE, AND LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE USING ANTHRACENE DERIVATIVE

Semiconductor Energy Labo...

1. A method for synthesizing a compound represented by the following formula:

the method comprising conducting a reaction according to the following scheme:

wherein:
X1 represents halogen;

Ar31 represents an aryl group having 6 to 25 carbon atoms;

R41 and R42 independently represent any of hydrogen, an alkyl group having 1 to 4 carbon atoms, and an aryl group having 6 to 25 carbon
atoms; and

? represents an arylene group having 6 to 25 carbon atoms.

US Pat. No. 9,286,848

METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE

Semiconductor Energy Labo...

1. A method for driving a liquid crystal display device comprising first light sources, second light sources, a detection
circuit, an image sensor driver circuit, a scan line driver circuit and a pixel portion, the pixel portion comprising display
pixels in m rows and n columns and image-capture pixels in x rows and y columns (m, n, x and y are natural numbers of 4 or
more), comprising the steps of:
performing first supply of an image signal of a first color for the display pixels in first to k-th rows sequentially (k is
a natural number of less than m/2) in a period;

performing second supply of an image signal of a second color for the display pixels in (k+1)-th to 2k-th rows sequentially
in the period;

emitting light of the first color for the display pixels in first to s-th rows and light of the second color for the display
pixels in (k+1)-th to (k+s)-th rows (s is a natural number of k/2 or less) in the period and after the first supply for the
display pixels in the first to s-th rows and the second supply for the display pixels in the (k+1)-th to (k+s)-th rows are
finished;

performing a first image capture utilizing light of the first color in the image-capture pixels in first to v-th rows sequentially
(v is a natural number of x/4 or less) while emitting the light of the first color to obtain an image of the first color;
and

performing a second image capture utilizing light of the second color in the image-capture pixels in (w+1)-th to (w+v)-th
rows sequentially (w is a natural number greater than or equal to 2v and less than or equal to x/2) while emitting the light
of the second color to obtain an image of the second color,

wherein the first color and the second color are different from each other,
wherein the first supply and the second supply are performed concurrently,
wherein the first image capture and the second image capture are performed concurrently,
wherein the first light sources emit light of the first color,
wherein the second light sources emit light of the second color,
wherein the liquid crystal display device further comprises a first image-capture signal line and a second image-capture signal
line which are parallel to each other and provided for each column of the image-capture pixels,

wherein in each column, the image-capture pixels in the first to v-th rows are connected to the first image-capture signal
line and the image-capture pixels in the (w+1)-th to (w+v)-th rows are connected to the second image-capture signal line,

wherein the first image capture is performed by determining a potential of the first image-capture signal line by the detection
circuit and the second image capture is performed by determining a potential of the second image-capture signal line by the
detection circuit,

wherein the pixel portion comprises a first region which includes the display pixels in the first to k-th rows and the image-capture
pixels in the first to v-th rows and a second region which includes the display pixels in the (k+1)-th to 2k-th rows and the
image-capture pixels in the (w+1)-th to (w+v)-th rows, and

wherein the second region includes the first image-capture signal line and the second image-capture signal line.

US Pat. No. 9,287,117

SEMICONDUCTOR DEVICE COMPRISING AN OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a base insulating layer;
a first oxide layer over the base insulating layer;
an oxide semiconductor layer over the first oxide layer;
a second oxide layer over the oxide semiconductor layer;
a first source electrode layer and a first drain electrode layer each of which is in contact with a top surface of the second
oxide layer;

a second source electrode layer and a second drain electrode layer over the first source electrode layer and the first drain
electrode layer, respectively, and in contact with the top surface of the second oxide layer;

a gate insulating layer over the second source electrode layer and the second drain electrode layer, and in contact with the
top surface of the second oxide layer between the second source electrode layer and the second drain electrode layer; and

a gate electrode layer overlapping with the oxide semiconductor layer with the gate insulating layer provided therebetween,
wherein the base insulating layer and the gate insulating layer are in contact with each other.

US Pat. No. 9,287,411

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising a transistor, the transistor comprising:
a gate electrode over a substrate;
a gate insulating film over the gate electrode;
a multilayer film over the gate insulating film;
a pair of electrodes in electrical contact with the multilayer film;
a first oxide insulating film over the multilayer film and the pair of electrodes; and
a second oxide insulating film over the first oxide insulating film,
wherein the multilayer film includes an oxide semiconductor film and an oxide film over the oxide semiconductor film,
wherein the oxide semiconductor film has an amorphous structure or a microcrystalline structure,
wherein the second oxide insulating film is an oxide insulating film containing more oxygen than that in the stoichiometric
composition,

wherein each of the oxide semiconductor film and the oxide film includes In-M-Zn oxide,
wherein the M represents Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf, and
wherein a proportion of M atoms in the oxide film is higher than a proportion of M atoms in the oxide semiconductor film.

US Pat. No. 9,224,792

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A light emitting device comprising:
a flexible substrate;
a transistor over the flexible substrate;
a first electrode electrically connected to the transistor;
an insulating film covering an end portion of the first electrode;
a layer comprising a light emitting material over the first electrode; and
a second electrode over the layer comprising the light emitting material, wherein the insulating film has a cross-sectional
shape,

wherein the cross-sectional shape comprises a first curved line, a second curved line, and a third curved line interposed
between the first curved line and the second-curved line,

wherein the third curved line has a first center of curvature located outside the cross-sectional shape, and
wherein a thickness of the insulating film at the first curved line is larger than a thickness of the insulating film at the
end portion of the first electrode.

US Pat. No. 9,373,525

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising:
forming a semiconductor layer that comprises an oxide semiconductor including indium;
processing the semiconductor layer by wet etching to form an island-shaped semiconductor layer;
processing the island-shaped semiconductor layer by dry etching to form a recessed portion in the island-shaped semiconductor
layer; and

performing oxygen radical treatment on the recessed portion.

US Pat. No. 9,269,315

DRIVING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for driving a semiconductor device,
the semiconductor device comprising a pixel portion provided with a plurality of pixels each including a transistor and a
storage capacitor,

the storage capacitor comprising:
a first electrode including a light-transmitting semiconductor film;
a second electrode; and
a dielectric film between the first electrode and the second electrode,
wherein in a period during which an image is displayed in the pixel portion, the method comprises steps of:
supplying a first potential to the second electrode;
supplying a second potential to the first electrode to form a potential difference between the first electrode and the second
electrode being a threshold voltage of the storage capacitor or higher; and

holding the potential difference between the first electrode and the second electrode to the storage capacitor and displaying
the image in the pixel portion, and

wherein in a period during which display of the image is stopped, the method comprises a step of supplying a third potential
higher than the first potential to the first electrode.

US Pat. No. 9,286,953

SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a memory cell including a first transistor configured to write data and a second transistor configured to hold the data in
a gate and read the data in accordance with a potential of the gate; and

a reference current generation circuit including a third transistor configured to determine a current flowing between a source
and a drain of the second transistor,

wherein a voltage source is provided between a gate and a source of the third transistor, and
wherein the second transistor is a common drain transistor.

US Pat. No. 9,280,931

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a transistor comprising a gate electrode, a first terminal, and a second terminal;
a first wiring;
a second wiring;
a first switch;
a second switch;
a third switch;
a first capacitor; and
a second capacitor,
wherein the first switch has a function of selecting conduction or non-conduction between the first wiring and a first electrode
of the first capacitor,

wherein the first electrode of the first capacitor is electrically connected to a first electrode of the second capacitor,
wherein a second electrode of the first capacitor is electrically connected to the gate electrode of the transistor,
wherein a second electrode of the second capacitor is electrically connected to the first terminal of the transistor,
wherein the second switch has a function of selecting conduction or non-conduction between the second wiring and the gate
electrode of the transistor, and

wherein the third switch has a function of selecting conduction or non-conduction between the first electrode of the first
capacitor and the first terminal of the transistor.

US Pat. No. 9,196,745

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an oxide semiconductor stacked layer comprising a first oxide semiconductor layer, a second oxide semiconductor layer over
the first oxide semiconductor layer, and a third oxide semiconductor layer over the second oxide semiconductor layer;

a gate electrode layer and the oxide semiconductor stacked layer overlap each other; and
a gate insulating film between the gate electrode layer and the oxide semiconductor stacked layer,
wherein energy at a bottom of a conduction band of the second oxide semiconductor layer is lower than energy at a bottom of
a conduction band of the first oxide semiconductor layer and energy at a bottom of a conduction band of the third oxide semiconductor
layer, and

wherein the second oxide semiconductor layer comprises a crystal including a c-axis alignment.

US Pat. No. 9,153,589

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first transistor comprising a gate electrode;
a first insulating layer comprising an opening, wherein the gate electrode of the first transistor is positioned in the opening;
a second transistor comprising:
an oxide semiconductor layer on the first insulating layer;
a first conductive layer and a second conductive layer over the oxide semiconductor layer;
a second insulating layer over the oxide semiconductor layer, the first conductive layer, and the second conductive layer;
and

a gate electrode over the second insulating layer and overlapping with the oxide semiconductor layer
a switching element electrically connected the second conductive layer; and
a driver circuit electrically connected to the second conductive layer through the switching element,
wherein the oxide semiconductor layer comprises indium and zinc,
wherein the first conductive layer is in contact with the surface of the gate electrode of the first transistor and the first
insulating layer.

US Pat. No. 9,123,574

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a memory cell comprising:
a first transistor comprising:
a first conductive layer;
a second conductive layer;
an oxide semiconductor layer electrically connected to the first conductive layer and the second conductive layer;
a first insulating layer over the first conductive layer, the second conductive layer, and the oxide semiconductor layer;
and

a third conductive layer over the first insulating layer, wherein the third conductive layer and the oxide semiconductor layer
are overlapped with each other; and

a fourth conductive layer over the first insulating layer, wherein the fourth conductive layer and the first conductive layer
are overlapped with each other,

wherein the oxide semiconductor layer comprises indium and zinc,
wherein the oxide semiconductor layer comprises a channel formation region of the first transistor, and
wherein the first conductive layer and the fourth conductive layer are electrically insulated from each other to compose a
capacitor.

US Pat. No. 9,287,370

MEMORY DEVICE COMPRISING A TRANSISTOR INCLUDING AN OXIDE SEMICONDUCTOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

Semiconductor Energy Labo...

1. A memory device comprising:
a first transistor including a first channel formation region;
a second transistor including a second channel formation region;
a third transistor including a third channel formation region;
a fourth transistor including a fourth channel formation region;
a first line;
a second line;
a third line;
a fourth line;
a fifth line;
a sixth line; and
a seventh line,
wherein one of a source and a drain of the first transistor is electrically connected to the first line,
wherein one of a source and a drain of the second transistor is electrically connected to the second line,
wherein one of a source and a drain of the third transistor is electrically connected to the third line,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fourth line,
wherein a gate of the first transistor is electrically connected to the fifth line,
wherein a gate of the third transistor is electrically connected to the sixth line,
wherein a gate of the fourth transistor is electrically connected to the seventh line,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor
so that a node is formed,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source
and the drain of the third transistor,

wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source
and the drain of the fourth transistor,

wherein the first channel formation region includes a semiconductor material that is different from a semiconductor material
in the second channel formation region, the third channel formation region and the fourth channel formation region, and

wherein the first channel formation region includes an oxide semiconductor.

US Pat. No. 9,285,618

LIQUID CRYSTAL DISPLAY DEVICE COMPRISING TWO OVERLAPPING CONDUCTIVE LINES UNDER A SEALANT

Semiconductor Energy Labo...

1. A liquid crystal display device comprising:
a substrate;
thin film transistors over the substrate;
pixel electrodes each electrically connected to one of the thin film transistors;
a counter substrate facing the substrate;
a liquid crystal material provided between the substrate and the counter substrate;
a sealant provided between the substrate and the counter substrate;
a first conductive line over the substrate;
a first insulating film over the first conductive line;
a second conductive line over the first insulating film;
a second insulating film over the second conductive line;
a transparent conductive film over the second insulating film; and
a flexible printed circuit over the transparent conductive film;
wherein the sealant is in direct contact with the second insulating film;
wherein the sealant overlaps the first conductive line and the second conductive line;
wherein the second conductive line overlaps the first conductive line;
wherein the sealant does not overlap the transparent conductive film;
wherein the first conductive line is electrically connected to the second conductive line;
wherein the second conductive line is electrically connected to the flexible printed circuit via the transparent conductive
film;

wherein the second conductive line and the transparent conductive film are in direct contact via an opening in the second
insulating film;

wherein the flexible printed circuit and the transparent conductive film each completely cover the opening; and
wherein the transparent conductive film is made from a same layer as the pixel electrodes.

US Pat. No. 9,263,589

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method of manufacturing a semiconductor device comprising the steps of:
forming an insulating layer configured to release oxygen by heating, over a substrate;
forming an oxide semiconductor layer over and in contact with the insulating layer;
performing a first heat treatment on the oxide semiconductor layer so that oxygen contained in the insulating layer is supplied
to the oxide semiconductor layer;

forming a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;
forming a gate insulating layer over the oxide semiconductor layer,
forming a gate electrode over the gate insulating layer;
forming a protective insulating layer comprising aluminum oxide over the gate electrode; and
performing a second heat treatment on the protective insulating layer,
wherein a released amount of oxygen molecules of the insulating layer is greater than or equal to 1×1018/cm3 in thermal desorption spectroscopy.

US Pat. No. 9,051,274

TRIARYLAMINE COMPOUND, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A compound represented by a general formula (G1),

wherein:
E1 represents an oxygen atom;

?1 to ?3 each independently represent a substituted or unsubstituted phenylene group or a substituted or unsubstituted biphenylene
group, and m and n are each independently 0 or 1;

Ar1 represents an aryl group represented by a general formula (G1-2) below;

Ar2 represents any of a substituted or unsubstituted phenyl group, a substituted or unsubstituted naphthyl group, a substituted
or unsubstituted phenanthryl group, a substituted or unsubstituted triphenylenyl group, a substituted or unsubstituted fluorenyl
group, a substituted or unsubstituted carbazolyl group, a substituted or unsubstituted dibenzothiophenyl group, and a substituted
or unsubstituted dibenzofuranyl group; and

R1 to R4 each independently represent any of a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, and a substituted or unsubstituted
phenyl group, and


wherein:
E2 represents an oxygen atom;

?4 to ?6 each independently represent a substituted or unsubstituted phenyl group or a substituted or unsubstituted biphenyl group,
and q is 0 or 1;

Ar3 represents any of a substituted or unsubstituted phenyl group, a substituted or unsubstituted naphthyl group, a substituted
or unsubstituted phenanthryl group, a substituted or unsubstituted triphenylenyl group, a substituted or unsubstituted fluorenyl
group, a substituted or unsubstituted carbazolyl group, a substituted or unsubstituted dibenzothiophenyl group, and a substituted
or unsubstituted dibenzofuranyl group; and

R5 to R8 each independently represent any of a hydrogen atom, an alkyl group having 1 to 6 carbon atoms, and a substituted or unsubstituted
phenyl group.

US Pat. No. 9,287,332

LIGHT-EMITTING DEVICE COMPRISING LIGHT-EMITTING ELEMENTS HAVING DIFFERENT OPTICAL PATH LENGTHS

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a first light-emitting element including a first reflective electrode, a first transparent conductive layer being in contact
with the first reflective electrode, an EL layer being in contact with the first transparent conductive layer, and a semi-transmissive
and semi-reflective electrode being in contact with the EL layer; and

a second light-emitting element including a second reflective electrode, the EL layer being in contact with the second reflective
electrode, and the semi-transmissive and semi-reflective electrode in contact with the EL layer;

wherein the EL layer includes a first light-emitting layer emitting light with a wavelength ?Y, and a second light-emitting layer emitting light with a wavelength ?B,

wherein, in the first light-emitting element, an optical path length from the first reflective electrode to the first light-emitting
layer is 3?B/4 and an optical path length from the first reflective electrode to the semi-transmissive and semi-reflective electrode is
?B, and

wherein, in the second light-emitting element, an optical path length from the second reflective electrode to the second light-emitting
layer is ?R/4 and an optical path length from the second reflective electrode to the semi-transmissive and semi-reflective electrode
is ?R/2, where a wavelength relation of ?R>?Y>?B is satisfied.

US Pat. No. 9,287,878

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first logic block;
a second logic block; and
a programmable switch comprising:
a pass transistor;
a first transistor;
a second transistor; and
a third transistor,
wherein the first logic block and the second logic block are connectable with each other through the programmable switch,
wherein the first transistor, the pass transistor and the second transistor are connected in series in this order,
wherein sources and drains of both the first transistor and the second transistor are located between the first logic block
and the second logic block in a circuit diagram, and

wherein the semiconductor device is designed so that a potential can be supplied to one of a source and a drain of the pass
transistor via the third transistor when both of the first transistor and the second transistor are in off-state.

US Pat. No. 9,276,091

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR ENERGY LABO...

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first insulating layer over an oxide semiconductor layer;
forming a sacrificial layer overlapping with a part of the oxide semiconductor layer with the first insulating layer interposed
therebetween;

forming a second insulating layer over the sacrificial layer;
removing a part of the second insulating layer and a part of the sacrificial layer so that a top surface of the sacrificial
layer is exposed and the top surface of the sacrificial layer is substantially flush with a top surface of the rest of the
second insulating layer;

removing the sacrificial layer, thereby forming a third insulating layer which does not cover a part of the first insulating
layer;

supplying oxygen into a region of the oxide semiconductor layer after removing the sacrificial layer;
forming a conductive layer over the first insulating layer and the third insulating layer after the supplying oxygen; and
forming a gate electrode by processing the conductive layer so that a top surface of the third insulating layer is exposed
and a top surface of the processed conductive layer is substantially flush with the top surface of the third insulating layer,
and

wherein the region does not overlap with the third insulating layer.

US Pat. No. 9,263,693

LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A light-emitting device comprising:
a first light-emitting layer over an anode, the first light-emitting layer comprising a first phosphorescent compound, a first
organic compound, and a second organic compound;

a second light-emitting layer over the first light-emitting layer, the second light-emitting layer comprising a second phosphorescent
compound, the first organic compound, and the second organic compound; and

a cathode over the second light-emitting layer,
wherein an emission spectrum of an exciplex of the first organic compound and the second organic compound overlaps with an
absorption corresponding to direct transition from a singlet ground state to a triplet excited state in an absorption spectrum
of each of the first phosphorescent compound and the second phosphorescent compound, and

wherein the first light-emitting layer comprises a higher proportion of the second organic compound than the second light-emitting
layer.

US Pat. No. 9,276,129

SEMICONDUCTOR DEVICE IN WHICH OXYGEN DEFICIENCY IN SEMICONDUCTOR IS REDUCED AND METHOD FOR MANUFACTURING THE SAME

SEMICONDUCTOR ENERGY LABO...

1. A semiconductor device comprising:
a first insulating layer comprising silicon and oxygen over a substrate;
an oxide semiconductor layer over and in contact with the first insulating layer;
a gate electrode over the oxide semiconductor layer;
a protective insulating layer over the gate electrode, the protective insulating layer comprising an opening; and
a source electrode and a drain electrode electrically connected to the oxide semiconductor layer through the opening,
wherein the number of oxygen atoms per unit volume of the first insulating layer is more than twice the number of silicon
atoms per unit volume of the first insulating layer.

US Pat. No. 9,260,463

SUBSTITUTED PYRIMIDINATO IRIDIUM COMPLEXES AND SUBSTITUTED PYRAZINATO IRIDIUM COMPLEXES HAVING AN ALICYCLIC DIKETONE LIGAND

Semiconductor Energy Labo...

1. An organometallic complex represented by Formula (G2) or Formula (G3),

wherein:
X represents a five-membered or six-membered alicycle composed of carbon and hydrogen,
R1 represents an alkyl group having 1 to 4 carbon atoms, and

R2, R3, R4, R5, R6, R7, R8, and R9 independently represent an alkyl group having 1 to 4 carbon atoms or a phenyl group.

US Pat. No. 9,444,059

ORGANOMETALLIC COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A compound comprising a structure represented by a formula (G1):

R1 represents a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms, or a substituted or unsubstituted aryl group
having 6 to 10 carbon atoms;

R2 to R7 separately represent hydrogen or a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms; and

M represents a metal.

US Pat. No. 9,276,224

ORGANIC LIGHT EMITTING DEVICE HAVING DUAL FLEXIBLE SUBSTRATES

SEMICONDUCTOR ENERGY LABO...

1. A light emitting device comprising:
a first flexible substrate;
a pixel portion over the first flexible substrate, the pixel portion comprising a transistor and an organic light emitting
diode;

a wiring electrically connected to the pixel portion;
a second flexible substrate over the first flexible substrate with the pixel portion and the wiring therebetween, the second
flexible substrate comprising a hole overlapping with the wiring; and

a flexible printed circuit over the second flexible substrate, the flexible printed circuit electrically connected to the
wiring through the hole,

wherein the organic light emitting diode comprises a first electrode, a second electrode, and, an organic light emitting laver
between the first electrode and the second electrode.

US Pat. No. 9,263,451

STORAGE DEVICE INCLUDING MEMORY CELL USING TRANSISTOR HAVING OXIDE SEMICONDUCTOR AND AMPLIFIER CIRCUIT

Semiconductor Energy Labo...

1. A storage device comprising:
a word line and a bit line;
a memory cell comprising a transistor and a storage capacitor;
a capacitor; and
an amplifier circuit,
wherein the transistor includes an oxide semiconductor,
wherein a gate electrode of the transistor is electrically connected to the word line,
wherein one of source and drain electrodes of the transistor is electrically connected to the bit line,
wherein a first terminal of the storage capacitor is electrically connected to the other of the source and drain electrodes
of the transistor,

wherein a second terminal of the storage capacitor is electrically connected to a first terminal of the capacitor to form
a node,

wherein an input terminal of the amplifier circuit is directly connected to the second terminal of the storage capacitor,
and

wherein a second terminal of the capacitor is electrically connected to a ground terminal.

US Pat. No. 9,263,691

LIGHT EMITTING DEVICE CONTAINING IRIDIUM COMPLEX

SEMICONDUCTOR ENERGY LABO...

1. A light-emitting device comprising:
an anode;
a first layer over the anode, the first layer including a nitrogen-containing compound;
a second layer over and in contact with the first layer, the second layer including a first metal complex containing lithium
or aluminum, and a second metal complex containing iridium;

a third layer over and in contact with the second layer, the third layer including at least one of lithium and fluorine; and
a cathode over and in contact with the third layer.

US Pat. No. 9,281,358

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, the method comprising the steps of:
providing a substrate having an electrically insulating top surface;
forming a first oxide semiconductor film over the substrate in a first atmosphere;
forming a second oxide semiconductor film on and in contact with the first oxide semiconductor film in a second atmosphere
having a higher concentration in nitrogen than the first atmosphere;

performing heat treatment to the first oxide semiconductor film and the second oxide semiconductor film so that the first
oxide semiconductor film is crystallized in a first crystal structure and the second oxide semiconductor film is crystallized
in a second crystal structure,

wherein the first crystal structure is a non-wurtzite structure or a deformed structure of a non-wurtzite structure; and
wherein the second crystal structure is a wurtzite structure.

US Pat. No. 9,269,571

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a gate electrode;
forming a gate insulating layer over the gate electrode;
forming an oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer overlapping with the gate
electrode;

introducing oxygen ions into the oxide semiconductor layer;
performing heat treatment on the oxide semiconductor layer after introducing the oxygen ions to reduce an amount of oxygen
vacancies in the oxide semiconductor layer, wherein the heat treatment is performed at higher than or equal to 250° C. and
lower than or equal to 450° C.;

forming a source electrode and a drain electrode over and electrically connected to the oxide semiconductor layer after performing
the heat treatment; and

forming an insulating layer over the oxide semiconductor layer, the source electrode, and the drain electrode.

US Pat. No. 9,257,422

SIGNAL PROCESSING CIRCUIT AND METHOD FOR DRIVING SIGNAL PROCESSING CIRCUIT

SEMICONDUCTOR ENERGY LABO...

1. A method for driving a signal processing circuit comprising:
a first transistor;
a capacitor;
a second transistor;
a third transistor; and
a fourth transistor,
wherein a low-level potential and a high-level potential higher than the low-level potential are input to one of a source
and a drain of the first transistor,

wherein the other of the source and the drain of the first transistor is connected to one electrode of the capacitor and a
gate of the second transistor,

wherein a drain of the second transistor is connected to one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is connected to a gate of the fourth transistor, and
wherein a capacitance connected to the other of the source and the drain of the first transistor is twice a gate capacitance
of the first transistor or smaller,

the method comprising:
turning on the first transistor when the third transistor is off;
turning off the first transistor when the third transistor is off; and
turning on the third transistor when the first transistor is off,
wherein the first transistor is always off when the third transistor is on,
wherein the third transistor is always off when the first transistor is on, and
wherein a highest potential applied to a gate of the first transistor is the high-level potential and a lowest potential applied
to the gate of the first transistor is lower than the low-level potential.

US Pat. No. 9,154,035

BOOSTING CIRCUIT AND RFID TAG INCLUDING BOOSTING CIRCUIT

Semiconductor Energy Labo...

1. A circuit comprising:
a first transistor comprising a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor comprising a second gate electrode, a second source electrode, and a second drain electrode;
a third transistor comprising a third gate electrode, a third source electrode, and a third drain electrode; and
a capacitor comprising a first electrode and a second electrode,
wherein the first gate electrode is electrically connected to the first electrode of the capacitor,
wherein one of the first source electrode and the first drain electrode is electrically connected to the second electrode
of the capacitor,

wherein the second gate electrode is electrically connected to one of the second source electrode and the second drain electrode,
wherein the other of the second source electrode and the second drain electrode is electrically connected to the first gate
electrode,

wherein one of the third source electrode and the third drain electrode is electrically connected to the one of the first
source electrode and the first drain electrode,

wherein the other of the third source electrode and the third drain electrode is electrically connected to a power supply
line,

wherein the third gate electrode is electrically connected to a clock signal line,
wherein the one of the second source electrode and the second drain electrode is configured to be input a first signal,
wherein the first transistor includes a channel formation region comprising a first oxide semiconductor,
wherein the second transistor includes a channel formation region comprising a second oxide semiconductor, and
wherein an off-state current density per a channel width of 1 ?m at 25° C. is less than or equal to 1×10?19 A/?m in the first transistor or the second transistor.

US Pat. No. 9,245,983

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

11. A method for manufacturing a semiconductor device, the method comprising:
forming a second transistor over a first transistor, the formation of the second transistor comprising:
forming a first insulating film over the first transistor;
forming an oxide semiconductor film over the first insulating film;
heating the oxide semiconductor film in an inert gas and then in a gas containing oxygen;
processing the heated oxide semiconductor film with a dry etching or a wet etching; and
heating the processed oxide semiconductor film in an inert gas,
wherein the first transistor comprises a channel formation region in a single crystal semiconductor substrate.

US Pat. No. 9,516,713

LIGHT-EMITTING DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A light-emitting device comprising:
a circuit comprising at least a first unit and a second unit connected in parallel, each of the first unit and the second
unit comprising at least a first light emitting element and a second light emitting element connected in series,

wherein each of the first light emitting element and the second light emitting element includes a lower electrode in contact
with an insulating surface, a light-emitting body layer over the lower electrode, and an upper electrode over the light-emitting
body layer,

wherein the first unit comprises a first wiring between the first light emitting element and the second light emitting element
of the first unit, and the second unit comprises a second wiring between the first light emitting element and the second light
emitting element of the second unit, and

wherein the first wiring and the second wiring are electrically connected with a third wiring comprising the same material
as the lower electrode and in contact with the insulating surface.

US Pat. No. 9,294,126

CYCLIC REDUNDANCY CHECK CIRCUIT AND SEMICONDUCTOR DEVICE HAVING THE CYCLIC REDUNDANCY CHECK CIRCUIT

Semiconductor Energy Labo...

1. A system including a semiconductor device, comprising:
a semiconductor device implanted into a creature, the semiconductor device comprising:
an antenna; and
a circuit portion configured to transmit a signal to the antenna and to receive a signal from the antenna, the circuit portion
comprising a cyclic redundancy check circuit and a memory circuit, the memory circuit comprising:

a first transistor;
a first invertor comprising a second transistor and a third transistor, and a second invertor comprising a fourth transistor
and a fifth transistor, each of the first invertor and the second invertor being electrically connected to the first transistor;
and

a sixth transistor electrically connected to the first invertor and the second invertor,
wherein at least one of the first to sixth transistors comprises a semiconductor layer comprising a channel forming region,
and wherein the channel forming region comprises a metal oxide semiconductor.

US Pat. No. 9,281,405

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a semiconductor layer over the gate insulating layer;
a first conductive layer over the semiconductor layer;
a second conductive layer over the first conductive layer;
a first insulating layer over the second conductive layer; and
a hard mask layer over the first insulating layer,
wherein the hard mask layer comprises an opening which overlaps with a channel formation region of the semiconductor layer.

US Pat. No. 9,281,409

THIN FILM TRANSISTOR FOR INTEGRATED CIRCUIT

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first oxide semiconductor film over an insulating surface;
a second oxide semiconductor film over the first oxide semiconductor film;
a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide
semiconductor film, a side surface of the second oxide semiconductor film, and a top surface of the second oxide semiconductor
film;

a gate insulating film over the third oxide semiconductor film; and
a gate electrode which is in contact with the gate insulating film and faces the top surface and the side surface of the second
oxide semiconductor film,

wherein a thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor
film and a thickness of the gate insulating film, and

wherein a difference between the thickness of the first oxide semiconductor film and the sum of the thickness of the third
oxide semiconductor film and the thickness of the gate insulating film is larger than or equal to 20 nm.

US Pat. No. 9,530,892

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a transistor including:
an oxide semiconductor film containing In and Ga; and
an oxide film containing In or Ga adjacent to the oxide semiconductor film; and
a silicon oxide insulating film over the transistor,
wherein the silicon oxide insulating film contains oxygen at a higher proportion than a stoichiometric composition,
wherein a proportion of Ga in the oxide film containing In or Ga is higher than a proportion of Ga in the oxide semiconductor
film, and

wherein change in a threshold voltage of the transistor by a bias-temperature stress test each in dark and photostress is
within a range of more than or equal to ?1.0 V and less than or equal to 1.0 V.

US Pat. No. 9,299,814

MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first insulating film over a substrate;
forming an oxide semiconductor film over and in contact with the first insulating film;
performing a first heat treatment to the oxide semiconductor film;
patterning the oxide semiconductor film after performing the first heat treatment to form an oxide semiconductor layer that
includes a region comprising c-axis-aligned crystalline oxide semiconductor that is a non-single-crystal oxide material;

forming a second insulating film covering the oxide semiconductor layer; and
performing a second heat treatment to the oxide semiconductor layer after forming the second insulating film,
wherein a part of oxygen in the first insulating film is desorbed during the first heat treatment, and
wherein a part of the desorbed oxygen is supplied to the oxide semiconductor film.

US Pat. No. 9,244,323

LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A transistor comprising an oxide semiconductor layer, wherein characteristics of the transistor comprises:
an off-current being less than or equal to 10 aA/?m at room temperature; and
an off-current being less than or equal to 100 aA/?m at a temperature of 85° C.

US Pat. No. 9,305,496

ELECTRIC FIELD DRIVING DISPLAY DEVICE

Semiconductor Energy Labo...

1. An electric field driving display device comprising:
a first semiconductor layer over a substrate;
a second semiconductor layer over the substrate;
a conductive layer over the substrate;
a first gate electrode over the first semiconductor layer;
a second gate electrode over the second semiconductor layer;
a first insulating film over the first semiconductor layer, the second semiconductor layer,
the conductive layer, the first gate electrode and the second gate electrode;
a first electrode over the first insulating film, the first electrode being electrically connected to the first semiconductor
layer;

a second electrode over the first insulating film, the second electrode being electrically connected to the second semiconductor
layer;

a second insulating film over the first electrode and the second electrode;
a third electrode over the second insulating film, the third electrode being electrically connected to the first electrode;
a fourth electrode over the second insulating film, the fourth electrode being electrically connected to the second electrode;
a layer comprising a charged particle, over the second insulating film, the third electrode and the fourth electrode; and
a fifth electrode over the layer comprising the charged particle,
wherein the third electrode overlaps with a first region of the second insulating film,
wherein the fourth electrode overlaps with a second region of the second insulating film,
wherein a third region between the first region and the second region of the second insulating film overlaps with at least
part of the first electrode,

wherein the third electrode does not overlap with the third region of the second insulating film,
wherein the fourth electrode does not overlap with the third region of the second insulating film,
wherein the conductive layer overlaps with the first region of the second insulating film, and
wherein a shortest distance between the first electrode and the second electrode is approximately equal to a shortest distance
between the third electrode and the fourth electrode.

US Pat. No. 9,307,611

PIXEL CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A pixel circuit implementing a circuit diagram comprising:
a first transistor;
a second transistor;
a display element; and
a memory comprising a first output terminal and a second output terminal,
wherein:
in the circuit diagram, the first output terminal is directly connected to a gate of the first transistor;
in the circuit diagram, the second output terminal is directly connected to a gate of the second transistor;
in the circuit diagram, the display element is electrically connected to one of a source and a drain of the first transistor;
in the circuit diagram, the display element is electrically connected to one of a source and a drain of the second transistor;
in the circuit diagram, the one of the source and the drain of the first transistor is directly connected to the one of the
source and the drain of the second transistor;

in the circuit diagram, the other of the source and the drain of the first transistor is directly connected to the other of
the source and the drain of the second transistor; and

a polarity of the first transistor is different from a polarity of the second transistor.

US Pat. No. 9,153,341

SHIFT REGISTER, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first circuit, the first circuit comprising a first transistor, a second transistor, a third transistor, and a fourth transistor;
and

a second circuit, the second circuit comprising a fifth transistor, a sixth transistor, a seventh transistor, and a eighth
transistor,

wherein one of a source and a drain of the first transistor is connected to a first wire, the other of the source and the
drain of the first transistor is connected to a gate electrode of the second transistor and the other of a source and a drain
of the third transistor, and a gate electrode of the first transistor is connected to a fifth wire,

wherein one of a source and a drain of the second transistor is connected to a third wire and the other of the source and
the drain of the second transistor is connected to a sixth wire,

wherein one of the source and the drain of the third transistor is connected to a second wire, the other of the source and
the drain of the third transistor is connected to the gate electrode of the second transistor, and a gate electrode of the
third transistor is connected to a fourth wire,

wherein one of a source and a drain of the fourth transistor is connected to the second wire, the other of the source and
the drain of the fourth transistor is connected to the sixth wire, and a gate electrode of the fourth transistor is connected
to the fourth wire,

wherein the first wire is connected to a power source line,
wherein the fifth wire is connected to an input terminal,
wherein one of a source and a drain of the fifth transistor is connected to the first wire, the other of the source and the
drain of the fifth transistor is connected to a gate electrode of the sixth transistor and the other of a source and a drain
of the seventh transistor, and a gate electrode of the fifth transistor is connected to the sixth wire,

wherein one of a source and a drain of the sixth transistor is connected to the fourth wire and the other of the source and
the drain of the sixth transistor is connected to an eighth wire,

wherein one of the source and the drain of the seventh transistor is connected to the second wire, the other of the source
and the drain of the seventh transistor is connected to the gate electrode of the sixth transistor, and a gate electrode of
the seventh transistor is connected to a seventh wire,

wherein one of a source and a drain of the eighth transistor is connected to the second wire, the other of the source and
the drain of the eighth transistor is connected to the eighth wire, and a gate electrode of the eighth transistor is connected
to the seventh wire,

wherein a first clock signal is input to the third wire,
wherein a second clock signal is input to the fourth wire, and
wherein a third clock signal is input to the seventh wire.

US Pat. No. 9,290,842

ELECTRODE COVER AND EVAPORATION DEVICE

Semiconductor Energy Labo...

1. An evaporation device comprising:
a conductive plate;
an insulating plate over and in contact with the conductive plate;
a first electrode over and in contact with the insulating plate, the first electrode comprising an upper surface and a first
side surface; and

a second electrode over the first electrode,
wherein the evaporation device is configured so that the first electrode is covered by an electrode cover comprising first
and second portions,

wherein the first portion is configured to be in direct contact with the first side surface which faces to an evaporation
source holder,

wherein the second portion is configured to be in direct contact with the upper surface, to hold the evaporation source holder
by sandwiching the evaporation source holder with the second electrode, and to electrically connect the evaporation source
holder to the first electrode, and

wherein the electrode cover is configured to fully expose a side surface of the first electrode other than the first side
surface when the electrode cover covers the first electrode,

wherein the electrode cover is further configured so that an outer surface of the first portion and a side surface which faces
the evaporation source holder of the insulating plate exist in a coplane when the electrode cover covers the first electrode,
and

wherein the electrode cover is further configured so that the first portion contacts with an upper surface of the insulating
plate when the electrode cover covers the first electrode.

US Pat. No. 9,281,410

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising the steps of:
forming an oxide semiconductor film over a substrate having an insulating surface;
forming an insulating film over the oxide semiconductor film so that the insulating film covers an edge portion of the oxide
semiconductor film;

exposing the insulating film and the oxide semiconductor film to plasma generated under an atmosphere containing oxygen;
forming a gate insulating film over the oxide semiconductor film at a temperature lower than a temperature at which oxygen
contained in the oxide semiconductor film is eliminated after the step of exposing the insulating film and the oxide semiconductor
film to plasma;

forming a gate electrode overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween;
and

forming a source wiring and a drain wiring electrically connected the oxide semiconductor film,
wherein the edge portion of the insulating film is curved, and
wherein the gate insulating film is formed by using plasma generated by a microwave.

US Pat. No. 9,275,987

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first circuit portion comprising a first node and a second node;
a second circuit portion comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth
transistor, a sixth transistor, a first capacitor, and a second capacitor; and

an insulating film over the second transistor, the third transistor, the fifth transistor, and the sixth transistor,
wherein a gate of the second transistor and a first electrode of the first capacitor are electrically connected to the first
node through the first transistor,

wherein a gate of the fifth transistor and a first electrode of the second capacitor are electrically connected to the second
node through the fourth transistor,

wherein one of a source and a drain of the second transistor is electrically connected to the second node through the third
transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to the first node through the sixth
transistor,

wherein the first transistor and the fourth transistor each include an oxide semiconductor including indium in a channel formation
region, and

wherein the first transistor and the fourth transistor are provided over the insulating film.

US Pat. No. 9,394,614

METHOD FOR FORMING PROJECTIONS AND DEPRESSIONS, SEALING STRUCTURE, AND LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A method for forming projections and depressions, comprising:
forming a film over a surface, the film containing a first metal and a second metal whose etching rate is lower than an etching
rate of the first metal;

heating the film so that the second metal segregates;
selectively etching the first metal after heating the film; and
selectively etching the surface using a residue containing the second metal as a mask,
wherein the film contains aluminum as the first metal and nickel as the second metal.

US Pat. No. 9,293,477

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a first transistor, a second transistor, a third transistor, a first line, a second line, a third line, and a light-emitting
element,

wherein the first transistor includes:
a semiconductor layer comprising a curved region;
an insulating film over the semiconductor layer; and
a gate electrode over the insulating film,
wherein an entire part of the curved region of the semiconductor layer and at least a part of the gate electrode of the first
transistor overlap with each other,

wherein a first terminal of the first transistor is electrically connected to the first line,
wherein a second terminal of the first transistor is electrically connected to the light-emitting element,
wherein the gate electrode of the first transistor is directly connected to a first terminal of the second transistor,
wherein the gate electrode of the first transistor is directly connected to a first terminal of the third transistor,
wherein a gate electrode of the second transistor is directly connected to the second line, and
wherein a gate electrode of the third transistor is directly connected to the third line.

US Pat. No. 9,263,504

LIGHT-EMITTING DEVICE, INFORMATION PROCESSING DEVICE, AND IMAGING DEVICE

Semiconductor Energy Labo...

1. An electronic device comprising:
a light-emitting portion comprising:
a first substrate;
a pair of electrodes over the first substrate;
a second substrate over the pair of electrodes; and
a light-emitting layer between the pair of electrodes, the light-emitting layer comprising a light-emitting organic compound;
and

an imaging unit configured to image an object,
wherein:
the light-emitting portion comprises an opening which passes the first substrate and the second substrate so that the light-emitting
layer is located on both sides of the opening;

a side surface of the opening is covered by a sealant so that a side surface of the light-emitting layer is not exposed; and
the imaging unit is mounted in the opening.

US Pat. No. 9,293,513

SELF-LIGHT-EMITTING DEVICE COMPRISING PROTECTIVE PORTIONS ON A PIXEL ELECTRODE

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a substrate;
a semiconductor film over the substrate;
a gate electrode over the substrate and overlapping with the semiconductor film;
a gate insulating film interposed between the semiconductor film and the gate electrode, the gate insulating film comprising
silicon;

a first interlayer insulating film over the semiconductor film, the gate electrode, and the gate insulating film, the first
interlayer insulating film comprising silicon;

a wiring on the first interlayer insulating film, in a first contact hole formed in the first interlayer insulating film,
and in direct contact with the semiconductor film via the first contact hole formed in the first interlayer insulating film;

a second interlayer insulating film over the wiring, the second interlayer insulating film comprising a first organic resin;
a pixel electrode on the second interlayer insulating film and in electrical contact with the wiring via a second contact
hole formed in the second interlayer insulating film;

a first protective portion formed from a second organic resin on and in contact with the second interlayer insulating film
and a peripheral portion of the pixel electrode, and a second protective portion formed from the second organic resin on and
in contact with the pixel electrode in the second contact hole;

an EL layer on the pixel electrode, and on the first protective portion and the second protective portion; and
a common electrode on the EL layer and overlapping the pixel electrode.

US Pat. No. 9,281,408

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

6. A semiconductor device comprising:
a stack comprising a first oxide semiconductor layer and a second oxide semiconductor layer sequentially formed over an insulating
surface;

a source electrode layer in contact with a first side surface of the stack;
a drain electrode layer in contact with a second side surface opposite to the first side surface of the stack; and
a third oxide semiconductor layer,
wherein the third oxide semiconductor layer comprises a first layer in contact with part of a third side surface of the stack,
part of a top surface of the stack, and part of a fourth side surface opposite to the third side surface of the stack,

wherein the third oxide semiconductor layer comprises a second layer over the first layer,
wherein the first layer comprises a microcrystalline layer, and
wherein the second layer comprises a crystalline layer in which c-axes are aligned in a direction substantially perpendicular
to a surface of the first layer.

US Pat. No. 9,293,590

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a base insulating film;
a first metal oxide film over the base insulating film;
a source electrode and a drain electrode which are in contact with the first metal oxide film;
a gate insulating film over the first metal oxide film, the source electrode, and the drain electrode; and
a gate electrode provided over the first metal oxide film with the gate insulating film interposed therebetween,
wherein the gate insulating film comprises a first insulating film, a second metal oxide film, and a second insulating film,
wherein the first insulating film is in contact with the first metal oxide film,
wherein the second metal oxide film is sandwiched by the first insulating film and the second insulating film, and
wherein all elements contained in the first metal oxide film are the same as all elements contained in the second metal oxide
film.

US Pat. No. 9,281,366

SEMICONDUCTOR FILM, TRANSISTOR, SEMICONDUCTOR DEVICE, DISPLAY DEVICE, AND ELECTRONIC APPLIANCE

Semiconductor Energy Labo...

1. An oxide semiconductor film,
wherein the oxide semiconductor film has a plurality of electron diffraction patterns, which are observed in such a manner
that a surface where the oxide semiconductor film is formed is irradiated with an electron beam having a probe diameter whose
half-width is 1 nm while the position of the oxide semiconductor film and the position of the electron beam are relatively
moved,

wherein the plurality of electron diffraction patterns include 50 or more electron diffraction patterns which are observed
in different areas,

wherein the plurality of electron diffraction patterns are oriented randomly,
wherein a sum of a percentage of first electron diffraction patterns and a percentage of second electron diffraction patterns
accounts for 100% of the 50 or more electron diffraction patterns,

wherein the first electron diffraction patterns account for 90% or more of the 50 or more electron diffraction patterns,
wherein the first electron diffraction patterns include observed points which indicate that a c-axis is oriented in a direction
substantially perpendicular to the surface where the oxide semiconductor film is formed, and

wherein the second electron diffraction patterns include observed points that are not symmetry or an observed region disposed
in a ring shape.

US Pat. No. 9,187,689

ORGANOMETALLIC COMPLEX AND LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND ELECTRONIC DEVICE USING THE SAME

Semiconductor Energy Labo...

1. An organometallic complex comprising a structure represented by a general formula (C?):

wherein:
R1 represents an alkyl group having 1 to 4 carbon atoms;

R2 and R3 each separately represents hydrogen or an alkyl group having 1 to 4 carbon atoms;

Ar is represented by a general formula (C?-1), wherein R4 and R6 each separately represents hydrogen, and wherein R5 is a phenyl group;

M is iridium;
n is 2; and
? represents a position of carbon which bonds to M.

US Pat. No. 9,293,483

ELECTRONIC DEVICE AND ELECTRONIC APPARATUS

SEMICONDUCTOR ENERGY LABO...

1. A semiconductor device comprising an EL element, a first transistor, a second transistor, a capacitor, a first wiring,
a second wiring and a third wiring,
wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,
wherein a gate electrode of the first transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to the EL element,
wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,
wherein the first transistor comprises a first semiconductor region, a first insulating film over the first semiconductor
region, and the gate electrode over the first insulating film,

wherein the first semiconductor region is included in the same semiconductor layer as a second semiconductor region,
wherein the second semiconductor region overlaps with a conductive film with the first insulating film provided therebetween,
wherein the third wiring is located over the conductive film,
wherein the third wiring overlaps with the conductive film with a second insulating film provided therebetween,
wherein the conductive film is configured to serve as one terminal of the capacitor,
wherein the conductive film is directly connected to the third wiring, and
wherein a region where the conductive film is directly connected to the third wiring overlaps with the second semiconductor
region.

US Pat. No. 9,312,278

DISPLAY DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a pixel portion comprising:
a pixel transistor;
a first insulating film including an inorganic material and covering the pixel transistor;
a second insulating film including an organic material over the first insulating film; and
a third insulating film including an inorganic material over the second insulating film; and
a driver circuit portion outside the pixel portion, the driver circuit portion comprising:
a driving transistor configured to supply a signal to the pixel transistor;
the first insulating film covering the driving transistor; and
the second insulating film over the first insulating film,
wherein the third insulating film includes an opening portion over the driving transistor,
wherein the third insulating film does not overlap a semiconductor layer of the driving transistor,
wherein the pixel portion and the driver circuit portion are over a substrate,
wherein the substrate comprises a fifth region,
wherein an entire region of the fifth region and an entire region of the pixel portion overlap each other, and
wherein the third insulating film does not overlap any region of the substrate other than the fifth region.

US Pat. No. 9,257,569

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising a first transistor, the first transistor comprising:
an oxide layer comprising a channel formation region;
a source electrode layer in contact with the oxide layer;
a first drain electrode layer in contact with the oxide layer;
a second drain electrode layer in contact with the oxide layer;
a gate insulating film in contact with the oxide layer;
a first gate electrode layer overlapping with a part of the source electrode layer, the first drain electrode layer, and a
part of the oxide layer with the gate insulating film interposed therebetween;

a second gate electrode layer overlapping with the other part of the source electrode layer, the second drain electrode layer,
and the other part of the oxide layer with the gate insulating film interposed therebetween; and

a third gate electrode layer overlapping with a side surface of the oxide layer with the gate insulating film interposed therebetween,
wherein the first drain electrode layer and the second drain electrode layer are separated from each other by a space overlapping
with the oxide layer.

US Pat. No. 9,245,589

SEMICONDUCTOR DEVICE HAVING SCHMITT TRIGGER NAND CIRCUIT AND SCHMITT TRIGGER INVERTER

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a memory circuit portion;
a Schmitt trigger inverter;
a first transistor;
a second transistor;
a third transistor; and
a capacitor,
wherein an input terminal of the Schmitt trigger inverter and one of a source and a drain of the first transistor are electrically
connected to the memory circuit portion,

wherein an output terminal of the Schmitt trigger inverter is electrically connected to one of a source and a drain of the
second transistor,

wherein the other of the source and the drain of the second transistor, a first electrode of the capacitor, and a gate of
the third transistor are electrically connected to one another,

wherein a second electrode of the capacitor and one of a source and a drain of the third transistor are electrically connected
to a wiring, and

wherein the other of the source and the drain of the third transistor is electrically connected to the other of the source
and the drain of the first transistor.

US Pat. No. 9,231,042

LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a plurality of sub-pixels;
an insulating layer;
a first lower electrode over the insulating layer in one of the plurality of sub-pixels;
a second lower electrode over the insulating layer in another one of the plurality of sub-pixels;
a partition over the insulating layer, the partition positioned between the first lower electrode and the second lower electrode;
a stacked-layer film over the first lower electrode, the partition, and the second lower electrode, the stacked-layer film
comprising a light-emitting layer containing a light-emitting substance and a layer having higher conductivity than a conductivity
of the light-emitting layer;

an upper electrode over the stacked-layer film; and
a third electrode under the partition, and between the first lower electrode and the second lower electrode,
wherein a length in a longitudinal direction of the third electrode is longer than a length in a longitudinal direction of
any of the plurality of sub-pixels.

US Pat. No. 9,287,409

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer provided over the second oxide semiconductor layer to cover side surfaces of the second
oxide semiconductor layer;

a source electrode layer and a drain electrode layer over the third oxide semiconductor layer;
a gate insulating film over the source electrode layer and the drain electrode layer; and
a gate electrode layer over the gate insulating film to overlap with the first oxide semiconductor layer, the second oxide
semiconductor layer, and the third oxide semiconductor layer,

wherein the second oxide semiconductor layer has a smaller energy gap than the first oxide semiconductor layer and the third
oxide semiconductor layer,

wherein the third oxide semiconductor layer comprises crystals of which c-axes are aligned substantially in one direction.

US Pat. No. 9,281,237

TRANSISTOR HAVING REDUCED CHANNEL LENGTH

SEMICONDUCTOR ENERGY LABO...

1. A semiconductor device comprising:
a semiconductor substrate;
an insulating layer over the semiconductor substrate, the insulating layer comprising a groove in which a conductive film
comprising a first region and a second region is provided;

an oxide semiconductor film comprising a third region and a fourth region over a top surface of the insulating layer;
a gate insulating layer over the oxide semiconductor film;
a gate electrode over the gate insulating layer, the gate electrode overlapping with the third region; and
a sidewall in contact with a side surface of the gate electrode and a top surface of the gate insulating layer,
wherein the second region is over the first region,
wherein a width of the second region is greater than a width of the first region, and
wherein the fourth region is over and in contact with the second region.

US Pat. No. 9,299,813

SEMICONDUCTOR DEVICE AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a bit line;
a source line;
a word line; and
a memory cell comprising a first transistor and a second transistor,
wherein the first transistor is a p-channel transistor,
wherein the first transistor comprises a first gate, a first source, a first drain, and a first channel formation region comprising
crystalline silicon,

wherein the second transistor comprises a second gate, a second source, a second drain, and an oxide semiconductor layer including
a second channel formation region,

wherein the first gate is electrically connected to one of the second source and the second drain,
wherein one of the first source and the first drain and the other of the second source and the second drain are electrically
connected to the bit line,

wherein the other of the first source and the first drain is electrically connected to the source line, and
wherein the second gate is electrically connected to the word line.

US Pat. No. 9,281,412

FIELD EFFECT TRANSISTOR

Semiconductor Energy Labo...

12. A field effect transistor comprising:
a first semiconductor layer including a first oxide semiconductor;
a second semiconductor layer including a second oxide semiconductor and being in contact with a first surface of the first
semiconductor layer;

a third semiconductor layer including a third oxide semiconductor and being in contact with a second surface of the first
semiconductor layer;

a conductive layer adjacent to the third semiconductor layer; and
an insulating film between the conductive layer and the third semiconductor layer,
wherein a bandgap of each of the second oxide semiconductor and the third oxide semiconductor is wider than a bandgap of the
first oxide semiconductor,

wherein an energy difference between a vacuum level of the second oxide semiconductor and a Fermi level of the second oxide
semiconductor is larger than an energy difference between a vacuum level of the first oxide semiconductor and a Fermi level
of the first oxide semiconductor, and

wherein an energy difference between a vacuum level of the third oxide semiconductor and a Fermi level of the third oxide
semiconductor is larger than the energy difference between the vacuum level of the first oxide semiconductor and the Fermi
level of the first oxide semiconductor.

US Pat. No. 9,425,045

SEMICONDUCTOR DEVICE INCLUDING OXIDE SEMICONDUCTOR AND MANUFACTURING METHOD THEREOF

SEMICONDUCTOR ENERGY LABO...

1. A method for manufacturing a semiconductor device comprising the step of:
forming an oxide semiconductor film serving as a channel formation region of a transistor by a sputtering method at a temperature
higher than 300° C. and lower than or equal to 500° C. so that the number of water molecules eliminated from the oxide semiconductor
film is 0.5/nm3 or less according to thermal desorption spectroscopy and a carrier density of the oxide semiconductor film is less than 1×1012/cm3,

wherein the number of water molecules is calculated by comparing a first value of integral of a TDS spectrum of water molecules
in the oxide semiconductor film with a second value of integral of a TDS spectrum of hydrogen molecules in a reference sample,

wherein the first value of integral and the second value of integral are calculated within a temperature range of higher than
or equal to 150° C. and lower than or equal to 400° C., and

wherein the reference sample is a silicon wafer.

US Pat. No. 9,257,594

THIN FILM TRANSISTOR WITH AN OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising a thin film transistor, the thin film transistor comprising:
a gate electrode layer;
a gate insulating layer over the gate electrode layer;
a first source region and a first drain region over the gate insulating layer;
a source electrode layer over the first source region;
a drain electrode layer over the first drain region;
a second source region over the source electrode layer;
a second drain region over the drain electrode layer; and
an oxide semiconductor layer over the gate insulating layer, the first source region, the first drain region, the source electrode
layer, the drain electrode layer, the second source region, and the second drain region,

wherein the oxide semiconductor layer has a higher oxygen concentration than oxygen concentrations of the first source region,
the first drain region, the second source region, and the second drain region,

wherein the oxide semiconductor layer is in contact with the gate insulating layer, the first source region, the first drain
region, the second source region, and the second drain region, and

wherein each of the oxide semiconductor layer, the first source region, the first drain region, the second source region,
and the second drain region comprises at least indium, gallium, and zinc.

US Pat. No. 9,608,006

SEMICONDUCTOR DEVICE AND TOUCH PANEL

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a display portion including a plurality of pixels;
a photosensor adjacent to at least one of the plurality of pixels;
an arithmetic circuit; and
a gradient detector,
wherein a function relating to display and input on the display portion is switched by the arithmetic circuit in response
to a signal from the gradient detector,

wherein the photosensor comprises:
a light-receiving element comprising a non-single-crystal semiconductor layer between a pair of electrodes;
a ground line electrically connected to one of the pair of electrodes;
a first transistor, a gate of which is electrically connected to a signal line, one of a source and a drain of which is electrically
connected to the other of the pair of electrodes, and a channel formation region of which is in a first oxide semiconductor
layer;

a second transistor, a gate of which is electrically connected to a reset line, one of a source and a drain of which is electrically
connected to the other of the source and the drain of the first transistor, the other of the source and the drain of which
is electrically connected to a power supply line, and a channel formation region of which is in a second oxide semiconductor
layer;

a third transistor, a gate of which is electrically connected to the other of the source and the drain of the first transistor
and the one of the source and the drain of the second transistor, one of a source and a drain of which is electrically connected
to the power supply line, and a channel formation region of which is in a third oxide semiconductor layer; and

a fourth transistor, a gate of which is electrically connected to a selection line, one of a source and a drain of which is
electrically connected to the other of the source and the drain of the third transistor, the other of the source and the drain
of which is electrically connected to a photosensor output signal line, and a channel formation region of which is in a fourth
oxide semiconductor layer.

US Pat. No. 9,331,207

OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEROF

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a gate electrode;
a gate insulating film over the gate electrode;
an oxide semiconductor film in contact with the gate insulating film, the oxide semiconductor film including a channel formation
region overlapping with the gate electrode; and

a source electrode and a drain electrode over the oxide semiconductor film; and
an insulating layer over the source electrode and the drain electrode,
wherein the source electrode and the drain electrode each include a first metal film, a second metal film over the first metal
film and containing copper, and a third metal film over the second metal film, and

wherein an end portion of the second metal film is offset from end portions of the first metal film and the third metal film
from a center of the channel formation region.

US Pat. No. 9,225,336

PROGRAMMABLE LOGIC DEVICE AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A programmable logic device comprising:
a programmable switch element comprising:
an input terminal;
an output terminal;
a first transistor;
a second transistor;
an insulating film over the first transistor and the second transistor;
a third transistor over the insulating film;
a fourth transistor over the insulating film;
a fifth transistor;
a sixth transistor;
a seventh transistor over the insulating film; and
an eighth transistor over the insulating film,
wherein a first terminal of the first transistor is electrically connected to the input terminal,
wherein a second terminal of the first transistor and a first terminal of the second transistor are electrically connected
to each other,

wherein a second terminal of the second transistor is electrically connected to the output terminal,
wherein a first terminal of the third transistor is electrically connected to a gate of the first transistor,
wherein a first terminal of the fourth transistor is electrically connected to a gate of the second transistor,
wherein a first terminal of the fifth transistor is electrically connected to the input terminal,
wherein a second terminal of the fifth transistor and a first terminal of the sixth transistor are electrically connected
to each other,

wherein a second terminal of the sixth transistor is electrically connected to the output terminal,
wherein a first terminal of the seventh transistor is electrically connected to a gate of the fifth transistor,
wherein a first terminal of the eighth transistor is electrically connected to a gate of the sixth transistor,
wherein a second terminal of the third transistor and a second terminal of the seventh transistor are electrically connected
to each other, and

wherein a gate of the fourth transistor and a gate of the eighth transistor are electrically connected to each other.

US Pat. No. 9,047,822

DISPLAY DEVICE WHERE SUPPLY OF CLOCK SIGNAL TO DRIVER CIRCUIT IS CONTROLLED

Semiconductor Energy Labo...

1. A display device comprising:
a first connecting terminal;
a second connecting terminal;
a signal line driver circuit comprising a shift register circuit, a first latch circuit and a second latch circuit, an analog
switch and a first transistor;

a pixel comprising:
a second transistor over a substrate;
a capacitor element over the substrate, the capacitor element comprising:
a first electrode comprising a same material as a gate electrode of the second transistor;
a second electrode on a first insulating film, the second electrode overlapping the first electrode with the first insulating
film therebetween; and

a third electrode on a second insulating film, the third electrode overlapping the second electrode with the second insulating
film therebetween;

a light-emitting element over the substrate, the light-emitting element comprising:
a fourth electrode electrically connected to one of a source and a drain of the second transistor;
an organic compound layer over the fourth electrode; and
a fifth electrode over the organic compound layer, the fifth electrode being electrically connected to the first connecting
terminal and the second connecting terminal;

a color filter over the light-emitting element, the color filter overlapping with the fourth electrode, the organic compound
layer and the fifth electrode; and

a black matrix on the color filter, the black matrix overlapping with the second transistor;
a scan line electrically connected to the pixel;
a first scan line driver circuit electrically connected to the scan line via a first switch; and
a second scan line driver circuit electrically connected to the scan line via a second switch,
wherein the shift register circuit is operatively connected to the first latch circuit,
wherein the first latch circuit is operatively connected to the second latch circuit,
wherein the second latch circuit is directly connected to the analog switch such that an output of the second latch circuit
is input to the pixel through the analog switch,

wherein one of a source and a drain of the first transistor is electrically connected to an output terminal of the second
latch circuit,

wherein the other of the source and the drain of the first transistor is electrically connected to a wire to which a potential
is applied,

wherein a clock signal is supplied to the shift register circuit in a first display mode,
wherein operation of the shift register circuit is stopped by stopping the supply of the clock signal to the shift register
circuit in a second display mode,

wherein the signal line driver circuit is configured to input an analog voltage to the pixel in the first display mode,
wherein the signal line driver circuit is configured to input a digital signal to the pixel in the second display mode, and
wherein the pixel is rewritten once every several frame periods in the second display mode.

US Pat. No. 9,489,088

INPUT-OUTPUT DEVICE AND METHOD FOR DRIVING INPUT-OUTPUT DEVICE

Semiconductor Energy Labo...

1. An input-output device comprising:
a light unit comprising Z (Z is a natural number of 3 or more) first light-emitting diodes emitting light with a wavelength
in a visible light range and a second light-emitting diode emitting light with a wavelength in an infrared range;

X (X is a natural number) display circuits overlapping with the light unit; and
a plurality of photodetectors overlapping with the light unit,
wherein the plurality of photodetectors include a filter for absorbing light with a wavelength in a visible light range,
wherein each of the plurality of photodetectors comprises a first transistor, a second transistor and a photoelectric conversion
element,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to the photoelectric
conversion element,

wherein a gate of the second transistor is electrically connected to the other of the source electrode and the drain electrode
of the first transistor,

wherein the Z first light-emitting diodes configured to emit light of different colors,
wherein the Z first light-emitting diodes configured to emit light sequentially in a first frame period,
wherein the second light-emitting diode is configured not to emit light during a first period in which a first light-emitting
diode of the Z first light-emitting diodes emits light and configured to emit light during a second period in which second
to Z-th light-emitting diodes of the Z first light emitting diodes emit light sequentially, in the first frame period,

wherein the X display circuits are configured to receive a display selection signal, receive a display data signal in accordance
with the display selection signal, and set to be in a display state in accordance with data of the display data signal, and

wherein the plurality of photodetectors are configured to perform detection by a global shutter method in which the plurality
of photodetectors receive the same photodetection control signal, and generate data based on illuminance of incident light
in accordance with the photodetection control signal during the second period of the first frame period.

US Pat. No. 9,263,705

SUCCESSIVE DEPOSITION APPARATUS AND SUCCESSIVE DEPOSITION METHOD

Semiconductor Energy Labo...

1. A method for successive deposition, comprising:
depositing a first deposition layer over a substrate with a first deposition source;
depositing a second deposition layer over the first deposition layer with a second deposition source; and
depositing a third deposition layer in which a material contained in the second deposition source is mixed with a material
contained in a third deposition source over the second deposition layer with the second deposition source and the third deposition
source,

wherein a highest occupied molecular orbital (HOMO) level of the material contained in the second deposition source is adjusted
to a highest occupied molecular orbital (HOMO) level of a material of the first deposition source, and

wherein the second deposition layer includes only an auxiliary dopant material.

US Pat. No. 9,437,832

LIGHT-EMITTING DEVICE AND PEELING METHOD

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a first substrate having flexibility;
a second substrate having flexibility;
an element layer between the first substrate and the second substrate;
an insulating layer between the first substrate and the element layer;
a first bonding layer between the first substrate and the insulating layer;
a second bonding layer between the second substrate and the element layer,
wherein the element layer comprises a light-emitting element,
wherein the first bonding layer comprises a first portion whose hardness is higher than Shore D of 70,
wherein the second bonding layer comprises a second portion whose hardness is higher than Shore D of 70,
wherein the first substrate comprises a third portion whose coefficient of expansion is less than 58 ppm/° C., and
wherein the second substrate comprises a fourth portion whose coefficient of expansion is less than 58 ppm/° C.

US Pat. No. 9,245,907

DISPLAY DEVICE AND ELECTRONIC DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A display device comprising:
a transistor over a substrate, the transistor comprising:
a semiconductor layer; and
source and drain electrode layers over the semiconductor layer;
a reflective electrode layer in a same layer as the source and drain electrode layers;
an anti-oxidation conductive layer over and in contact with one of the source and drain electrode layers;
an insulating layer over the source and drain electrode layers and the reflective electrode layer;
a coloring layer overlapping with the reflective electrode layer; and
a pixel electrode layer over and in contact with the anti-oxidation conductive layer,
wherein the pixel electrode layer and the coloring layer overlap with each other, and
wherein the pixel electrode layer is connected to the one of the source and drain electrode layers through the anti-oxidation
conductive layer.

US Pat. No. 9,287,405

SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an oxide semiconductor film over an oxide insulating film;
a gate insulating film over the oxide semiconductor film;
a gate electrode layer over the gate insulating film overlapping with the oxide semiconductor film;
an insulating film including an aluminum oxide film covering an entire top surface and an entire side surface of the gate
electrode layer;

an interlayer insulating layer over the oxide semiconductor film, the gate insulating film, the gate electrode layer, and
the insulating film including the aluminum oxide film, wherein an opening reaching the oxide semiconductor film is provided
in the interlayer insulating layer; and

a wiring layer in contact with the oxide semiconductor film and a top surface and a side surface of the insulating film including
the aluminum oxide film, the wiring layer being provided in the opening,

wherein the interlayer insulating layer is in contact with a top surface and a side surface of the oxide semiconductor film
and the top surface of the insulating film including the aluminum oxide film, and

wherein the insulating film including the aluminum oxide film is in contact with the top surface of the oxide semiconductor
film.

US Pat. No. 9,281,407

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

7. A semiconductor device comprising:
a gate electrode;
an insulating film over the gate electrode; and
an oxide semiconductor film including a channel formation region over the insulating film,
wherein the insulating film and the oxide semiconductor film comprise hydrogen,
wherein a peak of a concentration profile of the hydrogen is located in the insulating film,
wherein the insulating film includes a first region and a second region,
wherein the first region and the channel formation region overlap each other,
wherein the second region and the channel formation region do not overlap each other, and
wherein a hydrogen concentration in the second region is higher than a hydrogen concentration in the first region.

US Pat. No. 9,188,323

LIGHTING DEVICE

Semiconductor Energy Labo...

1. A lighting device comprising:
a first housing comprising a first depressed portion and a second depressed portion;
a light-emitting element over the first housing;
a metal plate over the light-emitting element;
a second housing over the metal plate;
a first adhesive layer in and over the first depressed portion, and between the first housing and the metal plate; and
a second adhesive layer in and over the second depressed portion, and between the first housing and the second housing,
wherein the first depressed portion and the second depressed portion are spaced from each other.

US Pat. No. 9,299,879

PEELING METHOD AND METHOD FOR MANUFACTURING DISPLAY DEVICE USING THE PEELING METHOD

Semiconductor Energy Labo...

1. A method for manufacturing a display device comprising the steps of:
forming a metal film comprising a metal over a glass substrate;
forming over the metal film a first insulating film comprising oxygen;
forming an element layer over the first insulating film, the element layer comprising:
a semiconductor film over the first insulating film;
a first electrode in electrical contact with the semiconductor film;
a second insulating film covering end portions of the first electrode;
a light emitting layer on the first electrode; and
a second electrode on the light emitting layer;
fixing a second substrate over the element layer;
separating the glass substrate from the first insulating film by peeling, the separation occurring between the metal film
and the first insulating film; and

fixing a third substrate underneath the first insulating film in place of the glass substrate after the separation from the
glass substrate, the third substrate being a substrate film and being fixed to the first insulating film with an adhesive
layer; and

separating the second substrate from the element layer,
wherein a film of an oxide of the metal is between the metal film and the first insulating film prior to the separation of
the glass substrate from the first insulating film,

wherein a thickness of the metal film is comprised between 10 nm and 200 nm,
wherein a thickness of the film of the oxide of the metal is comprised between 0.1 nm and 100 nm.

US Pat. No. 9,287,557

METHOD FOR MANUFACTURING NONAQUEOUS ELECTROLYTE SECONDARY BATTERY

SEMICONDUCTOR ENERGY LABO...

1. A method for manufacturing a nonaqueous electrolyte secondary battery, comprising:
forming a slurry including active material particles of an oxide, a binder and a conduction auxiliary agent, wherein each
of the active material particles comprises a transition metal, and an average value of cube roots of volume of each of the
active material particles is 5 nm to 50 nm;

applying the slurry to a surface of a current collector;
exposing the current collector coated with the slurry to a non-uniform magnetic field to separate the slurry into a first
portion of the slurry that includes the binder and the conduction auxiliary agent, and does not substantially include the
active material particles and a second portion of the slurry that contains most of the active material particles and is located
between the current collector and the first portion of the slurry; and

selectively removing the first portion of the slurry,
wherein a maximum of the non-uniform magnetic field at the surface of the current collector is 0.01 T to 2 T, and
wherein the step of selectively removing the first portion of the slurry is followed by a step of drying the second portion
of the slurry.

US Pat. No. 9,270,173

DC CONVERTER CIRCUIT AND POWER SUPPLY CIRCUIT

Semiconductor Energy Labo...

1. A power supply circuit comprising:
an inductor comprising a terminal;
a transistor connected to the terminal of the inductor, the transistor comprising:
a first conductive film over a first insulating layer, the first conductive film functioning as one of a source electrode
and a drain electrode;

an oxide semiconductor layer over the first conductive film;
a second conductive film over the oxide semiconductor layer, the second conductive film functioning as the other of the source
electrode and the drain electrode; and

a gate electrode over the second conductive film,
a rectifier connected to the terminal of the inductor; and
a control circuit connected to the transistor,
wherein a hydrogen concentration of the oxide semiconductor layer is less than or equal to 5×1019 atoms/cm3, and

wherein, in a top view of the transistor, the gate electrode includes a concentric circular shape having an opening overlapping
the second conductive film.

US Pat. No. 9,099,374

DISPLAY DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a substrate; and
a plurality of pixels over the substrate, the plurality of pixels comprising:
a first pixel comprising a transistor and a light-emitting element, the light-emitting element having a chromaticity whose
x-coordinate in a CIE-XY chromaticity diagram is 0.50 or more;

a second pixel and a third pixel each comprising a transistor and a light-emitting element, the light-emitting element having
a chromaticity whose y-coordinate in the CIE-XY chromaticity diagram is 0.55 or more;

a fourth pixel and a fifth pixel each comprising a transistor and a light-emitting element, the light-emitting element having
a chromaticity whose x-coordinate and y-coordinate in the CIE-XY chromaticity diagram are 0.20 or less and 0.25 or less, respectively;
and

a sixth pixel configured to emit white light,
wherein the transistor in each of the first to sixth pixels comprises an oxide semiconductor,
wherein the first pixel, the second pixel and the fourth pixel are arranged in a first row,
wherein the sixth pixel is arranged in a second row,
wherein the third pixel and the fifth pixel are arranged in a third row,
wherein the first row is adjacent to the second row,
wherein the second row is adjacent to the third row,
wherein the light-emitting elements provided in the fourth pixel and the fifth pixel have different thickness from each other,
wherein the fourth pixel and the fifth pixel have different emission spectrums, and
wherein a shape of each of the first to fifth pixels comprises a curvature.

US Pat. No. 9,991,290

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device, comprising:forming a first conductive film on an insulating surface;
forming a second conductive film over the first conductive film to be in contact with each other;
forming a first mask and a second mask over the second conductive film using a photo mask or a reticle each of which is provided with a pattern having a light intensity reducing function, the pattern comprising a diffraction grating pattern or a semi-translucent film wherein the first mask is partially thin;
forming a first wire and a second wire by etching the first conductive film and the second conductive film using the first mask and the second mask, wherein the second wire corresponding to the second conductive film has a part narrower than the first wire corresponding to the first conductive film;
forming a third wire electrically connected with the first wire and the second wire and intersecting with the first wire and the second wire; and
forming an insulating film covering the first wire, the second wire, and the third wire,
wherein the third wire overlaps with the first wire in a part in which the first wire is wider than the second wire.

US Pat. No. 9,356,030

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING ANTIFUSE WITH SEMICONDUCTOR AND INSULATING FILMS AS INTERMEDIATE LAYER

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device comprising a plurality of memory cells each comprising an antifuse, wherein
the antifuse comprises a first conductive layer, a second conductive layer, and an intermediate layer interposed between the
first conductive layer and the second conductive layer, comprising:
forming the first conductive layer;
forming a semiconductor film of the intermediate layer so as to be in direct contact with an upper surface of the first conductive
layer;

forming an insulating film of the intermediate layer so as to be in direct contact with the semiconductor film of the intermediate
layer; and

forming the second conductive layer so as to be in direct contact with an upper surface of the insulating film of the intermediate
layer,

wherein a thickness of the semiconductor film is greater than or equal to 5 nm and less than or equal to 200 nm, and
wherein a thickness of the insulating film is greater than or equal to 1 nm and less than or equal to 20 nm.

US Pat. No. 9,236,428

SEMICONDUCTOR ELEMENT, METHOD FOR MANUFACTURING THE SEMICONDUCTOR ELEMENT, AND SEMICONDUCTOR DEVICE INCLUDING THE SEMICONDUCTOR ELEMENT

Semiconductor Energy Labo...

10. A semiconductor device comprising:
a first insulating film;
a semiconductor film over the first insulating film;
a second insulating film over the semiconductor film;
a first electrode over the second insulating film; and
a second electrode over the second insulating film,
wherein the semiconductor film comprises indium, zinc, and oxygen, and
wherein the first electrode and the second electrode each penetrate the semiconductor film and are in contact with the first
insulating film.

US Pat. No. 9,130,367

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a protection circuit including a first conductive layer, a second conductive layer, and a semiconductor layer,
wherein the first conductive layer and the second conductive layer are spaced apart from each other,
wherein the semiconductor layer includes an oxide semiconductor layer,
wherein the first conductive layer and the second conductive layer are electrically connected to the semiconductor layer in
opening portions in an insulating layer which is in contact with the semiconductor layer, and

wherein the protection circuit does not include a transistor.

US Pat. No. 9,576,981

SEMICONDUCTOR DEVICE HAVING A GATE INSULTING FILM WITH THICK PORTIONS ALIGNED WITH A TAPERED GATE ELECTRODE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a transistor comprising:
a first semiconductor layer including a pair of LDD regions, a channel region between the pair of LDD regions, and source
and drain regions;

an insulating layer over the first semiconductor layer; and
a gate electrode over the insulating layer, the gate electrode including a first tapered side surfaces; and
a capacitor comprising:
a second semiconductor layer including an impurity region, the second semiconductor layer being contiguous with the first
semiconductor layer; and

a capacitor wiring over the second semiconductor layer, the capacitor wiring including a second tapered side surfaces,
wherein the insulating layer includes a first region overlapping the channel region and a second region overlapping one of
the source and drain regions, and

wherein a thickness of the first region is thicker than the second region.

US Pat. No. 9,425,107

MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A memory device comprising:
an insulating surface;
a transistor over the insulating surface, the transistor comprising a bit line, a semiconductor layer, a gate insulating layer,
and a word line, the gate insulating layer being interposed between a side face of the semiconductor layer and the word line;
and

a capacitor overlapping the transistor, the capacitor comprising an insulating layer interposed between a capacitor electrode
and a capacitor line, the capacitor electrode being in electrical contact with the semiconductor layer,

wherein a top surface of the semiconductor layer, a top surface of the gate insulating layer, and a top surface of the word
line are in a same horizontal plane,

wherein the bit line, the semiconductor layer, the capacitor electrode, the insulating layer, and the capacitor line are stacked
in this order, and

wherein the semiconductor layer comprises a semiconductor material having a wider band gap than silicon.

US Pat. No. 9,281,403

PEELING METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

11. A display device comprising:
a first flexible substrate;
a first bonding layer on and in contact with the first flexible substrate;
a film comprising an organic material, the film on and in contact with the first bonding layer;
a first insulating film on and in contact with the film;
a first thin film transistor in a pixel portion over the first insulating film, the first thin film transistor including a
first semiconductor film and a first gate electrode with a first gate insulating film interposed therebetween;

a second thin film transistor in a driver circuit portion over the first insulating film, the second thin film transistor
including a second semiconductor film and a second gate electrode with a second gate insulating film interposed therebetween;

a second insulating film over the first thin film transistor and the second thin film transistor;
a pixel electrode over the second insulating film, the pixel electrode being electrically connected to the first thin film
transistor;

a bank over an edge portion of the pixel electrode;
a light emitting layer comprising an organic light emitting material over the pixel electrode;
a second electrode over the light emitting layer and the second thin film transistor; and
a third insulating film on and in contact with the second electrode.

US Pat. No. 9,190,527

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first oxide layer;
an oxide semiconductor layer over and in contact with the first oxide layer;
a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer;
a second oxide layer over the source electrode layer and the drain electrode layer and in contact with the oxide semiconductor
layer;

a gate insulating layer over the second oxide layer;
a gate electrode layer over the gate insulating layer; and
an insulating layer over the gate electrode layer,
wherein the insulating layer is in contact with a side surface of the second oxide layer and a side surface of the gate insulating
layer,

wherein the oxide semiconductor layer includes one or more metal elements,
wherein the first oxide layer and the second oxide layer include at least one of the metal elements included in the oxide
semiconductor layer, and

wherein the insulating layer has lower permeability to oxygen than the second oxide layer and the gate insulating layer.

US Pat. No. 9,485,883

WIRELESS SENSOR DEVICE

Semiconductor Energy Labo...

1. A sensor device comprising:
a substrate comprising an antistatic film;
a circuit comprising a plurality of semiconductor elements over the substrate;
an antenna electrically connected to the circuit over the substrate;
a sensor provided over the substrate and electrically connected to the circuit; and
a flexible secondary battery over the substrate and electrically connected to the circuit and the antenna,
wherein the sensor device is configured to be implanted in a living body.

US Pat. No. 9,298,057

DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a pixel portion comprising:
a first transistor;
a first insulating film over the first transistor;
a second insulating film over the first insulating film;
a third insulating film covering the second insulating film; and
a first electrode over the third insulating film, the first electrode being electrically connected to the first transistor;
and

a driver circuit portion comprising:
a second transistor;
the first insulating film over the second transistor; and
the second insulating film over the first insulating film,
wherein the third insulating film is in a opening provided in the second insulating film,
wherein the first insulating film comprises an inorganic insulating material,
wherein the second insulating film comprises an organic insulating material,
wherein the third insulating film comprises an inorganic insulating material, and
wherein an edge portion of the second insulating film overlaps with the third insulating film.

US Pat. No. 9,190,525

SEMICONDUCTOR DEVICE INCLUDING OXIDE SEMICONDUCTOR LAYER

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first insulating layer over an insulating surface;
a first oxide semiconductor layer over the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a third oxide semiconductor layer over the second oxide semiconductor layer;
a first electrode layer and a second electrode layer over the third oxide semiconductor layer; and
a second insulating layer over the third oxide semiconductor layer,
wherein the first oxide semiconductor layer, the second oxide semiconductor layer and the third oxide semiconductor layer
comprise same constituent elements,

wherein a composition of the second oxide semiconductor layer is different from a composition of the first oxide semiconductor
layer and a composition of the third oxide semiconductor layer, and

wherein an energy level of a bottom of a conductive band of the first oxide semiconductor layer is continuously changed to
an energy level of a bottom of a conductive band of the second oxide semiconductor layer at an interface between the second
oxide semiconductor layer and the first oxide semiconductor layer.

US Pat. No. 9,059,247

METHOD FOR MANUFACTURING SOI SUBSTRATE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A method for manufacturing an SOI substrate, comprising the steps of:
forming a brittle layer in a single-crystalline semiconductor substrate so that a single-crystalline semiconductor layer is
provided on the brittle layer;

forming a cap layer over the single-crystalline semiconductor layer;
bonding the single-crystalline semiconductor layer and a supporting substrate to each other with the cap layer interposed
therebetween; and

separating the single-crystalline semiconductor layer from the single-crystalline semiconductor substrate at the brittle layer
so that the single-crystalline semiconductor layer is formed over the supporting substrate with the cap layer interposed therebetween,

wherein a thickness from a top surface to a bottom surface of the single-crystalline semiconductor substrate is 50 ?m or less,
and

wherein the top surface and the bottom surface of the single-crystalline semiconductor substrate are exposed to air.

US Pat. No. 9,263,469

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

21. A display panel comprising:
a substrate;
a pixel portion comprising on the substrate:
first pixels configured to emit red light and each comprising:
a first transistor comprising a first semiconductor layer; and
a first light emitting element electrically connected to the first semiconductor layer;
second pixels configured to emit light other than red light and each comprising:
a second transistor comprising a second semiconductor layer;
a second light emitting element electrically connected to the second semiconductor layer; and
a pixel color filter overlapping with the second light emitting element;
a third semiconductor layer on the substrate and outside of the pixel portion;
a first red color filter; and
a second red color filter,
wherein the first red color filter extends continuously to overlap with the first and the second transistors and with the
first light emitting elements of the first pixels configured to emit red light,

wherein the first red color filter comprises openings overlapping with the second light emitting elements of the second pixels
configured to emit light other than red light, and

wherein the second red color filter is separate from the first red color filter, and overlaps with the third semiconductor
layer.

US Pat. No. 9,104,395

PROCESSOR AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

1. A processor comprising:
a first circuit block connected to a first high potential power supply line;
a second circuit block comprising a first memory element and connected to a second high potential power supply line; and
a third circuit block comprising a second memory element and connected to a third high potential power supply line,
wherein the first high potential power supply line is electrically connected to a fourth high potential power supply line
through a first switch and a second switch,

wherein the second high potential power supply line is electrically connected to the fourth high potential power supply line
through the first switch,

wherein the third high potential power supply line is electrically connected to the fourth high potential power supply line
through the first switch and a third switch and to the first high potential power supply line through a fourth switch,

wherein the first switch and the second switch are configured to be in a conduction state in an arithmetic processing period,
wherein the first switch and the third switch are configured to be in a conduction state in a data storage period and a data
restorage period, and

wherein the first switch and the forth switch are configured to be in a conduction state in a charge period.

US Pat. No. 9,099,678

LIGHT EMITTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a transistor over a first substrate;
a first insulating film over the transistor;
a light-emitting element over the first substrate, the light-emitting element comprising a light-emitting layer provided between
a first electrode and a second electrode;

a second substrate over the transistor and the light-emitting element;
a sealing material provided between the first substrate and the second substrate; and
a gas partitioning layer provided between the first substrate and the second substrate, the gas partitioning er being along
the sealing material, an edge portion of the first substrate, and an edge portion of the second substrate,

wherein the light-emitting layer comprises a phosphorescent compound,
wherein an amount of hydrogen contained in the first insulating film is equal to or less than 1 atomic %, and
wherein the gas partitioning layer comprises silicon nitride.

US Pat. No. 9,355,602

LIQUID CRYSTAL DISPLAY DEVICE AND DRIVING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:
a display element; and
a backlight,
wherein the display element has a first period for analyzing gray scales of an image from a histogram of the image to obtain
a data of the image, and a second period for displaying the image,

wherein a transmittance of the display element is higher in the second period than in the first period,
wherein a luminance of the backlight is lower in the second period than in the first period,
wherein in the second period, a product of the transmittance of the display element and the luminance of the backlight is
saturated in a gray scale region at high gray scale side, and

wherein the gray scale region is determined so that a number of the data of the image included in the gray scale region is
equal to or less than 1/10 of a total number of the data of the image.

US Pat. No. 9,310,866

SEMICONDUCTOR DEVICE AND ALARM DEVICE

Semiconductor Energy Labo...

1. A device comprising:
a power gate controller electrically connected to a power supply line;
a power gate electrically connected to the power supply line and the power gate controller;
a CPU electrically connected to the power gate; and
a sensor portion electrically connected to the power gate and the CPU,
wherein the power gate controller comprises a timer and is configured to control the power gate with use of the timer,
wherein the power gate is configured to allow or stop supply of power from the power supply line to the CPU and the sensor
portion, in accordance with control by the power gate controller;

wherein the sensor portion is configured to transmit a measurement value obtained by measuring a physical quantity to the
CPU,

wherein the CPU is configured to perform an arithmetic processing on the measurement value and transmit a signal based on
an arithmetic result,

wherein the CPU comprises a first memory portion and a second memory portion electrically connected to the first memory portion,
wherein the first memory portion comprises a first transistor which comprises a first semiconductor,
wherein the second memory portion comprises a second transistor which comprises a second semiconductor, the second semiconductor
having a different band gap width from that of the first semiconductor, and

wherein the CPU is configured to store data of the first memory portion in the second memory portion before the power gate
stops the supply of power, and restore the data of the second memory portion to the first memory portion when the power gate
allows to resume the supply of power.

US Pat. No. 9,622,345

DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:
a substrate;
a semiconductor layer over the substrate;
a gate insulating layer over the semiconductor layer;
a gate electrode over the gate insulating layer;
a first insulating layer over the gate electrode; and
a second insulating layer comprising organic material over the first insulating layer,
wherein the gate electrode comprises a first layer comprising titanium and a second layer comprising copper,
wherein the second layer is over the first layer,
wherein the second insulating layer comprises a rounded portion in a vertical cross-sectional view of the second insulting
layer, and

wherein the second layer is narrower than the first layer.

US Pat. No. 9,356,048

LIGHT EMITTING DEVICE

Semiconductor Energy Labo...

1. A light emitting device comprising:
a first plastic substrate;
a sealant over the first plastic substrate;
a first transistor over the first plastic substrate;
a second transistor over the first plastic substrate;
a third transistor over the first plastic substrate;
a capacitor over the first plastic substrate;
a light emitting element over the first plastic substrate, the light emitting element including a first electrode, a light
emitting layer over the first electrode, and a second electrode over the light emitting layer; and

a conductive film over the first plastic substrate and in contact with the sealant;
a first insulating film over an edge portion of the first electrode of the light emitting element, and wherein the light emitting
layer of the light emitting element is positioned over the first insulating film;

a second insulating film over the first plastic substrate;
an organic resin over the second electrode, the organic resin being between the first plastic substrate and a second plastic
substrate,

wherein a gate of the first transistor is electrically connected to one terminal of the capacitor,
wherein the gate of the first transistor is electrically connected to one of a source and a drain of the third transistor,
wherein the first transistor and the second transistor are connected between a power supply line and the light emitting element,
wherein a gate of the second transistor is electrically connected to a signal line,
wherein the conductive film is not in contact with the first insulating film, and
wherein the conductive film is not in contact with the second insulating film.

US Pat. No. 9,219,160

SEMICONDUCTOR DEVICE

SEMICONDUCTOR ENERGY LABO...

10. A semiconductor device comprising:
a first insulating layer;
an oxide semiconductor layer over and in contact with the first insulating layer;
a source electrode and a drain electrode electrically connected to the oxide semiconductor layer;
a gate electrode adjacent to the oxide semiconductor layer; and
a second insulating layer over and in contact with the oxide semiconductor layer,
wherein the first insulating layer includes silicon,
wherein the oxide semiconductor layer includes a first region,
wherein a concentration of silicon in the first region is lower than or equal to 1.0 at. %,
wherein the second insulating layer includes silicon,
wherein the oxide semiconductor layer includes a second region,
wherein the concentration of silicon in the first region is lower than a concentration of silicon in the second region,
wherein the oxide semiconductor layer includes a third region between the first region and the second region, and
wherein a concentration of silicon in the third region is lower than the concentration of silicon in the first region.

US Pat. No. 9,202,814

MEMORY DEVICE AND SIGNAL PROCESSING CIRCUIT

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first inverter, a second inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a first
capacitor and a second capacitor;

wherein an input terminal of the first inverter is electrically connected to an output terminal of the second inverter and
a second node, and

wherein an input terminal of the second inverter is electrically connected to an output terminal of the first inverter and
a first node,

wherein one of a source and a drain of the first transistor is electrically connected to the output terminal of the first
inverter,

wherein one of a source and a drain of the second transistor is electrically connected to the output terminal of the second
inverter,

wherein one of a source and a drain of the third transistor is electrically connected to the output terminal of the first
inverter,

wherein one of a source and a drain of the fourth transistor is electrically connected to the output terminal of the second
inverter,

wherein the other of the source and the drain of the first transistor and a first electrode of the first capacitor are electrically
connected to a third node,

wherein the other of the source and the drain of the second transistor and a first electrode of the second capacitor are electrically
connected to a fourth node, and

wherein each of the first transistor and the second transistor comprises an oxide semiconductor.

US Pat. No. 9,083,327

SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
an arithmetic portion including a first node and a second node;
a third node;
a fourth node;
a first transistor including a channel in an oxide semiconductor layer;
a second transistor including a channel in an oxide semiconductor layer; and
a comparator comprising a third transistor including a channel in a silicon wafer or a silicon film,
wherein one of a source and a drain of the first transistor is electrically connected to the first node,
wherein the other of the source and the drain of the first transistor is electrically connected to the third node,
wherein one of a source and a drain of the second transistor is electrically connected to the second node,
wherein the other of the source and the drain of the second transistor is electrically connected to the fourth node,
wherein a non-inverting input terminal of the comparator is electrically connected to the third node,
wherein an inverting input terminal of the comparator is electrically connected to the fourth node,
wherein an output terminal of the comparator is electrically connected to the arithmetic portion,
wherein an insulating film is over the third transistor, and
wherein the first transistor and the second transistor are over the insulating film.

US Pat. No. 9,231,154

LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a plurality of light-emitting elements each including:
a reflective electrode;
a transparent electrode over the reflective electrode;
a plurality of light-emitting layers over the transparent electrode, the plurality of light-emitting layers emitting lights
of different colors from one another; and

a semi-transmissive and semi-reflective electrode over the plurality of light-emitting layers,
wherein a surface roughness of the transparent electrode in one of the plurality of light-emitting elements is greater than
surface roughnesses of the transparent electrodes in the others of the plurality of light-emitting elements,

wherein the one of the plurality of light-emitting elements is configured so that the light emitted from one of the plurality
of light-emitting layers, which is the closest to the reflective electrode among the plurality of light-emitting layers, is
optically amplified,

wherein the transparent electrode in the one of the plurality of light-emitting elements includes a polycrystalline conductive
oxide, and

wherein the transparent electrodes in the others of the plurality of light-emitting elements include an amorphous conductive
oxide.

US Pat. No. 9,207,798

TOUCH PANEL

Semiconductor Energy Labo...

1. A touch panel comprising:
a transistor over a first substrate, the transistor comprising a gate electrode, a semiconductor layer, a source electrode
and a drain electrode;

an insulating layer covering the transistor, the insulating layer having an opening,
a filler layer filling the opening;
a light-emitting element comprising a first electrode over the insulating layer, a light-emitting layer over the first electrode
and a second electrode over the light-emitting layer;

a first capacitor comprising a first lower electrode, an upper electrode and the filler layer between the first lower electrode
and the upper electrode;

a second capacitor comprising a second lower electrode, the upper electrode and the filler layer between the first lower electrode
and the upper electrode; and

a spacer between a second substrate and the first substrate, the spacer overlapping with the filler layer and the upper electrode,
wherein the first lower electrode and the second lower electrode are formed using the same material as the gate electrode,
and

wherein the upper electrode is over the insulating layer and formed using the same material as the first electrode.

US Pat. No. 9,059,689

SEMICONDUCTOR DEVICE INCLUDING FLIP-FLOP AND LOGIC CIRCUIT

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first transistor;
a circuit including a second transistor;
a flip-flop; and
a logic circuit,
wherein a channel of the first transistor is included in an oxide semiconductor layer,
wherein an output of the logic circuit is input to a gate of the first transistor,
wherein a first signal is input to one of a source and a drain of the first transistor,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein a first clock signal is input to the circuit,
wherein a second clock signal is output from the circuit to the flip-flop,
wherein a second signal and an output signal of the flip-flop are input to the logic circuit, and
wherein a timing of the second clock signal is different from a timing of the first clock signal.

US Pat. No. 9,159,841

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

29. A method for manufacturing a semiconductor device comprising:
forming a gate insulating film over a gate electrode;
forming a semiconductor film over the gate insulating film;
performing a plasma treatment to form an insulating region on a side surface and part of a top surface of the semiconductor
film;

forming a conductive film over the semiconductor film and the insulating region;
forming an etching protective film comprising an aluminum oxide over the conductive film;
forming a mask over the etching protective film;
performing a first etching treatment on the etching protective film, the conductive film, and the semiconductor film, thereby
exposing a first portion of the semiconductor film and forming a source electrode and a drain electrode from the conductive
film;

removing the mask;
after removing the mask, performing a second etching treatment on the first portion of the semiconductor film, thereby exposing
a second portion of the semiconductor film comprising a channel region;

forming an insulating film over the second portion of the semiconductor film and the etching protective film; and
forming a back gate electrode over the insulating film,
wherein fluorine or a fluoride is used as an etching gas in the second etching treatment.

US Pat. No. 9,310,641

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a first light-transmitting substrate;
a second light-transmitting substrate;
a display element sandwiched between the first light-transmitting substrate and the second light-transmitting substrate;
a first polarizing plate having a first transmission axis and a second polarizing plate having a second transmission axis;
a third polarizing plate having a third transmission axis; and
a backlight unit comprising a first diode and a lamp reflector,
wherein the lamp reflector is provided in the backlight unit at an opposite side of the display element,
wherein the first polarizing plate and the second polarizing plate are stacked outside the first light-transmitting substrate,
wherein the third polarizing plate is outside the second light-transmitting substrate,
wherein the backlight unit is provided outside the third polarizing plate,
wherein the first transmission axis is displaced so as to be parallel to a minor-axis direction of an ellipse of elliptically-polarized
light passing through the display element, and

wherein the first transmission axis and the second transmission axis are in a parallel nicol state.

US Pat. No. 9,153,604

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a semiconductor film;
a gate insulating film adjacent to the semiconductor film; and
a gate electrode adjacent to the semiconductor film with the gate insulating film interposed therebetween;
a first insulating film over the gate electrode, the gate insulating film and the semiconductor film, the first insulating
film comprising silicon, nitrogen and hydrogen;

a first conductive layer over the first insulating film, the first conductive layer being electrically connected to one of
a source region and a drain region of the semiconductor film;

a second insulating film comprising a resin over the first conductive layer;
a second conductive layer over the second insulating film, the second conductive layer having a light blocking ability;
a third insulating film over the second conductive layer, the third insulating film comprising silicon and nitrogen; and
a pixel electrode over the third insulating film,
wherein the pixel electrode is electrically connected to the one of the source region and the drain region through at least
the first conductive layer.

US Pat. No. 9,059,216

SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A display device comprising:
a substrate;
a source wiring line and a gate electrode formed over the substrate;
a first insulating film having a first contact hole formed over the source wiring line and the gate electrode;
a first amorphous semiconductor film containing a channel forming region formed over the first insulating film;
second and third amorphous semiconductor films containing an impurity element formed over the first amorphous semiconductor
film;

a metal wiring line formed over the second amorphous semiconductor film wherein the metal wiring line electrically connects
the second amorphous semiconductor film to the source wiring line through the first contact hole of the first insulating film;

a second insulating film having a second contact hole formed over the source wiring line and the second and third amorphous
semiconductor films; and

a pixel electrode formed over the second insulating film and electrically connected to the third amorphous semiconductor film
through the second contact hole of the second insulating film.

US Pat. No. 9,048,105

SEMICONDUCTOR INTEGRATED CIRCUIT

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a comparator comprising a first terminal and a second terminal;
a first memory portion comprising:
a first transistor comprising a semiconductor layer including an oxide semiconductor; and
a second transistor comprising a gate electrically connected to one of a source and a drain of the first transistor;
a second memory portion comprising:
a third transistor comprising a semiconductor layer including an oxide semiconductor; and
a fourth transistor comprising a gate electrically connected to one of a source and a drain of the third transistor; and
a circuit comprising a terminal electrically connected to one of a source and a drain of the second transistor and one of
a source and a drain of the fourth transistor,

wherein:
the first terminal is electrically connected to the other of the source and the drain of the second transistor; and
the second terminal is electrically connected to the other of the source and the drain of the fourth transistor.

US Pat. No. 9,431,430

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A method for manufacturing a semiconductor device including a transistor and a capacitor, comprising the steps of:
forming an oxide semiconductor film over an insulating surface;
forming a lower electrode film of the capacitor through a same step as forming a first electrode film covering an end portion
of the oxide semiconductor film;

forming an insulating film of the capacitor over the lower electrode film through a same step as forming a gate insulating
film over the oxide semiconductor film;

forming an upper electrode film of the capacitor over the insulating film through a same step as forming a gate electrode
over the gate insulating film;

forming a second insulating film covering at least a side surface of the gate electrode, and
forming a second electrode film electrically connected to the first electrode film and the oxide semiconductor film,
wherein a portion of the second electrode film is in direct contact with a top surface of the oxide semiconductor film.

US Pat. No. 9,396,676

SEMICONDUCTOR DEVICE, DISPLAY DEVICE AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a pixel;
a driving circuit; and
an input terminal,
wherein an output terminal of the driving circuit is directly connected to the pixel,
wherein the driving circuit comprises:
a first transistor comprising a first gate electrode, a first source electrode and a first drain electrode,
a second transistor comprising a second gate electrode, a second source electrode and a second drain electrode,
a third transistor comprising a third gate electrode, a third source electrode and a third drain electrode,
a fourth transistor comprising a fourth gate electrode, a fourth source electrode and a fourth drain electrode,
a fifth transistor comprising a fifth gate electrode, a fifth source electrode and a fifth drain electrode,
a sixth transistor comprising a sixth gate electrode, a sixth source electrode and a sixth drain electrode, and
a capacitor,
wherein one of the first source electrode and the first drain electrode of the first transistor is directly connected to the
capacitor and the output terminal,

wherein one of the second source electrode and the second drain electrode of the second transistor is directly connected to
the capacitor, the output terminal and the one of the first source electrode and the first drain electrode of the first transistor,

wherein one of the third source electrode and the third drain electrode of the third transistor is directly connected to the
capacitor and the first gate electrode of the first transistor, the other of the third source electrode and the third drain
electrode of the third transistor is directly connected to a terminal, and the third gate electrode of the third transistor
is directly connected to the second gate electrode of the second transistor,

wherein one of the fourth source electrode and the fourth drain electrode of the fourth transistor is directly connected to
the capacitor and the first gate electrode of the first transistor,

wherein the fifth gate electrode of the fifth transistor is directly connected to the one of the first source electrode and
the first drain electrode of the first transistor, the output terminal and the capacitor, and

wherein one of the sixth source electrode and the sixth drain electrode of the sixth transistor is directly connected to the
other of the second source electrode and the second drain electrode of the second transistor.

US Pat. No. 9,343,018

METHOD FOR DRIVING A LIQUID CRYSTAL DISPLAY DEVICE AT HIGHER RESOLUTION

Semiconductor Energy Labo...

1. A method for driving a liquid crystal display device, comprising:
performing a frame interpolation processing which uses a first part of a first data and creates a second data;
performing a first super-resolution processing which uses the second data and creates a third data;
performing a second super-resolution processing which uses a second part of the first data and creates a fourth data;
performing a first local dimming processing which uses a third part of the first data and creates a fifth data; and
performing a second local dimming processing which uses the third data and the fourth data and creates a sixth data.

US Pat. No. 9,299,855

SEMICONDUCTOR DEVICE HAVING DUAL GATE INSULATING LAYERS

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a semiconductor layer;
a gate electrode overlapping with the semiconductor layer;
a first gate insulating layer between the semiconductor layer and the gate electrode; and
a second gate insulating layer between the first gate insulating layer and the gate electrode,
wherein the semiconductor layer includes an oxide semiconductor,
wherein the first gate insulating layer includes an oxide whose nitrogen content is lower than or equal to 5 at. %, and
wherein the second gate insulating layer includes a charge trap state.

US Pat. No. 9,293,193

MEMORY CIRCUIT AND MEMORY DEVICE

Semiconductor Energy Labo...

1. A memory circuit comprising:
a latch unit;
a first switch unit between a first signal line and the latch unit;
a second switch unit between a second signal line and the latch unit; and
a third switch unit between the latch unit and a power supply line,
wherein the latch unit comprises a first inverter and a second inverter, an input terminal of the first inverter is electrically
connected to an output terminal of the second inverter, and an input terminal of the second inverter is electrically connected
to an output terminal of the first inverter,

wherein the first inverter comprises a field-effect transistor, and
wherein each of a gate of the field-effect transistor, the first switch unit, the second switch unit, and the third switch
unit is supplied with a control signal.

US Pat. No. 9,293,545

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a glass substrate;
a gate electrode over the glass substrate;
a gate insulating film over the gate electrode;
a first metal film and a second metal film over the gate insulating film; and
an oxide semiconductor film in contact with the first metal film and the second metal film,
wherein a side surface of the first metal film faces a side surface of the second metal film, and
wherein each of the side surface of the first metal film and the side surface of the second metal film has a step in a lower
end portion thereof.

US Pat. No. 9,257,071

SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first switch;
a second switch;
a third switch;
a fourth switch;
a fifth switch;
a sixth switch;
a first capacitor;
a second capacitor;
a transistor; and
a load,
wherein one terminal of the first switch is electrically connected to a first wiring,
wherein the other terminal of the first switch is directly connected to one terminal of the second switch, one terminal of
the second capacitor, and a gate of the transistor,

wherein the other terminal of the second switch is directly connected to one terminal of the third switch and one terminal
of the first capacitor,

wherein the other terminal of the third switch is directly connected to the other terminal of the second capacitor and one
terminal of the fourth switch,

wherein the other terminal of the fourth switch is directly connected to one of a source and a drain of the transistor and
one terminal of the fifth switch,

wherein the other terminal of the fifth switch is directly connected to the other terminal of the first capacitor and one
terminal of the sixth switch,

wherein the other terminal of the sixth switch is electrically connected to a fourth wiring,
wherein a first terminal of the load is electrically connected to the one terminal or the other terminal of the fifth switch,
wherein a second terminal of the load is electrically connected to a third wiring, and
wherein the other of the source and the drain of the transistor is electrically connected to a second wiring.

US Pat. No. 9,245,891

DISPLAY DEVICE INCLUDING AT LEAST SIX TRANSISTORS

Semiconductor Energy Labo...

1. A semiconductor device comprising: a first transistor; a second transistor; a third transistor; a fourth transistor; a
fifth transistor; and a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a first wiring,
wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring,
wherein one of a source and a drain of the second transistor is electrically connected to a third wiring,
wherein the other of the source and the drain of the second transistor is electrically connected to the second wiring,
wherein one of a source and a drain of the third transistor is electrically connected to a fourth wiring,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the sixth transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the sixth
transistor,

wherein one of a source and a drain of the fifth transistor is electrically connected to a gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a fifth wiring,
wherein one of a source and a drain of the sixth transistor is electrically connected to the third wiring,
wherein the other of the source and the drain of the sixth transistor is electrically connected to the gate of the first transistor,
wherein the gate of the sixth transistor is electrically connected to a sixth wiring, and
wherein a ratio W/L of a channel width W to a channel length L of the fourth transistor is higher than a ratio W/L of the
third transistor.

US Pat. No. 9,184,221

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

18. A method for manufacturing a semiconductor device, the method comprising the steps of:
forming a molybdenum film over a substrate;
forming a molybdenum oxide film over the molybdenum film;
forming a nonmetal inorganic film over the molybdenum oxide film;
forming an organic compound film over the nonmetal inorganic film;
forming a transistor over the organic compound film;
forming an interlayer insulating film over the transistor;
forming a first electrode over the interlayer insulating film;
forming a light-emitting layer over the first electrode;
forming a second electrode over the light-emitting layer;
forming a protective film over the second electrode; and
separating a stacked-body comprising the organic compound film, the transistor, the interlayer insulating film, the first
electrode, the light-emitting layer, the second electrode, and the protective film from the substrate,

wherein the transistor comprises a semiconductor layer, and
wherein the semiconductor layer comprises indium, zinc, and oxygen.

US Pat. No. 9,443,987

SEMICONDUCTOR DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A semiconductor device comprising:
a gate insulating film;
an oxide semiconductor film; and
a protective film,
wherein the oxide semiconductor film is provided between the gate insulating film and the protective film,
wherein at least one of the gate insulating film and the protective film has a spin density obtained by an electron spin resonance
spectrum, and

wherein the spin density is higher than or equal to 1×1017 spins/cm3 and lower than 1×1018 spins/cm3.

US Pat. No. 9,426,848

LIGHTING DEVICE

Semiconductor Energy Labo...

1. A lighting device comprising:
a surface light source portion comprising:
a light-emitting element comprising;
a first electrode;
a light-emitting layer over the first electrode; and
a second electrode over the light-emitting layer;
an insulating film over the light-emitting element;
a first wiring over the insulating film; and
a second wiring over the insulating film; and
a control circuit portion in a base portion,
wherein the control circuit portion comprises a variable current source circuit configured to supply a current to the light-emitting
element,

wherein the light-emitting layer comprises an organic compound,
wherein the first wiring is electrically connected to the first electrode, and
wherein the second wiring is electrically connected to the second electrode.

US Pat. No. 9,350,358

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first logic element;
a first switch electrically connected to the first logic element; and
a second logic element electrically connected to the first switch,
wherein the first logic element comprises a second switch,
wherein the second switch is configured to set an output potential of the first logic element to a L level,
wherein the first switch comprises a first transistor, a second transistor, a third transistor, and a capacitor,
wherein a gate of the second transistor is electrically connected to one of a source and a drain of the first transistor,
wherein the gate of the second transistor is electrically connected to a first electrode of the capacitor,
wherein a gate of the first transistor is electrically connected to a first signal line,
wherein a gate of the third transistor is electrically connected to a second signal line, and
wherein the second signal line is configured to supply a signal for selecting one of contexts.

US Pat. No. 9,318,506

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a glass substrate from which a gas with a mass-to-charge ratio of 32 is detected by thermal desorption spectroscopy;
an oxide semiconductor film over and in direct contact with the glass substrate, the oxide semiconductor film comprising a
first region and a second region;

a gate insulating film over the oxide semiconductor film; and
a gate electrode overlapping with the oxide semiconductor film with the gate insulating film interposed therebetween,
wherein an amount of the gas detected by the thermal desorption spectroscopy on an oxygen atom basis is greater than or equal
to 3.0×1014 atoms/cm2, and

wherein a resistance of the first region is lower than a resistance of the second region.

US Pat. No. 9,318,197

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first wiring;
a transistor, a gate terminal of which is electrically connected to the first wiring;
a first capacitor, a first terminal of which is configured to be negatively charged;
a second capacitor electrically connected to one of a source terminal and a drain terminal of the transistor;
a second wiring electrically connected to the other of the source terminal and the drain terminal of the transistor;
a first driver circuit configured to control a potential of a second terminal of the first capacitor: and
a second driver circuit configured to control a potential of the second wiring,
wherein a channel formation region of the transistor comprises an oxide semiconductor, and
wherein the first terminal of the first capacitor is electrically connected to the gate terminal of the transistor.

US Pat. No. 9,311,876

DRIVER CIRCUIT, DISPLAY DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A gate driver circuit comprising:
a flip-flop circuit, the flip-flop circuit comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor;
a sixth transistor;
a seventh transistor;
an eighth transistor; and
a capacitor,
wherein each of the first to eighth transistors comprises a gate terminal, a source terminal, and a drain terminal,
wherein one of the source terminal and the drain terminal of the first transistor is electrically connected to one of the
source terminal and the drain terminal of the second transistor, one of the source terminal and the drain terminal of the
third transistor, one of the source terminal and the drain terminal of the fourth transistor, and the gate terminal of the
fifth transistor,

wherein the gate terminal of the third transistor is electrically connected to the gate terminal of the sixth transistor,
wherein one of the source terminal and the drain terminal of the fifth transistor is electrically connected to one of the
source terminal and the drain terminal of the sixth transistor and one of the source terminal and the drain terminal of the
seventh transistor,

wherein the gate terminal of the eighth transistor is electrically connected to the other one of the source terminal and the
drain terminal of the first transistor and the gate terminal of the first transistor,

wherein one of the source terminal and the drain terminal of the eighth transistor is electrically connected to the gate terminal
of the fourth transistor,

wherein the capacitor is provided between the gate terminal of the fifth transistor and the one of the source terminal and
the drain terminal of the fifth transistor,

wherein at least one of the first to eighth transistors comprises a channel formation region comprising an oxide semiconductor,
and

wherein the other one of the source terminal and the drain terminal of the eighth transistor is electrically connected to
the other one of the source terminal and the drain terminal of the second transistor, the other one of the source terminal
and the drain terminal of the third transistor, and the other one of the source terminal and the drain terminal of the fourth
transistor.

US Pat. No. 9,309,458

PHOSPHORESCENT ORGANOMETALLIC IRIDIUM COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

SEMICONDUCTOR ENERGY LABO...

1. A complex comprising a structure represented by Formula (G1),

wherein:
R1 represents an alkyl group having 1 to 6 carbon atoms; and

R2 to R10 independently represent hydrogen or an alkyl group having 1 to 6 carbon atoms.

US Pat. No. 9,123,573

OXIDE SEMICONDUCTOR STACKED FILM AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first gate electrode layer;
a first insulating film over the first gate electrode layer;
an oxide semiconductor stacked film over the first insulating film; and
a pair of electrode layers in contact with the oxide semiconductor stacked film,
wherein the oxide semiconductor stacked film comprises:
a first oxide semiconductor layer;
a second oxide semiconductor layer over the first oxide semiconductor layer; and
a third oxide semiconductor layer over the second oxide semiconductor layer,
wherein each of the first oxide semiconductor layer, the second oxide semiconductor layer, and the third oxide semiconductor
layer comprises indium,

wherein a content percentage of indium in the second oxide semiconductor layer is higher than a content percentage of indium
in the first oxide semiconductor layer and a content percentage of indium in the third oxide semiconductor layer,

wherein an absorption coefficient of a channel formation region in the oxide semiconductor stacked film, which is measured
by the CPM, is lower than or equal to 3×10?3/cm in an energy range of 1.5 eV to 2.3 eV, and

wherein a conduction band of each of the first oxide semiconductor layer and the third oxide semiconductor layer is higher
than a conduction band of the second oxide semiconductor layer.

US Pat. No. 9,629,205

TEMPERATURE CONTROL DEVICE

Semiconductor Energy Labo...

1. A temperature control device comprising:
a temperature sensor configured to detect a temperature of an object heated by a radio wave;
a signal processing circuit configured to compare the temperature of the object with a standard temperature;
an antenna configured to generate electric energy by reception of the radio wave;
a rechargeable battery charged by the electric energy;
a charging circuit configured to control charging of the rechargeable battery;
a heater configured to heat the object in accordance with a comparison result by the signal processing circuit;
a first protective material covering the signal processing circuit, the rechargeable battery, and the charging circuit; and
a second protective material covering the first protective material, the temperature sensor, the heater, and the antenna,
wherein the second protective material transmits the radio wave more than the first protective material,
wherein the temperature sensor is configured to detect a temperature of the heater, and
wherein the heater is controlled by the signal processing circuit in accordance with the temperature of the heater.

US Pat. No. 9,293,427

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a coil;
a capacitor electrically connected to the coil in parallel;
a passive element that forms a resonance circuit with the coil and the capacitor by being electrically connected to the coil
and the capacitor in parallel;

a first transistor capable of controlling whether the passive element is electrically connected to the coil and the capacitor
in parallel or not; and

a memory circuit,
wherein the memory circuit includes:
a second transistor that comprises a semiconductor layer including a channel, the channel including an oxide semiconductor;
a second capacitor; and
a third transistor in which a voltage of one of a source and a drain of the third transistor is changed in accordance with
an electric wave received by the coil, the other one of the source and the drain of the third transistor is electrically connected
to a gate of the first transistor, and a gate of the third transistor is directly connected to one of a source and a drain
of the second transistor and one of electrodes of the second capacitor.

US Pat. No. 9,293,186

MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A memory device comprising:
a first transistor, a second transistor, a storage capacitor, a selection circuit, a memory circuit, and an inverter circuit,
wherein one of a source and a drain of the first transistor is electrically connected to one of terminals of the storage capacitor
and one of a source and a drain of the second transistor,

wherein the other of the source and the drain of the first transistor is electrically connected to an output terminal of the
memory circuit through the inverter circuit,

wherein the other of the source and the drain of the second transistor is electrically connected to a first input terminal
of the selection circuit,

wherein an output terminal of the selection circuit is electrically connected to an input terminal of the memory circuit,
wherein the memory circuit is electrically connected between the selection circuit and the inverter circuit,
wherein the first transistor includes an oxide semiconductor layer that includes a channel formation region, and
wherein the second transistor includes an oxide semiconductor layer that includes a channel formation region.

US Pat. No. 9,280,937

METHOD FOR DRIVING LIQUID CRYSTAL DISPLAY DEVICE

Semiconductor Energy Labo...

1. An electronic device, comprising:
a backlight comprising a first light source, a second light source, a first light guide plate, a second light guide plate
and a light diffusing plate;

a light modulation device; and
a circuit,
wherein the first light source is placed along with a first surface of the first light guide plate;
wherein the second light source is placed along with a first surface of the second light guide plate;
wherein a second surface of the first light guide plate is placed so as to face a first surface of the light diffusing plate;
wherein a second surface of the second light guide plate is placed so as to face the first surface of the light diffusing
plate;

wherein a surface of the light modulation device is placed so as to face a second surface of the light diffusing plate,
wherein each light intensity of a first area where the light modulation device is overlapped with the second surface of the
first light guide plate and a second area where the light modulation device is overlapped with the second surface of the second
light guide plate is independently controllable,

wherein the circuit is configured to form signals for a local dimming processing and to provide the signals to the backlight
and the light modulation device, and

wherein the backlight and the light modulation device is configured to perform the local dimming processing by using the signals.

US Pat. No. 9,153,650

OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. An oxide semiconductor comprising:
an aggregation of a plurality of InGaZnO4 crystals,

wherein each of the plurality of InGaZnO4 crystals has a size larger than or equal to 1 nm and smaller than or equal to 3 nm, and

wherein the plurality of InGaZnO4 crystals have no orientation.

US Pat. No. 9,112,170

LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, AND ELECTRONIC DEVICE

Semiconductor Energy Labo...

1. A light-emitting element comprising:
a first light-emitting layer and a second light-emitting layer being in contact with each other between a first electrode
and a second electrode, and

a hole transporting layer between the first electrode and the first light-emitting layer, and
an electron transporting layer between the second electrode and the second light-emitting layer,
wherein the first light-emitting layer comprises a compound represented by Formula (401) and a phosphorescent compound, and
the second light-emitting layer comprises an electron transporting host material and the phosphorescent compound


wherein a material of the hole transporting layer has triplet excitation energy lower than that of the phosphorescent compound,
and

wherein at least one of the first light-emitting layer and the second light-emitting layer emits green light or yellowish
green light.

US Pat. No. 9,105,511

SEMICONDUCTOR DEVICE COMPRISING OXIDE SEMICONDUCTOR

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a first wiring, a second wiring, a third wiring, a fourth wiring, a fifth wiring, and a plurality of storage elements connected
in parallel between the first wiring and the second wiring,

wherein one of the plurality of storage elements includes a first transistor having a first gate electrode, a first source
electrode, and a first drain electrode; a second transistor having a second gate electrode, a second source electrode, and
a second drain electrode; and a capacitor,

wherein the first transistor is provided in a substrate including a semiconductor material,
wherein the second transistor includes an oxide semiconductor layer,
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes
of the capacitor are electrically connected to each other,

wherein the first wiring and the first source electrode are electrically connected to each other,
wherein the second wiring and the first drain electrode are electrically connected to each other,
wherein the third wiring and the other of the second source electrode and the second drain electrode are electrically connected
to each other,

wherein the fourth wiring and the second gate electrode are electrically connected to each other, and
wherein the fifth wiring and the other of the electrodes of the capacitor are electrically connected to each other.

US Pat. No. 9,082,864

SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a gate electrode;
a gate insulating film;
a pair of electrodes; and
an n-type oxide semiconductor film overlapping with the gate electrode with the gate insulating film interposed therebetween
and in electrical contact with the pair of electrodes,

wherein the n-type oxide semiconductor film contains an n-type oxide semiconductor material and a p-type oxide semiconductor
material,

wherein the n-type oxide semiconductor film comprises a channel formation region of a transistor, the channel formation region
overlapping with the gate electrode, and

wherein a ratio of a concentration of atoms other than oxygen forming the p-type oxide semiconductor material over the sum
of the concentration of atoms other than oxygen forming the p-type oxide semiconductor material and a concentration of atoms
other than oxygen forming the n-type semiconductor material is comprised between 0.027 and 0.305.

US Pat. No. 9,299,393

MEMORY DEVICE AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A memory device comprising:
a first cell array comprising first memory cells;
a second cell array comprising second memory cells;
first word lines electrically connected to only the first cell array between the first cell array and the second cell array;
second word lines electrically connected to only the second cell array between the first cell array and the second cell array;
a word line driver circuit electrically connected to the first word lines and to the second word lines;
first bit lines electrically connected to only the first cell array between the first cell array and the second cell array;
second bit lines electrically connected to only the second cell array between the first cell array and the second cell array;
a first bit line driver circuit electrically connected to the first bit lines, the first bit line driver circuit comprising
a first bit line reading circuit; and

a second bit line driver circuit electrically connected to the second bit lines, the second bit line driver circuit comprising
a second bit line reading circuit,

wherein the first cell array and the second cell array overlap with the first bit line reading circuit and the second bit
line reading circuit, respectively, and

wherein any one of the first bit line reading circuit, and the second bit line reading circuit includes a transistor comprising
a channel formation region in polycrystalline silicon, single crystal silicon, polycrystalline germanium, or single crystal
germanium.

US Pat. No. 9,961,726

LIGHT-EMITTING DEVICE AND CAMERA

Semiconductor Energy Labo...

1. A semiconductor device comprising:a light-emitting portion including a light-emitting element; and
a camera comprising a lens,
wherein the light-emitting portion and the lens are provided over the same side of the semiconductor device,
wherein a constant current having a half width of more than or equal to 1 millisecond and less than or equal to 1000 milliseconds is configured to be supplied to the light-emitting portion, and
wherein a current density of the light-emitting element is configured to be greater than or equal to 10 mA/cm2 and less than or equal to 1000 mA/cm2.

US Pat. No. 9,263,404

MANAGING METHOD OF BUILDING MATERIAL AND WIRELESS CHIP APPLIED TO THE METHOD

Semiconductor Energy Labo...

1. A wireless chip comprising:
an adhesive layer having a first portion and a second portion over a material, wherein a bottom surface of the first portion
and a bottom surface of the second portion are in contact with the material;

a barrier layer over the adhesive layer, the barrier layer is in contact with a top surface of the first portion and a top
surface of the second portion;

a sheet including a plurality of wireless chips attached to the material via the adhesive layer and the barrier layer, each
of the plurality of wireless chips comprising an integrated circuit portion; and

an antenna configured to supply power to the integrated circuit portion,
wherein the first portion and a first wireless chip of the plurality of wireless chips overlap each other,
wherein the second portion and a region between the first wireless chip and a second wireless chip of the plurality of wireless
chips adjacent to the first wireless chip overlap each other, and

wherein adhesive intensity of the first portion is higher than adhesive intensity of the second portion.

US Pat. No. 9,257,489

ELECTRONIC APPLIANCE AND LIGHT-EMITTING DEVICE

Semiconductor Energy Labo...

1. A light-emitting device comprising:
a first substrate;
a first partition wall over the first substrate;
a second partition wall over the first partition wall;
a plurality of light-emitting elements over the first substrate, the plurality of light-emitting elements being partitioned
by the first partition wall; and

a second substrate over the first substrate,
wherein a width of a top surface of the first partition wall is larger than a width of a bottom surface of the second partition
wall,

wherein a width of a bottom surface of the first partition wall is larger than a width of a top surface of the second partition
wall, and

wherein the plurality of light-emitting elements comprises:
a first element emitting red light;
a second element emitting green light;
a third element emitting blue light; and
a fourth element emitting white light.

US Pat. No. 9,188,631

ELEMENT SUBSTRATE, INSPECTING METHOD, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

5. A wireless communication method of a semiconductor device comprising:
applying an electromagnetic wave to the semiconductor device comprising an antenna coil and a semiconductor element which
are electrically connected in series; and

evaluating characteristics of the semiconductor element by measuring power absorbed by the semiconductor device.

US Pat. No. 9,316,857

DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising:
a first substrate;
a display element over the first substrate;
a color filter layer over the display element;
a planarization layer over the color filter layer;
a stress relief layer over the planarization layer;
a sensor layer over the stress relief layer, the sensor layer including a first electrode, a second electrode, a third electrode,
an insulating layer, and a wiring; and

a second substrate over the sensor layer,
wherein the planarization layer comprises a same material of the insulating layer, and
wherein a product of a specific gravity and a dielectric constant of the stress relief layer is smaller than that of the second
substrate.

US Pat. No. 9,281,134

POWER STORAGE DEVICE AND METHOD FOR MANUFACTURING THE SAME

Semiconductor Energy Labo...

1. A power storage device comprising:
a current collector;
a mixed layer comprising silicon and a metal element that forms a silicide by reacting with silicon, over the current collector;
and

a silicon layer over the mixed layer;
wherein the silicon layer comprises:
a first silicon region; and
a whisker-shaped silicon region comprising a plurality of protrusions over the first silicon region,
wherein the plurality of protrusions comprise a first protrusion,
wherein a diameter of the first protrusion is greater than or equal to 500 nm and less than or equal to 3 ?m,
wherein a length of an axis of the first protrusion is greater than or equal to 0.5 ?m and less than or equal to 1000 ?m,
and

wherein at least one of the plurality of protrusions comprises a bending portion or a branching portion.

US Pat. No. 9,276,222

ORGANOMETALLIC IRIDIUM COMPLEX, LIGHT-EMITTING ELEMENT, LIGHT-EMITTING DEVICE, ELECTRONIC DEVICE, AND LIGHTING DEVICE

Semiconductor Energy Labo...

1. A compound comprising a structure represented by Formula (G1):

wherein R1 and R2 independently represent a substituted or unsubstituted alkyl group having 1 to 6 carbon atoms.

US Pat. No. 9,153,313

NORMALLY-OFF, POWER-GATED MEMORY CIRCUIT WITH TWO DATA RETENTION STAGES FOR REDUCING OVERHEAD POWER

Semiconductor Energy Labo...

1. A memory circuit comprising:
a first circuit configured to retain data in a first period during which a power supply voltage is supplied;
a second circuit configured to save the data retained in the first circuit in the first period and retain the data in a second
period during which the power supply voltage is not supplied, the second circuit comprising:

a first transistor; and
a first node configured to maintain a potential;
a third circuit configured to save the data retained in the second circuit in the second period and retain the data in a third
period during which the power supply voltage is not supplied, the third circuit comprising:

a second transistor; and
a second node configured to maintain a potential; and
a fourth circuit operationally connected to each of the first circuit, the second circuit, and the third circuit, wherein
the fourth circuit is capable of reading the data retained in the second circuit based on the potential of the first node
before the third circuit completes retaining the data in the third circuit.

US Pat. No. 10,219,395

POWER STORAGE UNIT AND ELECTRONIC DEVICE INCLUDING THE SAME

Semiconductor Energy Labo...

1. A power storage unit comprising:a first electrode plate;
a first insulating sheet, wherein the first electrode plate is covered with the first insulating sheet folded in two;
a second electrode plate adjacent to the first electrode plate with a first part of the first insulating sheet placed therebetween;
an exterior body covering the first electrode plate, the first insulating sheet, and the second electrode plate;
a first sealing material sealing a first edge of the exterior body; and
a second sealing material sealing a second edge of the exterior body, the second edge of the exterior body facing the first edge of the exterior body,
wherein a part of the first electrode plate and edges of the first insulating sheet are covered by the first sealing material,
wherein a part of the second electrode plate is covered by the second sealing material, and
wherein the first electrode plate and the first insulating sheet slide together in the exterior body when the exterior body is bent.

US Pat. No. 9,318,374

SEMICONDUCTOR STORAGE DEVICE COMPRISING PERIPHERAL CIRCUIT, SHIELDING LAYER, AND MEMORY CELL ARRAY

Semiconductor Energy Labo...

7. A semiconductor storage device comprising:
a peripheral circuit;
a shielding layer over the peripheral circuit; and
a memory cell array over the shielding layer,
wherein the memory cell array comprises a memory cell comprising a transistor,
wherein the shielding layer is configured to shield the peripheral circuit and the memory cell array from radiation noise
generated between the peripheral circuit and the memory cell array, and

wherein the shielding layer is configured to be supplied with a ground potential.

US Pat. No. 9,263,531

OXIDE SEMICONDUCTOR FILM, FILM FORMATION METHOD THEREOF, AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor device comprising:
a gate electrode layer;
a first insulating layer over the gate electrode layer;
a first oxide semiconductor layer over the first insulating layer;
a second oxide semiconductor layer over the first oxide semiconductor layer;
a source electrode layer and a drain electrode layer on and in contact with the second oxide semiconductor layer;
a third oxide semiconductor layer on and in contact with the second oxide semiconductor layer, the source electrode layer,
and the drain electrode layer,

wherein at least one of the first, second, and third oxide semiconductor layers comprises a single crystal region having a
crystal structure including indium, gallium, and zinc, and

wherein the crystal structure of the single crystal region has bonds for forming a hexagonal lattice in an a-b plane of the
crystal structure and includes a c-axis perpendicular to a surface of the first insulating layer.

US Pat. No. 9,159,793

P-TYPE SEMICONDUCTOR MATERIAL AND SEMICONDUCTOR DEVICE

Semiconductor Energy Labo...

1. A semiconductor material comprising molybdenum oxide, wherein the molybdenum oxide comprises MoOy (2

US Pat. No. 9,086,567

DISPLAY SYSTEM

Semiconductor Energy Labo...

1. A display system comprising:
a frame; and
a display device attached to the frame and arranged to be placed in front of an eye of a user of the display system,
wherein the display device comprises a pixel which comprises:
a transistor;
a first insulating film over the transistor;
a pixel electrode over the first insulating film; and
a second insulating film over the first insulating film, the second insulating film covering an edge portion of the pixel
electrode, and

wherein a portion of the second insulating film, which overlaps with the edge portion, has a taper shape.

US Pat. No. 9,053,675

SIGNAL LINE DRIVER CIRCUIT AND LIQUID CRYSTAL DISPLAY DEVICE

Semiconductor Energy Labo...

1. A driver circuit comprising:
a shift register;
a selection circuit having a function of determining that a pulse signal input from the shift register is output as a first
pulse signal or a second pulse signal, in accordance with a first clock signal and a second clock signal; and

a driving signal output circuit having functions of generating and outputting a driving signal for controlling a potential
of a signal line in accordance with the first and second pulse signals input from the selection circuit and a first control
signal and a second control signal,

wherein the driving signal output circuit comprises:
a latch unit configured to write and store first data and second data in accordance with the first and second pulse signals;
a buffer unit configured to set a potential of the driving signal in accordance with the first data and the second data and
output the driving signal; and

a switch unit configured to control pull-up of the latch unit output of only the first data by being turned on or off in accordance
with the first control signal and the second control signal so as to suppress a change in a potential of the first data.

US Pat. No. 9,865,867

LITHIUM MANGANESE COMPOSITE OXIDE, SECONDARY BATTERY, AND ELECTRICAL DEVICE

Semiconductor Energy Labo...

1. A lithium manganese composite oxide comprising:
a particle comprising a first region including a crystal with a layered rock-salt structure and a second region including
a crystal with a spinel structure,

wherein the second region is in contact with the first region,
wherein the second region covers 10% or more of an entire outside surface of the first region,
wherein the layered rock-salt structure is represented by LirMns-tMtO3,

wherein 1.4?r?2, 0.7?s<1.5, 0?t<1.5, and s?t are satisfied, and
wherein an element M is silicon, phosphorus, or a metal element other than lithium and manganese.

US Pat. No. 9,397,255

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

Semiconductor Energy Labo...

1. A semiconductor device comprising
a first conductive film;
a second conductive film;
a third conductive film over and in contact with the first conductive film;
a fourth conductive film over and in contact with the second conductive film;
a first insulating film over the first conductive film, the third conductive film and the fourth conductive film;
a pixel electrode over the third conductive film with the first insulating film therebetween; and
a transistor comprising a semiconductor film, a gate electrode, a source electrode, a drain electrode and a gate dielectric,
wherein the first conductive film and the second conductive film are transparent, and the third conductive film and the fourth
conductive film are not transparent,

wherein one of the source electrode and the drain electrode is electrically connected with the pixel electrode,
wherein the semiconductor film is an oxide comprising indium (In), gallium (Ga) and zinc (Zn),
wherein a first portion of the second conductive film works as the gate electrode,
wherein a first portion of the pixel electrode works as an upper electrode of a storage capacitor,
wherein a first portion of the first conductive film works as a lower electrode of the storage capacitor,
wherein a first portion of the first insulating film works as a dielectric of the storage capacitor,
wherein the storage capacitor is transparent such that a light passes through the storage capacitor, and
wherein an entirety of the third conductive film overlaps with the first conductive film while the first portion of the first
conductive film does not overlap with the third conductive film.

US Pat. No. 9,281,495

DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE DISPLAY DEVICE

Semiconductor Energy Labo...

1. A display device comprising a cross sectional structure, the cross sectional structure comprising:
a first substrate;
a thin film transistor over the first substrate;
a first insulating layer over the thin film transistor;
a first conductive layer over the first insulating layer wherein the first conductive layer is electrically connected to the
thin film transistor;

a second insulating layer over the first conductive layer;
a pixel electrode over the second insulating layer, the pixel electrode being electrically connected to the thin film transistor;
a third insulating layer over a part of the pixel electrode;
a light emitting layer comprising an organic compound over the pixel electrode, wherein a part of the light emitting layer
is formed over the third insulating layer;

a second electrode over the light emitting layer and the third insulating layer, wherein the pixel electrode is overlapped
with the second electrode with the light emitting layer therebetween;

a second substrate over the second electrode, the second substrate being fixed to the first substrate with a sealing material
therebetween, wherein the first substrate includes a portion which extends beyond a side edge of the second substrate and
is not covered by the second substrate;

a fourth insulating layer over the portion of the first substrate, wherein the fourth insulating layer comprises a same organic
material as the second insulating layer;

a fifth insulating layer over the portion of the first substrate, the fifth insulating layer being formed over the fourth
insulating layer, wherein the fifth insulating layer comprises a same organic material as the third insulating layer; and

a driver circuit over the first substrate, wherein a space is provided between the driver circuit and the sealing material.

US Pat. No. 9,059,029

SEMICONDUCTOR MEMORY DEVICE

Semiconductor Energy Labo...

1. A semiconductor memory device comprising:
a memory cell comprising:
a first transistor comprising:
a first semiconductor layer;
a first gate insulating layer over and in contact with the first semiconductor layer;
a first gate electrode which is in contact with the first gate insulating layer and overlaps with the first semiconductor
layer; and

a source region and a drain region with a region of the first semiconductor layer overlapping with the first gate electrode
located between the source region and the drain region;

a second transistor comprising:
a second semiconductor layer which overlaps with the first gate electrode and is electrically connected to the first gate
electrode;

a second gate insulating layer in contact with a side surface of the second semiconductor layer; and
a second gate electrode which is in contact with the second gate insulating layer and source region at least partly covers
the side surface of the second semiconductor layer; and

a capacitor comprising:
a capacitor layer in contact with a side surface of the first gate electrode; and
a first capacitor electrode which is in contact with the capacitor layer and at least partly covers the side surface of the
first gate electrode,

wherein the second gate insulating layer is over the first capacitor electrode, and the second gate electrode is over the
second gate insulating layer.