US Pat. No. 9,332,354

MICROMECHANICAL DETECTION STRUCTURE FOR A MEMS ACOUSTIC TRANSDUCER AND CORRESPONDING MANUFACTURING PROCESS

STMicroelectronics S.r.l....

1. A micromechanical structure comprising:
a semiconductor substrate having a first surface;
an anchorage structure including a plurality of pillar elements separated from each other by a conductive material; and
a detection capacitor including:
a membrane coupled to said substrate and configured to deform in response to acoustic-pressure waves; and
a fixed electrode that is rigid with respect to said acoustic-pressure waves and is coupled to said substrate by the anchorage
structure, the anchorage structure being configured to support the fixed electrode in a suspended position facing said membrane.

US Pat. No. 9,324,627

ELECTRONIC ASSEMBLY FOR MOUNTING ON ELECTRONIC BOARD

STMicroelectronics S.R.L....

1. An integrated-circuit assembly, comprising:
a package including a first side, a second side opposite to the first side, and a third side disposed between the first and
second sides, a conductive contact element disposed along the first side, and a heat dissipater disposed along the first side;

an integrated-circuit chip disposed in the package, the integrated-circuit chip being thermally coupled to the heat dissipater,
and the integrated-circuit chip having a conductive contact pad electrically coupled to the contact element;

a conductor having a first end electrically coupled to the contact element, extending along the third side of the package,
and having a second end that is accessible from the second side of the package;

a support element having an opening;
wherein the package is disposed in the opening; and
wherein the conductor is disposed in the support element.

US Pat. No. 9,429,967

HIGH PRECISION RESISTOR AND TRIMMING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. An electronic device comprising:
first and second pairs of contacts; and
a resistor comprising a phase change material so as to have an electrically modifiable resistivity;
said resistor comprising first and second portions extending transversely and in direct electrical contact to each other at
a crossing area, at least one of the first and second portions having a varying width;

said first and second portions each having respective ends connected to respective ones of the first and second pairs of contacts.

US Pat. No. 9,859,256

INK PRINTED WIRE BONDING

STMICROELECTRONICS S.R.L....

1. A device, comprising:
a package substrate;
a plurality of contact pads on the package substrate;
a first die coupled to the package substrate including a plurality of pillars;
a first plurality of ink printed wires, each wire having a first surface opposite a second surface, the first plurality of
ink printed wires electrically coupled between the plurality of contact pads and the plurality of pillars of first die; and

a molding compound on the package substrate, the first die, and the first plurality of ink printed wires, the molding compound
being on both the first surface and the second surface of each wire of the first plurality of ink printed wires.

US Pat. No. 9,391,708

MULTI-SUBSTRATE ELECTRO-OPTICAL INTERCONNECTION SYSTEM

STMICROELECTRONICS S.R.L....

1. A system of intra-board, chip-to-chip communications for an electronic system comprising:
at least one printed circuit board (PCB);
at least one multi-chip module primary substrate comprising electrical interconnections electrically coupled to said at least
one PCB and having a reserved area;

a plurality of IC chips mounted side-by-side around the reserved area of said at least one multi-chip module primary substrate,
with each IC chip electrically coupled to said at least one multi-chip module primary substrate via the electrical interconnections;

a photonic waveguide silicon die mounted on the reserved area of said at least one multi-chip module primary substrate and
to be optically coupled to at least one continuous wave laser source; and

a plurality of integrated transceiver circuit dies mounted to peripheral portions of said photonic waveguide silicon die,
side-by-side with said plurality of IC chips;

said photonic waveguide silicon die comprising
optical signal modulation devices and optical signal detection devices defined therein and under a footprint of said plurality
of integrated transceiver circuit dies and coupled to a respective IC chip,

at least one first optical waveguide network for distributing the continuous wave laser light to said optical modulation devices
underneath said respective integrated transceiver circuit dies, and

a second waveguide network for interconnecting an output of at least one of said optical modulation devices underneath a respective
one of said plurality of integrated transceiver circuit dies to said optical signal detection devices of another one of said
plurality of integrated transceiver circuit dies.

US Pat. No. 9,452,922

MICROELECTROMECHANICAL DEVICE WITH SIGNAL ROUTING THROUGH A PROTECTIVE CAP

STMICROELECTRONICS S.R.L....

1. A microelectromechanical device, comprising:
a body including a microelectromechanical structure, the microelectromechanical structure including a plurality of output
terminals configured to provide respective output signals;

conductive bonding regions;
a cap bonded to the body and electrically coupled to the microelectromechanical structure through the conductive bonding regions,
the cap including:

a selection module having:
first selection terminals coupled to respective ones of the plurality of output terminals of the microelectromechanical structure;
a second selection terminal; and
a control terminal configured to selectively couple one of the first selection terminals to the second selection terminal
in accordance with one of a plurality of coupling configurations corresponding to respective operating conditions.

US Pat. No. 9,325,450

METHOD AND SYSTEM FOR PROCESSING DIGITAL DATA, CORRESPONDING APPARATUS AND COMPUTER PROGRAM PRODUCT

STMicroelectronics S.r.l....

1. A method, comprising:
automatically producing from digital data signals a plurality of families of metrics, at least one family of the plurality
of families allowing metric wrapping;

automatically computing a set of differences of metrics selected out of said plurality of families of metrics, the set of
differences excluding differences between wrapping metrics of different families of the plurality of families of metrics;

automatically generating signals representative of order relationships of combinations of corresponding unwrapped metrics
based on said set of differences; and

automatically decoding encoded data in the digital data signals based on the generated signals representative of order relationships.

US Pat. No. 9,076,239

METHOD AND SYSTEMS FOR THUMBNAIL GENERATION, AND CORRESPONDING COMPUTER PROGRAM PRODUCT

STMICROELECTRONICS S.R.L....

12. A method of generating a thumbnail, the method comprising:
identifying a thumbnail having a given size from an image for which a spatial frequency domain representation is available;
reducing the size of said image by zooming;
wherein said zooming comprises a spatial frequency domain zooming on the image to generate the thumbnail having an initial
size and an image pixel domain zooming to fit said thumbnail to the given size;

wherein said spatial frequency domain zooming comprises applying a zooming factor z1 wherein:

z1 is equal to 1/k if (½qk) is less than a zoom value and if the zoom value is less than or equal to (1/qk) when k is equal
to 1, 2, or 4; and

wherein z1 is equal to ? if the zoom value is less than or equal to (1/q8);

where:
the zoom value comprises an overall zooming factor resulting from both said spatial frequency domain zooming and said pixel
domain zooming, and

q comprises a parameter selected in the interval {0.5, 1}.

US Pat. No. 9,466,347

ROW DECODER FOR NON-VOLATILE MEMORY DEVICES AND RELATED METHODS

STMICROELECTRONICS INTERN...

1. An integrated circuit comprising:
an array of phase-change memory (PCM) cells;
a plurality of wordlines coupled to the array of PCM cells; and
a row decoder circuit coupled to the plurality of wordlines, the row decoder circuit comprising
a first low voltage logic gate,
a first high voltage level shifter having an output coupled to an input of the first low voltage logic gate, the high voltage
being greater than the low voltage,

a second low voltage logic gate,
a second high voltage level shifter having an output coupled to an input of the second low voltage logic gate,
a first low voltage logic circuit having an output coupled to the input of the second low voltage logic gate,
a second low voltage logic circuit having an output coupled to the input of the second low voltage logic gate, and
a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and
an output coupled to a selected wordline of the plurality of wordlines.

US Pat. No. 9,245,200

METHOD FOR DETECTING A STRAIGHT LINE IN A DIGITAL IMAGE

STMicroelectronics S.r.l....

1. An apparatus, comprising:
an edge-detector circuit configured to identify an edge within an image that includes a boundary, the edge including a plurality
of pixels; and

a straight-line-detector circuit configured to identify,
a first straight line that intersects a first pixel of the identified edge with a first identifier that indicates at least
two points at which the first straight line intersects the boundary,

a second straight line that intersects a second pixel of the identified edge with a second identifier that indicates at least
two points at which the second straight line intersects the boundary,

an edge straight line representing the identified edge based on the first and second identifiers,
wherein the straight-line detector circuit is further configured to,
quantize a two-dimensional parameter space, defined by determined first and second identifiers, according to a predetermined
quantization map, including dividing the boundary into a plurality of segments and assigning a unique index to each segment
of the plurality of segments,

generate an accumulation space by accumulating the determined first and second identifiers in the quantized two-dimensional
parameter space, and

detect the straight line based on a distribution of the determined first and second identifiers in the accumulation space;
determine the unique indices of those segments of the plurality of segments, which comprise an intersection, to thereby detect
the at least two points of intersection for each straight line, and

select two unique indices out of the determined unique indices for each of the straight lines to determine the first and second
identifiers.

US Pat. No. 9,401,349

STACK OF INTEGRATED-CIRCUIT CHIPS AND ELECTRONIC DEVICE

STMICROELECTRONICS (GRENO...

1. A stack of integrated-circuit chips, comprising:
a first and a second integrated-circuit chip having opposing first and second faces, respectively, located at a distance from
one another;

a spacer interposed between a part of a peripheral region of the second face of the second chip and the first face of the
first chip, the spacer being vertically aligned with the first face of the first chip and the part of the peripheral region
of the second face of the second chip;

a first adhesive attaching the spacer only to one of the first and second faces; and
a second adhesive interposed between a central region of the second face of the second chip and the first face of the first
chip in order to fasten the first and second integrated-circuit chips to one another;

wherein the second adhesive is separated from and not in contact with the spacer.

US Pat. No. 9,234,859

INTEGRATED DEVICE OF A CAPACITIVE TYPE FOR DETECTING HUMIDITY, IN PARTICULAR MANUFACTURED USING A CMOS TECHNOLOGY

STMicroelectronics S.r.l....

5. A semiconductor chip;
a sensing capacitor and a reference capacitor integrated in the semiconductor chip, each of the sensing and reference capacitors
having a first electrode and a second electrode, the first and second electrodes of each of the sensing and reference capacitors
being arranged at a distance from each other and mutually insulated;

a hygroscopic layer over the sensing and reference capacitors;
a conductive shielding layer over the reference capacitor and not over the sensing capacitor;
an insulating structure that includes a plurality of metal regions arranged in a plurality of metal levels, the first and
second electrodes of the sensing and reference capacitors being formed by respective metal regions; and

a passivation layer over the conductive shielding layer, the conductive shielding layer and passivation layer having an opening
over the sensing capacitor.

US Pat. No. 9,461,130

ELECTRONIC DEVICE COMPRISING CONDUCTIVE REGIONS AND DUMMY REGIONS

STMicroelectronics S.r.l....

1. A method for integrating a power electronic device in a chip of semiconductor material of a first type of conductivity,
comprising:
forming an epitaxial layer of a second type of conductivity extending into the chip from a front surface of the chip and comprising
an epitaxial region, a portion of the chip between a rear surface of the chip opposite the front surface and the epitaxial
layer defining a collector layer comprising a collector region,

forming a body layer of the first type of conductivity extending into the epitaxial layer from the front surface,
forming a gate region of conductive material in a trench extending from the front surface into the epitaxial layer through
the body layer,

forming a source region of the second type of conductivity extending into the body layer from the front surface at a first
side of said trench, wherein the source region and portions of the body layer delimited by said first side identify an emitter
region, and portions of the body layer delimited by a second side of the trench opposite the first side identify a dummy emitter
region,

wherein forming the gate region comprises forming the gate region along a first wall of the trench facing the emitter region,
and

forming a dummy gate region in said trench, said dummy gate region being electrically isolated from said gate region and extending
along a second wall of the trench opposite said first wall.

US Pat. No. 9,324,825

MANUFACTURING METHOD OF A GRAPHENE-BASED ELECTROCHEMICAL SENSOR, AND ELECTROCHEMICAL SENSOR

STMICROELECTRONICS S.R.L....

1. An electrochemical sensor, comprising:
a substrate having a first side;
a first electrode and a second electrode extending over the first side of the substrate;
a graphene layer extending over the first side of the substrate, in electrical contact with the first and second electrodes;
a structural layer of dry resist, extending on the graphene layer; and
a fluidic path extending through a thickness of the structural layer and on said graphene layer, wherein the fluidic path
is disposed entirely between the first and second electrodes.

US Pat. No. 9,076,555

FAILURE DIAGNOSIS CIRCUIT

STMicroelectronics S.r.l....

1. A circuit, comprising:
a multiplexer configured to receive a first sequence of failure testing address signals and a second sequence of failure testing
address signals, and to selectively output one of the sequences of failure testing address signals in response to a selecting
signal for application to an addressable module having a set of addressable components; and

a controller configured to generate the first sequence of failure testing address signals and the selecting signal and to
read out an output of the addressable module in response to the first sequence of failure testing address signals.

US Pat. No. 9,070,694

MANUFACTURING OF ELECTRONIC DEVICES IN A WAFER OF SEMICONDUCTOR MATERIAL HAVING TRENCHES WITH DIFFERENT DIRECTIONS

STMicroelectronics S.r.l....

1. A method, comprising:
forming a plurality of trenches extending into a wafer of semiconductor material from a main surface thereof, said wafer including
a plurality of individual electronic devices;

forming at least one layer of electrically insulating material within each trench; and
forming at least one layer of electrically conductive material within each trench superimposed to said at least one layer
of insulating material,

wherein forming the plurality of trenches comprises:
forming the trenches partitioned into a plurality of sub-sets, the trenches of a first sub-set being oriented along a first
common direction and the trenches of a second sub-set being oriented along a second common direction different from the first
common direction, the trenches of the first sub-set being formed in a first area on a main surface of the wafer in each individual
electronic device, the trenches of the second sub-set being formed in a second area of the wafer in each individual electronic
device; and

forming a contact terminal for each individual electronic device, the contact terminal comprising a peripheral element encircling
the individual electronic device and being electrically connected to each end of said at least one layer of electrically conductive
material within the trenches of the first sub-set and to one end only of said at least one layer of electrically conductive
material within the trenches of the second sub-set.

US Pat. No. 9,219,481

CAPACITIVE COUPLING, ASYNCHRONOUS ELECTRONIC LEVEL SHIFTER CIRCUIT

STMicroelectronics S.r.l....

1. A device, comprising:
a substrate having a first well and a second well;
an asynchronous electronic level shifter circuit that includes:
a first transmitter circuit configured to be coupled to a first voltage and to generate a first electrical communication signal,
the first transmitter circuit being in the first well;

a second transmitter circuit configured to be coupled to a second voltage, that is different from the first voltage, and to
generate a second electrical communication signal, the second transmitter circuit being in the second well;

a first receiver circuit configured to be coupled to the second voltage, the first receiver circuit being in the second well;
and

a second receiver circuit configured to be coupled to the first voltage, the second receiver circuit being in the first well;
a capacitive coupling stage configured to operate in a first operating condition, during which the capacitive coupling stage
is configured to receive the first electrical communication signal and to supply a first filtered signal to said first receiver
circuit, and the capacitive coupling stage is configured to operate in a second operating condition, during which the capacitive
coupling stage is configured to receive the second electrical communication signal and to supply a second filtered signal
to said second receiver circuit.

US Pat. No. 9,096,424

ASSEMBLY OF A CAPACITIVE ACOUSTIC TRANSDUCER OF THE MICROELECTROMECHANICAL TYPE AND PACKAGE THEREOF

STMicroelectronics S.r.l....

1. An assembly comprising:
a first semiconductor die having a first surface and a second surface;
a microelectromechanical sensor (MEMS sensor) integrated in the first semiconductor die at the first surface and having a
fixed electrode and a mobile electrode, the fixed and mobile electrodes being configured to sense a change in capacitance,
the first semiconductor die including an opening at the second surface that exposes a bottom surface of the MEMS sensor;

a second semiconductor die coupled to the first surface of the first semiconductor die, the second die including a first through
hole, the first through hole of the second semiconductor die located above the MEMS sensor;

an electronic circuit integrated in the second semiconductor die, the electronic circuit operatively coupled to said MEMS
sensor;

conductive paths in the first semiconductor die configured to provide signals generated by the fixed electrode and the mobile
electrode;

conductive elements located between the first die and second die configured to provide the signals from the first semiconductor
die to the second semiconductor die; and

a substrate coupled to the second surface of the first semiconductor die, the substrate including a second through hole, the
second through hole located below the opening in the first semiconductor die.

US Pat. No. 9,297,905

METHOD OF ACQUIRING CDMA-MODULATED SATELLITE SIGNALS AND RECEIVING APPARATUS IMPLEMENTING THE METHOD

STMicroelectronics S.r.l....

1. A method of acquiring a satellite signal, comprising:
receiving a CDMA-modulated signal;
defining a first search frequency interval and a first reception sensitivity;
performing a first acquisition of the CDMA-modulated signal as a function of the first reception sensitivity and the first
search frequency interval;

providing, based on the performed first acquisition, a successful acquisition result or a failed acquisition result;
in response to providing the failed acquisition result:
defining a second search frequency interval, narrower than the first search frequency interval, and a second reception sensitivity,
greater than the first reception sensitivity, the second search frequency interval depending on a power of a side lobe of
the CDMA-modulated signal;

performing a second acquisition of the CDMA-modulated signal as a function of the second reception sensitivity and of the
second search frequency interval; and

providing, based on the performed second acquisition, a further successful acquisition result or the failed acquisition result.

US Pat. No. 9,461,769

OPTICAL DEMULTIPLEXER AND METHOD OF CONTROLLING AN OPTICAL DEMULTIPLEXER

STMICROELECTRONICS S.R.L....

1. An optical demultiplexer comprising:
a Mach-Zehnder interleaver having a first port configured to receive an input of a sum of a first optical signal with a second
optical signal, a second port configured to output the first optical signal, a third port configured to output the second
optical signal, and a fourth port; and

an optical component coupled to the second port and configured to split the first optical signal into a weak intensity optical
signal and a strong intensity optical signal;

said optical component configured to generate the weak intensity optical signal and back reflect it through said Mach-Zehnder
interleaver towards the fourth port.

US Pat. No. 9,071,260

METHOD AND RELATED DEVICE FOR GENERATING A DIGITAL OUTPUT SIGNAL CORRESPONDING TO AN ANALOG INPUT SIGNAL

STMicroelectronics S.r.l....

1. A circuit, comprising:
an input node configured to receive an input signal in a first domain;
a generator configured to generate a periodic signal in the first domain, said periodic signal having a main frequency and
first tones which are harmonics of the main frequency;

a combiner configured to combine the input and periodic signals into a resulting signal in the first domain;
a converter configured to sample the resulting signal at a sampling frequency and convert the sampled resulting signal into
a converted signal in a second domain; and

a filter having a frequency response including zeroes at a plurality of second tones with passbands between adjacent second
tones, said filter configured to remove frequency components of the periodic signal from the converted signal;

wherein the main frequency is equal to an integer fraction of the sampling frequency of the converter and the harmonic first
tones of the periodic signal are centered on ones of the second tones for the zeroes of the frequency response.

US Pat. No. 9,615,444

MANUFACTURING OF A HEAT SINK BY WAVE SOLDERING

STMicroelectronics S.r.l....

1. An electronic assembly, comprising:
an electronic board with a set of vias passing through the electronic board between a first surface and a second surface opposite
the first surface,

an electronic device attached to the first surface of the electronic board,
a heat sink precursor attached to the second surface of the electronic board, the heat sink precursor defining a cavity facing
the set of vias, and

solder material that fills the set of vias so as to join a back of the electronic device to the set of vias and at least partially
fills the cavity of the heat sink precursor so as to join the heat sink precursor to the set of vias and form a corresponding
heat sink;

wherein the electronic board comprises a first region and a second region arranged around the set of vias, the solder penetrating
through the set of vias causing a joining of a radiator of the electronic device to the first region and causing a joining
of an electrical contact of the electronic device to the second region.

US Pat. No. 9,077,253

CONTROL INTEGRATED CIRCUIT FOR A POWER TRANSISTOR OF A SWITCHING CURRENT REGULATOR

STMicroelectronics S.r.l....

1. A control circuit for controlling a first switch of a switching current regulator, said control circuit comprising:
a comparator configured to compare a first signal, representative of a first current through a primary winding of the switching
current regulator, with a second signal;

a charge/discharge circuit configured to selectively charge and discharge a capacitor; and
a divider circuit configured to generate said second signal as a ratio of a third signal, proportional to a the input voltage
of the switching current regulator, to a voltage on the capacitor.

US Pat. No. 9,329,610

BIASING CIRCUIT FOR A MICROELECTROMECHANICAL ACOUSTIC TRANSDUCER AND RELATED BIASING METHOD

STMicroelectronics S.r.l....

1. A biasing circuit, comprising:
an output terminal;
a biasing terminal configured to receive from a voltage-booster stage a boosted voltage for biasing the output terminal;
a filter coupled between the biasing terminal and said output terminal, and configured to filter disturbances on said boosted
voltage;

a switch configured to provide a current path between said biasing terminal and said output terminal when the switch is closed
and allow the filter to filter the disturbances when the switch is open, the switch having a control terminal; and

a control stage having an output terminal electrically coupled to the control terminal of the switch, the control stage being
configured to close the switch by providing a control signal from the output terminal of the control stage to the switch,
wherein the control stage includes a first input terminal configured to receive said boosted voltage and a second input terminal
configured to receive a timing signal, and the control stage is configured to supply said control signal based on the boosted
voltage and the timing signal.

US Pat. No. 9,325,263

SENSORLESS ROTOR ANGLE DETECTION CIRCUIT AND METHOD FOR A PERMANENT MAGNET SYNCHRONOUS MACHINE

STMicroelectronics S.r.l....

1. A sensorless rotor angle detection circuit for a motor having multiple phase windings, comprising:
a current sensing circuit configured to sense current in a plurality of the motor phase windings;
a first phase conversion circuit configured to convert a multi-phase current sense signal output from the current sensing
circuit to a two-phase current signal; and

a position detection circuit configured to process said two-phase current signal and determine a rotor angle of said motor;
wherein processing of the two-phase current signal comprises:
determining zero crossing points of an envelope of a first signal of the two-phase current signal, said zero crossings being
indicative of rotor angle direction;

sampling the first signal and a second signal of the two-phase current signal at positions positively and negatively offset
from one of the zero crossing points to determine a direction of a rotor flux axis;

sampling one of the first and second signals in correspondence with a phase reference to determine information indicative
of the rotor angle.

US Pat. No. 9,231,540

HIGH PERFORMANCE CLASS AB OPERATIONAL AMPLIFIER

STMICROELECTRONICS (GRENO...

1. A class AB operational amplifier comprising:
an input stage;
an output stage; and
a level shifter stage and a control circuit coupled thereto and configured to control a quiescent current of the output stage
and to transfer a signal from the input stage to the output stage,

the control circuit comprising
a differential pair of transistors having differential input terminals,
an impedance,
first and second intermediate transistors coupled in series by the impedance and arranged between a first and a second reference
voltage, and

the impedance having a voltage thereacross being a differential voltage at the differential input terminals that controls
the level shifter stage.

US Pat. No. 9,135,681

IMAGE CHROMA NOISE REDUCTION

STMicroelectronics S.r.l....

1. An apparatus, comprising:
a dynamic range calculation circuit configured to determine first and second dynamic ranges of first and second chrominance
signals representing respectively first and second chrominance planes of a plurality of pixels in an image, and further configured
to determine a dynamic range of a luminance signal representing luminance of the plurality of pixels;

a filter circuit configured to low pass filter the first chrominance signal and generate a low pass filtered first chrominance
signal;

a weighting coefficient calculation circuit configured to compute a weighting coefficient on the basis of the dynamic ranges
of the first chrominance signal, the second chrominance signal, and the luminance signal; and

a weighted sum calculation circuit configured to generate a first output chrominance signal by computing a weighted sum of
the first chrominance signal and the low pass filtered first chrominance signal using the computed weighting coefficient;

wherein the filter circuit is further configured to compute a weighted average of the first chrominance signal within a neighborhood
of a central pixel, each weight of the weighted average being a decreasing function of a difference between a luminance of
a respective pixel within the neighborhood and a luminance of the central pixel, and being a decreasing function of a difference
between a first chrominance plane of the respective pixel and a first chrominance plane of the central pixel and to set the
computed weighted average, as the low-pass filtered first chrominance signal for the central pixel.

US Pat. No. 9,105,316

INTEGRATED CIRCUIT PACKAGE WITH MULTIPLE DIES AND A MULTIPLEXED COMMUNICATIONS INTERFACE

STMicroelectronics S.r.l....

21. A method for use in a package comprising a first die and a second die, the method comprising:
providing control signals;
providing memory transactions;
multiplexing the control signals and the memory transactions onto a shared interface between the first and second die such
that a plurality of connections of the interface are shared by the control signals and the memory transactions; and

transporting the control signals and memory transactions over the shared interface in packets.

US Pat. No. 9,275,000

ELECTRONIC DEVICE WITH ADDRESS PROGRAMMABLE THROUGH REDUCED NUMBER OF TERMINALS

STMICROELECTRONICS S.R.L....

1. An electronic device having a device address associated therewith, the electronic device comprising:
a plurality of device terminals comprising a plurality of operative terminals configured to receive corresponding operative
signals comprising at least one of a data signal and a synchronization signal, and a plurality of reference terminals configured
to receive corresponding reference voltages comprising at least one of a supply voltage and a ground voltage;

at least one programming terminal; and
assignment circuitry coupled to said plurality of device terminals and said programming terminal and configured to
receive a plurality of comparison signals, via said plurality of device terminals, corresponding to at least one of the operative
signals and the reference voltages, and a programming signal via said at least one programming terminal, the programming signal
corresponding to any of the plurality of comparison signals and at least one of the operative signals varying over a given
time period during operation,

perform a plurality of comparisons over the given time period between the plurality of comparison signals and the programming
signal to recognize the programming signal as being one of the plurality of comparison signals, the plurality of comparison
signals also being for respective device functions that are different than the plurality of comparisons, and

generate the device address based upon the programming signal being equal to the one of the plurality of comparison signals,
the device address having a number of programmable address bits thereof that are determined based upon the programming signal,
the number of bits being greater than a quantity of the at least one programming terminal.

US Pat. No. 9,226,386

PRINTED CIRCUIT BOARD WITH REDUCED EMISSION OF ELECTRO-MAGNETIC RADIATION

STMICROELECTRONICS S.R.L....

1. A printed circuit board comprising:
a first outer layer;
a second outer layer;
an integrated circuit mounted on the second outer layer, said integrated circuit having:
a single exposed pad electrically connected to a ground reference,
a first supply pin electrically connected to a first power supply,
a second supply pin electrically connected to a second power supply,
wherein the first power supply is configured to generate a first supply current with frequency components higher than frequency
components of a second supply current generated by the second power supply;

a first decoupling capacitor mounted on the second outer layer in the proximity of the first supply pin, the first decoupling
capacitor having a first terminal electrically connected with the first supply pin and having a second terminal;

an inner layer interposed between the first outer layer and the second outer layer, the inner layer comprising a metal layer
electrically connected to said ground reference;

a first via configured to electrically connect the exposed pad with the metal layer of the inner layer;
a second via configured to electrically connect the second terminal of the first decoupling capacitor with the metal layer
of the inner layer;

a second decoupling capacitor having a first pin electrically connected to the second power supply and having a second pin
electrically connected to said ground reference, wherein the value of the capacitance of the second decoupling capacitor is
greater than the value of the capacitance of the first decoupling capacitor.

US Pat. No. 9,184,138

SEMICONDUCTOR INTEGRATED DEVICE WITH MECHANICALLY DECOUPLED ACTIVE AREA AND RELATED MANUFACTURING PROCESS

STMicroelectronics (Greno...

1. A semiconductor integrated device comprising:
a die having a body of semiconductor material with a front surface, a back surface, and an external frame, an active area
arranged at the front surface, a coating material covering a portion of the front surface, the body including a trench arrangement
that is configured to mechanically decouple the active area from stresses, wherein the trench arrangement is configured to
release the active area from the external frame of the body; and

a package that includes mold compound and a support element, the back surface of the die being located on the support element,
the external frame being configured to absorb the stresses induced by the package.

US Pat. No. 9,331,474

OVER-VOLTAGE PROTECTION CIRCUIT FOR A DRIVE TRANSISTOR

STMICROELECTRONICS INTERN...

1. A circuit, comprising:
a drive transistor having a control terminal configured to receive a drive signal and having a first conduction terminal and
a second conduction terminal, wherein said first conduction terminal is configured for connection to a load circuit;

a sense circuit configured to sense a voltage across the first and second conduction terminals;
a comparator circuit configured to compare the sensed voltage to voltage threshold and generate a signal indicative of an
over-voltage condition; and

drive circuitry configured to generate said drive signal in response to a pulse width modulation (PWM) signal, said drive
circuit including a force on circuit actuated in response to said signal indicative of the over-voltage condition to force
said drive transistor to turn on irrespective of the PWM signal.

US Pat. No. 9,270,855

SCANNER APPARATUS HAVING PRINTING UNIT AND SCANNING UNIT, RELATED METHOD AND COMPUTER PROGRAM PRODUCT

STMicroelectronics S.r.l....

1. An integrated scanner apparatus, including:
a support surface for objects to be scanned;
a scanner to perform a scanning movement relative to said support surface to capture images of portions of objects being scanned
when in a capture scanning position;

a printer carried by a carriage mobile with respect to said support surface;
wherein said scanner is carried by said carriage mobile carrying said printer to be imparted said scanning movement by said
carriage mobile; and

wherein said scanner is selectively tiltable between a preview scanning position and the capture scanning position, the scanner
configured to be automatically moved between the preview and capture scanning positions and to image a document to be scanned
from a stationary position when in the preview scanning position.

US Pat. No. 9,263,120

DYNAMICALLY CONFIGURABLE SRAM CELL FOR LOW VOLTAGE OPERATION

STMicroelectronics S.r.l....

1. A memory array including a plurality of memory cells configured to store data, wherein at least one memory cell of said
memory array comprises:
a first transistor;
a second transistor;
wherein the first and second transistors are coupled in series to form an inverter circuit of a latch;
a first bias node configured to generate a variable first bias voltage coupled to a body of the second transistor;
a second bias node configured to generate a variable second bias voltage coupled to a source terminal of the second transistor;
and

an access transistor coupled between an access node and an intermediate node between the first and second transistors,
wherein during writing of data into the latch of the memory cell, said variable second bias voltage having a first voltage
value selected dependent on a logic state of the data to be written into the memory cell that is present on the access node;
and

wherein during reading of data into the latch of the memory cell, said variable second bias voltage having a second voltage
value different from the first voltage value.

US Pat. No. 9,188,683

ENCAPSULATED PHOTOMULTIPLIER DEVICE OF SEMICONDUCTOR MATERIAL, FOR USE, FOR EXAMPLE, IN MACHINES FOR PERFORMING POSITRON-EMISSION TOMOGRAPHY

STMicroelectronics S.r.l....

8. A photomultiplier device, comprising a plurality of chips of semiconductor material, each chip integrating a plurality
of photon detecting elements, the chips being attached to a base substrate of an insulating organic material forming a plurality
of conductive paths and being covered by a transparent encapsulating layer of a silicone resin;
wherein the base substrate includes a core layer of insulating material, a first stack of conductive layers and of insulating
layers, formed on a first side of the core layer and a second stack of conductive layers and of insulating layers, formed
on a second side of the core layer, adjacent conductive layers in the first and in the second stacks being mutually spaced
by the insulating layers and being coupled to each other by interlevel conductive vias and the first and the second stacks
being electrically coupled by conductive through vias extending across the core layer; and

wherein the first stack includes, mutually overlapping, at least one chip coupling layer and a first shielding layer contiguous
with the core layer; and the second stack includes, mutually overlapping, at least one second shielding layer contiguous with
the core layer and an external coupling layer, at least one stack between the first and the second stacks including a routing
layer arranged between a pair of shielding layers.

US Pat. No. 9,253,567

ARRAY MICROPHONE APPARATUS FOR GENERATING A BEAM FORMING SIGNAL AND BEAM FORMING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. An array microphone apparatus to generate a beam forming signal, the apparatus comprising:
first, second, and third omni-directional microphones to convert an audible signal into corresponding first, second, and third
electrical signals, respectively, said first, second, and third omni-directional microphones arranged in a horizontal coplanar
alignment, the second omni-directional microphone being disposed between the first and third omni-directional microphones;

a directional microphone forming device to receive the first, second, and third electrical signals and to produce a first
directional microphone signal having a bi-directional pattern;

a magnitude and phase response handler device to receive the second electrical signal and to output a second directional microphone
signal having an omni-directional pattern, the omni-directional pattern shifted by a prefixed value with respect to the bi-directional
pattern of the first directional microphone signal; and

a combining device to receive the first and second directional microphone signals and to output a combined directional microphone
signal having a combined beam pattern correlated to the bi-directional pattern of the first directional microphone signal
and to the omni-directional pattern of the second directional microphone signal, the combined directional microphone signal
being perpendicular to the horizontal coplanar alignment of the first, second, and third omni-directional microphones.

US Pat. No. 9,230,720

ELECTRICALLY TRIMMABLE RESISTOR DEVICE AND TRIMMING METHOD THEREOF

STMicroelectronics S.r.l....

1. A circuit, comprising:
a circuit part;
first and second connection pads; and
a trimmable resistor trimmable by Joule effect, the trimmable resistor having:
first and second connection terminals electrically coupled to the circuit part, at least one of the first and second connection
terminals being configured to be electrically coupled in a trimming phase to the first connection pad;

an intermediate terminal electrically coupled to the second connection pad; and
first and second resistor portions, the first resistor portion positioned between the first connection terminal and the intermediate
terminal and the second resistor portion positioned between the second connection terminal and the intermediate terminal,
the first and second connection pads being configured to receive a substantially zero voltage drop between the first and the
second connection terminals and the intermediate terminal being configured to receive an electrical quantity able to generate
in the first and second resistor portions respective trimming current flows that modify an electric characteristic of the
trimmable resistor.

US Pat. No. 9,385,671

CONTROL CIRCUIT FOR LOW NOISE AMPLIFIER AND RELATED DIFFERENTIAL AND SINGLE-ENDED AMPLIFICATION DEVICES

STMicroelectronics S.r.l....

1. An apparatus, comprising a control circuit for generating a first control voltage, a second control voltage and a third
control voltage, for controlling a low noise amplifier that includes a transconductance amplification stage controlled by
said first control voltage, and a current steering stage controlled by said second control voltage and said third control
voltage, said control circuit comprising:
a first pair of matched transistors, comprising first and second transistors having respective first current terminals connected
in common and having respective second current terminals connected in common, and being respectively controlled by said third
control voltage and said second control voltage;

a diode-connected transistor coupled to said second current terminals of the first pair of matched transistors to sink currents
flowing there through, said first control voltage being the voltage at the control terminal of the diode-connected transistor;

a second pair of matched transistors comprising third and fourth transistors configured to be respectively controlled by said
third control voltage and said second control voltage and to generate respective single-ended output voltages, having respective
first current terminals connected in common, being of the same type of said first pair of matched transistors;

a fifth transistor and a sixth transistor connected to mirror a current flowing through said diode-connected transistor and
to sink currents flowing through said second pair of matched transistors;

a first operational amplifier configured to generate said second control voltage as an amplified replica of a difference between
said first output voltage and a first reference voltage; and

a second operational amplifier configured to generate said third control voltage as an amplified replica of a difference between
said second output voltage and a second reference voltage.

US Pat. No. 9,324,838

LDMOS POWER SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME

STMicroelectronics S.R.L....

1. An electronic semiconductor device comprising:
a semiconductor body having a first side and a second side opposite to one another along a first direction and including a
first structural region, which faces the second side and has a first conductivity; and a second structural region which extends
over the first structural region, faces the first side, and has a second conductivity opposite to the first conductivity;

a body region having the second conductivity and extending in the second structural region at the first side;
a source region having the first conductivity, extending within the body region and facing the first side;
a drain region having the first conductivity and facing the first side of the semiconductor body;
a gate electrode extending over a portion of the first side of the semiconductor body between the source region and the drain
region;

a first trench which extends through the second structural region and houses a trench dielectric region and a first trench
conductive region; and

a second trench which extends through part of the second structural region inside the body region, said second trench housing
a second trench conductive region in electrical contact with the body region and with the source region,

wherein the drain region extends through the second structural region, electrically contacts the first structural region,
and is arranged between, and in direct contact with, the body region and the trench dielectric region, said first and second
trench conductive regions being electrically coupled to one another.

US Pat. No. 9,097,525

DRIVING CIRCUIT FOR A MICROELECTROMECHANICAL GYROSCOPE AND RELATED MICROELECTROMECHANICAL GYROSCOPE

STMicroelectronics S.r.l....

1. A driving circuit, comprising:
a first output terminal and a second output terminal configured to be coupled to a set of driving electrodes, the driving
electrodes being configured to be coupled to a driving mass of a gyroscope and configured to drive the driving mass in resonance
condition;

a driving stage configured to supply driving signals to the first and the second output terminals to cause oscillation in
resonance condition of said driving mass;

a reading stage configured to read the first and the second output terminals to detect movement of said driving mass and implement
a feedback control of said driving signals; and

a switching circuit configured to selectively couple said reading stage to the first and the second output terminals to read
the first and the second output terminals and selectively decouple said driving stage from the set of driving electrodes for
a discrete-time detection of movement of said driving mass.

US Pat. No. 9,394,160

MICROFLUIDIC DEVICE WITH INTEGRATED STIRRING STRUCTURE AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. A microfluidic device comprising:
a semiconductor body having a first side and a second side;
a well in the semiconductor body at the first side, the well having a bottom surface, the well being configured to contain
a fluid; and

a first stirring structure integrated in the well, the first stirring structure having a first base coupled to the bottom
surface of the well and having a first plurality of beams cantilevered from the first base; and

an electrode in the bottom surface of the well, ends of the first plurality of beams that are distal from the first base overlapping
the electrode, the first plurality of beams being configured to move in a direction that is substantially perpendicular to
the bottom surface in response to a first voltage being applied to the electrode and a second voltage being applied to the
first plurality of beams.

US Pat. No. 9,245,606

SRAM MEMORY DEVICE AND TESTING METHOD THEREOF

STMICROELECTRONICS INTERN...

1. An integrated circuit, comprising:
a static random-access memory (SRAM) array having a plurality of memory cells;
a driving circuit configured to receive an internal clock signal; and
a controller configured to:
receive an external clock signal formed by a succession of external pulses;
generate the internal clock signal having a succession of internal pulses;
generate in a first mode, for each external pulse, a corresponding internal pulse;
control in the first mode the driving circuit to carry out one access to the memory array for each internal pulse;
generate in a second mode, for each external pulse, a pair of internal pulses, the pair of internal pulses including a first
pulse and a second pulse, the first pulse occurring before the second pulse;

direct in the second mode, upon receiving a first pulse of said pair of internal pulses, the driving circuit to write a first
data item in a set of memory cells;

direct in the second mode, upon receiving a second pulse of said pair of internal pulses, the driving circuit to read said
set of memory cells to acquire a second data item;

compare the first data item with the second data item; and
detect at least one faulty memory cell based on the comparison of the first and second data items.

US Pat. No. 9,456,474

BIASING AND DRIVING CIRCUIT, BASED ON A FEEDBACK VOLTAGE REGULATOR, FOR AN ELECTRIC LOAD

STMICROELECTRONICS S.R.L....

1. A biasing and driving circuit for an electric load, having input terminals configured to receive an a.c. input voltage
and output terminals configured to supply a d.c. output voltage to said electric load, comprising:
a voltage regulator with a feedback loop having a feedback input configured to receive a sensing voltage that is a function
of a supply current that flows through the electric load and for regulating, on the basis of the sensing voltage received,
said supply current; and

a resistive sensing element, operatively coupled to the feedback input, configured to receive the supply current and generate
said sensing voltage as a function of said supply current received;

a current transducer, of a resistive type, coupled to the feedback input; and
an auxiliary biasing circuit configured to receive said a.c. input voltage and to inject through said current transducer an
a.c. auxiliary biasing current that varies in a way inversely proportional to the a.c. input voltage.

US Pat. No. 9,244,067

BIOSENSOR

STMicroelectronics S.r.l....

1. A biosensor, comprising:
a flexible foil;
an electrode layer positioned on the flexible foil;
a first photo-definable hydrogel membrane arranged over the flexible foil and the electrode layer; and
a second photo-definable hydrogel membrane with an immobilized bio-recognition element positioned over and in contact with
the electrode layer, wherein:

the second photo-definable hydrogel membrane is arranged partly on and in direct contact with the first photo-definable hydrogel
membrane and partly on and in direct contact with the electrode layer; and

the second photo-definable hydrogel membrane contacts the electrode layer in a region where an opening in the first photo-definable
hydrogel membrane exposes the electrode layer.

US Pat. No. 9,165,237

SIM CARD ADAPTER

STMICROELECTRONICS S.R.L....

1. A subscriber identification module (SIM) card adapter assembly comprising:
a SIM card support comprising a first portion having a first thickness, and a second portion having a second thickness greater
than the first thickness;

a SIM card removably attached to the first portion, with the SIM card configured to be received by a SIM slot having a first
size; and

at least one SIM card adapter removably attached to the second portion, with the at least one SIM card adapter configured
to be received by a SIM slot having a second size different from the first size, and with the at least one SIM card adapter
also configured to receive the SIM card so as to adapt the SIM card to the second size SIM slot.

US Pat. No. 9,146,854

RESTORING STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD

STMicroelectronics Intern...

1. A method, comprising:
detecting a plurality of conflicting physical memory blocks for a corrupted logical memory block using a plurality of validity
indexes, each index being associated with at least one physical memory block and indicating the number of valid sectors of
the corrupted logical memory block stored in the at least one respective physical memory block;

selecting one of the physical memory blocks by comparing the validity indexes;
discarding data stored in each of the non-selected conflicting physical memory blocks;
selecting physical memory sectors in the selected physical memory block using a completion flag stored for each physical memory
sector, the completion flag including a plurality of bits having a first value indicating data of a logical memory sector
was properly stored in the physical memory sector, a second value indicating data of the physical memory sector has been erased,
and a plurality of additional values different than the first or second values where each of these additional values indicates
data was not properly stored in the corresponding physical memory sector; and

providing data for a logical memory sector of the logical memory block from the selected physical memory sector.

US Pat. No. 9,730,285

ELECTRONIC CIRCUIT FOR DRIVING LED STRINGS INCLUDING A PLURALITY OF REGULATION MODULES WHICH FUNCTION IN SEQUENCE

STMicroelectronics S.r.l....

1. An electronic circuit for driving a plurality of LED strings connected in a cascade, each LED string including an anode
terminal and a cathode terminal, comprising:
a plurality of regulation modules, wherein each regulation module is configured to be electrically coupled, in use, to the
cathode terminal of a corresponding LED string, and each regulation module further configured to be electrically coupled to
receive a reference voltage in phase with a rectified mains voltage and having an amplitude smaller than an amplitude of said
rectified mains voltage;

a reference circuit comprising:
a voltage divider configured to generate a reduced voltage as a function of said rectified mains voltage;
a peak-detector circuit configured to generate a peak voltage proportional to the peak value of said reduced voltage; and
a circuit configured to generate said reference voltage so that it is proportional to a ratio between the reduced voltage
and the peak voltage; and

wherein said regulation modules are configured to execute in turn a current-regulation phase, with the current-regulation
phases of said regulation modules occurring in sequence as a function of a trend of the reference voltage; and

wherein each regulation module is configured so that, when said regulation module executes the current-regulation phase, current
that flows in the corresponding LED string and in the previous LED strings is regulated so that it is proportional to the
reference voltage.

US Pat. No. 9,389,979

DEBUG SYSTEM, AND RELATED INTEGRATED CIRCUIT AND METHOD

STMICROELECTRONICS (GRENO...

1. A system, comprising:
a processor;
a plurality of circuits;
an interconnection network coupling the processor and the plurality of circuits, wherein to each circuit is associated a respective
communication interface configured to exchange data between the respective plurality of circuits and the interconnection network;
and

a debug unit associated with each communication interface, wherein each debug unit is configurable as:
a data-insertion point, wherein said debug unit transmits data via the respective communication interface to said interconnection
network, and wherein a destination for the transmission of said data is configurable, or

a data-reception point, wherein said debug unit receives data via the respective communication interface from said interconnection
network, wherein each debug unit includes at least one of:

a first transmission module configured to receive from said processor a personalized traffic profile, and configured to transmit
said personalized traffic profile via the respective communication interface to said interconnection network; and

a second transmission module configured to receive from said processor a selection request or a configuration request of a
predefined traffic profile, and configured to transmit said predefined traffic profile via the respective communication interface
to said interconnection network.

US Pat. No. 9,306,029

ELECTRONIC DEVICE COMPRISING CONDUCTIVE REGIONS AND DUMMY REGIONS

STMICROELECTRONICS S.R.L....

1. A power electronic device integrated in a chip of semiconductor material of a first type of conductivity, comprising:
an epitaxial region of a second type of conductivity extending into the chip from a front surface of the chip, a portion of
the chip between a rear surface of the chip opposite the front surface and the epitaxial region defining a collector region,

a gate region of conductive material in a trench extending into the epitaxial region from the front surface,
an emitter region extending into the epitaxial region from the front surface at a first side of said trench, said emitter
region comprising a body region of the first type of conductivity extending into the epitaxial region from the front surface,
and a source region of the second type of conductivity extending into the body region from the front surface at said trench,
and

a dummy emitter region of the first type of conductivity extending into the epitaxial region from the front surface at a second
side of said trench opposite said first side, said dummy emitter region lacking of said source region,

wherein said gate region extends along a first wall of the trench facing the emitter region, and
wherein a dummy gate region is formed in said trench, said dummy gate region being electrically isolated from said gate region
and extending along a second wall of the trench opposite said first wall.

US Pat. No. 9,224,694

TRACEABLE INTEGRATED CIRCUITS AND PRODUCTION METHOD THEREOF

STMicroelectronics S.r.l....

1. An integrated circuit, comprising:
a surface area delimited by edges;
a functional region for implementing specific functionalities of the integrated circuit;
at least one seal ring spaced apart from the edges and disposed around the functional region, wherein the at least one seal
ring comprises a metal layer having a thickness, an inner perimeter edge, and an outer perimeter edge; and

at least one marker indicative of information of the integrated circuit, wherein said at least one marker comprises at least
one removed portion in a top surface of said metal layer of the respective seal ring, the at least one marker visible from
outside of the integrated circuit, the at least one removed portion forming a groove having a depth that is less than said
thickness, and the groove is positioned in between and away from the inner perimeter edge and the outer perimeter edge.

US Pat. No. 9,279,867

BIASING CIRCUIT FOR A MAGNETIC FIELD SENSOR, AND CORRESPONDING BIASING METHOD

STMicroelectronics S.r.l....

1. A circuit, comprising:
output circuitry configured to couple to a magnetic-field sensor that includes a first detection structure configured to detect
a first directional component of an external magnetic field and a second detection structure configured to detect a second
directional component of said external magnetic field; and

a biasing circuit configured to electrically supply said first detection structure during a first biasing time interval and
to electrically supply said second detection structure during a second biasing time interval, the first and second bias time
intervals being at least partially distinct from one another in that the bias circuit is configured to electrically supply
said first detection structure without electrically supplying said second detection structure during at least a portion of
the first bias time interval and is configured to electrically supply said second detection structure without electrically
supplying said first detection structure during at least a portion of the second bias time interval.

US Pat. No. 9,202,002

SYSTEM FOR DESIGNING NETWORK ON CHIP INTERCONNECT ARRANGEMENTS

STMICROELECTRONICS (GRENO...

1. A system to design Network-on-Chip interconnect arrangements, comprising:
a Network-on-Chip backbone with a plurality of backbone ports;
a memory to store a source map of said Network-on-Chip backbone, the source map having information to route response transactions
from a slave IP core to a master IP core; and

a set of functional clusters of aggregated IP cores, each IP core providing a set of System-on-Chip functions, each functional
cluster in said set of functional clusters including a sub-network attachable to any of said backbone ports and attachable
to any other functional cluster in said set of functional clusters, the attachment made independent of the source map of said
Network-on-Chip backbone.

US Pat. No. 9,299,873

AVALANCHE PHOTODIODE OPERATING IN GEIGER MODE INCLUDING A STRUCTURE FOR ELECTRO-OPTICAL CONFINEMENT FOR CROSSTALK REDUCTION, AND ARRAY OF PHOTODIODES

STMicroelectronics S.r.l....

1. An avalanche photodiode, comprising:
a body of semiconductor material having a first surface and a second surface, said body including:
a cathode region of a first type of conductivity, forming the first and second surfaces; and
an anode region of a second type of conductivity, extending within the cathode region and contacting the cathode region along
an interface;

a lateral insulating region extending through the body starting from the first surface and surrounding the anode region and
at least part of the cathode region, said lateral insulating region comprising:

a barrier region; and
an insulating region which surrounds the barrier region; and
wherein the cathode region forms an optical guide of a planar type comprising a core region which is arranged between the
interface and the second surface and which extends between a minimum depth and a maximum depth and is designed to guide photons;

wherein the barrier region extends with a thickness at least equal to said maximum depth so as to surround the core region
laterally, the barrier region configured to prevent propagation beyond the barrier region of at least part of the photons
coming, in use, from the core region and impinging upon the barrier region;

wherein the core region forms an electrical-confinement region for minority carriers generated within the core region.

US Pat. No. 9,234,755

MICROELECTROMECHANICAL GYROSCOPE WITH CALIBRATED SYNCHRONIZATION OF ACTUATION AND METHOD FOR ACTUATING A MICROELECTROMECHANICAL GYROSCOPE

STMicroelectronics S.r.l....

1. A microelectromechanical gyroscope comprising:
a body;
a driving mass movable with respect to the body with a first degree of freedom;
a sensing mass mechanically coupled to the driving mass and movable with respect to the driving mass with a second degree
of freedom;

a driving device configured to maintain the driving mass in oscillation according to a driving frequency;
an oscillator configured to output a first clock signal having a frequency that is substantially equal to an integer multiple
of the driving frequency; and

a reading device coupled to the sensing mass and the oscillator and configured to sense movement of the sensing mass based
on the first clock signal.

US Pat. No. 9,258,139

METHOD FOR REGULATING DATA TRANSMISSION OVER A COMMUNICATION CHANNEL, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT

STMICROELECTRONICS S.R.L....

1. A method of regulating transmission of data frames over a channel in a communications network, wherein the transmission
is on a slotted time base and the method includes:
evaluating, by at least one node in the network having a frame available for transmission, whether the channel is available
for transmission based upon an initially synchronized slotted time base; and

if the evaluation indicates that the channel is available for transmission, transmitting the available frame on the channel;
and

if the evaluation indicates that the channel is unavailable for transmission due to a frame being transmitted over the channel
at a certain time and having a certain time length, re-synchronizing the slotted time base of the at least one node in the
network as a function of the frame being transmitted by identifying as a function of the certain time length a delay interval
to evaluate again at a subsequent time whether the channel is available for transmission of the available frame.

US Pat. No. 9,257,499

CONNECTION STRUCTURE FOR AN INTEGRATED CIRCUIT WITH CAPACITIVE FUNCTION

STMicroelectronics S.r.l....

1. A terminal structure for an integrated circuit chip, comprising:
a connection pad within the integrated circuit chip and forming an electrode of a first capacitor, wherein at least a portion
of an upper surface of the connection pad is exposed through an opening of the integrated circuit chip, said exposed portion
of the upper surface configured for making an electrical connection outside of the integrated circuit chip; and

a first conductor disposed within the integrated circuit chip and forming another electrode of the first capacitor that is
directly connected to a ground of the integrated circuit chip;

wherein the opening for the exposed portion of the connection pad and the first conductor are vertically aligned with each
other in a direction perpendicular to said upper surface;

a mechanical reinforcement structure comprising a plurality of first stacks of at least two vias and two metal lines that
are electrically connected to, and extend perpendicularly from, a bottom surface of the connection pad; and

a plurality of second stacks of at least two vias and two metal lines that are electrically connected to, and extend perpendicularly
from, an upper surface of the first conductor;

wherein at least one of the second stacks is positioned in a gap between two of the first stacks and adjacent to the connection
pad.

US Pat. No. 9,234,911

SENSOR DEVICE PROVIDED WITH A CIRCUIT FOR DETECTION OF SINGLE OR MULTIPLE EVENTS FOR GENERATING CORRESPONDING INTERRUPT SIGNALS

STMICROELECTRONICS S.R.L....

1. A sensor device, comprising:
a sensing structure to generate a motion-based detection signal; and
a dedicated integrated circuit coupled to the sensing structure, the dedicated integrated circuit configured to trigger an
interrupt in response to the motion-based detection signal changing within a predetermined time interval of the motion-based
detection signal, wherein the sensing structure and the dedicated integrated circuit are formed on a same die.

US Pat. No. 9,231,794

METHOD AND APPARATUS FOR MULTIPLE ANTENNA COMMUNICATIONS, COMPUTER PROGRAM PRODUCT THEREFOR

STMicroelectronics S.r.l....

1. A method, comprising:
receiving at a receiver a transmitted sequence of digitally modulated symbols, each symbol of the transmitted sequence originating
from a respective one of a number of multiple transmit sources;

processing equations of a complex-domain representation of a system through which the transmitted sequence propagates to obtain
a triangular matrix; and

performing, at the receiver, at least one of: (i) hard-decision detection of the transmitted sequence and demapping of corresponding
bits based on a reduced-complexity parallel search of a subset of all possible values of the transmitted sequence, the reduced-complexity
parallel search based on the triangular matrix, and (ii) generation of bit soft-output values based on the reduced-complexity
parallel search, a number of values in the subset being less than or equal to a product of factors, one of the factors being
equal to the number of multiple transmit sources; and wherein the reduced-complexity parallel search comprises solving a minimization
problem using values of a candidate sequence, the values of the candidate sequence obtained by:

identifying a set of possible values for the complex values of one or more reference transmitted complex symbols, the possible
values representing candidate values; and

obtaining the complex values of one or more remaining symbols through spatial-decisions feedback equalization starting from
each candidate value of the one or more reference symbols.

US Pat. No. 9,357,635

MICROFLUIDIC DELIVERY MEMBER WITH FILTER AND METHOD OF FORMING SAME

STMicroelectronics S.r.l....

1. A method comprising:
applying adhesive material to a first surface of a printed circuit board strip;
securing a plurality of filters to the first surface of the printed circuit board strip using the adhesive material, the plurality
of filters covering a plurality of through holes, respectively, in the printed circuit board;

applying adhesive material to a second surface of the printed circuit board strip; and
securing a plurality of semiconductor dice to the second surface of the printed circuit board strip, the plurality of semiconductor
dice covering the plurality of through holes, respectively, the plurality of semiconductor dice including an inlet path in
fluid communication with the plurality of through holes, respectively, and having nozzles for expelling a fluid.

US Pat. No. 9,072,139

CURRENT DRIVER FOR LED DIODES

STMicroelectronics S.r.l....

1. A current driver for an LED diode having a first terminal coupled to a supply node and having a second terminal, comprising:
a first series connection of a first transistor and a first resistance,
a second series connection of a second transistor and a second resistance,
said first and second series connections being arranged in parallel to each other and directly connected between said second
terminal of said LED diode and a voltage reference node,

an operational amplifier, and
a switch device driven by a clock signal and able to apply at a non-inverting input terminal and inverting input terminal
of the operational amplifier alternately a reference voltage and a voltage across the first resistance or the voltage across
the second resistance according to a half-period of the clock signal,

said switch device configured to apply an output signal of the operational amplifier to the first and second transistor according
to the half-period of the clock signal,

a storage element arranged to maintain turned on the first and second transistors when not driven by the output signal of
the operational amplifier.

US Pat. No. 9,404,951

METHOD OF DISCRIMINATION OF A DEVICE AS POWERABLE THROUGH A LAN LINE AND DEVICE FOR ESTIMATING ELECTRIC PARAMETERS OF A LAN LINE

STMICROELECTRONICS S.R.L....

1. A method of recognizing a device as being powerable through a local area network (LAN) line coupled thereto based upon
electrical parameters seen from first and second terminals of the LAN line comprising:
applying a first voltage across the first and second terminals for a first time interval and sensing a first steady-state
current;

applying a second voltage different than the first voltage across the first and second terminals for a second time interval
and sensing a second steady-state current;

estimating a resistance of the LAN line based upon the first and second voltages, and the first and second steady-state currents;
and

switching a supply voltage of the LAN line from the second voltage to a third voltage and sensing a third steady-state current;
estimating a capacitance of the LAN line seen from the first and second terminals, based upon the third steady-state current
failing to reach a threshold, by at least sensing a duration of a time interval starting from the switching during which the
third steady-state current is smaller than the first steady-state current, and estimating the capacitance based upon the time
interval, the resistance of the LAN line, a voltage drop across a load coupled to the LAN line, and the second and third voltages;
and

recognizing the device as being powerable through the LAN line based upon the resistance of the LAN line, the capacitance
of the LAN line, and the voltage drop across the load coupled to the LAN line.

US Pat. No. 9,368,209

EMBEDDED NON-VOLATILE MEMORY WITH SINGLE POLYSILICON LAYER MEMORY CELLS PROGRAMMABLE THROUGH CHANNEL HOT ELECTRONS AND ERASABLE THROUGH FOWLER-NORDHEIM TUNNELING

STMICROELECTRONICS S.R.L....

1. A non-volatile memory integrated in a semiconductor material chip, the non-volatile memory comprising:
a plurality of memory cells arranged in rows and columns, each memory cell comprising
a program/read portion,
an erase portion, and
an electrically floating layer comprising conductive material and coupling the program/read portion and the erase portion
to define a first capacitive coupling with the program/read portion, and a second capacitive coupling with the erase portion,

the program/read portion of each memory cell being formed in the semiconductor material chip in a first well of semiconductor
material having a doping of a first type, the erase portion being formed in the semiconductor material chip in a second well
of semiconductor material having a doping of a second type,

the program/read portion being configured to be traversed by an electric current indicative of a logic value stored in a given
memory cell during a read operation of the given memory cell,

the first capacitive coupling defining a first capacitance greater than a second capacitance defined by the second capacitive
coupling, the erase portion being configured to be traversed by an electric current configured to extract charge carriers
from the electrically floating layer to store a first logic value in the given memory cell,

the program/read portion being further configured to be traversed by an electric current configured to inject charge carriers
in the electrically floating layer to store a second logic value, respectively, in the given memory cell.

US Pat. No. 9,257,550

INTEGRATED ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING THEREOF

STMICROELECTRONICS S.R.L....

1. A method for making a semiconductor device comprising:
providing a first semiconductor layer having a first bandgap;
forming a second semiconductor layer over the first semiconductor layer and having a second bandgap that is wider than the
first bandgap, the second semiconductor layer comprising in stacked relation a first buffer semiconductor layer having a first
thickness, a second buffer semiconductor layer having the first thickness, and a drift semiconductor layer having a second
thickness;

forming a third semiconductor layer over the second semiconductor layer and having the first bandgap;
forming a trench in the third semiconductor layer defining first and second opposing walls;
forming a P+ type first semiconductor region spaced from the first wall and extending from a bottom surface of the third semiconductor
layer into the second semiconductor layer a first depth; and

forming a P+ type second semiconductor region spaced from the second wall and extending from the bottom surface of the third
semiconductor layer into the second semiconductor layer the first depth.

US Pat. No. 9,257,996

OSCILLATOR CIRCUITS AND METHODS TO COMPENSATE FREQUENCY PULLING

STMICROELECTRONICS S.R.L....

1. An oscillator circuit comprising:
a local oscillator configured to generate a carrier signal having a tunable frequency;
a first modulator and a power amplifier coupled to the local oscillator and configured to generate an output signal, the first
modulator configured to be activated from a first modulating signal alternatively defining ON and OFF states of the first
modulator;

an estimator unit configured to receive the carrier signal during a time window and to detect an estimated frequency variation
of the carrier signal during the ON and OFF states of the first modulator; and

a compensation unit coupled to the local oscillator and comprising a second modulator configured to generate a compensation
signal for tuning the tunable frequency, the compensation signal being related to the estimated frequency variation based
upon a second modulating signal different than the first modulating signal.

US Pat. No. 9,256,027

INTEGRATED OPTOELECTRONIC DEVICE AND SYSTEM WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF

STMicroelectronics S.r.l....

1. An integrated optoelectronic device, comprising:
a body of semiconductor material having formed inside at least a first optoelectronic component that is one of a detector
and an emitter;

an optical path integrally formed in the body of semiconductor material and traversing the body and extending between a first
surface and a second surface;

wherein the first optoelectronic component is optically coupled through the optical path to a first transmission medium and
a second transmission medium arranged, respectively, above and underneath the first and second surfaces; and

wherein the integrated optoelectronic device further comprises a top region, arranged on top of the body and forming the first
surface, the body being delimited by the second surface and by a main surface, the main surface being arranged between the
first and second surfaces; and wherein the optical path is formed by a first confinement region and a second confinement region,
the first confinement region extending within the top region, starting from the first surface, the second confinement region
extending within the body, starting from the second surface; and wherein the first confinement region is surrounded laterally
by a first lateral region, which has a refractive index less than the refractive index of the first confinement region so
that the first confinement region and the first lateral region form a first coupling waveguide; and wherein the second confinement
region is surrounded laterally by a second lateral region, which has a refractive index less than the refractive index of
the second confinement region so that the second confinement region and the second lateral region form a second coupling waveguide.

US Pat. No. 9,276,149

THIN FILM SOLAR CELL MODULE INCLUDING SERIES-CONNECTED CELLS FORMED ON A FLEXIBLE SUBSTRATE BY USING LITHOGRAPHY

STMICROELECTRONICS S.R.L....

1. A method of forming a solar module comprising:
forming a rear side metallization layer on an insulating substrate;
forming at least one first isolation trench in the rear side metallization layer;
forming a semiconductor junction layer on the rear side metallization layer; forming at least one second isolation trench
on the semiconductor junction layer and at least one contact trench in the rear side metallization layer and the semiconductor
junction layer so as to provide laterally isolated semiconductor junction layer regions, with the contact trench having a
width different from a width of the at least one first and second isolation trenches;

forming a transparent front side metallization layer on the semiconductor junction layer and in the at least one contact trench;
and

patterning the front side metallization layer so as to form series-connected solar cells based on the laterally isolated semiconductor
junction layer regions.

US Pat. No. 9,257,989

ELECTRONIC DEVICE FOR IMPLEMENTING DIGITAL FUNCTIONS THROUGH MOLECULAR FUNCTIONAL ELEMENTS

STMicroelectronics S.r.l....

1. An electronic device for implementing digital functions comprising:
an interposing region that includes a first dielectric region; and
a first electrode region and a second electrode region separated from each other by the interposing region, wherein said first
and second electrode regions include a first electrode and a second electrode, respectively, that are configured to generate
an electrode electric field in the interposing region depending on an electric potential difference to be applied to the first
and second electrodes, wherein:

the interposing region includes a molecular layer including a plurality of molecules, each configured to be responsive to
a sensed electric field and assume one or more electric states, in a controllable manner, according to the sensed electric
field; and

said first dielectric region has a spatially variable dielectric profile that is configured to define a corresponding field
profile of said electrode electric field and to spatially modulate said sensed electric field at the molecular layer.

US Pat. No. 9,178,776

ARRANGEMENT AND METHOD

STMICROELECTRONICS (GRENO...

1. A method to manage bandwidth usage on an interconnect, comprising:
providing at least one target bandwidth for traffic associated with a traffic initiator;
measuring a served bandwidth on said interconnect;
resetting said measuring of served bandwidth in response to an occurrence of an event; and
issuing said traffic from said traffic initiator under control of a processor, wherein said traffic includes at least one
of video decoding traffic and graphics traffic.

US Pat. No. 9,356,535

CONTROL METHOD FOR RECTIFIER OF SWITCHING CONVERTERS

STMicroelectronics S.r.l....

1. A control device, comprising:
a driver circuit configured to generate a first control signal configured to turn on and off a first transistor of a rectifier
of a switching converter; and

a measuring circuit configured to measure a conduction time of a body diode of the transistor during each of a plurality of
switching cycles of the converter, the measuring circuit being configured to cycle by cycle determine whether the measured
conduction time is greater or less than a first threshold value, wherein the driver circuit is configured to:

delay an off time instant of the transistor by a first fixed quantity in a next switching cycle when the measured conduction
time is greater than the first threshold value, cycle by cycle until the measured conduction time is less than the first threshold
value and comprised between said first threshold value and a second threshold value,

delay the off time instant of the transistor by a second fixed quantity in the next switching cycle when the measured conduction
time is lower than the first threshold value and comprised between said first threshold value and the second threshold value,
cycle by cycle until the measured conduction time is lower than the second threshold value, said second fixed quantity being
less than the first fixed quantity, and

advance the off time instant of the transistor by said second fixed quantity in the next switching cycle.

US Pat. No. 9,356,587

HIGH VOLTAGE COMPARISON CIRCUIT

STMicroelectronics S.r.l....

1. A high voltage comparison circuit, comprising:
an input stage arranged between a supply voltage node and a first voltage reference node, said input stage configured to receive
an input voltage signal and comprising a voltage comparator configured to provide an intermediate signal at an output terminal
of the input stage as a result of a comparison between the input voltage signal and a first voltage at said first voltage
reference node; and

an output stage arranged between said supply voltage node and a second voltage reference node configured to receive a second
voltage different from said first voltage, said output stage configured to receive said intermediate signal and to provide
an output voltage signal which is in response to said intermediate signal,

wherein said voltage comparator comprises:
a first-type MOSFET transistor and a second n-type MOSFET transistor having their gate terminals connected together to a common-gate
node, said second n-type MOSFET transistor being configured as a diode, and

a first resistor and a second resistor each connected in series with a source terminal of the first and second n-type MOSFET
transistors, respectively, and

wherein said input stage comprises:
a voltage buffer through which the input voltage signal is received, and
a pass-gate configured to receive the input voltage signal before the input signal is received by said voltage buffer, wherein
said pass-gate comprises an n-type MOSFET transistor having a gate terminal connected to the common-gate node.

US Pat. No. 9,232,554

METHOD AND SYSTEM FOR ENABLING MULTI-CHANNEL DIRECT LINK CONNECTION IN A COMMUNICATION NETWORK, RELATED NETWORK AND COMPUTER PROGRAM PRODUCT

STMICROELECTRONICS S.R.L....

1. A method of operating a basic service set of a wireless communication network comprising an access point and a plurality
of stations, the method comprising:
sending periodic information arranged in time frames to said plurality of stations by said access point;
communicating by said plurality of stations in a first mode through said access point;
communicating directly between stations in a second mode, without using said access point;
partitioning said time frames into a first time interval wherein said plurality of stations communicate in said first mode
over a first channel, a second time interval wherein said plurality of stations communicate in said second mode over a second
channel, and a third time interval wherein said plurality of stations communicate in either said first or second mode; and

negotiating communication in said second mode between a transmitter station and a receiver station in said plurality of stations
including allocating direct link transmission opportunities, in the form of bounded time intervals defined by a starting time
and a maximum duration, in which said transmitter station is allowed to communicate in the second mode with said receiver
station, wherein the maximum duration is defined based upon application quality of service requirements including data rate,
data unit size, overhead and at least one of physical rate and link capacity.

US Pat. No. 9,286,160

SYSTEM AND METHOD FOR PHASE CHANGE MEMORY WITH ERASE FLAG CELLS

STMicroelectronics S.R.L....

1. A memory array comprising:
a plurality of memory cells arranged in groups, each memory cell comprising a phase change memory cell;
a plurality of erase flag cells, wherein each erase flag cell of the plurality of erase flag cells is associated with a group
of the memory cells and indicates whether the group of the memory cells is to be treated as valid or erased; and

a memory control circuit configured to set an erase flag cell to an erased value during an erase operation on the group of
the memory cells associated with the erase flag cell without modifying the plurality of memory cells of the group of the memory
cells associated with the erase flag cell.

US Pat. No. 9,389,077

ACCELERATION AND ANGULAR VELOCITY RESONANT DETECTION INTEGRATED STRUCTURE, AND RELATED MEMS SENSOR DEVICE

STMicroelectronics S.r.l....

1. An integrated detection structure comprising:
a substrate;
first elastic anchorage elements;
second elastic anchorage elements;
a first inertial mass suspended over the substrate in a plane and anchored to the substrate by the first elastic anchorage
elements;

a second inertial mass suspended over the substrate in the plane and anchored to the substrate by the second elastic anchorage
elements;

a first set of driving electrodes operatively coupled to each of said first and second inertial masses and configured to drive
the first and second inertial masses with driving movements, in opposite directions along a first axis of said plane; and

first, second, third, and fourth elastic supporting elements;
a first pair of first resonator elements elastically coupled to said first inertial mass by the first and second elastic supporting
elements, respectively, said first and second elastic supporting elements being configured to enable independent resonant
movements of the first resonator elements of the first pair with respect to each other;

a second pair of first resonator element elastically coupled to said second inertial mass by the third and fourth elastic
supporting elements, respectively, said third and fourth elastic supporting elements being configured to enable independent
resonant movements of the first resonator elements of the second pair with respect to each other; wherein:

said first elastic anchorage elements are configured to allow the first inertial mass to perform a first linear driving movement
along the first axis in said plane, allow a first detection movement of rotation about a first rotation axis parallel to a
second axis transverse to said first axis and in said plane as a function of a first angular velocity or a first linear acceleration
to be detected and cause corresponding variations of resonance frequency of said first pair first resonator elements; and

said second elastic anchorage elements are configured to allow the second inertial mass to perform a second linear driving
movement along the first axis in said plane, allow a second detection movement of rotation about a second rotation axis parallel
to the second axis in said plane as a function of the first angular velocity or the first linear acceleration to be detected
and cause a corresponding variations of resonance frequency of said second pair of first resonator elements.

US Pat. No. 9,159,425

NON-VOLATILE MEMORY WITH REDUCED SUB-THRESHOLD LEAKAGE DURING PROGRAM AND ERASE OPERATIONS

STMicroelectronics Intern...

1. A circuit, comprising:
a non-volatile memory cell including an NMOS select transistor and a floating gate transistor connected to the NMOS select
transistor in series between a bit line and a source line, the memory cell configurable for operation in a programming mode;
and

a selection circuit configured to drive a gate terminal of the NMOS select transistor with a negative bias voltage in response
to said memory cell being configured in programming mode to program a data value into said floating gate transistor while
said negative bias voltage produces both a negative gate-to-source voltage and a negative gate-to-well voltage on said NMOS
select transistor.

US Pat. No. 9,485,087

METHOD AND CIRCUIT FOR CRYPTOGRAPHIC OPERATION

Proton World Internationa...

1. A method, comprising:
receiving a plurality of binary input values;
performing, using cryptographic circuitry of a computing system, a cryptographic operation on the plurality of binary input
values, the performing the cryptographic operation including:

transforming said plurality of binary input values into a plurality of non-binary input digits of base r, where r is an integer
greater than 2 and not equal to a power of 2, and wherein the plurality of non-binary input digits comprises a first non-binary
input digit and a second non-binary input digit, each non-binary digit being represented by a plurality of bits with some
redundancy; and

performing a modulo r operation on each of the plurality of non-binary input digits to generate at least one output digit
of base r, by performing a first modulo r operation on the first non-binary input digit and a second modulo r operation on
the second non-binary input digit, the second modulo r operation being qualitatively different from the first modulo r operation;
and

extracting from said at least one output digit of base r a plurality of binary output values, wherein extracting the plurality
of binary output values comprises performing imbalance correction.

US Pat. No. 9,385,049

PROCESS FOR MANUFACTURING INTEGRATED DEVICE INCORPORATING LOW-VOLTAGE COMPONENTS AND POWER COMPONENTS

STMICROELECTRONICS S.R.L....

1. A process for manufacturing an integrated device, comprising:
forming a STI insulation structure in a semiconductor body that extends above a depressed first portion of the semiconductor
body and laterally delimits second portions of the semiconductor body projecting from the first portion, said STI insulation
structure having a sidewall with the second portions of the semiconductor body that is disposed at a first angle with respect
to a plane defined by a top surface of the second portions that is less than ninety degrees;

forming low-voltage CMOS components in the second portions;
forming an aperture in the STI insulation structure to expose a region of the depressed first portion of the semiconductor
body, said aperture having a sidewall that is disposed at a second angle with respect to the plane defined by the top surface
of the second portions that is less than the first angle, wherein the first angle is between eighty and ninety degrees, and
the second angle is between twenty and seventy degrees; and

forming a power component in said region of the depressed first portion of the semiconductor body exposed by the aperture;
wherein forming the power component comprises:
forming at least one conduction region in the region of the depressed first portion of the semiconductor body exposed by the
aperture; and

forming a conduction contact that is connected to the at least one conduction region and crosses the STI insulation structure
perpendicular to the top surface of the second portions of the semiconductor body.

US Pat. No. 9,327,964

METHOD FOR MANUFACTURING A DIE ASSEMBLY HAVING A SMALL THICKNESS AND DIE ASSEMBLY RELATING THERETO

STMicroelectronics S.r.l....

1. A die assembly comprising:
a first die including a semiconductor body and an integrated electronic circuit and having first and second sides that extend
between first and second surfaces;

a recess formed in the first surface of the first die;
a second die of semiconductor material bonded to the second surface of the first die, the second die not including electrical
functions and providing stiffening structural support to the first die;

a third die bonded to the first surface of the first die, the first die being arranged between the second and third dice,
the third die including a micro-electromechanical sensing structure; and

a molding compound coating the first and second sides of the first die.

US Pat. No. 9,321,628

MEMS DEVICE INCORPORATING A FLUIDIC PATH, AND MANUFACTURING PROCESS THEREOF

STMicroelectronics S.r.l....

1. A MEMS device comprising:
a first semiconductor die having a first face and a second face;
a membrane formed in or on the first semiconductor die and at the first face;
a cap coupled to the first face of the first semiconductor die with an inner surface of the cap facing and spaced apart from
the membrane by a space, the cap having an outer surface opposite the inner surface;

a support coupled to the first semiconductor die and facing the second face of the first semiconductor die;
packaging material enclosing the outer surface the cap and portions of the first semiconductor die; and
a fluidic path extending through the support and the first semiconductor die and fluidly coupling the membrane to an environment
outside of the MEMS device.

US Pat. No. 9,299,610

METHOD FOR MANUFACTURING A TRANSISTOR WITH SELF-ALIGNED TERMINAL CONTACTS

STMICROELECTRONICS S.R.L....

18. A method, comprising:
forming a first opening in an insulating region above a body region of a semiconductor substrate;
forming a source region in the body region through the first opening;
forming a second opening in the body region adjacent to the source region through the first opening;
forming a body-contact region in the body region through the second opening; and
forming a source-body contact in the second opening.

US Pat. No. 9,322,839

MAGNETIC INERTIAL SENSOR AND METHOD FOR OPERATING THE SAME

STMICROELECTRONICS S.R.L....

1. An inertial sensor, comprising:
a body of semiconductor material, having a first surface and a second surface, the body including:
an excitation coil;
a first sensing coil extending at a first distance from the excitation coil along a first axis;
a suspended mass including a magnetic-field concentrator, the suspended mass extending above the first surface and being magnetically
coupled to the excitation coil and to the first sensing coil, and configured to be displaced by way of inertia; and

a supply and sensing circuit electrically coupled to the excitation coil and to the first sensing coil, and configured to
generate a time-variable flow of electric current through the excitation coil to generate a magnetic field that, in use, interacts
with said magnetic-field concentrator to induce an electrical quantity in the first sensing coil, the supply and sensing circuit
being configured to measure a value of said electrical quantity induced in the first sensing coil to detect a quantity associated
with a displacement of the suspended mass, the supply and sensing circuit is further configured to:

acquire an effective frequency of variation in time of the flow of electric current and an effective wavelength associated
with said effective frequency;

measure an apparent frequency of variation in time of said electrical quantity induced in the first sensing coil and obtaining
an apparent wavelength associated to said apparent frequency;

compute, on the basis of the values of the effective wavelength and of the apparent wavelength, a value of velocity at which
the suspended mass moves; and

determine a time derivative of the value of velocity to obtain a value of acceleration of the suspended mass.

US Pat. No. 9,275,962

PROBE PAD WITH INDENTATION

STMicroelectronics S.r.l....

1. An integrated circuit, comprising:
a substrate; and
a conductive pad disposed over the substrate and including:
a first conductive layer having an indentation, and
a second conductive layer disposed over the first conductive layer and having an opening that is aligned with the indentation,
and

a third conductive layer disposed over the first and second conductive layers filling the indentation in the first conductive
layer and the opening in the second conductive layer, the third conductive layer being at least coplanar with a top surface
of the second conductive layer.

US Pat. No. 9,497,464

GOP-INDEPENDENT DYNAMIC BIT-RATE CONTROLLER

STMICROELECTRONICS INTERN...

1. A system comprising:
a user interface configured to receive one or more input parameters;
a bit-rate controller configured to regulate a bit-rate of an output bit-stream, the bit-rate controller comprising
a plurality of bit-rate modules configured to determine a quantization parameter based on a bit-estimate,
a control module configured to calculate a convergence period based on the received one or more input parameters and a frame
rate, wherein the calculated convergence period corresponds to a number of picture frames to converge the bit-rate of the
output bit-stream to a target bit-rate and the control module selects a bit rate module to allocate a number of bits to each
different type of picture frame in the calculated convergence period based on the type of each picture frame; and

an encoder configured to encode once per picture frame and for generating the output bit-stream using the quantization parameter
determined by the selected bit rate module.

US Pat. No. 9,362,142

FLIP-CHIP ELECTRONIC DEVICE AND PRODUCTION METHOD THEREOF

STMicroelectronics S.r.l....

1. A method for making a plurality of electronic devices, the method comprising:
fixing a plurality of chips of semiconductor material onto respective portions of a base plate of electrically conductive
material, each chip having a first surface with a first conduction terminal and a second surface opposite the first surface
that is coupled to the base plate;

fixing a first insulating tape of electrically insulating material to the first surface of each chip, the first insulating
tape including a first set of one or more through-holes that expose portions of the first surface of the chips, the first
insulating tape over sections of the base plate that are not covered by the chips and including a second set of one or more
through-holes exposing portions of the sections of the base plate, wherein the first and second sets of the one or more through-holes
are open at completion of the fixing step; and

after the fixing step, forming a first electrical contact on the first conductive terminal of the chips through the first
set of the through-holes and a second electrical contact on the base plate through the second set of the through-holes.

US Pat. No. 9,317,925

DEPTH MAP GENERATION METHOD, RELATED SYSTEM AND COMPUTER PROGRAM PRODUCT

STMicroelectronics S.r.l....

1. A method, comprising:
detecting contours in a first image;
determining at least one sampling step size based on the detected contours;
selecting a plurality of reference pixels in said first image based on the detected contours and the at least one sampling
step size;

associating with each reference pixel a respective pixel in a second image;
determining a disparity between each reference pixel and the respective associated pixel in said second image; and
determining for each reference pixel a depth value as a function of the respective disparity.

US Pat. No. 9,239,583

CIRCUIT FOR GENERATION OF AN ELECTRIC CURRENT WITH A CONFIGURABLE VALUE

STMICROELECTRONICS S.R.L....

1. A circuit for generation of an output current for enabling electrical testing of at least one operating stage comprising:
an input terminal configured to receive a reference current;
an output terminal configured to supply the output current;
a first current mirror coupled between the input terminal and a first internal node;
a second current mirror coupled between the first internal node and a second internal node, and comprising a first PMOS transistor
and a second PMOS transistor;

a first reference resistor element coupled to the second internal node and having a first value of resistance;
a first buffer coupled between the second internal node and a third internal node;
a first reference transistor coupled to a third internal node, and having a control terminal coupled to an output of the first
buffer;

a resistive divider stage coupled to the third internal node and configured to receive a configuration signal;
a second buffer coupled between the resistive divider stage and a fourth internal node;
a second reference resistor element coupled to the fourth internal node and having a second value of resistance, wherein the
second value of resistance being matched to the first value by a ratio based upon the first value of resistance and a matching
factor; and

a second reference transistor coupled between the fourth internal node and said output terminal, and having a control terminal
coupled to an output of the second buffer, wherein the second reference transistor being matched to the second PMOS transistor
by a ratio based upon a size of the second PMOS transistor and the matching factor;

wherein the matching factor is greater than one.

US Pat. No. 9,212,910

MICROELECTROMECHANICAL GYROSCOPE WITH SELF-CALIBRATION FUNCTION AND METHOD OF CALIBRATING A MICROELECTROMECHANICAL GYROSCOPE

STMICROELECTRONICS S.R.L....

1. A microelectromechanical gyroscope, comprising:
a supporting structure having first and second sensing terminals;
a capacitive coupling coupled to the sensing terminals;
a sensing mass coupled to the supporting structure through the capacitive coupling, the sensing mass being movable with respect
to the supporting structure according to a first degree of freedom and being movable with respect to the supporting structure
according to a second degree of freedom in response to rotations of the supporting structure about an axis;

driving components configured to maintain the sensing mass in oscillation according to the first degree of freedom;
a reading interface connected to the sensing terminals and configured to sense transduction signals indicative of the capacitance
between the sensing mass and the supporting structure; and

first and second capacitive compensation modules connected to the first and second sensing terminals, respectively, and configured
to compensate for a capacitance of the capacitive coupling between the sensing mass and the supporting structure, the first
capacitive compensation module having a first variable capacitance coupled to the first sensing terminal, the second capacitive
compensation module having a second variable capacitance coupled to the second sensing terminal, and the first and second
variable capacitances being distinct from the capacitance of the capacitive coupling between the sensing mass and the supporting
structure; and

calibration components coupled to the reading interface and configured to detect systematic errors from the transduction signals
and to adjust the first and second variable capacitances of the first and second capacitive compensation modules as a function
of the transduction signals to mitigate the systematic errors.

US Pat. No. 9,162,876

PROCESS FOR MANUFACTURING A MEMBRANE MICROELECTROMECHANICAL DEVICE, AND MEMBRANE MICROELECTROMECHANICAL DEVICE

STMicroelectronics S.r.l....

1. A process comprising:
forming a microelectromechanical device including:
forming a structural layer on a single dielectric layer on a semiconductor substrate, the structural layer having an inner
portion and an outer portion, the dielectric layer having a sacrificial portion and a support portion;

opening a plurality of trenches through the inner portion of the structural layer, the plurality of trenches exposing the
sacrificial portion of the dielectric layer;

selectively removing the sacrificial portion of the dielectric layer through the plurality of trenches so as to cause the
inner portion of the structural layer to be suspended, thereby forming a membrane the support portion of the dielectric layer
remaining between the outer portion of the structural layer and the semiconductor substrate; and

closing the plurality of trenches, the closing the plurality of trenches including exposing the structural layer to an annealing
temperature for a time interval.

US Pat. No. 9,082,476

DATA ACCESSING METHOD TO BOOST PERFORMANCE OF FIR OPERATION ON BALANCED THROUGHPUT DATA-PATH ARCHITECTURE

STMICROELECTRONICS S.R.L....

1. An apparatus for performing signal processing operations comprising:
a system memory storage unit;
an Address Generator (AG) unit functionally connected to the system memory storage unit and operable to receive data from,
and write data to, the system memory storage unit over a data bus that has a plurality of data widths;

a register memory array functionally connected to the AG unit and operable to receive data from, and write data to, the AG
unit, wherein the data in the register memory array is stored using a register file system;

a multiply-accumulate (MAC) execution unit functionally connected to the register file system and operable to receive data
from and write data to the register memory array, and which multiplies and adds pairs of data values and writes the sum to
a location in the register memory array;

wherein the register file system is organized in a hierarchical scheme for the individual register memory locations, in which
pairs of individual register memory locations are organized into respective paired register (PR) units, and pairs of PR units
are organized into respective group register (GR) units; and

wherein the AG unit uses a misaligned address placement (MAP) system to place data from the system memory storage unit into
the register file system by aligning any misaligned address with a middle point of a group register unit.

US Pat. No. 9,430,328

ERROR CORRECTION IN MEMORY DEVICES BY MULTIPLE READINGS WITH DIFFERENT REFERENCES

STMICROELECTRONICS S.R.L....

1. A method for reading a memory device comprising a plurality of memory cells, the method comprising:
receiving a request of reading a selected data word associated with a selected code word comprising a plurality of logic values
stored in at least one selected memory cell of the plurality of memory cells with an error correction code;

reading a first code word representing a first version of the selected code word by comparing a state of the at least one
selected memory cell with a first reference;

verifying the first code word according to the error correction code;
setting the selected code word according to the first code word in response to a positive verification of the first code word;
reading at least one second code word representing a second version of the selected code word by comparing the state of the
at least one selected memory cell with a second reference;

verifying the second code word according to the error correction code; and
setting the selected code word according to the second code word in response to a negative verification of the first code
word and to a positive verification of the second code word.

US Pat. No. 9,413,408

METHOD FOR PERSONALIZING SIM CARDS WITH A PRODUCTION MACHINE

STMICROELECTRONICS S.R.L....

1. A method for personalizing a subscriber identity module (SIM) card comprising:
loading the SIM card on a conveyor of a production machine;
programming the SIM card with the production machine by moving at least one head of the production machine to contact the
SIM card;

checking whether an intermediate result of the programming is either wrong or correct;
when the intermediate result is wrong, then
repositioning the SIM card on the conveyor after the production machine has contacted the SIM card for a first time in the
programming of the SIM card, the repositioning comprising moving the at least one head to disconnect and reconnect to the
SIM card for adjusting a contact therebetween,

reprogramming the SIM card before unloading from the conveyor and after the repositioning, and
repeating the checking of the intermediate result; and
when the intermediate result is correct after at least one of the programming and the reprogramming, unloading the programmed
SIM card from the conveyor.

US Pat. No. 9,331,151

METHOD FOR COUPLING A GRAPHENE LAYER AND A SUBSTRATE AND DEVICE COMPRISING THE GRAPHENE/SUBSTRATE STRUCTURE OBTAINED

STMicroelectronics S.r.l....

1. An electronic device comprising:
a substrate having at least one hydrophilic surface that includes hydroxyl and silanolic groups,
a graphene layer, and
elements or functional groups from a solvent selected from the group consisting of acetone, ethyl lactate, isopropyl alcohol,
methylethyl ketone, and mixtures thereof, located between said substrate and said graphene layer and integrated with the hydrophilic
surface to obtain a contact angle of the hydrophilic surface of about 40 degrees.

US Pat. No. 9,258,148

METHOD FOR CHANNEL ESTIMATION, RELATED CHANNEL ESTIMATOR, RECEIVER, AND COMPUTER PROGRAM PRODUCT

STMicroelectronics S.r.l....

1. A method, comprising:
receiving a signal over a channel having a number of paths;
generating first channel-estimation values in response to the signal;
generating each of multiple versions of second channel-estimation values in response to a respective one of the first channel-estimation
values, wherein generating each of multiple versions of second channel-estimation values includes,

generating one of the versions of second channel-estimation values in response to one of the first channel-estimation values;
generating each of one or more subsequent ones of the versions of the second channel-estimation values in response to a previous
version of the second channel-estimation values and a respective other one of the first channel-estimation values;

generating each of multiple path-number-determination values in response to a respective version of the second channel-estimation
values; and

determining the number of paths in response to the path-number-determination values; and
wherein generating the second channel-estimation values is adaptively performed as a function of the determined number of
paths.

US Pat. No. 9,062,343

INTEGRATED DEVICE FOR REAL TIME QUANTITATIVE PCR

STMicroelectronics S.r.l....

1. A method for real-time quantitative detection of a single target nucleic acid sequence, comprising:
introducing into a microwell a sample comprising a target nucleic acid sequence, magnetic primers, and a labelled probe;
performing one or more amplification cycles to form magnetic amplification products;
attracting the magnetic primers to a surface through a magnetic field and forming a multilayer including the magnetic amplification
products and the labelled probe hybridized thereto; and

quantitatively detecting the magnetic amplification products by measuring the labelled probe in the multilayer with a spatially
discriminating detection method during one or more of said amplification cycles using a spatially discriminating detection
device having a vertical resolution, and the multilayer has a thickness matched to the vertical resolution of the spatially
discriminating detection device.

US Pat. No. 9,321,269

METHOD FOR THE SURFACE TREATMENT OF A SEMICONDUCTOR SUBSTRATE

STMICROELECTRONICS S.R.L....

21. An integrated ink-jet printhead, comprising:
a body housing an ink chamber;
an inlet channel;
an outlet channel; and
a nozzle plate extending over at least a portion of the body, the nozzle plate having a surface comprising a semiconductor
material covered with an anti-wetting coating,

the anti-wetting coating provided as a monolayer of hydrocarbons having an inclined and orderly orientation, the monolayer
of hydrocarbons comprising unsaturated hydrocarbons having a backbone selected from one or more of alkenes and alkynes with
from eight to twenty carbon atoms, the monolayer of hydrocarbons bonded to the semiconductor material, bonds being fixed chemically
to the semiconductor material, provided as stable Si—C bonds, the anti-wetting coating confined to the nozzle plate without
interfering with the outlet channel or electrical connections integrated to the body.

US Pat. No. 9,209,763

CIRCUIT AND METHOD FOR ADJUSTING THE ELECTRIC POWER SUPPLY OF AN ENERGY-SCAVENGING SYSTEM

STMicroelectronics S.r.l....

1. A circuit, comprising:
a differentiator configured to receive a first electrical signal which is a time-variable signal and supply a second electrical
signal that is a time derivative of said first electrical signal;

a transconductance amplifier configured to receive the second electrical signal and generate a third electrical signal that
is a function of the second electrical signal and is amplified with respect to the second electrical signal;

a power supply network for the differentiator and transconductance amplifier configured to supply respective power supply
signals to the differentiator and transconductance amplifier; and

a driving circuit of the power supply network, configured to drive the power supply signals in response to one or more biasing
signals;

said third electrical signal being, at least in part, supplied to said driving circuit for use in driving the power supply
network so as to modulate an amplitude of at least one of the power supply signals.

US Pat. No. 9,083,536

METHOD OF MONITORING THE POWERING OF A REMOTE DEVICE THROUGH A LAN LINE AND RELATIVE CIRCUIT

STMICROELECTRONICS S.R.L....

1. A method of monitoring powering of a device through a local area network (LAN) connection comprising:
applying a time-varying voltage to a second terminal of the LAN connection through a de-coupling capacitor while powering
the device by applying a DC voltage to a first terminal of the device, with the time-varying voltage and the de-coupling capacitor
being connected in series, with a diode having an anode terminal coupled between the de-coupling capacitor and the second
terminal, and having a cathode terminal;

sensing a time-varying voltage on the second terminal caused by the applied time-varying voltage; and
continuing powering of the device with the DC voltage based upon at least one electric parameter of the sensed time-varying
voltage via a switch coupled in parallel to the de-coupling capacitor and the time-varying voltage generator when the switch
is in a closed position, with the switch being operated based on a below ground voltage being detected at the anode terminal
of the diode.

US Pat. No. 9,083,867

DEVICE FOR ASSIGNING A GEOGRAPHICAL POSITION TO A PICTURE

STMICROELECTRONICS S.R.L....

1. A device for assigning a geographical position to a picture comprising:
at least one integrated circuit (IC) chip comprising
a photo camera module configured to take the picture,
a positioning system module configured to identify geographical coordinates when the picture is taken,
a cryptographic module configured to sign the picture and the geographical coordinates, and
a memory configured to store the signed picture and the geographical coordinates as a certified geographical position of the
picture; and

a package configured to enclose said at least one IC chip, said package comprising a rigid enveloping layer configured to,
if said package is opened, break said at least one IC chip.

US Pat. No. 9,061,248

PROCESS FOR MANUFACTURING A MICROMECHANICAL STRUCTURE HAVING A BURIED AREA PROVIDED WITH A FILTER

STMicroelectronics S.r.l....

1. A process for manufacturing a micromechanical structure, comprising:
forming a buried cavity within a body of semiconductor material having a top surface, said buried cavity being separated from
said top surface by a first surface layer of said body; and

forming a first access duct configured to enable fluid communication between said buried cavity and an environment external
to said body;

forming an etching mask on said top surface at a first access area;
forming a second surface layer on said top surface and said etching mask;
removing by etching, at said first access area, a portion of said second surface layer, and an underlying portion of said
first surface layer not covered by said etching mask until said buried cavity is reached, said etching thus forming both said
first access duct and a filter element, set between said first access duct and said buried cavity and formed by a remaining
portion of said first surface layer covered by said etching mask.

US Pat. No. 9,432,041

METHOD OF CALIBRATING A THERMOMETER-CODE SAR A/D CONVERTER AND THERMOMETER-CODE SAR-A/D CONVERTER IMPLEMENTING SAID METHOD

STMICROELECTRONICS S.R.L....

1. A method of calibrating a thermometer-code successive approximation register analog-to-digital (SAR-A/D) converter comprising
an Nbit-bit digital-to-analog converter (DAC) for outputting an Nbit-bit output code, the DAC comprising a first subconverter having a plurality of NTh thermometer elements Tj and a second subconverter having a plurality of NBin binary-weighted elements, the plurality of thermometer elements Tj defining the MSB bits of the Nbit-bit code and the plurality of binary-weighted elements Nbin defining the LSB bits of the Nbit-bit output code, with the Nbit-bit output code being equal to the sum of NBitTh and NBitBin where NTh=2NBitTh and NBitBin is equal to NBin=NBitBin, the method of calibrating comprising:
determining an Integral Non-Linearity error value (?R) of an Rth thermometer-code level of the thermometer elements Tj according to the formula:


where:
Ej represents relative mismatch differences between the plurality of thermometer elements Tj and a reference thermometer element Tref selected from the plurality of thermometer elements Tj of the first subconverter;

minimizing a maximum of the error value ?R to obtain a minimized error value; and

generating the output code according to the minimized error.

US Pat. No. 9,385,011

APPARATUS FOR PROCESSING SEMICONDUCTOR WAFERS, IN PARTICULAR FOR CARRYING OUT A POLYMERS REMOVAL PROCESS STEP

STMICROELECTRONICS S.R.L....

1. An apparatus for processing semiconductor wafers, comprising:
an automatic handling system including a connector coupled to a support, the support housing a wafer carrier carrying semiconductor
wafers, the automatic handling system being configured to convey the support housing the wafer carrier;

a wet bench including a first processing tank, a second processing tank and a third processing tank, separated from one another,
and a cleaning and drying tank, the first, second, and third processing tanks being configured to store first, second, and
third chemicals, respectively, for processing wafers in the wafer carrier, the cleaning and drying tank being configured to
receive and process the connector and the support; and

a pair of tracks positioned inside said support and configured to enable said wafer carrier to slide along the pair of tracks.

US Pat. No. 9,255,782

MEMS DEVICE INCLUDING A MOBILE ELEMENT AND A RESISTIVE SENSOR, AND METHOD FOR GENERATING A SIGNAL INDICATING THE POSITION OF THE MOBILE ELEMENT

STMicroelectronics S.r.l....

25. A MEMS device, comprising:
a fixed supporting body;
a first deformable element and a second deformable element constrained to the fixed supporting body;
a mobile element interposed between, and connected to, said first and second deformable elements, the mobile element being
rotatable with respect to the fixed supporting body, with consequent deformation of the first and second deformable elements;

a generator configured to cause a current to flow through at least one of the first and second deformable elements, so as
to generate an electrical position signal proportional to at least one of a first resistance, of the first deformable element,
and a second resistance, of the second deformable element, said first and second resistances being, respectively, proportional
to deformations of the first and second deformable elements and indicative of an angular position of the mobile element;

an electrical actuation circuit configured to exert a torque on the mobile element as a function of the electrical position
signal;

wherein the fixed supporting body moreover forms a second stator subregion, and wherein the electrical actuation circuit is
moreover configured to apply the electrical driving signal also to the second stator subregion; and

wherein each of the first and second deformable elements has a first dimension, a second dimension and a third dimension,
measured, respectively, in a first direction, a second direction and a third direction that are mutually orthogonal, said
first dimension being greater than said second and third dimensions, said first and second stator subregions being arranged
in such a way that, when they receive the electrical driving signal, the mobile element rotates about an axis of rotation
parallel to the first direction.

US Pat. No. 9,235,797

ENHANCED IC CARD

STMICROELECTRONICS S.R.L....

1. An integrated circuit (IC) card comprising:
a substrate having opposing first and second surfaces;
a circuit carried by said substrate and having a plurality of bond pads being coplanar with the first surface of said substrate;
said substrate comprising
a first area defining a first sector of said substrate carrying said circuit and configured to be separated from the IC card,
said first sector having a form and size based upon a Nano-SIM (4FF) IC card format, said first area having a first line delimiting
said first sector to the 4FF IC card format, and

a second area defining a second sector around said first sector and configured to be separated from the IC card based upon
a second line, said second sector having a form and size based upon at least one of a Mini-SIM (2FF) IC card format and a
Micro-SIM (3FF) IC card format; and

a coating on the second surface of said substrate and being aligned with said second area, said coating having, along said
second sector, a thickness equal to a difference between a thickness of said at least one of the 2FF IC card format and the
3FF IC card format and a thickness of said first sector.

US Pat. No. 9,188,635

INTEGRATED CIRCUIT COMPRISING AT LEAST AN INTEGRATED ANTENNA

STMicroelectronics S.r.l....

1. An integrated circuit comprising:
a substrate including a peripheral portion that surrounds an active area supporting a transceiver circuit, wherein said peripheral
portion is realized close to at least one scribe line, and

a conductive structure that extends above said peripheral portion on different planes starting from said substrate and comprising
a plurality of first conductive lines realized in said different planes, each first conductive line forming a coil, with the
coils made from the first conductive lines connected to form an integrated antenna having a first end and second end coupled
to said transceiver circuit; and

another conductive structure that extends above said peripheral portion on different planes comprising a plurality of second
conductive lines realized in said different planes to form a seal ring;

wherein the integrated antenna is positioned between the seal ring and the active area on the substrate.

US Pat. No. 9,107,331

INTELLIGENT POWER MODULE AND RELATED ASSEMBLING METHOD

STMicroelectronics S.r.l....

1. An intelligent power module, comprising:
a protective case that includes a case body, a base plate, and a lid that covers an opening of the case body;
a power circuit board including a plurality of power devices and fixed on the base plate;
a first control circuit board configured to drive said power devices of said power circuit board, said first control circuit
board being associated with said lid of the protective case in such a way that said first control circuit board is comprised
within the opening in the case body, wherein said first control circuit board includes a first plurality of through-holes
and said lid includes a second plurality through-holes respectively aligned with said through-holes of said first plurality;
and

press-fits of a first type positioned partially in internal walls of said case body and extending respectively through the
first plurality of through-holes and respectively through the second plurality of through-holes, each press fit of the first
type having a body, a needle with an eye, and a protrusion extending from the needle in an opposite direction with respect
to said body, said body being directed toward and electrically coupled to said power circuit board, said protrusions extending
outside of the lid and being configured to electrically couple said power circuit board to circuitry outside of the intelligent
power module.

US Pat. No. 9,362,855

DETERMINING A POSITION OF A MOTOR USING AN ON-CHIP COMPONENT

STMICROELECTRONICS, INC.,...

13. A method, comprising:
providing a first voltage to a first pair of coils of a motor;
determining a rate of change of a first current that flows through the first pair of coils;
providing a second voltage to a second pair of coils of the motor in response to the determining of the rate of change of
the first current, the second pair of coils being different from the first pair of coils;

determining a rate of change of a second current that flows through the second pair of coils; and
determining a position of a rotor of the motor based on the rate of change of the first current and the rate of change of
the second current.

US Pat. No. 9,278,847

MICROELECTROMECHANICAL GYROSCOPE WITH ENHANCED REJECTION OF ACCELERATION NOISES

STMicroelectronics S.r.l....

1. A microelectromechanical structure, comprising:
a substrate;
a driving assembly having a first set of driving electrodes and a second set of driving electrodes;
elastic anchorage elements anchoring portions of the driving assembly to the substrate;
first and second elastic supporting elements;
a first sensing mass and a second sensing mass positioned between the first and second set of driving electrodes, the first
sensing mass coupled to the driving assembly via the first elastic supporting element and the second sensing mass coupled
to the driving assembly via the second elastic supporting element, the first and second sensing masses being configured to
be moved by the driving assembly and configured to move in response to rotation of the microelectromechanical structure;

a rigid connection bar positioned between the first sensing mass and the second sensing mass;
first and second elastic coupling elements coupled between the first and second sensing masses and the connection bar, respectively,
the elastic coupling elements configured to couple movement of the first and second sensing masses together to move at substantially
the same frequency; and

a third sensing mass and a fourth sensing mass positioned between the first and second set of driving electrodes, the first
and second sensing masses being aligned along a first axis and the third and fourth sensing masses being aligned along a second
axis that is angled with respect to the first axis by less than 90 degrees, the third and fourth sensing masses being movably
coupled to the driving assembly without being moveably coupled to the connection bar.

US Pat. No. 9,229,250

ELECTRO-OPTICAL MODULATOR INTERFACE

STMICROELECTRONICS S.R.L....

1. An integrated electro-optical modulator interface comprising:
a two-branch output stage comprising a plurality of thin oxide CMOS transistors configured to generate rail-to-rail output
swings larger than twice a nominal limit of a supply voltage of said plurality of thin oxide CMOS transistors, each branch
of said two-branch output stage comprising two stacked CMOS inverter pairs from among said plurality of thin oxide CMOS transistors;

said two stacked CMOS inverter pairs of a given branch being configured to drive a respective load capacitance, in phase opposition
to the other branch; and

a pre-driver circuit configured to receive a differential modulating signal and output, to respective inputs of said two stacked
CMOS inverters, two synchronous differential voltage drive signals having a swing of half the supply voltage and being DC-shifted
by half of the supply voltage with respect to each other.

US Pat. No. 9,160,186

BATTERY CHARGER FOR PROVIDING BATTERY PROTECTION FROM OVER DISCHARGE FROM VOLTAGE OR CURRENT AND SHIPPING MODE

STMICROELECTRONICS S.R.L....

1. A battery charger comprising:
an input supply terminal configured to receive a supply signal;
a battery terminal configured to be connected to a battery and at least one output terminal;
a switch arranged in the electrical path between the battery terminal and said at least one output terminal;
a latch configured to store data representative of an alarm condition indicative of an over current discharge, over voltage
discharge, or shipping mode of the battery and to open the switch when said alarm condition occurs, with the supply signal
being absent and the battery supplying said at least one output terminal, and to close the switch when said supply signal
is received at the input supply terminal;

a first comparator configured to detect the over current discharge condition and emit a first output signal;
a second comparator configured to detect the over voltage discharge condition and emit a second output signal; and
a control circuit connected to first and second comparators and the latch and configured to emit a set signal to the latch
in response to at least one of the output signals from the comparators or an external signal representative of the shipping
mode condition when the battery supplies the at least one output terminal and emit a reset signal to the latch in response
to the signal representative of the presence of a supply voltage at the input supply terminal.

US Pat. No. 9,099,453

METHODS, CIRCUITS AND SYSTEMS FOR A PACKAGE STRUCTURE HAVING WIRELESS LATERAL CONNECTIONS

STMicroelectronics S.r.l....

1. An article, comprising:
a package having a side and including a wiring system including a first metallization layer, a second metallization layer,
and a via interconnecting the first and second metallization layers;

a first integrated circuit disposed in the package and coupled to the wiring system; and
a first communication pad disposed adjacent to the side of the package, coupled to the integrated circuit, and configured
to allow the integrated circuit to communicate wirelessly outside of the package, the first communication pad formed from
a surface portion of the via.

US Pat. No. 9,099,322

PROCESS FOR MANUFACTURING A SEMICONDUCTOR POWER DEVICE COMPRISING CHARGE-BALANCE COLUMN STRUCTURES AND RESPECTIVE DEVICE

STMICROELECTRONICS S.R.L....

1. A semiconductor power device, comprising:
a semiconductor body having a first conductivity device;
a trench in said semiconductor body having side walls and a bottom; and
a first column of semiconductor material within said trench, said column housing dopant ions having a second conductivity
type;

wherein crystalline planes <100> and <130> are exposed on the bottom of the trench, and crystalline plane <010> is exposed
on the side walls;

wherein said first column has a spatially uniform distribution of said dopant ions;
wherein said first column has a width of between 0.8 and 2 ?m, and a depth of between 3 and 50 ?m or between 5 and 30 ?m,
with an aspect ratio of between 1.5 and 62.5.

US Pat. No. 9,918,364

ELECTRONIC CIRCUIT FOR DRIVING LED STRINGS INCLUDING A PLURALITY OF REGULATION MODULES WHICH FUNCTION IN SEQUENCE

STMicroelectronics S.r.l....

1. An electronic circuit, comprising:
a first regulation module having a first controlled current path coupling a cathode terminal of a first LED string to ground
through a first resistor and a first control circuit for controlling conduction of the first controlled current path, said
first control circuit comprising:

a current sensing circuit configured to sense current flowing in said first controlled current path and generate a first signal
indicative of sensed current;

an adder circuit configured to add said first signal to a second signal indicative a voltage drop across said first resistor,
said adder circuit generating a first feedback signal; and

an error amplifier configured to generate a control signal for controlling conduction of the first controlled current path
as a function of a difference between the first feedback signal and a reference signal.

US Pat. No. 9,391,551

APPARATUS TO DETECT THE ZERO-CROSS OF THE BEMF OF A THREE-PHASE ELECTRIC MOTOR AND RELATED METHOD

STMICROELECTRONICS S.R.L....

1. Apparatus to detect a zero-cross event of a back electromotive force (BEMF) of an electric motor with first, second, and
third phase windings driven by respective first, second, and third power driving stages, the apparatus comprising:
a zero-cross detecting circuit; and
a control circuit configured to control the first, second, and third power driving stages by at least
placing at an impedance state the third power driving stage relative to the third phase winding, the third phase winding being
coupled to said zero-cross detecting circuit,

driving the first power driving stage relative to the first phase winding with a first pulse width modulated (PWM) driving
signal,

introducing a masking signal to mask an output signal of said zero-cross detecting circuit in correspondence with each rising
edge of the first PWM driving signal, and

determining whether a first duty-cycle of the first PWM driving signal relative to the first phase winding is such that a
duration of a masking window of the masking signal is greater than an on-time period of the first PWM driving signal, and
if then,

driving the second power driving stage relative to the second phase winding with a second PWM driving signal with a second
duty-cycle greater than zero, and

modifying the first duty-cycle to have a duration of the on-time period of the first PWM driving signal greater than the masking
window of the masking signal.

US Pat. No. 9,240,457

IGBT TRANSISTOR WITH PROTECTION AGAINST PARASITIC COMPONENT ACTIVATION AND MANUFACTURING PROCESS THEREOF

STMICROELECTRONICS S.R.L....

1. A process for manufacturing an IGST transistor, comprising:
providing, in a semiconductor wafer, a drift region;
forming, in said drift region, a body region having a first type of conductivity;
forming a conduction region, crossing said body region in a direction perpendicular to a surface of said drift region and
having said first type of conductivity and a resistance lower than that of said body region, wherein forming said conduction
region comprises carrying out a plurality of implantations having matching target concentrations of dopant species in said
body region at different target depths from said surface of said drift region using the same mask and increasing energy levels
for each implantation;

removing the mask; and
subjecting the semiconductor wafer to a thermal process at a time duration to activate electrically the implanted dopant species
without diffusion.

US Pat. No. 9,226,079

MICROELECTROMECHANICAL SENSING STRUCTURE FOR A CAPACITIVE ACOUSTIC TRANSDUCER INCLUDING AN ELEMENT LIMITING THE OSCILLATIONS OF A MEMBRANE, AND MANUFACTURING METHOD THEREOF

STMicroelectronics S.r.l....

1. A microelectromechanical sensing structure, comprising:
a substrate of semiconductor material;
a sensing capacitor that includes:
a rigid conductive electrode;
a conductive membrane coupled to the substrate and arranged between the substrate and the electrode, the membrane having a
first surface and a second surface, the membrane being configured to deform in response to pressure, the sensing capacitor
having a capacitance that varies as a function of the deformation of the membrane;

a first chamber delimited at least in part by the substrate and the first surface of the membrane;
a second chamber being delimited at least in part by the electrode and the second surface of the membrane; and
a beam located in the first chamber and coupled to the substrate, the beam being configured to limit oscillations of the membrane
when the pressure has an amplitude that is above a first threshold, thereby preventing plastic deformation of the membrane.

US Pat. No. 9,203,315

CURRENT SENSING DEVICE FOR A MULTI-PHASE SWITCHED VOLTAGE REGULATOR

STMicroelectronics S.r.l....

1. A current sensing device for sensing phase currents of a multi-phase switched voltage regulator having phase windings and
R-C series couplings respectively coupled to the phase windings, each R-C series coupling including a shunt resistor and a
filter capacitor coupled to each other at a first intermediate node of the R-C series coupling, the current sensing device
comprising:
a plurality of input modules configured to be coupled to respective phase windings of the regulator and configured to deliver
sense currents representing unbalances of respective phase currents of the regulator with respect to an average current delivered
by each phase winding, each input module including:

an operational amplifier having a first input configured to be coupled to said first intermediate node of the R-C series coupling
of the respective phase,

a transistor having a control input coupled to an output of said operational amplifier, a first current terminal coupled to
a second input of the operational amplifier, and a second current terminal configured to provide a respective one of said
sense currents,

a constant current generator to provide a constant current and to bias said transistor through said first current terminal,
and

an output resistor coupling said first terminal to a second intermediate node shared in common by all said modules; and
an output stage configured to deliver another sense current representative of a total current delivered by the regulator,
the output stage including:

an output operational amplifier having a first input coupled to said second intermediate node,
an output transistor having a control terminal coupled to an output of said output operational amplifier, a first current
terminal coupled to a second input of the output operational amplifier, and a second current terminal configured to provide
said another sense current, and

a plurality of sense resistors, equal in number to the input stages, coupled in common to said first current terminal of the
output transistor and each configured to be coupled to the respective phase winding of the regulator.

US Pat. No. 9,097,592

TEMPERATURE SENSING DEVICE AND METHOD OF GENERATING A SIGNAL REPRESENTING THE TEMPERATURE OF AN ENVIRONMENT

STMicroelectronics S.r.l....

1. A sensing device, comprising:
circuitry configured to apply a voltage to a thermistor;
a first sense resistor;
a first current mirror configured to mirror a first current flowing through the thermistor through said first sense resistor;
circuitry configured to apply said voltage to a reference resistor;
a second sense resistor;
a second current mirror configured to mirror a second current flowing through the reference resistor through said second sense
resistor;

a comparator configured to compare voltages on said first and second sense resistors to generate a comparison signal; and
output circuitry configured to receive the comparison signal and to generate an output signal representative of a difference
between a temperature of an environment of the thermistor and a reference temperature, wherein a mirroring ratio of the second
current mirror is configured to vary based on the output signal.

US Pat. No. 9,992,916

THERMAL CONTROL PROCESS FOR A MULTI-JUNCTION ELECTRONIC POWER DEVICE AND CORRESPONDING ELECTRONIC POWER DEVICE

STMICROELECTRONICS S.R.L....

1. A thermal control method for an electronic device comprising an integrated circuit having a plurality of junction groups, with each junction group comprising a plurality of junctions, and each junction group having a respective thermal detector associated therewith to detect a respective group temperature associated with the respective junction group, the method comprising:comparing the detected group temperatures with a critical thermal group threshold to identify a critical thermal group from among the plurality of junction groups, wherein the junction group having a group temperature exceeding the critical thermal group threshold is identified as the critical thermal group;
deactivating all junctions of the critical thermal group while maintaining the remaining junction groups active;
subsequent to deactivating all junctions of the critical thermal group in response to the group temperature exceeding the critical thermal group threshold, activating one given junction from among the plurality of junctions of the critical thermal group as an active junction while keeping deactivated all other junctions from among the plurality of junctions of the critical thermal group;
detecting the group temperature of the critical thermal group having the active junction and the all other deactivated junctions;
comparing the detected group temperature of the critical thermal group having the active junction and the all other deactivated junctions to a junction thermal critical threshold; and
deactivating the active junction in response to the detected group temperature exceeding the junction thermal critical threshold while activating all other junctions of the critical thermal group.

US Pat. No. 9,318,313

SEMICONDUCTOR STRUCTURE WITH LOW-MELTING-TEMPERATURE CONDUCTIVE REGIONS, AND METHOD OF REPAIRING A SEMICONDUCTOR STRUCTURE

STMicroelectronics S.r.l....

25. A method, comprising:
contacting a coupling pad of a semiconductor structure with a member; and
melting a portion of the coupling pad without melting any other portion of the semiconductor structure;
wherein the semiconductor structure includes a first die;
wherein contacting the coupling pad includes attaching a terminal of a second die to the coupling pad; and
detaching the terminal of the second die from the coupling pad of the first die while the portion of the coupling pad is molten.

US Pat. No. 9,236,839

CLASS-G AMPLIFIER AND AUDIO SYSTEM EMPLOYING THE AMPLIFIER

STMICROELECTRONICS S.R.L....

1. A Class-G amplifier, comprising:
a first and second driving transistor configured to receive an input voltage;
a first supplying terminal connected to the first driving transistor to supply a first supplying voltage;
a second supplying terminal connected to the second driving transistor to supply a second supplying voltage having an absolute
value higher than said first voltage;

a first power transistor connected to the first driving transistor to form a first Sziklai transistor pair with complementary
feedback and being structured to be activated by a first input voltage having an absolute value lower than the first supplying
voltage;

a second power transistor connected to the second driving transistor to form a second Sziklai transistor pair with complementary
feedback and being structured to be activated by an input signal comprised between the first supplying voltage and the second
supplying voltage.

US Pat. No. 9,105,811

PROCESS FOR REALIZING A SYSTEM FOR RECOVERING HEAT, IN PARTICULAR BASED ON THE SEEBECK'S EFFECT, AND CORRESPONDING SYSTEM

STMICROELECTRONICS S.R.L....

1. An apparatus, comprising:
a substrate having an upper surface;
an L-shaped first monolithic metal member, having first and second ends, and configured to have a first temperature, the second
end of the L-shaped first monolithic metal member being at a longer side of the L-shaped first monolithic metal member and
the longer side positioned directly on the upper surface of the substrate;

an L-shaped third monolithic metal member positioned directly on the upper surface of the substrate and having first and second
ends; and

an L-shaped second monolithic metal member disposed over the L-shaped first monolithic metal member and the L-shaped third
monolithic metal member, having a first end electrically coupled to an upper surface of the second end of the L-shaped first
monolithic metal member, having a second end electrically coupled to an upper surface of the first end of the L-shaped third
monolithic metal member, and configured to have a second temperature and to conduct a current from the L-shaped first monolithic
metal member in response to a nonzero difference between the first and second temperatures.

US Pat. No. 9,093,232

ELECTRONIC SWITCH FOR LOW-VOLTAGE AND HIGH SWITCHING SPEED APPLICATIONS

STMICROELECTRONICS S.R.L....

1. An electronic switch comprising:
a transfer transistor having a first conduction terminal configured to receive an input signal, a second conduction terminal,
and a control terminal;

said transfer transistor configured to enable/disable a transfer of the input signal from said first conduction terminal to
said second conduction terminal according to a control signal, the control signal having either a first value or a second
value different from the first value, a difference between the first value and the second value defining, in absolute value,
an operative value of the control signal; and

a driving circuit comprising
a capacitor comprising a first terminal, and a second terminal,
an input circuit comprising
an input transistor having a first conduction terminal configured to receive the input signal, a second conduction terminal
coupled to the first terminal of said capacitor, and a control terminal, and

a first latch circuit configured to receive the input signal and provide a corresponding shifted latched input signal to the
control terminal of said input transistor, the shifted latched input signal being equal to a difference between the input
signal and the operative value of the control signal, and

an output circuit configured to provide the driving signal to the control terminal of said transfer transistor, the driving
signal being equal to a sum of the input signal and the operative value of the control signal.

US Pat. No. 9,081,514

METHOD FOR CONTROLLING OPERATION OF A MEMORY USING A SINGLE WRITE LOCATION AND AN ASSOCIATED MEMORY

STMICROELECTRONICS S.R.L....

1. A method of controlling operation of a memory comprising a plurality of write locations, the method comprising:
writing input data to the memory in a single write location among the plurality of write locations; and
making the single write location available for writing new input data by shifting the input data written in the single write
location to another write location among the plurality of write locations;

wherein, at only each writing of input data in the single write location, scheduling the shifting at a next clock cycle without
having to wait for a next input write operation.

US Pat. No. 9,470,526

MICROELECTROMECHANICAL GYROSCOPE WITH ROTARY DRIVING MOTION AND IMPROVED ELECTRICAL PROPERTIES

STMICROELECTRONICS S.R.L....

1. A device, comprising:
a substrate;
a rectangular frame formed on the substrate, a first side of the frame extending along a first axis and a second side of the
frame extending along a second axis that is orthogonal to the first axis;

a driving assembly elastically coupled to the substrate and positioned within the frame, at least a portion of the driving
assembly being configured to move in a plane;

a first pair of sensing masses coupled to the driving assembly and positioned within the frame, the first pair of sensing
masses aligned with each other along a third axis, the third axis being transverse to the first axis, the first pair of sensing
masses being configured to move out of the plane to generate a first signal indicative of rotation about the first axis and
rotation about the second axis;

a second pair of sensing masses coupled to the driving assembly, the second pair of sensing masses aligned with each other
along a fourth axis, and the fourth axis being orthogonal to the third axis, the second pair of sensing masses being configured
to move out of the plane to generate a second signal indicative of rotation about the first axis and rotation about the second
axis; and

a read circuit coupled to the first pair of sensing masses and the second pair of sensing masses, the read circuit configured
to detect rotation about the first axis based on the first and second signals from the first pair of sensing masses and the
second pair of sensing masses, respectively.

US Pat. No. 9,275,943

POWER DEVICE HAVING REDUCED THICKNESS

STMicroelectronics S.r.l....

1. An electronic device, comprising:
at least one chip wherein at least one electronic component is integrated, the at least one chip comprising a first conduction
terminal on a first surface of the chip, and a second conduction terminal and a third conduction terminal on a second surface
of the chip opposite the first surface;

a first heat-sink formed by a solid plate consisting of an electrically conductive material, the solid plate provided with
at least one recess in a surface that defines a first portion of the solid plate having a first thickness and a second portion
of the solid plate having a second thickness less than the first thickness;

wherein the first surface with the first conduction terminal of said at least one chip is mounted to a bottom surface of the
at least one recess for dissipating heat generated by said at least one electronic component towards a mounting surface configured
to be mounted on a board;

wherein the first portion of the solid plate completely surrounds a peripheral edge of, said at least one chip housed within
said at least one recess;

a second heat-sink formed of an electrically conductive material for dissipating the heat generated by said at least one electronic
component towards a free surface opposite the mounting surface, the second heat-sink contacting the second conduction terminal
on the second surface and extending over at least one portion of the third conduction terminal, the second heat-sink comprising
at least one further recess for insulating the third conduction terminal from the second heat-sink; and

an insulating body encapsulating the at least one chip, the first heat-sink, and the second heat-sink, wherein the insulating
body is made of a non-electrically conductive material.

US Pat. No. 9,248,648

MICROFLUIDIC DIE WITH MULTIPLE HEATERS IN A CHAMBER

STMICROELECTRONICS S.R.L....

1. A device, comprising:
a substrate;
a first heater on the substrate;
a second heater spaced from the first heater on the substrate, the first heater being larger in area than the second heater;
a first microfluidic chamber aligned with the first heater and the second heater;
a first nozzle aligned with the first chamber; and
a channel region in fluid communication with the first microfluidic chamber and the first nozzle, the first heater being separated
from the channel region by the second heater, the first nozzle being separated from the channel region by the second heater.

US Pat. No. 9,187,310

WAFER-LEVEL PACKAGING OF A MEMS INTEGRATED DEVICE AND RELATED MANUFACTURING PROCESS

STMicroelectronics S.r.l....

1. A package for a MEMS integrated device, the package comprising:
a first body including semiconductor material and integrating a micromechanical structure;
a second body including an active region of semiconductor material and an application specific integrated circuit formed in
the active region of semiconductor material and coupled to said micromechanical structure, said second body defining a base
portion of said package and having an inner surface and an outer surface, wherein the inner surface of said second body has
a cavity having a base, said first body coupled to said base in said cavity, said cavity defining at least in part a housing
space;

first electrical contacts positioned on the outer surface and coupled to said application specific integrated circuit;
a routing layer having an inner surface in contact with the outer surface of said base portion;
electrical contact elements positioned on the outer surface of the routing layer, said routing layer providing electrical
connection paths between said first electrical contacts and said electrical contact elements; and

a third body coupled to said second body to close the housing space for housing said first body, said third body defining
a covering portion for said package.

US Pat. No. 9,174,445

MICROFLUIDIC DIE WITH A HIGH RATIO OF HEATER AREA TO NOZZLE EXIT AREA

STMicroelectronics S.r.l....

1. A device, comprising:
a substrate;
a plurality of heaters on the substrate, each heater having a heater area;
a plurality of nozzles disposed above the heaters, each nozzle having an entrance and an exit, each entrance being closer
to a heater than the exit, the exit having a first nozzle area, a ratio of the heater area to the first nozzle area being
greater than 9 to 1; and

a plurality of chambers disposed between the heaters and the nozzles.

US Pat. No. 9,159,644

MANUFACTURING OF DSC TYPE ELECTRONIC DEVICES BY MEANS OF SPACER INSERT

STMicroelectronics S.r.l....

1. A process for manufacturing dual side cooling type electronic devices, comprising:
placing, in each one of a set of molds, at least one assembly comprising a first heat sink, at least one chip of semiconductor
material mounted on the first heat sink, a second heat sink mounted on said at least one chip and a plurality of pin blocks
electrically connected to said at least one chip, the first heat sink having an outer surface in contact with a first inner
surface of the mold,

placing a spacer insert into each mold in contact with an outer surface of the second heat sink,
filling each mold with insulating material in the liquid state,
hardening the insulating material, and
extracting a resulting electronic device from each mold, wherein the hardened insulating material forms a protective package
for said at least one chip that exposes both the outer surface of the first heat sink and the outer surface of the second
heat sink, the resulting electronic device being separate from the spacer insert.

US Pat. No. 9,151,806

READING CIRCUIT FOR A MAGNETIC FIELD SENSOR WITH SENSITIVITY CALIBRATION, AND RELATED READING METHOD

STMicroelectronics S.r.l....

1. A reading circuit, comprising:
an amplifier having at least one input configured to receive a magnetic field detection signal of a magnetic field sensor
and at least one output, and configured to generate an output signal at the at least one output as a function of the magnetic
field detection signal and of an amplification gain between the at least one input and the at least one output of the amplifier;
and

calibration circuitry configured to generate one or more control signals to control a feedback loop of the amplifier based
on an indication of a detection sensitivity of the magnetic field sensor.

US Pat. No. 9,152,383

METHOD FOR ENCRYPTING A MESSAGE THROUGH THE COMPUTATION OF MATHEMATICAL FUNCTIONS COMPRISING MODULAR MULTIPLICATIONS

STMicroelectronics S.r.l....

1. An apparatus, comprising:
calculator circuitry configured to calculate a randomized number and a first parameter representative of an operation of squaring
of a Montgomery number co-prime of a module of a cryptographic algorithm and eater than the module, wherein the calculator
circuitry is further operable to calculate a Montgomery parameter based on the first parameter and an integer multiple of
the randomized number;

converter circuitry configured to generate a representation of a message to be encrypted in a Montgomery domain through a
Montgomery conversion function applied to the message and to the Montgomery parameter; and

coder circuitry configured to encrypt the representation of the message in the Montgomery domain.

US Pat. No. 9,450,076

POWER LDMOS SEMICONDUCTOR DEVICE WITH REDUCED ON-RESISTANCE AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. An electronic semiconductor device, comprising:
a semiconductor body having a first side and a second side opposite to one another along an axis, including:
a first structural region facing the second side and having a first conductivity;
a second structural region extending over the first structural region, facing the first side and housing a drain region;
a body region, having a second conductivity opposite to the first conductivity, extending into the second structural region
on the first side;

a source region, having the first conductivity, extending into the body region and facing the first side;
a gate electrode, extending over a portion of the first side of the semiconductor body;
a first trench, extending completely through the second structural region at a first side of the gate electrode and housing
a first trench conductive region electrically insulated from the second structural region; and

a second trench, extending completely through the source region, the body region, and the second structural region at a second
side opposite to the first side of the gate electrode, said second trench housing a second trench conductive region electrically
insulated from the second structural region and electrically coupled to the body region and to the source region.

US Pat. No. 9,383,591

STABILIZED PICO-PROJECTOR DEVICE AND RELATED IMAGE STABILIZATION METHOD

STMicroelectronics S.r.l....

1. A pico-projector device, comprising:
a light source operable to generate a light beam as a function of an image to be generated;
a mirror mechanism operable to direct the light beam towards a displaying surface; and
a driving circuit configured to supply driving signals for movement of said mirror mechanism, said driving circuit further
comprising:

a generator stage for receiving an image array and generating control signals; and
a compensation stage configured to receive angular velocity signals from a gyroscopic sensor coupled to said pico-projector
device, and to generate compensation signals by multiplication of the angular velocity signals with a corrective factor, and
to subtract the compensation signals from the control signals to generate said driving signals for stabilizing the image projected
on said displaying surface with respect to undesired movements of said pico-projector device.

US Pat. No. 9,237,039

TRANSCEIVER SUITABLE FOR IO-LINK DEVICES AND RELATED IO-LINK DEVICE

STMICROELECTRONICS S.R.L....

1. A transceiver suitable for IO-Link™ devices, connectable to a cable with at least three wires, comprising:
a positive supply pin connectable to a positive supply wire of the cable on which a positive supply voltage is made available;
a negative supply pin connectable to a negative supply wire of the cable on which a negative supply voltage is made available;
at least one input/output pin connectable to a digital data wire of the cable configured to receive/transmit data signals
switching between the positive supply voltage and negative supply voltage from/to IO-Link™ devices connected to the cable;

inner functional blocks;
an internal positive voltage line;
an internal negative voltage line; and
a controlled output stage configured to connect said at least one input/output pin to said positive supply pin or to said
negative supply pin, including a protection circuit for said inner functional blocks against reverse polarity due to a wrong
connection of said positive and negative supply pins to respective wires of the cable;

said controlled output stage comprising
a high-side leg, comprising two P-type transistors connected in series between them such as to have a common current terminal,
coupled between said at least one input/output pin and said positive supply pin, the common current terminal being connected
to said internal positive voltage line, said P-type transistors having body regions being shorted to the common current terminal,
and

a low-side leg, comprising two N-type transistors connected in series between them such as to have a common current terminal,
coupled between said at least one input/output pin and said negative supply pin, the common current terminal being connected
to said internal negative voltage line, said N-type transistors having body regions being shorted to the common current terminal;
and

a driver comprising a first current path extending between a positive supply terminal and the common current terminal of the
high-side leg, and a second current path extending between a negative supply terminal and common current terminal of the low-side
leg, and being configured to turn on/off said two P-type and two N-type transistors to allow transmission on the digital data
wire;

said protection circuit comprising a voltage clamper connected between the common current terminal for said high-side leg
and the common current terminal for said low-side leg, configured to enter in a conduction state in case of overvoltage on
the internal negative and positive supply voltage lines.

US Pat. No. 9,202,951

INTEGRATED OPTOELECTRONIC DEVICE AND SYSTEM WITH WAVEGUIDE AND MANUFACTURING PROCESS THEREOF

STMicroelectronics S.r.l....

1. An integrated optoelectronic device, delimited by a first surface and a second surface and comprising:
a body of semiconductor material including at least one optoelectronic component integrally formed in the body of semiconductor
material, the at least one optoelectronic component being a detector or an emitter; and

an optical path integrally formed in the body of semiconductor material, the optical path at least in part of a guided type
and extends between the first surface and the second surface, said optical path traversing the body of semiconductor material;
and

wherein the at least one optoelectronic component is optically coupled through the optical path and the first surface to free
space and through the optical path and the second surface to free space.

US Pat. No. 9,184,150

ELECTRONIC DEVICE WITH BIMETALLIC INTERFACE ELEMENT FOR WIRE BONDING

STMicroelectronics S.r.l....

1. An electronic device, comprising:
at least one chip on which at least one electronic component is integrated, said chip comprising at least one terminal of
said at least one electronic component comprising a first metal element,

at least one lead made of a second metal element different from the first metal element,
at least one bonding wire made of a selected one between the first metal element and the second metal element, the bonding
wire having opposite ends coupled with the terminal and with the lead, and

at least one interface element having a first layer made of the selected one of the first and second metal elements and a
second layer made of an unselected one of the first and second metal elements,

wherein said first layer is directly coupled with the bonding wire and wherein said second layer is directly coupled with
a component comprising one of the terminal or the lead.

US Pat. No. 9,176,185

ACTIVE PROBE CARD FOR ELECTRICAL WAFER SORT OF INTEGRATED CIRCUITS

STMicroelectronics S.r.l....

1. A probe card system for a testing apparatus, comprising:
a probe card configured to be coupled to a tester of the testing apparatus,
an active interposer coupled to the probe card and configured to be wirelessly coupled with a device to be tested that includes
a plurality of pads, said active interposer including:

a free surface configured to face the device;
a plurality of pads positioned on the free surface and configured to respectively face the pads of the device and to be separated
from the pads of the device by a dielectric, each pad of the active interposer being configured to form, with the respective
pad of the device, an elementary wireless coupling element that allows a wireless transmission between the active interposer
and the device; and

an amplifier circuit configured to amplify wireless signals from the device and forward the amplified wireless signals to
the tester; and

a transmission element coupled to the active interposer and configured to transmit a supply voltage to the device.

US Pat. No. 9,176,191

CONTINUITY TEST IN ELECTRONIC DEVICES WITH MULTIPLE-CONNECTION LEADS

STMICROELECTRONICS S.R.L....

1. An electronic device comprising:
at least one electronic component comprising a set of first terminals and a set of second terminals;
a protective package surrounding the at least one electronic component;
a set of first leads and a set of second leads exposed from the protective package;
a first electrical connection inside the protective package between each first lead and a corresponding one of the first terminals;
a plurality of second electrical connections inside the protective package each one between the second lead and a corresponding
one of the second terminals;

said at least one electronic component comprising a plurality of test structures for each second lead, each test structure
being coupled between a corresponding one of the second terminals connected to the second lead and a corresponding test one
of the first terminals connected to a test one of the first leads;

each test structure being configurable in a test condition for testing the corresponding second electrical connection through
the second lead and the test first lead or in an operative condition for not interfering with a normal operation of the second
lead and the test first lead.

US Pat. No. 9,118,250

POWER SUPPLY CIRCUIT FOR REMOTELY TURNING-ON ELECTRICAL APPLIANCES

STMICROELECTRONICS S.R.L....

1. A control circuit configured to control electronic equipment in response to a remote controller, comprising:
a converter circuit configured to convert electromagnetic energy received from the remote controller to stored energy;
a power management circuit configured to provide a regulated supply voltage based on the stored energy;
a control logic circuit energized by the regulated supply voltage and configured to to detect a match between an ID code received
from the remote controller and a local ID code representative of the electronic equipment, and to provide an enable signal
in response to detecting the match; and

an actuator circuit configured to activate the electronic equipment in response to the enable signal.

US Pat. No. 10,129,942

ELECTRONIC CIRCUIT FOR DRIVING LED STRINGS SO AS TO REDUCE THE LIGHT FLICKER

STMicroelectronics S.r.l....

1. An electronic circuit, comprising:a regulator circuit configured to regulate current flowing in a compensation LED string;
current sensing circuitry configured to generate first output signals that are indicative of current flowing in each LED string of a plurality of LED strings cascaded to one another and generate a second output signal indicative of current flowing in the compensation LED string;
a summation circuit configured to sum said first and second output signals and generate a sum signal;
a difference circuit configured to detect change in said sum signal and generate a difference signal;
wherein said regulator circuit includes an amplifier circuit configured to regulate current flowing in the compensation LED string in response to a difference between the second output signal and the difference signal.

US Pat. No. 9,941,850

FULLY DIFFERENTIAL OPERATIONAL AMPLIFIER

STMICROELECTRONICS S.R.L....

1. A fully differential operational amplifier, comprising:first and second amplifier input nodes;
first and second amplifier output nodes;
a differential input stage having a first input coupled to the first amplifier input node, a second input coupled to the second amplifier input node, a first output coupled to a first intermediary node and a second output coupled to a second intermediary node;
a level shifting and amplification stage having first and second outputs, the level shifting and amplification stage including:
a fully differential amplification stage having a positive input coupled to the first intermediary node, a negative input coupled to the second intermediary node, a negative output, and a positive output;
a first compensation transistor having a first conduction terminal coupled to the first intermediary node, a second conduction terminal coupled to the first output of the level shifting and amplification stage, and a control terminal coupled to the negative output of the fully differential amplification stage; and
a second compensation transistor having a first conduction terminal coupled to the second intermediary node, a second conduction terminal coupled to the second output of the level shifting and amplification stage, and a control terminal coupled to the positive output of the fully differential amplification stage;
a positive output stage having an input coupled to first output of the level shifting and amplification stage, and an output coupled to the first amplifier output node, the positive output stage including a first compensating capacitor coupled between the first amplifier output node and the positive input of the fully differential amplification stage at the first intermediary node; and
a negative output stage having an input coupled to the first output of the level shifting and amplification stage and an output coupled to the second amplifier output node, the negative output stage including a second compensating capacitor coupled between the second amplifier output node and the negative input of the fully differential amplification stage at the second intermediary node.

US Pat. No. 9,642,244

MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) AND CORRESPONDING MANUFACTURING PROCESS

STMicroelectronics S.r.l....

1. A Micro-Electro-Mechanical System (MEMS), comprising:
at least one micro-electro-mechanical device of the MEMS type;
a junction including a duct suitable to provide a fluidic connection between an external apparatus and the micro-electro-mechanical
device through the duct;

wherein said junction comprises a printed circuit board having the micro-electro-mechanical device mounted to the printed
circuit board, the printed circuit board including:

a first layer having first and second conductive surfaces;
a second layer disposed over the first layer and having a third conductive surface and a fourth opposite conductive surface
that faces and is insulated from the first surface;

a first duct disposed and extending substantially parallel and free from any obstruction, disposed between the first surface
of the first layer and the fourth surface of the second layer, the duct having a cavity with a first opening through one of
the second and third surfaces and the cavity having a second opening through one of the second and third surfaces, the first
opening configured to provide a fluidic connection between the duct and the micro-electro-mechanical device and the second
opening configured to receive an external apparatus and to provide a fluidic connection between the external apparatus and
the duct to thereby provide a fluidic coupling between the micro-electro-mechanical device and the external apparatus through
the duct.

US Pat. No. 9,455,636

CONTROL METHOD AND DEVICE EMPLOYING PRIMARY SIDE REGULATION IN A QUASI-RESONANT AC/DC FLYBACK CONVERTER

STMICROELECTRONICS S.R.L....

1. A device for controlling a power transistor of a power stage, comprising:
a divider having a first input, a second input and an output, the divider being configured to produce a voltage reference
signal;

a first current generator configured to produce an output current;
a shaper circuit configured to output to the first input of the divider a first signal based on the output current of the
first current generator;

a bias circuit configured to output a second signal to the second input of the divider based on the first signal; and
a driver circuit having a first input, configured to receive the voltage reference signal, and an output configured to drive
the power transistor.

US Pat. No. 9,383,382

MICROELECTROMECHANICAL SENSOR WITH OUT-OF-PLANE SENSING AND PROCESS FOR MANUFACTURING A MICROELECTROMECHANICAL SENSOR

STMICROELECTRONICS S.R.L....

1. A microelectromechanical sensor comprising:
a supporting structure having a substrate and electrode structures anchored to the substrate, each electrode structure including
a first fixed electrode, a second fixed electrode, and a dielectric region, the first fixed electrode and the second fixed
electrode being mutually insulated by the dielectric region and arranged in succession in a direction substantially perpendicular
to a face of the substrate; and

a sensing mass of a continuous and uniform material movable with respect to the supporting structure so that a distance between
the sensing mass and the substrate is variable, the sensing mass including movable electrodes capacitively coupled to the
electrode structures.

US Pat. No. 9,137,895

MICRO-ELECTRO-MECHANICAL SYSTEMS (MEMS) AND CORRESPONDING MANUFACTURING PROCESS

STMicroelectronics S.r.l....

1. A circuit support, comprising:
a first layer having first and second conductive surfaces;
a second layer disposed over the first layer and having a third conductive surface and a fourth opposite conductive surface
that faces and is insulated from the first surface;

a first duct disposed and extending substantially parallel and free from any obstruction, disposed between the first surface
of the first layer and the fourth surface of the second layer, the duct having a cavity having a first opening through one
of the second and third surfaces, the cavity having a second opening through one of the second and third surfaces, and the
first and second openings configured to receive an external apparatus coupled to the circuit support and to provide a fluidic
connection between the external apparatus and the first duct of the circuit support.

US Pat. No. 9,105,698

MULTILEVEL INTERCONNECT STRUCTURES AND METHODS OF FABRICATING SAME

STMicroelectronics S.r.l....

1. A method for fabricating a multilevel interconnect structure with a first conducting level and a second conducting level,
comprising:
depositing a first dielectric layer over the first conducting level;
depositing an intermediate dielectric layer on the first dielectric layer;
performing chemical mechanical polishing after depositing the intermediate dielectric layer, wherein the chemical mechanical
polishing ends below an upper level of the first dielectric layer;

depositing a second dielectric layer touching the intermediate dielectric layer and the first dielectric layer, wherein the
second dielectric layer includes a lower planar surface that is directly in contact with the first dielectric layer and the
intermediate dielectric layer along a single plane of contact; and

opening a funnel-shaped connecting via through the first dielectric layer and the second dielectric layer, wherein the funnel-shaped
connecting via comprises an upper wide portion opened only in the second dielectric layer and a narrower lower portion with
two vertical or almost vertical sidewalls extending in both the first dielectric layer and the second dielectric layer,

wherein the upper wide portion is formed using isotropic etching and the narrower lower portion is formed using anisotropic
etching.

US Pat. No. 9,728,837

METHOD AND APPARATUS FOR TUNING A RESONANT CIRCUIT USING A LASER

STMicroelectronics S.r.l....

1. A system for tuning a resonant circuit comprised of an inductive circuit portion and a capacitive circuit portion of an
integrated circuit communications device, comprising:
a transparent substrate separate from the integrated circuit communications device;
a test antenna supported by the transparent substrate;
an automated test equipment circuit coupled to the test antenna and configured to apply a variable signal to said test antenna
for communication to said resonant circuit of the separate integrated circuit communications device to identify a resonant
frequency of said resonant circuit; and

a trimming laser configured to emit a laser beam directed through said transparent substrate and towards said separate integrated
circuit communications device to effectuate a trimming of a structure of at least one of the inductive circuit portion and
the capacitive circuit portion for adjusting the resonant frequency of said resonant circuit.

US Pat. No. 9,450,434

ENERGY HARVESTING SYSTEM WITH SELECTIVELY ACTIVATABLE HARVESTING INTERFACE, AND METHOD OF ENERGY HARVESTING

STMICROELECTRONICS S.R.L....

1. An energy harvesting system, comprising:
a transducer configured to harvest environmental energy and convert harvested environmental energy into a harvesting electrical
signal;

a storage element configured to store electric energy derived from conversion of the environmental energy harvested by the
transducer;

a harvesting interface coupled to the transducer and configured to supply a charge electrical signal to the storage element
as a function of the harvesting electrical signal; and

a selective connection device comprising:
a switch coupled between the supply terminal of the harvesting interface and the storage element and having a driving node;
a capacitive element coupled to the driving node;
a charge circuit coupled to the storage element and driving node and configured to charge the capacitive element; and
an activation transistor having a control terminal coupled to the transducer so as to receive the harvesting electrical signal
and configured to selectively actuate said switch to connect a supply terminal of the harvesting interface to the storage
element when a voltage of the harvesting electrical signal exceeds a threshold voltage of the activation transistor and to
disconnect the supply terminal of the harvesting interface from the storage element when the voltage of the harvesting electrical
signal does not exceed the threshold voltage of the activation transistor.

US Pat. No. 9,378,077

SYSTEM FOR DETECTING OPERATING ERRORS IN INTEGRATED CIRCUITS

STMICROELECTRONICS S.R.L....

1. A method of detecting errors induced by noise pulses in a digital electronic circuit clocked by a first clock signal, the
method comprising:
providing a second clock signal offset in time of a given interval with respect to said first clock signal, each rising edge
of the second clock signal preceding a subsequent rising edge of the first clock signal;

performing, for at least one component of the digital electronic circuit, a correspondence check between two versions of a
same signal in said digital electronic circuit, the correspondence check being clocked by the second clock signal;

feeding each result of the correspondence check to a logic gate, the absence of correspondence between said two versions of
said signal being indicative of an error induced in said digital electronic circuit by a noise pulse; and

driving an output flip-flop with an output signal of the logic gate, the output flip-flop being clocked by an auxiliary clock
signal, each rising edge of the auxiliary clock signal having a delay with respect to a preceding rising edge of the first
clock signal;

wherein the first clock signal clocks a first plurality of flip-flops of the digital electronic circuit, and the second clock
signal clocks a second plurality of flip-flops of the digital electronic circuit.

US Pat. No. 9,234,913

MICROELECTROMECHANICAL DEVICE INCORPORATING A GYROSCOPE AND AN ACCELEROMETER

STMICROELECTRONICS S.R.L....

1. A microelectromechanical device, comprising:
a supporting structure;
a first sensing mass and a second sensing mass, each movable with respect to the supporting structure, both movable according
to a first axis and each movable according to a respective second axis, perpendicular to the first axis;

a driving device configured to maintain the first sensing mass and the second sensing mass in oscillation along the first
axis in phase opposition;

a first group of sensors and a second group of sensors configured to supply sensing signals, respectively indicative of displacements
of the first sensing mass and of the second sensing mass according to the second axis; and

processing components configured to:
combine the sensing signals in a first sensing mode and in a second sensing mode,
amplify in the first sensing mode, effects on the sensing signals of concordant displacements of the first sensing mass and
of the second sensing mass, and attenuate effects of discordant displacements of the first sensing mass and of the second
sensing mass; and

amplify in the second sensing mode, effects on the sensing signals of discordant displacements of the first sensing mass and
of the second sensing mass, and attenuate effects of concordant displacements of the first sensing mass and of the second
sensing mass.

US Pat. No. 9,200,953

SPECTROMETER INCLUDING A GEIGER-MODE AVALANCHE PHOTODIODE

STMicroelectronics S.r.l....

1. A spectrometer, comprising:
an avalanche photodiode, including a first region and a second region having different types of conductivity and forming a
first junction, the photodiode being configured to:

form a first depletion region; and
generate a detection signal indicative of instants of detection of photons of optical pulses;
a converter configured to:
receive the detection signal and a synchronization signal indicative of instants of emission of optical pulses; and
generate a delay signal indicative of delays between instants of detection and corresponding instants of emission; and
one or more processing devices configured to:
determine a statistical distribution of delays between instants of detection and corresponding instants of emission based
on the electrical delay signal;

select a first portion of the statistical distribution;
determine a sample value correlated to a ratio between a number of delays that fall within the first portion of the statistical
distribution and a total number of delays of the statistical distribution; and

estimate a wavelength of optical pulses based on stored correlation information and the sample value.

US Pat. No. 9,099,480

INDEXING OF ELECTRONIC DEVICES DISTRIBUTED ON DIFFERENT CHIPS

STMicroelectronics S.r.l....

1. An electronic device comprising:
a first chip associated with information corresponding to a location on a wafer from which the first chip originated;
a second chip coupled with the first chip; and
an index indicative of the information;
wherein the index includes a first portion on the first chip and a second portion on the second chip.

US Pat. No. 9,386,372

EMBEDDED SPEAKER PROTECTION FOR AUTOMOTIVE AUDIO POWER AMPLIFIER

STMICROELECTRONICS S.R.L....

1. A method of operating a speaker system including a speaker coupled to an amplifier, comprising:
turning on the amplifier in a mute mode;
after a first delay period, issuing a play command to the amplifier to place the amplifier in a play mode, but without an
input signal during a second delay period; and

performing a speaker offset detection during the second delay period;
wherein, if there is an offset, then the amplifier is forced back into the mute mode, and if there is no offset, then the
amplifier is allowed to continue to operate in the play mode.

US Pat. No. 9,372,085

MICROELECTROMECHANICAL SENSOR WITH DIFFERENTIATED PERFORMANCES AND METHOD OF CONTROLLING A MICROELECTROMECHANICAL SENSOR

STMICROELECTRONICS S.R.L....

1. A microelectromechanical sensor, comprising:
a supporting structure;
a first sensing mass, elastically coupled to the supporting structure, movable with respect to the supporting structure according
to a first degree of freedom, in response to movements of the supporting structure according to a first axis, and coupled
to the supporting structure through a first capacitive coupling variable as a function of a relative position of the first
sensing mass with respect to the supporting structure;

a second sensing mass, elastically coupled to the supporting structure, movable with respect to the supporting structure according
to a second degree of freedom, in response to movements of the supporting structure according to a second axis, and coupled
to the supporting structure through a second capacitive coupling variable as a function of a relative position of the second
sensing mass with respect to the supporting structure, the second capacitive coupling having second terminals;

a sensing device, configured to sense, at first terminals of the first capacitive coupling, transduction signals indicative
of displacements of the first sensing mass according to the first degree of freedom and to convert the transduction signals
into measurement signals,

the sensing device, including:
a first reading chain having first operative parameters;
a second reading chain having second operative parameters different from the first operative parameters; and
a selective electrical connection structure configured to alternatively couple the first reading chain and the second reading
chain to the first terminals and the second terminals, the selective electrical connection structure configured to prevent
the first reading chain and the second reading chain from being simultaneously coupled to the first terminals or to the second
terminals.

US Pat. No. 9,318,966

METHOD OF CONTROLLING A SWITCHING CONVERTER IN BURST MODE AND RELATED CONTROLLER FOR A SWITCHING CONVERTER

STMicroelectronics S.r.l....

1. A method, comprising:
controlling a switching converter configured to output in operation a regulated DC voltage or current, the switching converter
including a switching stage configured to drive an energy tank circuit, said controlling including:

controlling in a burst mode the switching stage to increase the regulated DC voltage or current by performing switching cycles
synchronously with active edges of a clock signal for switching the energy tank circuit between a positive voltage line and
a negative voltage line, or to decrease the regulated DC voltage or current when an error signal, representative of a difference
between the regulated DC voltage or current and a nominal output voltage or current, surpasses a burst-stop threshold,

sensing a difference between the error signal and the burst-stop threshold at a beginning of a burst period;
determining an integer first number based on the difference between the error signal and the burst-stop threshold at a beginning
of a burst period;

if the error signal has surpassed the burst-stop threshold:
setting the switching stage in a high impedance state at a new active edge of the clock signal,
keeping the switching stage in the high impedance state for a number of cycles of said clock signal equal to the first number,
and

re-enabling, up to an end of the burst period, the switching stage to switch the energy tank circuit.

US Pat. No. 9,312,028

METHOD FOR DETECTING PERMANENT FAULTS OF AN ADDRESS DECODER OF AN ELECTRONIC MEMORY DEVICE

STMICROELECTRONICS S.R.L....

1. A test module, comprising:
an error detecting module configured to detect an error at a first memory location having an address that corresponds to portions
of an address decoder;

a first submodule configured to write first test data to the first memory location in response to detection of the error;
a second submodule configured to write second test data to second memory locations having respective addresses that each correspond
to a subgroup of the portions of the address decoder in response to detection of the error, the second test data different
than the first test data;

a third submodule configured to read data from the first memory location after writing of the second test data by the second
submodule; and

a fourth submodule configured to compare the data read by the third submodule to the first test data and indicate that a fault
exists in the address decoder if the data read by the third submodule and first test data are not equal.

US Pat. No. 9,237,644

MANUFACTURING OF A HEAT SINK BY WAVE SOLDERING

STMicroelectronics S.r.l....

1. A method for producing an electronic assembly, comprising:
attaching an electronic device to a first surface of an electronic board including a set of vias passing through the electronic
board between the first surface and a second surface opposite the first surface,

attaching a heat sink precursor to the second surface of the electronic board, the heat sink precursor having a cavity facing
the set of vias, and

providing a wave of solder penetrating through at least one opening of the heat sink precursor into the cavity and penetrating
from the cavity into the set of vias, wherein the solder penetrating in the corresponding vias joins the electronic device
to the set of vias and the solder penetrating in the cavity joins the heat sink precursor to the vias to form a corresponding
heat sink.

US Pat. No. 9,160,223

RECTIFIER CIRCUIT, AND ENVIRONMENTAL ENERGY HARVESTING SYSTEM COMPRISING THE RECTIFIER CIRCUIT

STMicroelectronics S.r.l....

1. A rectifier circuit, comprising:
a first and a second diode electrically connected to one another to form a diode rectifier;
a first and a second switch connected in parallel, respectively, to the first and second diodes; and
a first biasing network coupled to control terminals of the first and second switches and configured to close, during a step
of turning-on of the rectifier circuit, the first and second switches by generating a first turning-on signal which is a function
of an input signal so as to generate at an output a rectified output signal;

wherein the first biasing network comprises:
a first charge pump connected to the control terminal of the second switch and configured to receive at an input the first
turning-on signal and generate at an output a first intermediate signal that is adapted to close the second switch; and

a first resistive element connected to the control terminal of the first switch and configured for biasing, by the first turning-on
signal, the control terminal of the first switch.

US Pat. No. 9,077,873

COLOR FILTER ARRAY DEFECT CORRECTION

STMICROELECTRONICS S.R.L....

1. An apparatus, comprising:
a detector circuit configured to detect whether a single-color pixel is located in a flat area or a non-flat area of a digital
image containing the single-color pixel, and to detect whether the single color pixel is defective based on whether the single-color
pixel is located in a flat area or a non-flat area and based on a noise curve associated with the single-color pixel; and

a corrector circuit configured, if the single-color pixel is detected to be defective, to correct the defective single-color
pixel with a flat-type correction if the single-color pixel is detected to be in a flat area and correcting the single-color
pixel with a non-flat-type correction if the single-color pixel is detected to be in a non-flat area.

US Pat. No. 9,986,631

ELECTRONIC POWER MODULE WITH ENHANCED THERMAL DISSIPATION AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. An electronic power module comprising:a case; and
a stack housed by the case and including:
a first substrate, including a first top metal region, a first bottom metal region, and a first insulating region arranged between the first top metal region and the first bottom metal region;
a first die integrating a first electronic component having one or more electrical-conduction terminals, the first die being mechanically and thermally coupled to a first face of the first substrate;
a second substrate, including a second top metal region, a second bottom metal region, and a second insulating region arranged between the second top metal region and the second bottom metal region, the second substrate extending over the first substrate and over the first die and having a first conductive path in the second bottom metal region;
a first coupling region of a sintered thermoconductive paste mechanically and thermally coupling the first die to the first substrate; and
a second coupling region of sintered thermoconductive paste mechanically, electrically, and thermally coupling said one or more electrical-conduction terminals of the first electronic component to the first conductive path of the second substrate,
wherein the first top metal region, first bottom metal region, and first insulating region of the first substrate have an area greater than an area of the second top metal region, second bottom metal region, and second insulating region of the second substrate.

US Pat. No. 9,423,474

INTEGRATED MULTILAYER MAGNETORESISTIVE SENSOR AND MANUFACTURING METHOD THEREOF

STMICROELECTRONICS S.R.L....

1. A magnetic-field sensor, comprising:
a substrate having a first surface and a second surface;
an insulating layer on the first surface;
a first magnetoresistor extending in the insulating layer and having a main axis of magnetization and a secondary axis of
magnetization;

a second magnetoresistor extending in the insulating layer and having a main axis of magnetization and a secondary axis of
magnetization, the main axis of magnetization of the second magnetoresistor extending in a direction transverse to the main
axis of magnetization of the first magnetoresistor and the secondary axis of magnetization of the second magnetoresistor extending
in a direction transverse to the secondary axis of magnetization of the first magnetoresistor;

a first magnetic-field generator configured to generate a first magnetic field having field lines along the main axis of magnetization
of the first magnetoresistor; and

a second magnetic-field generator configured to generate a second magnetic field having field lines along the main axis of
magnetization of the second magnetoresistor, wherein the first and second magnetoresistors extend in the insulating layer
at respective first and second distances from the first surface, the first and second distances being different from one another.

US Pat. No. 9,384,315

METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR ELECTRICAL AND THERMAL ANALYSIS AT A SUBSTRATE LEVEL

STMICROELECTRONICS S.R.L....

1. A non-transitory computer storage medium having stored thereon computer program code that, when executed by a processor,
performs the steps of:
generating a layout of an electronic circuit;
generating abstract data at a level of a substrate that are associated to the layout of said electronic circuit;
generating a grid of partitioning, with respect to a view regarding said abstract data, into meshes and nodes and applying
it to said substrate; and

extracting, on the basis of said partition grid, a list of nodes or netlist representing a thermal network that represents
the thermal behavior of the substrate or of portions or elements of the substrate,

wherein said netlist is configured for use in simulation operations, in particular of a SPICE type, for making an evaluation
of said thermal effects in said electronic circuit; and

supplying said netlist to one of an operation of simulation of the thermal behavior and an operation of coupled electro-thermal
simulation which simulates simultaneously both the electrical behavior and the thermal behavior of the electronic circuit
or of a device thereof, taking into account the interactions with the electronic circuit or with parts thereof.

US Pat. No. 9,356,655

METHOD OF OPERATING COMMUNICATION NETWORKS, CORRESPONDING COMMUNICATION NETWORK AND COMPUTER PROGRAM PRODUCT

STMICROELECTRONICS S.R.L....

1. A method of operating a Power Line Communications (PLC) network comprising a plurality of nodes coupled together and configured
to propagate PLC signals between the plurality of nodes, the method comprising:
selecting one of a plurality of combinations of nodes to define a plurality of branches, each branch having a partitioning
filter coupled to at least one node of a respective branch;

activating a respective partitioning filter coupled to the at least one node of the respective branch to partition the at
least one node within the respective branch to define a first configuration of a sub-network of the PLC network to counter
propagation of the PLC signals through the sub-network; and

de-activating the respective partitioning filter to define a second configuration of the sub-network to permit propagation
of the PLC signals through the respective branch.

US Pat. No. 9,286,382

METHOD AND SYSTEM FOR SIMULTANEOUS PLAYBACK OF AUDIO TRACKS FROM A PLURALITY OF DIGITAL DEVICES

STMicroelectronics S.r.l....

1. A method, comprising:
generating, using a master device of a communication network, a pilot signal including at least a portion of an audio track
and a synchronization signal;

transmitting the generated pilot signal;
receiving, by at least one other device of the communication network, the transmitted pilot signal;
retrieving, by the at least one other device and based on the pilot signal, a stored copy of the audio track; and
synchronizing playback of the audio track by the master device with playback of the retrieved copy of the audio track by the
at least one other device based on the synchronization signal included in the received pilot signal.

US Pat. No. 9,258,564

VISUAL SEARCH SYSTEM ARCHITECTURES BASED ON COMPRESSED OR COMPACT FEATURE DESCRIPTORS

STMicroelectronics S.r.l....

1. A vehicle visual search system, comprising:
at least four cameras, each camera configured to be positioned on one side of a vehicle and configured to capture corresponding
digital images, each of the cameras comprising:

a feature descriptor extraction circuit configured to receive the corresponding captured digital images and configured to
generate feature descriptors from the captured digital images; and

a descriptor encoding circuit coupled to the feature descriptor extraction circuit to receive the feature descriptors and
configured to generate compact feature descriptors from the feature descriptors wherein the descriptor encoding circuit generates
the compact feature descriptors by performing zero-thresholding on the feature descriptors to generate zero-threshold delimited
three-dimensional feature descriptors, quantizing the zero-threshold delimited three-dimensional feature descriptors to generate
quantized feature descriptors, and coding the quantized feature descriptors to generate the compact feature descriptors; and

an application processor connected through a wired network to each of the at least four cameras, the application processor
configured to receive the compact feature descriptors through the wired network and to process the received compact feature
descriptors to generate output information that is utilized in controlling the operation of the vehicle.

US Pat. No. 9,189,085

KEY ACTUATION DETECTION APPARATUS AND METHOD

STMicroelectronics S.r.l....

1. An apparatus, comprising:
a first key configured to be manually actuatable by a user, the first key having a mechanism operative to mechanically generate
vibrations in the first key that propagate outwardly from the first key along first, second, and third detection axes that
are perpendicular to each other, in response to actuation of the first key;

a key-actuation detection circuit coupled to the first key and configured to detect actuation of the first key, the key-actuation
detection circuit including an inertial-sensor circuit configured to detect the vibrations propagating from the first key
along the first, second, and third detection axes and to supply first, second, and third detection signals in response to
the detection of the vibrations acting along the first, second, and third detection axes, respectively;

a casing on which the first key is arranged;
a board coupled to the casing and rigidly coupled to the inertial-sensor circuit in a manner that enables the inertial-sensor
circuit to detect the vibrations that propagate through the casing from the first key along the first, second, and third detection
axes in response to actuation of the first key; and

a compliant-support device mounted between the casing and the board, the compliant support device configured to support the
board in a resting position and to enable the board to move along the third detection axis with respect to the casing,

wherein the first key includes a first mechanical-coupling element configured to exert a pressure on the board asymmetrically
with respect to the second detection axis in response to actuation of the first key and cause the board to be inclined and
rotate about the second detection axis.

US Pat. No. 9,191,033

CIRCUIT FOR ASYNCHRONOUS COMMUNICATIONS, RELATED SYSTEM AND METHOD

STMicroelectronics S.r.l....

1. A device, comprising:
input circuitry configured to detect data on a plurality of signal lines and to generate:
a first signal indicative of asynchronous data on said plurality of signal lines satisfying a stability criteria; and
a second signal indicative of said plurality of signal lines being de-asserted; and
output circuitry configured to generate a detection signal having:
a first value when said first signal is asserted; and
a second value when said second signal is asserted, wherein the output circuitry is configured to hold a current value of
the detection signal when the first and second signals are not asserted.

US Pat. No. 9,105,789

GEIGER-MODE AVALANCHE PHOTODIODE WITH HIGH SIGNAL-TO-NOISE RATIO, AND CORRESPONDING MANUFACTURING PROCESS

STMICROELECTRONICS S.R.L....

1. A semiconductor device comprising:
a first layer of semiconductor material having a first conductivity type;
a first region being in the first layer and having the first conductivity type;
a second region being in the first region, having a second conductivity type, said second region having
a plurality of fingers extending across said first region and being separated from one another by portions of the first region,
and

a ring being integral with and surrounding the plurality of fingers, said plurality of fingers defining a diode junction with
said first region, the portions of the first region having a width less than or equal to twice a depletion region depth of
the diode junction;

a third region being in the first layer below the ring of the second region, having the second conductivity type, and having
a dopant concentration greater than a dopant concentration of the ring of the second region;

an anode contact layer contacting said ring; and
a cathode contact layer laterally spaced apart from said first and second regions.

US Pat. No. 9,558,052

SAFE SCHEDULER FOR FINITE STATE DETERMINISTIC APPLICATION

STMicroelectronics Intern...

1. An embedded controller, comprising:
a functional logic module interface;
a task scheduler module arranged to schedule a finite number of events of one or more functional logic modules accessible
via the functional logic module interface, wherein the finite number of monitored events include a trigger of at least one
analog to digital conversion, a received indication of a completed analog to digital conversion, and an interaction with at
least one timer; and

a safety module, the safety module arranged to:
monitor the finite number of events;
incrementally create a mathematic check value, each increment based on at least one of the finite number of monitored events;
compare the mathematic check value to a pre-computed model check value; and
set a test result value based on the comparison.

US Pat. No. 9,323,268

LOW VOLTAGE ISOLATION SWITCH, IN PARTICULAR FOR A TRANSMISSION CHANNEL FOR ULTRASOUND APPLICATIONS

STMicroelectronics S.r.l....

1. A switching circuit, comprising:
a connection terminal;
an output terminal;
first and second voltage reference terminals;
first and second switching transistors electrically coupled in series to each other, and having respective body diodes coupled
in anti-series, between said connection terminal and said output terminal, the first switching transistor having a first control
terminal and the second switching transistor having a second control terminal;

a bootstrap circuit connected to the first and second control terminals and to the first and second voltage references and
including:

first and second bootstrap nodes;
a first parasitic capacitance electrically coupled directly between said first control gate terminal and the first bootstrap
node; and

a second parasitic capacitance electrically coupled directly between said second control gate terminal and the second bootstrap
node, the first and second parasitic capacitances having capacitance values of at least one order of magnitude lower than
gate-source capacitances of said first and second switching transistors.

US Pat. No. 9,196,714

IGBT DEVICE WITH BURIED EMITTER REGIONS

STMicroelectronics S.r.l....

1. An IGBT device integrated in a chip of semiconductor material including:
a substrate of a first type of conductivity,
an active layer of a second type of conductivity formed on an inner surface of the substrate,
a body region of the first type of conductivity extending within the active layer from a front surface thereof opposite the
inner surface,

a source region of the second type of conductivity extending within the body region from the front surface,
a channel region being defined within the body region between the source region and the active layer, a gate element insulated
from the front surface extending over the channel region,

a collector terminal contacting the substrate on a rear surface thereof opposite the inner surface,
an emitter terminal contacting the source region and the body region on the front surface,
a gate terminal contacting the gate element, and
at least one buried emitter region of the first type of conductivity with a concentration of impurities higher than a concentration
of impurities of the substrate being formed in a portion of the substrate, said at least one buried emitter region having
lateral sides and a bottom in contact with the substrate of the first type of conductivity,

wherein a further portion of the substrate is interposed between the bottom of the at least one buried emitter region and
the collector terminal defining an emitter resistor.

US Pat. No. 9,076,883

INTEGRATED ELECTRONIC DEVICE WITH TRANSCEIVING ANTENNA AND MAGNETIC INTERCONNECTION

STMicroelectronics S.r.l....

1. A semiconductor structure, comprising:
a semiconductor layer having top and bottom surfaces;
a first magnetic region disposed inside the semiconductor layer and having top and bottom surfaces;
a first insulating layer over the top surface of the first semiconductor layer;
a first winding formed wholly within said insulating layer above the top surface of the semiconductor layer and aligned with
the first magnetic region;

a second insulating layer mounted beneath the bottom surface of the semiconductor layer; and
a second winding formed wholly within said second insulating layer and aligned with the first magnetic region.

US Pat. No. 9,461,558

CONTROL DEVICE OF A SWITCHING POWER SUPPLY

STMicroelectronics S.r.l....

1. A device, comprising:
a switching converter having:
an input terminal configured to receive an alternating current supply voltage,
an output terminal configured to provide a regulated direct current voltage,
an inductor coupled between the input terminal and the output terminal,
a current detector configured to provide a sensed signal corresponding to a current that is equal or proportional to a current
through the inductor of the converter, and

a switch coupled between the inductor and a circuit ground; and
a control device configured to control closing and opening of said switch, said control device having:
a ramp voltage generator circuit configured to generate a ramp voltage,
a switch control circuit configured to open the switch based on a comparison of the ramp voltage with a first voltage, and
a generator control circuit configured to receive the sensed signal, receive a first reference signal having a value different
from zero, and synchronize the start of the ramp voltage with a crossing of the sensed signal and the first reference signal
while the switch is already in a closed state prior to the synchronization.

US Pat. No. 9,431,912

CONTROL DEVICE FOR RECTIFIERS OF SWITCHING CONVERTERS

STMicroelectronics S.r.l....

1. A control device for a rectifier of a switching converter, said control device comprising:
a zero crossing detector configured to detect a zero crossing of a current through a rectifier transistor of the rectifier
and output a zero crossing signal indicating a detection of the zero crossing;

a selectable slow discharge path configured to discharge a control terminal of the rectifier transistor to ground;
a selectable fast discharge path configured to discharge the control terminal of the rectifier transistor to ground more quickly
than the slow discharge path; and

a controller configured to enable the slow discharge path to discharge the control terminal of the rectifier transistor in
a normal operation condition and enable the fast discharge path to discharge the control terminal of the rectifier transistor
in response to the zero crossing signal indicating the zero crossing of the current through said rectifier transistor.

US Pat. No. 9,525,371

APPARATUS FOR DETECTING THE ROTOR POSITION OF AN ELECTRIC MOTOR AND RELATED METHOD

STMICROELECTRONICS S.R.L....

1. An apparatus for an electric motor having a plurality of windings and a rotor associated therewith, the apparatus comprising:
a circuit configured to couple at least two of the plurality of windings between a supply voltage and a reference voltage
according to a first current path and to discharge a current stored in the two windings according to a second current path,
said circuit configured to force the at least two windings to a short circuit condition in the second current path;

a measurement circuit configured to measure a time period of discharge of the current stored in the two windings between a
peak value of the current in the first current path and a portion of said peak value reached by the current in the second
path; and

a rotor position detector configured to detect a rotor position based on the measured time period of discharge of the current
in the second path.

US Pat. No. 9,469,109

MICROFLUID DELIVERY DEVICE AND METHOD FOR MANUFACTURING THE SAME

STMicroelectronics S.r.l....

1. A microfluidic device comprising:
a nozzle plate including a dielectric layer, a substrate layer, and a nozzle;
a chamber body, the chamber body including a semiconductor substrate, a dielectric layer over the semiconductor substrate,
and a semiconductor layer over the dielectric layer, the semiconductor layer being a layer of epitaxial polysilicon and the
semiconductor substrate being a silicon substrate;

a chamber at least partially formed in the semiconductor layer and covered by the nozzle plate, the chamber in fluid communication
with the nozzle; and

a fluid inlet comprising an aperture through the chamber body and in fluid communication with the chamber.