US Pat. No. 9,222,974

SYSTEM AND METHOD FOR REDUCING VOLTAGE DROP DURING AUTOMATIC TESTING OF INTEGRATED CIRCUITS

STMicroelectronics Intern...

1. A device, comprising:
a test circuit having a plurality of switchable components and including a plurality of LBIST partitions;
a clock circuit coupled to the test circuit and configured to switch the plurality of switchable components; and
a voltage-drop reduction circuit coupled to the test circuit and coupled to the clock circuit and configured to adjust the
switching of the plurality of switchable components, the voltage-drop reduction circuit including a respective LBIST controller
coupled to each of the plurality of LBIST partitions each LBIST controller configured to respectively asynchronously switch
each of the plurality of LBIST partitions.

US Pat. No. 9,466,347

ROW DECODER FOR NON-VOLATILE MEMORY DEVICES AND RELATED METHODS

STMICROELECTRONICS INTERN...

1. An integrated circuit comprising:
an array of phase-change memory (PCM) cells;
a plurality of wordlines coupled to the array of PCM cells; and
a row decoder circuit coupled to the plurality of wordlines, the row decoder circuit comprising
a first low voltage logic gate,
a first high voltage level shifter having an output coupled to an input of the first low voltage logic gate, the high voltage
being greater than the low voltage,

a second low voltage logic gate,
a second high voltage level shifter having an output coupled to an input of the second low voltage logic gate,
a first low voltage logic circuit having an output coupled to the input of the second low voltage logic gate,
a second low voltage logic circuit having an output coupled to the input of the second low voltage logic gate, and
a low voltage wordline driver having an input coupled to the outputs of the first and second low voltage logic gates, and
an output coupled to a selected wordline of the plurality of wordlines.

US Pat. No. 9,245,200

METHOD FOR DETECTING A STRAIGHT LINE IN A DIGITAL IMAGE

STMicroelectronics S.r.l....

1. An apparatus, comprising:
an edge-detector circuit configured to identify an edge within an image that includes a boundary, the edge including a plurality
of pixels; and

a straight-line-detector circuit configured to identify,
a first straight line that intersects a first pixel of the identified edge with a first identifier that indicates at least
two points at which the first straight line intersects the boundary,

a second straight line that intersects a second pixel of the identified edge with a second identifier that indicates at least
two points at which the second straight line intersects the boundary,

an edge straight line representing the identified edge based on the first and second identifiers,
wherein the straight-line detector circuit is further configured to,
quantize a two-dimensional parameter space, defined by determined first and second identifiers, according to a predetermined
quantization map, including dividing the boundary into a plurality of segments and assigning a unique index to each segment
of the plurality of segments,

generate an accumulation space by accumulating the determined first and second identifiers in the quantized two-dimensional
parameter space, and

detect the straight line based on a distribution of the determined first and second identifiers in the accumulation space;
determine the unique indices of those segments of the plurality of segments, which comprise an intersection, to thereby detect
the at least two points of intersection for each straight line, and

select two unique indices out of the determined unique indices for each of the straight lines to determine the first and second
identifiers.

US Pat. No. 9,521,723

INTEGRATED DEVICE COMPRISING A MATRIX OF OLED ACTIVE PIXELS WITH IMPROVED DYNAMIC RANGE

STMicroelectronics Intern...

1. A device, comprising:
a semiconductor substrate having first and second parts electrically insulated from one another; and
a pixel formed in the semiconductor substrate and comprising:
an OLED diode, and
a control circuit comprising:
a first transistor formed in the first part of the semiconductor substrate and having a gate, a body, and a source, the source
of the first transistor being coupled to the body of the first transistor and to the OLED diode, and

a refresh circuit comprising a second transistor formed in the second part of the semiconductor substrate and being coupled
to the gate of the first transistor;

wherein the first transistor is an nMOS transistor and the second transistor is an nMOS transistor.

US Pat. No. 9,325,490

REFERENCELESS CLOCK AND DATA RECOVERY CIRCUIT

STMicroelectronics Intern...

1. A device, comprising:
a data input configured to receive a stream of data bits;
a first detection loop part coupled to the data input and configured to compare a phase of the stream of data bits to that
of a first clock signal and generate a phase error signal based thereupon;

a second detection loop part coupled to the data input and configured to compare a frequency of the stream of data bits to
that of a second clock signal and generate a frequency error signal based thereupon; and

a common loop part comprising a voltage controlled oscillator coupled to the first and detection loop parts and configured
to generate the first and second clock signals as a function of a sum of the phase error signal and the frequency error signal;

wherein the first clock signal and second clock signal are in quadrature with each other.

US Pat. No. 9,390,786

METHOD OF MINIMIZING THE OPERATING VOLTAGE OF AN SRAM CELL

STMicroelectronics SA, M...

1. An integrated SRAM memory cell, comprising:
a silicon on insulator substrate including a semiconductor layer, an insulating layer and a semiconductor support;
an n-channel transistor having source, channel and drain regions formed in said semiconductor layer;
a p-channel transistor having source, channel and drain regions for in said semiconductor layer;
a doped well region in said semiconductor support located under said n- and p-channel transistors; and
a circuit configured to apply a variable bias voltage to said doped well region, wherein said circuit is configured to:
carry out measurements representative of a threshold voltage of the n-channel transistor and of a threshold voltage of the
p-channel transistor; and

adjust the variable bias voltage so that the threshold voltages of the n-channel transistor and of the p-channel transistor
are substantially equal to n and p target threshold voltages, respectively.

US Pat. No. 9,419,634

LOW-NOISE MULTIPLE PHASE OSCILLATOR

STMICROELECTRONICS SA, M...

1. A multiple phase oscillator, comprising:
a master oscillator;
a first ring oscillator connected to be injection locked to the master oscillator and having a first free-running frequency
adjustable through a control signal;

a second ring oscillator having a same structure as the first ring oscillator, the second ring oscillator not injection locked
to the master oscillator and operating in free-running mode having a second free-running frequency adjustable through said
control signal; and

a control loop connected to an output of the second ring oscillator and configured to adjust the control signal so that the
second free-running frequency of the second ring oscillator matches a desired value.

US Pat. No. 9,331,474

OVER-VOLTAGE PROTECTION CIRCUIT FOR A DRIVE TRANSISTOR

STMICROELECTRONICS INTERN...

1. A circuit, comprising:
a drive transistor having a control terminal configured to receive a drive signal and having a first conduction terminal and
a second conduction terminal, wherein said first conduction terminal is configured for connection to a load circuit;

a sense circuit configured to sense a voltage across the first and second conduction terminals;
a comparator circuit configured to compare the sensed voltage to voltage threshold and generate a signal indicative of an
over-voltage condition; and

drive circuitry configured to generate said drive signal in response to a pulse width modulation (PWM) signal, said drive
circuit including a force on circuit actuated in response to said signal indicative of the over-voltage condition to force
said drive transistor to turn on irrespective of the PWM signal.

US Pat. No. 9,245,606

SRAM MEMORY DEVICE AND TESTING METHOD THEREOF

STMICROELECTRONICS INTERN...

1. An integrated circuit, comprising:
a static random-access memory (SRAM) array having a plurality of memory cells;
a driving circuit configured to receive an internal clock signal; and
a controller configured to:
receive an external clock signal formed by a succession of external pulses;
generate the internal clock signal having a succession of internal pulses;
generate in a first mode, for each external pulse, a corresponding internal pulse;
control in the first mode the driving circuit to carry out one access to the memory array for each internal pulse;
generate in a second mode, for each external pulse, a pair of internal pulses, the pair of internal pulses including a first
pulse and a second pulse, the first pulse occurring before the second pulse;

direct in the second mode, upon receiving a first pulse of said pair of internal pulses, the driving circuit to write a first
data item in a set of memory cells;

direct in the second mode, upon receiving a second pulse of said pair of internal pulses, the driving circuit to read said
set of memory cells to acquire a second data item;

compare the first data item with the second data item; and
detect at least one faulty memory cell based on the comparison of the first and second data items.

US Pat. No. 9,432,648

ADAPTIVE PAL FIELD COMBER

STMicroelectronics Intern...

1. A video decoder comprising:
an adaptive comb configured to generate a combed video image from an image signal; and
an adaptive comb controller comprising:
at least one of a vertical image correlator and a spatio-temporal image correlator configured to generate an output signal
representing at least one of a vertical image correlation value of the image signal and a spatio-temporal image correlation
value of the image signal,

a field motion detector configured to determine a field motion value as a function of field motion between adjacent fields
of the combed video image and to, based thereupon, generate the output signal representing the field motion value; and

controller logic configured to generate a control signal to cause the adaptive comb to selectively comb using 2D combing,
frame combing, or field combing based upon the output signal;

wherein the adaptive comb comprises at least one blender configured to receive signals from a frame comb and a field comb;
wherein the at least one blender is configured to selectively combine the received signals dependent on the control signal;
wherein the control signal causes the frame comb to process a region dependent on the spatio-temporal image correlator determining
the field motion value to be less than a first motion threshold value; and

wherein the control signal causes the field comb to process the region dependent on the spatio-temporal image correlator determining
the field motion value to be indicative of motion, to be greater than the first motion threshold value, and to be less than
a second motion threshold value.

US Pat. No. 9,419,952

MEMORY ENCRYPTION METHOD COMPATIBLE WITH A MEMORY INTERLEAVED SYSTEM AND CORRESPONDING SYSTEM

STMICROELECTRONICS (GRENO...

1. A method for managing an encrypted global interleaved memory space physically implemented according to an interleaving
addressing scheme in encrypted memory banks of a plurality of memories respectively belonging to a plurality of channels,
the encrypted global interleaved memory space being addressable with transactions through the interleaving addressing scheme
for routing each transaction to a channel containing a physical memory location corresponding to a transaction address in
accordance with the interleaving addressing scheme, and a range of addresses of an interleaved memory zone being equal to
an address interleaving step, the method comprising:
providing each channel with a local address pointer configured to be incrementally moved along the encrypted global interleaved
memory space each time the encrypted global interleaved memory space is addressed at a current address pointed by the local
address pointer;

addressing the encrypted global interleaved memory space from the channel with a specific transaction at the current address
in an absence of movement of the local address pointer during a time period;

re-encrypting data located at the current address with a new encryption key and incrementing the local address pointer to
its next position upon reception at the channel of the specific transaction having been initiated by the channel; and

if the specific transaction was initiated by another channel, discarding the specific transaction and sending an error transaction
to that another channel, and incrementing a local address pointer of the another channel by the address interleaving step
upon receiving the error transaction.

US Pat. No. 9,146,854

RESTORING STORAGE DEVICES BASED ON FLASH MEMORIES AND RELATED CIRCUIT, SYSTEM, AND METHOD

STMicroelectronics Intern...

1. A method, comprising:
detecting a plurality of conflicting physical memory blocks for a corrupted logical memory block using a plurality of validity
indexes, each index being associated with at least one physical memory block and indicating the number of valid sectors of
the corrupted logical memory block stored in the at least one respective physical memory block;

selecting one of the physical memory blocks by comparing the validity indexes;
discarding data stored in each of the non-selected conflicting physical memory blocks;
selecting physical memory sectors in the selected physical memory block using a completion flag stored for each physical memory
sector, the completion flag including a plurality of bits having a first value indicating data of a logical memory sector
was properly stored in the physical memory sector, a second value indicating data of the physical memory sector has been erased,
and a plurality of additional values different than the first or second values where each of these additional values indicates
data was not properly stored in the corresponding physical memory sector; and

providing data for a logical memory sector of the logical memory block from the selected physical memory sector.

US Pat. No. 9,256,233

GENERATING A ROOT OF AN OPEN-LOOP FREQENCY RESPONSE THAT TRACKS AN OPPOSITE ROOT OF THE FREQUENCY RESPONSE

STMicroelectronics Intern...

1. An electronic circuit, comprising:
a feedback-coupled circuit stage including a drive circuit configured to drive a load, said drive circuit having a control
input; and

a compensation circuit stage coupled to the feedback-coupled stage;
wherein the compensation circuit stage comprises a capacitor coupled in series with a compensation transistor at the control
input, said compensation transistor configured to exhibit a variable transconductance that is dependent on a voltage signal
replicating voltage across the load and a current signal replicating current in the load.

US Pat. No. 9,165,237

SIM CARD ADAPTER

STMICROELECTRONICS S.R.L....

1. A subscriber identification module (SIM) card adapter assembly comprising:
a SIM card support comprising a first portion having a first thickness, and a second portion having a second thickness greater
than the first thickness;

a SIM card removably attached to the first portion, with the SIM card configured to be received by a SIM slot having a first
size; and

at least one SIM card adapter removably attached to the second portion, with the at least one SIM card adapter configured
to be received by a SIM slot having a second size different from the first size, and with the at least one SIM card adapter
also configured to receive the SIM card so as to adapt the SIM card to the second size SIM slot.

US Pat. No. 9,075,947

INPUT/OUTPUT CELL DESIGN FOR THIN GATE OXIDE TRANSISTORS WITH RESTRICTED POLY GATE ORIENTATION

STMicroelectronics Intern...

1. An integrated circuit including an input/output circuit, comprising:
a first section in which first transistors powered from a higher supply voltage and having a first thickness gate oxide are
located;

a second section in which second transistors powered from a lower supply voltage and having a second thickness gate oxide,
thinner than the first thickness, are located;

wherein said second section includes at least one layout section having a square shaped perimeter including a first edge and
a second edge adjacent to the first edge and including second transistors with transistor gates oriented in a single common
direction; and

wherein said at least one layout section further includes:
a plurality of first connection pins coupled to said second transistors and which are oriented to extend inwardly from and
perpendicular to said first edge; and

a plurality of second connection pins coupled to said second transistors and which are oriented to extend inwardly from and
perpendicular to said second edge.

US Pat. No. 9,432,008

VARIABLE DELAY ELEMENT

STMicroelectronics Intern...

1. A delay circuit comprising:
an input node;
an output node;
a first transistor of a first conductivity type, the first transistor having a control node coupled to the input node, a first
main current node coupled to a first supply voltage node, and a second main current node coupled to the output node through
a third transistor;

a second transistor of a second conductivity type, the second transistor having a control node coupled to the input node,
a first main current node coupled to a second supply voltage node, and a second main current node coupled to the output node
through a fourth transistor;

the third transistor having the first conductivity type and having a control node, wherein the first main current node of
the first transistor is coupled to the first supply voltage node via the third transistor;

the fourth transistor having the second conductivity type and having a control node, wherein the first main current node of
the second transistor is coupled to the second supply voltage node via the fourth transistor; and

a biasing circuit having a first differential control voltage output coupled to a further control node of the first transistor
and a second differential control voltage output coupled to a further control node of the second transistor.

US Pat. No. 9,234,938

MONITORING ON-CHIP CLOCK CONTROL DURING INTEGRATED CIRCUIT TESTING

STMICROELECTRONICS INTERN...

1. An On-Chip Clock (OCC) circuit of an integrated circuit having logic blocks coupled in scan chains, the OCC circuit comprising:
a clock generator configured to generate a plurality of clock signals;
an OCC controller configured to receive the plurality of clock signals and output a plurality of shift/capture clock signals
for use by the scan chains of logic blocks, the plurality of shift/capture clock signals comprising at least two consecutive
at-speed capture clock pulses; and

an OCC monitor configured to provide a verification of OCC operation based upon the at least two consecutive at-speed capture
clock pulses.

US Pat. No. 9,294,106

CAPACITANCE MULTIPLIER AND LOOP FILTER NOISE REDUCTION IN A PLL

STMicroelectronics Intern...

1. A circuit comprising:
a first charge pump configured to generate a first current at a first node;
a second charge pump configured to generate a second current at a second node, the second current being different than the
first current;

a loop filter coupled between the first and second nodes, the loop filter comprising:
a first filter path comprising a first capacitor coupled between the first node and a reference voltage node;
a second filter path comprising a second capacitor and a resistor, the second capacitor being coupled between the second node
and the reference voltage node, the resistor being coupled to the second node; and

an isolation buffer comprising an operational amplifier interposed between the first and second filter paths, the first node
being coupled to a first input of the operational amplifier, the resistor of the second filter path being coupled between
an output of the operational amplifier and the second node, the resistor being directly connected to the output of the operational
amplifier; and

an oscillator having a first input and a second input, the first input coupled to the first node, the second input coupled
to the second node, the second node being between the output of the operational amplifier and the second input of the oscillator.

US Pat. No. 9,391,769

SERIAL TRANSMISSION HAVING A LOW LEVEL EMI

STMicroelectronics (Greno...

16. A device, comprising:
a scrambler configured to scramble an input serial data signal using a pseudo-random sequence, producing a scrambled serial
data signal;

an alternative-signal generator configured to generate an alternative serial data signal based on the input serial data signal,
the alternative serial data signal having a delay corresponding to a delay introduced by the scrambler;

repeat-tracking circuitry configured to monitor a number of consecutive occurrences of a data pattern of several bits in the
scrambled serial data signal;

a multiplexer configured to select one of the scrambled serial data signal and the alternative serial data signal based on
the monitoring; and

output circuitry configured to generate an output signal using the selected one of the scrambled serial data signal and the
alternative serial data signal.

US Pat. No. 9,385,708

METHODOLOGY TO AVOID GATE STRESS FOR LOW VOLTAGE DEVICES IN FDSOI TECHNOLOGY

STMicroelectronics Intern...

1. A device comprising:
a first semiconductor substrate;
a dielectric layer on the first semiconductor substrate;
a second semiconductor substrate on the dielectric layer and separated from the first semiconductor substrate by the dielectric
layer;

a gate dielectric layer on the second semiconductor substrate;
a plurality of transistors each respectively including:
a gate terminal on the gate dielectric layer and separated from the second semiconductor substrate by the gate dielectric
layer;

a channel region in the second semiconductor substrate below the gate terminal; and
a source and drain region in the second semiconductor substrate, the source and the gate terminal being electrically connected;
a voltage source coupled to the first semiconductor substrate and configured to turn the plurality of transistors on or off
by applying a high voltage or a low voltage to the first semiconductor substrate.

US Pat. No. 9,167,378

METHOD TO ACCESS MULTIMEDIA CONTENTS ASSOCIATED TO A GEOGRAPHICAL AREA

STMICROELECTRONICS INTERN...

1. A method of accessing a plurality of multimedia contents associated with a geographical area including a plurality of items,
each multimedia content being stored in a multimedia content provider and including information of at least one of the items,
the method comprising:
providing an IC card application for a mobile device to execute the following
detect the geographical area and send the detected geographical area to a memory of an IC card, with the geographical area
being detected by identifying the geographical area from among a list of geographical areas stored in the memory of the IC
card,

connect to the multimedia content provider and select content from the plurality of multimedia content associated with the
detected geographical area,

download and send the selected multimedia content to the memory of the IC Card, and
receive an identification code associated with an item of the plurality thereof located in the detected geographical area
and access information about the item in the selected multimedia content.

US Pat. No. 9,167,023

POWER MEASUREMENT CIRCUIT

STMICROELECTRONICS INTERN...

1. A method for measuring power consumed by a mobile wireless communications device, the method comprising:
modulating a carrier signal based on a sensed voltage across a power source;
combining the modulated carrier signal with at least one wireless communication signal received by the mobile wireless communications
device;

converting the combined signal to a digital combined signal; and
demodulating a digitized modulated carrier signal from the digital combined signal to estimate the power consumed by the mobile
wireless communications device.

US Pat. No. 9,305,633

SRAM CELL AND CELL LAYOUT METHOD

STMicroelectronics Intern...

1. An array of static random access memory (SRAM) cells comprising:
a plurality of overlapping rectangular regions, each of the overlapping rectangular regions comprises:
an entire first SRAM cell;
a portion of a second adjacent SRAM cell in a first corner region of the rectangular region; and
a portion of a third adjacent SRAM cell in a second corner region of the rectangular region, the second corner region being
opposite the first corner region.

US Pat. No. 9,258,008

ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

STMicroelectronics Intern...

1. An analog-to-digital converter, comprising:
an input configured to receive an analog signal;
a conversion circuit configured to convert the analog signal to a digital representation of the analog signal; and
a delay circuit coupled to the conversion circuit and configured to trigger the conversion circuit with a logic signal;
wherein the delay circuit comprises a first comparator having a first input and second input, each input coupled to the conversion
circuit, the first comparator configured to generate the logic signal at a variable interval that is inversely proportional
to a voltage difference between a signal on the first input and a signal on the second input.

US Pat. No. 9,235,345

METHOD AND SYSTEM FOR CONTROLLING LOSS OF RELIABILITY OF NON-VOLATILE MEMORY

STMICROELECTRONICS INTERN...

1. A method for controlling a loss of reliability of a non-volatile memory (NVM) comprising:
determining whether a portion of the NVM is reliable using an operating system (OS) by at least
writing with a weak update mechanism a prescribed pattern in a prescribed location of the NVM,
retrieving a stored pattern from the prescribed location of the NVM,
comparing the prescribed pattern with the stored pattern, and
determining that the portion of the NVM is unreliable, if the prescribed pattern is different from the stored pattern;
generating a data retention warning associated with the reliability of the NVM using the OS;
communicating the data retention warning to an application operatively coupled to the OS if the portion of the NVM is determined
to be unreliable; and

dividing the NVM into a plurality of different areas comprising a first memory area for storing data to be updated and a second
memory area for storing other data, the OS detecting events associated with the data retention warning only over the second
area.

US Pat. No. 9,306,550

SCHMITT TRIGGER IN FDSOI TECHNOLOGY

STMicroelectronics Intern...

1. An integrated circuit die:
a first inverter including;
a first transistor having a first gate, a second gate, a channel region, a source, and a drain;
a second transistor having a first gate, a second gate, a channel region, a source, and a drain coupled to the drain of the
first transistor;

an input coupled to the first gates of the first and second transistors; and
an output coupled to drain terminals of the first and second transistors;
a second inverter including:
an input coupled to the output of the first inverter; and
an output coupled configured to supply an output signal to the second gates of the first and second transistors;
an insulator layer;
a first semiconductor substrate on the insulator layer, the channel regions, the sources, and the drains of the first and
second transistors being positioned in the first semiconductor substrate;

a gate dielectric on the first semiconductor substrate, the first gates of the first and second transistors being separated
from the first semiconductor substrate by the gate dielectric; and

a second semiconductor substrate separated from the first semiconductor substrate by the insulator layer, the second gates
of the first and second transistors being positioned in the first semiconductor substrate and separated from the respective
channel regions by the insulator layer.

US Pat. No. 9,236,140

COMPLEMENTARY READ-ONLY MEMORY (ROM) CELL AND METHOD FOR MANUFACTURING THE SAME

STMICROELECTRONICS INTERN...

1. A ROM unit comprising an array of complementary ROM cells, each complementary ROM cell comprising:
a transistor; and
a bit line and a complementary bit line disposed adjacent the transistor;
wherein a drain terminal of the transistor is configured to be connected to one of the bit line and the complementary bit
line based on data programmed in the ROM cell.

US Pat. No. 9,459,447

MOEMS APPARATUS AND A METHOD FOR MANUFACTURING SAME

STMICROELECTRONICS INTERN...

1. An apparatus, comprising:
a double active layer silicon on insulator substrate including a first active layer separated from a second active layer by
an insulating layer;

a first plurality of comb teeth formed in the first active layer and defined by a first plurality of cavities;
a second plurality of comb teeth formed in the second active layer and defined by a second plurality of cavities;
wherein an aspect ratio of the first and second pluralities of cavities defining the first and second pluralities of comb
teeth is greater than 1:20.

US Pat. No. 9,436,610

ENHANCED PRE-FETCH IN A MEMORY MANAGEMENT SYSTEM

STMicroelectronics Intern...

18. A method comprising:
sending page table walk requests to a page table descriptor in a main memory system and receive address translation information
from the page table descriptor, the page table walk requests including information that specifies an amount of further address
translation information, using a memory management unit;

receiving the further address translation information from the page table descriptor, using the memory management unit;
intercepting the page table walk requests, using a cache unit;
modifying content of the intercepted page table walk requests such that the information that specifies the amount of further
address translation information is extended from a first amount to a second amount, the second amount being greater than the
first amount, using the cache unit;

storing the second amount of further address translation information for use in connection with data requests that are subsequent
to a current data request, using the cache unit;

providing the address translation information based upon an intercepted page table walk request being associated with address
translation information already stored in the cache unit from a data request that is prior to the current data request.

US Pat. No. 9,239,588

METHOD AND SYSTEM FOR CALCULATING A CLOCK FREQUENCY OF A CLOCK SIGNAL FOR AN IC CARD

STMICROELECTRONICS INTERN...

1. A method for calculating a clock frequency of a clock signal received by an IC card, and comprising:
receiving a first time-stamp from a terminal;
setting a first timer value of a timer of the IC card and starting the timer when the first time-stamp is received;
receiving a second time-stamp from the terminal;
reading a second timer value of the timer when the second time-stamp is received; and
calculating the clock frequency based on comparing a difference between the second and first timer values, and a difference
between the second and first time-stamps.

US Pat. No. 9,159,425

NON-VOLATILE MEMORY WITH REDUCED SUB-THRESHOLD LEAKAGE DURING PROGRAM AND ERASE OPERATIONS

STMicroelectronics Intern...

1. A circuit, comprising:
a non-volatile memory cell including an NMOS select transistor and a floating gate transistor connected to the NMOS select
transistor in series between a bit line and a source line, the memory cell configurable for operation in a programming mode;
and

a selection circuit configured to drive a gate terminal of the NMOS select transistor with a negative bias voltage in response
to said memory cell being configured in programming mode to program a data value into said floating gate transistor while
said negative bias voltage produces both a negative gate-to-source voltage and a negative gate-to-well voltage on said NMOS
select transistor.

US Pat. No. 9,129,685

WORD-LINE DRIVER FOR MEMORY

STMICROELECTRONICS INTERN...

1. A memory comprising:
a memory array having memory cells arranged in a plurality of rows wherein each of the rows is controlled by a corresponding
word-line; and

a plurality of word-line drivers, wherein each of the word-line drivers is configured to drive the corresponding word-line
based at least on a first sub-group selection signal, a second sub-group selection signal, and group selection signals comprising
a first group selection signal, a second group selection signal and a third group selection signal, and wherein each word-line
driver comprises,

a first transistor having a gate terminal driven by the first group selection signal, a first conduction terminal driven by
the second sub-group selection signal, and a second conduction terminal coupled to the corresponding word-line;

a second transistor having a gate terminal driven by the second group selection signal, a second conduction terminal driven
by the second sub-group selection signal, and a first conduction terminal coupled to the corresponding word-line; and

a third transistor having a gate terminal driven by the third group selection signal, a first conduction terminal driven by
the first sub-group selection signal, and a second conduction terminal coupled to the corresponding word-line, wherein the
first group selection signal, the second group selection signal, the third group selection signal, the first sub-group selection
signal, and the second sub-group selection signal are in a first operative configuration in a memory program/read operation,
are in a second operative configuration in a memory erase operation, and are in a third operative configuration in a memory
erase verify operation, wherein the word-line driver is configured to select the word-line for a memory program operation
and a memory read operation when the second group selection signal and the second sub-group selection signal are at a first
voltage, and the first group selection signal, the third group selection signal and the first sub-group selection signal are
at a second voltage different than the first voltage, and wherein the word-line driver is configured to select the word-line
for the memory erase operation when the first and third group selection signals and the first and second sub-group selection
signals are at a negative voltage, and the second group selection signal is at a zero voltage.

US Pat. No. 9,436,432

FIRST-IN FIRST-OUT (FIFO) MEMORY WITH MULTI-PORT FUNCTIONALITY

STMICROELECTRONICS INTERN...

1. A first-in first-out (FIFO) memory providing multi-port functionality, the FIFO memory comprising:
a plurality of single-port memory structures, each single port memory structure having a plurality of addresses to read and
write data thereto;

an indexing block configured to store, for each data write operation, a unique memory identifier corresponding to a single-port
memory structure in which the data write operation is performed; and

an access controller configured to control operations in the single-port memory structures based on contents of the indexing
block,

wherein the access controller is configured to perform a plurality of write operations to the plurality of single-port memory
structures in a single clock cycle,

and
wherein the access controller is further configured to continue at least one write operation of the plurality of write operations
in the single clock cycle to a write address of a different single port memory structure of the plurality of single-port memory
structures during the single clock cycle whenever there is a read and write operation request at a same time on one of the
plurality of single-port memory structures.

US Pat. No. 9,395,730

VOLTAGE REGULATOR

STMICROELECTRONICS INTERN...

1. An apparatus, comprising:
a plurality of devices forming a positive feedback loop for driving a regulated output voltage towards a reference voltage,
the plurality of devices including:

a sensing element configured to sense a change in the regulated output voltage, and
a control element configured to generate a control signal in response to an indication of the sensed change in the regulated
output voltage; and

a ratio of a transductance of the sensing element to a transductance of the control element being set to provide that the
positive feedback loop is stable.

US Pat. No. 9,225,321

SIGNAL SYNCHRONIZING SYSTEMS AND METHODS

STMicroelectronics Intern...

1. A signal synchronizing system comprising:
a sequential logic circuit comprising:
a first sequential logic circuit configured to receive an input signal and generate a first intermediate signal from the input
signal based on a single clock signal, the first sequential logic circuit comprising a first-stage flip flop coupled in series
to a second-stage flip flop, the first-stage flip flop and second-stage flip flop being clocked by the single clock signal;

a second sequential logic circuit to receive the input signal and generate a second intermediate signal from the input signal
based upon an inverse of the single clock signal, the second sequential logic circuit comprising a first-stage flip flop coupled
in series to a second-stage flip flop, the first-stage flip flop and second-stage flip flop being clocked by the inverse of
the single clock signal; and

a logic circuit configured to combine the first and second intermediate signals to generate an output signal, the logic circuit
comprising a first logic gate to receive the first intermediate signal and the second intermediate signal and a second logic
gate to receive the first intermediate signal and the second intermediate signal.

US Pat. No. 9,337,851

PHASE LOCKED LOOP CIRCUIT EQUIPPED WITH UNITY GAIN BANDWIDTH ADJUSTMENT

STMicroelectronics Intern...

1. An electronic circuit comprising:
a digital phase locked loop;
a measurement stage that includes a frequency-to-current converter, the measurement stage configured to measure and adjust
a gain of the phase locked loop; and

a current comparator that triggers operation of the measurement stage.

US Pat. No. 9,306,627

ACTIVE PASSIVE NEAR FIELD COMMUNICATION ANTI-COLLISION METHOD, INITIATOR AND TAG

STMICROELECTRONICS INTERN...

1. A near field communication (NFC) anti-collision method, comprising the steps of:
broadcasting by an NFC initiator device a poll request signal in accordance with an initiation process, wherein the poll request
signal includes a sequence of introduction vectors each coupled to an allocation vector;

responding by at least one NFC listening device responding to the poll request signal to transmit a poll response signal;
wherein responding comprises:
receiving each introduction vector at the at least one NFC listening device;
reading an embedded introduction vector stored in the at least one NFC listening device;
comparing each received introduction vector to the embedded introduction vector stored in the at least one NFC listening device;
and

in response to a match of the received introduction vector and embedded introduction vector, transmitting a poll response
signal in accordance with timing determined from the allocation vector coupled to the matched received introduction vector.

US Pat. No. 9,306,630

NEAR FIELD COMMUNICATION ENABLED DEVICE WITH IMPROVED ELECTROMAGNETIC COMPATIBILITY AND A METHOD OF LOAD MODULATING IN NEAR FIELD COMMUNICATION

STMicroelectronics Intern...

1. An NFC enabled device capable of operating in a target mode, comprising:
a device antenna circuit;
a load modulator connected to the device antenna circuit and configured to load modulate a radio frequency magnetic field
by altering the voltage amplitude of a carrier wave applied at terminals of the device antenna circuit, wherein the modulation
transitions between high and low values to transmit a digital signal,

wherein the load modulator alters the voltage amplitude of the carrier wave applied at the terminals of the drive antenna
circuit by:

applying a sequence of resistances of different values across the terminals in a first predefined order during a first transition
between a high value and a low value, and

applying the sequence of resistances of different values across the terminals in a second predefined order opposite from the
first predefined order during a second transition between the low value and the high value,

a controller configured to impose a waveform on each transition by the load modulator which is a truncated step response of
a low pass filter so as to attenuate generation of out of band higher order harmonics.

US Pat. No. 9,300,317

ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER

STMICROELECTRONICS INTERN...

1. An analog to digital converter, comprising:
a differencing circuit configured to receive as input a sampled differential input voltage and a fraction of a reference voltage
and to generate a differential output voltage representing a difference between the sampled differential input voltage and
the fraction of the reference voltage;

a delay circuit configured to generate a delay signal having a delay value that is a function of said differential output
voltage;

a comparison circuit configured to receive as input the differential output voltage and to generate an output signal as a
function of a sign of the differential output voltage when triggered by a trigger signal derived from the delay signal; and

control logic configured to receive the output signal and generate said fraction of the reference voltage as a function of
the output signal.

US Pat. No. 9,407,224

DIGITAL MICROPHONE DEVICE WITH EXTENDED DYNAMIC RANGE

STMicroelectronics Intern...

1. An apparatus, comprising:
a digital microphone device configured to provide a single-bit Pulse Density Modulation (PDM) output signal the device including:
a microphone configured to convert an acoustic input signal into an analog electrical signal;
a preamplifier, having a variable gain based on a gain control signal, the preamplifier being configured to receive the analog
electrical signal and to provide an amplified analog electrical signal that depends on the variable gain;

an Analog-to-Digital Converter, configured to receive the amplified analog electrical signal and to provide a digital signal;
a compensation circuit, configured to receive the digital signal, to perform a digital operation on the digital signal, and
based on a compensation signal generate a compensated signal;

an Automatic Gain Controller, configured to detect the digital signal, to generate said gain control signal based on the detected
digital signal, and to output the gain control signal to the preamplifier, the Automatic Gain Controller block configured
to generate said compensation signal based on the gain control signal, and to provide the compensation signal to the compensation
block, to compensate a variation of the digital signal resulting from the variable gain of the preamplifier; and

a conversion circuit, configured to receive the compensated signal and to convert it into the single-bit PDM output signal.

US Pat. No. 9,276,477

DC-DC CONVERTER WITH ENHANCED AUTOMATIC SWITCHING BETWEEN CCM AND DCM OPERATING MODES

STMicroelectronics Intern...

1. A DC-DC converter operative to receive a source DC voltage and provide an output DC voltage to a load, comprising:
a power stage comprising first and second transistors connected in series between a first source voltage level and a second
source voltage level;

an inductor connected between a node connecting the first and second transistors and the load and operative to provide an
inductor current from the DC-DC converter to the load; and

control logic operative to generate control pulses to the power stage operative to cause the transistors to successively and
alternately connect the inductor to the first and second source voltage levels, wherein the controller is further operative
to generate a continuous stream of control pulses in a continuous conduction mode and to selectively generate control pulses,
with the transistors disconnecting the inductor from both the first and second source voltage levels between control pulses,
in a discontinuous conduction mode;

wherein the control logic is operative to switch between continuous and discontinuous conduction modes without causing an
overshoot or undershoot deviation in the output voltage by skipping the generation of control pulses in response to detecting
reversal of the inductor current;

a pulse width modulation circuit comprising:
a feedback path operative to generate a Verror signal indicative of a difference between the output DC voltage and a reference
voltage,

a ramp generation circuit operative to generate a periodic ramp signal having a slope, and
a comparator operative to generate a pulse width modulation signal operative to vary a duty cycle of the control pulses in
the continuous conduction mode by comparing the Verror signal and the periodic ramp signal; and

a pulse skipping circuit operative to detect and indicate reversal of the inductor current comprising:
a sample and hold circuit operative to sample a voltage indicative of the inductor current, and to output a sampled current
reversal signal having a positive voltage if the inductor current is negative;

an integrator operative to integrate the sampled current reversal signal; and
a comparator operative to generate a pulse skipping signal when the integrated sampled current reversal signal is greater
than the Verror signal.

US Pat. No. 9,414,176

ACCESSORY PLUG DETECTION

STMICROELECTRONICS INTERN...

1. An apparatus, comprising:
a microphone detection circuit configured to detect connection of a microphone to a signal line through a jack connection
and generate a first connection signal, wherein the microphone detection circuit comprises a logic gate configured to logically
combine a voltage on said signal line with an enable signal;

a headset detection circuit configured to detect connection of a headset through said jack connection and generate a gating
signal; and

a gating circuit configured to pass said first connection signal for output as a headset connected signal in response to said
gating signal.

US Pat. No. 9,231,627

ADAPTIVE ISO-GAIN PRE-DISTORTION FOR AN RF POWER AMPLIFIER OPERATING IN ENVELOPE TRACKING

STMicroelectronics Intern...

1. An adaptive method of pre-distorting an envelope tracking modulation of supply voltage for a Radio Frequency (RF) power
amplifier (PA), comprising:
calculating the amplitude envelope of a complex baseband transmission signal; frequency up-converting the complex baseband
transmission signal to RF;

modulating a supply voltage, output by a dynamic power supply to a RF PA, in response to the amplitude envelope of the baseband
transmission signal;

amplifying the RF transmission signal by the RF PA receiving the modulated supply voltage;
sampling an RF feedback signal at the RF PA output, frequency down-converting the RF feedback signal to baseband and extracting
an amplitude envelope of the baseband feedback signal;

comparing the amplitude envelope of the baseband feedback signal with the amplitude envelope of the baseband transmission
signal; and

pre-distorting the modulation of the supply voltage in response to the comparison so as to achieve a constant gain in the
RF PA, the pre-distorting being performed by executing:

a Learning Sequence comprising sampling the baseband feedback signal amplitude envelope at a plurality of predetermined interpolation
nodes,

an Interpolation Sequence comprising generating a nonlinear polynomial function to fit the sampled interpolation node values,
and

a Computation Sequence comprising multiplying the baseband transmission signal amplitude envelope by the nonlinear polynomial
function.

US Pat. No. 9,264,049

SYNCHRONOUS ON-CHIP CLOCK CONTROLLERS

STMicroelectronics Intern...

1. An on-chip clock (OCC) controller receiving a scan enable signal, a first clock signal, and a synchronous mode signal,
the OCC controller comprising:
one or more meta-stability registers configured to synchronize the scan enable signal with the first clock signal when the
synchronous mode signal is in a first state; and

an OCC engine circuit configured to receive pulse commands from a control unit and generate:
first clock pulses of the scan enable signal synchronized with the first clock signal by the one or more meta-stability registers
according to the pulse commands when the synchronous mode signal is in the first state,

second clock pulses of an external synchronization signal synchronized with the first clock signal according to the pulse
commands when the synchronous mode signal is in a second state, and

a counter unit configured to count clock cycles of the first clock signal and generate the first clock pulses or the second
clock pulses based on the counted clock cycles.

US Pat. No. 9,229,462

CAPLESS ON CHIP VOLTAGE REGULATOR USING ADAPTIVE BULK BIAS

STMicroelectronics Intern...

1. An integrated circuit die comprising:
an FDSOI semiconductor substrate including:
a first layer of semiconductor material;
a buried dielectric layer positioned on the first layer of semiconductor material; and
a second layer of semiconductor material positioned on the buried dielectric layer;
an output node that supplies an output voltage;
an output transistor that supplies an output current to the output node;
a feedback loop coupled to the output transistor, wherein the feedback loop regulates the output voltage by generating a loop
current based on the output current, the feedback loop including a first loop transistor having a control gate and a back
gate, the back gate of the first loop transistor being implemented in the first layer of semiconductor material; and

an adaptive bias generator coupled to the feedback loop, wherein the adaptive bias generator applies a back gate bias voltage
to the back gate of the first loop transistor and adapts a ratio of the loop current and the output current by adjusting the
back gate bias voltage based on the output current.

US Pat. No. 9,148,075

MEMS DEVICE AND METHODS FOR MANUFACTURING AND USING SAME

STMicroelectronics Intern...

6. A MEMS device, comprising:
a rotor formed of a multilayer structure and including a first plurality of rotor teeth formed in an upper layer of said multilayer
structure and extending from a first side of the rotor and including a second plurality of rotor teeth formed in a lower layer
of said multilayer structure and extending from a second side of the rotor; and

a stator formed of said multilayer structure and including a first plurality of stator teeth formed in the upper layer of
said multilayer structure and extending from a first side of the stator and including a second plurality of rotor teeth formed
in the lower layer of said second multilayer structure and extending from a second side of the stator;

wherein the first side of the rotor is adjacent the second side of the stator and wherein the second side of the rotor is
adjacent the first side of the stator.

US Pat. No. 9,459,311

METHOD OF VALLEY INDUCTANCE CURRENT POLARITY DETECTION IN A PULSE WIDTH MODULATED CIRCUIT WITH AN INDUCTIVE CHARGE

STMicroelectronics Intern...

15. A circuit, comprising:
a pulse width modulated circuit charged with an inductive charge and having a first output;
a pulse width modulated reference circuit with no inductive charge having a second output;
a detector circuit configured to detect valley inductance current polarity change in said pulse width modulated circuit charged
with an inductive charge, wherein the detector circuit comprises a comparator configured to compare respective times that
the first output and second output reach a voltage level.

US Pat. No. 9,191,025

SEGMENTED DIGITAL-TO-ANALOG CONVERTER

STMicroelectronics Intern...

1. A digital-to-analog converter, comprising:
a first segment including a first number of first elements that are configured to generate a first analog signal in response
to a first portion of a digital signal;

a second segment including a second number of second elements that are configured to generate a second analog signal in response
to a second portion of the digital signal;

a combiner configured to combine the first analog signal and the second analog signal to generate a resulting analog signal;
and

a controller configured to deactivate one of the first elements and to activate one of the second elements in place of the
deactivated one of the first elements.

US Pat. No. 9,172,303

POWER MANAGEMENT UNIT SYSTEMS AND METHODS

STMICROELECTRONICS INTERN...

9. A method for operating a power management unit, the method comprising:
receiving, by a step-down power converter, a first voltage and outputting a second voltage, wherein the second voltage is
less than the first voltage;

comparing, by a first feedback amplifier within the step-down power converter, a sensed proportion of the second voltage with
a first reference voltage and providing a first control input to a first finite state machine (FSM) within the step-down power
converter based upon the comparison;

synchronizing, by the first FSM within the step-down power converter, a time sharing of an inductive element with a second
FSM;

receiving, by a step-up power converter, the second voltage and outputting a third voltage, wherein the third voltage is greater
than the second voltage;

comparing, by a second feedback amplifier within at least one step-up power converter, a sensed proportion of the third voltage
with a second reference voltage and providing a second control input to a second FSM within the at least one step-up power
converter based upon the comparison;

synchronizing, by the second FSM within the at least one step-up power converter, a time sharing of the inductive element
with the first FSM; and

storing, by the inductive element, energy and selectively releasing the stored energy, wherein the inductive element is time
shared by both the step-down power converter and the at least one step-up power converter.

US Pat. No. 9,159,402

SRAM BITCELL IMPLEMENTED IN DOUBLE GATE TECHNOLOGY

STMicroelectronics Intern...

1. A static random access memory (SRAM) bitcell circuit, comprising:
a first CMOS inverter having a first input and a first output and formed by a first p-channel transistor and a first n-channel
transistor;

a second CMOS inverter having a second input and a second output and formed by a second p-channel transistor and a second
n-channel transistor;

wherein the first output is coupled to the second input at a true node;
wherein the second output is coupled to the first input at a complement node;
a first pass transistor coupled between a true bitline node and the true node;
a second pass transistor coupled between a complement bitline node and the complement node;
a first direct connection of the true bitline node to apply a true bitline potential to a back gate of the second p-channel
transistor in the second CMOS inverter; and

a second direct connection of the complement bitline node to apply a complement bitline potential to a back gate of the first
p-channel transistor in the first CMOS inverter.

US Pat. No. 9,378,779

SYSTEM AND METHOD FOR AUTOMATIC DETECTION OF POWER UP FOR A DUAL-RAIL CIRCUIT

STMicroelectronics Intern...

1. An integrated circuit, comprising:
a first circuit stage having an input node coupled to a first supply voltage node and configured to receive a first supply
voltage, the input node coupled to an inverter having an output node;

a second circuit stage having a first auto-sequencing circuit configured to generate a first holding signal and a second auto-sequencing
circuit configured to generate a second holding signal; and

a third circuit stage having a pull-up circuit controlled by the first holding signal and configured to hold the output node
at a second supply voltage corresponding to a second supply voltage node until the first supply voltage exceeds a threshold
and a pull-down circuit controlled by the second holding signal and configured to hold the output node at a reference voltage
corresponding to a reference node until the first supply voltage falls below a second threshold.

US Pat. No. 9,143,922

METHOD AND SYSTEM FOR CONTROLLING COMMUNICATION BETWEEN AN UICC AND AN EXTERNAL APPLICATION

STMICROELECTRONICS INTERN...

1. A method for controlling communication among an universal integrated circuit card (UICC), a handset including the UICC,
and an external device associated with an external application running outside of the handset, the method comprising:
switching on the UICC via the handset;
after the switching, executing a first initialization procedure via the handset to establish a first communication session
between the handset and the UICC;

after the executing of the first initialization procedure, executing a second initialization procedure for exchanging a connection
request between the handset and the external device to establish a second communication session between the UICC and the external
device, the handset causing the UICC to reset when the connection request is received and during the second initialization
procedure;

using the UICC to retrieve a unique handset identification number of the handset after completing the first initialization
procedure;

after the retrieving of the unique handset identification number, storing the unique handset identification number in a memory
of the UICC;

using the UICC to retrieve an attribute of the external device via the handset after completing the second initialization
procedure;

using the UICC to compare the unique handset identification number of the handset with the attribute of the external device
to distinguish the second communication session from the first communication session; and

when the unique handset identification number of the handset and the attribute of the external device do not match and subsequently
receiving a request from the external device for a record stored in the UICC, using the UICC to reply with an empty record.

US Pat. No. 9,331,671

AUTOMATIC POWER SWITCHING AND POWER HARVESTING IN THIN OXIDE OPEN DRAIN TRANSMITTER CIRCUITS, SYSTEMS, AND METHODS

STMicroelectronics Intern...

1. An open drain transmitter, comprising:
at least one data channel, each data channel operable to communicate data and to provide a drive current that is received
over the data channel and is used in generating a harvested voltage on a harvested node, and the value of the drive current
being a function of a cascode drive voltage;

a clock channel operable to communicate a clock signal and including:
a communications and power harvesting circuit operable to communicate a clock signal and to provide a drive current that is
received over the clock channel and is used in generating the harvested voltage, and the value of the drive current being
a function of the cascode drive voltage, and

a power harvesting control circuit coupled to the clock channel to receive a bias current over the clock channel and operable
in an active mode to generate the cascode drive voltage responsive to this bias current and operable in a power down mode
to generate the cascode drive voltage having a value that ensures that the maximum tolerable junction voltage is not exceeded
for transistors in the clock and data channels, wherein the power harvesting control circuit comprises:

a first transistor having first and second signal nodes and a control node, the first signal node coupled to a first complementary
clock line of the clock channel and the control node receiving the cascode drive voltage;

a second transistor having first and second signal nodes and a control node, the first signal node coupled to a second complementary
clock line of the clock channel and the control node receiving the cascode drive voltage;

a third transistor having a first signal node coupled to the second signal node of the first transistor and having a second
signal node coupled to a bias node, and having a control node adapted to receive a first complementary clock signal;

a fourth transistor having a first signal node coupled to the second signal node of the second transistor and having a second
signal node coupled to the bias node, and having a control node adapted to receive a second complementary clock signal;

an external resistor coupled between the bias node and a reference voltage source;
wherein a bias current of the clock channel is operable to flow from the corresponding complementary clock line through the
corresponding first or second transistor and through the activated one of the third and fourth transistors to the bias node
and through the external resistor to generate a control voltage; and

a cascode drive voltage generation circuit coupled to the bias node and operable to generate the cascode drive voltage responsive
to the control voltage during an active mode of operation and operable during a power down mode of operation to generate the
cascode drive voltage having a value that is a function of a pull-up voltage applied on the complementary clock lines and
of the harvested voltage.

US Pat. No. 9,588,538

REFERENCE VOLTAGE GENERATION CIRCUIT

STMICROELECTRONICS SA, M...

1. A circuit for generating a reference voltage, comprising:
first and second supply terminals configured to provide a power supply voltage;
a first MOS transistor and a first bipolar transistor electrically coupled in series between the first and second supply terminals;
a second MOS transistor and a first resistive element electrically coupled between the first and second supply terminals,
the second MOS transistor and the first resistive element being directly electrically coupled to each other by a first junction
point that is electrically coupled to a base of the first bipolar transistor;

a third MOS transistor and a second bipolar transistor electrically coupled in series between the first and second supply
terminals, the third MOS transistor forming a current mirror with the first MOS transistor;

a second resistive element electrically coupled between a base of the second bipolar transistor and the first junction point;
and

a fourth MOS transistor and a third resistive element electrically coupled between the first and second supply terminals,
the fourth MOS transistor and the third resistive element being electrically coupled to each other at a second junction point
that defines an output terminal configured to provide the reference voltage, the fourth MOS transistor forming a current mirror
with the second MOS transistor, a gate of the fourth MOS transistor and a gate of the second MOS transistor being electrically
coupled to each other at a third junction point, the third MOS transistor being electrically coupled between the first supply
terminal and the third junction point.

US Pat. No. 9,324,414

SELECTIVE DUAL CYCLE WRITE OPERATION FOR A SELF-TIMED MEMORY

STMICROELECTRONICS INTERN...

1. A method, comprising:
performing a write operation to a first cell of a memory array at a first row and first column location during a first memory
access cycle; and

performing a memory access operation to a second cell of the memory array at a second row and second column location during
a second memory access cycle, said second memory access cycle immediately following the first memory access cycle, wherein
performing comprises:

determining if the second row is a same row as the first row;
determining if the second column is a different column than the first column; and
if the second row is the same row as the first row and the memory access operation is a read, or if the second row is the
same row as the first row, the second column is the different column than the first column and the memory access operation
is a write, then:

simultaneously within said second memory access cycle accessing the second cell and re-writing data from the first memory
access cycle write operation to the first cell.

US Pat. No. 9,098,097

SYSTEM AND METHOD FOR REMOTE TEMPERATURE SENSING WITH ROUTING RESISTANCE COMPENSATION

STMicroelectronics Intern...

1. An integrated circuit die comprising:
a controller including:
an analog-to-digital converter having an input;
a bandgap voltage generator coupled to the input of the analog-to-digital converter and configured to provide a bandgap voltage
to the analog-to-digital converter;

a first input coupled to the bandgap voltage generator;
a second input coupled to the bandgap voltage generator;
a multiplexer coupled to the controller;
a plurality of temperature sensor units;
a plurality of groups of conductive signal lines, each group of conductive signal lines electrically connecting a respective
one of the temperature sensor units to the multiplexer, each group of conductive signal lines including:

a respective first signal line;
a respective second signal line; and
a respective plurality of resistance compensation areas in which a length of the first signal line is extended with respect
to a length of the second signal line, the multiplexer configured to selectively electrically couple a respective one of the
groups of conductive signal lines to the first and second inputs of the controller.

US Pat. No. 9,077,362

MEMORYLESS SLIDING WINDOW HISTOGRAM BASED BIST

STMicroelectronics Intern...

1. A method for determining nonlinearity characteristics of an analog-to-digital converter (ADC), comprising:
incrementally supplying an input analog voltage to the ADC;
determining first nonlinearity values for a first subset of digital codes generated by the ADC in response to the input analog
voltage;

determining second nonlinearity values for a second subset of digital codes generated by the ADC in response to the input
analog voltage;

incrementing one or more counters when the first and second nonlinearity values exceed nonlinearity value thresholds; and
determining nonlinearity characteristics about the ADC based, at least in part, on the one or more counters.

US Pat. No. 9,466,304

METHOD AND SYSTEM FOR DIGITAL WATERMARKING

STMICROELECTRONICS INTERN...

1. A system comprising:
a signal source configured to generate an audio signal; and
an integrated circuit coupled to the signal source, the integrated circuit configured to add a watermark to the audio signal,
the integrated circuit including:

a spectrum modulator configured to perform spectrum modulation on a watermark bit and a pseudo noise signal to be embedded
into the audio signal to generate a modulated signal;

a distortion controller coupled to the signal source and the spectrum modulator and configured to shape the modulated signal
based on the audio signal to generate a shaped signal satisfying a predetermined distortion constraint;

an interference compensator coupled to the signal source and the distortion controller and configured to generate a compensation
signal based on the audio signal, the pseudo noise signal and the shaped signal; and

a signal generator configured to generate a watermarked audio signal based on the compensation signal, the shaped signal and
the audio signal.

US Pat. No. 9,361,117

TAG-BASED IMPLEMENTATIONS ENABLING HIGH SPEED DATA CAPTURE AND TRANSPARENT PRE-FETCH FROM A NOR FLASH

STMICROELECTRONICS (GRENO...

1. A system comprising a controller operating on a controller clock signal and electrically coupled to a flash memory device
through an input/output (I/O) socket and capable of receiving data from the flash memory device, the system comprising:
a transmitter state module receiving the controller clock signal and configured to generate a selective clock signal based
on the controller clock signal and configured to provide the selective clock signal to the I/O socket, wherein passage of
the selective clock signal through the I/O socket creates a feedback clock signal; and

data capture logic configured to receive the feedback clock signal from the I/O socket and comprising one or more storage
elements configured to capture data from the flash memory device according to the feedback clock signal;

wherein the one or more storage elements of the data capture logic comprise a negative first-in-first-out storage element
for capturing the data from the flash memory device on negative edges of the feedback clock signal.

US Pat. No. 9,336,418

SYSTEM AND METHOD FOR POLLING NFC-A DEVICES ALONGSIDE RF BARCODE DEVICES

STMicroelectronics Intern...

1. A method of connecting a near-field communication (NFC) reader to a plurality of NFC devices including at least one NFC-A
device and at least one RF barcode device, comprising:
detecting and logging the active and sleep intervals of the RF barcode device when an RF field is switched on; and
synchronizing the transmission and reception of data to and from each NFC-A device such that transmission and reception of
data to and from each NFC-A device occurs only during sleep intervals of the RF barcode device.

US Pat. No. 9,048,308

REGENERATIVE BUILDING BLOCK AND DIODE BRIDGE RECTIFIER AND METHODS

STMICROELECTRONICS INTERN...

1. A rectifier device comprising:
first and second transistors, each transistor comprising
a gate region;
a source region adjacent said gate region;
a drain region;
a drift region adjacent said drain region;
a semiconductor region in the drift region and aligned with an opening of the gate region;
a first electrode coupled to the gate region; and
a second electrode coupled to the semiconductor region of the drift region, the first electrode and second electrode being
configured to control a voltage of the gate region independent of a voltage of the semiconductor region;

said second electrode of said first transistor being coupled to the first electrode of the second transistor, and said second
electrode of said second transistor being coupled to the first electrode of the first transistor.

US Pat. No. 9,356,770

OVERSAMPLING CDR WHICH COMPENSATES FREQUENCY DIFFERENCE WITHOUT ELASTICITY BUFFER

STMicroelectronics Intern...

1. A clock and data recovery circuit comprising:
a clock input providing a first clock signal;
a data input configured to receive data bits from a transmitting electronic device;
a circuit for generating a plurality of samples of each data bit and collecting the samples into a group for processing, wherein
a number of the samples of each data bit is an oversampling ratio (OSR);

a programmable frequency divider circuit configured to divide a frequency of the first clock signal and output a divided clock
signal that is used for processing the samples at a lesser rate and as a recovered clock output of the clock and data recovery
circuit, wherein the programmable frequency divider circuit comprises a divider circuit to divide the input clock by a base
value (N) and a control input to change a division ratio from the base value (N) by a fixed value (P) for a fixed number of
cycles (Q);

a fast lock circuit configured to find an initial center sample;
a phase tracker circuit configured to decide a new position of the center sample for every group of collected samples;
a unit interval (UI) movement controller circuit configured to request a change in the division ratio of the programmable
frequency divider circuit when an accumulated phase difference has crossed a threshold PTH, and to act on an acknowledgement from the programmable frequency divider circuit, wherein M is greater than a product of
P and Q and PTH is between (M?1)*OSR+OSR/2 and (M?1)*OSR+OSR, and wherein M is greater than 1 and is less than N?1; and

a data selector circuit configured to extract recovered data bits from each group of samples using the new center sample for
that group.

US Pat. No. 9,317,054

FEEDBACK NETWORK FOR LOW-DROP-OUT GENERATOR

STMICROELECTRONICS INTERN...

1. A circuit, comprising:
a chain of resistance sets coupled in series and having a first end terminal and a second end terminal;
respective nodes coupled between successive ones of the resistance sets;
a feedback terminal;
a set of switches capable of electrically coupling a given one of the respective nodes to the feedback terminal;
a first resistance set of the chain adjacent the first end terminal comprising two resistance subsets coupled in series at
an intermediate node between the two resistance subsets; and

a first programmable current generator having a current output terminal directly connected to the intermediate node between
the two resistance subsets and being configured to produce a controlled value of current at the current output terminal flowing
into or out of the intermediate node.

US Pat. No. 9,054,637

AMPLITUDE LIMITING CIRCUIT FOR A CRYSTAL OSCILLATOR

STMicroelectronics Intern...

1. An amplitude limiting circuit for a crystal oscillator circuit, comprising:
a current source configured to supply drive current to the crystal oscillator circuit;
a current sensing circuit configured to sense operating current of the crystal oscillator circuit;
a current comparison circuit configured to compare the sensed operating current to a comparison current and generate an output
signal; and

a current control circuit configured to generate a control signal for controlling operation of the current source in response
to said output signal.

US Pat. No. 9,306,605

ELECTRONIC DEVICE HAVING FREQUENCY SHIFTING UART

STMicroelectronics Intern...

1. A system, comprising:
a circuit configured to operate at a communications frequency; and
a UART configured to support data communications in accordance with a baud rate when the communications frequency is not evenly
divisible by the baud rate, the UART further configured to generate a frequency shift based upon the communications frequency
being evenly divisible by the baud rate, shift the baud rate by the frequency shift when the communications frequency is evenly
divisible by the baud rate so that the communications frequency is not evenly divisible by the baud rate as shifted and support
data communications in accordance with the baud rate as shifted.

US Pat. No. 9,223,894

METHOD FOR PRODUCING AT LEAST A PORTION OF A DATA VISUALIZATION LAYOUT ON A DISPLAY OF A DEVICE PROVIDED WITH AT LEAST A SMART CARD, METHOD FOR CODIFYING A PLURALITY OF HTML INSTRUCTIONS AND CORRESPONDING SYSTEM

STMICROELECTRONICS INTERN...

1. A method for generating at least one portion of a data display layout on a display of a device cooperating with at least
one smart card comprising a smart card body and circuitry carried by the smart card body, the method comprising:
generating a code sequence to define the at least one portion of the data display layout and storing the code sequence in
the at least one smart card, each code of the code sequence having a first portion comprising a first numerical code, and
a second portion comprising a second numerical code, the first numerical code corresponding to a primitive action from among
a plurality thereof, and the second numerical code corresponding to a coded item of data correlated with the primitive action,
the primitive action comprising an action for processing a uniform resource locator (URL) string having a URL address therein
and an action related to a display characteristic, the coded item of data being based upon the URL string;

processing the code sequence to generate the at least one portion of the data display layout with the coded item of data in
a selected position and based upon the display characteristic; and

wirelessly sending, based upon the URL address, the at least one portion of the data display layout with the coded item of
data in the selected position and with the display characteristic to the display of the device.

US Pat. No. 9,218,782

VIDEO WINDOW DETECTION

STMicroelectronics Intern...

1. A video detection method comprising:
providing first and second video windows that overlap, the first and second video windows each playing a video therein;
using at least one of horizontal and vertical continuous edges within an overlap video region of the first and second video
windows to create separations between the first and second video windows;

differentiating the first video window from the second video window based upon the separations created by at least one of
the horizontal and vertical continuous edges;

determining whether the first video window overlaps the second video window or whether the second video window overlaps the
first video window;

if the first video window overlaps the second video window, enhancing the video playing in the first video window and not
the video playing in the second video window in the overlap video region based upon the differentiation of the first video
window from the second video window, the enhancing being performance of noise reduction on the video playing in the first
video window; and

if the second video window overlaps the first video window, enhancing the video playing in the second video window and not
the video playing in the first video window in the overlap video region based upon the differentiation of the first video
window from the second video window, the enhancing being performance of noise reduction on the video playing in the second
video window.

US Pat. No. 9,413,346

CLOCK GLITCH AND LOSS DETECTION CIRCUIT

STMicroelectronics Intern...

21. A method, comprising:
measuring a signal parameter with respect to each period within a plurality of individual periods of a clock signal;
selecting a first parameter value from the measured signal parameters;
first comparing the first parameter value to a first threshold; and
outputting a first clock error signal in response to said first comparison.

US Pat. No. 9,385,593

SUSPEND MODE IN CHARGE PUMP

STMicroelectronics Intern...

1. A voltage supply comprising:
a charge pump coupled to a power source and configured to output a pulse-width modulated voltage based upon an input voltage
from the power source;

a low-pass filter comprising an output capacitor, the output capacitor configured to average the pulsed-width modulated voltage
and output a filtered voltage having a value different than that of the input voltage;

a controller configured to selectively decouple the charge pump from the power source when a load imposed on the low-pass
filter is below a threshold load, the load imposed on the low-pass filter being based upon a load control signal, the load
control signal comprising a digital signal, the digital signal comprising a series of sampled values;

an analyzer configured to analyze the load control signal, estimate whether the load is below the threshold load, and selectively
operate the controller based upon the estimate of whether the load is below the threshold load.

US Pat. No. 9,311,990

PSEUDO DUAL PORT MEMORY USING A DUAL PORT CELL AND A SINGLE PORT CELL WITH ASSOCIATED VALID DATA BITS AND RELATED METHODS

STMICROELECTRONICS INTERN...

1. A pseudo dual port memory comprising:
a set of dual port memory cells having a read port and a write port, and configured to store data words in each of a plurality
of addressed locations;

a set of single port memory cells having a read/write port, and configured to store data words in each of a plurality of addressed
locations;

a valid data storage unit configured to store valid bits corresponding to the addressed locations of the set of dual port
memory cells and the set of single port memory cells; and

control circuitry configured to access the addressed locations of the set of dual port memory cells and the set of single
port memory cells by

performing a simultaneous write operation using the write port of the set of dual port memory cells and the read/write port
of the set of single port memory cells, and updating corresponding valid bits in the valid data storage unit, and

performing a parallel read operation, at a same addressed location of the set of dual port memory cells and the set of single
port memory cells, using the read port of the set of dual port memory cells and the read/write port of the set of single port
memory cells, and determining which stored data word is valid based upon the corresponding valid bits in the valid data storage
unit.

US Pat. No. 9,146,574

NOISE CANCELING CURRENT MIRROR CIRCUIT FOR IMPROVED PSR

STMicroelectronics Intern...

1. A device, comprising:
a bias circuit that generates a bias voltage;
a first transistor connected to the bias circuit and receiving the bias voltage, the first transistor conducting a first current
based on the bias voltage;

a second transistor connected to the bias circuit and receiving the bias voltage, the second transistor conducting a second
current, the second current including a DC component and a noise component;

a third transistor connected to the bias circuit and receiving the bias voltage, the third transistor conducting a third current
based on the bias voltage; and

a fourth transistor connected to the output of the second transistor and drawing less than half of the DC component of the
second current and more than half of the noise component of the second current, the fourth transistor being biased at least
in part by the first and third currents.

US Pat. No. 9,247,245

ADAPTIVE FILTER FOR VIDEO SIGNAL PROCESSING FOR DECODER THAT SELECTS RATE OF SWITCHING BETWEEN 2D AND 3D FILTERS FOR SEPARATION OF CHROMA AND LUMA SIGNALS

STMicroelectronics Intern...

1. A video decoder system, comprising:
a motion detector configured to determine presence of motion in a current composite video signal by comparing the current
composite video signal with a corresponding delayed composite video signal;

a chroma-luma (Y/C) separation module configured to decode a pixel based on the presence of motion, using at least a filter
selected from a 2D filter and a 3D filter; and

an adaptive temporal motion filter configured to adaptively select a rate of switching between the 2D filter and the 3D filter,
the adaptive temporal motion filter having a time constant that is varied by selectively changing a gain factor of the adaptive
temporal motion filter based at least in part on a motion magnitude, a motion polarity, and a chroma-luma status of the pixel;

wherein the adaptive temporal motion filter is further configured to automatically switch modes between infinite impulse response
mode, a max mode, and a bypass mode based at least in part on the motion magnitude, the motion polarity, and the chroma-luma
status of the pixel.

US Pat. No. 9,313,713

METHOD FOR DISCOVERING A PLURALITY OF NFC-B DEVICES BY A NFC-B READER AND CORRESPONDING NFC-B READER

STMicroelectronics Intern...

1. A method for identifying a plurality of Near Field Communication-type B devices operating in a listen mode (NFC-B listen
mode devices) by a Near Field Communication-type B device operating in a poll mode (NFC-B poll mode device) during more than
one collision resolution cycles, each collision resolution cycle starting with a first command sent by the NFC-B poll mode
device and including a number of time slots less than or equal to a maximum number, a first collision resolution cycle including
one time slot, the method comprising:
when the NFC-B poll mode device is to start another collision resolution cycle after a current collision resolution cycle
is ended, increasing, by the NFC-B poll mode device, the number of time slots with respect to the number of time slots of
the ended current collision resolution cycle if and only if no NFC-B listen mode device has been identified during the ended
current collision resolution cycle and no empty time slot has been detected during the ended current collision resolution
cycle; and

when a NFC-B listen mode device is identified within a time slot of a current collision resolution cycle, sending, by the
NFC-B poll mode device to the identified NFC-B listen mode device, a second command for putting the identified NFC-B listen
mode device in a sleep state, the second command being sent within a subsequent time slot of the current collision resolution
cycle except for the NFC-B listen mode device lastly identified within the last collision resolution cycle.

US Pat. No. 9,264,045

BUFFER CIRCUIT WITH REDUCED STATIC LEAKAGE THROUGH CONTROLLED BODY BIASING IN FDSOI TECHNOLOGY

STMicroelectronics Intern...

1. A circuit, comprising:
a first system including a drive circuit configured to generate a first digital signal having a first logic state and a second
logic state referenced, respectively, to a first high voltage and a first low voltage of a first supply domain;

a second system including a buffer circuit configured to receive the first digital signal and generate a second digital signal
having a first logic state and a second logic state referenced, respectively, to a second high voltage and a second low voltage
of a second supply domain;

wherein the second high voltage is greater than the first high voltage; and
wherein the buffer circuit comprises:
a first inverter circuit including a p-channel MOSFET having a gate terminal configured to receive the first digital signal
and a transistor body;

a second inverter having an input coupled to an output of the first inverter circuit and having an output configured to generate
the second digital signal; and

a feedback circuit configured to apply the output signal as a bias to the transistor body of the p-channel MOSFET of the first
inverter circuit.

US Pat. No. 9,497,464

GOP-INDEPENDENT DYNAMIC BIT-RATE CONTROLLER

STMICROELECTRONICS INTERN...

1. A system comprising:
a user interface configured to receive one or more input parameters;
a bit-rate controller configured to regulate a bit-rate of an output bit-stream, the bit-rate controller comprising
a plurality of bit-rate modules configured to determine a quantization parameter based on a bit-estimate,
a control module configured to calculate a convergence period based on the received one or more input parameters and a frame
rate, wherein the calculated convergence period corresponds to a number of picture frames to converge the bit-rate of the
output bit-stream to a target bit-rate and the control module selects a bit rate module to allocate a number of bits to each
different type of picture frame in the calculated convergence period based on the type of each picture frame; and

an encoder configured to encode once per picture frame and for generating the output bit-stream using the quantization parameter
determined by the selected bit rate module.

US Pat. No. 9,325,323

CMOS OSCILLATOR HAVING STABLE FREQUENCY WITH PROCESS, TEMPERATURE, AND VOLTAGE VARIATION

STMicroelectronics Intern...

1. A device, comprising:
a node configured to receive a voltage signal;
a first circuit coupled to the node and configured to generate a clock signal in response to the voltage signal; and
a second circuit coupled to the first circuit and configured to alter the generated clock signal in response to an operating
condition;

wherein the first circuit comprises a CMOS oscillator comprising:
a level shifter;
a first current-starved inverter coupled to the level shifter;
a first buffer coupled to the first current-starved inverter;
a first capacitor coupled to the first current-starved inverter and coupled to the level shifter;
a second current-starved inverter coupled to the level shifter;
a second buffer coupled to the second current-starved inverter; and
a second capacitor coupled to the second current-starved inverter and coupled to the level shifter.

US Pat. No. 9,178,517

WIDE RANGE CORE SUPPLY COMPATIBLE LEVEL SHIFTER CIRCUIT

STMicroelectronics Intern...

1. A circuit, comprising:
first and second p-channel fully depleted silicon on insulator (FDSOI) devices electrically cross-coupled to one another through
an inverter to form a level shifter that shifts a low supply voltage to a high supply voltage, each p-channel FDSOI device
including a primary gate and a secondary gate, the secondary gates of the p-FDSOI device being coupled to the high supply
voltage;

first and second dual-gate n-channel FDSOI devices, each dual-gate n-channel FDSOI device including a primary gate and a secondary
gate, the primary and secondary gates of each n-channel FDSOI device being electrically coupled to one another, and each n-channel
device coupled to a corresponding one of the p-channel devices; and

an inverter having an input and an inverted output, the input electrically coupled to the primary and the secondary gates
of the first n-channel device, and the inverted output electrically coupled to the primary and the secondary gates of the
second n-channel device.

US Pat. No. 9,558,052

SAFE SCHEDULER FOR FINITE STATE DETERMINISTIC APPLICATION

STMicroelectronics Intern...

1. An embedded controller, comprising:
a functional logic module interface;
a task scheduler module arranged to schedule a finite number of events of one or more functional logic modules accessible
via the functional logic module interface, wherein the finite number of monitored events include a trigger of at least one
analog to digital conversion, a received indication of a completed analog to digital conversion, and an interaction with at
least one timer; and

a safety module, the safety module arranged to:
monitor the finite number of events;
incrementally create a mathematic check value, each increment based on at least one of the finite number of monitored events;
compare the mathematic check value to a pre-computed model check value; and
set a test result value based on the comparison.

US Pat. No. 9,508,405

METHOD AND CIRCUIT TO ENABLE WIDE SUPPLY VOLTAGE DIFFERENCE IN MULTI-SUPPLY MEMORY

STMicroelectronics Intern...

1. A memory device comprising:
a bit line;
a complementary bit line;
a memory cell coupled to the bit line or the complementary bit line;
a first pre-charge circuit coupled between the bit line and the complementary bit line, the first pre-charge circuit being
configured to pre-charge the bit line and the complementary bit line to a first voltage level, wherein the first voltage level
comprises a peripheral voltage level;

a second pre-charge circuit coupled between the bit line and the complementary bit line, the second pre-charge circuit being
configured to pre-charge the bit line and the complementary bit line to a second voltage level that is different than the
first voltage level, wherein the second voltage level comprises an array voltage level;

control circuitry configured to activate the first pre-charge circuit to pre-charge the bit line and complementary bit line
to the first voltage level in response to an access request, the access request enabling the second pre-charge circuit to
pre-charge the bit line and complementary bit line to the second voltage level only when the peripheral voltage level is lower
than the array voltage level and the access request disabling the second pre-charge circuit for charging when the peripheral
voltage is higher than the array voltage by a noise margin safe range; and

a delay generation circuit coupled to the control circuitry and configured to control a delay so that the memory cell is selected
after the bit line and complementary bit line have reached a static noise margin safe level.

US Pat. No. 9,710,722

SYSTEM AND METHOD FOR ADAPTIVE PIXEL FILTERING

STMicroelectronics Intern...

1. A method, comprising:
receiving an image having a plurality of pixels;
selecting an apply patch of the image, the apply patch including first and second pixels of the plurality of pixels, the second
pixel being adjacent to the first pixel;

selecting a search area of the image, the search area including at least a third pixel of the plurality of pixels;
determining a difference value between the first pixel and the third pixel based on the pixels surrounding the first pixel
and the third pixel;

determining a weight value based on the difference value;
assigning the weight value to the third pixel;
modifying the first pixel with the weight value assigned to the third pixel;
selecting a fourth pixel, the fourth pixel being adjacent to the third pixel;
assigning the weight value to the fourth pixel; and
modifying the second pixel with the weight value assigned to the fourth pixel, therein filtering the image.

US Pat. No. 9,482,719

ON-THE-FLY TEST AND DEBUG LOGIC FOR ATPG FAILURES OF DESIGNS USING ON-CHIP CLOCKING

STMicroelectronics Intern...

1. A system for interfacing with a design under test (DUT), comprising:
an on-chip clock controller (OCC) circuit configured to receive a test pattern and responsively generate one or more clock
pulses in response to the test pattern;

an OCC test circuit coupled to the OCC circuit and configured to detect the one or more clock pulses generated by the OCC
circuit and generate corresponding OCC test outputs;

a clipping test circuit configured to capture outputs generated by a plurality of pulse-width critical flip-flops of the DUT
and generate corresponding pulse-width debug outputs;

a test output logic circuit configured to receive the OCC test outputs and the pulse-width debug outputs; and
a debug controller operable to configure the test output logic circuit to selectively map the OCC test outputs and the pulse-width
debug outputs to a test output.

US Pat. No. 9,178,418

PRE-EMPHASIS CIRCUIT

STMicroelectronics Intern...

1. A drive-signal booster, comprising:
a differential current mode driver having a first output node and a second output node;
a first control signal generator configured to output a first control signal in response to a transition of a first input
signal applied to control operation of the differential current mode driver;

a first current generator configured to apply a first drive-source current signal to the first output node in response to
the first control signal; and

a second current generator configured to apply a first drive-sink current signal to the second output node in response to
the first control signal.

US Pat. No. 9,170,595

LOW POWER REFERENCE GENERATOR CIRCUIT

STMicroelectronics Intern...

22. A reference generator circuit, comprising:
a PTAT circuit including a first transistor, a second transistor, and a first resistive element, wherein the first and second
transistors have control terminals coupled to each other, the first resistive element having a first end coupled to a conduction
terminal of the second transistor and a second end coupled to a reference supply node;

a current source circuit configured to source additional current into the first end of the first resistive element; and
a diode circuit connected in series with a second resistive element and coupled between the output of the current source circuit
and the first end of the first resistive element.

US Pat. No. 9,473,134

SYSTEM AND METHOD FOR A PRE-DRIVER CIRCUIT

STMicroelectronics Intern...

1. A drive circuit comprising:
an input;
a driver comprising a first PMOS transistor and a first NMOS transistor, wherein the first PMOS transistor and the first NMOS
transistor are coupled in series between a supply terminal and a reference terminal;

a first buffer coupled between the input and a control terminal of the first PMOS transistor;
a second buffer coupled between the input and a control terminal of the first NMOS transistor;
a first capacitance element coupled to the control terminal of the first PMOS transistor through a first semiconductor switch;
and

a second capacitance element coupled to the control terminal of the first NMOS transistor through a second semiconductor switch,
wherein

the first capacitance element with the first semiconductor switch and the second capacitance element with the second semiconductor
switch comprise variable capacitance elements,

the variable capacitance elements are controlled such that
the first capacitance element provides a capacitance value of substantially zero when the second capacitance element provides
a non-zero capacitance value during a first portion of a data transition from 1 to 0 on the control terminal of the first
PMOS transistor,

the first capacitance element provides a non-zero capacitance value when the second capacitance element provides a capacitance
value of substantially zero during a second portion of a data transition from 1 to 0 on the control terminal of the first
PMOS transistor,

the second capacitance element provides a capacitance value of substantially zero when the first capacitance element provides
a non-zero capacitance value during a first portion of a data transition from 0 to 1 on the control terminal of the first
NMOS transistor, and

the second capacitance element provides a non-zero capacitance value when the first capacitance element provides a capacitance
value of substantially zero during a second portion of a data transition from 0 to 1 on the control terminal of the first
NMOS transistor.

US Pat. No. 9,949,108

METHOD FOR DETECTING AN ADJACENT ACTIVE NEAR-FIELD COMMUNICATION DEVICE

STMICROELECTRONICS INTERN...

1. A method using near-field communication (NFC), the method comprising:assuming, by a first active NFC device configured to generate a radio frequency field, a field detection mode, the field detection mode being a low power mode of the first active NFC device;
generating, by the first active NFC device while the first active NFC device is in the field detection mode, an advertisement pulse;
checking, by the first active NFC device while the first active NFC device is in the field detection mode, whether a predefined condition is fulfilled;
if the checking determines that the predefined condition is fulfilled, assuming, by the first active NFC device, an active mode and communicating with an adjacent active NFC device while the first active NFC device is in the active mode, the active mode being different from the field detection mode, the active mode being a mode in which the first active NFC device requires more processing power than in the field detection mode; and
if the checking does not determine that the predefined condition is fulfilled, staying in the field detection mode and generating, by the first active NFC device, another advertisement pulse.

US Pat. No. 9,762,383

SERIAL TRANSMISSION HAVING A LOW LEVEL EMI

STMICROELECTRONICS (GRENO...

1. A method, comprising:
generating an output signal based on a serial data signal, the generating including scrambling, using a pseudo-random sequence,
the serial data signal, producing a scrambled signal;

detecting occurrences of a data pattern in the scrambled signal; and
responding to the detection of one or more occurrences of the data pattern in the scrambled signal by taking one or more actions
to condition data encoded in the output signal.

US Pat. No. 9,510,195

SECURED TRANSACTIONS IN INTERNET OF THINGS EMBEDDED SYSTEMS NETWORKS

STMICROELECTRONICS INTERN...

1. A secure network enabled device, comprising:
a functional logic module, the functional logic module arranged as a utility meter to measure consumption of a resource;
at least one bidirectional transceiver, the at least one bidirectional transceiver providing the only communication to pass
electronic data associated with the consumption of the resource to and from the secure network enabled device;

a first memory;
a second memory;
a third memory, the third memory being a one-time programmable memory;
a microcontroller embedded in an integrated circuit, the microcontroller arranged to execute instructions stored in the first
memory, the microcontroller incapable of reading from the second memory and the third memory; and

a security module embedded in the integrated circuit, the security module arranged to access all of the electronic data passed
to and from the secure network enabled device and to analyze at least some of the electronic data passed to and from the secure
network enabled device, wherein analyzing at least some of the electronic data includes comparing data in a first data location
of the second memory to data stored in a redundant data location in the second memory, the redundant data location in the
second memory dedicated to storage of redundant data, the security module arranged to communicate data to and from the second
memory, the security module arranged to communicate electronic signature data to and from the third memory.

US Pat. No. 9,208,040

REPAIR CONTROL LOGIC FOR SAFE MEMORIES HAVING REDUNDANT ELEMENTS

STMicroelectronics Intern...

1. Repair control logic for a safe memory having redundant elements, comprising:
comparison logic comprising, for each bit slice of a memory array, a comparator circuit configured to determine whether a
location value of an associated bit slice of the memory array is greater than a location value of a defective bit slice of
the memory array; and

data switching logic comprising, for each bit slice of the memory array, a switching circuit, responsive to a determination
that the location value of the associated bit slice is greater than the location value of the defective bit slice, to switch
data from the associated bit slice to an adjacent bit slice of the memory array.

US Pat. No. 9,948,752

DEFAULT DATA PACKET ROUTING IN A NFC DEVICE

STMICROELECTRONICS INTERN...

1. A method, comprising:receiving a data packet transmitted by a near field communications (NFC) device at a NFC controller, the data packet potentially containing routing information;
wherein, if the data packet contains routing information, the routing information consists of at least one of application identifier routing information, protocol routing information, and technology routing information;
determining whether the data packet includes application identifier routing information, and based thereupon routing the data packet to a default application identifier routing address based on a look-up table lacking an application identifier routing address associated with the application identifier routing information, using the NFC controller;
determining whether the data packet includes protocol routing information based upon the data packet lacking the application identifier routing information, and routing the data packet to a default protocol routing address based upon the look-up table lacking a protocol routing address associated with the protocol routing information, using the NFC controller;
wherein the default application identifier routing address is different than the default protocol routing address;
determining whether the data packet includes technology routing information based upon the data packet lacking the protocol routing information, and routing the data packet to a default technology routing address based upon the look-up table lacking a technology routing address associated with the technology routing information, using the NFC controller;
where the data packet does not include application identifier routing information, protocol routing information, and technology routing information, routing the data packet to a default address, using the NFC controller;
wherein the default technology routing address is different than the default protocol routing address; and
wherein the default address is different than the default technology routing address, the default protocol routing address, and the default application identifier routing address.

US Pat. No. 9,396,790

MULTI-SUPPLY DUAL PORT REGISTER FILE

STMICROELECTRONICS INTERN...

1. A system comprising:
a plurality of isolated power domains comprising a memory cell power domain, a write power domain and a read power domain,
wherein:

the memory cell power domain is configured to supply a reference voltage to a memory cell reference voltage node;
the write power domain is configured to supply voltage to a first write domain node and a second write domain node; and
the read power domain is configured to supply voltage to a first read domain node, second read domain node and third read
domain node and sense voltage at a fourth read domain node;

a memory cell comprising a first inverter and a second inverter, a first node of the memory cell is electrically coupled to
an input node of the second inverter and an output node of the first inverter and a second node of the memory cell is electrically
coupled to an input node of the first inverter and an output node of the second inverter, a power supply node of the first
inverter and the second inverter being electrically coupled to the memory cell reference voltage node;

a write bit line electrically coupled to the first write domain node or the reference voltage of the memory cell power domain;
a complementary write bit line electrically coupled to the second write domain node or the reference voltage of the memory
cell power domain;

a first write access transistor having a source electrically coupled to the first node, a drain electrically coupled to the
write bit line and a gate electrically coupled to a write word line;

a second write access transistor having a source electrically coupled to the second node, a drain electrically coupled to
the complementary write bit line and a gate electrically coupled to the write word line;

a read word line electrically coupled to the first read domain node;
a read bit line electrically coupled to the second read domain node;
a read port comprising stacked first and second read transistors, the first read transistor having a source electrically coupled
to the read bit line, a drain electrically coupled to a source of the second read transistor, and a gate electrically coupled
to the read word line, the second read transistor having a drain electrically coupled to ground and a gate electrically coupled
to the second node of the static memory cell; and

a sense transistor having a gate electrically coupled to the third read domain node, a drain electrically coupled to the fourth
read domain node and a source electrically coupled to the read bit line.

US Pat. No. 9,325,324

PHASE LOCKED LOOP (PLL) CIRCUIT WITH COMPENSATED BANDWIDTH ACROSS PROCESS, VOLTAGE AND TEMPERATURE

STMicroelectronics Intern...

1. A phase locked loop (PLL) circuit, comprising:
a phase comparison circuit configured to compare phase of an input signal to phase of a feedback signal and generate a control
signal responsive to the phase comparison;

an oscillator circuit configured to generate an output signal at a frequency set by said control signal, where said feedback
signal is derived from said output signal;

wherein the oscillator circuit comprises a variable current source comprising a plurality of selectively actuated current
source circuits each biased by a bias signal;

wherein the oscillator circuit is configured to operate in a frequency locked loop (FLL) mode during a calibration mode of
operation to compare frequency of the input signal to frequency of the output signal and center a gain of the oscillator circuit
across process, voltage and temperature in response to the frequency comparison; and

wherein the bias signal comprises a reference voltage during the calibration mode of operation and the voltage of the control
signal when not in the calibration mode of operation.

US Pat. No. 9,651,958

CIRCUIT FOR REGULATING STARTUP AND OPERATION VOLTAGE OF AN ELECTRONIC DEVICE

STMicroelectronics Intern...

1. An electronic device, comprising:
a power supply node;
a ground node;
an intermediate ground node configured at a voltage between a voltage of the power supply node and a voltage at the ground
node; and

an error amplifier having an input stage coupled between the power supply node and the ground node, and an output stage coupled
between the power supply node and the intermediate ground node;

wherein the output stage comprises:
a first output transistor having a first conduction terminal coupled to the power supply node, a second conduction terminal
coupled to an output of the error amplifier, and a control terminal coupled to a first output of the input stage; and

a second output transistor having a first conduction terminal coupled to the intermediate ground node, a second conduction
terminal coupled to the output of the error amplifier, and a control terminal coupled to a second output of the input stage.

US Pat. No. 9,467,125

CMOS SCHMITT TRIGGER CIRCUIT AND ASSOCIATED METHODS

STMICROELECTRONICS INTERN...

1. A Schmitt trigger circuit comprising:
a signal input;
a first inverter coupled to the signal input and configured to operate at a first voltage;
a second inverter coupled downstream of the first inverter and configured to operate at a second voltage lower than the first
voltage;

a protection device coupled between the first inverter and the second inverter, and configured to limit a voltage input to
the second inverter at the second voltage;

a feedback circuit coupled downstream of the protection device between the first inverter and the second inverter and configured
to introduce hysteresis; and

an output circuit coupled to the second inverter and configured to provide an output signal at the second voltage.

US Pat. No. 9,444,440

TRANSITION DETECTOR

STMicroelectronics Intern...

1. A transition detector, comprising:
clock-pulse-generation circuitry configured to receive a clock signal and generate a clock pulse comprising a first pair of
consecutive opposite logic transitions in response to a single transition edge of the clock signal, said first pair of consecutive
opposite logic transitions separated by a length that is approximately equal to a length of a time window that is offset from
the single transition edge of the clock signal; and

data-pulse-generation circuitry configured to receive a data signal and generate a data pulse comprising a second pair of
consecutive opposite logic transitions in response to a single transition edge of the data signal, the data-pulse-generation
circuitry including delay circuitry configured to delay the generation of the data pulse; and

a logic circuit coupled to logically combine the data pulse and the clock pulse in order to detect whether the data pulse
and clock pulse simultaneously have a same logic state and generate an output signal in response thereto indicating that the
single transition edge of the data signal has occurred within said time window.

US Pat. No. 9,246,509

METHODS AND APPARATUS FOR OFFLINE MISMATCH REMOVAL IN SIGMA DELTA ANALOG-TO-DIGITAL CONVERTERS

STMICROELECTRONICS INTERN...

1. A sigma delta analog-to-digital converter comprising:
a first summing unit having a first input to receive an analog input;
a loop filter configured to filter an output of the first summing unit;
a quantizer configured to quantize an output of the loop filter and to provide a coarse quantized signal and a fine quantized
signal;

a segmented digital-to-analog converter (DAC) including a coarse DAC to receive the coarse quantized signal, a fine DAC to
receive the fine quantized signal and a second summing unit to combine outputs of the coarse DAC and the fine DAC and to provide
a feedback signal to a second input of the first summing unit;

recombination logic configured to combine the coarse quantized signal and the fine quantized signal; and
a calibration circuit, operable in a calibration mode, to calibrate the recombination logic to compensate for mismatch between
the coarse DAC and the fine DAC of the segmented DAC.

US Pat. No. 9,209,935

LOW COMPLEXITY MAXIMUM-LIKELIHOOD-BASED METHOD FOR ESTIMATING EMITTED SYMBOLS IN A SM-MIMO RECEIVER

STMicroelectronics Intern...

1. A method for estimating a vector of emitted symbols over a MIMO transmission channel emitted by a first plurality of emitting
antennas, comprising:
receiving a vector of received symbols on a second plurality of receiving antennas; and
estimating said vector of emitted symbols by:
determining a subset of all possible vectors of emitted symbols by defining intervals for each symbol of the vector of emitted
symbols;

wherein the intervals for each symbol of the vector of emitted symbols are defined by performing a sphere decoding process
that replaces an unknown difference between symbols of the vector of emitted symbols to be evaluated and symbols of the vector
of emitted symbols to be estimated with a predetermined factor;

calculating a metric associated with a criterion for each vector of the subset of all possible vectors of emitted symbols;
and

selecting an estimation for said vector of emitted symbol as the vector of emitted symbols among said subset which minimizes
said metric.

US Pat. No. 9,601,185

INTEGRATED CMOS CIRCUIT HAVING FIRST AND SECOND CIRCUIT PARTS

STMicroelectronics Intern...

1. A system, comprising:
a semiconductor substrate;
a random access memory defined in the semiconductor substrate;
a logic controller defined in the semiconductor substrate adjacent the random access memory, and configured to decode addresses
of memory cells of the random access memory and to perform read/write control for the random access memory;

the semiconductor substrate having, for the random access memory and the logic controller, an active upper layer comprising:
an upper doping well,
a remaining upper region,
first highly doped terminals arranged in the remaining upper region, and
second highly doped terminals arranged in the upper doping well,
wherein the remaining upper region is coupled to a first substrate supply;
wherein the second highly doped terminals are coupled to a common power supply dedicated to the random access memory, within
the random access memory;

wherein the upper doping well is coupled to a second substrate power supply dedicated to the logic controller, within the
logic controller;

wherein the second high doped terminals are coupled to an other power supply, within the logic controller;
an electrically conducting path coupling the upper doping well of the random access memory and the logic controller so that
the common power supply and the second substrate power supply are merged; and

a switching unit configured to selectively electrically short the common power supply, second substrate power supply, and
the other power supply to one another and to the second highly doped terminals of the logic controller;

wherein the system is configured to implement at least one radio communication mode, an operation of the at least one radio
communication mode being inactive when the switching unit is not coupling the second highly doped terminals of the logic controller
and the upper doping well of the logic controller.

US Pat. No. 9,559,708

CHARGE PUMP CIRCUIT FOR A PHASE LOCKED LOOP

STMicroelectronics Intern...

1. A circuit, comprising:
a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate first
and second control signals as a function of that comparison;

a node;
a switching node; and
an attenuation circuit coupled to the node and the switching node, and comprising a capacitor coupled in series between the
switching node and the node;

the attenuation circuit configured to
charge the capacitor and disconnect the switching node from ground based on assertion of the first control signal, and
discharge the capacitor and connect the switching node to ground based on assertion of the second control signal.

US Pat. No. 9,495,629

MEMORY CARD AND COMMUNICATION METHOD BETWEEN A MEMORY CARD AND A HOST UNIT

STMICROELECTRONICS INTERN...

1. A memory card adapted to communicate with a host unit, the memory card comprising:
a memory unit configured to store data;
a first direct communications interface coupled to said memory unit; and
a control unit coupled to said memory unit via said first direct communications interface and configured to
control an operation of said memory unit via said first direct communications interface, and
communicate with the host unit via a second communication interface between said control unit and the host unit, the second
communication interface being configured to transfer data at a frequency lower than a frequency of said first direct communications
interface so that communication with the host unit begins once a portion of the data to be transferred is communicated from
said memory unit,

receive a command from the host unit via the second communication interface, the host unit configured to wait a threshold
time period for a response to the command corresponding to a memory card response time in terms of a number of cycles of a
clock, the clock operating at a frequency of the second communication interface, and the threshold time period being based
upon the frequency of the second communication interface,

cooperate with said memory unit via the first direct communications interface to provide the response to the command based
upon the frequency of the first direct communications interface so that the response is provided within the threshold time
period, and

send the response to the host unit within the threshold time period via the second communication interface, wherein the response
would not be within the threshold time period if the frequency of the first communications interface was lower than the frequency
of the second communications interface.

US Pat. No. 9,189,049

POWER MANAGEMENT IN A DEVICE

STMICROELECTRONICS INTERN...

1. A device comprising:
a system-on-chip (SOC) hardware comprising a plurality of components including at least one clock;
a memory;
power subsystems configured as drivers for controlling the plurality of components of the SOC hardware;
a user interface configured to receive a selected power mode as an input and to identify profiles of one or more applications
being executed; and

a power driver configured to direct the power subsystems to change a mode of operation of at least one component of the SOC
hardware based on the selected power mode, wherein the at least one component is determined from the profiles of the one or
more applications being executed, wherein the selected power mode is selected from a group of an active mode, an active standby
mode, and a passive standby mode, and

wherein, before placing the device in the passive standby mode, data associated with an application is stored in the memory
such that, while in the passive standby mode, the memory is placed in a self-refresh mode so that any state data is available
for low latency recovery, and

if a clock is shared by any components, the power driver sends call back functions from all components sharing the clock to
scale down or switch off the clock when all components sharing the clock agree, and if the clock is exclusive to the component,
the power driver will scale down the clock directly;

a control unit for controlling power supplied to the components of the SOC hardware, wherein the power driver is further configured
to direct the control unit to switch off the power supplied to the plurality of components of the SOC hardware in the passive
standby mode; and

wherein, before placing the device in the active standby mode, data for a profile entry of the component and whether it is
customized is stored in memory, and the control unit retrieves the profile entry from memory and determines whether a component
is customized to resume operation from the active standby mode.

US Pat. No. 9,833,806

MICROFLUIDIC SYSTEM WITH SINGLE DRIVE SIGNAL FOR MULTIPLE NOZZLES

STMicroelectronics, Inc.,...

1. A device, comprising:
a microfluidic substrate;
an inlet path through the microfluidic substrate;
a plurality of heaters on the microfluidic substrate, each heater having:
an input contact; and
an output contact being positioned between the heater and the inlet path;
a first contact pad coupled to each of the output contacts;
a plurality of second contact pads, each second contact pad being coupled to a group of the input contacts, a number of second
contact pads being smaller than a number of the input contacts, the number of second contact pads being equal to a number
of groups of the input contacts.

US Pat. No. 9,804,225

SCHEME TO MEASURE INDIVIDUALLY RISE AND FALL DELAYS OF NON-INVERTING LOGIC CELLS

STMICROELECTRONICS INTERN...

1. A device, comprising:
a flip-flop;
a test device including:
an input;
a first output;
a plurality of test cells connected in series between the input of the test device and the first output of the test device;
and

a second output;
a subset of the plurality of test cells connected in series between and the input of the test device and the second output
of the test device;

a first circuit path coupled between an output of the flip-flop and the input of the test device;
a second circuit path coupled between an input of the flip-flop and the first and second outputs of the test device, the second
circuit path including a first multiplexor having:

a first input coupled to the first output of the test device;
a second input coupled to the second output of the test device;
a control input that receives a mode control signal indicating a first mode or a second mode; and
an output that supplies a signal from either the first or the second input of the first multiplexor based on the mode control
signal; and

a control circuit coupled to the test device that measures a first frequency of the first output of the test device when the
first multiplexor is in the first mode and measures a second frequency of the second output of the test device when the first
multiplexor is in the second mode;

wherein the control circuit calculates a delay of a single cell of the test cells based on a difference between the first
and the second frequencies, and a difference in the number of the plurality of test cells for the first output and the number
of test cells in the subset of the plurality of test cells for the second output.

US Pat. No. 9,613,696

MEMORY DEVICE INCLUDING DECODER FOR A PROGRAM PULSE AND RELATED METHODS

STMICROELECTRONICS INTERN...

1. An integrated circuit comprising:
an array of phase-change memory (PCM) cells;
a plurality of bitlines coupled to the array of PCM cells;
a first decoder circuit comprising a respective plurality of transistors having a first conductivity type being coupled together
and to a given bitline from among the plurality thereof and configured to inject a program current pulse into a selected PCM
cell from among the array thereof; and

a second decoder circuit comprising a plurality of transistors having a second conductivity type being coupled together and
to the given bitline and configured to discharge the given bitline at an end of the program current pulse.

US Pat. No. 9,473,162

METHOD FOR DIGITAL ERROR CORRECTION FOR BINARY SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER (ADC)

STMicroelectronics Intern...

1. A method, comprising:
generating, using control logic, a first binary code having M+1 bits, M being an integer greater than 1;
generating, using control logic, a second binary code having N?M+1 bits, N being an integer greater than M;
carrying out a first binary decision using successive approximation register (SAR) processing on the bits of the first binary
code by a first digital to analog conversion block of an analog to digital converter to generate a first voltage to be compared,
using a comparator, with an input voltage to be converted;

generating a first segment of M+1 confirmed bits based on the comparison of the first voltage with the input voltage;
after the first segment of M+1 confirmed bits are generated, carrying out a second binary decision using SAR processing on
the bits of the second binary code by a second digital to analog conversion block of the analog to digital converter to generate
a second voltage to be compared with said input voltage;

generating a second segment of N?M+1 confirmed bits based on the comparison of the second voltage with the input voltage;
assigning a weight to a Least Significant Bit (LSB) of the first binary code;
assigning the same weight to a Most Significant Bit (MSB) of the second binary code;
providing a voltage shift using an adder between the comparison of the first voltage with the input voltage and the comparison
of the second voltage with the input voltage, the voltage shift corresponding to half of the assigned weight in the analog-to-digital
(A/D) converter; and

generating a digital output code based on the first segment of confirmed bits, the second segment of confirmed bits and a
constant term corresponding to said voltage shift.

US Pat. No. 9,379,728

SELF-CALIBRATED DIGITAL-TO-ANALOG CONVERTER

STMicroelectronics Intern...

1. A circuit, comprising:
a plurality of current source cells coupled to an output and each configured to generate an output current in response to
digital-to-analog conversion of digital data, a sum of said output currents producing an output voltage; and

a calibration circuit comprising:
a training code generator configured to generate first and second training codes for application to the plurality of current
source cells as said digital data, the first and second training codes configured to isolate a selected one of the current
source cells;

an analog-to-digital converter configured to sample the output voltage in response to each of the first and second training
codes and generate corresponding first and second digital voltage signals;

a differencing circuit configured to determine a difference between the first and second digital voltage signals, said difference
being indicative of mismatch in the selected one of the current source cells;

an error code generator configured to generate a digital calibration signal in response to said difference and the digital
data for digital-to-analog conversion by the plurality of current source cells; and

a redundancy digital-to-analog converter configured to convert the digital calibration signal to an analog compensation signal
for application to said output.

US Pat. No. 9,147,453

PROGRAMMABLE DELAY INTRODUCING CIRCUIT IN SELF TIMED MEMORY

STMICROELECTRONICS INTERN...

1. A method for introducing a programmable delay in a memory device comprising a plurality of conducting layers and at least
one capacitor in a path of a signal to be delayed and being formed in a portion of the plurality of conducting layers, the
method comprising:
controlling the at least one capacitor being in the path of the signal to be delayed using at least one switch coupled to
the at least one capacitor, with a signal introducing the programmable delay passing through the at least one switch; and

controlling a state of the at least one switch based upon a selection signal.

US Pat. No. 9,148,099

HDMI RECEIVER

STMicroelectronics Intern...

1. An apparatus, comprising:
a HDMI receiver printed circuit board (PCB) having discrete components thereon comprising:
an HDMI cable connector on the HDMI receiver PCB and configured to receive a differential signal having a DC component at
first and second differential lines;

a first pull-up circuit coupled to the HDMI cable connector and configured to pull up the received differential signal, the
first pull-up circuit comprising first and second discrete resistors on the HDMI receiver PCB respectively coupled between
the first and second differential lines and a first voltage source;

a HDMI receiver integrated circuit (IC) having integrated components therein comprising:
third and fourth differential lines;
a second pull-up circuit configured to pull up the differential signal without the DC component thereof being present and
to output the differential signal thereafter, the second pull-up circuit comprising first and second integrated resistors
integrated within the HDMI receiver IC respectively coupled between the third and fourth differential lines and a second voltage
source;

an integrated HDMI receiver coupled to receive the differential signal as output by the second pull-up circuit, the HDMI receiver
being integrated using CMOS technology and within the HDMI receiver IC;

the HDMI receiver PCB further comprising a coupling circuit respectively coupling the first and second differential lines
to the third and fourth differential lines and configured to remove the DC component from the differential signal, the coupling
circuit comprising first and second discrete capacitors on the HDMI receiver PCB respectively coupling the first and second
differential lines to the third and fourth differential lines.

US Pat. No. 9,106,219

IMPEDANCE CALIBRATION CIRCUIT AND METHOD

STMicroelectronics Intern...

1. A circuit, comprising:
a driver with an adjustable driver impedance; and
an impedance calibration circuit, comprising:
a comparator configured to compare voltage levels at an external node and an internal node of the impedance calibration circuit
and to generate an output based on the comparison;

a programmable resistor coupled between the internal node and a chip ground line; and
respective resistor and capacitor components coupled between the external node and a first input of the comparator, and between
the internal node and a second input of the comparator;

wherein the resistor and capacitor components are coupled to said chip ground line and configured for symmetric noise injection
into the comparator from said chip ground line;

a counter configured to generate first calibration codes in response to the output for application to control said programmable
resistor; and

a digital filter circuit configured to filter said first calibration codes to generate second calibration codes for application
to control said adjustable driver impedance.

US Pat. No. 9,865,197

METHOD FOR DETERMINING A REFRESH FREQUENCY FOR A MATRIX OF OLED ACTIVE PIXELS AND CORRESPONDING DEVICE

STMICROELECTRONICS INTERN...

1. A method for determining a refresh frequency for a matrix of active OLED pixels, comprising:
controlling first and second dummy control circuits at a first time, the first and second dummy control circuits each being
a replica of a control circuit for the active OLED pixels;

wherein controlling the first dummy control circuit comprises applying a first voltage to an input thereof so as to obtain
a first output voltage therefrom;

wherein controlling the second dummy control circuit comprises applying the first voltage to an input thereof, and operating
the second dummy control circuit such that a leakage current flows therethrough, so as to obtain a second output voltage;

determining an elapsed time separating the first time from a second time at which a difference between the first and second
output voltages is greater than a threshold; and

determining the refresh frequency from the elapsed time.

US Pat. No. 9,851,731

ULTRA LOW TEMPERATURE DRIFT BANDGAP REFERENCE WITH SINGLE POINT CALIBRATION TECHNIQUE

STMicroelectronics Intern...

1. A bandgap voltage generator, comprising:
a first plurality of transistors each having a first terminal coupled to a positive power supply;
a second plurality of transistors each having a first terminal coupled to ground;
a first resistor having a first terminal coupled to a second terminal of a first transistor of the first plurality of transistors;
an output node of a bandgap reference voltage, the output node being between the first terminal of the first resistor and
the second terminal of the first transistor of the first plurality of transistors;

a second resistor having a first terminal coupled directly to a second terminal of the first resistor and to a second terminal
of a first transistor of the second plurality of transistors at a calibration junction, the calibration junction being in
the electric path of the bandgap reference voltage, the second resistor having a second terminal coupled directly to a second
terminal of a second transistor of the second plurality of transistors;

a third resistor having a first terminal coupled directly to a second terminal of a second transistor of the first plurality
of transistors, and a second terminal coupled directly to the second terminal of the second transistor of the second plurality
of transistors and to the second terminal of the second resistor;

a fourth resistor having a first terminal coupled to a second terminal of a third transistor of the first plurality of transistors;
an amplifier having a first terminal coupled to a second terminal of the fourth resistor, and a second terminal coupled to
the second terminal of the second resistor;

a fifth resistor having a first terminal coupled to the first terminal of the amplifier, and a second terminal coupled to
a second terminal of a third transistor of the second plurality of transistors;

a plurality of switches, each of the switches coupled to the calibration junction;
a plurality of calibration transistors having a current path selectively connected from the calibration junction to ground
through the switches, the path being connected to draw current through the first resistor at its second terminal and away
from the output node of the bandgap reference voltage; and

a calibration input at the plurality of calibration transistors that receives a calibration signal enabling a first set of
the plurality of the calibration transistors to draw current away from the output node of the bandgap reference and not enabling
a second set of calibration transistors to prevent them from drawing current away from the output node of the bandgap reference.

US Pat. No. 9,813,024

DEPLETED SILICON-ON-INSULATOR CAPACITIVE MOSFET FOR ANALOG MICROCIRCUITS

STMICROELECTRONICS INTERN...

1. A microcircuit, comprising:
a voltage supply;
an operational amplifier electrically coupled to the voltage supply, the operational amplifier having inverting and non-inverting
input terminals and an output terminal; and

a dual gate capacitive field effect transistor including:
a primary gate coupled to the output terminal of the operational amplifier;
a secondary gate coupled to a ground reference voltage;
a source region coupled to the voltage supply; and
a drain region coupled to the voltage supply, the transistor including a doped substrate and a buried oxide layer on the doped
substrate, and a decoupling capacitor having a first electrode including the source and drain regions and a second electrode
including the secondary gate.

US Pat. No. 9,494,992

MULTI-CORE PROCESSOR SYSTEM AVOIDING STOPPING OF CORES TOO CLOSE IN TIME

STMICROELECTRONICS INTERN...

1. A device comprising:
a central processing unit including a first core and a second core;
a power consumption management circuit for the central processing unit, the power consumption management circuit comprising:
a power consumption estimation block configured to estimate power consumption of the central processing unit based on information
related to a status of the central processing unit, the information related to the status of the central processing unit indicating
whether the central processing unit is in a first stop state in which the first core stops running or in a second stop state
in which the first core which has stopped running stays inactive until expiration of a timer;

an activity control block configured to generate an interrupt request based on the central processing unit being in the second
stop state, and use the estimated power consumption to determine a control to be applied to the central processing unit for
regulating a rate of change in power consumption of the central processing unit as a function of the interrupt request, the
control being to stop running of the second core of the central processing unit.

US Pat. No. 9,401,699

HIGH FREQUENCY LOW-GAIN NOISE RING-TYPE VCO OSCILLATOR LEADING TO A LOW-NOISE/AREA PLL

STMicroelectronics Intern...

1. A device comprising:
a ring oscillator configured to output an oscillator signal;
a first capacitor having a first terminal coupled to an output of the ring oscillator and a second terminal coupled to a variable
control voltage, a capacitance between the first terminal and the second terminal of the first capacitor varying based on
the variable control voltage, the first capacitor being configured to fine-frequency tune a frequency of the oscillator signal
output from the ring oscillator;

a first transistor configured to supply a drive current to the ring oscillator;
a second transistor coupled to the first transistor in a current mirror configuration;
a bias current generator configured to pass a bias current through the second transistor, a gate terminal of the second transistor
being electrically connected to a node between a drain terminal and the bias current generator;

a first switch coupled between the node and the drain terminal of the second transistor;
a second switch coupled between the node and the bias current generator;
a frequency divider configured to receive an oscillator signal output from the ring oscillator and to output a divided oscillator
signal;

a phase detector configured to receive the divided oscillator signal and an input oscillator signal and to output a phase
difference signal indicative of a phase difference between the divided oscillator signal and the input oscillator signal;
and

a loop filter coupled between the phase detector and the ring oscillator, the loop filter being configured to filter the phase
difference signal output from the phase detector and to output the variable control voltage to the second terminal of the
first capacitor.

US Pat. No. 9,319,341

LIMITATION OF SERIAL LINK INTERFERENCE

STMICROELECTRONICS INTERN...

1. A method of transmitting a plurality of frames of data over a serial interface, the method comprising:
for each frame of the plurality of frames of data:
generating a pseudo-random number;
asserting a read control signal at a moment in time, wherein a timing of the moment in time is influenced by the pseudo-random
number;

adjusting a threshold value as a function of the pseudo-random number;
comparing a data buffer fill level with the adjusted threshold value and asserting an enabling signal in response to satisfaction
of a comparison criterion;

enabling assertion of the read control signal in response to assertion of the enabling signal;
in response to the asserted read control signal, reading a frame of data from a data buffer; and
transmitting the read frame of data over the serial interface.

US Pat. No. 10,050,606

DECIMATION FIR FILTERS AND METHODS

STMicroelectronics Intern...

1. A cascaded integrator-comb (CIC) filter comprising:an mth order digital integrator configured to operate with modulo arithmetic and two's complement, the mth order digital integrator configured to receive input samples and to generate integrated input samples; and
a finite impulse response (FIR) filter configured to process the integrated input samples and produce output samples with a decimation factor k, the FIR filter comprising:
a plurality of multiplier accumulator circuits, each multiplier accumulator circuit configured to accumulate products of FIR filter coefficients and respective integrated input samples, wherein the FIR filter coefficients are derived as a difference of the mth order of original FIR filter coefficients, stored as the difference of the original FIR filter coefficients, and applied to respective multiplier accumulator circuits, wherein the original FIR filter coefficients have a first word length, and wherein the FIR filter coefficients have a second word length smaller than the first word length.

US Pat. No. 9,858,913

NOISE REMOVAL SYSTEM

STMICROELECTRONICS INTERN...

1. A system, comprising:
a signal unit configured to generate a digital signal; and
a noise removal system configured to receive the digital signal, the noise removal system comprising:
a transformation module configured to transform the digital signal from a time domain signal to a frequency domain signal,
the frequency domain signal being an f-digital signal;

a signal optimizer configured to perform a phase correction on the f-digital signal to produce an optimized digital signal,
the phase correction being based on a noise profile;

a threshold filter configured to generate a noise-filtered digital signal from the optimized digital signal by removing a
frequency bin having an amplitude less than an amplitude threshold, the noise-filtered digital signal comprising a dynamic
headroom; and

a signal synthesizer configured to process the noise-filtered digital signal to occupy the dynamic headroom.

US Pat. No. 9,812,219

AUTOMATIC TEST-PATTERN GENERATION FOR MEMORY-SHADOW-LOGIC TESTING

STMicroelectronics Intern...

1. A method for automated test pattern generation (ATPG), the method comprising:
generating a test pattern using respective ATPG memory address locations of a memory coupled to a logic circuit under test,
in an ATPG mode of operation;

wherein the generation of the test pattern using the respective ATPG memory address locations produces a voltage differential
at inputs to sense amplifiers coupled to the memory that is substantially equal to a voltage differential produced at the
inputs to the sense amplifiers by data memory address locations of the memory during a normal mode of operation;

applying the generated test pattern to the logic circuit under test.

US Pat. No. 9,685,209

CIRCUIT FOR GENERATING A SENSE AMPLIFIER ENABLE SIGNAL WITH VARIABLE TIMING

STMicroelectronics Intern...

1. A sense amplifier enable signal generating circuit, comprising:
an input coupled to a dummy bit line of a memory;
a voltage comparator circuit configured to compare a voltage on the dummy bit line to a threshold voltage and generate an
output signal in response thereto;

a multi-bit counter circuit configured to count a count value in response to the output signal;
a pull-up circuit configured to pull up the voltage on the dummy bit line in response to the output signal; and
a count comparator circuit configured to compare the count value to a count threshold and generate a sense amplifier enable
signal in response thereto.

US Pat. No. 9,606,180

SCAN COMPRESSION ARCHITECTURE FOR HIGHLY COMPRESSED DESIGNS AND ASSOCIATED METHODS

STMICROELECTRONICS INTERN...

1. An integrated circuit (IC) having a scan compression architecture comprising:
a test access input;
decompression logic coupled to said test access input;
a block of IC elements, coupled to the decompression logic, and including a plurality of IC elements coupled together to define
a first scan path and a plurality of downstream scan paths;

said block of IC elements including an initial data selector at an initial position of the first scan path and each of the
downstream scan paths;

an additional data selector sequentially moved down one additional IC element in each of the successive downstream scan paths
and configured to reconfigure an order of said IC elements within a respective downstream scan path;

compression logic coupled to said block of IC elements; and
a test access output coupled to said compression logic.

US Pat. No. 9,455,729

METHOD AND APPARATUS FOR AVOIDING SPURS IN CHIP

STMICROELECTRONICS INTERN...

9. An apparatus for rejecting spurs within a chip including at least one analog function and at least one digital function,
the spurs being timed by a clock signal derived from an output frequency of a high frequency fractional phase locked loop,
the apparatus comprising:
a frequency evasion manager configured to
determine at least one original analog rejection bandwidth associated with operation of the at least one analog function,
identify original spurs associated with operation of the at least one digital function and to affect the at least one original
analog rejection bandwidth,

obtain a final analog rejection bandwidth based on the at least one original analog rejection bandwidth,
obtain final spurs based on the original spurs,
determine a frequency shift of the output frequency of the high frequency fractional phase locked loop adapted to reject the
final spurs from the final analog rejection bandwidth, and

control the high frequency fractional phase locked loop so as to shift the output frequency by the frequency shift;
wherein the determined frequency shift is obtained by shifting the final spurs within a given range such that a weighted power
spectral density calculated on the final spurs inside the final analog rejection bandwidth is below a threshold value.

US Pat. No. 9,197,903

METHOD AND SYSTEM FOR DETERMINING A MACROBLOCK PARTITION FOR DATA TRANSCODING

STMICROELECTRONICS S.R.L....

1. A method for selecting a macroblock partition to transcode digital data with an arbitrary spatial resolution from a first
video standard to a second video standard, the method comprising:
a hardware decoder for decoding an input signal to generate the digital data, with the digital data being based on a single
input signal;

a hardware processor for processing the digital data corresponding to the first video standard, the processing comprising
resizing and anti-aliasing the digital data;

determining a plurality of partitions for a macroblock for transcoding the second video standard with an arbitrarily changed
spatial resolution and without any motion estimation;

generating at least one motion vector for a plurality of macroblock partitions so as to avoid motion estimation;
determining a plurality of macroblock residuals for the plurality of macroblock partitions;
selecting the macroblock partition and a macroblock encoding mode based on a minimum macroblock residual value selected from
the plurality of macroblock residuals; and

encoding the digital data based on the selected macroblock partition to the second video standard.

US Pat. No. 9,500,939

SAFETY FEATURE FOR PROJECTION SUBSYSTEM USING LASER TECHNOLOGY

STMicroelectronics intern...

1. A method for safely projecting an image comprising steps of:
Projecting an image on a projection surface by actuating a projector;
Computing a depth view corresponding to at least a portion of said projection surface;
Acquiring a captured image by a camera;
Detecting from said depth view and said captured image a presence of a human between said projector and the projecting surface,
wherein detecting comprises:

delimiting at least one area within said depth view;
applying a body feature recognition algorithm on an area of said captured image corresponding to said delimited area; and
determining that the human is present and located between said projector and the projecting surface when a body feature of
the human is recognized; and

Tuning said projector in response to the detection.

US Pat. No. 9,490,796

POWER-ON-RESET AND SUPPLY BROWN OUT DETECTION CIRCUIT WITH PROGRAMMABILITY

STMicroelectronics Intern...

1. A device comprising:
a supply voltage detector configured to
set independently programmable trip points,
set a programmable hysteresis voltage,
detect a supply voltage level, and
produce an active low internal reset signal depending on the detected supply voltage level, the independently programmable
trip points, and the programmable hysteresis voltage; and

a delay circuit configured to receive the active low internal reset signal and to introduce delays on rising and falling edges
of the active low internal reset signal to produce a final active low reset signal.

US Pat. No. 9,438,254

CHARGE PUMP CIRCUIT FOR A PHASE LOCKED LOOP

STMicroelectronics Intern...

1. A phase locked loop, comprising:
a phase frequency detector (PFD) configured to compare phases of an input signal and a feedback signal, and to generate therefrom
control signals;

an attenuation circuit coupled in series with the PFD and comprising:
first and second current sources;
a loop filter coupled between a voltage controlled oscillator (VCO) control node and a ground node;
a buffer having an input coupled to the VCO control node;
an impedance network coupled to the VCO control node and comprising at least one impedance element configured to be:
coupled to the first current source such that voltage at the VCO control node increases, based upon the control signals indicating
that the phase of the input signal leads the phase of the feedback signal, and

coupled to the second current source such that the voltage at the VCO control node decreases, based upon the control signals
indicating that the phase of the feedback signal leads the phase of the input signal;

a VCO coupled to the VCO control node and to generate an output signal based upon a signal at the VCO control node, the phase
of the output signal matching the phase of the input signal;

wherein the feedback signal is based upon the output signal.

US Pat. No. 9,430,188

METHOD FOR PROTECTING A CRYPTOGRAPHIC DEVICE AGAINST SPA, DPA AND TIME ATTACKS

STMICROELECTRONICS INTERN...

1. A method of operating a cryptographic device to reduce effects of power analysis attacks, the method comprising:
splitting cryptographic computations in the cryptographic device into a first set of cryptographic algorithm computations
and a second set of cryptographic algorithm computations and pseudo-randomly assigning the first and second sets of cryptographic
algorithm computations to a first crypto-processor and at least one second crypto-processor;

executing the first set of cryptographic algorithm computations with the first crypto-processor of the cryptographic device,
the first set of cryptographic algorithm computations providing encryption of a first set of data to be protected with a first
secret key;

executing the second set of cryptographic algorithm computations with the at least one second crypto-processor of the cryptographic
device for providing encryption of a second set of data different from the first set of data to be protected with a second
different secret key; and

generating varying power consumption from the first crypto-processor and the at least one second crypto-processor respectively
based upon the execution of the first and second sets of cryptographic algorithm computations, thereby reducing the effects
of power analysis attacks.

US Pat. No. 9,250,696

APPARATUS FOR REFERENCE VOLTAGE GENERATING CIRCUIT

STMicroelectronics Intern...

1. An apparatus comprising:
a reference voltage bias generator coupled to an external device having a maximum voltage rating and to an external voltage
source having a supply voltage potential; and

a reference voltage current booster coupled to the reference voltage bias generator, wherein
the reference voltage bias generator is configured to operate in a low supply mode when the supply voltage potential is not
greater than the maximum voltage rating,

the reference voltage bias generator is configured to operate in a high supply mode when the supply voltage potential is greater
than the maximum voltage rating,

the reference voltage bias generator is configured to generate:
a first reference voltage, wherein during the low supply mode, the first reference voltage is equal to the supply voltage
potential and during the high supply mode, the first reference voltage is equal to a first fraction times the supply voltage
potential; and

a second reference voltage, wherein during the low supply mode, the second reference voltage is equal to a ground potential,
and during the high supply mode, the second reference voltage is equal to a second fraction times the supply voltage potential,
and

the reference voltage current booster is configured to generate the first reference voltage and the second reference voltage
with increased drive capability when a plurality of input and output interface circuits are coupled to the reference voltage
bias generator.

US Pat. No. 9,142,322

MEMORY MANAGER

STMicroelectronics Intern...

1. A memory manager circuit, comprising:
an input node configured to receive sensor information regarding a region of an integrated circuit; and
a reliability aware intelligent memory management circuit configured to determine a likelihood that the region will cause
an error to data stored in the region, the likelihood being determined using a ranking table based on the sensor information
and on reliability information defining reliability of data storage in the region under different operating conditions, the
ranking table including a plurality of sensed-parameter tables, each sensed-parameter table being associated with a sensed
parameter of the region where each sensed parameter is part of the sensor information, and the ranking table further including
a final decision table that determines a final reliability parameter for the region using all of the sensed-parameters.

US Pat. No. 9,136,733

SYSTEM AND METHOD FOR SWITCHING BETWEEN A FIRST SUPPLY VOLTAGE AND A SECOND SUPPLY VOLTAGE OF A LOAD

STMicroelectronics Intern...

1. A system for switching between a first supply voltage and a second supply voltage of a load, the system comprising:
first circuitry configured to apply, at a first time, the first supply voltage to the load;
a regulator circuit configured to generate the second supply voltage, the second supply voltage being a regulated output voltage
of the regulator circuit;

second circuitry configured to apply, at a later second time, the second supply voltage to the load; and
third circuitry configured, prior to the second time, to apply the first supply voltage to an input node of the regulator
circuit;

a voltage reference circuit configured to generate a reference voltage; and
fourth circuitry configured to apply, at a third time equal to or later than the second time, the reference voltage to the
input node of the regulator circuit;

wherein the first supply voltage and the second supply voltage provide power to the load at the respective times.

US Pat. No. 9,689,924

CIRCUIT FOR TESTING INTEGRATED CIRCUITS

STMICROELECTRONICS INTERN...

1. An integrated circuit (IC) comprising:
at least one first group comprising a plurality of first portions to be tested, each of said plurality of first portions having
respective first test circuits; and

at least one second group comprising at least one second portion to be tested, the at least one second portion having at least
one respective second test circuit;

said at least one first and second groups being configured so that in use said first test circuits are configured to run in
parallel with said at least one second test circuit, and said first test circuits are configured to run serially;

wherein each of said first test circuits and at least one second test circuit comprises an output node configured to output
a first output signal as a test completed output signal and otherwise a second output signal; and

wherein said output node is coupled to an associated input node of a subsequent test circuit.

US Pat. No. 9,473,135

DRIVER CIRCUIT INCLUDING DRIVER TRANSISTORS WITH CONTROLLED BODY BIASING

STMicroelectronics Intern...

1. A circuit, comprising:
a first drive transistor coupled between a first supply node and an output node, the first drive transistor having a first
control terminal configured to receive a control signal from an input node, and further having a first body terminal;

a second drive transistor coupled between a second supply node and said output node, the second drive transistor having a
second control terminal configured to receive said control signal, and further having a second body terminal; and

a body bias generator circuit comprising a logic circuit with power supply terminals connected to said first and second supply
nodes and having inputs coupled to the input node and output node and outputs configured to apply a first body bias voltage
to said first body terminal and a second body bias voltage to said second body terminal;

wherein said first and second body bias voltages vary as a function of said control signal and a voltage at said output node.

US Pat. No. 9,397,622

PROGRAMMABLE HYSTERESIS COMPARATOR

STMicroelectronics Intern...

1. A circuit comprising:
a differential amplifier comprising a differential pair comprising a first transistor and second transistor, each of the first
and the second transistors comprising a front gate contact and a back gate contact;

an inverting circuit having an input and an output, wherein the input of the inverting circuit is coupled to an output of
the differential amplifier;

a first node between the input of the inverting circuit and the output of the differential amplifier;
a second node coupled to the output of the inverting circuit;
a first digital feedback loop coupled between the first node and the back gate contact of the first transistor; and
a second digital feedback loop coupled between the second node and the back gate contact of the second transistor, wherein
the first digital feedback loop is configured to be opposite in phase to the second digital feedback loop.

US Pat. No. 9,191,667

SYSTEM AND METHOD FOR TRANSCODING DATA FROM ONE VIDEO STANDARD TO ANOTHER VIDEO STANDARD

STMicroelectronics Intern...

1. A system for transcoding an input video bit stream having a first encoding profile into an output video bit stream having
a second encoding profile, comprising:
a first module configured to decode the input video bit stream having the first encoding profile to generate pixel data and
macroblock specifications; and

a second module operatively coupled to the first module, the second module configured to encode the pixel data and macroblock
specifications obtained from the first module to construct the output video bit stream having the second encoding profile,
the second module comprising a macroblock mapping module configured to select a macroblock coding mode for the output video
bit stream from among a plurality of macroblock coding modes supported by the second encoding profile that corresponds with
one or more macroblock coding modes supported by the first module.

US Pat. No. 9,184,748

ADAPTIVE BUFFER

STMicroelectronics Intern...

1. A circuit, comprising:
a node configured to be coupled to a signal-propagation medium, the signal-propagation medium having an impedance;
a driver having an adjustable output impedance and configured to drive a test signal onto the node;
a receiver configured to sense the test signal at a near end of the signal-propagation medium; and
a calibrator coupled to the node and comprising:
an emulated impedance stage configured to emulate the impedance of the signal-propagation medium,
a comparator configured to compare the test signal as sensed at a near end of the signal-propagation medium prior to arrival
of a reflection of the test signal off a far end of the signal-propagation medium to a voltage from the emulated impedance
stage, and

a code generator configured to generate, in response to the comparison between the sensed test signal as sensed and the voltage
from the emulated impedance stage, an impedance signal that is related to the impedance of the signal-propagation medium;

said driver further configured to adjust its output impedance of the driver in response to the impedance signal.

US Pat. No. 9,170,591

LOW DROP-OUT REGULATOR WITH A CURRENT CONTROL CIRCUIT

STMicroelectronics Intern...

1. A low drop-out regulator (LDO) circuit, comprising:
an LDO input connector to receive an input voltage;
an LDO output connector to supply an output voltage;
a power MOS transistor having a source connected to the LDO input connector and a drain connected to the LDO output connector;
an LDO differential amplifier connected to drive a gate of the power MOS transistor, and to receive a feedback signal from
the LDO output connector at a first input and a first reference voltage at a second input;

a small MOS transistor having a source connected to the LDO input connector, a gate connected between the LDO differential
amplifier and the gate of the power MOS transistor;

current source circuitry configured to provide a reference current, having an output connected to a drain of the small MOS
transistor;

a current-control differential amplifier configured to compare a voltage at the output of the current source circuitry with
a second reference voltage, the current-control differential amplifier having an AB type output stage connected between the
LDO input connector and a fixed low voltage;

a switch connected between the LDO differential amplifier and the gate of the small MOS transistor;
a comparator configured to compare the output voltage from the LDO output connector with a threshold voltage; and
a current controller configured to receive an indication from the comparator and output an output-capacitor signal.

US Pat. No. 10,050,640

HIGH SPEED DATA WEIGHTED AVERAGING ARCHITECTURE

STMicroelectronics Intern...

1. A circuit for generating a data weighted averaging signal from a thermometric code signal, comprising:a crossbar switch matrix having an input configured to receive the thermometric code signal and an output configured to output the data weighted averaging signal, wherein switching between the input and output by the crossbar switch matrix is controlled by a crossbar selection signal; and
a control circuit configured to receive a previous time cycle of the data weighted averaging signal and determine from bits of the previous time cycle of the data weighted averaging signal a bit location within the previous time cycle of the data weighted averaging signal where an ending logic transition occurs and generate the crossbar selection signal to control switching between the input and output by the crossbar switch matrix to select a bit location within a current time cycle of the data weighted averaging signal where a beginning logic transition occurs.

US Pat. No. 10,030,623

METHOD AND SYSTEM FOR IMPROVING THE EFFICIENCY OF 2-WHEELED AND 3-WHEELED MOTOR VEHICLES

STMICROELECTRONICS INTERN...

1. A two-wheeled or three-wheeled motor vehicle system, comprising:an engine having a rotor that rotates during a combustion cycle of the engine and a magneto system operably coupled to the rotor, the magneto system including one or more inductive coils and one or more permanent magnets;
a voltage converter electrically coupled to the magneto system to receive voltage from the magneto system when the magneto system is driven by the engine, and to provide voltage to the magneto system to cause the magneto system to start the engine; and
a controller communicatively coupled to the voltage converter and configured to cause the voltage converter to start the engine through a selective application of a battery voltage to the one or more inductive coils of the magneto system, in response to one or more motor vehicle system conditions.

US Pat. No. 9,509,373

METHOD FOR A CONTACTLESS COMMUNICATION BETWEEN TWO NFC DEVICES WITH IMPACT REDUCTION OF AN EXTERNAL NOISE EMISSION

STMICROELECTRONICS INTERN...

1. A method for contactless communication of information between a first device and a second device coupled via a near magnetic
field, the first and second devices each having an antenna, the method comprising:
within the first device, generating a digital data stream corresponding to information to be transmitter and generating a
first amplitude-modulated and dithered signal in the antenna of the first device from the digital data stream and from an
application of a first dithering, the first dithering being performed by converting the digital data stream to analog data
using a dithered clock signal so that samples of the digital data stream are taken with varying delays; and

within the second device, performing a frequency transposition of a second amplitude-modulated and dithered signal originating
from the first amplitude-modulated and dithered signal with application of a second dithering synchronous with the first dithering.

US Pat. No. 9,335,375

INTEGRATED DEVICE TEST CIRCUITS AND METHODS

STMICROELECTRONICS INTERN...

1. A circuit comprising:
an input node that receives a test signal;
a multiplexer that receives as input the test signal, an internal power-on reset signal, and a regulator by-pass signal, that
selects between the test signal and the internal power-on reset signal based on the regulator by-pass signal, and that outputs
one of the test signal and the internal power-on reset signal as a power-on reset multiplex signal;

a transition circuit that generates a transit on at least one voltage level indicator pin dependent on the power-on reset
multiplex signal; and

a data capture circuit that captures the output of the at least one voltage level indicator pin to determine a stuck-at fault.

US Pat. No. 9,923,566

SPREAD SPECTRUM CLOCK GENERATOR

STMicroelectronics Intern...

1. A circuit, comprising:
a locked-loop circuit including:
an oscillator configured to generate an output clock signal having a frequency set by a first oscillator control signal;
a modulator circuit having a first input configured to receive a second oscillator control signal and a second input configured
to receive a spread spectrum modulation control signal, said modulator circuit configured to generate a third oscillator control
signal by directly modulating the second oscillator control signal in response to said spread spectrum modulation control
signal; and

a filter circuit configured to generate said first oscillator control signal by filtering the third oscillator control signal;
and

a delta-sigma modulator circuit configured to modulate the spread spectrum modulation control signal in response to a modulation
profile so that said output clock signal is a spread spectrum clock signal.

US Pat. No. 9,819,344

DYNAMIC ELEMENT MATCHING OF RESISTORS IN A SENSOR

STMICROELECTRONICS INTERN...

1. An apparatus, comprising:
a sensor having a first terminal and a second terminal;
a resistor array coupled to the first terminal and the second terminal of the sensor and configured to compensate for resistor
mismatch seen by the sensor, each resistor in the resistor array having approximately the same resistance value, the resistor
array including:

a first group of resistors;
a second group of resistors;
a third group of resistors; and
a fourth group of resistors, a number of resistors in the fourth group being greater than a number of resistors in the third
group, the first group having a same number of resistors as the second group;

a switching device coupled to each group of resistors in the resistor array and configured to selectively couple a node from
each group of resistors to the first and second terminals of the sensor;

a comparator configured to provide a comparison signal indicative of a difference between a first output voltage of the resistor
array and an output voltage of the sensor; and

a current regulator coupled to an output of the comparator and configured to receive the comparison signal and regulate an
input current provided to the resistor array based on the comparison signal.

US Pat. No. 9,698,771

TESTING OF POWER ON RESET (POR) AND UNMASKABLE VOLTAGE MONITORS

STMicroelectronics Intern...

1. A circuit, comprising:
a power on reset (POR) circuit configured to monitor a supply voltage and output a POR signal in response to a comparison
of the supply voltage to a POR threshold voltage;

a first voltage monitoring circuit configured to monitor an input voltage and output a first voltage monitoring signal in
response to a comparison of the input voltage to a first voltage monitoring threshold;

an analog multiplexer circuit having a first input configured to receive the supply voltage and a second input configured
to receive a variable test voltage, said analog multiplexer having an output providing said input voltage to the first voltage
monitoring circuit, said analog multiplexer further having a control input configured to receive a control signal for selecting
between the first and second inputs; and

logic circuitry configured to logically combine the POR signal and the first voltage monitoring signal.

US Pat. No. 9,690,344

SYSTEM AND METHOD FOR A POWER SEQUENCING CIRCUIT

STMICROELECTRONICS INTERN...

1. A circuit comprising:
a main power supply coupled to a first node;
a charge reservoir coupled between a second node and a ground voltage;
an isolation circuit coupled between the first node and the second node;
a plurality of secondary power supplies coupled to the second node, the plurality of secondary power supplies configured to
receive power from the main power supply;

a detector circuit coupled to the first node, the detector circuit configured to detect the presence and absence of a first
supply voltage at the first node; and

a timing circuit coupled between the detector circuit and the plurality of secondary power supplies, the timing circuit comprising:
a first resistor-capacitor (RC) circuit for each of the plurality of secondary power supplies, the first RC circuits being
coupled between the detector circuit and one of the plurality of secondary power supplies; and

a second RC circuit for each of the plurality of secondary power supplies, the second RC circuits being coupled between the
detector circuit and one of the plurality of secondary power supplies, the first and second RC circuits each comprising:

a diode and a resistor in series between the detector circuit and a respective one of the plurality of secondary power supplies;
and

a capacitor coupled between the respective one of the plurality of secondary power supplies and a ground voltage;
wherein the detector circuit is further configured to:
determine the status of the first supply voltage at the first node;
couple a first input of the timing circuit to the first node and a second input of the timing circuit to a floating voltage
when the first supply voltage at the first node is a high voltage; and

couple the first input of the timing circuit to a floating voltage and the second input of the timing circuit to a ground
voltage when the first supply voltage at the first node is a low voltage.

US Pat. No. 9,613,692

SENSE AMPLIFIER FOR NON-VOLATILE MEMORY DEVICES AND RELATED METHODS

STMICROELECTRONICS INTERN...

1. A memory device comprising:
an array of phase-change memory (PCM) cells and complementary PCM cells;
a column decoder coupled to the array of PCM cells and complementary PCM cells and having first and second outputs;
a bitline coupled to the PCM cells;
a complementary bitline coupled to the complementary PCM cells; and
a sense amplifier coupled to the column decoder and comprising
a current integrator coupled to the first and second outputs and configured to receive first and second currents of a given
PCM cell and complementary PCM cell, respectively,

a current-to-voltage converter coupled to the current integrator and configured to receive the first and second currents and
to provide first and second voltages of the given PCM cell and complementary PCM cell to first and second nodes, respectively,

a differential comparator coupled to the first and second nodes and configured to generate an output signal from the first
and second voltages; and

a logic circuit directly coupled to the first and second nodes and configured to disable the column decoder and discharge
the bitline and complementary bitline voltages in response to the first and second voltages, respectively.

US Pat. No. 9,543,044

SYSTEM AND METHOD FOR IMPROVING MEMORY PERFORMANCE AND IDENTIFYING WEAK BITS

STMicroelectronics Intern...

1. A method for testing a memory, the method comprising:
receiving an address and a start signal at the memory;
generating a first detector pulse at a test circuit in response to the start signal, the first detector pulse having a leading
edge and a trailing edge;

detecting a data transition of a bit associated with the address, wherein the bit is a functional bit; and
determining whether the bit is a weak bit by determining whether the data transition occurred after the trailing edge, wherein
detecting the data transition comprises generating a pulse of a specific pulse width when the transition is detected and comparing
the generated pulse with the first detector pulse to determine that the data transition occurred after the trailing edge.

US Pat. No. 9,524,798

DATA SAMPLER CIRCUIT

STMICROELECTRONICS INTERN...

1. A circuit, comprising:
a first circuit stage configured to sample a differential input signal in response to a transition of a sampling clock to
a first logic state and regenerate the sampled differential input signal in response to a next immediate transition of the
sampling clock to a second logic state to output a first regenerated differential signal;

a second circuit stage configured to amplify the first regenerated differential signal in response to said next immediate
transition of the sampling clock to the second logic state to output an amplified differential signal; and

a third circuit stage configured to regenerate the amplified differential signal in response to an immediate subsequent transition
of the sampling clock back to the first logic state to output a second regenerated differential signal.

US Pat. No. 9,461,584

COMPENSATION CIRCUIT AND INVERTER STAGE FOR OSCILLATOR CIRCUIT

STMICROELECTRONICS INTERN...

1. An electronic device, comprising:
an oscillator circuit having a motional resistance and a negative resistance, and comprising a crystal coupled to a first
transistor; and

a compensation circuit coupled to the oscillator circuit and configured to modulate a first current of the first transistor
such that a transconductance of the first transistor increases the negative resistance in the oscillator circuit to compensate
for the motional resistance in the oscillator circuit;

wherein the compensation circuit comprises:
a second transistor having a first conduction terminal coupled to a node, a second conduction terminal coupled to a first
reference supply voltage, and a control terminal coupled to the first transistor such that a second current flowing through
the second transistor mirrors the first current;

a reference transistor having a first conduction terminal coupled to a second reference supply voltage, a second conduction
terminal coupled to said node, and a control terminal coupled to receive a bias voltage that biases the reference transistor
to generate a reference current applied to said node; and

a third transistor having a first conduction terminal coupled to said node, a second conduction terminal coupled to the second
reference supply voltage, and a control terminal for controlling generation of said first current, the third transistor configured
to carry a third current representing a difference between the reference current and the second current.

US Pat. No. 9,425,781

SYNCLESS UNIT INTERVAL VARIATION TOLERANT PWM RECEIVER CIRCUIT, SYSTEM AND METHOD

STMICROELECTRONICS INTERN...

1. A method of demodulating a pulse width modulation signal, comprising:
receiving the pulse width modulation signal, the pulse width modulation signal having first and second levels;
charging, by a first current source, a first capacitor in response to the pulse width modulation signal changing from the
first level to the second level during a first time interval;

charging, by a second current source, a second capacitor in response to the pulse width modulation changing from the second
level to the first level during the first time interval; and

demodulating the pulse width modulation signal for the first time interval based on voltages of the first and second capacitors.

US Pat. No. 9,401,715

CONDITIONAL PULSE GENERATOR CIRCUIT FOR LOW POWER PULSE TRIGGERED FLIP FLOP

STMicroelectronics Intern...

1. An electronic device, comprising:
a pulsed latch circuit configured to latch a data input signal to an output based upon receipt of a pulse signal; and
a pulse generation circuit configured to compare the data input signal and an output signal at the output of the pulsed latch
circuit, and to generate the pulse signal based upon a mismatch therebetween in response to a clock signal.

US Pat. No. 9,747,477

ULTRA-HIGH-FREQUENCY, UHF, RADIO FREQUENCY IDENTIFICATION, RFID, READER

STMICROELECTRONICS INTERN...

1. A communication device comprising:
a ultra-high frequency radio frequency identification (UHF RFID) reader adapted to selectively operate in a reader mode and
in a tag emulation mode,

wherein in the reader mode the UHF RFID reader communicates with at least one RFID tag to access information stored in the
at least one tag, and

wherein in the tag emulation mode the UHF RFID reader communicates with at least one other UHF RFID reader to share the information
with the at least one other UHF RFID reader, wherein the communication device is configured to directly communicate only with
other UHF RFID devices.

US Pat. No. 9,625,529

BATTERY PACK MANAGEMENT

STMicroelectronics, Inc.,...

1. A method, comprising:
measuring a voltage of a battery using measurement circuitry associated with the battery in real time while the battery is
discharging;

determining in real time while the battery is discharging and while the voltage of the battery is being measured, and using
a processor coupled to the measurement circuitry, a plurality of time periods, each time period being determined as a function
of the measured voltage of the battery that was measured in real time while the battery is discharging and each time period
corresponding to an elapsed time for the measured voltage of the battery to change in a voltage step from an initial voltage
for that time period to a final voltage for that time period, and each time period being associated with a first condition
of the battery;

calculating in real time while the battery is discharging and while the voltage of the battery is being measured, using the
processor, a run time to empty of the battery based on a given one of the determined plurality of time periods that was determined
as a function of the measured voltage of the battery that was measured in real time while the battery is discharging;

compensating in real time while the battery is discharging and while the voltage of the battery is being measured, using the
processor, a remaining capacity of the battery based on the calculated run time to empty of the battery, the compensating
being performed due to self discharge of the battery, based upon lack of variation of the first condition associated with
the given one of the determined plurality of time periods used in calculating the run time to empty of the battery, the given
one of the determined plurality of time periods having been determined as a function of the measured voltage of the battery
that was measured in real time while the battery is discharging;

compensating in real time while the battery is discharging and while the voltage of the battery is being measured, using the
processor, the remaining capacity of the battery based on the calculated run time to empty of the battery, the compensating
being performed due to the first condition of the battery, associated with the given one of the determined plurality of time
periods used in calculating the run time to empty, based upon variation of the first condition, wherein the self discharge
of the battery is a second condition of the battery, the given one of the determined plurality of time periods having been
determined as a function of the measured voltage of the battery that was measured in real time while the battery is discharging.

US Pat. No. 9,997,236

READ ASSIST CIRCUIT WITH PROCESS, VOLTAGE AND TEMPERATURE TRACKING FOR A STATIC RANDOM ACCESS MEMORY (SRAM)

STMicroelectronics Intern...

1. A circuit, comprising:a wordline configured to be coupled to a plurality of memory cells;
a pull-down transistor having a source-drain path connected between the wordline and a ground node; and
a bias circuit configured to apply a biasing voltage to a control terminal of the pull-down transistor to provide wordline underdrive in response to assertion of a read assist control signal, wherein the bias circuit comprises:
a first n-channel transistor coupled between a positive supply voltage node and the control terminal of the pull-down transistor;
a diode-connected first p-channel transistor coupled between the control terminal of the pull-down transistor and the ground node; and
a switching circuit configured to connect the first n-channel transistor in a diode-connected configuration in response to assertion of the read assist control signal.

US Pat. No. 9,837,718

DISPLAY ARRANGEMENT AND METHOD FOR FABRICATION OF A DISPLAY ARRANGEMENT

STMICROELECTRONICS INTERN...

1. A display arrangement, comprising:
a display device;
a conductive shield disposed over a peripheral portion of a major surface of the display device;
a ferrite layer disposed over the conductive shield and over the peripheral portion of the major surface of the display device;
and

a conducting line of an antenna disposed within a carrier and over the ferrite layer.

US Pat. No. 9,748,957

VOLTAGE LEVEL SHIFTER CIRCUIT, SYSTEM, AND METHOD FOR WIDE SUPPLY VOLTAGE APPLICATIONS

STMICROELECTRONICS INTERN...

1. A level shifter circuit configured to receive first and second complementary input signals, each of the first and second
complementary input signals having a value of either a first supply voltage or a first reference voltage and the level shifter
further including a strong latch circuit operable in response to the first and second complementary input signals to drive
one of first and second complementary output signals to a second supply voltage and including a weak latch circuit operable
to drive the other of the first and second complementary output signals to a second reference voltage;
wherein the strong latch circuit is coupled between a first supply voltage node and first and second complementary output
nodes on which the first and second output signals are provided, respectively;

wherein the weak latch circuit is coupled between a first reference voltage node and the first and second complementary output
nodes; and

wherein the level shifter circuit further includes:
a first input signal write circuit coupled between the first complementary output node and a second supply voltage node, the
first input signal write circuit configured to receive the first complementary input signal on a first complementary input
node and operable in response to the first complementary input signal to cause the strong latch circuit to drive the second
output signal on the second complementary output node to approximately a supply voltage on the first supply voltage node,
and the weak latch circuit operable responsive to the second output signal to drive the first output signal on the first complementary
output node to approximately a reference voltage on the first reference node; and

a second input signal write circuit coupled between the second complementary output node and the second supply voltage node,
the second input signal write circuit configured to receive the second complementary input signal on a second complementary
input node and operable in response to the second complementary input signal to cause the strong latch circuit to drive the
first output signal on the first complementary output node to approximately the supply voltage on the first supply voltage
node, and the weak latch circuit operable responsive to the first output signal to drive the second output signal on the second
complementary output node to approximately the reference voltage on the first reference node.

US Pat. No. 9,342,085

CIRCUIT FOR REGULATING STARTUP AND OPERATION VOLTAGE OF AN ELECTRONIC DEVICE

STMICROELECTRONICS INTERN...

1. An electronic device, comprising:
a power supply node;
a ground node;
an intermediate ground node configured at a voltage between a voltage of the power supply node and a voltage at the ground
node; and

an error amplifier having an input stage coupled between the power supply node and the ground node, and an output stage coupled
between the power supply node and the intermediate ground node;

wherein the error amplifier has a first input coupled to receive a reference voltage, and a second input coupled to receive
an intermediate reference voltage, and wherein the error amplifier is switchable between:

a startup mode wherein the error amplifier is configured to generate an output in response to the intermediate reference voltage
at the second input, and

a normal operation mode wherein the error amplifier is configured to generate the output in response to the reference voltage
at the first input

wherein the error amplifier comprises:
a first differential input stage having differential inputs coupled to receive the reference voltage and a second feedback
voltage, and having a first tail,

a second differential input stage having differential inputs coupled to receive the intermediate reference voltage and a first
feedback voltage, and having a second tail,

a first switch configured to couple the first tail of the first differential input stage to the ground node when in the normal
operation mode and to decouple the tail of the first differential input stage from the ground node when in the startup mode,
and

a second switch configured to selectively couple the second tail of the second differential input stage to the ground node
when in the startup mode and to decouple the tail of the second differential input stage from the ground node when in the
normal operation mode.

US Pat. No. 9,268,894

AREA OPTIMIZED DRIVER LAYOUT

STMICROELECTRONICS INTERN...

1. A method comprising:
designing a layout of a driver of a semiconductor device by
analyzing a schematic circuit for the driver, the schematic circuit comprising PMOSFETs and NMOSFETs;
grouping PMOSFETs coupled between first common nodes into one or more first classes;
grouping NMOSFETs coupled between second common nodes into one or more second classes; and
generating a layout for each MOSFET at each location in a layout area of the layout of the driver by
generating a super parameterized cell (PCELL) layout block comprising a master MOSFET PCELL and a master guard ring PCELL
for each of the first class and the second class, the master MOSFET PCELL comprising a first set of parameters for the MOSFET
and the master guard ring PCELL comprising a second set of parameters for the guard ring around the MOSFET, wherein the first
and the second parameters include all design rules relating to the layout of the driver, and

instantiating a child PCELL of the master MOSFET PCELL and the master guard ring PCELL at each location in the layout area,
the child PCELLs inheriting all the first and the second parameters and including layout cell location information.

US Pat. No. 10,134,894

DUAL GATE FD-SOI TRANSISTOR

STMicroelectronics Intern...

1. A device, comprising:a silicon substrate;
a first doped well having a first conductivity type;
a second doped well having the first conductivity type, the second doped well being physically separated from the first doped well;
a first pass gate formed on the silicon substrate, the first pass gate including a fully-depleted silicon-on-insulator (FD-SOI) dual gate NMOS transistor having:
a source terminal,
a drain terminal,
a primary gate,
a secondary gate in the first doped well, the primary gate having a first surface that is spaced apart from the secondary gate by a first distance, and
a secondary gate contact on the secondary gate, the secondary gate electrically coupled to the primary gate through the secondary gate contact, the secondary gate contact oriented in a direction transverse to the primary gate and extending from the secondary gate to a second surface, the second surface being spaced apart from the secondary gate by a second distance that is less than the first distance, each of the first voltage, the second voltage, and the third voltage being different from one another; and
a second pass gate formed on the silicon substrate, the second pass gate including a FD-SOI dual gate PMOS transistor having:
a source terminal,
a drain terminal,
a primary gate,
a secondary gate in the second doped well, and
a secondary gate contact on the secondary gate, the secondary gate electrically coupled to the primary gate through the secondary gate contact, the secondary gate contact oriented in a direction transverse to the primary gate.

US Pat. No. 9,865,333

TEMPERATURE COMPENSATED READ ASSIST CIRCUIT FOR A STATIC RANDOM ACCESS MEMORY (SRAM)

STMicroelectronics Intern...

1. A circuit, comprising:
a wordline;
a plurality of memory cells connected to the wordline;
a pull-down transistor having a source-drain path connected between the wordline and a ground node; and
a bias circuit configured to apply a temperature dependent biasing voltage to a control terminal of the pull-down transistor;
wherein the bias circuit comprises:
a first diode-connected transistor coupled between a positive supply voltage node and the control terminal of the pull-down
transistor; and

a second diode-connected transistor coupled between the control terminal of the pull-down transistor and the ground node.

US Pat. No. 9,786,364

LOW VOLTAGE SELFTIME TRACKING CIRCUITRY FOR WRITE ASSIST BASED MEMORY OPERATION

STMicroelectronics Intern...

1. An electronic device, comprising:
a bit line and a complementary bit line;
first and second cross coupled inverters;
a first pass gate coupled between the complementary bit line and the first inverter;
a second pass gate coupled between the bit line and the second inverter;
third and fourth cross coupled inverters;
a third pass gate coupled between the complementary bit line and the third inverter; and
a fourth pass gate coupled between the bit line and the fourth inverter;
wherein the first, second, and fourth inverters are powered between a supply node and a reference node, and the third inverter
is powered between a floating node and the reference node;

wherein the first pass gate and third pass gate are coupled in parallel.

US Pat. No. 9,753,480

VOLTAGE REGULATORS

STMicroelectronics intern...

1. A power supply, comprising:
a regulator circuit configured to generate a regulated signal in response to a selected one of a plurality of first reference
signals provided on a reference node of the regulator circuit;

a reference circuit configured to simultaneously generate the plurality of first reference signals; and
a controller configured to compare each of a plurality of second simultaneously generated reference signals to the regulated
signal and, in response to these comparisons, the controller configured to provide the selected one of the plurality of first
reference signals on the reference node of the regulator circuit, wherein the controller further includes:

a plurality of comparators, each comparator configured to compare the regulated signal to a corresponding one of the plurality
of second reference signals and to generate a corresponding output signal responsive to the comparison; and

a digital logic circuit coupled to receive the respective output signals from the plurality of comparators, the digital logic
circuit further configured to generate a count value based on the values of the output signals and configured to provide a
selected one of the plurality of first reference signals to the regulator circuit based upon the count value.

US Pat. No. 9,685,867

ELECTRICAL POWER SUPPLY

STMicroelectronics Intern...

1. An electrical power supply circuit for delivering power from a power source to a load, the electrical power supply circuit
comprising:
an power input node coupleable to the power source;
a step-up converter having an input coupled to the power input node;
a step-down converter having a step-down converter node and an output coupleable to the load;
a conductive bypass path;
a switching stage that includes: a first switch configured to selectively couple the step-down converter node of the step-down
converter to the input of the step-up converter via the bypass path that bypasses the step-up converter; a second switch configured
to selectively couple an output of the step-up converter to the step-down converter node of the step-down converter; and a
third switch configured to selectively couple the step-down converter node of the step-down converter to a ground; and

a controller configured to:
in a first mode, open the second switch and, alternatingly:
close the first switch and open the third switch; and
open the first switch and close the third switch; and
in a second mode, open the third switch and, alternatingly:
close the first switch and open the second switch; and
open the first switch and close the second switch.

US Pat. No. 9,673,521

DISPLAY ARRANGEMENT AND METHOD FOR FABRICATION OF A DISPLAY ARRANGEMENT

STMICROELECTRONICS INTERN...

1. A display arrangement, comprising
a display,
a conductive shield arranged at the display,
a ferrite layer, and
a conducting line of an antenna,
wherein the conductive shield covers a first area of a first main surface of the display at which the conducting line is arranged
and the ferrite layer is arranged between the conducting line and the conductive shield.

US Pat. No. 9,501,980

DISPLAY PANEL AND DISPLAY PANEL SYSTEM

STMICROELECTRONICS INTERN...

1. A display panel comprising:
an array of light elements arranged in n rows by m columns;
a controller configured to provide first drive data and second drive data,
at least one driver configured to directly drive a first one of said m columns or said n rows, wherein the controller is further
configured to provide control signals directly to the at least one driver of the display panel and directly to a panel output,
and wherein the controller is further configured to provide the control signals through the panel output to at least one second
driver in at least one other panel, wherein the control signals include a system clock, at least one pulse width modulation
timer clock, and a latch enable signal and are provided separately from the first drive data and the second drive data, wherein
the at least one driver is configured to drive each of the first one of said m columns or said n rows using first drive data
and according to the control signals received separately from the first drive data, wherein the at least one driver operates
with a duty cycle according to the at least one pulse width modulation timer clock, wherein the at least one driver of the
display panel is further configured to provide the second drive data by a serial data out (SDO) connection directly to a panel
output, and wherein the at least one driver is further configured to provide the second drive data through the panel output
to at the least one second driver in at the least one other panel; and

a plurality of MOSFETs, each of the plurality of MOSFETs connected to a respective first end of a second one of the m columns
or n rows;

wherein a second end of each of the second one of the m columns or n rows is connected directly to the panel output separately
from the SDO connection; and

wherein each of the plurality of MOSFETs is configured to control a row control signal and propagate the row control signal
through a respective one of the second one of the m columns or n rows of the display panel, and through the panel output to
the at least one other panel.

US Pat. No. 9,432,015

HYSTERESIS COMPARATOR CIRCUIT HAVING DIFFERENTIAL INPUT TRANSISTORS WITH SWITCHED BULK BIAS VOLTAGES

STMicroelectronics Intern...

1. A circuit, comprising:
a first differential circuit including a first transistor and a second transistor coupled as a first differential input pair,
at least one of the first and second transistors having a floating bulk;

a third transistor configured as a tail current source coupled to the first differential input pair;
a switching circuit configured to selectively apply a first bulk bias voltage and a second bulk bias voltage to said floating
bulk of the at least one of the first and second transistors in dependence on an output of the first differential circuit;
and

a bulk bias voltage generator circuit comprising:
a second differential circuit including a fourth transistor and a fifth transistor coupled as a second differential input
pair, at least one of the fourth and fifth transistors having a floating bulk;

a sixth transistor configured as a tail current source coupled to the second differential input pair; and
a differential amplifier circuit having a first input coupled to a first differential output of the second differential circuit
and a second input coupled to a second differential output of the second differential circuit and further having an output
coupled to floating bulk of the at least one of the fourth and fifth transistors and further coupled to supply at least one
of said first and second bulk bias voltages.

US Pat. No. 9,165,642

LOW VOLTAGE DUAL SUPPLY MEMORY CELL WITH TWO WORD LINES AND ACTIVATION CIRCUITRY

STMicroelectronics Intern...

1. A circuit, comprising:
a memory cell having a latch circuit with a true data storage node and a complement data storage node;
a true bitline;
a complement bitline;
a first access transistor coupled between the true bitline and the true data storage node;
a second access transistor coupled between the complement bitline and the complement data storage node;
bitline circuitry coupled to the true and complement bitlines, said bitline circuitry powered from a first set of power supply
voltages including a first high supply voltage; and

a wordline driver circuit including a true wordline coupled to a control terminal of the first access transistor and a complement
wordline coupled to a control terminal of the second access transistor, said wordline driver powered from a second set of
power supply voltages including a second high supply voltage that is greater than the first high supply voltage;

wherein the wordline driver circuit is configured, when the memory cell is operable in a read mode, to implement in a single
memory read cycle:

a first time period which starts at a beginning of the single memory read cycle comprising actuation of the first access transistor
while the second access transistor is simultaneously not actuated;

followed immediately by a second time period comprising actuation of the second access transistor while the first access transistor
is simultaneously not actuated which terminates at an end of the single memory read cycle.

US Pat. No. 10,405,384

DRIVING CIRCUIT USING BUCK CONVERTER CAPABLE OF GENERATING SUFFICIENT VOLTAGE TO POWER A LED CIRCUIT AND ASSOCIATED AUXILIARY CIRCUITRY IN A NORMAL MODE OF OPERATION, AND INSUFFICIENT TO POWER THE LED CIRCUIT BUT SUFFICIENT TO POWER THE ASSOCIATED AUXILIA

STMicroelectronics Intern...

1. A circuit, comprising:a voltage converter configured to convert a source voltage to a supply voltage at a first node as a function of a feedback voltage at a feedback node;
a first output path coupled between the first node and a second node; and
feedback circuitry configured:
when the circuit is in a first mode of operation, to couple the second node to the feedback node if a voltage at the second node exceeds a first overvoltage; and
when the circuit is in a second mode of operation, to couple the second node to the feedback node if the voltage at the second node exceeds a second overvoltage less than the first overvoltage; and
impedance circuitry coupled between the first node and a third node and configured to generate an auxiliary supply voltage and an auxiliary ground voltage when the circuit is in both the first and second modes of operation, the auxiliary supply voltage being less than the supply voltage in both the first and second modes of operation.

US Pat. No. 10,032,506

CONFIGURABLE PSEUDO DUAL PORT ARCHITECTURE FOR USE WITH SINGLE PORT SRAM

STMicroelectronics Intern...

1. A memory controller for a memory array having word lines and bit lines, the memory controller comprising:a row decoder configured to decode a row address and select a word line corresponding to the decoded row address;
a row pre-decoder configured to output an address to the row decoder as the row address,
a read-write clock generator configured to generate a hold clock signal; and
an address clock generator configured to receive a read address, a write address, a dual port mode control signal, a read chip select signal, and a write chip select signal;
wherein the address clock generator, when operating in dual port mode as indicated by the dual port mode control signal, and when operating in a read mode as indicated by the read chip select signal, is configured to latch the read address and output the read address to the row pre-decoder as the address as a function of the hold clock signal; and
wherein the address clock generator, when operating in dual port mode as indicated by the dual port mode control signal, and when operating in a write mode as indicated by the write chip select signal, is configured to latch the write address and output the write address to the row pre-decoder as the address as a function of the hold clock signal.

US Pat. No. 9,841,465

BATTERY DC IMPEDANCE MEASUREMENT

STMicroelectronics Intern...

1. A method of determining a state of charge of a battery comprising steps of:
calculating a DC impedance of the battery by:
performing a first constant current discharge of the battery at a first C-rate;
measuring voltage of the battery and current flowing from the battery during an interval of the first constant current discharge
and calculating an amount of charge extracted from the battery up to a point i where the voltage of the battery drops to a
first threshold value;

calculating a first state of charge as being equal to ((Qmax?Qi)/Qmax)×100, where Qmax is a total amount of charge extracted from the battery, and where Qi is the amount of charge extracted at the point i;

performing a second constant current discharge of the battery at a second C-rate lower than the first C-rate;
measuring the voltage of the battery and current flowing from the battery during an interval of the second constant current
discharge and calculating the amount of charge extracted from the battery up to a point j where the voltage of the battery
drops to a second threshold value;

calculating a second state of charge as being equal to ((Qmax?Qj)/Qmax)×100, where Qmax is the total amount of charge extracted from the battery, and where Qj is the amount of charge extracted at the point j; and

calculating the DC impedance of the battery, for a given state of charge as being: ((Vbatsecond C-rate?Vbatfirst C-rate)/(Iloadfirst C-rate?Iloadsecond C-rate), where Vbatsecond C-rate and Vbatfirst C-rate are the voltages of the battery measured at the second C-rate and the first C-rate and based upon the first and second states
of charge, respectively, and where Iloadsecond C-rate and Iloadfirst C-rate are the current flowing from the battery when discharging at the second C-rate and the first C-rate, respectively.

US Pat. No. 9,775,251

DC/DC CONVERTER CONTROL CIRCUIT INCLUDING A PLURALITY OF SERIES-CONNECTED TRANSISTORS AND A CAPACITIVE ELEMENT COUPLING NODES OF THE PLURALITY OF SERIES CONNECTED TRANSISTORS

STMICROELECTRONICS INTERN...

1. A circuit for controlling a power transistor of a direct current/direct current (DC/DC) converter, the circuit comprising:
first and second transistors coupled in series between a first reference voltage and a control terminal of the power transistor,
said first and second transistors defining a first junction node therebetween;

third and fourth transistors coupled in series between the control terminal and a second reference voltage, said third and
fourth transistors defining a second junction node therebetween, wherein a source terminal of the second transistor is coupled
with a drain terminal of the third transistor to form an output junction node, the output junction node being configured to
drive the control terminal of the power transistor;

said first and second transistors having a first conductivity type different from a second conductivity type of said third
and fourth transistors; and

a capacitive element coupled between the first and second junction nodes.

US Pat. No. 9,722,623

ANALOG-TO-DIGITAL CONVERTER WITH DYNAMIC ELEMENT MATCHING

STMICROELECTRONICS INTERN...

1. A device, comprising:
a plurality of comparator elements, each comparator element of the plurality of comparator elements having a first input connected
to an input port, each comparator element of the plurality of comparator elements having a second input port connected to
a reference signal port;

a switch matrix having routing circuitry connected to an output of each comparator of the plurality of comparators; and
a plurality of latches, each latch of the plurality of latches having an input connected to the routing circuitry;
wherein the routing circuitry is configured to connect the output of each comparator of the plurality of comparators to an
input of each latch of the plurality of latches according to one or more signals received at one or more control ports.

US Pat. No. 9,659,933

BODY BIAS MULTIPLEXER FOR STRESS-FREE TRANSMISSION OF POSITIVE AND NEGATIVE SUPPLIES

STMICROELECTRONICS INTERN...

1. An integrated circuit die comprising:
a semiconductor substrate;
a doped well in the semiconductor substrate;
a plurality of transistors including at least one PMOS transistor and at least one NMOS transistor having body regions positioned
in the doped well;

a temperature sensor that outputs a temperature signal indicative of a temperature of the semiconductor substrate;
a body bias generator that outputs a positive body bias voltage, a negative body bias voltage, and a ground body bias voltage;
and

a bias output multiplexer that receives the positive body bias voltage, the negative body bias voltage, and the ground body
bias voltage and selectively applies one of the positive body bias voltage, the negative body bias voltage, or the ground
body bias voltage to the doped well based at least in part on the temperature signal.

US Pat. No. 9,615,196

NFC DEVICE CONFIGURATION AFTER DEVICE POWER UP

STMICROELECTRONICS INTERN...

1. An electronic device, comprising:
a near field communications (NFC) controller; and
a secure element coupled to the NFC controller and configured to send first configuration data to the NFC controller and not
second configuration data;

wherein the first configuration data comprises data to be used by the NFC controller to generate responses to initial polling
and anti-collision commands from an external NFC device and not data to be used by the NFC controller in processing a command
from the external NFC device involving the use of an upper layer NFC protocol;

wherein the second configuration data comprises data to be used by the NFC controller in processing a command involving the
use of an upper layer NFC protocol from the external NFC device;

wherein the NFC controller is further configured to:
receive the command involving the use of the upper layer NFC protocol from the external NFC device, and
send a wait period request to the external NFC device that instructs the external NFC device to wait a given period of time
to receive a response to the command involving the use of the upper layer NFC protocol;

wherein the secure element is further configured to send the second configuration data to the NFC controller during the given
period of time.

US Pat. No. 9,590,602

SYSTEM AND METHOD FOR A PULSE GENERATOR

STMicroelectronics Intern...

1. A method of generating a clock pulse, the method comprising:
receiving an enable signal at an input of a tri-state buffer;
receiving a leading edge of an input clock at a clock input at a time when an enable signal is active, the clock input coupled
to a first input of a logic gate;

generating a leading edge of an output clock at a clock output based on the received leading edge of the input clock;
latching a logic value corresponding to the leading edge of the output clock at the clock output;
after the logic value is latched, feeding a value representative of the output clock back to second input of the logic gate
to prevent changes at the clock input from affecting the latched logic value and feeding the value representative of the output
clock back to a control input of the tri-state buffer to isolate the latched logic value from changes of the enable signal
at the input of the tri-state buffer;

resetting the latched logic value after a first delay time thereby causing a trailing edge at the clock output; and
maintaining the reset logic value until a second leading edge is received at the clock input.

US Pat. No. 9,564,904

ASYNCHRONOUS HIGH-SPEED PROGRAMMABLE DIVIDER

STMICROELECTRONICS INTERN...

1. A circuit, comprising:
an input configured to receive an input signal comprising most significant bits and least significant bits;
an adder configured to add the most significant bits of the input signal to an operand so as to generate a divisor;
a divider configured to divide a clock signal by the divisor a given number of times, the given number of times being equal
to two raised to a difference between a total number of bits in the input signal and a number of most significant bits in
the input signal;

a logic circuit configured to:
generate the operand as zero one less than the given number of times spread over the given number of times that the divider
is to divide the clock signal,

generate the operand as the least significant bits of the number signal one time during the given number of times that the
divider is to divide the clock signal.

US Pat. No. 9,412,424

NOISE TOLERANT SENSE CIRCUIT

STMICROELECTRONICS INTERN...

1. A method of controlling a sense circuit comprising a bit line coupled to a memory cell, a sense amplifier having a first
sensing node coupled to a first transistor and a second sensing node coupled to a second transistor, the second sensing node
coupled to the bit line through the second transistor, a power supply voltage coupled to the first sensing node through a
first reference line and configured to activate the bit line through a second reference line, a first decoupling device and
a first sampling device coupled to the first reference line, a second decoupling device and a second sampling device coupled
to the second reference line, and an inverter coupled to the second reference line, the method comprising:
applying a pre-charge ON signal to activate the first and second decoupling devices to pre-charge the first and second reference
lines, and to activate the inverter based on the power supply voltage from the second reference line to activate the bit line;

decoupling the power supply voltage from the first sensing node using the first decoupling device, and decoupling the power
supply voltage from activating the bit line using the second decoupling device during a read operation of the sense amplifier
in response to receiving a pre-charge OFF signal;

deactivating the first and second transistors in response to receiving a sense signal to activate the sense amplifier during
the read operation; and

activating the first and second sampling devices at an end of the read operation to couple the first reference line and the
second reference line, respectively, to the power supply voltage until a next pre-charge ON signal.

US Pat. No. 9,685,150

NOISE REMOVAL SYSTEM

STMICROELECTRONICS INTERN...

1. A system comprising:
a signal unit configured to provide a digital signal;
a noise removal system coupled to the signal unit, the noise removal system comprising
a transformation module configured to transform the digital signal into an f-digital signal,
a threshold filter configured to generate a noise filtered signal from the f-digital signal based on a threshold profile having
a single threshold value,

a signal synthesizer configured to
provide a gain to the noise filtered signal, and
transform the noise filtered signal into an output signal, and
a noise module configured to determine the threshold profile.