US Pat. No. 9,701,534

SEMICONDUCTOR DEVICE AND METHOD OF FORMING MEMS PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming an insulating material around the first semiconductor die;
forming an interconnect structure over the first semiconductor die and insulating material;
providing a second semiconductor die;
forming a cavity in the second semiconductor die;
disposing the second semiconductor die over the first semiconductor die; and
disposing a lid over the second semiconductor die.

US Pat. No. 9,576,873

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH ROUTABLE TRACE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
forming a lead having a top lead side opposite a bottom lead side;
forming routable traces directly on the top lead side, the routable traces having a top plate mounted thereon, and a portion
of the routable traces completely covering a side of the top plate facing the routable traces;

mounting an integrated circuit partially over the routable traces;
forming an encapsulation over and around the routable traces and the integrated circuit;
forming a hole through the encapsulation to the top plate; and
forming a protective coat having a top coat side directly on a side of the routable traces facing opposite of the top plate
and the protective coat directly on the encapsulation and a non-horizontal side of the lead.

US Pat. No. 9,545,013

FLIP CHIP INTERCONNECT SOLDER MASK

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
a masking layer including a plurality of elongated openings formed over a surface of the substrate;
a plurality of traces formed over the surface of the substrate including a first portion of the plurality of traces passing
beneath a first elongated opening of the plurality of elongated openings and parallel with respect to a first width across
the first elongated opening and a second portion of the plurality of traces passing beneath a second elongated opening of
the plurality of elongated openings and angled with respect to a second width across the second elongated opening; and

a semiconductor die disposed over the substrate and including a plurality of contact pads electrically connected to interconnect
sites on the traces.

US Pat. No. 9,543,258

SEMICONDUCTOR DEVICE AND METHOD OF FORMING HOLES IN SUBSTRATE TO INTERCONNECT TOP SHIELD AND GROUND SHIELD

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate including a first shielding layer disposed within the substrate;
a semiconductor die disposed over the first shielding layer, wherein a surface area of the first shielding layer is greater
than a surface area of the semiconductor die to extend beyond opposing sides of the semiconductor die; and

a second shielding layer formed over the semiconductor die and extending into the substrate to the first shielding layer.

US Pat. No. 9,391,046

SEMICONDUCTOR DEVICE AND METHOD OF FORMING 3D SEMICONDUCTOR PACKAGE WITH SEMICONDUCTOR DIE STACKED OVER SEMICONDUCTOR WAFER

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate formed from a semiconductor material and including a plurality of first conductive vias formed through
the substrate;

forming an insulating layer over the substrate and first conductive vias;
removing a portion of the insulating layer to expose the first conductive vias;
depositing a conductive material over the substrate in the insulating layer to form conductive traces in contact with the
first conductive vias;

providing a plurality of first semiconductor die including second conductive vias formed through the first semiconductor die;
disposing the plurality of first semiconductor die over the substrate including an active surface oriented toward the substrate;
forming an interconnect structure on the conductive traces and a surface of the substrate outside the first semiconductor
die and between side-by-side ones of the first semiconductor die;

disposing a second semiconductor die over the first semiconductor die and coupled to the interconnect structure with each
of the first semiconductor die completely within a footprint of the second semiconductor die, the second semiconductor die
being electrically connected through the interconnect structure to the conductive traces of the substrate and through the
second conductive vias to the first semiconductor die;

disposing a thermal interface material on the second semiconductor die; and
disposing a heat spreader over the second semiconductor die and extending to a top surface of the conductive traces of the
substrate after disposing the thermal interface material on the second semiconductor die.

US Pat. No. 9,502,267

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

11. An integrated circuit packaging system comprising:
a support structure having:
an internal insulation layer having a hole, a device connection side, and a system connection side opposite to the device
connection side, the internal insulation layer within the support structure,

a first conductive pad in the hole at the device connection side,
a second conductive pad having an internal surface directly on the system connection side,
an exterior insulation layer over the first conductive pad and directly on the device connection side, and
a second exterior insulation layer over and partially directly on a second pad external surface of the second conductive pad,
the second exterior insulation layer directly on the system connection side, and the second pad external surface facing away
from the internal surface;

an integrated circuit over the exterior insulation layer; and
an encapsulation over the integrated circuit.

US Pat. No. 9,385,052

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUILD-UP INTERCONNECT STRUCTURES OVER CARRIER FOR TESTING AT INTERIM STAGES

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first interconnect structure by,
(a) providing a first insulating layer, and
(b) forming a first conductive layer over the first insulating layer;
testing the first interconnect structure at a wafer-level;
after testing the first interconnect structure, disposing a semiconductor die over the first interconnect structure at the
same wafer-level as the testing of the first interconnect structure;

forming a vertical interconnect structure over the first interconnect structure, the vertical interconnect structure including
an inner conductive bump in contact with the first interconnect structure and protective layer disposed over the inner conductive
bump;

depositing an encapsulant over the semiconductor die, first interconnect structure, and vertical interconnect structure;
removing a portion of the encapsulant and a portion of the protective layer to expose the inner conductive bump;
forming a second interconnect structure over the encapsulant; and
removing a portion of the first insulating layer after forming the second interconnect structure.

US Pat. No. 9,385,074

SEMICONDUCTOR PACKAGE WITH EMBEDDED DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a conductive layer in a peripheral region around the semiconductor die; and
forming a first stud bump over the conductive layer by pressing a wire over the conductive layer under temperature to flatten
an end of the wire and form an enlarged base portion covering a top surface and side surface of the conductive layer.

US Pat. No. 9,449,932

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE SUBSTRATE WITH RECESSES FOR CAPTURING BUMPED SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a base substrate including a plurality of first recesses formed in a first surface of the base substrate;
a first conductive layer formed over a second surface of the base substrate opposite the first recesses; and
a first semiconductor die disposed over the base substrate with a plurality of interconnect structures of the first semiconductor
die disposed in the first recesses, wherein a portion of the base substrate within a footprint of the semiconductor die is
separated through the second surface of the base substrate to form electrically isolated leads.

US Pat. No. 9,437,552

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER AROUND SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
depositing an encapsulant between the semiconductor die;
designating a singulation area between the semiconductor die;
forming an insulating layer over the encapsulant in the singulation area;
forming a double channel in the insulating layer in the singulation area while leaving a portion of the encapsulant in the
singulation area covered by the insulating layer; and

singulating the semiconductor die through the insulating layer and encapsulant in the singulation area after forming the double
channel, the singulation area being devoid of conductive material.

US Pat. No. 9,385,100

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SURFACE TREATMENT AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
providing a base embedded trace substrate having traces and bonding sites embedded in a base material, the bonding sites lower
than a top surface of the base material;

forming a mask over the bonding sites;
forming an insulation layer on the traces, the insulation layer having a top surface coplanar with a top surface of the base
material;

removing the mask; and
connecting an integrated circuit die to the bonding sites; andwherein:
forming the insulation layer includes forming the insulation layer on the bonding sites.

US Pat. No. 9,379,064

SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING SEMICONDUCTOR DIE TO HEAT SPREADER ON TEMPORARY CARRIER AND FORMING POLYMER LAYER AND CONDUCTIVE LAYER OVER THE DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a shielding layer;
forming an interface layer over the shielding layer;
disposing a semiconductor die over the interface layer;
forming a first insulating layer over the shielding layer;
forming a via through a surface of the first insulating layer and extending through the first insulating layer to the shielding
layer; and

forming a first conductive layer over the surface of the first insulating layer and into the via to the shielding layer.

US Pat. No. 9,508,621

SEMICONDUCTOR DEVICE AND METHOD OF FORMING COMPLIANT STRESS RELIEF BUFFER AROUND LARGE ARRAY WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die or component including an electrical functionality and a mechanical functionality;
disposing a stress relief buffer including a compliant material partially along a side of the semiconductor die or component;
depositing an encapsulant over the semiconductor die or component and stress relief buffer; and
singulating through the stress relief buffer to expose the stress relief buffer from a side surface of the semiconductor device.

US Pat. No. 9,443,797

SEMICONDUCTOR DEVICE HAVING WIRE STUDS AS VERTICAL INTERCONNECT IN FO-WLP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
a semiconductor die mounted to a first surface of the substrate;
a wire stud including a base and wire stem extending from the base with the base attached to the first surface of the substrate,
wherein a height of the wire stud is less than or equal to a height of the semiconductor die;

an encapsulant deposited over the semiconductor die, wire stud, the first surface of the substrate, and a second surface of
the substrate opposite the first surface of the substrate; and

an interconnect structure formed over the encapsulant and extending to the wire stud.

US Pat. No. 9,443,762

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A THIN WAFER WITHOUT A CARRIER

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
a conductive via formed through the substrate;
an encapsulant deposited over a first surface of the substrate;
a first bump disposed in the encapsulant, wherein a surface of the first bump is coplanar with a surface of the encapsulant;
a first interconnect structure contacting a surface of the first bump over the first surface of the substrate; and
a second bump formed over or laterally offset from a surface of the conductive via opposite the first surface of the substrate.

US Pat. No. 9,443,828

SEMICONDUCTOR DEVICE AND METHOD OF EMBEDDING THERMALLY CONDUCTIVE LAYER IN INTERCONNECT STRUCTURE FOR HEAT DISSIPATION

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die;
a first thermally conductive layer formed over the first semiconductor die;
an interconnect structure formed over the first semiconductor die; and
a first conductive via formed through the first semiconductor die.

US Pat. No. 9,508,635

METHODS OF FORMING CONDUCTIVE JUMPER TRACES

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
disposing a semiconductor die on the substrate;
forming a first conductive trace and second conductive trace on the substrate adjacent to the semiconductor die;
forming a third conductive trace on the substrate between the first conductive trace and second conductive trace;
forming a first insulating layer over the third conductive trace;
forming a first conductive layer over the first insulating layer and electrically connected to the first conductive trace
and second conductive trace;

forming a bond wire extending from the semiconductor die to the first conductive trace, wherein the semiconductor die is electrically
coupled to the second conductive trace by the bond wire, first conductive trace, and first conductive layer; and

depositing an encapsulant over and around the semiconductor die, bond wire, first conductive trace, second conductive trace,
third conductive trace, and first conductive layer.

US Pat. No. 9,478,485

SEMICONDUCTOR DEVICE AND METHOD OF STACKING SEMICONDUCTOR DIE ON A FAN-OUT WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a plurality of contact pads formed over a central region of the first semiconductor
die;

forming a first conductive layer over the first semiconductor die and extending from the contact pads to a peripheral region
of the first semiconductor die;

forming a plurality of first interconnect structures over the first conductive layer in the peripheral region of the first
semiconductor die;

forming a first protective coating over the first semiconductor die and around the first interconnect structures;
removing a portion of the first semiconductor die opposite the first interconnect structures after forming the first protective
coating;

removing the first protective coating after removing the portion of the first semiconductor die;
providing a second semiconductor die including a plurality of bumps formed on an active surface of the second semiconductor
die;

disposing the first semiconductor die over the second semiconductor die with the bumps oriented away from the first semiconductor
die and with the first interconnect structures disposed around the second semiconductor die;

depositing an encapsulant around the first semiconductor die and second semiconductor die; and
forming a second conductive layer contacting the bumps and first interconnect structures.

US Pat. No. 9,437,482

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER ACTIVE SURFACE OF SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of semiconductor die with a plurality of contact pads formed over an
active surface of the semiconductor die;

forming a first opening into the active surface of the semiconductor die with the first opening extending partially through
the semiconductor wafer;

forming a second opening into a saw street in an inactive area of the semiconductor wafer between the semiconductor die with
the second opening extending partially through the semiconductor wafer;

forming a conductive layer over the active surface of the semiconductor die and into the first opening and second opening
to operate as a shielding layer extending over the active surface, into the first opening, and around side surfaces of the
semiconductor die; and

removing a portion of the semiconductor wafer opposite the active surface of the semiconductor die, wherein after removing
the portion of the semiconductor wafer the first opening extends from the active surface of the semiconductor die through
the semiconductor die to reach a second surface of the semiconductor die opposite the active surface of the semiconductor
die.

US Pat. No. 9,406,533

METHODS OF FORMING CONDUCTIVE AND INSULATING LAYERS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device comprising:
providing a substrate;
disposing a first semiconductor die over a surface of the substrate with an active surface of the first semiconductor die
oriented toward the substrate;

disposing an interconnect structure over the surface of the substrate adjacent to the first semiconductor die, wherein a surface
of the interconnect structure is substantially coplanar with a back surface opposite the active surface of the first semiconductor
die;

disposing an encapsulation material around the first semiconductor die and the interconnect structure;
disposing an insulating material over the encapsulation material and contacting the back surface of the first semiconductor
die; and

forming a first conductive material over a portion of the interconnect structure and the insulating material by,
(i) depositing the first conductive material over the portion of the interconnect structure and the insulating material including
a first state, wherein the first state comprises a liquid, viscous, or paste form, and

(ii) heating the first conductive material from the first state to a second state different from the first state, wherein
the second state comprises a solid, crystal, or sintered form.

US Pat. No. 9,397,236

OPTICAL SEMICONDUCTOR DEVICE HAVING PRE-MOLDED LEADFRAME WITH WINDOW AND METHOD THEREFOR

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die including an optically active area;
providing a substrate including a contact pad extending from a first surface of the substrate through an opaque perimeter
region of the substrate to a second surface of the substrate opposite the first surface of the substrate;

disposing a light transmitting material within an interior portion of the substrate to create a light transmitting region;
disposing the semiconductor die over the substrate to align the light transmitting region with the optically active area;
and

depositing an encapsulant over the semiconductor die and substrate, wherein an elevated area of the substrate blocks the encapsulant
to maintain light transmission through the light transmitting region to the optically active area of the semiconductor die.

US Pat. No. 9,397,058

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PATTERNED REPASSIVATION OPENINGS BETWEEN RDL AND UBM TO REDUCE ADVERSE EFFECTS OF ELECTRO-MIGRATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first conductive layer over the semiconductor die;
forming an insulating layer over the first conductive layer;
forming a first opening and a second opening in the insulating layer over the first conductive layer; and
forming a first bump over the first and second openings in the insulating layer.

US Pat. No. 9,385,066

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED LASER VIA INTERPOSER AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. An integrated circuit packaging system comprising:
a substrate;
an integrated circuit on the substrate;
an interposer substrate having interposer pads on the integrated circuit;
an encapsulant around the integrated circuit and the interposer substrate with holes in the encapsulant aligned over the interposer
pads, the holes being wider at the bottom and top of the holes than the middle of the holes; and

a conductive connector on and in direct contact with the interposer pads, in the holes in the encapsulant, and embedded in
the encapsulant.

US Pat. No. 9,385,101

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP-ON-LEAD INTERCONNECTION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die including an interconnect structure;
providing a substrate including a conductive trace formed over the substrate; and
bonding the interconnect structure to an upper surface and side surface of the conductive trace with a width of the interconnect
structure across the conductive trace less than a length of the interconnect structure along the conductive trace.

US Pat. No. 9,466,577

SEMICONDUCTOR INTERCONNECT STRUCTURE WITH STACKED VIAS SEPARATED BY SIGNAL LINE AND METHOD THEREFOR

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first conductive layer over the substrate;
forming a first insulating layer over the first conductive layer;
forming a first via in the first insulating layer to expose the first conductive layer and including a maximum width and a
minimum width that is different from the maximum width;

forming a second conductive layer over the first insulating layer and within the first via to electrically connect the second
conductive layer to the first conductive layer, the second conductive layer including an upper surface that follows a contour
of the first via;

forming a second insulating layer over the second conductive layer; and
forming a second via in the second insulating layer and extending into the first via to expose a flat surface of the second
conductive layer.

US Pat. No. 9,449,925

INTEGRATED PASSIVE DEVICES

STATS ChipPAC Pte. Ltd., ...

1. An intermediate structure for a semiconductor device, comprising:
a first substrate;
a first insulating layer formed over the substrate including a first trench;
an integrated passive device disposed over the first insulating layer;
a second insulating layer disposed over the integrated passive device and first substrate including a second trench aligned
with the first trench;

a conductive layer formed over the second insulating layer;
a third insulating layer formed over the second insulating layer and conductive layer;
an insulating material disposed continuously in the first trench and the second trench with the first trench and second trench
being devoid of conductive material;

a second substrate disposed over the third insulating layer; and
a non-conductive adhesive layer disposed between the third insulating layer and the second substrate.

US Pat. No. 9,385,009

SEMICONDUCTOR DEVICE AND METHOD OF FORMING STACKED VIAS WITHIN INTERCONNECT STRUCTURE FOR FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die including a contact pad formed on a surface of the semiconductor die;
depositing an encapsulant around the semiconductor die;
forming a first insulating layer in contact with a first surface of the encapsulant and the semiconductor die;
forming a first via through the first insulating layer extending to the contact pad of the semiconductor die;
forming a second via through the first insulating layer and extending to expose the encapsulant;
forming a first conductive layer over the first insulating layer and into the first via and second via to electrically connect
to the contact pad of the semiconductor die;

forming a conductive via through a second surface of the encapsulant opposite the first surface of the encapsulant and aligned
with the second via and extending to the first conductive layer after forming the first conductive layer;

forming a second insulating layer in contact with the first insulating layer and first conductive layer;
forming a third via through the second insulating layer and aligned with the second via and extending to the first conductive
layer;

forming a second conductive layer over the second insulating layer and into the third via over the first conductive layer
in the second via; and

forming a bump to contact the second conductive layer in the third via.

US Pat. No. 9,553,162

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS

STATS ChipPAC Pte. Ltd., ...

5. A semiconductor device, comprising:
a first semiconductor die including a light-sensitive sensor formed in an active region of the first semiconductor die;
a first encapsulant deposited over and extending completely around side surfaces of the first semiconductor die;
a first conductive layer formed directly on the first encapsulant and the first semiconductor die;
a first optically transmissive layer formed on the first semiconductor die over the active region and first conductive layer
including an opening completely through the first optically transmissive layer;

a second semiconductor die disposed in the opening of the first optically transmissive layer and connected to the first semiconductor
die by direct chip to chip assembly using a plurality of first conductive bumps;

a second encapsulant deposited within the opening of the first optically transmissive layer between the second semiconductor
die and first optically transmissive layer and contacting the first semiconductor die and side surfaces of the second semiconductor
die and first optically transmissive layer;

a second conductive bump formed completely through the first encapsulant directly over the first conductive layer and completely
outside a footprint of the first semiconductor die; and

a substrate including the first semiconductor die mounted to the substrate with a second conductive layer of the substrate
directly metallurgically connected to the second conductive bump and with the second conductive bump including a portion of
solder extending uninterrupted between the first conductive layer and second conductive layer.

US Pat. No. 9,545,014

FLIP CHIP INTERCONNECT SOLDER MASK

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a surface which is non-wettable by solder;
forming a plurality of traces over the non-wettable surface of the substrate;
forming a masking layer over the non-wettable surface of the substrate with the traces passing beneath first and second elongated
openings of the masking layer at interconnect sites and with the traces being parallel with respect to a width across the
first elongated opening and being angled with respect to a width across the second elongated opening;

disposing a semiconductor die over the substrate; and
coupling the semiconductor die to the interconnect sites on the substrate.

US Pat. No. 9,508,626

SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPENINGS IN THERMALLY-CONDUCTIVE FRAME OF FO-WLCSP TO DISSIPATE HEAT AND REDUCE PACKAGE HEIGHT

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a thermally-conductive frame;
forming an opening through the thermally-conductive frame;
depositing a sacrificial material in the opening of the thermally-conductive frame;
forming an interconnect structure over the thermally-conductive frame, the interconnect structure including an electrical
conduction path and thermal conduction path;

mounting a first semiconductor die to the electrical conduction path and thermal conduction path of the interconnect structure;
removing the sacrificial material from the opening of the thermally-conductive frame; and
mounting a second semiconductor die over a surface of the thermally-conductive frame opposite the first semiconductor die,
the second semiconductor die being electrically connected to the interconnect structure using a first bump disposed in the
opening of the thermally-conductive frame.

US Pat. No. 9,443,829

SEMICONDUCTOR DEVICE AND METHOD OF DUAL-MOLDING DIE FORMED ON OPPOSITE SIDES OF BUILD-UP INTERCONNECT STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming a first interconnect structure over the first semiconductor die;
disposing a second semiconductor die over the first interconnect structure opposite the first semiconductor die with an active
surface of the second semiconductor die oriented toward an active surface of the first semiconductor die; and

forming a second interconnect structure directly over the first semiconductor die, over the first interconnect structure,
and around the second semiconductor die.

US Pat. No. 9,437,538

SEMICONDUCTOR DEVICE INCLUDING RDL ALONG SLOPED SIDE SURFACE OF SEMICONDUCTOR DIE FOR Z-DIRECTION INTERCONNECT

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die including a first sloped side surface extending from an active surface to a back surface, the back
surface smaller than the active surface;

a conductive layer contacting the back surface of the first semiconductor die and the first sloped side surface and including
a segment comprising a surface coplanar with the active surface of the first semiconductor die;

an encapsulant disposed over the conductive layer and the first sloped side surface of the first semiconductor die, the back
surface of the first semiconductor die being devoid of the encapsulant;

a redistribution layer (RDL) formed over the encapsulant and the back surface of the first semiconductor die;
an interconnect structure formed under the surface of the conductive layer that is coplanar with the active surface of the
first semiconductor die and electrically connected to the conductive layer; and

a first bump formed under the interconnect structure.

US Pat. No. 9,431,331

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PENETRABLE FILM ENCAPSULANT AROUND SEMICONDUCTOR DIE AND INTERCONNECT STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die;
a plurality of bumps disposed adjacent to the semiconductor die; and
a multi-layer film encapsulant including,
(a) a thermo-setting adhesive film layer pressed over the semiconductor die and in contact with the bumps to embed the semiconductor
die and a first portion of the bumps,

(b) a ultraviolet B-stage film adhesive layer in contact with a first surface of the thermo-setting adhesive film layer with
a second portion of the bumps extending into the ultraviolet B-stage film adhesive layer, and

(c) a base layer in contact with a surface of the ultraviolet B-stage film adhesive layer opposite the thermo-setting adhesive
film layer.

US Pat. No. 9,379,084

SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor structure including a first interconnect site;
providing a second semiconductor structure including a second interconnect site;
depositing a conductive material self-confined between the first interconnect site and second interconnect site by a wettable
state of the conductive material; and

forming an insulating layer around the first interconnect site.

US Pat. No. 9,368,563

SEMICONDUCTOR DEVICE INCLUDING INTEGRATED PASSIVE DEVICE FORMED OVER SEMICONDUCTOR DIE WITH CONDUCTIVE BRIDGE AND FAN-OUT REDISTRIBUTION LAYER

STATS ChipPAC Pte. Ltd., ...

19. A semiconductor device, comprising:
a first semiconductor die;
a first insulating layer formed over the first semiconductor die;
a first inductor formed on a surface of the first insulating layer;
a second insulating layer formed over the first insulating layer and first inductor;
an encapsulant deposited around the first semiconductor die, first insulating layer, and second insulating layer; and
an interconnect structure formed over the first semiconductor die and first inductor.

US Pat. No. 9,484,259

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PROTECTION AND SUPPORT STRUCTURE FOR CONDUCTIVE INTERCONNECT STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of contact pads;
forming a first insulating layer over the semiconductor wafer and contact pads;
forming an under bump metallization layer over the contact pads and the first insulating layer;
forming a plurality of bumps over the under bump metallization layer;
forming a second insulating layer over the semiconductor wafer to completely cover the first insulating layer, a sidewall
of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps;

etching the second insulating layer to remove a portion of the second insulating layer covering the upper surface of the bumps
and a first portion of the sidewall of the bumps, while maintaining coverage of the second insulating layer over a second
portion of the sidewall of the bumps and the sidewall of the under bump metallization layer to provide structural support
for the bumps and form an area over the second insulating layer and between the bumps devoid of material; and

singulating the semiconductor wafer with the area over the second insulating layer and between the bumps devoid of material.

US Pat. No. 9,484,279

SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMI SHIELDING LAYER WITH CONDUCTIVE MATERIAL AROUND SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a temporary carrier including an interface layer;
disposing a first semiconductor die over the interface layer with an active surface of the first semiconductor die oriented
toward the interface layer;

depositing an encapsulant over the first semiconductor die;
forming a flat shielding layer over the encapsulant and a back surface opposite the active surface of the first semiconductor
die;

forming a channel completely around the semiconductor die, through the flat shielding layer and encapsulant, and partially
through the interface layer wherein a portion of the interface layer remains under the channel;

depositing conductive material in the channel completely around the semiconductor die and electrically connected to the flat
shielding layer, the conductive material contacting a sidewall of the interface layer;

removing the temporary carrier and the interface layer to expose the active surface of the first semiconductor die and the
conductive material including a sidewall of the conductive material; and

forming a build-up interconnect structure contacting the conductive material, encapsulant, and the active surface of the first
semiconductor die by,

(a) forming a redistribution layer (RDL) over the encapsulant and contacting both the exposed conductive material and the
active surface of the first semiconductor die, and

(b) forming an insulating layer over the RDL and contacting the exposed sidewall of the conductive material.

US Pat. No. 9,478,513

SEMICONDUCTOR DEVICE WITH CONDUCTIVE PILLARS HAVING RECESSES OR PROTRUSIONS TO DETECT INTERCONNECT CONTINUITY BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die;
a conductive pillar formed over a surface of the semiconductor die, wherein the conductive pillar includes an exterior sidewall
extending a height of the conductive pillar;

a recess formed in the exterior sidewall of the conductive pillar; and
a substrate including a bump material disposed over a surface of the substrate and into the recess.

US Pat. No. 9,418,962

SEMICONDUCTOR DEVICE AND METHOD OF FORMING WLP WITH SEMICONDUCTOR DIE EMBEDDED WITHIN PENETRABLE ENCAPSULANT BETWEEN TSV INTERPOSERS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first substrate having a plurality of first conductive vias formed partially through the first substrate;
mounting a first semiconductor die over the first substrate, the first semiconductor die including an active surface and electrically
connected to the plurality of the first conductive vias;

depositing an underfill between the first semiconductor die and first substrate;
providing a second substrate having a plurality of second conductive vias formed partially through the second substrate;
disposing the second substrate over the first substrate and first semiconductor die;
forming an interconnect structure between the first substrate and second substrate;
disposing a penetrable encapsulant between the first substrate and second substrate by,
(a) disposing the penetrable encapsulant over a surface of the second substrate, and
(b) embedding the first semiconductor die and interconnect structure in the penetrable encapsulant by pressing the second
substrate and the first substrate together;

removing a portion of the first substrate to expose the first conductive vias;
removing a portion of the second substrate to expose the second conductive vias; and
wire bonding the active surface of the first semiconductor die to at least one of the first conductive vias.

US Pat. No. 9,401,289

SEMICONDUCTOR DEVICE AND METHOD OF BACKGRINDING AND SINGULATION OF SEMICONDUCTOR WAFER WHILE REDUCING KERF SHIFTING AND PROTECTING WAFER SURFACES

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor wafer including a plurality of semiconductor die;
a trench formed through a saw street of the semiconductor wafer between the semiconductor die;
a protective coating disposed over a first surface of the semiconductor wafer and filling the trench between the semiconductor
die;

a die attach film disposed over a second surface of the semiconductor wafer opposite the first surface of the semiconductor
wafer; and

a modified region susceptible to fracture formed in the die attach film and aligned with the saw street between the semiconductor
die.

US Pat. No. 9,385,102

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUPPORTING LAYER OVER SEMICONDUCTOR DIE IN THIN FAN-OUT WAFER LEVEL CHIP SCALE PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a first supporting layer over the semiconductor die;
forming an encapsulant around the semiconductor die and over a side surface of the first supporting layer; and
forming an interconnect structure over the semiconductor die and encapsulant opposite the first supporting layer, wherein
a surface of the encapsulant opposite the interconnect structure is devoid of the first supporting layer.

US Pat. No. 9,378,983

SEMICONDUCTOR DEVICE AND METHOD OF MOUNTING COVER TO SEMICONDUCTOR DIE AND INTERPOSER WITH ADHESIVE MATERIAL

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
disposing a semiconductor die over a surface of the substrate;
forming a containment structure on the surface of the substrate and extending from the surface of the substrate to a height
less than a height of the semiconductor die;

providing a cover;
depositing a conductive adhesive material on the surface of the substrate between the semiconductor die and containment structure;
and

disposing the cover over the semiconductor die and substrate and in contact with the conductive adhesive material and containment
structure, wherein the containment structure blocks outward flow of the conductive adhesive material.

US Pat. No. 9,373,578

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE WITH CONDUCTIVE PADS HAVING EXPANDED INTERCONNECT SURFACE AREA FOR ENHANCED INTERCONNECTION PROPERTIES

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a conductive layer over the substrate;
forming a first insulating layer over the substrate including forming a first portion of the first insulating layer over the
conductive layer;

forming a first conductive pad over the first portion of the first insulating layer and the conductive layer to form an interconnect
surface area, the first conductive pad including an outer sidewall;

expanding the interconnect surface area by removing a first portion of the first conductive pad to form a plurality of recesses
in the first conductive pad, a first recess of the plurality of recesses forming a circular ring directly overlying the first
portion of the first insulating layer and the conductive layer; and

bonding a semiconductor die to the substrate by bonding an interconnect structure of the semiconductor die into the expanded
interconnect surface area and contacting the outer sidewall of the first conductive pad.

US Pat. No. 9,484,334

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DIRECTIONAL RF COUPLER WITH IPD FOR ADDITIONAL RF SIGNAL PROCESSING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming an integrated passive device (IPD) including,
a first conductive coil, and
a second conductive coil exhibiting mutual inductance with the first conductive coil;
providing a direct capacitive or inductive coupling between a conductive trace and a portion of the first conductive coil
disposed in proximity to the conductive trace with a portion of the first conductive coil remaining outside the proximity
of the conductive trace; and

forming a first capacitor including a first terminal coupled to a first end of the first conductive coil and a second terminal
coupled to a first end of the conductive trace.

US Pat. No. 9,431,316

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CHANNELS IN BACK SURFACE OF FO-WLCSP FOR HEAT DISSIPATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die including an active surface;
depositing an insulating material over a second surface of the semiconductor die opposite the active surface and around the
first semiconductor die;

planarizing a surface of the insulating material to the second surface of the first semiconductor die;
forming a channel in the second surface of the first semiconductor die;
forming a conductive via through the insulating material around the first semiconductor die;
forming a heat sink extending into the channel and over the surface of the insulating material and contacting the conductive
via; and

forming an interconnect structure over the insulating material and first semiconductor die and contacting the conductive via.

US Pat. No. 9,373,573

SOLDER JOINT FLIP CHIP INTERCONNECTION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first substrate including a first interconnect site;
providing a second substrate including a second interconnect site comprising a width less than a width of the first interconnect
site;

forming an interconnect structure between the first interconnect site and second interconnect site with the interconnect structure
including a tapered profile; and

disposing a non-wettable material outside the second interconnect site.

US Pat. No. 9,524,938

PACKAGE-IN-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die;
an insulating material disposed around a peripheral region of the first semiconductor die including a first surface of the
insulating material coplanar with a first surface of the first semiconductor die;

a conductive via formed through the insulating material with a side surface of the conductive via coplanar with a side surface
of the insulating material;

a bond pad formed on the first surface of the first semiconductor die;
a conductive trace formed between the bond pad and the conductive via; and
a second semiconductor die disposed over the first surface of the first semiconductor die.

US Pat. No. 9,368,423

SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE WITH CONDUCTIVE POSTS AND PROTECTIVE LAYERS TO FORM EMBEDDED SENSOR DIE PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a base and a plurality of conductive posts extending from the base;
forming a contact pad over a surface of a first conductive post of the plurality of conductive posts;
providing a semiconductor die including a sensor area;
disposing the semiconductor die over the base between the conductive posts with a back surface of the semiconductor die opposite
an active surface of the semiconductor die disposed below the contact pad;

forming an interconnect structure between the semiconductor die and the first conductive post;
disposing a penetrable adhesive layer over the semiconductor die and sensor area with a portion of the interconnect structure
embedded within the penetrable adhesive layer;

disposing a sacrificial layer over the penetrable adhesive layer;
depositing an encapsulant around the semiconductor die and conductive posts with a surface of the encapsulant coplanar with
a surface of the sacrificial layer; and

removing the sacrificial layer while leaving the penetrable adhesive layer over the semiconductor die and sensor area.

US Pat. No. 9,484,319

SEMICONDUCTOR DEVICE AND METHOD OF FORMING EXTENDED SEMICONDUCTOR DEVICE WITH FAN-OUT INTERCONNECT STRUCTURE TO REDUCE COMPLEXITY OF SUBSTRATE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die;
an insulating material deposited in a peripheral region around the first semiconductor die;
an interconnect structure formed over the first semiconductor die and including,
(a) a first conductive layer extending from a contact pad of the first semiconductor die over a surface of the insulating
material, and

(b) a plurality of bumps formed over the first conductive layer; and
a substrate including a second conductive layer, wherein the first semiconductor die is mounted to the substrate with the
bumps contacting the second conductive layer and a fan-out ratio (FR) of an I/O density of the first semiconductor die to
an I/O density of the substrate is given as FR=p2*(N/d2), where p is package pitch, N is number of non-redundant I/O per die, and d is die size.

US Pat. No. 9,601,369

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS WITH TRENCH IN SAW STREET

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
providing a second semiconductor die;
forming a first via through a first surface of the first semiconductor die;
forming a second via through the first surface of the first semiconductor die;
forming a trench in a peripheral region between the first semiconductor die and second semiconductor die and extending parallel
with adjacent edges of the first semiconductor die from the first via to the second via;

depositing a first conductive layer conformally in the trench and extending continuously from the first via to the second
via;

back-grinding a second surface of the semiconductor die opposite the first surface to remove a portion of the first conductive
layer in the trench; and

removing the peripheral region between the first semiconductor die and second semiconductor die to electrically isolate the
first via from the second via.

US Pat. No. 9,478,486

SEMICONDUCTOR DEVICE AND METHOD OF FORMING TOPSIDE AND BOTTOM-SIDE INTERCONNECT STRUCTURES AROUND CORE DIE WITH TSV

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first conductive layer;
disposing a first semiconductor die over the first conductive layer;
forming a first interconnect structure over the first conductive layer opposite the first semiconductor die;
forming a conductive via through the first semiconductor die with the conductive via extending from a first surface of the
first semiconductor die to a second surface of the first semiconductor die opposite the first surface;

forming an insulating layer around the first semiconductor die;
disposing a second conductive layer over the insulating layer and first surface of the first semiconductor die; and
forming a second interconnect structure over the second conductive layer.

US Pat. No. 9,390,991

SEMICONDUCTOR DEVICE AND METHOD OF FORMING WAFER LEVEL GROUND PLANE AND POWER RING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around a peripheral area of the semiconductor die to form a die extension region;
forming a plurality of conductive vias through the encapsulant in the die extension region;
forming a conductive plane over the semiconductor die and electrically connected to a first one of the conductive vias; and
forming a conductive ring over the semiconductor die and electrically connected to a second one of the conductive vias.

US Pat. No. 9,559,046

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-IN PACKAGE-ON-PACKAGE STRUCTURE USING THROUGH SILICON VIAS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die including a plurality of conductive vias formed through the first semiconductor die and
a build-up interconnect structure formed across an active surface of the first semiconductor die;

disposing a second semiconductor die over the first semiconductor die to form a first semiconductor package, wherein the second
semiconductor die includes a plurality of first bumps in direct contact with the build-up interconnect structure;

forming a plurality of second bumps in direct contact with the build-up interconnect structure outside a footprint of the
second semiconductor die after forming the first semiconductor package;

providing a substrate including a plurality of first conductive layers formed through the substrate and on a planar first
surface of the substrate;

disposing the first semiconductor package over the planar first surface of the substrate with the second bumps in direct contact
with the first conductive layers on the planar first surface of the substrate;

disposing a discrete component between the first semiconductor package and substrate;
depositing an encapsulant around the first semiconductor die and between the first semiconductor package and substrate; and
disposing a second semiconductor package over the first semiconductor die opposite the substrate, wherein the second semiconductor
package includes a plurality of third bumps in direct contact with the conductive vias.

US Pat. No. 9,527,723

SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICROELECTROMECHANICAL SYSTEMS (MEMS) PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die;
a modular interconnect structure including a conductive via disposed laterally adjacent to the first semiconductor die;
an encapsulant deposited between the first semiconductor die and the modular interconnect structure;
a conductive layer formed over the first semiconductor die and modular interconnect structure; and
a second semiconductor die disposed over the conductive layer, wherein the second semiconductor die includes a microelectromechanical
system.

US Pat. No. 9,525,080

SEMICONDUCTOR DEVICE WITH OPTICAL SENSOR AND METHOD OF FORMING INTERCONNECT STRUCTURE ON FRONT AND BACKSIDE OF THE DEVICE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing an insulating layer in contact with an active surface of the semiconductor die;
disposing a substrate over the semiconductor die and insulating layer;
depositing an encapsulant to surround the semiconductor die;
removing the substrate after depositing the encapsulant;
forming an opening in the insulating layer extending to the semiconductor die using a laser; and
forming a first conductive material within the opening and electrically connected to the semiconductor die.

US Pat. No. 9,449,943

SEMICONDUCTOR DEVICE AND METHOD OF BALANCING SURFACES OF AN EMBEDDED PCB UNIT WITH A DUMMY COPPER PATTERN

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a carrier;
providing a substrate;
forming a first conductive layer over a first surface of the substrate;
forming a second conductive layer over a second surface of the substrate, the second conductive layer including a dummy pattern
to approximately balance the second conductive layer with the first conductive layer;

disposing the substrate on the carrier;
disposing a semiconductor die on the carrier laterally offset from the substrate; and
depositing an encapsulant over the carrier between a side surface of the semiconductor die and a side surface of the substrate
that opposes the side surface of the semiconductor die.

US Pat. No. 9,589,910

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BASE LEADS FROM BASE SUBSTRATE AS STANDOFF FOR STACKING SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a base substrate including a conductive base material and first and second opposing surfaces;
a first conductive layer formed over the first surface of the base substrate and including a first contact pad, a second contact
pad, and a conductive trace extending from the first contact pad to the second contact pad;

a second conductive layer including an etch-resistant material formed over the second surface of the base substrate, wherein
portions of the base substrate form isolated base leads from the conductive base material disposed between the first conductive
layer and second conductive layer including a first base lead extending from the second contact pad of the first conductive
layer to a third contact pad of the second conductive layer;

a first semiconductor die mounted to the first conductive layer including a first conductive bump of the first semiconductor
die bonded to the first contact pad of the first conductive layer, wherein the second contact pad is located outside a footprint
of the first semiconductor die;

an encapsulant deposited over the first semiconductor die and first conductive layer; and
a second semiconductor die mounted to the first conductive layer opposite the first semiconductor die and between the base
leads including a second conductive bump of the second semiconductor die bonded to the first contact pad of the first conductive
layer directly opposite the first conductive bump.

US Pat. No. 9,558,958

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SACRIFICIAL PROTECTIVE LAYER TO PROTECT SEMICONDUCTOR DIE EDGE DURING SINGULATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming an insulating layer including a non-planar surface covering an entire surface of the semiconductor die;
forming a protective layer over the semiconductor die and covering the entire surface of the semiconductor die;
removing the protective layer; and
forming an interconnect structure over the semiconductor die.

US Pat. No. 9,401,331

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first conductive layer;
forming a conductive pillar over a first surface of a first portion of the first conductive layer;
disposing a semiconductor die over the first surface of a second portion of the first conductive layer; and
forming a bump over a second surface of the first conductive layer opposite the first surface of the conductive layer to contact
the first portion of the first conductive layer and second portion of the first conductive layer.

US Pat. No. 9,385,006

SEMICONDUCTOR DEVICE AND METHOD OF FORMING AN EMBEDDED SOP FAN-OUT PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor package further including,
(a) providing a substrate,
(b) disposing a first semiconductor die below a first surface of the substrate,
(c) depositing a first encapsulant below the first semiconductor die and completely covering the first surface of the substrate,
and

(d) disposing a plurality of first bumps directly on a second surface of the substrate opposite the first surface;
disposing a second semiconductor die over the second surface of the substrate between the first bumps including a back surface
of the second semiconductor die oriented toward the second surface of the substrate;

depositing a second encapsulant around the substrate, first semiconductor die, first encapsulant, first bumps, and second
semiconductor die, wherein an active surface opposite the back surface of the second semiconductor die and a portion of the
first bumps are exposed from the second encapsulant;

forming a first insulating layer over the second encapsulant and the active surface of the second semiconductor die;
forming a first conductive layer in contact with a contact pad of the second semiconductor die, the exposed portion of the
first bumps, and the first insulating layer; and

forming an interconnect structure over the first conductive layer, wherein a height of the semiconductor device is less than
1 millimeter (mm).

US Pat. No. 9,397,050

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PRE-MOLDED SEMICONDUCTOR DIE HAVING BUMPS EMBEDDED IN ENCAPSULANT

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer containing a plurality of semiconductor die;
forming a plurality of bumps on contact pads distributed across an entire surface of the semiconductor die;
depositing a first encapsulant over the semiconductor wafer to embed all of the bumps distributed across the entire surface
of the semiconductor die with the first encapsulant contacting a surface of all of the bumps opposite the contact pads;

singulating the semiconductor wafer to separate the semiconductor die while all of the bumps distributed across the entire
surface of the semiconductor die remain embedded in the first encapsulant;

depositing a second encapsulant over a side surface of the semiconductor die and further over a side surface of the first
encapsulant and further over a surface of the semiconductor die opposite the bumps;

removing a portion of the first encapsulant to form a plurality of openings over all of the bumps distributed across the entire
surface of the semiconductor die after depositing the second encapsulant;

forming a first interconnect structure contacting a first surface of the second encapsulant and the surface of the first encapsulant,
wherein the interconnect structure includes a conductive layer conformally applied over the first encapsulant and into the
openings to contact all of the bumps distributed across the entire surface of the semiconductor die;

forming a plurality of conductive pillars through the second encapsulant; and
forming a second interconnect structure over a second surface of the second encapsulant opposite the first surface of the
second encapsulant.

US Pat. No. 9,589,876

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A WAFER LEVEL PACKAGE WITH TOP AND BOTTOM SOLDER BUMP INTERCONNECTION

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die including an active surface and a back surface;
a second semiconductor die including an active surface and a back surface, wherein the active surface of the first semiconductor
die is attached to the back surface of the second semiconductor die;

a vertical interconnect structure disposed adjacent to the first semiconductor die;
an encapsulant deposited around the vertical interconnect structure, wherein the vertical interconnect structure extends partially
through the encapsulant from above the active surface of the first semiconductor die to beyond a first surface of the encapsulant;
and

a conductive layer formed over the first semiconductor die and a second surface of the encapsulant opposite the first surface
of the encapsulant, wherein the conductive layer extends into a first via in the encapsulant to contact the vertical interconnect
structure.

US Pat. No. 9,472,533

SEMICONDUCTOR DEVICE AND METHOD OF FORMING WIRE BONDABLE FAN-OUT EWLB PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
depositing a first encapsulant over the first semiconductor die;
forming an interconnect structure over the first semiconductor die and first encapsulant;
disposing a second semiconductor die over the first semiconductor die opposite the interconnect structure;
forming an opening in the first encapsulant adjacent to the first semiconductor die and over the interconnect structure; and
forming a bond wire in the opening in the first encapsulant and coupled between the second semiconductor die and interconnect
structure.

US Pat. No. 9,472,452

SEMICONDUCTOR DEVICE AND METHOD OF FORMING REPASSIVATION LAYER WITH REDUCED OPENING TO CONTACT PAD OF SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die including a first conductive layer;
forming a first insulating layer over the semiconductor die and first conductive layer;
forming an opening in the first insulating layer over the first conductive layer;
forming a second insulating layer over the first insulating layer; and
forming a via in the second insulating layer over the first conductive layer, wherein a width of the via is less than a width
of the opening in the first insulating layer.

US Pat. No. 9,401,347

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER OVER A SEMICONDUCTOR DIE DISPOSED IN A CAVITY OF AN INTERCONNECT STRUCTURE AND GROUNDED THROUGH THE DIE TSV

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a cavity;
disposing a first semiconductor die or component in the cavity of the substrate;
disposing a planar shielding layer over the first semiconductor die or component and electrically connected to the substrate;
forming a first opening in the planar shielding layer including a first slot extending along a length of the planar shielding
layer;

disposing a second semiconductor die or component over the planar shielding layer and electrically connected to the substrate;
and

dispensing an encapsulant into the cavity over the first semiconductor die or component through the first slot.

US Pat. No. 9,390,945

SEMICONDUCTOR DEVICE AND METHOD OF DEPOSITING UNDERFILL MATERIAL WITH UNIFORM FLOW RATE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming an insulating layer over a first surface of the substrate;
forming a plurality of openings in the insulating layer;
providing a semiconductor die including a first region with a first bump density and a second region with a second bump density
less than the first bump density;

disposing the semiconductor die over the first surface of the substrate; and
depositing an underfill material between the semiconductor die and substrate, wherein the openings in the insulating layer
reduce a flow rate of the underfill material proximate to the openings.

US Pat. No. 9,530,753

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CHIP STACKING AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
providing a first substrate having a first substrate non-horizontal side;
mounting an integrated circuit structure on the first substrate including:
mounting a base integrated circuit on the first substrate,
attaching an adhesive layer directly on the base integrated circuit, and
mounting a stack device directly on the adhesive layer;
mounting a second substrate on the integrated circuit structure, the second substrate includes conductive layers and conductive
traces embedded within the second substrate;

coupling a vertical chip to the first substrate and to the second substrate, the vertical chip having a bond pad, a vertical
chip stacking side, and a vertical chip outer side, the vertical chip outer side facing away from the bond pad and perpendicular
to the vertical chip stacking side directly on a component side of the first substrate, the bond pad coupled to the first
substrate and the second substrate with an arch interconnect, the arch interconnect in direct contact with the bond pad and
a top side of the second substrate;

coupling a second vertical chip on the component side and attached to the second substrate, the second vertical chip positioned
on the opposite side of the integrated circuit structure; and

forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second
substrate, the package body having a cavity between the vertical chip and the second vertical chip, the package body directly
on the vertical chip outer side and having a package body outer sidewall coplanar with the first substrate non-horizontal
side.

US Pat. No. 9,472,427

SEMICONDUCTOR DEVICE AND METHOD OF FORMING LEADFRAME WITH NOTCHED FINGERS FOR STACKING SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a leadframe including a first surface and a second surface opposite the first surface of the leadframe, the leadframe
including a first finger and a second finger with a die mounting site disposed between the first finger and second finger,
wherein a first portion of the first finger and a second portion of the second finger extend between the first surface and
second surface of the leadframe and a first notched portion of the first finger extends from the first portion of the first
finger along the second surface of the leadframe and a second notched portion of the second finger extends from the second
portion of the first finger along the second surface of the leadframe, wherein the first notched portion of the first finger
and the second notched portion of the second finger each have a height less than a height between the first surface and second
surface of the leadframe;

disposing a first semiconductor die over the die mounting site between the first finger and the second finger;
forming a bond wire between a contact pad on the first semiconductor die and the first notched portion of the first finger;
depositing an encapsulant over the first semiconductor die and bond wire and further over the first notched portion of the
first finger and the second notched portion of the second finger, wherein a surface of the encapsulant is coplanar with the
first surface of the leadframe; and

forming a bump over the first surface or second surface over the first portion of the first finger after depositing the encapsulant.

US Pat. No. 9,460,972

SEMICONDUCTOR DEVICE AND METHOD OF FORMING REDUCED SURFACE ROUGHNESS IN MOLDED UNDERFILL FOR IMPROVED C-SAM INSPECTION

STATS ChipPAC Pte. Ltd., ...

4. A semiconductor device, comprising:
a semiconductor die;
an interconnect structure formed over the semiconductor die; and
an encapsulant formed over and around the semiconductor die, wherein a surface of the encapsulant opposite the interconnect
structure comprises a first portion including a first surface roughness and a first average thickness around the semiconductor
die and a second portion including a second surface roughness and a second average thickness over the semiconductor die, the
second surface roughness less than the first surface roughness and the first average thickness of the encapsulant greater
than the second average thickness of the encapsulant.

US Pat. No. 9,418,941

SEMICONDUCTOR DEVICE AND METHOD OF FORMING B-STAGE CONDUCTIVE POLYMER OVER CONTACT PADS OF SEMICONDUCTOR DIE IN FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die including contact pads formed on an active surface of the semiconductor die;
a first insulating layer disposed in contact with the active surface of the semiconductor die;
a conductive polymer disposed in openings formed in the first insulating layer and in physical contact with the contact pads
of the semiconductor die;

an encapsulant disposed over the semiconductor die and the first insulating layer; and
an interconnect structure formed in physical contact with the first insulating layer and conductive polymer, the interconnect
structure being electrically connected through the conductive polymer to the contact pads on the active surface of the semiconductor
die.

US Pat. No. 9,406,531

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PHOTOIMAGABLE DIELECTRIC-DEFINED TRACE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. An integrated circuit packaging system comprising:
a photoimagable dielectric layer having a trace opening for exposing a carrier;
a trace within the trace opening;
an inner solder resist layer directly on the photoimagable dielectric layer and the trace, the inner solder resist layer having
a bond pad opening for exposing the trace, and the trace includes a trace recess partially filling the trace opening for mold
locking with the inner solder resist layer;

an integrated circuit over the inner solder resist layer, the integrated circuit electrically connected to the trace through
the bond pad opening;

an encapsulation directly on the integrated circuit and the inner solder resist layer; and
an external interconnect electrically coupled to the trace and the integrated circuit.

US Pat. No. 9,406,619

SEMICONDUCTOR DEVICE INCLUDING PRE-FABRICATED SHIELDING FRAME DISPOSED OVER SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a frame including,
(a) a plate,
(b) a body integrated on a surface of the plate, and
(c) a conductive pillar integrated on the surface of the plate and adjacent to the body;
a semiconductor die disposed over the body including a back surface of the semiconductor die oriented toward the body; and
an encapsulant disposed around the semiconductor die, body, and conductive pillar including a surface of the encapsulant coplanar
with an active surface of the semiconductor die opposite the back surface.

US Pat. No. 9,406,647

EXTENDED REDISTRIBUTION LAYERS BUMPED WAFER

STATS ChipPAC Pte. Ltd., ...

14. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die separated by a space;
depositing an insulating material in the space separating the semiconductor die;
forming a conductive layer over the insulating material and semiconductor die; and
forming a plurality of interconnect structures over the insulating material and semiconductor die.

US Pat. No. 9,564,413

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SEMICONDUCTOR DIE WITH ACTIVE REGION RESPONSIVE TO EXTERNAL STIMULUS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor wafer including a plurality of first semiconductor die, wherein each first semiconductor die
includes an active region comprising a sensor formed on a first surface of the first semiconductor die;

singulating the first semiconductor wafer to separate the first semiconductor die;
depositing an encapsulant over and around the first semiconductor die after singulating the first semiconductor wafer;
forming a first conductive layer over a first surface of the encapsulant and the first surface of the first semiconductor
die;

forming a transmissive layer over the active region of the first semiconductor die and first conductive layer;
forming an opening through the encapsulant outside a footprint of the semiconductor die and extending to the first conductive
layer;

depositing a bump material into the opening with the bump material contacting the first conductive layer and extending above
a second surface of the encapsulant opposite the first surface of the encapsulant;

providing a substrate including a second conductive layer formed over the substrate; and
mounting the first semiconductor die to the substrate with the bump material contacting the second conductive layer, wherein
the bump material comprises a portion of solder extending uninterrupted between the first conductive layer and second conductive
layer.

US Pat. No. 9,530,738

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE AND MOUNTING SEMICONDUCTOR DIE IN RECESSED ENCAPSULANT

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
disposing a first semiconductor die over the substrate;
disposing a first interconnect structure over the substrate adjacent to the first semiconductor die;
depositing an encapsulant over the substrate and around the first semiconductor die and first interconnect structure; and
forming a second interconnect structure to electrically couple the first interconnect structure and the first semiconductor
die after depositing the encapsulant.

US Pat. No. 9,601,434

SEMICONDUCTOR DEVICE AND METHOD OF FORMING OPENINGS THROUGH INSULATING LAYER OVER ENCAPSULANT FOR ENHANCED ADHESION OF INTERCONNECT STRUCTURE

STATS ChipPAC Pte. Ltd., ...

20. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited over the semiconductor die;
a first insulating layer formed over a surface of the encapsulant;
an interconnect site located outside a footprint of the semiconductor die, wherein the interconnect structures includes an
opening in the first insulating layer and a portion of the first insulating layer in an interior region of the interconnect
site;

a first conductive layer formed over the interconnect site to contact the portion of the first insulating layer and extending
into the opening to contact the surface of the encapsulant; and

forming a second insulating layer over the surface of the semiconductor die, wherein the first insulating layer extends over
the second insulating layer to contact a second conductive layer on the semiconductor die.

US Pat. No. 9,496,152

CARRIER SYSTEM WITH MULTI-TIER CONDUCTIVE POSTS AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of a carrier system comprising:
providing a carrier base, the carrier base formed from a metallic material;
forming a recess in the carrier base with the recess around a planar surface;
forming a first barrier on and protruding from the planar surface;
forming a second barrier on the carrier base in the recess;
forming a first post on the first barrier; and
forming a second post on the second barrier.

US Pat. No. 9,460,951

SEMICONDUCTOR DEVICE AND METHOD OF WAFER LEVEL PACKAGE INTEGRATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a silicon substrate capable of sustaining temperatures equal to or greater than 200° C.;
forming an interconnect structure over the silicon substrate at temperatures equal to or greater than 200° C. by,
(a) forming a multi-layer under bump metallization (UBM) comprising a wetting layer in contact with a surface of the silicon
substrate and an adhesion layer formed over the wetting layer,

(b) forming an insulating layer over the multi-layer UBM and substrate, and
(c) forming a conductive layer over the insulating layer;
disposing a semiconductor die over the interconnect structure;
depositing a first encapsulant over the semiconductor die with the first encapsulant disposed over a surface of the semiconductor
die opposite the interconnect structure and between the semiconductor die and interconnect structure;

removing a portion of the first encapsulant to planarize the first encapsulant with the surface of the semiconductor die;
depositing a second encapsulant over semiconductor die and first encapsulant;
removing the silicon substrate from over the wetting layer of the multi-layer UBM and insulating layer after disposing the
semiconductor die over the interconnect structure; and

forming a plurality of first conductive bumps contacting the wetting layer of the multi-layer UBM.

US Pat. No. 9,496,195

SEMICONDUCTOR DEVICE AND METHOD OF DEPOSITING ENCAPSULANT ALONG SIDES AND SURFACE EDGE OF SEMICONDUCTOR DIE IN EMBEDDED WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of semiconductor die;
forming an insulating layer over the semiconductor wafer;
removing a portion of the insulating layer along a surface edge of the semiconductor die;
forming a conductive layer over the semiconductor wafer;
singulating the semiconductor wafer into the plurality of semiconductor die;
depositing an encapsulant over the semiconductor die to cover a side of the semiconductor die and the surface edge of the
semiconductor die after singulating the semiconductor wafer; and

forming a conductive bump on the conductive layer after depositing the encapsulant.

US Pat. No. 9,418,878

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ADHESIVE MATERIAL TO SECURE SEMICONDUCTOR DIE TO CARRIER IN WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing an adhesive material over a surface of the semiconductor die as a plurality of adhesive bumps; and
depositing an encapsulant around the semiconductor die and over the surface of the semiconductor die.

US Pat. No. 9,418,913

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER ON CONDUCTIVE TRACES FOR ELECTRICAL ISOLATION IN FINE PITCH BONDING

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
an interconnect site contacting a surface of the substrate;
a surface treatment formed over a top surface and a side surface of the interconnect site;
a conductive trace formed over the surface of the substrate less than 150 micrometers from the interconnect site and electrically
isolated from the interconnect site; and

a copper oxide layer formed over the conductive trace with the interconnect site and surface treatment devoid of the copper
oxide layer.

US Pat. No. 9,412,624

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUBSTRATE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

11. An integrated circuit packaging system comprising:
a substrate including:
a first trace layer,
a first via layer on the first trace layer, the first via layer having vertical sidewalls,
an encapsulation on the first trace layer and the first via layer, the first trace layer having a surface exposed from the
encapsulation with a rough texture characteristic of removal of a conductive carrier coating,

a second trace layer on the encapsulation and over the first trace layer, the second trace layer connected to the first trace
layer through the first via layer,

a protective layer on the first trace layer and the second trace layer; and
an integrated circuit die attached to the substrate.

US Pat. No. 9,847,253

PACKAGE-ON-PACKAGE USING THROUGH-HOLE VIA DIE ON SAW STREETS

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die singulated from a semiconductor wafer as a first singulated semiconductor die, the first singulated
semiconductor die including a plurality of first contact pads;

a first organic material deposited in a peripheral region outside a footprint of the first singulated semiconductor die over
a side surface remaining from singulation and extending from a first surface of the first singulated semiconductor die to
a second surface of the first singulated semiconductor die opposite the first surface;

a plurality of first conductive vias formed through the first organic material in the peripheral region outside the footprint
of the first singulated semiconductor die;

a plurality of conductive traces formed over the first singulated semiconductor die respectively between the first conductive
vias and first contact pads;

a plurality of first bumps formed over the first conductive vias or the first singulated semiconductor die; and
a second semiconductor die disposed over the first singulated semiconductor die and electrically connected to the first bumps.

US Pat. No. 9,824,975

SEMICONDUCTOR DEVICE AND METHOD OF FORMING STEPPED INTERCONNECT LAYER FOR STACKED SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
depositing an encapsulant around the first semiconductor die;
forming a first stepped interconnect structure over a surface of the encapsulant by,
(a) forming an insulating layer, and
(b) forming a conductive via through the insulating layer; and
forming an opening in the insulating layer of the first stepped interconnect structure, wherein the opening extends through
the insulating layer over the first semiconductor die.

US Pat. No. 9,607,938

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH EMBEDDED PAD ON LAYERED SUBSTRATE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
forming a dielectric core having an embedded pad, another embedded pad, a surface trace between the embedded pad and the another
embedded pad, and having core sidewalls, the core sidewalls extending between a core top side of the dielectric core and a
pad top surface of the embedded pad, and a portion of the core sidewalls exposed from the embedded pad;

forming a top solder resist layer on the dielectric core, a pad top surface of the embedded pad below the top solder resist
layer, the top solder resist layer exposing a mounting region continuously exposing both the embedded pad and the another
embedded pad, and the surface trace exposed from the dielectric core within the mounting region;

forming a device interconnect on the embedded pad, the device interconnect in contact with the core sidewalls; and
mounting an integrated circuit device having an interconnect pillar, the interconnect pillar attached to the device interconnect
for mounting the integrated circuit device to the dielectric core.

US Pat. No. 9,824,923

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE PILLAR HAVING AN EXPANDED BASE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die;
a first conductive layer formed over a first surface of the first semiconductor die; and
a first conductive pillar formed in contact with the first conductive layer, the first conductive pillar including,
(a) a body with a first width, and
(b) an expanded base with a second width at the first conductive layer greater than the first width,
wherein the expanded base increases in width from the first width to the second width in a linear manner.

US Pat. No. 9,559,029

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERCONNECT STRUCTURE FOR ENCAPSULATED DIE HAVING PRE-APPLIED PROTECTIVE LAYER

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a first insulating layer contacting the semiconductor die;
depositing an encapsulant around the semiconductor die, a surface of the encapsulant being coplanar with a surface of the
first insulating layer;

forming a second insulating layer over the first insulating layer; and
forming an interconnect structure over the semiconductor die by using a laser to form an opening through the first insulating
layer and second insulating layer to electrically connect the interconnect structure to the semiconductor die.

US Pat. No. 10,043,733

INTEGRATED CIRCUIT PACKAGING SYSTEM AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. An integrated circuit packaging system comprising:a carrier;
a device mounted over the carrier, the device having an active side and an inactive side, wherein the active side includes an indent about a peripheral region of the active side, wherein the active side includes a flange about a perimeter of an elevated portion, the elevated portion about a central region of the active side, and wherein the device includes at least one of an integrated circuit, an interposer, and a laminated substrate;
a conformal interconnect, having an elevated segment, a sloped segment, and a flange segment, over the indent, wherein the sloped segment is between the flange segment and the elevated segment, and wherein the flange segment is connected to a first side of the carrier via internal interconnects, the internal interconnects including at least one solder bump or solder ball; and
an encapsulation over the device and the first side of the carrier exposing a second side of the carrier.

US Pat. No. 9,786,623

SEMICONDUCTOR DEVICE AND METHOD OF FORMING POP SEMICONDUCTOR DEVICE WITH RDL OVER TOP PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
forming a first semiconductor package by,
providing an interposer,
disposing a first semiconductor die over the interposer;
depositing a first encapsulant over the first semiconductor die and interposer,
depositing a second encapsulant over the first semiconductor die and contacting a surface of the interposer and a surface
of the first encapsulant, wherein the second encapsulant covers an entirety of the surface of the first encapsulant and an
entirety of the surface of the interposer, and

forming a first interconnect structure over the interposer opposite the first semiconductor die;
forming a second semiconductor package by,
providing a second semiconductor die,
disposing a modular interconnect unit completely outside a footprint of the second semiconductor die,
depositing a third encapsulant over the second semiconductor die and modular interconnect unit, and
forming a build-up interconnect structure over the second semiconductor die, modular interconnect unit, and third encapsulant;
and

disposing the first semiconductor package over the second semiconductor package opposite the build-up interconnect structure,
wherein the first interconnect structure of the first semiconductor package extends to the modular interconnect unit of the
second semiconductor package.

US Pat. No. 9,693,455

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH PLATED COPPER POSTS AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

11. An integrated circuit packaging system comprising:
a copper film includes a horizontal planar top surface;
a first metal layer directly on the copper film;
an insulation layer directly on and over the first metal layer, the insulation layer having an insulation bottom surface and
a via hole, the insulation bottom surface coplanar with a metal layer bottom surface of the first metal layer, the metal layer
bottom surface on the horizontal planar top surface, the via hole through the insulation layer;

a conductive via within the via hole and directly on the first metal layer;
a second metal layer directly on the conductive via and the insulation layer;
copper posts having a pitch of between 15-20 microns (?m) directly on the side of the copper film opposite the first metal
layer and the second metal layer;

solder pads over the copper posts; and
an interposer coupled to the copper posts and the solder pads.

US Pat. No. 9,653,445

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING 3D PACKAGE WITH SHORT CYCLE TIME AND HIGH YIELD

STATS ChipPAC Pte. Ltd., ...

15. A method of making a semiconductor device, comprising:
forming a first redistribution interconnect structure using a first manufacturing line;
forming a second redistribution interconnect structure using a second manufacturing line;
testing a second unit of the first redistribution interconnect structure to determine a rejected unit; and
disposing a dummy die over the rejected unit of the first redistribution interconnect structure.

US Pat. No. 9,583,446

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A SHIELDING LAYER BETWEEN STACKED SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming a shielding layer over the first semiconductor die;
providing a bond wire electrically connected between the shielding layer and a ground point; and
disposing a second semiconductor die over the shielding layer with the bond wire disposed between the first semiconductor
die and second semiconductor die.

US Pat. No. 9,524,958

SEMICONDUCTOR DEVICE AND METHOD OF INDIVIDUAL DIE BONDING FOLLOWED BY SIMULTANEOUS MULTIPLE DIE THERMAL COMPRESSION BONDING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a carrier;
applying a non-conductive interface layer to the carrier;
providing a plurality of semiconductor dice including bumps;
temporarily mounting the plurality of semiconductor dice to the carrier and non-conductive interface layer by,
(a) pressing the bumps of a first semiconductor die of the plurality of semiconductor dice at least partially into the non-conductive
interface layer while holding at a first pressure and first temperature for a first time period one second or less,

(b) pressing the bumps of a second semiconductor die of the plurality of semiconductor dice at least partially into the non-conductive
interface layer while holding at the first pressure and the first temperature for the first time period, and

(c) after steps (a) and (b), simultaneously thermal compression bonding the first semiconductor die and the second semiconductor
die of the plurality of semiconductor dice to the non-conductive interface layer while holding at a second pressure and second
temperature greater than the first pressure and first temperature for a second time period greater than the first time period;

depositing an encapsulant over the plurality of semiconductor dice and the non-conductive interface layer;
removing the non-conductive interface layer and carrier; and
forming an interconnect structure over the plurality of semiconductor dice and encapsulant.

US Pat. No. 9,875,911

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER WITH OPENING TO CONTAIN SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first interposer including an opening and a vertical conduction path through the first interposer;
disposing a first semiconductor die over a first surface of the first interposer, an active surface of the first semiconductor
die oriented toward the first interposer;

disposing a second semiconductor die within the opening of the first interposer, a non-active surface of the second semiconductor
die oriented toward the first semiconductor die;

depositing an encapsulant over the first semiconductor die and around the second semiconductor die within the opening of the
first interposer; and

forming an interconnect structure over the first interposer, the encapsulant, and the second semiconductor die by,
(a) forming an insulating layer on a surface of the encapsulant, on an active surface of the second semiconductor die opposite
the non-active surface, and on a second surface of the first interposer opposite the first surface, and

(b) forming a conductive layer on the active surface of the second semiconductor die and on the second surface of the first
interposer.

US Pat. No. 9,847,309

SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT STRUCTURE BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a substrate;
forming a vertical interconnect structure including a linear sidewall extending from the semiconductor die to the substrate;
and

mounting the semiconductor die to the substrate including a fixed offset between the semiconductor die and substrate, wherein
a first width of the vertical interconnect structure in a cross-section taken perpendicular to the linear sidewall is greater
than a second width of the vertical interconnect structure in the cross-section of the first width of the vertical interconnect
structure prior to mounting the semiconductor die to the substrate.

US Pat. No. 9,847,324

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
forming a first insulating layer around the first semiconductor die;
forming a second insulating layer over the first semiconductor die and first insulating layer;
forming a second opening through the second insulating layer and extending into the first insulating layer;
forming a conductive layer over the second insulating layer and extending into the second opening and to a contact pad of
the first semiconductor die;

forming a first opening in the first insulating layer after forming the first insulating layer, wherein the first opening
extends to the conductive layer; and

forming a first interconnect structure in the first opening.

US Pat. No. 9,780,057

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PAD LAYOUT FOR FLIPCHIP SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a substrate;
forming a plurality of conductive traces including a plurality of interconnect sites over the substrate arranged in a layout
comprising signal sites located primarily in a perimeter region of the substrate;

forming a plurality of physically separate solder mask patches disposed interstitially between and physically isolated from
the interconnect sites; and

disposing an interconnect structure between the semiconductor die and substrate, wherein a width of the interconnect structure
is greater than a width of the interconnect sites and the interconnect structure covers a side surface of the conductive traces.

US Pat. No. 9,773,685

SOLDER JOINT FLIP CHIP INTERCONNECTION HAVING RELIEF STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate including an interconnect site;
a semiconductor die including an interconnect pad, the semiconductor die disposed over the substrate; and
a bump material disposed between the interconnect pad and interconnect site in contact with the interconnect site at a contact
surface, wherein a width of the contact surface of the interconnect site in a direction across the interconnect site is less
than a length of the contact surface of the interconnect site in a direction along the interconnect site.

US Pat. No. 9,721,921

SEMICONDUCTOR DEVICE AND METHOD OF BONDING SEMICONDUCTOR DIE TO SUBSTRATE IN RECONSTITUTED WAFER FORM

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a reconstituted panel including a plurality of semiconductor die;
disposing the reconstituted panel over a substrate;
bonding the semiconductor die to the substrate;
depositing an encapsulant around the semiconductor die after bonding the semiconductor die to the substrate; and
singulating the substrate after bonding the semiconductor die to the substrate.

US Pat. No. 9,601,462

SEMICONDUCTOR DEVICE AND METHOD OF FORMING UBM STRUCTURE ON BACK SURFACE OF TSV SEMICONDUCTOR WAFER

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die;
a conductive via formed through the semiconductor die;
a first insulating layer formed around the conductive via and extending beyond a first surface of the semiconductor die;
a second insulating layer formed in direct contact with the first surface of the semiconductor die and extending over a portion
of the first insulating layer which extends beyond the first surface of the semiconductor die to contact the conductive via,
wherein a first end of the conductive via extends beyond the first insulating layer and second insulating layer, and the second
insulating layer includes a first thickness over the portion of the first insulating layer and a second thickness greater
than the first thickness over the first surface of the semiconductor die; and

a first bump formed in contact with the first end of the conductive via and a side surface of the conductive via.

US Pat. No. 9,559,004

SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING THIN SEMICONDUCTOR WAFER ON CARRIER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a carrier including an adhesive disposed over the carrier;
providing a semiconductor wafer including a plurality of semiconductor die separated by a non-active region;
forming a plurality of bumps over the semiconductor die;
disposing the semiconductor wafer over the carrier to embed the bumps in the adhesive with the adhesive extending to the semiconductor
wafer;

applying irradiated energy to the non-active region to form a modified region within the non-active region;
singulating the semiconductor wafer along the modified region by,
disposing a heating element over a first surface of the semiconductor wafer, and
disposing a cooling element over a second surface of the semiconductor wafer opposite the first surface;
removing the bumps from the adhesive after singulating the semiconductor wafer; and
depositing an encapsulant over the plurality of semiconductor die after removing the bumps from the adhesive.

US Pat. No. 9,978,654

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUAL-SIDED INTERCONNECT STRUCTURES IN FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a substrate including a first conductive layer formed over a first surface of the substrate;
forming a plurality of wire studs over the first surface of the substrate;
disposing a semiconductor die over the first surface of the substrate between the wire studs including a first interconnect structure formed on an active surface of the semiconductor die opposite the substrate;
depositing a first encapsulant around the substrate, wire studs, semiconductor die, and first interconnect structure, wherein a portion of the first interconnect structure and first ends of the wire studs are exposed from the encapsulant; and
forming a second interconnect structure over a surface of the first encapsulant opposite the substrate and contacting the first interconnect structure and wire studs.

US Pat. No. 9,966,335

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME ELECTRICALLY CONNECTED TO EMBEDDED SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:an interposer frame including a die opening formed completely through the interposer frame;
a first semiconductor die disposed within the die opening of the interposer frame with a first surface of the first semiconductor die coplanar with a first surface of the interposer frame and a conductive bump formed on a second surface of the first semiconductor die; and
a first interconnect structure formed between the first semiconductor die and interposer frame.

US Pat. No. 9,899,286

SEMICONDUCTOR DEVICE AND METHOD OF SELF-CONFINEMENT OF CONDUCTIVE BUMP MATERIAL DURING REFLOW WITHOUT SOLDER MASK

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a first interconnect site and a second interconnect site;
depositing a conductive material self-confined with respect to and contacting a top surface and side surfaces of the first
interconnect site and second interconnect site immediately adjacent to a surface of the substrate by surface tension of a
wettable state of the conductive material absent mask material between the first interconnect site and second interconnect
site; and

forming an insulating layer around the first interconnect site and second interconnect site.

US Pat. No. 9,768,066

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS BY DIRECT VIA REVEAL WITH ORGANIC PASSIVATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of semiconductor die;
forming a plurality of conductive vias extending into a first surface of the semiconductor wafer and only partially through
the semiconductor wafer including a conductive via in each of the plurality of semiconductor die;

planarizing the semiconductor wafer to leave a second surface of the semiconductor wafer coplanar with surfaces of the plurality
of conductive vias;

forming a first insulating layer on the second surface of the semiconductor wafer to cover the surfaces of the plurality of
conductive vias;

forming a second insulating layer over the first insulating layer;
forming a plurality of openings in the second insulating layer over the plurality of conductive vias;
etching the first insulating layer using the second insulating layer as a mask to extend the plurality of openings through
the first insulating layer and expose the plurality of conductive vias, wherein each of the plurality of openings through
the first insulating layer and second insulating layer includes a footprint smaller than a footprint of an underlying conductive
via;

forming an under-bump metallization (UBM) layer over the second insulating layer outside the plurality of openings and contacting
the plurality of conductive vias through the plurality of openings; and

forming a plurality of conductive bumps over the UBM layer, wherein each of the conductive bumps extends into one of the plurality
of openings.

US Pat. No. 9,754,867

SEMICONDUCTOR DEVICE AND METHOD OF FORMING REPASSIVATION LAYER FOR ROBUST LOW COST FAN-OUT SEMICONDUCTOR PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant around the semiconductor die;
forming a plurality of compliant islands over the semiconductor die;
forming a compliant layer over an interface between the semiconductor die and encapsulant; and
forming a plurality of interconnect structures over the semiconductor die with each of the interconnect structures aligned
with one of the compliant islands or over the compliant layer.

US Pat. No. 9,685,402

SEMICONDUCTOR DEVICE AND METHOD OF FORMING RECESSES IN CONDUCTIVE LAYER TO DETECT CONTINUITY FOR INTERCONNECT BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE

STATS ChipPAC Pte. Ltd., ...

20. A method of making a semiconductor device, comprising:
providing a semiconductor die including a plurality of interconnect structures formed on a surface of the semiconductor die;
providing a substrate;
forming a plurality of conductive traces over the substrate, wherein the conductive traces each include an open channel formed
within an interior region of the conductive traces, wherein the open channel extends along a length of the conductive traces
under the interconnect structures and in opposing directions beyond a footprint of the first interconnect structures to terminate
within the interior region of the conductive traces;

disposing the semiconductor die over the substrate with the interconnect structures aligned to the conductive traces over
the open channel;

mounting the semiconductor die over the substrate to make a connection between the interconnect structures and the conductive
traces over the open channel; and

detecting a state of connection between the interconnect structures and the conductive traces by whether a portion of the
interconnect structures is found in the open channel which extend beyond the footprint of the interconnect structures.

US Pat. No. 9,607,965

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING WARPAGE IN RECONSTITUTED WAFER

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
providing a substrate including a planar die placement area;
disposing the semiconductor die over the planar die placement area of the substrate while leaving a portion of the planar
die placement area in a central area of the substrate that could accommodate additional semiconductor die absent the semiconductor
die; and

depositing an encapsulant over the semiconductor die and substrate and further in contact with the portion of the planar die
placement area of the substrate that could accommodate additional semiconductor die.

US Pat. No. 9,524,955

SEMICONDUCTOR DEVICE AND METHOD OF FORMING NO-FLOW UNDERFILL MATERIAL AROUND VERTICAL INTERCONNECT STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first conductive layer;
a vertical interconnect structure disposed over the first conductive layer;
a no-flow insulating material disposed around the vertical interconnect structure and the first conductive layer;
a first semiconductor die embedded within the no-flow insulating material over the first conductive layer, wherein the no-flow
insulating material, first semiconductor die, and vertical interconnect structure includes a planar surface and the first
conductive layer is partially embedded in the no-flow insulating material to cover a side surface of the first conductive
layer;

a first interconnect structure formed over the planar surface, the first interconnect structure including a second conductive
layer formed in direct contact with the vertical interconnect structure and a surface of the no-flow insulating material and
extending over the surface of the no-flow insulating material outside a contact interface between the first interconnect structure
and the vertical interconnect structure;

a second semiconductor die disposed over the first interconnect structure and directly overlying the first semiconductor die,
wherein the second semiconductor die is a duplicate of the first semiconductor die; and

a second interconnect structure formed over and contacting the first conductive layer opposite the first interconnect structure.

US Pat. No. 9,515,016

SEMICONDUCTOR PACKAGE AND METHOD OF FORMING Z-DIRECTION CONDUCTIVE POSTS EMBEDDED IN STRUCTURALLY PROTECTIVE ENCAPSULANT

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a base plate including a plurality of conductive posts physically connected to and extending from the base plate;
an encapsulant disposed over the base plate and around the conductive posts including a height of the encapsulant equal to
a height of the conductive posts; and

a semiconductor die embedded within the encapsulant between the conductive posts including a height of the semiconductor die
less than the height of the conductive posts.

US Pat. No. 9,859,200

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER SUPPORT STRUCTURE MECHANISM AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
mounting an integrated circuit device over a base substrate;
forming a bottom conductive joint over a base terminal of the base substrate the bottom conductive joint having pre-mounted
solder with fluxing in direct contact with the base terminal;

mounting a conductive ball over the bottom conductive joint that has been pre-mounted over the base terminal, the conductive
ball having a core body and a coating on the core body, the coating having a thickness of less than approximately 4 micrometers
(?m), the conductive ball having a pitch in an approximate range of 0.2 millimeters (mm) to 0.3 mm, and the core body having
a diameter in an approximate range of 150 ?m to 200 ?m;

forming an interposer with a top conductive joint; and
mounting the interposer with the top conductive joint over the conductive ball;
and
wherein the top conductive joint, the bottom conductive joint, and the coating are distinct from each other, the top conductive
joint is in direct contact with the conductive ball, and the conductive ball is in direct contact with the bottom conductive
joint.

US Pat. No. 9,842,798

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A POP DEVICE WITH EMBEDDED VERTICAL INTERCONNECT UNITS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a conductive via formed through the substrate;
disposing a modular interconnect unit including a vertical interconnect structure over the substrate;
disposing a first semiconductor die over the substrate;
depositing an encapsulant over the first semiconductor die and vertical interconnect structure;
planarizing the encapsulant to form a surface of the encapsulant coplanar with a back surface opposite an active surface of
the first semiconductor die while leaving a portion of the encapsulant over the modular interconnect unit;

removing a portion of the encapsulant over the vertical interconnect structure to form an opening in the encapsulant after
planarizing the encapsulant; and

disposing a second semiconductor die over the first semiconductor die including disposing a bump of the second semiconductor
die within the opening of the encapsulant and electrically connected to the vertical interconnect structure.

US Pat. No. 9,748,157

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH JOINT ASSEMBLY AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
providing a base substrate having a bottom pad;
mounting an integrated circuit device on the base substrate;
providing an interposer having a package interconnect mounted thereon;
clamping the interposer to the base substrate, the package interconnect coined onto the bottom pad, the package interconnect
coined to a fixed height allowing a set amount of clearance between the interposer and a device top side of the integrated
circuit device, the interposer over the integrated circuit device with the package interconnect outside a perimeter of the
integrated circuit device, and the package interconnect includes an irregular surface characteristic of a mechanical pressing
method; and

forming an encapsulation between the interposer and the base substrate.

US Pat. No. 9,666,540

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PREFABRICATED HEAT SPREADER FRAME WITH EMBEDDED SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a heat spreader frame including a body extending perpendicularly from a flat plate;
disposing a semiconductor die over the flat plate of the heat spreader frame;
depositing an encapsulant over the flat plate including a surface of the encapsulant that is coplanar with a surface of the
semiconductor die and a surface of the body; and

forming a first conductive layer over the surface of the semiconductor die and contacting the surface of the encapsulant.

US Pat. No. 9,627,338

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ULTRA HIGH DENSITY EMBEDDED SEMICONDUCTOR DIE PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a reinforced insulating film;
disposing a conductive layer on a first surface of the reinforced insulating film;
disposing a semiconductor die in contact with a second surface of the reinforced insulating film;
disposing a prefabricated laminating layer over the semiconductor die, wherein the prefabricated laminating layer extends
completely over the semiconductor die; and

laminating the prefabricated laminating layer over the reinforced insulating film by applying pressure to the prefabricated
laminating layer against the semiconductor die to embed the semiconductor die in the prefabricated laminating layer and expose
an active surface of the semiconductor die from the prefabricated laminating layer opposite the reinforced insulating film,
wherein a thickness of the prefabricated laminating layer is approximately equal to a thickness of the semiconductor die across
an entire width of the semiconductor device after laminating.

US Pat. No. 9,607,958

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING OPENINGS AND TRENCHES IN INSULATING LAYER BY FIRST LDA AND SECOND LDA FOR RDL FORMATION

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die;
an encapsulant deposited over the semiconductor die and contacting a side surface of the semiconductor die, wherein a top
surface of the semiconductor die is approximately coplanar with a top surface of the encapsulant;

a first insulating layer formed on the top surface of the semiconductor die and the top surface of the encapsulant, the first
insulating layer including a first opening extending into the encapsulant through the top surface of the encapsulant outside
a footprint of the semiconductor die, a second opening over the semiconductor die, and a trench extending completely between
the first opening and second opening;

a conductive layer disposed within the trench, first opening, and second opening, wherein the conductive layer contacts the
encapsulant below the top surface of the encapsulant within the first opening;

a second insulating layer formed over the conductive layer; and
a third opening formed completely through the encapsulant over the first opening to expose a portion of the conductive layer
in the first opening.

US Pat. No. 9,997,468

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SHIELDING AND METHOD OF MANUFACTURING THEREOF

STATS ChipPAC Pte. Ltd., ...

6. A method of manufacture of an integrated circuit packaging system comprising:providing a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides;
forming a solder resist layer across the substrate bottom side, the solder resist layer having a solder resist trench extending continuously around an outer perimeter of the solder resist layer with the solder resist trench exposing a portion of the substrate bottom side;
coupling an integrated circuit to the internal circuitry includes coupling chip interconnects between the integrated circuit and the internal circuitry;
forming a molded package body directly on the integrated circuit and the substrate top side of the substrate; and
applying a conductive conformal shield structure directly on the molded package body, a portion of the substrate bottom side, and the vertical sides of the substrate, and adjacent to the solder resist trench with the conductive conformal shield structure electrically coupled to the internal circuitry through the vertical sides, the substrate bottom side, or a combination thereof.

US Pat. No. 9,922,955

SEMICONDUCTOR DEVICE AND METHOD OF FORMING PACKAGE-ON-PACKAGE STRUCTURE ELECTRICALLY INTERCONNECTED THROUGH TSV IN WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of semiconductor die;
forming a first conductive layer over an active surface of the semiconductor die including active devices;
forming a second conductive layer over a second surface of the semiconductor die opposite the active surface of the semiconductor
die such that each semiconductor die constitutes a wafer level chip scale package (WLCSP);

forming a conductive through silicon via (TSV) through the active surface of the WLCSP;
mounting a first semiconductor component to the WLCSP;
electrically connecting the first semiconductor component to the first conductive layer;
forming a first bump over the first conductive layer;
mounting a second semiconductor component to the first bump and electrically connecting the second semiconductor component
to the first semiconductor component and WLCSP through the first bump and TSV; and

singulating the semiconductor wafer after mounting the second semiconductor component.

US Pat. No. 9,748,203

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CONDUCTIVE PILLARS AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. An integrated circuit packaging system comprising:
a package carrier;
a first integrated circuit mounted to the package carrier;
an underfill between the package carrier and the first integrated circuit;
a circuit interposer mounted above the first integrated circuit and connected to the package carrier, wherein the circuit
interposer is an integrated passive device or an active device;

a second integrated circuit mounted above the circuit interposer;
a conductive pillar formed to the circuit interposer adjacent to the second integrated circuit; and
an encapsulation formed on the package carrier and the second integrated circuit, a non-active side of the second integrated
circuit exposed from and coplanar with a horizontal surface of the encapsulation; and

wherein a top surface of the conductive pillar is below a top surface of the second integrated circuit, and the top surface
of the conductive pillar and the top surface of the second integrated circuit are exposed from the encapsulation.

US Pat. No. 9,685,415

SEMICONDUCTOR DEVICE AND METHOD OF FORMING MICRO-VIAS PARTIALLY THROUGH INSULATING MATERIAL AROUND BUMP INTERCONNECT

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
a conductive layer formed over the substrate;
a first insulating layer formed over the conductive layer and including an opening over the conductive layer formed through
the first insulating layer and further including a plurality of first micro-openings formed from a top surface of the first
insulating layer partially through the first insulating layer with a depth of each first micro-opening of the plurality of
first micro-openings from the top surface of the first insulating layer extending toward the conductive layer around the opening
over the conductive layer and completely within a vertical projection of the conductive layer; and

an interconnect structure formed over the conductive layer with the plurality of first micro-openings disposed around the
interconnect structure.

US Pat. No. 9,627,229

SEMICONDUCTOR DEVICE AND METHOD OF FORMING TRENCH AND DISPOSING SEMICONDUCTOR DIE OVER SUBSTRATE TO CONTROL OUTWARD FLOW OF UNDERFILL MATERIAL

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including an opening devoid of material and extending from a first surface of the substrate to a second
surface of the substrate;

forming a first insulating layer over the first surface of the substrate;
removing a portion of the first insulating layer to form a trench over the first surface of the substrate and around the opening;
forming an interconnect structure in the trench;
disposing an underfill material in the trench around the opening and interconnect structure; and
disposing a first semiconductor die over the substrate and interconnect structure after depositing the underfill material
in the trench, wherein a sensor of the first semiconductor die is disposed over the opening in the substrate and the trench
contains the underfill material to prevent the underfill material from reaching the opening.

US Pat. No. 10,181,423

SEMICONDUCTOR DEVICE AND METHOD OF USING A STANDARDIZED CARRIER IN SEMICONDUCTOR PACKAGING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first semiconductor wafer including a plurality of first semiconductor die;
singulating the first semiconductor wafer to separate the first semiconductor die;
providing a first carrier, wherein a size of the first carrier is independent of a size of the first semiconductor die and a size of the first semiconductor wafer;
disposing the first semiconductor die over the first carrier, wherein the first semiconductor die are spaced 300 micrometers (?m) apart from each other or less;
processing the first semiconductor die on the first carrier using a piece of equipment;
providing a second semiconductor wafer including a plurality of second semiconductor die, wherein a size of the second semiconductor die is different from the size of the first semiconductor die;
singulating the second semiconductor wafer to separate the second semiconductor die;
providing a second carrier, wherein a size of the second carrier is substantially equal to the size of the first carrier;
disposing the second semiconductor die over the second carrier, wherein the second semiconductor die are spaced 300 ?m apart from each other or less; and
processing the second semiconductor die on the second carrier using the piece of equipment.

US Pat. No. 10,068,843

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CAVITY IN BUILD-UP INTERCONNECT STRUCTURE FOR SHORT SIGNAL PATH BETWEEN DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a semiconductor die including an active surface and a contact pad formed on the active surface;
an encapsulant deposited over the semiconductor die, wherein a surface of the encapsulant is coplanar with the active surface of the semiconductor die;
a masking layer formed in contact with a first portion of the active surface of the semiconductor die while leaving a second portion of the active surface including the contact pad devoid of the masking layer; and
a build-up interconnect structure formed in contact with the second portion of the active surface, wherein the build-up interconnect structure includes a conductive layer and an insulating layer formed over the conductive layer and terminates in a lateral direction across the semiconductor die at an edge of the masking layer with no portion of the build-up interconnect structure over the first portion of the active surface of the semiconductor die, and the insulating layer contacts the encapsulant.

US Pat. No. 9,978,665

SEMICONDUCTOR DEVICE AND METHOD OF FORMING LOW PROFILE FAN-OUT PACKAGE WITH VERTICAL INTERCONNECTION UNITS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first semiconductor die;
disposing the first semiconductor die on a carrier with an active surface of the first semiconductor die oriented toward the carrier;
disposing a modular interconnect unit on the carrier adjacent to the first semiconductor die;
removing the carrier to expose a surface of the modular interconnect unit and the active surface of the first semiconductor die;
forming a build-up interconnect structure over the active surface of the first semiconductor die and the surface of the modular interconnect unit; and
disposing a second semiconductor die over the modular interconnect unit and first semiconductor die opposite the build-up interconnect structure, wherein the second semiconductor die is coupled to the build-up interconnect structure through the modular interconnect unit.

US Pat. No. 9,865,482

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-OUT STRUCTURE WITH INTEGRATED PASSIVE DEVICE AND DISCRETE COMPONENT

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
a conductive via formed through the substrate;
an integrated passive device (IPD) structure including a first IPD formed directly over the conductive via and the substrate
and electrically connected to the conductive via, the conductive via disposed within a footprint of the first IPD;

an encapsulant deposited over a side surface of the substrate and the IPD structure;
a first interconnect structure formed over the IPD structure and the encapsulant and electrically connected to the IPD structure;
and

a discrete semiconductor component disposed within the encapsulant outside a footprint of the substrate, wherein the discrete
semiconductor component includes a capacitor comprising a capacitance value over 100 picofarads (pF).

US Pat. No. 9,865,575

METHODS OF FORMING CONDUCTIVE AND INSULATING LAYERS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
disposing a semiconductor die over the substrate;
depositing an encapsulant around the semiconductor die;
forming an insulating material over a portion of the encapsulant and a portion of the semiconductor die using an inkjet printing
process; and

forming a first conductive layer over the insulating material, wherein a portion of the first conductive layer over the semiconductor
die is contained completely within a footprint of the insulating material.

US Pat. No. 9,780,063

SEMICONDUCTOR DEVICE AND METHOD OF FORMING BUMP STRUCTURE WITH INSULATING BUFFER LAYER TO REDUCE STRESS ON SEMICONDUCTOR WAFER

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a contact pad;
forming a buffer layer over the semiconductor wafer by,
depositing an insulating layer over the semiconductor wafer,
removing a first portion of the insulating layer to form an opening over the contact pad, and
removing a second portion of the insulating layer completely surrounding the contact pad;
forming a ring-shaped conductive pillar over the buffer layer; and
forming a bump within the ring-shaped conductive pillar and extending into the opening of the insulating layer by,
forming a photoresist layer over the ring-shaped conductive pillar,
removing a portion of the photoresist layer within the ring-shaped conductive pillar, and
depositing a bump material within the ring-shaped conductive pillar.

US Pat. No. 9,735,113

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ULTRA THIN MULTI-DIE FACE-TO-FACE WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a temporary carrier;
providing a plurality of first semiconductor die each including an active surface and back surface opposite the active surface;
mounting the back surfaces of the plurality of first semiconductor die to the temporary carrier;
mounting a plurality of second semiconductor die over the plurality of first semiconductor die with an active surface of each
of the plurality of second semiconductor die oriented toward the respective active surfaces of the plurality of first semiconductor
die;

forming a plurality of bumps over the active surfaces of the plurality of first semiconductor die around a respective perimeter
of each of the plurality of second semiconductor die;

depositing an encapsulant over the plurality of first semiconductor die, the plurality of second semiconductor die, and the
temporary carrier;

forming a plurality of conductive vias partially through the encapsulant around the plurality of first semiconductor die and
the plurality of second semiconductor die;

removing a first portion of the encapsulant and the plurality of first semiconductor die to expose the conductive vias;
forming a first interconnect structure over the encapsulant and the back surfaces of the plurality of first semiconductor
die, the interconnect structure being electrically connected to the conductive vias; and

removing the temporary carrier.

US Pat. No. 9,659,897

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH INTERPOSER STRUCTURE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. An integrated circuit packaging system comprising:
a first trace layer having a pillar extending perpendicularly away from a first trace layer;
a via directly on the first trace layer, the via extending away from the first trace layer on a side opposite from the pillar;
a conductive buildup having the first trace layer and a second trace layer electrically connected by the via; and
a molded body partially encapsulating the first trace layer and the via of the conductive buildup, the first trace layer coplanar
with a body first side of the molded body, the pillar extending out of the body first side of the molded body, and the second
trace layer over and coplanar with a body second side of the molded body.

US Pat. No. 9,559,039

SEMICONDUCTOR DEVICE AND METHOD OF USING SUBSTRATE HAVING BASE AND CONDUCTIVE POSTS TO FORM VERTICAL INTERCONNECT STRUCTURE IN EMBEDDED DIE PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a base and a plurality of conductive posts extending from the base;
disposing a semiconductor die through an opening in the base between the conductive posts;
depositing an encapsulant over the semiconductor die and around the conductive posts; and
removing the base to electrically isolate the conductive posts.

US Pat. No. 9,520,365

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die including a plurality of contact pads;
a first insulating layer formed in contact with an active surface of the semiconductor die;
an encapsulant deposited over a second surface of the semiconductor die opposite the active surface and in a peripheral region
around the semiconductor die; and

an interconnect structure formed over the encapsulant and first insulating layer, wherein the interconnect structure includes,
(a) a second insulating layer formed in direct contact with the encapsulant and first insulating layer, wherein a coefficient
of thermal expansion (CTE) of the second insulating layer is within a first range of 30-90 parts per million (ppm),

(b) a first conductive layer formed over the second insulating layer and the plurality of contact pads,
(c) a third insulating layer formed in direct contact with the second insulating layer and first conductive layer, wherein
a CTE of the third insulating layer is within a second range of 90-110 ppm,

(d) a second conductive layer formed over the second insulating layer and first conductive layer, and
(e) a fourth insulating layer formed in direct contact with the third insulating layer and second conductive layer, wherein
a CTE of the fourth insulating layer is within a third range of 110-150 ppm.

US Pat. No. 9,406,579

SEMICONDUCTOR DEVICE AND METHOD OF CONTROLLING WARPAGE IN SEMICONDUCTOR PACKAGE

STATS ChipPAC Pte. Ltd., ...

10. A semiconductor device, comprising:
a substrate including first and second opposing surfaces;
a conductive via formed through the substrate extending from the first surface of the substrate to the second surface of the
substrate;

an insulating layer formed over the first surface of the substrate;
a conductive layer formed entirely above the first surface of the substrate in the insulating layer and over the conductive
via;

a semiconductor die disposed over the first surface of the substrate and contacting the conductive layer;
a channel formed in the insulating layer outside a footprint of the semiconductor die extending to the first surface of the
substrate surrounding the semiconductor die;

an underfill material deposited between the semiconductor die and the substrate and in the channel wherein a portion of the
insulating layer between the footprint of the semiconductor die and the channel is devoid of the underfill material; and

a heat spreader disposed over the semiconductor die with the heat spreader thermally connected to the substrate.

US Pat. No. 9,978,700

METHOD FOR BUILDING UP A FAN-OUT RDL STRUCTURE WITH FINE PITCH LINE-WIDTH AND LINE-SPACING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a plurality of semiconductor die as a semiconductor wafer;
forming a third insulating layer over an active surface of the semiconductor wafer;
forming a third opening in the third insulating layer, wherein the third opening is elongated in a first direction parallel to the active surface of the semiconductor wafer such that a length of the third opening is greater than a width of the third opening and the length and width of the third opening are both parallel to the active surface of the semiconductor wafer;
forming a fourth insulating layer over the semiconductor wafer and third insulating layer;
forming a fourth opening in the fourth insulating layer aligned with the third opening in the third insulating layer, wherein the fourth opening is elongated in a second direction substantially perpendicular to the first direction and parallel to both the width of the third opening and the active surface such that the fourth opening extends outside a footprint of the third opening and the third opening extends outside a footprint of the fourth opening;
singulating the plurality of semiconductor die from the semiconductor wafer after forming the third insulating layer, third opening, fourth insulating layer, and fourth opening;
disposing the plurality of semiconductor die on a carrier with the third insulating layer and fourth insulating layer oriented toward the carrier;
depositing an encapsulant over the carrier and plurality of semiconductor die to cover a back surface of the plurality of semiconductor die opposite the active surface, wherein a first surface of the encapsulant is coplanar with a surface of the fourth insulating layer opposite the semiconductor die;
forming a backside insulating layer over a second surface of the encapsulant opposite the first surface of the encapsulant while the semiconductor die and encapsulant remain on the carrier, wherein the backside insulating layer includes a higher resistance to wear than the encapsulant and a portion of the encapsulant extends between the backside insulating layer and the back surface of the plurality of semiconductor die;
removing the carrier after forming the backside insulating layer;
forming a first insulating layer over the first surface of the encapsulant and the active surface of the plurality of semiconductor die after forming the backside insulating layer, wherein the first insulating layer extends into the third opening of the third insulating layer and the fourth opening of the fourth insulating layer;
forming a first opening in the first insulating layer aligned with the third opening of the third insulating layer and the fourth opening of the fourth insulating layer, wherein a footprint of the first opening is completely within the footprint of the third opening and the footprint of the fourth opening;
forming a conductive layer over the first insulating layer and extending into the first opening in the first insulating layer to contact the semiconductor die, wherein the first insulating layer creates a physical separation between the conductive layer and the third insulating layer; and
singulating through the encapsulant and backside insulating layer, thereby separating each of the plurality of semiconductor die into individual packages.

US Pat. No. 9,881,894

THIN 3D FAN-OUT EMBEDDED WAFER LEVEL PACKAGE (EWLB) FOR APPLICATION PROCESSOR AND MEMORY INTEGRATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor die;
mounting the first semiconductor die on a carrier with an active surface of the first semiconductor die oriented toward the
carrier;

depositing an encapsulant around the first semiconductor die while the first semiconductor die is on the carrier, wherein
a surface of the encapsulant is coplanar with the active surface of the first semiconductor die;

removing the carrier to expose the active surface of the first semiconductor die after depositing the encapsulant;
forming an insulating layer on the encapsulant and active surface of the first semiconductor die after removing the carrier;
forming a conductive via on the active surface of the first semiconductor die and through the insulating layer by depositing
a conductive material into an opening of the insulating layer;

forming a conductive trace on the insulating layer, wherein the conductive trace extends from the first semiconductor die
to outside a footprint of the first semiconductor die; and

disposing a second semiconductor die over the insulating layer opposite the first semiconductor die, wherein the second semiconductor
die includes a first conductive bump on an active surface of the second semiconductor die contacting the conductive via and
the conductive via extends vertically from the first semiconductor die to the first conductive bump.

US Pat. No. 9,875,973

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING SEMICONDUCTOR PACKAGE HAVING BUILD-UP INTERCONNECT STRUCTURE OVER SEMICONDUCTOR DIE WITH DIFFERENT CTE INSULATING LAYERS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die in a reconstituted wafer;
depositing an encapsulant over the plurality of semiconductor die;
forming a first insulating layer over the plurality of semiconductor die and directly on the encapsulant;
curing the first insulating layer with multiple dwell cycles;
forming a first conductive layer over the first insulating layer; and
forming a second insulating layer directly on the first insulating layer and the first conductive layer, wherein a coefficient
of thermal expansion (CTE) of the second insulating layer is different from a CTE of the first insulating layer.

US Pat. No. 9,865,524

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS USING BACKSIDE VIA REVEAL AND SELECTIVE PASSIVATION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a plurality of openings into a first surface of the semiconductor die;
depositing an insulating material over sidewalls of the openings;
depositing a conductive material into the openings of the semiconductor die to form a plurality of conductive vias in the
semiconductor die;

planarizing a second surface of the semiconductor die to remove a portion of the insulating material and expose a top horizontal
surface of the conductive vias;

applying a first insulating layer selectively onto the second surface of the semiconductor die across an entire width of the
semiconductor die except for the top horizontal surfaces of the conductive vias, wherein the second surface of the semiconductor
die remains coplanar with the top horizontal surface of the conductive vias while applying the first insulating layer; and

forming a first solder bump on the top horizontal surface of one of the conductive vias and extending into an opening of the
first insulating layer, wherein forming the first solder bump is after depositing the conductive material to form the plurality
of conductive vias and planarizing the second surface of the semiconductor die.

US Pat. No. 9,837,484

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SUBSTRATE INCLUDING EMBEDDED COMPONENT WITH SYMMETRICAL STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including a first conductive layer;
forming a first insulating layer over the first conductive layer;
forming a fourth conductive layer over the first insulating layer;
forming a third insulating layer over the first insulating layer and fourth conductive layer;
forming a second conductive layer over the first conductive layer and third insulating layer;
forming an opening through the third insulating layer over the fourth conductive layer;
removing the fourth conductive layer;
disposing a semiconductor component in the opening of the third insulating layer such that the second conductive layer lies
in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component;

forming a second insulating layer over the semiconductor component; and
forming a third conductive layer over the second insulating layer.

US Pat. No. 9,691,707

SEMICONDUCTOR DEVICE AND METHOD OF FORMING 3D DUAL SIDE DIE EMBEDDED BUILD-UP SEMICONDUCTOR PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die;
a first bump disposed over a substrate, the first bump including a conductive core and a conductive material disposed around
the conductive core;

a first insulating film disposed between the substrate and a back surface of the semiconductor die;
an opening formed through the conductive material and extending into the conductive core;
a conductive layer formed over the first insulating film and extending into the opening to contact the conductive material
and conductive core; and

a second bump disposed directly on the conductive layer opposite the first bump.

US Pat. No. 9,685,403

SEMICONDUCTOR DEVICE AND METHOD OF FORMING SHIELDING LAYER OVER SEMICONDUCTOR DIE MOUNTED TO TSV INTERPOSER

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first substrate;
forming a plurality of conductive vias into the first substrate;
providing a second substrate;
disposing a semiconductor die over the first substrate and electrically connected to a first conductive via of the plurality
of conductive vias;

depositing an encapsulant over the first substrate and semiconductor die;
forming a trench through the encapsulant to expose a second conductive via of the plurality of conductive vias;
forming a shielding layer over the encapsulant and extending into the trench to contact the second conductive via;
planarizing a surface of the first substrate opposite the semiconductor die with the plurality of conductive vias;
forming a build-up interconnect structure over the surface of the first substrate; and
disposing the first substrate over the second substrate with the semiconductor die and shielding layer electrically coupled
to the second substrate through the plurality of conductive vias and the build-up interconnect structure.

US Pat. No. 9,673,171

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH CORELESS SUBSTRATE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
depositing an insulation layer on a semiconductor die having semiconductor die contacts, the semiconductor die contacts exposed;
applying a conductive layer on the semiconductor die contacts and the insulation layer, the applying including forming a heat
slug directly on an active region of the semiconductor die, spaced away from the semiconductor die contacts; and

coupling system interconnects directly on the conductive layer for electrically connecting the semiconductor die, the system
interconnects, a contact layer, or a combination thereof in a base package having an adhesive layer and the contact layer
each having an exposed surface that is coplanar with a surface of the base package that is opposite to the system interconnects,
the system interconnects coupled on the heat slugs.

US Pat. No. 10,049,964

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a first semiconductor die;
forming a plurality of modular interconnect units by,
(a) providing a core substrate,
(b) forming a plurality of vertical interconnects through the core substrate,
(c) forming a first insulating layer over the core substrate and vertical interconnects, and
(d) forming a plurality of openings in the first insulating layer extending to the vertical interconnects;
after forming the modular interconnect units, disposing the modular interconnect units in a peripheral region around the first semiconductor die, wherein a height of the modular interconnect units is less than a height of the first semiconductor die;
depositing an encapsulant over the first insulating layer and around the first semiconductor die;
forming a plurality of openings into a surface of the encapsulant aligned with the openings in the first insulating layer and extending to the vertical interconnects;
providing a prefabricated interposer including a second insulating layer and a conductive layer embedded within the second insulating layer and extending through the prefabricated interposer;
disposing the prefabricated interposer over the first semiconductor die and modular interconnect units; and
bonding the prefabricated interposer to the modular interconnect units with a plurality of interconnect structures contacting the conductive layer and further extending into the openings of the encapsulant to contact the vertical interconnects.

US Pat. No. 9,934,998

SEMICONDUCTOR DEVICE AND METHOD OF SINGULATING THIN SEMICONDUCTOR WAFER ON CARRIER ALONG MODIFIED REGION WITHIN NON-ACTIVE REGION FORMED BY IRRADIATING ENERGY

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a carrier including an adhesive disposed over the carrier;
providing a semiconductor wafer including a plurality of semiconductor die separated by a non-active region;
forming a plurality of bumps over the semiconductor die;
mounting the semiconductor wafer to the carrier with the adhesive disposed around the plurality of bumps;
applying irradiated energy to the non-active region to form a modified region within the non-active region;
singulating the semiconductor wafer along the modified region to separate the semiconductor die; and
removing the adhesive from around the plurality of bumps after singulating the semiconductor wafer.

US Pat. No. 9,806,040

ANTENNA IN EMBEDDED WAFER-LEVEL BALL-GRID ARRAY PACKAGE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
depositing an encapsulant over the semiconductor die to form a reconstituted wafer;
depositing a first conductive layer including an antenna onto a first surface of the reconstituted wafer after depositing
the encapsulant; and

depositing a second conductive layer including a ground plane onto a second surface of the reconstituted wafer after depositing
the encapsulant, wherein the antenna is located within a footprint of the ground plane.

US Pat. No. 9,768,102

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH SUPPORT STRUCTURE AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
forming a one-layer substrate with a symmetrical structure, the one-layer substrate having an attachment pad, a redistribution
pad, a vertical connector, and an insulation, the redistribution pad having a vertical height greater than a vertical height
of the attachment pad and only at an insulation top side of the insulation, and the vertical connector having a height greater
than a height of the redistribution pad, coplanar with a bottom side of the insulation, directly on the redistribution pad,
within the insulation, and having a bottom width greater than a top width;

mounting an integrated circuit over the one-layer substrate, the integrated circuit having an inactive side attached to the
insulation top side of the insulation; and

forming an encapsulation over the integrated circuit.

US Pat. No. 9,768,155

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A VERTICAL INTERCONNECT STRUCTURE FOR 3-D FO-WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing the semiconductor die over a carrier with an active surface of the semiconductor die oriented toward the carrier;
depositing an encapsulant over the carrier and around the semiconductor die to form a reconstituted panel;
removing the reconstituted panel from the carrier;
forming a first insulating layer over a surface of the encapsulant and the active surface of the semiconductor die;
forming a conductive via through the first insulating layer;
forming an opening through the encapsulant extending to the conductive via after forming the conductive via; and
depositing a conductive material in the opening.

US Pat. No. 9,754,858

SEMICONDUCTOR DEVICE AND METHOD OF FORMING TSV SEMICONDUCTOR WAFER WITH EMBEDDED SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a substrate;
a first cavity formed in a first surface of the substrate;
a first semiconductor die disposed within the first cavity of the substrate;
a first encapsulant deposited within the first cavity;
a first interconnect structure formed over the substrate and first semiconductor die;
a conductive via formed through the substrate and electrically connected to the first interconnect structure;
a second cavity formed in a second surface of the substrate opposite the first surface of the substrate;
a second semiconductor die disposed within the second cavity of the substrate; and
a second encapsulant deposited within the second cavity over the second semiconductor die.

US Pat. No. 9,620,557

SEMICONDUCTOR DEVICE AND METHOD OF FORMING EWLB SEMICONDUCTOR PACKAGE WITH VERTICAL INTERCONNECT STRUCTURE AND CAVITY REGION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate including an optical grade material;
disposing a plurality of spacers over a surface of the substrate;
disposing a first semiconductor die over the spacers with an optically active region of the first semiconductor die oriented
toward the substrate and positioned over an opening between the spacers;

depositing an encapsulant around the first semiconductor die; and
forming an interconnect structure over a surface of the first semiconductor die opposite the optically active region.

US Pat. No. 10,163,744

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A LOW PROFILE DUAL-PURPOSE SHIELD AND HEAT-DISSIPATION STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a substrate including a recess formed partially through the substrate;
a conductive via formed through a surface of the substrate;
a first semiconductor die disposed within the recess over the conductive via;
a planar shaped heat spreader in thermal contact with the first semiconductor die;
a second semiconductor die disposed over the planar shaped heat spreader; and
a first bond wire extending from the second semiconductor die through an opening in the planar shaped heat spreader to the substrate.

US Pat. No. 10,141,222

SEMICONDUCTOR DEVICE AND METHOD OF FORMING CONDUCTIVE VIAS THROUGH INTERCONNECT STRUCTURES AND ENCAPSULANT OF WLCSP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a carrier;
providing a semiconductor die;
disposing a first interconnect structure over an active surface of the semiconductor die;
disposing the semiconductor die over the carrier with the active surface of the semiconductor die oriented toward the carrier;
forming a second interconnect structure over a second surface of the semiconductor die opposite the active surface;
forming a first insulating layer over the second interconnect structure;
forming a protective layer on the first insulating layer;
forming a via in order through the protective layer, second interconnect structure, first interconnect structure, and partially into the carrier;
removing the protective layer after forming the via;
removing the carrier after forming the via;
forming a first conductive layer in the via and extending over the semiconductor die directly on a major surface of the first insulating layer; and
forming an opening in the first insulating layer, wherein the first conductive layer extends into the opening to contact the second interconnect structure.

US Pat. No. 10,115,672

DOUBLE-SIDED SEMICONDUCTOR PACKAGE AND DUAL-MOLD METHOD OF MAKING SAME

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:a first conductive layer;
a semiconductor die disposed over the first conductive layer;
a conductive pillar formed over the first conductive layer;
a first encapsulant deposited over the first conductive layer and semiconductor die;
a second encapsulant deposited around the first encapsulant, first conductive layer, and semiconductor die; and
a second conductive layer formed over the semiconductor die, first encapsulant, and second encapsulant opposite the first conductive layer, wherein the conductive pillar extends through the first encapsulant between the first conductive layer and second conductive layer.

US Pat. No. 10,083,903

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MOLDED LASER VIA INTERPOSER AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

11. An integrated circuit packaging system comprising:an integrated circuit on a substrate;
an interposer substrate on the integrated circuit, the interposer substrate having an interposer pad electrically connected to the integrated circuit with an interposer interconnect;
an encapsulant around the integrated circuit and the interposer substrate with a hole in the encapsulant aligned over the interposer pad; and
a conductive connector on and in direct contact with the interposer pad, the conductive connector completely encircled by the hole at a top planar surface of the encapsulant, and the conductive connector having a regular spacing between the conductive connector and a further conductive connector immediately adjacent to the conductive connector less than a regular external spacing between an external interconnect and a further external interconnect immediately adjacent to the external interconnect.

US Pat. No. 10,074,553

WAFER LEVEL PACKAGE INTEGRATION AND METHOD

STATS ChipPAC Pte. Ltd., ...

1. A method of making a wafer level chip scale package, comprising the steps (a)-(j) in sequence:(a) providing a temporary wafer level substrate;
(b) forming a wafer level interconnect structure over the temporary wafer level substrate using wafer level processes including at a temperature greater than or equal to 200° C. by,
(i) forming a first insulating layer over a surface of the temporary wafer level substrate, wherein a first surface of the first insulating layer is in direct contact with the surface of the temporary wafer level substrate, and
(ii) forming a first conductive layer in direct contact with a second surface of the first insulating layer opposite the first surface of the first insulating layer after forming the first insulating layer;
(c) disposing a plurality of first semiconductor die over the wafer level interconnect structure;
(d) depositing an underfill material between the first semiconductor die and the wafer level interconnect structure;
(e) depositing a first encapsulant over an entire surface of the wafer level interconnect structure and around the plurality of first semiconductor die;
(f) removing the temporary wafer level substrate while retaining the entire first insulating layer;
(g) forming a plurality of openings through the first insulating layer and exposing a portion of the first conductive layer;
(h) forming an under bump metallization (UBM) layer in the openings to contact the first conductive layer;
(i) forming a second insulating layer in contact with the first surface of the first insulating layer; and
(j) forming a plurality of bumps on the UBM layer,
wherein forming the wafer level interconnect structure further includes forming a third insulating layer over the first conductive layer and the first insulating layer; forming a second conductive layer over the first conductive layer and the third insulating layer; forming a fourth insulating layer over the second conductive layer and the third insulating layer; forming a third conductive layer over the second conductive layer and the fourth insulating layer; and forming a fifth insulating layer over the third conductive layer and the fourth insulating layer; removing a portion of the fifth insulating layer to expose apportion of the third conductive layer and depositing a metal layer in the removed portion of the fifth insulating layer.

US Pat. No. 9,922,915

BUMP-ON-LEAD FLIP CHIP INTERCONNECTION

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a trace including an interconnect site over a surface of the substrate;
providing a first semiconductor die;
forming a composite interconnect structure over the first semiconductor die, the composite interconnect structure including
a non-collapsible portion and a collapsible portion formed over the first semiconductor die; and

disposing the first semiconductor die with the composite interconnect structure over the interconnect site.

US Pat. No. 9,865,525

SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT POP DEVICE WITH PWB VERTICAL INTERCONNECT UNITS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
providing a plurality of modular interconnect units by providing a core material and forming a plurality of vertical interconnect
structures extending through the core material to a surface of the modular interconnect units;

disposing the modular interconnect units and semiconductor die in proximity to each other;
depositing an encapsulant over and around the semiconductor die and modular interconnect units;
removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion
of the encapsulant over the surface of the modular interconnect units; and

forming an opening through the second portion of the encapsulant extending to the vertical interconnect structures of the
modular interconnect units.

US Pat. No. 9,837,303

SEMICONDUCTOR METHOD AND DEVICE OF FORMING A FAN-OUT DEVICE WITH PWB VERTICAL INTERCONNECT UNITS

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
disposing a modular interconnect unit including a plurality of interconnect structures adjacent to the semiconductor die;
depositing an encapsulant over the semiconductor die and modular interconnect unit;
removing a first portion of the encapsulant extending to a surface of the semiconductor die while leaving a second portion
of the encapsulant over the modular interconnect unit;

forming a first insulating layer over the semiconductor die and modular interconnect unit;
forming a plurality of openings in the first insulating layer over a first interconnect structure of the plurality of interconnect
structures with each opening of the plurality of openings extending to a surface of the first interconnect structure leaving
a continuous portion of the first insulating layer between the plurality of openings over the surface of the first interconnect
structure; and

forming a conductive layer over the first insulating layer and into the plurality of openings to contact the first interconnect
structure.

US Pat. No. 9,728,415

SEMICONDUCTOR DEVICE AND METHOD OF WAFER THINNING INVOLVING EDGE TRIMMING AND CMP

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer containing a plurality of semiconductor dies formed in a base material extending across the
semiconductor wafer and a plurality of conductive vias formed partially through an active surface of the base material with
a distal end of the conductive vias embedded in the base material;

depositing an encapsulant over the active surface of the base material and around a peripheral region of the semiconductor
wafer;

removing a first portion of the encapsulant and a first portion of the base material from a second surface of the base material
opposite the active surface of the base material around the peripheral region to form a notch extending laterally through
the encapsulant to remove all of the encapsulant around the perimeter of the semiconductor wafer within a height of the notch
and further extending laterally into the base material, wherein the notch terminates prior to the conductive vias to leave
the distal end of the conductive vias embedded in the base material; and

removing a second portion of the base material after forming the notch to remove the notch and expose the distal end of the
conductive vias.

US Pat. No. 9,721,862

SEMICONDUCTOR DEVICE AND METHOD OF USING A STANDARDIZED CARRIER TO FORM EMBEDDED WAFER LEVEL CHIP SCALE PACKAGES

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor wafers, each semiconductor wafer including a first number of semiconductor die;
singulating the semiconductor die from the semiconductor wafers including singulating the semiconductor wafers through a first
portion of a base semiconductor material to separate the semiconductor die and singulating through a second portion of the
base semiconductor material to remove the second portion of the base semiconductor material from a side of the semiconductor
die;

providing a standardized carrier;
disposing a second number of the semiconductor die over the standardized carrier, the second number greater than the first
number;

depositing an encapsulant over the semiconductor die and standardized carrier; and
singulating through the encapsulant to form a semiconductor package.

US Pat. No. 9,704,824

SEMICONDUCTOR DEVICE AND METHOD OF FORMING EMBEDDED WAFER LEVEL CHIP SCALE PACKAGES

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a semiconductor die including a notch formed in a peripheral region of an active surface of the semiconductor die;
an encapsulant deposited around the semiconductor die and into the notch, wherein a surface of the encapsulant is coplanar
with the notched active surface of the semiconductor die; and

a build-up interconnect structure formed over the semiconductor die and entirely within a footprint of the semiconductor die.

US Pat. No. 9,640,603

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INDUCTOR OVER INSULATING MATERIAL FILLED TRENCH IN SUBSTRATE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a trench in the substrate to follow a coiled path;
conformally applying a first insulating layer into the trench;
depositing an insulating material in contact with the first insulating layer to fill the trench;
forming a first conductive layer over a surface of the insulating material opposite the first insulating layer; and
forming a second conductive layer over the first conductive layer as a coil to exhibit an inductive property, the insulating
material in the trench isolating the first conductive layer and second conductive layer from the substrate.

US Pat. No. 9,620,413

SEMICONDUCTOR DEVICE AND METHOD OF USING A STANDARDIZED CARRIER IN SEMICONDUCTOR PACKAGING

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first semiconductor wafer including a plurality of first semiconductor die;
singulating the first semiconductor wafer to separate each of the first semiconductor die;
providing a first carrier, wherein a size of the first carrier is independent of both a size and number of the first semiconductor
die singulated from the first semiconductor wafer; and

disposing the first semiconductor die over the first carrier in a high-density arrangement after singulating the first semiconductor
wafer.

US Pat. No. 9,905,491

INTERPOSER SUBSTRATE DESIGNS FOR SEMICONDUCTOR PACKAGES

STATS ChipPAC Pte. Ltd., ...

1. A package comprising:
a first substrate having a first surface and a second surface opposite the first surface;
an integrated circuit device mounted on the first substrate via a plurality of device interconnects, the plurality of device
interconnects between the first surface and the integrated circuit device;

a plurality of internal interconnects mounted on the first surface adjacent the integrated circuit device, wherein each internal
interconnect includes a first height;

a second substrate having a third surface and a fourth surface opposite the third surface, the second substrate mounted over
the first substrate, the third surface is in contact with the plurality of internal interconnects and faces the first surface,
the third surface not in contact with the integrated circuit device;

an encapsulation between the first substrate and the second substrate, the encapsulation in direct contact with the integrated
circuit device and the plurality of the internal interconnects, the encapsulation completely covering the first surface and
the third surface; and

wherein:
the second substrate includes a cavity formed on the third surface extending into at least a portion of the second substrate
to configure a second height as measured from a base of the cavity to the upper surface of the integrated circuit device,
wherein the second height is in the range of from about 15% to about 40% of the first height, and the encapsulation having
an encapsulation protrusion filling the cavity; and

the fourth surface includes a recess extending into the second substrate, the recess formed at an edge of the second substrate.

US Pat. No. 9,893,017

DOUBLE-SIDED SEMICONDUCTOR PACKAGE AND DUAL-MOLD METHOD OF MAKING SAME

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
forming a first conductive layer;
disposing a first semiconductor die over the first conductive layer;
forming a conductive pillar over the first conductive layer;
depositing a first encapsulant over the first conductive layer and first semiconductor die;
depositing a second encapsulant around the first encapsulant, first conductive layer, and first semiconductor die; and
forming a second conductive layer over the first semiconductor die, first encapsulant, and second encapsulant opposite the
first conductive layer, wherein the conductive pillar extends through the first encapsulant between the first conductive layer
and second conductive layer.

US Pat. No. 9,893,045

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INTERPOSER FRAME OVER SEMICONDUCTOR DIE TO PROVIDE VERTICAL INTERCONNECT

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing an interposer substrate including,
a core substrate,
a plurality of conductive vias formed through the core substrate,
a plurality of conductive pillars extending from a surface of the interposer substrate and electrically connected to the conductive
vias, and

an opening formed through the interposer substrate;
disposing the interposer substrate over a first semiconductor die with the opening of the interposer substrate outside a footprint
of the first semiconductor die;

depositing an encapsulant over the first semiconductor die, wherein the encapsulant passes into the opening of the interposer
substrate; and

forming an interconnect structure over the encapsulant and first semiconductor die.

US Pat. No. 9,842,775

SEMICONDUCTOR DEVICE AND METHOD OF FORMING A THIN WAFER WITHOUT A CARRIER

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming a conductive via partially through the semiconductor die and exposed at a first surface of the semiconductor die;
forming a first redistribution layer over the first surface of the semiconductor die and coupled to the conductive via;
forming a first solder bump over the first redistribution layer, wherein the first solder bump is electrically coupled to
the conductive via through the first redistribution layer;

depositing an encapsulant over the first surface of the semiconductor die to completely cover the first redistribution layer
and first solder bump;

removing a portion of the semiconductor die opposite the first surface after depositing the encapsulant to expose the conductive
via and create a second surface of the semiconductor die;

forming a second redistribution layer over the second surface of the semiconductor die and coupled to the conductive via;
and

forming a second solder bump over the second redistribution layer, wherein the second solder bump is electrically coupled
to the conductive via through the second redistribution layer.

US Pat. No. 9,842,808

SEMICONDUCTOR DEVICE AND METHOD OF FORMING VERTICAL INTERCONNECT IN FO-WLCSP USING LEADFRAME DISPOSED BETWEEN SEMICONDUCTOR DIE

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die or component;
a first substrate including a plate and a plurality of conductive bodies extending from a first exterior surface of the plate,
the conductive bodies extending from the first substrate and disposed around a side surface of the first semiconductor die
or component such that the first semiconductor die or component is disposed directly between a first conductive body and a
second conductive body of the conductive bodies, wherein a second exterior surface of the plate opposite the first exterior
surface of the plate is coplanar with a back exterior surface of the first semiconductor die or component;

a first encapsulant deposited over the first substrate and first semiconductor die or component and between the conductive
bodies; and

a first interconnect structure formed over the first encapsulant and electrically connected to the conductive bodies of the
first substrate.

US Pat. No. 9,704,769

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ENCAPSULATED WAFER LEVEL CHIP SCALE PACKAGE (EWLCSP)

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a plurality of semiconductor die;
depositing an encapsulant around and over the semiconductor die;
forming a first insulating layer over an active surface of the semiconductor die and in contact with the encapsulant;
forming an interconnect structure over the first insulating layer and semiconductor die by,
(a) forming a conductive layer, and
(b) forming a bump over the conductive layer, wherein the entire interconnect structure is disposed within a footprint of
the semiconductor die as a fan-in interconnect structure;

forming a protection layer over a top surface of the encapsulant and over a second surface of the semiconductor die opposite
the active surface; and

singulating the plurality of semiconductor die through the protective layer, encapsulant, and first insulating layer to leave
a thickness of the encapsulant disposed over a side surface of the semiconductor die less than 100 micrometers and the first
insulating layer and protection layer terminating at an outside surface of the encapsulant.

US Pat. No. 9,673,093

SEMICONDUCTOR DEVICE AND METHOD OF MAKING WAFER LEVEL CHIP SCALE PACKAGE

STATS ChipPAC Pte. Ltd., ...

14. A semiconductor device, comprising:
a semiconductor die including a contact pad;
a conductive layer formed over the semiconductor die, wherein the conductive layer includes a top surface extending from the
contact pad over a surface of the semiconductor die to include an interconnect site of the conductive layer outside the contact
pad;

a first insulating layer formed over the top surface of the conductive layer including an opening in the first insulating
layer over the interconnect site of the conductive layer; and

an interconnect structure formed within the opening over the interconnect site of the conductive layer, wherein a first portion
of the interconnect structure terminates on the top surface of the conductive layer and a second portion of the interconnect
structure opposite the first portion contacts a side surface of the conductive layer.

US Pat. No. 9,666,500

SEMICONDUCTOR DEVICE AND METHOD OF FORMING INSULATING LAYER DISPOSED OVER THE SEMICONDUCTOR DIE FOR STRESS RELIEF

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer;
forming a first insulating layer over the semiconductor wafer;
forming a second insulating layer over the first insulating layer; and
singulating the semiconductor wafer into a plurality of semiconductor die.

US Pat. No. 9,620,455

SEMICONDUCTOR DEVICE AND METHOD OF FORMING ANISOTROPIC CONDUCTIVE FILM BETWEEN SEMICONDUCTOR DIE AND BUILD-UP INTERCONNECT STRUCTURE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a semiconductor wafer including a plurality of semiconductor die comprising bumps formed over contact pads on an
active surface of the semiconductor die;

depositing an anisotropic conductive film (ACF) over the bumps and active surface of the semiconductor wafer;
singulating the semiconductor wafer to separate the semiconductor die;
providing a temporary carrier;
disposing the semiconductor die with the ACF oriented to the temporary carrier;
compressing the ACF under the bumps to form a conductive portion of the ACF electrically connected to the bumps;
curing the ACF to form a cured ACF;
depositing an encapsulant over the semiconductor die and temporary carrier;
removing the temporary carrier to expose the conductive portion of the cured ACF under the bumps; and
forming an interconnect structure over the semiconductor die, cured ACF, and encapsulant with the interconnect structure being
electrically connected through the conductive portion of the cured ACF to the bumps.

US Pat. No. 9,558,965

SEMICONDUCTOR DEVICE WITH THIN PROFILE WLCSP WITH VERTICAL INTERCONNECT OVER PACKAGE FOOTPRINT

STATS ChipPAC Pte. Ltd., ...

1. A semiconductor device, comprising:
a first semiconductor die including a first thickness during fabrication;
a second semiconductor die including a first thickness during fabrication and an active surface of the second semiconductor
die disposed over an active surface of the first semiconductor die;

an encapsulant deposited over the first semiconductor die and second semiconductor die;
a conductive pillar formed through the encapsulant within a footprint of the first semiconductor die;
a build-up interconnect structure including an insulating layer and a redistribution layer each formed directly on the encapsulant
and a non-active surface of the second semiconductor die, the redistribution layer of the build-up interconnect structure
directly contacting the conductive pillar;

wherein the first semiconductor die includes a second thickness less than the first thickness of the first semiconductor die
and the second semiconductor die includes a second thickness less than the first thickness of the second semiconductor die
in the semiconductor device; and

a contact pad formed on a non-active surface of the first semiconductor die, the contact pad electrically connected to the
conductive pillar and the build-up interconnect structure.

US Pat. No. 10,096,540

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUMMY PILLARS BETWEEN SEMICONDUCTOR DIE AND SUBSTRATE FOR MAINTAINING STANDOFF DISTANCE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:providing a semiconductor die;
forming a conductive layer over the semiconductor die;
forming an insulating layer over the conductive layer;
depositing a conductive material within openings of the insulating layer to form a plurality of conductive pillars over the conductive layer and a plurality of rigid dummy pillars over the semiconductor die electrically isolated from the conductive layer and conductive pillars, wherein a height of the rigid dummy pillars is greater than a height of the conductive pillars;
disposing a bump material over the conductive pillars;
providing a substrate;
disposing the semiconductor die over the substrate after forming the conductive pillars and rigid dummy pillars with the rigid dummy pillars maintaining a fixed standoff distance between the semiconductor die and substrate; and
reflowing the bump material, wherein surface tension retains the bump material within a footprint of the conductive pillars and the fixed standoff distance reduces pressure on the bump material.

US Pat. No. 9,941,207

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING 3D PACKAGE WITH SHORT CYCLE TIME AND HIGH YIELD

STATS ChipPAC Pte. Ltd., ...

22. A method of making a semiconductor device, comprising:providing a first build-up interconnect structure;
disposing a semiconductor die over the first build-up interconnect structure;
disposing a vertical interconnect structure over the first build-up interconnect structure adjacent to the semiconductor die;
providing a carrier;
forming a second build-up interconnect structure on the carrier;
disposing the second build-up interconnect structure over the first build-up interconnect structure, vertical interconnect structure, and semiconductor die; and
removing the carrier after disposing the second build-up interconnect structure over the first build-up interconnect structure to expose a contact pad of the second build-up interconnect structure.

US Pat. No. 9,799,589

INTEGRATED CIRCUIT PACKAGING SYSTEM WITH A GRID ARRAY WITH A LEADFRAME AND METHOD OF MANUFACTURE THEREOF

STATS ChipPAC Pte. Ltd., ...

1. A method of manufacture of an integrated circuit packaging system comprising:
forming a conductive trace having a terminal end and a circuit end, the conductive trace, the terminal end, and the circuit
end having identical and uniform physical and chemical properties;

forming a terminal on the terminal end;
connecting an integrated circuit die having interconnects directly on the circuit end of the conductive trace, the integrated
circuit die laterally offset from the terminal, the active side of the integrated circuit die facing the circuit end;

forming an insulation layer directly on the terminal and the integrated circuit die, the integrated circuit die covered by
the insulation layer, the interconnects of the integrated circuit die in direct contact with only the circuit end of the conductive
trace and the insulation layer; and

forming a package body on the insulation layer and the conductive trace, the package body having a concave surface between
the terminal and another terminal with the concave surface having the characteristics of an etching process.

US Pat. No. 9,799,621

SEMICONDUCTOR DEVICE AND METHOD OF FORMING DUPLEX PLATED BUMP-ON-LEAD PAD OVER SUBSTRATE FOR FINER PITCH BETWEEN ADJACENT TRACES

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a substrate;
forming a first patterning layer over the substrate;
forming a plurality of conductive segments over the substrate within a plurality of openings of the first patterning layer;
forming a second patterning layer over the first patterning layer and conductive segments;
forming a first conductive layer within an opening of the second patterning layer, wherein the opening of the second patterning
layer is aligned with one of the openings in the first patterning layer and the first conductive layer includes a cross-sectional
width equal to a cross-sectional width of a first one of the conductive segments and in contact with the first one of the
conductive segments and vertically offset from a second one of the conductive segments; and

forming an insulating layer over the substrate, first conductive layer, and conductive segments after forming the first conductive
layer, wherein the insulating layer is disposed between the first one of the conductive segments and the second one of the
conductive segments and contacts a surface of the second one of the conductive segments opposite the substrate.

US Pat. No. 9,640,504

SEMICONDUCTOR DEVICE AND METHOD OF PROVIDING Z-INTERCONNECT CONDUCTIVE PILLARS WITH INNER POLYMER CORE

STATS ChipPAC Pte. Ltd., ...

1. A method of making a semiconductor device, comprising:
providing a first conductive layer;
forming a plurality of polymer pillars over the first conductive layer;
forming a second conductive layer over the polymer pillars to form a plurality of conductive z-interconnect structures; and
disposing a semiconductor die between the conductive z-interconnect structures and contacting the first conductive layer.