US Pat. No. 9,287,861

CASCODED COMPARATOR WITH DYNAMIC BIASING FOR COLUMN PARALLEL SINGLE SLOPE ADCS

SK Hynix Inc., Gyeonggi-...

1. Circuitry for processing signals, the circuitry comprising:
a first PMOS transistor with a source terminal coupled to a positive voltage supply;
a drain terminal of the first PMOS transistor coupled to a source terminal of a second PMOS transistor and to a source terminal
of a third PMOS transistor;

a first NMOS transistor with a drain terminal coupled to a drain terminal of the second PMOS transistor and to a gate terminal
of the second PMOS transistor;

a second NMOS transistor with a drain terminal coupled to a drain terminal of the third PMOS transistor and to a gate terminal
of the second NMOS transistor;

a source terminal of the first NMOS transistor and a source terminal of the second NMOS transistor coupled to ground;
an input ramp signal applied to a gate terminal of the third PMOS transistor; and
an output signal provided at the source terminal of the second PMOS transistor which is coupled at the drain terminal of the
second PMOS transistor and at the drain terminal of the first NMOS transistor.

US Pat. No. 9,275,693

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a power control signal generator suitable for generating a first to a third power control signal in response to a detection
signal generated from detecting a level of a power supply voltage signal; and

a sense amplifier circuit suitable for generating a first power signal driven to have a third drive voltage in response to
the third power control signal and suitable for sensing and amplifying a level of a bit line using the first power signal
as a power supply voltage, wherein the first power signal is driven to have a first drive voltage in response to the first
power control signal and the first power signal is driven to have a second drive voltage in response to the second power control
signal.

US Pat. No. 9,529,714

ELECTRONIC DEVICE

SK Hynix Inc., Gyeonggi-...

1. An electronic device comprising a semiconductor memory, wherein the semiconductor memory includes:
a first magnetic layer having a variable magnetization direction;
a second magnetic layer having a pinned magnetization direction; and
a tunnel barrier layer interposed between the first magnetic layer and the second magnetic layer,
wherein the second magnetic layer includes FeCoB and molybdenum (Mo) as an additive,
wherein a content of the molybdenum in the second magnetic layer is more than zero and less than 10%, and
wherein the second magnetic layer has a thickness of 10 Å to 30 Å.

US Pat. No. 9,263,114

ELECTRONIC DEVICE

SK Hynix Inc., Gyeonggi-...

1. An electronic device comprising a semiconductor memory unit, the semiconductor memory unit comprising:
first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural
number equal to or greater than 2;

a reference resistance element having a first reference resistance value; and
first to Nth comparison units which correspond to the first to Nth in variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding
variable resistance element is greater or less than a second reference resistance value,

wherein the first to Nth comparison units are commonly coupled to the reference resistance element.

US Pat. No. 9,335,777

VOLTAGE GENERATION CIRCUITS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A voltage generation circuit comprising:
a reference voltage generator suitable for generating a reference voltage signal having a constant level without a correspondence
to a temperature variation;

a comparator suitable for comparing a first drivability controlled by a level of the reference voltage signal with a second
drivability controlled by a level of a comparison voltage signal to generate a comparison signal;

a voltage divider suitable for dividing a power supply voltage to generate first to fourth division voltage signals whose
levels are divided by a plurality of resistors serially connected between a power supply voltage terminal and a ground voltage
terminal;

a counter suitable for outputting first and second count signals counted in response to an external clock if the comparison
signal is disabled; and

a selection transmitter suitable for outputting any one of the first to fourth division voltage signals as the comparison
voltage signal according to a level combination of the first and second count signals.

US Pat. No. 9,530,768

GATE-COUPLED NMOS DEVICE FOR ELECTRO-STATIC DISCHARGE PROTECTION

SK Hynix Inc., Gyeonggi-...

1. A gate-coupled NMOS device comprising:
a P-type well region;
an N-type well region surrounding the P-type well region;
an N-channel MOS transistor disposed in the P-type well region;
an N+-type tap region disposed in the N-type well region;

a first conductive layer disposed over the N-type well region by interposing a first insulation layer and constituting a MOS
capacitor with the N-type well region and the first insulation layer; and

a second conductive layer disposed over the N-type well region by interposing a second insulation layer and constituting a
resistor,

wherein a first end portion of the first conductive layer contacts a first end portion of the second conductive layer.

US Pat. No. 9,087,984

SEMICONDCUTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a semiconductor device, comprising:
forming a pinned layer, a tunnel insulating layer, a free layer, a first conducting layer, and a mask pattern;
etching the first conducting layer by using the mask pattern as an etch barrier;
etching the free layer, the tunnel insulating layer and the pinned layer by using the etched first conducting layer as an
etch barrier;

forming a spacer pattern at sides of the etched first conducting layer, free layer, tunnel insulting layer and pinned layer;
and

forming a magnetic induction layer to surround the spacer pattern connected to the pinned layer,
wherein a height of the magnetic induction layer is equal to or lower than that of the pinned layer.

US Pat. No. 9,281,035

SEMICONDUCTOR INTEGRATED CIRCUIT CAPABLE OF CONTROLLING READ COMMAND

SK HYNIX INC., Gyeonggi-...

1. A semiconductor integrated circuit comprising:
a command decoder configured to provide a read command in synchronization with a second edge of a clock according to an external
command in synchronization with a first edge of the clock having first and second edges;

a read/write command controller configured to provide a read clock in synchronization with the second edge of the clock in
response to the read command;

a column address latch unit configured to latch an external address in response to the read command, and provide a column
address in synchronization with the second edge of the clock; and

a column command generator configured to provide a write-read command for generating the read clock in response to the read
command.

US Pat. No. 9,530,480

SEMICONDUCTOR MEMORY DEVICE

KABUSHIKI KAISHA TOSHIBA,...

1. A method of controlling a magnetoresistive random access memory, comprising:
receiving an active command through command/address pins at a rising edge and a falling edge of a clock signal, the active
command specifying a first set of row addresses;

receiving a read command, after receiving the active command, through the command/address pins at a rising edge and a falling
edge of the clock signal, the read command specifying column addresses and a second set of row addresses;

reading data from at least one of memory cells, in response to receiving the read command, according to the first set of row
addresses and the second set of row addresses associated with the read command;

receiving a write command through the command/address pins at a rising edge and a falling edge of the clock signal, while
reading the data from the at least one of memory cells, the write command specifying column addresses and a second set of
row addresses;

outputting the data read from the at least one of memory cells to data input/output pins, according to the column addresses
associated with the read command, after a lapse of a predetermined read latency from receiving the read command;

receiving data through the data input/output pins, according to the column addresses associated with the write command, after
a lapse of a predetermined write latency from receiving the write command; and

writing the data inputted from the data input/output pins to at least one of memory cells according to the first set of row
addresses and the second set of row addresses associated with the write command.

US Pat. No. 9,058,900

SYSTEM, SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A method for operating a semiconductor memory device including a memory block-constituted by main memory cells and dummy
memory cells, the method comprising:
reading out an erase count of the memory block stored in the dummy memory cells, erasing the memory block, increasing the
read-out erase count, and storing the increased erase count in the dummy memory cells,

wherein the dummy memory cells are connected to at least one dummy word line,
wherein the main memory cells are divided into a main cell area and a flag cell area,
wherein the dummy memory cells are divided into a dummy main cell area and a dummy flag cell area,
wherein the erase count of the memory block is read out from the dummy flag cell area, and
wherein the increased erase count is stored in the dummy flag cell area.

US Pat. No. 9,231,065

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

SK HYNIX INC., Icheon (K...

1. A semiconductor device comprising:
a first well provided at a first level; and
a gettering layer provided at a second level and including a first doping layer and a second doping layer, wherein the second
doping layer comprises a polarity opposite to a polarity of the first doping layer, the second level being deeper than the
first level,

wherein the first doping layer and the second doping layer overlap at least partially.

US Pat. No. 9,531,572

INTERFACE CIRCUIT FOR HIGH SPEED COMMUNICATION AND SYSTEM INCLUDING THE SAME

SK HYNIX INC., Icheon-Si...

1. An interface circuit comprising:
a receiver configured to receive a multi-level symbol according to a status of a wire bus;
a clock recovery circuit configured to generate a recovered clock based on the multi-level symbol, wherein whether or not
the clock recovery circuit operates is determined based on a clock selection signal;

a clock selection circuit configured to generate an internal clock from one of an external clock and the recovered clock according
to the clock selection signal; and

a latch and decoding circuit configured to latch the multi-level symbol based on the internal clock.

US Pat. No. 9,231,619

LDPC DECODER WITH A VARIABLE NODE UPDATER WHICH USES A SCALING CONSTANT

SK Hynix Inc., Gyeonggi-...

6. A method, comprising:
using a processor to compute a first message, associated with going from one of a plurality of variable nodes to one of a
plurality of check nodes, wherein:

one or more connections between the plurality of variable nodes and the plurality of check nodes are specified by an LDPC
parity check matrix;

a scaling constant is used to compute the first message; and
computing the first message includes:
determining if all log-likelihood ratio (LLR) values, used in computing the first message, are guaranteed to have the same
magnitude; and

in the event it is determined that said all LLR values are guaranteed to have the same magnitude:
obtaining a stored magnitude associated with the same magnitude which said all LLR values are guaranteed to have; and
calculating the first message, including by selecting an appropriate sign and using the stored magnitude; and
using the processor to compute a second message, associated with going from one of the plurality of check nodes to one of
the plurality of variable nodes, wherein the scaling constant is not used to compute the second message.

US Pat. No. 9,130,053

NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A nonvolatile memory device, comprising:
a pipe connection gate electrode having a bottom in a groove buried in a substrate;
one or more pipe channel layers formed within the pipe connection gate electrode;
pairs of main channel layers each coupled to the pipe channel layer and extended in a direction substantially perpendicular
to the substrate; and

a plurality of interlayer insulating layers and a plurality of cell gate electrodes alternately stacked along the main channel
layers,

wherein the pipe connection gate electrode comprises a metal silicide layer formed within the groove,
wherein the nonvolatile memory device includes a three-dimensional (3-D) structure,
wherein the pipe connection gate electrode comprises a second conductive layer for a gate electrode configured to be in contact
with a top of the pipe channel layer,

wherein the pipe connection gate electrode comprises the metal silicide layer over the substrate, a first conductive layer
over the metal silicide layer, and the second conductive layer over the first conductive layer.

US Pat. No. 9,236,386

SEMICONDUCTOR DEVICE WITH BURIED BIT LINE AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a semiconductor substrate;
an active region, including a body, formed on a surface of the semiconductor substrate;
pillars formed on the body;
a supporter buried the active region; and
buried bit lines formed in the body and including fully silicided metal silicide,
wherein the supporter is formed between adjacent pillars and between adjacent buried bit lines.

US Pat. No. 9,123,426

SEMICONDUCTOR DEVICE INCLUDING FUSE ARRAY

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a control signal driver suitable for driving a control signal in response to a fuse reset signal, a fuse set signal and fuse
data;

a control signal latch unit suitable for latching the control signal in response to the fuse set signal and the fuse data;
an internal driver suitable for driving an internal node in response to the control signal, an address signal and a write
strobe signal; and

a buffer suitable for buffering a signal of the internal node to generate a redundancy signal.

US Pat. No. 9,337,203

SEMICONDUCTOR DEVICE WITH LINE-TYPE AIR GAPS AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a semiconductor device, comprising:
forming a first inter-layer dielectric layer over a substrate;
forming a first contact hole by etching the first inter-layer dielectric layer;
forming a preliminary first conductive plug that fills the first contact hole;
forming a bit line structure including a bit line over the preliminary first conductive plug;
forming a first conductive plug and a gap by etching the preliminary first conductive plug so that the gap is formed inside
of the first contact hole and between a sidewall of the first contact hole and the first conductive plug;

forming an insulating plug in the gap;
forming a multi-layer spacer including a sacrificial spacer and extending from over an upper portion of the insulating plug
to over a sidewall of the bit line structure;

forming a second conductive plug neighboring the bit line structures and the first conductive plugs with the multi-layer spacer
and the insulating plug therebetween; and

forming a line-type air gap within the multi-layer spacer by removing the sacrificial spacer.

US Pat. No. 9,323,260

INTERNAL VOLTAGE GENERATION CIRCUITS AND SEMICONDUCTOR DEVICES INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. An internal voltage generation circuit, the circuit comprising:
a voltage generator suitable for generating a temperature reference voltage signal whose level depends on an internal temperature,
a division reference voltage signal whose level is constant regardless of the internal temperature, and a selection reference
voltage signal obtained by detecting a level of an internal voltage signal, a level of the selection reference voltage signal
being controlled according to a first test mode signal; and

a detection voltage generator suitable for comparing the division reference voltage signal and the selection reference voltage
signal in response to the temperature reference voltage signal to generate a detection voltage signal controlling a pumping
operation of the internal voltage signal.

US Pat. No. 9,281,373

SEMICONDUCTOR DEVICE HAVING TUNGSTEN GATE ELECTRODE AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a substrate including an NMOS region and a PMOS region;
a first gate electrode formed in the NMOS region, wherein the first gate electrode is substantially consisting of a stack
of a carbon-containing tungsten film and a tungsten film; and

a second gate electrode formed in the PMOS region, wherein the second gate electrode comprises a stack of a carbon-containing
tungsten nitride film and a tungsten film,

wherein the carbon-containing tungsten film includes a fluorine-free tungsten containing carbon and has a low work function,
wherein a carbon content of the carbon-containing tungsten nitride film is less than a carbon content of the carbon-containing
tungsten film.

US Pat. No. 9,263,118

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:
a first pre-charge control block suitable for generating a first control signal by counting a number of toggles of an operation
clock in response to a first active pulse in a self-refresh operation exit mode;

a second pre-charge control block suitable for generating a second control signal in response to an active command for an
active operation in a self-refresh operation mode; and

an operation control block suitable for disabling the first pre-charge control block in the self-refresh operation mode, and
disabling the second pre-charge control block in a self-refresh operation exit mode, wherein

a pre-charge operation starts in response to the first and second control signals after the active operation.

US Pat. No. 9,299,714

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK HYNIX INC., Icheon (K...

1. A method of manufacturing a semiconductor device, the method comprising:
alternately forming first material layers and second material layers;
forming channel holes by etching the first material layers and the second material layers;
forming first recessed regions by etching the first material layers exposed to inner walls of the channel holes by a first
thickness;

forming floating gates in the first recessed regions;
forming second recessed regions by etching the second material layers exposed to the inner walls of the channel holes by a
second thickness; and

forming a channel layer having protrusions in the channel holes having the second recessed regions therein.

US Pat. No. 9,263,112

SEMICONDUCTOR INTEGRATED CIRCUIT

SK Hynix Inc., Gyeonggi-...

10. A semiconductor integrated circuit comprising:
one or more channels,
wherein each of the one or more channels comprises:
a first sub-channel configured to have a plurality of memory blocks;
a second sub-channel configured to have a plurality of memory blocks; and
a control block configured to recognize the first sub-channel and the second sub-channel as one channel or as independent
channels in response to a sub-channel setup signal,

wherein the first and second sub-channels are configured to share commands and addresses with each other and to have independent
input/output arrays, respectively.

US Pat. No. 9,286,988

NONVOLATILE MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A method for operating a nonvolatile memory device, comprising:
applying a negative erase voltage to a control gate electrode of a memory cell; and
applying a first voltage higher than the negative erase voltage to a channel through a source region to erase charges stored
in the memory cell through F-N tunneling,

wherein the nonvolatile memory device comprises:
the channel vertically extending from a substrate;
a plurality of memory cells stacked along the channel;
the source region connected to a first end portion of the channel; and
a bit line connected to a second end portion of the channel,
wherein the first end portion of the channel is formed as an undoped semiconductor layer or a semiconductor layer doped with
P-type impurities,

wherein the second end portion of the channel is formed of a semiconductor material of which a conductivity type is different
from that of the first end portion, and

wherein an intermediate portion of the channel is provided between the first end portion and the second end portion and is
formed of a semiconductor material of which a conductivity type is the same as that of the first end portion.

US Pat. No. 9,274,886

DATA STORAGE DEVICE HAVING A REDUCED ERROR OCCURRENCE, OPERATING METHOD THEREOF, AND DATA PROCESSING SYSTEM INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. An operating method of a data storage device, the operating method comprising the steps of:
reading a first data group associated with the data storage device;
detecting errors in the first data group;
correcting the errors in the first data group, if the errors detected in the first data group can be corrected;
estimating a read retry estimation voltage for a subsequent read retry operation of a second data group that is different
than the first data group and associated with the data storage device based on error correction data associated with the correcting
the errors of the first data group.

US Pat. No. 9,263,099

SEMICONDUCTOR MEMORY DEVICE FOR REDUCING STANDBY CURRENT

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:
a standby voltage providing unit configured to receive an external voltage, primarily clamp a predetermined voltage, secondarily
clamp the primarily clamped voltage, and provide the secondarily clamped voltage as an internal voltage, during a standby
mode.

US Pat. No. 9,154,140

DELAY LOCKED LOOP

SK Hynix Inc., Icheon (K...

1. A delay locked loop for locking a delay between an input signal and an output signal, comprising:
a variable delay line circuit configured to delay a pulse selection circuit output to generate the output signal;
a delay model circuit configured to delay the output signal to generate a first feedback signal;
a first phase comparator circuit configured to control a delay amount of the variable delay line circuit depending on a phase
difference between the input signal and the first feedback signal;

a pulse generation circuit configured to generate a pulse signal in response to the input signal and the first feedback signal
during a tracking operation;

a pulse retainer circuit configured to delay the output signal to generate a second feedback signal during the tracking operation;
a pulse selection circuit configured to select the pulse signal generated by the pulse generation circuit or the second feedback
signal as the pulse selection circuit output during the tracking operation; and

a second phase comparator circuit configured to generate a delay control signal to control the delay amount of the variable
delay line circuit depending on a phase difference between the pulse selection circuit output and the output signal during
the tracking operation.

US Pat. No. 9,130,150

SEMICONDUCTOR DEVICE AND FABRICATION METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a local silicon-on-insulator (SOI) substrate in which a portion of a line-shaped active region is connected to a semiconductor
substrate, and a remaining portion thereof is insulated from the semiconductor substrate;

gate structures formed in a line shape to be substantially perpendicular to the active region on the active region insulated
from the semiconductor substrate, and to surround outer sidewalls and an upper surface of the active region, and having a
stacking structure of a gate insulating layer, a liner conductive layer, a gate conductive layer, and a hard mask layer;

a source region formed in the active region connected to the semiconductor substrate; and
a drain region formed in the active region insulated from the semiconductor substrate between the gate structures,
wherein the gate insulating layer is formed along on the upper surface and the outer sidewalls of the active region, and a
bottom of a space between adjacent active regions;

the liner conductive layer is formed on the gate insulating layer along over the upper surface and the outer sidewalls of
the active region, and the bottom of the space between adjacent active regions: and

the gate conductive layer is formed on the liner conductive layer so as to fill the space between adjacent active regions.

US Pat. No. 9,275,703

SEMICONDUCTOR INTEGRATED CIRCUIT WITH STACK PACKAGE STRUCTURE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit including first semiconductor chip and second semiconductor chip that are stacked, wherein
the first semiconductor chip comprises:
a first column data driving circuit configured to transmit internal data in series to the second semiconductor chip based
on an internal strobe signal; and

a first column strobe signal driving circuit configured to generate first column strobe signals that are source-synchronized
with first column data transmitted to the second semiconductor chip by the first column data driving circuit, based on the
internal strobe signal, and transmit the first column strobe signals to the second semiconductor chip,

wherein the first column data is transmitted through a first through-chip via that vertically passes through the first semiconductor
chip or the second semiconductor chip,

wherein the first column strobe signals are differential strobe signals, and
wherein the first column strobe signals are transmitted through a second through-chip via and a third through-chip via that
vertically pass through the first semiconductor chip or the second semiconductor chip.

US Pat. No. 9,281,310

SEMICONDUCTOR DEVICE INCLUDING GATE STRUCTURE FOR THRESHOLD VOLTAGE MODULATION IN TRANSISTORS AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a semiconductor device, comprising:
forming an NMOS region and a PMOS region in a substrate;
forming a gate dielectric layer over the substrate;
forming a first work function layer that contains aluminum over the gate dielectric layer;
forming a reaction preventing layer consisting of polysilicon over the first work function layer;
selectively removing the reaction preventing layer and the first work function layer from the NMOS region;
forming a threshold voltage modulation layer that contains lanthanum over the remaining reaction preventing layer of the PMOS
region and the gate dielectric layer of the NMOS region;

forming a second work function layer over the threshold voltage modulation layer; and
annealing, thereby forming a first dipole-interface by diffusion of the aluminum into the gate dielectric layer of the PMOS
region and a second dipole-interface by diffusion of the lanthanum into the gate dielectric layer of the NMOS region, respectively,

wherein the remaining reaction preventing layer is formed between the first work function layer and the threshold voltage
modulation layer over the PMOS region.

US Pat. No. 9,231,580

SEMICONDUTOR APPARATUS FOR CONTROLLING BACK BIAS

SK Hynix Inc., Gyeonggi-...

1. A semiconductor apparatus comprising:
a back bias control block configured to generate a first P channel control signal, a second P channel control signal, a first
N channel control signal and a second N channel control signal according to an operation mode based on a command signal;

a first back bias switching block configured to provide one of a first high voltage and a second high voltage as a first P
channel back bias of a first internal circuit in response to the first P channel control signal, and to provide one of a first
low voltage and a second low voltage as a first N channel back bias of the first internal circuit in response to the first
N channel control signal; and

a second back bias switching block configured to provide one of the first high voltage and the second high voltage as a second
P channel back bias of a second internal circuit in response to the second P channel control signal, and to provide one of
the first low voltage and the second low voltage as a second N channel back bias of the second internal circuit in response
to the second N channel control signal,

wherein the first P channel control signal includes a first high voltage control signal and a second high voltage control
signal, and

wherein the back bias control block is configured to generate the first high voltage control signal having the first low voltage
and the second high voltage control signal having the second high voltage in a first operation mode, and to generate the first
high voltage control signal having the first high voltage and the second high voltage control signal having the first low
voltage in a second operation mode and in a third operation mode.

US Pat. No. 9,214,195

STACK BANK TYPE SEMICONDUCTOR MEMORY APPARATUS CAPABLE OF IMPROVING ALIGNMENT MARGIN

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory apparatus comprising:
a plurality of stack bank structures having at least two sub-banks continuously arranged without disconnection of data signal
lines;

a share block having a predecoder and a fuse set interposed between sub-banks in the stack bank structure; and
a main decoder interposed between the sub-bank and the share block.

US Pat. No. 9,093,524

VERTICAL-TYPE SEMICONDUCTOR APPARATUS AND FABRICATION METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

10. A method of fabricating a vertical-type semiconductor apparatus, the method comprising:
forming an inactive region having a first depth in a semiconductor substrate and formed from a surface thereof;
forming hard mask patterns on the semiconductor substrate including the inactive region and forming a plurality of pillars
by patterning the semiconductor substrate and the inactive region to a second depth;

forming a gate conductive layer on an outer circumference of each of the plurality of pillars;
forming a first insulating layer on the semiconductor substrate including the gate conductive layer and planarizing the first
insulating layer;

forming a gate contact hole by removing at least one of pillars formed on the inactive region to have a height lower than
the gate conductive layer; and

forming a gate contact by burying a conductive material in the gate contact hole.

US Pat. No. 9,153,339

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a fuse array having one valid fuse set which outputs a valid fuse status signal and a plurality of fuse sets, the fuse array
suitable for outputting a plurality of fuse status signals having different levels according to whether fuses in the plurality
of fuse sets are cut or not;

a code counter suitable for counting selection codes in a preset order in response to an enable signal and an operation clock;
and

a plurality of storage blocks suitable for receiving and storing the plurality of fuse status signals in a preset order in
response to the selection codes,

wherein the storage block comprises:
a plurality of latches suitable for storing the plurality of fuse status signals; and
a plurality of selectors suitable for enabling any of the plurality of latches in response to the selection codes,
wherein each of the plurality of selectors is on/off controlled in its operation in response to the valid fuse status signal
regardless of values of the selection codes.

US Pat. No. 9,274,939

MEMORY SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A memory system, comprising:
a memory controller configured to change data to be stored in memory cells according to an address of a weak cell in order
to store changed data having a lower program level than a highest program level among a plurality of program levels in peripheral
cells adjacent to the weak cell; and

a memory device configured to execute a program loop in order to store the changed data in a selected page,
wherein the memory controller generates an address of the changed data for identifying peripheral cells in which the changed
data is stored,

wherein the memory device stores the address of the changed data in a Content Address Memory block in a standby mode.

US Pat. No. 9,275,722

MEMORY DEVICE PREVENTING FAIL CAUSED BY SUCCESSIVE READ OPERATIONS AND SYSTEM INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A memory device comprising:
a memory array;
a transmitter suitable for outputting data to the outside of the memory device; and
a data bus suitable for transmitting data of a selected memory cell in the memory array to the transmitter during a read operation,
wherein when successive read commands for the same memory cell are applied, data transmission from the memory array to the
data bus is blocked, and data previously loaded in the data bus is outputted through the transmitter.

US Pat. No. 9,455,005

SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a plurality of data pads; a plurality of data buffers each suitable for buffering a signal inputted through a first input
node using a voltage inputted through a second input node, and outputting the buffered signal;

a plurality of driving units suitable for pull-up driving or pull-down driving output nodes of the plurality of data buffers
in response to the outputs of the plurality of data buffers, respectively; and

a calibration control unit suitable for generating a test signal in a calibration mode, adjusting the level of the test signal,
receiving outputs of the plurality of driving units while adjusting the level of the test signal, and adjusting drivabilities
of the plurality of driving units such that the logical values of the outputs of the plurality of driving units transit when
the test signal has a target level,

wherein data of the corresponding data pad is inputted to the first input node, and a reference voltage is applied to the
second input node, and

in the calibration mode, the test signal is inputted to the first input node, and a test voltage is applied to the second
input node.

US Pat. No. 9,285,414

METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE

SK Hynix Inc., Gyeonggi-...

1. A system for testing a semiconductor device, comprising:
an operation result decider configured to test and determine whether the semiconductor satisfies a condition set for an operation
mode of a plurality of operation modes based on an output of the semiconductor device; and

a set information controller configured to receive a determination result of the operation result thereof, change set information
based on the determination result of the operation result decider and transmit the set information to the semiconductor device,

wherein the semiconductor device is configured to operate in at least one of the plurality of operation modes in response
to the set information during a test operation.

US Pat. No. 9,286,999

SEMICONDUCTOR DEVICES

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a first input/output (I/O) part suitable for buffering command/address (C/A) signals inputted through a first pad part to
generate delay address signals;

an internal address generator suitable for generating a plurality of internal address signals according to a level combination
of the delay address signals; and

a second I/O part including a plurality of fuses selected by the plurality of internal address signals in a test mode,
wherein the plurality of fuses of the second I/O part are programmed according to logic levels of data inputted to the second
I/O part through a second pad part to control I/O characteristics of the second I/O part.

US Pat. No. 9,274,162

METHOD AND SYSTEM FOR TESTING SEMICONDUCTOR DEVICE

SK Hynix Inc., Gyeonggi-...

1. A method for testing a semiconductor device, comprising:
testing the semiconductor device in a normal operation mode; and
testing the semiconductor device in a first operation mode if the semiconductor device passes the testing in the normal operation
mode,

wherein if the semiconductor device passes the testing in the first operation mode, the semiconductor device is tested in
a second operation mode, and

wherein the semiconductor device is programmed to operate in the first operation mode if the semiconductor device fails the
testing in the second operation mode and the semiconductor device is programmed to operate in the second operation mode if
the semiconductor device passes the testing in the second operation mode.

US Pat. No. 9,276,500

RESERVOIR CAPACITOR AND SEMICONDUCTOR DEVICE INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A reservoir capacitor, comprising:
a first capacitor group having at least two capacitors, which are serially coupled to each other between a first power voltage
supply terminal and a second power voltage supply terminal;

a second capacitor group having at least two capacitors, which are serially coupled to each other between a third power voltage
supply terminal and a fourth power voltage supply terminal; and

a connection line suitable for electrically coupling a first coupling node between the at least two capacitors included in
the first capacitor group to a second coupling node between the at least two capacitors included in the second capacitor group,

wherein the first power voltage supply terminal and the third power voltage supply terminal are different from each other
and receive different power voltages, respectively, and the second power voltage supply terminal and the fourth power voltage
supply terminal are different from each other and receive different power voltages, respectively.

US Pat. No. 9,269,780

SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a semiconductor substrate including a trench;
a gate insulation film located over a bottom and sidewall of the trench;
a first gate formed over the gate insulation film and in a lower portion of the trench;
a second gate formed over the first gate and in an upper portion of the trench, wherein the first gate is electrically connected
to the second gate; and

a multi-layered structure including a nitride film and an oxide film provided between the gate insulation film and the second
gate, wherein an interface layer between the nitride film pattern and the insulation film pattern includes a plurality of
positive charges.

US Pat. No. 9,576,970

THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICE

SK HYNIX INC., Icheon-si...

1. A semiconductor device, comprising:
an insulating layer;
a plurality of first source layers formed substantially in the insulating layer and insulated from each other by the insulating
layer;

a plurality of conductive layers stacked substantially over the insulating layer;
channel layers that pass through the plurality of conductive layers and couple to the first source layer; and
second source layers formed substantially in the plurality of first source layers, respectively.

US Pat. No. 9,374,075

INPUT APPARATUS AND INPUT SYSTEM

SK hynix Inc., Icheon-si...

1. An input apparatus comprising:
a pulse width control circuit configured to generate a pulse width control signal by performing a logical operation on a pulse
width detection signal and a clock signal;

a reception circuit configured to selectively provide a received input signal as a period signal based on the clock signal
and the pulse width control signal; and

a latch circuit configured to provide an output signal by inverting the period signal, and provide the output signal as the
pulse width detection signal in response to the clock signal,

wherein the reception circuit further includes:
a path blocking circuit configured to block a path wherein the input signal is inverted so that the inverted resultant signal
is provided as the period signal in response to an inverted pulse width detection signal corresponding to inversion of the
pulse width detection signal.

US Pat. No. 9,287,325

VERTICAL TYPE SEMICONDUCTOR DEVICE, FABRICATION METHOD THEREOF AND OPERATION METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A vertical type semiconductor device, comprising:
a pillar structure having a stacking structure of a conductive layer and a data storage material and formed over a common
source region; and

a gate electrode formed to surround the data storage material of the pillar structure,
wherein the data conductive layer and the data storage material are sequentially stacked.

US Pat. No. 9,281,316

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a first direction in a cross-section view and a second direction in a plan view, wherein the second direction is perpendicular
to the first direction;

first stacked groups each including first interlayer insulating patterns and first conductive patterns alternately stacked
over a substrate in the first direction;

second stacked groups each including second interlayer insulating patterns and second conductive patterns alternately stacked
over the first stacked groups in the first direction;

a plurality of channel layers passing through the first stacked group, a support body, and the second stacked group in the
first direction;

first slits located between the first stacked groups to completely separate the first stacked groups from each other in the
second direction;

second slits located between the second stacked groups to completely separate the second stacked groups from each other in
the second direction; and

the support body including holes arranged at a predetermined interval and overlapping the first and second slits, wherein
the support body is formed between the first stacked groups and the second stacked groups in the first direction.

US Pat. No. 9,262,291

TEST DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A test device comprising:
a circuit modelling portion suitable for generating one or more model circuits by modelling a test-object circuit in a one-to-one
ratio relationship between the test-object circuit and the model circuits or in a one-to-multi ratio relationship between
the test-object circuit and the model circuits; and

a test operation portion suitable for synthesizing the model circuits and performing a test operation on the model circuits,
wherein the circuit modelling portion models the test-object circuit with the one-to-multi relationship to generate the model
circuits of different types based on a delay amount of the test-object circuit.

US Pat. No. 9,286,156

DATA STORAGE DEVICE AND METHOD FOR PROCESSING ERROR CORRECTION CODE THEREOF

SK Hynix Inc., Gyeonggi-...

1. A data storage device comprising:
a data storage medium; and
an error correction code unit configured to process an error correction code for data to be stored in the data storage medium,
wherein the error correction code unit comprises:
a storage block configured to include a plurality of regions, wherein each of the plurality of regions is addressed by a first
address and a second address and the data to be stored in the data storage medium is stored in first regions of the plurality
of regions; and

an encoder configured to divide the data stored in the first regions into a plurality of data groups according to the first
address, to rearrange data bits in each of the plurality of data groups according to the first address for generating a plurality
of rearranged data groups, to encode the plurality of rearranged data groups for generating a plurality of parity data groups,
to store the plurality of parity data groups in second regions of the plurality of regions, to rearrange data bits of the
plurality of data groups and the plurality of parity data groups according to the second address for generating a data set,
and to encode the data set for generating final parity data.

US Pat. No. 9,287,198

INTERCONNECTION STRUCTURE INCLUDING AIR GAP, SEMICONDUCTOR DEVICE INCLUDING AIR GAP, AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a first insulating layer;
a second insulating layer formed on the first insulating layer;
a first air gap disposed between the first insulating layer and the second insulating layer; and
a plurality of interconnection lines formed in the second insulating layer,
wherein a lower part of the interconnection lines protrudes into the first air gap and is surrounded by the first air gap,
wherein a height of the first air gap is less than a height of the interconnection lines, and a space between the interconnection
lines above the first air gap is filled with the second insulating layer.

US Pat. No. 9,275,758

ERROR DETECTION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT USING THE SAME

SK Hynix Inc., Gyeonggi-...

1. An error detection circuit comprising:
first error detection operation unit configured to perform a serial error detection operation on a serial data signal inputted
through each of multiple input/output pads, and to generate multiple pieces of preliminary information; and

a second error detection operation unit configured to perform a parallel error detection operation on the multiple pieces
of preliminary information, and to generate an error detection code.

US Pat. No. 9,275,705

INTEGRATED CIRCUIT FOR STORING INFORMATION

SK Hynix Inc., Gyeonggi-...

1. An integrated circuit comprising:
a first variable resistance unit including first and second transistors configured to change resistances through the first
and second transistors in response to first and second control signals in a programming operation mode, wherein the first
and second transistors are commonly coupled to a first output terminal;

a second variable resistance unit including third and fourth transistors configured to change resistances through the third
and fourth transistors values in response to third and fourth control signals in the programming operation mode, wherein the
third and fourth transistors are commonly coupled to a second output terminal; and

an information detection unit configured to compare voltages of the first and second output terminals and detect programming
information in a normal operation mode.

US Pat. No. 9,274,411

REFLECTION TYPE BLANK MASKS, METHODS OF FABRICATING THE SAME, AND METHODS OF FABRICATING REFLECTION TYPE PHOTO MASKS USING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A reflection type blank mask, the blank mask comprising:
a substrate having a recessed pattern with a predetermined depth;
a reflection layer substantially on the substrate;
an absorption layer substantially on the reflection layer; and
a resist layer substantially on the absorption layer, wherein the resist layer has a recessed part that is formed by transference
of the profile from the recessed pattern.

US Pat. No. 9,275,745

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a memory cell array including a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein
at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated
with the plurality of pages;

a second storage unit into which a page address, of the plurality of page addresses, stored in the first storage unit is loaded;
and

a control circuit configured to cancel a program operation if an externally inputted page address is less than or equal to
the page address loaded into the second storage unit, perform the program operation and update the second storage unit with
the externally inputted page address if the externally inputted page address is greater than the page address, transfer the
externally inputted page address to the first storage unit if the program operation is canceled, read the second storage unit
after the program operation is terminated to determine whether or not a delay time has occurred, and determine that the delay
time has occurred if a page address corresponding to a last programmed page is stored in the second storage unit and that
the delay time has not occurred if the page address corresponding to the last programmed page is not stored in the second
storage unit.

US Pat. No. 9,269,426

3D VARIABLE RESISTANCE MEMORY DEVICE HAVING JUNCTION FET AND DRIVING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A method of driving a variable resistance memory device, in which a plurality of memory cells are stacked, and each of
the plurality of memory cell includes a junction transistor and a variable resistor connected in parallel to the junction
transistor, the method comprising:
turning off a junction transistor of a selected one of the plurality of stacked memory cells; and
turning on junction transistors of non-selected memory cells of the plurality of stacked memory cells to form a current path
in a variable resistance layer of the selected memory cell.

US Pat. No. 9,275,712

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A semiconductor system comprising:
a controller configured to output external commands and external addresses; and
a semiconductor device configured to generate internal commands from the external commands by a delay amount controlled according
to PVT information in a boot-up operation, generate internal addresses by delaying the external addresses, and select a plurality
of banks according to the internal addresses in synchronization with the internal commands.

US Pat. No. 9,275,968

FLIP CHIP PACKAGES HAVING CHIP FIXING STRUCTURES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME

SK HYNIX INC., Icheon (K...

1. A flip chip package comprising:
a chip;
main bumps disposed on a first region of a surface of the chip;
dummy bumps disposed on a second region of the surface of the chip;
a substrate;
dams disposed on a surface of the substrate;
connection pads disposed on the surface of the substrate and electrically connected to respective ones of the main bumps;
and

adhesion patterns attaching the dummy bumps to respective ones of the dams.

US Pat. No. 9,275,755

SEMICONDUCTOR SYSTEM AND SEMICONDUCTOR PACKAGE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor system comprising a plurality of memory chips, wherein each of the memory chips comprises:
an oscillator suitable for generating a periodic wave in a self refresh mode;
a delay unit suitable for delaying the periodic wave to generate a refresh pulse and for setting a delay value based on a
corresponding chip identification; and

an arithmetic unit for receiving a preceding chip identification generated from an arithmetic unit of a preceding memory chip
to generate the corresponding chip identification, wherein the corresponding chip identification is generated by adding a
predetermined value to the received preceding chip identification.

US Pat. No. 9,274,881

SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A memory system, comprising:
a semiconductor memory device including a CAM data block for storing CAM data; and
a controller configured to control an operation of the semiconductor memory device in response to a CAM data program command
received from a host,

wherein, the semiconductor memory device is configured to sequentially perform a pre-program operation and an erase operation
of the CAM data block prior to performance of a CAM data program operation associated with the CAM data block.

US Pat. No. 9,270,275

LEVEL SHIFTER AND SERIALIZER HAVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A level shifter comprising:
a level shifting unit configured to change a swing voltage level of an input signal from a first swing voltage level to a
second swing voltage level based on a clock signal;

a precharge driving unit configured to precharge an output node of the level shifting unit based on the clock signal;
a leakage current prevention unit configured to switch a current path between the precharge driving unit and the output nodes
based on a voltage level of the output node; and

an output unit configured to latch a signal of the output node having the second swing voltage level to output as an output
signal.

US Pat. No. 9,263,448

SEMICONDUCTOR DEVICE WITH BURIED METAL LAYER

SK HYNIX INC., Icheon (K...

1. A semiconductor device comprising:
a peripheral region in a semiconductor substrate, the peripheral region including a first region, a second region, and a third
region;

first active regions formed in the first region and the second region, the first active regions defined by recesses provided
in device isolation films of the first region and the second region;

a second active region defined by the device isolation film and provided in the third region;
a buried metal layer buried in one or more of the recesses;
a first conductive layer of a first type formed over a first portion of the first active regions and a first portion of the
buried metal layer in the first region; and

a second conductive layer of a second type formed over a second portion of the first active regions and a second portion of
the buried metal layer in the second region, wherein the first type is different from the second type,

wherein one of the first conductive layer and the second conductive layer is further formed over the second active region
in the third region, and

wherein a top surface of the buried metal layer is substantially coplanar with top surfaces of the first active regions.

US Pat. No. 9,384,841

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM HAVING THE SAME AND OPERATING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor device, comprising:
memory blocks including a plurality of strings that include drain select transistors and memory cells electrically coupled
in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in
series between a common source line and the pipe transistor;

a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected
memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory
blocks and to ground a pipe line electrically coupled to the pipe transistor included in the unselected memory blocks when
a program operation of a selected memory block among the memory blocks is performed; and

a control circuit configured to control the circuit group.

US Pat. No. 9,270,256

DUTY CYCLE CORRECTION CIRCUIT

SK Hynix Inc., Gyeonggi-...

1. A duty cycle correction circuit comprising:
an error booster suitable for amplifying a duty error of an input clock;
a driver suitable for driving an output clock based on the input clock; and
a duty corrector suitable for correcting a duty of the output clock based on the duty error amplified by the error booster,
wherein the input clock includes an input clock signal and a complementary input clock signal, the amplified duty error includes
an amplified duty error signal and a complementary amplified duty error signal, and the output clock includes an output clock
signal and a complementary output clock signal, and

wherein the driver comprises:
a first differential comparison unit suitable for comparing the input clock signal with the complementary input clock signal,
driving the output clock signal to a high level when a level of the input clock signal is higher than a level of the complementary
input clock signal, and driving the output clock signal to a low level when the level of the complementary input clock signal
is higher than the level of the input clock signal; and

a second differential comparison unit suitable for comparing the input clock signal with the complementary input clock signal,
driving the complementary output clock signal to a low level when the level of the input clock signal is higher than the level
of the complementary input clock signal, and driving the complementary output clock signal to a high level when the level
of the complementary input clock signal is higher than the level of the input clock signal.

US Pat. No. 9,270,285

SEMICONDUCTOR CHIPS AND SEMICONDUCTOR SYSTEMS FOR EXECUTING A TEST MODE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor chip comprising:
a selection phase clock generator configured to receive an external clock signal and an inversed external clock signal to
generate phase clock signals, configured to receive a first external test clock signal and a second external test clock signal
in response to a reference voltage having a constant level to generate test phase clock signals, and configured to output
the phase clock signals or the test phase clock signals as selection phase clock signals in response to a test mode signal;
and

a data input/output portion configured to receive and output data in synchronization with the selection phase clock signals.

US Pat. No. 9,263,383

ANTI-FUSE ARRAY OF SEMICONDUCTOR DEVICE AND METHOD FOR OPERATING THE SAME

SK HYNIX INC., Icheon (K...

1. An anti-fuse array comprising:
a plurality of first transistors having a matrix structure over a semiconductor substrate, the plurality of first transistors
including a plurality of gate lines extending along a first direction, a plurality of channel lines extending along a second
direction, and a plurality of gate insulation film lines extending in the first direction to overlap portions of the plurality
of channel lines;

a plurality of second transistors respectively disposed adjacent to first ends of the plurality of gate lines; and
a plurality of third transistors respectively disposed at second ends of the plurality of channel lines.

US Pat. No. 9,275,716

CELL ARRAY AND MEMORY WITH STORED VALUE UPDATE

SK Hynix Inc., Gyeonggi-...

1. A memory comprising:
a first cell array configured to include a plurality of first memory cells connected to a plurality of word lines;
a second cell array configured to include a plurality of second memory cells, which are connected to the plurality of word
lines, wherein a group of the plurality of second memory cells, which are connected to a word line, stores a number of activations
for the word line;

a transfer signal generation unit configured to activate a first transfer signal in response to an active command or a refresh
command, and to activate a second transfer signal after the first transfer signal is activated and a predetemined time lapses;
and

a stored value update unit configured to receive and increase a value stored in the group of the plurality of second memory
cells connected to an activated word line among the plurality of word lines, in response to the first transfer signal, and
to transfer and update the increased value to the group of the plurality of second memory cells in response to the second
transfer signal.

US Pat. No. 9,275,718

SEMICONDUCTOR DEVICES WITH PERIODIC SIGNAL GENERATION CIRCUITS AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

14. A semiconductor system comprising:
a controller suitable for receiving a temperature signal including information on temperature variation to generate an auto-refresh
signal; and

a semiconductor device suitable for generating the temperature signal, controlling an amount of electric charges discharged
from an internal node according to the temperature variation to generate a periodic signal including pulses sequentially created,
and receiving the periodic signal or the auto-refresh signal to perform a refresh operation.

US Pat. No. 9,269,618

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

SK HYNIX INC., Icheon (K...

1. A method for manufacturing a semiconductor device, the method comprising:
forming a multi-width bit line having a lower portion with a width greater than a width of an upper portion over a semiconductor
substrate;

forming a barrier film over sidewalls of the multi-width bit line; and
forming a storage node contact plug by filling a gap between neighboring multi-width bit lines, the storage node contact plug
having an upper portion with a width that is greater than a width of a lower portion,

wherein the step of forming a multi-width bit line includes:
forming a bit line over the semiconductor substrate with vertical sidewalls;
forming an insulating film over the semiconductor substrate and sidewalls and an upper surface of the bit line; and
performing a partial etch-back process on the insulating film to form the multi-width bit line,
wherein a thickness of the insulating film formed over a sidewall of a lower portion of the bit line is greater than a thickness
of the insulating film formed over a sidewall of an upper portion of the bit line, the lower portion being closer to the semiconductor
substrate than the upper portion.

US Pat. No. 9,287,320

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a substrate comprising a plurality of transistors; and
a piezoelectric formed to be contacted with the substrate,
wherein the piezoelectric is formed expendably in a direction parallel to a gate direction of the transistors,
wherein the substrate comprises a semiconductor chip which a packaging process is completed,
wherein the piezoelectric has a larger size than the substrate.

US Pat. No. 9,276,464

VOLTAGE GENERATION CIRCUIT USING SINGLE AND DOUBLE REGULATION MODES

SK HYNIX INC., Icheon (K...

1. A voltage generation circuit comprising:
a first pumping unit configured to perform a first pumping operation using a power supply voltage inputted from an external
power source;

a second pumping unit configured to perform a second pumping operation using the power supply voltage; and
a voltage regulation unit configured to control the first and second pumping units to generate first and second pumping voltages,
respectively, and configured to output the first and second pumping voltages as a first target voltage and a second target
voltage, respectively, in the first mode, the voltage regulation unit configured to control the first pumping unit and the
second pumping unit to generate a reserve voltage and configured to generate the first target voltage and the second target
voltage by down-converting the reserve voltage in the second mode,

wherein the voltage regulation unit selectively operates according to one of the first mode and the second mode and outputs
the first and second target voltages through first and second output terminals, and

wherein in a third mode, the voltage regulation unit is configured to control the first pumping unit and the second pumping
unit to generate a third pumping voltage, output the third pumping voltage as the first target voltage, and generate the second
target voltage by down-converting the third pumping voltage.

US Pat. No. 9,275,743

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

18. A semiconductor memory device, comprising:
a cell string including a plurality of source select transistors electrically coupled to a common source line in series, at
least one drain select transistor electrically coupled to a bit line, and memory cells electrically coupled between the at
least one drain select transistor and the source select transistors; and

a peripheral circuit configured to control the cell string,
wherein the peripheral circuit is configured to program a second source select transistor electrically coupled to the common
source line through a first source select transistor, the peripheral circuit being configured to reprogram the second source
select transistor when a threshold voltage of the second source select transistor is less than a target voltage and configured
to end a program with respect to the second source select transistor when the threshold voltage of the second source select
transistor is greater than or equal to the target voltage, and

the peripheral circuit applies a program permission voltage to the bit line during the programming, turns on the at least
one drain select transistor and the memory cells and transmits the program permission voltage to the second source select
transistor, turns off the first source select transistor and electrically decouples the second source select transistor from
the common source line, and applies a program voltage to a gate of the second source select transistor and increases the threshold
voltage of the second source select transistor.

US Pat. No. 9,275,897

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SK HYNIX INC., Icheon (K...

1. A method for fabricating a semiconductor device, the method comprising:
forming a through silicon via in a semiconductor substrate doped with impurities of a first type;
implanting impurities of a second type into an upper layer of the semiconductor substrate disposed around upper sidewalls
of the through silicon via to form a first doped layer;

forming a second doped layer with impurities of the first type on an outer portion of the first doped layer;
forming an insulation film that covers the first doped layer and the through silicon via;
patterning a portion of the insulation film to expose the through silicon via; and
forming a bump on the through silicon via, wherein the through silicon via is separated from the insulation film.

US Pat. No. 9,261,557

SEMICONDUCTOR APPARATUS AND TEST DEVICE THEREFOR

SK Hynix Inc., Gyeonggi-...

1. A semiconductor apparatus comprising:
a clock enable signal buffer unit configured to receive an input clock enable signal, and generate an output clock enable
signal;

a buffer control unit configured to generate a buffer enable signal in response to the output clock enable signal and a test
enable signal;

an input/output buffer unit configured to receive input patterns and generate output patterns; and
a compression test unit configured to test the output patterns and the output clock enable signal according to the test enable
signal.

US Pat. No. 9,263,125

NONVOLATILE MEMORY APPARATUS, AND SEMICONDUCTOR SYSTEM AND COMPUTER DEVICE USING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A nonvolatile memory apparatus comprising:
a memory cell array including a plurality of sub arrays;
a plurality of analog-to-digital converters (ADCs) configured to sense sensing voltages outputted from memory cells of the
plurality of sub arrays; and

a path selection unit configured to electrically couple the plurality of sub arrays with the plurality of ADCs in one-to-one
correspondence in a first operation mode, and electrically couple the plurality of ADCs with a terminal of a power supply
voltage in a second operation mode,

wherein the plurality of ADCs monitor a noise of the power supply voltage when the plurality of ADCs are electrically coupled
with the terminal of the power supply voltage.

US Pat. No. 9,281,369

SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME

SK HYNIX INC., Icheon (K...

9. A method for manufacturing a semiconductor device, the method comprising:
forming a device isolation region defining an active region;
providing first and second gate electrode materials in the active region, the first gate electrode material being provided
below the second gate electrode material;

partially etching the second gate electrode material to form a gate electrode pattern and a first space, the first space exposing
the first gate electrode material;

removing the first gate electrode material to form a second space, wherein the second space is disposed under the first space
and the gate electrode pattern; and

forming a capping layer in the first space and the second space.

US Pat. No. 9,225,316

DUTY CYCLE CORRECTION CIRCUIT AND OPERATION METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. An operating method of a duty cycle correction circuit, the operating method comprising:
detecting a duty ratio of an clock signal;
assigning first and second bits into which first and second tracking types are incorporated among a plurality of bits forming
a duty control signal based on the duty ratio of the clock signal;

setting respective bits of the first bits; and
setting respective bits of the second bits,
wherein the duty ratio of the clock signal is adjusted in response to the duty control signal when a bit of the first or second
bits is set,

wherein the first tracking type comprises a successive approximation register (SAR) tracking type, and the second tracking
type comprises a linear tracking type.

US Pat. No. 9,279,855

SEMICONDUCTOR INTEGTRATED CIRCUIT INCLUDING TEST PADS

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit comprising:
a test input/output port including a plurality of test pads;
an internal input interface configured to generate an internal clock, an internal address, an internal command, internal data
and temporary storage data in response to external signals through the test input/output port; and
an error detection block configured to determine whether the internal data and the temporary storage data are the same with
each other, and output a determination result through one test pad of the test input/output port,
wherein the internal input interface includes a data input/output block which generates the internal data, and wherein the
data input/output block comprises:

a temporary storage part which stores the internal data as the temporary storage data;
a data output part which receives the temporary storage data; and
a data input part which receives an output of the data output part and outputs it as the internal data.

US Pat. No. 9,275,959

SEMICONDUCTOR PACKAGES HAVING EMI SHIELDING LAYERS, METHODS OF FABRICATING THE SAME, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME

SK HYNIX INC., Icheon (K...

1. A semiconductor package comprising:
a substrate including an insulation layer;
a first ground line including a first internal ground line disposed along edges of the substrate and a plurality of first
extended ground lines extending between the first internal ground line and sidewalls of the substrate, the first extended
ground lines including end portions that are exposed at the sidewalls of the substrate;

a second ground line including a second internal ground line disposed along the edges of the substrate and a plurality of
second extended ground lines extending between the second internal ground line and the sidewalls of the substrate, the plurality
of second extended ground lines including end portions that are exposed at the sidewalls of the substrate, and being spaced
apart from each other along the edges of the substrate by the insulation layer;

a chip on the substrate;
a molding member disposed on the substrate to cover the chip; and
an electromagnetic interference (EMI) shielding layer covering the molding member and extending along the sidewalls of the
substrate, the EMI shielding layer contacting the end portions of the plurality of first extended ground lines, and alternately
contacting the end portions of the plurality of second extended ground lines and exposed portions of the sidewalls of the
insulation layer along a circumference of the substrate.

US Pat. No. 9,263,368

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a substrate on which a plurality of contact regions are defined;
a plurality of transistors formed in the plurality of contact regions;
a support body formed over the plurality of transistors and including a top surface, portions of which have different heights
in the plurality of contact regions;

a plurality of stacked structures including a plurality of conductive layers stacked over the support body;
slits located between the plurality of stacked structures;
first lines coupled to first junctions of the plurality of transistors through the slits; and
second lines coupled to second junctions of the plurality of transistors through the slits.

US Pat. No. 9,263,148

SEMICONDUCTOR DEVICE WITH PASS/FAIL CIRCUIT

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a memory block including memory cells coupled to word lines; and
an operation circuit suitable for performing a program operation and a verify operation on memory cells coupled to a selected
word line,

wherein, when performing the program operation, the operation circuit applies a first program allowance voltage to a bit line
of a first program fail cell, to keep a program fail status, and a second program allowance voltage having a voltage level
different from the first program allowance voltage to a bit line of a second program fail cell, to change a program pass status
to a program fall status.

US Pat. No. 9,269,670

BONDING STRUCTURE OF SEMICONDUCTOR PACKAGE, METHOD FOR FABRICATING THE SAME, AND STACK-TYPE SEMICONDUCTOR PACKAGE

SK Hynix Inc., Gyeonggi-...

1. A bonding structure of a semiconductor package, comprising:
a substrate, having a front side and a back side;
a TSV through the substrate, the TSV being configured with conductive layer, wherein a surface of the TSV is exposed at the
front side of the substrate; and

a plurality of sub bonding pads configured to be electrically coupled to the exposed surface of the TSV in common, and
wherein the surfaces of the sub bonding pads are directly contacted to the exposed surface of the TSV.

US Pat. No. 9,287,163

METHOD FOR FORMING VOID-FREE POLYSILICON AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a semiconductor device, the method comprising:
forming a second layer over a first layer;
forming an open portion by etching the second layer;
forming a sacrificial layer on sidewalls of the second layer defining the open portion;
forming a polysilicon layer pattern in the open portion;
removing the sacrificial layer to form a gap between the polysilicon layer pattern and the second layer, wherein the gap exposes
sidewalls and a top surface of the polysilicon layer pattern; and

performing a thermal process to diffuse a seam in the polysilicon layer pattern to the exposed sidewalls and the top surface
of the polysilicon layer pattern after the removing the sacrificial layer,

wherein the thermal process is performed at a temperature range from 500° C. to 800° C. with a furnace annealing.

US Pat. No. 9,281,033

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a first internal command generator suitable for generating first internal command signals after decoding an external command
signals in response to an external control signal;

a column control signal generator suitable for generating a column control signal after decoding the external command signals
in response to the external control signal; and

a second internal command generator suitable for generating second internal command signals from the first internal command
signals in response to the column control signal.

US Pat. No. 9,275,920

SEMICONDUCTOR APPARATUS AND STACKED SEMICONDUCTOR APPARATUS FOR CHECKING FORMATION AND CONNECTION OF THROUGH SILICON VIA

SK Hynix Inc., Gyeonggi-...

1. A stacked semiconductor apparatus comprising:
a first chip having a first TSV connected between a first node and a second node;
a second chip having a second TSV connected between a third node and a fourth node; and
a connection unit configured to electrically connect the second node and the third node with each other,
wherein the first chip includes a first TSV test unit configured to check a capacitance value of the first TSV and generate
a first single test result in a single TSV test mode, and supply a power supply voltage to the first node in a stacked TSV
test mode, and

wherein the second chip includes a second TSV test unit configured to check a capacitance value of the second TSV and is generate
a second single test result in the single TSV test mode, and electrically connect the third node and a fifth node with each
other in the stacked TSV test mode.

US Pat. No. 9,275,937

SEMICONDUCTOR DEVICE WITH DAMASCENE BIT LINE AND METHOD FOR FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a substrate having a plurality of contact surfaces;
an interlayer dielectric layer formed over the substrate and having a first open portion which exposes a part of the contact
surfaces and a second open portion which has a line shape to expose the other contact surfaces and a first portion between
two adjacent contact surfaces among the other contact surfaces;

a storage node contact (SNC) plug filling the first open portion; and
a damascene structure filing the second open portion and comprising a bit line, a spacer formed on at least both sidewalls
of the bit line, and an air gap that is formed between the bit line and the spacer,

wherein uppermost portions of the other contact surfaces include a metal silicide,
the spacer is further formed under the bit line and the air gap in a region overlapping with the first portion, and
a bottom surface of the bit line directly contacts the metal silicide except for the region overlapping with the first portion.

US Pat. No. 9,275,687

SEMICONDUCTOR CHIPS

SK Hynix Inc., Gyeonggi-...

1. A semiconductor chip comprising:
a core region including a plurality of first memory cells; and
a first edge adjacent to a first side of the core region,
wherein the first edge includes a first region and a second region,
wherein the first region includes a plurality of second memory cells and the second region includes a first pad portion through
which at least one of an address signal, a command signal, a clock signal, a data signal and a control signal is inputted
or outputted,

wherein the first edge and the core region are sequentially arrayed in a first direction, and
wherein the first region and the second region are sequentially arrayed in a second direction.

US Pat. No. 9,275,984

MULTI-CHIP PACKAGE SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A multi-chip package comprising a plurality of semiconductor chips coupled to a through-silicon via (TSV) for transmitting
a predetermined signal,
wherein each of the semiconductor chips comprises:
a chip identification (ID) generator suitable for generating a chip ID of a corresponding semiconductor chip; and
a termination controller suitable for controlling a termination operation on the TSV in response to an output signal of the
chip ID generator.

US Pat. No. 9,275,736

SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a CAM block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor
substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each
of the plurality of word lines is electrically coupled to a plurality of CAM cells;

a peripheral circuit configured to program CAM cells selected from the plurality of CAM cells; and
a control circuit configured to control the peripheral circuit to simultaneously apply a program voltage to an nth word line, an n?1th word line and an n+1th word line to simultaneously program the CAM cells electrically coupled to the n?1th word line, the nth word line and the n+1th word line, wherein the n?1th word line and the n+1th are adjacent to the nth word line and the selected CAM cells are electrically coupled to the nth word line.

US Pat. No. 9,275,700

SEMICONDUCTOR DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read
data, and generating a DBI decision signal corresponding to a result of the decision;

an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision
is reflected, during a DBI operation mode;

a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized
read data and inverted signals of the synchronized read data, during the DBI operation mode; and

a data output unit suitable for receiving the synchronized read data, the inverted signals of the synchronized read data,
the arrangement control signal and an output control signal, and selectively outputting the synchronized read data and the
inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control
signal and the output control signal, during the DBI operation mode.

US Pat. No. 9,269,819

SEMICONDUCTOR DEVICE HAVING A GATE AND A CONDUCTIVE LINE IN A PILLAR PATTERN

SK HYNIX INC., Icheon-Si...

1. A semiconductor device comprising:
a plurality of pillar patterns, including first pillar patterns arranged along a first direction and second pillar patterns
arranged along a second direction, formed over a semiconductor substrate;

a gate extending in the first direction, arranged along sidewalls of the first pillar patterns, and coupling the first pillar
patterns;

a junction region disposed in an upper portion of the pillar patterns; and
a conductive line extending in the first direction and disposed directly on sidewalls of the first pillar patterns, the conductive
line provided in a region laterally adjacent to the junction region,

wherein a bottom surface of the conductive line is disposed above a top surface of the gate,
wherein the gate is not electrically coupled to the conductive line, and,
wherein the conductive line removes a hole formed in the first pillar patterns and the second pillar patterns.

US Pat. No. 9,269,667

SEMICONDUCTOR APPARATUS AND AN IMPROVED STRUCTURE FOR POWER LINES

SK Hynix Inc., Gyeonggi-...

1. A semiconductor apparatus comprising:
a first power line arranged in a first direction;
a second power line arranged to be parallel to the first power line;
a first power supply pad arranged between the first power line and the second power line to be directly connected to the first
power line,

wherein an entire portion of the first power supply pad is arranged between the first power line and the second power line;
and

a second power supply pad arranged between the first power line and the second power line and directly connected to the second
power line,

wherein an entire portion of the second power supply pad is arranged between the first power line and the second power line;
a first auxiliary power line arranged to be parallel to the first power line and electrically coupled with the first power
supply pad; and

a second auxiliary power line arranged to be parallel to the second power line and electrically coupled with the second power
supply pad,

wherein the first power supply pad and the second power supply pad are arranged in a line.

US Pat. No. 9,419,654

ENCODING DEVICE AND METHOD FOR GENERATING MESSAGE MATRIX

SK HYNIX INC., Icheon (K...

1. A method for generating a message matrix and encoding the message matrix, the message matrix comprising a plurality of
message blocks, the method comprising:
determining a plurality of row lengths of respective rows of the message matrix such that a length difference between any
of the plurality of row lengths is equal to or less than a critical point, each of the row lengths corresponding to the number
of all units included in a corresponding one of the rows of the message matrix;

determining a plurality of message block lengths of the respective message blocks such that a length difference between any
of the plurality of message block lengths is equal to or less than the critical point, each of the message block lengths corresponding
to the number of all units included in a corresponding one of the plurality of message blocks;

arranging the message blocks in each row of the message matrix such that a length difference between any of a plurality of
column lengths of respective columns of the message matrix is equal to or less than the critical point, each of the column
lengths corresponding to the number of all units included in a corresponding one of the columns of the message matrix;

encoding each row of the message matrix to generate a plurality of row parity blocks; and
encoding each column of the message matrix to generate a plurality of column parity blocks,
wherein the plurality of message blocks are arranged along the rows and the columns of the message matrix.

US Pat. No. 9,269,657

FLEXIBLE STACK PACKAGES, ELECTRONIC SYSTEMS INCLUDING THE SAME, AND MEMORY CARDS INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A flexible stack package comprising:
a first unit package and a second unit package which are sequentially stacked, each of the first and second unit packages
having a fixed area and a floating area;

a fixing part that connects and fixes each fixing portions of the fixed areas of the first and second unit packages,
wherein each of the first and second unit packages includes a lower flexible layer, an upper flexible layer on the lower flexible
layer, and a chip between the lower and upper flexible layers; and

a plurality of first contact protrusions that protrude from a bottom surface of the floating area of the first unit package
toward a top surface of the floating area of the second unit package,

wherein the plurality of first contact protrusions is configured to conduct force applied to the floating area of the first
unit package to the floating area of the second unit package,

wherein the plurality of first contact protrusions is fixed on the bottom surface and is not fixed with the top surface of
the floating area of the second unit package, and

wherein the plurality of first contact protrusions is capable of sliding along a surface of the upper flexible layer.

US Pat. No. 9,209,226

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A three-dimensional (3D) semiconductor device, comprising:
a semiconductor substrate;
a common source region formed on the semiconductor substrate and extending in a line shape;
an active region formed on the common source region and including a lateral channel region, which is substantially in parallel
to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region
to a direction substantially perpendicular to the surface of the semiconductor substrate; and

a gate formed in a space between the source region and the drain region.

US Pat. No. 9,223,694

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

SK HYNIX INC., Icheon (K...

1. A data storage device comprising:
a first memory device configured to store first data having a hot property;
a second memory device comprising a first block configured to store second data having a cold property and a second block
configured to store third data transferred from the first memory device, wherein the second data and the third data are stored
in different physical blocks of the second memory device; and

a request separator configured to classify data requested from outside into the first data having the hot property or the
second data having the cold property, wherein the request separator comprises:

a first selection circuit configured to classify the requested data into the first data having the hot property or fourth
data having the cold property according to a length of the requested data; and

a second selection circuit configured to reclassify the fourth data into fifth data having the hot property or the second
data having the cold property according to a number of requests for a logical address corresponding to the requested data,
the first data including the fifth data.

US Pat. No. 9,269,453

FUSE ARRAY

SK Hynix Inc., Gyeonggi-...

1. A fuse array comprising:
an E-fuse including an active region, a floating node and a contact node;
a plurality of gates overlapping the active region and separated from each other between the floating node and the contact
node; and

a plurality of fuse sets each comprising two or more E-fuses that share the floating node or the contact node.

US Pat. No. 9,888,567

FLEXIBLE DEVICE INCLUDING SLIDING INTERCONNECTION STRUCTURE

SK hynix Inc., Icheon-si...

1. A flexible device comprising:
a first conductive pattern including a first sliding contact portion and a first extension portion;
a second conductive pattern including a second sliding contact portion overlapping with the first sliding contact portion
and the second conductive pattern includes a second extension portion, the second sliding contact portion being in contact
with the first sliding contact portion and being movable on the first sliding contact portion for a sliding motion; and

a dielectric layer in which the first and second conductive patterns are embedded,
wherein the dielectric layer comprises:
a first dielectric layer disposed on the first conductive pattern; and
a second dielectric layer disposed on the second conductive pattern, and
wherein the first dielectric layer directly contacts the second dielectric layer.

US Pat. No. 9,257,202

SEMICONDUCTOR DEVICES

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a normal test signal generator suitable for generating a first enablement signal and a first pulse signal in response to an
external command signal when a first code signal and a second code signal have a predetermined logic combination and suitable
for decoding a first test address signal and a second test address signal to generate first to fourth normal test signals;
and

a termination signal generator suitable for receiving the first pulse signal during an enablement period of the first enablement
signal to generate a first termination signal which is enabled when a predetermined signal among the first to fourth normal
test signals is generated,

wherein the first termination signal is a signal, which is enabled to terminate a generation of the first to fourth normal
test signals.

US Pat. No. 9,136,376

SEMICONDUCTOR DEVICE HAVING JUNCTIONLESS VERTICAL GATE TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

SK HYNIX INC., Icheon (K...

1. A semiconductor device comprising:
a plurality of active pillars, each of the active pillars including a first impurity region disposed over a surface of a substrate,
a plurality of second impurity regions disposed over the first impurity region, and a plurality of third impurity regions
disposed over the plurality of second impurity regions, respectively, wherein the plurality of second impurity regions is
arranged at a constant interval over the first impurity region;

a gate electrode extending across each of the plurality of active pillars along a row of second impurity regions and disposed
over sidewalls of the second impurity regions in the row, wherein the sidewalls of the second impurity regions in the row
are each disposed between second impurity regions that are adjacent in a corresponding active pillar of the active pillars;
and

a bit line disposed between adjacent first impurity regions, disposed under the gate electrode, crossing the gate electrode,
and being in contact with one of the adjacent first impurity regions,

wherein the first, second, and third impurity regions comprise impurities of the same polarity.

US Pat. No. 9,312,004

DRIVER FOR SEMICONDUCTOR MEMORY AND SYSTEM INCLUDING THE SAME

SK HYNIX INC., Icheon (K...

1. A driver for a semiconductor memory, comprising:
a momentarily dropping voltage generation circuit configured to generate a momentarily dropping voltage using first data for
adjusting a height of an overdrive current that flows into a cell of a memory cell array and second data for adjusting a width
of the overdrive current;

a digital/analog (D/A) conversion circuit configured to output a first spike current that includes the overdrive current using
the momentarily dropping voltage;

a cell voltage detection circuit configured to compare a cell voltage to a predetermined reference voltage, and to output
a comparison signal representing the comparison result, the cell voltage being generated based on a second spike current that
flows into a cell of a test cell array;

a calibration controller configured to calibrate the height and width of the overdrive current using the comparison signal
output from the cell voltage detection unit; and

a calibration table storage configured to store the first data for adjusting the height of the overdrive current and the second
data for adjusting the width of the overdrive current,

wherein the test cell array is arranged to correspond to the memory cell array.

US Pat. No. 9,196,365

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

14. A method comprising:
precharging channels of a string, wherein the string comprises a drain select transistor, a source select transistor, a first
drain side dummy memory cell, a second drain side dummy memory cell, a first source side dummy memory cell, a second source
side dummy memory cell, and a plurality of memory cells,

wherein a semiconductor memory device comprises the string;
applying a turn-off voltage to the first drain side dummy memory cell and the first source side dummy memory cell;
generating a gate-induced drain leakage;
applying a pass voltage to the second drain side dummy memory cell while the first drain side dummy memory cell is in a turn-off
state and to the second source side dummy memory cell while the first source side dummy memory cell is in the turn-off state;

increasing threshold voltages of the second drain side dummy memory cell and the second source side dummy memory cell; and
applying a program voltage to a selected memory cell from among the plurality of memory cells.

US Pat. No. 9,443,569

DRIVER FOR A SEMICONDUCTOR MEMORY AND METHOD THEREOF

SK Hynix Inc., Icheon (K...

1. A driver for semiconductor memory, comprising:
a storage unit configured to match and store a memory cell address and bucket charge current data corresponding to the memory
cell address;

a selection controller configured to receive the memory cell address and target charge current data, and output a bucket charge
current select signal and a target charge current select signal corresponding to the bucket charge current data and the target
charge current data, respectively, by referring to the storage unit;

a current supply unit configured to supply a bucket charge current and a target charge current in response to the bucket charge
current select signal and the target charge current select signal, respectively; and

a bucket charge current setting unit configured to set the bucket charge current data stored in the storage unit with respect
to each memory cell address.

US Pat. No. 9,214,631

RESISTIVE RAM, METHOD FOR FABRICATING THE SAME, AND METHOD FOR DRIVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a resistive random access memory (ReRAM), comprising:
forming a non-stoichiometric phase change layer over a first electrode;
forming a second electrode over the phase change layer; and
applying a voltage to the first and second electrodes, modifying the phase change layer into a threshold switching layer for
a switching operation, and oxidizing a part of the second electrode to form a resistance change layer.

US Pat. No. 9,337,849

PHASE DETECTOR, PHASE-FREQUENCY DETECTOR, AND DIGITAL PHASE LOCKED LOOP

SK HYNIX INC., Icheon (K...

1. A phase detector comprising:
a phase comparing circuit configured to detect and output a phase difference between a first clock signal and a second clock
signal;

a latch circuit configured to latch an output signal of the phase comparing circuit and output a phase detection signal; and
an initial voltage control circuit configured to variably control an initial voltage of an input terminal of the latch circuit
by performing a voltage determining operation based on a control signal.

US Pat. No. 9,312,305

PHASE-CHANGE MEMORY DEVICE HAVING MULTIPLE DIODES

SK Hynix Inc., Gyeonggi-...

1. A phase-change memory device, comprising:
a semiconductor substrate;
a metal word line formed on the semiconductor substrate;
a polysilicon layer of a first conductivity type being in contact with an upper portion of the metal word line; and
an auxiliary diode layer formed laterally and directly adjacent to outer sidewalls of the polysilicon layer to be in electrical
contact with the metal word line and having a second conductivity type opposite to the first conductivity type.

US Pat. No. 9,208,869

RESISTIVE RAM, METHOD FOR FABRICATING THE SAME, AND METHOD FOR DRIVING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for driving a resistive random access memory (ReRAM) which includes a first electrode, a threshold switching layer
of stoichiometric transition oxide formed over the first electrode, a resistance change layer of a non-stoichiometric transition
metal oxide formed over the threshold switching layer, and a second electrode formed over the resistance change layer, the
method comprising;
applying a first voltage to turn on the threshold switching layer and to change the resistance change layer from a high resistance
state to a low resistance state;

turning off the threshold switching layer by reducing the first voltage;
applying a second voltage having an opposite polarity of the first voltage to turn on the threshold switching layer and to
change the resistance change layer from a low resistance state to a high resistance state; and

turning off the threshold switching layer by reducing the second voltage.

US Pat. No. 9,530,464

SEMICONDUCTOR APPARATUS AND DATA BIT INVERSION

SK HYNIX INC., Icheon-Si...

17. A semiconductor apparatus comprising:
a first semiconductor chip;
a second semiconductor chip stacked over the first semiconductor chip and configured to transmit and receive signals from
the first semiconductor chip through one or more vias;

a serializer/deserializer configured to deserialize data inputted in series or serialize data transmitted in parallel from
the second semiconductor chip; and

a data bit inversion logic coupled to the serializer/deserializer and configured to perform a data inversion operation on
the data deserialized through the serializer/deserializer in response to a data bit inversion signal,

wherein the first semiconductor chip comprises:
a pad unit configured to input/output data and the data bit inversion signal;
a first transmission/reception block configured to transmit/receive signals to/from the pad unit; and
a second transmission/reception block configured to transmit/receive signals between the second semiconductor chip and the
first transmission/reception block.

US Pat. No. 9,287,289

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method of manufacturing a semiconductor device, comprising:
forming a gate insulating layer on a substrate;
forming a gate line over the gate insulating layer, wherein the gate line includes a first conductive layer and one or more
second conductive pattern layers which are formed in the first conductive layer; and

forming a third conductive layer over the first conductive layer in which the second conductive pattern layer is formed,
wherein the first conductive layer and the third conductive layer include the same type of impurities or different types of
impurities.

US Pat. No. 9,269,719

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

13. A semiconductor device comprising:
source-side memory cells stacked along a first source-side channel layer;
drain-side memory cells stacked along a first drain-side channel layer; and
a conductive layer configured to connect the first source-side channel layer and the first drain-side channel layer;
a source-side transistor connected between the source-side memory cells and the conductive layer; and
a drain-side transistor connected between the drain-side memory cells and the conductive layer.

US Pat. No. 9,269,413

SEMICONDUCTOR DEVICE HAVING TRANSISTOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a pulse voltage generator configured to generate a pulse voltage; and
a transistor including a gate,
wherein the pulse voltage swings between first and second voltages having a first frequency and a second frequency, respectively,
in response to operation modes of the semiconductor device,

wherein the pulse voltage generator applies the pulse voltage to the gate so that the transistor is in an off-state or an
on-state,

wherein the pulse voltage generator generates the pulse voltage to have the first frequency when a precharge command is given,
and

wherein the pulse voltage generator generates the pulse voltage having the second frequency lower than the first frequency
when an active command is given.

US Pat. No. 9,576,974

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

SK HYNIX INC., Icheon-si...

1. A method of manufacturing a semiconductor device, the method comprising:
forming on a lower structure, a first stack structure in which first material layers and second material layers are alternately
stacked;

forming, on the first stack structure, a second stack structure in which third material layers and fourth material layers
are alternately stacked;

forming preliminary holes penetrating the second stack structure;
forming a fifth material layer covering the preliminary holes on the second stack structure to define a first air-gap inside
the preliminary holes; and

forming through holes connected to the preliminary holes by penetrating from the fifth material layer overlapping the preliminary
holes to the first stack structure.

US Pat. No. 9,356,000

SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR SYSTEM WITH THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit comprising:
a plurality of semiconductor chips configured to be stacked in three dimensions;
a first group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be
used for a density extension and a bandwidth extension of the semiconductor integrated circuit; and

a second group of through-chip vias configured to go through the plurality of semiconductor chips, respectively, and to be
used for the bandwidth extension of the semiconductor integrated circuit,

wherein each of the plurality of semiconductor chips includes
a path selection unit configured to select one of the first group of through-chip vias arranged in the semiconductor chip
or one of the second group of through-chip vias arranged in the semiconductor chip in response to a mode switching signal
activated for the density extension or the bandwidth extension, and

an internal circuit configured to be selectively coupled to a through-chip via selected by the path selection unit.

US Pat. No. 9,335,369

SEMICONDUCTOR INTEGRATED CIRCUIT

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit comprising:
a test bump pad coupled to a test through-silicon-via (TSV);
a first bump pad coupled to a second TSV;
a second bump pad coupled to a first TSV;
a latching unit, coupled between the test bump pad and the first bump pad, suitable for storing data; and
a switching unit suitable for selectively coupling the first bump pad to the second bump pad in response to a test operation
control signal,

wherein the first bump pad is disposed closer than the second bump pad to the test bump pad, and the first TSV is disposed
closer than the second TSV to the test TSV.

US Pat. No. 9,311,257

SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM AND METHOD OF OPERATING THE SAME

SK hynix Inc., Icheon-si...

19. A method of operating a semiconductor memory device, the method comprising:
receiving a multichip select command;
receiving an operation request in response to the multichip select command;
receiving an operation confirm signal instructing to perform an operation according to the operation request; and
performing the operation according to the operation request in response to the operation confirm signal.

US Pat. No. 9,082,718

FINE PATTERN STRUCTURES HAVING BLOCK CO-POLYMER MATERIALS

SK HYNIX INC., Icheon (K...

1. A method of fabricating a fine pattern structure, the method comprising:
providing a layer of alternating protrusion portions and recess portions;
forming polymer patterns in recess regions formed in the recess portions;
forming brush patterns on top surfaces of the protrusion portions;
forming first polymer block patterns on the brush patterns and second polymer block patterns on the polymer patterns; and
removing the second polymer block patterns and the polymer patterns.

US Pat. No. 9,455,230

SEMICONDUCTOR PACKAGES AND METHODS OF FABRICATING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor package comprising:
a semiconductor chip electrically connected to a substrate; and
a molding part disposed on the substrate and the semiconductor chip, and including first molding members and second molding
members arranged in an alternating pattern,

wherein the first molding members have a first physical flexibility and the second molding members have a second physical
flexibility, the first physical flexibility being different from the second physical flexibility.

US Pat. No. 9,263,596

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which
the channel layer extends;

a tunnel insulating layer surrounding the channel layer;
first charge storage patterns surrounding the tunnel insulating layer formed in the depressions;
blocking insulation patterns surrounding the first charge storage patterns formed in the depressions, wherein the blocking
insulating patterns include connecting portions coupled to the tunnel insulating layer; and

second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.

US Pat. No. 9,236,501

DUMMY BIT LINE MOS CAPACITOR AND DEVICE USING THE SAME

SK HYNIX INC., Icheon (K...

1. A metal oxide semiconductor (MOS) capacitor, comprising:
a gate buried in a semiconductor substrate;
a first dielectric layer disposed between the gate and the semiconductor substrate;
a first contact coupled to the semiconductor substrate at a first side of the gate;
a second dielectric layer disposed on the semiconductor substrate at a second side of the gate; and
a second contact disposed on the second dielectric layer and coupled to a dummy bit line in an outermost cell block of a cell
array,

wherein the second dielectric layer prevents direct electrical conduction between the second contact and the semiconductor
substrate, and

wherein the second contact is electrically insulated from the gate.

US Pat. No. 9,191,184

TRANSMITTER, RECEIVER AND SYSTEM INCLUDING THE SAME

SK HYNIX INC., Icheon (K...

1. A transmitter comprising:
an aligner configured to align a phase of an input clock signal and a phase of a data signal and output an aligned clock signal
and an aligned data signal; and

a transmission circuit configured to generate a transmission signal,
wherein a phase of the transmission signal is controlled according to the aligned clock signal and an amplitude of the transmission
signal is controlled according to the aligned data signal, and

wherein the transmission circuit comprises:
a first driver configured to generate the transmission signal using the aligned clock signal; and
a second driver configured to control the amplitude of the transmission signal according to the aligned data signal.

US Pat. No. 9,865,345

ELECTRONIC DEVICE INCLUDING A SEMICONDUCTOR MEMORY HAVING MEMORY ARRAYS WITH VARIABLE RESISTANCE STORAGE ELEMENTS AND A BIAS VOLTAGE GENERATOR ARRANGED BETWEEN THE ARRAYS

SK hynix Inc., Gyeonggi-...

1. An electronic device including a semiconductor memory unit, wherein the semiconductor memory unit comprises:
a first circuit area including a plurality of first storage cells, each having a variable resistance element and being selected
when a corresponding word line is activated, a first reference resistance element having a first resistance value, and a first
read control unit for reading data of a storage cell selected among the plurality of first storage cells based on a bias voltage;

a second circuit area including a plurality of second storage cells, each having a variable resistance element and being selected
when a corresponding word line is activated, a second reference resistance element having a second resistance value, and a
second read control unit for reading data of a storage cell selected among the plurality of second storage cells based on
the bias voltage, the second circuit area being arranged spaced apart from the first circuit area; and

a third circuit area arranged between the first circuit area and the second circuit area, wherein the third circuit area includes
a word line driving unit for driving a plurality of word lines, and a bias voltage generation unit for generating the bias
voltage based on currents flowing through the first reference resistance element and the second reference resistance element,

wherein the first reference resistance element and the second reference resistance element are arranged adjacent to the third
circuit area.

US Pat. No. 9,530,484

SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

SK HYNIX INC., Icheon-Si...

1. A semiconductor apparatus comprising:
a plurality of unit memory blocks;
a plurality of sense amplifier arrays configured to be shared with two or more unit memory blocks among the plurality of unit
memory blocks and amplify data of the unit memory blocks;

a refresh counter configured to generate a refresh address, and fix a value of the refresh address according to an activation
of a refresh control signal; and

a refresh control circuit configured to store the refresh address, execute a normal operation command on the unit memory block
corresponding to an external address, and activate the refresh control signal, in response to a unit memory block corresponding
to the external address and a unit memory block corresponding to a refresh address among the plurality of unit memory blocks
being coupled in common to one of the plurality of sense amplifier arrays.

US Pat. No. 9,490,853

DATA TRANSMITTER

SK HYNIX INC., Icheon (K...

1. A data transmitter comprising:
a transmitter circuit configured to be coupled to a receiver through a channel, the transmitter circuit configured to provide
to the channel an output signal based on an input signal, and adjust an output impedance value according to a bias signal;
and

a calibration controller configured to adjust the bias signal by comparing the output signal of the transmitter circuit to
a reference signal during a calibration operation,

wherein the transmitter circuit is configured to keep the output impedance value substantially unchanged after the calibration
operation is performed, and the transmitter circuit comprises a plurality of switching elements coupled in parallel to each
other and a switching circuit, and

wherein the plurality of switching elements are configured to adjust a magnitude of the output signal according to the bias
signal and the switching circuit is configured to adjust the output signal according to the input signal.

US Pat. No. 9,312,479

VARIABLE RESISTANCE MEMORY DEVICE

SK HYNIX INC., Icheon (K...

1. A variable resistance memory device comprising:
a first electrode;
a second electrode spaced apart from the first electrode;
a resistance variable layer and a metal-insulator transition layer provided between the first electrode and the second electrode;
and a heat barrier layer provided between the first electrode and the metal-insulator transition layer, between the metal-insulator
transition layer and the resistance variable layer, or between the second electrode and the metal-insulator transition layer,

wherein the heat barrier layer includes an insulating material having a thickness that allows electron tunneling.

US Pat. No. 9,263,883

SEMICONDUCTOR INTEGRATED CIRCUIT

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit comprising:
a first power line configured to receive a first voltage;
a second power line configured to receive a second voltage which is lower than the first voltage;
a first clamping unit configured to be connected to the first power line;
a second clamping unit configured to be connected between the first clamping unit and the second power line; and
a discharging unit configured to, when an abnormal voltage introduced through the first power line or the second power line
is applied, discharge the abnormal voltage by coupling with the first clamping unit or the second clamping unit,

wherein the first clamping unit and the second clamping unit are configured with the same type of MOS transistors, and
wherein the discharging unit is configured with a type of transistor which is opposite to the type of the transistors for
the first and second clamping units.

US Pat. No. 9,098,389

MEMORY SYSTEM AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A memory system, comprising:
a memory device configured to comprise a plurality of memory dies having different page sizes; and
a memory controller configured to generate a plurality of chip selection signals for activating the plurality of memory dies
based on a reordering number of requests received from a processor,

wherein the memory controller activates a memory die having a larger page size, from among the plurality of memory dies, as
the reordering number is greater than a threshold and activates a memory die having a smaller page size, from among the plurality
of memory dies, as the reordering number is smaller than the threshold.

US Pat. No. 9,373,369

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A data storage device comprising:
a nonvolatile memory apparatus including a plurality of memory areas; and
a controller suitable for randomizing write data and generating random write data based on an offset value of a target memory
area of the memory areas and a flag corresponding to the target memory area,

wherein the controller sets the flag based on a number of times an erase operation is performed on the target memory area.

US Pat. No. 9,318,576

METHOD OF MANUFACTURING THREE-DIMENSIONAL SEMICONDUCTOR DEVICE AND VARIABLE RESISTIVE MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A method of manufacturing a three-dimensional (3D) semiconductor device, the method comprising:
forming a source on a semiconductor substrate;
sequentially forming a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer, on the source;
patterning the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer to form an active
pillar;

oxidizing an outer circumference of the active pillar to form a gate insulating layer; and
forming a gate on an outer circumference of the gate insulating layer,
wherein the second semiconductor layer is formed of a material having a higher oxidation rate than those of the first semiconductor
layer and the third semiconductor layer.

US Pat. No. 9,312,872

SIGNAL CONVERTER

SK Hynix Inc., Gyeonggi-...

1. A signal converter comprising:
a clock generation unit suitable for generating a counting clock signal having a given period value;
a signal dividing unit suitable for dividing an input signal having time information by a preset division value correlated
with the given period value; and

a counting unit suitable for generating a counting value by counting an output signal of the signal dividing unit in response
to the counting clock signal.

US Pat. No. 9,312,190

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK HYNIX INC., Icheon (K...

1. A method of manufacturing a semiconductor device, comprising:
forming a first TiN layer in a PMOS of a substrate;
forming an Al thin film over the first TiN layer in the PMOS region and in a NMOS region of the substrate;
forming a second TiN layer over the Al thin film;
forming each of a first and a second TiAlN layers in the NMOS region and the PMOS region by annealing the substrate on which
the second TiN layer is formed; and

forming a first metal gate electrode in the NMOS region and a second metal gate electrode in the PMOS region by patterning
the first and the second TiAlN layers,

wherein the first TiAlN layer and the second TiAiN layer have a different composition.

US Pat. No. 9,280,415

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SYSTEM AND CONTROL METHOD OF SEMICONDUCTOR DEVICE

SK Hynix Inc., Gyeonngi-...

1. A semiconductor device comprising:
a mode register set suitable for generating internal control signals including a first internal control signal and a second
internal control signal;

a per-DRAM addressability (PDA) driving unit suitable for resetting the mode register set in response to the first internal
control signal and an input value of data inputted through a data pad; and

a cycle redundancy check (CRC) driving unit suitable for performing a CRC operation by checking whether or not data are correctly
inputted through the data pad without an error in response to the first internal control signal and the second internal control
signal.

US Pat. No. 9,263,101

SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:
first and second memory regions suitable for storing data in a mirrored fashion with respect to each other during a high speed
operation period; and

a read operation block suitable for alternately selecting the first and second memory regions and reading data from a selected
memory region, when the first or second memory region is repeatedly selected in read operations performed two or more times
during the high speed operation period.

US Pat. No. 9,355,695

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF TESTING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device comprising:
a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding
to an active command, during a test operation of the active command;

a column input section suitable for receiving a second row signal including a second row address corresponding to the active
command during the test operation of the active command; and

a signal control section suitable for generating an internal row signal for an operation of the active command by transforming
the first row signal and the second row signal outputted from the row input section and the column input section.

US Pat. No. 9,318,201

SEMICONDUCTOR MEMORY DEVICE INCLUDING THREE-DIMENSIONAL ARRAY STRUCTURE

SK hynix Inc., Icheon-si...

1. A semiconductor memory device including normal memory cells stacked over a substrate, the semiconductor memory device comprising:
source selection transistors coupled to a common source line;
source side dummy memory cells coupled between the source selection transistors and the normal memory cells;
drain selection transistors coupled to a bit line; and
drain side dummy memory cells coupled between the drain selection transistors and the normal memory cells,
wherein a number of the source side dummy memory cells is less than a number of the drain side dummy memory cells, and
wherein a number of the drain selection transistors is greater than a number of the source selection transistors.

US Pat. No. 9,269,421

SEMICONDUCTOR MEMORY AND METHOD FOR OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory comprising:
a storage unit suitable for storing a minimum operation interval between row command operations;
a detection unit suitable for detecting whether row command signals inputted for the row command operations are activated
at the minimum operation interval;

a latching unit suitable for generating flag signals by latching the row command signals; and
a shifting unit suitable for shifting the flag signals based on the minimum operation interval in response to an output signal
of the detection unit, and generating internal row command signals.

US Pat. No. 9,208,843

INTERNAL ADDRESS GENERATION CIRCUITS

SK Hynix Inc., Gyeonggi-...

1. An internal address generation circuit, the circuit comprising:
an aging detector suitable for generating an aging signal enabled when the number of times that an internal command signal
for accessing memory cells is inputted is equal to or more than a reference number; and

an address decoder suitable for decoding an address signal in response to the aging signal to generate an internal address
signal, wherein the internal address signal includes a first internal address signal and a second internal address signal,
wherein when the aging signal is disabled, the address decoder decodes the address signal having a first level combination
to generate the first internal address signal enabled and decodes the address signal having a second level combination to
generate the second internal address signal enabled, and wherein when the aging signal is enabled, the address decoder decodes
the address signal having the first level combination to generate the second internal address signal enabled and decodes the
address signal having the second level combination to generate the first internal address signal enabled.

US Pat. No. 9,576,973

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
stack structures including interlayer insulating patterns and conductive line patterns, which are alternately stacked;
a first slit between the stack structures;
string pillars passing through the stack structures; and
dummy holes passing through top portions of the stack structures to be spaced apart from bottom surface of the stack structures
and disposed between the string pillars,

wherein each of the dummy holes is filled with a filling material different from materials of structures of the string pillars,
and

wherein each of the conductive line patterns includes:
a first conductive pattern formed in a line pattern area between two interlayer insulating patterns, which are arranged adjacent
to each other in the vertical direction, and formed along surfaces of the interlayer insulating patterns and the string pillars;

a second conductive pattern provided in the line pattern area and provided over the first conductive pattern; and
a non-conductive pattern provided in the line pattern area, provided between each of the string pillars and the first conductive
pattern, and surrounded by the first conductive pattern.

US Pat. No. 9,269,443

SEMICONDUCTOR DEVICE AND PROGRAM FAIL CELLS

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device, comprising:
a memory block including even memory cells configured to form an even physical page and odd memory cells configured to form
an odd physical page; and

an operation circuit configured to perform a program operation on the even memory cells and the odd memory cells, a first
verify operation for separately verifying the even memory cells and the odd memory cells, and a second verify operation for
simultaneously verifying the even memory cells and the odd memory cells,

wherein the operation circuit is configured to selectively perform the first verify operation and the second verify operation
depending on a number of adjacent program fail cells, among a plurality of program fail cells, in response to a verify result
value.

US Pat. No. 9,111,797

3-D NONVOLATILE MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A three-dimensional (3-D) nonvolatile memory device, comprising:
a support protruded from a surface of a substrate and configured to have an inclined sidewall;
channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked
over the substrate including the support, wherein each of the channel structures comprises a cell region where the channel
layers are horizontally stacked and a contact region where the channel layers are bent upward along the inclined sidewall
of the support and each of the channel layers are exposed;

select lines formed over the contact region of the channel structures; and
a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines,
wherein the support has a trapezoidal shape and widths of the channel layers exposed on the top surface of the channel structures
are determined by an inclined angle of the support.

US Pat. No. 9,048,139

METHOD FOR FABRICATING NON-VOLATILE MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a non-volatile memory device, comprising:
forming a pass gate electrode layer surrounding a sacrificial layer pattern on a substrate;
alternately stacking a plurality of inter-layer dielectric layers and a plurality of sacrificial layers over the pass gate
electrode layer;

forming at least a pair of channel holes that exposes the sacrificial layer pattern by selectively etching the inter-layer
dielectric layers and the sacrificial layers;

removing the sacrificial layer pattern to form at least a sub-channel hole coupling the pair of the channel holes;
forming a protective layer on sidewalls of the sacrificial layers that are exposed through the channel holes;
sequentially forming a memory layer and a channel layer on the internal walls of the channel holes and the sub-channel hole;
forming slit holes that penetrate through the inter-layer dielectric layers and the sacrificial layers on the both sides of
the channel holes;

removing the sacrificial layers that are exposed through the slit holes;
removing the protective layer; and
forming gate electrodes in space from which the sacrificial layers and the protective layer are removed.

US Pat. No. 9,374,071

SEMICONDUCTOR APPARATUS

SK hynix Inc., Icheon-si...

1. A delay circuit of a semiconductor apparatus, comprising:
a control signal generation block configured to output a control signal having an analog voltage level in response to an input
signal; and

an input/output block configured to delay the input signal by a delay amount based on the analog voltage level of the control
signal, and output a resultant signal,

wherein the control signal generation block comprises:
a voltage supply unit configured to supply an internal voltage to a first node;
a pull-down driving unit configured to pull-down drive a second node;
a first variable resistor and a first transistor electrically coupled between the first and the second nodes in series, a
gate of the first transistor receiving a reference voltage; and

a second variable resistor and a second transistor electrically coupled between the first and the second nodes in series,
a gate of the second transistor receiving the input signal; and

wherein the control signal is output from a third node between the second variable resistor and the second transistor.

US Pat. No. 9,368,167

SEMICONDUCTOR APPARATUS AND TESTING METHOD THEREOF

SK hynix Inc., Icheon-si...

1. A semiconductor apparatus having a through via to be electrically coupled with a chip, comprising:
a latch memory cell configured to be electrically coupled with the through via and receive a signal transmitted through the
through via when a wafer test signal and a write enable signal are enabled, to output a stored signal to the through via when
the wafer test signal and a read enable signal are enabled, and to be continuously coupled with the through via and latch
the signal transmitted through the through via when a stack enable signal is enabled;

wherein the latch memory cell is located in the base chip, and the base chip does not have a memory cell array for storing
data;

wherein the wafer test signal is enabled and the stack enable signal is disable when the base chip is not stacked with another
chip, and the wafer test signal is disable and the stacked enable signal is enabled when the base chip is stacked with another
chip.

US Pat. No. 9,355,729

NON-VOLATILE MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A non-volatile memory device, comprising:
a floating gate having a plurality of fingers extended in a first direction;
a first coupling unit including an active control gate formed below the floating gate;
a second coupling unit including a plurality of line type control plugs extended in the first direction and formed between
the plurality of fingers; and

a control unit which electrically connects the active control gate to the line type control plugs and controls a bias to be
applied to the active control gate.

US Pat. No. 9,330,768

SEMICONDUCTOR MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME AND OPERATING METHOD THEREOF

SK hynix Inc., Icheon-si...

19. An operating method of a semiconductor memory device, comprising:
applying program voltages to selected memory cells, and performing a program operation using an ISPP method to perform a program
verification operation;

controlling a potential level of a bit line of set memory cells among the selected memory cells when the program operation
using the ISPP method ends; and

performing an additional program operation to apply set program voltages to the set memory cells,
wherein the set program voltages are program voltages applied when a threshold voltage of a majority of the memory cells is
increased to a target threshold voltage from among a plurality of program voltages used in the program operation using the
ISPP method and the set memory cells are memory cells verified from program fail to program pass when the program operation
using the ISPP method is performed and the program voltages having the same potential levels as the set program voltages are
applied.

US Pat. No. 9,202,540

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:
an active state detector suitable for detecting whether or not a predetermined time passes after a moment when a normal active
command or an additional active pulse is activated in an active state detection mode, and generating an additional precharge
pulse based on a detection result;

a column controller suitable for generating the additional active pulse based on the additional precharge pulse, a column
address, and an external column command in the active state detection mode; and

a core region suitable for being activated based on the normal active command or an additional active command corresponding
to the additional active pulse, and being precharged based on an additional precharge command corresponding to the additional
precharge pulse or a normal precharge command.

US Pat. No. 9,530,735

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
stepped stack structures each including first to nth conductive patterns sequentially stacked with exposed ends, the stepped
stack structures being separated by slits and arranged along a first direction to constitute a memory block, wherein the n
is a natural number;

first connecting lines disposed on the stepped stack structures, and spaced apart from one another along the first direction,
while extending along a second direction intersecting the first direction, wherein one ends of the first connecting lines
further protrude in the second direction as the first connecting lines get further away from first stepped stacked structures
at outermost portions of the memory block; and

contact pads extending along the first direction from the one ends of the first connecting lines to overlap the first stepped
stack structures.

US Pat. No. 9,368,645

NONVOLATILE MEMORY DEVICE AND METHOD OF FABRICATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method of fabricating a nonvolatile memory device, comprising:
forming a conductive layer for a gate electrode comprising at least one or more sacrificial layer patterns over a substrate;
forming a pipe connection gate electrode by selectively etching the conductive layer; and
forming etch stop layers including metal silicide over the pipe connection gate electrode other than some regions over the
sacrificial layer patterns,

wherein forming the etch stop layers comprises:
forming a hard mask pattern covering parts of the pipe connection gate electrode; and
siliciding the exposed pipe connection gate electrode.

US Pat. No. 9,230,668

SEMICONDUCTOR MEMORY APPARATUS

SK Hynix Inc., Gyeonggi-...

8. A semiconductor memory apparatus comprising:
a latch unit configured to be driven in response to the activation of a reset selection signal and resetting a first node
and a second node; and

a first auxiliary driving unit configured to connect the first node to a ground voltage and to receive the reset selection
signal and a selected one of a voltage of the second node and an inverted voltage of a voltage at the first node as input
signals, in response to the reset selection signal and the selected voltage; and

a second auxiliary driving unit configured to connect the second node to the ground voltage and to receive the reset selection
signal and a selected one of a voltage of the first node or an inverted voltage of a voltage at the second node as input signals,
in response to the reset selection signal and the selected voltage,

wherein the first node and the second node have opposite voltage logic levels.

US Pat. No. 9,129,664

INTERNAL VOLTAGE GENERATING CIRCUIT CAPABLE OF CONTROLLING SWING WIDTH OF DETECTION SIGNAL IN SEMICONDUCTOR MEMORY APPARATUS

SK HYNIX INC., Gyeonggi-...

1. An internal voltage generating circuit of a semiconductor memory apparatus comprising:
a comparison unit configured to generate a preliminary detection signal by comparing an internal voltage with a reference
voltage;

an A/D converting unit configured to generate a code based on the internal voltage;
a code voltage generating unit configured to output a code voltage corresponding to the code;
a code detection unit configured to generate a control signal which is enabled when a value of the code is lower than a predetermined
code value;

a control-voltage-level controlling unit configured to output a control voltage which is at a ground voltage level when the
control signal is enabled and to output the control voltage corresponding to the code voltage when the control signal is disabled;

a driving unit configured to output a detection signal by receiving an external voltage and the control voltage as driving
voltages and then driving the preliminary detection signal; and

an internal voltage level control unit configured to increase the internal voltage as a voltage level of the detection signal
is lowered.

US Pat. No. 9,530,742

SEMICONDUCTOR DEVICE WITH STRUCTURAL STABILITY

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a stack including alternately stacked conductive layers and insulating layers;
supports passing through the stack, each of the supports having a cross-section of an equilateral polygon or a circular shape,
the supports being equidistantly arranged in a first direction and a second direction, the first and second directions crossing
each other; and

contact plugs coupled respectively to the conductive layers, each of the contact plugs being disposed between at least two
adjacent supports of the supports.

US Pat. No. 9,318,497

NONVOLATILE MEMORY DEVICES HAVING SINGLE-LAYERED FLOATING GATES

SK Hynix Inc., Gyeonggi-...

1. A nonvolatile memory device comprising:
a first junction protruding from a surface of a substrate;
a second junction disposed in the substrate and spaced apart from the first junction; and
a floating gate overlapping a sidewall surface of the first junction to overlap a first impurity region in the sidewall surface
of the first junction and extending to the second junction,

wherein the floating gate extends over a portion of a top surface of the first junction.

US Pat. No. 9,450,574

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

SK hynix Inc., Icheon-si...

1. A semiconductor system comprising:
a first semiconductor device including an offset signal generation circuit configured to compare at least one sensing code
and a temperature code and generate an input offset signal; and

a second semiconductor device including a temperature code generation circuit configured to be inputted with the input offset
signal, compare a reference voltage controlled according to the input offset signal and a temperature signal, and generate
the temperature code, wherein the sensing code is generated by sensing an internal temperature of the first semiconductor
device, and

wherein the first semiconductor device further comprises:
a first temperature sensor configured to sense a temperature in a first region and to generate a first sensing code; and
a second temperature sensor configured to sense a temperature in a second region and to generate a second sensing code.

US Pat. No. 9,373,420

SEMICONDUCTOR TEST DEVICE

SK HYNIX INC., Icheon (K...

1. A semiconductor test device comprising:
a pre-driver suitable for outputting a first output signal by driving first output data in response to a rising clock and
a falling clock;

a data generator suitable for generating second output data in response to the rising clock and the falling clock;
an internal pre-driver suitable for driving the second output data in response to the rising clock and the falling clock and
outputting a second output signal;

a data comparator suitable for outputting a comparison signal by comparing the first output signal to the second output signal;
a data accumulator suitable for accumulating the comparison signal in response to the rising clock and the falling clock;
and

an output driver suitable for driving an output signal of the data accumulator during a test mode.

US Pat. No. 9,355,902

METHOD OF FABRICATING SEMICONDUCTOR APPARATUS WITH THROUGH-SILICON VIA AND METHOD OF FABRICATING STACK PACKAGE INCLUDING THE SEMICONDUCTOR CHIP

SK HYNIX INC., Icheon-Si...

1. A method of fabricating a semiconductor apparatus, comprising the steps of:
forming a first semiconductor chip including a first through-silicon via, the first though-silicon via being protruded beyond
heights of the first semiconductor chip;

forming a first insulating layer having a first bump on the first semiconductor chip, wherein the first bump includes a first
portion with a first line width and a second portion with a second line width being wider than the first line width, and the
first through-silicon via is electrically contacted with the first portion of the bump;

forming a second semiconductor chip including a second through-silicon via, the second though-silicon via being protruded
beyond heights of the second semiconductor chip; and

stacking the first semiconductor chip and the second semiconductor chip using a conductive connection member such that an
upper surface of the conductive connection member is contacted to the second portion of the first bump and a bottom surface
of the conductive connection member is contacted to a protruding portion of the second through-silicon via,

wherein a diameter of the protruding portion is smaller than that of the conductive connection member.

US Pat. No. 9,318,176

SEMICONDUCTOR INTEGRATED CIRCUIT

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit, comprising:
a clock pulse generating circuit suitable for outputting a command enable clock pulse when a predetermined command is input
during a predetermined command-masking period;

a command interface circuit suitable for outputting an internal command signal based on the command enable clock pulse and
the command; and

a target operating circuit suitable for performing an operation corresponding to the command based on the internal command
signal.

US Pat. No. 9,274,539

VOLTAGE TRIMMING CIRCUIT AND METHOD OF SEMICONDUCTOR APPARATUS

SK Hynix Inc., Gyeonggi-...

1. A voltage trimming circuit of a semiconductor apparatus, comprising:
a first voltage trimming unit configured to trim a first reference voltage having a first characteristic with respect to temperature
based on a first trimming signal, and generate a first trimming reference voltage;

a second voltage trimming unit configured to trim a second reference voltage having a second characteristic with respect to
the temperature based on a second trimming signal, and generate a second trimming reference voltage; and

an adjusting unit configured to trim a plurality of third divided voltages formed from a potential difference between the
first and second trimming reference voltages, and output a third divided voltage selected from the plurality of third divided
voltages as a final trimming reference voltage in response to a select signal,

wherein the first and second trimming signals are set in such a manner that the first and second trimming reference voltages
having a first level are generated at a first temperature,

the select signal is set in such a manner that the final trimming reference voltage is generated with a target level at a
second temperature,

the adjusting unit is configured to output the final trimming reference voltage having a slope of a line connecting the first
level and the target level, and

the plurality of third divided voltages comprise a first divided voltage group having at least one third divided voltage dependent
on a difference between the first trimming reference voltage and a third divided voltage applied to a first node, a second
divided voltage group having at least one third divided voltage dependent on a difference between the second trimming reference
voltage and a third divided voltage applied to a second node, and a third divided voltage group having at least one third
divided voltage dependent on a potential difference between the first node and the second node.

US Pat. No. 10,019,199

CONTROLLER COUPLED TO SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A controller for controlling a semiconductor memory device, the controller comprising:a command generation unit configured to generate commands to be performed by the semiconductor memory device;
a command queue configured to store the commands and provide at least one command among the stored commands to the semiconductor memory device; and
a command removal unit configured to remove the at least one command and related commands of the at least one command from the command queue if the semiconductor memory device fails in the performance of the at least one command,
wherein the at least one command and the related commands constitute operation commands, the operation commands being used to perform a single operation, and
wherein a command constituting other operation commands different from the operation commands is not removed.

US Pat. No. 9,576,965

SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME

SK HYNIX INC., Icheon (K...

1. A method for forming a semiconductor device, the method comprising:
forming first and second bit lines spaced apart from each other by a first distance over a semiconductor substrate;
forming first and second supporting films spaced apart from each other by a second distance in a direction perpendicular to
the first and second bit lines;

forming a first storage node contact and a second storage node contact between the first supporting film and the second supporting
film, after forming the first and second supporting films, so that the first and second storage node contacts are supported
by the first and second supporting films; and

etching upper portions of the second storage node contact and the first and second supporting films in a diagonal direction
across the first and second bit lines at the same time.

US Pat. No. 9,287,169

METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING BURIED BIT LINES

SK Hynix Inc., Gyeonggi-...

1. A method for fabricating a semiconductor device, comprising:
forming a pair of body lines that is separated by a trench;
etching both sidewalls of a lower portion of the trench and forming recessed sidewalls that face each other;
forming a barrier layer containing germanium, on the recessed sidewalls; and
forming a pair of separated buried bit lines including a metal silicide, in the trench.

US Pat. No. 9,190,139

MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A memory comprising:
a plurality of word lines;
one or more redundancy word lines suitable for replacing one or more word lines among the plurality of word lines;
a target address generation unit suitable for generating one or more target addresses using a stored address; and
a control unit suitable for sequentially refreshing the plurality of word lines in response to a refresh command which is
periodically inputted, refreshing a word line selected based on the target address when the refresh command is inputted M
times, and refreshing the one or more redundancy word lines whenever the refresh command is inputted N times, wherein the
M and N are natural numbers.

US Pat. No. 9,208,867

ELECTRONIC DEVICE AND METHOD FOR FABRICATING THE SAME

SK hynix Inc., Icheon-Si...

1. An electronic device including a semiconductor memory, wherein the semiconductor memory includes:
a substrate including a plurality of active regions which are defined by isolation layers extending in a first direction and
word lines extending in a second direction intersecting the first direction;

source line contacts disposed over every other of the active regions arranged in the first and second directions and disposed
over each of the active regions arranged in a third direction intersecting the first and second directions;

source lines extending in the third direction and being coupled to the source line contacts;
contacts disposed over the active regions over which the source line contacts are not disposed;
variable resistance elements disposed over and coupled to the contacts, respectively;
bit line contacts disposed over and coupled to the variable resistance elements, respectively; and
bit lines extending in a fourth direction intersecting the first to third directions and be coupled to the bit line contacts.

US Pat. No. 9,418,008

ELECTRONIC DEVICE WITH VARIABLE RESISTIVE PATTERNS

SK HYNIX INC., Icheon (K...

1. An electronic device comprising a semiconductor memory unit, wherein the semiconductor memory unit comprises:
a plurality of first lines extending in a first direction;
a plurality of second lines extending in a second direction intersecting the first direction; and
a plurality of variable resistance patterns positioned at intersections of the first lines and the second lines and disposed
between the first lines and the second lines in a direction that is perpendicular to the first and second directions,

wherein each of the variable resistance patterns has an elongated shape in a plan view and a portion of each of the variable
resistance patterns extends outside a region in which a corresponding first line and a corresponding second line overlap with
each other,

wherein each of the variable resistance patterns overlaps with each of the intersections of the first lines and the second
lines so that there is a one-to-one correspondence between the variable resistance patterns and the intersections of the first
lines and the second lines, and

wherein, in a direction of a major axis of each of the variable resistance patterns, two adjacent variable resistance patterns
are spaced apart from each other.

US Pat. No. 9,373,390

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF PROGRAMMING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A method for operating a semiconductor memory device includes a plurality of memory cells configured to have a single program
state among first through Nth program states, wherein each one of the first through Nth program states is respectively determined
based on threshold voltages of the plurality of memory cells, the method comprising:
applying a program pulse to a selected word line connected to the plurality of memory cells;
performing a pre-verification to verify program states of the plurality of memory cells using a pre-verify voltage; and
performing, if a result of the pre-verification is determined to have passed, a main-verification to verify the program states
of the plurality of memory cells using a main-verify voltage,

wherein the pre-verify voltage of (k)th program state among the first through Nth program states has a same voltage level
with the main verify voltage of (k?2)th program state,

wherein N is a positive integer, and
wherein k is a positive integer.

US Pat. No. 9,336,854

SEMICONDUCTOR MEMORY APPARATUS

SK hynix Inc., Icheon-si...

1. A semiconductor memory apparatus comprising:
an active control portion configured to generate a preliminary bank active signal and a single bank refresh signal in response
to a command, a refresh control signal, and a bank active signal; and

a signal combination portion configured to enable the bank active signal when either the preliminary bank active signal or
the single bank refresh signal is enabled.

US Pat. No. 9,231,610

SAR ANALOG-TO-DIGITAL CONVERTING APPARATUS AND OPERATING METHOD THEREOF AND CMOS IMAGE SENSOR INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A Successive Approximation Register (SAR) analog-to-digital converting apparatus, comprising:
a reference voltage supply unit suitable for supplying different reference voltages depending on bits of a pixel output signal
to be converted;

an N bit SAR analog-to-digital conversion unit suitable for sequentially converting upper N?1 bits and lower N bits of the
pixel output signal by selectively using the reference voltages supplied from the reference voltage supply unit, where N is
a natural number; and

an error correction unit suitable for calculating an error correction value based on a difference between conversion results
of the lower N bits, and outputting a 2N?2 bit analog-to-digital conversion result by combining converted upper N?1 bits and
converted lower N bits and correcting an error of the reference voltages using the error correction value in the combining.

US Pat. No. 9,214,956

SEMICONDUCTOR DEVICE, MULTICHIP PACKAGE AND SEMICONDUCTOR SYSTEM USING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
an error detection unit suitable for receiving data and a cyclic redundancy check (CRC) code, and for outputting a detection
signal by detecting a transmission error of the data, wherein the detection signal is a signal for detecting an error, which
occurs in a data transmission; and

a signal change unit suitable for generating error information based on the detection signal while changing the error information
based on a signal transmission environment of the data.

US Pat. No. 9,190,123

SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor system comprising:
a controller suitable for generating command signal and an address signal;
a semiconductor device suitable for electrically disconnecting a first local line from a second local line in response to
an input control signal enabled in a read mode,

wherein the semiconductor device suitable for electrically connecting the first local line and the second local line in response
to the input control signal disabled in a write mode;

further wherein the read mode is set in accordance with a logic combination of the command signal; and
further wherein the semiconductor device suitable for sensing and amplifying a data on the first local line or the second
local line in accordance with the address signal to output the amplified data through an input/output line.

US Pat. No. 9,148,057

SEMICONDUCTOR APPARATUS

SK Hynix Inc., Gyeonggi-...

1. A semiconductor apparatus comprising:
a first structural body including a first temperature voltage generation unit configured to generate a first temperature voltage
and a second temperature voltage which have different voltage level variations according to a temperature variation, in response
to a temperature measurement command, and a first temperature information determination unit configured to generate first
temperature information depending on a difference between levels of the first and second temperature voltages; and

a second structural body including a second temperature voltage generation unit configured to generate a third temperature
voltage and a fourth temperature voltage which have different voltage level variations according to a temperature variation,
when a predetermined time elapses after the first and second temperature voltages are generated from the first structural
body, and a second temperature information determination unit configured to generate second temperature information depending
on a difference between levels of the third and fourth temperature voltages,

wherein the first temperature voltage generation unit generates a preliminary output control pulse when the temperature measurement
command is inputted, and transfers an output control pulse which is acquired by synchronizing the preliminary output control
pulse with a clock, to the second structural body through a through via.

US Pat. No. 9,076,550

TEST CIRCUIT FOR TESTING REFRESH CIRCUITRY OF A SEMICONDUCTOR MEMORY DEVICE

SK Hynix Inc., Gyeonggi-...

1. A test circuit of a semiconductor apparatus comprising:
a test temperature information generation section configured to output test temperature information having a plurality of
bits in a test operation mode, and to irregularly change logic values of the plurality of bits and transition time points
of the logic values regardless of a temperature of the semiconductor apparatus, wherein the test temperature information is
not dependent on the temperature of the semiconductor apparatus;

an erroneous operation prevention unit configured to generate a temperature compensation signal in response to the test temperature
information; and

a refresh cycle adjustment unit configured to change a cycle of a reference refresh signal in response to the temperature
compensation signal, and to generate a refresh signal.

US Pat. No. 9,214,216

SEMICONDUCTOR DEVICE AND OPERATION METHOD THEREOF

SK Hynix Inc., Gyeonggi-...

1. A semiconductor device comprising:
a plurality of memory cell blocks;
a counting unit suitable for counting the number of active operations on each of the memory cell blocks, based on an active
command and a row address; and

a refresh control unit suitable for determining a target memory cell block among the memory cell blocks and controlling an
additional refresh operation for the target memory cell block to be performed based on the counting result,

wherein the refresh control unit controls a normal refresh operation to be sequentially performed on the memory cell blocks
during a normal refresh mode, and controls the additional refresh operation to be performed on the target memory cell block,
and

wherein the additional refresh operation is performed on all rows of the target cell block.

US Pat. No. 9,153,593

NONVOLATILE MEMORY DEVICE HAVING SINGLE-LAYER GATE, METHOD OF OPERATING THE SAME, AND MEMORY CELL ARRAY THEREOF

SK Hynix Inc., Gyeonggi-...

1. A nonvolatile memory device comprising:
a single-layer gate;
a first area including a first well region, a first contact region arranged in the first well region, and source and drain
regions arranged at both sides of the single-layer gate in the first well region; and

a second area including a second well region, a second contact region arranged to overlap a part of the single-layer gate
in the second well region, and a third contact region arranged in the second well region,

wherein the first and second well regions and the first and third contact regions have a first conductivity while the second
contact region and the source and drain regions have a second conductivity.

US Pat. No. 9,064,554

DATA INPUT/OUTPUT CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A data input/output circuit comprising:
a precharge voltage supply unit configured to supply a precharge voltage driven by a first internal voltage in a standby state,
and supply the precharge voltage driven by a second internal voltage in response to a first and second control signals when
an active operation is performed; and

a precharge unit configured to receive the precharge voltage, precharge a first input/output line and a first inverted input/output
line to a level of the first internal voltage in the standby state, and precharge the first input/output line and the first
inverted input/output line by the second internal voltage when the active operation is performed, wherein the first control
signal is disabled during a period in which the active operation and a read operation are performed, and the second control
signal is enabled during the period in which the read operation is performed.

US Pat. No. 10,430,297

DATA STORAGE DEVICE AND OPERATING METHOD THEREOF

SK hynix Inc., Gyeonggi-...

1. A method for operating a data storage device which includes a nonvolatile memory device including a plurality of memory blocks, the method comprising: generating a valid page count table including a number of valid pages of each of closed blocks among the plurality of memory blocks in which data are written in ail pages thereof and the number of valid pages of at least one open block among the plurality of so memory blocks in which data is written in a part of pages thereof; generating a valid page scan table including a scan pointer for scanning the number of valid pages of the open block; and backing up the valid page count table and the valid page scan table in a meta block among the plurality of memory blocks.

US Pat. No. 9,298,558

MEMORY AND MEMORY MODULE INCLUDING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A memory unit, comprising:
a first data transferring/receiving unit suitable for transferring/receiving data through a first data bus for communication
with a host;

a second data transferring/receiving unit suitable for transferring/receiving data through a second data bus for a data backup;
a control unit suitable for controlling the first data transferring/receiving unit and the second data transferring/receiving
unit to be activated or inactivated according to whether a power failure occurs;

a cell array;
an internal data bus electrically coupled to the cell array; and
a selection unit suitable for allowing the internal data bus to transfer data to and from one of the first and second data
transferring/receiving units.

US Pat. No. 9,124,826

IMAGE SENSING DEVICE AND METHOD FOR OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. An image sensing device comprising:
first and second common column lines, each coupled to a plurality of unit pixels;
a column binning unit suitable for performing a column binning on a plurality of unit pixel signals, which are sequentially
outputted from the first and second column lines, in a basis of rows in a binning mode; and

a row binning unit suitable for performing a row binning on a plurality of column binning signals outputted from the column
binning unit in the binning mode,

wherein the first common column line is commonly coupled to first and second column lines, and the second common column line
is commonly coupled to third and fourth column lines.

US Pat. No. 9,324,400

SEMICONDUCTOR MEMORY DEVICE AND SEMICONDUCTOR MEMORY SYSTEM

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device having an open bit line structure, comprising:
a unit memory bank having a plurality of memory cell mats, which shares a local data line, and divided by a row address; and
at least one dummy cell mat disposed between the plurality of memory cell mats,
wherein the dummy cell mat comprises reference bit lines corresponding to reference bit lines of the plurality of memory cell
mats disposed adjacent to the dummy cell mat,

wherein the reference bit lines of the dummy cell mat corresponding to the reference bit lines of the plurality of memory
cell mats are disposed to be isolated from each other.

US Pat. No. 9,269,414

SEMICONDUCTOR INTEGRATED CIRCUIT

SK Hynix Inc., Gyeonggi-...

1. A semiconductor integrated circuit comprising a plurality of semiconductor chips, wherein each of the plurality of semiconductor
chips comprises:
a chip selection unit suitable for generating an internal chip selection signal in response to one or more selective chip
selection signals;

a selective setting unit suitable for generating a selective internal signal in response to the internal chip selection signal
and a setting signal inputted from an outside of the semiconductor integrated circuit; and

a common setting unit suitable for generating a common internal signal in response to the setting signal and a common chip
selection signal inputted from the outside,

wherein the common internal signals are activated in common and selective internal signals are selectively activated in the
semiconductor chips.

US Pat. No. 9,875,777

SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME

SK Hynix Inc., Gyeonggi-...

1. A semiconductor memory device, comprising:
an enable signal generation portion configured to generate a data output enable signal started to be activated to a first
logic level from a predetermined first moment corresponding to column address strobe (CAS) latency based on a read command;

a strobe signal generation portion configured to generate a data strobe signal which has a preamble section until the data
output enable signal is activated to the first logic level from a predetermined second moment corresponding to a predetermined
clock cycle of a source clock ahead of the first moment based on the read command and toggles based on the source clock during
an activated section of the data output enable signal;

a data output portion configured to output internal data in synchronization with the data strobe signal during the activated
section of the data output enable signal: and

a read signal generation portion configured to generate a read signal which is activated to a second logic level at the second
moment and deactivated to the first logic level at the first moment based on the read command, wherein the data output enable
signal is activated at the first moment when one clock cycle of the source clock passes after the read signal is activated,
wherein the first logic level is opposite to the second logic level.