1. A method for producing an image sensor comprising an array of pixels that includes vertical charge-coupled device (VCCD)
shift registers that extend along a direction of charge transfer, the method comprising:
forming gate electrodes over the VCCD shift registers extending in a direction transverse to the direction of charge transfer;
and

forming a physical gap in the gate electrodes physically separating and electrically isolating a first section of gate electrodes
and a second section of gate electrodes, the physical gap extending along the direction of charge transfer.

1. A method for controlling a light-emitting element comprising:
adjusting a conduction angle of an AC voltage to generate an adjusted AC voltage;
rectifying the adjusted AC voltage to generate a rectified voltage;
generating a current in response to the rectified voltage;
adjusting the current to be intermittent using a switch so that current flow is on or off;
regenerating energy stored in a choke coil in response to the current flow being off; and
controlling the switch with a clock signal from a clock circuit whose period is varied, wherein the clock signal is input
to a counter to generate a count signal used to vary the period of the clock signal, wherein the clock circuit includes the
counter, and wherein the counter changes a counter value in response to the clock signal and a reference voltage selector
unit selects one of a plurality of terminal voltages as a reference voltage based on a counter value of the counter by varying
a period of the clock signal generated from the clock.

1. A method of manufacturing a circuit device, comprising the steps of:
providing a substrate having a pad formed thereon, the pad having an upper surface;
forming a plurality of portions of a first solder on the upper surface of the pad, the portions of the plurality of portions
of the first solder being spaced away from each other so that they can maintain a discretized state even after they are melted,
and wherein the portions of first solder are arranged as an array of elements laterally positioned in rows and columns on
the upper surface of the pad; and

heating the plurality of portions of the first solder to melt the portions of the plurality of portions of the first solder,
wherein each portion of the plurality of portions of the first solder maintains a discretized state after melting, and wherein
each portion of the plurality of portions of the first solder comprises an alloy portion having a first thickness formed vertically
between a corresponding portion of the pad and a solder portion;

applying a second solder to the upper surface of the pad and the plurality of solder portions;
mounting a component to the second solder; and
heating the second solder and the discretized portions of the plurality of portions of the first solder to form an alloy layer,
wherein heating the second solder increases the thickness of the alloy portions between the corresponding portions of the
pad and the solder portions to a second thickness and creates another alloy portion laterally between the plurality of solder
portions, the another alloy portion having a third thickness, the third thickness less than the second thickness.

14. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device having an array of optical cavity image pixels, wherein each optical cavity image pixel comprises:
a photosensitive element formed in a substrate;
a reflective cavity that at least partially surrounds the photosensitive element, wherein the reflective cavity comprises
a frontside reflector, a backside reflector, and a plurality of vertical sidewall reflectors;

a light-guide trench that guides image light into the reflective cavity, wherein at least a portion of the backside reflector
is interposed between the photosensitive element and the light-guide trench; and

dielectric material on a first side of the substrate, wherein the backside reflector is formed in the dielectric material
between the photosensitive element and the light-guide trench.

1. A process of forming an electronic device comprising:
providing a substrate and a semiconductor layer overlying the substrate, wherein the semiconductor layer has a primary surface
and an opposite surface, wherein the substrate is closer to the opposite surface than the primary surface;

removing portions of the semiconductor layer to define a first trench, wherein the first trench lies within a termination
region of the electronic device;

forming a first insulating layer to fill the first trench to form a first insulating region within the termination region,
wherein the first insulating region extends a depth into the semiconductor layer, wherein the depth is less than 50% of the
thickness of the semiconductor layer;

forming a vertical region in the termination region, the vertical region extending a depth greater than the first trench,
wherein in a finished device, the first insulating region is disposed between the vertical region and an electronic component
region;

forming a doped region immediately adjacent to the first trench, wherein a peak doping concentration of the doped region is
in a range of 0.5 to 1.5 orders of magnitude higher than the semiconductor layer; and

forming a field electrode over the first insulating region.

1. An adaptive MOS gate driver circuit comprising:
a gate control circuit configured to form a drive signal to drive a gate of an MOS transistor;
a variable frequency oscillator configured to form a clock signal and to adjust a frequency of the clock signal responsively
to a difference between a Vgs of the MOS transistor and a first threshold value;

a charge pump circuit configured to provide an output voltage and an output current to the gate control circuit wherein a
value of the output current varies proportionally to variations of the frequency of the clock signal; and

the gate control circuit configured to couple the output current from the charge pump circuit to the gate of the MOS transistor
responsively to the Vgs of the MOS transistor having a value greater than a second threshold value and to provide a current
from a selectively enabled current source of the gate control circuit responsively to the Vgs of the MOS transistor having
a value no greater than the second threshold value.

1. A method of forming a direct bonded copper (DBC) substrate for a power electronic, comprising:
coupling a first surface of a ceramic layer to a second surface of a metallic baseplate, the ceramic layer having a second
surface opposing the first surface;

coupling a first surface of a copper layer with the second surface of the ceramic layer, the first surface of the copper layer
having a pattern comprising a first thickness and a second thickness greater than the first thickness, the first thickness
and the second thickness both measured perpendicularly to the first surface of the ceramic layer; and

forming traces in the copper layer by etching through the copper layer at the first thickness and etching through the copper
layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses are
measured perpendicularly to the first surface of the ceramic layer.

1. A method of operating an image sensor having pixels, comprising:
detecting a first trigger control signal transition;
resetting and integrating the pixels after a first duration of time from the first trigger control signal transition;
in response to detecting the first trigger control signal transition, commencing read out from the pixels after a second duration
of time from the first trigger control signal transition that is greater than zero;

and detecting and responding to a second trigger control signal transition that is subsequent to the first trigger control
signal transition while reading out from the pixels, wherein the image sensor finishes reading out from at least some of the
pixels before detecting the second trigger control signal transition, and wherein there are no additional trigger control
signal transitions in between the detected first and second trigger control signal transitions.

1. A method for detecting connection of a type of charger, comprising: receiving a first reset signal from a processing unit
in response to starting a control unit of an input-output circuit and receiving a power supply signal from an internal power
supply, wherein the input output circuit comprises: a power supply detection circuit coupled to the control unit; a charger
detection circuit coupled to the control unit, wherein the control unit comprises: an I2CI/F circuit having a first input, a first output, and a second output; and a logic gate having a first input, a second input,
a third input, and an output, the first input of the logic gate coupled to the first input of the I2CI/F circuit; and wherein the charger redetection register includes a first input, a second input, a third input, and an output,
wherein the first input of the charger redetection circuit is coupled to the first input of the I2CI/F circuit and to the first input of the logic gate, the second input of the charger redetection circuit is coupled to the
first output of the I2CI/F circuit, and the third input of the charger redetection circuit is coupled to the second output of the I2CI/F circuit; setting the charger redetection register coupled to the control unit in response to receiving the first reset
signal; detecting power supplied to a connector from an external source; performing a first charger kind detection process
which includes monitoring a voltage of a first terminal and a voltage of a second terminal of the connector in response to
the detected power supplied to the connector from the external source to detect an open, a pull up, and a pull down of at
least one of the first terminal and the second terminal; generating a first comparison result in response to comparing the
voltage of the first terminal with a first reference voltage; generating a second comparison result in response to comparing
the voltage of the second terminal with a second reference voltage; generating a third comparison result in response comparing
the voltage of the second terminal with a third reference voltage; and determining the first charger kind in accordance with
the first comparison result, the second comparison result, and the third comparison result; resetting a charger redetection
register within a control unit in response to the internal power supply; and starting a second charger kind detection process
in response to detection of the power.

1. A CMOS image sensor pixel array that includes at least one pixel circuit, comprising:
at least one concentric dual gate Bulk Charge Modulated Device (BCMD) transistor coupled to a single photodiode, wherein the
at least one concentric dual gate BCMD transistor is operable to store charge transferred from the photodiode for all the
pixels of the array simultaneously, wherein the stored charge is accumulated in at least one integration time, wherein the
at least one concentric dual gate BCMD comprises an inner ring gate and an outer ring gate, and wherein the outer ring gate
completely surrounds the inner ring gate; and

peripheral circuitry, wherein the at least one concentric dual gate BCMD transistors are additionally operable to be subsequently
addressed and scanned in a row by row manner.

1. A power supply circuit for generating an internal power supply voltage from a first power supply capable of supplying a
first power supply voltage if connected to a first power supply terminal and a second power supply capable of supplying a
second power supply voltage, which is lower than the first power supply voltage, if connected to a second power supply terminal,
the first power supply and the second power supply being separate from each other, the power supply circuit comprising:
a first transistor provided between the first power supply terminal and an output node;
a second transistor provided between the second power supply terminal and the output node;
a first supply unit having an input for receiving a voltage representative of a voltage of the first power supply terminal
and configured to continuously supply an inverted value of the input to a gate input of said first transistor; and

a second supply unit configured to continuously supply the voltage representative of the voltage of the first power supply
to a gate input of said second transistor.

1. An LED control circuit comprising:
a control circuit configured to form a drive signal to control LED current through a plurality of LED strings;
an input to receive a sense signal that is representative of the LED current through the plurality of LED strings;
an error detector circuit configured to use the sense signal to detect the LED current being less than a desired value for
a first time period; and

the LED control circuit configured to inhibit the LED current responsively to the error detector circuit detecting the LED
current being less than the desired value for the first time period.

1. A method for driving a light emitting diode with a driver circuit, comprising:
operating the driver circuit in a calibration phase in response to the light emitting diode emitting light at a first level,
wherein operating the driver circuit in the calibration phase includes:

providing a comparator having first and second inputs and an output, the second input coupled to a first node and the output
coupled to the first node;

providing a voltage follower circuit having first, second, and third terminals, the first terminal coupled for receiving an
input signal from a first digital-to-analog converter circuit, the second terminal coupled to the first node, and the third
terminal coupled to a second node;

providing a reference voltage at the first input of the comparator;
generating a first voltage at the second input of the comparator in response to a first current that flows from the first
node and a second current that flows towards the first node, the second current having first and second components; and

changing a level of the second current in response to the first voltage being more than or less than the reference voltage
at the first input of the comparator; and

operating the driver circuit in an active phase in response to the light emitting diode emitting light at a second level,
the second level greater than the first level, wherein operating the driver circuit in the active phase includes:

generating a third current that flows through the light emitting diode towards the first node.

1. A method of forming an electronic device comprising:
providing a wafer having a plurality of die formed as part of the wafer and separated by spaces, wherein the wafer has first
and second opposing major surfaces;

placing the wafer onto a carrier substrate;
singulating the wafer through the spaces to form singulation lines exposing side surfaces of the die; and
forming an insulating layer on the side surfaces,
wherein singulating the wafer and forming the insulating layer are done in one apparatus, and wherein the insulating layer
is formed at least in part while singulating the wafer.

1. A semiconductor package structure comprising:
a substrate having at least one conductive plane layer, a plurality of conductive traces on a first major surface, a plurality
of solder pads on an opposing second major surface, and a plurality of conductive solder bumps coupled to the plurality of
solder pads, wherein the plurality of solder pads are electrically coupled with the plurality of conductive traces by a plurality
of conductive vias extending vertically from the first major surface to the second major surface, wherein at least one of
the plurality of conductive solder bumps is laterally spaced apart from one of the plurality of conductive vias, and wherein
the at least one conductive plane layer includes a recess overlapping all of the solder pad having at least one of the plurality
of conductive solder bumps laterally spaced apart from one of the plurality of conductive vias;

a semiconductor device attached to the substrate; and
a package body covering at least the semiconductor device.

1. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device, comprising:
a device substrate having a first side and a second side;
a plurality of semiconductor components located on the first side of the device substrate;
a carrier substrate having a first side mounted to the first side of the device substrate and having alignment marks on a
second side; and

at least one component on the second side of the device substrate, wherein the at least one component is formed in alignment
with the semiconductor components located on the first side of the device substrate and the alignment marks on the second
side of the carrier substrate.

16. A monolithically integrated common mode filter and protection device configured as a chip scale package, comprising:
a semiconductor material having a resistivity of at least 5 Ohm-centimeters;
a protection device formed from the semiconductor material;
a first layer of material over the semiconductor material, the first layer of the first material having an opening filled
with a first electrically conductive material, wherein the first layer of material is a photosensitive material; and

a first coil over the first layer of material.

1. A circuit device, comprising:
a circuit board having a periphery region that is configured to accept a case material that forms a frame-shape, the circuit
board having a central region that is distal from the periphery region;

a semiconductor element disposed on an upper surface of the circuit board;
a first lead electrically connected to the semiconductor element, on the upper surface of the circuit board;
a second lead electrically connected to the semiconductor element, at least a part of the second lead being superimposed on
the first lead, wherein the first lead and the second lead are disposed in the central region of the circuit board; and

one or more third leads electrically connected to the semiconductor element, at least one third lead of the one or more third
leads having an “L” shape with a first portion of the “L” shape being superimposed on both the first lead and the second lead
in the central region, and a long side of the “L” shape extending continuously and laterally in a first direction from the
central region to the periphery region and in the first direction through the frame-shape of the case material.

1. An image sensor, comprising:
an array of image pixels arranged in pixel rows and pixel columns;
a plurality of column lines, wherein each one of the plurality of column lines is coupled to a corresponding pixel column;
and

a plurality of column readout circuits, wherein each one of the plurality of column readout circuits is coupled to an associated
one of the plurality of column lines, wherein each one of the plurality of column readout circuits comprises a corresponding
data converting circuit and a corresponding latch circuit, and wherein the corresponding latch circuit is configured to selectively
power on the data converting circuit in that column readout circuit by selectively providing a column enabling signal to the
data converting circuit in that column readout circuit.

1. A method of operating with an image sensing pixel that includes a photodiode, a given transistor coupled between the photodiode
and a bias voltage, a charge storage region, a global shutter transistor coupled between the photodiode and the charge storage
region, a floating diffusion region, and a transfer transistor coupled between the charge storage region and the floating
diffusion region, the method comprising:
with the photodiode, converting incident light into first accumulated charge during a first integration period;
following the first integration period and with the global shutter transistor, transferring the first accumulated charge from
the photodiode to the charge storage region;

following the transfer of the first accumulated charge, resetting the photodiode with the given transistor;
after resetting the photodiode, converting incident light into second accumulated charge during a second integration period,
wherein the first and second integration periods have substantially equal lengths; and

following the second integration period and with the global shutter transistor, transferring the second accumulated charge
from the photodiode to the charge storage region such that the first and second accumulated charges are summed in the charge
storage region as a combined accumulated charge, wherein resetting the photodiode comprises resetting the photodiode over
a delay period, and wherein the delay period is at least a hundred times the length of the first integration period.

1. A light emitting element driving circuit comprising:
a rectifying circuit configured to output a rectified voltage obtained by providing rectification to an AC voltage;
a voltage-dividing circuit configured to output as a reference voltage, a divided voltage obtained by dividing the rectified
voltage, the voltage dividing circuit including a first resistor coupled between the rectified voltage and a source of operating
potential;

a transistor configured to increase a driving current of a light emitting element in accordance with the rectified voltage
when turned on and to reduce the driving current of the light emitting element when turned off;

a control circuit configured to bring the transistor to an on state or an off state at predetermined intervals and to bring
the transistor to the other of the on state or the off state when a voltage according to a current flowing through the transistor
increases and becomes the reference voltage; and

a voltage-dividing ratio adjustment circuit configured to set a voltage-dividing ratio of the voltage dividing circuit as
a first voltage-dividing ratio to reduce the reference voltage when an amplitude of the rectified voltage is larger than a
predetermined amplitude and to set the voltage-dividing ratio as a second voltage-dividing ratio to increase the reference
voltage when an amplitude of the rectified voltage is smaller than the predetermined amplitude, the voltage dividing ratio
adjustment circuit comprising a switch having a control terminal and first and second current carrying terminals, wherein
the first resistor has a terminal connected to the first current carrying terminal a of the switch and a second terminal connected
to the second current carrying terminal of the switch.

4. A driving circuit for a single-phase brushless motor, comprising:
a driving signal generating circuit configured to generate a driving signal for supplying, to a driving coil of the single-phase
brushless motor, a first driving current and a second driving current opposite in direction to the first driving current,
in an alternate manner with a de-energized period therebetween during which neither of the first driving current or the second
driving current is supplied to the driving coil;

an output circuit configured to supply the first or the second driving current to the driving coil in response to the driving
signal; and

a zero-cross detecting circuit configured to detect a zero cross of an induced voltage generated across the driving coil,
during the de-energized period, wherein

the driving signal generating circuit is further configured to determine a length of a subsequent energized period based on
a driving cycle from a start of an energized period, during which the output circuit supplies the first or the second driving
current to the driving coil, to a time when the zero-cross detecting circuit detects the zero cross; and wherein

the driving signal generating circuit includes
a first counter circuit configured to count using a predetermined clock, and reset every time the zero-cross detecting circuit
detects the zero cross,

a register configured to store, as the driving cycle, a count value acquired immediately before the first counter circuit
is reset, every time the zero-cross detecting circuit detects the zero cross, and

a timing control circuit configured to control the energized period and the de-energized period by outputting the driving
signal based on a count value of the first counter circuit, wherein

the timing control circuit is further configured to,
every time the zero-cross detecting circuit detects the zero cross, switch between the first driving current and the second
driving current, and cause the first or the second driving current to start to be supplied from the output circuit to the
driving coil, and

when the count value of the first counter circuit reaches a value acquired by multiplying the driving cycle stored in the
register by a predetermined coefficient greater than zero and smaller than one, cause both the first and the second driving
currents to stop being supplied from the output circuit to the driving coil.

1. An image sensor, comprising:
a substrate;
an image pixel array formed in the substrate, wherein the image pixel array includes first and second groups of image pixels
and wherein each image pixel in the first and second groups of image pixels comprises a signal photodiode; and

spectral response adjustment circuitry in each image pixel in the first group of image pixels, wherein the spectral response
adjustment circuitry comprises a responsivity adjustment photodiode that is configured to divert charge from the signal photodiode,

wherein the first group of image pixels comprises broadband image pixels having broadband color filter elements, wherein the
second group of image pixels comprises red and blue image pixels having red and blue color filter elements, and

wherein the responsivity adjustment photodiode is surrounded on three sides by the signal photodiode in the substrate.

1. A system for processing an incoming signal for audio application, comprising:
a parameter extraction module having an input terminal, an output terminal, a first input/output terminal, a second input/output
terminal, and a third input/output terminal, the input terminal coupled for receiving the incoming signal wherein the incoming
signal has a first frequency, the output terminal transmits an output signal having a second frequency, and wherein the parameter
extraction module is configured to extract least one parameter from the incoming signal, the at least one parameter including
a component that indicates the presence of a speech signal in the incoming signal;

at least one processing engine having an input terminal, an output terminal, a first input/output terminal, a second input/output
terminal, and a third input/output terminal, the first input/output terminal of the at least one processing engine coupled
to the first input/output terminal of the parameter extraction module, the second input/output terminal of the at least one
processing engine coupled to the second input/output terminal of the parameter extraction module, the third input/output terminal
of the at least one processing engine coupled to the third input/output terminal of the parameter extraction module, wherein
the input terminal of the at least one processing engine is coupled for receiving a clock signal having a clock frequency,
the at least one processing engine performing at least one first processing and subsequently performing at least one second
processing depending on whether the component of the at least one parameter indicates the presence of speech, and wherein
the at least one processing engine is configured for adjusting a clock frequency of the clock signal adaptively depending
on parameters of the incoming signal extracted or analyzed in the first processing; and

at least one oscillator having an input terminal and an output terminal, the input terminal of the at least one oscillator
directly connected to the output terminal of the at least one processing engine and the output terminal of the at least one
oscillator directly connected to the input terminal of the processing engine for transmitting the clock signal to the at least
one processing engine.

1. A method for operating an imaging system comprising processing circuitry and an image sensor having an array of image pixels,
the method comprising:
capturing, by the image sensor, first pixel values of a first color in response to image light;
capturing, by the image sensor, second pixel values of a second color that is different from the first color in response to
the image light;

with the processing circuitry, determining a first black pedestal value based on the first pixel values;
with the processing circuitry, determining a second black pedestal value based on the second pixel values, wherein the second
black pedestal value is different from the first black pedestal value;

with the processing circuitry, adding the first black pedestal value to the first pixel values to generate first corrected
pixel values;

with the processing circuitry, adding the second black pedestal value to the second pixel values to generate second corrected
pixel values, wherein the first and second corrected pixel values are substantially free from clipping; and

generating, by the processing circuitry, an output image based on the generated first and second corrected pixel values.

1. A battery power determination circuit, comprising:
a central processing unit having an input, an output, a first input/output, and a second input/output;
a selector circuit having a plurality of inputs and an output, a first input of the selector circuit coupled to the output
of the central processing unit;

an interface circuit having an input, a plurality of outputs, and an input/output, the input/output of the interface circuit
coupled to the first input/output of the central processing unit;

an analog-to-digital converter having an input and an output, the input of the analog-to-digital converter coupled to the
output of the selector circuit; and

a first storage element having an input/output coupled the second input/output of the central processing unit.

1. An imaging pixel, comprising:
a substrate;
a first layer of a first doping type in the substrate;
a second layer of a second doping type in the substrate, wherein the first and second layers form a p-n junction and the second
layer is directly beneath the first layer;

a third layer of the second doping type in the substrate, wherein the third layer is directly beneath the second layer; and
a counter-doping implant region in the substrate, wherein the counter-doping implant region has a first portion that extends
into the second layer and a second portion that extends into the third layer.

1. A control circuit for a light-emitting device, comprising:
a rectification circuit rectifying an AC voltage to generate a rectified voltage;
a switching device configured to turn on and off the light emitting device;
a reference voltage generation circuit generating a reference voltage;
a first comparator comparing a comparison voltage with the reference voltage, the comparison voltage corresponding to a current
flowing through the light-emitting device in response to the rectified voltage; and

a flip-flop configured to be set in response to a trigger pulse and reset in response to a result of comparison by the first
comparator, the flip-flop outputting an output voltage and controlling the switching device in accordance with the output
voltage, wherein the reference voltage generation circuit is configured so that a change in amplitude of the reference voltage
is suppressed when amplitude of the AC voltage varies.

1. A semiconductor package, comprising: first and second die flags each having a top and a bottom surface, wherein the first
and second die flags are separated by a gap, and wherein the first and the second die flags are electrically coupled through
a conductive layer formed on the bottom surface of the first and the second die flags; first and second metal oxide semiconductor
field effect transistor (MOSFET) die, each having a drain metal pad on a bottom surface of the MOSFET die, wherein the drain
metal pads are positioned on the top surface of the first and the second die flags, and wherein the drain metal pad of the
first MOSFET die is electrically coupled to the drain metal pad of the second MOSFET die, respectively; a power control integrated
circuit (IC) stacked on top of at least one of the first or the second MOSFET die; a mold compound encapsulating the power
control IC, the first and second MOSFET die, and the first and second die flags.

1. A time-of-flight image pixel comprising:
a photosensitive element;
first and second charge storage regions coupled to the photosensitive element;
a first transfer transistor coupled between the photosensitive element and the first charge storage region; and
a second transfer transistor coupled between the photosensitive element and the second charge storage region, wherein the
second transfer transistor includes a gate terminal that is coupled to the first charge storage region.

1. An imaging system, comprising:
an image sensor having an array of image sensor pixels, wherein the array of image sensor pixels includes red image sensor
pixels configured to generate red image signals in response to red light, blue image sensor pixels configured to generate
blue image signals in response to blue light, and clear image sensor pixels configured to generate white image signals in
response to at least red light, green light and blue light; and

processing circuitry configured to perform filtering operations on the red image signals, the blue image signals, and the
white image signals that increase noise correlations associated with red image signals, the blue image signals, and the white
image signals, wherein the processing circuitry is configured to perform the filtering operations on the red, blue, and white
image signals that increase the noise correlations associated with the red, blue, and white image signals such that noise
fluctuations in the red, blue, and white image signals increase and decrease together in a correlated manner.

9. A system, comprising:
a central processing unit;
memory;
input-output circuitry; and
an imaging device, wherein the imaging device comprises:
a monochromatic image sensor having a first array of image pixels, wherein the image pixels in the first array of image pixels
are diamond-shaped image pixels;

a polychromatic image sensor comprising:
a second array of image pixels, wherein the image pixels in the second array of image pixels are diamond-shaped image pixels;
and

a color filter array formed over the second array of image pixels and comprising red and blue color filter elements, wherein
the red color filter elements and the blue color filter elements are arranged in respective groups of red color filter elements
and groups of blue color filter elements, wherein each group of red color filter elements and each group of blue color filter
elements forms a zigzag pattern that extends from an upper edge of the second array to a lower edge of the second array, wherein
each red color filter element within each group of red color filter elements shares a side with at least one other red color
filter element, and wherein the groups of red color filter elements are interleaved with the groups of blue color filter elements;
and

processing circuitry configured to combine monochromatic image data from the monochromatic image sensor with polychromatic
image data from the polychromatic image sensor to form full-color images, wherein the monochromatic image sensor and the polychromatic
image sensor have an associated pixel pitch, wherein the processing circuitry interpolates missing pixel data to form the
full-color images, and wherein a maximum interpolation distance is ?{square root over (5)} times the pixel pitch.

1. A method for driving a light emitting unit, comprising:
providing the light emitting unit and a switching element, the light emitting unit having an input and an output, wherein
the input comprises an anode of a light emitting diode and the output comprises a terminal of a first inductor, and the switching
element coupled to the output of the light emitting unit;

providing a switching element having a control terminal and first and second conducting terminals, the first conducting terminal
coupled to the second terminal of the light emitting unit;

providing a control element having a supply input coupled for receiving an inductor signal;
providing a second inductor having first and second terminals, the first terminal of the second inductor coupled to the first
input of the first controller, the second inductor configured to be electromagnetically coupled to the first inductor;

providing a third inductor having first and second terminals, the third inductor configured to be electromagnetically coupled
to the first inductor, and configured to provide energy stored in the third inductor to an external circuit;

providing a first voltage at the input of light emitting unit;
continuously monitoring the first voltage to generate a monitor signal;
generating an output signal from the light emitting unit in response to a state of the switching element; and
using the monitor signal to control the switching element in response to the first voltage.

1. A method, comprising:
with an electronic device, prompting a user to perform a mechanical gesture with the electronic device, wherein prompting
the user to perform the mechanical gesture with the electronic device comprises prompting the user to move the electronic
device along a curved path while holding the electronic device at arm's length;

with at least one camera sensor in the electronic device and during the particular mechanical gesture, capturing image data
of an environment around the electronic device;

with image processing circuitry in the electronic device, identifying lighting characteristics of the environment based on
the image data;

with circuitry in the electronic device, determining imaging settings based on the identified lighting characteristics; and
with the at least one camera sensor, capturing an image using the determined imaging settings.

1. An image sensor, comprising:
a plurality of image sensor pixels;
an output line that is coupled to a portion of the plurality of image sensor pixels; and
anti-eclipse control circuitry that is coupled to the output line and that determines whether a selected pixel in the portion
of the plurality of image sensor pixels is over-exposed, wherein the anti-eclipse control circuitry includes an eclipse condition
judgment circuit that receives signals from the output line and that determines whether the selected pixel is over-exposed
by monitoring the received signals, and wherein the eclipse condition judgment circuit obtains first and second digital pixel
measurements, computes a difference of the first and second digital pixel measurements, and compares the computed difference
to a predetermined threshold value to determine whether the selected pixel is over-exposed, and wherein the anti-eclipse control
circuitry further includes an analog-to-digital converter interposed between the output line and the eclipse condition judgement
circuit.

1. A semiconductor device structure comprising:
a substrate;
a first semiconductor layer overlying the substrate and having a major surface spaced apart from the substrate;
a localized superjunction structure within a portion of the first semiconductor layer and extending from the major surface
into at least the first semiconductor layer, wherein the localized superjunction structure comprises:

a trench extending from the major surface into at least the first semiconductor layer, wherein the trench has a sidewall surface,
a second semiconductor layer of a first conductivity type overlying the sidewall surface of the trench, having a generally
vertical orientation and adjoining the first semiconductor layer, and

a third semiconductor layer of a second conductivity type disposed within the trench, wherein the third semiconductor layer
is disposed adjacent to the second semiconductor layer;

a control electrode adjacent the major surface and spaced apart from the localized superjunction structure;
a body region adjacent the major surface, the body region being laterally interposed between the control electrode and the
localized superjunction structure, wherein the localized superjunction structure adjoins a vertically oriented side surface
of the body region and the first semiconductor layer adjoins a bottom surface of the body region, and wherein the body region
extends downward from the major surface to a first depth; and

a first doped region of the second conductivity type disposed extending from the major surface to a top surface of the third
semiconductor layer, wherein the first doped region has a higher dopant concentration than the third semiconductor layer and
is configured to provide a charge imbalance within the localized superjunction structure, and wherein:

a first portion of the first doped region overlaps a top portion of the second semiconductor layer to laterally connect the
body region to the third semiconductor layer, the first portion of the first doped region abutting the vertically oriented
side surface of the body region,

the first doped region extends vertically downward from the major surface to a second depth greater than the first depth,
and

the top portion of the second semiconductor layer separates a second portion of the first doped region from at least a portion
of the vertically oriented side surface of the body region, the second portion of the first doped region being different from
the first portion of the first doped region.

1. A Schottky device, comprising:
a semiconductor material of a first conductivity type having first and second major surfaces;
a layer of in-situ doped polysilicon over the semiconductor material;
a doped region of a second conductivity type extending from the first major surface a distance that is less than a depth of
a zero bias depletion boundary, wherein an impurity material for the doped region is derived from the layer of in-situ doped
polysilicon over the semiconductor material; and

a Schottky contact in contact with the doped region.

1. An image sensor pixel comprising:
a substrate having opposing front and back surfaces, wherein the substrate comprises a p-type doped substrate;
a charge storage region formed at the back surface of the substrate, wherein the charge storage region is configured to accumulate
photo-generated charge, and wherein the charge storage region comprises an n-type doping layer; and

a charge readout node formed at the front surface of the substrate, wherein the charge readout node is configured to receive
the accumulated photo-generated charge from the charge storage region, wherein the charge readout node comprises an n-type
doped floating diffusion region, and wherein only p-type doped silicon is interposed between the charge storage region and
the charge readout node.

1. A method of forming an array of color filter elements over an imaging device integrated circuit including an array of photodiodes
in an imaging device, comprising:
depositing a layer of color filter material on a planar surface of a carrier substrate;
bonding the layer of color filter material to the imaging device integrated circuit;
while the layer of color filter material is bonded to the imaging device integrated circuit, removing the carrier substrate
from the layer of color filter material; and

after removing the carrier substrate from the layer of color filter material, patterning the layer of color filter material
to form the array of color filter elements on the integrated circuit.

1. A method for operating a stacked-chip image sensor having a planar array of image pixels, control circuitry, storage and
processing circuitry, a first two-dimensional array of conductive vias coupled between the planar image pixel array and the
control circuitry and a second two-dimensional array of conductive vias coupled between the control circuitry and the storage
and processing circuitry, the method comprising:
with the image pixels, capturing an image frame at a first frame rate;
with the control circuitry, reading out the image frame over a portion of the first two-dimensional array of conductive vias;
with the control circuitry, providing the image frame to the storage and processing circuitry over a portion of the second
two-dimensional array of conductive vias;

with the storage and processing circuitry, detecting an image of a moving object in the image frame;
with the storage and processing circuitry, generating a processed image frame by aligning the image of the detected moving
object in the image frame with an image of the moving object in a previously captured image frame, wherein the plurality of
previously captured image frames are captured with the image pixels; and

with the storage and processing circuitry, outputting the processed image frame at a second frame rate that is less than the
first frame rate.

1. A method for reducing flicker, comprising:
generating an adjusted rectified voltage in response to a TRIAC signal from a TRIAC dimmer;
generating a switching current in response to the adjusted rectified voltage being greater than a first reference voltage;
decreasing the switching current in response to the adjusted rectified voltage becoming less than the first reference voltage;
generating a first control signal in response to the adjusted rectified voltage becoming less than the first reference voltage;
decreasing a second reference voltage in response to the first control signal; and
turning off the TRIAC dimmer in response to decreasing the switching current.

15. A system, comprising:
a vehicle with an interior and an exterior;
a central processing unit;
memory;
input-output circuitry;
an imaging device configured to capture image data, wherein the imaging device is mounted at the interior of the vehicle and
oriented to face the exterior of the vehicle, wherein the imaging device comprises a single image sensor that captures image
data;

a host subsystem configured to perform vehicle assist functions for the vehicle using the captured image data, wherein the
vehicle assist functions comprise a vehicle safety system function selected from the group consisting of: a parking assistance
function, a cruise control function, an auto-braking function, a collision avoidance function, a pedestrian detection function,
and a lane keeping function;

a transparent protective layer separating the imaging device from the exterior of the vehicle; and
a light source mounted at the interior of the vehicle, wherein the light source is configured to emit a predetermined pattern
of light and wherein the central processing unit is configured to detect a near-field obstruction of the single image sensor
by identifying reflections of the predetermined pattern of light in the captured image data.

1. A method for operating an imaging system having processing circuitry and an array of image sensor pixels, wherein the array
of image sensor pixels includes a reference pixel, the method comprising:
with the array of image sensor pixels, receiving direct image light and stray light;
with the image sensor pixels, generating pixel values in response to the direct image light and the stray light;
with the reference pixel, generating a reference pixel value primarily in response to the stray light; and
with the processing circuitry, adjusting the pixel values generated by the image sensor pixels based on the reference pixel
value generated by the reference pixel, wherein adjusting the pixel values comprises:

determining whether the pixel values comprise a texture area; and
in response to determining that the pixel values comprise a texture, performing veiling glare compensation operations on the
pixel values.

1. A semiconductor device comprising:
a semiconductor substrate having an active region and an inactive region;
a plurality of active trenches formed in the active region, a first active trench of the plurality of active trenches having
a longitudinal portion extending a first distance in a first direction along an axis and having trench ends at distal ends
of the first active trench;

an outer periphery of the plurality of active trenches wherein a first portion of the outer periphery extends along the first
direction and a second portion of the outer periphery extends in second direction different from the first direction;

a plate conductor within the first active trench;
a termination trench substantially surrounding the outer periphery of the plurality of active trenches;
a termination conductor within the termination trench;
a longitudinal side of the termination trench extending in the first direction outside the outer periphery of the plurality
of active trenches; and

a second side of the termination trench outside the second portion of the outer periphery of the plurality of active trenches,
a first section of the second side of the termination trench juxtaposed to a first trench end of the first active trench wherein
the first section includes a non-linear shape including one of a scalloped shape or angular shape or projection shape or flared
shape or diamond shape, the first section positioned to form a second distance between an interior edge of the first section
and a first corner of the first trench end of the first active trench and between the interior edge and a second corner of
the first trench end of the first active trench, and to form a third distance between one of a longitudinal side of the first
active trench and a longitudinal side of an adjacent active trench or between the longitudinal side of the first active trench
and the longitudinal side of the termination trench wherein the second distance is substantially one of no greater than or
less than the third distance.

1. A semiconductor device, comprising:
a circuit board made of a metal, the circuit board having an upper surface;
an oxide film directly on the upper surface;
an island made of a metal film directly on the oxide film;
a fixation substrate made of a ceramic and fixed to the island with a fixing material; and
a semiconductor element mounted on an upper surface of the fixation substrate.

1. A process of forming a semiconductor wafer comprising:
providing a substrate having a primary surface and including a central region, an edge region including a side surface adjacent
to the primary surface, and an intermediate region disposed between the central region and the edge region;

forming a patterned poly template layer over the primary surface within the edge region wherein the central region is not
covered by the patterned poly template layer; and

forming a semiconductor layer over all of the primary surface and along the side surface, wherein the semiconductor layer
is monocrystalline within the central region and polycrystalline where formed over the patterned poly template layer; and

removing a portion of the semiconductor layer from over the intermediate region, wherein after removing the part of the semiconductor
layer:

a first remaining portion of the semiconductor layer is monocrystalline and lies within the central region,
a second remaining portion of the semiconductor layer is polycrystalline and lies along the side surface, and
the first remaining portion of the semiconductor layer is laterally spaced apart from the second remaining portion of the
semiconductor layer, wherein the intermediate region is disposed between the first and second remaining portions of the semiconductor
layer and does not include any portion of each of the semiconductor layer and the patterned poly template layer.

1. A hybrid imaging pixel comprising:
a floating diffusion region;
a transistor coupled to the floating diffusion region;
a switch that has a first configuration that couples the transistor to a supply voltage of the hybrid imaging pixel and that
has a second configuration that couples the transistor to an output line of the hybrid imaging pixel;

a first photodiode that is coupled to the floating diffusion region, wherein the first photodiode accumulates charge during
a first integration period;

a transfer gate that is coupled to the floating diffusion region; and
a second photodiode that is coupled to the floating diffusion region by the transfer gate, wherein the second photodiode accumulates
charge during a second integration period.

1. A battery charger for a portable electronic device, comprising:
a power supply;
a power supply line connected to the power supply;
a ground line connected to the power supply;
a USB connector comprising a Vbus terminal;
a switching device connected between the power supply line and the Vbus terminal; and
a controller configured to:
perform a first detection to detect a change in a voltage at the Vbus terminal by outputting a first voltage to the Vbus terminal
from a voltage output portion of the controller while the switching device is open and terminating the outputting of the first
voltage, to judge whether the portable electronic device is connected to the USB connector based on a result of the first
detection, wherein the first detection is performed after the terminating of the outputting of the first voltage;

turn on the switching device when the controller judges that the portable electronic device is connected to the USB connector;
perform a second detection to detect a change in the voltage at the Vbus terminal by outputting a second voltage that is different
from the first voltage to the Vbus terminal and then terminating the outputting of the second voltage to and determining whether
the voltage at the Vbus terminal changes from the second voltage when the controller judges that the portable electronic device
is not connected to the USB connector based on the result of the first detection, and judges whether the portable electronic
device is connected to the USB connector based on a result of the second detection; and

turn on the switching device when the controller judges that the portable electronic device is connected to the USB connector.

1. A semiconductor device comprising:
a first conductive substrate electrically coupled to a first lead, wherein the first conductive substrate comprises two or
more elevated regions on a first side of the first conductive substrate, wherein each of the elevated regions comprises a
planar surface on the first side of the first conductive substrate;

a semiconductor die comprising one or more first contact pads, a second contact pad, and a third contact pad, wherein the
first contact pads are disposed on a first side of the semiconductor die, and wherein each of the first contact pads are soldered
to at least one of the elevated regions such that each of the first contacts pads has two or more linear edges that are each
laterally aligned and parallel with at least one edge of the planar surfaces on the elevated regions, and wherein at least
one of the first contact pads is soldered to two or more of the elevated regions;

a second lead electrically coupled to the second contact pad of the semiconductor die; and
a third lead electrically coupled to the third contact pad of the semiconductor die.

1. Image sensor pixel circuitry, comprising:
a photosensitive element;
a floating diffusion region;
a charge transfer transistor coupled between the photosensitive element and the floating diffusion region;
a source follower transistor having a gate terminal, a first source-drain terminal, and a second source-drain terminal, wherein
the gate terminal of the source follower transistor is coupled to the floating diffusion region;

a capacitor having a first terminal that is directly coupled to the floating diffusion region and a second terminal that is
directly coupled to the first source-drain terminal of the source follower transistor, wherein the image sensor pixel circuitry
is operable in a low conversion gain mode and a high conversion gain mode;

a power supply line;
a reset transistor coupled between the power supply line and the floating diffusion region; and
a first switch that is coupled between the power supply line and the first source-drain terminal of the source follower transistor,
wherein the first switch is turned on during the low conversion gain mode and is turned off during the high conversion gain
mode.

1. A chip scale package (CSP), comprising:
a die;
a first lead mechanically and electrically coupled to a first surface of the die at a first surface of the first lead, the
first surface of the first lead forming a first plane and a second surface of the first lead forming a fifth plane, a thickness
of the first lead present between the first plane and the fifth plane;

a second lead mechanically coupled to a second surface of the die at a first surface of the second lead, the first surface
of the second lead forming a second plane and a second surface of the second lead forming a fourth plane, a thickness of the
second lead present between the second plane and the fourth plane; and

a mold compound at least partially encapsulating the die, where the die, first lead, second lead, and mold compound form a
chip scale package (CSP);

wherein the first plane of the first lead and the second plane of the second lead are oriented substantially perpendicularly
to a third plane formed by a motherboard when the CSP is coupled to the motherboard at the thickness of the first lead and
the thickness of the second lead.

1. An imaging system, comprising:
an array of image sensors formed in an image sensor substrate, wherein each image sensor includes an array of image sensor
pixels;

a transparent cover layer formed over the array of image sensors;
an adhesive interposed between the image sensor substrate and the transparent cover layer, wherein the adhesive attaches the
transparent cover layer to the image sensor substrate; and

a light blocking material formed on the adhesive, wherein the light blocking material is interposed between adjacent image
sensors in the array of image sensors.

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type, wherein the first conductivity type is a n-type conductivity;
a first semiconducting layer of the first conductivity type overlying the semiconductor substrate, wherein the first semiconducting
layer is an epitaxial layer; and

an edge termination structure surrounding an active region of the semiconductor device, wherein the edge termination structure
comprises one or more first super junction trenches disposed in the first semiconducting layer, wherein the first super-junction
trenches each comprise:

a first semiconducting region having a second conductivity type, wherein the second conductivity type is a n-type conductivity;
a second semiconducting region adjacent to the first semiconducting region, wherein the second semiconducting region has a
third conductivity type, wherein the third conductivity type is a p-type conductivity, and wherein the second semiconducting
region comprises a first p-well region that is adjacent to the first semiconducting layer;

a first buffer region adjacent to the second semiconducting region, wherein a portion the second semiconducting region is
disposed between the first semiconducting region and the first buffer region;

a third semiconducting region adjacent to the first buffer region, wherein the third semiconducting region has the third conductivity
type, and wherein the third semiconducting region comprises a second p-well region that is adjacent to the first semiconducting
layer;

a fourth semiconducting region adjacent to the third semiconducting region, wherein the fourth semiconducting region has the
second conductivity type, and wherein a portion of the third semiconducting region is disposed between the first buffer region
and the fourth semiconducting region; and

a first conducting region electrically coupling the second semiconducting region to the third semiconducting region, wherein
the first conducting region is adjacent the first p-well region of the second semiconducting region and the second p-well
region of the third semiconducting region.

1. An image sensor, comprising:
a plurality of red image sensor pixels each having a red color filter element;
a plurality of blue image sensor pixels each having a blue color filter element; and
a plurality of modified clear image pixels each having a modified clear color filter element that includes a mixture of transparent
material and color pigment material, wherein the plurality of red image sensor pixels, the plurality of blue image sensor
pixels, and the plurality of modified clear image pixels are arranged in a pattern of repeating two-pixel by two-pixel unit
cells across an image sensor pixel array, and wherein each of the two-pixel by two-pixel unit cells comprises a corresponding
pair of the modified clear image pixels.

1. An image sensor, comprising;
an array of photodiodes in a substrate;
color filter material in a color filter array;
a microlens array; and
a metamaterial layer between the color filter material and the microlens array, wherein a resonance cavity is formed at least
partly from the color filter material and a first partially-reflecting interface between the color filter material and the
metamaterial layer, and wherein the color filter array is formed between the microlens array and the substrate on a first
side of the substrate, wherein the image sensor further includes an additional color filter array with an additional resonance
cavity on a second side of the substrate.

1. A method of manufacturing a semiconductor device package, the method comprising:
coupling a single layer clip comprising at least one source finger, at least one drain finger, and at least one gate finger
to a plurality of source standoff contacts, a plurality of drain standoff contacts, and one or more gate standoff contacts,
respectively, comprised in a lateral semiconductor device;

coupling a leadframe to the single layer clip, the leadframe comprising at least one source section, at least one drain section,
and at least one gate section;

one of overmolding and encapsulating the lateral semiconductor device, a majority of the single layer clip, and a face of
the leadframe facing the lateral semiconductor device with a mold compound; and

singulating the at least one source finger, the at least one drain finger, and the at least one gate finger.

1. A charging system for portable electronic equipment to charge a battery incorporated in the portable electronic equipment
by connecting a USB battery charger to the portable electronic equipment, the charging system comprising:
a power supply terminal;
a first switching device providing the battery with a charging current received at the power supply terminal from the USB
battery charger;

a second switching device connected between the power supply terminal and a ground;
a control circuit controlling the first and second switching devices, wherein the control circuit turns on the first switching
device to commence providing the battery with the charging current and, in response to a voltage at the power supply terminal
having a first value that is lower than a first predetermined voltage, turns off the first switching device and turns on the
second switching device so that the voltage at the power supply terminal is reduced to a second value that is lower than a
second predetermined voltage, the second predetermined voltage being lower than the first predetermined voltage; and

the charging system configured to maintain the power supply terminal at substantially the second value for a predetermined
period of time.

1. A ripple suppressor circuit comprising:
a first input configured to receive a first signal that is a pulse width modulated signal having a duty cycle that is representative
of a requested output voltage value;

a second input configured to receive a second signal that is a filtered value of the first signal;
a first storage element;
a second storage element;
a first switch configured to store a first value of the second signal on the first storage element responsively to a first
transition of the first signal;

a second switch configured to store a second value of the second signal on she second storage element responsively to a second
transition of the first signal; and

an averaging circuit configured to receive the first value of the second signal from the first storage element and to receive
the second value of the second signal from the second storage element and form a reference signal having a value that is an
average value of the first value and the second value.

1. An electronic device including a nonvolatile memory cell, wherein the nonvolatile memory cell comprises:
a substrate;
an access transistor having source/drain regions at least partly within the substrate, a gate dielectric layer overlying the
substrate, and a gate electrode overlying the gate dielectric layer;

a read transistor having source/drain regions at least partly within the substrate, a gate dielectric layer overlying the
substrate, and a gate electrode overlying the gate dielectric layer; and

an antifuse component including a first electrode lying at least partly within the substrate, an antifuse dielectric layer
overlying the substrate, and a second electrode overlying the antifuse dielectric layer,

wherein the second electrode of the antifuse component is coupled to one of the source/drain regions of the access transistor
and to the gate electrode of the read transistor.

8. A method of operating an image sensor, comprising:
selecting an image sensor pixel from a plurality of image sensor pixels for readout;
using the selected image sensor pixel to output a pixel signal onto an output line; and
with analog-to-digital converter (ADC) circuitry, converting the pixel signal into a corresponding floating point number by
performing an exponent conversion and a mantissa conversion for the floating point number, wherein the ADC circuitry comprises
a single slope analog-to-digital converter, and wherein converting the pixel signal comprises using a first ramp signal with
a first ramp step during the exponent conversion and using a second ramp signal with a second ramp step that is different
than the first ramp step during the mantissa conversion.

1. A method of forming a semiconductor package, comprising:
providing an electrically insulative layer having a first surface opposing a second surface;
plating a first copper layer onto the second surface of the electrically insulative layer;
patterning the first copper layer;
forming traces in the first copper layer by etching through exposed portions of the first copper layer;
plating a second copper layer onto the traces in the first copper layer;
patterning the second copper layer;
forming traces in the second copper layer that correspond with the traces in the first copper layer by etching through exposed
portions of the second copper layer;

bonding at least one semiconductor device with at least one of the traces in the second copper layer;
encapsulating the at least one semiconductor device with a mold compound; and
bonding at least one package electrical connector with one of the first copper layer and the second copper layer;
wherein a width of the traces of the second copper layer are thinner than a width of the traces of the first copper layer
by an offset distance.

1. An imaging system, comprising:
an image sensor;
a surface that is at least partially translucent;
a lens that focuses light from the surface onto the image sensor; and
processing circuitry configured to operate the image sensor to capture images of an object through the surface and to extract
user input data from the captured images of the object, wherein the processing circuitry comprises memory, and wherein the
processing circuitry is configured to extract the user input data from the captured images of the object by extracting gesture
point locations from the captured images, to store coordinate data associated with the extracted gesture point locations using
the memory, to rotate the stored coordinate data, to scale distances between the coordinate data, and to compare the scaled
and rotated coordinate data with template data associated with a plurality of characters.

1. A cutting tool comprising:
a central support section having a major axis;
a cutting tip;
a cutting surface adjacent to the cutting tip and extending from the cutting tip toward the central support section terminating
in a distal end of the cutting surface wherein the cutting surface is attached to the central support section;

a depth stop spaced a first distance from the cutting tip toward the central support section wherein a first volume is formed
by a portion of the cutting surface extending from the cutting tip to the depth stop; and

an accumulation region adjacent to the central support section and extending away from the cutting surface, the accumulation
region having a second volume that approximates the first volume.

1. A process of forming an electronic device comprising:
forming a semiconductor layer over a substrate, wherein the semiconductor layer has a primary surface;
patterning the semiconductor layer to define a first trench and a second trench that extend from the primary surface towards
the substrate;

forming first conductive structures within the first and second trenches;
forming a first insulating member within the first trench after forming the first conductive structures;
forming a gate electrode within the first trench, wherein within the first trench, the first insulating member is disposed
between the gate electrode and the first conductive structure;

forming a source region adjacent to the first trench;
forming a second insulating member within the second trench after forming the first conductive structures; and
forming a second conductive structure, wherein within the second trench, the second insulating member is disposed between
the second conductive structure and the first conductive structure, wherein the source region is electrically connected to
the second conductive structure.

1. A pulse width modulated controller system for a semiconductor switch, the system comprising:
a microcontroller coupled with a memory;
a switch controller coupled with the microcontroller; and
a calibration unit, the calibration unit comprising:
at least two comparators, one or more passive electrical components, and an encoder logic all operatively coupled together
and coupled with the microcontroller and with the switch controller;

wherein the microcontroller is configured to send a calibration trigger signal to the encoder logic of the calibration unit,
and, in response, the calibration unit is configured to:

using a first one of the at least two comparators, generate a first comparator output for a switching-on operation of the
semiconductor switch;

using a second one of the at least two comparators, generate a second comparator output for a switching-off operation of the
semiconductor switch;

generate a status signal using the encoder logic using one of the first comparator output, the second comparator output, and
both the first comparator output and the second comparator output; and

send the status signal to the microcontroller;
wherein the one or more comparators and the one or more passive electrical components are electrically coupled with a supply
voltage to the semiconductor switch and with an output voltage from the semiconductor switch;

wherein the memory coupled to the microcontroller comprises a digitally stored model comprising one or more control parameters
for generating a control signal for the semiconductor switch; and

wherein the microcontroller is configured to receive one or more operating condition parameters, and, using one or more operating
condition parameters and the digitally stored model, to generate control parameters for generating the control signal for
the semiconductor switch.

1. An image sensor comprising:
a substrate having a first conductivity type;
a first well in the substrate and having an opposite conductivity type and doped with opposite conductivity type dopant at
a first dosage at a first implantation energy;

a second well in the first well and having the opposite conductivity type and doped with opposite conductivity type dopant
at a second dosage higher than the first dosage;

a first region in the second well and having the opposite conductivity type and doped with opposite conductivity type dopant
at a second implantation energy higher than the first implantation energy;

a second region in the first region and having the first conductivity type and doped with first conductivity type dopant at
a third dosage higher than the second dosage at the first implantation energy;

a third region in the second well adjacent the first region and having the opposite conductivity type and doped with opposite
conductivity type dopant at the third dosage at the first implantation energy

a temperature sensor for measuring temperature measurements of the image sensor and disposed between the second region and
the third region and connected to each of the second region and the third region; and

a third well having the first conductivity type in the first well and adjacent the second well.

1. A circuit device, comprising:
a circuit board having a perimeter and a central portion that is interior to the perimeter and does not extend through the
perimeter;

a semiconductor element disposed on an upper surface of the circuit board;
a first lead electrically connected to the semiconductor element, on the upper surface of the circuit board wherein the first
lead traverses the central portion of the circuit board;

a second lead electrically connected to the semiconductor element, at least a part of the second lead being superimposed on
the first lead;

a case material forming a frame-shape assembled onto the upper surface of the circuit board, the frame-shape forming a space
overlying the semiconductor element wherein a portion of the frame-shape of the case material traverses the central portion
underlying the first lead and is positioned between the first lead and the circuit board and between the first lead and the
second lead and wherein the semiconductor element is not connected to another lead having a portion that is both on the circuit
board and not on the frame-shape of the case material; and

a sealing resin disposed within the space.

1. An electronic device comprising:
a first switch having a first current-carrying electrode and a second current-carrying electrode, wherein:
the first switch has a first breakdown voltage between the first and second current-carrying electrodes;
the first current-carrying electrode is coupled to a first input terminal; and
the second current-carrying electrode is coupled to a switching node,
wherein:
the first switch is part of an electronic circuit having a designed operating voltage between the first input terminal and
a second input terminal, wherein the second input terminal is coupled to the second current-carrying electrode; and

the first breakdown voltage is less than 2.0 times the designed operating voltage during at least part of a transient period
after switching states, the first switch or the second switch operates in avalanche mode.

1. A method of operating an image sensor coupled to image processing circuitry, wherein the image sensor comprises an array
of image sensor pixels and readout circuitry, the method comprising:
with an image sensor pixel in the array, capturing a first image signal while a dual conversion gain gate in the image sensor
pixel is turned off;

with the image sensor pixel, capturing a second image signal subsequent to capturing the first image signal while the dual
conversion gain gate is turned on;

with a memory circuit in the readout circuitry, storing the first image signal;
with the readout circuitry, identifying a selected one of the first and second image signals to output to the image processing
circuitry based on the captured first image signal, wherein identifying the selected one of the first and second image signals
to output to the image processing circuitry comprises:

determining whether the first image signal exceeds a predetermined threshold; and
in response to determining that the first image signal does not exceed the predetermined threshold, labeling the first image
signal with an indication bit that instructs the readout circuitry not to overwrite the first image signal on the memory circuit;
and

with the readout circuitry, outputting the identified image signal to the image processing circuitry.

1. A structured light imaging system comprising:
an infrared light source configured to generate a stream of light pulses, wherein each of the light pulses comprises a structured
light pulse that projects a known pattern of light onto an object; and

an image sensor comprising:
a photodiode that converts the stream after reflection by a scene to charge,
a first storage element,
a first switch coupled between the photodiode and the first storage element,
a second storage element,
a second switch coupled between the photodiode and the second storage element,
a third and a fourth storage element, and
a controller coupled to the first and second switches, the controller configured to synchronize the image sensor to the infrared
light source, actuate the first switch to couple the first storage element to the photodiode to store charge converted during
one or more of the light pulses, and actuate the second switch to couple the second storage element to the photodiode to store
charge converted between one or more of the light pulses, wherein the controller is further configured to subtract the charge
stored in the second storage element from the charge stored in the first storage element, subtract the charge stored in the
second storage element from the charge stored in the third storage element, and subtract the charge stored in the second storage
element from the charge stored in the fourth storage element.

1. An image sensor pixel in an image sensor having a silicon substrate and an interconnect stack formed on a surface of the
silicon substrate, wherein the interconnect stack comprises a plurality of oxide layers, the image sensor pixel comprising:
a photodiode formed in the surface of the silicon substrate;
a transfer gate formed on the surface of the silicon substrate, wherein the transfer gate is configured to transfer charge
from the photodiode to a floating diffusion;

a blooming control structure, wherein the blooming control structure is configured to remove overflow charge from the photodiode
and wherein the blooming control structure is separate from the transfer gate; and

a conductive contact material in the interconnect stack that provides a bias voltage to the blooming control structure, wherein
the conductive contact material is in contact with the surface of the silicon substrate and is at least partially surrounded
by spacer structures that align the conductive contact material with the blooming control structure.

1. An electronic device, comprising:
a group of image sensor pixels;
sub-histogram generation circuitry configured to generate a plurality of sub-histograms of pixel values, wherein each sub-histogram
comprises pixel values generated by a respective subset of the image sensor pixels in the group of image sensor pixels, wherein
the sub-histogram generation circuitry comprises:

input gate circuitry configured to receive the pixel values from the array of image sensor pixels; and
bin identification decoder circuitry, wherein the bin identification decoder circuitry is configured to provide a sub-histogram
bin identification signal to the input gate circuitry; and

histogram accumulation circuitry configured to generate an accumulated histogram of pixel values by combining the generated
plurality of sub-histograms.

1. Image sensor pixel circuitry comprising:
a substrate having opposing front and back surfaces;
a charge storage region formed at the back surface of the substrate, wherein the charge storage region is configured to accumulate
photo-generated charge;

a charge readout node formed at the front surface of the substrate, wherein the charge readout node is configured to receive
the accumulated photo-generated charge from the charge storage region;

a first reset transistor formed on the front surface of the substrate and coupled to the charge readout node; and
a second reset transistor formed on the front surface of the substrate and coupled to the charge readout node through a capacitor.

1. A method of forming an insulated metal substrate (IMS) for a power electronic, comprising:
partially etching a first surface of a copper layer to form a pattern comprising a first thickness and a second thickness
greater than the first thickness, the first thickness and the second thickness both measured perpendicular to a second surface
of the copper layer opposite the first surface of the copper layer;

laminating the first surface of the copper layer with a second surface of a dielectric layer, the dielectric layer coupled
to a metallic baseplate at a first surface of the dielectric layer opposite the second surface of the dielectric layer and
at a second surface of the metallic baseplate; and

forming traces in the copper layer by etching through the copper layer at the first thickness and etching completely through
the copper layer at the second thickness, wherein the traces comprise two different trace thicknesses, where the trace thicknesses
are measured perpendicularly to the first surface of the dielectric layer.

1. A method of forming a semiconductor device comprising:
providing a region of semiconductor material having a trench extending from a major surface and having an isolated shield
electrode structure in a lower portion of the trench and a gate dielectric layer adjacent sidewalls of the trench;

forming conductive spacers adjacent the gate dielectric layer in the trench, the conductive spacers configured as part of
a gate electrode structure;

forming a stress inducing structure within the trench and interposed between the conductive spacers, wherein the stress inducing
structure and the conductive spacers comprise different materials; and

thereafter forming a conductive layer adjacent the stress inducing layer and interposed between the conductive spacers, the
conductive layer configured as another part of the gate electrode structure.

1. A sequencing lighting system comprising:
at least two integrated circuits, wherein each integrated circuit comprises a control input and a sequence output;
a control unit coupled to a first integrated circuit of the at least two integrated circuits;
an intermediate communication signal coupling the sequence output of the first integrated circuit to the control input of
a second integrated circuit of the at least two integrated circuits;

a diagnostic circuit contained within each integrated circuit, wherein the diagnostic circuit detects an open circuit condition
and produces an open circuit signal.

1. An electrical circuit, comprising:a control circuit having a plurality of switches; and
an electrical load coupled to the control circuit and having a plurality of load components, wherein a first of the plurality of switches is configured to control a first of the plurality of load components, and wherein a second of the plurality of switches is configured to control a second of the plurality of load components synchronously with the first of the plurality of switches, and wherein an input of the second of the plurality of switches is coupled to an input of the first of the plurality of switches via a diode.

1. A transistor structure comprising:
a semiconductor layer overlying a substrate and having a primary surface that generally corresponds to a first plane;
a trench extending into the semiconductor layer and having a tapered shape including a relatively wider portion adjacent to
the primary surface and a relatively narrower portion farther from the primary surface as compared to the relatively wider
portion, wherein, from a cross-sectional view, the relatively narrower portion is defined by a substantially planar sidewall
that lies along a second plane that intersects the first plane at an angle of greater than approximately 70°;

a doped semiconductor region that lies adjacent to a sidewall of the trench having the tapered shape, wherein the doped semiconductor
region extends to the narrower portion and has a dopant concentration greater than a dopant concentration of the semiconductor
layer at a location adjacent to the primary surface, and wherein the doped semiconductor region is part of the drain region
of the transistor structure; and a gate member disposed outside of the trench.

1. An image sensor, comprising:
an array of image sensor pixels arranged in rows and columns;
a plurality of pixel column lines, each of which is coupled to image sensor pixels arranged along a respective column in the
array;

analog-to-digital converter circuitry interposed in the plurality of pixel column lines, wherein the analog-to-digital converter
circuitry is directly connected to one of the plurality of pixel column lines; and

column memory and repair circuitry, wherein the column memory and repair circuitry receives pixel signals from the plurality
of pixel column lines and stores the received pixel signals into corresponding column memory circuits in the column memory
and repair circuitry, wherein the column memory and repair circuitry implements column-wise repair by selectively bypassing
a defective column memory circuit in the column memory circuits, wherein the analog-to-digital converter circuitry is interposed
between the image sensor pixels and the column memory and repair circuitry, and wherein the column memory and repair circuitry
comprises:

a plurality of multiplexers each of which is coupled to a respective one of the column memory circuits; and
a scan chain coupled to inputs of the plurality of multiplexers, wherein the scan chain comprises a plurality of flip-flop
circuits controlled by a clock signal.

1. A power supply controller comprising:
a first input configured to receive a first current sense signal that is representative of an adapter current supplied from
an ac adapter to at least a load;

a second input configured to receive a feedback signal that is representative of a voltage of a battery;
an error circuit configured to form an error signal that is representative of a deviation of the adapter current from a desired
value of the adapter current;

a switching control circuit configured to form a switching control signal to control first and second switches, the switching
control circuit configured to form a ramp signal and to control a duty cycle of the switching control signal responsively
to a difference between the ramp signal and the error signal wherein the switching control circuit controls the first and
second switches to charge the battery from the ac adapter responsively to the adapter current being less than a first value;

a control circuit configured to detect that the adapter current is greater than the first value, the control circuit configured
to offset a dc value of the ramp signal responsively to detecting that the adapter current is greater than the first value
wherein the switching control circuit controls the first and second switches to supply current from the battery to the load
responsively to the adapter current being greater than the first value; and

a clamp circuit configured to clamp a low value of the error signal to a lower clamp value, the clamp circuit configured to
change the lower clamp value of the error signal from a first clamp value to a second clamp value, that is less than the first
clamp value, a first time interval after detecting that the adapter current is greater than the first value.

14. An image sensor comprising:
a time-delay-and-integrate (TDI) image sensor comprising (i) a plurality of integrating CCDs (ICCDs), arranged in parallel,
that accumulate photo charge in response to exposure to light, (ii) electrically coupled to the plurality of ICCDs, a readout
CCD (RCCD) for receiving photo charge from the plurality of ICCDs, and (iii) electrically coupled to the RCCD, readout circuitry
for converting charge received from the RCCD into voltage,

wherein each ICCD comprises (i) a plurality of independently controllable stages, wherein each of said plurality of independently
controllable stages is further independently resettable, (ii) a photosensitive channel for containing photo charge, (iii)
a drain for removing photo charge from the channel, and (iv) a gate for controlling flow of photo charge from the channel
to the drain; and

a control circuit coupled to the TDI image sensor, for controlling the plurality of ICCDs to acquire an image and transfer
charge along the plurality of ICCDs to the RCCD, and to reset a selected one of the plurality of independently controllable
stages based on an image intensity.

1. A method for processing semiconductor die comprising:
providing a semiconductor wafer having a plurality of semiconductor die formed on the semiconductor wafer and separated from
each other by spaces, wherein the semiconductor wafer has first and second opposing major surfaces, and wherein a conductive
layer is affixed adjoining the second major surface;

placing the semiconductor wafer onto a first carrier substrate;
plasma etching the semiconductor wafer through the spaces to form singulation lines adjacent the plurality of semiconductor
die, wherein the plasma etching step stops proximate to the conductive layer in the singulation lines;

using a water miscible solvent to reduce the presence of residual contaminants resulting from the plasma etching step from
surfaces of the plurality of semiconductor die; and

removing the conductive layer in the singulation lines using a first fluid ablation process.

1. A method for detecting a position of a lens, comprising:
generating an approximated relationship between the position of the lens and a current;
generating a corrected detection current in response to the approximated relationship; and
using the corrected detection current to determine the position of the lens.

1. An imager, comprising:
an array of pixels that receives at least one control signal that controls the array of pixels to produce image pixel signals;
an array of error detection circuits that receives the at least one control signal, wherein the array of error detection circuits
produces error detection signals based on the at least one control signal wherein the array of error-detection circuits is
arranged in rows and columns, and wherein the array of pixels is arranged in matching rows and columns; and

a readout path over which the image pixels and the error detection signals are conveyed together to form a composite image.

1. A method for operating an imaging system having a stacked-chip image sensor and an adjustable lens system to capture an
image of an object in a scene, wherein the stacked-chip image sensor comprises a planar array of image pixels and storage
and processing circuitry, the method comprising:
moving at least one lens in the adjustable lens system into a plurality of focus positions while passing light from a scene
to the image pixels through the at least one lens;

with the image pixels, capturing a focus bracket of image frames while moving the at least one lens;
with the storage and processing circuitry, gathering depth map information for the scene by comparing a first image frame
in the focus bracket with a second image frame in the focus bracket, wherein gathering the depth map information comprises
determining a distance between the object in the scene and the imaging system; and

with the storage and processing circuitry, combining a set of image frames from the focus bracket of image frames to generate
a focused image based on the gathered depth map information.

1. An electronic device comprising:
a substrate having a first dopant with a first conductivity type;
a first semiconductor layer over the substrate and including a second dopant of the first conductivity type;
a second semiconductor layer over the first semiconductor layer; and
a first doped region at an interface of and extending into the first and second semiconductor layers, wherein the first doped
region has a third dopant with a second conductivity type opposite the first conductivity type,

wherein:
a first dopant concentration profile of the first and second dopants has a first relatively steeper portion adjacent to the
substrate, a second relatively steeper portion adjacent to an interface between the first and second semiconductor layers,
and a relatively flatter portion between the first and second relative steeper portions; and

a first diode is formed at a pn junction where a second dopant concentration profile of the third dopant intersects the relatively
flatter portion of the first dopant concentration profile.

1. A light emitting diode (LED) control circuit comprising:a metal oxide semiconductor (MOS) transistor, the MOS transistor having a first terminal that is connected to an input voltage of the LED control circuit;
a sense resistor having a first end connected to a second terminal of the MOS transistor and a second end that is connected to ground;
a controller integrated circuit (IC) that is configured to control a switching operation of the MOS transistor by hysteretic control, to sense a current sense voltage that is developed on the sense resistor by an output current, to turn off the MOS transistor when the current sense voltage reaches a first threshold voltage, to generate a sawtooth voltage, and to turn on the MOS transistor when the sawtooth voltage reaches a second threshold voltage.

1. A method of operating an imaging system, wherein the imaging system comprises an image sensor and control and processing
circuitry, the method comprising:
with the image sensor, capturing a frame of image data;
with the control and processing circuitry, detecting an optical marker in the frame of image data, wherein the optical marker
represents a privacy request;

in response to detecting the optical marker in the frame of image data, modifying the frame of image data; and
in response to detecting the optical marker in the frame of image data, detecting a license plate present in the frame of
image data.

1. An image sensor, comprising:
an array of image pixels arranged in pixel rows and pixel columns;
a conductive column line coupled to each pixel column;
column readout circuitry coupled to the pixel columns through the conductive column lines; and
row control circuitry configured to operate the array of image pixels to capture a column-interleaved image with short-exposure
pixel values and long-exposure pixel values that are interleaved in a column-based pattern, wherein the row control circuity
comprises first and second reset lines coupled to each pixel row, wherein the first reset lines are coupled to a first set
of pixels in each pixel row that capture the long-exposure pixel values and the second reset lines are coupled to a second
set of pixels in each pixel row that capture the short-exposure pixel values, and wherein the row control circuitry is configured
to provide reset control signals over the first and second reset lines to perform at least two resets of both the first and
second sets of pixels between consecutive readouts of the long and short-exposure pixel values from the array of image pixels.

1. A method for determining a fault in a transformer, comprising:
providing the transformer having primary and secondary sides;
in a first configuration, determining the occurrence of a ground-to-neutral fault; and
in a second configuration determining the occurrence of a differential ground fault, wherein determining the occurrence of
the differential ground fault includes:

generating an input current to the transconductance amplifier in response to a value of the reflected impedance;
generating a first copy of the input current;
using the first copy of the input current to determine a value of the impedance, wherein using the first copy of the input
current to determine the value of the impedance includes determining a real component of the impedance;

generating a second copy of the input current; and
using the second copy of the input current to determine a reactive component of the impedance.

1. A method of making a semiconductor device, the method comprising:
providing a lead frame, the lead frame comprising:
an internal region comprising an island and two or more leads;
an outer frame surrounding the internal region and defining an outer periphery of the lead frame;
two or more connection portions connecting the internal region and the outer frame; and
a notch formed in an edge of the outer frame that is closest to the internal region, wherein the notch is between two of the
connection portions, and wherein the notch is spaced apart from each of the connection portions;

die-bonding a semiconductor die to the internal region of the lead frame;
electrically connecting the semiconductor die and the lead frame;
sealing the semiconductor die bonded to the lead frame within an encapsulating resin; and
cutting the lead frame to form a semiconductor device, wherein cutting the lead frame comprises cutting through the notch
formed in the outer frame of the lead frame.

1. An image sensor pixel, comprising:
a photodiode that generates charge in response to image light;
a floating diffusion node;
a charge transfer transistor configured to transfer the generated charge from the photodiode to the floating diffusion node;
an amplifying transistor having a drain terminal coupled to a pixel output node, wherein the floating diffusion node is coupled
between a drain terminal of the charge transfer transistor and a gate terminal of the amplifying transistor;

a feedback capacitor coupled between the pixel output node and the floating diffusion node, wherein the amplifying transistor
is configured to provide the transferred charge with a greater than unity gain and the feedback capacitor is configured to
provide negative voltage feedback to the floating diffusion node; and

a pre-charge capacitor coupled between the floating diffusion node and a pre-charge bus line.

4. An array of pixels, comprising:
a substrate having an array of photodiodes;
an array of color filters over the array of photodiodes; and
vertical dielectric walls between the color filters, wherein the dielectric walls do not extend over the color filters, wherein
the array of photodiodes has a center, and wherein the widths of the dielectric walls increases with increasing distance from
the center of the array of photodiodes.

1. A method of forming a semiconductor device comprising:
providing a semiconductor substrate of a first conductivity type;
forming a first doped region of a second conductivity type on the semiconductor substrate;
forming a second doped region of the first conductivity type overlying the first doped region the second doped region having
a first surface that is opposite to the first doped region;

forming a third doped region having the second conductivity type on the first surface of the second doped region;
forming a fourth doped region of the first conductivity type in the third doped region;
forming one or more gate structures extending through the fourth doped region;
forming a plurality of termination trenches extending through the third doped region and into the first doped region wherein
the plurality of termination trenches surround the first, second, third, and fourth doped regions and the one or more gate
structures; and

removing a portion of the semiconductor substrate to expose the first doped region.

1. An electronic device comprising:
a buried conductive region;
a semiconductor layer having a primary surface and an opposing surface, wherein the buried conductive region is disposed closer
to the opposing surface than to the primary surface;

a horizontally-oriented doped region adjacent to the primary surface;
a first vertical conductive region adjacent to the primary surface and extending through the semiconductor layer toward the
buried conductive region, wherein the first vertical conductive region is electrically connected to the horizontally-oriented
doped region and the buried conductive region;

a first insulating layer overlying the horizontally oriented doped region;
a conductive electrode overlying the first insulating layer and the horizontally-oriented doped region; and
a gate electrode of a power transistor, wherein the gate electrode is spaced apart from and electrically isolated from the
conductive electrode, wherein the first vertical conductive region does not underlie the conductive electrode.

1. A stacked-chip image sensor, comprising:
a semiconductor substrate having opposing first and second surfaces;
an array of image sensor pixels in the semiconductor substrate that are configured to receive image light through the first
surface; and

control circuitry coupled to the array of image sensor pixels by a plurality of vertical conductive interconnects that extend
through the second surface, the array of image sensor pixels comprising image sensor pixels arranged in pixel rows and pixel
columns, and the plurality of vertical conductive interconnects comprising a plurality of vertical column interconnects, wherein
each pixel column is coupled to a selected one of the vertical column interconnects.

1. A method for processing a first image and a second image comprising:
receiving first pixel information corresponding to the first image from a first image generator;
receiving second pixel information corresponding to the second image from a second image generator;
determining a first contrast value corresponding to only a portion of the first image based on the first pixel information;
determining a second contrast value corresponding to only a portion of the second image based on the second pixel information;
selecting one of the first and second images responsive to the first and second contrast values;
generating a first tone mapping function based on the first and second contrast values for modifying contrast of the selected
one of the first and second images, wherein the first and second contrast values are determined according to the following:

wherein “H” is the luminance channel histogram and “I” is the luminance channel image of the corresponding first or second
image; and
generating compensated image pixel information corresponding to the selected one of the first and second images by applying
the first tone mapping function to the pixel information corresponding to the selected one of the first and second images.

1. A HEMT semiconductor device comprising:
a substrate having a primary surface;
a GaN film overlying the primary surface of the substrate;
a dielectric layer overlying the GaN film, wherein the dielectric layer includes a first silicon nitride film overlying the
GaN film, and an AlN film on the first silicon nitride film; and

a gate electrode disposed above the dielectric layer such that a line vertically bisecting the gate electrode intersects the
first silicon nitride film and the AlN film.

1. An image sensor, comprising:
an array of image pixels in which each image pixel in a first set of image pixels includes a microlens having a first common
size and each image pixel in a second set of image pixels includes a microlens having a second common size that is different
from the first common size, wherein each image pixel in the first and second sets of image pixels includes a color filter
element having a common size.

1. A process of forming an electronic device comprising:
providing a first semiconductor layer over a substrate, wherein:
the substrate includes a first dopant of a first conductivity type at a first dopant concentration;
the first semiconductor layer includes a first portion closer to the substrate and a second portion further from the substrate;
the first portion includes a second dopant of the first conductivity type at a second dopant concentration that is lower than
the first dopant concentration; and

the second portion has no dopant or includes a third dopant of the first conductivity type at a third dopant concentration
that is lower than the second dopant concentration;

forming a first doped region within the first semiconductor layer, wherein the first doped region has a second conductivity
type opposite that of the first conductivity type; and

forming a second semiconductor layer over the first doped region,
wherein in a finished electronic device, a first diode is formed at a pn junction between the first doped region and the substrate.

1. An image sensor, comprising:
an array of image pixels having a plurality of light-receiving image pixels and a plurality of dark image pixels that are
optically shielded, wherein each dark image pixel has floating diffusion node with a floating diffusion capacitance that receives
a test signal via capacitive coupling to an associated signal node, wherein the floating diffusion capacitance of each dark
image pixel is set to a predetermined level, and wherein the predetermined level of floating diffusion capacitance of a first
dark image pixel is different than the predetermined level of floating diffusion capacitance of a second dark image pixel.

1. An image sensor, comprising:
a graded n-type epitaxial substrate layer;
a plurality of photodiodes formed in the graded n-type epitaxial substrate layer;
a plurality of isolation trenches in the graded n-type epitaxial substrate layer that separate adjacent photodiodes;
a reflective layer; and
a dielectric stack on the reflective layer, wherein the reflective layer is interposed between the plurality of photodiodes
and the dielectric stack.

1. A method of forming an image sensor with isolation regions in an image sensor substrate, comprising:
depositing a plurality of layers onto an upper surface of the image sensor substrate, wherein the plurality of layers comprises
at least a first layer formed from a first material, a second layer formed from a second material, a third layer formed from
a third material, and a fourth layer formed from a fourth material, and wherein the first layer is interposed between the
upper surface of the image sensor substrate and the second layer;

implanting a first set of ions into the image sensor substrate through the first and second layers;
after implanting the first set of ions into the image sensor substrate, removing the second layer;
after removing the second layer, implanting a second set of ions into the image sensor substrate through the first layer;
implanting a third set of ions into the image sensor substrate through the first, second, and third layers; and
implanting a fourth set of ions into the image sensor substrate through the first, second, third, and fourth layers.

1. A semiconductor device comprising:
a region of semiconductor material of a first conductivity type having a major surface;
a trench extending into the region of semiconductor material from the major surface;
a first dielectric layer formed within the trench and adjacent sidewall surfaces of the trench, wherein the first dielectric
layer comprises a first shield layer, a gate layer and a second shield layer;

a first shield electrode in a bottom portion of the trench and overlying a portion of the first dielectric layer and spaced
apart from the sidewall surfaces of the trench by the first shield layer;

a gate electrode in the trench and overlying the first shield electrode and spaced apart from the sidewall surfaces of the
trench by the gate layer;

a second shield electrode in the trench and overlying the gate electrode and spaced apart from the sidewall surfaces of the
trench by the second shield layer;

a body region of a second conductivity type formed within the region of semiconductor material, adjacent the gate electrode
and spaced apart from the gate electrode by the gate layer, and spaced apart from the major surface; and

a lower electrode adjoining a portion of a lower surface of the region of semiconductor material of the first conductivity
type and an upper electrode adjoining a portion of the major surface of the region of semiconductor material of the first
conductivity type, wherein the second shield electrode is electrically connected to the lower electrode and wherein the first
shield electrode is electrically connected to the upper electrode.

1. A semiconductor structure comprising:
a substrate of a first material type, the substrate having a first surface and a second surface;
a first semiconductor region comprising a Group III-nitride material on the first surface of the substrate and including a
first fin structure, the first fin structure comprising:

a generally horizontal first top surface;
a recessed surface portion adjacent the first top surface; and
first sidewall surfaces extending between the recessed surface portion and the first top surface, the first sidewall surfaces
being sloped so that a base portion of the first fin structure is wider than the first top surface;

a second semiconductor region comprising a Group III-nitride material disposed over the first fin structure;
a gate conductor overlying at least part of the recessed surface portion;
a first current carrying electrode electrically coupled to the second semiconductor region along at least the first top surface;
and

a shield conductor above and insulated from the gate conductor.

1. An analog to digital conversion circuit that converts an analog voltage signal into a multiple bit digital value representing
the analog voltage signal, the circuit comprising:
successive approximation register (SAR) conversion circuitry including a comparator configured to receive the analog voltage
signal, wherein the comparator includes an input for receiving the analog voltage signal, at least one other input, and at
least one output, the SAR conversion circuitry generating a first subset of bits of the multiple bit digital value representing
the analog voltage signal; and

ramp conversion circuitry including the comparator, the ramp conversion circuitry generating a second subset of bits of the
multiple bit digital value representing the analog voltage signal, wherein the second subset of bits is different than the
first subset of bits, and wherein the SAR conversion circuitry further comprises:

a SAR coupled to the at least one output of the comparator;
a memory associated with the SAR, the SAR configured to store the at least one bit of the multiple bit digital value in the
memory;

a digital to analog converter (DAC) coupled to the at least one other input of the comparator; and
a SAR controller, wherein the SAR controller includes a first input coupled to the output of the comparator, a second input
coupled to the SAR, and an output coupled to the DAC, wherein the SAR controller is configured to adjust the DAC to generate
a SAR comparison voltage level at the at least one other input of the comparator, determine a SAR voltage level associated
with the bits, and present the SAR voltage level at the at least one other input of the comparator for use by the ramp conversion
circuitry.

1. A semiconductor component, comprising:
a semiconductor material having a major surface;
an electrically conductive structure over a portion of the major surface;
an electrical interconnect having a top surface and opposing edges, wherein tapered portions of the opposing edges are in
contact with the electrically conductive structure; and

a protective structure on the top surface and the opposing edges of the electrical interconnect and on a portion of the electrically
conductive structure, wherein the protective structure forms first and second L-shaped portions laterally adjacent vertical
portions of the opposing edges of the electrical interconnect, the first L-shaped portion adjacent a first vertical edge portion
of the electrical interconnect and having a first subportion that extends away from the first vertical edge portion of the
electrical interconnect and the second L-shaped portion adjacent a second vertical edge portion of the electrical interconnect
and having a subportion that extends away from the second vertical edge portion of the electrical interconnect, and wherein
the protective structure forms a seal that protects the electrical interconnect, wherein the seal completely seals the electrical
interconnect so that the electrical interconnect is devoid of corrosion that degrades the reliability of the semiconductor
component.

1. A method for color compensation in multi-view video comprising:
sensing a first video sequence in a master channel;
sensing a second video sequence in a slave channel;
wherein the first and second video sequences are acquired from a common scene of interest;
generating a set of global color ratio statistics from the master channel and the slave channel, wherein the global color
ratio statistics are based on a ratio of master channel image data to master channel image size and a ratio of slave channel
image data to slave channel image size, and wherein the slave channel image size depends on the similarity between a master
channel image and a slave channel image;

calculating at least one compensation gain based upon the set of global color ratio statistics; and
applying the at least one compensation gain to the slave channel to obtain a gain-compensated first slave channel.

1. A sound amplification system, comprising:
a controller configured to control one or more output signals to excite a detachable device;
one or more information inputs of the controller configured to receive one or more information signals from the detachable
device wherein the one or more information signals are selectively representative of codes of the detachable device; and

the controller configured to selectively set the controller to one of initiate a wireless connection with an external device
in response to a first value of the codes or to initiate a method for a user action or to operate in one of a master mode
or slave mode wherein operation in the master mode is initiated in response to receiving the one or more information signals
representing the first value of the codes and operation in the slave mode is initiated in response to receiving the one or
more information signals representing a second value of the codes, the master mode including the controller configured to
send signals to control an operation of an external device operating in the slave mode.

1. A method of forming a semiconductor die comprising:
providing a semiconductor wafer having a semiconductor substrate and having a plurality of semiconductor die formed on the
semiconductor substrate and separated from each other by portions of the semiconductor substrate where singulation lines are
to be formed, the semiconductor substrate having a first surface and a second surface;

forming an opening through a first semiconductor die of the plurality of semiconductor die wherein the opening has sloped
sidewalls so that a width of the opening is greater at one end of the opening than at an opposite end of the opening; and

forming a first conductor on the sloped sidewalls of the opening and forming an electrical connection between the first conductor
and at least a portion of the sloped sidewall.

1. An image sensor, comprising:
a substrate;
digital circuitry on a first portion of the substrate;
analog circuitry on a second portion of the substrate;
an array of image pixels on a third portion of the substrate;
an intermetal dielectric stack attached to the substrate; and
at least one trench isolation structure in the substrate that electrically isolates the analog circuitry from the digital
circuitry, wherein the at least one trench isolation structure is interposed between the first portion of the substrate and
the second portion of the substrate, and wherein the at least one trench isolation structure comprises dielectric material
formed in a trench in the substrate.

1. An input-output circuit that connects a USB connector and an internal circuit to each other, the USB connector being configured
by five pins including an identification terminal used for identifying a connected accessory device, a data plus terminal
and a data minus terminal that form a differential pair, a power supply terminal, and a ground terminal, the input-output
circuit comprising:
a power supply detecting circuit for determining whether the connected accessory device includes a charger by detecting a
feeding of power from outside of the input-output circuit;

an identification terminal voltage detecting circuit that detects a voltage of the identification terminal produced by a current
provided by the identification terminal voltage detecting circuit being provided to an identification resistance in the connected
accessory device;

a control unit that controls a charging circuit for charging an electronic device connected to the input-output circuit using
the power supply terminal and the ground terminal when the accessory device includes a charger and controls a switching unit
in accordance with the connected accessory device based on a detection result acquired through the identification terminal
voltage detecting circuit; and

a video switch that is inserted into a signal line connecting a video circuit included in the internal circuit and the identification
terminal, wherein

the USB connector can be connected to a video cable including one video signal line and two stereo audio signal lines, the
identification terminal can be connected to the video signal line, and the data plus terminal and the data minus terminal
can be connected to the stereo audio signal lines, and

when a first voltage representing that the video cable is connected to the USB connector is detected by the identification
terminal voltage detecting circuit and then a second voltage representing that the video cable is terminated with specified
impedance is detected corresponding to an external display device, the control unit turns on the video switch.

1. A method of manufacturing a semiconductor device, comprising:
providing a device intermediate comprising a semiconductor substrate, a first insulation layer disposed on a front surface
of the semiconductor substrate and a pad electrode disposed on the first insulation layer;

forming a first opening in the semiconductor substrate from a back surface thereof so that the first insulation layer is exposed
at a bottom of the first opening and that the first opening has a maximum lateral size thereof in a position closer to the
front surface than to the back surface;

removing the exposed first insulation layer to form a second opening so that the pad electrode is exposed at a bottom of the
second opening and that a lateral size of the second opening increases from the pad electrode toward the first opening, the
first opening and the second opening forming a via hole penetrating the semiconductor substrate and the first insulation layer;
and

cutting the device intermediate so as not to cut through the via hole and so as to produce a semiconductor device having the
via hole therein.

1. A semiconductor device comprising:
a semiconductor region of a first conductivity type;
a trench extending from a first major surface of the semiconductor region;
a first dielectric layer at least along lower sidewall surfaces of the trench, but not along upper sidewall surfaces of the
trench;

a first conductive layer disposed on at least a portion of upper sidewall surfaces of the trench;
a second conductive layer disposed in the trench overlying at least portions of the first dielectric layer;
a gate dielectric layer overlying the first major surface;
a third conductive layer overlying the gate dielectric layer;
a first region of a second conductivity type adjacent the trench and spaced apart from the major surface, wherein:
the first conductive layer is configured as a first electrode of a Schottky diode structure, and wherein at least a portion
of the semiconductor region adjacent the first conductive layer is configured as a second electrode of the Schottky diode
structure;

the semiconductor region, gate dielectric layer, and the third conductive layer are configured as a first MOS structure; and
the first region and the semiconductor region are configured as a first diode structure.

1. A method for adjusting a current sense (CS) amplifier, increasing a common mode rejection ratio (CMRR) and reducing a gain
error of the CS amplifier as compared to an unadjusted CS amplifier, the method comprising:
measuring a first referred to input (RTI) offset voltage while presenting a given common mode (CM) input voltage to both an
inverting input and a non-inverting input of the CS amplifier;

adding a first trim resistor of a plurality of selectable trim resistors within an adjustable feedback resistor chain to a
feedback electrical path of the adjustable feedback resistor chain, said adjustable feedback resistor chain coupling an output
of a differential amplifier within the CS amplifier to an inverting input of the differential amplifier;

measuring, after adding the first trim resistor, a second RTI offset voltage while presenting the given CM input voltage to
both the inverting input and the non-inverting input of the CS amplifier;

estimating, based upon the first and second RTI offset voltages, a third RTI offset voltage value that would result by adding
a second trim resistor of the plurality of selectable trim resistors to the feedback electrical path;

using the first, second and third RTI offset voltage values to identify the combination of selectable trim resistors that
achieves an RTI offset voltage closest to zero volts as compared to other combinations of selectable trim resistors; and

adding the identified selectable trim resistors to the feedback electrical path.

1. A method of forming a semiconductor die comprising:
providing a semiconductor wafer including a bulk semiconductor substrate having a top surface and a bottom surface;
forming a plurality of semiconductor die on the top surface of the silicon bulk semiconductor substrate with at least one
die of the plurality of semiconductor die having regions for forming two substantially straight sides that intersect to form
a first corner having a substantially curved shape and other regions for forming one or more other corners of the semiconductor
die having a different shape than the first corner;

forming a singulation region as a region of the semiconductor wafer that is between the semiconductor die; and
using a dry etch to form an opening through the silicon bulk semiconductor substrate to simultaneously singulate the plurality
of semiconductor die and form at least the first corner, the one or more other corners, and the two substantially straight
sides.

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type;
a first doped region of a second conductivity type opposite to the first conductivity type on the semiconductor substrate;
a second doped region of the first conductivity type adjacent the first doped region;
a cathode region of the second conductivity type within the second doped region;
an anode region of the first conductivity type within the cathode region;
a first electrode electrically coupled to the anode region; and
a second electrode electrically coupled to the cathode region and the second doped region, wherein the first doped region
is configured as a floating region.

1. A semiconductor device comprising:
a semiconductor substrate;
a first semiconductor region formed as a doped region overlying the semiconductor substrate;
a drift region formed as a first doped region of a first conductivity type within the first semiconductor region and overlying
the semiconductor substrate, the drift region having a first doping concentration;

a first drain region formed as a second doped region of the first conductivity type within the drift region, the first drain
region having a second doping concentration that is greater than the first doping concentration;

a second drain region of the first conductivity type within the first drain region, the second drain region having a third
doping concentration that is greater than the second doping concentration;

a body region of a second conductivity type in the first semiconductor region and spaced laterally apart from the drift region;
a source region of the first conductivity type in the body region; and
a buried region of the second conductivity type underlying the source region, at least a portion of the body region, and at
least a portion of the drift region but not underlying the first drain region and the second drain region.

1. An image sensor pixel formed on a semiconductor substrate, comprising:
a photodiode that generates charge in response to image light, wherein the photodiode extends across a lateral area of the
semiconductor substrate;

a floating diffusion region formed at a location on the semiconductor substrate that is substantially centered with respect
to the lateral area; and

a charge transfer gate that is formed within the lateral area on the semiconductor substrate, wherein the charge transfer
gate is interposed between the floating diffusion region and the photodiode and configured to transfer the generated charge
from the photodiode to the floating diffusion region.

1. A color electronic imager comprising:
a pixel sensor array formed on a substrate;
a plurality of elements of a color filter array (CFA) containing pigments forming multiple color filter patterns on the pixel
sensor array; and

a silylating agent formed between respective elements of at least first and second ones of the multiple color filter patterns.

1. A method of singulating semiconductor die from a semiconductor wafer comprising:
providing a semiconductor wafer having a plurality of semiconductor die formed on the semiconductor wafer and separated from
each other by spaces, wherein the semiconductor wafer has first and second opposing major surfaces, and wherein a layer of
material is formed along the second major surface, and wherein the layer of material comprises a conductive material;

placing the semiconductor wafer onto a first carrier substrate, wherein the layer of material is adjacent the first carrier
substrate;

singulating the semiconductor wafer through the spaces to form singulation lines, wherein singulating includes stopping in
proximity to the layer of material; and

separating portions of the layer of material proximate to the singulation lines using a fluid.

1. An IGBT comprising:
a semiconductor substrate having a first surface and a second surface that is disposed opposite to the first surface;
a first doped region of a first conductivity type overlying the first surface wherein a first P-N junction is formed along
the first doped region;

a second doped region of the first conductivity type on the second surface of the semiconductor substrate and extending a
first distance into the semiconductor substrate;

a third doped region having a second conductivity type in the second doped region and extending a second distance into the
second doped region;

a plurality of termination trenches in a termination region of the semiconductor device, the plurality of termination trenches
surrounding an outer perimeter of the second doped region and extending from the second surface toward the first surface wherein
at least a portion of an end of one or more termination trenches of the plurality of termination trenches extends through
the first surface; and

a plurality of gate structures extending through the third doped region and into the second doped region.

1. An electronic device comprising:
an electronic component region; and
a termination region adjacent to the electronic component region and including:
a substrate including a buried conductive region having a first conductivity type;
a vertical region overlying the substrate, wherein the vertical region includes a doped vertical region having the first conductivity
type, and wherein the doped vertical region overlies and is electrically connected to the buried conductive region;

a semiconductor layer having a thickness, a primary surface and an opposite surface, wherein:
the semiconductor layer overlies the substrate; and
the substrate is closer to the opposite surface than the primary surface; and
an insulating region that extends a depth into the semiconductor layer, wherein the depth is less than 50% of the thickness
of the semiconductor layer.

1. A method of determining a capacitance of a device having a first terminal and a second terminal, comprising:
connecting the first terminal of the device to a first channel of an oscilloscope;
connecting a first terminal of a capacitor having a known capacitance to the first terminal of the device;
connecting a second terminal of the device to a second channel of the oscilloscope;
connecting a second terminal of the capacitor to a third channel of the oscilloscope;
supplying an alternating current (AC) voltage to the first terminal of the device and the first terminal of the capacitor;
determining a voltage as a function of time across the device while supplying the AC voltage from information collected by
the first channel of the oscilloscope;

determining a current through the device from information collected by the second channel of the oscilloscope while supplying
the AC voltage to the first terminal of the device;

determining a current through the capacitor from information collected by the third channel of the oscilloscope while supplying
the AC voltage to the first terminal of the capacitor;

computing a capacitance of the device as a function of time by multiplying the capacitance of the capacitor by the ratio of
the current through the device to the current through the capacitor;

determining a capacitance of the device as a function of voltage based on the computed capacitance as a function of time and
the voltage across the device as a function of time; and

outputting data of the capacitance of the device as a function of voltage.

1. An imager including a self test mode comprising: a pixel array for providing pixel output signals, a plurality of analog-to-digital
converters (ADCs) for converting the pixel output signals into pixel digital data, a digital processor for processing the
pixel digital data, and a multiplexer for receiving a test signal and the pixel digital data, wherein the multiplexer provides
the test signal to the digital processor for testing the imager.

1. Image sensor pixel circuitry, comprising:
a first floating diffusion region;
a second floating diffusion region; and
first and second control transistors coupled in series between the first and second floating diffusion regions, wherein the
first control transistor has a first source-drain terminal that is coupled to the first floating diffusion region and a second
source-drain terminal that is coupled to an intermediate node, and wherein the second control transistor has a first source-drain
terminal that is coupled to the second floating diffusion region and a second source-drain terminal that is coupled to the
intermediate node; and

a reset transistor having a first source-drain terminal that is coupled to the intermediate node and a second source-drain
terminal at which a reset voltage is applied.

1. An image sensor integrated circuit, comprising:
a substrate,
a plurality of arrays of image pixels on the substrate;
first row control circuitry on the substrate that is configured to operate the image pixels of a first portion of the plurality
of arrays of image pixels to capture image data;

second row control circuitry on the substrate that is configured to operate the image pixels of a second portion of the plurality
of arrays of image pixels to capture additional image data;

a first line buffer for storing the image data from the image pixels of the first portion of the plurality of arrays of image
pixels; and

a second line buffer for storing the image data from the image pixels of the second portion of the plurality of arrays of
image pixels, wherein the second line buffer is different from the first line buffer, and the first and second line buffers
are respectively capable of storing the image data from the image pixels of the first and second portion of the plurality
of arrays of image pixels simultaneously.

1. An extended common mode (CM) input voltage range current sense amplifier, comprising:
a low voltage (LV) p-type metal oxide semiconductor (PMOS) input module coupled to a positive supply rail, wherein said positive
supply rail provides a voltage comprising the maximum between a positive input signal (IN+) voltage applied to the amplifier
and an internal power supply voltage; and

a voltage regulator coupled to the positive supply rail that generates a decreased voltage level relative to the positive
supply rail voltage that is provided to the LV PMOS input module via a high voltage ground (HV_GND) line,

wherein at least part of the LV PMOS input module is powered by a voltage difference between the positive supply rail and
the HV_GND line, and

wherein the voltage regulator maintains said voltage difference within an operating range of one or more LV devices within
the LV PMOS input module.

1. Imaging circuitry, comprising:
an analog-to-digital converter circuit that produces a digital output code from an analog input voltage and comprises a plurality
of capacitors and an additional capacitor having a given capacitance, wherein the plurality of capacitors comprises a first
capacitor and a set of capacitors, wherein the first capacitor has a first capacitance, wherein each of the capacitors in
the set of capacitors has a capacitance that is equal to the first capacitance multiplied by some power of 2, and wherein
the given capacitance is greater than the capacitances of each of the capacitors in the plurality of capacitors and less than
twice the capacitance of a capacitor in the plurality of capacitors that has the largest capacitance; and

digital processing circuitry that generates a digital output value from the digital output code from the analog-to-digital
converter circuit.

1. An imaging device having an image pixel array with a plurality of phase detection pixels arranged consecutively in a line,
wherein the plurality of phase detection pixels comprises:
first and second photosensitive regions formed in a substrate and covered by a first microlens; and
third and fourth photosensitive regions formed in the substrate and covered by a second microlens, wherein the first microlens
is directly adjacent to the second microlens and wherein the second and third photosensitive regions are interposed between
the first and fourth photosensitive regions, wherein the first microlens has a first optical axis, wherein the second microlens
has a second optical axis, wherein the first and second photosensitive regions are offset from the first optical axis, and
wherein the third and fourth photosensitive regions are offset from the second optical axis.

1. A semiconductor device comprising:
a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region
on a first side of the conductive substrate and second elevated region on the first side of the conductive substrate, wherein
the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the
second elevated region comprises a second planar surface on the first side of the conductive substrate; and

a semiconductor die comprising a first contact pad electrically coupled to the conductive substrate, wherein the first contact
pad is soldered to both the first planar surface of the first elevated region and the second planar surface of the second
elevated region, and wherein the first planar surface of the first elevated region has different dimensions than the second
planar surface of the second elevated region, and wherein the first planar surface of the first elevated region has a first
corner that is laterally aligned with a first corner of the first contact pad.

1. A semiconductor die comprising:
a semiconductor substrate having a first surface and a second surface wherein the semiconductor substrate includes a bulk
silicon semiconductor substrate and a silicon semiconductor material overlying the bulk silicon semiconductor substrate;

a doped region formed in at least a portion of the silicon semiconductor material;
an opening extending through the semiconductor die including through the bulk silicon semiconductor substrate and through
the semiconductor material overlying the bulk silicon semiconductor substrate, the opening having sidewalls wherein the sidewalls
include rough sidewalls and at least one sidewall is a sloped sidewall so that a width of a first end of the opening is greater
than a width of an opposite end of the opening; and

a first conductor on the sloped sidewall.

1. An electronic device comprising:
a buried conductive region;
a semiconductor layer having a primary surface and an opposing surface, wherein the buried conductive region is disposed closer
to the opposing surface than to the primary surface, and the semiconductor layer defines a first trench having a sidewall
and being adjacent to the primary surface and extending toward the buried conductive region;

a first horizontally-oriented doped region adjacent to the primary surface, wherein the first horizontally-oriented doped
region is at least part of a drain region or a collector of a first transistor structure;

a first insulating layer overlying the first horizontally-oriented doped region;
a conductive electrode overlying the first insulating layer;
a first capacitor structure including:
a first capacitor electrode including a first vertical conductive region adjacent to the sidewall of the first trench and
extending toward the buried conductive region, wherein the vertical conductive region is electrically connected to the first
horizontally-oriented doped region and the buried conductive region;

a capacitor dielectric layer; and
a second capacitor electrode within the first trench,
wherein the first capacitor structure is spaced apart from and does not underlie the conductive electrode, and wherein the
electronic device comprises a power transistor.

1. An imager, comprising:
an imaging die that receives light, wherein the imaging die comprises a pixel array that is arranged in rows and columns;
an image processing die that is stacked with the imaging die and processes output image signals from the imaging die; and
a plurality of through-silicon vias in the imaging die that electrically couple the imaging die to the image processing die,
wherein each of the plurality of through-silicon vias is coupled to a corresponding one of the columns in the pixel array.

1. A pixel array, comprising:
an imaging pixel having a floating diffusion region; and
ramp circuitry that provides a ramp signal to the floating diffusion region of the imaging pixel, wherein the imaging pixel
comprises

a photodiode;
a transfer gate that is coupled between the photodiode and the floating diffusion region;
a source-follower transistor having a gate terminal coupled to the floating diffusion region;
supply circuitry;
a row select transistor coupled between the ramp circuitry and the floating diffusion region; and
a reset transistor coupled between the floating diffusion region and the supply circuitry wherein the reset transistor has
a gate terminal that receives a reset signal, wherein the supply circuitry provides a control signal to a source-drain terminal
of the reset transistor, and wherein the reset transistor uses the reset signal and the control signal to selectively enable
and disable the source-follower transistor.

12. A circuit comprising:
a high-side transistor having a first current-carrying electrode and a second current-carrying electrode;
a low-side transistor having a first current-carrying electrode and a second current-carrying electrode, wherein the first
current-carrying electrode of the low-side transistor is coupled to the second current-carrying electrode of the high-side
transistor;

a first rectifying element having an anode and a cathode, wherein the cathode of the first rectifying element is coupled to
the second current-carrying electrode of the high-side transistor;

a second rectifying element having an anode and a cathode, wherein the anode of the second rectifying element is coupled to
the first current-carrying electrode of the low-side transistor; and

a first charge storage element having a first terminal and a second terminal, wherein the first terminal of the first charge
storage element is coupled to the first current-carrying electrode of the high-side transistor, and the second terminal of
the first charge storage element is coupled to the anode of the first rectifying element; and

a second charge storage element having a first terminal and a second terminal, wherein the first terminal of the second charge
storage element is coupled to the cathode of the second rectifying element, and the second terminal of the second charge storage
element is coupled to the second current-carrying electrode of the low-side transistor,

wherein:
a parasitic characteristic between a negative terminal of the circuit and the first charge storage element is more significant
than a parasitic characteristic between the high-side transistor and the first charge storage element; or

a parasitic characteristic between a positive terminal of the circuit and the second charge storage element is more significant
than a parasitic characteristic between the low-side transistor and the second charge storage element; and

wherein:
the first rectifying element is closer to the high-side transistor than to a negative terminal of the circuit; or
the second rectifying element is closer to the low-side transistor than to a positive terminal of the circuit.

1. A driver circuit suitable for driving a motor, comprising:
an output control circuit having first and second inputs and an output;
an output circuit having first and second inputs and a plurality of outputs configured for coupling to a plurality of coils
of a 2-phase stepping motor; and

a detecting circuit having a plurality of inputs and at least a first output, wherein first and second inputs of the plurality
of inputs of the detecting circuit are coupled to first and second outputs of the plurality of outputs of the output circuit,
respectively, the first output coupled to the second input of the output control circuit and the second output coupled to
the second input of the output circuit, wherein the detecting circuit generates an adjustment signal at its first output in
response to detecting an induced voltage at a first coil of the plurality of coils during a period when the first coil is
in a high-impedance state and a second coil of the plurality of coils is driven with a first duty ratio.

1. A switch circuit to be mounted in a device having a common terminal which allows insertion of a terminal of a cable for
transmitting high-frequency signals and insertion of a terminal of a cable dedicated to the transmission of audio signals,
the switch circuit comprising:
a high-frequency signal switch capable of switching between passage and no passage of high-frequency signals, wherein the
high-frequency signal switch comprises a pair of series connected MOSFETs; and

a bidirectional audio signal switch dedicated to switching between passage and no passage of audio signals, wherein the bidirectional
audio signal switch comprises a pair of series connected MOSFETs,

wherein a signal line from the common terminal is branched into one line connected to one end of said high-frequency signal
switch and another line connected to one end of an audio signal switch in a primary hierarchical position,

wherein a signal line from the other end of said high-frequency signal switch is connected to a target circuit, and
wherein a signal line from the other end of the audio signal switch in the primary hierarchical position is branched into
a plurality of lines,

the respective plurality of lines are connected to one end of a plurality of audio signal switches in a secondary hierarchical
position,

the respective signal lines from the other end of the plurality of audio signal switches in the secondary hierarchical position
are connected to respective target circuits,

the high-frequency signal switch is of a first type having a center potential that is clamped to a supply voltage when the
high-frequency signal switch is in an off state and not allowing passage of the high-frequency signals and disconnected from
the supply voltage when in the high-frequency signal switch is in an on state and allowing passage of the high-frequency signals,
and wherein the audio signal switch is of a second type having a center potential than is clamped to a ground when in an off
state and disconnected from ground when in an on state and allowing passage of the audio signals.

1. An optical accelerometer, comprising:
an image sensor; and
light-guide structures on the image sensor, wherein the light-guide structures include optical elements that extend over the
image sensor, wherein the optical elements are configured to move when the light-guide structures are moved, wherein each
of the optical elements comprises a first end that receives light from a light source and that remains in a fixed position
such that the first end does not move with respect to the image sensor during motion of the optical accelerometer and a second
end opposite the first end that directs light onto the image sensor and that moves with respect to the image sensor in response
to the motion of the optical accelerometer, and wherein the image sensor is configured to capture images of light from the
light-guide structures during the motion; and

processing circuitry configured to extract acceleration information from the captured images.

1. A current saturation detection and clamping circuit, comprising:
a switch having a control terminal and first and second conduction terminals;
a first amplifier having first and second inputs and first and second outputs, the first input coupled to the second conduction
terminal of the switch and the first output coupled to the control terminal of the switch;

a first impedance coupled between the second input of the first amplifier and the first conduction terminal of the switch;
and

a ground fault circuit interrupter engine having first and second inputs, the first input coupled to the first conduction
terminal of the switch and the second input coupled to the second conduction terminal of the switch.

1. An apparatus for powering an electrical load, comprising:
a driver module comprising:
a buck converter module, operably connected to an electrical load, and comprising at least one energy storage module;
a first switch configured to operably couple a power source to the buck converter module during a first operating state occurring
over a first time period;

a second switch configured to operably couple the buck converter module to the electrical load during a second operating state
occurring over a second time period;

wherein an operating cycle comprises the first operating state and the second operating state;
a first current sensor configured to sense an electrical current provided to the electrical load while the apparatus is operating
in the first state, and output a first current sensed signal; and

a second current sensor configured to sense the electrical current provided to the electrical load while the apparatus is
operating in the second state, and output a second current sensed signal; and

a regulating module operable to instruct and regulate the time periods during which each of the first switch and the second
switch are configured into at least one of the first operating state and the second operating state such that a maximum current
and a minimum current provided by the buck converter module to the load over a given operating cycle are symmetrically disposed
about an average current provided to the load during the given operating cycle.

1. A method for regulating an output voltage, comprising:
generating an input current that flows through a first inductor in response to a load condition on a converter and a switching
activity of a switching device;

generating a current indicator signal that is a representation of a level of the input current;
limiting a switching frequency of the switching device in response to the current indicator signal and to a sense signal generated
in response to an input voltage signal;

operating the converter in a critical conduction mode in response to the current indicator signal being greater than a first
reference voltage, wherein in the critical conduction mode the input current increases from a first level to a second level
over a first period of time, decreases from the second level to the first level over a second period of time, increases from
the first level to the second level over a third period of time, and decreases from the second level to the first level over
a fourth period of time;

operating the converter in a frequency fold-back mode in response to the current indicator signal being less than the first
reference voltage, wherein in the frequency fold-back mode the input current increases from a third level to a fourth level
over a fifth period of time in response to the controller generating a drive signal and the switching device being on, the
input current decreases from the fourth level to the third level over a sixth period of time in response to the controller
generating the drive signal that turns off the switching device, the input current remains at the third level over a seventh
period of time in response to the controller generating the drive signal that leaves the switching device off, and the input
current increases from the third level to the fourth level over an eighth period of time in response to the controller generating
the drive signal that turns on the switching device.

1. An imaging system, comprising:
a substrate having an array of photodiodes arranged in rows and columns, wherein the array comprises a first set of photodiodes
and a second set of photodiodes that is different from the first set of photodiodes;

a first set of color filter elements, wherein each color filter element in the first set is formed over a respective photodiode
in the first set of photodiodes, wherein the first set of photodiodes is configured to generate image data in response to
light received through the first set of color filter elements;

a second set of color filter elements formed over the second set of photodiodes, wherein the second set of color filter elements
is offset with respect to the first set of color filter elements, wherein the second set of photodiodes is configured to generate
auto-focus data in response to light received through the second set of color filter elements, wherein each color filter element
in the second set of color filter elements is formed over an associated pair of photodiodes in the second set of photodiodes,
wherein the second set of photodiodes comprise a row of photodiodes in the array of photodiodes, and wherein the row of photodiodes
is interposed between at least two rows of photodiodes from the first set of photodiodes.

1. An off-line power converter, comprising:
integrated circuit power factor controller including:
a multi-function input terminal, wherein said multi-function input terminal is adapted to receive a voltage representative
of a voltage proportional to a current flowing through a drive transistor and upon a voltage produced by a voltage sensing
circuit;

a drive terminal for providing a drive signal to a gate of a drive transistor;
a processing circuit coupled to said multi-function input terminal and, based on a voltage on said multi-function input terminal,
providing at least one current signal representative of a current conducted in the off-line power converter, and at least
one voltage signal representative of a voltage provided to a load; and

a controller for providing said drive signal selectively in response to said at least one current signal and said at least
one voltage signal.

1. A process of forming an electronic device comprising:
providing a substrate including a lightly doped region at a primary surface, wherein the lightly doped region has a first
conductivity type;

forming a tunnel dielectric layer over the substrate;
forming a second electrode of the tunnel structure over the tunnel dielectric layer, wherein at least a part of the second
electrode has the first conductivity type;

forming a first intermediate doped region within a portion of the lightly doped region, wherein the first intermediate doped
region is at the primary surface, abuts the lightly doped region, has a second conductivity type opposite the first conductivity
type, and has a dopant concentration that is greater than a dopant concentration of the lightly doped region;

forming a first heavily doped region at the primary surface, wherein the first heavily doped region abuts the first intermediate
doped region and has the second conductivity type and a concentration that is higher than the first intermediate doped region;

forming a second heavily doped region at the primary surface, wherein the second heavily doped region is at the primary surface,
contacts the lightly doped region, has the first conductivity type and a concentration that is higher than the first intermediate
doped region, wherein from a top view, the first heavily doped region is disposed between the first intermediate doped region
and the second heavily doped region; and

forming a second intermediate doped region spaced apart from the first intermediate doped region, wherein:
the second electrode has a first side and a second side;
the first intermediate doped region is disposed closer to the first side than the second side;
the second intermediate doped region is disposed closer to the second side than the first side; and
the second electrode overlies a portion of the first intermediate doped region and a portion of the second intermediate doped
region.

1. A method for operating a stacked-chip image sensor, wherein the stacked-chip image sensor comprises a planar array of image
sensor pixels, an array of vertical conductive vias, and processing circuitry coupled to the planar array of image sensor
pixels through the array of vertical conductive vias, the method comprising:
with the image sensor pixels, capturing a first set of image data;
providing the captured first set of image data to the processing circuitry using the array of vertical conductive vias;
with the processing circuitry, storing the first set of image data;
with the image sensor pixels, capturing a second set of image data;
with the processing circuitry, determining a motion score for the second set of image data by comparing the second set of
image data to the stored first set of image data; and

with the processing circuitry, generating an output image using the determined motion score, wherein the output image has
a first region with a first effective integration time and a second region with a second effective integration time.

1. A method for capturing images with an image sensor having multi-storage pixels, wherein each multi-storage pixel has a
photodiode, at least first and second storage nodes, and a floating diffusion node, for each multi-storage pixel the method
comprising:
transferring from the photodiode at least first and second pluralities of charge portions to the at least first and second
storage nodes, respectively;

summing the first plurality of charge portions to produce a first stored charge at the first storage node;
summing the second plurality of charge portions to produce a second stored charge at the second storage node;
transferring the first stored charge from the first storage node to a floating diffusion node;
reading out the first stored charge from the floating diffusion node as a first pixel signal having a first exposure time,
without resetting the floating diffusion node;

transferring the second stored charge from the second storage node to the floating diffusion node;
reading out a sum of the first and second stored charges from the floating diffusion node as a second pixel signal having
a second exposure time, wherein the at least first and second storage nodes comprise first, second, third, and fourth storage
nodes and wherein the at least first and second pluralities of charge portions comprise first, second, third, and fourth pluralities
of charge portions, without resetting the floating diffusion node;

transferring the third stored charge from the third storage node to the floating diffusion node;
reading out a sum of the first, second and third stored charges from the floating diffusion node as a third pixel signal having
a third exposure time, without resetting the floating diffusion node;

transferring the fourth stored charge from the fourth storage node to the floating diffusion node; and
reading out a sum of the first, second, third, and fourth stored charges from the floating diffusion node as a fourth pixel
signal having a fourth exposure time.

1. A method of improving quality of an audio circuit, the method comprising:
configuring the audio circuit to monitor the state of an output subsystem for driving an output transducer based on a system
clock, the output transducer for outputting audio sound;

configuring the audio circuit to monitor an event affecting the frequency of the system clock; and
configuring the audio circuit to, in response to the event, synchronize the timing of the change of the clock frequency based
on the state of the output subsystem to reduce or eliminate audio artifacts including configuring the audio circuit to initiate
the change of the clock frequency in response to the state of the output subsystem, and in response to the state of the output
subsystem indicating possible audio artifacts, modify the state of the output subsystem to create the timing of the change
of the clock frequency.

1. An instruction execution circuit, comprising:
a processor for providing addresses to an address bus and transferring data over a data bus for fetching and executing instructions;
a memory having a first plurality of memory locations allocated to a first predetermined portion of a memory map and an enable
input for receiving a first enable signal, wherein the memory goes into a low power mode when the first enable signal is inactive;

a register having a second plurality of memory locations allocated to a second predetermined portion of the memory map and
an enable input for receiving a second enable signal;

an address decoder having an input coupled to the address bus, for activating the first enable signal when an address provided
by the processor is in the first predetermined portion of the memory map, and activating the second enable signal when an
address provided by the processor is in the second predetermined portion of the memory map;

wherein the memory stores a plurality of instructions including a jump instruction to one of the second plurality of memory
locations; and

wherein the register stores a loop of instructions starting from the one of the second plurality of memory locations and returning
to the one of the second plurality of memory locations.

1. A semiconductor device structure comprising:a semiconductor substrate having first and second opposing major surfaces, wherein the semiconductor substrate includes:
a floating buried doped region of a first conductivity type;
a first doped region of a second conductivity type disposed between the floating buried doped region and the first major surface; and
a semiconductor region of the second conductivity type disposed between the floating buried doped region and the second major surface;
a trench isolation structure extending from the first major surface through the first doped region, extending through the floating buried doped region, and extending into the semiconductor region, wherein:
the floating buried doped region abuts the trench isolation structure; and
the trench isolation structure defines a perimeter for an active region of the semiconductor device structure;
an insulated trench structure extending from the first major surface through the first doped region and terminating within the floating buried doped region, wherein:
the insulated trench structure is disposed within the perimeter of the trench isolation structure;
the insulated trench structure defines a first portion and a second portion of the active region; and
the floating buried doped region electrically couples the first portion and the second portion of the active region together;
a first semiconductor device disposed within the first doped region and within the second portion of the active region;
a first conductive electrode electrically coupled to the first semiconductor device; and
a second conductive electrode electrically coupled to the first portion of the active region, wherein:
the second conductive electrode, the first portion of the active region, and the floating buried doped region form a bias semiconductor device configured to set a potential of the floating buried doped region.

1. An imaging system comprising:
a time-delay-and-integrate (TDI) image sensor comprising (i) a plurality of identical integrating CCDs (ICCDs), arranged in
parallel and abutting each other, that accumulate photocharge in response to exposure to light, (ii) electrically coupled
to the plurality of ICCDs, a readout CCD (RCCD) for receiving photocharge from the plurality of ICCDs, and (iii) electrically
coupled to the RCCD, readout circuitry for converting charge received from the RCCD into voltage;

an optical system for receiving light from a scene to be imaged and projecting it on the plurality of ICCDs; and
wherein each ICCD comprises (i) a plurality of independently controllable stages, (ii) a photosensitive channel for containing
photocharge and a channel stop to produce a barrier to separate each ICCD from adjacent ICCDs, (iii) for each of a plurality
of charge collection regions, a sense node located between the photosensitive channel and the channel stop for measuring photocharge
received thereby from the photosensitive channel, and (iv) for each of the plurality of charge collection regions, a gate
for controlling flow of photocharge from the photosensitive channel to the sense node, and

the imaging system comprises, for each charge collection region, a spillover charge measurement circuit to alternatively reset
the sense node and measure a charge in the sense node of an associated charge collection region.

1. An image sensor, comprising:
a substrate having a surface;
first and second adjacent photodiodes formed in the substrate, wherein the first and second photodiodes form a portion of
the surface;

a floating diffusion region that is formed between the first and second photodiodes; and
a buried light shield structure that is formed on the substrate over the floating diffusion region and that makes direct physical
contact with the surface of the substrate.

1. A camera module, comprising:
an anamorphic lens having a corresponding image circle and a corresponding compression ratio; and
an image sensor having a square image pixel array arranged in pixel columns and pixel rows, wherein the square image pixel
array includes more pixel columns than pixel rows, wherein the square image pixel array is located entirely within the image
circle of the anamorphic lens, and wherein the square image pixel array comprises:

a plurality of rectangular image pixels having a height and a width, wherein a ratio of the height to the width is based on
the compression ratio of the anamorphic lens, and wherein the ratio of the height to the width is between 0.7 and 0.8.

1. A semiconductor component, comprising a common mode filter monolithically integrated with a protection device, the common
mode filter comprising:
a first coil having first and second terminals;
a second coil having first and second terminals, the first terminal of the second coil coupled to the first terminal of the
first coil, the first coil magnetically coupled to the second coil;

the protection device having a first terminal coupled to the first terminal of the first coil and a second terminal coupled
to the first terminal of the second coil; and
wherein the protection device further comprises a first capacitor coupled between the first terminal and the second terminal
of the first coil and a second capacitor coupled between the first terminal and the second terminal of the second coil.

1. A chopper-stabilized amplifier comprising:
a first operational transconductance amplifier;
a first chopper circuit coupled to an input of the first operational transconductance amplifier for chopping an input signal
and applying a chopped input signal to the input of the first operational transconductance amplifier;

a second chopper circuit coupled to an output of the first operational transconductance amplifier for chopping an output signal
produced by the first operational transconductance amplifier; and

a symmetrical passive RC notch filter with two cutoff frequencies having an input coupled to an output of the second chopper
circuit to filter a chopped output signal produced by the second chopper circuit to notch filter ripple voltages received
from the output of the second chopper circuit

wherein the symmetrical passive RC notch filter includes first and second inputs, wherein the symmetrical passive RC notch
filter includes first and second outputs, and wherein the symmetrical passive RC notch filter includes:

a first path including a first resistor coupled between the first input and a first node, and a second resistor coupled between
the first node and a second node;

a second path including a first capacitor coupled between the first input and a third node, and a second capacitor coupled
between the third node and the second node;

a third path including a third resistor coupled between the second input and a fourth node, and a fourth resistor coupled
between the fourth node and a fifth node;

a fourth path including a third capacitor coupled between the second input and a sixth node, and a fourth capacitor coupled
between the sixth node and the fifth node;

a fifth resistor coupled between the third node and the sixth node and a fifth capacitor coupled between the first node and
the fourth node.

1. A system for analyte measurement, comprising:
a transimpedance amplifier including a first input terminal configured for operatively coupling to an output of a sensor for
sensing an analyte, a second input terminal coupled to a voltage source, and an output terminal that provides an output based
on a difference between first and second inputs on the first input terminal and the second input terminal;

a differential programmable gain amplifier (DPGA) having a first input terminal coupled to the output of the output terminal
of the transimpedance amplifier and a second input terminal coupled to a reference voltage source and that provides an output
based on a difference between the first and second input terminals of the DPGA, the DPGA including first and second programmable
buffers with each of the first and second terminals of the DPGA coupled to an output of a respective one of the first and
second programmable buffers wherein the first and second programmable buffers each have a plurality of selectable operation
ranges where each selectable operation range has a different linearity region and wherein at least one operation range of
the plurality of selectable operation ranges is selected responsive to a control signal; and

a controller operatively coupled to the DPGA, wherein the controller forms a state of the control signal responsively to an
input common mode voltage of each of the first and second programmable buffers, the control signal coupled between the controller
and the first and second programmable buffers.

1. A method of forming a semiconductor device structure comprising:
providing a semiconductor substrate having a major surface;
forming a first region comprising pillars of first and second conductivity type doped material extending in a generally vertical
orientation with respect to the major surface, wherein the first conductivity type is opposite to the second conductivity
type, and wherein the first pillar is configured as a vertical current path;

providing a second region of the first conductivity type spaced apart from the major surface, wherein the second region adjoins
a lower portion of the first region;

forming a third region of the second conductivity type, wherein the third region adjoins the first region between the major
surface and the second region;

forming a body region overlying a portion of the third region;
forming a source region adjoining the body region; and
forming a control electrode adjacent the body region and the source region, wherein the control electrode is configured to
control a channel region within the body region but not within the third region.

1. An image sensor having an array of image pixels, comprising:
a substrate;
an array of photodiodes formed in the substrate;
an array of microlenses formed over the array of photodiodes;
an array of color filter elements interposed between the array of microlenses and the array of photodiodes;
a grid of baffles that extend above the array of microlenses, wherein the grid of baffles is configured to block stray light
from reaching the array of image pixels; and

a material formed over the array of microlenses, wherein the material has a planar surface and wherein the baffles are formed
on the planar surface.

1. A method for producing an image sensor, comprising:
providing a horizontal shift register electrically connected to a pixel array for receiving charge packets from the pixel
array;

providing a non-destructive sense node connected to an output of the horizontal shift register;
providing a charge directing switch electrically connected to the non-destructive sense node, wherein the charge directing
switch includes first and second outputs; and

providing a charge multiplying horizontal shift register electrically connected to the first output of the charge directing
switch.

1. A semiconductor device comprising:
a conductive substrate electrically coupled to a first lead, wherein the conductive substrate comprises a first elevated region
on a first side of the conductive substrate and a second elevated region on the first side of the conductive substrate, wherein
the first elevated region comprises a first planar surface on the first side of the conductive substrate, and wherein the
second elevated region comprises a second planar surface on the first side of the conductive substrate; and

a semiconductor die comprising a first contact pad electrically coupled to the conductive substrate, wherein the first contact
pad is soldered to both the first planar surface of the first elevated region and the second planar surface of the second
elevated region, and wherein only a portion of the first planar surface is soldered to the first contact pad.

1. An igniter circuit comprising:
an output configured for coupling to a primary side of an ignition coil;
a first circuit configured to form a drive signal to selectively enable or disable a load switch to control a load current
through the load switch;

a selectively enabled switch configured to receive a DC voltage and selectively couple or decouple the DC voltage to an internal
node and to the output;

a second circuit configured to monitor a load current through the load switch and detect the load current having a first value
that is no less than a threshold value;

a third circuit configured to disable the selectively enabled switch in response to the combined conditions of the first circuit
forming a signal to disable the load switch and the second circuit detecting that the load current is no less than the threshold
value; and

a diagnostic circuit configured to detect a failure of the selectively enabled switch and to responsively disable the load
switch.

1. A method for testing an image sensor having an array of image sensor pixels, comprising:
injecting a first signal into an image sensor pixel in the array;
sampling a first voltage corresponding to the first signal from the image sensor pixel;
injecting a second signal into the image sensor pixel;
sampling a second voltage corresponding to the second signal from the image sensor pixel;
assessing a validity of the first sampled voltage based on the second sampled voltage; and
in response to assessing that the first sampled voltage is invalid, withholding transmission of image signal data from the
image sensor pixel.

1. A method for manufacturing a semiconductor component, comprising:
providing a semiconductor material having a surface;
forming a passivation layer on the semiconductor material;
removing first and second portions of the passivation layer and portions of the semiconductor material exposed by removing
the first and second portions of the passivation layer;

forming a layer of dielectric material on the passivation layer and the exposed portions of the semiconductor material;
forming first and second cavities in the layer of dielectric material, the first cavity exposing a first portion of the semiconductor
material and having at least one sidewall configured as a portion of a field plate, the second cavity exposing a second portion
of the semiconductor material; and

forming a first electrode in the first cavity and a second electrode in the second cavity.

1. A semiconductor device comprising:
a region of semiconductor material having a major surface;
a trench extending from the major surface;
a first layer overlying surfaces of the trench;
a second layer adjacent the first layer, where the second layer comprises a material different than the first layer, and where
the second layer is disposed in a lower portion of the trench and not an upper portion of the trench, and where the second
layer is discontinuous in proximity to a lower surface of the trench;

a first region comprising a material different than the second layer in proximity to the lower surface of the trench;
a first electrode in the lower portion of the trench and adjacent portions of the second layer and the first region, where
portions of the first layer are between the first electrode and the region of semiconductor material;

a dielectric layer above the first electrode; and
a second electrode adjacent the first layer and the dielectric layer, where at least a portion of the second electrode is
within the trench.

1. A method for controlling an actuator, comprising:
providing a drive circuit having an input and a first input/output terminal and an actuator coupled to the first input/output
terminal;

causing the actuator to move in response to a first drive signal generated by a signal generator coupled to the input of the
drive circuit;

determining a resonant frequency and a ringing amplitude from a movement of the actuator using a ringing characteristic determination
circuit, wherein the ringing characteristic determination circuit has an input coupled to the first input/output terminal
of the drive circuit and to the actuator;

generating a second drive signal from the signal generator in response to resonant period data and ringing amplitude data
received from the ringing characteristic determination circuit and in response to actuator position data, wherein the actuator
position data is derived by summing or subtracting a new position of the actuator generated by a first position indicator
to or from a previous position of the actuator generated by a second position indicator; and

causing the actuator to move in response to the second drive signal.

1. A circuit for programming a fuse element comprising:
a memory cell having the fuse element that includes a first semiconductor material body region and a silicide layer;
a programming circuit configured to form a programming current to program the fuse element; and
a programming element configured to control a value of the programming current, the programming element having a second semiconductor
material body region but not a silicide layer;

the programming circuit configured to control the programming current to a first value responsively to a value of the fuse
element and to subsequently control the programming current to a different value responsively to a value of the programming
element.

1. A method of variable-rate encoding of image data, comprising:
capturing the image data using an array of image pixels having a corresponding array of color filter elements;
partitioning the captured image data into fixed-size blocks of image data;
separating each fixed-size block of image data into red, green, and blue color components;
performing a one dimensional discrete wavelet transform on the red and blue color components;
performing a discrete cosine transform on an output of the one dimensional discrete wavelet transform;
compressing each fixed-size block of image data; and
outputting an encoded bitstream for each fixed-size block at a fixed rate.

1. A power supply driver module comprising:a buck converter module coupled to provide electrical power in the form an output current and an output voltage, over one or more operating cycles, to a load;
wherein each of the one or more operating cycles includes an “on” period and an “off” period for the buck converter module;
a first switch configurable, over each of the one or more operating cycles, into a first operating state corresponding to the “on” period and a second operating state corresponding to the “off” period;
wherein, during the first operating state,
the first switch couples a power source to the buck converter module such that the buck converter can store electrical power provided by the power source while also providing, to the load, an output current which increases to a target maximum output current;
wherein, during the second operating state,
the first switch decouples the power source from the buck converter module;
a current sensor configured to sense the output current and output a current sense signal to a regulating module; and
a first switch control lead configured to receive a first switch control signal from the regulating module.

1. A process of forming an electronic device comprising:
providing a semiconductor layer;
forming a first insulating layer over the semiconductor layer;
forming a first conductive electrode member over the first insulating layer;
forming a patterned second insulating layer over the first conductive electrode member, wherein the patterned second insulating
layer defines an opening having a bottom; and

forming a conductive layer within the opening of the patterned second insulating layer, wherein the conductive layer fills
only part, and not all, of the opening;

forming a gate electrode of a transistor over the semiconductor layer, wherein:
forming the gate electrode is performed after forming the first conductive electrode member; and
forming the second conductive electrode member is performed after forming the gate electrode; and
anisotropically etching the conductive layer to remove the conductive layer from the bottom of the opening, wherein:
anisotropically etching the conductive layer forms a second conductive electrode member;
the second conductive electrode member lies along only a part, and not all, of the bottom of the opening; and
the first conductive electrode member abuts the second conductive electrode member.

1. A semiconductor device, comprising:
a close proximity zone flag circuit operable to assert a close proximity zone flag while a present period of a received signal
from an acoustic transducer is within a preselected range during a proximity window time period;

a time of flight circuit operable to produce a time of flight count based on a time period when a stream of present periods
of the received signal, after being low pass filtered, overcrosses a preselected threshold value; and

a close proximity time of flight valid flag circuit operable to compare the time of flight count to a valid time interval
threshold value and assert a close proximity time of flight valid flag when the time of flight count is within the valid distance
threshold interval.

1. A discharge circuit for discharging a voltage from a pin of a USB connector, the discharge circuit comprising:a discharge load coupled to the pin and configured to discharge the voltage on the pin;
a first control circuit coupled to the discharge load and configured to adjust a magnitude of the discharge load during discharging, such that a power consumption of the discharge load meets a first preset condition, and a discharge time is within a first preset range, the first preset condition indicating that the generated power consumption does not trigger Over Temperature Protection (OTP); and
a second control circuit coupled to the discharge load and configured to detect whether the voltage of the pin is changed based on a reference voltage during discharging and adjust the magnitude of the discharge load in response to the change, such that a slew rate of the voltage of the pin is within a second preset range.

18. A semiconductor device comprising:
a first transistor having a first current carrying electrode, a second current carrying electrode, and a control electrode;
a first bipolar transistor having a collector coupled to the first current carrying electrode of the first transistor, a base
coupled to the second current carrying electrode of the first transistor, and an emitter of the first bipolar transistor coupled
to a first terminal of the semiconductor device;

a component coupled between the control electrode of the first transistor and the emitter of the first bipolar transistor
wherein a first terminal of the component is connected directly to the control electrode of the first transistor such that
the component is coupled in series between the control electrode of the first transistor and a second terminal of the semiconductor
device; and

wherein the first transistor is one of a second bipolar transistor or a first MOS transistor, wherein the first bipolar transistor
has an emitter-collector breakdown voltage that is either no less than an emitter-collector breakdown voltage of the second
bipolar transistor or no less than a gate-to-source operating voltage of the first MOS transistor.

1. Imaging circuitry, comprising:
an image sensor die that includes:
a substrate;
a plurality of photosensitive elements formed in the substrate;
a plurality of microlenses formed over the photosensitive elements;
an external bond pad structure;
a dielectric layer interposed between the substrate and the external bond pad structure; and
a passivation layer that is formed directly on the plurality of microlenses and directly on the external bond pad structure.

1. A method for driving light-emitting elements, comprising:
providing m current paths coupled in a parallel configuration, wherein each current path includes a light-emitting element
and wherein m is an integer;

sequentially turning on and off a plurality of light-emitting elements in the m current paths, including turning on and off
a first light emitting element of the plurality of light emitting elements in a first current path of the m current paths
then turning on and off a second light-emitting element of the plurality of light emitting elements in a second current path
of the m current paths, wherein each light-emitting element is illuminated for a first light-emission time and wherein a sum
of the first light-emission times of the m light-emitting elements is a first light emission period; and

adjusting the first light-emission time to a second light emission time in response to a change in the first light-emission
period.

1. A method of defocusing a first image to produce a second image, the method comprising:
obtaining the first image and a depth map associated with the first image;
for each of a plurality of pixels of the first image and using the depth map, determining the distance between that pixel
and a focal plane in the second image;

for each of the plurality of pixels of the first image, identifying an associated sampling region that includes that pixel
and that has an area at least based on the distance between that pixel and the focal plane; and

for each of the plurality of pixels of the first image, identifying a given number of sample pixels that includes at least
that pixel and each of which lie within the associated sampling region of that pixel, wherein the given number of sample pixels
is substantially equal for all of the sample regions.