US Pat. No. 9,183,166

EXPANDABLE ASYMMETRIC-CHANNEL MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. An integrated circuit device for use in a memory system comprising memory sockets, the integrated circuit device comprising:
an internal data path formed by a first number of internal signaling links that convey data to be output from the integrated
circuit device;

a signaling interface having a second number of interface nodes to be coupled to the memory sockets via respective external
signaling links, the second number being greater than the first number; and

switch circuitry to switchably couple the internal data path to one of a plurality of different subsets of the interface nodes
in accordance with occupancy of the memory sockets, each of the different subsets of the interface nodes being constituted
by the same number of the interface nodes as the others of the different subsets of the interface nodes.

US Pat. No. 9,378,849

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A controller comprising:
an internal memory to store an address; and
a memory control unit operatively coupled with the internal memory, the memory control unit comprising logic to:
identify a malfunctioning address of primary data storage elements within an external memory device, the external memory device
being another semiconductor device separate from the controller,

store the malfunctioning address in the internal memory, and
transmit, to the external memory device, a command to initiate a repair of the malfunctioning address using redundant data
storage elements and an indication of an address associated with the malfunctioning address.

US Pat. No. 9,479,176

METHODS AND CIRCUITS FOR PROTECTING INTEGRATED CIRCUITS FROM REVERSE ENGINEERING

Rambus Inc., Sunnyvale, ...

16. A camouflage circuit instantiated on a substrate, the circuit comprising:
a signal generator to generate a transitioning signal; and
a buffer coupled to the signal generator, the buffer including electrically distinct reference elements that are visibly indistinct
from a perspective normal to a surface of the substrate, absent any overlying material layers, the buffer to output a camouflage
signal responsive to the transitioning signal.

US Pat. No. 9,294,262

RECEIVER CLOCK TEST CIRCUITRY AND RELATED METHODS AND APPARATUSES

Rambus Inc., Sunnyvale, ...

1. An integrated circuit, comprising:
a first receiver to receive a first signal from a first transmitter via a first transmission path and a first clock recovery
circuit to generate a first recovered clock from the first signal for use in sampling the first signal during a normal mode
of operation;

a second receiver to receive a second signal from a second transmitter via a second transmission path and a second clock recovery
circuit to generate a second recovered clock from the second signal for use in sampling the second signal during the normal
mode of operation; and

circuitry to apply adjustments to a clock signal generated by the first clock recovery circuit during a test mode of operation,
to deterministically-vary timing of the clock signal generated by the first clock recovery circuit during the test mode of
operation, and to provide the clock signal with the deterministically-varied timing to the second clock recovery circuit for
use as a reference clock during the test mode of operation.

US Pat. No. 9,356,743

METHOD AND APPARATUS FOR EVALUATING AND OPTIMIZING A SIGNALING SYSTEM

Rambus Inc., Sunnyvale, ...

1. An integrated circuit, comprising:
a receiver to serially receive a signal via at least one electrical conductor from a transmitter and to equalize the signal
using a set of equalization coefficients, the signal comprising a repeating test pattern during a test mode and a data signal
during a normal mode; and

circuitry to evaluate the repeating test pattern received by the receiver during the test mode against an expected pattern
to generate comparison outputs using first values of the set of equalization coefficients during a first time period and second
values of the set of equalization coefficients during a second time period;

where the receiver is to equalize the data signal during the normal mode using the first or the second values for the set
of equalization coefficients selected in dependence on the comparison outputs.

US Pat. No. 9,298,543

ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY DEVICE THAT GENERATES ERROR-DETECTION INFORMATION

Rambus Inc., Sunnyvale, ...

10. A method of operation in a solid state memory device, the method comprising:
receiving a write data bits in parallel, on rising and falling edges of a clock signal, and first error-detection information
from a controller, the first error-detection information encoded by the controller using the write data bits;

generating second error-detection information corresponding to the received write data bits;
comparing the first error-detection information with the second error-detection information;
signaling an error condition to the controller if comparing the first error-detection information with the second error-detection
information signals an error condition; and

performing a remedial action in the event of the error condition, the remedial action including disabling a write operation
of the write data bits in the event of the error condition.

US Pat. No. 9,256,279

MULTI-ELEMENT MEMORY DEVICE WITH POWER CONTROL FOR INDIVIDUAL ELEMENTS

RAMBUS INC., Sunnyvale, ...

1. A multi-element device, comprising:
a plurality of memory elements;
each memory element including:
a memory array;
access circuitry to control access to the memory array;
power control circuitry, including one or more control registers storing first and second control values, the power control
circuitry to control distribution of power to the access circuitry in accordance with the first control value stored in the
one or more registers, and to control distribution of power to the memory array in accordance with the second control value
stored in the one or more registers; and

sideband circuitry for enabling a host system to set at least the first control value and the second control value in the
one or more control registers.

US Pat. No. 9,160,346

AREA AND POWER EFFICIENT CLOCK GENERATION

Rambus Inc., Sunnyvale, ...

1. An apparatus comprising:
a plurality of integrated circuit dies, including a capacitive element;
first interconnect structures extending between respective pairs of the integrated circuit dies and coupled to one another;
and

second interconnect structures extending between the respective pairs of the integrated circuit dies and coupled to one another,
wherein the first plurality of interconnect structures and the second plurality of interconnect structures are coupled to
one another and to respective nodes of the capacitive element to form an LC (inductor-capacitor) tank circuit.

US Pat. No. 9,135,206

COMMAND-TRIGGERED ON-DIE TERMINATION

Rambus Inc., Sunnyvale, ...

1. A method of controlling a dynamic random access memory device (DRAM), the method comprising:
transmitting to the DRAM one or more commands that specify programming of a digital control value within the DRAM, the digital
control value indicating a termination impedance that the DRAM is to couple to a data interface of the DRAM in response to
receiving a write command and during reception of write data corresponding to the write command, and that the DRAM is to decouple
from the data interface after reception of the write data corresponding to the write command; and

transmitting to the DRAM a write command indicating that write data is to be sampled by the data interface of the DRAM during
a first time interval and, as a consequence of transmitting the one or more commands that specify programming of the digital
control value, to cause the DRAM to couple the termination impedance to the data interface during the first time interval
and decouple the termination impedance from the data interface after the first time interval.

US Pat. No. 9,160,350

INTEGRATED CIRCUIT COMPRISING A DELAY-LOCKED LOOP

RAMBUS INC., Sunnyvale, ...

1. An integrated circuit (IC), comprising:
first circuitry to generate a first clock signal by delaying an input clock signal by a first delay;
a set of delay elements to generate a set of delayed versions of the input clock signal, wherein each delayed version of the
input clock signal has a different delay;

a time-to-digital converter (TDC) to generate a code based on the first clock signal and the set of delayed versions of the
input clock signal;

one or more injection-locked oscillators (ILOs) having a set of injection locations, wherein an output of an ILO in the one
or more ILOs is provided as the output clock signal; and

a de-multiplexer to inject an injection signal into an injection location that is selected from the set of injection locations
based on the code, wherein the injection signal is generated based on the input clock signal.

US Pat. No. 9,087,568

MEMORY WITH MERGED CONTROL INPUT

Rambus Inc., Sunnyvale, ...

1. An integrated circuit memory component comprising:
first logic to assert a chip-select signal in response to detecting a transition of an externally-generated control signal
and to enable a predetermined number of transitions of a timing signal in response to detecting the transition of the externally-generated
control signal;

second logic to decode a command in response to assertion of the chip-select signal; and
circuitry to perform operations indicated by the command at respective times indicated by respective transitions of the timing
signal.

US Pat. No. 9,116,810

MARGIN TEST METHODS AND CIRCUITS

Rambus Inc., Sunnyvale, ...

1. A receiver comprising:
a data input to receive a data signal;
a first sampler having a first sampler input coupled to the data input, the first sampler to sample the data signal to produce
a first sampled data stream representing first historical bits;

a second sampler having a second sampler input coupled to the data input, the second sampler to sample the data signal to
produce a second sampled data stream representing second historical bits;

a data-weighting circuit coupled between the second sampler and the data input, the data-weighting circuit to apply a weighted
sum of a plurality of the second historical bits to the first sampler input and to the second sampler input; and

a comparison circuit to identify differences between the first sampled data stream and the second sampled data stream.

US Pat. No. 9,165,621

MEMORY SYSTEM COMPONENTS THAT SUPPORT ERROR DETECTION AND CORRECTION

Rambus Inc., Sunnyvale, ...

1. A method of operating a memory device, the method comprising:
receiving a write memory access command that specifies a write access of data and a write access of error information associated
with the data at a memory bank within the memory device;

receiving a base row address associated with the write memory access command; and
generating first and second row addresses based on the base row address;
wherein the write access of data accesses a first row in a first storage region of the memory bank based on the first row
address; and

wherein the write access of error information accesses a second row in a second storage region of the memory bank based on
the second row address.

US Pat. No. 9,826,638

LOAD REDUCED MEMORY MODULE

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
a data buffer component;
a circuit board comprising a plurality of device sites, the plurality of device sites being coupled to the data buffer component,
wherein each device site, of the plurality of device sites, is a location on the circuit board at which at least one respective
memory device is disposed; and

a command and address (CA) buffer component disposed on the circuit board, wherein the CA buffer component comprises:
a primary interface comprising a first pin to receive a local chip select (CS) signal and a second pin to receive a distant
chip select (CS) signal; and

a secondary interface to select a first set of one or more of the plurality of device sites when the local CS signal is received
on the first pin or a second set of one or more of the plurality of device sites when the distant CS signal is received on
the second pin.

US Pat. No. 9,111,587

STACKED MEMORY WITH REDUNDANCY

Rambus Inc., Sunnyvale, ...

1. A stacked memory comprising:
a first integrated circuit memory chip having first storage locations;
a second integrated circuit memory chip disposed in a stacked relationship with the first integrated circuit memory chip,
the second integrated circuit memory chip having second storage locations;

redundant storage including a first storage area dedicated to storing failure address information of failure address locations
in the first or second integrated circuit memory chips, the redundant storage including a second storage area dedicated to
storing data corresponding to the failure address locations; and

matching logic to match incoming data transfer addresses to the stored failure address information.

US Pat. No. 9,165,617

MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

Rambus Inc., Sunnyvale, ...

1. A memory controller comprising:
a memory interface for communicating with a memory device at a signaling rate;
a timing control circuit having inputs to receive respective first and second signal components of a memory access request,
the timing circuit having outputs to launch the respective first and second signal components at times that are staggered
to define an offset; and

wherein a value of the offset is based on the signaling rate.

US Pat. No. 9,136,826

INTEGRATED CIRCUIT COMPRISING FREQUENCY CHANGE DETECTION CIRCUITRY

RAMBUS INC., Sunnyvale, ...

1. An integrated circuit (IC), comprising:
first circuitry to generate a second clock signal based on a first clock signal, wherein the first clock signal has a first
clock frequency, and wherein the second clock signal has a second clock frequency that is an integral multiple of the first
clock frequency;

second circuitry to obtain samples by oversampling the first clock signal using the second clock signal; and
third circuitry to detect a change in the first clock frequency based on the samples.

US Pat. No. 9,116,210

INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE

RAMBUS INC., Sunnyvale, ...

1. An apparatus, comprising:
a first component to communicate at a first frequency, the first components comprising a receiving component to receive a
test signal at the first frequency and to output information derived from the test signal;

a data generating component coupled to receive the information from the first component and to generate test data responsive
to the information; and

a second component to transmit test data based on the information to at a second frequency different than the first frequency.

US Pat. No. 9,110,828

CHIP HAVING REGISTER TO STORE VALUE THAT REPRESENTS ADJUSTMENT TO REFERENCE VOLTAGE

Rambus Inc., Sunnyvale, ...

1. A method of configuring a plurality of flash memory devices disposed on a memory module, the method comprising:
reading parameter information from storage, the parameter information pertaining to at least one flash memory device of the
plurality of flash memory devices; and

for each flash memory device of the plurality of flash memory devices, storing a plurality of control values in respective
registers disposed on the flash memory device of the plurality of flash memory devices, and configuring a transceiver of the
flash memory device for operation using the plurality of control values stored in the respective registers disposed on the
flash memory device, wherein the control values stored in the respective registers include control values determined in accordance
with the parameter information read from storage.

US Pat. No. 9,215,103

PARTIAL RESPONSE RECEIVER AND RELATED METHOD

Rambus Inc., Sunnyvale, ...

1. A receiver comprising:
a first multiplexer having a first pair of multiplexer data inputs, a first-multiplexer select input, and a first-multiplexer
output;

a second multiplexer having a second pair of multiplexer data inputs, a second-multiplexer select input asynchronously coupled
to the first-multiplexer output, and a second-multiplexer output; and

a storage circuit having a storage-circuit input coupled to the second-multiplexer output, a clock input, and a storage-circuit
output coupled to the first-multiplexer select input.

US Pat. No. 9,047,942

NON-TRANSITORY COMPUTER-READABLE MEDIA DESCRIBING A HYBRID VOLATILE AND NON-VOLATILE MEMORY DEVICE WITH AN OVERLAPPING REGION OF ADDRESSABLE RANGE OF STORAGE CELLS

Rambus Inc., Sunnyvale, ...

1. Non-transitory computer-readable media having information embodied therein that includes a description of an integrated
circuit device, the information comprising descriptions of:
a volatile storage die having a first addressable range of storage cells;
a non-volatile storage die having a second addressable range of storage cells that defines an overlapping region with the
first addressable range of storage cells; and

an interface circuit coupled to the volatile and non-volatile storage die to selectively transfer data stored in the overlapping
region of storage cells between the die.

US Pat. No. 9,378,787

MEMORY CONTROLLERS, SYSTEMS, AND METHODS SUPPORTING MULTIPLE REQUEST MODES

Rambus Inc., Sunnyvale, ...

1. A memory controller to direct requests to sections of a memory die, via respective channels, the memory controller comprising:
for each one of the respective channels, at least one queue to schedule issuance of respective ones of the requests to a corresponding
one of the sections of the memory die;

logic to receive the requests from a host and to steer each request to the at least one queue for one of the respective channels
according to a corresponding one of the sections of the memory die to be accessed according to the request; and

for each one of the respective channels, interface circuitry to transmit requests from the at least one queue to the corresponding
one of the sections, via the one of the respective channels;

wherein each section of the memory die includes banks, and wherein
the memory controller is to transmit requests to each bank of the memory die no more frequently than once during a first interval
of time,

the logic is to steer each request to a corresponding bank in the corresponding one of the sections of the memory die, and
the interface circuitry for each one of the respective channels is to transmit the respective ones of the requests from the
at least one queue via the one of the respective channels in a manner threaded between banks of the corresponding one of the
sections of the memory die, at a rate that is greater than once per first interval of time.

US Pat. No. 9,349,422

SUPPORTING CALIBRATION FOR SUB-RATE OPERATION IN CLOCKED MEMORY SYSTEMS

Rambus Inc., Sunnyvale, ...

1. An apparatus to calibrate a clocked memory system, comprising:
a calibration mechanism to perform a calibration operation at a first frequency to determine a first calibration state for
a delay between a clock signal and a corresponding data signal in the clocked memory system;

wherein the calibration mechanism is to use the first calibration state to determine a second calibration state, which is
different than the first calibration state, for operation of the clocked memory system at a second frequency; and

wherein the clocked memory system is to use the second calibration state when the clocked memory system is operating at the
second frequency.

US Pat. No. 9,257,151

PRINTED-CIRCUIT BOARD SUPPORTING MEMORY SYSTEMS WITH MULTIPLE DATA-BUS CONFIGURATIONS

Rambus Inc., Sunnyvale, ...

1. A printed-circuit board comprising:
a circuit mounting location for an integrated circuit comprising a memory controller;
a first module connector on the printed-circuit board, the first module connector to accept a first memory module having a
first data bus width, the first data bus width specifying a first number of data bit lines;

a second module connector on the printed-circuit board, the second module connector to accept a second memory module having
the first data bus width;

a first set of system data lines, fewer than the first number of data bit lines, extending directly to the first module connector
from the circuit mounting location without connection to the second module connector;

a second set of system data lines, fewer than the first number of data bit lines, extending directly to the second module
connector from the circuit mounting location without connection to the first module connector; and

a third set of system data lines, fewer than the first number of data bit lines, extending directly to the first module connector
from the second module connector without connection to the circuit mounting location.

US Pat. No. 9,141,479

MEMORY SYSTEM WITH ERROR DETECTION AND RETRY MODES OF OPERATION

Rambus Inc., Sunnyvale, ...

1. A method of transmitting data to a dynamic random access memory device, comprising:
at a memory controller coupled to the dynamic random access memory device:
generating an error detection code for data to be transmitted;
transmitting the data and error detection code to the dynamic random access memory device in a normal mode of operation;
receiving an error indication from the dynamic random access memory device;
in response to the error indication, retransmitting the data in a remedial mode of operation to the dynamic random access
memory device using a modified transmission parameter, the modified transmission parameter selected from the group consisting
of voltage, current, timing, and data rate, such that the data is transmitted differently in the remedial mode of operation
as compared to the normal mode of operation; and

exiting the remedial mode of operation after retransmitting the data in the remedial mode of operation.

US Pat. No. 9,083,280

TECHNIQUES FOR PHASE DETECTION

Rambus Inc., Sunnyvale, ...

1. A circuit comprising:
a phase detector input circuit to receive first and second periodic signals and to generate phase detector input signals,
the phase detector input signals comprising the first periodic signal and a delayed second periodic signal when a clock signal
is in a first logic state, and the phase detector input signals comprising the second periodic signal and a delayed first
periodic signal when the clock signal is in a second logic state;

a phase detector to receive the phase detector input signals and to generate a phase comparison signal indicative of a phase
difference between the first and second periodic signals, wherein the phase comparison signal has a non-zero value in response
to the phase detector input signals being aligned in phase; and

an output circuit to receive the phase comparison signal and to generate based on the phase comparison signal, an output signal
having a zero value when the first and the second periodic signals are aligned in phase.

US Pat. No. 9,262,342

PROCESS AUTHENTICATED MEMORY PAGE ENCRYPTION

Rambus Inc., Sunnyvale, ...

1. A method of securing contents of a memory comprising:
encrypting, by a memory controller, contents of a page frame of the memory based at least in part on a frame key associated
with the page frame;

generating, by the memory controller, a first encrypted version of the frame key based at least in part on a first process
key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table
associated with the first process; and

generating, by the memory controller, a second encrypted version of the frame key different from the first encrypted version
of the frame key based at least in part on a second process key associated with a second process and different from the first
process key, wherein the second encrypted version of the frame key is stored in a second memory table associated with the
second process, the first process and the second process sharing access to the page frame using the first encrypted version
of the frame key and the second encrypted version of the frame key, respectively.

US Pat. No. 9,137,063

HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION

Rambus Inc., Sunnyvale, ...

1. A system comprising:
a transmitter having transmit pre-emphasis circuitry with a plurality of transmit filter taps;
a receiver to receive a signal from the transmitter via a channel, the channel having a channel length, the receiver having
a decision-feedback equalizer having at least one filter tap, the receiver further comprising a linear equalizer coupled between
the channel and the decision-feedback equalizer and having at least one linear equalizer tap, the plurality of transmit filter
taps further including an adjustable filter tap of an adjustable symbol latency, the adjustable filter tap having a pre-cursor
latency in a first equalization mode and a post-cursor latency in a second equalization mode, the system further comprising
tap control logic coupled to the at least one linear equalizer tap and the adjustable filter tap of the transmit pre-emphasis
circuitry; and

where the system supports a training mode for link training operations and at least the first and second equalization modes
for data transfer operations, including the first equalization mode where the transmit pre-emphasis circuitry and the decision-feedback
equalizer are activated, and the second equalization mode where the transmit pre-emphasis circuitry is activated and the decision-feedback
equalizer is deactivated, and where a selection between the first equalization mode and the second equalization mode is based
on the channel length.

US Pat. No. 9,135,160

DEVICES, SYSTEMS, AND METHODS FOR WEAR LEVELING MEMORY

Rambus Inc., Sunnyvale, ...

1. A system for performing wear leveling, the system comprising:
a memory;
one or more wear leveling engines;
one or more wear leveling policies;
a decision engine having a write traffic signature mechanism; and
wherein the decision engine selects a wear leveling mechanism based upon:
receiving a write traffic signature of the memory from the write traffic signature mechanism wherein the write traffic signature
comprises data that is a function of a number of writes to the memory,

receiving status data from the memory;
wherein the wear leveling mechanism includes a wear leveling engine selected from the one or more wear leveling engines and
a wear leveling policy selected from the one or more wear leveling policies.

US Pat. No. 9,111,612

DIRECT RELATIVE MEASUREMENT OF MEMORY DURABILITY

Rambus Inc., Sunnyvale, ...

1. A method comprising:
selecting a first group of memory cells in a memory;
while the first group of memory cells are in a predetermined test state, measuring a first metric indicative of a remaining
endurance of the first group of memory cells;

selecting a second group of memory cells in the memory;
while the second group of memory cells are in the predetermined test state, measuring a second metric indicative of a remaining
endurance of the second group of memory cells;

comparing the first and second metrics; and
forming a result responsive to the comparing step.

US Pat. No. 9,111,645

REQUEST-COMMAND ENCODING FOR REDUCED-DATA-RATE TESTING

Rambus Inc., Sunnyvale, ...

1. A memory device, comprising:
a signal connector to electrically couple to a command/address (CA) link;
an interface circuit, electrically coupled to the signal connector, to receive CA packets via the CA link, each CA packet
including N CA bits, where N is an integer greater than 1;

a receiver having two operating modes, wherein, during a first operating mode, the receiver samples each of the N CA bits
at respective sample times using full-field sampling, at a first sampling rate, and, during the second operating mode, the
receiver samples only a subset of the N bits at selected sample times using sub-field sampling, at a second sampling rate
that is less than the first sampling rate; and

storage having storage cells that, in the first operating mode, are accessed via an address defined by the sampled N CA bits,
and in the second operating mode, are accessed via a portion of a partial address defined by the subset of the N CA bits.

US Pat. No. 9,275,733

METHODS AND SYSTEMS FOR MAPPING A PERIPHERAL FUNCTION ONTO A LEGACY MEMORY INTERFACE

Rambus Inc., Sunnyvale, ...

15. A system, comprising:
a central processing unit (CPU) with a memory controller configured to direct delivery of module data from the CPU to module
memory using parallel data channels; and,

a dual-inline memory module (DIMM) configured to receive the module data from the CPU, including:
a processor to receive the module data to be processed from a first memory on the module that is associated with a first aperture
and to receive the module data to be processed from a second memory on the module that is associated with a second aperture,
the processor initiate accesses of the first memory on the module, the processor to initiate accesses of the second memory
on the module; and,

a memory interface configured to interface with the memory controller using parallel data channels, the memory interface including
a memory data interface and a memory command/address interface, the memory data interface to operate bidirectionally, the
memory command/address interface to operate unidirectionally, the host to provide the data to be processed to the memory controller
for provision to the module via the memory interface, the module configurable to provide the processor with access to the
first memory concurrent with the memory controller accessing the second memory, and the module configurable to provide the
processor with access to the second memory concurrent with the memory controller accessing the first memory.

US Pat. No. 9,257,161

MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY

Rambus Inc., Sunnyvale, ...

1. A memory controller to control a memory device having first and second storage arrays, the memory controller comprising:
circuitry to receive commands for execution by the memory device;
circuitry to selectively delay each of the commands; and
circuitry to transmit each of the selectively-delayed commands to the memory device as a sequence of the commands;
wherein the circuitry to selectively delay each of the commands is
to delay each given command if the given command and any prior command in the sequence separated from the given command by
less than a predetermined time interval are directed to a same one of the first and second storage arrays, and

to not delay the given command if
(a) the given command and
(b) all prior commands in the sequence separated from the given command by less than the predetermined time interval,
are such that (a) and (b) are directed to different ones of the first and second storage arrays; and
wherein the selectively-delayed commands comprise distinct row access commands and column access commands, and wherein the
memory controller can transmit a row access command directed to the first storage array contemporaneous with transmission
of a column access command directed to the second storage array, and can transmit a column access command directed to the
first storage array contemporaneous with transmission of a row access command directed to the second storage array.

US Pat. No. 9,110,596

FAST-WAKE MEMORY

Rambus Inc., Sunnyvale (...

14. A memory device comprising:
first command signaling circuitry to receive memory access commands from a memory controller at a first command-signaling
frequency of the memory device;

power-state logic to transition the memory device to a first power mode in which at least part of the first command signaling
circuitry is disabled; and

second command signaling circuitry to receive at least one memory access command from the memory controller during a transitional
interval in which the at least part of the first command signaling circuitry is re-enabled.

US Pat. No. 9,094,028

WIDE RANGE FREQUENCY SYNTHESIZER WITH QUADRATURE GENERATION AND SPUR CANCELLATION

Rambus Inc., Sunnyvale, ...

1. A circuit comprising:
a first phase-locked loop circuit to receive a reference signal having a first frequency and generate an intermediate signal
having a second frequency;

a feedforward circuit to receive a control signal from the first phase-locked loop circuit and generate a feedforward signal;
and

a second phase-locked loop circuit to receive the intermediate signal having the second frequency and the feedforward signal,
and generate an output signal having a third frequency based on the intermediate signal and the feedforward signal.

US Pat. No. 9,491,391

IMAGE SENSOR WITH THRESHOLD-BASED OUTPUT ENCODING

Rambus Inc., Sunnyvale, ...

1. A method of operation within an integrated-circuit image sensor having a pixel array, the method comprising:
determining, for each of a plurality of pixels within the pixel array, whether charge integrated within the pixel in response
to incident light during a first interval exceeds a first threshold;

generating a first plurality of N-bit digital samples corresponding to the charge integrated during the first interval within
at least a subset of the plurality of pixels; and

indexing a first lookup table using the first plurality of N-bit digital samples to retrieve respective M-bit digital values,
M being less than N and wherein a stepwise range of charge integration levels represented by possible states of the M-bit
digital values extends upward from a first starting charge integration level determined based at least in part on the first
threshold.

US Pat. No. 9,299,407

ON-DIE TERMINATION OF ADDRESS AND COMMAND SIGNALS

RAMBUS INC., Sunnyvale, ...

1. A system comprising:
a plurality of memory devices arranged in a fly-by topology, each of the memory devices having on-die termination (ODT) circuitry
for connecting to an address and control (RQ) bus, the ODT circuitry of each memory device including a set of one or more
control registers for controlling on-die termination of one or more signal lines of the RQ bus;

wherein a first memory device of the plurality of memory devices includes a first set of one or more control registers to
store a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the
first memory device and a second memory device of the plurality of memory devices includes a second set of one or more control
registers to store a second ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry
of the second memory device.

US Pat. No. 9,390,798

1T-1R ARCHITECTURE FOR RESISTIVE RANDOM ACCESS MEMORY

Rambus Inc., Sunnyvale, ...

1. A method of operating an array of memory cells, comprising:
applying a selected source line voltage to a selected source line corresponding to a selected memory cell that is selected
for an operation;

applying an unselected source line voltage that is different from the selected source line voltage to unselected source lines
corresponding to unselected memory cells that are not selected for the operation;

applying a selected word line voltage to a selected word line corresponding to the selected memory cell; and
forming or setting the selected memory cell in response to applying the selected word line voltage to the selected word line;
wherein each memory cell includes a resistive memory element electrically coupled in series to a corresponding transistor
having a gate coupled to receive a corresponding one of a plurality of word lines and a source coupled to receive a corresponding
one of a plurality of source lines.

US Pat. No. 9,355,021

CROSS-THREADED MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. A multi-chip package comprising:
a logic integrated circuit (IC) die formed with plural memory controller circuits;
a memory including a first memory IC die and a second memory IC die, the second memory IC die mounted to the first memory
IC die, the first memory IC die and the logic IC die mounted to one another;

wherein the logic IC die includes a serial link interface for coupling to multiple serial links;a crossbar switch coupled to the serial link interface of the logic IC die; and
wherein the memory is partitioned into plural independently accessible memory groups and accessed concurrently via a corresponding
logic circuit.

US Pat. No. 9,411,678

DRAM RETENTION MONITORING METHOD FOR DYNAMIC ERROR CORRECTION

Rambus Inc., Sunnyvale, ...

1. A method of operation in an integrated circuit (IC) memory device, the method to monitor the validity of error information
associated with first data, the method comprising:
storing the first data in a first group of storage locations in the memory device;
storing the error information associated with the stored data in a second group of storage locations in the memory device;
evaluating the validity of the error information based on a state of an error enable bit, the state based on whether a most
recent access to the first group of storage locations involved a partial access;

identifying a faulty storage location based on the error information;
storing an address corresponding to the faulty storage location; and
repairing the faulty storage location for subsequent accesses by augmenting data stored in the faulty storage location with
error correction bits from a repair group of storage cells.

US Pat. No. 9,286,965

MEMORY REFRESH METHOD AND DEVICES

Rambus Inc., Sunnyvale, ...

1. An integrated circuit device that controls a memory device, the integrated circuit device comprising:
a circuit configured to:
receive an activate command and a data access command; and
responsive to receiving the activate command and the data access command, provide:
a bank address, wherein the bank address identifies a bank of a plurality of banks in a memory device;
a first row address that identifies a first row within the bank of the memory device for a memory access; and
a second row address that identifies a second row within the bank of the memory device to perform a refresh operation; and
a command interface coupled to the circuit, the command interface configured to output the bank address, the first row address,
and the second row address provided by the circuit to the memory device, wherein the first row address and the second row
address are simultaneously output to the memory device.

US Pat. No. 9,268,071

PHASE GRATINGS WITH ODD SYMMETRY FOR HIGH-RESOLUTION LENSED AND LENSELESS OPTICAL SENSING

Rambus Inc., Sunnyvale, ...

1. An imaging device to sense patterns of incident light over a wavelength band of interest, the imaging device comprising:
a photodetector array defining a focal plane; and
a phase grating defining a transverse plane to receive the incident light, the phase grating including:
a pair of adjacent first grating segments, of a first segment width W1, defining a boundary of odd symmetry extending in the transverse plane, the first grating segments inducing destructive interference
below the boundary of odd symmetry and at the focal plane for the incident light within the wavelength band of interest;

a pair of second grating segments, one on either side of the pair of first grating segments, of a second segment width W2 greater than the first segment width, the second grating segments inducing destructive interference below the boundary of
odd symmetry and at the focal plane for the incident light within the wavelength band of interest; and

a pair of third grating segments, one on either side of the pair of second grating segments, of a third segment width W3, the third grating segments inducing destructive interference below the boundary of odd symmetry and at the focal plane for
the incident light within the wavelength band of interest.

US Pat. No. 9,165,615

CODED DIFFERENTIAL INTERSYMBOL INTERFERENCE REDUCTION

Rambus Inc., Sunnyvale, ...

1. An integrated circuit, comprising:
an encoder circuit to encode a series of 2-bit data words into a series of 4-bit code; and
a transmitter circuit to transmit in succession the series of 4-bit code words over a set of 4 links that convey respective
bits in each of the series of code words;

wherein the encoder is configured to select a code word out of a set of six symbols for each of the series of data words,
the set of six symbols including a first group of two symbols, a second group of two symbols, and a third group of two symbols,
and wherein the encoder is further configured to encode the series of 2-bit data words such that any two consecutive code
words in the series of 4-bit code words are selected from two different groups of symbols.

US Pat. No. 9,472,262

MEMORY CONTROLLER

Rambus Inc., Sunnyvale, ...

1. A memory controller component comprising:
transmit circuitry to transmit, to a dynamic random access memory device (DRAM):
write data to be sampled by the DRAM in response to a timing signal, the timing signal requiring a first time interval to
propagate from the memory controller component to the DRAM;

a first clock signal that requires a second time interval to propagate from the memory controller component to the DRAM; and
a write command to be sampled by the DRAM in response to the first clock signal, the write command associated with the write
data; and

adjusting circuitry to control transmit timing within the transmit circuitry, the adjusting circuitry to adjust transmit timing
of the write data and timing of the timing signal based on a difference between the first and second time intervals such that
an edge transition of the timing signal at the DRAM is aligned with an edge transition of the first clock signal at the DRAM.

US Pat. No. 9,263,103

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. A method for calibrating timing relationships between signals involved in performing write operations, wherein the signals
are communicated between a memory controller and a memory chip in a set of memory chips, the method comprising:
using a phase detector located on the memory chip to calibrate a phase relationship between a data-strobe signal and a clock
signal received at the memory chip from the memory controller; and

performing at least one write-read-validate operation to calibrate a clock-cycle relationship between the data-strobe signal
and the clock signal, wherein the write-read-validate operation involves varying a delay on the data-strobe signal relative
to the clock signal by a multiple of a clock period of the clock signal.

US Pat. No. 9,262,262

MEMORY DEVICE WITH RETRANSMISSION UPON ERROR

Rambus Inc., Sunnyvale, ...

10. A method of operation of a solid state memory device, the method comprising:
configuring a link interface to transfer signals in one of a bidirectional format in a first configuration, and a unidirectional
format in a second configuration;

in one of the first configuration and the second configuration, receiving, from a controller device, command information and
first error detection information associated with the command information and transmitting a group of read data bits in response
to the command information, the group of read data bits being transmitted time multiplexed with second error-detection information;

prior to transmitting, generating the second error-detection information from the group of read data bits; and
retransmitting the group of read data bits and the second error detection information in the event that an error condition
associated with the group of read data bits is detected.

US Pat. No. 9,368,172

READ STROBE GATING MECHANISM

Rambus Inc., Sunnyvale, ...

1. A memory controller, comprising:
a control circuit to generate a gating signal indicative of a read window;
a gating adjustment circuit to receive the gating signal and a timing reference signal for reading data and to generate an
adjusted gating signal indicative of an adjusted read window based on the gating signal and the timing reference signal; and

a gating circuit to generate a gated timing reference signal for reading data, the gated timing reference signal generated
by gating a delayed version of the timing reference signal with the adjusted gating signal.

US Pat. No. 9,305,644

RESISTANCE MEMORY CELL

Rambus Inc., Sunnyvale, ...

1. A resistance memory, comprising:
a conductive-bridging resistance memory cell, comprising:
a conductive-bridging resistance memory element having an asymmetric current-voltage characteristic; and
a two-terminal access device connected in series with the resistance memory element, the two-terminal access device configured
to enable a bi-directional flow of current through the resistance memory element in response to application of a voltage greater
than a threshold voltage; and

a circuit to apply across the resistance memory cell a set voltage pulse having a set polarity to set the resistance memory
cell to a low-resistance state that is retained after application of the set voltage pulse, a reset voltage pulse having a
reset polarity, opposite to the set polarity, to reset the resistance memory cell to a high-resistance state that is retained
after application of the reset voltage pules, wherein the reset voltage pulse exhibits a magnitude that is larger than a magnitude
of the set voltage pulse, the circuit to apply a read voltage pulse of the reset polarity and smaller in magnitude than the
reset voltage pulse to determine the resistance state of the resistance memory cell without changing the resistance state
of the resistance memory cell.

US Pat. No. 9,104,646

MEMORY DISTURBANCE RECOVERY MECHANISM

Rambus Inc., Sunnyvale, ...

1. A method of operation in a memory device, the method comprising:
responsive to activation of a memory row specified by a row access command, determining whether a disturbance condition is
present in the memory row based on a state of a disturbance warning circuit associated with the memory row, the state of the
disturbance warning circuit corresponding to accumulated disturbances of the memory row; and

performing a recovery operation on the memory row to reduce the accumulated disturbances responsive to determining that the
disturbance condition is present.

US Pat. No. 9,324,411

MULTI-DIE MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A memory comprising:
a logic die including a serial interface having plural transmitters;
a first memory die stacked on the logic die and coupled to the serial interface; and
wherein the serial interface includes
mode select logic responsive to an interface select signal to, in a first mode of operation, activate all of the plural transmitters
for transmitting serialized read data to a memory controller at a first data rate, and in a second mode of operation, activate
less than all of the plural transmitters for transmitting serialized read data to the memory controller at a second data rate
that is different than the first data rate.

US Pat. No. 10,003,479

APPARATUS AND METHOD FOR UN-DELAYED DECISION FEEDBACK WITH SAMPLE AND HOLD AT SELECTED TIMING

Rambus Inc., Sunnyvale, ...

1. An apparatus, comprising:first sampling circuitry to sample incoming data symbols, each having a state of at least two alternative logic states, and to responsively produce a first output;
second sampling circuitry to sample incoming data symbols, each having a state of at least two alternative logic states, and to responsively produce a second output;
wherein the sampling by the second sampling circuitry is dependent on the first output, and the first output is directly provided to the second sampling circuitry without the use of an intervening clocked delay element;
a latch to also receive the second output from the second sampling circuitry and to output data samples according to timing provided by a sampling clock; and
circuitry to select the timing provided by the sampling clock.

US Pat. No. 9,298,609

MEMORY CONTROLLER SUPPORTING NONVOLATILE PHYSICAL MEMORY

Rambus Inc., Sunnyvale, ...

1. A computer-readable medium having stored thereon a data structure having information defining at least a portion of an
integrated-circuit memory controller, the data structure comprising:
first data representing a first connection to couple to a cache memory of volatile access units;
second data representing a second connection to couple to a nonvolatile memory with erase blocks of nonvolatile access units
specified by respective nonvolatile-access-unit addresses;

third data representing a head register to store, as a head nonvolatile address, the nonvolatile-access-unit address of a
next nonvolatile access unit to receive write data from one of the volatile access units;

fourth data representing a tail register to store, as a tail nonvolatile address, the nonvolatile-access-unit address of the
one of the erase blocks storing eldest of the data, the head and tail nonvolatile addresses to define between them a contiguous
group of valid and invalid page entries that snake through nonvolatile memory to support wear leveling without a counter to
track writes to the erase blocks; and

fifth data representing circuitry to compare the head and tail nonvolatile addresses to initiate a garbage-collection process.

US Pat. No. 9,185,311

IMAGE SENSOR WITH A SPLIT-COUNTER ARCHITECTURE

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit image sensor comprising:
an image sensor region comprising:
an array of pixel regions, each pixel region including at least one photosensitive element for detecting light incident upon
the pixel region; and

a plurality of local registers coupled to the pixel regions for storing K-bit values, each K-bit value indicative of the light
detected by at least one of the photosensitive elements of a coupled pixel region, the K-bit values comprising K1 less significant
bits and K2 more significant bits;

communication line groups, each communication line group selectably coupled to a plurality of the local registers and configurable
to receive the K1 less significant bits and the K2 more significant bits from each of the selectably coupled local registers;
and

a controller coupled to the image sensor region and configured to instruct the local registers to, for each pixel region:
output the K2 more significant bits on the respective communication line group for that local register and reset the K2 more
significant bits; and

output the K1 less significant bits on the respective communication line group for that local register and reset the K1 less
significant bits, wherein the K2 more significant bits are output multiple times for each time the K1 less significant bits
are output.

US Pat. No. 9,165,638

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. A memory controller to control the operation of a dynamic random access memory (DRAM), the memory controller comprising:
a circuit to transmit a clock signal to the DRAM;
a circuit to transmit a strobe signal to the DRAM, the strobe signal to convey phase information to the DRAM for sampling
data associated with the strobe signal; and

calibration logic to, in a calibration mode of operation, align at the DRAM, arrival of the strobe signal with arrival of
the clock signal and calibrate a clock cycle delay between commands received at the DRAM and data corresponding to the commands,
wherein the calibration logic delays the strobe signal as a delayed strobe such that it arrives at the DRAM at an edge transition
of the clock signal, the calibration logic to set the clock cycle delay for the strobe signal by iteratively writing a first
data using the delayed strobe to a specific location in the DRAM, reading back second data from the specific location in which
the first data was written, and selectively adjusting the clock cycle delay by an integer number of cycles based on whether
the second data matches the first data.

US Pat. No. 9,111,588

MULTI-DIE DRAM BANKS ARRANGEMENT AND WIRING

RAMBUS INC., Sunnyvale, ...

1. A memory die for use in a multi-die stack having at least one other die, comprising:
a plurality of memory banks, each having a plurality of signal lines;
a plurality of contacts arranged in a field, the contacts configured to interface to the at least one other die of the multi-die
stack;

buffer lines, including a first subset of buffer lines and a second subset of buffer lines, the first subset of buffer lines
being connected to respective contacts in the field;

a plurality of buffers, each buffer of the plurality of buffers having a first terminal coupled to a respective signal line,
a second terminal coupled to another buffer of the plurality of buffers, and a third terminal coupled to a respective buffer
line; and

a plurality of cross-bar lines interconnecting respective pairs of buffer lines in the second subset of buffer lines.

US Pat. No. 9,913,363

STRUCTURE FOR DELIVERING POWER

Rambus Inc., Sunnyvale, ...

1. A structure for delivering power, comprising:
a first set of interdigitated conductors disposed on a first layer, wherein a first conductor in the first set of interdigitated
conductors is maintained at a first voltage, wherein a second conductor in the first set of interdigitated conductors is maintained
at a second voltage, and wherein the second voltage is different from the first voltage;

a conducting structure disposed on a second layer, wherein the second layer is different from the first layer, and wherein
a third conductor in the conducting structure is maintained at the first voltage; and

wherein the first conductor and the second conductor form a first current loop, wherein the third conductor and the second
conductor form a second current loop, and wherein inductances contributed by the first current loop and the second current
loop are coupled in parallel.

US Pat. No. 9,306,564

NONVOLATILE MEMORY DEVICE WITH ON-DIE CONTROL AND DATA SIGNAL TERMINATION

Rambus Inc., Sunnyvale, ...

1. A non-volatile memory device comprising:
an array of non-volatile storage elements;
a plurality of input/output (I/O) nodes to receive data signals representative of data to be stored within the array of non-volatile
storage elements and to output data signals representative of data read from the array of non-volatile storage elements;

one or more control input nodes to receive control information indicating that data signals are to be received or output via
the I/O nodes during a subsequent time interval; and

on-die termination circuitry to switchably couple and decouple respective termination elements to and from the I/O nodes based
at least in part on the control information, and also to switchably couple and decouple respective termination elements to
and from the one or more control input nodes.

US Pat. No. 9,298,228

MEMORY CAPACITY EXPANSION USING A MEMORY RISER

Rambus Inc., Sunnyvale, ...

1. A computing system comprising:
a memory controller;
a motherboard including a first memory module connector;
a first riser card inserted into the first memory module connector;
a first mezzanine card connected to the first riser card, the first mezzanine card including a first mezzanine memory module
connector and a second mezzanine memory module connector;

a memory channel electrically connecting the memory controller to the first mezzanine memory module connector and the second
mezzanine memory module connector via the motherboard, the first riser card and the first mezzanine card, the memory channel
comprising:

a first data sub-channel for a first plurality of data bits, the first data sub-channel electrically connecting the memory
controller to the first mezzanine memory module connector via the motherboard, the first riser card and the first mezzanine
card, the first data sub-channel not electrically connected to the second mezzanine memory module connector;

a second data sub-channel for a second plurality of data bits, the second data sub-channel electrically connecting the memory
controller to the second mezzanine memory module connector via the motherboard, the first riser card and the first mezzanine
card, the second-data sub-channel not connected to the first mezzanine memory module connector; and

a command and address (C/A) channel electrically connecting the memory controller to both the first mezzanine memory module
connector and the second mezzanine memory module connector via the motherboard, the first riser card and the first mezzanine
card; and

a first memory module connected to the first mezzanine memory module connector and a second memory module connected to the
second mezzanine memory module connector, the first memory module comprising:

a first plurality of pins and a second plurality of pins;
a first integrated circuit chip comprising a first dynamic data buffer, the first dynamic data buffer selectively routing
data between the first plurality of pins and a selected one of the first memory die and the second memory die; and

a second integrated circuit chip comprising a second dynamic data buffer, the second dynamic data buffer selectively routing
data between the second plurality of pins and a selected one of the third memory die and the fourth memory die.

US Pat. No. 9,142,262

STACKED SEMICONDUCTOR DEVICE

Rambus Inc., Sunnyvale, ...

1. A stacked semiconductor system comprising:
a plurality of semiconductor dies, each having oppositely disposed first and second surfaces, a plurality of pads formed on
the first surface, a plurality of pads formed on the second surface, and a plurality of through-vias connecting respective
pads on the first surface to respective pads on the second surface, the plurality of through-vias in each semiconductor die
including a first group of through-vias coupled to respective I/O circuitry on the semiconductor die and a second group of
through-vias not coupled to I/O circuitry on the semiconductor die;

wherein the plurality of semiconductor dies are stacked such that the first group of through-vias in a first one of the plurality
of semiconductor dies are aligned with respective ones of at least a portion of the second group of through-vias in a second
one of the plurality of semiconductor dies.

US Pat. No. 9,466,568

DISTRIBUTED ON-CHIP DECOUPLING APPARATUS AND METHOD USING PACKAGE INTERCONNECT

Rambus Inc., Sunnyvale, ...

1. An integrated circuit device comprising:
a semiconductor die fabricated by a front-end semiconductor process and having oppositely disposed planar surfaces, the semiconductor
die formed with

semiconductor devices,
power supply circuitry coupled to the semiconductor devices,
decoupling capacitance circuitry, and
through-vias including a first group of vias coupled to the power supply circuitry and a second group of vias coupled to the
decoupling capacitance circuitry; and

conductors formed in a first metal layer disposed on the semiconductor die, the first metal layer fabricated by a back-end
semiconductor process, the conductors configured to couple to the first and second groups of vias to establish conductive
paths from the power supply circuitry to the decoupling capacitance circuitry.

US Pat. No. 9,337,835

CONTROLLING A FLASH DEVICE HAVING TIME-MULTIPLEXED, ON-DIE-TERMINATED SIGNALING INTERFACE

Rambus Inc., Sunnyvale, ...

1. An integrated circuit (IC) die having a memory controller function to control a flash memory device having an array of
non-volatile storage elements and a termination element, the IC die comprising:
a first signaling circuit to transmit to the flash memory device, via a time-multiplexed signaling line external to the IC
die, command signals, address signals and data signals at respective times, the data signals representing data to be stored
within the array of non-volatile storage elements; and

circuitry to transmit a control signal to the flash memory device via one or more control signal lines external to the IC
die, the control signal to direct the flash memory device to switchably couple the termination element to the time-multiplexed
signaling line.

US Pat. No. 9,281,816

MODULATED ON-DIE TERMINATION

Rambus Inc., Sunnyvale, ...

1. A method of operation within an integrated circuit device, the method comprising:
coupling a first termination impedance to a signaling link during a first portion of a bit time interval in which a data bit
is conveyed via the signaling link; and

coupling a second termination impedance to the signaling link during a second portion of the bit time interval, the second
termination impedance being different from the first termination impedance.

US Pat. No. 9,202,572

THERMAL ANNEAL USING WORD-LINE HEATING ELEMENT

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit memory device comprising:
charge-storing memory cells;
a word line coupled to the charge-storing memory cells;
control circuitry to output one or more control signals in response to detecting an event during operation of the integrated-circuit
memory device; and

annealing circuitry to enable electric current to flow through the word line for a limited interval, in response to the one
or more control signals, to heat the charge-storing memory cells to an annealing temperature range above 250° C., the limited
interval having a duration between a time shorter than a duration of an erase operation within the integrated-circuit memory
device and a time not substantially longer than the duration of the erase operation.

US Pat. No. 9,111,608

STROBE-OFFSET CONTROL CIRCUIT

Rambus Inc., Sunnyvale, ...

1. An integrated circuit (IC) memory controller comprising:
a first pin to receive a first data signal;
a first adjustable delay element to delay the received first data signal and generate a first delayed data signal;
a second pin to receive a second data signal;
a second adjustable delay element to delay the received second data signal and generate a second delayed data signal;
a pin to receive a strobe signal;
a first sampling circuit to sample the first delayed data signal based on the strobe signal; and
a second sampling circuit to sample the second delayed data signal based on the received strobe signal.

US Pat. No. 9,082,463

MULTI-DIE MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A memory comprising:
a logic die including first and second memory interface circuits;
a first memory die stacked with the logic die, the first memory die including first and second memory arrays, the first memory
array coupled to the first memory interface circuit, the second memory array coupled to the second interface circuit;

a second memory die stacked with the logic die and the first memory die, the second memory die including third and fourth
memory arrays, the third memory array coupled to the first memory interface circuit, the fourth memory array coupled to the
second memory interface circuit; and

wherein accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth
memory arrays.

US Pat. No. 9,264,055

INTEGRATED CIRCUIT HAVING A CLOCK DESKEW CIRCUIT THAT INCLUDES AN INJECTION-LOCKED OSCILLATOR

RAMBUS INC., Sunnyvale, ...

1. A circuit, comprising:
an injection-locked oscillator (ILO) having a free-running frequency that is controlled by at least a control value; and
circuitry to determine at least a first control value that corresponds to a phase boundary between two adjacent phase tuning
ranges of the ILO.

US Pat. No. 9,148,322

HIGH-SPEED SIGNALING SYSTEMS WITH ADAPTABLE PRE-EMPHASIS AND EQUALIZATION

Rambus Inc., Sunnyvale, ...

23. A method comprising:
in a first power mode,
using circuitry on a first integrated circuit to equalize an input data signal only for precursor interference and transmit
an equalized data signal to a second integrated circuit, the circuitry including a post-cursor tap, a main tap, and a pre-cursor
tap;

using a linear equalizer on the second integrated circuit to further equalize the equalized data signal to provide a first
receiver-equalized signal; and

using a decision-feedback equalizer (DFE) on the second integrated circuit to further equalize the first receiver-equalized
signal only for post cursor interference to provide a second receiver-equalized signal;

where using the decision-feedback equalizer includes equalizing the first receiver-equalized signal for symbol latency exceeding
a first latency relative to a current symbol, and where using the circuitry on the first integrated circuit includes equalizing
the input data signal for symbol latency not exceeding the first latency relative to the current symbol; and

in a second power mode,
disabling the linear equalizer and the DFE, and using the circuitry to equalize for post-cursor intersymbol interference.

US Pat. No. 9,318,183

MAINTENANCE OPERATIONS IN A DRAM

RAMBUS INC., Sunnyvale, ...

1. A method of operating a memory device, the memory device including a command interface and a plurality of memory banks,
each bank including a plurality of rows of memory cells, the method comprising:
receiving a self-refresh command from a memory controller;
responsive to the self-refresh command, during a first time interval, performing a self-refresh operation to refresh data
stored in at least one bank of the plurality of memory banks;

receiving an operation code from the memory controller, the operation code specifying a calibration operation; and
in response to receiving the operation code, performing a calibration operation of the command interface during at least a
portion of the first interval.

US Pat. No. 9,124,390

DRIFT TRACKING FEEDBACK FOR COMMUNICATION CHANNELS

RAMBUS INC., Sunnyvale, ...

1. A memory controller comprising:
a receiver to receive a signal indicative of a system condition which drifts relative to a reference by an amount that correlates
with drift in timing of a parameter of a communication channel;

a monitoring circuit to monitor the signal indicative of the system condition; and
an adjustment circuit to update a receiver sample timing based on the amount of drift in the system condition of monitored
signal.

US Pat. No. 9,098,281

POWER-MANAGEMENT FOR INTEGRATED CIRCUITS

Rambus Inc., Sunnyvale, ...

1. A integrated circuit comprising a physical layer interface having a first timing domain and a second timing domain, the
first timing domain including a group of one or more circuits to process a command and address signal, distribution of a first
timing signal in the first timing domain being enabled in response to a first enable signal, and the second timing domain
including a group of one or more circuits to process a data signal, distribution of a second timing signal in the second timing
domain being enabled in response to a second enable signal, one of the first and second enable signals being selectively activated
at a time when the other of the first and second enable is signals inactive to enable distribution of one of the first and
second timing signals while distribution of the other of the first and second timing signals is disabled.

US Pat. No. 9,275,784

ELECTRONIC CIRCUITS USING COUPLED MULTI-INDUCTORS

Rambus Inc., Sunnyvale, ...

1. An apparatus, comprising:
N circuit stages coupled in a loop, N>2, each of the N circuit stages having an inductive element that overlaps with inductive
elements from two adjacent circuit stages in the loop, the overlapping inductive elements forming N pairs of inductively coupled
elements, the N circuit stages including:

a first circuit stage having a first inductive element including a first coil and a second coil electrically connected to
the first coil;

a second circuit stage having a second inductive element overlapping with the first coil of the first inductive element to
form a first pair of inductively coupled elements, wherein a magnetic flux induced in the first coil of the first inductive
element by a current through the first inductive element is oriented in a first direction at a given time, and

a third circuit stage having a third inductive element overlapping with the second coil of the first inductive element to
form a second pair of inductively coupled elements, wherein a magnetic flux induced in the second coil of the first inductive
element by the current through the first inductive element is oriented in a second direction, substantially opposite to the
first direction at the given time.

US Pat. No. 9,195,602

SYSTEM INCLUDING HIERARCHICAL MEMORY MODULES HAVING DIFFERENT TYPES OF INTEGRATED CIRCUIT MEMORY DEVICES

Rambus Inc., Sunnyvale, ...

1. A memory system having a memory controller, the memory system comprising:
a plurality of volatile memory devices defining a first memory hierarchy, the plurality of volatile memory devices disposed
on a first memory module, the first memory module coupled to the memory controller by a first signal path;

a nonvolatile memory device defining a second memory hierarchy, the nonvolatile memory device disposed on a second memory
module, the second memory module coupled to the first memory module by a second signal path, wherein a plurality of memory
transactions for the nonvolatile memory device defining the second memory hierarchy are transferred from the memory controller
to the first memory hierarchy using the first signal path, and wherein data associated with an accumulation of the plurality
of memory transactions stored in a number of contiguous bits is to be selectively written from the first memory hierarchy
to the second memory hierarchy using the second signal path, a first control signal, and a second control signal;

a durability circuit detecting wear in the nonvolatile memory device based on a number of writes to a memory location in the
nonvolatile memory device, wherein the durability circuit comprises a storage circuit to store a write threshold value, wherein
the wear is detected for the memory location in response to a comparison of the number of writes to the memory location with
the write threshold value, and wherein the durability circuit generates the first control signal to indicate a different memory
location in the nonvolatile memory device that has a fewer number of writes than other memory locations in the nonvolatile
memory device; and

a defect circuit detecting a defect in the nonvolatile memory device based on a comparison of a test value with a value associated
with another memory location, wherein the defect circuit generates the second control signal to indicate another different
memory location based on the comparison.

US Pat. No. 9,164,933

MEMORY SYSTEM WITH CALIBRATED DATA COMMUNICATION

Rambus Inc., Sunnyvale, ...

1. A memory sub-system comprising:
a plurality of flash memory devices coupled to a bus; and
a set of bus transceiver devices coupled to the bus, each individual bus transceiver device in the set comprising:
an interface circuit for coupling the bus transceiver device to a memory controller;
circuitry to receive a signal to individually address the individual bus transceiver device by the memory controller;
a reference voltage register to store a device-specific value; and
a receiver circuit to receive a data signal transmitted by the memory controller to the individual bus transceiver device;
wherein the device-specific value stored in the reference voltage register of each individual bus transceiver device controls
a reference voltage used by the corresponding receiver circuit when receiving the data signal transmitted by the memory controller
to the individual bus transceiver device.

US Pat. No. 9,344,074

LOW-LATENCY, FREQUENCY-AGILE CLOCK MULTIPLIER

Rambus Inc., Sunnyvale, ...

1. A method of operation within an integrated circuit device, the method comprising:
generating a plurality of frequency-multiplied clock signals within respective clock-frequency multiplying circuits in response
to an input clock signal;

evaluating the frequency-multiplied clocks signals to determine one or more characteristics thereof; and
selecting, according to the one or more characteristics, a preferred one of the frequency-multiplied clock signals to be an
output clock signal.

US Pat. No. 9,269,460

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A controller comprising:
an internal memory to store an address; and
a memory control unit operatively coupled with the internal memory, the memory control unit comprising a memory test logic
circuit to detect a malfunctioning row of primary data storage elements within an external memory device, the external memory
device being another semiconductor device separate from the controller, the memory test logic circuit to store the address
in the internal memory, the address indicating the malfunctioning row of primary data storage elements, wherein the memory
control unit further comprises a memory setup logic circuit.

US Pat. No. 9,191,243

CALIBRATION METHODS AND CIRCUITS TO CALIBRATE DRIVE CURRENT AND TERMINATION IMPEDANCE

Rambus Inc., Sunnyvale, ...

1. An integrated circuit comprising:
a reference node operable to receive a first reference;
a resistor operable to exhibit an adjustable impedance to current flow responsive to an impedance-control signal;
a comparator having a first input coupled to the reference node to receive the first reference, a second input coupled to
the resistor, and a comparator output;

a transistor disposed in series with the resistor between the second input and a supply terminal, the transistor operable
to disable the current flow through the resistor;

a counter operatively disposed between the comparator output and the resistor, the counter operable to update the impedance-control
signal responsive to the comparator output;

wherein the counter is operatively coupled between the comparator and the resistor via a latch, the latch to capture the signal
from the comparator output;

adjustable termination elements each having a control port coupled to the counter; and
a differential amplifier operable to receive a pair of complementary signals via respective first and second signal pads,
and wherein each of the signal pads is coupled to a DC voltage via a respective one of the adjustable termination elements.

US Pat. No. 9,148,187

METHODS AND SYSTEMS FOR SELF-REFERENCING SINGLE-ENDED SIGNALS

Rambus Inc., Sunnyvale, ...

1. A circuit comprising:
a data node to receive a series of data symbols, including even data symbols and odd data symbols represented as even and
odd signal levels;

an even sample-and-hold circuit coupled to the data node to sample and hold the even signal levels;
an odd sample-and-hold circuit coupled to the data node to sample and hold the odd signal levels;
a sampling circuit coupled to the even and odd sample-and-hold circuits, the sampling circuit to compare the even signal levels
to the odd signal levels to produce even samples, and to compare the odd signal levels to the even signal levels to produce
odd samples; and

a feedback circuit coupled to the sampling circuit, the feedback circuit to offset the comparisons that produce the even and
odd samples, respectively, based on immediately prior odd and even samples;

wherein the feedback circuit applies, for an even sample, an offset of a first polarity when the immediately prior odd sample
represents a first logic state, and applies an offset of a second polarity when the immediately prior odd sample represents
a second logic state; and

wherein the offset of the first polarity is of a magnitude and the offset of the second polarity is of the same magnitude.

US Pat. No. 9,117,508

INTEGRATED CIRCUIT WITH ADAPTIVE POWER STATE MANAGEMENT

RAMBUS INC., Sunnyvale, ...

1. An integrated circuit (IC) that controls the operation of a memory device, the IC comprising:
first circuitry capable of transitioning from a first operational state to a second operational state responsive to detecting
that a condition has occurred;

second circuitry capable of measuring a first set of performance values based on memory requests serviced by the IC; and
third circuitry capable of modifying the condition based on comparing the first set of performance values with a second set
of performance values stored in a set of registers.

US Pat. No. 9,378,786

MEMORY CONTROLLER WITH PHASE ADJUSTED CLOCK FOR PERFORMING MEMORY OPERATIONS

Rambus Inc., Sunnyvale, ...

1. Apparatus comprising:
a pad for coupling the apparatus to a bidirectional data bus supporting data transfer with one or more memory devices separate
from the apparatus;

a read data path on which data is transferred for read memory operations with the one or more memory devices via the pad;
a write data path on which data is transferred for write memory operations with the one or more memory devices via the pad;
a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one
first clock output to output a first phase adjusted clock signal;

a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least
one second clock output to output a second phase adjusted clock signal; and

a cross coupler to selectively couple one of the first clock output and the second clock output to either the read data path
or the write data path during a first memory operation and to selectively couple the other of the first clock output and the
second clock output to either the read data path or the write data path during a second memory operation following the first
memory operation.

US Pat. No. 9,294,317

EQUALIZER-COMPENSATED AC-COUPLED TERMINATION

Rambus Inc., Sunnyvale, ...

1. A signaling system comprising:
a signaling link;
a first integrated circuit device coupled to receive a signal via the signaling link and including termination circuitry to
switchably DC-couple a series resistor-capacitor termination structure to the signaling link while receiving the signal;

a second integrated circuit device coupled to transmit the signal via the signaling link; and
wherein at least one of the first and second integrated circuit devices comprises equalization circuitry to apply an equalization
signal to the signaling link to compensate for inter-symbol interference induced by the series resistor-capacitor termination
structure.

US Pat. No. 10,552,310

SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit memory chip comprising:a memory core including an array of memory cells and a sense amplifier bank;
a first signaling interface to receive a memory access command, a column address and a plurality of control values via first signaling links external to the integrated-circuit memory chip;
a second signaling interface to receive a plurality of write data values via second signaling links external to the integrated-circuit memory chip, the second signaling links being distinct from the first signaling links;
core access circuitry to carry out a memory access operation with respect to the memory core in response to the memory access command, including circuitry to:
decode the column address in response to the memory access command to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute the sense amplifier bank;
read, out of the address-specified sense amplifiers and in response to the memory access command, first data constituted by a plurality of read data values;
temporally align the plurality of read data values and the plurality of write data values by routing the plurality of read data values or the plurality of write data values through delay circuitry;
after temporally aligning the plurality of read data values and the plurality of write data values, generate second data by selecting, as each of a plurality of constituent values of the second data, a respective read data value of the plurality of read data values or a respective write data value of the plurality of write data values based on a respective control value of the plurality of control values; and
overwrite the first data within the address-specified sense amplifiers with second data in response to the memory access command.

US Pat. No. 9,135,186

CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO OUTPUT DRIVER PARAMETER

Rambus Inc., Sunnyvale, ...

1. A flash memory device, comprising:
a port to receive, from a controller, information representing at least one parameter for data transfer over a bidirectional
bus;

a register to store the information;
parameter adjustment circuitry to adjust a parameter control signal in accordance with the information; and,
an output driver to drive an output signal onto the bidirectional bus via the port, the output driver setting a transmission
parameter of the output signal in accordance with the parameter control signal.

US Pat. No. 9,274,892

MEMORY CHIP WITH ERROR DETECTION AND RETRY MODES OF OPERATION

Rambus Inc., Sunnyvale, ...

1. An electrically erasable programmable memory chip, comprising:
a memory core;
a link interface to receive commands from a memory controller;
a circuit to generate an error detection code in connection with a data packet, the data packet accessed from the memory core
of the memory chip in response to a first command received at the link interface; and

a transmitter circuit to transmit to the memory controller, a first instance of the data packet along with the error detection
code, wherein the transmitter circuit is to transmit a second instance of the data packet and an error detection code in response
to a second command received at the link interface, the second instance of the data packet being transmitted to the memory
controller in the event of at least one error detected in the first instance of the data packet using the error detection
code transmitted with the first instance of the data packet;

wherein the memory chip is to receive the second command in response to a memory controller determination, the memory controller
determination being dependent on the error detection code transmitted with the first instance of the data packet that the
first instance of the data packet contains at least one error.

US Pat. No. 9,397,868

SPLIT-PATH EQUALIZER AND RELATED METHODS, DEVICES AND SYSTEMS

Rambus Inc., Sunnyvale, ...

1. An integrated circuit, comprising:
an electrical contact adapted to receive an incoming data signal from a path external to the integrated circuit;
circuitry operatively coupled to the electrical contact so as to receive the incoming data signal and equalize the incoming
data signal using a first linear equalizer to generate a first output;

circuitry operatively coupled to the electrical contact so as to receive the incoming data signal and equalize the incoming
data signal using a second linear equalizer to generate a second output in parallel with the first output; and

circuitry operatively coupled to the first output and to the second output to generate a clock therefrom;
wherein the second output is equalized differently than the first output according to equalization characteristics respective
to the first linear equalizer and the second linear equalizer; and

wherein the circuitry to generate the clock comprises
a data sampler to receive the first output and to produce data samples therefrom,
an edge sampler to receive the second output and to produce edge samples therefrom, and
logic to receive the data samples and edge samples and to alternatively advance and delay a generated clock in dependence
on the data samples and edge samples, to thereby generate the clock as a recovered clock from the incoming data signal.

US Pat. No. 9,165,639

HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

RAMBUS INC., Sunnyvale, ...

1. A system comprising:
a motherboard substrate;
a memory controller disposed on the motherboard substrate;
a memory module disposed on the motherboard substrate and coupled to the memory controller; wherein the memory module comprises:
a plurality of device sites; and
a data (DQ) buffer component coupled to the plurality of device sites, wherein the DQ buffer component is to operate in a
first mode when the memory module is inserted onto a first type of memory channel with multi-drop data-links and to operate
in a second mode when the memory module is inserted onto a second type of memory channel with point-to-point data-links;

at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites;
nine DQ buffer components coupled to the at least eighteen DRAM devices, each of the nine DQ buffer components being coupled
to a respective pair of the at least eighteen DRAM devices, wherein the nine DQ buffer components includes the DQ buffer component;
and

a command and address (CA) buffer component coupled to the at least eighteen DRAM devices.

US Pat. No. 9,564,879

REFERENCE VOLTAGE GENERATION AND CALIBRATION FOR SINGLE-ENDED SIGNALING

Rambus Inc., Sunnyvale, ...

1. A signaling system, comprising:
an integrated circuit transmitter;
an integrated circuit receiver; and
a conductive signal path coupling the integrated circuit transmitter and the integrated circuit receiver, the conductive signal
path to convey a signal from the integrated circuit transmitter to the integrated circuit receiver, wherein bits of the signal
are conveyed as a function of signal levels in the signal;

wherein
the integrated circuit transmitter is to convey a first one of the signal levels by coupling a transmitter power supply voltage
to the conductive signal path and is to convey a second one of the signal levels by coupling a ground plane to the conductive
signal path, the integrated circuit transmitter further to capacitively-couple the first one of the signal levels to the ground
plane, such that ground plane noise is coupled to the conductive signal path irrespective of whether the first or second one
of the signal levels is to be transmitted, and

the integrated circuit receiver is to discriminate between the first and second ones of the signal levels by comparing the
signal to a reference voltage and, further, is to capacitively-couple the reference voltage to the ground plane in a manner
such that a ground plane noise profile associated with transmission of the signal by the transmitter integrated circuit is
mimicked in the reference voltage at the receiver integrated circuit.

US Pat. No. 9,129,712

PROGRAMMABLE MEMORY REPAIR SCHEME

RAMBUS INC., Sunnyvale, ...

1. A semiconductor memory package device comprising:
a plurality of primary data storage elements having respective addresses for memory access operations;
a plurality of redundant data storage elements distributed across two or more separate chips; and
a programmable repair circuit configured to recognize a malfunctioning address corresponding to one of the plurality of primary
data storage elements and reroute memory access operations from the one of the primary data storage elements to a corresponding
one of the plurality of redundant data storage elements, wherein the programmable repair circuit is programmable by a memory
controller separate from the semiconductor memory package.

US Pat. No. 9,659,671

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A controller comprising:
an internal memory to store an address; and
a memory control unit operatively coupled with the internal memory, the memory control unit comprising logic to:
identify a malfunctioning row address within an external memory device;
store the malfunctioning row address in the internal memory;
transmit a first register setting command to initiate a row repair mode in the external memory device;
transmit an activation command comprising an indication of the malfunctioning row address to be repaired;
transmit a precharge command; and
transmit a second register setting command to terminate the row repair mode in the external memory device.

US Pat. No. 9,652,409

MEMORY ACCESS DURING MEMORY CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A method of operation in a memory system including a plurality of ranks of memory devices including at least a first memory
device in a first memory rank and a second memory device in a second memory rank, each memory device being coupled to both
a first data bus and second data bus, the method comprising:
receiving, by the first memory device, a first command that specifies a calibration operation; and
receiving, by the second memory device, a second command that specifies a memory access operation, such that the memory access
operation is performed by the second memory device while the calibration operation is performed by the first memory device.

US Pat. No. 9,098,209

COMMUNICATION VIA A MEMORY INTERFACE

Rambus Inc., Sunnyvale, ...

1. A module, comprising:
a memory interface configured to interface with a memory controller, the memory interface including a memory data interface
and a memory command/address interface; and,

the module to execute instructions received via the memory data interface from the memory controller, the instructions to
be addressed to a memory space of the module that includes an instruction queue, the instruction queue comprising a plurality
of column addresses,

wherein the instructions received via the memory data interface include command tag pairs, each command tag pair including
a tag value corresponding to an instruction order bit and a command associated with the instruction order bit,

wherein the instruction order bits determine a relative order of the instructions and the execution of instructions are reordered
using the instruction order bits.

US Pat. No. 9,077,575

METHODS AND CIRCUITS FOR ASYMMETRIC DISTRIBUTION OF CHANNEL EQUALIZATION BETWEEN DEVICES

Rambus Inc., Sunnyvale, ...

1. A memory system comprising:
a memory channel to convey a first signal in a first direction at a symbol rate and a second signal in a second direction
opposite the first direction at the symbol rate, wherein the memory channel induces intersymbol interference (ISI) onto the
first and second signals;

a memory controller having:
a first receiver node coupled to the memory channel, the memory controller to receive the first signal over the memory channel
as a first waveform with a first receive signal-to-ISI ratio (SIR) at the first receiver node; and

a first transmitter node coupled to the memory channel, the memory controller to transmit the second signal over the memory
channel as a second waveform with a first transmit SIR at the first transmitter node; and

a memory device having:
a second receiver node coupled to the memory channel, the memory device to receive the second signal over the memory channel
as a third waveform with a second receive SIR at the second receiver node, wherein the first receive SIR is at least 30% lower
than the second receive SIR; and

a second transmitter node coupled to the memory channel, the memory device to transmit the first signal over the memory channel
as a forth waveform with a second transmit SIR at the second transmitter node, wherein the first transmit SIR is at least
30% lower than the second transmit SIR.

US Pat. No. 10,401,900

USING A STUTTERED CLOCK SIGNAL TO REDUCE SELF-INDUCED VOLTAGE NOISE

Rambus Inc., Sunnyvale, ...

1. A device that supports operation of a synchronous system, the device comprising:a storage structure to store modification information defining a modified timing signal waveform for the synchronous system, wherein the modified timing signal waveform exhibits a different state over a given period of operation that differs from a normal timing signal waveform; and
control logic,
wherein during normal operation of the synchronous system, the control logic is configured to use the normal timing signal waveform to control operation of the synchronous system; and
wherein during a transient period of time associated with a deterministic event that generates a transient power response characteristic within the transient period of time and causing the system to change from using a first timing signal waveform to using the normal timing signal waveform after the transient period, the control logic is configured to use the modified timing signal waveform, to control the operation of the synchronous system, wherein the modified timing signal waveform exhibits a different speed with respect to the first timing signal waveform and the second timing signal waveform.

US Pat. No. 9,417,800

MECHANISM FOR ENABLING FULL DATA BUS UTILIZATION WITHOUT INCREASING DATA GRANULARITY

Rambus Inc., Sunnyvale, ...

11. A method of operation in a controller, wherein the controller operates a dynamic random access memory (DRAM) having at
least first and second memory portions, wherein each of the first and second memory portions includes a plurality of memory
banks, the method comprising:
sending to the DRAM, a plurality of indications for which memory portion, of the first and second memory portions, are to
be selected for consecutive accesses; and

timing access requests to include commands interleaved between the first and the second memory portions; such that for each
of the consecutive accesses to the first and second memory portions, a delay time between consecutive access requests to banks
within anyone of the first and second memory portions is longer than a time between any access request to a bank within the
first memory portion followed by an access request to a bank within the second memory portion.

US Pat. No. 10,404,258

INTEGRATED CIRCUIT DEVICE HAVING AN INJECTION-LOCKED OSCILLATOR

Rambus Inc., Sunnyvale, ...

1. A first circuit, wherein the first circuit generates an output clock signal that is used to clock a second circuit, the first circuit comprising:an amplifier to generate an adjusted input clock signal based on an input clock signal;
an injection-locked oscillator (ILO) to generate an ILO output clock signal based on the adjusted input clock signal;
a latch to output the output clock signal based on the ILO output clock signal; and
a control circuit to (1) modify a gain of the amplifier based on power mode information associated with the second circuit, and (2) operate the latch based on enable/disable information associated with the ILO.

US Pat. No. 10,404,908

OPTICAL SYSTEMS AND METHODS SUPPORTING DIVERSE OPTICAL AND COMPUTATIONAL FUNCTIONS

Rambus Inc., Sunnyvale, ...

1. A system for imaging a scene, the system comprising:at least one photodetector array having a first region of pixels and a second region of pixels;
a first phase grating overlying the first region of pixels, the first phase grating and the first region of pixels collectively exhibiting a first impulse response, the first region of pixels to sample first image data modulated by the first phase grating and representing the scene;
a second phase grating overlying the second region of pixels, the second phase grating and the second region of pixels exhibiting a second impulse response different from the first impulse response, the second region of pixels to sample second image data modulated by the second phase grating and representing the scene; and
circuitry to perform a first computational function on the first image data and a second computational function different from the first computational function on the second image data.

US Pat. No. 9,170,894

MEMORY ERROR DETECTION

Rambus Inc., Sunnyvale, ...

1. A dynamic random access memory (DRAM) integrated circuit, comprising:
circuitry to receive, from a memory controller, an address with a write command that specifies a write operation;
circuitry to buffer the write command for an interval of time comprising a latency associated with time to perform the write
operation and a time associated with detection of an error in the address; and

circuitry to cause the DRAM integrated circuit to preclude the write operation from being completed if an error is determined
to exist in the address within the time associated with detection of an error in the address and to complete the write operation
following expiration of the interval of time in absence of a determination that there is an error associated with the write
command.

US Pat. No. 9,438,826

PIXEL STRUCTURE AND RESET SCHEME

Rambus Inc., Sunnyvale, ...

1. A pixel circuit of an image sensor, comprising:
at least one photodetecting section;
a signal node coupled to the at least one photodetecting section;
a reset element to reset the signal node; and
a row-enabled switch to pass or not pass, depending on a state of a row signal, a column reset signal to the reset element.

US Pat. No. 9,405,678

FLASH MEMORY CONTROLLER WITH CALIBRATED DATA COMMUNICATION

Rambus Inc., Sunnyvale, ...

1. A flash memory controller, comprising:
a bus interface to couple to a plurality of flash memory devices, the bus interface including a circuit to send at least one
signal to individually address a selected flash memory device of the plurality of flash memory devices and store a device-specific
value in a reference voltage register of the selected flash memory device; and

a transmitter to output a data signal to the selected flash memory device
wherein the device-specific value stored in the reference voltage register of the selected flash memory device controls a
reference voltage used by a corresponding receiver circuit of the selected flash memory device, the receiver circuit to receive
the data signal transmitted by the flash memory controller to the selected flash memory device.

US Pat. No. 9,046,909

ON-CHIP REGULATOR WITH VARIABLE LOAD COMPENSATION

Rambus Inc., Sunnyvale, ...

1. An integrated circuit comprising:
a voltage regulator to supply a regulated voltage;
a circuit to process data, the circuit drawing a variable amount of power from the voltage regulator according to the data;
wherein the voltage regulator comprises
a first current source to provide a calibrated current that is dependent on the data, and
a second current source to provide a supplemental current in dependence on a difference between the current required by the
circuit and the calibrated, data-dependent current.

US Pat. No. 9,653,146

HIGH CAPACITY MEMORY SYSTEM USING STANDARD CONTROLLER COMPONENT

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
a plurality of device sites;
a data buffer component coupled to the plurality of device sites;
at least eighteen dynamic random access memory (DRAM) devices disposed at respective device sites;
nine data buffer components coupled to the at least eighteen DRAM devices, each of the nine data buffer components being coupled
to a respective pair of the at least eighteen DRAM devices, wherein the nine data buffer components includes the data buffer
component; and

a command and address (CA) buffer component coupled to the at least eighteen DRAM devices, wherein the data buffer component
is to couple to point-to-point data-links of a memory channel, wherein the data buffer component comprises:

three primary ports to couple to three multi-drop data-links in a first mode and to couple to three point-to-point data-links
in a second mode; and

three secondary ports coupled to three of the at least eighteen DRAM devices.

US Pat. No. 9,135,010

PROCESSOR EXECUTING INSTRUCTIONS IN ALU IN FIRST/SECOND PIPELINE STAGE DURING NON-ECC/ECC MODE

Rambus Inc., Sunnyvale, ...

1. A processor, comprising:
an arithmetic logic unit (ALU);
pipeline circuitry to, in a non-error correction code (ECC) operating mode, execute a sequence of single-cycle instructions
in the ALU in a first execution stage, and in an ECC operating mode, execute the same sequence of single-cycle instructions
in the ALU in a second execution stage instead of the first execution stage, wherein the execution of the single-cycle instructions
in the first or second execution stage is necessarily determined by whether the pipeline circuitry is operating in the non-ECC
operating mode or the ECC operating mode; and

mode control signaling to configure the pipeline circuitry between the non-ECC and ECC operating modes.

US Pat. No. 10,135,427

RECEIVER WITH TIME-VARYING THRESHOLD VOLTAGE

Rambus Inc., Sunnyvale, ...

1. A method of operation in an integrated circuit (IC) chip, comprising:receiving from a serial link a serial stream of data bits, the data bits having logical values, wherein a given logical value is within a corresponding bit-duration;
generating a time-varying threshold voltage during the bit-duration;
resolving the logical values from the serial stream of data bits based at least on the time-varying threshold voltage;
storing an activation bit; and
selectively enabling or disabling the time-varying threshold voltage based at least on the stored activation bit.

US Pat. No. 9,336,834

OFFSETTING CLOCK PACKAGE PINS IN A CLAMSHELL TOPOLOGY TO IMPROVE SIGNAL INTEGRITY

Rambus Inc., Sunnyvale, ...

1. A memory system, comprising:
a circuit board having one or more pairs of opposing memory chips which are located on opposite sides of the circuit board
in a clamshell configuration and including a first memory chip disposed opposite a second memory chip;

a multi-drop path including a timing signal line coupled to each memory chip; and
wherein the first memory chip is coupled to the timing signal line at a first location and the second memory chip is coupled
to the timing signal line at second location, wherein the first location and the second location are separated from each other
by a distance d1 along the signal line, wherein the distance d1 is at least half of a spacing d2 between like edges of successive pairs of opposing memory chips along the timing signal line, whereby coupling locations and
associated loads for individual memory chips are distributed along the timing signal line.

US Pat. No. 9,442,228

PHASE GRATINGS WITH ODD SYMMETRY FOR LENSED OPTICAL SENSING

Rambus Inc., Sunnyvale, ...

1. A camera for sensing incident light within a wavelength band of interest, the camera comprising:
an optical element operable to converge the incident light;
an array of pixels spaced from the optical element and defining a focal plane in a path of the converged incident light; and
a phase grating in the path of the converged incident light and spaced from the array of pixels to cast an interference pattern
on the array of pixels, the phase grating spaced from the array of pixels by more than fifteen microns and including:

boundaries of odd symmetry separating stepped features on opposite sides of each boundary, the stepped features on the opposite
sides of each boundary offset from the array by half of a wavelength within the wavelength band of interest, plus an integer
multiple of the wavelength, to produce curtains of destructive interference at the array of pixels.

US Pat. No. 9,423,441

INTEGRATED CIRCUIT HAVING RECEIVER JITTER TOLERANCE (“JTOL”) MEASUREMENT

Rambus Inc., Sunnyvale, ...

1. An integrated circuit, comprising:
circuitry to sample an input signal according to a sampling clock, to generate data samples;
a clock source to generate the sampling clock;
circuitry to compare expected data values with the data samples and to generate an error indication in dependence on whether
the expected data values match the data samples; and

circuitry to inject jitter into the sampling clock to simulate jitter in the input signal;
wherein the clock source comprises a clock recovery circuit operable to generate a recovered clock in dependence on transitions
in the input signal, the sampling clock being dependent on the recovered clock.

US Pat. No. 9,338,037

INTEGRATED CIRCUIT WITH CONFIGURABLE ON-DIE TERMINATION

Rambus Inc., Sunnyvale, ...

1. A communication system comprising:
a first integrated circuit (IC) having:
a transmitter to transmit a differential signal; and
first differential pads to convey the differential signal from the first IC;
a differential channel coupled to the first differential pads to communicate the differential signal; and
a second IC having:
second differential pads coupled to the differential channel to receive the differential signal, the second differential pads
including a first pad and a second pad; and

on-die termination circuitry that includes:
a common node;
a first termination leg extending between the common node and the first pad, the first termination leg including a first termination
impedance;

a second termination leg extending between the common node and the second pad, the second termination leg including a second
termination impedance; and

a third termination leg extending between the common node and a reference-voltage node, the third termination leg including
a switch to selectively couple the common node to the reference-voltage node.

US Pat. No. 9,257,159

LOW POWER MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A memory device, comprising:
at least one memory bank;
interface circuitry to receive memory read requests from an external source and to responsively supply read data from the
at least one memory bank to the external source, and to receive memory write requests and associated write data from the external
source,

wherein each memory read request is to specify a read request row corresponding to row address of memory cells in the at least
one memory bank and a column address of memory cells within a row corresponding to the row address, and each memory write
request is to specify a write row corresponding to a row address of memory cells in the at least one memory bank and a column
address of memory cells within the write row, and

wherein each memory read request and each memory write request is to be accompanied by bits that according to their states
are to determine a variable amount of data to be exchanged with the external source; and

logic responsive to the memory read requests and the memory write requests to, in dependence on state of the bits provided
with each request, exchange the variable amount of data with the external source;

wherein the bits are first bits and wherein the memory write requests are selectively accompanied by write mask bits, such
that the memory device is to selectively perform a masked write according to write mask bits accompanying a given memory write
request, and such that the memory device is to selectively write a subset of a column of memory, independent from any write
mask bits accompanying the given memory write request, in dependence on respective states of the first bits accompanying the
given memory write request.

US Pat. No. 9,412,428

MEMORY COMPONENTS AND CONTROLLERS THAT CALIBRATE MULTIPHASE SYNCHRONOUS TIMING REFERENCES

Rambus Inc., Sunnyvale, ...

1. A memory controller, comprising:
a first circuit to send a first timing reference signal to a memory device;
a second circuit to send a second timing reference signal to the memory device, the second timing reference signal to have
a quadrature phase relationship with respect to the first timing reference signal, the memory device to send a plurality of
calibration bit patterns synchronously with respect to the first timing reference signal and the second timing reference signal;

a receiver circuit to sample the plurality of calibration bit patterns over a range of receive timings, the sampling of the
plurality of calibration bit patterns over the range of receive timings resolving a plurality of timing indicators associated
with when transitions between bits of the plurality of calibration bit patterns are received; and,

a timing adjustment circuit to adjust, based on the plurality of timing indicators, a duty cycle of the first timing reference,
a duty cycle of the second timing reference, and a quadrature phase adjustment between the first timing reference and the
second timing reference.

US Pat. No. 9,268,632

MEMORY DEVICE WITH ECC HISTORY TABLE

Rambus Inc., Sunnyvale, ...

1. A method of reading data from a non-volatile integrated circuit (IC) memory device, the method comprising:
accessing preexisting data from a location in the non-volatile IC memory device in response to a read command, the preexisting
data associated with a stored ECC code;

identifying an error in the preexisting data based on supplemental error information from an error history table, the supplemental
error information other than the stored ECC code;

correcting the identified error to produce corrected data;
storing error information representing the error; and
retaining the preexisting data in the location of the memory device in uncorrected form for subsequent read accesses.

US Pat. No. 9,092,352

MEMORY CONTROLLER WITH WRITE DATA ERROR DETECTION AND REMEDIATION

RAMBUS INC., Sunnyvale, ...

1. A memory controller integrated circuit, comprising:
a transmit circuit that transmits a block of write data to a dynamic random access memory (DRAM) device, where the block of
data comprises a plurality of sequential data bit sets, sent over each of a plurality of bus lines;

an encoder to generate first error-detection information corresponding to the block of write data; and
logic circuitry to receive information from the DRAM device and signal an error condition based on the first error-detection
information and the information received from the DRAM device, the logic circuitry to perform a remedial action in the event
that the logic circuitry signals the error condition, the remedial action including retransmitting the write data to the DRAM.

US Pat. No. 9,087,572

CONTENT ADDRESSABLE MEMORY

Rambus Inc., Sunnyvale, ...

1. A content addressable memory array comprising a plurality of bitlines and a plurality of memory cell groups, each memory
cell group comprising:
a selection transistor; and
multiple resistive memory devices, wherein each of the resistive memory devices includes:
a first node coupled to a source node of the selection transistor; and
a second node coupled to a respective one of the bitlines such that each resistive memory device in the group is coupled to
a different bitline;

wherein, in response to application of a word line to a gate node of the selection transistor, electrically coupling the second
node to a matchline in a match mode.

US Pat. No. 9,054,907

PARTIAL RESPONSE RECEIVER AND RELATED METHOD

Rambus Inc., Sunnyvale, ...

1. A receiver to sample an input signal, the receiver comprising:
first sampler circuits to sample the input signal with reference to first thresholds to produce first sample streams;
a first multiplexer to select between the first sample streams to produce a first selected-samples stream;
a first storage circuit to store first selected samples from the first selected-sample stream as stored first selected samples;
second sampler circuits to sample the input signal with reference to second thresholds to produce second sample streams;
a second multiplexer to select between the second sample streams to produce a second selected-samples stream;
a second storage circuit to store second selected samples from the second selected-sample stream as stored second selected
samples;

an asynchronous first select path from the first multiplexer to the second multiplexer, the first selected-samples stream
to directly control the selection between the second sample streams; and

a synchronous second select path from the second multiplexer to the first multiplexer via the second storage circuit, the
stored second selected samples to control the selection between the first sample streams.

US Pat. No. 9,431,131

TIMING-DRIFT CALIBRATION

Rambus Inc., Sunnyvale, ...

1. An apparatus comprising:
a processing device that implements functionality of a memory controller, the processing device programmed to:
transmit a plurality of timing calibration instructions to the memory device, the timing calibration instructions to trigger
a plurality of frequency measurements in the memory device;

receive a plurality of count values indicative of a plurality of measured frequencies of an internal ring oscillator in the
memory device, wherein a change in the measured frequencies of the internal ring oscillator is indicative of a change in a
timing delay in a clock tree structure of a clock distribution circuit in the memory device; and

determine a timing drift of the memory device based on the plurality of count values.

US Pat. No. 9,401,225

TIMING-DRIFT CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A method of operation of a memory controller, comprising:
transmitting a request to a memory device which triggers the memory device to measure a frequency, wherein a change in the
measured frequency is indicative of a timing drift in the memory device;

receiving the measured frequency from the memory device; and
determining the timing drift of the memory device based at least in part on the measured frequency and a previous consecutively
measured frequency from the memory device.

US Pat. No. 9,367,248

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

Rambus Inc., Sunnyvale, ...

1. A controller to control operations of a memory component, the controller comprising;
a first circuit to transmit commands to the memory component, the commands including a read command that specifies data to
be accessed from a memory core of the memory component;

a second circuit to receive data sent by the memory component via an external bus, the data sent by the memory component in
response to the read command;

calibration circuitry, operable during calibration, to receive at least a first data pattern and a second data pattern from
the memory component, the first data pattern and the second data pattern being provided from pattern register circuitry in
the memory component, wherein, during the calibration, a selected one of the first data pattern and the second data pattern
is transmitted by the memory component onto the external bus in response to one of the commands.

US Pat. No. 9,299,408

INTEGRATED CIRCUIT COMPRISING CIRCUITRY TO CHANGE A CLOCK SIGNAL FREQUENCY WHILE A DATA SIGNAL IS VALID

RAMBUS INC., Sunnyvale, ...

1. A memory system, comprising:
a memory controller;
a memory device;
a first signal line to couple a first set of pins on the memory controller with a first set of pins on the memory device,
wherein the first signal line carries a clock signal having a clock signal frequency;

a second signal line to couple a second set of pins on the memory controller with a second set of pins on the memory device,
wherein the second signal line carries a data signal whose bits are timed according to the clock signal;

wherein the memory controller includes circuitry to modify the clock signal frequency from a first frequency value to a second
frequency value, wherein bits of the data signal continue to be timed according to the clock signal while the clock signal
frequency changes from the first frequency value to the second frequency value.

US Pat. No. 9,287,239

TECHNIQUES FOR INTERCONNECTING STACKED DIES USING CONNECTION SITES

Rambus Inc., Sunnyvale, ...

1. An integrated circuit die, comprising:
conductive connection sites located at least on a surface of the integrated circuit die within a contiguous region thereof;
a first core circuit located outside the contiguous region; and
alignment circuitry configurable to couple a first subset of the connection sites to the first core circuit and to decouple
a second subset of the connection sites from the first core circuit, the alignment circuitry additionally configurable to
decouple the first subset of the connection sites from the first core circuit and to couple the second subset of the connection
sites to the first core circuit.

US Pat. No. 9,256,557

MEMORY CONTROLLER FOR SELECTIVE RANK OR SUBRANK ACCESS

Rambus Inc., Sunnyvale, ...

1. A memory controller, comprising:
at least one transaction queue to direct memory commands to first and second memory devices as a unified rank in a first mode,
and to direct memory commands to the first and second memory devices as respective subranks in a second mode;

a command bus interface to direct the memory commands to the memory devices via a shared command bus;
a data bus interface having a width with a first portion of the width to be coupled to the first memory device but not the
second memory device and a second portion of the width to be coupled to the second memory device but not the first memory
device; and

circuitry to associate data exchanged via both of the first portion and the second portion with each of the memory commands
in the first mode, and to associate data exchanged via an exclusive one of the first portion and the second portion with respective
memory commands in the second mode.

US Pat. No. 9,196,348

MAINTENANCE OPERATIONS IN A DRAM

RAMBUS INC., Sunnyvale, ...

1. A method of operating a memory controller in a system that includes the memory controller and a memory device, the memory
device including a command interface and a plurality of memory banks, each bank including a plurality of rows of memory cells,
the method comprising:
transmitting a self-refresh command from the memory controller to the memory device, wherein responsive to the self-refresh
command, during a first time interval, the memory device performs a self-refresh operation to refresh data stored in at least
one bank of the plurality of memory banks; and

transmitting an operation code from the memory controller to the memory device, the operation code specifying a calibration
operation;

wherein, after receiving the operation code, the memory device performs a calibration of the command interface of the memory
device while performing the self-refresh operation.

US Pat. No. 9,178,647

INTERFACE WITH VARIABLE DATA RATE

RAMBUS INC., Sunnyvale, ...

1. A device, comprising:
a node to couple to a wired link;
a receiver having an input coupled to the node for receiving a baseband signal that includes data transmitted by another device
having a transmitter, the transmitter having an output coupled to the node; and

control logic to determine a performance metric, the performance metric comprising at least one of a timing margin corresponding
to an error rate of the wired link and a voltage margin corresponding to the error rate of the wired link;

wherein, during a calibration mode, an initial data rate of the wired link is increased from the initial data rate to an increased
data rate that is a non-integer multiple of the initial data rate, and in response to the determination of the performance
metric, a voltage swing of the transmitter output coupled to the node is adjusted.

US Pat. No. 9,171,824

STACKED SEMICONDUCTOR DEVICE ASSEMBLY

Rambus Inc., Sunnyvale, ...

1. A stacked semiconductor device assembly comprising:
first and second substantially identical integrated circuit (IC) devices, each of the first and second IC devices including:
first interface circuits each having a first capacitance;
second interface circuits each having a second capacitance that is lower than the first capacitance;
a first set of through vias coupled to respective ones of the first interface circuits; and
a second set of through vias coupled to respective ones of the second interface circuits; and
wherein the first and second IC devices are stacked one on top of another and offset from each other such that the first set
of through vias of the first IC device are aligned with and electrically connected to respective ones of the second set of
through vias of the second IC device, and the first interface circuits of the first IC device are electrically coupled to
the second interface circuits of the second IC device via the first set of through vias of the first IC device and the respective
ones of the second set of through vias of the second IC device.

US Pat. No. 9,142,281

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. A memory controller comprising:
calibration logic to, in a calibration mode of operation, phase align a strobe signal with a clock signal based on feedback
from an integrated circuit (IC) memory device, the feedback indicating whether the strobe signal is edge-aligned with the
clock signal, to establish a write-leveled timing relationship; and

wherein the calibration logic is to selectively adjust the write leveled timing relationship, by an integer number of cycles
of the strobe signal, responsive to whether a first data pattern, written to a location in the IC memory device, matches a
second data pattern retrieved from the location in the IC memory device.

US Pat. No. 9,065,628

FREQUENCY-AGILE CLOCK MULTIPLIER

Rambus Inc., Sunnyvale, ...

1. A method of operation within an integrated circuit device, the method comprising:
operating a clock generating circuit in a closed-loop operating state to generate an output clock signal that is frequency-locked
with respect to an oscillatory input signal;

detecting a transition of the oscillatory input signal from a first nonzero frequency to a second nonzero frequency;
in response to detecting the transition of the oscillatory input signal, switching the clock generating circuit from the closed-loop
operating state to an open-loop operating state to enable the output clock signal to oscillate at a first free-running frequency;

determining a frequency ratio between the first free-running frequency of the output clock signal and the second nonzero frequency
of the oscillatory input signal;

adjusting a frequency-lock range of the clock generating circuit, based at least in part on the frequency ratio, to transition
the output clock signal from the first free-running frequency to a second free-running frequency; and

after adjusting the frequency-lock range of the clock generating circuit and while the oscillatory input signal is oscillating
at the second nonzero frequency, switching the clock generating circuit from the open-loop operating state to the closed-loop
operating state to frequency-lock the output clock signal with respect to oscillatory input signal.

US Pat. No. 9,459,960

CONTROLLER DEVICE FOR USE WITH ELECTRICALLY ERASABLE PROGRAMMABLE MEMORY CHIP WITH ERROR DETECTION AND RETRY MODES OF OPERATION

Rambus Inc., Sunnyvale, ...

1. A controller device to control the operation of an electrically erasable programmable memory chip, the controller device
comprising:
a transmitter circuit to transmit a read command and a first error detection code to the memory chip;
a receiver circuit to receive read data and a second error detection code from the memory chip, the second error detection
code encoded by the memory chip in connection with the read data;

a circuit, coupled to the receiver, to detect an error in the received read data based on the second error detection code;
and

logic circuitry to signal an error condition in the event of the detected error, the controller device to re-receive the read
data from the memory chip in the event that the logic circuitry signals the error condition;

wherein the memory chip is to detect existence of error in the read command using the first error detection code; and
wherein at least one of the first error code and the second error detection code is to be exchanged between the controller
device and the memory chip using a link independent of a link used to receive the read data.

US Pat. No. 9,444,442

OPEN-LOOP CORRECTION OF DUTY-CYCLE ERROR AND QUADRATURE PHASE ERROR

RAMBUS INC., Sunnuyvale,...

1. A method of for duty-cycle correction of a clock signal comprising:
receiving a clock signal in a clock-forwarded serial communication link;
sampling the received clock signal over a selected number of samples to measure a duty-cycle of the received clock signal;
estimating a delay to adjust the received clock signal to achieve a desired duty-cycle;
expressing the delay in terms of a phase code adjustment (?) compatible with a predetermined phase interpolator step size;
and

conveying the phase code adjustment (?) to a transmitter to adjust the duty-cycle of the clock signal, using a phase interpolator,
so as to achieve the desired duty-cycle of the received clock signal.

US Pat. No. 9,391,816

EDGE BASED PARTIAL RESPONSE EQUALIZATION

Rambus Inc., Sunnyvale, ...

1. A method of compensating for inter-symbol interference (ISI) in a received data signal, comprising:
sampling the data signal, the data signal exhibiting a single-bit response with a data cursor d representing a first ISI component
associated with a first data sample value and an edge cursor e exhibiting a second ISI component associated with a first edge
sample value;

determining a data equalizer coefficient value ?DATA based on a determined edge equalizer coefficient value ?EDGE that corresponds to the edge cursor e; and

applying the determined data equalizer coefficient value ?DATA to compensate for the first ISI component of the ISI.

US Pat. No. 9,287,003

MULTI-CYCLE WRITE LEVELING

Rambus Inc., Sunnyvale, ...

1. A method comprising:
sending, by a memory controller, a command to a memory device, the command to cause the memory device to set a reference voltage
value of the memory device to a test value;

writing, by the memory controller, a first data pattern to the memory device;
reading, by the memory controller, the first data pattern from the memory device;
performing, by the memory controller, a density check on at least a portion of the first data pattern read from the memory
device; and

determining, by the memory controller, that the test value comprises a potential reference voltage value for the memory device
when the at least the portion of the first data pattern passes the density check.

US Pat. No. 9,268,719

MEMORY SIGNAL BUFFERS AND MODULES SUPPORTING VARIABLE ACCESS GRANULARITY

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
a signal buffer having a module data interface to communicate module data, a module command interface to receive module commands,
a first memory data interface, a second memory data interface, a first memory command interface, and a second memory command
interface separate from the first memory command interface;

a first memory device group, including at least one memory device, the first memory device group receiving first-memory commands
from the first memory command interface and communicating first-memory data with the first memory data interface; and

a second memory device group, separate from the first memory device group and comprising at least one memory device, the second
memory device group receiving second-memory commands from the second memory command interface and communicating second-memory
data with the second memory data interface;

the signal buffer having steering logic to derive the first-memory commands and the second-memory commands from the module
commands, and to communicate the module data associated with each module command between the module data interface and one
of the first or second memory device groups as the first or second memory data, respectively;

wherein the steering logic conveys the module data associated with each module command between the module data interface and
one of the first and second memory data interfaces in a first mode and conveys the module data associated with each module
command between the module data interface and both the first and second memory data interfaces in a second mode.

US Pat. No. 9,158,679

DATA BUFFER WITH A STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE

RAMBUS INC., Sunnyvale, ...

1. A memory module comprising:
an address buffer;
a data buffer comprising a controller interface and a memory interface, wherein the controller interface is a strobe-based
interface and the memory interface is a strobe-less interface; and

a plurality of dynamic random-access memory (DRAM) devices coupled to the address buffer and coupled to the data buffer via
the memory interface, wherein the address buffer is configured to generate a timing reference signal based on a reference
clock received at the address buffer and to forward the timing reference signal to the data buffer and to the plurality of
DRAM devices for one or more transactions between the data buffer and the plurality of DRAM devices via the memory interface
using the timing reference signal, wherein the data buffer is configured to communicate data to and from a memory controller
on the controller interface using strobe signals and to communicate the data to and from the plurality of DRAM devices on
the memory interface using the timing reference signal.

US Pat. No. 9,141,472

SHARING A CHECK BIT MEMORY DEVICE BETWEEN GROUPS OF MEMORY DEVICES

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
first memory chips;
second memory chips;
a third memory chip; and
a memory buffer to transfer first data with the first memory chips, to transfer second data with the second memory chips,
and to transfer first error checking information corresponding to the first data with the third memory chip and to transfer
second error checking information corresponding to the second data with the third memory chip,

wherein the memory buffer determines an error address indicating a location in the third memory chip corresponding to one
of the first error checking information or the second error checking information, the error address determined differently
depending on whether the first data is being transferred with the first memory chips or the second data is being transferred
with the second memory chips.

US Pat. No. 9,117,031

GENERATING INTERFACE ADJUSTMENT SIGNALS IN A DEVICE-TO-DEVICE INTERCONNECTION SYSTEM

RAMBUS INC., Sunnyvale, ...

1. An integrated circuit device, comprising:
an interface, including a plurality of interface control circuits, each respective interface control circuit comprising a
respective computational element, each computational element comprising a processing element that executes a sequence of instructions;

wherein a respective interface control circuit is configured to receive one or more respective external signals from one or
more respective devices external to the integrated circuit device, and the respective computational element is selectively
enabled or disabled according to the state of respective enable bits; and

a processor to execute machine-readable instructions to adjust, in conjunction with processing of at least one of the respective
external signals by the respective computational element of at least one of the plurality of interface control circuits, receive
timing of at least one signal received by the interface.

US Pat. No. 9,053,778

MEMORY CONTROLLER THAT ENFORCES STROBE-TO-STROBE TIMING OFFSET

Rambus Inc., Sunnyvale, ...

1. A method of operation within a memory controller component, the method comprising:
transmitting a clock signal to first and second dynamic random access memory (DRAM) components disposed on a memory module
via a clock signal line, the clock signal line being coupled to the first and second DRAM components at different points along
its length such that the clock signal propagates past the first DRAM component to the second DRAM component, the clock signal
having a first arrival time at the first DRAM and a second arrival time at the second DRAM, the first arrival time preceding
the second arrival time;

transmitting a write command to the first and second DRAM components via a set of signal lines, the write command to be sampled
by the first and second DRAM components at respective times corresponding to one or more transitions of the clock signal,
the set of signal lines being coupled to the first and second DRAM components at different points along its length such that
the write command propagates past the first DRAM component to the second DRAM component and arrives at the first DRAM component
before arriving at the second DRAM component;

transmitting, in association with the write command, first write data to the first DRAM component and second write data to
the second DRAM component;

generating a first strobe signal to time reception of the first write data within the first DRAM component, wherein a phase
of the first strobe signal is adjusted to compensate for skew between an arrival time, at the first DRAM component, of the
first strobe signal and the first arrival time of the clock signal; and

generating a second strobe signal to time reception of the second write data within the second DRAM component, wherein a phase
of the second strobe signal is adjusted to compensate for skew between an arrival time, at the second DRAM component, of the
second strobe signal and the second arrival time of the clock signal.

US Pat. No. 9,491,008

ON-CHIP AC COUPLED RECEIVER WITH REAL-TIME LINEAR BASELINE-WANDER COMPENSATION

Rambus Inc., Sunnyvale, ...

1. An on-chip alternating current (AC) coupled receiver with baseline wander compensation, the receiver comprising:
a first input terminal to receive a first input signal;
first AC coupling circuitry between the first input terminal and a first node, the first AC coupling circuitry coupling the
first input signal into a first coupled signal at the first node;

a data recovery circuit to recover data from the first coupled signal at the first node; and
a control loop circuit comprising a low pass filter to generate a signal indicative of low frequency signal content at the
first node based on the first coupled signal at the first node, the control loop using a linear buffer in adjusting the first
coupled signal at the first node based on the signal indicative of the low frequency signal content.

US Pat. No. 9,490,002

REDUCED REFRESH POWER

Rambus Inc., Sunnyvale, ...

1. A memory module, comprising:
an interface to receive a plurality of auto-refresh commands, the plurality of auto-refresh commands including a first auto-refresh
command and a second auto refresh command;

at least one memory component; and,
a buffer component coupled to the interface and coupled to the at least one memory component, the buffer component to receive
the plurality of auto-refresh commands via the interface, the buffer component to, based on a configured proportion of received
auto-refresh commands, send the first auto-refresh command to the at least one memory component, the buffer component to also,
based on the configured proportion of received auto-refresh commands, not send the second auto-refresh command to the at least
one memory component.

US Pat. No. 9,225,328

NONVOLATILE MEMORY DEVICE WITH TIME-MULTIPLEXED, ON-DIE-TERMINATED SIGNALING INTERFACE

Rambus Inc., Sunnyvale, ...

1. A non-volatile memory device comprising:
an array of non-volatile storage elements;
a first signaling circuit to receive, via a time-multiplexed signaling line external to the non-volatile memory device, command,
address and data signals at respective times, the data signals representing data to be stored within the array of non-volatile
storage elements; and

on-die termination circuitry to receive a control signal via a signaling path external to the non-volatile memory device and
to switchably couple a termination element to the time-multiplexed signaling line at least in part in response to a transition
of the control signal from a first logic state to a second logic state.

US Pat. No. 9,208,836

CHIP-TO-CHIP SIGNALING WITH IMPROVED BANDWIDTH UTILIZATION

Rambus Inc., Sunnyvale, ...

1. A method of operation within a component of a memory system, the method comprising:
receiving, as part of a first memory access operation, first data that consists of N data words conveyed via a first number
of signaling links in N respective transmit intervals; and

receiving, as part of a second memory access operation, second data that consists of (i) N?1 data words conveyed via the first
number of signaling links in N?1 respective transmit intervals, and (ii) a data word conveyed via one or more additional signaling
links that are distinct from the first number of signaling links.

US Pat. No. 9,177,632

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. A controller integrated circuit (IC) device to control the operation of a dynamic random access memory (DRAM), the controller
IC comprising:
an interface to transmit a clock signal and a strobe signal to the DRAM, the strobe signal to convey phase information to
the DRAM for sampling data associated with the strobe signal; and

calibration logic to establish a receiver phase offset for receiving read data and to align at the DRAM, arrival of the strobe
signal with arrival of the clock signal at an edge transition of the clock signal by using a delayed strobe, the calibration
logic to calibrate a clock cycle delay between commands received at the DRAM and data corresponding to the commands, the calibration
logic to set the clock cycle delay for the strobe signal by iteratively writing first data, using the delayed strobe, to a
specific location in the DRAM, read back second data, using the receiver phase offset, from the specific location, and selectively
adjust the clock cycle delay by an integer number of cycles based on whether the second data matches the first data.

US Pat. No. 9,166,583

BUFFERED MEMORY MODULE HAVING MULTI-VALUED ON-DIE TERMINATION

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
one or more integrated-circuit memory devices to store write data; and
an integrated-circuit buffer device having:
an interface to receive signals from a control component external to the memory module, the interface including a set of data
inputs to receive the write data and a set of termination circuits coupled respectively to the data inputs, each termination
circuit having a plurality of controllable termination impedance configurations, the interface further including a termination
control signal input to receive an indication that the buffer device is to apply one of the controllable termination impedance
configurations at each of the data inputs; and

logic to apply one of a first and a second of the controllable termination impedance configurations at the data inputs based
on the indication received at the termination control signal input and an internal state of the buffer device such that, during
a first internal state of the buffer device corresponding to the reception of the write data on the data inputs, the first
of the controllable termination impedance configurations is applied at each of the data inputs, and during a second internal
state of the buffer device following the first internal state, the second of the controllable termination impedance configurations
is applied at each of the data inputs.

US Pat. No. 9,153,321

RESISTANCE CHANGE MEMORY CELL CIRCUITS AND METHODS

Rambus Inc., Sunnyvale, ...

8. An integrated circuit device having a resistive change memory cell in an array having a plurality of bit lines and a plurality
of word lines, comprising:
a bit line driver to drive a first voltage onto one of the plurality of bit lines to change a state of the resistive change
memory cell; and

a word line driver to drive a second voltage on a word line of the plurality of word lines, the second voltage to determine
a maximum current to flow through a resistive change memory element of the resistive change memory cell as a state of the
resistive change memory element is changed by the first voltage.

US Pat. No. 9,117,035

MEMORY SYSTEM TOPOLOGIES INCLUDING A BUFFER DEVICE AND AN INTEGRATED CIRCUIT MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A memory module, comprising:
first connectors to connect the memory module to an external data bus and second connectors to connect the memory module to
an external command and address bus;

integrated circuit memory devices, each integrated circuit memory device to transfer a slice of data using one or more respective
ones of the first connectors in connection with a memory access command common to multiple ones of the memory devices;

data buffer devices, to buffer transfer of the slices of data, each buffer device to couple at least one of the integrated
circuit memory devices with the external data bus; and

at least one command-and-address buffer device to buffer provision of the memory access command to the multiple ones of the
integrated circuit memory devices from the external command and address bus.

US Pat. No. 9,106,397

SELECTABLE-TAP EQUALIZER

Rambus Inc., Sunnyvale, ...

1. An integrated circuit receiver to receive an input signal from a conductive signal path, comprising:
a sampling circuit to sample the input signal and generate digital samples according to a first timing signal;
an equalization circuit to equalize the input signal, in dependence on at least one preceding digital sample, according to
a second timing signal; and

circuitry to generate the second timing signal in a manner that is phase-offset relative to edges of the first timing signal.

US Pat. No. 9,106,399

PHASE CONTROL BLOCK FOR MANAGING MULTIPLE CLOCK DOMAINS IN SYSTEMS WITH FREQUENCY OFFSETS

RAMBUS INC., Sunnyvale, ...

1. A circuit for receiving a digital signal comprising:
at least three samplers for sampling the digital signal, each sampler having a clock input, wherein the samplers include an
edge sampler and a data sampler and an adaptive sampler;

edge clock circuitry to generate an edge clock signal, coupled to the edge sampler to sample the digital signal in accordance
with the edge clock signal;

data clock circuitry to generate a data clock signal, coupled to the data sampler to sample the digital signal in accordance
with the data clock signal; and

adaptive clock circuitry to generate an adaptive clock signal, coupled to the adaptive sampler to sample the digital signal
in accordance with the adaptive clock signal, and to phase shift the adaptive clock signal so as to sample the digital signal
at selected phases in a data eye of the digital signal.

US Pat. No. 9,054,916

CONFIGURABLE RECEIVER

Rambus Inc., Sunnyvale, ...

1. A receiver that is selectively reconfigurable, comprising:
a first input to couple to, in a first selectable configuration of the receiver, a resistor load and a source terminal of
a first transistor that is part of a first differential pair of field-effect transistors (FETs) of a first amplifier of the
receiver; and

the first input to couple to, in a second selectable configuration of the receiver, a gate terminal of a second transistor
that is part of a second differential pair of FETs of a second amplifier of the receiver;

mode selector circuitry coupled with the first differential pair of FETs and the second differential pairs of FETs for, in
the first selectable configuration of the receiver, activating the first differential pair of FETs and deactivating the second
differential pair of FETs, and for, in the second selectable configuration, deactivating the first differential pair of FETs
and activating the second differential pair of FETs.

US Pat. No. 9,563,597

HIGH CAPACITY MEMORY SYSTEMS WITH INTER-RANK SKEW TOLERANCE

Rambus Inc., Sunnyvale, ...

1. A memory controller adapted for use in a memory system in which the memory controller is to issue commands, each command
to an addressed one of a first rank of memory or a second rank of memory, over a command/address bus having (i) at least one
shared link that couples the memory controller with both of the first rank of memory and the second rank of memory in a point-to-multi-point
configuration, (ii) one or more first dedicated links that couples the memory controller with the first rank of memory but
not the second rank of memory, and (iii) one or more second dedicated links that couple the memory controller with the second
rank of memory but not the first rank of memory, where each rank of memory has an open loop clock distribution architecture
that defines a respective sampling instant used to sample each shared link of the command/address bus, and the respective
first or second dedicated links, the memory controller comprising:
logic operable to generate a first command/address signal and to transmit the first command/address signal to an addressed
one of the first rank of memory or the second rank of memory over the respective one of the one or more first or second dedicated
links, according to a unique clock phase corresponding to offset experienced by the addressed one of the first or second ranks
of memory relative to the other of the first or second ranks of memory; and

logic operable to generate a second command/address signal and to transmit the second command/address signal over the at least
one shared link to either one of the first or second ranks of memory.

US Pat. No. 9,552,865

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

Rambus Inc., Sunnyvale, ...

1. A memory controller to control the operation of a dynamic random access memory (DRAM), the DRAM being among a plurality
of DRAMs that receive a clock signal that is routed to the DRAMs in a flyby configuration, such that each DRAM of the plurality
of DRAMs receives the clock signal in sequence, the memory controller comprising:
a circuit to transmit the clock signal to the DRAM;
a circuit to transmit a strobe signal to the DRAM, the strobe signal to convey phase information to the DRAM for sampling
data associated with the strobe signal; and

calibration logic to, in a calibration mode of operation, align at the DRAM, arrival of the strobe signal with arrival of
the clock signal, based on feedback received from the DRAM, wherein the calibration logic delays the strobe signal as a delayed
strobe such that it arrives at the DRAM at an edge transition of the clock signal, the calibration logic to further adjust
the delayed strobe by iteratively writing first data using the delayed strobe to a specific location in the DRAM, reading
back second data from the specific location in which the first data was written, and selectively adjusting the delayed strobe
based on whether the second data matches the first data; and

an interface port to transmit the first data, receive the second data, and to receive the feedback from the DRAM.

US Pat. No. 9,502,085

MEMORY BUFFERS AND MODULES SUPPORTING DYNAMIC POINT-TO-POINT CONNECTIONS

Rambus Inc., Sunnyvale, ...

1. A method for configuring a data width of a memory module, the memory module having memory devices and module data-group
ports to communicate respective data groups, the method comprising:
sensing a value indicative of the data width;
responsive to a first value indicative of a first data width, coupling each module-data group port to a respective one of
the memory devices;

responsive to a second value indicative of a second data width, alternatively coupling a subset of the module data-group ports
to a first or a second subset of the memory devices; and

receiving first commands and, responsive to the first value and the first commands, issuing second commands to the memory
devices or, responsive to the second value and the first commands, issuing third commands to one or the other of the first
and second subsets of the memory devices.

US Pat. No. 9,491,011

METHODS AND SYSTEMS FOR TRANSMITTING DATA BY MODULATING TRANSMITTER FILTER COEFFICIENTS

Rambus Inc., Sunnyvale, ...

1. A circuit comprising:
a transmitter including a first data-input node to receive a first data signal, a first data output node, and a first filter-coefficient
input node;

a modulator including a second data-input node to receive a second data signal, a second filter-coefficient input node; and
a modulator output node coupled to the first filter-coefficient input node; and

a filter-coefficient source having a filter-coefficient output node coupled to the second filter-coefficient input node to
convey filter coefficients;

wherein the modulator modulates the filter coefficients with the second data signal to generate modulated second data and
conveys the modulated second data from the modulator output node to the first filter-coefficient input node.

US Pat. No. 9,465,961

METHODS AND CIRCUITS FOR SECURING PROPRIETARY MEMORY TRANSACTIONS

Rambus Inc., Sunnyvale, ...

1. A memory system comprising:
a memory controller to issue write data, the memory controller including:
a first link-pad generator to issue a sequence of first pad values of a first pad width; and
a first cipher circuit connected to the first link-pad generator, the first cipher circuit to combine the write data with
the first pad values to produce ciphertext of the first pad width;

data links extending from the memory controller to convey the ciphertext; and
a memory device coupled to the memory controller via a subset of the data links to receive a subset of the ciphertext, the
memory device including:

a second link-pad generator to issue a sequence of second pad values of a second pad width, the second link-pad generator
including a width-selection port to control the second pad width; and

a second cipher circuit connected to the second link-pad generator, the second cipher circuit to combine the subset of the
ciphertext with the second pad values to recover a subset of the write data.

US Pat. No. 9,466,353

METHODS AND APPARATUS FOR SYNCHRONIZING COMMUNICATION WITH A MEMORY CONTROLLER

Rambus Inc., Sunnyvale, ...

1. A controller chip to control a memory chip, the controller chip comprising:
a clock generation circuit to generate an internal clock signal;
first circuitry to receive a strobe signal from the memory chip, the first circuitry to detect a phase difference between
the internal clock signal and the strobe signal and provide a phase-adjusted clock signal; and

a plurality of receiver circuits to sample respective data bits using the phase-adjusted clock signal, the data bits being
provided by the memory chip;

wherein the strobe signal is idle absent the data bits.

US Pat. No. 9,459,952

CODE-ASSISTED ERROR-DETECTION TECHNIQUE

Rambus Inc., Sunnyvale, ...

1. A method of operation in a memory controller, the method comprising:
generating first error information for a selectively dynamic-bus-inversion (DBI)-encoded data word, the selectively DBI-encoded
data word for transfer to a memory device;

receiving second error information associated with the selectively DBI-encoded data word from the memory device;
receiving third error information associated with the selectively DBI-encoded data word from the memory device, the third
error information identifying a first type of error based on a decoding of the selectively DBI-encoded data word; and

detecting a second type of error in the data word by comparing the first error information to the second error information.

US Pat. No. 9,431,089

OPTIMIZING POWER IN A MEMORY DEVICE

Rambus Inc., Sunnyvale, ...

1. A memory device comprising:
a clock receiver circuit to receive an external clock signal and provide an internal clock signal;
a delay-locked loop circuit (DLL) having an input; and
a circuit having an input, wherein a command driven pulse selection signal and the internal clock signal drive the input of
the circuit, such that an output signal from the circuit is applied to the input of the DLL during a predetermined interval,
wherein the output signal comprises no more than two clock pulses selected from at least three consecutive pulses of the internal
clock signal.

US Pat. No. 9,419,825

SELECTABLE-TAP EQUALIZER

Rambus Inc., Sunnyvale, ...

1. An integrated circuit receiver to receive an input signal from a conductive signal path, comprising:
a clock recovery circuit to generate an edge clock;
circuitry to generate a data clock and an equalization clock, each of the data clock and the equalization clock being phase-offset
relative to the edge clock;

a sampling circuit to sample the input signal and generate digital samples according to the data clock; and
an equalization circuit to equalize the input signal, in dependence on at least one preceding digital sample, according to
the equalization clock; and

wherein during a calibration mode,
the integrated circuit receiver is to lock the edge clock against phase adjustment,
the equalization circuit is to drive a data pattern onto the conductive signal path according to the equalization clock,
the clock recovery circuit is to generate phase adjustments which track transitions in the data pattern relative to the edge
clock, and

the circuitry to generate is to adjust the equalization clock responsive to the phase adjustments which track the transitions
in the data pattern until the transitions in the data pattern align with the edge clock, to thereby establish the phase-offset
of the equalization clock relative to the edge clock for use in a normal operating mode.

US Pat. No. 9,417,807

DATA BUFFER WITH STROBE-BASED PRIMARY INTERFACE AND A STROBE-LESS SECONDARY INTERFACE

RAMBUS INC., Sunnyvale, ...

1. A data buffer comprising:
a primary interface to be coupled to a memory controller; and
a secondary interface to be coupled to at least one dynamic random-access memory (DRAM) device, and wherein the data buffer
is configured to:

receive a forwarded clock signal to sample data in a transaction between the data buffer and the at least one DRAM device;
communicate data to and from the memory controller on the primary interface using a strobe signal; and
communicate the data to and from the at least one DRAM device on the secondary interface using the forwarded clock signal.

US Pat. No. 9,362,002

STACKED SEMICONDUCTOR DEVICE

Rambus Inc., Sunnyvale, ...

1. A packaged semiconductor device comprising:
multiple integrated circuit (IC) chips arranged as a stack, each chip including multiple input/output (I/O) pads, each I/O
pad selectively coupled to an input/output (I/O ) circuit;

wherein the I/O pads for each chip in the stack are vertically aligned with corresponding I/O pads in the other stacked chips
to define vertically aligned sets of I/O pads;

wherein a given vertically aligned set of I/O pads for the stacked chips is electrically coupled via a conductive path; and
wherein less than all of the I/O circuits corresponding to a given vertically aligned set of I/O pads are electrically coupled
to the conductive path.

US Pat. No. 9,311,976

MEMORY MODULE

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
a circuit board;
a first plurality of integrated circuit (IC) components disposed on the circuit board, each of the IC components having an
address/control input, a clock input, a data output and a strobe output;

a termination structure disposed on the circuit board;
an address/control signal path coupled at one end to the termination structure and coupled to the address/control input of
each of the IC components such that control signals propagating toward the termination structure on the address/control signal
path arrive at the address/control inputs of respective IC components at progressively later times corresponding to relative
positions of the IC components;

a clock signal path coupled to the clock input of each of the IC components such that a clock signal propagating on the clock
signal path arrives at the clock inputs of respective IC components at progressively later times corresponding to the times
at which the control signals arrive at the address/control inputs of the IC components, the clock signal indicating to the
IC components respective times at which to sample the control signals arriving at their address/control inputs;

a plurality of data signal paths, each of the data signal paths extending from the data output of a respective one of the
IC components to an edge of the circuit board and including a plurality of data signal conductors to convey a respective read
data value; and

a plurality of strobe signal paths, each of the strobe signal paths extending from the strobe output of a respective one of
the IC components to the edge of the circuit board, each of the strobe signal paths to convey a strobe signal that indicates
that the read data value is present on the data signal path extending from the data output of the one of the IC components.

US Pat. No. 9,287,909

HIGH SPEED SIGNALING SYSTEM WITH ADAPTIVE TRANSMIT PRE-EMPHASIS

Rambus Inc., Sunnyvale, ...

1. A circuit board comprising:
at least one signal trace to connect to a signal path;
an integrated circuit including a multi-tap transmitter, the multi-tap transmitter operable to output a digital sequence onto
the signal path via the at least one signal trace in accordance with a set of tap weights; and

the multi-tap transmitter operable to update the set of tap weights responsive to an indication from a receiver, the indication
generated responsive to a power constraint of the multi-tap transmitter.

US Pat. No. 9,257,163

STROBE ACQUISITION AND TRACKING

RAMBUS INC., Sunnyvale, ...

1. A memory controller, comprising:
an interface to receive a data strobe signal and corresponding read data, wherein the data strobe signal and the read data
correspond to a read command issued by the memory controller, and wherein the read data is received in accordance with the
data strobe signal;

a circuit to dynamically adjust a timing offset between the read data and an internal timing signal corresponding to the data
strobe signal; and

control logic to maintain at least a predefined minimum frequency of data strobe signals received at the interface by issuing
a supplemental read command when a time interval since a last read command issued by the memory controller exceeds a first
predetermined value.

US Pat. No. 9,154,145

INTEGRATED CIRCUIT HAVING A MULTIPLYING INJECTION-LOCKED OSCILLATOR

RAMBUS INC., Sunnyvale, ...

1. A circuit, comprising:
a first injection-locked oscillator to generate a first set of output signals, the first injection-locked oscillator having
a first set of injection points, wherein each injection point in the first set of injection points is capable of receiving
a corresponding input signal in a set of input signals, wherein each input signal in the set of input signals is a delayed
version of a sequence of pulses, and wherein the sequence of pulses includes return-to-null pulses; and

a second injection-locked oscillator to generate a second set of output signals, the second injection-locked oscillator having
a second set of injection points, wherein each injection point in the second set of injection points is capable of receiving
a corresponding output signal in the first set of output signals.

US Pat. No. 9,123,433

MEMORY COMPONENT WITH PATTERN REGISTER CIRCUITRY TO PROVIDE DATA PATTERNS FOR CALIBRATION

RAMBUS INC., Sunnyvale, ...

1. A memory component comprising;
a memory core;
a first circuit to receive external commands, the external commands including a read command that specifies transmitting data
accessed from the memory core;

a second circuit to transmit data onto an external bus in response to a read command;
pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern,
wherein, during the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the
second circuit onto the external bus in response to a read command received during the calibration.

US Pat. No. 9,691,447

MEMORY CONTROLLER WITH STAGGERED REQUEST SIGNAL OUTPUT

Rambus Inc., Sunnyvale, ...

18. An integrated circuit (IC) chip comprising:
memory control circuitry including request logic to generate a memory access request, the memory access request including
command information and control information, the control information to be used by a memory device to receive the command
information;

a first output driver circuit to launch the control information to the memory device; and
a second output driver circuit to launch the command information in accordance with a programmable offset after launch of
the control information.

US Pat. No. 9,507,738

METHOD AND SYSTEM FOR SYNCHRONIZING ADDRESS AND CONTROL SIGNALS IN THREADED MEMORY MODULES

Rambus Inc., Sunnyvale, ...

1. A memory module, comprising:
interface circuitry to receive from an external bus addresses for memory locations addressed by memory commands;
memory devices; and
an internal bus electronically coupling the memory devices with the interface circuitry in a manner such that the addresses
and a clock signal arrive together at a first one of the memory devices at a first time and then, sequentially, arrive together
at a second one of the memory devices at a second time;

wherein the interface circuitry is to also receive a first control signal and a second control signal from the external bus,
the first control signal to control the first one of the memory devices responsive to each of the memory commands, the second
control signal to control the second one of the memory devices responsive to each of the memory commands.

US Pat. No. 9,449,676

DRIVER CIRCUIT

Rambus Inc., Sunnyvale, ...

1. A method of operation in a memory controller, the method comprising:
operating a pull-up driver within a first voltage swing range;
operating a pull-down driver within a second voltage swing range that is not coterminal with the first voltage swing range,
synchronizing data signals driving the pull-up driver and the pull-down driver, and producing an output signal having a voltage
swing based on a coupled configuration of the pull-up driver and the pull-down driver.

US Pat. No. 9,430,324

MEMORY REPAIR METHOD AND APPARATUS BASED ON ERROR CODE TRACKING

Rambus Inc., Sunnyvale, ...

1. A memory module comprising:
a substrate;
a memory device disposed on the substrate, the memory device to output read data; and
a buffer having a primary interface for transferring the read data to a memory controller and a secondary interface coupled
to the memory device, the secondary interface to receive the read data, the buffer including

error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated
with the error, and

repair logic to map a replacement storage element as a substitute storage element for the storage cell location associated
with the error.

US Pat. No. 9,390,777

MEMORY CONTROLLER FOR STROBE-BASED MEMORY SYSTEMS

Rambus Inc., Sunnyvale, ...

1. An integrated circuit (IC) memory controller comprising:
a timing signal pin to receive a timing signal having first timing information;
a delay circuit to delay an enable signal by a selectable delay to generate a delayed enable signal having second timing information,
the enable signal corresponding to transitions of the timing signal that indicate the presence of valid data;

a mask circuit to generate a masked timing signal using the first timing information and the second timing information; and
a sampler to sample data using the masked timing signal.

US Pat. No. 9,230,609

MEMORY BANDWIDTH AGGREGATION USING SIMULTANEOUS ACCESS OF STACKED SEMICONDUCTOR MEMORY DIE

Rambus Inc., Sunnyvale, ...

1. A packaged semiconductor memory device, comprising:
a data pin;
a first memory die comprising:
a first data interface coupled to the data pin, and
a first memory core having a plurality of banks; and
a second memory die stacked with the first memory die and comprising a second memory core having a plurality of banks; wherein:
a respective bank of the first memory core and a respective bank of the second memory core are to perform parallel row access
operations in response to a first command signal and parallel column access operations in response to a second command signal;
and

the first data interface is to provide aggregated data from the parallel column access operations to the data pin.

US Pat. No. 9,209,966

CLOCK RECOVERY CIRCUIT

Rambus Inc., Sunnyvale, ...

1. An integrated circuit, comprising:
a receiver to receive a digital signal from a signal path; and
a clock recovery circuit to generate a recovered clock from the digital signal;
wherein the clock recovery circuit
is to receive a first phase detection signal representing a comparison of timing of the digital signal with timing of the
recovered clock signal, the first phase detection signal to vary linearly with phase difference,

is to receive a second phase detection signal representing a binary comparison of the digital signal with timing of the recovered
clock signal, and

comprises a variable frequency oscillator to generate the recovered clock in dependence on each of the first phase detection
signal and the second phase detection signal.

US Pat. No. 9,166,650

CAPACITIVE-COUPLED CROSSTALK CANCELLATION

Rambus Inc., Sunnyvale, ...

1. A transmitter to convey signals to a receiver over a parallel bus that includes at least first and second signal lines,
comprising:
a first driver to transmit a first signal to the receiver via the first signal line;
a second driver to transmit a second signal to the receiver via the second signal line;
a first coupling circuit to capacitively-couple a representation of the first signal to the second signal line; and
a second coupling circuit to capacitively-couple a representation of the second signal to the first signal line;
where each of the first coupling circuit and the second coupling circuit comprises a driver in series with a capacitor.

US Pat. No. 9,116,781

MEMORY CONTROLLER AND MEMORY DEVICE COMMAND PROTOCOL

Rambus Inc., Sunnyvale, ...

1. A method of operation of a memory controller, the method comprising:
transmitting a first command that specifies assertion of a wordline of a memory device, wherein assertion of the wordline
connects a plurality of memory cells to a plurality of bitlines;

transmitting a second command that specifies connecting the plurality of bitlines to a plurality of sense amplifiers, wherein
the plurality of sense amplifiers sense data stored in the plurality of memory cells in response to the second command; and

transmitting a third command that specifies a data transfer operation and is accompanied by a column address, wherein the
column address specifies a subset that is less than all of the plurality of sense amplifiers for the data transfer operation.

US Pat. No. 9,059,695

METHODS AND SYSTEMS FOR REDUCING SUPPLY AND TERMINATION NOISE

Rambus Inc., Sunnyvale, ...

1. An integrated circuit supporting a transmit mode and a receive mode, the integrated circuit comprising:
at least one reference termination element connected to a reference pad to exhibit a transmit-reference signal on the reference
pad in the transmit mode and a receive-reference signal different from the transmit-reference signal on the reference pad
in the receive mode; and

data transceivers, each data transceiver coupled to the reference pad and to a respective information pad, each transceiver
to transmit a transmit-data signal in the transmit mode and to compare a respective receive-data signal with the receive-reference
signal in the receive mode.

US Pat. No. 9,470,823

PHASE GRATINGS WITH ODD SYMMETRY FOR OPTICAL SENSING

Rambus Inc., Sunnyvale, ...

1. An imaging device to sense incident light over a wavelength band of interest, the imaging device comprising:
photosensitive elements defining a focal plane; and
a phase grating defining a transverse plane, spaced from the focal plane, to modulate the incident light, the phase grating
including:

pairs of adjacent segments, each pair of adjacent segments defining between them a boundary extending away from a center in
the transverse plane, each segment widening in the transverse plane as a function of distance from the center and in a dimension
perpendicular to the boundary;

the boundaries producing curtains of minimum intensity separated by foci and extending to the focal plane.

US Pat. No. 9,361,960

CONFIGURABLE MEMORY BANKS OF A MEMORY DEVICE

RAMBUS INC., Sunnyvale, ...

1. A method of operating a memory module, comprising:
providing a storage array having a plurality of memory banks and a first set of memory segments, wherein each of the plurality
of memory banks includes a second set of memory segments;

in a first mode of operation, using the first set of memory segments as an additional memory bank; and
in a second mode of operation, accessing a memory segment in the first set of memory segments in parallel with a corresponding
one of the plurality of memory banks;

wherein in the first mode of operation, each accessible memory bank of the memory module has a first number of memory segments
accessible in parallel, and in the second mode of operation, each accessible memory bank of the memory module has a second
number of memory segments accessible in parallel, wherein the second number is greater than the first number, and the first
number of memory segments is an integer multiple of 8 and the second number of memory segments is an integer multiple of 9;
and

wherein a total number of memory segments accessible in the first mode of operation is the same as a total number of memory
segments accessible in the second mode of operation.

US Pat. No. 9,337,872

CONFIGURABLE, ERROR-TOLERANT MEMORY CONTROL

Rambus Inc., Sunnyvale, ...

1. An integrated-circuit memory component comprising:
a data storage array;
a command/address interface to receive command/address information via a variable number of external signaling links in accordance
with a command/address interface width indicated by a width configuration value, the command/address information specifying
a storage location within the data storage array and a memory access operation to be executed with respect to the storage
location;

an error information interface to receive error-checking information via one or more error information links external to the
integrated-circuit memory component; and

error circuitry to detect errors within the command/address information using the error-checking information according to
(i) a first error detection scheme if the width configuration value indicates a first command/address interface width in which
the command/address information is to be received via a first number of external signaling links, and (ii) a second error
detection scheme if the width configuration value indicates a second command/address interface width in which the command/address
information is to be received via a second number of external signaling links, wherein the first and second error detection
schemes are different from one another and the first and second numbers of external signaling links are different from one
another.

US Pat. No. 9,275,699

MEMORY WITH ALTERNATIVE COMMAND INTERFACES

Rambus Inc., Sunnyvale, ...

1. A memory device for storing and retrieving data responsive to memory commands, the memory device comprising:
memory banks;
control logic having a command interface to receive the memory commands, the control logic to extract memory control signals
and memory addresses from the memory commands to provide access to each and every one of the memory banks on the memory device;
and

a command multiplexer having alternative first and second command ports, the command multiplexer to direct the memory commands
from the first command port to the command interface in a first mode, and to direct the memory commands from the second command
port to the command interface in a second mode;

the control logic providing access to each and every one of the memory banks on the memory device responsive to the commands
from the first command port in the first mode, and providing access to each and every one of the memory banks on the memory
device responsive to the commands from the second command port in the second mode.

US Pat. No. 9,391,613

CALIBRATION METHODS AND CIRCUITS TO CALIBRATE DRIVE CURRENT AND TERMINATION IMPEDANCE

Rambus Inc., Sunnyvale, ...

1. An integrated circuit (IC) chip comprising:
transceiver circuits, each including a driver circuit to transmit data, a receiver circuit to receive data, each driver circuit
including an on-die termination element exhibiting a termination impedance;

a termination control circuit coupled to the transceiver circuits, the termination control circuit to calibrate the termination
impedances and a voltage swing of the driver circuits, the termination control circuit including:

a reference-impedance pad to couple to a reference resistor external to the chip;
a reference-voltage pad to couple to a reference voltage source external to the chip;
a comparator to compare a reference-resistor voltage on the reference-impedance pad with an external reference voltage on
the reference-voltage pad and develop first control settings responsive to the comparison; and

an adjustable impedance, coupled to the comparator, the comparator to compare the reference-resistor voltage on the reference-voltage
pad with a voltage from the adjustable impedance to develop second control settings responsive to the comparison between the
reference-resistor voltage and the voltage from the adjustable impedance; and

a bus extending between the termination control circuit and the transceiver circuits, the bus to communicate the first control
settings to the transceiver circuits.

US Pat. No. 9,323,711

CHIP HAVING PORT TO RECEIVE VALUE THAT REPRESENTS ADJUSTMENT TO TRANSMISSION PARAMETER

Rambus Inc., Sunnyvale, ...

1. A flash memory device, comprising:
memory for storing data;
a bidirectional port of a bus for receiving a parameter whose value varies in accordance with a count of devices on the bus
to be driven via the bidirectional port, the parameter to set a transmission parameter of the flash memory device;

a register for storing a parameter control value corresponding to the parameter, received via the bidirectional port, whose
value varies in accordance with the count of devices on the bus to be driven via the bidirectional port;

adjustment circuitry for setting the transmission parameter in accordance with the parameter control value; and,
an output driver, coupled to the bidirectional port for driving data via the bidirectional port, the data retrieved from the
memory, the data to be driven in accordance with the parameter control value.