US Pat. No. 9,069,923

IP PROTECTION

GLOBALFOUNDRIES SINGAPORE...

1. A method of forming a device comprising:
providing a substrate with a device layer;
providing a MPW mask comprising first and second patterns of first and second chiplets pertaining to first and second IP owners,
the MPW mask is used to form a device for the first IP owner, wherein the first pattern of the first chiplet is according
to that of the first IP owner and the second pattern of the second chiplet is a modified second pattern, the modified second
pattern is different from that according to the second IP owner to protect IP information of the second IP owner from disclosure
to the first IP owner;

providing an exposure source to expose the substrate using the MPW mask without providing a cover on the MPW mask over the
second chiplet;

patterning the device layer in first and second chiplet regions after the exposure, wherein the first pattern of the first
chiplet is transferred to the device layer and the second pattern with IP protection of the second chiplet is transferred
to the device layer;

delivering the device to the first IP owner, the device includes first and second chiplets, wherein the second chiplet includes
IF protection to reduce disclosure of IP information of the second IP owner to the first IP owner; and

continue processing of the device to form the desired function of the device.

US Pat. No. 9,141,163

PORTABLE TERMINAL, RECORDING MEDIUM

NTT DOCOMO, INC., Chiyod...

1. A portable terminal comprising;
a host;
a battery;
a power controller, which includes a first host power controller, a second host power controller, a first contactless front
end (CLF) power controller, and a second CLF power controller;

a chip card in the portable terminal;
a CLF;
an antenna;
a first switch;
a second switch; and
a switch controller,
wherein the power controller supplies power generated by the battery to the host, the chip card in the portable terminal,
and the CLF,

the first switch is connected to open or close a power supply channel to the chip card in the portable terminal and a single
wire protocol (SWP) interface, branching off from a power supply channel from the second host power controller to the host,

the second switch is connected to open or close a power supply channel to the chip card in the portable terminal and the SWP
interface, branching off from a power supply channel from the second CLF power controller to the CLF,

the switch controller opens the first switch and closes the second switch when a) the CLF detects a contactless RF signal,
b) the host is off or the portable terminal is in a low battery mode, and c) the contactless RF signal conforms to the communication
method of the chip card in the portable terminal, and

the switch controller closes the first switch and opens the second switch when the host is on.

US Pat. No. 9,059,002

NON-MERGED EPITAXIALLY GROWN MOSFET DEVICES

INTERNATIONAL BUSINESS MA...

1. A method for forming semiconductor devices, comprising:
forming fins on a substrate;
forming a dummy gate over the fins, leaving a source and drain region exposed;
forming an insulator layer around the fins after forming the dummy gate;
etching the fins below a surface level of the insulator layer; and
epitaxially growing fin extensions from the etched fins that extend vertically and laterally beyond the etched fins.

US Pat. No. 9,275,256

SEMICONDUCTOR INTEGRATED CIRCUIT

Renesas Electronics Corpo...

1. A method of a semiconductor integrated circuit comprising a logic circuit including n storage elements (n is a positive
integer) which can each store 1-bit information and an attack detection circuit, the method comprising:
detecting, by an error determination circuit, through a logic operation that k-bit or less errors (k is a positive integer)
have occurred in n-bit codes stored in the n storage elements;

detecting, by a light irradiation detection circuit which includes light detection elements, that light has been irradiated
to (k+1) or more of the n storage elements; and

determining that the logic circuit has been attacked from outside when the error determination circuit detects an error or
the light irradiation detection circuit detects light irradiation.

US Pat. No. 9,325,358

METHOD FOR REDUCING SECOND ORDER DISTORTION IN HARMONIC REJECTION MIXER

IMEC, Leuven (BE) Renesa...

1. A method for reducing second order intermodulation distortion in a harmonic rejection mixer arranged for down-converting
a radio frequency signal to an in-phase and a quadrature baseband signal, the harmonic rejection mixer including a plurality
of mixers arranged for multiplying the radio frequency signal with a plurality of local oscillator signals, each local oscillator
signal having a different phase with respect to the other local oscillator signals, thereby obtaining a plurality of down-converted
signals having different phases with respect to each other, a plurality of amplifiers arranged for amplifying each down-converted
signal with an amplification factor depending on its phase, and a plurality of summing means for summing the plurality of
amplified down-converted signals to produce the in-phase and the quadrature baseband signals, the method comprising:
adjusting an output current of a first mixer, to reduce the second order intermodulation distortion in the quadrature baseband
signal to a first value, wherein the first mixer is not contributing to the reconstruction of the in-phase baseband signal;
and

adjusting an output current of a second mixer, to reduce the second order intermodulation distortion in the in-phase baseband
signal to a second value, wherein the second mixer is not contributing to the reconstruction of the quadrature baseband signal.

US Pat. No. 9,349,743

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device equipped with a memory cell of a nonvolatile memory, comprising the steps
of:
(a) providing a semiconductor substrate;
(b) forming a first gate electrode for the memory cell over the semiconductor substrate via a first insulating film;
(c) forming a second gate electrode for the memory cell over the semiconductor substrate via a second insulating film having
therein a charge storage portion so as to be adjacent to the first gate electrode;

(c1) after the step (c), forming a dummy gate electrode over the semiconductor substrate;
(d) after the step (c1), forming a first semiconductor region for source or drain of the memory cell in the semiconductor
substrate by ion implantation;

(e) after the step (d), forming sidewall insulating films on respective side walls of the first gate electrode and the second
gate electrode which are on the sides opposite to the side walls adjacent to each other;

(f) after the step (e), forming a second semiconductor region for source or drain of the memory cell in the semiconductor
substrate by ion implantation;

(g) after the step (f), forming a first interlayer insulating film so as to cover the first gate electrode, the second gate
electrode, and the dummy gate electrode; and

(h) polishing the first interlayer insulating film to expose the first gate electrode, the second gate electrode, and the
dummy gate electrode,

wherein the second gate electrode formed in the step (c) is adjacent to the first gate electrode via the second insulating
film,

wherein the second semiconductor region formed in the step (f) has the same conductivity type as that of the first semiconductor
region and has an impurity concentration higher than that of the first semiconductor region,

wherein in the step (h), an upper portion of the second insulating film present between the first gate electrode and the second
gate electrode is removed,

wherein a removal length of the second insulating film in the step (h) is larger than a depth of the second semiconductor
region formed in the step (f), and

wherein the method further comprises the steps of:
(i) after the step (h), removing the dummy gate electrode; and
(j) forming a third gate electrode in a trench which is a region from which the dummy gate electrode has been removed by the
step (i).

US Pat. No. 9,293,396

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the following steps of:
(a) preparing a lead frame that comprises a die pad having a first plane and a second plane located on the opposite side of
the first plane, and a plurality of leads arranged next to the die pad;

(b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side
located on the opposite side of the surface over a chip mounting area of the first plane of the die pad;

(c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires
and electrically coupling the other parts of the electrodes and the die pad through a second wire after the step (b); and

(d) after the steps above, sealing the semiconductor chip, the first wires, and the second wire with a resin so that a part
of each of the leads and the second plane of the die pad may be exposed after the step (c),

wherein an area of the first plane of the die pad is larger than an area of the reverse side of the semiconductor chip,
wherein the first plane of the die pad has the chip mounting area, a first bonding area that is located between the chip mounting
area and the leads and to which the second wire is bonded, and a first hollow part arrangement area that is located between
the first bonding area and the chip mounting area and in which a groove or a plurality of holes are formed, and

wherein surface roughness of the first plane in the chip mounting area, the first bonding area, and the first hollow part
arrangement area is coarser than surface roughness of the second plane.

US Pat. No. 9,356,126

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:
defining, in a main surface of a semiconductor substrate, first through third element formation regions using isolation insulating
films;

forming a first gate electrode over a surface of the first element formation region;
forming a second gate electrode between one of side walls of the first gate electrode and the surface of the first element
formation region with an insulating film holding charges being disposed therebetween;

forming an offset spacer over a side wall of the second gate electrode;
after forming the offset spacer, forming a third gate electrode over a surface of the second element formation region and
forming a fourth gate electrode over a surface of the third element formation region;

implanting a predetermined impurity into a first area of the first element formation region which is located on a side on
which the second gate electrode of the first and second gate electrodes is disposed to form an impurity region of a predetermined
conductivity type; and

removing the offset spacer.

US Pat. No. 9,190,409

REPLACEMENT METAL GATE TRANSISTOR WITH CONTROLLED THRESHOLD VOLTAGE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a semiconductor substrate; and
an N-channel transistor and a P-channel transistor provided on the semiconductor substrate, each of the N-channel transistor
and the P-channel transistor respectively having a gate dielectric film on said semiconductor substrate, and a gate electrode
respectively formed on said gate dielectric,

wherein each said gate electrode comprises a metal conductive layer,
wherein an oxygen concentration in said metal conductive layer for the N-channel transistor differs from that for the P-channel
transistor,

wherein said metal conductive layer includes a component which serves to provide a work function metal having a strong bond
with oxygen so as to provide a high thermal stability, and

wherein said component providing a strong bond with oxygen comprises aluminum.

US Pat. No. 9,391,686

WIRELESS COMMUNICATION SYSTEM AND DATA TRANSMITTER

Renesas Electronics Corpo...

1. A wireless communication system comprising:
a first radio equipment that transmits first data using a first radio wave;
a data transmitter that transmits a second radio wave, the second radio wave causing a disturbance on the first radio wave
according to second data to be transmitted; and

a second radio equipment that demodulates the first data transmitted from the first radio equipment, and demodulates the second
data transmitted from the data transmitter using a variation in a bit error rate of communication between the first radio
equipment and the second radio equipment, wherein

the data transmitter includes:
a first antenna that receives the first radio wave;
an input amplifier that amplifies a signal corresponding to the first radio wave received by the first antenna;
an oscillator that is supplied with an output from the input amplifier, and oscillates at the same frequency as that of the
first radio wave;

an output amplifier that amplifies a signal output from the oscillator; and
a modulator that modulates a signal output from the output amplifier according to the second data; and
a second antenna that transmits the modulated signal as the second radio wave.

US Pat. No. 9,324,790

SELF-ALIGNED DUAL-HEIGHT ISOLATION FOR BULK FINFET

INTERNATIONAL BUSINESS MA...

1. A method of forming a semiconductor structure, the method comprising:
forming a first isolation region between fins of a first group of fins and between fins of a second group of fins, the first
and second group of fins being formed in a bulk semiconductor substrate, wherein said forming said first isolation region
comprises:

conformally depositing a first dielectric layer above the bulk semiconductor substrate and between the first and second group
of fins,

forming a dummy material on a portion of said first dielectric layer that is located between said first and second group of
fins, said dummy material having a topmost surface that is coplanar with a topmost surface of the first dielectric layer that
is located atop the first and second group of fins, and

recessing exposed portions of said first dielectric layer selective to said first and second group of fins and said dummy
material; and

forming a second isolation region between the first group of fins and the second group of fins, the second isolation region
extending through a portion of the first isolation region such that the first and second isolation regions are in direct contact
and a height above the bulk semiconductor substrate of the second isolation region is greater than a height above the bulk
semiconductor substrate of the first isolation region, wherein said forming said second isolation region comprises removing
said dummy material and etching entirely through a remaining portion of said first dielectric layer and partially into said
bulk semiconductor substrate.

US Pat. No. 9,412,669

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing a semiconductor device including a first MISFET and a second MISFET, comprising steps of:
(a) forming a first gate electrode of the first MISFET over a semiconductor substrate;
(b) forming a second gate electrode of the second MISFET over the semiconductor substrate;
(c) forming a first film including silicon and nitrogen over the first and second MISFETs to cover the first and second gate
electrodes;

(d) after the step (c), forming a second film including silicon and oxygen over the first film;
(e) after the step (d), patterning the first and second films, so that the first and second films of the first MISFET are
kept and the first and second films of the second MISFET are removed;

(f) after the step (e), forming a third film including silicon and nitrogen over the first and second MISFETs in order to
cover the first and second gate electrodes; and

(g) after the step (f), patterning the third film, so that the third film of the first MISFET is removed and the third film
of the second MISFET is kept.

US Pat. No. 9,312,327

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a substrate;
a transistor which is formed over the substrate;
a capacitor which is electrically coupled to the transistor and includes a first electrode electrically coupled to the transistor,
a second electrode separate from the first electrode, and a capacitance insulating film situated between the first electrode
and the second electrode;

an insulating cover film which covers the second electrode;
a plurality of coupling holes which are formed in the insulating cover film and whose lower ends are each in contact with
the second electrode; and

vias which are embedded in the coupling holes,
wherein, when the capacitance of the second electrode is represented by C [nF] and the total area of the lower ends of the
coupling holes is represented by A [?m2], the following expression (1) is satisfied

C/A?1.98 [nF/?m2].  (1)

US Pat. No. 9,306,027

SEMICONDUCTOR DEVICE AND A METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a first nitride semiconductor layer formed over a substrate;
a second nitride semiconductor layer formed over the first nitride semiconductor layer, and wider in band gap than the first
nitride semiconductor layer;

a trench formed in the second nitride semiconductor layer, the trench penetrating through the second nitride semiconductor
layer and reaching the first nitride semiconductor layer at a bottom surface thereof,

a first insulation film formed over the second nitride semiconductor layer to surround the trench;
a gate insulation film being formed over the first insulation film and being formed on a side surface and the bottom surface
of the trench;

a gate electrode formed on the gate insulation film to overlap with the first insulation film; and
a first electrode and a second electrode formed over the second nitride semiconductor layer on the opposite sides of the gate
electrode, respectively,

wherein the first insulation film has a first silicon nitride film in contact with the second nitride semiconductor layer,
and a second silicon nitride film formed over the first silicon nitride film in contact with the gate insulating film,

wherein the second silicon nitride film is larger in composition ratio of silicon (Si) than the first silicon nitride film,
wherein the first silicon nitride film is larger in composition ratio of nitrogen (N) than the second silicon nitride film,
and

wherein a portion of the gate electrode is provided at least over the second silicon nitride film.

US Pat. No. 9,510,417

LED DRIVE METHOD AND LED DRIVE DEVICE

Renesas Electronics Corpo...

1. An LED drive method that drives an LED by a drive current, the LED drive method using:
a voltage conversion unit which includes a coil and a first switch, and which converts an external voltage into a first voltage,
which is a DC voltage, by controlling the first switch to be on in an on-pulse period of a first drive signal;

a constant current drive unit which is provided with the first voltage and which generates a drive current having a current
value according to light control information inputted from outside; and

a control unit,
wherein the control unit performs:
a first step of comparing brightness based on the light control information and a predetermined reference brightness;
a second step of generating the first drive signal based on an error between the first voltage and a target voltage representing
a target of the first voltage in a first case in which brightness based on the light control information is higher than the
predetermined reference brightness; and

a third step of generating the first drive signal having a predetermined fixed on-pulse period in a second case in which the
brightness based on the light control information is lower than the predetermined reference brightness, and

wherein, in the second step, the control unit performs:
a fourth step of converting the first voltage into a first digital value proportional to the first voltage; and
a fifth step of calculating an error between the first digital value and a target voltage digital value representing the target
of the first voltage and determining the on-pulse period of the first drive signal by a digital calculation using the error
as an input.

US Pat. No. 9,349,439

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising a memory circuit including a memory cell having a first field-effect transistor of a
first conductive type and a second field-effect transistor of a second conductive type different from the first conductive
type,
wherein the memory cell has:
an active mode in which the first field-effect transistor is activated by a first threshold voltage and the second field-effect
transistor is activated by a second threshold voltage; and

a standby mode in which the first field-effect transistor is activated by a third threshold voltage higher than the first
threshold voltage and the second field-effect transistor is activated by a fourth threshold voltage higher than the second
threshold voltage, and

when a mode is shifted from the active mode to the standby mode, a threshold voltage of the first field-effect transistor
is shifted temporarily from the first threshold voltage to a fifth threshold voltage between the first threshold voltage and
the third threshold voltage, and a threshold voltage of the second field-effect transistor is shifted temporarily from the
second threshold voltage to a sixth threshold voltage between the second threshold voltage and the fourth threshold voltage.

US Pat. No. 9,369,261

CIRCUIT FOR BASEBAND HARMONIC REJECTION

IMEC, Leuven (BE) RENESA...

1. A circuit for reducing counter-intermodulation in a modulated signal caused by an oscillator frequency and harmonics of
a baseband signal, the circuit comprising:
a first baseband section configured to generate a first baseband signal comprising a first in-phase component and a first
quadrature component;

a second baseband section configured to generate a second baseband signal, the second baseband signal being phase shifted
with respect to the first baseband signal, the second baseband signal comprising a second in-phase component and a second
quadrature component being phase shifted from the respective first components; and

three signal paths, each signal path comprising a mixer for multiplication of the first and second baseband signals with a
local oscillator signal, whereby the local oscillator signal in one signal path is a phase-rotated version of the local oscillator
signal in the other two signal paths, so that three upconverted signals with rotated phase with respect to each other are
obtained, and each signal path further comprising a scaling unit configured to apply a scaling factor dependent on the rotated
phases; and

a combination unit configured to combine the three upconverted signals.

US Pat. No. 9,532,455

SEMICONDUCTOR DEVICE AND CIRCUIT BOARD

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a semiconductor chip;
a plurality of external terminals; and
a board for electrically connecting the semiconductor chip and the external terminal,
wherein the board includes
a first main surface in which a plurality of first electrodes electrically connected to the semiconductor chip are formed,
a second main surface, facing the first main surface, in which a plurality of second electrodes electrically connected to
the plurality of external terminals are formed, and

a plurality of interconnect layers, provided between the first main surface and the second main surface, for forming a plurality
of signal paths that electrically connect the first electrode and the second electrode corresponding thereto, and

the interconnect layers include a plurality of metal members which are dispersedly disposed in equidistance at a distance
shorter than an electromagnetic wavelength equivalent to a signal band of a signal supplied to the signal paths, in a vicinity
of a portion in which an interconnect for forming the signal paths has a different structure than an adjacent interconnect.

US Pat. No. 9,474,124

OUTPUT CIRCUIT

Renesas Electronics Corpo...

1. A Light Emitting Diode (LED) drive circuit, comprising:
an input port;
an output port coupled to an LED circuit;
an output circuit that outputs a first current or a second current to the output port, the first current having a predetermined
current value and the second current having a current value higher than the predetermined current value; and

a short-circuit detection circuit that detects a short circuit in the LED circuit,
wherein the output circuit outputs the first current when the LED drive circuit receives an input signal from the input port,
and

wherein the output circuit switches to output the second current when the short-circuit detection circuit does not detect
the short circuit after the first current is outputted.

US Pat. No. 9,166,036

POWER MOSFET, AN IGBT, AND A POWER DIODE

Renesas Electronics Corpo...

1. A power MOSFET comprising:
(a) a source electrode disposed over a first main surface of a semiconductor substrate, the semiconductor substrate having
the first main surface and a second main surface, and assuming a substantially rectangular shape;

(b) a first conductivity type drift region disposed in a semiconductor surface region over almost an entire surface on the
first main surface side of the semiconductor substrate;

(c) an active cell region disposed at a substantially central part over the first main surface, being almost equal in orientation
to the semiconductor substrate, and having a substantially rectangular shape, a plurality of peripheral side regions disposed
along each side of the active cell region, and in the outside thereof, and, a plurality of peripheral corner regions disposed
in the outside of each corner part of the active cell region; and

(d) a ring-shaped field plate disposed over the first main surface in a peripheral super-junction region of the drift region
in such a manner as to surround the active cell region, where a plurality of second conductivity type regions are disposed
in the peripheral super-junction region,

wherein the field plate has an ohmic contact part which contacts the semiconductor surface region and extends over at least
one of the second conductivity type regions in at least one of the peripheral side regions, and the ohmic contact part does
not contact the semiconductor surface region in any of the peripheral corner regions.

US Pat. No. 9,104,470

TASK PROCESSOR

Renesas Electronics Corpo...

1. A task control circuit connected via a signal line to a processor which executes a task, comprising:
a state register that stores state data representing state of a task; and
a task switching circuit that controls state of a task, wherein
the task switching circuit, when a system call signal is received from the processor, reads out a parameter from an internal
register of the processor by itself, performs a system call process based on the parameter, updates the state data, and writes
back a return value resulting from the system call process in the internal register by itself.

US Pat. No. 9,348,403

SEMICONDUCTOR DEVICE AND AUTOMOBILE CONTROL SYSTEM

Renesas Electronics Corpo...

1. A microcontroller having a normal operation mode and a low-power operation mode, the microcontroller comprising:
a phase locked loop (PLL) circuit that receives a clock signal and generates a first clock in response to the clock signal
in a normal-oscillation mode, and that generates a second clock independently from the clock signal in a self-oscillation
mode; and

a central processing unit (CPU) that operates with the first clock or the second clock in the normal operation mode, and that
stops its operation in the low-power operation mode,

wherein when the microcontroller returns to the normal operation mode from the low-power operation mode after the microcontroller
switches to the low-power operation mode from the normal operation mode, an operation mode of the PLL circuit is determined
by the operation mode of the PLL circuit before the switching.

US Pat. No. 9,294,264

HIGH-FREQUENCY SIGNAL PROCESSING DEVICE AND WIRELESS COMMUNICATION SYSTEM

Renesas Electronics Corpo...

1. A wireless communication system comprising:
an antenna configured to receive a radio frequency signal;
a duplexer coupled with the antenna;
a low noise amplifier configured to amplify the radio signal via the duplexer and output a reception signal;
a reception mixer circuit configured to output a reception baseband signal based on the reception signal;
a reception phase-locked loop circuit configured to provide a reception local signal to the reception mixer circuit,
the reception phase-locked loop circuit operating in synchronization with a first clock signal of a first frequency;
a baseband processing unit configured to output a transmission baseband signal based on the reception baseband signal;
a transmission mixer circuit configured to output a modulated signal based on the transmission baseband signal,
a transmission phase-locked loop circuit configured to provide a transmission local signal to the transmission mixer circuit,
the transmission phase-locked loop circuit operating in synchronization with a second clock signal of a second frequency;
and

a power amplifier configured to amplify the modulated signal and output a transmission signal to the duplexer,
wherein the reception mixer circuit outputs the reception baseband signal based on the reception local signal,
wherein the transmission mixer circuit outputs the modulated signal based on the transmission local signal,
wherein the reception phase-locked loop circuit is configured to select the first frequency based on first frequency band
information of a reception standard such that a spurious signal frequency does not overlap with a predetermined signal band
of the reception standard centered at a transmission carrier frequency,

wherein the transmission phase-locked loop circuit is configured to select the second frequency based on a second frequency
band information of a transmission standard such that a spurious signal frequency does not overlap with a predetermined signal
band of the transmission standard centered at a receiving carrier frequency.

US Pat. No. 9,263,280

SEMICONDUCTOR DEVICE WITH EQUIPOTENTIAL RING CONTACT AT CURVED PORTION OF EQUIPOTENTIAL RING ELECTRODE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device which comprises an active area formed in a semiconductor body, the semiconductor
body having a polygonal contour, the semiconductor device comprising:
forming an Equipotential Ring (EQR) electrode over the semiconductor body so as to surround the active area, the EQR electrode
having curved portions at corners of the polygonal contour;

forming an insulating film covering the semiconductor body and the EQR electrode;
removing a part of the insulating film, and forming a source contact hole in the active area from which the semiconductor
body is exposed, and EQR contact holes only in the curved portions of the EQR electrode from which the EQR electrode and the
semiconductor body outside the EQR electrode are exposed, at the same time, in which each of the EQR contact holes has an
opening larger than that of the source contact hole;

depositing a conductive material on the insulating film and within the source contact hole and the EQR contact holes; and
etching the conductive material until an upper surface of the insulating film is exposed, forming a source contact and EQR
contact at the same time, in which an upper surface of the EQR contact is lower in level than an upper surface of the insulating
film and an upper surface of the source contact.

US Pat. No. 9,331,031

WIRELESS COMMUNICATION SYSTEM

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a semiconductor chip including:
a low noise amplifier configured to amplify a radio frequency signal;
a plurality of pads disposed over the main surface; and
an insulating resin covering the semiconductor chip,
wherein the plurality of pads includes:
an input pad coupled with an input node of the low noise amplifier;
a plurality of ground pads coupled with ground voltage level,
wherein the input pad is located between two of the plurality of ground pads,
wherein the input pad is adjacent to at least one of the two of the plurality of ground pads.

US Pat. No. 9,276,462

VOLTAGE REGULATOR CONTROLLER AND SYSTEM INCLUDING VOLTAGE REGULATOR CONTROLLER

Renesas Electronics Corpo...

1. A controller for controlling a voltage regulator that supplies a power supply voltage supplied to a load, the controller
comprising:
a differential amplifier that outputs a measurement voltage corresponding to the power supply voltage supplied to the load;
an error amplifier including an non-inverting input terminal and an inverting input terminal that compares a target voltage
and the measurement voltage and controls the voltage regulator, the non-inverting input terminal being supplied with the target
voltage, and the inverting input terminal being supplied with the measurement voltage; and

a digital-to-analog conversion circuit that applies an offset voltage to the inverting input terminal in response to a change
in a voltage value of the power supply voltage supplied to the load,

wherein the offset voltage is changed according to digital data supplied to the digital-to-analog conversion circuit.

US Pat. No. 9,246,720

SEMICONDUCTOR DEVICE AND RECEIVER

Renesas Electronics Corpo...

1. A receiver configured to receive an input signal through power lines, comprising:
a narrow band noise detector configured to detect narrow band noise frequency in an input signal;
a reference signal generator configured to generate a second reference signal whose amplitude value corresponding to the narrow
band noise frequency of a first reference signal has been reduced,

a correlation calculator configured to calculate a correlating value between the input signal and the second reference signal,
and

a demodulator configured to perform frame synchronization processing of the input signal using the correlating value and to
generate a demodulating signal,

wherein the reference signal generator comprises:
an amplitude adjuster configured to reduce amplitude value of the first reference signal corresponding to the narrow band
noise frequency to generate a second frequency domain reference signal, and

a converter configured to convert the second frequency domain reference signal to a second time domain reference signal, and
configured to supply the correlation calculator with the second time domain reference signal as the second reference signal.

US Pat. No. 9,563,443

INFORMATION PROCESSING DEVICE, PERIPHERAL DEVICE CONTROL METHOD, AND NON-TRANSITORY COMPUTER READABLE MEDIUM STORING FILTER DRIVER FOR CONTROLLING A POWER STATE OF A PERIPHERAL DEVICE

Renesas Electronics Corpo...

1. An information processing device comprising:
a first application program configured to transmit a control request for a peripheral device;
a second application program configured to run on an operating system on which the first application program runs and to transmit
a control request for the peripheral device;

a class driver configured to relay the control request from the first application program; and
a filter driver sitting below the class driver and configured to control the peripheral device in accordance with the control
request from the first application program through the class driver and to control the peripheral device in accordance with
the control request from the second application program without passing through the class driver, wherein

the filter driver comprises:
a power state management unit configured to change a power state of the peripheral device in accordance with a change request
of the power state of the peripheral device from the class driver and to recognize the changed power state of the peripheral
device; and

a control unit configured to control the peripheral device in accordance with the control request from the first application
program and second application program, and

if the power state of the peripheral device recognized by the power state management unit is a low-power state, the control
unit suspends controlling the peripheral device in accordance with the control request from the second application program
until the power state of the peripheral device returns to a normal state.

US Pat. No. 9,245,614

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a first well region of a first conductivity type including a first part to a third part;
a first power feeding region of the first conductivity type having a higher impurity concentration than an impurity concentration
of the first well region; and

a second well region of a second conductivity type including a fourth part,
wherein the first part and the second part are arranged to be adjacent to both sides of the fourth part in a first direction,
the third part has a shape extending in the first direction, and is arranged to be joined to the first part and the second
part and be adjacent to the fourth part in a second direction intersecting with the first direction,

the first power feeding region is formed in a substantially rectangular shape in the third part, and supplies a predetermined
voltage to the first part and the second part via the first well region, and

a size of the first power feeding region in the first direction is larger than a size of the first power feeding region in
the second direction.

US Pat. No. 9,054,093

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a wiring board having a plurality of electrodes, and
a semiconductor chip which is mounted over the wiring board and coupled to the electrodes via solder,
wherein the semiconductor chip includes a rectangular substrate, an insulating film which is formed over the substrate, a
plurality of openings which are formed in the insulating film and arranged along a first side of the substrate, a plurality
of electrode pads which are situated in the respective openings, and conductor posts which are formed over the respective
electrode pads and coupled to the solder and at least part of the periphery of each of which is situated over the insulating
film;

wherein when a region where each of the conductor posts is overlapped with the insulating film is designated as an overlapped
region, a first width which is the width of the overlapped region situated on a first straight line extending from the center
of a first conductor post closest to one end of the first side of the substrate as a starting point to the center of the substrate
as an end point is smaller than a second width which is the width of the overlapped region on an extension line extending
in a direction passing through the center of the first conductor post of the first straight line toward the external side
of the substrate, and

wherein a second straight line passing through the center of the first conductor post and the center of a first opening overlapped
with the first conductor post and the first side intersect with each other at an angle other than 90°.

US Pat. No. 9,609,750

PACKAGE SUBSTRATE AND ELECTRONIC DEVICE

RENESAS ELECTRONICS CORPO...

1. A package substrate, comprising:
a first array of bumps that is an outermost array arranged along a first side of the package substrate, adjacent bumps of
the first array of bumps being shifted in relation to respective adjacent bumps in a first axial direction that is a normal
direction of the first side and in a second axial direction that intersects perpendicularly with the first axial direction
in a plan view; and

a second array of bumps arranged in the inside of the first array of bumps, a plurality of bumps of the second array of bumps
being shifted in relation to all respective adjacent bumps to the plurality of bumps in the first axial direction and in the
second axial direction in a plan view.

US Pat. No. 9,293,496

LIGHT RECEIVING ELEMENTS FOR PHOTOELECTRIC CONVERSION AND CAPACITOR ELEMENTS FOR CHARGE STORING IN JOINED SUBSTRATES

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a first substrate forming at least a part of each of a plurality of pixels including a plurality of light receiving elements
in each of which photoelectric conversion is performed; and

a second substrate having capacitor elements which store therein charges supplied from the light receiving elements,
wherein the first substrate and the second substrate are joined together at a junction surface therebetween so as to be integrated
with each other,

wherein the light receiving elements and the capacitor elements are placed so as to be opposed to each other in a direction
perpendicular to the junction surface,

wherein the capacitor elements are at positions away from a surface of the second substrate corresponding to the junction
surface,

wherein the first substrate includes:
a light-receiving-element-side light blocking film placed on a side of each of the light receiving elements where light is
supplied to the light receiving element so as to block the light supplied to the light receiving element; and

a plurality of first coupling portions formed at a surface of the first substrate corresponding to the junction surface so
as to electrically couple the first substrate and the second substrate to each other,

wherein the second substrate includes:
a plurality of second coupling portions formed at the surface of the second substrate corresponding to the junction surface
so as to be electrically coupled to the first coupling portions, and

wherein a first gap portion interposed between the first coupling portions and a second gap portion interposed between the
second coupling portions, each of which is present outside regions overlapping the light receiving elements in planar view,
are placed so as to overlap the light-receiving-element-side light blocking film in the direction perpendicular to the junction
surface at which the first substrate and the second substrate are joined together.

US Pat. No. 9,397,072

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a base material having a surface, a wiring formed on the surface, and a solder resist film covering the wiring;
a first chip group including a first semiconductor chip and a second semiconductor chip, and mounted on a surface of the solder
resist film;

a second chip group including a first semiconductor chip, a second semiconductor chip and a third semiconductor chip, and
mounted on the first chip group;

a first wire group including a plurality of first wires and a plurality of second wires, and connected with the first chip
group;

a second wire group including a plurality of first wires, a plurality of second wires and a plurality of third wires, and
connected with the second chip group; and

a sealing body sealing the first chip group, the second chip group, the first wire group and the second wire group,
wherein the sealing body has a first side surface and a second side surface opposite to the first side surface,
wherein the first semiconductor chip of the first chip group has a side surface along which a plurality of pads connected
with the plurality of first wires of the first wire group are arranged, and facing the first side surface of the sealing body,

wherein the second semiconductor chip of the first chip group has a side surface along which a plurality of pads connected
with the plurality of second wires of the first wire group are arranged, and facing the first side surface of the sealing
body,

wherein the first semiconductor chip of the second chip group has a side surface along which a plurality of pads connected
with the plurality of first wires of the second wire group are arranged, and facing the second side surface of the sealing
body,

wherein the second semiconductor chip of the second chip group has a side surface along which a plurality of pads connected
with the plurality of second wires of the second wire group are arranged, and facing the second side surface of the sealing
body,

wherein the third semiconductor chip of the second chip group has a side surface along which a plurality of pads connected
with the plurality of third wires of the second wire group are arranged, and facing the second side surface of the sealing
body,

wherein the first semiconductor chip of the first chip group is a lowermost chip,
wherein the first semiconductor chip of the second chip group is a lowermost chip of the second chip group,
wherein the third semiconductor chip of the second chip group is an uppermost chip,
wherein each of the third semiconductor chip of the second chip group, the first semiconductor chip of the second chip group
and the first semiconductor chip of the first chip group has greater thickness than each of the second semiconductor chip
of the first chip group and the second semiconductor chip of the second chip group, and

wherein the third semiconductor chip of the second chip group, the first semiconductor chip of the second chip group and the
first semiconductor chip of the first chip group have the same thickness.

US Pat. No. 9,329,927

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a first processor;
a second processor;
a first delay circuit that brings in a signal that is input into the first processor, delays the brought-in signal by the
time period of a predefined number of cycles, and inputs the delayed signal info the second processor;

a first compression circuit that brings in a signal of n-bit width output from the first processor and compresses the signal
of n-bit width into a signal of m-bit width (wherein m
a second compression circuit that brings in a signal of n-bit width output from the second processor and compresses the signal
of n-bit width into a signal of m-bit width;

a second delay circuit that brings in the signal of m-bit width output from the first compressor, delays the signal of m-bit
width by the time period of the predefined number of cycles used by the first delay circuit, and outputs the delayed signal;
and

a coincidence comparison circuit that brings in the signal of m-bit width output from the second delay circuit and the signal
of m-bit width output from the second compression circuit, and compares bit-wise the corresponding bits of the two brought-in
signals with each other to check whether the corresponding bits of the two brought-in signals coincide with each other or
not.

US Pat. No. 9,367,494

DATA PROCESSOR AND CONTROL SYSTEM

Renesas Electronics Corpo...

1. A data processor comprising:
a central processing unit which executes an instruction;
a first circuit module controlled by the central processing unit;
a second circuit module controlled by the central processing unit;
a first controller configured to send a request for interruption to the central processing unit in response to a generated
event signal; and

a second controller,
wherein the second controller receives a first event signal output from the first circuit module, outputs a first start signal
to the first controller, and outputs a second start signal to the second circuit module.

US Pat. No. 9,281,289

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a wiring substrate having a chip-mounting surface, a plurality of terminals formed on the chip-mounting surface, and a mounting
surface opposite to the chip-mounting surface;

a first semiconductor chip having a first main surface, a plurality of first electrodes formed over the first main surface
and a first rear surface opposite to the first main surface, and mounted over the chip-mounting surface such that the first
rear surface faces the chip-mounting surface of the wiring substrate; and

a plurality of wires each having a ball part and a stitch part, and coupled to the plurality of terminals respectively,
wherein:
the plurality of wires have a plurality of first wires and a second wire;
in plan view, the plurality of terminals are arranged along a side of the first main surface of the first semiconductor chip
in series;

the plurality of terminals have a plurality of first terminals to which the plurality of first wires are respectively coupled
via the stitch part, and a second terminal to which the ball part of the second wire is coupled via the ball part;

in plan view, the second terminal is located at a position different from over an arrangement of the plurality of first terminals;
and

in plan view, a width of the second terminal is larger than a width of each of the plurality of first terminals.

US Pat. No. 9,585,192

ELECTRONIC DEVICE

RENESAS ELECTRONICS CORPO...

1. An electronic device serving as an element of a wireless communication system, the electronic device comprising:
a module unit,
a battery that supplies electric power to the module unit, and
a coupling part that electrically couples the module unit and the battery,
wherein the module unit includes:
a sensor that detects a physical quantity;
a wireless communication unit configured to transmit data based on an output signal from the sensor; and
a plurality of wiring boards, the sensor and the wireless communication unit being respectively disposed on surfaces of the
plurality of wiring boards that face away from each other.

US Pat. No. 9,305,253

INTERFACE IC AND MEMORY CARD INCLUDING THE SAME

Renesas Electronics Corpo...

1. A memory card comprising:
a memory that stores data;
a driver that transmits the data received from the memory;
at least one transmitter that transmits the data received from the driver to a receiver provided in an external main unit,
wherein the driver and the at least one transmitter are provided in a single IC (integrated circuit) chip and are not overlapped
with each other in a planar view; and

a clock receiver that receives a clock signal from the external main unit,
wherein a size of the at least one transmitter differs from a size of the clock receiver.

US Pat. No. 9,298,080

MASK FOR PERFORMING PATTERN EXPOSURE USING REFLECTED LIGHT

RENESAS ELECTRONICS CORPO...

1. A mask for performing pattern exposure using reflected light which is exposure light irradiating a top surface of the mask
and reflected by the top surface, the mask comprising:
the top surface;
a back surface opposite to the top surface;
a side surface disposed between the top surface and the back surface;
an exposure pattern formed over the top surface; and
a side surface portion formed over the side surface,
wherein the exposure pattern includes a reflection film formed over the top surface to reflect the exposure light, and an
absorber pattern formed over the reflection film to absorb the exposure light,

wherein a water repellency of the side surface portion is higher than the water repellency of the top surface, and
wherein the exposure light is extreme ultraviolet light.

US Pat. No. 9,293,383

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing semiconductor devices, comprising the steps of:
(a) providing a base material having a first surface, a plurality of device regions formed in the first surface, a plurality
of semiconductor chips mounted in the plurality of device regions, respectively, a frame region provided in the first surface
and outside the plurality of device regions, a marking region provided in part of the frame region, and first identification
information affixed to the marking region,

wherein the first surface has a first side and a second side opposed to the first side;
wherein the frame region has a first region located between the device regions and the first side and a second region other
than the first region; and

wherein the marking region is provided in the second region;
(b) after the step (a), sealing the plurality of semiconductor chips with resin and forming a sealing body by clamping the
base material using a first metal mold and a second metal mold such that the plurality of semiconductor chips are located
inside a cavity provided in the first metal mold and supplying resin into the cavity from the side of the first side of the
base material;

(c) after the step (b), reading the first identification information; and
(d) after the step (b), newly affixing a second identification information to the sealing body,
wherein, before the step (b), a dam part of the frame region is formed between the marking region and the plurality of device
regions.

US Pat. No. 9,215,108

DECISION FEEDBACK EQUALIZER

Renesas Electronics Corpo...

1. A decision feedback equalizer, comprising:
a first weighting addition circuit that adds an input signal and weighted versions of second to nth feedback signals together,
n being an integer not less than 2;

a first decision circuit that decides whether or not a result of addition by the first weighting addition circuit is not less
than a first defined threshold value and that outputs the result of the decision as a first feedback signal of the n feedback
signals, the first decision circuit operating in synchronism with a clock signal;

a second decision circuit that decides whether or not the result of the addition by the first weighting addition circuit is
not less than a second defined threshold value and that outputs the result of the decision, the second decision circuit operating
in synchronism with the clock signal; and

a plurality of latch circuits that sequentially hold the result of decision of the second decision circuit in synchronism
with the clock signal and that output the contents held by component registers thereof as the second to nth feedback signals,
respectively,

wherein the second decision circuit is configured so that the second defined threshold value is controllable by a weighted
version of the first feedback signal.

US Pat. No. 9,166,009

SEMICONDUCTOR APPARATUS AND METHOD FOR MAKING SEMICONDUCTOR APPARATUS

RENESAS ELECTRONICS CORPO...

18. A semiconductor apparatus comprising:
a substrate;
an epitaxial layer that is formed on the substrate; and
a gate electrode, a source electrode, and a drain electrode that are formed on the epitaxial layer,
wherein the source electrode and the drain electrode each include at least two first divided electrodes that are formed to
extend in parallel to each other in a first direction, the at least two first divided electrodes of the source electrode being
disposed on one side of the gate electrode and the at least two first divided electrodes of the drain electrode being disposed
on another side of the gate electrode that is opposite the one side, an inter-electrode distance between the first divided
electrodes is greater than or equal to a radius of an abnormal growth portion formed on a surface of the epitaxial layer,
and widths of the first divided electrodes are less than or equal to the radius of the abnormal growth portion, and

the at least two first divided electrodes of the source electrode are disposed in relation to each other without the gate
electrode or the drain electrode being disposed between the at least two first divided electrodes of the source electrode,
and

the at least two first divided electrodes of the drain electrode are disposed in relation to each other without the gate electrode
or the source electrode being disposed between the at least two first divided electrodes of the drain electrode.

US Pat. No. 9,324,763

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a substrate having a first main surface and a second main surface on the side opposite to the first main surface
and forming a plurality of semiconductor elements over the first main surface of the substrate to form a semiconductor wafer;

(b) providing an annular ring to which an adhesive tape has been attached;
(c) attaching the semiconductor wafer onto the adhesive tape so that the second main surface of the semiconductor wafer faces
the adhesion surface of the adhesive tape located in the ring;

(d) dicing the semiconductor wafer into a plurality of semiconductor chips to form a sawn wafer in which the plurality of
semiconductor chips are retained by the ring while being attached to the adhesive tape;

(e) after the step (d), housing the sawn wafer in a shipping case having a first case portion that covers a first surface
of the sawn wafer to which the semiconductor chips have been attached and a second case portion that covers a second surface
of the sawn wafer on the side opposite to the first surface and thereby fixing the ring;

(f) after the step (e), housing the shipping case in a shipping bag; and
(g) after the step (f), sucking a gas from the shipping bag to reduce a pressure in the shipping case,
wherein the first case portion has, in the step (e), a first recess portion that covers the semiconductor chips and a first
ventilation route communicated with the first recess portion and coupled to an external space of the shipping case;

wherein the second case portion has, in the step (e), a second recess portion that covers the second surface of the sawn wafer;
and

wherein in the step (g), a gas is discharged from the shipping case via the first ventilation route.

US Pat. No. 9,312,267

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a semiconductor substrate;
a first region arranged in a surface of said semiconductor substrate and including a plurality of first element formation
regions each defined by a first element isolation region;

a second region arranged in said surface of said semiconductor substrate as being adjacent to said first region and including
a dummy element formation region defined by a second element isolation region;

a plurality of memory cell transistors formed in a plurality of said first element formation regions and each including a
floating gate electrode and a control gate electrode;

a dummy floating gate electrode formed in said second region;
a word line formed on said dummy floating gate electrode so as to cross said dummy floating gate electrode and electrically
connected to the control gate electrode of at least one memory cell transistor of said plurality of memory cell transistors;

an interlayer insulating film formed to cover said word line; and
a conductor portion formed in a portion of said interlayer insulating film located in said second region and electrically
connected to said word line,

said dummy floating gate electrode being arranged to partially be superimposed on said dummy element formation region in a
two-dimensional view.

US Pat. No. 9,275,945

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) providing, respectively, a lead frame having a die pad, a plurality of suspension leads for supporting the die pad, and
a plurality of leads arranged around the die pad in plan view,

a first semiconductor chip having a first main surface, a plurality of first pads formed over the first main surface and along
each side of the first main surface, and a first back surface opposite to the first main surface, and

a second semiconductor chip having a second main surface, a plurality of second pads formed over the second main surface and
along each side of the second main surface, and a second back surface opposite to the second main surface;

(b) after the step (a), mounting the first semiconductor chip over a first chip mounting region in a chip mounting surface
of the die pad, and

mounting the second semiconductor chip over a second chip mounting region located next to the first chip mounting region in
the chip mounting surface of the die pad;

(c) after the step (b), electrically coupling, respectively, a plurality of lead connection pads of the first pads of the
first semiconductor chip with a first lead group of the leads via a plurality of first wires,

a plurality of lead connection pads of the second pads of the second semiconductor chip with a second lead group of the leads
via a plurality of second wires, and

a plurality of chip-to-chip connection pads of the first pads of the first semiconductor chip with a plurality of chip-to-chip
connection pads of the second pads of the second semiconductor chip via a plurality of third wires; and

(d) sealing the die pad, the first semiconductor chip, the second semiconductor chip, the first wires, the second wires and
the third wires with resin such that a surface opposite to the chip mounting surface of the die pad and a part of each of
the leads are exposed,

wherein, in the step (b), the first and second semiconductor chips are mounted such that a first side of the first main surface
and a first side of the second main surface are next to each other;

wherein, in the step (c), after parts of the third wires are electrically coupled to the second semiconductor chip, the other
parts of the third wires are electrically coupled to the first semiconductor chip, respectively;

wherein a distance between the first side of the first semiconductor chip and the chip-to-chip connection pads of the first
semiconductor chip formed along the first side of the first semiconductor chip is greater than a distance between the first
side of the semiconductor chip and the chip-to-chip connection pads of the second semiconductor chip formed along the first
side of the second semiconductor chip, and

wherein, in a thickness direction of the lead frame, the first and second main surfaces of the first and second semiconductor
chips are located between each of the leads and the die pad.

US Pat. No. 9,053,764

MEMORY INTERFACE CIRCUIT AND SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a data terminal to be coupled to a memory device;
a data output buffer coupled to the data terminal and configured to output first write data to the memory device;
a data input buffer coupled to the data terminal and the data output buffer; and
a first latch coupled to the data input buffer,
wherein when data is written to the memory device, both the data output buffer and the data input buffer are enabled such
that the first latch latches second write data looped-back through the data input buffer.

US Pat. No. 9,153,683

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a substrate having a base layer, a buffer layer formed over the base layer, and a compound semiconductor layer formed over
the buffer layer,

a first transistor with a channel being formed in the compound semiconductor layer and having a drain, a gate electrode, and
a source, the drain, the gate electrode, and the source being arranged with respect to each other along a first direction,
and

a buried electrode extending through a thickness of the compound semiconductor layer such that an end portion of the buried
electrode protrudes into the buffer layer, at least a portion of the buried electrode being arranged on a side of the gate
electrode in the first direction opposite to the source, and

a connection member electrically connecting the buried electrode and the source,
wherein a Schottky junction is formed at a lateral sidewall of the buried electrode contacting the compound semiconductor
layer.

US Pat. No. 9,299,797

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor memory device, comprising:
a pair of bit lines connected to a plurality of memory cells;
a first transistor connected between the pair of bit lines;
a second transistor between at least one of the pair of bit lines and a first power supply voltage line; and
a diffusion layer region shared between the first transistor and the second transistor, and connected to the one of the pair
of bit lines,

wherein a gate of the first transistor and a gate of the second transistor are connected to each other, and
wherein the gate of the first transistor is provided such that both a direction of a gate width of the first transistor and
a direction of a gate width of second transistor are on one identical extension line.

US Pat. No. 9,275,863

METHOD OF FABRICATING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device including a MISFET, comprising steps of:
(a) forming a first trench in a semiconductor substrate, the first trench including a first portion and a second portion arranged
near a top surface of the semiconductor substrate rather than the first portion such that the second portion has a sloping
shape rather than first portion;

(b) forming a gate insulating film of the MISFET over the semiconductor substrate including the first trench;
(c) forming a gate electrode of the MISFET over the gate insulating film in order to be embedded in the first trench;
(d) after the step (c), recessing the gate electrode such that an upper surface of the gate electrode is arranged at a position
lower than the second portion;

(e) after the step (d), recessing the gate insulating film such that an upper surface of the gate insulating film is arranged
at a position lower than the second portion; and

(f) after the step (e), forming a first insulating film over the gate electrode, the gate insulating film, the second portion
and the top surface of the semiconductor substrate.

US Pat. No. 9,190,977

SEMICONDUCTOR DEVICE AND ADJUSTMENT METHOD OF FILTER CIRCUIT

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a filter circuit operable to pass a desired signal component of a high-frequency signal inputted and operable to attenuate
a harmonic component of an integral multiple of the desired signal,

wherein the filter circuit comprises:
a first inductor and a second inductor coupled in series to a signal line transmitting the high-frequency signal;
a first variable capacitor coupled between a power supply line and a node of the first inductor and the second inductor; and
a second variable capacitor coupled between the signal line and the power supply line,
wherein the filter circuit further comprises:
a first input terminal and a second input terminal operable to receive the high-frequency signal as a differential signal,
wherein the first inductor and the second inductor are formed by a first differential inductor and a second differential inductor
coupled in series between the first input terminal and the second input terminal,

wherein the first variable capacitor is coupled between the power supply line and a node of the first differential inductor
and the second differential inductor, and

wherein the second variable capacitor is coupled between the first input terminal and the power supply line and between the
second input terminal and the power supply line.

US Pat. No. 9,287,142

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE USING MARKINGS ON BOTH LEAD FRAME AND SEALING BODY

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a base material including a device area having a chip mounting portion, and an outer frame portion located around
the device area;

(b) after the step (a), putting a first identification number to the outer frame portion of the base material;
(c) after the step (b), mounting a semiconductor chip on the chip mounting portion of the base material;
(d) after the step (c), sealing the semiconductor chip with resin such that the outer frame portion is exposed from the resin,
thereby forming a sealing body; and

(e) after the step (d), reading the first identification number, and putting a first piece of intra-server information as
a second identification number to the sealing body, the first piece of intra-server information of a plural pieces of intra-server
information stored in a server corresponding to the read first identification number;

wherein the step (c) is performed by the following steps (c1)-(c4):
(c1) reading the first identification number of the base material, conveyed to a first apparatus, with a first recognition
tool of the first apparatus,

(c2) after the step (c1), retrieving a first piece of intra-server information of the plural pieces of intra-server information
stored in the server, corresponding to the read first identification number,

(c3) after the step (c2), mounting the semiconductor chip on the chip mounting portion of the base material, and
(c4) after the step (c3), storing the first piece of intra-server information corrected by correlating the first piece of
intra-server information with manufacturing condition of the step (c);

wherein the step (d) is performed by the following steps (d1)-(d4):
(d1) reading the first identification number of the base material, conveyed to a second apparatus, with a second recognition
tool of the second apparatus,

(d2) after the step (d1), retrieving the first piece of intra-server information of the plural pieces of intra-server information
stored in the server, corresponding to the read first identification number and corrected before this step (d2),

(d3) after the step (d2), sealing the semiconductor chip with the resin, and
(d4) after the step (d3), storing the first piece of intra-server information corrected by correlating the first piece of
intra-server information with manufacturing condition of the step (d); and

wherein the step (e) is performed by following steps (e1)-(e2),
(e1) reading the first identification number of the base material, conveyed to a third apparatus, with a third recognition
tool of the third apparatus, and

(e2) after the step (e1), putting the first piece of intra-server information, of the plural pieces of intra-server information
stored in the server, corresponding to the read first identification number and corrected before this step (e2), to the sealing
body as the second identification number.

US Pat. No. 9,281,291

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) providing a glass substrate having an electrode;
(b) providing a semiconductor chip;
the semiconductor chip includes:
a MISFET formed over the semiconductor substrate, the MISFET being formed in the integrated circuit formation region;
a first wiring layer formed over the MISFET, the first wiring layer formed in the integrated circuit formation region;
a plurality of first patterns formed over the semiconductor substrate and in the same layer as the first wiring layer, the
plurality of first patterns being formed in the alignment mark formation region;

a first interlayer insulating film formed over the semiconductor substrate to cover the first wiring layer and the plurality
of first patterns;

a second wiring layer formed over the first interlayer insulating film, the second wiring layer being formed in the integrated
circuit formation region;

a plurality of second patterns formed over the first interlayer insulating film and in the same layer as the second wiring
layer, the plurality of second patterns being formed in the alignment mark formation region;

a second interlayer insulating film formed over the semiconductor substrate to cover the second wiring layer and the plurality
of second patterns;

a third wiring layer formed over the second interlayer insulating film, the third wiring layer being formed in the integrated
circuit formation region;

an alignment mark formed over the second interlayer insulating film and in the same layer as the third wiring layer, the alignment
mark being formed in the alignment mark formation region;

a further insulating film formed over the semiconductor substrate to cover the third wiring and the alignment mark, the insulating
film having an opening at an upper side of the third wiring layer; and

a bump electrode formed over the insulating film such that the bump electrode is electrically connected to the third wiring
layer via the opening,

wherein the first wiring, the second wiring and the third wiring are electrically connected to the MISFET, and
wherein the plurality of first patterns and the plurality of second patterns are not electrically connected to the MISFET;
and

(c) mounting the semiconductor chip over the glass substrate such that the bump electrode is electrically connected to the
electrode of the glass substrate,

wherein the connection between the bump electrode and the electrode of the glass substrate in the step (c) is performed by
recognizing the alignment mark with a camera.

US Pat. No. 9,373,630

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device,
comprising the steps of:
(a) providing a semiconductor substrate having a first MISFET formed in a first region, and a nonvolatile memory formed in
a second region;

(b) forming a first insulating film over the first MISFET and the nonvolatile memory cell;
(c) forming a second insulating film over the first insulating film;
(d) removing the second insulating film in the second region therefrom; and
(e) after the step (d), performing heat treatment to apply a stress to the first MISFET,
wherein the nonvolatile memory cell has a first gate electrode formed over the semiconductor substrate, and a first gate insulating
film formed between the first gate electrode and the semiconductor substrate and having a charge storage portion in the inside
thereof.

US Pat. No. 9,280,671

SEMICONDUCTOR DEVICE AND ENCRYPTION KEY WRITING METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a central processing unit (CPU) having a first operation mode and a second operation mode;
an electrically rewritable first nonvolatile memory provided with a first region and a second region, the first region being
forbidden to access from the CPU in the second operation mode;

an electrically non-rewritable second nonvolatile memory provided with a third region and a fourth region, the third region
being operable to store an encryption code as at least one of an encrypted instruction and encrypted data; and

a decrypter,
wherein the first nonvolatile memory is provided with a plurality of distributed address areas in the first region, for holding
a plurality of split keys composing an encryption key for decrypting the encryption code,

wherein the decrypter holds the encryption key, and in the second operation mode, the decrypter is operable to decrypt the
encryption code read from the third region of the second nonvolatile memory with the use of the encryption key, and operable
to supply the decrypted encryption code to the CPU, and

wherein the second nonvolatile memory holds an encryption key reading program in the fourth region, which is executed by the
CPU in the first operation mode to restore the encryption key and to supply it to the decrypter, by reading and reconfigurating
the split keys held in the first nonvolatile memory in a distributed manner.

US Pat. No. 9,261,529

ACCELERATION SENSOR

RENESAS ELECTRONICS CORPO...

1. An acceleration sensor comprising:
an outer frame body in which a fluid sealing chamber capable of sealing a fluid inside thereof is formed;
a heating element formed on a specific inner wall surface which is a specific inner wall surface of a plurality of inner wall
surfaces defining the fluid sealing chamber;

a first temperature sensing element for temperature measurement and a second temperature sensing element for temperature measurement,
which are formed on the specific inner surface, with the distance from the first temperature sensing element to the heating
element being shorter than the distance from the second temperature sensing element to the heating element; and

a difference operation circuit configured to calculate a difference between a measurement result by the first temperature
sensing element and a measurement result by the second temperature sensing element.

US Pat. No. 9,214,980

HIGH-FREQUENCY SIGNAL PROCESSOR AND WIRELESS COMMUNICATION SYSTEM

Renesas Electronics Corpo...

1. A high-frequency signal processor circuitry provided with a first operation mode and a second operation mode, the high-frequency
signal processor circuit comprising:
a test signal generating circuit that generates a test signal having a first frequency component and a second frequency component;
a first switch that transmits a signal received as a first signal at an antenna in the first operation mode and transmits
the test signal as the first signal in the second operation mode;

a first mixer circuit A that includes a differential circuit capable of correcting a differential balance within a specified
variable range and uses a first local signal A? to down-convert the first signal into a second signal A? having a frequency
band lower than the first signal;

a first mixer circuit B that includes a differential circuit capable of correcting a differential balance within a specified
variable range and uses a first local signal B? to down-convert the first signal into a second signal B?, the first local
signal B? having a phase 90° different from the first local signal A?;

a phase detection portion that, in the second operation mode, extracts a third signal A?? from the second signal A?, the third
signal A?? having a frequency component equivalent to a difference between the first frequency component and the second frequency
component, extracts a third signal B?? from the second signal B?, the third signal B?? having a frequency component equivalent
to the difference between the first frequency component and the second frequency component, and detects a phase for the third
signal A?? and a phase for the third signal B??; and

a control portion that changes the differential balance for the first mixer circuit A according to a result from the phase
detection portion detecting a phase for the third signal A?? and changes the differential balance for the first mixer circuit
B according to a result from the phase detection portion detecting a phase for the third signal B??,

wherein the first mixer circuit A operates in the first operation mode while the differential balance for the first mixer
circuit A is set to a first correction value CVA within a variable range,

wherein the first mixer circuit B operates in the first operation mode while the differential balance for the first mixer
circuit B is set to a first correction value CVB within a variable range,

wherein the control portion performs a first process, a second process, and a third process in the second operation mode,
wherein the first process varies the differential balance for the first mixer circuit A and concurrently searches for a first
transition point TPA that allows a phase for the third signal A?? to transition by approximately 180° before and after varying
the differential balance within a minimum fluctuation range,

wherein the second process varies the differential balance for the first mixer circuit B and concurrently searches for a first
transition point TPB that allows a phase for the third signal B?? to transition by approximately 180° before and after varying
the differential balance within a minimum fluctuation range, and

wherein the third process supplies the first mixer circuit A with the differential balance corresponding to the first transition
point TPA as the first correction value CVA and supplies the first mixer circuit B with the differential balance corresponding
to the first transition point TPB as the first correction value CVB.

US Pat. No. 9,196,748

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a semiconductor substrate,
a first gate electrode and a second gate electrode spaced along a first direction in a first main surface of the semiconductor
substrate,

a first gate insulation film formed between the first gate electrode and the semiconductor substrate,
a second gate insulation film formed between the second gate electrode and the semiconductor substrate,
a first cap insulation film formed over the first gate electrode,
a second cap insulation film formed over the second gate electrode,
a third gate electrode arranged opposite to the second gate electrode across the first gate electrode, and adjacent to the
first gate electrode,

a fourth gate electrode arranged opposite to the first gate electrode across the second gate electrode, and adjacent to the
second gate electrode,

a third gate insulation film formed between the third gate electrode and the semiconductor substrate, and between the first
gate electrode and the third gate electrode, and having a first charge accumulation part in the inside thereof, and

a fourth gate insulation film formed between the fourth gate electrode and the semiconductor substrate, and between the second
gate electrode and the fourth gate electrode, and having a second charge accumulation part in the inside thereof,

wherein the first gate electrode, the first gate insulation film, the first cap insulation film, the third gate electrode,
and the third gate insulation film form a first memory cell,

wherein the second gate electrode, the second gate insulation film, the second cap insulation film, the fourth gate electrode,
and the fourth gate insulation film form a second memory cell,

wherein in the first main surface, an end at a top surface of the first cap insulation film on the second gate electrode side
is situated closer to the third gate electrode side than a side surface of the first gate electrode on the second gate electrode
side,

wherein in the first main surface, an end at a top surface of the first cap insulation film on the third gate electrode side
is situated closer to the second gate electrode side than a side surface of the first gate electrode on the third gate electrode
side,

wherein the third gate electrode is formed at a side surface of the first cap insulation film on the third gate electrode
side, and at the side surface of the first gate electrode on the third gate electrode side via the third gate insulation film,

wherein the third gate electrode is formed of a first silicon film,
wherein a first metal silicide layer is formed at a top surface of the third gate electrode, and
wherein a portion of the first metal silicide layer overlaps the third gate insulating film disposed between the first gate
electrode and the third gate electrode in a direction perpendicular to the surface of the surface semiconductor substrate.

US Pat. No. 9,653,587

IE TYPE TRENCH GATE IGBT

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
(a) a semiconductor substrate having a first and a second main surfaces;
(b) a drift area disposed in the semiconductor substrate and having a first conductive type;
(c) a cell formation area disposed on the first main surface and having a plurality of trenches arranged in parallel;
(d) a metal gate electrode disposed on the first main surface;
(e) a metal gate wire surrounding the cell formation area and connected to the metal gate electrode;
(f) a metal emitter electrode disposed on the first main surface;
(g) a metal collector electrode disposed on the second main surface;
(h) a collector area disposed between the metal collector electrode and the drift area and having a second conductive type;
(i) a linear active cell having a pair of first and second linear trench gate electrodes and a linear hole collector cell
area having a pair of third and fourth linear trench gate electrodes which are disposed alternately on the first main surface;

(j) a body area disposed in a surface area on the side of the first main surface of the drift area and having the second conductive
type;

(k) a floating area disposed in the surface area on the side of the first main surface between the linear active cell area
and the linear hole collector cell area and having the same conductive type as that of the body area; and

wherein an emitter area of the first conductive type is disposed in the surface area on the side of the first main surface
of the body area between the first and the second linear trench gate electrodes, wherein the first and the second linear trench
gate electrodes are connected to the metal gate electrode and disposed in first and second trenches in the first main surface,

wherein the third and the fourth linear trench gate electrodes are connected to the metal emitter electrode and disposed in
third and fourth trenches in the first main surface, and

wherein a distance from the emitter area disposed on the outer side of the longitudinal direction in the linear active cell
area to an edge of the cell formation area is longer than a distance from an edge of the linear hole collector cell area in
the longitudinal direction to the edge of the cell formation area in a plan view.

US Pat. No. 9,576,993

METHOD FOR MANUFACTURING IMAGE CAPTURING DEVICE AND IMAGE CAPTURING DEVICE

Renesas Electronics Corpo...

1. A method for manufacturing an image capturing device having a photoelectric conversion unit, a transfer transistor, and
a first peripheral transistor, said transfer transistor transferring a charge generated in said photoelectric conversion unit,
said first peripheral transistor processing said charge as a signal, the method comprising the steps of:
defining an element formation region by forming an element isolation insulating film in a semiconductor substrate, said element
formation region including a pixel region and a first peripheral region, said photoelectric conversion unit and said transfer
transistor being formed in said pixel region, said first peripheral transistor being formed in said first peripheral region;

forming gate electrodes, the step of forming said gate electrodes including the step of forming a transfer gate electrode
of said transfer transistor in said pixel region and forming a first peripheral gate electrode of said first peripheral transistor
in said first peripheral region;

forming the photoelectric conversion unit at a portion of said pixel region on one side relative to said transfer gate electrode;
forming a first insulating film to serve as an offset spacer film so as to cover said element formation region and said gate
electrodes;

forming said offset spacer film on each of side wall surfaces of said gate electrodes by providing anisotropic etching process
to said first insulating film while a portion of said first insulating film covering said photoelectric conversion unit remains;

removing the portion of said first insulating film covering said photoelectric conversion unit by providing wet etching process;
and

forming a sidewall insulating film on each of the side wall surfaces of said gate electrodes after the portion of said first
insulating film is removed.

US Pat. No. 9,344,149

POWER LINE CARRIER TRANSMISSION APPARATUS AND COMMUNICATION SYSTEM

Renesas Electronics Corpo...

1. A power line carrier transmission apparatus for transmitting a transmission symbol via a power line, the power line carrier
transmission apparatus comprising:
an interleave unit interleaving the transmission symbol;
a modulation unit for modulating the transmission symbol interleaved by the interleave unit; and
a transmission unit repeatedly transmitting the transmission symbol modulated by the modulation unit M times (where M is an
integer greater than 1),

wherein M symbols (where M denotes the number of the symbols), which are generated by repeatedly transmitting the transmission
symbol M times by the transmission unit, are transmitted without guard intervals being added therebetween.

US Pat. No. 9,276,586

SEMICONDUCTOR DEVICE AND CLOCK CORRECTION METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a frequency error calculator circuit that calculates a frequency error of a first clock based on a first clock and a second
clock having a higher frequency than the first clock;

a correction clock generator circuit that outputs a correction clock having a corrected frequency determined by the first
clock and the frequency error calculated by the frequency error calculator circuit; and

a control circuit that generates an ON-OFF control signal based on the frequency error calculated by the frequency error calculator
circuit,

wherein the frequency error calculator circuit calculates the frequency error at a calculation timing specified by the ON-OFF
control signal.

US Pat. No. 9,281,191

SEMICONDUCTOR DEVICE MANUFACTURING METHOD

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) holding a first mask by a mask holding unit, the first mask having a first base, a first reflective film formed on a first
front surface of the first base to reflect first exposure light, and a first absorber pattern formed on the first reflective
film to absorb the first exposure light;

(b) forming a first resist film on a first film to be etched, which is formed on a main surface of a first substrate;
(c) after the step (b), holding the first substrate by a substrate holding unit;
(d) irradiating the first front surface of the first mask being held by the mask holding unit with the first exposure light
and irradiating the first resist film of the first substrate being held by the substrate holding unit with first reflected
light, which is the first exposure light for irradiation reflected from the first front surface;

(e) after the step (d), forming a first resist pattern by developing the first resist film; and
(f) etching the first film to be etched, by using the first resist pattern as an etching mask,
wherein, in the step (d), the irradiation of the first reflected light is repeated while a focal position of the first reflected
light with which the first resist film is irradiated is changed along a film thickness direction of the first resist film,
and

in the step (d), the focal position of the first reflected light is changed in a range smaller than or equal to half of a
depth of focus,

the method further comprising the steps of:
(g) before the step (a), determining a line width of the first absorber pattern, a first value being determined as the line
width of the first absorber pattern so that a line width of the first resist pattern that is formed when the first mask does
not have a phase defect is included in a first range set in advance; and

(h) after the step (g) and before the step (a), manufacturing the first mask, the first mask having the first absorber pattern
with a corrected line width obtained by correcting a second value that is smaller than the first value, the line width of
the first absorber pattern being corrected to the second value by uniformly decreasing the line width of the first absorber
pattern from both sides,

wherein in the step (d), the first exposure light is irradiated with an exposure condition in which an exposure amount is
decreased from the exposure amount when the line width of the first absorber pattern is not corrected to the second value,
and

the first exposure light is extreme ultraviolet light.

US Pat. No. 9,231,598

MULTIPLEXED OSCILLATORS

Renesas Electronics Corpo...

7. An integrated circuit device comprising:
a total of two oscillators including a first oscillator that outputs a first clock signal and a second oscillator that outputs
a second clock signal;

a comparator circuit configured to compare a frequency of the first clock signal with a frequency of the second clock signal,
and configured to generate a selection signal indicating a selection of an output signal from among a plurality of signals
including the first clock signal and the second clock signal; and

a selector configured to output the output signal in response to the selection signal.

US Pat. No. 9,281,780

RESISTANCE CORRECTION CIRCUIT, RESISTANCE CORRECTION METHOD, AND SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
an oscillator circuit generating a clock signal; and
circuit blocks operating based on the clock signal,
wherein the oscillator circuit comprises a resistance correction circuit including:
a first resistor whose stress-resistance value relationship is a first relationship;
a second resistor whose stress-resistance value relationship is a second relationship;
a correction target resistor; and
a correction section that controls the resistance value of the correction target resistor,
wherein the correction section detects the difference between the resistance value of the first resistor and the resistance
value of the second resistor and corrects, in accordance with the result of detection, the resistance value of the correction
target resistor, and

wherein the clock signal has a frequency corresponding to the resistance value of the correction target resistor.

US Pat. No. 9,263,108

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising a data strobe receiving circuit including:
a termination circuit which couples input terminals receiving a data strobe signal and an inverted data strobe signal output
from a memory to a terminal potential from before the start timing of a preamble of the data strobe signal and the inverted
data strobe signal;

a first comparator circuit which, after the input terminals are coupled to the terminal potential, outputs the difference
between the data strobe signal and the inverted data strobe signal from before the start timing of the preamble;

a second comparator circuit which compares the level of either the data strobe signal or the inverted data strobe signal with
a reference voltage so as to output a signal representing the result of the comparison;

a gate circuit which masks the output signal of the first comparator circuit with a mask signal; and
a control circuit which controls the level change of the mask signal,
wherein the control circuit identifies the start timing of the preamble based on the output signal of the second comparator
circuit, the control circuit further setting the mask signal to a masking state before the start of the preamble and to an
unmasking state from the start timing of the preamble.

US Pat. No. 9,165,879

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a wiring board;
a first semiconductor chip that is mounted over a first surface of the wiring board so that an element formation surface faces
the first surface, and has a first circuit;

a second semiconductor chip that is disposed over the first semiconductor chip; and
a plurality of connection terminals that couple the first semiconductor chip with the wiring board,
wherein the first semiconductor chip has the element formation surface facing the first surface and has a plurality of first
through-silicon vias,

wherein the second semiconductor chip is electrically coupled to the first through-silicon vias of the first semiconductor
chip,

wherein each of the first through-silicon vias is arranged on any of grid points arranged in m rows and n columns (m>n),
wherein a through-silicon via area defined by coupling the outermost grid points arranged in m rows and n columns does not
overlap with the first circuit in plan view, and

wherein some of the connection terminals are located between the first circuit and the first through-silicon vias in plan
view.

US Pat. No. 9,406,352

SEMICONDUCTOR MEMORY WITH SENSE AMPLIFIER

RENESAS ELECTRONICS CORPO...

1. A semiconductor memory device, comprising:
a plurality of sense amplifiers, each of the sense amplifiers amplifying a difference in potential between a pair of bit lines;
a plurality of sense amplifier drivers supplying a power supply to the sense amplifiers, each of the sense amplifier drivers
having a first driver transistor and a second driver transistor, the first driver transistor having a different conductivity
type from the second driver transistor, the first driver transistor and the second driver transistor being alternately arranged
in a first direction, and

an element separation boundary arranged between the first driver transistor and the second driver transistor in a second direction
which is different from the first direction,

wherein a third direction orthogonal to a direction of gate length of the first driver transistor is parallel to the first
direction,

wherein a fourth direction orthogonal to a direction of gate length of the second driver transistor is parallel to the first
direction,

wherein the first direction is parallel to the extending direction of word lines.

US Pat. No. 9,293,456

SEMICONDUCTOR APPARATUS

Renesas Electronics Corpo...

1. A semiconductor apparatus comprising:
a first area, a first transistor being formed in two or more divided areas of the first area; and
a second area, a second transistor being formed in two or more divided areas of the second area, wherein
a total area of the second area is larger than a total area of the first area,
the divided areas of the first area and the second area are alternately arranged, and
the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area.

US Pat. No. 9,711,451

SEMICONDUCTOR DEVICE WITH COILS IN DIFFERENT WIRING LAYERS

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a substrate having a main surface;
a first insulating film formed on the main surface of the substrate;
a first coil and a first wiring formed on the first insulating film;
a second insulating film formed on the first coil and the first wiring;
a second wiring formed on the second insulating film;
a third insulating film formed on the second wiring; and
a second coil and a third wiring formed on the third insulating film,
wherein the first coil and a third wiring formed on the third insulating film,
wherein a shortest distance between the second coil and the third wiring is longer than a shortest distance between the first
coil and the second coil in a cross section view, and

wherein a wiring is not arranged along the shortest distance between the second coil and the third wiring in the cross section
view.

US Pat. No. 9,263,346

SEMICONDUCTOR DEVICE WITH SILICON LAYER CONTAINING CARBON

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a substrate having a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor
layer formed on the insulating layer and containing carbon;

a field effect transistor having a gate electrode formed on the semiconductor layer via a gate insulating film, source and
drain regions formed in the semiconductor layer on both sides of the gate electrode, and a channel region formed in the semiconductor
layer between the source and drain regions and containing carbon; and

a semiconductor region disposed in the semiconductor substrate below the gate electrode via the semiconductor layer and the
insulating layer, the semiconductor region being below the insulating layer,

wherein an impurity concentration profile of a p type or n type impurity extends from the semiconductor region through the
insulating layer and into the semiconductor layer, the impurity concentration profile having a maximum in the semiconductor
region, and the p type or n type impurity in the semiconductor layer is inactivated by the carbon in the semiconductor layer.

US Pat. No. 9,263,274

METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) providing a leadframe including:
a die pad,
a plurality of leads arranged around the die pad, and
a dam bar connecting the plurality of leads to one another,
wherein each of the plurality of leads includes:
an inner portion, and
an outer portion located closer than the inner portion to the dam bar,
wherein the inner portion includes:
a first upper surface,
a first lower surface opposite to the first upper surface, and
a first side surface between the first upper surface and the first lower surface, and
wherein the outer portion includes:
a second upper surface located at the same side as the first upper surface,
a second lower surface opposite to the second upper surface, and
a second side surface between the second upper surface and the second lower surface;
(b) after the step (a), mounting a semiconductor chip over a third upper surface of the die pad,
wherein the third upper surface of the die pad is a surface located at the same side as the first upper surface of the inner
portion;

(c) after the step (b), forming a resin-sealing-body sealing the semiconductor chip and the inner portion of each of the plurality
of leads, and forming a resin-protruding-portion sealing an area surrounded by the dam bar, the outer portion of each of the
plurality of leads and the resin-sealing-body,

wherein the resin-sealing-body includes:
a fourth upper surface located at the same side as the third upper surface of the die pad,
a fourth lower surface opposite to the fourth upper surface, and
a fourth side surface between the fourth upper surface and the fourth lower surface;
(d) after the step (c), irradiating the resin-protruding-portion and the outer portion of each of the plurality of leads with
a first laser light so as to remove the resin-protruding-portion, and thereby exposing the second side surface of the outer
portion;

(e) after the step (d), irradiating a first portion of the resin-sealing-body exposed by the step (d) with a second laser
light so as to remove the first portion of the resin-sealing-body,

wherein, in plan view, the first portion of the resin-sealing-body is located between the outer portion of each of the plurality
of leads, and also is faced to the dam bar; and

(f) after the step (e), forming a plating layer on the first lower surface, the second upper surface, the second lower surface
and the second side surface,

wherein the first lower surface is exposed from the fourth lower surface of the resin-sealing-body.

US Pat. No. 9,221,357

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Renesas Electronics Corpo...

6. A method for controlling a rotation speed of a motor provided in a vehicle with a semiconductor data processing device
comprising the steps of:
1) converting an analog resolver signal outputted from a resolver into a digital resolver value;
2) converting a current value of the motor to the digital current value;
3) receiving the digital resolver value by an interface of the semiconductor data processing device;
4) detecting whether the rotation speed of the motor is lower or higher than a predetermined value from a frequency of the
digital resolver value by a motor speed determining circuit in the semiconductor data processing device;

5) providing a resolver correction value of the digital resolver value;
6) calculating a position data indicating a rotation angle of the motor by adding or subtracting the resolver correction value
to or from the digital resolver value;

7) computing a current instruction value from information indicating acceleration or deceleration from an axel or a brake,
the position data, the current value of the motor and a current instruction value; and

8) generating a motor driving waveform based on the current instruction value and outputting the motor driving waveform to
the motor via a power module,

wherein the steps 5), 6) and 7) are executed by a central processing unit (CPU) in the semiconductor data processing device
when the rotation speed of the motor is lower than the predetermined value with the step 4), and

wherein the steps 5), 6) and 7) are executed by a resolver value correction circuit, a motor control computing circuit in
the semiconductor data processing device when the rotation speed of the motor is higher than the predetermined value with
the step 4).

US Pat. No. 9,263,532

SEMICONDUCTOR DEVICE, SEMICONDUCTOR SUBSTRATE, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR SUBSTRATE

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising:
preparing a semiconductor substrate, the semiconductor substrate comprising a first epitaxial layer and a second epitaxial
layer formed over the first epitaxial layer; and

forming an element using the second epitaxial layer,
wherein the first epitaxial layer includes:
an epitaxially grown layer; and
a defect layer that is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer,
wherein dislocations are formed in the epitaxially grown layer, and
wherein some of the dislocations penetrate through the defect layer and form loops in the second epitaxial layer without reaching
a surface layer of the second epitaxial layer.

US Pat. No. 9,327,457

ELECTRONIC DEVICE AND METHOD FOR MANUFACTURING ELECTRONIC DEVICE

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing an electronic device, said method comprising:
forming a resin film over a wafer, the wafer comprising a plurality of elements formed therein, and each of the elements comprising
a functional unit;

patterning the resin film to form a plurality of frame members, each of the frame members being provided on said each of the
elements to surround each functional unit;

providing an encapsulation by:
installing at least one of the elements over a base member;
pressing a molding surface of a first encapsulating metal mold and a molding surface of a second encapsulating metal mold
against an upper surface of at least one of said frame members and against a lower surface of the base member, respectively;

injecting an encapsulating resin into a space between the molding surfaces of the first and second encapsulating metal molds
but other than into a space surrounded by each frame member, thereby forming an encapsulating resin layer in a periphery of
each frame member; and

removing the first and second encapsulating metal molds after said injecting;
after said removing the first and second encapsulating metal molds, forming a protective film over the upper surface of the
frame member and over an upper surface of the encapsulating resin layer so that each functional unit is exposed to the protective
film;

dividing the wafer including the protective film into divided wafer portions each comprising one of said elements; and
removing the protective film from said each of the wafer portions divided as a result of said dividing of the wafer,
wherein the upper surface of the frame member is located higher than the upper surface of the encapsulating resin layer after
said removing the first and second encapsulating metal molds.

US Pat. No. 9,281,804

SEMICONDUCTOR DEVICE WITH AMPLIFICATION CIRCUIT AND OUTPUT BUFFER CIRCUIT COUPLED TO TERMINAL

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a first terminal;
an amplification circuit coupled to the first terminal; and
an output buffer whose output terminal is coupled to the first terminal,
wherein the output buffer has a first transistor of a first conduction type whose source and drain are coupled to a first
power supply line and a first node, respectively, and a second transistor of the first conduction type whose source and drain
are coupled to the first node and the output terminal, respectively, and

wherein the conduction states of the first and second transistors are controlled in response to a first control signal which
is applied commonly to the gate of each of the first and second transistors.

US Pat. No. 9,324,725

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A method for manufacturing a semiconductor device, comprising the steps of:
(a) providing a semiconductor substrate,
(b) forming a first insulation film over a first main surface of the semiconductor substrate,
(c) forming a first conductive film over the first insulation film,
(d) forming a second insulation film over the first conductive film,
(e) patterning the second insulation film and the first conductive film, forming a first gate electrode and a second gate
electrode spaced along a first direction in the first main surface of the semiconductor substrate with the first conductive
film, forming a first gate insulation film formed of the first insulation film between the first gate electrode and the semiconductor
substrate, forming a second gate insulation film formed of the first insulation film between the second gate electrode and
the semiconductor substrate, forming a first cap insulation film formed of the second insulation film over the first gate
electrode, and forming a second cap insulation film formed of the second insulation film over the second gate electrode,

(f) removing a portion of the first cap insulation film exposed at the side surface on the second gate electrode side, and
setting the side surface of the first cap insulation film on the second gate electrode side back from the side surface of
the first gate electrode on the second gate electrode side,

(g) forming a third insulation film having a first charge accumulation part in the inside thereof at the first main surface
of the semiconductor substrate, the surface of the first gate electrode, the surface of the second gate electrode, the surface
of the first cap insulation film, and the surface of the second cap insulation film,

(h) forming a second conductive film over the third insulation film,
(i) etching back the second conductive film, and thereby leaving the second conductive film, and forming a third gate electrode
at the side surface of the first gate electrode opposite to the second gate electrode side via the third insulation film,
and leaving the second conductive film, and forming a fourth gate electrode at the side surface of the second gate electrode
opposite to the first gate electrode side via the third insulation film, and

(j) removing a portion of the third insulation film not covered with any of the third gate electrode and the fourth gate electrode,
and forming a third gate insulation film formed of the third insulation between the third gate electrode and the semiconductor
substrate, and the third insulation film between the first gate electrode and the third gate electrode, and forming a fourth
gate insulation film formed of the third insulation film between the fourth gate electrode and the semiconductor substrate,
and the third insulation film between the second gate electrode and the fourth gate electrode.

US Pat. No. 9,275,956

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND PROCESS FOR MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a semiconductor substrate including a scribe region and a product region;
grooves formed in the scribe region;
a first insulating film embedded in the grooves, the grooves with the first insulating film being configured to be used as
an isolation region;

an active region formed in the product region;
a semiconductor element formed in the active region; and
dummy patterns formed in the scribe region,
wherein the dummy patterns include a first dummy pattern and a plurality of second dummy patterns configured for preventing
a dishing of the first insulating film,

wherein the second dummy patterns are surrounded and defined by the isolation region,
wherein a target pattern is arranged over the first dummy pattern, includes a first conductive film and is configured to be
used for optical pattern recognition,

wherein a plane area of the first dummy pattern is larger than a plane area of each of the second dummy patterns, and
wherein the first dummy pattern and the second dummy patterns are arranged in order from an edge of the semiconductor substrate
toward the product region.

US Pat. No. 9,245,800

METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising the steps of:
(a) forming a first insulating film over a first main surface of a semiconductor substrate;
(b) etching the first insulating film to form, respectively, a plurality of connection holes reaching the first main surface
of the semiconductor substrate in each of partitioned regions formed by partitioning a connection pad-forming region;

(c) embedding a first metal film inside the connection holes to form, respectively, a plurality of connection electrodes including
the first metal film in each of the partitioned regions;

(d) forming a second insulating film over the first insulating film and the connection electrodes;
(e) etching the second insulating film to form, respectively, trenches passing through the second insulating film from the
upper surface to the lower surface in each of the partitioned regions;

(f) embedding a second metal film inside the trench in each of the partitioned regions to form, respectively connection pads
including the second metal film in each of the partitioned regions;

(g) after subjecting the semiconductor substrate to a processing thinly from a second main surface opposite to the first main
surface, forming a through hole reaching the first main surface in the semiconductor substrate;

(h) forming a third insulating film on a side surface of the through hole; and
(i) forming, inside the through hole, a through electrode electrically coupled to the connection pad in each of partitioned
regions.

US Pat. No. 10,008,466

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A manufacturing method of a semiconductor device, comprising the steps of:(a) applying a resist film having an opening over a terminal pad formed over a semiconductor substrate;
(b) forming a pillar layer, a barrier layer, and a bump in the opening in this order from below;
(c) removing the resist film;
(d) etching outer peripheries of the bump; and
(e) reflowing the bump by a heat treatment such that a width of the bump is smaller than that of the barrier layer in a cross section of the semiconductor device.

US Pat. No. 9,111,938

COPPER INTERCONNECT WITH CVD LINER AND METALLIC CAP

International Business Ma...

1. A structure comprising:
a diffusion barrier positioned adjacent to a sidewall having a re-entrant feature and a bottom of an opening being etched
in a layer of dielectric material;

a metal liner positioned directly on top of the diffusion barrier;
a seed layer positioned directly on top of the metal liner, wherein the seed layer is made from a material comprising copper;
a copper material positioned directly on top of the seed layer;
a metallic cap positioned directly on top of and selective to the copper material; and
a capping layer positioned directly on top of and adjacent to the metallic cap;
wherein, the diffusion barrier, the metal liner, the seed layer, and the copper material having the re-entrant feature.

US Pat. No. 9,355,869

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising the steps of:
(a) providing a support substrate having a first surface;
(b) after said step (a),
mounting a first semiconductor chip over said first surface of said support substrate such that a first back surface of said
first semiconductor chip faces said first surface of said support substrate,

wherein said first semiconductor chip has a first main surface, a first semiconductor element, a first main surface pad formed
on said first main surface and electrically connected with said first semiconductor element, and a first conductive member
formed over said first main surface pad, and

wherein said first back surface is opposite to said first main surface;
(c) after said step (b),
mounting a second semiconductor chip over said first main surface of said first semiconductor chip such that a second back
surface of said second semiconductor chip faces said first main surface of said first semiconductor chip, and

electrically connecting said first main surface pad of said first semiconductor chip with a second back surface pad of said
second semiconductor chip via said first conductive member,

wherein said second semiconductor chip has a second main surface, a second semiconductor element, a second main surface pad
formed over said second main surface and electrically connected with said second semiconductor element, and a second conductive
member formed over said second main surface pad,

wherein said second back surface is opposite to said second main surface,
wherein said second back surface pad is formed on said second back surface and electrically connected with said second main
surface pad, and

wherein, in plan view, an area of said second semiconductor chip is smaller than an area of said first semiconductor chip;
(d) after said step (c),
sealing said first semiconductor chip, said second semiconductor chip, and said second conductive member by applying a sealing
material in a single application;

(e) after said step (d),
arranging a base substrate over said first surface of said support substrate such that a third surface of said base substrate
faces said first surface of said support substrate,

mounting said base substrate directly to said sealing material, and
electrically connecting a bonding lead of said base substrate with said second conductive member of said second semiconductor
chip,

wherein said bonding lead is formed on said third surface,
wherein a fourth surface of said base substrate is opposite to said third surface, and
wherein a bump land is formed on said fourth surface and electrically connected with said bonding lead; and
(f) after said step (e),
forming an external terminal on said bump land of said base substrate.

US Pat. No. 9,230,909

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF, AND MOUNTING METHOD OF SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a semiconductor substrate;
a first insulating film formed over the semiconductor substrate;
a plurality of first wiring having a first thickness formed over the first insulating film;
a second insulating film that includes an inorganic insulating film covering the first wiring and that has a flat surface
on which CMP processing has been performed;

a third insulating film including an inorganic insulating film formed over the flat surface of the second insulating film;
and

a plurality of second wiring having a second thickness formed over the third insulating film,
wherein the third insulating film has moisture resistance higher than that of the second insulating film,
wherein the second thickness is 10 times or more larger than the first thickness,
wherein the second wiring is located over the third insulating film without an organic insulating film being interposed between
itself and the third insulating film, and

wherein the thickness of the second insulating film in a region between two of the first wiring is almost equal to the total
of the thickness of the second insulating film over the first wiring and the first thickness.

US Pat. No. 9,530,769

SEMICONDUCTOR DEVICE WITH ELECTRO-STATIC DISCHARGE PROTECTION DEVICE ABOVE SEMICONDUCTOR DEVICE AREA

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first transistor formed on the main surface of the semiconductor substrate;
a first insulating film formed over the first transistor;
a second insulating film formed over the first insulating film; and
a second transistor formed over the first transistor in the main surface and over the first insulating film and formed in
the second insulating film,

wherein the second transistor includes a source electrode, a drain electrode, a gate electrode and a semiconductor layer,
wherein the source electrode and the drain electrode are connected to the semiconductor layer,
wherein a gate insulating film is between the semiconductor layer and the gate electrode,
wherein the source electrode is connected with a ground pad, and
wherein the drain electrode is connected with a pad for a signal.

US Pat. No. 9,331,212

SEMICONDUCTOR DEVICE COMPRISING AN ANTIFERROELECTRIC GATE INSULATING FILM

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a semiconductor substrate having a main surface;
source and drain regions formed in the main surface of the semiconductor substrate;
a gate insulating film formed, over a region between the source and drain regions, to be in contact with the main surface;
and

a gate electrode formed to be in contact with an upper surface of the gate insulating film and having a length of less than
45 nm and greater than zero in a direction from the source region to the drain region so as to make a transistor function,

wherein the source and drain regions, the gate insulating film, and the gate electrode configure the transistor, and
wherein the gate insulating film has an antiferroelectric film including at least one selected from a group of Pb(In0.5Nb0.5)O3, NH4H2PO4, and NH4H2AsO4.

US Pat. No. 9,324,663

SEMICONDUCTOR DEVICE INCLUDING A PLURALITY OF MAGNETIC SHIELDS

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a substrate;
a semiconductor chip formed on the substrate and having a first main surface facing the substrate, a second main surface opposite
to the first main surface, and a side surface arranged between the first main surface and the second main surface;

a magnetic storage device formed on the first main surface;
a first magnetic shield overlaying on the first main surface;
a second magnetic shield overlaying on the second main surface, the magnetic storage device being formed between the first
and second magnetic shields; and

a third magnetic shield overlaying on the side surface,
wherein the first and second magnetic shields are mechanically connected via the third magnetic shield.

US Pat. No. 9,324,644

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a die pad including a first surface, a second surface opposite to the first surface, and a first groove formed on the first
surface;

a suspension lead connected with the die pad; and
a semiconductor chip mounted on the first surface of the die pad via a die-bond material,
wherein the die pad is substantially quadrangular in plan view,
wherein the suspension lead is connected with a corner portion of the die pad,
wherein the semiconductor chip is substantially quadrangular in plan view,
wherein the semiconductor chip is mounted on the first surface of the die pad such that sides of the semiconductor chip are
arranged along sides of the die pad, respectively, in plan view,

wherein the first groove includes a bottom located between the first surface and the second surface,
wherein the suspension lead extends along a first direction in plan view,
wherein the first groove extends along a second direction intersecting with the first direction in plan view, and
wherein the first groove includes first portions not covered with the semiconductor chip in plan view, and a second portion
located between the first portions and also covered with the semiconductor chip in plan view.

US Pat. No. 9,124,284

A/D CONVERTER CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

Renesas Electronics Corpo...

1. An analog-to-digital converter circuit that converts an analog input signal into a digital quantity comprising:
an analog-to-digital converter unit that converts the analog input signal into a pre-correction digital value; and
a corrector unit that digitally corrects the pre-correction digital value output from the analog-to-digital converter unit,
wherein the corrector unit includes:
a weighting coefficient multiplier unit that outputs a post-correction digital value obtained by multiplying weighting coefficients
provided for each bit by each bit of the pre-correction digital value output from the analog-to-digital converter unit and
summing them, and

a weighting coefficient search unit that searches for weighting coefficients so as to minimize an error signal generated based
on the post-correction digital value and an approximate value for the post-correction digital value.

US Pat. No. 9,337,016

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising steps of:
(a) forming a first interlayer insulating film on a semiconductor substrate;
(b) forming a first contact hole in the first interlayer insulating film;
(c) after the step of (b), forming a first conductive film on the semiconductor substrate so as to bury the first conductive
film inside the first contact hole;

(d) removing the first conductive film outside the first contact hole so as to form a first plug made of the first conductive
film;

(e) after the step of (d), making an upper surface of the first interlayer insulating film to recede so that an upper surface
of the first interlayer insulating film is lower than an upper surface of the first plug;

(f) after the step of (e), forming a second interlayer insulating film having a dielectric constant lower than a dielectric
constant of silicon oxide on the semiconductor substrate;

(g) forming a first wiring trench in the second interlayer insulating film so that a part of the first plug is exposed and
so that a lower surface of the first wiring trench is lower than the upper surface of the first plug;

(h) after the step of (g), forming a second conductive film on the semiconductor substrate so as to bury the second conductive
film inside the first wiring trench; and

(i) removing the second conductive film outside the first wiring trench so as to form a first wiring made of the second conductive
film and connected to the first plug.

US Pat. No. 9,300,470

SEMICONDUCTOR DEVICE AND METHOD OF WRITING DATA TO SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
an identification information holding unit which outputs identification information which is preliminarily set as a fixed
value in each device;

a unique code generating unit which generates an initial unique code, the initial unique code being a value unique to the
semiconductor device and including an error in a random bit;

a first error correcting unit which is configured to receive external data from an external device and which corrects the
error in the initial unique code based on the external data to generate an intermediate unique code, wherein the external
data is data associated with the identification information;

a second error correcting unit which corrects an error in the intermediate unique code to generate a first determinate unique
code; and

a decrypting unit which decrypts, with the first determinate unique code as first encryption key information, transmission
data received from the external device, the transmission data being generated by the external device by encrypting confidential
information with second encryption key information generated by the external device on the basis of the intermediate unique
code, the decrypting reproducing the confidential information.

US Pat. No. 9,368,403

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a first wiring layer having a first wire over a semiconductor substrate,
forming a gate electrode not coupled with the first wire over the first wiring layer,
forming a gate insulation film over a side surface of the gate electrode,
forming a semiconductor layer coupled without via the gate insulation film, over the side surface of the gate electrode, and
forming a second wiring layer having a second wire not coupled with the gate electrode, and coupled with the semiconductor
layer, over the first wiring layer,

wherein the first wiring layer has a third wire,
the method, comprising the steps of:
after the step of forming the first wiring layer, and before the step of forming the gate electrode,
forming a first insulation film formed of a first lower layer insulation film, and a first upper layer insulation film stacked
over the first lower layer insulation film, over the first wiring layer,

forming a resist film having an opening at a position overlapping the third wire in plan view over the first insulation film,
by etching with the resist film as a mask, removing a part of the first upper layer insulation film,
removing the resist film by ashing, and
by etching with the first upper layer insulation film as a mask, removing a part of the first lower layer insulation film,
and exposing the third wire,

wherein in the step of forming the gate electrode, the gate electrode is formed in such a manner as to be coupled with the
third wire.

US Pat. No. 9,362,110

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device comprising:
forming a layer comprising aluminum oxide; and
heat treating the layer in an atmosphere not containing an oxidizing agent, wherein temperature and time of the heat treating
are predetermined as being effective to form, from the layer, an interface layer having a crystal structure containing both
tetra-coordinated Al atoms and hexa-coordinated Al atoms, with from 30% to 50% of the Al atoms being tetra-coordinated.

US Pat. No. 9,342,350

SYSTEM FOR SELECTING A TASK TO BE EXECUTED ACCORDING TO AN OUTPUT FROM A TASK CONTROL CIRCUIT

RENESAS ELECTRONICS CORPO...

1. A task processor comprising:
a processor;
a plurality of save registers for saving the data in the processor and that are respectively associated with a plurality of
tasks and connected to the processor via a plurality of data lines; and

a task control circuit that controls switching of tasks and is connected to the processor and the plurality of save registers
via signal lines,

wherein the processor includes:
a processing register that temporarily stores data for execution of a task; and
an execution control circuit that loads an instruction and an operand from a memory into the processing register, and to execute
the task according to the instruction and operand in the processing register,

wherein the execution control circuit includes an instruction decoder that determines whether the instruction to be executed
is a predetermined system call instruction or not and transmits a predetermined system call signal to the task control circuit
when executing the predetermined system call instruction, the predetermined system call signal not including any information
regarding which task to be executed next, and

wherein the task control circuit switches between tasks for execution autonomously upon receipt of the system call signal
by:

causing the data stored in the processing register to be saved in the save register associated with a task being executed,
selecting a task to be executed next in accordance with a predetermined rule, by not referring to the system call signal but
by referring to context information of each task, and

causing data in the save register associated with the selected task to be loaded into the processing register.

US Pat. No. 9,300,279

DETECTING AND DRIVING LOAD USING MOS TRANSISTOR

Renesas Electronics Corpo...

1. A semiconductor high-side driver comprising:
a power supply terminal;
an input terminal;
an output terminal to be coupled to a load element;
an output MOS transistor having a drain coupled to the power supply terminal, a source coupled to the output terminal and
a gate;

a sense MOS transistor having a drain coupled to the power supply terminal, a gate coupled to the gate of the output MOS transistor
and a source;

a control circuit coupled to the input terminal and provides a control signal to the gate of the output MOS transistor; and
a voltage detection circuit which includes:
a threshold voltage generation circuit having a first terminal coupled to the power supply terminal and a second terminal
which generates a voltage lower than a voltage of the power supply terminal by a threshold voltage; and

a comparator having:
a first input coupled to the second terminal of the threshold voltage generation circuit;
a second input coupled to the source of the sense MOS transistor; and
an output for providing a detection signal, wherein the detection signal is of a high level when a voltage at the first input
thereof is higher than a voltage at the second input thereof, and wherein the detection signal is of a low level when a voltage
at the first input thereof is lower than a voltage at the second input thereof.

US Pat. No. 9,153,271

OPTICAL DISC DEVICE

RENESAS ELECTRONICS CORPO...

1. A single-chip data processing unit for use in an optical disc device which can record and reproduce information by irradiating
a face of an optical disc with laser light from an objective lens and perform label printing by irradiating the other face
of the optical disc with the laser light from the objective lens, wherein the single-chip data processing unit can feedback-control
a position to which the objective lens is moved by a focusing actuator, based on a focus error signal for a focus servo based
on a reflection light from the optical disc exposed to the laser light, the single-chip data processing unit comprising:
an analog-to-digital conversion circuit which converts the focus error signal into digital data;
a servo control circuit which an output of the analog-to-digital conversion circuit is input to and which produces servo control
data; and

a digital-to-analog conversion circuit which converts the servo control data output by the servo control circuit or control
data for label printing into analog signals,

wherein the optical disc device further has:
a driver circuit which amplifies an output of the digital-to-analog conversion circuit and supplies the resultant signals
to the focusing actuator, the driver circuit being arranged so that its gain can be switched,

wherein when performing the label printing, the single-chip data processing unit feedforward-controls a position to which
the objective lens is moved by the focusing actuator based on the control data for the label printing which is stored in a
memory circuit as digital data and converted to an analog signal with the digital-to-analog conversion circuit,

wherein when performing the feedforward control, the data processing unit switches and controls a gain of the driver circuit
so as to become smaller than that of the driver circuit in the feedback control.

US Pat. No. 9,356,026

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a first transistor; and
a second transistor,
wherein the first transistor comprises:
a first p-type metal oxide semiconductor region;
a first source electrode connected with the first p-type metal oxide semiconductor region;
a first drain electrode connected with the first p-type metal oxide semiconductor region; and
a first gate electrode arranged to oppose to a part of the first p-type metal oxide semiconductor region, and
wherein the first gate electrode is arranged between the first source electrode and the first drain electrode in a top view,
and the first gate electrode and the first drain electrode overlap partially in the top view,

wherein the second transistor comprises:
a second p-type metal oxide semiconductor region;
a second source electrode connected with the second p-type metal oxide semiconductor region;
a second drain electrode connected with the second p-type metal oxide semiconductor region; and
a second gate electrode arranged to oppose to a part of the second p-type metal oxide semiconductor region,
wherein the second gate electrode is arranged between the second source electrode and the second drain electrode in the top
view, and the second gate electrode and the second drain electrode overlap partially in the top view,

wherein the first source electrode, the first drain electrode and the second gate electrode are provided in a same wiring
layer,

wherein the first p-type metal oxide semiconductor region and the second p-type metal oxide semiconductor region are provided
on the wiring layer, and the first p-type metal oxide semiconductor region and the second p-type metal oxide semiconductor
region are covered with an insulating film, and

wherein the first gate electrode, the second source electrode and the second drain electrode are arranged to be embedded in
the insulating film.

US Pat. No. 9,159,762

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a semiconductor layer with a front-side main surface and a back-side main surface opposed to the front-side main surface;
a plurality of light receiving elements formed in the semiconductor layer for performing photoelectric conversion;
a light receiving lens disposed above the back-side main surface of the semiconductor layer and supplying light to the light
receiving element; and

a mark formed inside the semiconductor layer,
wherein the mark extends from the front-side main surface to the back-side main surface,
wherein the mark has a deeply located surface recessed toward the front-side main surface rather than the back-side main surface,
and

wherein the deeply located surface is formed of silicon.

US Pat. No. 9,349,727

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
an active region formed on a main surface of a semiconductor substrate and including a plurality of impurity regions of the
same conductivity type arranged one-dimensionally; and

a plurality of gate electrodes, each of which is provided individually in each region between two adjacent impurity regions
of said plurality of impurity regions when the main surface of said semiconductor substrate is seen in a plan view, and each
of which forms an insulated gate field effect transistor together with the two adjacent impurity regions,

wherein said plurality of impurity regions include:
a first impurity region to which a predetermined voltage is applied via contact hole formed on said first impurity region,
second and third impurity regions forming a pair of conductive electrodes of an insulated gate field effect transistor, and
at least one impurity region disposed between said first and second impurity regions,
wherein a voltage that causes electrical conduction between said second and third impurity regions is applied to a gate electrode,
disposed between said second and third impurity regions, of said plurality of gate electrodes,

wherein all gate electrodes disposed between said first and second impurity regions, of said plurality of gate electrodes,
are configured to be electrically connected to said first impurity region constantly,

wherein no contact holes are arranged on the impurity regions disposed between said first and second impurity regions, and
wherein, by supplying said predetermined voltage, via a gate contact hole, to all gate electrodes disposed between said first
and second impurity regions, the impurity regions disposed between said first and second impurity regions are electrically
isolated from said first and second impurity regions.

US Pat. No. 9,337,419

MAGNETIC MEMORY CELL AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a magnetic memory cell, the method comprising:
forming a first magnetic layer comprising a reversible magnetization area;
forming a tunnel barrier layer over the reversible magnetization area of the first magnetic layer;
forming a second magnetic layer over the tunnel barrier layer and over the reversible magnetization area of the first magnetic
layer, the second magnetic layer comprising a fixed magnetization;

forming a mask over the second magnetic layer;
etching an unmasked part of the second magnetic layer to an intermediate position of the second magnetic layer in a thickness
direction of the second magnetic layer; and

forming a metallic oxide layer by oxidizing an unetched part of the unmasked part of the second magnetic layer.

US Pat. No. 9,225,434

SEMICONDUCTOR DEVICE FOR ELECTRICAL ISOLATION USING A PHOTOCOUPLER AND ISOLATOR TO CONVEY A SIGNAL

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a filter circuit to sub-divide and output a received signal as a relatively low frequency first signal and a relatively high
frequency second signal;

a first channel containing a photocoupler to convey the first signal output from the filter circuit;
a second channel containing an isolator, the isolator conveying the second signal output from the filter circuit independent
of the output of the photocoupler; and

a signal synthesis circuit to sum and output the first signal conveyed by way of the first channel and the second signal conveyed
by way of the second channel.

US Pat. No. 9,199,836

METHOD OF MANUFACTURING A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING A MEMS ELEMENT

Renesas Electronics Corpo...

1. A semiconductor integrated circuit device having a micro electro mechanical system (MEMS) element and comprising, in a
cross-section thereof:
a substrate (1s) underlying a first region (70) in which the MEMS element (MD) primarily is formed, the substrate (1s) also underlying a second region (72) in which a bump electrode (6) primarily is formed;

a lower MEMS electrode (LE) formed in the first region (70);

a wiring underlayer insulating film (15) formed on either side of the lower MEMS electrode (MD) and defining opposing sidewalls (15a, 15b) of a cavity (CV) of the MEMS element (MD), the wiring underlayer insulating film (15) extending into the second region (72);

an upper MEMS electrode (DP) spaced apart from the lower MEMS electrode (LE) and defining an upper wall of said cavity (CV),
the upper MEMS electrode (DP) comprising:

a first metal film (19) having spaced apart apertures (19h) formed over the cavity (CV), in the first region (70), and extending over the wiring underlayer insulating film (15), in the second region (72); and

a first insulating film (21) covering the first metal film (19) and occupying the spaced apart apertures (19h) formed therein, in the first region (70);

a diaphragm cover (11) formed over the upper MEMS electrode (DP), in the first region;

a rewiring layer (18) formed over the first metal film (19), in the second region (72); and

a bump electrode (6) formed over the rewiring layer (18), in the second region (72).

US Pat. No. 9,575,525

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

RENESAS ELECTRONICS CORPO...

1. A communication system for an automotive, comprising:
a plurality of electrical controller units, a first electrical controller unit of which has an active mode and a low consumption
mode; and

a communication bus coupled with the electrical controller units, wherein
when the first electrical controller unit is in the low consumption mode,
a second electrical controller unit outputs a first message for activating the first electrical controller in a first predetermined
time to the communication bus, and then outputs a second message including an ID signal of the first electrical controller
unit to the communication bus, and

the first electrical controller unit receives the first message and the second message including the ID signal output by the
second electrical controller unit from the communication bus, checks the ID signal whether the ID signal indicates the first
electrical controller unit or not, and when the ID signal indicates the first electrical controller unit, the first electrical
controller unit shifts to the active mode from the low consumption mode, and

no ID signal is included in the first message.

US Pat. No. 9,575,545

LSI AND INFORMATION PROCESSING SYSTEM

RENESAS ELECTRONICS CORPO...

1. A large scale integrated circuit (LSI) connectable to a peripheral device that enters power down mode in response to a
power down command, is released from the power down mode to normal mode in response to a release command, and when being in
the power down mode, is maintained in the power down mode even if it receives any commands other than the release command,
the LSI comprising:
a CPU;
a volatile memory that stores intermediate data of the peripheral device and is accessible from the CPU, the intermediate
data including data indicating that the peripheral device is in the power down mode; and

a control unit that transmits commands including the power down command and the release command to the peripheral device,
wherein the LSI has a plurality of operation modes including a low power consumption mode that volatilizes the intermediate
data stored in the volatile memory, and

the LSI causes the control unit to transmit the release command to the peripheral device when the LSI is released from the
low power consumption mode.

US Pat. No. 9,368,194

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SYSTEM WITH MEMORY CELL ARRAY

Renesas Electronics Corpo...

1. A semiconductor integrated circuit, comprising;
a first line provided with a power supply potential;
a first P-channel transistor having a source electrode which is coupled to the first line and a gate electrode which is coupled
to a first signal line;

a second P-channel transistor having a source electrode which is coupled to the first line and a gate electrode which is coupled
to a second signal line;

a third P-channel transistor having a source electrode which is coupled to a drain electrode of the second P-channel transistor;
a memory cell array which is coupled to a drain electrode of the first P-channel transistor and a drain electrode of the third
P-channel transistor; and

wherein first and second signals set the memory cell array to a first state when the first and second P-channel transistors
are set to an on state.

US Pat. No. 9,338,376

SOLID-STATE IMAGING DEVICE AND TECHNIQUE OF IMPROVING SIGNAL OUTPUT CHARACTERISTICS FROM A LIGHT RECEIVING ELEMENT

RENESAS ELECTRONICS CORPO...

1. A solid-state imaging device, comprising:
a light receiving element generating and storing charges in accordance with an amount of received light;
a floating diffusion configured to receive charges transferred from said light receiving element;
a first output circuit driven by a power supply voltage, and configured to output a voltage in accordance with a potential
of said floating diffusion to a data line;

a second output circuit connected in parallel with said first output circuit to said data line;
a reset voltage generating circuit configured to output a reset voltage to a reset voltage line by lowering said power supply
voltage; and

a reset transistor electrically connected between said reset voltage line and said floating diffusion and turned on in response
to a reset signal; wherein

said first output circuit includes at least one first transistor electrically connected between said data line and a power
supply line supplying said power supply voltage;

said second output circuit includes
an output node to which an output voltage in accordance with the potential of said floating diffusion is generated, and
at least one second transistor connected between said output node and said data line on a path from said power supply line
through said output node to said data line; and

said second transistor is configured to generate a potential difference equivalent to a potential difference between said
floating diffusion and said data line derived from said first transistor between said data line and said output node, when
a current equivalent to a current flowing through said first transistor is caused to flow through said second transistor.

US Pat. No. 9,461,163

SEMICONDUCTOR DEVICE INCLUDING SCHOTTKY BARRIER DIODE AND POWER MOSFETS AND A MANUFACTURING METHOD OF THE SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a semiconductor chip including a schottky barrier diode and a plurality of power MOSFETs which are formed on a semiconductor
substrate,

wherein the semiconductor substrate includes a first long side, a second long side located on the opposite side of the first
long side, a first short side and a second short side located on the opposite side of the first short side,

wherein the schottky barrier diode is formed in a first region of the semiconductor substrate and includes an anode electrode
and a cathode electrode,

wherein the plurality of power MOSFETs are formed in a plurality of second regions of the semiconductor substrate and respectively
include a gate electrode, a source region and a drain region,

wherein a first metal layer is formed over the semiconductor substrate, is electrically connected to the gate electrodes and
surrounds the first region and the second regions in a planar view,

wherein a plurality of gate fingers are unified with the first metal layer, are extending to a direction along the first short
side and are arranged between each of the second regions,

wherein a second metal layer is formed over the first region and the second regions and is electrically connected to the source
regions and the anode electrode, and

wherein a length along the first long side of the first region is larger than a length along the first short side of the first
region.

US Pat. No. 9,453,886

SWITCH CIRCUIT, SELECTION CIRCUIT, AND VOLTAGE MEASUREMENT DEVICE

Renesas Electronics Corpo...

1. A switch circuit comprising:
a switch element that is provided between an input terminal and an output terminal; and
a switch driving unit that drives the switch element on the basis of a control signal for instructing turn-on and turn-off
of the switch element, wherein

the switch driving unit is driven between a first power supply voltage and a second power supply voltage that are different
from each other,

an input voltage is supplied to the input terminal,
the input voltage is different from the first power supply voltage and the second power supply voltage, and
the switch driving unit includes
a source follower circuit having a drain side being connected to a first power supply terminal side that is supplied with
the first power supply voltage, inputting a voltage based on the input voltage, and supplying a voltage generated in an output
side to the switch element as a driving voltage for driving the switch element, and

a current control unit that opens and closes a current path between the output side of the source follower circuit and a second
power supply terminal supplied with the second power supply voltage, in response to the control signal.

US Pat. No. 9,344,089

SEMICONDUCTOR INTEGRATED CIRCUIT AND POWER-SUPPLY VOLTAGE ADAPTIVE CONTROL SYSTEM

Renesas Electronics Corpo...

1. A semiconductor integrated circuit comprising:
a plurality of input terminals;
a plurality of output terminals;
a plurality of flip-flop circuits;
a memory circuit configured to store configuration information to configure connection relationship between said input terminals
and said flip-flop circuits and connection relationship between said output terminals and said flip-flop circuits;

a first selector circuit configured to switch connection between said input terminals and said flip-flop circuits based on
said configuration information from said memory circuit;

a second selector circuit configured to switch connection between said output terminals and said flip-flop circuits based
on said configuration information from said memory circuit;

a third selector circuit configured to select an output of said flip-flop; and
a counter circuit configured to receive said selected output from said third selector, count a number of toggle times of said
output of said flip-flop circuits, and output the count value to a control device.

US Pat. No. 9,270,128

CELL PROTECTION SYSTEM

Renesas Electronics Corpo...

1. A cell protection system comprising:
a charge control MOSFET;
a charge current detection MOSFET having a drain and a gate which are common with the charge control MOSFET and having a cell
ratio which is different from that of the charge control MOSFET;

a discharge control MOSFET having a drain common with the charge control MOSFET;
a discharge current detection MOSFET having a drain and a gate which are common with the discharge control MOSFET and having
a cell ratio which is different from that of the discharge control MOSFET;

a charge current detection resistance provided in correspondence to the charge current detection MOSFET;
a discharge current detection resistance provided in correspondence to the discharge current detection MOSFET; and
a control circuit configured to generate a control signal which is supplied to gates of the charge control MOSFET and the
charge current detection MOSFET by digital signal processing which is based on a voltage value of the charge current detection
resistance, and to generate a control signal which is supplied to gates of the discharge control MOSFET and the discharge
current detection MOSFET by digital signal processing which is based on a voltage value of the discharge current detection
resistance.

US Pat. No. 9,318,330

PATTERNING PROCESS METHOD FOR SEMICONDUCTOR DEVICES

Renesas Electronics Corpo...

1. A method for forming a semiconductor device comprising:
obtaining a wafer, the wafer comprising an anti-reflective coating (ARC) layer formed over a photoresist layer which is formed
over spacer portions which are formed on a spacer assist layer which is formed over a hard mask layer, wherein the ARC layer
has an etch rate substantially similar to an etch rate of the spacer assist layer;

removing the photoresist layer and the ARC layer from a first region of the wafer exposing the spacer portions and portions
of the spacer assist layer while leaving the photoresist layer in a second region of the wafer, the photoresist layer in the
second region of the wafer contacting a spacer portion in the second region;

simultaneously etching the ARC layer in a second region of the wafer and the exposed spacer assist layer in the first region
of the wafer leaving remaining spacer portions and remaining spacer assist layer portions; and

etching a part of the hard mask layer to form hard mask portions in the first region, using the remaining spacer portions
and the remaining spacer assist layer portions as an etching mask.

US Pat. No. 9,166,041

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

12. A semiconductor device manufacturing method comprising the steps of:
(a) preparing a substrate, the substrate including a semiconductor substrate that has a first region, a second region, a third
region, and a fourth region on a main surface of the semiconductor substrate, an insulating layer formed on the main surface
of the semiconductor substrate, and a semiconductor layer formed on the insulating layer;

(b) forming, on the substrate, a device isolation region penetrating through the semiconductor layer and the insulating layer
so that the first region, the second region, the third region, and the fourth region are each surrounded by the device isolation
region when seen in a plan view;

(c) after the step (b), forming a first semiconductor region of a first conductivity type in the semiconductor substrate so
as to include the first region and the third region when seen in a plan view;

(d) after the step (b), forming a second semiconductor region of the first conductivity type in the semiconductor substrate
so as to include the first region and the third region when seen in a plan view;

(e) after the step (b), forming a third semiconductor region of a second conductivity type that is opposite to the first conductivity
type in the semiconductor substrate so as to include the second region and the fourth region when seen in a plan view;

(f) after the step (b), forming a fourth semiconductor region of the second conductivity type in the semiconductor substrate
so as to include the second region and the fourth region when seen in a plan view;

(g) after the step (b), removing the semiconductor layer and the insulating layer on the semiconductor substrate in the first
region and the second region; and

(h) after the steps (b), (c), (d), (e), (f), and (g), forming a first MISFET in the semiconductor layer that is remaining
via the insulating layer on the semiconductor substrate in the third region and forming a second MISFET in the semiconductor
layer that is remaining via the insulating layer on the semiconductor substrate in the fourth region,

wherein the second semiconductor region has impurity concentration higher than that of the first semiconductor region, is
contained in the first semiconductor region, and is shallower than the first semiconductor region,

the fourth semiconductor region has impurity concentration higher than impurity concentration of the third semiconductor region,
is contained in the third semiconductor region, and is shallower than the third semiconductor region,

the second semiconductor region has a bottom surface at a deeper level than a bottom surface of a portion of the device isolation
region interposed between the first region and the third region when seen in a plan view,

the second semiconductor region extends to also under a portion of the device isolation region interposed between the first
region and the third region when seen in a plan view,

the fourth semiconductor region has a bottom surface at a deeper level than a bottom surface of a portion of the device isolation
region interposed between the second region and the fourth region when seen in a plan view, and

the fourth semiconductor region extends to also under a portion of the device isolation region interposed between the second
region and the fourth region when seen in a plan view.

US Pat. No. 9,094,021

SEMICONDUCTOR DEVICE AND VARIATION INFORMATION OBTAINING PROGRAM

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
an oscillation circuit, including a transistor, configured to output a signal having a predetermined frequency; and
a control circuit, coupled to the oscillation circuit, configured to:
output a current set value to set an operation current of the oscillation circuit to a first current value,
obtain first frequency information related to the frequency of the output signal of the oscillating circuit when the operation
current is set to the first current value,

output the current set value to set the operation current of the oscillation circuit to a second current value,
obtain second frequency information related to the frequency of the output signal of the oscillation circuit when the operation
current is set to the second current value,

obtain manufacture variation information, including a variation amount of a threshold voltage of the transistor, based on
a difference between the first and second frequency information, and

correct the current set value used for oscillating operation of the oscillator circuit based on the variation amount of the
threshold voltage of the transistor.

US Pat. No. 9,299,794

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
(a) a laterally diffused MISFET, including:
(a1) a gate electrode disposed over a first surface of a semiconductor substrate via a gate insulating film to extend in a
first direction in plan view; and

(a2) a source region disposed in the semiconductor substrate on one side of the gate electrode, and a drain region disposed
in the semiconductor substrate on the other side of the gate electrode;

(b) a source plug disposed in a second region located on the one side of the gate electrode over the semiconductor substrate
to be electrically coupled to the source region;

(c) a source wiring disposed over the source plug;
(d) a drain plug disposed in a first region located on the other side of the gate electrode over the semiconductor substrate
to be electrically coupled to the drain region; and

(e) a drain wiring disposed over the drain plug,
wherein the drain plug is linearly disposed in the first region to extend in the first direction in plan view,
wherein the source plug includes a plurality of separated source plugs arranged at predetermined intervals in the first direction
in the second region in plan view,

wherein the source plugs include a first separated source plug column and a second separated source plug column,
wherein the first separated source plug column includes a plurality of separated source plugs arranged at first intervals
in the first direction,

wherein the second separated source plug column includes a plurality of separated source plugs arranged in the first direction
at third intervals smaller than the first intervals, and

wherein the first separated source plug column is disposed closer to the drain plug side than to the second separated source
plug column.

US Pat. No. 9,143,118

SEMICONDUCTOR MEMORY DEVICE WITH POWER INTERRUPTION DETECTION AND RESET CIRCUIT

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a plurality of memory cells each storing data depending on a change in level of a threshold voltage;
a voltage generation circuit generating a voltage to be applied to said memory cell;
a control logic unit generating a control signal activated while a power supply voltage is normally supplied;
a charge circuit connected to a first node on a voltage control line supplied with the voltage generated by said voltage generation
circuit, said charge circuit including a second node and a capacitive element connected to said second node;

a first discharge circuit connected to said second node, and connecting said second node to a ground when said control signal
is activated; and

a second discharge circuit connecting said first node to said ground when a voltage of said second node exceeds a threshold
value.

US Pat. No. 9,063,828

CONTROLLER AND TRANSFER SPEED CONTROL METHOD

Renesas Electronics Corpo...

1. A controller connected between a first device that adopts a bus standard A specifying a plurality of transfer speeds for
data transfer and a second device that adopts a bus standard B, the controller comprising:
a first interface that is connected to the first device and transmits and is configured to receive data to and from the first
device;

a second interface that is connected to the second device and is configured to transmit and receive data to and from the second
device;

a transfer data converting unit that is configured to convert data of the bus standard A and data of the bus standard B between
the first interface and the second interface; and

a transfer speed switching unit that is configured to receive transfer information regarding data transfer from the first
device via the first interface when the first device is connected, to evaluate a target transfer speed to be used by the second
device according to the transfer information or a result of analyzing the transfer information, and when a current transfer
speed input from the second device is different from the target transfer speed, to transmit a speed switching signal to the
second device via the second interface, the speed switching signal indicating switch to the target transfer speed, wherein
the transfer information includes information indicating a data transfer type indicating a different data transfer system
according to a kind of transfer data and a transfer method, and the transfer speed switching unit is configured to determine
the target transfer speed to be used by the second device according to the data transfer type.

US Pat. No. 9,312,295

SEMICONDUCTOR DEVICE AND A MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a chip region,
the chip region including:
a semiconductor substrate having main surfaces;
a photoelectric conversion element formed in the semiconductor substrate;
a mark-like appearance part extending from one of the main surfaces of the semiconductor substrate toward the other main surface
side opposite to the one main surface, and for applying a light to the photoelectric conversion element;

a pad electrode arranged at a position overlapping the mark-like appearance part on the one main surface side of the semiconductor
substrate; and

a coupling part for coupling the pad electrode and the mark-like appearance part,
wherein the mark-like appearance part includes an insulation film covering the entire side surface of a trench part formed
in the semiconductor substrate,

wherein at least a part of the pad electrode on the other main surface side is exposed through an opening reaching the pad
electrode from the other main surface side of the semiconductor substrate, and

wherein the mark-like appearance part and the coupling part are arranged in such a manner as to surround at least a part of
the outer circumference of the opening in plan view.

US Pat. No. 9,299,715

FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE

Renesas Electronics Corpo...

1. A manufacturing method of a semiconductor device including a memory cell region and a peripheral circuit region on a semiconductor
substrate, comprising the steps of:
(a) forming a first insulating film over the semiconductor substrate of the memory cell region and the peripheral circuit
region;

(b) forming a first conductive film over the first insulating film of the memory cell region and the peripheral circuit region;
(c) selectively patterning the first conductive film of the memory cell region while leaving the first conductive film of
the peripheral circuit region, thereby forming a first gate electrode in the memory cell region;

(d) forming a second insulating film including a charge storing region over the memory cell region and the peripheral circuit
region after the step (c);

(e) forming a second conductive film over the second insulating film of the memory cell region and the peripheral circuit
region;

(f) etching back the second conductive film, thereby removing the second conductive film in the peripheral circuit region
and forming a second gate electrode via the second insulating film on a sidewall of the first gate electrode in the memory
cell region; and

(g) patterning the first conductive film of the peripheral circuit region, thereby forming a third gate electrode in the peripheral
circuit region after the step (f).

US Pat. No. 9,275,940

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a wiring substrate having a first surface and a second surface opposite thereto, the first surface being formed in a rectangular
shape and provided with a plurality of leads;

a semiconductor chip having a quadrilateral main surface and a back surface opposite thereto, the main surface being provided
with a plurality of electrode pads, the semiconductor chip being mounted over the first surface of the wiring substrate;

a plurality of metal wires for electrically coupling the leads of the wiring substrate to the electrode pads of the semiconductor
chip; and

a plurality of terminals for external coupling provided at the second surface of the wiring substrate,
wherein the metal wires are respectively arranged at three out of four sides of the main surface of the semiconductor chip,
wherein the leads are provided in:
a plurality of lines at the first surface of the wiring substrate along a short side of the first surface outside the respective
sides of any one of two pairs of the opposed sides of the main surface of the semiconductor chip; and

a line formed along a long side of the first surface, a distance between the short side of the first surface and the plurality
of lines being greater than a distance between the long side of the first surface and the line formed along the long side
of the first surface, and

wherein the metal wires are electrically coupled to the leads.

US Pat. No. 9,214,930

POWER SUPPLY VOLTAGE TRANSITION COMPARISON CIRCUIT, POWER SUPPLY VOLTAGE TRANSITION COMPARISON METHOD, AND SEMICONDUCTOR INTEGRATED CIRCUIT

Renesas Electronics Corpo...

1. A power supply voltage transition comparison circuit comprising:
a comparator evaluation voltage setting circuit that generates a first divided voltage of a power supply voltage;
a first comparator that compares a reference voltage with the first divided voltage;
a voltage evaluation circuit that evaluates the power supply voltage based on a result of a comparison between the reference
voltage and the first divided voltage;

an evaluation voltage setting value output circuit that changes a ratio between the power supply voltage and the first divided
voltage based on a result of an evaluation of the power supply voltage; and

a voltage evaluation control circuit, wherein the voltage evaluation control circuit comprises an evaluation step counter
that counts a number of evaluation steps based on the result of the evaluation of the power supply voltage output from the
voltage evaluation circuit, and outputs a count value of the evaluation step counter to the evaluation voltage setting value
output circuit, the evaluation voltage setting value output circuit sets the ratio between the power supply voltage and the
first divided voltage based on a setting value associated with the count value, and the voltage evaluation control circuit
outputs a lock cancellation signal indicating a cancellation of a lock of an access-protected circuit when the count value
of the evaluation step counter is an upper-limit value for the evaluation step number and the evaluation result of the power
supply voltage output from the voltage evaluation circuit indicates that the power supply voltage is within an expected voltage
range.

US Pat. No. 9,214,412

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
(a) a first chip mounting portion;
(b) a first semiconductor chip arranged over the first chip mounting portion;
(c) a first pad formed in a surface of the first semiconductor chip;
(d) a first lead which serves as an external coupling terminal;
(e) a first conductive member which electrically couples the first pad and the first lead to each other; and
(f) a sealing body which seals a part of the first chip mounting portion, the first semiconductor chip, a part of the first
lead, and the first conductive member,

wherein the first conductive member includes:
(g1) a first plate-shaped portion; and
(g2) a first support portion formed integrally with the first plate-shaped portion,
and (g3) a second support portion formed integrally with the first plate-shaped portion, wherein the sealing body seals the
first support portion such that only a side surface of an end of the first support portion is exposed from a side surface
of the sealing body,

wherein the sealing body seals the second support portion such that only a side surface of an end of the second support portion
is exposed from a side surface of the sealing body,

wherein the first support portion is formed with a first bent portion, the first bent portion extending, in a plan view, from
a side surface of the plate-shaped portion,

and wherein the second support portion is formed with a second bent portion, the second bent portion extending, in a plan
view, from a side surface of the plate-shaped portion.

US Pat. No. 9,576,934

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a through via formed to penetrate a semiconductor substrate;
a first buffer circuit and a second buffer circuit;
a wiring forming layer formed in an upper layer of the semiconductor substrate;
a connecting wiring portion formed directly in an upper portion of the through via, a direction from the semiconductor substrate
to the wiring forming layer being an upward direction, and the connecting wiring portion being formed on a chip inner end
face which is an end face of the through via, and facing the upper portion of the semiconductor substrate at an end face of
the through via;

a first path connecting the first buffer circuit and the through via;
a second path connecting the second buffer circuit and the through via;
a first via connecting line formed directly on the connecting wiring portion in the upper portion of the through via to connect
the first path to the through via; and

a second via connecting line formed directly on the connecting wiring portion in the upper portion of the through via to connect
the second path to the through via,

wherein each of the first buffer circuit and the second buffer circuit comprises a transistor and the transistor of the first
buffer circuit and the transistor of the second buffer circuit are simultaneously in a conduction state,

wherein the first path and the second path are electrically connected via the connecting wiring portion, the first via connecting
line and the second via connecting line, and the first via connecting line and the second via connecting line do not directly
contact each other in the upper portion of the through via.

US Pat. No. 9,331,114

IMAGE PICKUP DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. An image pickup device, comprising:
a semiconductor substrate having a main surface;
a photoelectric conversion part that is formed in a predetermined region in the semiconductor substrate and converts entering
light into a charge;

a gate electrode of a transfer transistor that is formed over a surface of the semiconductor substrate and transfers the charge
generated in the photoelectric conversion part;

a sidewall insulating film that covers a side wall face of the gate electrode and that includes a part extending from a part
covering the side wall face and covering a surface of the photoelectric conversion part;

an interlayer insulating film formed so as to cover the sidewall insulating film; and
a waveguide that is formed so as to penetrate through the interlayer insulating film and to reach the sidewall insulating
film, and guides light to the photoelectric conversion part.

US Pat. No. 9,142,559

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit device, comprising:
a pair of complementary signal lines;
a first transistor including a gate, a source, and a drain, one of the source and the drain of the first transistor being
coupled to one of the pair of the complementary signal lines; and

a second transistor including a gate, a source, and a drain, the gate of the second transistor being coupled to the gate of
the first transistor, one of a source and a drain of the second transistor being coupled to an other of the source and the
drain of the first transistor, and an other of the source and the drain of the second transistor being coupled to an other
of the pair of the complementary signal lines,

wherein a direction of a gate width of the first transistor is different from a direction of a gate width of the second transistor.

US Pat. No. 9,081,058

SCAN TEST CIRCUIT, TEST PATTERN GENERATION CONTROL CIRCUIT, AND SCAN TEST CONTROL METHOD

Renesas Electronics Corpo...

1. A scan test circuit comprising:
a plurality of flip-flop circuits forming a clock domain that operates according to a same clock within a semiconductor integrated
circuit including a target of a delay fault test;

a test pattern generation mode control unit that is supplied with the same clock as the clock supplied to the plurality of
flip-flop circuits, and selects one of a skewed-load mode and a broadside mode as a test pattern generation mode of the delay
fault test; and

a scan enable signal output unit that outputs a first scan enable signal to the plurality of flip-flop circuits, the first
scan enable signal being determined based on the test pattern generation mode.

US Pat. No. 9,413,525

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device having a serdes (serializer/deserializer) that mutually convert serial data and parallel data, comprising:
one or more pairs of transmitter circuits and receiver circuits; and
a PLL (phase locked loop) which is connected with one or more of the transmitter circuits and one or more of the receiver
circuits, and includes an SSC (spread spectrum clocking) controller, and outputs an SSC clock signal,

wherein each of the transmitter circuits receives the SSC clock signal subjected to the spread-spectrum frequency modulation
from the PLL, and conducts parallel/serial conversion on the basis of the SSC clock signal, to thereby output the serial data
that has been subjected to the spread-spectrum frequency modulation,

wherein each of the receiver circuits, comprising:
a phase detector that detects an advance and a retard of a phase between input data and an extracted clock signal;
a frequency tracking loop that conducts a tracking control to reduce a frequency deviation between a frequency of the input
data and a frequency of the extracted clock signal on the basis of a result of integrating a detection result of the phase
detector together; and

a phase interpolator that receives the SSC clock signal subjected to spread-spectrum frequency modulation from the PLL, adjusts
a phase of the SSC clock signal on the basis of a detection result of the frequency deviation in the frequency tracking loop,
and supplies the SSC clock signal to the phase detector as the extracted clock signal,

wherein the frequency tracking loop receives frequency modulation information corresponding to the SSC clock signal subjected
to the spread-spectrum frequency modulation from the PLL, corrects the frequency deviation on the basis of the frequency modulation
information, and reduces the frequency modulation of the clock signal.

US Pat. No. 9,172,995

TRANSCODING DEVICE, TRANSCODING METHOD AND PROGRAM THEREOF

RENESAS ELECTRONICS CORPO...

1. A transcoding device to transcode either or both the video data or audio data contained in the input TTS (timestamped transport
stream) including time stamps attached to each packet, the transcoding device comprising:
a video processor to decode and recompress the video packets in the input TTS, and to also reattach time stamps in sequence
within the applicable frame period of each video frame to each video packet in the applicable video frame after recompression
when transcoding video data, and to output each video packet in the input TTS unchanged when not transcoding the video data;

an audio processor unit to decode and recompress the audio packet in the input TTS and to also reattach time stamps in sequence
within the applicable video frame period of each video frame to each audio packet in the applicable video frame after recompression
when transcoding the audio data, and to output the audio packet in the input TTS unchanged when not transcoding the audio
data; and

a remultiplexer unit to position the video packets and audio packets output from the video processor unit and audio processor
unit in the time sequence shown on each time stamp and obtain the output TTS,

wherein the video processor unit reattaches the time stamps so that the times shown on the time stamp of each video packet
after recompression are arranged at regularly spaced intervals within the period of the applicable video frame,

wherein the audio processor unit reattaches the time stamps so that the times shown on the time stamp of each audio packet
after recompression are arranged at regularly spaced intervals within the period of the applicable video frame, and

wherein the remultiplexer unit includes a correcting unit to correct the time stamps of the video packets or the audio packets
so that the respective times shown on the time stamps do not overlap during remultiplexing.

US Pat. No. 10,123,426

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, PRINTED BOARD AND MANUFACTURING METHOD OF THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

RENESAS ELECTRONICS CORPO...

1. A printed board comprising:a component built-in board in which at least a first core layer on which a first electronic component is mounted, a second core layer on which a second electronic component is mounted, an adhesive layer arranged between the first core layer and the second core layer, and a wiring layer are stacked,
wherein the wiring layer includes:
a front-surface-side wiring layer for electrically connecting a third electronic component mounted in a first core layer side of the component built-in board to at least one of the first electronic component and the second electronic component; and
a back-surface-side wiring layer for electrically connecting an external connection terminal formed in a second core layer side of the component built-in board to at least one of the first electronic component and the second electronic component, and
wherein the component built-in board includes a through electrode penetrating through at least the first core layer, the adhesive layer, and the second core layer.

US Pat. No. 9,530,819

MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of:
(a) providing a semiconductor wafer with numerous chip regions, the semiconductor wafer having numerous photodiodes formed
in a matrix at a semiconductor region in a first main surface of the semiconductor wafer in each of the chip regions so as
to configure a surface-irradiation type image sensor;

(b) after the step (a), forming a multi-layer wiring layer over the first main surface of the semiconductor wafer; and
(c) after the step (b), forming a color filter layer over the multi-layer wiring layer,
wherein the step (b) comprises sub-steps of:
(b1) forming a first wiring layer included in the multi-layer wiring layer;
(b2) after the step (b1), irradiating the first main surface of the semiconductor wafer with far-ultraviolet ray; and
(b3) after the step (b2), applying a heat treatment to the semiconductor wafer.

US Pat. No. 9,299,632

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a substrate having a first surface and a second surface opposite the first surface;
a semiconductor chip having a first main surface, a second main surface opposite the first main surface and a first side on
the first main surface, the semiconductor chip mounted on the substrate such that the second main surface is faced to the
first surface of the substrate, the semiconductor chip including:

a first electrode pad arranged along the first side on the first main surface;
an insulating film formed over the first electrode on the first main surface, the insulating film having a first opening exposing
a first part of the first electrode pad;

a first electrode disposed outside of the semiconductor chip and arranged along the first side of the semiconductor chip,
and the first electrode being connected with the first electrode pad on the semiconductor chip via a first wiring; and

a sealed resin body sealing the substrate, the semiconductor chip, the first electrode, the first electrode pad and the first
wiring,

wherein an area of the first opening is smaller than an area of the first electrode pad in a plan view,
wherein the first electrode pad is the closest to one end of the first side of the semiconductor chip,
wherein a center of the first electrode pad is positioned closer to the one end in a direction along the first side as compared
to a center of the first opening, and

wherein the first wiring is joined with the first part of the first electrode pad on the semiconductor chip.

US Pat. No. 9,257,371

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
(a) a die pad including:
a first surface,
a second surface opposite to the first surface,
a first side surface located between the first surface and the second surface,
a second side surface located between the first surface and the second surface, and opposite to the first side surface, and
a first step part protruding from the first side surface;
(b) a first component mounted on the die pad, and also arranged on the first surface of the die pad;
(c) a second component mounted on the die pad, and also arranged on the first step part; and
(d) a sealing body sealing the first component and the second component such that the sealing body exposes the second surface
of the die pad and covers the first step part,

wherein the second component is spaced from the first component in a plan view, and arranged side-by-side with the first component
along a first direction extending from the second side surface toward the first side surface.

US Pat. No. 9,171,595

SEMICONDUCTOR DEVICE INCLUDING NEGATIVE BIAS VOLTAGE GENERATION CIRCUIT

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a first memory macro having memory cells arranged in a first number of rows; and
a second memory macro having memory cells arranged in a second number of rows,
said first memory macro including
a first bit line connected to said memory cells,
a first negative bias voltage generation circuit generating a first negative bias voltage that is to be applied to said first
bit line during writing, and

a first negative bias reference voltage generation unit, and
said second memory macro including
a second bit line connected to said memory cells,
a second negative bias voltage generation circuit generating a second negative bias voltage that is to be applied to said
second bit line during writing, and

a second negative bias reference voltage generation unit, wherein
said first negative bias reference voltage generation unit generates a first negative bias reference voltage based on a first
resistance ratio between a first resistor and a second resistor, and outputs the first negative bias reference voltage to
a first negative bias reference interconnection,

said second negative bias reference voltage generation unit generates a second negative bias reference voltage based on a
second resistance ratio between a third resistor and a fourth resistor, and outputs the second negative bias reference voltage
to a second negative bias reference interconnection,

said first negative bias voltage generation circuit generates said first negative bias voltage based on said first negative
bias reference voltage,

said second negative bias voltage generation circuit generates said second negative bias voltage based on said second negative
bias reference voltage, and

said first resistance ratio is different from said second resistance ratio.

US Pat. No. 9,363,023

SEMICONDUCTOR DEVICE FOR ELECTRICAL ISOLATION USING A PHOTOCOUPLER AND ISOLATOR TO CONVEY A SIGNAL

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a filter circuit to sub-divide and output a received signal as a relatively low frequency first signal and a relatively high
frequency second signal;

a first channel containing a photocoupler to convey the first signal output from the filter circuit;
a second channel containing an isolator, the isolator conveying the second signal output from the filter circuit independent
of the output of the photocoupler; and

a signal synthesis circuit to sum and output the first signal conveyed by way of the first channel and the second signal conveyed
by way of the second channel.

US Pat. No. 9,356,810

SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit comprising:
a first wireless access system reception unit comprising a first analog reception unit and a first digital reception unit;
a voltage-controlled oscillator;
a phase locked loop;
a digital interface,
wherein the first analog reception unit comprises a first reception mixer for down-converting an RF reception signal into
a first analog reception signal and a first analog-digital converter for converting the first analog reception signal into
a first digital reception signal, and

wherein the first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop enable
switching from a reception operation for a first RF reception signal of a first system to a reception operation for a second
RF reception signal of a second system; and

a second wireless access system reception unit comprising a second analog reception unit and a second digital reception unit,
wherein the second analog reception unit comprises a second reception mixer for down-converting an RF reception signal into
a second analog reception signal and a second analog-digital converter for converting the second analog reception signal into
a second digital reception signal,

wherein the second digital reception unit comprises a second digital filter including an input terminal to which the second
digital reception signal is supplied,

wherein a second digital filter reception output signal outputted from an output terminal of the second digital filter in
the second digital reception unit can be outputted to the outside of the semiconductor integrated circuit through the digital
interface,

wherein the voltage-controlled oscillator generates an oscillation output signal as a base for the first reception local signal
supplied to the first reception mixer, and the phase locked loop locks a frequency of the oscillation output signal generated
from the voltage-controlled oscillator to a desired frequency of the first system,

wherein the voltage-controlled oscillator generates an oscillation output signal as a base for a second reception local signal
supplied to the second reception mixer, and the phase locked loop locks a frequency of the oscillation output signal generated
from the voltage-controlled oscillator to a desired frequency of the second system,

wherein the first wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop can
perform the reception operation for the first RF reception signal of the first system,

wherein the second wireless access system reception unit, the voltage-controlled oscillator, and the phase locked loop can
perform the reception operation for the second RF reception signal of the second system,

wherein the first wireless access system reception unit, the second wireless access system reception unit, the voltage-controlled
oscillator, and the phase locked loop enable switching from the reception operation for the first RF reception signal of the
first system to the reception operation for the second RF reception signal of the second system,

wherein in the switching, as for the reception operation for the first RF reception signal of the first system, the end transition
operation of the first digital reception unit is performed subsequent to the end transition operation of the first analog
reception unit,

wherein in the switching, for the reception operation for the second RF reception signal of the second system, a start transition
operation of the second analog reception unit and a start transition operation of the second digital reception unit are performed,
and

wherein in a period of the end transition operation of the first digital reception unit in the switching, the phase locked
loop starts a lock operation so as to match the frequency of the oscillation output signal generated from the voltage-controlled
oscillator to the desired frequency of the second system.

US Pat. No. 9,281,272

SEMICONDUCTOR DEVICE INCLUDING CONDUCTOR PATTERNS AS ELECTRODES OF A CAPACITIVE ELEMENT AND MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a first conductor pattern and a second conductor pattern running side by side with each other,
wherein the first conductor pattern serves as a first electrode of a capacitive element,
wherein the second conductor pattern serves as a second electrode of the capacitive element,
wherein the first conductor pattern and the second conductor pattern each include:
a first portion extending in a first direction;
a second portion that extends in the first direction and is arranged deviated from the first portion in a second direction
orthogonal to the first direction; and

a coupling portion that couples the first portion and the second portion and extends in the second direction,
wherein the first portion of the first conductor pattern and the second portion of the second conductor pattern are arranged
over a straight line,

wherein the first portion of the first conductor pattern and second portion of the first conductor pattern are not arranged
in parallel, and

wherein the first portion of the second conductor pattern and second portion of the second conductor pattern are not arranged
in parallel.

US Pat. No. 9,170,577

SEMICONDUCTOR INTEGRATED CIRCUIT AND OPERATION METHOD THEREOF

Renesas Electronics Corpo...

1. A semiconductor integrated circuit comprising a central processing unit, a built-in memory, and a pulse generating circuit,
the pulse generating circuit comprising a rise setting register, a fall setting register, a phase adjustment data register,
a cycle data register, a phase arithmetic circuit, a counter, a 1st comparator, a 2nd comparator, and a pulse generator,

wherein the counter starts to count up, incrementing its count value from a count initial value,
wherein the cycle data register stores, as cycle data, a count maximum value for the counter to count up to it,
wherein, when the count value of the counter has reached the count maximum value after the counter starts to count up from
the count initial value, the count value of the counter returns to the count initial value again and the counter restarts
to count up,

wherein the rise setting register stores a rise setting count value of the counter to make a pulse output signal being generated
by the pulse generator rise from a low level to a high level,

wherein the fall setting register stores a fall setting count value of the counter to make a pulse output signal being generated
by the pulse generator fall from the high level to the low level,

wherein, in response to detection of a match occurring between the count value of the counter and the rise setting count value,
detected by the 1st comparator, the pulse generator makes the pulse output signal change from the low level to the high level,

wherein, in response to detection of a match occurring between the count value of the counter and the fall setting count value,
detected by the 2nd comparator, the pulse generator makes the pulse output signal change from the high level to the low level,

wherein the phase adjustment data register stores a phase angle change value for timing adjustment of the pulse output signal
being generated by the pulse generator,

wherein the phase arithmetic circuit in the pulse generating circuit comprises a digital multiplying circuit, a digital dividing
circuit, a digital adding circuit, and a digital subtracting circuit,

wherein the digital multiplying circuit generates a multiplication output signal by performing multiplication of the phase
angle change value stored in the phase adjustment data register and the count maximum value stored in the cycle data register,

wherein the digital dividing circuit generates a division output signal by dividing the multiplication output signal from
the digital multiplying circuit by a phase angle for one cycle,

wherein the digital adding circuit is capable of adding the division output signal from the digital dividing circuit and the
rise setting count value stored in the rise setting register as well as adding the division output signal and the fall setting
count value stored in the fall setting register,

wherein the addition performed by the digital adding circuit generates a new rise setting count value and a new fall setting
count value required to delay the phase by the phase angle change value,

wherein the digital subtracting circuit is capable of subtracting the division output signal from the digital dividing circuit
from the rise setting count value stored in the rise setting register as well as subtracting the division output signal from
the fall setting count value stored in the fall setting register, and

wherein the subtraction performed by the digital subtracting circuit generates a new rise setting count value and a new fall
setting count value required to advance the phase by the phase angle change value.

US Pat. No. 9,159,807

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A manufacturing method of a semiconductor device including a field-effect transistor formed over a semiconductor substrate
with an SOI structure, comprising the steps of:
(a) preparing the semiconductor substrate including a support substrate, an insulating layer formed over the support substrate,
and a semiconductor layer formed over the insulating layer;

(b) after the step (a), forming an element isolation region at a main surface of the semiconductor substrate;
(c) after the step (b), forming a first impurity diffusion layer of a first conduction type over an upper surface of the support
substrate by implanting impurities of the first conduction type from the main surface of the semiconductor substrate into
the main surface of the semiconductor substrate, the first impurity diffusion layer having a lower resistance than that of
the support substrate;

(d) after the step (b), forming a second impurity diffusion layer of a second conduction type in the semiconductor layer by
implanting impurities of a second conduction type from the main surface of the semiconductor substrate into the main surface
of the semiconductor substrate,

(e) after the steps (c) and (d), forming the field-effect transistors including a gate electrode and source/drain regions
of the first conduction type over an upper surface of the semiconductor layer;

(f) after the step (e), forming a silicide layer over a surface of each of the gate electrode and the source/drain regions;
(g) after the step (f), forming a first insulating film over the main surface of the semiconductor substrate so as to cover
the main surface of the semiconductor substrate including the element isolation region, the gate electrode, the source/drain
region, and the silicide layer,

(h) after the step (g), forming a second insulating film over the first insulating film,
(i) after the step (h), respectively forming a first contact hole for exposing an upper surface of the silicide layer located
over each of the source/drain regions and the gate electrode, and a second contact hole for exposing an upper surface of the
first impurity diffusion layer directly under the element isolation region by etching; and

(j) after the step (i), respectively forming connection portions in the first and second contact holes,
wherein in the step (i), the first and second contact holes are formed in the same etching step,
wherein after the step (g) and before the step (h), a part of the first insulating film formed over the element isolation
region is removed and an opening formed by removing the part of the first insulating film has a diameter in a direction along
the main surface of the semiconductor substrate larger than that, in the same direction, of the second contact hole formed
in the step (i),

wherein in the step (i), an upper surface of the element isolation region in an area where the second contact hole is to be
formed is exposed,

wherein in the step (i), the second contact hole is formed to pass through an area where the first insulating film is to be
removed, and

wherein in the step (i), in the etching to form the second contact hole, the first insulating film is not removed.

US Pat. No. 9,143,102

OPERATIONAL AMPLIFYING CIRCUIT AND LIQUID CRYSTAL PANEL DRIVE DEVICE USING THE SAME

Renesas Electronics Corpo...

1. An operational amplifier circuit comprising:
a first differential amplifier section comprising a P-type differential pair of P-type transistors;
a second differential amplifier section comprising an N-type differential pair of N-type transistors;
an intermediate stage connected with outputs of said first and second differential amplifier sections and comprising a first
current mirror circuit of P-type transistors, and a second current mirror circuit of N-type transistors; and

an output stage configured to amplify a power of an output of said intermediate stage, wherein said first differential amplifier
section comprises a first current source and a first capacitor between sources of said P-type transistors of said P-type differential
pair and a positive side power supply voltage, and

wherein said second differential amplifier section comprises a second current source and a second capacitor between sources
of said N-type transistors of said N-type differential pair and a negative side power supply voltage.

US Pat. No. 9,069,254

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, AND MASK

RENESAS ELECTRONICS CORPO...

14. A method of manufacturing a semiconductor device, comprising the steps of:
providing a mask having a top surface, a back surface opposite to the top surface, a side surface disposed between the top
surface and the back surface, a side surface portion formed over the side surface, an exposure pattern formed over the top
surface, the exposure pattern including a reflection film formed over the top surface to reflect the exposure light, and an
absorber pattern formed over the reflection film to absorb the exposure light and a conductive film formed over the back surface,
wherein a water repellency of the side surface of the mask and the side surface portion is higher than a water repellency
of the top surface of the mask;

cleaning the back surface of the mask;
holding the mask using a holder for holding the mask with the back surface being in contact with the holder, using the holder
for holding the mask to electrostatically suck the conductive film while being in contact with the back surface to hold the
mask;

forming a resist film over a film to be etched formed over a main surface of a substrate;
irradiating the top surface of the mask held on the holder with exposure light to subject the resist film to pattern exposure
using reflected light which is the exposure light used for the irradiation and reflected by the top surface, the mask being
held with the cleaned back surface being in contact with the holder;

developing the resist film subjected to the pattern exposure to form a resist pattern to which the exposure pattern has been
transferred; and

using the resist pattern as an etching mask to etch the film to be etched.

US Pat. No. 10,026,700

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:a silicon substrate;
a Through-Silicon Via (TSV) penetrating through the silicon substrate from a rear surface of the silicon substrate to a front surface of the silicon substrate;
a first low relative permittivity film disposed over the front surface of the silicon substrate;
a second low relative permittivity film disposed over the first low relative permittivity film;
a contact layer disposed over the front surface of the silicon substrate and between the silicon substrate and the first low relative permittivity film;
a semiconductor element disposed in the silicon substrate;
a seal ring disposed surrounding the TSV in a plan view,
a wiring layer connected to the semiconductor element through the contact layer;
a TSV electrode disposed in the TSV to extend through the contact layer from the rear surface of the silicon substrate;
a metal electrode disposed over the second low relative permittivity film; and
one or more wiring layers that connect the metal electrode to the TSV electrode, extend through the first low relative permittivity film and the second low relative permittivity film, and are surrounded by the seal ring,
wherein the first low relative permittivity film is the closest low relative permittivity film to the silicon substrate, and the second low relative permittivity film is the farthest low relative permittivity film from the silicon substrate, and
wherein the seal ring extends continuously from the contact layer through the second low relative permittivity film.

US Pat. No. 9,269,767

POWER SUPERJUNCTION MOSFET DEVICE WITH RESURF REGIONS

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a semiconductor substrate of a first conductive type having first and second sides arranged along a first direction, and third
and fourth sides arranged along a second direction which is perpendicular to the first direction;

a drift region of the first conductive type formed on the semiconductor substrate;
a cell region arranged in the drift region;
a plurality of power MOSFETs formed in the cell region;
a first peripheral region arranged in the drift region and arranged between the cell region and the first side;
a second peripheral region arranged in the drift region and arranged between the cell region and the second side;
a third peripheral region arranged in the drift region and arranged between the cell region and the third side; and
a fourth peripheral region arranged in the drift region and arranged between the cell region and the fourth side,
wherein the first peripheral region has a plurality of first columns of the second conductive type opposite to the first conductive
type which are formed in the drift region and which extend along the first direction,

wherein the second peripheral region has a plurality of second columns of the second conductive type which are formed in the
drift region and which extend along the first direction,

wherein the third peripheral region has a plurality of third columns of the second conductive type which are formed in the
drift region and which extend along the second direction,

wherein the fourth peripheral region has a plurality of fourth columns of the second conductive type which are formed in the
drift region and which extend along the second direction,

wherein the cell region has a plurality of fifth columns of the second conductive type which are formed in the drift region
and which extend along the first direction,

wherein a resurf region of the second conductive type is formed in the drift region and is arranged at upper portions of the
first, second, third and fourth columns,

wherein a plurality of gate electrodes of the power MOSFETs are formed over the drift region of the cell region,
wherein a plurality of well regions of the second conductive type are formed in the drift region of the cell region, are arranged
at upper portions of the fifth columns and have higher impurity concentration than the resurf region,

wherein a plurality of source regions of the power MOSFETs of the first conductive type are formed in the well regions,
wherein, in the first direction, the cell region, the first peripheral region and the second peripheral region are arranged
between the third peripheral region and the fourth peripheral region,

wherein the third column and the fourth column extend along the second direction in order to abut the cell region, the first
peripheral region and the second peripheral region in the first direction,

wherein a plurality of impurity regions of the second conductive type having higher impurity concentration than the resurf
region are formed in the first, second, third and fourth peripheral regions in order to contact with the resurf region and
each of the first, second, third and fourth columns,

wherein the impurity region formed in the first peripheral region extends along the first column,
wherein the impurity region formed in the second peripheral region extends along the second column,
wherein the impurity region formed in the third peripheral region extends along the third column, and
wherein the impurity region formed in the fourth peripheral region extends along the fourth column.

US Pat. No. 9,239,612

FIRST POWER-ON RESET CIRCUIT WITH HIGHER POWER CONSUMPTION THAN A SECOND POWER-ON RESET CIRCUIT

RENESAS ELECTRONICS CORPO...

1. A data processing device, comprising:
a first power-on reset circuit;
a second power-on reset circuit with a higher power consumption and a higher reset voltage accuracy than said first power-on
reset circuit;

a low voltage detect circuit;
a storage unit storing information for determining whether to keep said second power-on reset circuit and said low voltage
detect circuit in an active state or an inactive state;

a central processing unit initialized in a response to respective outputs of said first and second power-on reset circuits
and setting said information in said storage unit; and

a power supply node providing a power to the data processing device,
wherein said first power-on reset circuit includes an internal node that is charged to have a variable potential as a potential
of the power supply node changes,

wherein the data processing device is configured to select one of a first operation and a second operation in a standby mode,
wherein, in the first operation, said first power-on reset circuit with a lower reset voltage is enabled, while said low voltage
detect circuit and said second power-on reset circuit is enabled, and

wherein, in the second operation, said first power-on reset circuit with the lower reset voltage is enabled, while said low
voltage detect circuit and said second power-on reset circuit is disabled.

US Pat. No. 9,166,057

SEMICONDUCTOR DEVICE HAVING THE BOTTOM GATE TYPE TRANSISTOR FORMED IN A WIRING LAYER

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
an underlying logic element formed over a substrate; and
a bottom gate type transistor comprising a semiconductor layer, a gate insulation film under the semiconductor layer, and
an antireflection film formed over an aluminum wire as a gate electrode, the gate electrode being under the gate insulation
film,

wherein the bottom gate type transistor is formed in a wiring layer formed over the underlying logic element and at least
in part overlaps the underlying logic element.

US Pat. No. 9,449,678

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Renesas Electronics Corpo...

1. A semiconductor integrated circuit device provided with a plurality of lead layers over a semiconductor substrate, comprising:
a plurality of first memory cells arranged along a first direction;
a plurality of second memory cells arranged along the first direction;
a first bit line and a second bit line, each commonly connected to the plurality of first memory cells;
a third bit line and a fourth bit line, each commonly connected to the plurality of second memory cells;
a plurality of word lines extending in a second direction, different from the first direction, each of the plurality of word
lines being connected to one of the plurality of first memory cells and one of the plurality of second memory cells, respectively;

first, second and third P-well regions provided on a main surface of the semiconductor substrate;
a first N-well region provided on the main surface of the semiconductor substrate and arranged between the first and second
P-well regions;

a second N-well region provided on the main surface of the semiconductor substrate and arranged between the second and third
P-well regions;

a first voltage supply lead formed at a first level of the plurality of lead layers;
a first supply path physically contacting a first portion of the first voltage supply lead opposite to the semiconductor substrate
and configured to supply a first voltage to the first P-well region from the first voltage supply lead;

a second supply path physically contacting a second portion of the first voltage supply lead, which is different from the
first portion, opposite to the semiconductor substrate and configured to supply the first voltage to the second P-well region
from the first voltage supply lead;

a third supply path connecting to a third portion of the first voltage supply lead, which is different from the first and
the second portions, opposite to the semiconductor substrate and configured to supply the first voltage to the third P-well
region from the first voltage supply lead;

a second voltage supply lead formed at the first level of the plurality of lead layers;
a fourth supply path physically contacting a fourth portion of the second voltage supply lead opposite to the semiconductor
substrate and supplying a second voltage to the first N-well region from the second voltage supply lead; and

a fifth supply path physically contacting a fifth portion of the second voltage supply lead, which is different from the fourth
portion, opposite to the semiconductor substrate and supplying the second voltage to the second N-well region from the second
voltage supply lead,

wherein the first, the second and the third portions are provided to be aligned linearly along the second direction in plan
view,

wherein the fourth and the fifth portions are provided to be aligned linearly along the second direction in plan view,
wherein the plurality of word lines are formed at the first level of the plurality of lead layers,
wherein the first, the second, the third and the fourth bit lines are formed at a second level of the plurality of lead layers
which is located at a higher level of the plurality of lead layers than the first level,

wherein each of the plurality of first memory cells includes:
first and second P-channel transistors provided on the first N-well region;
first and second N-channel transistors provided on the first P-well region; and
third and fourth N-channel transistors provided on the second P-well region,
wherein the first N-channel transistor and the first P-channel transistor configure a first inverter, the third N-channel
transistor and the second P-channel transistor configure a second inverter with an input of the first inverter coupled to
an output of the second inverter and with an output of the first inverter coupled to an input of the second inverter, and

wherein the second N-channel transistor electrically connects the first bit line with the output of the first inverter, and
the fourth N-channel transistor electrically connects the second bit line with the output of the second inverter, wherein
a gate of the fourth N-channel transistor and a gate of the second N-channel transistor are both coupled to a corresponding
word line, and

wherein each of the plurality of second memory cells includes:
third and fourth P-channel transistors provided on the second N-well region;
fifth and sixth N-channel transistors provided on the second P-well region; and
seventh and eighth N-channel transistors provided on the third P-well region,
wherein the fifth N-channel transistor and the third P-channel transistor configure a third inverter, the seventh N-channel
transistor and the fourth P-channel transistor configure a fourth inverter with an input of the third inverter coupled to
an output of the fourth inverter and with an output of the third inverter coupled to an input of the fourth inverter, and

wherein the sixth N-channel transistor electrically connects the third bit line with the output of the third inverter, and
the eighth N-channel transistor electrically connects the fourth bit line with the output of the fourth inverter, wherein
a gate of the eighth N-channel transistor and a gate of the sixth transistor are both coupled to a corresponding word line.

US Pat. No. 9,412,459

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A nonvolatile memory device comprising:
a voltage generator which generates a first voltage and a second voltage;
a first driver circuit and a second driver circuit, including respective MOS transistors;
a nonvolatile memory cell having a first gate and a second gate; and
a logic circuit having a MOS transistor and arranged to control operation of said nonvolatile memory cell,
wherein said first driver circuit is coupled with said first gate of said nonvolatile memory cell,
wherein said second driver circuit is coupled with said second gate of said nonvolatile memory cell,
wherein said voltage generator supplies said first voltage to said first driver circuit and said second voltage to said second
driver circuit,

wherein a thickness of a MOS transistor gate insulating film of said first driver circuit is thinner than a thickness of a
MOS transistor gate insulating film of said second driver circuit,

wherein said nonvolatile memory cell has a charge storage region between said second gate and a channel region,
wherein said first driver circuit is arranged on a first side of said nonvolatile memory cell,
wherein said second driver circuit is arranged on a second side, which is opposite side to said first side, of said nonvolatile
memory cell, and

wherein a thickness of a gate insulating film of said MOS transistor in said logic circuit is thinner than said thickness
of said MOS transistor gate insulating film of said second driver circuit.

US Pat. No. 9,391,606

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit device, comprising:
a reset pulse control unit that generates a reset pulse for recovery from degradation caused by Negative Bias Temperature
Instability (NBTI) of a Metal Oxide Semiconductor (MOS) transistor, inputs the reset pulse to a gate of the MOS transistor,
and then inputs an action control signal for activating the MOS transistor to the gate of the MOS transistor,

wherein the reset pulse control unit comprises:
a reset pulse generating unit that generates the reset pulse based on the action control signal; and
a signal switching control unit that outputs one of the action control signal and the reset pulse to the gate of the MOS transistor
based on the reset pulse generated by the reset pulse generating unit,

the signal switching control unit outputting the reset pulse to the gate of the MOS transistor before outputting the action
control signal to the gate of the MOS transistor.

US Pat. No. 9,349,438

SEMICONDUCTOR STORAGE DEVICE

Renesas Electronics Corpo...

1. A semiconductor storage device comprising:
a plurality of memory cells arranged in a matrix;
a plurality of bit-line pairs arranged corresponding to each column of the memory cells;
a write driver circuit operable to transmit data to a bit-line pair of a selected column according to write data; and
a write assist circuit operable to drive a bit line on a low potential side of the bit-line pair of the selected column to
a level of a negative voltage,

wherein the write assist circuit comprises:
first signal wiring;
a first driver circuit operable to drive the first signal wiring according to a control signal; and
second signal wiring coupled to the bit line on the low potential side and operable to generate the negative voltage by the
driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

US Pat. No. 9,343,395

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF SAME

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
an electrode pad formed over a first portion of a substrate;
a polyimide layer formed over a second portion of the substrate, the polyimide layer does not overlap the electrode pad in
a cross-sectional view;

a Cu film formed over the electrode pad and a portion of the polyimide layer;
a Ni film formed adjacent to the upper surface of the Cu film; and
a Pd film formed adjacent to the upper surface of the Ni film and having a film thickness less than that of the Ni film and
greater than or equal to 0.2 ?m and less than 1 ?m,

wherein a bonding wire consisting essentially of Au is directly coupled to an upper surface of the Pd film that is over the
second portion of the substrate,

wherein the thickness of the Cu film is greater than each of the Ni film and the Pd film, and
wherein the semiconductor device is sealed with a resin.

US Pat. No. 9,274,537

REGULATOR CIRCUIT

RENESAS ELECTRONICS CORPO...

1. A semiconductor integrated circuit comprising;
an internal circuit which is supplied an internal power supply voltage via an internal power supply voltage line, the internal
circuit consuming a current of the internal power supply voltage line,

a regulator circuit which converts a power supply voltage supplied from an input terminal to the internal power supply voltage
and outputs the internal power supply voltage to the internal power supply voltage line via an output terminal,

wherein the regulator circuit comprising:
a depression NMOS transistor coupled between the input and output terminals;
a control circuit configured to compare an output voltage of the output terminal with a predetermined reference voltage and
to control a gate voltage of the depression NMOS transistor according to the comparison result so that the output voltage
agrees with the reference voltage; and

a clamping circuit which is coupled between the output terminal and the gate of the depression NMOS transistor so that the
gate voltage of the depression NMOS transistor is within a predetermined voltage.

US Pat. No. 9,136,801

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE, ELECTRONIC DEVICE, AND RADIO COMMUNICATION DEVICE

Renesas Electronics Corpo...

1. A radio communication device, comprising:
a radio frequency IC for processing radio frequency signals; a baseband IC for processing baseband signals, coupled to the
radio frequency IC; an application processor IC including a driver circuit and a system state control unit, coupled to the
baseband IC; a first peripheral device coupled to the driver circuit via a first transmission line and controlled by the driver
circuit; a second peripheral device coupled to the driver circuit via a second transmission line and controlled by the driver
circuit; and a power management IC controlled by the system state control unit and configured to control a power supply to
the first and second peripheral devices, wherein the driver circuit and the first transmission line are coupled via a variable-impedance
circuit, wherein the driver circuit and the second transmission line are coupled via the variable-impedance circuit, wherein
the system state control unit is configured to adjust an impedance value of the variable-impedance circuit depending on a
state of the power supply to the first and second peripheral devices, and wherein a series termination circuit of the first
and second peripheral devices has a resistance of 50 ohms.

US Pat. No. 9,054,583

POWER-SUPPLY APPARATUS

Renesas Electronics Corpo...

1. A power-supply apparatus comprising:
an inductor;
a first transistor that supplies, in an on-state, a current to an input side of the inductor;
a second transistor that becomes, when the first transistor is in an off-state, an on-state and thereby brings the input side
of the inductor to a predetermined potential;

a signal generation unit that generates a first voltage signal corresponding to a first current flowing to the inductor;
a trans-conductance amplifier that outputs a second current according to the first voltage signal generated by the signal
generation unit;

a converter connected to an output side of the trans-conductance amplifier that converts the second current output from the
trans-conductance amplifier into a second voltage signal; and

a control unit that receives a first feedback signal corresponding to a voltage on an output side of the inductor and a second
feedback signal, which is the second voltage signal, and controls the first and second transistors based on the first feedback
signal and the second feedback signal.

US Pat. No. 9,484,271

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device, comprising steps of:
(a) forming a MISFET in a MISFET forming region of a substrate including a semiconductor layer arranged on a supporting substrate
so as to interpose an insulating layer;

(b) forming an opening portion by removing a portion of the insulating layer and the semiconductor layer in the MISFET forming
region of the substrate so as to expose the supporting substrate adjacent to a gate electrode of the MISFET without exposing
the supporting substrate directly below the gate electrode of the MISFET; and

(c) after the steps of (a) and (b), forming an integrally-formed first conductive film by filing the opening portion with
a conductive material such that the conductive material extends from above the gate electrode of the MISFET to the opening
portion.

US Pat. No. 9,378,804

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device, comprising:
a data receiving circuit coupled to a data input terminal receiving the data signal from a memory, and
a data strobe receiving circuit coupled to a first and a second input terminal receiving the data strobe signal and the inverted
data strobe signal from the memory, respectively, the data strobe receiving circuit including:

a termination circuit which couples the first and the second input terminal to a terminal potential based on a termination
enable signal;

a first comparator circuit which outputs the difference between the data strobe signal and the inverted data strobe signal;
a second comparator circuit which compares the level of one of the data strobe signal and the inverted data strobe signal;
a gate circuit which masks the output signal of the first comparator circuit with a mask signal; and
a control circuit which identifies the start timing of the preamble of the data strobe signal and the inverted data strobe
signal based on the output signal of the second comparator circuit, and sets the mask signal that instructs a masking state
of the output signal of the first comparator circuit until the start of the preamble,

wherein the control circuit sets the mask signal that instruct a unmasking state of the output signal of the first comparator
after the start of the preamble, and

wherein the data receiving circuit outputs the data signal as a read data from the memory based on an output signal of the
gate circuit while the mask signal indicates the unmasking state.

US Pat. No. 9,373,364

SEMICONDUCTOR MEMORY AND METHOD OF OPERATING SEMICONDUCTOR MEMORY

Renesas Electronics Corpo...

1. A semiconductor memory comprising:
a reference voltage control circuit containing a reference voltage generating circuit that generates a reference voltage;
a first memory circuit including: a first memory cell coupled to a first word line; a first bit line pair where data stored
in the first memory cell is read; a first precharge circuit that couples the reference voltage generating circuit with the
first bit line pair to precharge the first bit line pair to the reference voltage; a first equalizer circuit that equalizes
the first bit line pair; and a first sense amplifier that is coupled to the first bit line pair to amplify a voltage difference
of the first bit line pair during activation;

a second memory circuit including: a second memory cell coupled to a second word line; a second bit line pair where data stored
in the second memory cell is read; a second precharge circuit that couples the reference voltage generating circuit with the
second bit line pair to precharge the second bit line pair to the reference voltage; a second equalizer circuit that equalizes
the second bit line pair; and a second sense amplifier that is coupled to the second bit line pair to amplify a voltage difference
of the second bit line pair during activation,

wherein the second bit line pair is set at a dummy-bit-line voltage ranging from a ground voltage to ½×VDD in a reading/writing
period during which the first memory circuit is selected and the second memory circuit is unselected, and

wherein the first and second precharge circuits couple the first and second bit line pairs to the reference voltage generating
circuit in a precharge period after the reading/writing period;

a dummy-bit-line voltage generating circuit that generates the dummy-bit-line voltage, the dummy-bit-line voltage generating
circuit generating the dummy-bit-line voltage fluctuating with a power supply voltage,

wherein the dummy-bit-line voltage generating circuit determines the dummy-bit-line voltage according to a relation where
the lower the VDD, the higher the dummy-bit-line voltage and vice versa; and

a dummy-bit-line level switching circuit, which couples the second bit line pair to the dummy-bit-line voltage generating
circuit to apply the dummy-bit-line voltage to the second bit line pair in the reading/writing period during which the first
memory circuit is selected and the second memory circuit is unselected.

US Pat. No. 9,356,110

SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising:
forming a first polysilicon film on a substrate;
forming an oxide layer on a surface of the first polysilicon film;
forming a second polysilicon film above the first polysilicon film, the second polysilicon film being in contact with the
oxide layer; and

performing annealing at a temperature higher than a film formation temperature of the first and second polysilicon films in
a gas atmosphere containing at least one of N2, NO or N2O, after the formation of the second polysilicon film, such that nitrogen is introduced to the oxide layer to suppress grain
growth inside the polysilicon films.

US Pat. No. 9,349,816

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH OFFSET SIDEWALL STRUCTURE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device including a first n-type MISFET formed in a first region of a semiconductor substrate, a first p-type
MISFET formed in a second region of the semiconductor substrate, a second n-type MISFET formed in a third region of the semiconductor
substrate and having a thicker gate insulating film than that of the first n-type MISFET, and a second p-type MISFET formed
in a fourth region of the semiconductor substrate and having a thicker gate insulating film than that of the first p-type
MISFET, comprising:
a first gate insulating film formed over the first region;
a second gate insulating film formed over the second region;
a first gate electrode formed over the first gate insulating film;
a second gate electrode formed over the second gate insulating film;
a first n-type impurity region formed in the first region;
a second n-type impurity region formed in the first region and having a higher impurity concentration than the first n-type
impurity region;

a first p-type impurity region formed in the second region; and
a second p-type impurity region formed in the second region and having a higher impurity concentration than the first p-type
impurity region,

wherein first insulating films are formed over a side surface of the first gate electrode and over a side surface of the second
gate electrode;

wherein second insulating films are formed over the side surface of the first gate electrode and over the side surface of
the second gate electrode through the first insulating films;

wherein third insulating films are formed over the side surface of the first gate electrode and over the side surface of the
second gate electrode through the first and second insulating films;

wherein the first n-type impurity region is formed by introducing first impurities in self alignment with the first insulating
film formed in the first region,

wherein the first p-type impurity region is formed by introducing second impurities in self alignment with the second insulating
film formed in the second region,

wherein the second n-type impurity region is formed by introducing third impurities in self alignment with the third insulating
film formed in the first region,

wherein the second p-type impurity region is formed by introducing fourth impurities in self alignment with the third insulating
film formed in the second region,

wherein a first silicide film is formed on the second n-type impurity region and is formed in self alignment with the third
insulating film,

wherein a second silicide film is formed on the second p-type impurity region and is formed in self alignment with the third
insulating film,

wherein the second insulating film is a spacer state, and
wherein the third insulating film is a spacer state.

US Pat. No. 9,293,405

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
(a) a semiconductor chip having a surface on which a plurality of protruding electrodes are arranged;
(b) a wiring board including a core layer, the core layer having a first front surface on which a plurality of terminals corresponding
to the plurality of protruding electrodes are arranged, and a first back surface opposite the first front surface, the semiconductor
chip being mounted over the first front surface so that the plurality of protruding electrodes are electrically connected
to the plurality of terminals, respectively; and

(c) a sealing resin filled between the semiconductor chip and the wiring board,
wherein the plurality of protruding electrodes includes a plurality of first protruding electrodes and a plurality of second
protruding electrodes, and the plurality of terminals includes a plurality of first terminals and a plurality of second terminals,

wherein the core layer includes the plurality of first terminals, a plurality of first through-holes, and the plurality of
second terminals,

wherein the plurality of first terminals are arranged in a first area of the first front surface of the core layer, each of
the plurality of first terminals being electrically connected to a respective first protruding electrode of the plurality
of first protruding electrodes of the semiconductor chip,

wherein the plurality of first through-holes are arranged in a second area of the first front surface of the core layer, the
second area being closer to a center portion of the core layer than the first area is,

wherein the plurality of second terminals are arranged in a third area of the first front surface of the core layer, the third
area being closer to the center portion of the core layer than the second area is, each of the plurality of second terminals
being electrically connected to a respective second protruding electrode of the plurality of second protruding electrodes
of the semiconductor chip,

wherein each of the plurality of first through-holes penetrates from the first front surface of the core layer to the first
back surface of the core layer,

wherein some of the plurality of first through-holes are electrically connected to respective first terminals of the plurality
of first terminals,

wherein, in a plan view, the plurality of protruding electrodes of the semiconductor chip are not overlapped with the plurality
of first through-holes,

wherein the plurality of first terminals include first supply terminals which are configured to supply a first power supply
voltage or a first reference voltage from outside, and first signal terminals which are configured to transmit a signal voltage
to the outside, and

wherein the plurality of second terminals include only second supply terminals which are configured to supply a second power
supply voltage or a second reference voltage from the outside.

US Pat. No. 9,202,537

SEMICONDUCTOR MEMORY DEVICE

Renesas Electronics Corpo...

1. A semiconductor memory device comprising: a sense amplifier section that detects information stored in a memory cell through
a bit line; wherein the sense amplifier section includes a plurality of first diffusion layers that are formed over a semiconductor
layer and disposed at predetermined intervals in a first direction, a plurality of second diffusion layers that are formed
over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction,
and disposed at the predetermined intervals in the first direction, a plurality of first regions that have a predetermined
width in the first direction for separating the first diffusion layers from each other, a plurality of second regions that
align with the first regions in the second direction and have the predetermined width for separating the second diffusion
layers from each other, a plurality of contacts that are formed over the first diffusion layers and over the second diffusion
layers, and a plurality of gates that are long in the second direction, formed over one or both of portions of the semiconductor
layer that are exposed by the first regions and the second regions.

US Pat. No. 9,190,475

SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD

Renesas Electronics Corpo...

1. A semiconductor device manufacturing method comprising:
forming a first insulating film over a semiconductor substrate;
forming a first wiring layer in the first insulating film, the first wiring layer including a gate electrode;
forming a gate insulating film over the gate electrode and at least a portion of the first insulating film;
forming a semiconductor layer over the gate insulating film such that the gate insulating film is between the gate electrode
and the semiconductor layer; and

forming a source electrode and a drain electrode over the semiconductor layer so as to be connected with first and second
portions of the semiconductor layer, respectively,

wherein the semiconductor layer comprises a p-type metal oxide semiconductor,
wherein the forming the drain electrode causes at least the second portion of the semiconductor layer to exhibit n-type semiconductor
characteristics, and

wherein the gate electrode and the drain electrode are separated from each other in a top view.

US Pat. No. 9,157,948

SEMICONDUCTOR DEVICE AND FAULT DIAGNOSIS SYSTEM

Renesas Electronics Corpo...

1. A semiconductor device comprising:
an analog to digital conversion unit that converts a second analog signal into a first digital signal, the second analog signal
being obtained by adding a first analog signal and an offset signal with a signal band different from the first analog signal;

a signal extraction unit that extracts a second digital signal from the first digital signal, the second digital signal corresponding
to the signal band of the offset signal; and

a fault detection unit that detects a fault in the analog to digital conversion unit based on the second digital signal and
a setting value, the setting value being set upon generating the offset signal.

US Pat. No. 9,299,681

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device, comprising:
(a) providing a semiconductor chip having a main surface over which a plurality of pad electrodes are formed,
wherein a plurality of metal bumps are formed on the plurality of pad electrodes, respectively;
(b) positioning the semiconductor over a first main surface of a wiring substrate such that the main surface of the semiconductor
chip faces the first main surface of the wiring substrate, and contacting the plurality of metal bumps of the semiconductor
chip to a plurality of solders of the wiring substrate without using a flux, respectively and scrubbing the plurality of metal
bumps of the semiconductor chip and the plurality of solders of the wiring substrate with each other;

(c) after the step (b), supplying O2 plasma to the semiconductor chip and the wiring substrate; and
(d) after the step (c), injecting under-filling resin between the main surface of the semiconductor chip and the first main
surface of the wiring substrate.

US Pat. No. 9,264,083

COMMUNICATION CIRCUIT AND SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A communication circuit, comprising:
a receiver that provides communication by using a first transmission path and a second transmission path, the first transmission
path being used to transmit a first signal, and the second transmission path being used to transmit a second signal;

wherein the receiver includes:
a compensation circuit that compensates for an attenuation of a current when noise is superimposed on the first signal and
on the second signal;

wherein the compensation circuit includes:
a first compensation circuit; and
wherein the first compensation circuit detects an electric current attenuation of the first signal when the noise is superimposed
on the first signal, and compensates for the attenuation of the first signal by adding the detected electric current attenuation
to the second signal.

US Pat. No. 9,257,171

SEMICONDUCTOR STORAGE APPARATUS WITH MASK SELECTION GATES FOR DATA WRITE

RENESAS ELECTRONICS CORPO...

1. A semiconductor memory device, comprising:
a plurality of word lines;
a plurality of pairs of bit lines;
a plurality of memory cells coupled to the plurality of word lines and the plurality of pairs of bit lines;
a plurality of sense amplifiers each coupled between a corresponding pair of bit lines;
a plurality of first driver transistors coupled between at least one of the sense amplifiers and a first power supply line;
a plurality of second driver transistors coupled between at least two of the sense amplifiers and a second power supply line;
a pair of common data lines;
a plurality of column selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one
of pair of common data lines, and

a plurality of mask selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one
of column selection gates.

US Pat. No. 9,166,738

SEMICONDUCTOR DEVICE AND DATA TRANSMISSION METHOD

Renesas Electronics Corpo...

1. A semiconductor device comprising:
a transmitting circuit that operates in a first power supply system and outputs a pulse signal based on an input data signal
and an input first retransmission request signal;

a receiving circuit that operates in a second power supply system different from the first power supply system and restores
a delayed data signal based on the pulse signal; and

an insulation coupler that couples the transmitting circuit and the receiving circuit by a magnetic field or an electric field,
wherein

the transmitting circuit generates the delayed data signal and a first delayed retransmission request signal by delaying the
input data signal and the first retransmission request signal, respectively, and further generates a prohibiting signal during
a first specified period from a first time before an edge of the delayed data signal to a second time after the edge of the
delayed data signal and outputs the pulse signal at the edge of the delayed signal and an edge of the first delayed retransmission
request signal based on the prohibiting signal.

US Pat. No. 9,166,017

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device having an active portion and a peripheral portion outside the active portion
and having elements of an IGBT formed in the active portion, the method comprising the steps of:
(a) preparing a substrate exhibiting n-type conductivity type that is to serve as a base layer of the IGBT;
(b) forming a first insulating film on a main surface of the substrate, the first insulating film including a plurality of
thick-film portions having a first thickness and a plurality of thin-film portions having a second thickness smaller than
the first thickness;

(c) forming a spacing portion in the thin-film portion of the first insulating film, the spacing portion reaching the substrate;
(d) forming a surface semiconductor layer exhibiting n-type conductivity type on the thin-film portion of the first insulating
film by burying the spacing portion, the surface semiconductor layer having a thickness of 20 to 100 nm;

(e) forming a channel layer exhibiting p-type conductivity type of the IGBT in the surface semiconductor layer of the active
portion;

(f) forming an emitter layer exhibiting p-type conductivity type of the IGBT in the surface semiconductor layer of the active
portion so that the emitter layer is in contact with the channel layer, the emitter layer having a higher concentration than
the channel layer;

(g) forming a gate insulating film of the IGBT on a surface of the surface semiconductor layer of the active portion;
(h) forming a gate electrode of the IGBT on the gate insulating film;
(i) introducing an impurity exhibiting n-type conductivity type into the surface semiconductor layer of the active portion
to form a source layer of the IGBT in the surface semiconductor layer on both sides of the gate electrode;

(j) forming an interlayer insulating film on the main surface of the substrate, the interlayer insulating film composed of
a first oxide film, a nitride film, and a second oxide film;

(k) etching the second oxide film using the nitride film as an etching stopper and then sequentially etching the nitride film
and the first oxide film to form, in the interlayer insulating film, openings reaching the emitter layer and the source layer;

(l) forming an emitter electrode of the IGBT on the emitter layer and the source layer the emitter electrode electrically
connected to the emitter layer and the source layer;

(m) reducing the thickness of the substrate from a back surface to form the base layer of the IGBT;
(n) forming a buffer layer exhibiting n-type conductivity type of the IGBT on the back surface of the substrate;
(o) forming a collector layer exhibiting p-type conductivity type of the IGBT on the back surface of the substrate; and
(p) forming a collector electrode of the IGBT electrically connected to the collector layer.

US Pat. No. 9,157,959

SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A semiconductor device comprising:
a plurality of modules;
a plurality of delay monitors, wherein each delay monitor includes a ring oscillator having a plurality of gate elements and
measures a delay time of said gate elements, and

a control unit that determines if a module of the plurality of modules, which is proximate to said delay monitor suffers from
aged deterioration, based on the delay time measured by said delay monitor,

wherein, of said delay monitors, every two delay monitors disposed near to each other form one pair, wherein a ring oscillator
in one delay monitor of said pair continues to oscillate except for a predetermined number of cycles before and after a delay
time measurement period and a ring oscillator in the other delay monitor of said pair oscillates only during a delay time
measurement period, and said control unit determines if the module suffers from aged deterioration, according to a difference
between a delay time measured by said one delay monitor and a delay time measured by said other delay monitor.

US Pat. No. 9,054,726

PASSIVE AMPLIFICATION CIRCUIT AND ANALOG-DIGITAL CONVERTOR

RENESAS ELECTRONICS CORPO...

1. A passive amplification circuit comprising:
an input terminal group configured to input a differential signal;
first to fourth capacitances charged with voltages of a differential signal in a sampling operation;
a plurality of switches configured to switch a connection relation of the first to fourth capacitances between a first state
of the sampling operation and a second state of an amplification operation; and

an output terminal group configured to output the differential signal amplified in the amplification operation,
wherein in the first state, the first capacitance and the second capacitance are connected in parallel and the third capacitance
and the fourth capacitance are connected in parallel,

wherein in the second state, the first capacitance and the second capacitance are connected in series and the third capacitance
and the fourth capacitance are connected in series,

wherein each of one end and the other end of each of the first to fourth capacitances is connected with any one of the plurality
of switches, the output terminal group, a power supply voltage and a ground voltage,

wherein one end and the other end of each of the plurality of switches is connected with any one of the first to fourth capacitances,
the input terminal group, the output terminal group, the power supply voltage and the ground voltage;

wherein the plurality of switches comprise:
a first switch group set to a conductive state in the first state and a block-off state in the second state; and
a second switch group set to the block-off state in the first state and the conductive state in the second state,
wherein the one end of each of the switches of the first switch group is connected with any one of the input terminals of
the input terminal group and the other end thereof is connected with any one of the first to fourth capacitances, and

wherein the one end of each of the switches of the second switch group is connected with the power supply voltage or the ground
voltage, and the other end thereof is connected with any one of the first to fourth capacitances,

wherein the input terminal group comprises:
a positive side input terminal configured to input a positive side voltage of the differential signal; and
a negative side input terminal configured to input a negative side voltage of the differential signal,
wherein the output terminal group comprises:
a positive side output terminal configured to output the positive side voltage of the amplified differential signal; and
a negative side output terminal configured to output the negative side voltage of the amplified differential signal,
wherein in the first state, the first to fourth capacitances are connected in parallel between the positive side input terminal
and the negative side input terminal,

wherein in the second state, the first capacitance is connected between the power supply voltage and the negative side output
terminal,

wherein in the second state, the second capacitance is connected between the negative side output terminal and the ground
voltage,

wherein in the second state, the third capacitance is connected between the power supply voltage and the positive side output
terminal,

wherein in the second state, the fourth capacitance is connected between the positive side output terminal and the ground
voltage, and

wherein the first capacitance and the third capacitance have an identical first capacitance value, and the second capacitance
of the fourth capacitance have an identical second capacitance value.

US Pat. No. 10,068,941

IMAGE PICKUP DEVICE AND METHOD FOR MANUFACTURING THE SAME

RENESAS ELECTRONICS CORPO...

1. A method for manufacturing an image pickup device, comprising:preparing a semiconductor substrate having a main surface and a rectangular pixel region at the main surface;
forming a plurality of photoelectric conversion devices in the pixel region of the semiconductor substrate;
forming, over the plurality of photoelectric conversion devices, an interconnect layer containing copper;
forming an insulating liner layer containing nitrogen to cover an upper surface of the interconnect layer; and
selectively removing the insulating liner layer in a region that is outside the pixel region and is located within a region that has a corner in a vertical angle relationship with one of four corners of the pixel region in a plan view, to form an extra-pixel removal region in the insulating liner layer,
wherein an active region of a single conduction type surrounded by an element isolating insulating layer is formed in an entire region of the main surface of the semiconductor substrate located directly under the extra-pixel removal region.

US Pat. No. 9,355,890

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE

RENESAS ELECTRONICS CORPO...

1. A method of manufacturing a semiconductor device comprising:
providing a semiconductor substrate that is comprised of: a supporting substrate; a first insulating film formed over the
supporting substrate; and a semiconductor layer formed over the first insulating film, and that includes a first region and
a second region over the upper surface of the semiconductor layer;

exposing the upper surface of the first insulating film in the second region by forming a second insulating film over the
semiconductor layer and by processing the semiconductor layer with the use of the second insulating film as a mask;

forming a third insulating film so as to cover the semiconductor layer, the second insulating film, and the first insulating
film;

exposing the upper surface of the supporting substrate by opening the third insulating film and the first insulating film
in the second region;

forming a first epitaxial layer in the opening of the first insulating film and the third insulating film;
exposing the upper surface of the semiconductor layer by polishing the first epitaxial layer, the third insulating film, and
the second insulating film; and

after the exposing of the upper surface of the semiconductor layer, forming a semiconductor element over each of the semiconductor
layer in the first region and the first epitaxial layer in the second region.

US Pat. No. 9,342,097

MICROCONTROLLER AND METHOD OF CONTROLLING THE SAME

RENESAS ELECTRONICS CORPO...

1. A microcontroller comprising:
a CPU (Central Processing Unit);
a data input unit; and
an oscillator that supplies a clock signal in response to operational modes of the microcontroller, wherein
the operational modes include a STOP mode, a SNOOZE mode and a RUN mode,
in the STOP mode, the oscillator and the CPU are stopped,
in the RUN mode, the CPU and the data input unit operate using the clock signal supplied from the oscillator, and
in the SNOOZE mode, the oscillator starts and supplies the clock signal to the data input unit when the data input unit receives
first data, and the microcontroller switches to the RUN mode after the data input unit receives second data using the clock
signal.

US Pat. No. 9,088,725

IMAGE PICKUP APPARATUS

Renesas Electronics Corpo...

1. An image pickup apparatus comprising:
a first image pickup unit that repeats an exposure and output of an image signal obtained through the exposure to obtain a
first picture signal and outputs the first picture signal;

a second image pickup unit that repeats an exposure and output of an image signal obtained through the exposure to obtain
a second picture signal and outputs the second picture signal; and

a first control unit that controls the timing at which the first image pickup unit or the second image pickup unit starts
an exposure,

wherein
the first control unit subtracts a first difference from an exposure-output time of the first image pickup unit to obtain
a second difference, and outputs a first control signal,

the first control signal delaying one of i) the timing at which the second image pickup unit starts an exposure, by a value
obtained by subtracting the second difference from an exposure interval, and ii) the timing at which the first image pickup
unit starts an exposure, by the second difference,

the exposure-output time being a time lag between when each of the first and second image pickup units starts an exposure
and when the image pickup unit starts outputting an image signal obtained through the exposure,

the first difference being a difference between the timing when the first image pickup unit started outputting a predetermined
image signal and the timing when the second image pickup unit started an exposure for obtaining an image signal that the second
image pickup unit outputted immediately after the first image pickup unit started outputting the predetermined image signal.

US Pat. No. 9,391,066

SEMICONDUCTOR DEVICE

Renesas Electronics Corpo...

1. A semiconductor device comprising:
(a) a semiconductor substrate of substantially rectangular shape having a pair of long edges and a pair of short edges;
(b) an internal circuit including a plurality of MISFETs formed over the semiconductor substrate;
(c) a plurality of input protection elements formed over the semiconductor substrate so as to protect the internal circuit
against static electricity;

(d) a first insulating film formed over the semiconductor substrate so as to cover the plurality of MISFETs and the plurality
of input protection elements; and

(e) a plurality of input bump electrodes formed over the first insulating film, the plurality of input bump electrodes being
arranged along a first long edge of the pair of long edges,

wherein the plurality of input bump electrodes are for receiving input signals from an external device,
wherein the plurality of input protection elements are electrically coupled between respective ones of the plurality of input
bump electrodes and the internal circuit,

wherein the plurality of input bump electrodes include a first input bump electrode and a second input bump electrode,
wherein the plurality of input protection elements include a first input protection element and a second input protection
element,

wherein the first input protection element electrically coupled to the first input bump electrode overlaps the first input
bump electrode in a planar view, and

wherein the second input protection element electrically coupled to the second input bump electrode does not overlap the second
input bump electrode in a planar view.

US Pat. No. 9,176,568

CLOCK CONTROL AND POWER MANAGEMENT FOR SEMICONDUCTOR APPARATUS AND SYSTEM

Renesas Electronics Corpo...

1. A semiconductor apparatus comprising;
a circuit including a predetermined function;
a clock generating circuit that generates a clock signal supplied to the circuit;
a clock control circuit that outputs:
a plurality of control signals to the clock generating circuit,
a first signal that indicates when a frequency of the clock signal is being changed from a predetermined frequency to a higher
frequency, and

a second signal that indicates when the clock signal is being supplied to the circuit; and
a notification signal generating circuit, coupled to the clock control circuit, that generates a notification signal for notifying
a power supply apparatus when the clock signal frequency is being changed based on the first signal, and when the clock signal
is being supplied to the circuit based on the second signal.

US Pat. No. 9,354,893

DEVICE FOR OFFLOADING INSTRUCTIONS AND DATA FROM PRIMARY TO SECONDARY DATA PATH

Renesas Electronics Corpo...

1. An information processing device comprising:
a first cache that stores a first instruction code comprising a plurality of specific instruction codes;
a second cache that stores data to be processed;
first and second arithmetic unit group circuits configured to execute operations on the data by a plurality of arithmetic
units configured to operate in parallel;

a first arithmetic-control circuit configured to read the first instruction code, and to generate one or more operation instructions
for the first arithmetic unit group circuit based on the first instruction code; and

a second arithmetic-control circuit configured to include a fixed instruction register fixed in length that stores a second
instruction code, comprising one or more specific instruction codes, specified by the first arithmetic unit group circuit,
and to generate one or more operation instructions for the second arithmetic unit group circuit based on the second instruction
code, wherein

the first instruction code at least includes first and second specific instruction codes,
when the one or more operation instructions generated by the first arithmetic-control circuit include a first operation instruction
on a basis of the first specific instruction code, the first arithmetic unit group circuit is configured to set the second
instruction code to the fixed instruction register in accordance with the first operation instruction, and when the one or
more operation instructions generated by the first arithmetic-control circuit include a second operation instruction on a
basis of the second specific instruction code, the first arithmetic unit group circuit is configured to provide data to be
processed by the second arithmetic unit group circuit to the second arithmetic unit group circuit, and

the second arithmetic unit group circuit repeatedly executes operations on a basis of the one or more operation instructions
generated based on the second instruction code by the second arithmetic-control circuit,

wherein the first arithmetic unit group circuit and the second arithmetic unit group circuit have an identical but separate
configuration of the plurality of arithmetic units, such that the first arithmetic unit group circuit and the second arithmetic
unit group circuit have identical arithmetic units interconnected in the same manner.

US Pat. No. 9,263,561

SEMICONDUCTOR DEVICE AND AN ELECTRONIC DEVICE

Renesas Electronics Corpo...

1. A semiconductor device, comprising:
a semiconductor chip having a main surface, and a back surface opposite to the main surface, and having a first terminal on
the main surface side, and a second terminal on the back surface side; and

a metal plate electrically coupled to the first terminal of the semiconductor chip via a solder,
wherein the semiconductor chip includes:
a semiconductor substrate;
an interlayer insulation film formed over the semiconductor substrate;
a first conductive film pattern for the first terminal, formed over the interlayer insulation film;
an insulation film formed over the interlayer insulation film in such a manner as to cover the first conductive film pattern;
a first opening for the first terminal formed in the insulation film, and for exposing apart of the first conductive film
pattern; and

a first nickel film formed over the first conductive film pattern at a portion thereof exposed from the first opening,
wherein a semiconductor element for controlling the conduction between the first terminal and the second terminal is formed
at the semiconductor substrate,

wherein the first terminal is formed of the first conductive film pattern and the first nickel film,
wherein the first conductive film pattern is formed of a lamination film having a first conductor film containing aluminum
as a main component, and a second conductor film formed over the entire top surface of the first conductor film,

wherein the first nickel film is formed over the second conductor film at a portion thereof exposed from the first opening,
and

wherein the second conductor film is formed of a titanium film, a tungsten film, or a titanium tungsten film.

US Pat. No. 9,258,507

SOLID-STATE IMAGING APPARATUS

RENESAS ELECTRONICS CORPO...

1. A solid-state imaging apparatus comprising:
a pixel circuit to output an analog voltage having a level corresponding to an incident light quantity;
a reference voltage generation circuit to generate a reference voltage which has a ramp waveform;
a counter to generate a counter code by counting a main clock signal; and
an integral A/D converter to convert the analog voltage into a digital signal,
wherein the integral A/D converter includes:
a comparator to compare the reference voltage with the analog voltage; and
a latch circuit to latch the counter code based on a comparison result from the comparator when high-low relationship between
the reference voltage and the analog voltage reverses, and

wherein the counter includes:
a Johnson counter to generate first to Mth clock signals corresponding to the main clock signal, the first to Mth clock signals
each have a cycle equal to a cycle of the main clock signal multiplied by 2×M and a phase to shift from each other by the
cycle of the main clock signal;

a binary counter to generate a binary code by counting the first clock signal; and
a binary/gray converter to convert the binary code into the gray code,
wherein the second through Mth clock signals configure a low-order bit code of the counter code, and
wherein the gray code configure a high-order bit code of the counter code.

US Pat. No. 9,412,747

SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME

Renesas Electronics Corpo...

1. A method of manufacturing a semiconductor device having a non-volatile memory cell including a word line extending to a
first direction and a plurality of floating gates, comprising the steps of:
(a) forming a plurality of first insulating films and a plurality of first conductive films arranged between each of the first
insulating films over semiconductor substrate, wherein the first insulating films and the first conductive films extend in
a second direction being perpendicular to the first direction, and wherein the first insulating films cover sidewalls of the
first conductive films, respectively;

(b) after the step (a), recessing the first insulating films by using the first conductive films as a mask, thereby a height
of a top surface of the first insulating film is lower than a height of a top surface of the first conductive film, such that
the first insulating films respectively cover lower sidewall portions of the first conductive films and upper sidewall portions
of the first conductive films are exposed;

(c) after the step (b), forming a second insulating film over the first conductive films and the first insulating films, such
that the exposed upper sidewall portions of the first conductive films and upper surfaces of the first insulating films covering
the lower sidewall portions of the first conductive films are covered by the second insulating film;

(d) after the step (c), forming a second conductive film over the second insulating film; and
(e) after the step (d), patterning the second conductive film, the second insulating film and the first conductive films,
respectively,

wherein, by the step (e), the word line including the second conductive film is formed, and the floating gates including the
first conductive films are formed,

wherein, after the step (e), a length of the floating gates in the second direction is larger than a maximum length of the
floating gates in the first direction, and

wherein a protrusion height of the floating gates, which are covered by the second insulating film, from a top surface of
a portion of the second insulating film which is formed over the top surface of first insulating films, covering the lower
sidewall portions of the first conductive films forming the floating gates, to a top surface of the floating gates is larger
than a length of a space between the each of the floating gates in the first direction.