US Pat. No. 9,350,463

ELECTRONIC DEVICE, COMMUNICATION METHOD, AUDIO DEVICE AND AMPLIFIER DEVICE USING PULSE DENSITY MODULATION FOR COMMUNICATION

REALTEK SEMICONDUCTOR COR...

1. An electronic device using pulse density modulation for communication, comprising:
a pulse density modulation interface between a first circuit and a second circuit;
the first circuit to output a clock signal and a data signal to the second circuit through the pulse density modulation interface;
and

the second circuit to receive the clock and data signals from the first circuit through the pulse density modulation interface
and determine whether the level change times of the data signal reach a predetermined threshold while the clock signal remains
unchanged, so as to verify whether the clock and data signals conform to a start protocol,

wherein the predetermined threshold is equal to or more than three.

US Pat. No. 9,473,344

CIRCUIT AND METHOD FOR SETTING DATA AND THEIR APPLICATION TO INTEGRATED CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. An integrated circuit, comprising:
plural configuration pins that, when configured, establish a priority value assigned to the integrated circuit;
a storage unit;
a detecting circuit that receives the priority value from the configuration pins and stores the priority value in the storage
unit;

an interface circuit that receives plural PHY addresses in succession, wherein the plural PHY addresses include a first PHY
address and a second PHY address;

a determining circuit comprising:
a register;
a comparing circuit; and
a priority control circuit, wherein based on the priority value, the determining circuit stores the first PHY address in the
register, and based on receiving the second PHY address, the comparing circuit compares the first PHY address stored in the
register with the second PHY address and outputs a comparison result, wherein the priority control circuit receives the comparison
result and based on the priority value, determines:

if the first PHY address is equal to the second PHY address, the priority control circuit does not store the second PHY address;
and

if the first PHY address is not equal to the second PHY address, the priority control circuit stores the second PHY address
in the storage unit.

US Pat. No. 9,344,103

HIGH-RESOLUTION TIME-TO-DIGITAL CONVERTER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a rectifier configured to receive a first clock signal and a second clock signal and output a rectified signal, wherein the
second clock signal is the same as the first clock signal except for an offset in timing;

a low-pass filter configured to receive the rectified signal and output a filtered signal; and
an analog-to-digital converter configured to convert the filtered signal into a digital signal.

US Pat. No. 9,052,921

UNIVERSAL SERIAL BUS NETWORK INTERFACE CONTROLLER AND OPERATION MODE SWITCHING METHOD

REALTEK SEMICONDUCTOR COR...

1. An operation mode switching method for use in a network interface device, the network interface device being coupled to
a host, the operation mode switching method comprising the following steps of:
searching a wireless network access point within a communication range;
determining that the wireless network access point operates within an access point network band; and
determining to perform data transmission between the host and the network interface device in a second operation mode when
an operation frequency of a first operation mode interferes with the access point network band.

US Pat. No. 9,503,067

TIME SHIFTER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a first gated buffer configured to receive a first logical signal and output a second logical signal; a second gated buffer
configured to receive a third logical signal and output a delayed signal; and a finite state machine configured to receive
the delayed signal and a clock signal, wherein the first gated buffer is configured to be conditionally enabled in accordance
with a state of the finite state machine, while the second gated buffer is configured to be enabled regardless of the state
of the finite state machine.

US Pat. No. 9,521,691

WIRELESS COMMUNICATION DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A wireless communication device capable of adaptively permitting packet transmission, said wireless communication device
comprising:
a reception circuit operable to measure signal energy and generate a plurality of energy measurement values, and then to generate
a plurality of comparison results according to the energy measurement values and at least one threshold;

a control circuit, coupled to the reception circuit, operable to generate a transmission control signal according to the plurality
of comparison results or derived information of the comparison results; and

a transmission circuit, coupled to the reception circuit and the control circuit, operable to allow packet transmission according
to the comparison results if the transmission control signal indicates a normal state, and operable to allow packet transmission
if the transmission control signal indicates an abnormal state.

US Pat. No. 9,350,297

ACTIVE MIXER AND ACTIVE MIXING METHOD

REALTEK SEMICONDUCTOR COR...

1. An active mixer, comprising:
a voltage-to-current converting circuit operable to generate a conversion signal according to an input signal;
a switching circuit, coupled with the voltage-to-current converting circuit, operable to carry out a switching action according
to a clock signal and thereby electrically connect the voltage-to-current converting circuit with a load circuit;

the load circuit operable to provide an output signal for a first output node and a second output node according to the conversion
signal through the switching action;

a first supplement current source, coupled between a first voltage and a first node between the switching circuit and the
first output node, operable to supply a first supplemental current to the switching circuit; and

a second supplement current source, coupled between a second voltage and a second node between the switching circuit and the
second output node, operable to supply a second supplemental current to the switching circuit,

each of the first and second voltages is higher than a working voltage of the load circuit.

US Pat. No. 9,345,101

PROTECTION CIRCUIT FOR USE IN CONTROLLING INTEGRATED CIRCUIT OF LIGHT EMITTING DIODE

Realtek Semiconductor Cor...

1. A protection circuit for use in a controlling integrated circuit (IC) of a light emitting diode (LED), comprising:
a voltage division circuit, being coupled to a terminal of an LED assembly, and configured to generate a division voltage
according to a terminal voltage of the terminal; and

a voltage reduction circuit, being coupled to the voltage division circuit, and configured to reduce the division voltage
of the voltage division circuit;

a detection circuit, being coupled to the voltage division circuit and the voltage reduction circuit, and configured to generate
a detection signal according to the division voltage;

wherein the voltage division circuit is disposed outside the controlling IC of the LED, the voltage reduction circuit is disposed
in the controlling IC of the LED, the voltage reduction circuit is configured to reduce the division voltage of the voltage
division circuit according to the detection signal, and the detection circuit is disposed in the controlling IC of the LED.

US Pat. No. 9,438,453

METHOD AND CIRCUIT FOR ESTABLISHING NETWORK CONNECTION

REALTEK SEMICONDUCTOR COR...

1. A circuit for establishing network connection, capable of preventing a link procedure from being strangled in a training
state, comprising a physical layer circuit (PHY), a counting unit operable to count a number during the training state and
make the PHY return to a Slave Silent step of BroadR-Reach technology if a local receiver is not ready after finishing counting
the number, and all of the following units:
a detecting unit operable to detect a reception signal according to a signal detection level during the training state, and
make the PHY return to the Slave Silent step if none of the reception signal is detected;

a determining unit operable to determine a number of level(s) of the reception signal during the training state, and make
the PHY return to the Slave Silent step if the number of level(s) is less than an expected level number; and

a comparing unit operable to compare a signal-to-noise ratio of the reception signal with a signal-to-noise threshold during
the training state, and make the PHY return to the Slave Silent step if the signal-to-noise ratio fails to satisfy the signal-to-noise
threshold.

US Pat. No. 9,439,014

MICROPHONE DETECTION AND SELECTION CIRCUIT AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A microphone detection circuit for detecting whether an external device includes a microphone, comprising:
an audio circuit for receiving an analog input signal which is a signal from the external device or a preset signal, the audio
circuit including:

at least one analog-to-digital conversion unit to generate a digital audio signal according to the analog input signal;
a decision unit, coupled to the analog-to-digital conversion unit, to determine whether the digital audio signal satisfies
a predetermined threshold to thereby generate an analysis result, wherein if the digital audio signal satisfies the predetermined
threshold, the analysis result indicates that the external device includes the microphone; and

a control unit, coupled to the decision unit, to control an operation of the audio circuit according to the analysis result,
wherein when the external device includes the microphone, the analog input signal is the signal generated by the microphone
and the digital audio signal generated according to the analog input signal has a value varying by time to reflect human voice
or background sound, and then the decision unit determines that the digital audio signal satisfies the predetermined threshold;
and when the external device includes no microphone, the analog input signal is the preset signal and the digital audio signal
generated according to the analog input signal is a constant value, and then the decision unit determines that the digital
audio signal fails to satisfy the predetermined threshold.

US Pat. No. 9,350,317

EMI SUPPRESSION DEVICE AND METHOD FOR NETWORK TRANSMISSION

REALTEK SEMICONDUCTOR COR...

1. An electromagnetic interference (EMI) suppression device for network transmission, comprising:
a first transformer including a first circuit-end central tap operable to receive a first circuit signal from two first circuit-end
signal taps, and a first cable-end central tap operable to receive a first cable signal from two first cable-end signal taps;

a second transformer including a second circuit-end central tap operable to receive a second circuit signal from two second
circuit-end signal taps, and a second cable-end central tap operable to receive a second cable signal from two second cable-end
signal taps;

a first circuit-end inductance element, coupled between the first circuit-end central tap and a system ground, operable to
reduce the common mode noise of the first circuit signal; and

a second circuit-end inductance element, coupled between the second circuit-end central tap and the system ground, operable
to reduce the common mode noise of the second circuit signal,

wherein the first and second circuit-end inductance elements are independent of each other and operate separately.

US Pat. No. 9,135,980

MEMORY CONTROL CIRCUIT AND METHOD OF CONTROLLING DATA READING PROCESS OF MEMORY MODULE

REALTEK SEMICONDUCTOR COR...

1. A memory control circuit, for controlling a data reading process of a memory module, during which the memory module transmitting
a data signal and a data strobe signal that is used to recover the data signal to the memory control circuit, the data strobe
signal comprising a preamble part, and the memory control circuit comprising:
a clock generating circuit for generating a clock;
a control unit coupled to the memory module and the clock generating circuit for controlling an impedance matching circuit
of the memory module and generating an enabling signal according to the clock; and

a sampling circuit coupled to the control unit for sampling the data strobe signal according to the enabling signal to generate
a sampling result;

wherein, the control unit first control the impedance matching circuit to make the data strobe signal keep at a fixed level
before the preamble part and then controls the sampling circuit to sample the data strobe signal according to the enabling
signal, and adjusts an enabling time of the enabling signal according to the sampling result and starts the process of recovering
the data signal according to the enabling signal.

US Pat. No. 9,479,863

COMBO-JACK DETECTING CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. A combo-jack detecting circuit for use in an audio codec, connecting with an audio apparatus electrically, the audio apparatus
comprising a first terminal and a second terminal, the combo-jack detecting circuit comprising:
a switch unit, being coupled to the first terminal and the second terminal, and selectively switching to output a first voltage
signal of the first terminal or a second voltage signal of the second terminal;

a detecting unit, being coupled to the switch unit to receive the first voltage signal and the second voltage signal, and
determining a jack type of the audio apparatus according to the first voltage signal and the second voltage signal;

a low pass filter, being coupled between the switch unit and the detecting unit; wherein the low pass filter receives the
first voltage signal and the second voltage signal via the switch unit and provides a first direct current signal of the first
voltage signal and a second direct current signal of the second voltage signal respectively, and the detecting unit determines
the jack type of the audio apparatus according to the first direct current signal and the second direct current signal; and

a first stage buffer, having a first input terminal, a second input terminal, a first output terminal and a second output
terminal, wherein the first input terminal of the first stage buffer is coupled between the switch unit and the low pass filter
to receive the second voltage signal, the second input terminal of the first stage buffer is coupled between the low pass
filter and the detecting unit to receive the second direct current signal, the first output terminal and the second output
terminal of the first stage buffer respectively output a first alternating current signal corresponding to the second voltage
signal and a second alternating current signal corresponding to the second direct current signal, and phases of the first
alternating current signal and the second alternating current signal are opposite.

US Pat. No. 9,479,150

SELF-CALIBRATING MULTI-PHASE CLOCK CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a phase tuning circuit configured to receive a primitive N-phase clock comprising N primitive clocks of the same period but
distinct phases and output a calibrated N-phase clock comprising N calibrated clocks in accordance with a first tuning signal,
where N is an integer greater than one;

a clock multiplexing circuit configured to receive the N calibrated clocks and output a first output clock and a second output
clock in accordance with a multiplexing control signal;

a time-to-digital converter configured to receive the first output clock and the second output clock and output a digital
code; and

a calibration controller configured to receive the digital code and output the first tuning signal in accordance with a mode
select signal.

US Pat. No. 9,419,572

AUDIO DEVICE AND AUDIO UTILIZATION METHOD HAVING HAPTIC COMPENSATION FUNCTION

REALTEK SEMICONDUCTOR COR...

1. An audio device for compensating a haptic effect according to a power measuring result and an audio signal, comprising:
an audio signal generating circuit configured to generate the audio signal;
a power measuring circuit configured to measure a remaining electric quantity of a power source and thereby generate the power
measuring result; and

a haptic compensating circuit, coupled to the audio signal generating circuit and the power measuring circuit, configured
to adjust a gain of the audio signal or the derived signal thereof according to the power measuring result and thereby output
a haptic compensation signal which is used to compensate the haptic effect.

US Pat. No. 9,385,760

WIRELESS SIGNAL RECEIVING DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A wireless signal receiving device capable of receiving three or more signals of different central frequencies, comprising:
a receiving circuit operable to generate a reception signal according to a wireless signal including a first, second and third
wireless signals of different central frequencies;

a mixer operable to generate a mixing signal by processing the reception signal according to a local oscillation clock in
which the mixing signal includes a first, second and third intermediate-frequency (IF) signals related to the first, second
and third wireless signals in turn while the maximum frequency of the third IF signal is higher than the maximum frequency
of the first and second IF signals;

a digital signal generating circuit including:
a first digital signal generating path operable to process at least one of the in-phase and quadrature-phase parts of the
mixing signal according to the central frequency and bandwidth of the first IF signal and a first sampling frequency, and
thereby generate a first digital signal;

a second digital signal generating path operable to process at least one of the in-phase and quadrature-phase parts of the
mixing signal according to the central frequency and bandwidth of the second IF signal and a second sampling frequency, and
thereby generate a second digital signal; and

a third digital signal generating path operable to process at least one of the in-phase and quadrature-phase parts of the
mixing signal according to the central frequency and bandwidth of the third IF signal and a third sampling frequency, and
thereby generate a third digital signal, wherein the third sampling frequency is lower than the double of the maximum frequency
of the third IF signal; and

a control circuit coupled with the digital signal generating circuit, operable to turn off some or all of at least one of
the first, second and third digital signal generating paths according to a prescribed condition.

US Pat. No. 9,519,952

IMAGE PROCESSING APPARATUS AND METHOD

REALTEK SEMICONDUCTOR COR...

1. An image processing apparatus, comprising:
a gradient calculation unit configured to perform an operation on an input image to generate gradient magnitudes and gradient
angles respectively associated with a plurality of input pixels of the input image;

a direction determining unit configured to generate a plurality of interpolation angles and a plurality of directional confidence
values according to the gradient magnitudes and the gradient angles associated with the input pixels;

a directional interpolation unit configured to perform directional interpolation on the input image according to the interpolation
angles, so as to generate a first image with an image resolution different from that of the input image; and

a blender unit configured to receive the first image and a second image generated from interpolating the input image, and
configured to blend the first image and the second image into an output image according to weights of the first image and
the second image associated with the directional confidence values, wherein the resolution of the second image is the same
as that of the first image.

US Pat. No. 9,373,508

SEMICONDUCTOR DEVICE AND FABRICATING METHOD THEREOF

Realtek Semiconductor Cor...

1. A semiconductor device, being formed on a substrate and comprising:
a first first-type metal-oxide-semiconductor field effect transistor (MOSFET), having a first gate structure, a first source
area, a first drain area, and two first pocket implant areas formed on the substrate; and

a second first-type MOSFET, having a second gate structure, a second source area, and a second drain area, and two second
pocket implant areas formed on the substrate;

wherein a first pocket implant process is applied to the first first-type MOSFET via a first photomask to form the two first
pocket implant areas, a second pocket implant process is applied to the second first-type MOSFET via a second photomask to
form the two second pocket implant areas, and a direction of the first gate structure and a direction of the second gate structure
are different.

US Pat. No. 9,504,045

BLUETOOTH SERVICE ESTIMATION APPARATUS AND BLUETOOTH SERVICE ESTIMATION METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A Bluetooth service estimation method for a Bluetooth service estimation apparatus, the Bluetooth service estimation apparatus
being disposed in a Bluetooth controller, and electrically connected with a Wi-Fi host and a Bluetooth host, the Bluetooth
service estimation method comprising the following steps:
(a) detecting, by the Bluetooth service estimation apparatus, a plurality of data packets transmitted between the Bluetooth
host and a remote Bluetooth device, wherein the plurality of data packets comprises a service packet transmitted from the
remote Bluetooth device to the Bluetooth host;

(b) determining, by the Bluetooth service estimation apparatus, a Bluetooth service type between the Bluetooth host and the
remote Bluetooth device according to contents of the plurality of data packets; and

(c) transmitting, by the Bluetooth service estimation apparatus, the Bluetooth service type to the Wi-Fi host so that the
Wi-Fi host determines a weight of network resources according to the Bluetooth service type and decides a utilization rate
of an antenna according to the weight of the network resources;
wherein step (b) comprises:
(i) determining, by the Bluetooth service estimation apparatus, whether the service packet transmitted between the Bluetooth
host and the remote Bluetooth device is an asynchronous connectionless (ACL) packet according to a data type bit of the service
packet;

(ii) determining, by the Bluetooth service estimation apparatus, that the Bluetooth service type is an ACL service if the
service packet transmitted between the Bluetooth host and the remote Bluetooth device is the ACL packet;

(iii) accumulating, by the Bluetooth service estimation apparatus, a plurality of ACL data packets transmitted between the
Bluetooth host and the remote Bluetooth device if the service estimator determines that the Bluetooth service type is the
ACL service;

(iv) determining, by the Bluetooth service estimation apparatus, that a total data amount of the plurality of ACL data packets
exceeds a data threshold value within a fixed time period; and

(v) determining, by the Bluetooth service estimation apparatus, that the ACL service is one of a Personal Area Network (PAN)
service, a File Transfer Profile (FTP) service and an Object Push Profile (OPP) service if the total data amount of the plurality
of ACL data packets exceeds the data threshold value within the fixed time period.

US Pat. No. 9,136,863

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND CONVERSION METHOD

REALTEK SEMICONDUCTOR COR...

1. A successive approximation analog-to-digital converter capable of determining the sampling value of an input signal, comprising:
a first capacitor array operable to sample a first input signal under a sampling mode, including a plurality of first capacitors
which include at least a first designated capacitor and at least a first sampling capacitor while each of the first capacitors
includes a first upper electrode terminal and a first lower electrode terminal;

a comparator operable to compare a first voltage from the first capacitor array with a second voltage under a comparison mode
and thereby generate a comparison result;

a first switching circuit, coupled with the first capacitor array, operable to determine the charge amount stored in the first
capacitor array according to a first control signal under the sampling mode and determine the first voltage outputted from
the first capacitor array according to the first control signal under the comparison mode; and

a control circuit, coupled with the comparator and the first switching circuit, operable to generate the first control signal
according to a sampling setting under the sampling mode and generate the first control signal according to the comparison
result under the comparison mode,

wherein the first control signal is operable to prevent the at least one first designated capacitor from sampling the first
input signal through the first switching circuit under the sampling mode while making the at least one first sampling capacitor
sample the first input signal, and operable to stop the first capacitor array from sampling through the first switching circuit
under the comparison mode while making the at least one first designated capacitor and the least one first sampling capacitor
share charges.

US Pat. No. 9,496,883

CHIP AND CALIBRATION METHOD THEREOF

Realtek Semiconductor Cor...

1. A chip, comprising:
an analog-to-digital converter;
a memory unit configured to store a look up table, wherein the look up table is configured to store a plurality of first digital
code differences, and is configured to be calibrated according to a variation parameter, wherein the first digital code differences
are generated, according to a first predetermined voltage and a second predetermined voltage, by the analog-to-digital converter
at a plurality of gains respectively; and

a digital-to-analog converter configured to generate the first predetermined voltage and the second predetermined voltage
and output the same to the analog-to-digital converter to measure a second digital code difference generated by the analog-to-digital
converter at a first gain among the plurality of the gains;

wherein the variation parameter is a ratio of the second digital code difference and one of the first digital code differences.

US Pat. No. 9,269,674

INTEGRATED CIRCUIT HAVING ELECTROMAGNETIC SHIELDING CAPABILITY AND MANUFACTURING METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An integrated circuit having electromagnetic shielding capability, comprising:
a semiconductor circuit structure including a first surface which covers an electromagnetic radiation area;
an electromagnetic shielding layer covering the first surface and including at least one contact; and
at least one conducting path operable to electrically connect the at least one contact with a steady voltage and thereby shield
off the electromagnetic wave from the electromagnetic radiation area,

wherein the current running through the electromagnetic shielding layer is zero or less than the maximum current running through
the electromagnetic radiation area.

US Pat. No. 9,131,200

WHITE BALANCE ADJUSTING METHOD WITH SCENE DETECTION AND DEVICE THEREOF

REALTEK SEMICONDUCTOR COR...

1. A white balance adjusting method with scene detection carried out by a white balance adjusting device, comprising:
receiving source image data corresponding to a plurality of sensing units;
generating an initial white balance gain according to the source image data;
generating at least one image parameter corresponding to a plurality of parameter elements according to the source image data,
wherein the at least one image parameter includes at least one of a brightness parameter, a chrominance parameter and a texture
parameter;

determining whether at least one preset condition is satisfied according to the at least one image parameter, and thereby
generating a decision result, wherein the step of generating the decision result includes:

determining whether an element number or a percentage of the parameter elements in compliance with a predetermined color is
higher than a predetermined threshold according to the chrominance parameter to thereby generate a chrominance decision result;

determining whether an average or weighted brightness value of the parameter elements in compliance with the predetermined
color is higher or lower than a predetermined brightness value according to the brightness parameter to thereby generate a
brightness decision result; and

generating the decision result according to the chrominance decision result and the brightness decision result;
determining whether the source image data are associated with any of built-in scenes and/or an association between the source
image data and the built-in scenes according to the decision result in which the built-in scenes include a first scene in
connection with a first-scene adjustment rule; and

if the source image data are associated with the first scene, adjusting the initial white balance gain or processing the source
image data according to the first-scene adjustment rule to thereby obtain a scenic white balance gain and adjust the source
image data with the scenic white balance gain.

US Pat. No. 9,883,590

SHIELDING STRUCTURE FOR INTEGRATED INDUCTOR/TRANSFORMER

REALTEK SEMICONDUCTOR COR...

1. A shielding structure for integrated inductor/transformer, used in an inductor or a transformer, configured under the inductor
or the transformer and upon a substrate, comprising:
a plurality of conductive units, comprising a first conductive unit, a second conductive unit, a third conductive unit and
a fourth conductive unit, each conductive unit comprising a first conductive sub-unit and a second conductive sub-unit, both
of the first conductive sub-unit and the second conductive sub-unit comprising a first conductive portion and a plurality
of second conductive portions extending from the first conductive portion, the number of the second conductive portions being
odd, the length of each second conductive portion progressively diminishing along the first conductive portion, wherein the
longest second conductive portion of the first conductive sub-unit and the longest second conductive portion of the second
conductive sub-unit are connected;

a plurality of first connecting portions, configured to connect the first conductive unit and the second conductive unit and
to connect the third conductive unit and the fourth conductive unit; and

a grounding portion;
wherein the first conductive portion of the first conductive sub-unit of the first conductive unit is connected to the first
conductive portion of the second conductive sub-unit of the fourth conductive unit and the grounding portion is connected
to where these two first conductive portions are connected, or the first conductive portion of the second conductive sub-unit
of the second conductive unit is connected to the first conductive portion of the first conductive sub-unit of the third conductive
unit and the grounding portion is connected to where these two first conductive portions are connected.

US Pat. No. 9,059,833

DATA RECEIVING DEVICE AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A data receiving device for identifying a transmission mode of a data signal, comprising:
a clock generating circuit for generating a first reference clock according to a source clock;
a phase detector for generating a phase detection signal according to the data signal and a data recovery clock;
a phase adjusting circuit, coupled to the clock generating circuit and the phase detector, for adjusting a phase of the first
reference clock according to the phase detection signal to generate the data recovery clock and outputting the data recovery
clock to the phase detector and generating a second reference clock according to the phase detection signal and the first
reference clock, the second reference clock and the data recovery clock having the same frequency and a phase difference;

a mode detector, coupled to the phase adjusting circuit, for detecting the transmission mode according to the second reference
clock and the data signal and generating a mode signal accordingly; and

a control circuit, coupled to the mode detector and the clock generating circuit, for determining whether to control the clock
generating circuit to change the frequency of the first reference clock or not according to the mode signal.

US Pat. No. 9,287,841

GAIN CONTROL CIRCUIT AND METHOD CAPABLE OF EASING LEAKAGE CURRENT INFLUENCE

REALTEK SEMICONDUCTOR COR...

1. A gain control circuit capable of easing leakage current influence, comprising:
at least one signal input end operable to receive at least one input signal;
a signal output end operable to output an output signal;
an amplifier coupled between an amplifier input end and the signal output end; and
a plurality of gain schemes, each of which is set between the at least one signal input end and the signal output end, including:
a first gain scheme including:
a first node;
a first signal path operable to electrically connect or disconnect the at least one signal input end with or from the amplifier
input end through the first node according to a first control signal; and

a first grounding path operable to electrically connect or disconnect the first node with or from a reference voltage end
according to the inversion of the first control signal, and especially operable to disconnect the first node from the reference
voltage end when the first signal path electrically connects the at least one signal input end with the amplifier input end
through the first node; and

a second gain scheme including:
a second node;
a second signal path operable to electrically connect or disconnect the at least one signal input end with or from the amplifier
input end through the second node according to a second control signal; and

a second grounding path operable to electrically connect or disconnect the second node with or from the reference voltage
end according to the inversion of the second control signal, and especially disconnect the second node from the reference
voltage end when the second signal path electrically connects the at least one signal input end with the amplifier input end
through the second node.

US Pat. No. 9,160,575

DISCRETE-TIME LINEAR EQUALIZER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An equalizer comprising:
a first switch sampling an input signal at a first phase of a clock to output a first sampled signal;
a first buffer receiving the first sampled signal and outputting a held signal;
a second switch sampling the held signal at a second phase of the clock to output a second sampled signal;
a second buffer receiving the second sampled signal and outputting an output signal; and
a capacitor providing a capacitive coupling between the held signal and the output signal.

US Pat. No. 9,407,234

CURRENT BALANCING DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A current balancing device capable of balancing an output current and an input current of a current loop, comprising:
a transmission circuit including an output end and an input end operable to output the output current and receive the input
current respectively;

at least one adjustable resistor set in the current loop, operable to provide resistance according to at least one adjustment
signal; and

a current balancing circuit, coupled to the transmission circuit and the at least one adjustable resistor, operable to determine
whether the difference between the output and input currents satisfies a predetermined requirement in light of a predetermined
duration and thereby generate the at least one adjustment signal,

wherein if the difference between the output and input currents fails to satisfy the predetermined requirement, the current
balancing circuit is operable to adjust the resistance of the at least one adjustable resistor through the at least one adjustment
signal, so as to reduce the difference between the output and input currents.

US Pat. No. 9,386,613

WIRELESS NETWORK SYSTEM AND CONNECTING METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A connecting method for use in a wireless network system, the wireless network system comprising a Wi-Fi apparatus and
a communication apparatus, and the Wi-Fi apparatus possessing a connection password, the connecting method comprising the
following steps of:
(a) enabling the Wi-Fi apparatus to provide a Service Set Identifier (SSID), wherein the SSID comprises a first identifier
value and a second identifier value, and the second identifier value is derived from the first identifier value by a hash
function;

(b) enabling the communication apparatus to search the SSID of the Wi-Fi apparatus;
(c) enabling the communication apparatus to determine that a value derived from the first identifier value of the SSID by
the hash function is equal to the second identifier value;

(d) enabling the communication apparatus to generate the connection password and establish a Wi-Fi authenticating connection
with the Wi-Fi apparatus according to the connection password;

(e) enabling the Wi-Fi apparatus to determine that the communication apparatus is legal according to the Wi-Fi authenticating
connection; and

(f) enabling the communication apparatus to establish a data transmission connection with the Wi-Fi apparatus.

US Pat. No. 9,471,542

PARAMETER GENERATING DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

9. A parameter generating method carried out by a parameter generating device and operable to generate a parameter for circuit
operation, in which the parameter is associated with an N degree polynomial of a characteristic curve while the N is a positive
integer and the parameter is based on a physical condition, the parameter generating method comprising the following steps:
providing at least N+1 initial values by a storage circuit, in which the at least N+1 initial values are determined in accordance
with a start value and a unit variation amount;

executing addition calculation for at least [(K?1)×N+1] time(s) by a parameter calculating circuit if a multiple K is positive
or executing subtraction calculation for at least ?K×N time(s) by the parameter calculating circuit if the multiple K is negative,
so as to generate the parameter;

approximating the N degree polynomial to a target polynomial according to a correlation by an operation circuit to thereby
obtain each coefficient of the correlation; and

calculating a target parameter of the target polynomial according to the correlation and the parameter by the operation circuit,
wherein the multiple K is derived from a difference divided by the unit variation amount while the difference is a current
value minus the start value.

US Pat. No. 9,386,517

ENERGY EFFICIENT NETWORK COMMUNICATION DEVICE AND METHOD

Realtek Semiconductor Cor...

17. An energy efficient network communication method, which is carried out by an energy efficient network communication device,
comprising:
entering an idle mode from a normal mode;
generating a transmission-end lower power idle indication (TX-LPI indication);
generating a transmission-end lower power idle signal (TX-LPI signal) according to the TX-LPI indication;
converting the TX-LPI signal into a transmission signal with at least the following sub-steps:
generating a transmission-bit conversion signal according to the TX-LPI signal in which the bit number of the TX-LPI signal
is different from the bit number of the transmission-bit conversion signal;

generating a plurality of transmission-end encryption bits according to the transmission-bit conversion signal and performing
a logic operation with at least some of the transmission-end encryption bits to generate a transmission-end encryption signal;
and

generating the transmission signal according to the transmission-end encryption signal;
using at least one of several pairs of transmission lines to output the transmission signal to a reception end for asking
the reception end to enter a lower power idle mode (LPI mode) when keeping at least another one of the several pairs of transmission
lines unused;

using the at least one of the several pairs of transmission lines to receive a reception signal from the reception end when
keeping the at least another one of the several pairs of transmission lines unused;

converting the reception signal into a reception-end low power idle signal (RX-LPI signal) with at least the following sub-steps:
generating a reception-end encryption signal according to the reception signal;
generating a plurality of reception-end encryption bits according to the reception-end encryption signal and performing a
comparison operation with at least some of the reception-end encryption bits to generate a reception-bit conversion signal;
and

generating the RX-LPI signal according to the reception-bit conversion signal in which the bit number of the RX-LPI signal
is different from the bit number of the reception-bit conversion signal; and

after outputting the transmission signal and/or receiving the RX-LPI signal, entering the LPI mode from the idle mode for
power saving,

wherein the power consumption under the normal mode is higher than the power consumption under the idle mode while the power
consumption under the idle mode is higher than the power consumption under the LPI mode.

US Pat. No. 9,313,467

PIXEL VALUE CALIBRATION DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A pixel value calibration device operable to calibrate the pixel value of a target pixel, comprising:
an edge detecting unit operable to generate a plurality of edge detection values according to the pixel value of the target
pixel and the pixel values of several neighboring pixels in which the target and neighboring pixels are of a first color and
each of them is arranged with several pixels of a second color in the same row of a pixel array;

a weighted value estimating unit operable to generate a plurality of weighted values according to the edge detection values
and a predetermined algorithm in which the weighted values are associated with a plurality of candidate pixels while each
of the candidate pixels is arranged with several pixels of a third color in the same row of the pixel array;

a calibration value generating unit operable to generate a calibration value according to the pixel value of the target pixel
and the pixel value(s) of some or all of the candidate pixels plus the weighted value(s) corresponding thereto; and

a calibrating unit operable to generate a calibrated pixel value of the target pixel according to the pixel value of the target
pixel and the calibration value.

US Pat. No. 9,294,124

DICTIONARY-BASED COMPRESSION METHOD, DICTIONARY-BASED DECOMPRESSION METHOD AND DICTIONARY COMPOSING METHOD

REALTEK SEMICONDUCTOR COR...

1. A dictionary-based compression method comprising the following steps:
receiving digital data including a plurality of data blocks by a micro controller unit (MCU), wherein each of the data blocks
includes a plurality of data units, and each of the data units includes a plurality of bits;

compressing the digital data and generating compressed digital data according to a multilayer dictionary-based compression
algorithm by the MCU, in which the multilayer dictionary-based compression algorithm includes a first dictionary-based compression
algorithm, a second dictionary-based compression algorithm and a third dictionary-based compression algorithm, wherein the
first dictionary-based compression algorithm is operable to execute compression to a first content of the digital data by
a unit range of N data blocks, the second dictionary-based compression algorithm is operable to execute compression to a second
content of the digital data by a unit range of M data blocks, and the third dictionary-based compression algorithm is operable
to execute compression to a third content of the digital data by a unit range of L data block(s), in which the first, second
and third contents are different, each of N, M, L is a positive integer not greater than a number of the plurality of data
blocks, N is greater than M, and M is greater than L; and

storing the compressed digital data in a memory circuit.

US Pat. No. 9,252,758

MULTI-PHASE PHASE INTERPOLATOR

REALTEK SEMICONDUCTOR COR...

1. A multi-phase phase interpolator having a plurality of voltage-mode phase interpolators, the multi-phase interpolator receiving
a first input clock and a second input clock to generate a plurality of equally spaced output clocks, the first input clock
leading the second input clock, a first voltage-mode phase interpolator in the plurality of voltage-mode phase interpolators
being configured to generate a first output clock in the plurality of output clocks, the first voltage-mode phase interpolator
comprising:
a first circuit branch configured to be controlled by the first input clock, the first circuit branch comprising a first sub-branch
and a second sub-branch, the first sub-branch of the first circuit branch comprising a first transistor in series with a first
resistor, the second sub-branch of the first circuit branch comprising a second transistor in series with a second resistor,
the first transistor and the second transistor being coupled to the first input clock such that the first transistor is ON
when the second transistor is OFF and vice versa, the first sub-branch of the first circuit branch being configured such that
current flows through the first resistor and the first transistor when the first transistor is ON, the second sub-branch of
the first circuit branch being configured such that current flows through the second resistor and the second transistor when
the second transistor is ON, a terminal of the first transistor and a terminal of the second transistor being coupled together
to an output node of the first voltage-mode phase interpolator; and

a second circuit branch configured to be controlled by the second input clock, the second circuit branch comprising a first
sub-branch and a second sub-branch, the first sub-branch of the second circuit branch comprising a third transistor in series
with a third resistor, the second sub-branch of the second circuit branch comprising a fourth transistor in series with a
fourth resistor, the third transistor and the fourth transistor being coupled to the second input clock such that the third
transistor is ON when the fourth transistor is OFF and vice versa, the first sub-branch of the second circuit branch being
configured such that current flows through the third resistor and the third transistor when the third transistor is ON, the
second sub-branch of the second circuit branch being configured such that current flows through the fourth resistor and the
fourth transistor when the fourth transistor is ON, a terminal of the third transistor and a terminal of the fourth transistor
being coupled together to the output node of the first voltage-mode phase interpolator.

US Pat. No. 9,236,919

MIMO WIRELESS COMMUNICATION METHOD AND SYSTEM

REALTEK SEMICONDUCTOR COR...

24. A multiple-input multiple-output (MIMO) wireless communication system, comprising:
a first wireless communication device possessing a transmission opportunity to passively start a joint transmission by issuing
a distributed MIMO initiation frame and receiving an initial portion from a second wireless communication device, or actively
start the joint transmission by issuing the distributed MIMO initiation frame and the initial portion thereafter, or actively
start the joint transmission by issuing a distributed MIMO invitation frame and issuing the initial portion; and

the second wireless communication device running after the transmission opportunity to participate in the joint transmission
by accepting the joint transmission offer from the distributed MIMO initiation frame and issuing the initial portion, or by
accepting the joint transmission offer from the distributed MIMO initiation frame and receiving the initial portion from the
first wireless communication device, or by accepting the joint transmission offer from the distributed MIMO invitation frame
and receiving the initial portion from the first wireless communication device,

wherein the distributed MIMO initiation or invitation frame includes a first number of transmission spatial stream(s) of the
first wireless communication device and a first number of reception spatial streams which a first receiver in connection with
the first wireless communication device is operable to process, and the joint transmission allows the first and second wireless
communication devices to transmit distributed MIMO packets concurrently provided that the sum of the first number of transmission
spatial stream(s) and a second number of transmission spatial stream(s) of the second wireless communication device is equal
to or less than the first number of reception spatial streams.

US Pat. No. 9,157,957

PLL STATUS DETECTION CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A phase lock loop (PLL) status detection circuit for detecting a clock generated by a PLL of a chip to determine a status
of the PLL, comprising:
a counter, configured to generate a count value by counting a number of cycles of the clock according to a control signal
to;

a status analyzing circuit, coupled to the counter, configured to analyze the count value according to the control signal
to generate an analyzed result; and

a status storing circuit, coupled to the status analyzing circuit, configured to store the analyzed result;
wherein the status storing circuit is coupled to a scan chain of the chip, and the analyzed result is transmitted via the
scan chain.

US Pat. No. 9,471,498

MEMORY CARD ACCESS DEVICE, CONTROL METHOD THEREOF, AND MEMORY CARD ACCESS SYSTEM

REALTEK SEMICONDUCTOR COR...

1. A memory card access device comprising:
a memory card interface circuit to receive a card-read signal from a memory card or output a card-writing signal to the memory
card, including:

a card signal processing unit operable to generate card-read data according to the card-read signal or generate the card-writing
signal according to card-writing data;

a host interface circuit to receive a host-read signal from a host or output a host-writing signal to the host, including:
a host signal processing unit operable to generate host-read data according to the host-read signal or generate the host-writing
signal according to host-writing data; and

a control circuit, coupled to the card and host signal processing units, operable to execute at least the following operation:
a protocol operation to generate the host-writing data by processing the card-read data according to a predetermined cache
protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol,
so as to treat the memory card as a cache device of the host,

wherein the predetermined cache protocol is the Advance Host Controller Interface (AHCI) protocol or the Non-Volatile Memory
Express (NVM-Express) protocol, and when the card-read data is composed of several pieces of data of small size, the control
circuit is operable to generate the host-writing data according to the card-read data at an average rate more than 10 Mbyte
per second while the size of each of the several pieces of data is equal to or less than 4 Kbyte.

US Pat. No. 9,473,962

WIRELESS TRANSMISSION RATE ADJUSTMENT METHOD

REALTEK SEMICONDUCTOR COR...

1. A wireless transmission rate adjustment method to adjust the wireless transmission rate of a wireless transmission device
which is capable of selecting one of several transmission rates to transmit data in which at least one of the several transmission
rates corresponds to multiple transmission modes including a first transmission mode and a second transmission mode, comprising:
having the wireless transmission device enter a try state from a normal state in which the wireless transmission device transmits
data at an original transmission rate before entering the try state;

under the try state, having the wireless transmission device transmit one or more test packets according to a first modulation
and coding scheme (MCS), and determining whether the wireless transmission device transmits the one or more test packets successfully
according to a predetermined condition;

if the transmission of the one or more test packets is successful with the first MCS, having the wireless transmission device
return to the normal state and transmit data with the first MCS;

if the transmission of the one or more test packets is unsuccessful with the first MCS, having the wireless transmission device
transmit another one or more test packets according to a second MCS in the try state, and determining whether the wireless
transmission device transmits the another one or more test packets successfully in accordance with the predetermined condition;

if the transmission of the another one or more test packets is successful with the second MCS, having the wireless transmission
device return to the normal state and transmit data with the second MCS; and

if the transmission of the another one or more test packets is failed with the second MCS, having the wireless transmission
device return to the normal state and transmit data at the original transmission rate or with the first MCS,

wherein at least one of the transmission rates of the first MCS and the second MCS is different from the original transmission
rate, the first MCS corresponds to the first transmission mode while the second MCS corresponds to the second transmission
mode, and if the transmission rate of the first MCS is higher than the original transmission rate, the first transmission
mode is a multiple spatial stream mode and the second transmission mode is a single spatial stream mode.

US Pat. No. 9,430,812

IMAGE PROCESSING METHOD, IMAGE OUTPUT PROCESSING METHOD, AND IMAGE RECEPTION PROCESSING METHOD

REALTEK SEMICONDUCTOR COR...

1. An image processing method carried out by an image processing system which includes an image output device, a transmission
interface and an image reception device, comprising:
using the image output device to generate a scale-down image according to a source image in which the scale-down image has
the size smaller than the size of the source image;

using the image output device to generate a plurality of divided images of the same size according to the scale-down image
in which each of the divided images has the size smaller than the size of the scale-down image;

using the image output device to compress the divided images so as to generate a plurality of encoded image;
using the image output device to output the plurality of encoded images to the image reception device through the transmission
interface;

using the image reception device to decompress the plurality of encoded images to recover the plurality of divided images;
and

using the image reception device to generate a display image according to the plurality of divided images in which the display
image has the size larger than the size of any of the divided images.

US Pat. No. 9,407,277

SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER AND CONVERSION METHOD

REALTEK SEMICONDUCTOR COR...

1. A successive approximation analog-to-digital converter capable of improving the accuracy of analog-to-digital conversion,
comprising:
a successive approximation analog-to-digital converting circuit operable to generate M bits according to an analog input signal
in which the M bits include a most significant bit (MSB) and successive M?1 bit(s) in succession to the MSB while M is an
integer greater than one; and

a multibit generating circuit including:
an accumulation signal generating circuit operable to accumulate a capacitor array output signal and a comparison signal from
the successive approximation analog-to-digital converting circuit after the generation of the M bits and thereby generate
an accumulation signal; and

a multibit analog-to-digital converting circuit operable to generate N bits according to the accumulation signal in which
the N bits include a least significant bit (LSB) and successive N?1 bit(s) ahead of the LSB while N is an integer greater
than one.

US Pat. No. 9,288,385

IMAGE SHARING SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT

REALTEK SEMICONDUCTOR COR...

1. An image sharing system, comprising:
an image providing server, comprising:
a storage device, configured to operably store a site location data and a site orientation data of a target site, multiple
image data, and multiple photographing position data respectively corresponding to multiple image data, wherein each of the
multiple image data is photographed within a predetermined distance from the target site or contains at least a portion of
image content of an event occurred at the target site;

a processing circuit, coupled with the storage device, configured to operably calculate a photographing positions distribution
information representing a spatial distribution of the multiple photographing position data according to the site location
data, the site orientation data, and the multiple photographing position data; and

a transmission circuit, coupled with the processing circuit, configured to operably transmit the photographing positions distribution
information through Internet after an image enquiry request is received; and

an image playback device, comprising:
an input device, configured to operably generate the image enquiry request according to a user's manipulation;
a communication circuit, configured to operably transmit the image enquiry request to the transmission circuit of the image
providing server through the Internet, and to operably receive the photographing positions distribution information transmitted
from the transmission circuit;

a control circuit, coupled with the communication circuit and the input device, configured to operably generate multiple option
objects respectively corresponding to the multiple image data, and to operably arrange the multiple option objects according
to the photographing positions distribution information so as to generate a graphic user interface (GUI) containing the multiple
option objects and one or more reference indicators; and

a display device, coupled with the control circuit, configured to operably display the GUI;
wherein when the display device displays the GUI, if a moving command issued by the user is received by the input device,
the control circuit controls the display device to move at least part of the multiple option objects in the GUI toward a same
side and to correspondingly change position or content of at least one of the one or more reference indicators, and if an
option object selection command corresponding to a target option object in the GUI is received by the input device, the control
circuit controls the communication circuit to transmit an image data request corresponding to the target option object to
the transmission circuit of the image providing server through the Internet;

wherein when the image data request is received by the image providing server, the processing circuit controls the transmission
circuit to transmit a target image data out of the multiple image data to the communication circuit through the Internet,
and when the target image data is received by the communication circuit, the control circuit controls the display device to
display the target image data.

US Pat. No. 9,287,860

NEGATIVE RESISTANCE GENERATOR, LOAD INCLUDING NEGATIVE RESISTANCE AND LOAD OF AMPLIFIER

REALTEK SEMICONDUCTOR COR...

1. A negative resistance generator, comprising:
a first signal end, operable to receive a first signal including a first AC (alternating current) component and a first DC
(direct current) component;

a second signal end, operable to receive a second signal including a second AC component and a second DC component;
a first transistor, including a first high voltage-level electrode, a first low voltage-level electrode and a first gate,
in which the first high voltage-level electrode connects with the first signal end;

a second transistor, including a second high voltage-level electrode, a second low voltage-level electrode and a second gate,
in which the second high voltage-level electrode connects with the second signal end;

a power source circuit, one end of the power source circuit coupled with the first and second low voltage-level electrodes,
and another end of the power source circuit coupled with a voltage end;

a first DC level setting circuit, coupled between the first signal end and the second gate, operable to provide a second gate
voltage for the second gate according to a first DC voltage and the first AC component, in which the second gate voltage is
lower than the voltage of the first signal and the first DC level setting circuit comprises:

a third transistor, including a third high voltage-level electrode, a third low voltage-level electrode, and a third gate,
in which the third high voltage-level electrode connects with a load circuit, the third low voltage-level electrode connects
with the second gate, the third gate connects with the first signal end, and the voltage difference between the voltages of
the third gate and the third low voltage-level electrode is the first DC voltage; and

a first current source circuit, including one end coupled with the third low voltage-level electrode and another end coupled
with a first voltage end, operable to determine an active region of the third transistor in conjunction with the first signal
and the load circuit, and

a second DC level setting circuit, coupled between the second signal end and the first gate, operable to provide a first gate
voltage for the first gate according to a second DC voltage and the second AC component, in which the first gate voltage is
lower than the voltage of the second signal and the second DC level setting circuit comprises:

a fourth transistor, including a fourth high voltage-level electrode, a fourth low voltage-level electrode, and a fourth gate,
in which the fourth high voltage-level electrode connects with the load circuit, the fourth low voltage-level electrode connects
with the first gate, the fourth gate connects with the second signal end, and the voltage difference between the voltages
of the fourth gate and the fourth low voltage-level electrode is the second DC voltage; and

a second current source circuit, including one end coupled with the fourth low voltage-level electrode and another end coupled
with a second voltage end, operable to determine an active region of the fourth transistor in conjunction with the second
signal and the load circuit,

wherein the first gate voltage is equal to the voltage of the second signal subtracting the second DC voltage, and the second
gate voltage is equal to the voltage of the first signal subtracting the first DC voltage.

US Pat. No. 9,231,751

CLOCK-DATA RECOVERY CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a variable delay circuit receiving a recovered clock and outputting a calibrated clock in accordance with a control code;
a two-bit analog-to-digital converter for converting a received signal into two-bit data in accordance with a timing of the
calibrated clock; and

a vertical eye monitor circuit receiving the two-bit data and outputting the control code, wherein the timing of the recovered
clock is approximately aligned with a transition portion of serial binary data carried by the received signal.

US Pat. No. 9,160,518

HALF-RATE CLOCK-DATA RECOVERY CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a half-rate phase detector receiving a received signal comprising a stream of binary symbols alternating between an even symbol
and an odd symbol, and further receiving a four-phase clock comprising a first phase, a second phase, a third phase, and a
fourth phase, said half-rate phase detector outputting a phase error signal;

a phase error dissect circuit receiving the phase error signal and outputting an even-symbol phase error signal and an odd-symbol
phase error signal;

a first 2-bit ADC (analog-to-digital converter) receiving the received signal and outputting an even-symbol data in accordance
with the second phase of the four-phase clock;

a second 2-bit ADC receiving the received signal and outputting an odd-symbol data in accordance with the fourth phase of
the four-phase clock;

a first filter receiving the even-symbol phase error signal and outputting a first control signal;
a first vertical eye monitor circuit receiving the even-symbol data and outputting a second control signal;
a second filter receiving the odd-symbol phase error signal and outputting a third control signal;
a second vertical eye monitor circuit receiving the odd-symbol data and outputting a fourth control signal; and
a quadrature clock generator receiving the first control signal, the second control signal, the third control signal, and
the fourth control signal and outputting the four-phase clock.

US Pat. No. 9,854,719

PATTERNED GROUND SHIELD

REALTEK SEMICONDUCTOR COR...

1. A patterned ground shield, comprising:
a plurality of portions;
a first connection member and a second connection member, wherein each of the first connection member and the second connection
member is coupled to any two of the portions which are not adjacent to each other; and

a third connection member coupled to two of the portions which are adjacent to each other, wherein the connection members
do not directly couple to each other.

US Pat. No. 9,313,594

IMPEDANCE DETECTING DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. An impedance detecting device capable of detecting the impedance value of a load, comprising:
an alternating current (AC) signal generating circuit operable to generate an AC signal;
an output buffer operable to generate an output voltage and an output current according to the AC signal and the impedance
value of the load;

a current mirror operable to generate a mirror current according to the output current;
a detection impedance operable to generate a detection voltage according to the mirror current;
a comparing circuit operable to generate a comparison result by comparing the output voltage with the detection voltage; and
a control circuit, coupled to the comparing circuit and at least one of the current mirror and the detection impedance, operable
to adjust at least one of a current ratio of the mirror current to the output current and the impedance value of the detection
impedance according to the comparison result until the comparison result has satisfied a predetermined requirement.

US Pat. No. 9,225,504

CIRCUIT AND METHOD FOR CLOCK DATA RECOVERY AND CIRCUIT AND METHOD FOR ANALYZING EQUALIZED SIGNAL

REALTEK SEMICONDUCTOR COR...

1. A clock data recovery circuit for sampling an input signal according to a reference clock to generate a plurality of sampling
results, comprising:
a clock generation circuit, for generating a first sampling clock and a second sampling clock according to the reference clock,
wherein a phase difference between the first sampling clock and the second sampling clock is larger than 0 and smaller than
half a UI (unit interval) of the input signal, and each UI corresponds to an input data;

a sampling circuit, coupled to the clock generation circuit and receiving the input signal, for sampling successive UIs of
the input signal according to the first sampling clock and the second sampling clock, wherein a first sampling result and
a second sampling result corresponding respectively to the first sampling clock and the second sampling clock are generated
in each UI;

a comparing circuit, coupled to the sampling circuit, for comparing the first sampling result and the second sampling result
to generate a comparison result; and

a determination circuit, coupled to the comparing circuit, for generating an adjusting signal according to the comparison
result and the input data;

wherein the clock generation circuit adjusts the first sampling clock and the second sampling clock according to the adjusting
signal to make at least one of the two sampling results of each UI substantially correspond to a peak value at the UI of the
input signal.

US Pat. No. 9,413,374

METHOD AND APPARATUS FOR CALIBRATING COMPARATOR OFFSET OF SUCCESSIVE-APPROXIMATION-REGISTER ANALOG-TO-DIGITAL CONVERTER

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a multiplexed sampling network sampling either an input voltage or a common-mode voltage into a sampled voltage in accordance
with a sampling signal and a status of a foreground calibration indicator;

a first digital-to-analog converter outputting a conversion voltage in response to a conversion code;
a second digital-to-analog converter outputting an offset-correction voltage in response to an offset-correction code;
a summing circuit receiving the sampled voltage, the conversion voltage, and the offset-correction voltage and outputting
an error voltage;

a comparator receiving the error voltage and outputting a binary decision; and
a successive-approximation-register finite state machine receiving the binary decision and outputting an output data, the
sampling signal, the foreground calibration indicator, the conversion code, and the offset-correction code,

wherein the finite stage machine includes a foreground calibration state and a normal operation state;
wherein when the finite state machine operates in the foreground calibration state, the common-mode voltage is sampled, the
conversion code is set to a common-mode code, and a calibrated value of the offset-correction code is established by successive
approximation and

wherein when the finite state machine is in the normal operation state, the input voltage is sampled, the offset-correction
code is set to the calibrated value, and the conversion code is established by successive approximation.

US Pat. No. 9,312,912

SIGNAL TRANSMITTING AND RECEIVING CIRCUIT OF DIGITAL SUBSCRIBER LINE

REALTEK SEMICONDUCTOR COR...

1. A signal transmitting and receiving circuit of a digital subscriber line for transmitting an output signal to a telecommunication
loop or receiving an input signal from the telecommunication loop, comprising:
a transformer comprising a first winding, a second winding, and a third winding, the first winding comprising a first coil
and a second coil, the third winding coupled to the telecommunication loop and the first and the second coils comprising respectively
a first polarity end and a second polarity end;

a first impedance unit comprising two ends coupled respectively to the first polarity end of the first coil and the first
polarity end of the second coil;

a second impedance unit comprising two ends coupled respectively to the second polarity end of the first coil and the second
polarity end of the second coil;

a signal transmitting module, coupled to the first winding, for generating the output signal; and
a signal receiving module, coupled to the second winding, for processing the input signal;
wherein, the first winding and the third winding transmit the output signal to the telecommunication loop by electromagnetic
coupling, and the third winding and the second winding transmits the input signal to the signal receiving module by electromagnetic
coupling.

US Pat. No. 9,083,427

TRANSCEIVER AND COMMUNICATION METHOD OF DIGITAL SUBSCRIBER LINE

REALTEK SEMICONDUCTOR COR...

1. A transceiver of digital subscriber line (DSL) capable of supporting a variety of DSL systems, comprising:
a transmission circuit including:
a transmission selector to receive an output signal and provide the output signal for a first DSL analog-front-end transmission
circuit or a second DSL analog-front-end transmission circuit according to a transmission selection parameter;

the first DSL analog-front-end transmission circuit corresponding to a first DSL system to generate a first DSL transmission
signal according to the output signal; and

the second DSL analog-front-end transmission circuit corresponding to a second DSL system to generate a second DSL transmission
signal according to the output signal;

a hybrid circuit, coupled with the transmission circuit, to generate a line transmission signal according to the first DSL
transmission signal or the second DSL transmission signal and generate a DSL reception signal according to a line reception
signal, including:

a first echo canceller to carry out a first echo cancellation on the line reception signal; and
a second echo canceller to carry out a first DSL echo cancellation or a second DSL echo cancellation on the line reception
signal according to an echo cancellation selection parameter, including:

a first filtering circuit to carry out the first DSL echo cancellation if the echo cancellation selection parameter indicates
the first DSL system, and carry out the second DSL echo cancellation if the echo cancellation selection parameter indicates
the second DSL system; and

a second filtering circuit to carry out a second echo cancellation according to a line impedance detection result or an echo
cancellation amount estimation result; and

a reception circuit, coupled with the hybrid circuit, including:
a first DSL analog-front-end reception circuit corresponding to the first DSL system to generate a first DSL reception signal
according to the DSL reception signal;

a second DSL analog-front-end reception circuit corresponding to the second DSL system to generate a second DSL reception
signal according to the DSL reception signal; and

a reception selector to output the first DSL reception signal or the second DSL reception signal as an input signal according
to a reception selection parameter.

US Pat. No. 9,313,019

MULTI-CHANNEL TIMING RECOVERY DEVICE

REALTEK SEMICONDUCTOR COR...

1. A multi-channel timing recovery device capable of generating a common clock for dealing with a plurality of data channel
signals, comprising:
a first channel timing recovery circuit operable to generate the common clock, including:
a first detecting circuit capable of detecting phase and/or frequency and operable to detect a first channel signal according
to a first clock to thereby generate a first detection signal;

an oscillation control circuit operable to generate an oscillation control signal according to the first detection signal,
including one of the follows: a combination of a timing-to-digital converter and a first digital filter, a combination of
a first charge pump and a first analog filter, and a digital filter;

an oscillator operable to generate the common clock according to the oscillation control signal; and
a feedback circuit operable to provide the first clock according to the common clock; and
a second channel timing recovery circuit operable to generate a second clock according to the common clock, including:
a second phase detecting circuit operable to detect a second channel signal according to the second clock and thereby generate
a second phase detection signal;

a second phase control circuit operable to generate a second phase control signal according to the second phase detection
signal; and

a second clock output circuit operable to generate the second clock according to the common clock and determine the phase
of the second clock according to the second phase control signal; and

a selecting circuit operable to receive one of the first detection signal and the derived signal thereof and receive one of
the second phase detection signal and the derived signal thereof, and output the first detection signal or the derived signal
thereof to one of the oscillation control circuit and the oscillator according to a selection control signal.

US Pat. No. 9,490,858

TRANSMITTER CAPABLE OF REDUCING LOCAL OSCILLATION LEAKAGE AND IN-PHASE/QUADRATURE-PHASE (I/Q) MISMATCH AND ADJUSTING METHODS THEREOF

REALTEK SEMICONDUCTOR COR...

12. A transmitter comprising:
a compensating unit for performing phase and amplitude compensation upon first and second base band signals so as to generate
first and second output signals;

first and second digital-to-analog converters coupled electrically to said compensating unit for converting the first and
second output signals received from said compensating unit into corresponding first and second analog signals, respectively;

first and second low pass filters coupled electrically and respectively to said first and second digital-to-analog converters
for performing low pass filtering respectively upon the first and second analog signals;

first and second mixers coupled electrically and respectively to said first and second low pass filters, said first mixer
mixing output of said first low pass filter with an in-phase local oscillator signal so as to generate a first radio frequency
signal, said second mixer mixing output of said second low pass filter with a quadrature-phase local oscillator signal so
as to generate a second radio frequency signal;

a first adder coupled electrically to said first and second mixers for combining the first and second radio frequency signals;
a detecting unit coupled electrically to said first adder, and generating a detection signal that represents an extent of
in-phase/quadrature-phase (I/Q) mismatch from output of said first adder; and

an adjusting unit coupled electrically to said compensating unit for outputting at least one control signal thereto to control
a current operating state of said compensating unit, said adjusting unit being further coupled electrically to said detecting
unit, and determining whether there is a reduction in the extent of I/Q mismatch based on the detection signal from said detecting
unit;

wherein said adjusting unit maintains an adjusting direction corresponding to each of said at least one control signal upon
determining that the extent of I/Q mismatch is reduced, reverses the adjusting direction corresponding to each of said at
least one control signal upon determining that the extent of I/Q mismatch is not reduced, and adjusts each of said at least
one control signal according to the adjusting direction corresponding thereto.

US Pat. No. 9,473,128

DC VOLTAGE GENERATION CIRCUIT AND PULSE GENERATION CIRCUIT THEREOF

REALTEK SEMICONDUCTOR COR...

1. A pulse generation circuit for generating a pulse signal at an output terminal, comprising:
a PMOS having a source coupled to a first reference voltage level, a drain coupled to the output terminal, and a gate coupled
to receive a first gate control signal;

an NMOS having a source coupled to a second voltage level, a drain coupled to the output terminal, and a gate coupled to receive
a second gate control signal; and

a logic circuit, coupled to the gate of the PMOS and the gate of the NMOS, for generating the first gate control signal according
to a control signal and a first delay signal and generating the second gate control signal according to the control signal
and a second delay signal;

wherein the first delay signal is a delay of a first logic signal generated according to the second gate control signal and
the control signal, and the second delay signal is a delay of a second logic signal generated according to the first gate
control signal and the control signal.

US Pat. No. 9,578,657

WIRELESS COMMUNICATION METHOD AND DEVICE

REALTEK SEMICONDUCTOR COR...

1. A wireless communication method carried out by a wireless transmitter, comprising:
preparing a packet carrying an indication of a clear channel assessment (CCA) threshold level for an unintended wireless device;
transmitting the packet to an intended wireless device under a protocol by which the unintended wireless device is expected
to abide;

adjusting the CCA threshold level; and
adjusting a number or a value range of a backoff counter of the wireless transmitter in accordance with the variation of the
CCA threshold level.

US Pat. No. 9,312,892

DIGITAL PRE-DISTORTION CIRCUIT AND METHOD, AND DIGITAL PRE-DISTORTION TRAINING CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. A digital pre-distortion circuit capable of compensating for a non-linear characteristic of an analog circuit, comprising:
a pre-distortion training circuit operable to process a digital feedback signal according to a modified Cholesky Decomposition
algorithm and thereby generate a plurality of coefficients in which the digital feedback signal is derived from an output
signal of the analog circuit and the output signal of the analog circuit is derived from an original digital signal; and

a pre-distortion circuit, including the pre-distortion training circuit or being independent of the pre-distortion training
circuit, operable to process the original digital signal according to the plurality of coefficients under a compensation mode
and thereby generate a digital pre-distortion signal,

wherein the non-linear characteristic of the digital pre-distortion signal is operable to compensate for the non-linear characteristic
of the analog circuit and thereby make the output signal of the analog circuit conform to a predetermined characteristic,
and the pre-distortion training circuit is operable to generate the plurality of coefficients through carrying out at least
the following steps:

obtaining a pre-distortion transformation matrix according to the digital feedback signal, the order of a memory polynomial
and the depth of a memory effect;

doing a calculation according to the conjugate matrix of the pre-distortion transformation matrix, the pre-distortion transformation
matrix and the original digital signal to thereby obtain a calculation result; and

processing the calculation result according to the modified Cholesky Decomposition algorithm to thereby obtain the plurality
of coefficients.

US Pat. No. 9,501,088

CLOCK GENERATOR, COMMUNICATION DEVICE AND SEQUENTIAL CLOCK GATING CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. A clock generator comprising:
an oscillator operable to generate a reference clock;
a multi-phase clock generating circuit, coupled to the oscillator, operable to generate a plurality of output clocks according
to the reference clock, and operable to stop or start outputting the output clocks according to a power control signal in
which the output clocks have the same frequency but different phases;

a sequential clock gating circuit, coupled to the multi-phase clock generating circuit, operable to sequentially stop or start
outputting a plurality of gated clocks according to a gate control signal and the plurality of output clocks, and operable
to maintain an output cycle number relation between the gated clocks after the multi-phase clock generating circuit stopped
and then starts outputting the output clocks; and

a clock operation control circuit, coupled to the multi-phase clock generating circuit and the sequential clock gating circuit,
operable to provide the power control signal and the gate control signal.

US Pat. No. 9,337,181

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

REALTEK SEMICONDUCTOR COR...

1. A semiconductor device, comprising:
a substrate;
a first trough structure on the substrate, comprising:
a first conductive layer;
a first doping layer, a doping concentration of which is higher than a doping concentration of the substrate; and
a first insulation layer, formed between the first conductive layer and the first doping layer;
a second trough structure on the substrate and separated from the first trough structure by a separation part of the substrate,
comprising:

a second conductive layer;
a second doping layer, a doping concentration of which is higher than a doping concentration of the substrate; and
a second insulation layer, formed between the second conductive layer and the second doping layer;
a first contact, connecting the first doping layer;
a second contact, connecting the second doping layer; and
a third contact, connecting the second conductive layer;
wherein the separation part of the substrate forms a resistor, which is coupled between the first contact and the second contact,
and the second doping layer, the second insulation layer and the second conductive layer together form a capacitor, which
is coupled between the second contact and the third contact.

US Pat. No. 9,564,910

CLOCK GENERATION CIRCUIT AND METHOD THEREOF

Realtek Semiconductor Cor...

1. A clock generation circuit for generating a clock comprising:
a reference clock generation circuit, which is installed in a chip for independently generating a reference clock;
a temperature sensor for sensing an ambient temperature to generate temperature information;
a temperature compensation module, coupled to the temperature sensor, for generating a temperature compensation coefficient
according to the temperature information; and

a clock adjusting circuit, coupled to the reference clock generation circuit, for generating the clock according to the reference
clock and the temperature compensation coefficient;

wherein, the temperature compensation module generates the temperature compensation coefficient dynamically so that a frequency
of the clock approaches a target frequency and does not substantially vary with the temperature.

US Pat. No. 9,473,292

DEVICE AND METHOD FOR NRZ CDR CALIBRATION

REALTEK SEMICONDUCTOR COR...

1. A device for Non Return to Zero (NRZ) Clock Data Recovery (CDR) calibration, comprising:
a CDR unit, for receiving a compensative signal to generate a sampling clock signal, a data signal, an error signal and a
transition sampling signal, the error signal being output from the CDR unit; and

a weight calculator unit, separate and distinct from the CDR unit, coupled to the CDR unit, and configured to receive the
error signal and the data signal and then performing weight calculation to generate a weight data;

wherein the CDR unit adjusts the sampling clock signal according to the weight data.

US Pat. No. 9,160,322

CLOCK EDGE DETECTION DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A clock edge detection device capable of detecting the positive and negative edges of a target clock, comprising:
a delay circuit including a plurality of delay units connected in series for receiving and transmitting the target clock by
a predetermined transmission arrangement;

a register circuit including a plurality of registers coupled to the delay circuit for recording and outputting target clock
levels of the target clock in accordance with a working clock whose frequency is higher than the frequency of the target clock,
wherein each of the registers includes a data input end for receiving the target clock from one of the delay units, a data
output end, and a working clock reception end for receiving the working clock;

a positive edge detection circuit including a plurality of positive edge detectors coupled to the data output ends of the
register circuit for detecting the positive edge of the target clock, wherein each of the positive edge detectors includes
a positive edge detection unit for generating a positive edge detection value according to the target clock levels from adjacent
two of the registers; and

a negative edge detection circuit including a plurality of negative edge detectors coupled to the data output ends of the
register circuit for detecting the negative edge of the target clock, wherein the configuration of the negative edge detection
circuit is not identical to the configuration of the positive edge detection circuit in consideration of the predetermined
transmission arrangement and each of the negative edge detectors includes a negative edge detection unit for generating a
negative edge detection value according to the target clock levels from adjacent two of the registers,

wherein the positive edge detection values record at least two positive edges and the negative edge detection values record
at least one negative edge, or the negative edge detection values record at least two negative edges and the positive edge
detection values record at least one positive edge.

US Pat. No. 9,705,512

SELF-CALIBRATING FRACTIONAL-N PHASE LOCK LOOP AND METHOD THEREOF

Realtek Semiconductor Cor...

1. A circuit comprising:
a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third
clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal;

a timing detection circuit configured to receive the third clock and the fourth clock and output a timing error signal;
a filtering circuit configure to receive the timing error signal and output an oscillator control signal;
a controllable oscillator configured to receive the oscillator control signal and output a fifth clock;
a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor;
a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation
signal, wherein a mean value of the division factor is equal to the clock multiplication factor; and

a calibration circuit configured to receive the timing error signal and the noise cancellation signal and output the gain
control signal.

US Pat. No. 9,590,640

CLOCK AND DATA RECOVERY APPARATUS AND METHOD OF THE SAME

REALTEK SEMICONDUCTOR COR...

1. An electronic apparatus comprising:
an oscillator, generating a reference clock signal and an auxiliary dock signal offset by 90 degrees and having transition
edges, wherein one of the transition edges is a data-sampling edge;

a sampler, sampling an input data signal at each of the transition edges to generate a plurality of primary sampled signals;
a phase detector, determining a phase difference of a data transition of the input data signal relative to the reference clock
signal by comparing each of the primary sampled signals with the data-sampling edge;

a phase rotator, rotating the primary sampled signals and the reference clock signal according to the phase difference such
that the phase detector receives the rotated primary sampled signals and the rotated reference clock signal; and

a loop filter, generating a control voltage to the oscillator to vary phases of the reference clock signal and the auxiliary
clock signal according to phase difference of the data transition relative to the rotated reference clock signal.

US Pat. No. 9,473,204

FULL-DUPLEX TRANSCEIVER CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A full-duplex transceiver circuit comprising:
a line driver configured to output a first current to a first node and a second current to a second node;
a first resistor configured to shunt the first node to ground;
a second resistor configured to shunt the second node to ground;
a first capacitor configured to couple the first node to a third node;
a second capacitor configured to couple the second node to the third node;
an operational amplifier configured to receive a first input from a reference node and a second input from the third node
and output an output voltage at a fourth node;

a feedback network comprising a parallel connection of a third resistor and a third capacitor configured to provide a feedback
from the fourth node to the third node; and

a transmission line of a characteristic impedance configured to couple the first node to a remote transceiver.

US Pat. No. 9,621,157

SAMPLING CIRCUIT AND SAMPLING METHOD

REALTEK SEMICONDUCTOR COR...

1. A sampling circuit for sampling an input voltage and generating an output voltage, comprising:
a switch, switching off in a first switching state and switching on to make the output voltage equal to the input voltage
in a second switching state, wherein the switch has a control terminal;

a capacitor, coupled to the switch;
a first switch group, coupled to the capacitor;
a second switch group, coupled to the capacitor;
an operational amplifier, having an inverting input, a non-inverting input and an output, wherein the non-inverting input
is coupled to the ground;

a first resistor having one terminal coupled to the inverting input and another terminal receiving the input voltage;
a second resistor having one terminal coupled to the inverting input and another terminal coupled to the output of the operational
amplifier; and

an inverter having an input coupled to the output of the operational amplifier and an output coupled to the capacitor;
wherein, the resistance of the first resistor is equal or close to the resistance of the second resistor so that a voltage
at the output of the inverter is substantially equal or close to the input voltage, and in the first switching state when
the first switch group switches on and the second switch group switches off, the capacitor is charged to generate a voltage
difference across the two terminals thereof, and in the second switching state when the first switch group switches off and
the second switch group switches on, the output of the inverter is directly connected to the capacitor and the input voltage
is coupled to the control terminal of the switch through the operational amplifier, the first resistor, the second resistor,
the inverter, and the capacitor so that a voltage at the control terminal is substantially equal or close to the input voltage
plus the voltage difference across the capacitor.

US Pat. No. 9,570,982

DC VOLTAGE GENERATION CIRCUIT AND PULSE GENERATION CIRCUIT THEREOF

REALTEK SEMICONDUCTOR COR...

1. A pulse generation circuit for generating a pulse signal at an output terminal, comprising:
a PMOS having a source coupled to a first voltage level, a drain coupled to the output terminal, and a gate coupled to receive
a first gate control signal;

an NMOS having a source coupled to a second voltage level, a drain coupled to the output terminal, and a gate coupled to receive
a second gate control signal; and

a logic circuit, coupled to the gate of the PMOS and the gate of the NMOS, for generating the first gate control signal according
to a control signal and a first logic signal and generating the second gate control signal according to the control signal
and a second logic signal;

wherein, the first logic signal is a logic operation result based simultaneously on a first delay signal and the second gate
control signal, the first delay signal being a delayed signal of the second gate control signal, and the second logic signal
is a logic operation result based simultaneously on a second delay signal and the first gate control signal, the second delay
signal being a delayed signal of the first gate control signal.

US Pat. No. 9,590,560

SUMMING AMPLIFIER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An apparatus comprising:
a first transconductance device of a first type configured to convert a first voltage into a first current of an output node;
a second transconductance device of a second type configured to convert a second voltage into a second current of the output
node;

a common mode feedback circuit coupled to the output node configured to control a mean voltage at the output node in accordance
with a reference voltage; and

a reset circuit configured to reset a voltage at the output node in accordance with a clock signal, wherein the clock signal
is a periodic logic signal.

US Pat. No. 9,312,867

PHASE LOCK LOOP DEVICE WITH CORRECTING FUNCTION OF LOOP BANDWIDTH AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A phase lock loop (PLL) device with a correcting function of a loop bandwidth, comprising:
a PLL circuit, for generating a control voltage according to a reference signal and a feedback signal, and generating an output
signal according to the control voltage, wherein the feedback signal is related to the output signal, and there is a feedback
coefficient between the feedback signal and the output signal; and

a correcting circuit, for modulating the feedback coefficient to unlock the feedback signal and the reference signal, calculating
an oscillation frequency according to two valid crossovers of a phase difference between the reference signal and the feedback
signal, and adjusting a control parameter of the PLL circuit according to the oscillation frequency,

wherein the PLL circuit comprises:
a loop filter comprising:
a resistor, for providing the control voltage; and
a capacitor, electrically connected between the resistor and a ground; and
wherein the correcting circuit comprises:
a control unit, for calculating the oscillation frequency according to the two valid crossovers of the phase difference between
the reference signal and the feedback signal and adjusting the control parameter according to the oscillation frequency;

a switch, bridged over the resistor; and
a setting unit, for setting the feedback coefficient;
wherein the control unit is used for controlling the setting unit to modulate the feedback coefficient, and then controlling
the switch to short-circuit the resistor, so that the control voltage occurs with an oscillation effect.

US Pat. No. 9,385,661

AMPLIFIER WITH DETERMINISTIC NOISE CANCELLATION AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a passive input network of an input impedance configured to couple an input voltage to a first circuit node;
an adaptive current source configured to output an adaptive bias current to the first circuit node;
a cascode device controlled by a control voltage and configured to receive a sum current from the first circuit node and output
an output current to a second circuit node; and

a load network of a load impedance configured to provide termination to the second circuit node, wherein the adaptive bias
current is dynamically adapted to track a deterministic noise component in the input voltage.

US Pat. No. 9,572,114

CHANNEL MAP GENERATION METHOD AND APPARATUS THEREFOR

Realtek Semiconductor Cor...

1. A channel map generation method, comprising:
performing a power spectrum density detection on a plurality of channels in a frequency band, to generate a first channel
map;

performing a first smoothing operation on the first channel map by a first window size to generate a second channel map, wherein
the first smoothing operation comprises:

grouping channels of the first channel map into a plurality of channel groups according to the first window size, wherein
window sizes of the channel groups are the same; and

according to the number of good channels or bad channels in each of the respective channel groups of the first channel map,
deciding to retain channel determinations in the respective channel group of the first channel map, or re-designating all
the channels in the respective channel group of the first channel map, so as to generate the second channel map; and

performing a second smoothing operation on the second channel map by a second window size and accordingly generating a third
channel map, wherein the second smoothing operation comprises:

grouping channels of the second channel map into a plurality of channel groups according to the second window size, wherein
window sizes of the channel groups of the second channel map are the same; and

according to the number of good channels or bad channels in each of the respective channel groups of the second channel map,
deciding to retain channel determinations in the respective channel group of the second channel map, or re-designating all
the channels in the respective channel group of the second channel map, so as to generate the third channel map, wherein the
second window size is wider than the first window size; and

wherein, for each channel group in the first and second channel maps, re-designating all channels in the respective channel
group as bad channels according to a number of good channels in the respective channel group being less than a good channel
threshold or a number of bad channels in the respective channel group being more than a bad channel threshold.

US Pat. No. 9,576,946

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SAME

REALTEK SEMICONDUCTOR COR...

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first trough structure on the substrate, the first trough structure comprising at least a first sidewall;
forming a first doping layer on the first sidewall;
covering the first doping layer and a part of a surface of the substrate by a photoresist;
forming a second trough structure on a part of the substrate which is not covered by the photoresist, the second trough structure
comprising at least a second sidewall;

removing the photoresist;
forming an insulation layer on the substrate, the first trough structure, and the second trough structure, wherein a first
part of the insulation layer is in the first trough structure and covers the first doping layer, and a second part of the
insulation layer is in the second trough structure;

forming a conductive layer on the substrate, the first trough structure, and the second trough structure, wherein a first
part of the conductive layer is in the first trough structure and covers the first insulation layer, and a second part of
the conductive layer is in the second trough structure and covers the second insulation layer; and

removing parts of the insulation layer and the conductive layer that are outside the first trough structure and the second
trough structure to expose a surface of the first doping layer at the opening of the first trough structure.

US Pat. No. 9,252,753

QUADRATURE OUTPUT RING OSCILLATOR AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
four primary inverters configured in a ring topology;
four coupling resistors uniformly disposed in the ring among the four primary inverters, wherein a coupling resistor is interposed
between each successive primary inverter; and

four feedforward inverters forming four sub-feedback loops, respectively, each comprising two primary inverters, one coupling
resistor, and one feedforward inverter, wherein each end of each of the four coupling resistors shares a connection with one
of the four primary inverters and one of the four feedforward inverters.

US Pat. No. 9,214,190

AUDIO SIGNAL PROCESSING METHOD

REALTEK SEMICONDUCTOR COR...

7. An audio signal processing method, comprising the steps of:
dividing an audio signal data stream into a plurality of selection segments;
determining a target segment in the audio signal data stream, the target segment including a splice point for splicing a splice
segment thereto;

selecting one of the selection segments as the splice segment according to at least one parameter of the target segment;
processing the target segment and the splice segment to splice the splice segment to the target segment, and outputting a
processed segment;

calculating an error value equal to number of target audio signal data points minus number of audio signal data points of
the processed segment; and

outputting the audio signal data stream, comprising the processed segment with added or removed points of audio signal data,
for playback.

US Pat. No. 9,214,951

SELF-CALIBRATING VCO-BASED ANALOG-TO-DIGITAL CONVERTER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
an input dispatch unit for receiving an input signal and a calibration signal and outputting N dispatched signals in accordance
with a selection signal, where N is an integer greater than two;

N analog-to-digital converter (ADC) units for receiving the N dispatched signals, N control signals, and N mapping tables
and outputting N raw data, and N refined data, respectively;

an output dispatch unit for receiving the N refined data and outputting an output data in accordance with the selection signal;
a calibration controller for receiving the N raw data and outputting the selection signal, the N control signals, the N mapping
tables, and a digital code; and

a DAC (digital-to-analog converter) for receiving the digital code and outputting the calibration signal, wherein the selection
signal has N possible values, and one of the N dispatched signals as specified by the selection signal is from the calibration
signal while the other N?1 dispatched signals are from the input signal.

US Pat. No. 9,195,244

VOLTAGE REGULATING APPARATUS WITH ENHANCEMENT FUNCTIONS FOR TRANSIENT RESPONSE

REALTEK SEMICONDUCTOR COR...

1. A voltage regulating apparatus, comprising:
a power transistor, having a control terminal, a first terminal for receiving a power supply, and a second terminal for providing
an output voltage;

a feedback circuit, coupled to the second terminal, configured for providing a feedback voltage according to the output voltage;
an amplifier having a source current unit and a sink current unit, configured for driving the power transistor through the
control terminal by use of the source and sink current units according to a reference voltage and the feedback voltage; and

a transient enhancement unit, configured for monitoring the source and sink current units, and regulating a voltage at the
control terminal according to the monitored result.

US Pat. No. 9,253,759

SELECTING FROM A PLURALITY OF CHANNELS ACCORDING TO QUALITY OF TEST CARRIERS

Realtek Semiconductor Cor...

1. A channel selection method, comprising:
generating a plurality of test carriers on a plurality of different candidate channels of a wireless device, respectively;
obtaining a plurality of channel quality information corresponding to the plurality of test carriers, respectively;
generating a test result according to the plurality of channel quality information; and
selecting a target channel from the plurality of candidate channels according to the test result;
wherein the step of generating the test result according to the plurality of channel quality information comprises:
calculating a plurality of weighted scores according to the plurality of channel quality information, respectively, and the
calculating step comprises: regarding a specific channel quality information corresponding to a specific candidate channel
in the plurality of channel quality information:

determining a plurality of weightings corresponding to the specific channel quality information and channel quality information
of the at least one neighboring candidate channel according to relative position between the specific candidate channel and
the at least one neighboring candidate channel, respectively;

obtaining a plurality of weighting results by multiplying the plurality of weightings with the specific channel quality information
and channel quality information of the at least one neighboring candidate channel, respectively; and

summing up the plurality of weighting results as a weighted score corresponding to the specific channel quality information;
and

generating the test result according to the plurality of weighted scores.

US Pat. No. 9,274,986

DATA TRANSMISSION CIRCUIT AND DATA TRANSMISSION METHOD USING CONFIGURABLE THRESHOLD AND RELATED UNIVERSAL SERIAL BUS SYSTEM

Realtek Semiconductor Cor...

1. A data transmission circuit applied to a universal serial bus (USB) system, comprising:
a memory, arranged for receiving and storing external data;
a direct memory access (DMA) engine, coupled to the memory and arranged for controlling data retrieved from the memory; and
a USB controller, coupled to the DMA engine, the USB controller arranged for receiving data from the DMA engine and for transmitting
the received data to a host;

wherein the DMA engine starts to fetch data from the memory when a data volume of stored data in the memory changes from a
first value to a first threshold while in the memory, transmits fetched data to the USB controller until a data volume of
the fetched data reaches a second threshold or no data left in the memory, and the first value is lower than the first threshold,
and the second threshold is greater than the first threshold;

wherein a transmission bandwidth between the memory and the DMA engine is less than a transmission bandwidth between the USB
controller and the host.

US Pat. No. 9,274,988

MODE SWITCHING METHOD OF ELECTRONIC DEVICE AND ASSOCIATED ELECTRONIC DEVICE

Realtek Semiconductor Cor...

1. A mode switching method of an electronic device, comprising:
setting the electronic device to start operating in a first mode when the electronic device is electrically connected to a
host;

detecting whether the host has a driver of the electronic device installed therein or not, by the electronic device, when
the host has an operating system installed therein;

maintaining the electronic device to be operated in the first mode when the electronic device determines that the host has
the driver installed therein;

switching the electronic device to be operated in a second mode when the electronic device determines that the host does not
have the driver installed therein; and

after switching the electronic device to the second mode: determining whether the electronic device is switched to the second
mode under an operation of the operating system of the host;

maintaining the electronic device in the second mode when the electronic device is switched to the second mode under the operation
of the operating system of the host; and

when the electronic device is not switched to the second mode under the operation of the operating system of the host, switching
the electronic device to the first mode, and determining whether the host has the driver of the electronic device installed
therein to decide whether to maintain the electronic device in the first mode or switch the electronic device to the second
mode again for installation of the driver;

wherein the second mode is a storage device mode for installation of the driver;
wherein the step of determining whether the electronic device is switched to the second mode under the operation of the operating
system of the host comprises: recording a time point at which the electronic device is switched to the second mode;

receiving a resetting signal from the host and recording a time point at which the resetting signal is received; and
determining whether the electronic device is switched to the second mode under the operation of the operating system of the
host according to the time point at which the electronic device is switched to the second mode and the time point at which
the resetting signal is received;

wherein the step of determining whether the electronic device is switched to the second mode under the operation of the operating
system of the host comprises: referring to a time difference between the time point at which the electric device is switched
to the second mode and the time point at which the resetting signal is received to determine whether the electronic device
is switched to the second mode under the operation of the operating system of the host;

determining that the electronic device is not switched to the second mode under the operation of the operating system of the
host when the time difference is lamer than a threshold value; and

determining that the electronic device is switched to the second mode under the operation of the operating system of the host
when the time difference is smaller than a threshold value.

US Pat. No. 9,147,257

CONSECUTIVE THIN EDGE DETECTION SYSTEM AND METHOD FOR ENHANCING A COLOR FILTER ARRAY IMAGE

REALTEK SEMICONDUCTOR COR...

1. A consecutive thin edge detection system, comprising:
a consecutive thin edge detector, receiving a color pixel array including a plurality of color pixels, alternately setting
each color pixel as a target pixel, detecting a difference value between a plurality of first green pixels and a plurality
of second green pixels nearby the target pixel, and determining whether the target pixel comprises a consecutive thin edge
feature or not according to the difference value; wherein the plurality of first green pixels are in red pixel rows which
comprises a plurality red pixels and the plurality of first green pixels, and the plurality of second green pixels are in
a blue pixel row which comprises blue pixels and the plurality of second green pixels;

a color gradient estimator, coupled to the consecutive thin edge detector, wherein the color gradient estimator estimates
color gradients of the target pixels having the consecutive thin edge feature to generate a horizontal gradient value and
a vertical gradient value; and

a direction indicator, coupled to the color gradient estimator, wherein the direction indicator generates direction indicating
values corresponding to the target pixels having the consecutive thin edge feature respectively according to the horizontal
gradient value and the vertical gradient value.

US Pat. No. 9,075,602

METHOD AND DEVICE OF POWER SAVING FOR TRANSMITTING SIGNALS

REALTEK SEMICONDUCTOR COR...

1. A power saving method controlled by a Link Training and Status State Machine (LTSSM) in a PCI Express device for data signal
transmission during a link training and initialization process, comprising:
providing a local terminal including a first training sequence (TS1) and a second training sequence (TS2);

transmitting a test signal from the local terminal to initiate the link training and initialization process, wherein the test
signal has a first test amplitude selected from a plurality of preset amplitudes;

receiving an acknowledgement signal from a remote terminal when the test signal from the local terminal is received by the
remote terminal;

acknowledging by transmitting the TS2 of the local terminal from the local terminal if the acknowledgement signal transmitted from the remote terminal for a response
to the test signal is received by the local terminal to finish the link training and initialization process; and

transmitting a data signal having a data signal amplitude based on the first test amplitude by the local terminal after the
link training and initialization process is finished,
wherein:
the test signal is one of the TS1 of the local terminal and the TS2 of the local terminal, and the acknowledgement signal includes a second training sequence (TS2) of the remote terminal; and

the TS1 and TS2 of the local terminal and the TS2 of the remote terminal are transmitted in the PCI Express device;

the local terminal transmits the test signal and receives the acknowledgement signal respectively through a first channel
and a second channel, and the first channel and the second channel are arranged as parallel cables; and

the method is repeated if at least three consecutive Non-Acknowledgement (NAK) signals are transmitted from the remote terminal
and received by the local terminal while the local terminal is transmitting the data signal.

US Pat. No. 9,466,526

METAL TRENCH DECOUPLING CAPACITOR STRUCTURE PENETRATING THROUGH A SHALLOW TRENCH ISOLATION

Realtek Semiconductor Cor...

6. A metal trench de-coupling capacitor structure, comprising:
a substrate which is grounded;
a vertical trench penetrating a shallow trench isolation and disposed in said substrate;
an insulating layer disposed on the sidewall of said vertical trench; and
a metal connection layer comprising a lateral extending portion, disposed on said substrate, without directly contacting said
shallow trench isolation and filling up said vertical trench, wherein said metal connection layer is electrically connected
to a power.

US Pat. No. 9,300,278

METHOD AND APPARATUS FOR CALIBRATING CMOS INVERTER

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a first tunable CMOS (complementary metal-oxide semiconductor) inverter, controlled by a control signal, receiving a first
voltage from a first circuit node and outputting a second voltage to a second circuit node;

a second tunable CMOS inverter, controlled by the control signal, receiving the second voltage from the second circuit node
and outputting the first voltage to the first circuit node;

a resistor coupling the first circuit node to the second circuit node;
a switch controlled by a reset signal conditionally shorting the first circuit node to the second circuit node; and
a finite state machine receiving the first voltage and the second voltage and outputting the reset signal and the control
signal, wherein the control signal is adjusted based on a difference between the first voltage and the second voltage.

US Pat. No. 9,225,543

NETWORK INTERFACE CARD, NETWORK SYSTEM, AND METHOD FOR BUILDING NETWORK CONNECTIONS WITH A REMOTE NETWORK APPARATUS VIA HDMI

Realtek Semiconductor Cor...

1. A network interface card utilized as a front-end device prior to a High Definition Multimedia Interface (HDMI) card, comprising:
a receiving unit, for receiving a first hot-plug signal transmitted from a remote network apparatus via an HDMI, and generating
a second hot-plug signal according to the first hot-plug signal; and

a capturing unit, coupled to the receiving unit, for capturing a physical address of the remote network apparatus via the
HDMI;

wherein after the physical address of the remote network apparatus is captured by the capturing unit, the network interface
card communicates with the remote network apparatus by using the HDMI, and the receiving unit prevents a transformation of
the second hot-plug signal until the physical address of the remote network apparatus is captured.

US Pat. No. 9,161,127

SIGNAL PROCESSING APPARATUS

Realtek Semiconductor Cor...

1. A signal processing apparatus, for receiving a noise signal to generate a noise cancellation signal, comprising:
an inverting circuit, for inverting a first signal to generate an inverted first signal;
a selecting circuit, coupled to the inverting circuit, for selecting one of the first signal and the inverted first signal
as an output signal;

a switch circuit, coupled to the inverting circuit and the selecting circuit, for controlling an operation of the signal processing
apparatus; and

an evaluation circuit, coupled to the switch circuit, for evaluating an energy value corresponding to the first signal and
controlling the switch circuit according to the energy value.

US Pat. No. 9,059,708

SIGNAL GENERATING APPARATUS FOR GENERATING POWER-ON-RESET SIGNAL

REALTEK SEMICONDUCTOR COR...

1. A signal generating apparatus for generating a power-on-reset signal, comprising:
a bias circuit for generating an output bias voltage, wherein the bias circuit comprises at least one bipolar junction transistor
(BJT), a base terminal of the BJT is coupled to a collector terminal of the BJT, and the output bias voltage is related to
an emitter-to-base voltage of the BJT;

a power-on-reset signal generating circuit comprising a duplication unit and a hysteresis unit, the duplication unit configured
to generate a first voltage by substantially duplicating the output bias voltage, the hysteresis unit configured to receive
the first voltage and generate a second voltage based on the first voltage;

a bandgap reference circuit, for generating a third voltage; and
a determination unit, coupled to the power-on-reset signal generating circuit and the bandgap reference circuit, the determination
unit generating the power-on-reset signal according to the second voltage and the third voltage.

US Pat. No. 9,252,199

INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD

Realtek Semiconductor Cor...

1. An integrated inductor, comprising:
a semiconductor substrate;
a plurality of deep trenches, formed in the semiconductor substrate extending from a surface of the semiconductor substrate
towards an opposite surface without reaching the opposite surface of the semiconductor substrate and arranged in a specific
pattern such that a width of each deep trench is smaller than a depth of each deep trench of the plurality of deep trenches,
and wherein the deep trenches are filled with a metal material to form a patterned ground shield (PGS); and an inductor, formed
directly above the PGS and having a pattern directly covering the PGS such that a coil of the inductor crosses some of the
deep trenches among the plurality of trenches in the width direction in a top view.

US Pat. No. 9,240,828

TRANSMITTING METHOD AND TRANSMISSION SYSTEM USING THE SAME

REALTEK SEMICONDUCTOR COR...

1. A transmitting method comprising:
processing a transmitted data to generate a plurality of data streams;
transmitting the plurality of data streams by using a plurality of transmitting paths, and computing a transmission quality
of each of the plurality of transmitting paths based on a threshold and a corresponding channel parameter in accordance with
the following equations:

wherein Nn denotes the transmission quality, Tp denotes the threshold, hn(k) denotes the corresponding channel parameter, n is an integer representing an estimated transmitting path, k is an integer
representing an estimated tone, and K denotes a total of tones for signal transmission of the transmission system; and
determining whether at least one of the data streams is transmitted using space block-coding technique or not in response
to the transmission qualities.

US Pat. No. 9,213,427

OVER-DRIVE CONTROLLER APPLIED TO A DISPLAY PANEL AND METHOD FOR OVER-DRIVE CONTROL THEREIN

REALTEK SEMICONDUCTOR COR...

1. An over-drive controller applied to a display panel, comprising:
an analyzing unit, arranged for analyzing information of a current pixel in order to generate an over-drive information;
an over-drive delta value determining unit, coupled to the analyzing unit, arranged for determining an over-drive delta value
according to the over-drive information;

wherein the over-drive information comprises a position information or a field information of the current pixel: and
a receiving unit, arranged for receiving a visual angle signal and providing the visual angle signal to the analyzing unit;
wherein the analyzing unit is further arranged for generating the over-drive information based on the visual angle signal,
and providing the over-drive information to the over-drive delta value determining unit, the visual angle signal related to
a viewing location where a user is viewing the display panel.

US Pat. No. 9,161,093

CORDLESS MULTIMEDIA SYSTEM AND IMAGE DISPLAY SYSTEM

REALTEK SEMICONDUCTOR COR...

1. A multimedia system comprising:
a data source for providing a multimedia data;
a wireless transmitting module, coupled to the data source, comprising a wireless transmitter for transmitting the multimedia
data, a detector, and an analog-to digital converter,

the analog-to-digital converter being utilized for converting the multimedia data from an analog format to a digital format,
the detector being configured to determine a sampling rate of the analog-to-digital converter according to a vertical synchronization
signal or a horizontal synchronization signal;

a packet former configured to generate packets according to the sampling rate determined by the detector and the multimedia
data;

a wireless receiving module comprising a wireless receiver for receiving the multimedia data from the wireless transmitter;
and

a reproducing device, coupled to the wireless receiving module, for reproducing the multimedia data received by the wireless
receiver.

US Pat. No. 9,135,956

METHOD AND COMPUTER PROGRAM PRODUCT FOR ESTABLISHING PLAYBACK TIMING CORRELATION BETWEEN DIFFERENT CONTENTS TO BE PLAYBACKED

REALTEK SEMICONDUCTOR COR...

1. A playback timing correlation editing method for controlling a timing correlation establishing device to establish playback
timing correlation between contents to be playbacked by different playback devices, wherein the timing correlation establishing
device comprises a display device, a input device, a communication circuit, and a control circuit, the method comprising:
utilizing the display device to display an editing screen containing a timeline;
displaying a main device block corresponding to a main display device in the editing screen;
when an editor requests to add a main video clip corresponding to the main display device through the input device, displaying
a main event block corresponding to the main video clip in the main device block, and displaying a main event name corresponding
to the main video clip and a main event graph representing a total time length of the main video clip in the main event block;

when the editor requests to add a device block though the input device, displaying a first auxiliary device block corresponding
to a first auxiliary display device in the editing screen;

when the editor requests to add a first auxiliary video clip corresponding to the first auxiliary display device through the
input device, displaying a first auxiliary event block corresponding to the first auxiliary video clip in the first auxiliary
device block, and displaying a first auxiliary event name corresponding to the first auxiliary video clip and a first auxiliary
event graph representing a total time length of the first auxiliary video clip in the first auxiliary event block;

displaying a time marker on a position of a first time point on the timeline according to the editor's manipulation to the
input device;

when the editor selects the main event name or the main event graph through the input device, configuring the main event block
to have a highlighted pattern; and

when the time marker is located at the position of the first time point on the timeline, if the editor conducts a first set
of predetermined manipulations through the input device, configuring the main video clip as a first trigger source event,
configuring the first auxiliary video clip as a first trigger target event, and utilizing the control circuit to establish
a first trigger timing data for indicating that the first auxiliary display device has to begin playbacking the first auxiliary
video clip when the main display device playbacks the main video clip to the first time point.

US Pat. No. 9,136,902

METHOD AND DEVICE FOR IMPLEMENTATION OF ADAPTIVE FREQUENCY HOPPING BY POWER SPECTRAL DENSITY

REALTEK SEMICONDUCTOR COR...

1. A wireless communication device, comprising:
a single antenna;
a frequency hopping communication circuit switchably coupled to the single antenna and including a channel map for selecting
a channel from a plurality of channels in turn according to the channel map to connect to a frequency hopping communication
device;

a power spectral density circuit switchably coupled to the single antenna, the power spectral density circuit for measuring
spectra of a bandwidth when the frequency hopping communication circuit is idle according to a time-division multiplexing
process involving the frequency hopping communication circuit and the power spectral density circuit, the spectra of the bandwidth
comprising all the channels of the frequency hopping communication circuit to generate power spectral density data, the power
spectral density data comprising an interference power curve comprising a defined magnitude of power per channel frequency
for each point on the interference power curve, where the magnitudes of power above a predefined power magnitude threshold
of the curve correspond to greater interference than the magnitudes of power below the predefined power magnitude threshold;
and

a control circuit, for updating the channel map according to the power spectral density data.

US Pat. No. 9,112,264

SWITCHED BEAM SMART ANTENNA APPARATUS AND RELATED WIRELESS COMMUNICATION CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. A switched beam smart antenna apparatus, comprising:
a first, a second, a third, a fourth, a fifth, a sixth, a seventh, and an eighth beam adjusting elements;
a first, a second, a third, and a fourth radiation strips positioned within an area surrounded by the first to the eighth
beam adjusting elements;

a radiation strip control module for selecting either the first and the second radiation strips or the third and the fourth
radiation strips to transmit signals;

a first beam control module coupled with the first and the second beam adjusting elements;
a second beam control module coupled with the third and the fourth beam adjusting elements;
a third beam control module coupled with the fifth and the sixth beam adjusting elements; and
a fourth beam control module coupled with the seventh and the eighth beam adjusting elements;
wherein when the first beam control module conducts the first and second beam adjusting elements, the third beam control module
does not conduct the fifth and sixth beam adjusting elements, and when the second beam control module conducts the third and
fourth beam adjusting elements, the fourth beam control module does not conduct the seventh and eighth beam adjusting elements;

wherein the first beam adjusting element has an equivalent current path of a length less than or equal to a total length of
an equivalent current path of the first radiation strip and an equivalent current path of the second radiation strip, but
a total length of an equivalent current path of the first beam adjusting element and an equivalent current path of the second
beam adjusting element is greater than the total length of the equivalent current path of the first radiation strip and the
equivalent current path of the second radiation strip.

US Pat. No. 9,355,604

OVERDRIVING CONTROL METHOD WITH IMAGE COMPRESSION CONTROL AND RELATED CIRCUIT

Realtek Semiconductor Cor...

1. An overdriving control method, comprising:
receiving an input image;
determining whether the input image is a moving image or a still image and generating a determining signal, wherein the determining
signal indicates the input image is the moving image or the still image;

using an image compression process dynamically according to the determining signal; and
using an overdriving process dynamically according to the determining signal;
wherein the step of step of using the image compression process dynamically according to the determining signal comprises:
according to the determining signal, when the input image is the moving image, performing the image compression process upon
the input image to generate a compressed image; and

according to the determining signal, when the input image is the still image, not performing the image compression process
upon the input image;

wherein the step of using the overdriving process dynamically according to the determining signal comprises:
according to the determining signal, when the input image is the moving image, performing the overdriving process with a first
compression rate upon the compressed image; and

according to the determining signal, when the input image is the still image, performing the overdriving process with a second
compression rate upon the input image;

wherein the first compression rate is greater than the second compression rate.

US Pat. No. 9,329,243

APPARATUS AND METHOD OF LED SHORT DETECTION

REALTEK SEMICONDUCTOR COR...

15. A method for detecting a status of a first light emitting diode (LED) string, wherein the first LED string comprises a
plurality of first LEDs connected in series and the first LED string is coupled to a high-voltage device, the method comprising:
providing a first current to the first LED string of a first external circuit via a first node and the high voltage device;
providing a control voltage to a control input of the high-voltage device to generate a first node voltage at the first node
according to the first current flowing through the first LED string; and

generating a first comparison result according to the first node voltage and a reference voltage; wherein the first comparison
result indicates whether the status of at least one of LEDs in the first LED string is short.

US Pat. No. 9,319,353

NETWORK TASK OFFLOAD APPARATUS AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A network task offload apparatus, comprising:
an offload circuit, for sequentially receiving a plurality of packets from a host and for simultaneously performing different
network processing tasks on each of the plurality of packets in parallel according to an offload command from the host; and

a buffer scheduler, coupled to the offload circuit, comprising:
a plurality of buffer units, for temporarily storing the plurality of packets during at least a time between time slots when
the offload circuit performs the different network processing tasks, respectively, wherein each of the plurality of buffer
units is used for temporary storage of a respective packet among the plurality of packets for all of the times between the
time slots for the different processing tasks corresponding to the respective packet, and for providing the respective processed
packet to a transmitter for transmission to a network;

wherein the offload circuit comprises an encryption unit, the encryption unit simultaneously performing the different network
processing tasks by simultaneously performing encryption tasks on each of the plurality of packets; and

wherein the encryption unit comprises at least one each of a data-link layer encryption unit, a network-layer encryption unit,
and a transport-layer encryption unit, wherein the encryption unit repeatedly access a first buffer unit of the plurality
of buffer units between the time slots to perform a transport-layer encryption for the first packet during a first time slot
of the time slots, followed by a network-layer encryption for the first packet during a second time slot of the time slots,
followed by a data-link layer encryption for the first packet during a third time slot of the time slots.

US Pat. No. 9,310,776

HIGH-SPEED ANALOG-TO-DIGITAL CONVERTER AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a comparator array comprising a first comparator configured to receive an input voltage and output a first polarity signal
indicating a polarity of the input voltage along with a first ready signal indicating the first polarity signal is ready in
accordance with a timing of a clock signal, and a second comparator configured to receive a first reference voltage and output
a second polarity signal indicating a polarity of the first reference voltage along with a second ready signal indicating
the second polarity signal is ready in accordance with the timing of the clock signal;

a time-to-digital converter configured to receive the first ready signal and the second ready signal and output a digital
signal indicating a relative timing between the first ready signal and the second ready signal; and

an output encoder configured to receive the first polarity signal and the digital signal and output an output data representing
an analog-to-digital conversion of the input voltage.

US Pat. No. 9,214,511

INTEGRATED INDUCTOR AND INTEGRATED INDUCTOR FABRICATING METHOD

Realtek Semiconductor Cor...

1. An integrated inductor, comprising:
a semiconductor substrate;
an inductor, formed above the semiconductor substrate; andonly one redistribution layer (RDL) of metal, formed above the inductor with a specific pattern to form a patterned ground
shield (PGS) that is grounded, wherein the RDL of metal comprises a plurality of metal strips, and wherein the semiconductor
substrate, the inductor, and the plurality of metal strips are within a semiconductor chip, and each of the metal strips has
an exposed surface from the semiconductor chip.

US Pat. No. 9,438,264

HIGH-SPEED CAPACITIVE DIGITAL-TO-ANALOG CONVERTER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a capacitor coupling a first circuit node to a second circuit node;
a first switch network circuit coupling the second circuit node to either a first reference voltage or a second reference
voltage in accordance with a value of a logical signal; and

a second switch network circuit coupling the second circuit node to a third reference voltage when the logical signal undergoes
a transition but decouple the second circuit node from the third reference voltage when the logical signal finishes the transition.

US Pat. No. 9,355,708

MEMORY CONTROL CIRCUIT FOR ADJUSTING REFERENCE VOLTAGE AND ASSOCIATED MEMORY CONTROL METHOD

Realtek Semiconductor Cor...

1. A memory control circuit, comprising:
a comparator arranged to compare a data signal with a reference voltage to generate a compared data signal;
an eye width measuring circuit, coupled to the comparator, arranged to measure an eye width of the compared data signal by
using a plurality of first clock signals with different phases to generate a measuring result; and

a calibration circuit, coupled to the comparator and the eye width measuring circuit, arranged to adjust a level of the reference
voltage according to the measuring result.

US Pat. No. 9,300,299

HIGH-SPEED INVERTER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a first CMOS (complementary metal oxide semiconductor) inverter comprising a first PMOS (p-channel metal oxide semiconductor)
transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, and a first resistor, configured to receive a first
signal and a second signal and output a third signal and a fourth signal, and

a second CMOS inverter comprising a second PMOS transistor, a second NMOS transistor, and a second resistor, configured to
receive the third signal and the fourth signal and output a fifth signal and a sixth signal, wherein:

the first PMOS transistor inverts a high-to-low transition of the first signal into a low-to-high transition of the fourth
signal;

the first NMOS transistor inverts a low-to-high transition of the second signal into a high-to-low transition of the third
signal;

the first resistor provides an isolation between the third signal and the fourth signal;
the second PMOS transistor inverts a high-to-low transition of the third signal into a low-to-high transition of the sixth
signal;

the second NMOS transistor inverts a low-to-high transition of the fourth signal into a high-to-low transition of the fifth
signal; and

the second resistor provides an isolation between the fifth signal and the sixth signal.

US Pat. No. 9,215,014

WIRELESS TRANSMISSION SYSTEM, AND METHOD FOR DETERMINING DEFAULT GAIN OF WIRELESS TRANSMISSION SYSTEM

Realtek Semiconductor Cor...

10. A wireless transmission system, comprising:
a signal transmission path, comprising:
a gain stage, having a plurality of transmission gains; and
a power amplification circuit;
a signal feedback path, coupled to the signal transmission path;
a control unit, for setting a gain of the gain stage as a specific transmission gain of the transmission gains;
a signal generation unit, coupled to the signal transmission path, the signal generation unit arranged for generating a plurality
of test signals, and transmitting the test signals through the signal transmission path in sequence to generate a plurality
of amplified test signals when the gain of the gain stage is set as the specific transmission gain, wherein at least a portion
of powers of the test signals correspond to the transmission gains, respectively; and

a signal processing unit, coupled to the signal feedback path, the signal processing unit arranged for receiving the amplified
test signals through the signal feedback path, accordingly obtaining corresponding signal gains, and determining a default
gain of the gain stage according to the signal gains.

US Pat. No. 9,136,963

WIRELESS TRANSMISSION APPARATUS AND RELATED WIRELESS TRANSMISSION METHOD

REALTEK SEMICONDUCTOR COR...

1. A wireless transmission apparatus for broadcasting packets to a plurality of receiving devices, the wireless transmission
apparatus comprising:
a transmitter for broadcasting first packets to the plurality of receiving devices;
a receiver for receiving signals transmitted from at least one of the receiving devices, the signals including at least a
receiving quality component representing the quality at which each of the receiving devices receives the first packets broadcasted
by the transmitter; and

an estimation circuit, coupled to the receiver, for determining, for each of the receiving devices, whether the receiving
device is suitable for receiving additional packets to be broadcast by the transmitter, the estimation circuit determining
whether the receiving device is suitable based on the receiving quality component and a signal quality threshold, the estimation
circuit further configured to designate each one of the receiving devices that is suitable for receiving the additional packets
to be broadcast by the transmitter as a target receiving device, the estimation circuit comprising:

a signal quality estimation circuit for generating a plurality of estimation results based on the signals transmitted from
the at least one of the receiving devices, each of the estimation results corresponding to the receiving quality component
of each receiving device for receiving the first packets broadcasted by the transmitter;

a control circuit, coupled to the signal quality estimation circuit, for determining whether each of the receiving devices
is a target receiving device or not based on the receiving quality component of the corresponding receiving device and the
signal quality threshold, wherein based on the control circuit determining that a number of ACK signals transmitted by at
least one of the target devices within a unit period changes, the control circuit adjusts a consecutive transmission frequency
transmission count to prompt adjustment of a signal quality component corresponding to a packet error ratio; and

a storage unit, coupled to the control circuit, for storing identification information of at least one of the target receiving
devices;

wherein the transmitter is configured to broadcast the additional packets to the target receiving devices;
wherein the control circuit determines whether at least one of the target receiving devices needs to receive the broadcasted
additional packets again according to the identification information and the receiving quality component of the at least one
of the target receiving devices; and

wherein the transmitter rebroadcasts the additional packets again if needed.

US Pat. No. 9,077,932

MULTIMEDIA SYSTEM, RELEVANT MULTIMEDIA INFORMATION DISPLAY DEVICE AND MULTIMEDIA INFORMATION TRANSMISSION METHOD

REALTEK SEMICONDUCTOR COR...

1. A multimedia information display device, comprising:
a first display device;
a human machine interface device;
a wireless communication device, configured to operably receive a multimedia content and a multimedia information, wherein
the multimedia content comprises a plurality of image frames, and the multimedia information comprises a plurality of instances;
and

a signal processing device, in a first interval, configuring the first display device to display a first image frame of the
multimedia content, a first instance of the multimedia information, and a progress indicator indicating a first progress of
displaying the first image frame; and in a second interval, configuring the first display device to display a second image
frame of the multimedia content, a second instance of the multimedia information, and the progress indicator indicating a
second progress of displaying the second image frame;

wherein the first instance comprises one or more information fields related to a first object of the first image frame, and
the first object comprises at least one of a character, an article, a sound, a scene, and a time of the first image frame;
and the second instance comprises one or more information fields related to a second object of the second image frame, and
the second object comprises at least one of a character, an article, a sound, a scene, and a time of the second image frame;
when the human machine interface device receives one or more input signals in the first interval, the signal processing device
configures the first display device to display the first image frame of the multimedia content, a third instance of the multimedia
information, and the progress indicator indicating the first progress of displaying the first image frame in a third interval
according to the one or more input signals; and the third instance comprises one or more information fields related to a third
object of the first image frame, and the third object comprises at least one of a character, an article, a sound, a scene,
and a time of the first image frame; the one or more input signals comprise at least one of a click input signal and a move
input signal performed on the human machine interface device when the first display device displays the first image frame,
the first instance, and the progress indicator in the first interval, and

wherein when a direction of the move input signal is parallel to the progress indicator in the first interval, the signal
progress device configures the first display device to display a third image frame of the multimedia content, a fourth instance
of the multimedia information, and the progress indicator indicating a third progress of displaying the third image frame;
the fourth instance comprises one or more information fields related to a fourth object of the third image frame, and the
fourth object comprises at least one of a character, an article, a sound, a scene, and a time of the third image frame; and
when the direction of the move input signal is vertical to the progress indicator in the first interval, the signal progress
device configures the first display device to display the first image frame of the multimedia content, the third instance
of the multimedia information, and the progress indicator indicating the first progress of displaying the first image frame.

US Pat. No. 9,391,583

TRANSMISSION LINE DRIVER CIRCUIT FOR AUTOMATICALLY CALIBRATING IMPEDANCE MATCHING

REALTEK SEMICONDUCTOR COR...

1. A transmission line driver circuit for automatically calibrating impedance matching, comprising:
a transmission line driving amplifier comprising a first transmission terminal and a second transmission terminal for providing
a pair of differential transmission signals;

a first signal node for coupling with a first load-end signal node of an equivalent load circuit;
a second signal node for coupling with a second load-end signal node of the equivalent load circuit;
a first adjustable resistor positioned on a signal path between the first transmission terminal and the first signal node;
a second adjustable resistor positioned on a signal path between the second transmission terminal and the second signal node;
a first signal difference generating circuit, coupled with two terminals of the first adjustable resistor, configured to operably
generate a first voltage difference value;

a second signal difference generating circuit, coupled with two terminals of the second adjustable resistor, configured to
operably generate a second voltage difference value;

a first sample-and-hold circuit, coupled with the first signal difference generating circuit, configured to operably conduct
a sample-and-hold operation on the first voltage difference value to generate a first sampled signal;

a second sample-and-hold circuit, coupled with the second signal difference generating circuit, configured to operably conduct
a sample-and-hold operation on the second voltage difference value to generate a second sampled signal;

a comparing circuit, coupled with the first sample-and-hold circuit and the second sample-and-hold circuit, configured to
operably compare the first sampled signal with the second sampled signal; and

an adjusting circuit, coupled with the first adjustable resistor, the second adjustable resistor, and the comparing circuit,
configured to operably adjust resistance of at least one of the first adjustable resistor and the second adjustable resistor
according to a comparing result of the comparing circuit.

US Pat. No. 9,384,836

CONTENT ADDRESSABLE MEMORY

REALTEK SEMICONDUCTOR COR...

1. A content addressable memory comprising:
a data memory cell for storing a data bit;
a mask memory cell for storing a mask bit; and
a comparing and readout unit connected to at least one read word line for receiving at least one read word signal, connected
to at least one function bit line for receiving a search bit signal, and connected to the data memory cell and the mask memory
cell for receiving the data bit and the mask bit, wherein said at least one function bit line includes a pair of search bit
lines;

wherein the data memory cell is connected to a data-use write word line for receiving a data-use write word signal, the mask
memory cell is connected to a mask-use write word line for receiving a mask-use write word signal, so as to decide whether
a write bit signal can be written into the data bit and the mask bit through a pair of write bit lines;

wherein the comparing and readout unit compares the data bit, the mask bit and the search bit signal, so as to determine whether
they match each other;

wherein the comparing and readout unit decides whether the data bit and the mask bit can be read out according to the at least
one read word signal; and

wherein the comparing and readout unit includes:
a first transistor stack connected to one of the pair of search bit lines for receiving the search bit signal, and connected
to the data memory cell and the mask memory cell for receiving the data bit and the mask bit; and

a second transistor stack connected to the other search bit line for receiving the search bit signal, and connected to the
data memory cell and the mask memory cell for receiving the data bit and the mask bit, wherein the first and second transistor
stacks compares the data bit, the mask bit and the search bit signal to produce a match signal;

a first transistor connected to the first transistor stack, the pair of search bit lines, and the at least one read word line
for receiving at least one read word signal; and

a second transistor connected to the second transistor stack, the pair of search bit lines, and the at least one read word
line for receiving at least one read word signal;

wherein the first and second transistors decides whether the data bit and the mask bit can be read out according to the at
least one read word signal.

US Pat. No. 9,269,130

IMAGE CORRECTION METHOD USING APPROXIMATELY NON-LINEAR REGRESSION APPROACH AND RELATED IMAGE CORRECTION CIRCUIT

Realtek Semiconductor Cor...

1. An image correction method, arranged for processing an original image to obtain a corrected image, wherein the original
image is a non-rectangular-shaped image, and the corrected image is a rectangular-shaped image, and the image correction method
comprising:
receiving the original image from an image sensor;
regarding each pixel of the original image, calculating a horizontal distance and a vertical distance between the pixel and
a reference point in the original image;

determining a horizontal ratio parameter and a vertical ratio parameter according to the horizontal distance and the vertical
distance between the pixel and the reference point in the original image;

performing an approximately non-linear regression calculation on the horizontal ratio parameter, the vertical ratio parameter
and a coordinate of the pixel to obtain a position of the pixel in the corrected image; and

determining a pixel value of the pixel of the corrected image by referring to a pixel value of the pixel of the original image.

US Pat. No. 9,251,872

ELECTRONIC DEVICE AND CONTROL METHOD FOR ELECTRONIC DEVICE

Realtek Semiconductor Cor...

1. An electronic device, comprising:
a memory unit;
a metal pad, coupled to the memory unit, and utilized for receiving a first signal and a second signal from the memory unit;
and

a control unit, coupled to the metal pad, and utilized for generating a control signal during a specific time period to control
the first signal and the second signal received by the metal pad, to pull up a level of the first signal and to pull down
a level of the second signal during the specific time period, so as to make the first signal and the second signal have a
voltage difference.

US Pat. No. 9,219,457

RECEIVER DEVICE AND METHOD FOR CONTROLLING AMPLIFICATION FACTOR THEREOF

REALTEK SEMICONDUCTOR COR...

1. A method for controlling amplification factor of a receiver device, comprising:
detecting a first variation of an equivalent length of a cable;
detecting a second variation of an amplification factor of a digital automatic gain controller (DAGC);
determining a first update value of an amplification factor of an analog automatic gain controller (AAGC) according to the
first variation and the second variation;

calculating a tuning ratio of the first update value to a current value of the amplification factor of the AAGC;
calculating a second update value of the amplification factor of the DAGC according to the tuning ratio;
updating a set value of the amplification factor of the AAGC based on the first update value; and
updating a set value of the amplification factor of the DAGC based on the second update value.

US Pat. No. 9,213,799

SYSTEMATIC DEFECT ANALYSIS METHOD AND MACHINE READABLE MEDIA

Realtek Semiconductor Cor...

1. A systematic defect analyzing method, comprising:
utilizing a processor to perform following steps:
receiving a plurality of physical features and a plurality of equivalence classes of suspected physical sites of a portion
or all of a chip;

partitioning physical sites into groups to obtain a plurality of groups of physical sites according to the plurality of physical
features of a chip corresponding to different potential systematic defects;

computing at least one defect probability of each group of physical sites; and
deriving an analysis result according to the plurality of defect probabilities corresponding to the plurality of groups of
physical sites, wherein the analysis result includes a trend result;

wherein the step of computing the defect probability of each of the groups of physical sites comprises:
according to the plurality of groups of physical sites and the plurality of equivalence classes of suspected physical sites
obtained through defect diagnosis, computing a defect probability of each group of physical sites of a site where an equivalence
class of a suspected physical site is located for each of the plurality of equivalence classes of suspected physical sites;
and

the step of deriving the analysis result according to the plurality of defect probabilities corresponding to the plurality
of groups of physical sites comprises:

computing a variance-within-group of each of the plurality of groups of physical sites according to the plurality of defect
probabilities;

deriving a simultaneous confidence intervals (SCI) between two neighboring physical sites of the plurality of physical sites
according to the plurality of defect probabilities and a plurality of variance-between-groups respectively corresponding to
the plurality of groups of physical sites, and further obtaining a plurality of SCIs; and

obtaining the trend result according to the plurality of SCIs.

US Pat. No. 9,112,582

NETWORK APPARATUS AND METHOD FOR ELIMINATING INTERFERENCE BETWEEN TRANSPORT PORTS

Realtek Semiconductor Cor...

1. A network apparatus, comprising: a plurality of transport ports; a plurality of seed comparators, coupled to the plurality
of transport ports,
respectively, wherein a first seed comparator of the plurality of seed comparators is utilized for comparing a first seed
of a first transport port with a second seed of a second transport port and accordingly generating a comparing result; and

a control unit, coupled to the first seed comparator, for generating a control signal to cancel interference between the plurality
of transport ports according to the comparing result, and determining whether to stop updating a parameter of a near-end crosstalk
cancellation of the network apparatus and whether to enable a cross-port cancellation of the network apparatus according to
the comparing result,

wherein each of the plurality of transport ports comprises:
a cross-port canceller, coupled to the control unit, for canceling the interference between the plurality of transport ports
according to the comparing result; and

at least one near-end crosstalk (NEXT) canceller, coupled to the control unit, for canceling near-end crosstalk from other
channels of the transport port that is different from a specific channel of the transport port;

wherein the control unit stops updating a parameter of the NEXT canceller and enables the cross-port canceller when the comparison
result indicates that a time distance between the first seed and the second seed is less than a threshold, and the control
unit re-enables a parameter updating mechanism of the NEXT canceller when the comparison result indicates that the time distance
between the first see and the second seed is larger than the threshold.

US Pat. No. 9,100,233

BINARY SIGNAL DETECTION BASED ON NON-UNIFORM ADC

REALTEK SEMICONDUCTOR COR...

1. An apparatus comprising:
a linear equalizer for receiving an input signal and outputting a partly equalized signal;
a VGA (variable gain amplifier) for receiving the partly equalized signal and outputting an amplitude-adjusted signal in accordance
with a gain control signal;

a non-uniform ADC for receiving the amplitude-adjusted signal and outputting a digitized signal, the digitized signal comprising
digitized levels that are non-uniformly displaced; and

a DSP (digital signal processing) circuit for receiving the digitized signal and outputting a recovered bit stream by performing
a signal detection and establishing the gain control signal by performing automatic gain control, wherein the non-uniform
ADC has a lower precision when a level of the amplitude-adjusted signal is sufficiently close to an ideal level corresponding
to a logical “1” datum, sufficiently close to an ideal level corresponding to a logical “0” datum, or sufficiently different
from a middle level of an ideal level corresponding to a logical “1” datum and an ideal level corresponding to a logical “0”
datum, and the non-uniform ADC has a higher precision when the level of the amplitude-adjusted signal is sufficiently close
to the middle level.

US Pat. No. 9,331,652

AUTO GAIN ADJUSTING DEVICE AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An automatic gain adjusting device, comprising:
a predistorter for generating a plurality of test signals in a calibration mode, wherein the powers between a current test
signal and a previous test signal includes a first difference value;

a gain unit for providing a substantially constant gain value to the current test signal and the previous test signal to generate
a current amplified test signal and a previous amplified test signal;

a power amplifier for amplifying the current amplified test signal and the previous amplified test signal to generate a first
transmitting signal and a second transmitting signal;

a receiving unit for converting the first transmitting signal and the second transmitting signal into a first baseband signal
and a second baseband signal respectively; and

a calculation unit for calculating a second difference value between powers of the first baseband signal and the second baseband
signal and comparing the second difference value with the first difference value to determine whether the substantially constant
gain value causes the plurality of test signals to be operated in a linear region and a compression region of the power amplifier.

US Pat. No. 9,215,109

METHOD FOR EQUALIZING TRANSMISSION SPECTRUM OF A WIRELESS COMMUNICATION TRANSMITTER

REALTEK SEMICONDUCTOR COR...

1. A method for equalizing a transmission spectrum of a wireless communication transmitter, comprising:
providing a plurality of single-frequency signals;
respectively inputting the plurality of single-frequency signals into the transmitter,
wherein each single-frequency signal has a predetermined frequency and all the predetermined frequencies are different from
each other;

loopbacking the plurality of single-frequency signals to an analog to digital converter so as to generate a plurality of digital
loopback signals;

calculating a frequency response of the transmitter at a base band circuit according to the plurality of digital loopback
signals; and

equalizing the transmission spectrum of the transmitter according to the frequency response of the transmitter;
wherein the method is for the Wi-Fi wireless local area network;
wherein each of the single-frequency signals has a frequency selected from the group consisting of 5MHz, 40MHz, 80MHz, -5MHz,
-40MHz and -80MHz.

US Pat. No. 9,158,697

METHOD FOR CLEANING CACHE OF PROCESSOR AND ASSOCIATED PROCESSOR

Realtek Semiconductor Cor...

1. A method for cleaning a cache of a processor, wherein the cache comprises a plurality of cache lines, each cache line contains
a plurality of segments, and the method comprises:
generating a specific command according to a request, wherein the specific command comprises an operation command, a first
field and a second field, and the operation command comprises a “write-back” command;

obtaining an offset and a starting address according to the first field and the second field;
selecting a specific segment from the cache according to the starting address and the offset; and
writing data stored in the specific segment back to a memory in response to the “write-back” command.

US Pat. No. 9,356,837

ELECTRONIC DEVICE HAVING NETWORK AUTO-SWITCHING FUNCTIONS AND NETWORK AUTO-SWITCHING METHOD UTILIZED IN ELECTRONIC DEVICE

Realtek Semiconductor Cor...

1. An electronic device having network auto-switching functions, comprising:
a first network connecting unit, having a first network transmission specification;
a second network connecting unit, having a second network transmission specification different from the first network transmission
specification;

a detecting unit, coupled to the first network connecting unit and the second network connecting unit, for detecting network
connecting statuses of the first network connecting unit and the second network connecting unit to generate a detecting result;

a network access unit, coupled to the detecting unit, the first network connecting unit, and the second network connecting
unit, for determining to select the first network connecting unit or the second network connecting unit to perform a network
connecting operation or to not perform the network connecting operation at least according to the detecting result; and

a processing unit, coupled to the network access unit, for adjusting at least one network setting parameter of the network
access unit;

wherein the network access unit determines to select the first network connecting unit or the second network connecting unit
to perform the network connecting operation or to not perform the network connecting operation according to the detecting
result and the at least one network setting parameter, and the at least one network setting parameter comprises: a current
connection priority parameter, a priority selecting connection parameter, and a fixed selecting connection parameter; when
the current connection priority parameter has a first current connection priority setting value, the network access unit will
not select the current selected first network connecting unit or the current selected second network connecting unit with
priority; when the current connection priority parameter has a second current connection priority setting value, the network
access unit will select the current selected first network connecting unit or the current selected second network connecting
unit with priority; when the priority selecting connection parameter has a first priority selecting connection setting value,
the network access unit will select the first network connecting unit with priority; when the priority selecting connection
parameter has a second priority selecting connection setting value, the network access unit will select the second network
connecting unit with priority; when the fixed selecting connection parameter has a first fixed selecting connection setting
value, the network access unit will select the first network connecting unit fixedly; and when the fixed selecting connection
parameter has a second fixed selecting connection setting value, the network access unit will select the second network connecting
unit fixedly;

when the network access unit determines to select the first network connecting unit or the second network connecting unit
to perform the network connecting operation or to not perform the network connecting operation according to the detecting
result, the current connection priority parameter, and the priority selecting connection parameter, and the current connection
priority parameter and the priority selecting connection parameter respectively has the first current connection priority
setting value and the first priority selecting connection setting value, if the first network connecting unit and the second
network connecting unit both are capable of connecting network, then the network access unit will select the first network
connecting unit to perform the network connecting operation; if the first network connecting unit is capable of connecting
network and the second network connecting unit is not capable of connecting network, then the network access unit will select
the first network connecting unit to perform the network connecting operation; if the first network connecting unit is not
capable of connecting network and the second network connecting unit is capable of connecting network, then the network access
unit will select the second network connecting unit to perform the network connecting operation; and if the first network
connecting unit and the second network connecting unit are not capable of connecting network, then the network access unit
will select to not perform the network connecting operation.

US Pat. No. 9,232,598

OPERATING CIRCUIT APPLIED TO BACKLIGHT AND ASSOCIATED METHOD

Realtek Semiconductor Cor...

1. An operating circuit applied to a backlight, wherein the backlight comprises at least one lighting element, the lighting
element comprises at least one lighting unit, and the operating circuit comprises:
at least one current control circuit, coupled to the lighting element, for controlling a current of the lighting element,
wherein the current control circuit comprises:

a first transistor having a gate, a first electrode and a second electrode, wherein the first electrode is coupled to the
lighting element, and the second electrode is coupled to a resistor;

an operational amplifier having a positive input terminal, a negative input terminal, a positive output terminal and a negative
output terminal; and

a switch module, coupled between the first transistor, the operational amplifier and a reference voltage, for switching a
connection relationship between the positive input terminal, the negative input terminal, the reference voltage and the second
electrode of the first transistor, and for switching a connection relationship between the positive output terminal, the negative
output terminal and the gate of the first transistor to make the close loop form a negative feedback, and the current of the
lighting element not influenced by an offset voltage of the operational amplifier.

US Pat. No. 9,083,319

OSCILLATOR AND CONTROL METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An oscillator, comprising:
an oscillation unit configured to receive a first current and to generate an oscillating signal according to the first current;
a frequency-to-voltage converter comprising at least one switch and a current source, the frequency-to-voltage converter being
configured to receive the oscillating signal, the frequency-to-voltage converter being configured to generate a converted
voltage according to a varied frequency of the oscillating signal, the frequency-to-voltage converter comprising a controller
configured to detect the oscillating signal and reduce the converted voltage while maintaining oscillation of the oscillating
signal by enabling one of a plurality of combinations of current sources; and

a voltage-to-current converter to receive the converted voltage and to generate the first current according to the converted
voltage;

wherein the voltage-to-current converter is configured to modulate the first current from a first value to a second value
after the initiation of the oscillation unit, wherein the oscillation unit comprises an inverter with a transconductance within
an oscillation range that enables oscillation, wherein the first value and the second value of the first current correspond
to transconductance values within the oscillation range.

US Pat. No. 9,723,638

METHOD FOR ESTABLISHING NETWORKING CONNECTION

REALTEK SEMICONDUCTOR COR...

1. A method for establishing a networking connection between a wireless communication device and a wireless access point,
the method comprising:
utilizing a mobile communication device to wirelessly communicate with the wireless access point to establish a networking
connection between the mobile communication device and the wireless access point;

utilizing the mobile communication device to encode a profile of a wireless local area network (WLAN) corresponding to the
wireless access point to generate one or more profile encoded packets without communicating with the wireless communication
device in advance;

utilizing the mobile communication device to transmit the one or more profile encoded packets;
utilizing the wireless communication device to receive the one or more profile encoded packets;
utilizing the wireless communication device to parse the one or more profile encoded packets to obtain the profile of the
WLAN; and

utilizing the wireless communication device to connect to the wireless access point according to the profile of the WLAN to
establish a networking connection between the wireless communication device and the wireless access point.

US Pat. No. 9,252,994

NETWORK APPARATUS AND NETWORK SIGNAL PROCESSING METHOD

REALTEK SEMICONDUCTOR COR...

1. A network apparatus, for processing a network signal and outputting an output signal, the network apparatus comprising:
an asynchronous signal processing module, operating in an asynchronous domain, for receiving and processing the network signal
to generate a first processed signal;

a sampling rate converter, coupled to the asynchronous signal processing module, for performing sampling rate conversion on
the first processed signal generated from the asynchronous signal processing module to generate a first converted signal;
and

a synchronous signal processing module, operating in a synchronous domain, for processing the first converted signal to generate
the output signal; wherein the asynchronous signal processing module has a first operating frequency, the synchronous signal
processing module has a second operating frequency, and the first operating frequency is different from the second operating
frequency.

US Pat. No. 9,147,675

INTEGRATED CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. An integrated circuit (IC), comprising:
a packaging body;
a plurality of interface connectors, disposed on an outer surface of the packaging body;
a functional chip, comprising:
a first power pad, connected electrically to a first one of the interface connectors;
a first ground pad, connected electrically to a second one of the interface connectors;
a first signal pad; and
an electronic functional circuit, connected electrically to the first power pad, the first signal pad, and the first ground
pad; and

an Electrostatic Discharge (ESD) protection chip, comprising:
a second signal pad, connected electrically between a third one of the interface connectors and the first signal pad; and
a first ESD protection circuit, connected electrically to the second signal pad;
wherein the functional chip is formed using process technology different from that of the ESD protection chip.

US Pat. No. 9,391,633

DIGITAL-TO-ANALOG CONVERTER FOR REDUCING POP NOISE AND HARMONIC TONE AND RELATED CONVERTING METHOD

REALTEK SEMICONDUCTOR COR...

1. An apparatus for converting a digital audio signal into an analog audio signal, the apparatus comprising:
a first circuit configured to receiving the digital audio signal and converting the digital audio signal into an N-bit sigma-delta
modulation signal, wherein N is larger than 1;

a multiplexer, for receiving the N-bit sigma-delta modulation signal and a zero signal, and selectively outputting the N-bit
sigma-delta modulation signal or the zero signal as an output signal according to a selection signal;

a low-pass filter, coupled to the multiplexer, for generating a filtered output signal according to the output signal, wherein
the filtered output signal is a pulse-code modulation (PCM) signal; and

a digital-to-analog converter, coupled to the low-pass filter, for generating the analog audio signal according to the filtered
output signal.

US Pat. No. 9,137,743

METHOD AND MOBILE DEVICE FOR AUTOMATICALLY CHOOSING COMMUNICATION NETWORK

REALTEK SEMICONDUCTOR COR...

1. A method for automatically choosing a communication network, comprising:
receiving a communication request from a user interface;
determining a status of a network card module according to the communication request by a processing unit;
sending a network packet through the network card module and receiving a response packet corresponding to the network packet
to determine whether the network card module is connected to the Internet;

sending a first inquiry packet to a voice over Internet protocol (VoIP) proxy server by the network card module and receiving
a first response packet corresponding to the first inquiry packet to determine whether a contact corresponding to the communication
request is online; and

sending a second inquiry packet to the VoIP proxy server by the network card module and receiving a second response packet
corresponding to the second inquiry packet to determine whether a balance in a VoIP account of a user is positive when the
contact is offline;

wherein the communication request is carried out through the VoIP proxy server by the network card module when the contact
is online or the balance in the VoIP account is positive, whereas the communication request is carried out by a cellular phone
module when the network card module is not installed, the network card module is not enabled, the network card module is not
connected to the Internet, or the balance in the VoIP account is not positive.

US Pat. No. 9,099,463

LAYOUT STRUCTURE AND VERSION CONTROL CIRCUIT FOR INTEGRATED CIRCUITS

Realtek Semiconductor Cor...

1. A layout structure for integrated circuits, comprising:
a signal-supplying unit, receiving a first signal and converting said first signal to a second signal; and
at least a transfer cell, connected electrically to said signal-supplying unit, said signal-supplying unit supplying said
first signal or said second signal to said transfer cell, said transfer cell having a first transfer path and a second transfer
path, each of said first transfer path and said second transfer path having a plurality of metal layers interconnected in
series, said first transfer path connected electrically to said second transfer path in series;

wherein when said first signal transferred by said transfer cell is changed to said second signal, one metal layer of said
first signal transfer path is interrupted to interrupt transferring of said first signal, and one metal layer of said second
signal transfer path receiving and outputting said second signal.

US Pat. No. 9,385,859

MULTI-LANE SERIAL DATA LINK RECEIVER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An apparatus comprising:
a multi-lane receiver for concurrently receiving plural bit streams clocked according to a common clock source, the multi-lane
receiver comprising:

a first equalizer for receiving a first received signal of the plural bit streams and outputting a first equalized signal;
a second equalizer for receiving a second received signal of the plural bit streams and outputting a second equalized signal;
an analog CDR (clock-data recovery) circuit for receiving the first equalized signal and outputting a first recovered bit
stream and a first recovered clock generated in accordance with an analog control voltage; and

a digital CDR circuit for receiving the second equalized signal and the first recovered clock and outputting a second recovered
bit stream and a second recovered clock based on selecting a phase of the first recovered clock in accordance with a digital
phase selection signal.

US Pat. No. 9,137,522

DEVICE AND METHOD FOR 3-D DISPLAY CONTROL

REALTEK SEMICONDUCTOR COR...

1. A control device for a three dimensional display device, comprising:
an image processor, for receiving a first and a second input image frame signals to generate a first, a second, and a third
output image frame signals; and

a timing signal generator, for generating a timing control signal corresponding to the first, the second, and the third output
image frame signals;

wherein the first output image frame signal comprises at least part of the first input image frame signal; the second output
image frame signal comprises at least part of the first input image frame signal and at least part of the second input image
frame signal; and the third output image frame signal comprises at least part of the second input image frame signal;

wherein the timing control signal comprises a first lens control signal for configuring a first lens of a pair of shutter
glasses to be non-opaque when the second output image frame signal is displayed on the three dimensional display device, and
a second lens control signal for configuring a second lens of the shutter glasses to be non-opaque when the third output image
frame signal is displayed on the three dimensional display device.

US Pat. No. 9,128,719

CONTROLLING CIRCUIT WITH POWER SAVING MECHANISM AND METHOD THEREOF

Realtek Semiconductor Cor...

1. A controlling circuit with a power saving mechanism, comprising:
a transmitting interface, arranged to perform a signal transmission with a specific controlling circuit;
a setting unit, coupled to the transmitting interface, arranged to control the specific controlling circuit to operate in
the power saving mechanism; and

a counter, arranged to count a number of times off-link occurs between the controlling circuit and the specific controlling
circuit after the setting unit forces the transmitting interface to perform the power saving mechanism;

wherein the controlling circuit has no Auto-negotiation (NWAY) mechanism; after the transmitting interface links to the specific
controlling circuit, the setting unit further forces the transmitting interface to perform the power saving mechanism; and
the setting unit further decides whether to disable the power saving mechanism or not according to the number of times off-link
occurs, and when the number of times off-link occurs reaches a predetermined number, the setting unit disables the power saving
mechanism.

US Pat. No. 9,060,399

OPERATING CIRCUIT APPLIED TO BACKLIGHT AND ASSOCIATED METHOD

Realtek Semiconductor Cor...

1. An operating circuit applied to a backlight, wherein the backlight comprises a plurality of lighting elements, each of
the lighting elements comprises at least one lighting unit, and the operating circuit comprises:
a plurality of current control circuits, coupled to the plurality of lighting elements via a plurality of nodes, respectively;
a plurality of switches, coupled to the plurality of nodes, respectively;
a minimum voltage selector, coupled to the plurality of switches, for receiving at least a portion of voltages of the plurality
of nodes, and selecting a minimum voltage among the received voltages;

a supply voltage generating circuit, coupled to the minimum voltage selector, for generating a supply voltage of the plurality
of lighting elements according to the minimum voltage; and

a control unit, coupled to the plurality of switches and the supply voltage generating circuit, wherein for each of the switches,
the control unit determines an on/off state of the switch by determining whether the corresponding lighting element is an
open circuit or not;

wherein the control circuit comprises:
a plurality of second comparators, for generating a plurality of switch control signals by comparing the voltages of the plurality
of nodes with a second reference voltage, respectively; and

a first comparator, for determining whether to enable the plurality of second comparators or not by detecting if the supply
voltage is greater than a first reference voltage, wherein when the supply voltage is greater than the first reference voltage,
the second comparators are enabled; and when the supply voltage is not greater than the first reference voltage, the second
comparators are disabled;

wherein the plurality of switch control signals are utilized for switching on or switching off the plurality of switches,
respectively.

US Pat. No. 9,214,898

TRIPLE CASCODE POWER AMPLIFIER

REALTEK SEMICONDUCTOR COR...

1. A triple cascode power amplifier, comprising:
a first-stage transistor pair comprising two first-stage transistors that respectively receive two dynamic bias voltages with
opposite polarities;

a second-stage transistor pair coupled with the first-stage transistor pair to four a first node, the second-stage transistor
pair comprising two second-stage transistors coupled with each other to form a second node; and

a third-stage transistor pair coupled with the second-stage transistor pair, the third-stage transistor pair comprising two
third-stage transistors for outputting a differential signal;

wherein the first-stage transistor pair and the second-stage transistor pair are low voltage components while the third-stage
transistor pair is a high voltage component; and

wherein the power amplifier transforms the differential signal into a single-ended signal for output; and
a control circuit for generating a control signal at the second node to control a voltage at the first node with respect to
a ground within a predetermined range;

wherein the control circuit comprises:
an operational amplifier, a first input terminal of which receives a first voltage and an output terminal of which generates
the control signal;

a first current source for supplying a current;
a second transistor, a gate of which is coupled with the output terminal of the operational amplifier to form a third node,
a drain of which is coupled with the first current source and a source of which is coupled with a second input terminal of
the operational amplifier to form a fourth node; and

a first transistor, a drain of which is coupled with the fourth node and a source of which is grounded;
wherein the second node is coupled to the third node;
wherein amplification coefficients of the first transistor and the first-stage transistors are proportional and amplification
coefficients of the second transistor and the second-stage transistors are proportional; and

wherein a voltage at the first node varies according to a voltage at the fourth node.

US Pat. No. 9,214,945

DIGITAL PHASE LOCK LOOP AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An apparatus comprising:
an analog-to-digital converter (ADC) configured to convert a voltage level of an output clock into a first digital word in
accordance with a timing defined by a reference clock;

a first digital loop filter configured to receive the first digital word and outputting a control code, wherein the first
digital loop filter comprises a digital integrator;

a circuit to receive the reference clock and the output clock and output an offset code according to a frequency error of
the output clock with respect to a frequency of the reference clock;

an adder for generating an offset control code by summing the control code with the offset code; and
a digitally controlled oscillator for outputting the output clock in accordance with the offset control code.

US Pat. No. 9,152,237

POWER BOUNCING REDUCTION CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a core circuit for sinking a first current from a first internal power supply node;
a power bouncing reduction circuit receiving power from a second internal power supply node and sourcing a second current
to the first internal power supply node in accordance with a comparison between a voltage at the first internal power supply
node and a low-pass filtered voltage of the first internal power supply node; and

a package coupling the first internal power supply node and the second internal power supply node to a first external power
supply node and a second external power supply node, respectively.

US Pat. No. 9,077,843

VIDEO PLAYBACK SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT FOR JOINTLY DISPLAYING VIDEO WITH MULTIPLE SCREENS

REALTEK SEMICONDUCTOR COR...

1. A video playback system for jointly displaying video with multiple screens, comprising:
multiple portable communication devices each comprising at least one of the multiple screens, wherein the multiple portable
communication devices comprise a first portable communication device having a first screen, and the first screen is one of
the multiple screens;

a location detection circuit, configured to dynamically detect a spatial location and an orientation for each of the multiple
portable communication devices; and

a multi-screen display controlling server, configured to operably establish a device group relationship among the multiple
portable communication devices, to dynamically generate multiple partitioned videos respectively corresponding to multiple
non-overlap image areas of a target video according to detection results of the location detection circuit, and to respectively
transmit the multiple partitioned videos to the multiple portable communication devices;

wherein a relative position among the multiple image areas matches with a relative position among the multiple portable communication
devices;

wherein the multi-screen display controlling server controls the multiple portable communication devices to respectively display
the multiple partitioned videos on the multiple screens to jointly display at least a portion of a visible area of the target
video;

wherein when a location or orientation of the first portable communication device changes, the multi-screen display controlling
server dynamically generates an adjusted partitioned video according to a new location or orientation of the first portable
communication device, and controls the first portable communication device to display the adjusted partitioned video on the
first screen;

wherein while the multiple screens display the multiple partitioned videos, if the location of the first portable communication
device is changed to change a distance between the first portable communication device and the location detection circuit,
the first portable communication device generates a video scaling command; and

wherein while the multiple screens display the multiple partitioned videos, if the multi-screen display controlling server
received the video scaling command generated by the first portable communication device, the multi-screen display controlling
server dynamically generates multiple adjusted partitioned videos respectively corresponding to the multiple image areas and
controls the multiple portable communication devices to respectively display the multiple adjusted partitioned videos on the
multiple screens to jointly present executing result of the video scaling command.

US Pat. No. 9,570,130

MEMORY SYSTEM AND MEMORY PHYSICAL LAYER INTERFACE CIRCUIT

REALTEK SEMICONDUCTOR COR...

1. A memory physical layer interface circuit electrically connected between a memory controller and a memory device, wherein
the memory physical layer interface circuit comprises:
a clock generation module to generate a reference clock signal and a plurality of output related clock signals, wherein the
reference clock signal is transmitted to the memory device; and

a plurality of first-in-first-out (FIFO) modules where each of the FIFO modules is to write an input information therein transmitted
by the memory controller according to a write-related clock signal and to retrieve the input information therefrom according
to one of the output related clock signals to generate an output signal and to transmit the output signal to the memory device
to operate the memory device, wherein the write-related clock signal is generated by dividing a frequency of one of the output
related clock signals.

US Pat. No. 9,621,785

PASSIVE AUTO-FOCUS DEVICE AND METHOD

REALTEK SEMICONDUCTOR COR...

1. A passive auto-focus device, comprising:
a scene variation detecting circuit operable to determine a range of a variation area of a current scene by comparing image
record(s) of information block(s) of the current scene with image record(s) of information block(s) of a preceding scene;

a focus-searching-range decision circuit operable to compare the range of the variation area of the current scene with a predetermined
range so as to determine a focus-searching range, in which the variation area of the current scene is defined according to
the comparison between the current scene and the preceding scene;

a focal-distance-variation decision circuit operable to generate a current step setting value according to the focus-searching
range or by comparing the definition pertaining to the focus-searching range with a first predetermined definition; and

an image record generating circuit operable to generate a plurality of first step image records in connection with the focus-searching
range when the current step setting value indicates a first step, and generate a plurality of second step image records in
connection with the focus-searching range when the current step setting value indicates a second step, in which the first
step is shorter than the second step.

US Pat. No. 9,729,121

LC TANK CAPABLE OF REDUCING ELECTROMAGNETIC RADIATION BY ITSELF AND MANUFACTURING METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An inductance-capacitance (LC) tank capable of reducing electromagnetic radiation by itself, comprising:
a plurality of tank areas including:
a first tank area whose boundary is defined by a first part of an inductance; and
a second tank area whose boundary is defined by a second part of the inductance in which the second part includes a gap;
a cross-interconnection structure operable to electrically connect the first and second parts of the inductance and distinguish
the first tank area from the second tank area; and

at least one capacitance being inside at least one of the plurality of tank areas,
wherein the area ratio of the first tank area to the second tank area is between 20% and 80%.

US Pat. No. 9,503,078

METHOD AND APPARATUS FOR CHARGE TRANSFER

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a first capacitor;
a second capacitor;
a MOS (metal oxide semiconductor) transistor;
an operational amplifier, wherein the first capacitor is configured to couple to the second capacitor via the MOS transistor;
the operational amplifier is configured to receive a voltage at the first capacitor and output a control voltage; and the
MOS transistor is configured to be controlled by the control voltage;

a third capacitor;
a fourth capacitor; and
a second MOS (metal oxide semiconductor) transistor, wherein: the third capacitor is configured to couple to the fourth capacitor
via the second MOS transistor; the operational amplifier is configured to receive a voltage at the third capacitor and output
a second control voltage; and the second MOS transistor is configured to be controlled by the second control voltage.

US Pat. No. 9,780,162

INTEGRATED INDUCTOR

REALTEK SEMICONDUCTOR COR...

1. An integrated inductor, comprising:
a patterned ground shield disposed in a first direction;
an inner rail coupled to the patterned ground shield, and disposed inside the integrated inductor and in a second direction,
wherein the first direction is perpendicular to the second direction, wherein the inner rail extends upward from the patterned
ground shield in a perpendicular manner; and

an inductor disposed above the patterned ground shield;
wherein the inner rail is not part of the inductor.

US Pat. No. 9,748,325

INTEGRATED INDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

REALTEK SEMICONDUCTOR COR...

1. An integrated inductor structure, comprising:
a capacitor;
a guard ring coupled to the capacitor;
a patterned shield, comprising:
a first patterned shield portion disposed in a first metal layer, connected to the capacitor, and coupled to the guard ring
through the capacitor, thereby floating the patterned shield; and

a second patterned shield portion disposed in a second metal layer and connected to the guard ring, wherein the second metal
layer is above and separated from the first metal layer; and

an inductor disposed above the guard ring and the patterned shield.

US Pat. No. 9,742,368

DRIVER

REALTEK SEMICONDUCTOR COR...

1. A driver, suitable for driving a power amplifier, wherein the driver comprises:
a voltage buffer circuit, configured to receive an input signal, to buffer the input signal, and to output a first output
signal; and

a voltage transforming circuit, configured to receive the first output signal and to output a second output signal to the
power amplifier, wherein an equivalent inductance of the voltage transforming circuit and an input capacitance of the power
amplifier are arranged to make the voltage buffer circuit have a voltage gain approximated to 1.

US Pat. No. 9,859,911

SUCCESSIVE APPROXIMATION REGISTER ANALOG-TO-DIGITAL CONVERTER AND ANALOG-TO-DIGITAL SIGNAL CONVERSION METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A successive approximation register (SAR) analog-to-digital converter (ADC), comprising:
a digital-to-analog converter (DAC), comprising N capacitors whose capacitance values are substantially the same, generating
an analog signal, N being an integer greater than two;

a SAR, comprising N memory units, wherein said N memory units are respectively coupled to said N capacitors, each said memory
unit stores a control value, and N terminal voltages of said N capacitors are respectively controlled by said N control values;

a write control unit, coupled to said N memory units, generating a write-enable signal, according to which M memory units
of said N memory units and M capacitors corresponding to said M memory units are selected, wherein M is a positive integer
smaller than N; and

a comparator, coupled to said DAC and said N memory units, generating a comparison value according to said analog signal;
wherein, said M control values of said M memory units change in correspondence to said comparison value.

US Pat. No. 9,853,169

STACKED CAPACITOR STRUCTURE

REALTEK SEMICONDUCTOR COR...

1. A stacked capacitor structure, comprising:
a MOS (Metal-Oxide-Semiconductor) varactor, comprising:
a substrate having a well;
a gate positioned on the well; and
a first source/drain and a second source/drain formed in the well and positioned at opposing sides of the gate;
a stacked capacitor electrically connected to the MOS varactor, wherein the stacked capacitor comprises a plurality of metal
layers spaced from each other, stacked above the gate, and positioned below an inductive element, wherein each first metal
layer of the metal layers above the gate serves as a first capacitor electrode, and each second metal layer of the metal layers
above the gate serves as a second capacitor electrode, wherein the each first metal layer and the each second metal layer
are alternately arranged; and

a first switch having one terminal electrically connected to an anode, and another terminal electrically connected to the
second capacitor electrode.

US Pat. No. 9,571,916

AUDIO CODEC WITH AUDIO JACK DETECTION FUNCTION AND AUDIO JACK DETECTION METHOD

Realtek Semiconductor Cor...

1. An audio codec with an audio jack detection function, which is operable to connect with a plug and comprises:
a first-contact signal input end operable to electrically connect with a sleeve contact of the plug and receive a first-contact
signal indicating the presence or absence of the plug;

a second-contact signal input end operable to electrically connect with a ring contact or the sleeve contact of the plug and
receive a second-contact signal indicating the presence or absence of the plug;

a plug detecting circuit operable to detect whether a voltage level of the first-contact signal has changed when the plug
detecting circuit is coupled to the first-contact signal input end, or detect whether a voltage level of the second-contact
signal has changed when the plug detecting circuit is coupled to the second-contact signal input end, and accordingly generate
a plug detection signal;

a control circuit operable to determine the presence or absence of the plug in accordance with the plug detection signal;
and

a switch coupled between the second-contact signal input end and a ground level if the plug detecting circuit generates the
plug detection signal according to the first-contact signal, or coupled between the first-contact signal input end and the
ground level if the plug detecting circuit generates the plug detection signal according to the second-contact signal,

wherein if the control circuit determines the absence of the plug, the control circuit keeps the switch on; and if the control
circuit determines the presence of the plug, the control circuit turns off the switch.

US Pat. No. 9,270,391

CALIBRATION METHOD PERFORMING SPECTRUM ANALYSIS UPON TEST SIGNAL AND ASSOCIATED APPARATUS FOR COMMUNICATION SYSTEM

Realtek Semiconductor Cor...

1. A calibration method for a communication system, comprising:
generating a test signal at a transmitter;
configuring at least one calibration coefficient at the transmitter;
transmitting the test signal from the transmitter to a receiver via the at least one calibration coefficient;
performing a spectrum analysis upon the test signal received by the receiver to generate a spectrum analysis result;
adjusting the test signal according to the spectrum analysis result; and
adjusting the at least one calibration coefficient according to the spectrum analysis result in order to calibrate the transmitter;
wherein when the spectrum analysis result indicates a power of the received test signal is less than a predetermined power,
the transmitter is notified to increase the power of the test signal; and when the spectrum analysis result indicates a plurality
of harmonic powers of the test signal are higher than the background noise, the transmitter is notified to decrease the power
of the test signal.

US Pat. No. 9,104,367

MULTIMEDIA INTERACTION SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT CAPABLE OF AVOIDING UNEXPECTED INTERACTION BEHAVIOR

REALTEK SEMICONDUCTOR COR...

1. A multimedia interaction system having multiple displays, comprising:
a plurality of electronic devices;
a plurality of displays, respectively arranged on the electronic devices; and
a location detection circuit, configured to dynamically detect a spatial location and an orientation for each of the electronic
devices, and configured to transmit information related to detection results to at least one of the electronic devices through
a wireless communication approach;

wherein when a user instructs a source electronic device of the electronic devices to transmit a target image object toward
a target direction, the source electronic device determines whether a relative position between a candidate electronic device
of other electronic devices and the target direction satisfies a predetermined condition, and only if the relative position
between the candidate electronic device and the target direction satisfies the predetermined condition, the source electronic
device transmits a target command corresponding to the target image object to the candidate electronic device, so that the
candidate electronic device utilizes a corresponding candidate display to perform a multimedia operation corresponding to
the target image object according to the target command;

wherein the location detection circuit detects and transmits spatial coordinates of multiple transmitting-end reference points
of the source electronic device to the source electronic device, and the location detection circuit detects and transmits
spatial coordinates of multiple receiving-end reference points of the candidate electronic device to the candidate electronic
device; and

wherein the source electronic device computes a central location of a first multimedia interaction program window displayed
on the source display according to the spatial coordinates of the transmitting-end reference points to represent a spatial
location of the source electronic device, and the candidate electronic device computes a central location of a second multimedia
interaction program window displayed on the candidate display according to the spatial coordinates of the receiving-end reference
points to represent a spatial location of the candidate electronic device.

US Pat. No. 9,571,880

PIXEL CLOCK GENERATION CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A pixel clock generation circuit, comprising:
a reference clock generation circuit for generating a reference clock;
an image processing circuit, for processing an image signal of a first format to generate a control signal; and
a clock adjustment circuit, coupled to the reference clock generation circuit and the image processing circuit, for generating
a pixel clock according to the reference clock and the control signal, the pixel clock being able to be used to generate an
image signal of a second format;

wherein, the control signal is substantially periodic and the frequency of the control signal is proportional to the frequency
of a synchronization signal of the image signal of the second format.

US Pat. No. 9,859,997

RECEIVING CIRCUIT CAPABLE OF PERFORMING I/Q MISMATCH CALIBRATION BASED ON EXTERNAL OSCILLATING SIGNAL

REALTEK SEMICONDUCTOR COR...

1. A receiving circuit (100) for processing a radio frequency signal (RF) transmitted from an external antenna (102) and capable of performing an I/Q mismatch calibration based on an external oscillating signal (ES) generated by an external
oscillator (104), the receiving circuit (100) comprising:
a first receiving terminal (112) utilized for coupling with the external antenna (102) to receive the radio frequency signal (RF);

a second receiving terminal (114) utilized for coupling with an output terminal of the external oscillator (104) to receive the external oscillating signal (ES);

a low-noise amplifier (120), coupled with the first receiving terminal (112) and the second receiving terminal (114), arranged to operably generate an output signal (SA) based on an incoming signal;

a band-pass filter (130), positioned on the signal path between the second receiving terminal (114) and the low-noise amplifier (120), arranged to operably generate a calibration signal (CS) according to the external oscillating signal (ES);

a first switch element (142) positioned on a signal path between the second receiving terminal (114) and the low-noise amplifier (120);

an in-phase signal processing circuit (170), coupled with an output terminal of the low-noise amplifier (120), arranged to operably generate an in-phase detection signal (DI) based on the output signal (SA);

a quadrature signal processing circuit (180), coupled with the output terminal of the low-noise amplifier (120), arranged to operably generate a quadrature detection signal (DQ) based on the output signal (SA); and

a calibration circuit (190), coupled with the first switch element (142), the in-phase signal processing circuit (170), and the quadrature signal processing circuit (180), arranged to operably control the first switch element (142) and capable of performing the I/Q mismatch calibration according to the in-phase detection signal (DI) and the quadrature
detection signal (DQ) when the first switch element (142) is turned on.

US Pat. No. 9,130,547

RAIL-TO-RAIL COMPARATOR CIRCUIT AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a PMOS (p-channel metal oxide semiconductor) transistor pair receiving a first voltage at a first circuit node and a second
voltage at a second circuit node and outputting a third voltage at a third circuit node and a fourth voltage at a fourth circuit
node;

an NMOS (n-channel metal oxide semiconductor) transistor pair receiving the third voltage at the third circuit node and the
fourth voltage at the fourth circuit node and outputting the first voltage at the first circuit node and the second voltage
at the second circuit node;

a first voltage-controlled resistor (VCR) controlled by a first control voltage and a second control voltage in accordance
with a first clock signal providing a coupling between the third voltage at the third circuit node and the second voltage
at the second circuit node; and

a second VCR controlled by the second control voltage and the first control voltage in accordance with a second clock signal
providing a coupling between the fourth voltage at the fourth circuit node and the first voltage at the first circuit node.

US Pat. No. 9,859,929

NOISE VARIANCE ESTIMATION CIRCUIT AND METHOD FOR WIRELESS COMMUNICATION

REALTEK SEMICONDUCTOR COR...

1. A noise variance estimation circuit for wireless communication, comprising:
a first estimation unit configured to generate a first estimation signal according to a reception signal and a reference signal,
in which the reception signal is derived from an equivalent of the reference signal;

a first noise reduction unit configured to generate a first noise reduction signal by performing a first noise reduction process
to the first estimation signal;

a second estimation unit configured to generate a second estimation signal according to the difference between the first estimation
signal and the first noise reduction signal; and

a second noise reduction unit configured to execute a noise reduction adjustment according to the second estimation signal,
and configured to perform a second noise reduction process to the first estimation signal so as to generate a second noise
reduction signal, in which the noise reduction adjustment affects the second noise reduction process.

US Pat. No. 9,685,780

ESD PROTECTION CIRCUIT

Realtek Semiconductor Cor...

1. An ESD protection circuit, comprising:
a clamping unit, coupled between a first power source and a second power source;
a driving unit, coupled between the clamping device and a reference node;
a resistance unit, coupled between the first power source and the reference node;
a switch unit, coupled to the driving unit; and
a capacitance unit, coupled between the switch unit and the second power source;
wherein the switch unit is coupled between the resistance unit and the capacitance unit, and under a normal operation condition,
the driving unit controls the switch unit to be in an un-conducting status, and under an ESD condition, the driving unit controls
the switch unit to be in a conducting status; the switch unit is a transmission gate; and the switch unit is coupled between
the reference node and the capacitance unit.

US Pat. No. 9,565,709

WIRELESS COMMUNICATION DEVICE AND METHOD CAPABLE OF PEER-TO-PEER INTERCONNECTION

Realtek Semiconductor Cor...

1. A wireless communication device capable of passively establishing peer-to-peer connection under the regulation of an IEEE
802.11 standard, comprising:
a control block operable to generate a local-end peer-to-peer connection message without referring to any information from
a first connection-end, in which the local-end peer-to-peer connection message includes a local-end group owner intent;

a transmission circuit operable to broadcast a local-end peer-to-peer connection packet according to the local-end peer-to-peer
connection message; and

a reception circuit operable to receive a first connection-end peer-to-peer connection request from the first connection-end
for the first time after the broadcasting of the local-end peer-to-peer connection packet, in which the first connection-end
peer-to-peer connection request includes a first connection-end group owner decision in relation to the local-end group owner
intent;

wherein the wireless communication device is operable to function as a master or a slave in relation to the first connection-end
according to the first connection-end group owner decision and to establish the peer-to-peer connection with the first connection-end.

US Pat. No. 9,813,057

SAMPLING CIRCUIT AND SAMPLING METHOD

REALTEK SEMICONDUCTOR COR...

1. A sampling circuit for sampling an input voltage and generating an output voltage, comprising:
a switch, switching off in a first switching state and switching on to make the output voltage equal to the input voltage
in a second switching state, wherein the switch has a control terminal;

a capacitor, coupled to the switch;
a first switch group, coupled to the capacitor;
a second switch group, coupled to the capacitor; and
a voltage buffer, coupled to the switch, the capacitor, the first switch group and the second switch group, having large input
impedance, wherein an input of the voltage buffer receives the input voltage and an output of the voltage buffer provides
a voltage which is equal or close to the input voltage;

wherein, in the first switching state when the first switch group switches on and the second switch group switches off, the
capacitor is charged to generate a voltage difference across the two terminals thereof, and in the second switching state
when the first switch group switches off and the second switch group switches on, the input voltage is coupled to the control
terminal of the switch through the voltage buffer and the capacitor so that a voltage at the control terminal is substantially
equal or close to the input voltage plus the voltage difference across the capacitor.

US Pat. No. 9,748,326

STRUCTURE OF INTEGRATED INDUCTOR

REALTEK SEMICONDUCTOR COR...

1. An integrated inductor structure, comprising:
an outer metal segment;
an inner metal segment in an area surrounded by the outer metal segment;
at least a bridging metal segment for connecting the outer metal segment and the inner metal segment; and
at least a connecting structure for connecting the bridging metal segment and the outer metal segment or the inner metal segment;
wherein, the outer metal segment and the inner metal segment are on different metal layers of a semiconductor structure;
wherein the outer metal segment comprises:
a first metal segment connecting a first bridging metal segment through a first connecting structure; and
a second metal segment connecting a second bridging metal segment;
wherein, the first bridging metal segment connects the inner metal segment and the second bridging metal segment connects
the inner metal segment through a second connecting structure.

US Pat. No. 9,619,864

IMAGE PROCESSING APPARATUS AND METHOD FOR INCREASING SHARPNESS OF IMAGES

REALTEK SEMICONDUCTOR COR...

1. An image processing apparatus, comprising:
at least one processor connected to a memory, wherein the at least one processor is configured to:
extract and translate a plurality of first high-frequency components of an input image to generate a first image;
extract a plurality of second high-frequency components of the input image to generate a second image;
generate a plurality of detail gains respectively associated with a plurality of input pixels in the input image according
to a conversion table and pixel values of the input pixels, wherein the detail gain of a first input pixel of the input pixels
is corresponding to a pixel value sum of pixel values of the first input pixel and a plurality of neighboring pixels separate
from the first input pixel by at least one pixel; and

calculate a weighted superposition of the first image and the second image and to generate a high-frequency component of an
output image according to the detail gains and the weighted superposition.

US Pat. No. 9,425,680

SWITCHING REGULATOR WITH RIPPLE-BASED CONTROL AND METHOD FOR SWITCHING REGULATOR WITH RIPPLE-BASED CONTROL

Realtek Semiconductor Cor...

1. A ripple-based control switching regulator, comprising:
a switch, for selectively outputting a first reference voltage or a second reference voltage as an output voltage according
to a control signal;

an inductor, coupled to the switch, for producing an inductor output voltage according to the output voltage;
a capacitor, coupled to the inductor;
an output voltage processing unit, for outputting a processed inductor output voltage according to the output voltage and
the inductor output voltage, wherein the output voltage processing unit comprises:

a double pulse detecting unit, for detecting whether the output voltage has a double pulse to generate a detecting result;
and

a voltage calibrating unit, for generating the processed inductor output voltage according to the detecting result, the output
voltage, and the inductor output voltage, wherein the voltage calibrating unit comprises:

a calibrating circuit, for generating a calibrated output voltage according to the detecting result, the output voltage, and
the inductor output voltage; and

a differentiator, for differentiating the calibrated output voltage to generate the processed inductor output voltage; and
a control unit, for outputting the control signal according to at least the processed inductor output voltage.

US Pat. No. 9,161,375

METHOD FOR SHARING ACCESS TO A WIRELESS LAN ACCESS POINT

REALTEK SEMICONDUCTOR COR...

1. A method for sharing access to a wireless LAN access point, the method being applicable between a target client device
and a host device which is coupled to the wireless LAN access point, wherein the host device has an established communication
coupling with the wireless LAN access point and the target device not having an established communication coupling with the
wireless LAN access point, the method comprising the steps of:
configuring the host device to send an invite request directly to the target client device, the host device having access
to a network via the wireless LAN access point, wherein the invite request is configured for inviting the target device to
share access to the wireless LAN access point;

configuring the host device to receive an invite response sent directly to the host device by the target client device; and
configuring the host device, in response to receiving the invite response from the target client device, to exchange connection
information directly with the target client device, the exchanged connection information being information necessary for the
target client device to establish a communication coupling with the wireless LAN access point, such that the target client
device thereafter uses the exchanged connection information to connect to the wireless LAN access point via the host device
according to the connection information.

US Pat. No. 9,088,291

USB APPARATUS

REALTEK SEMICONDUCTOR COR...

1. A Universal Serial Bus (USB) apparatus, comprising:
a signal detecting unit, for detecting a packet signal transmitted from a USB host and generating an acknowledgment signal
in response to a detection result indicating that the packet signal is a start of frame (SOF) packet signal;

an error detecting unit, coupled to the signal detecting unit, for utilizing an output clock signal to count a time interval
between two adjacent acknowledgment signals to generate a counting result and generating a control signal according to the
counting result, the output clock signal comprising a per interval quantity of clock cycles equal to a product of the time
interval and a frequency of the output clock signal; and

a frequency generating unit, coupled to the error detecting unit for generating the output clock signal according to the control
signal, wherein the frequency generating unit comprises:

a reference clock generator, for generating a reference clock signal; and
a fractional-N frequency synthesizer, for generating an adjusted clock signal according to the reference clock signal and
the control signal, the fractional-N frequency generator comprising a charge pump and a sigma-delta controller.

US Pat. No. 9,798,520

DIVISION OPERATION APPARATUS AND METHOD OF THE SAME

REALTEK SEMICONDUCTOR COR...

1. A division operation apparatus comprising:
a memory configured to store a divisor look-up table comprising a plurality of entries;
a non-zero bit detection circuit configured to generate a determination result signal by receiving a divisor to detect a number
of a highest non-zero bit of the divisor and determine whether the divisor exceeds a range of the divisor look-up table based
on the detected number;

a mapping calculation circuit configured to generate a mapped value of the divisor within a range of the divisor look-up table
according to a mapping function if the divisor exceeds the range of the divisor look-up table;

a look-up circuit configured to select between the divisor and the mapped value based on the determination result signal and
look up the divisor look-up table according to the selected value to retrieve a corresponding entry having a stored reciprocal;

a compensation circuit configured to generate a compensation value according to the mapping function; and
a multiplication circuit configured to multiply a dividend, the stored reciprocal and the compensation value to generate a
divided result of the dividend and the divisor.

US Pat. No. 9,521,359

MOBILE HIGH-DEFINITION LINK DATA CONVERTER AND MOBILE HIGH-DEFINITION LINK DATA CONVERTING METHOD

Realtek Semiconductor Cor...

1. A Mobile High-Definition Link (MHL) data converter, comprising:
a data decoding circuit, arranged to decode an input data according to an MHL specification and output a decoded data; and
a data parsing circuit, coupled to the data decoding circuit, the data parsing circuit arranged to parse out a plurality of
output data from the decoded data;

wherein the data parsing circuit transmits the plurality of output data to a Media Access Control (MAC) circuit which complies
with a High Definition Multimedia Interface (HDMI) specification; and the data decoding circuit compares control period data
and/or guard band data in at least one known data pattern defined by the MHL specification with the input data to find out
data boundaries, and decodes the input data according to the data boundaries to output the decoded data and each of the at
least one known data pattern is a data pattern of a plurality of consecutive control periods, and following received data
is data of one of a plurality channels by turns periodically.

US Pat. No. 9,450,544

PRE-DISTORTION METHOD, ASSOCIATED APPARATUS AND NON-TRANSITORY MACHINE READABLE MEDIUM

Realtek Semiconductor Cor...

1. A pre-distortion method, comprising:
receiving an input data;
obtaining a pre-distorted output by inputting the input data into a pre-distortion function, wherein the pre-distortion function
is determined according to a following power amplifier;

obtaining a pre-distortion ratio, wherein the pre-distortion ratio is an output of the power amplifier to the input data;
and

multiplying a reciprocal of the pre-distortion ratio with the output of the power amplifier;
wherein the step of obtaining the pre-distorted output by inputting the input data into the pre-distortion function comprises:
deriving a plurality of coefficients corresponding to each of a plurality of power levels of the pre-distorted output within
a specific power level range by utilizing an adaptive algorithm, wherein the plurality of coefficients includes at least a
first coefficient and a second coefficient of a function of the power amplifier;

storing a reciprocal of the at least a first coefficient corresponding to each of the plurality of power levels into a first
look-up table;

storing the at least a second coefficient corresponding to each of the plurality of power levels into a second look-up table;
and

deriving the pre-distortion function according to the first look-up table and the second look-up table in order to mitigate
or cancel unwanted characteristics of the power amplifier.

US Pat. No. 9,412,751

ELECTRONIC DEVICE

Realtek Semiconductor Cor...

1. An electronic device, comprising:
a core circuit comprising a plurality of core metal oxide semiconductors (core MOS); and
a plurality of pad units, respectively electrically connected to said core circuit, and each pad unit comprising a plurality
of pad metal-oxide-semiconductors (pad MOS), wherein the longer dimension of a core gate in each said core MOS and the longer
dimension of a pad gate in each said pad MOS all extend in the same direction;

wherein said pad unit further comprises an individual N-type metal oxide semiconductor (NMOS) region, an individual pad region
and an individual P-type metal oxide semiconductor (PMOS) region, one of said N-type metal oxide semiconductor (NMOS) region,
said pad region and said P-type metal oxide semiconductor (PMOS) region of each said pad unit is sandwiched between the other
two of said N-type metal oxide semiconductor (NMOS) region, said pad region and said P-type metal oxide semiconductor (PMOS)
region of each said pad unit, and said pad metal-oxide-semiconductors are disposed in said pad region and in at least one
of said NMOS region and said PMOS region of said pad unit.

US Pat. No. 9,413,539

ANALOG FRONT-END TRANSMITTER AND A CONNECTION METHOD OF AN X-DIGITAL SUBSCRIBER LINE HAVING A PRE-DISTORTION MECHANISM

REALTEK SEMICONDUCTOR COR...

1. An analog front-end transmitter having a pre-distortion mechanism, comprising:
a line driver, for receiving an input differential signal and generating an output differential signal wherein the input differential
signal comprises a first input signal and a second input signal; the output differential signal comprises a first output signal
and a second output signal; the line driver receives the first input signal to generate the first output signal and receives
the second input signal to generate the second output signal; and

a pre-distortion signal generator, coupled to input ends and output ends of the line driver, wherein the pre-distortion signal
generator generates a pre-distortion signal according to a first difference between the first input signal and the first output
signal, and a second difference between the second input signal and the second output signal so as to adjust an output of
the analog front-end transmitter having a pre-distortion mechanism.

US Pat. No. 9,350,686

DATA ACCESS DEVICE AND METHOD FOR COMMUNICATION SYSTEM

REALTEK SEMICONDUCTOR COR...

3. A data access method for a communication system to be implemented by a data access device including a transmit buffer,
the transmit buffer downloading data according to a write pointer and transmitting data according to a read pointer, said
data access method comprising:
calculating a distance between the write pointer and the read pointer to obtain a pointer difference, wherein the read pointer
is outputted by a read controller being controlled by the write pointer;

generating a download status indication according to the pointer difference and a first predetermined length; and
changing the write pointer according to the download status indication,
wherein the first predetermined length is equal to a predetermined retransmit length.

US Pat. No. 9,331,647

LOW-VOLTAGE AMPLIFIER AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. An amplifier comprising:
a first mixed-length MOS (metal-oxide semiconductor) device set for receiving an input signal and outputting an output signal;
and

a first load for providing termination for the output signal,
wherein the first mixed-length MOS device set comprises a parallel connection of a plurality of MOS devices having different
channel lengths including at least a short channel length MOS device and a long channel length MOS device, wherein the channel
length of the long channel length MOS device is longer than the channel length of the short channel length MOS device, wherein
the plurality of MOS devices includes a first MOS transistor and a second MOS transistor, and the parallel connection is defined
by a source terminal of the first MOS transistor being directly connected to a source terminal of the second MOS transistor
and a drain terminal of the first MOS transistor being directly connected to a drain terminal of the second MOS transistor.

US Pat. No. 9,307,058

NEGOTIATION METHOD AND ELECTRONIC APPARATUS USED IN ETHERNET CHANNEL OF HIGH DEFINITION MULTIMEDIA INTERFACE

Realtek Semiconductor Cor...

1. A negotiation method used in a multimedia interface, comprising: transmitting a first negotiation signal from a first side
to a second side during a first/second specific time period when receiving any negotiation signal transmitted from the second
side for enabling a negotiation of an Ethernet channel; transmitting a second negotiation signal from the first side to the
second side
during a third specific time period after the first/second specific time period; and checking whether any negotiation signal
from the second side is detected or not during the third specific time period for determining a result of the negotiation;
wherein a time interval of the first specific time period is substantially identical to a time interval of the second/third
specific time period, and a step of determining the result of the negotiation comprises: when the first side receives any
negotiation signal: re-transmitting the second negotiation signal to the second side during a fourth specific time period;
transmitting a fourth negotiation signal to the second side during a fifth specific time period; and checking whether the
fourth negotiation signal from the second side is detected or not during the fifth specific time period to determine the result
of the negotiation.

US Pat. No. 9,287,888

CONVERTER WITH AN ADDITIONAL DC OFFSET AND METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A converter, comprising:
a switch circuit, comprising a plurality of switches;
a first capacitor, storing a first charge according to switching control of the switch circuit and comprising a first additional
capacitor cell and a second additional capacitor cell wherein there is a capacitor difference between the first additional
capacitor cell and the second additional capacitor cell; and the first additional capacitor cell and the second additional
capacitor cell store a second charge and a third charge having different polarity and magnitude with the second charge, respectively,
according to switching control of the switch circuit; and

an operational amplifier, generating a DC bias including a DC offset according to the first charge and further generating
an inverted DC offset according to a difference between the second charge and the third charge to compensate the DC offset.

US Pat. No. 9,270,313

WIRELESS RECEIVER AND METHOD FOR WIRELESS RECEPTION

Realtek Semiconductor Cor...

1. A wireless receiver, for receiving an input radio frequency (RF) signal and outputting a baseband decoded signal, comprising:
a RF receiving unit, comprising:
a first path, for receiving the input RF signal and generating a first baseband input signal, the first path comprising a
first filter, wherein a bandwidth of the first filter is broader than a bandwidth of a packet of the input RF signal;

a second path, for receiving the input RF signal and generating a second baseband input signal; and
a baseband receiving unit, for receiving the first baseband input signal and the second baseband input signal to generate
the baseband decoded signal;

wherein the first path is an in-phase path, and the second path is a quadrature-phase path, and when the RF receiving unit
operates in a first mode, the RF receiving unit only uses the first path or the second path to receive the input RF signal.

US Pat. No. 9,258,380

CROSS-PLATFORM MULTIMEDIA INTERACTION SYSTEM WITH MULTIPLE DISPLAYS AND DYNAMICALLY-CONFIGURED HIERARCHICAL SERVERS AND RELATED METHOD, ELECTRONIC DEVICE AND COMPUTER PROGRAM PRODUCT

REALTEK SEMICONDUCTOR COR...

1. A cross-platform multimedia interaction system with dynamically-configured hierarchical servers, comprising:
a central relay server (CRS);
a plurality of electronic devices for communicating with the CRS to conduct an identity authentication; and
a plurality of displays respectively arranged on the plurality of electronic devices;
wherein the CRS dynamically assigns one of the plurality of electronic devices as a local relay server (LRS) and instructs
the LRS to activate a websocket server module, and the CRS notifies the other electronic devices of a network address of the
LRS;

wherein after the LRS activated the websocket server module, other electronic devices of the plurality of electronic devices
establish one or more network sockets with the LRS, and the plurality of electronic devices communicate control parameters
via the websocket server module, generate corresponding images according to received control parameters, and respectively
display the resulting images on the plurality of displays.

US Pat. No. 9,195,469

NETWORK APPARATUS AND METHOD IN A COMPUTER SYSTEM OPERATING A BOOT-STRAP OR A WORK PERIOD

REALTEK SEMICONDUCTOR COR...

1. A network apparatus, mounted in a computer system operating a boot-strap period or a work period, comprising:
a communication interface;
an enabling circuit, coupled to the communication interface, for generating an internal enabling signal; and
an application circuit, coupled to the enabling circuit, for performing the application circuit operation according to the
internal enabling signal;

wherein the enabling circuit generates the internal enabling signal to enable the application circuit in the boot-strap period,
and the enabling circuit generates the internal enabling signal according to a external enabling instruction signal outputted
from the communication interface for determining whether enable or disable the application circuit after the boot-strap period;
and whereby the network apparatus is able to be enabled prior to the external enabling instruction signal during the boot-strap
period and execute a power saving function according to the external enabling instruction signal after the boot-strap period.

US Pat. No. 9,105,221

MULTIMEDIA INTERACTION SYSTEM AND RELATED COMPUTER PROGRAM PRODUCT CAPABLE OF BLOCKING MULTIMEDIA INTERACTION COMMANDS THAT AGAINST INTERACTIVE RULES

REALTEK SEMICONDUCTOR COR...

1. A multimedia interaction system having multiple displays, comprising:
a plurality of electronic devices;
a plurality of displays, respectively arranged on the electronic devices;
a forwarding electronic device, configured to be a command transmitting medium among the electronic devices;
a location detection circuit, configured to dynamically detect a spatial location and an orientation for each of the electronic
devices, and configured to transmit information related to detection results to at least one of the forwarding electronic
device and the electronic devices through a wireless communication approach;

wherein when a user instructs a source electronic device of the electronic devices to transmit a target image object toward
a target direction, the source electronic device transmits information of the target direction and a target command corresponding
to the target image object to the forwarding electronic device, the forwarding electronic device determines whether a relative
position between a candidate electronic device of other electronic devices and the target direction satisfies a predetermined
condition, and only if the relative position between the candidate electronic device and the target direction satisfies the
predetermined condition, the forwarding electronic device transmits the target command to the candidate electronic device
the candidate electronic device utilizes a corresponding candidate display to perform a multimedia operation corresponding
to the target image object according to the target command;

wherein the location detection circuit detects and transmits spatial coordinates of multiple transmitting-end reference points
of the source electronic device to the source electronic device, and the location detection circuit detects and transmits
spatial coordinates of multiple receiving-end reference points of the candidate electronic device to the candidate electronic
device; and

wherein the source electronic device computes a central location of a first multimedia interaction program window displayed
on the source display according to the spatial coordinates of the transmitting-end reference points to represent a spatial
location of the source electronic device, and the candidate electronic device computes a central location of a second multimedia
interaction program window displayed on the candidate display according to the spatial coordinates of the receiving-end reference
points to represent a spatial location of the candidate electronic device.

US Pat. No. 9,083,917

TELEVISION SYSTEM AND VIDEO PROCESSING METHOD

REALTEK SEMICONDUCTOR COR...

1. A TV system comprising
a first integrated circuit (IC) chip, comprising:
a first logic module, for executing a first video process on a received video signal; and
a second logic module, for generating a still or a corresponsively still image signal;
a first transmission interface, coupled to said first IC chip, for transmitting said video signal processed by said first
logic module through a first transmission form;

a second transmission interface, coupled to said first IC chip, for transmitting said still or corresponsively still image
signal generated by said second logic module through a second transmission form;

a second IC chip, coupled to said first transmission interface and said second transmission interface, said second IC chip
comprising:

a third logic module, for executing a second video process on said processed video signal from said first transmission interface;
and

a fourth logic module, for blending said video signal processed by said third logic module with said still or corresponsively
still image signal from said second transmission interface to generate a blended signal; and

a display panel coupled to said fourth logic module, for displaying according to said blended signal.

US Pat. No. 9,058,134

SIGNAL SYNCHRONIZING DEVICE

Realtek Semiconductor Cor...

1. A signal synchronizing device comprising:
a trigger module, for capturing an input signal according to a first clock signal so as to generate a trigger signal in a
form of a pulse wave, the first clock signal corresponding with the input signal;

a first storage unit, for forming a first pulse signal by pulling an output of the first storage unit to a first logic level
according to the trigger signal, and by pulling the output of the first storage unit from the first logic level to a second
logic level according to a feedback reset signal; and

a synchronizing module, for performing synchronous transfer according to the first pulse signal so as to output an output
signal corresponding with frequency of a second clock signal, and for generating the feedback reset signal according to the
output signal, and an OR gate, for performing a logic OR operation between the output signal and an external reset signal
so as to generate the feedback reset signal.

US Pat. No. 9,900,019

CALIBRATION CIRCUIT AND CALIBRATION METHOD FOR TIME-INTERLEAVED ANALOG-TO-DIGITAL CONVERTER

REALTEK SEMICONDUCTOR COR...

1. A calibration circuit for a time-interleaved analog-to-digital converter (TI ADC), wherein the calibration circuit comprises:
a filter circuit configured to receive a first signal and generate a second signal based on the first signal, wherein the
first signal comprises an image of an interference signal, the second signal comprises a reconstructed image of the interference
signal, and a frequency of the reconstructed image of the interference signal is the same as a frequency of the image of the
interference signal; and

a calculating circuit configured to cancel the image of the interference signal of the first signal according to the second
signal.

US Pat. No. 9,859,912

CHARGE-REDISTRIBUTION SUCCESSIVE APPROXIMATION ADC AND CONTROL METHOD THEREOF

REALTEK SEMICONDUCTOR COR...

1. A charge-redistribution successive approximation analog-to-digital converter (ADC), applied to a single-ended signal, comprising:
a comparator, receiving the single-ended signal, and generating a comparison result;
a register, coupled to the comparator, storing a digital output code, determining bit values of the digital output code according
to the comparison result;

a control circuit, coupled to the register, generating a control signal according to the digital output code;
a plurality of first capacitors, each of the first capacitors comprising a first end and a second end, the first end coupled
to a first input end of the comparator;

at least one second capacitor, comprising a third end and a fourth end, the third end coupled to the first input end of the
comparator; and

at least one third capacitor, coupled to a second input end of the comparator;
wherein, when the control signal controls the second end of one of the first capacitors to switch from a first voltage to
a second voltage, the fourth end of the second capacitor is kept at the second voltage; when the control signal controls the
fourth end of the second capacitor to switch from the second voltage to the first voltage, the second end of the first capacitor
is kept at the first voltage;

wherein, a total of the numbers of the second capacitor(s) and the third capacitor(s) is equal to the number of the first
capacitors.

US Pat. No. 9,572,177

CONTROL CIRCUIT OF WIRELESS USER EQUIPMENT FOR DYNAMICALLY REPLACING RRC MESSAGES

REALTEK SEMICONDUCTOR COR...

1. A control circuit (124) of a wireless UE (120) for controlling the wireless UE (120) to conduct wireless communication with a communication station (110), the control circuit (124) comprising:
a message generating circuit (125), arranged to operably generate a first RRC message (MSG_A) and a second RRC message (MSG_B) to be transmitted to the communication
station (110) through a wireless communication circuit (121) of the wireless UE (120), to operably configure a first message identification (MID_A) and a first priority (PRI_A) corresponding to the first RRC
message (MSG_A), and to operably configure a second message identification (MID_B) and a second priority (PRI_B) corresponding
to the second RRC message (MSG_B); and

a message reordering circuit (126), coupled with the message generating circuit (125), arranged to operably compare the first priority (PRI_A) with the second priority (PRI_B), wherein if the first priority
(PRI_A) is higher than the second priority (PRI_B), the message reordering circuit (126) configures a transmission order of the second RRC message (MSG_B) in a message queue to be after that of the first RRC message
(MSG_A);

wherein when the message generating circuit (125) afterward generates a third RRC message (MSG_C) to be transmitted to the communication station (110) through the wireless communication circuit (121), the message generating circuit (125) configures a third message identification (MID_C) and a third priority (PRI_C) corresponding to the third RRC message (MSG_C);

wherein the message reordering circuit (126) compares the first priority (PRI_A), the second priority (PRI_B), and the third priority (PRI_C) to rearrange transmission
orders of RRC messages in the message queue, and if the third priority (PRI_C) is equal to the second priority (PRI_B), the
message reordering circuit (126) replaces the second RRC message (MSG_B) in the message queue with the third RRC message (MSG_C).

US Pat. No. 9,438,983

SIGNAL PROCESSING CIRCUIT AND ASSOCIATED SIGNAL PROCESSING METHOD APPLIED TO HEADSET

Realtek Semiconductor Cor...

1. A signal processing circuit applied to a headset, wherein the headset comprises a left earphone, a right earphone and a
microphone, and the signal processing circuit receives a sound signal from the microphone, and generates audio signals to
the left earphone and the right earphone, respectively; the signal processing circuit comprising:
an analog-to-digital converter, arranged for receiving the sound signal from the microphone, and converting the sound signal
into a digital input signal;

an audio processing circuit, arranged for generating a left channel signal and a right channel signal, wherein the left channel
signal and the right channel signal are utilized to generate the audio signals;

a first gain and phase adjuster, coupled to the audio processing circuit, wherein the first gain and phase adjuster is arranged
to adjust gains and phases of the left channel signal and the right channel signal to generate a first adjusted signal; and

a first adder, coupled to the analog-to-digital converter, the first gain and phase adjuster, and the audio processing circuit,
wherein the first adder is arranged to combine the digital input signal and the first adjusted signal to generate an adjusted
digital input signal, and provide the adjusted digital input signal to the audio processing circuit.

US Pat. No. 9,385,677

METHOD AND APPARATUS FOR GAIN ENHANCEMENT OF DIFFERENTIAL AMPLIFIER

REALTEK SEMICONDUCTOR COR...

1. A circuit comprising:
a feed-in network coupling a differential input signal to a differential intermediate signal;
a differential amplifier amplifying the differential intermediate signal by a gain factor to output a differential output
signal to a load network;

a feedback network configured in a negative feedback topology coupling the differential output signal to the differential
intermediate signal, the feedback network comprising two feedback circuits having substantially equal impedances, wherein
a first feedback circuit is connected between the negative differential output signal and the positive differential intermediate
signal and a second feedback circuit is connected between the positive differential output signal and the negative differential
intermediate signal; and

a gain enhancing network configured in a positive feedback topology coupling the differential output signal to the differential
intermediate signal, wherein an impedance of the gain enhancing network is approximately equal to an impedance of the feed-in
network times the gain factor minus one, the gain enhancing network comprising two gain enhancing circuits having substantially
equal impedances, wherein a gain enhancing circuit is connected between the negative differential output signal and the negative
differential intermediate signal and a second gain enhancing circuit is connected between the positive differential output
signal and the positive differential intermediate signal.

US Pat. No. 9,350,529

METHOD AND APPARATUS FOR DETECTING LOGICAL SIGNAL

REALTEK SEMICONDUCTOR COR...

1. A system comprising:
a driver circuit configured to receive a source data and output a first voltage at a first node;
a transmission line having a characteristic impedance configured to couple the first node to a second node;
a three-point three-level slicer circuit configured to receive a second voltage at the second node and output a first ternary
signal, a second ternary signal, and a third ternary signal in accordance with a first reference voltage, a second reference
voltage, a first clock, a second clock, and a third clock; and

a CDR (clock-data recovery) circuit configured to receive a reference clock, the first ternary signal, the second ternary
signal, and the third ternary signal and output a recovered data, the first reference voltage, the second reference voltage,
the first clock, the second clock, and the third clock.