US Pat. No. 9,690,722

MEMORY CONTROLLER AND MEMORY ACCESS METHOD

QUIXANT PLC, Cambridgesh...

1. A memory controller for a plurality of banks of memory,
the memory controller including an interface connectable to a bus to communicate with a processor,
the memory controller redundantly mapping the plurality of banks of memory to a memory space and includes a plurality of memory
operators, each of the plurality of memory operators being executable by the memory controller for performing a different
function on data in the memory space and/or one or more of the plurality of banks of memory, wherein, responsive to receipt
at said interface of a request from said processor for one of said memory operators, the memory controller is configured to
execute, independently of the processor, the respective memory operator on the memory space and/or one or more of the plurality
of banks of memory;

a first control pathway to provide the processor access to the memory space as a single addressable memory wherein, when first
data is stored in the single addressable memory and a duplicate of the first data is stored in one of the plurality of banks
of memory, the one of the plurality of banks of memory is not visible to the processor and the processor is not able to access
the duplicate of the first data via the first control pathway;

a second control pathway to provide the processor direct access to the data in each of said plurality of banks of memory including
the first data and the duplicate of the first data;

a pathway selection input to receive a selection of one of the first control pathway or the second control pathway to be used
for a memory access request received via the interface from the processor.

US Pat. No. 9,666,241

FIRMWARE PROTECTION AND VALIDATION

QUIXANT PLC, Cambridgesh...

1. A system for firmware protection and validation comprising:
a memory device, including BIOS firmware;
a chipset wherein the chipset controls communication between the memory device and the microprocessor including allowing the
microprocessor to load and execute the BIOS firmware;

the microprocessor in electrical communication with the chipset;
a secure logic device in electrical communication with the chipset and the memory device wherein, prior to validation of the
BIOS firmware, the secure logic device prevents the microprocessor from operating including executing instructions; and

a power on reset circuit in communication with the secure logic device, wherein, when the secure logic device receives a reset
signal from the power on reset circuit, the secure logic device applies a hold signal to the chipset and the microprocessor,
wherein the secure logic device applies a hold signal to the microprocessor through the chipset, while the hold signal is
applied to the chipset by the secure logic device, the power on reset circuit de-asserts the reset signal, when the reset
signal is de-asserted, only the secure logic device validates the content of the firmware in the memory device, and further
wherein, when the content of the firmware is validated by the secure logic device, the secure logic device de-asserts the
hold signal applied to the chipset, further wherein the hold signal is continuously asserted from the receipt of the reset
signal until the content of the firmware in the memory device is validated.

US Pat. No. 10,019,389

MEMORY CONTROLLER AND MEMORY ACCESS METHOD

QUIXANT PLC, Cambridgesh...

1. A computing device comprising:a processor configured to execute game software and to communicate with a memory controller via a communication bus;
the memory controller including:
a processor interface coupled to the communication bus configured to receive or to transfer data to the processor via the communication bus, receive memory addresses from the processor via the communication bus and receive control commands from the processor via the communication bus;
a memory bank interface configured to communicate with a plurality of memory banks including writing data or reading the data from the plurality of memory banks;
a mode control register configured to receive a selection of an operational mode of the memory controller from the processor via the processor interface;
the plurality of memory banks including a first memory bank storing first data and one or more second memory banks each storing a duplicate of the first data
wherein, when a first operational mode is selected in the mode control register by the processor, the memory controller allows the processor to access only the first data in the first memory bank via the memory addresses and wherein, when a second operational mode is selected in the mode control register by the processor, the memory controller allows access by the processor to the first data in the first memory bank and the one or more duplicates of the first data in the one or more second memory banks, via the memory addresses.

US Pat. No. 10,194,558

GAME CONTROLLER AND SECURE ENCLOSURE FOR AN ELECTRONIC GAMING MACHINE

QUIXANT PLC, Cambridgesh...

1. A system comprising:an enclosure including two compartments wherein a first compartment is accessed via a door including a locking mechanism and wherein a second compartment is secured via a cover;
a game control unit, disposed within the first compartment of the enclosure, including a frame, two heat dissipation units coupled to the frame, a plurality of electrical circuit boards forming a game controller, coupled to an outside of the heat dissipation units adjacent to walls of the enclosure,
wherein the game controller includes a CPU, GPU, RAM, BIOS and a mass storage device storing game software and wherein the game controller executes the game software to control a wager-based game played on an electronic gaming machine;
a first fan disposed within the second compartment; and
a first plurality of apertures, between the first compartment and the second compartment, which allow air driven by the first fan, to move between the first compartment and the second compartment to cause heat from the heat dissipation units to be removed from the first compartment;
wherein the heat dissipation units in the first compartment are disposed adjacent to a first side of the first plurality of apertures such, such that when the door to the first compartment is locked via the locking mechanism and the cover and the first fan is removed from the second compartment for servicing the first fan, the game controller is not exposed to tampering allowing the first fan to be serviced by a service technician without a presence of security personnel.

US Pat. No. 10,201,111

GAME CONTROLLER AND SECURE ENCLOSURE FOR AN ELECTRONIC GAMING MACHINE

QUIXANT PLC, Cambridgesh...

1. A device comprising:an enclosure including two compartments wherein a first compartment is accessed via a door including a locking mechanism and wherein a second compartment is secured via a cover;
a game control unit, disposed within the first compartment of the enclosure, including
a frame,
a first heat dissipation units coupled to the frame, the first heat dissipation unit having a first plate with first fins extending from the first plate;
a second heat dissipation unit coupled to the frame, the second heat dissipation unit having a second plate with second fins extending from the second plate;
wherein ends of the first fins substantially reach ends of the second fins;
a first circuit board including at least a CPU mounted to the first plate, on a side opposite the first fins, between the first plate and a first wall of the enclosure forming the first compartment wherein the first fins are configured to dissipate heat from the CPU;
a second circuit board including at least a GPU mounted to the second plate, on a side opposite the second fins, between the second plate and a second wall of the enclosure forming the first compartment wherein the second fins are configured to dissipate heat from the GPU;
a game controller including the CPU, the GPU, the first circuit board, the second circuit board, RAM, a BIOS and a mass storage device storing game software wherein the game controller executes the game software to control a wager-based game played on an electronic gaming machine;
a first fan disposed within the second compartment; and
a first plurality of apertures, between the first compartment and the second compartment, which allow air driven by the first fan, to move between the first compartment and the second compartment to cause heat from the first heat dissipation unit and the second heat dissipation unit to be removed from the first compartment.