US Pat. No. 9,374,890

CHIP SUBSTRATE HAVING A LENS INSERT

Point Engineering Co., Lt...

1. A chip substrate comprising:
a conductive layer being stacked in a horizontal direction and constituting a chip substrate;
an insulator being alternately stacked with the conductive layer in the horizontal direction and electrically separating the
conductive layer; and

a lens insert having: a depression reaching down to a predetermined depth from a specified area of an upper surface of the
chip substrate overlapping with the insulator; and a predetermined number of sides on the upper surface wherein arcs reaching
down to the predetermined depth from the specified area of the upper surface of the chip substrate are formed at regions where
the arcs protrude outwardly from a region defined by where extended lines of the sides meet each other.

US Pat. No. 9,913,381

BASE SUBSTRATE WHICH PREVENTS BURRS GENERATED DURING THE CUTTING PROCESS AND METHOD FOR MANUFACTURING THE SAME

Point Engineering Co., Lt...

1. An uncut substrate having an upper surface and a lower surface, the substrate comprising:
a plurality of conductive layers arranged laterally in one direction;
at least one vertical insulation layer interposed between and laterally adjacent to the conductive layers so as to electrically
separate the conductive layers from one another;

a plurality of cavities, each of which comprising a concave pit downwardly reaching from the upper surface of the uncut substrate
to a predetermined depth at a region of the upper surface including a portion of the insulation layer; and

a plurality of through holes that are empty inside,
wherein the uncut substrate is partitioned into a plurality of unit substrate areas arranged in a two-dimensional array along
a plurality of rows and a plurality of columns, each of the unit substrate areas accommodating one of the cavities at a central
region thereof,

wherein each of the through holes is located on one of border lines between the plurality of columns, and completely penetrates
a portion of the vertical insulation layer and a portion of the conductive layers adjacent to the portion of the insulation
layer from the upper surface to the lower surface so as to prevent generation of burrs in case of the uncut substrate being
cut along the border lines between the plurality of columns.

US Pat. No. 9,306,142

HIGH HEAT-RADIANT OPTICAL DEVICE SUBSTRATE AND MANUFACTURING METHOD THEREOF

Point Engineering Co., Lt...

1. A method of manufacturing an optical device substrate, comprising:
anodizing surfaces of a plurality of metal plates;
coating anodized surfaces of the metal plates with an insulating liquid binder having a viscosity adapted to infiltrate anodized
oxide films of the metal plates;

alternately stacking the metal plates coated with the liquid binder and insulating binder films, before curing the liquid
binder; and

curing a laminate comprising the metal plates and the binder films using hot pressing, so that the liquid binder infiltrates
the anodized oxide films of the metal plates.

US Pat. No. 9,281,452

METHOD FOR MANUFACTURING A CAN PACKAGE-TYPE OPTICAL DEVICE, AND OPTICAL DEVICE MANUFACTURED THEREBY

Point Engineering Co., Lt...

1. A method for manufacturing a can package-type optical device including the steps of:
(a) preparing a metal plate;
(b) preparing a metal substrate having a bottom surface and an anodized top surface, and a plurality of vertical insulation
layers crossing the substrate from the anodized top surface to the bottom surface;

(c) bonding said metal plate on the anodized top surface of said metal substrate;
(d) forming a cavity on an intermediate product that has undergone step (c) in a form of a pit having a side wall and a bottom
wall, the pit having a depth reaching the anodized top surface of said metal substrate by passing through said metal plate
and an adhesive layer formed by said bonding, the anodized top surface of the metal substrate defining the bottom wall of
the cavity, wherein said cavity exposes one of said vertical insulation layers in the bottom wall thereof;

(f) connecting a first wire from an anode of an optical device to a first location on the wall of the cavity, and connecting
a second wire from a cathode of the optical device to a second location on the wall of the cavity, the first location on the
wall of the cavity isolated from the second location on the wall of the cavity by the exposed vertical insulation layer; and

(h) sealing said cavity by means of a protective plate made from a light-transmitting material, and a can cap formed as a
picture frame whose top central portion and bottom are open and encompassing a perimeter of said protective plate.

US Pat. No. 9,378,986

METHOD FOR MOUNTING A CHIP AND CHIP PACKAGE

Point Engineering Co., In...

1. A chip package, comprising:
a substrate having a plating layer formed on a surface thereof and including a cavity formed concavely in an inner direction;
a chip wherein an electrode portion or a metal portion is formed on a bottom of the chip;
an insulating portion configured to electrically isolate a first conductive portion of the substrate from a second conductive
portion of the substrate and wherein the plating layer includes one plated surface of the cavity on the first conductive portion
of the substrate and another plated surface of the cavity on the second conductive portion of the substrate electrically isolated
from the one plated surface;

a bump formed on the one plated surface of the cavity; and
a solder for bonding the chip and the bump by being melted, and sealing a space between the chip and the substrate formed
by bonding the chip and the bump,

and a wire configured to electrically connect the chip and the another plated surface of the cavity on the second conductive
portion of the substrate.

US Pat. No. 9,318,679

OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME

Point Engineering Co., Lt...

1. An optical device comprising:
a metal substrate wherein at least one vertical insulation layer is formed from an upper surface of the metal substrate towards
a downward direction;

a metal plated layer formed on the upper surface of the metal substrate except for the vertical insulation layer; and
an optical device chip bonded to one portion of the metal plated layer, wherein one electrode of the optical device chip is
electrically connected to a bonded surface of the metal plated layer, and the other electrode of the optical device chip is
wire bonded to the other portion of metal plated layer wherein said one portion of the metal plated layer is located in one
side and the other portion of the metal plated layer is located in the other side with respect to the vertical insulation
layer,

wherein the optical device chip and a peripheral region thereof is shielded with a sealant, and at least one groove is formed
on a partial surface of the metal plated layer so that a portion of the sealant is directly bonded to the metal substrate.

US Pat. No. 9,316,768

SUBSTRATE FOR PREVENTING BURR GENERATION

Point Engineering Co., Lt...

1. A substrate for an optical device comprising an optical device substrate including a plurality of conductive plates elongated
along a length direction, wherein side surfaces of the conductive plates are bonded to each other with insulators interposed
therebetween, the insulators being respectively formed on the side surfaces,
wherein a groove having a predetermined depth for preventing burrs is formed in a lower surface of the optical device substrate
at each point where a cutting line is crossed with one of the insulators when the optical device substrate is cut in a length
direction and in a vertical direction, the groove being formed in such a way that said one of the insulators is exposed to
an inside of the groove.

US Pat. No. 9,773,617

FOLDING TYPE CAPACITOR COMPRISING THROUGH HOLE

POINT ENGINEERING CO., LT...

1. A folding type capacitor comprising:
a metal substrate having a first surface and a second surface which is opposite to the first surface, wherein a through hole
penetrates an inside thereof;

at least one dielectric layer formed on the first surface of the metal substrate and an inner surface of the through hole
in a manner that an entire portion of the inner surface of the through hole is covered by the at least one dielectric layer
to prevent the metal substrate from being exposed in the through hole; and

an electrode layer formed on the at least one dielectric layer,
wherein the metal substrate has bended portions so that a portion of the first surface of the metal substrate faces another
portion of the first surface of the metal substrate, and

wherein the electrode layer passes through the through hole.

US Pat. No. 9,537,074

HIGH HEAT-RADIANT OPTICAL DEVICE SUBSTRATE

Point Engineering Co., Lt...

1. An optical device substrate comprising metal plates and insulating layers formed between the metal plates,
wherein each insulating layer includes a cured insulating layer formed by curing insulating material and an anodized layer
merged with each metal plate, the anodized layer formed by anodizing a first metal and a second metal of each metal plate,

the first metal and the second metal include a first anodized layer and a second anodized layer, respectively, and are electrically
insulated by interfaces including a first interface formed between the first metal and the first anodized layer, a second
interface formed between the first anodized layer and the cured insulating layer, a third interface formed between the cured
insulating layer and the second anodized layer and a fourth interface formed between the second anodized layer and the second
metal.

US Pat. No. 9,287,243

OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME

Point Engineering Co., Lt...

26. A metal substrate for an optical device comprising:
the substrate made of aluminum and having a top surface and a bottom surface; and
wherein the substrate comprising a first isolated portion and adjacent a second isolated portion and an anodized isolated
region disposed between the first isolated portion and the second isolated portion;

wherein the first isolated portion and the second isolated portion are electrically isolated, wherein the isolated region
extends from the top surface to the bottom surface, and wherein an adhesive insulation member is provided inside the anodized
isolated region.

US Pat. No. 9,214,453

OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME

Point Engineering Co., Lt...

1. A metal substrate for an optical device comprising:
a metal plate having a top surface and a bottom surface and including a plurality of metal portions;
a plurality of insulation regions, each passing vertically through the thickness of the metal plate;
a plurality of light emitting chips disposed on a plurality of the metal portions; and
a barrier that defines a region including a plurality of the metal portions and a plurality of the insulation regions;
wherein the plurality of the metal portions are separated by the plurality of the insulation regions,
wherein a plurality of the light emitting chips are electrically connected in parallel along the insulation regions and a
plurality of the light emitting chips are electrically connected in series along an orthogonal direction of the insulation
regions.

US Pat. No. 9,683,711

LIGHT EMITTING DEVICE SUBSTRATE AND METHOD FOR MANUFACTURING THE SAME

Point Engineering Co., Lt...

1. An optical device substrate comprising:
a stack of unit block substrates, each unit block substrate accommodating therein (n?1) number of insulating members, where
(n>1), for insulating adjacent partitioned areas of a flat panel metal substrate, the insulating members partitioning the
flat panel metal substrate into n number of optical device attachment areas;

first horizontal insulators for insulating surfaces of each unit block substrate in a horizontal direction from surfaces of
adjacent unit block substrates;

outer metal electrode substrates bonded to the unit block substrates at the top and bottom of the stack, the outer metal electrode
substrates supplying power;

second horizontal insulating members for insulating between the outer metal electrode substrates and the unit block substrates
to which the outer metal electrode substrates are bonded;

a pair of inner metal electrode substrates positioned between two consecutive unit block substrates within the stack; and
third horizontal insulating members for insulating surfaces of the inner metal electrode substrates from the unit block substrates.

US Pat. No. 9,559,276

LED METAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURING SAME

Point Engineering Co., Lt...

1. A method for manufacturing an LED metal package comprising:
forming at least one cavity comprising a concave pit reaching down to a predetermined depth of a metal substrate which is
electrically separated by at least one vertical insulation layer, wherein said at least one vertical insulation layer is accommodated
at the bottom thereof;

shadow masking the entire upper surface of the metal substrate using a mask except a portion of the upper surface of said
metal substrate which is formed inside of each of said at least one cavity;

removing the oxide layer which is formed on said portion of the upper surface not covered by said shadow masking;
depositing an electrode layer on each of said portion of the upper surface where said oxide layer has been removed;
removing said mask;
bonding an optical device chip on said electrode layer by soldering using a gold-tin (AuSn) alloy soldering layer; and
wire bonding an electrode of said optical device located in one side of said metal substrate with respect to each of said
vertical insulation layer to a portion of said metal substrate located in the other side of said metal substrate with respect
to each of said vertical insulation layer.

US Pat. No. 9,865,787

CHIP SUBSTRATE AND CHIP PACKAGE MODULE

Point Engineering Co., Lt...

1. A chip substrate, comprising:
conductive portions;
insulation portions to electrically isolate the conductive portions from one another;
lens insertion grooves formed at an upper surface, each of the lens insertion grooves having a first predetermined depth,
an outer periphery of each of the lens insertion grooves being generally shaped as a polygon with a plurality of straight
sides whose corners are arc-shaped;

cavities further depressed from the lens insertion grooves with a second predetermined depth, each of the cavities having
a bottom surface wherein one of the insulation portions is exposed at the bottom surface of each of the cavities; and

a heat dissipating portion bonded to a lower.

US Pat. No. 9,773,618

CAPACITOR

POINT ENGINEERING CO., LT...

1. A capacitor comprising:
a substrate;
a dielectric layer formed on the substrate, said dielectric layer comprising an upper dielectric layer and a lower dielectric
layer respectively formed on an upper surface of the substrate and the lower surface of the substrate;

a side dielectric layer formed on a side surface of the substrate so as to connect the upper dielectric layer and the lower
dielectric layer; and

an electrode layer comprising a first electrode layer and a second electrode layer formed on the dielectric layer, wherein
the first electrode layer and the second electrode layer are separated from each other, and at least a portion of the first
electrode layer and at least a portion of the second electrode layer are disposed on a same surface,

wherein the electrode layer comprises an upper electrode layer formed on an upper surface of the upper dielectric layer and
a lower electrode layer formed on a lower surface of the lower dielectric layer;

wherein the upper electrode layer and the lower electrode layer are electrically connected to each other; and
wherein a side electrode layer formed on the side dielectric layer, and the upper dielectric layer and the lower dielectric
layer are connected to the side electrode layer.

US Pat. No. 9,653,664

CHIP SUBSTRATE COMPRISING A GROOVE PORTION AND CHIP PACKAGE USING THE CHIP SUBSTRATE

Point Engineering Co., Lt...

1. A chip package, comprising:
a chip substrate which includes conductive portions laminated in one direction to constitute the chip substrate, insulation
portions alternately laminated with the conductive portions to electrically isolate the conductive portions, a cavity depressed
inward of the conductive portions in a region including the insulation portions, and a groove portion disposed outside the
cavity in a spaced-apart relationship with the cavity and formed at a predetermined depth in a recessed shape;

an optical element mounted within the cavity; and
a sealing member bonded to the chip substrate by an adhesive agent disposed within the groove portion in order to seal the
cavity, the sealing member including a shielding portion formed on one surface corresponding to the groove portion,

wherein the groove portion is formed on partial regions of the conductive portions and partial regions of the insulation portions,
and the adhesive agent is disposed on the partial regions of the conductive portions and the partial regions of the insulation
portions.

US Pat. No. 9,673,367

SUBSTRATE FOR MOUNTING CHIP AND CHIP PACKAGE

Point Engineering Co., Lt...

1. A chip mounting substrate, comprising:
a plurality of conductive portions configured to apply an electrode voltage to a mounted chip having electrode portions;
at least one insulation portion configured to electrically isolate the conductive portions; and
a plurality of bumps formed at a predetermined height to be bonded to the electrode portions of the chip wherein the chip
is mounted on the bumps,

wherein a cavity depressed inward of the conductive portions and configured to provide a space in which the chip is mounted
is formed in the conductive portions, and a recess depressed downward from a bottom surface of the cavity is formed at a central
portion of the cavity,

wherein the electrode portions of the chip are formed on one surface of the chip facing surfaces of the conductive portions
having the cavity, and the bumps protrude upward from a bottom surface of the recess, and

wherein a height of each of the bumps is set such that a side surface of the chip mounted on the bumps is located higher than
the bottom surface of the cavity so as to prevent a light emitted from the side surface of the chip from being obstructed.

US Pat. No. 9,666,558

SUBSTRATE FOR MOUNTING A CHIP AND CHIP PACKAGE USING THE SUBSTRATE

Point Engineering Co., Lt...

11. An uncut chip-mounting plate, comprising:
a plurality of conductive portions configured to apply voltages to at least two or more chips which are mounted on each of
unit chip-mounting substrates defined on the uncut chip-mounting plate;

a plurality of insulation portions formed between the conductive portions in each of the unit chip-mounting substrates and
configured to electrically isolate the conductive portions;

a cavity formed in a region of each of the unit chip-mounting substrates which includes at least three or more of the conductive
portions and at least two or more of the insulation portions and depressed inward to form a space in which the chips are mounted;
and

through-holes located on cutting lines of the uncut chip-mounting plate so as to penetrate and divide the insulation portions,
wherein the cutting lines are lines along which the uncut chip-mounting plate is diced into unit chip-mounting substrates.

US Pat. No. 9,768,369

LED METAL SUBSTRATE PACKAGE AND METHOD OF MANUFACTURING SAME

Point Engineering Co., Lt...

1. A method for manufacturing an LED metal package comprising:
forming at least one cavity comprising a concave pit reaching down to a predetermined depth of a metal substrate which is
electrically separated by at least one vertical insulation layer, wherein said at least one vertical insulation layer is accommodated
in the bottom thereof;

shadow masking the entire upper surface of the metal substrate using a mask except a portion of the upper surface of said
metal substrate which is formed inside of each of said at least one cavity;

removing the oxide layer which is formed on said portion of the upper surface not covered by said shadow masking;
depositing an electrode layer on each of said portion of the upper surface where said oxide layer has been removed; and
removing said mask.

US Pat. No. 9,496,470

CHIP PACKAGE HAVING A LIGHT SHIELD

Point Engineering Co., Lt...

1. A chip package having a light shield comprising:
a chip substrate comprising a conductive portion and at least one insulating portion electrically separating said conductive
portion;

an optical device mounted on said chip substrate;
a sealing portion sealing the upper surface of said chip substrate;
an adhesive bonding said sealing portion to said chip substrate; and
a light shield formed in said sealing portion and blocking the light of said optical device from entering into said adhesive.

US Pat. No. 9,666,565

OPTICAL DEVICE AND METHOD FOR MANUFACTURING SAME

Point Engineering Co., Lt...

1. A metal substrate for an optical device comprising:
a metal plate having a top surface and a bottom surface and including a plurality of metal portions including first metal
portions and second metal portions arranged alternately with the first metal portions;

a plurality of insulation regions, each passing vertically through the thickness of the metal plate, the insulation regions
being interposed between the first metal portions and the second metal portions so as to electrically insulate the first metal
portions from the second metal portions; and

a plurality of light emitting chips disposed on a plurality of the metal portions;
wherein the light emitting chips are arranged on the metal portions along a plurality of rows including a first row and a
second row substantially perpendicular to a lengthwise direction of the metal portions in a manner that light emitting chips
of the first row are disposed on the first metal portions without being disposed on the second metal portions electrically
insulated from the first metal portions by the insulation regions interposed therebetween, and light emitting chips of the
second row are disposed on the second metal portions without being disposed on the first metal portions electrically insulated
from the second metal portions by the insulation regions interposed therebetween.

US Pat. No. 10,039,160

LIGHT ENGINE FOR LIGHT EMITTING ELEMENT

Point Engineering Co., Lt...

1. A light engine for light emitting elements, comprising:an element substrate on which a plurality of light emitting elements are mounted;
circuit substrates contacting one another in an insulated state in order to apply a drive voltage to the light emitting elements and contacting the element substrate in an insulated state; and
protection substrates surrounding and contacting the element substrate and the circuit substrates in an insulated state;
wherein the circuit substrates include a first circuit substrate and a second circuit substrate divided from each other, disposed to make contact with the element substrate and configured to apply voltages of different polarities to the light emitting elements, and
wherein the circuit substrates include a third circuit substrate configured to make simultaneous contact with the first circuit substrate and the second circuit substrate at the opposite side of the first circuit substrate and the second circuit substrate from the element substrate.

US Pat. No. 9,847,462

ARRAY SUBSTRATE FOR MOUNTING CHIP AND METHOD FOR MANUFACTURING THE SAME

Point Engineering Co., Lt...

1. An array substrate for mounting a chip to a circuit board, the array substrate comprising:
a plurality of conductive parts arranged in one direction, whereon a plurality of chips are mounted in the one direction,
each of the plurality of conductive parts having a chip-mounting surface, and a back surface opposite the chip-mounting surface
for mounting the array substrate to the circuit board;

one or more insulating parts alternately arranged with the plurality of conductive parts for electrically separating the plurality
of conductive parts,

protrusion parts whose heights are different from that of a surface of the conductive parts whereon the chip is mounted, the
protrusion parts being arranged at both ends and a central portion of the array substrate; and

concave parts depressed in a lateral direction with respect to side surfaces of the array substrate, the concave parts being
arranged only at the both ends and the central portion where the protrusion parts are arranged.

US Pat. No. 9,559,268

METHOD FOR MANUFACTURING OPTICAL ELEMENT FOR BACKLIGHT UNIT AND OPTICAL ELEMENT AND OPTICAL ELEMENT ARRAY MANUFACTURED BY METHOD

Point Engineering Co., Lt...

1. A method of manufacturing an optical device for a back light unit, comprising:
forming a metal ingot having therein insulating layers arranged with intervals therebetween by adhering metal plates having
a predetermined thickness to the insulating layers such that the insulating layers are arranged between the metal plates;

manufacturing original substrates by cutting the metal ingot in a vertical direction such that each original substrate includes
insulating layer portions arranged in parallel with intervals therebetween, wherein the metal ingot is cut by a wire sawing
method; and

depositing a solder resist on at least one of a top surface and a bottom surface of each original substrate.

US Pat. No. 9,818,913

CHIP SUBSTRATE

Point Engineering Co., Lt...

1. A chip substrate comprising:
conductive portions arranged in one direction;
an insulation portion interposed between the conductive portions to electrically isolate the conductive portions from one
another;

a cavity formed by being recessed from a region of an upper surface of the chip substrate including a part of the insulation
portion; and

an insulation layer coated on the upper surface of the chip substrate excluding the region where the cavity is formed,
wherein a portion of a top surface of the insulation portion is exposed on the cavity, and the other portion of the top surface
of the insulation portion is coated with the insulation layer.

US Pat. No. 9,764,949

ANODIC OXIDE FILM STRUCTURE CUTTING METHOD AND UNIT ANODIC OXIDE FILM STRUCTURE

Point Engineering Co., Lt...

1. A unit anodic oxide film structure, comprising:
a body portion having a plurality of anodizing pores formed vertically therein;
a step portion having a step difference formed so as to surround the periphery of said body portion, wherein an upper surface
of said step portion is positioned lower than an upper surface of said body portion;

electrodes formed on said upper surface of said body portion; and
a plurality of increased-diameter pores formed on said upper surface of said step portion, the diameter of entrances of the
increased-diameter pores is larger than the diameter of entrances of the anodizing pores formed on said upper surface of said
body portion, and at least some of said entrances of said increased-diameter pores formed on said upper surface of said step
portion being connected to each other to form a space, wherein the increased-diameter pores and the space serve to relieve
external stresses acting in a lateral direction.

US Pat. No. 10,008,638

METHOD FOR MANUFACTURING OPTICAL ELEMENT FOR BACKLIGHT UNIT AND OPTICAL ELEMENT AND OPTICAL ELEMENT ARRAY MANUFACTURED BY METHOD

Point Engineering Co., Lt...

1. A method of manufacturing an optical device for a back light unit, the method comprising steps of:(a) preparing an original substrate having vertical insulating layers interposed therebetween, the original substrate having an upper surface;
(a1) forming a cavity including a groove at a predetermined depth from the upper surface and including the vertical insulating layers on the original substrate;
(pb1) depositing a solder resist at least on the upper surface of the original substrate;
(pb2) forming through holes between which the vertical insulating layers are interposed;
(b) partially cutting the original substrate, along the through holes, to a predetermined depth from the upper surface thereof such that the cut portion is orthogonal at least to the vertical insulation layers, and exposing a region where a plating layer for soldering is to be formed;
(c) performing plating;
(d) mounting, inside the cavity, optical device chips on a plurality of chip substrate regions divided to include the vertical insulating layers; and
(e) cutting each chip substrate region;
wherein said step (pb1) is performed after said step (a) and before said step (b); and
wherein said step (a1) is performed before said step (pb1) and before said step (c).

US Pat. No. 9,595,642

CHIP SUBSTRATE COMPRISING A PLATED LAYER AND CHIP PACKAGE USING THE SAME

Point Engineering Co., Lt...

1. A chip substrate, comprising:
conductive portions laminated in one direction to constitute the chip substrate;
insulation portions vertically penetrating the conductive portions to electrically isolate the conductive portions;
a cavity formed at a predetermined depth in a recessed shape in a region including the insulation portions on an upper surface
of the chip substrate;

an insulation layer coated on an upper surface of the chip substrate excluding a region of the cavity; and
a plating layer continuously formed at a predetermined width along a periphery of the chip substrate on the insulation layer,
wherein a portion of a top surface of each insulation portion is exposed in the cavity, and another portion of the top surface
of each insulation portion is coated with the insulation layer.

US Pat. No. 10,015,841

MICRO HEATER AND MICRO SENSOR AND MANUFACTURING METHODS THEREOF

Point Engineering Co., Lt...

1. A micro heater comprising:a porous substrate formed of an aluminum oxide porous layer;
a heater electrode which is formed on said porous substrate and includes a heater wire and a heater electrode pad which is connected to said heater wire; and
an air gap which surrounds said heater wire is formed in said porous substrate,
wherein said air gap is formed by completely penetrating said porous substrate.

US Pat. No. 10,014,446

CHIP SUBSTRATE

POINT ENGINEERING CO., LT...

1. A chip substrate, comprising:a first conductive layer and a second conductive layer;
an insulation layer disposed between the first conductive layer and the second conductive layer, and configured to electrically isolate the first conductive layer and the second conductive layer from each other;
a cavity formed in a region including the first conductive layer, the second conductive layer and the insulation layer, and having a predetermined depth and a circular cross-section, wherein the cavity has a bottom surface exposing the insulation layer, a first inclined side surface formed in the first conductive layer and a second inclined side surface formed in the second conductive layer, the first inclined side surface and the second inclined side surface making the circular cross-section gradually larger upwardly from the bottom surface;
an optical element chip disposed at a center of the bottom surface; and
a wire electrically connecting the optical element chip and the first conductive layer to each other,
wherein the bottom surface includes a first bottom surface formed in the first conductive layer and a second bottom surface formed in the second conductive layer, a chip being capable of being disposed on the second bottom surface,
wherein the first inclined side surface includes an upper portion and a lower portion, the lower portion of the first inclined side surface extending from the first bottom surface,
wherein the second inclined side surface includes an upper portion and a lower portion, the lower portion of the second inclined side surface extending from the second bottom surface,
wherein the lower portion of the first inclined side surface extends vertically from the first bottom surface and the upper portion of the first inclined side surface extends from the lower portion of the first inclined side surface, and
wherein a first distance in a horizontal direction between the center of the upper portion of the cavity and the lower portion of the first inclined side surface is larger than a second distance in the horizontal distance between the center of the upper portion of the cavity and the lower portion of the second inclined side surface.

US Pat. No. 10,014,455

CHIP SUBSTRATE COMPRISING CAVITY WITH CURVED SURFACES

Point Engineering Co., Lt...

1. A chip substrate, comprising:conductive portions;
an insulation portion interposed between the conductive portions to electrically isolate the conductive portions from each other; and
a cavity formed on an upper surface of the chip substrate at a predetermined depth in a region including at least a part of the insulation portion,
wherein the cavity is defined by a plurality of continuously-extending curved surfaces having predetermined radii of curvature and a shape symmetrical with respect to a chip to be mounted on the chip substrate, and includes a central portion formed into a planar surface, and
the plurality of continuously-extending curved surfaces include a first smoothly curved surface and a second smoothly curved surface smoothly extending from the first curved surface, the first and the second curved surface being edgeless, wherein one of the first and the second curved surface is concave-up and the other of the first and the second curved surface is concave-down,
wherein the conductive portions having a predetermined thickness and made of an electrically conductive material and the insulation portion made of an insulating material are bonded to each other in parallel surface, and the insulation portion is in the continuously-extending curved surfaces,
and wherein the cavity further includes an auxiliary groove which is formed in a smaller area and a smaller depth than the cavity and is contiguous to the surface of the cavity in one of the conductive portions and has a planar bottom surface so that one end of a wire is bonded to the electrode portion of an optical element chip and the other end of the wire is bonded to the planar bottom surface of the auxiliary groove when the optical element chip is mounted within the cavity in the other of the conductive portion.

US Pat. No. 10,062,812

SUBSTRATE FOR CAN PACKAGE-TYPE OPTICAL DEVICE AND OPTICAL DEVICE USING SAME

Point Engineering Co., Lt...

1. A substrate for a can package-type optical device comprising:a metal plate wherein at least one through hole is formed in the metal plate;
a metal substrate having at least one vertical insulation layer crossing the metal substrate completely in a vertical direction, wherein at least one cavity defined by a bottom surface of the cavity depressed from a top surface of the metal substrate and a side wall surface of the cavity connecting the bottom surface of the cavity with the top surface of the metal substrate is formed in the metal substrate such that the cavity vertically overlaps the through hole to expose the bottom surface of the cavity and the sidewall surface of the cavity whereas the top surface of the metal substrate is completely covered by the metal plate; and
an adhesive layer bonding a bottom surface of the metal plate and the top surface of the metal substrate, the adhesive layer formed from a liquid adhesive and further comprising an adhesive film inserted in the adhesive layer,
wherein the vertical insulation layer is exposed at the bottom surface of each cavity,
an inner surface of the through hole is metal-plated,
the side wall surface and the bottom surface of the cavity are metal-plated, and
the adhesive layer is exposed without being metal-plated.

US Pat. No. 10,128,414

CHIP SUBSTRATE PROVIDED WITH JOINING GROOVES IN LENS INSERT

Point Engineering Co., Lt...

1. A chip substrate comprising:a plurality of conductive layers arranged horizontally;
a plurality of insulation layers arranged alternately with said plurality of conductive layers and electrically separating said plurality of conductive layers from one another;
a lens insert depressed from an upper surface of the chip substrate, the lens insert having a shape of a polygon whose corners are convex arc-shaped;
a cavity reaching down to a predetermined depth at an area including at least a part of said plurality of insulation layers within said lens insert; and
a plurality of joining grooves formed on a surface of said lens insert.

US Pat. No. 10,163,567

MULTI-LAYERED ALUMINUM OXIDE CAPACITOR

POINT ENGINEERING CO., LT...

1. A multi-layered capacitor comprising:an aluminum substrate having at least one bending portion;
anodized aluminum oxide layers partially formed on both sides of the aluminum substrate by anodizing the aluminum substrate such that the anodized aluminum oxide layers are vertically aligned with each other with respect to a surface of the aluminum substrate;
metal electrode layers, formed on and in direct contact with the anodized aluminum oxide layers, respectively; and
at least one lead portion formed between the metal electrode layers for applying electricity to the metal electrode layers which are bonded together,
wherein the anodized aluminum oxide layers are not formed at the bending portion, and the anodized aluminum oxide layers function as dielectric layers of the capacitor,
wherein the bending portion comprises a groove having a V-shaped cross-section, and
a peak of the V-shaped cross-section of the groove faces a direction perpendicular to a stacking direction of the multi-layered capacitor.

US Pat. No. 10,170,731

MASK AND MASKING ASSEMBLY

Point Engineering Co., Lt...

1. A mask for forming a pattern on a substrate, comprising:an anodic oxide film formed by anodizing metal;
at least one transmission hole configured to vertically penetrate the anodic oxide film and formed in a corresponding relationship with the pattern, the at least one transmission hole having a diameter;
a plurality of pores formed in the anodic oxide film so as to have a smaller diameter than the at least one transmission hole; and
a magnetic material provided in each of the pores such that each of the pores is at least partially filled with the magnetic material.

US Pat. No. 10,193,207

SUBSTRATE FOR SUPPORTING ANTENNA PATTERN AND ANTENNA USING SAME

Point Engineering Co., Lt...

1. A substrate for supporting an antenna pattern, comprising:a porous anodic oxide layer having a plurality of pores formed by anodizing metal;
a first metal pattern formed on the porous anodic oxide layer; and
a second metal pattern formed so as to surround at least a part of the first metal pattern;
wherein metallic materials are filled in the pores positioned below the first and second metal patterns.

US Pat. No. 10,241,094

MICRO HEATER, MICRO SENSOR AND MICRO SENSOR MANUFACTURING METHOD

Point Engineering Co., Lt...

1. A micro heater, comprising:a substrate having an upper surface and a lower surface and including a first support portion;
a heater electrode formed on the substrate and provided with a heat generation wiring line supported by the first support portion; and
a plurality of air gaps formed in the substrate around the heat generation wiring line, wherein the air gaps are formed discontinuously around the periphery of the first support portion among the regions excluding the portion supporting the heater electrode and includes a space formed penetrating from the upper surface to the lower surface of the substrate,
wherein the heat generation wiring line includes at least a first heat generation wiring line and a second heat generation wiring line laminated along the up-down direction,
wherein a passivation layer is formed between the first heat generation wiring line and the second heat generation wiring line,
wherein the substrate is formed of an aluminum oxide porous layer,characterized in that the aluminum oxide porous layer is formed to form pores penetrating from the upper surface to the lower surface of the substrate.

US Pat. No. 10,281,418

MICRO HEATER AND MICRO SENSOR

Point Engineering Co., Lt...

1. A micro heater comprising:a substrate having a first supporting portion;
a heater electrode formed on said first supporting portion;
an anti-etching dam configured for preventing shape deformation of the first supporting portion by etching solution, formed on said first supporting portion; and
an air gap formed by etching and surrounding the periphery of said first supporting portion,
wherein the substrate further comprises a second supporting portion and a bridge portion connecting said first supporting portion and said second supporting portion, and said heater electrode comprises a heating wire formed on said first supporting portion and a heater electrode pad connected to said heating wire and formed on said second supporting portion and said bridged portion,
wherein the heating wire comprises a plurality of arc portions formed in the shape of an arc, and a plurality of connecting portions connecting said arc portions,
wherein the anti-etching dam is formed between one end of the outermost arcs of the plurality of arc portions forming the heating wire and the other end of the outermost arcs.

US Pat. No. 10,433,370

MICRO MULTI-ARRAY HEATER AND MICRO MULTI-ARRAY SENSOR

Point Engineering Co., Lt...

1. A multi-array sensor with a multi-array heater comprising:a substrate, which is an anodic oxide film including a porous layer, obtained by anodizing a metallic base material and then removing the base material; and
heater electrodes formed on the substrate, wherein the heater electrodes include a first heater electrode having a first heat generation pattern and a second heater electrode having a second heat generation pattern, and
the first heat generation pattern and the second heat generation pattern are formed to have different heat generation amounts and different thicknesses.