US Pat. No. 9,585,272

STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A storage device, comprising:
a casing having a bottom plate, a top plate, and a main assembling structure;
a bearing member having an interfering portion and a sub-assembling structure; and
a storage unit having a body, a limiting portion and a terminal set, wherein the body has a first surface and a second surface
opposite to each other, parts of the terminal set and the limiting portion are located at the first surface, the storage unit
and the interfering portion are accommodated in the casing, and the interfering portion is located between the top plate and
the limiting portion, wherein the interfering portion provides an interfering force to the limiting portion and the bottom
plate provides a supporting force to the second surface so that the storage unit is positioned in the casing, and the main
assembling structure and the sub-assembling structure are assembled detachably to each other to configure or detach the bearing
member and the casing,

wherein the body has at least one memory chip and elements belonging to the body are entirely enclosed in a single package,
and

wherein a length of the bearing member along a first axis is greater than a length of the storage unit along the first axis,
and the first axis is parallel to the first surface.

US Pat. No. 9,526,186

STORAGE DEVICE AND PRODUCING METHOD OF THE SAME

PHISON ELECTRONICS CORP.,...

1. A storage device, comprising:
a housing, having an opening, wherein the housing comprises:
a bottom plate;
a top plate, having the opening, wherein the opening extends from a rear of the housing into a top surface of the top plate;
and

a pair of side plates, each of which is connected between the bottom plate and the top plate and opposite to each other;
a connector, disposed in the housing and having a main body, a first terminal set, a plurality of pad terminals, and a plurality
of elastic terminals,

wherein the pad terminals and the elastic terminals are disposed at a first end of the main body, the first terminal set is
disposed at a second end opposite to the first end of the main body, and the pad terminals and the elastic terminals are electrically
connected with the first terminal set correspondingly,

wherein the main body has a first supporting portion and a second supporting portion, the first terminal set is disposed on
the first supporting portion, the pad terminals and the elastic terminals are disposed on the second supporting portion,

wherein the pad terminals and the elastic terminals are for electrically connecting an external device, the pad terminals
and the elastic terminals are electrically independent from each other, and the elastic terminals are covered by the top plate,

wherein the pad terminals are integrally formed with a portion of terminals of the first terminal set respectively, and the
elastic terminals are integrally formed with another portion of terminals of the first terminal set respectively; and

a storage element, disposed in the housing and having a plurality of pads, wherein the first terminal set is connected with
the pads correspondingly to enable the connector to be electrically connected with the storage element, and the first terminal
set and the pads are exposed out of the housing through the opening, wherein the bottom plate has at least one protrusion
toward the top plate, and the protrusion leans against the storage element.

US Pat. No. 9,563,508

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory management method for a rewritable non-volatile memory module, the rewritable non-volatile memory module having
a plurality of physical programming units, and each of the physical programming units having a plurality of bits, the memory
management method comprising:
identifying a first physical programming unit among the physical programming units by applying a predetermined read voltage,
wherein the first physical programming unit is identified as in a fully-erased status;

identifying a second physical programming unit and at least one third physical programming unit, wherein the second physical
programming unit is programmed before the first physical programming unit, and the at least one third physical programming
unit is programmed before the second physical programming unit;

acquiring status data of the second physical programming unit and at least one status data of the at least one third physical
programming unit;

computing a difference between the status data of the second physical programming unit and the at least one status data of
the at least one third physical programming unit; and

if the difference is greater than a threshold, identifying the second physical programming unit as in a program failure status.

US Pat. No. 9,064,968

NON-VOLATILE MEMORY DEVICE AND OPERATION AND FABRICATING METHODS THEREOF

PHISON ELECTRONICS CORP.,...

1. A non-volatile memory device, comprising:
a well, disposed in a substrate;
a plurality of first word lines and a plurality of second word lines, disposed on the substrate, arranged periodically and
extending in a first direction;

a plurality of inter-poly dielectric films, disposed on the substrate and respectively beneath the plurality of first word
lines and the plurality of second word lines;

a plurality of floating gates, disposed between the well and the plurality of inter-poly dielectric films; and
a plurality of tunnel oxide films, disposed between the well and the plurality of floating gates,
wherein a first distance from the first word lines to the substrate is smaller than a second distance from the second word
lines to the substrate.

US Pat. No. 9,158,476

METHOD FOR SWITCHING OPERATION MODE, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. An operation mode switching method for a memory storage apparatus, an operation mode of the memory storage apparatus comprising
a first mode and a second mode, the operation mode switching method comprising:
receiving at least one access command from a host system;
determining whether the at least one access command conforms to a predetermined pattern; and
switching the operation mode of the memory storage apparatus from the first mode to the second mode if the at least one access
command conforms to the predetermined pattern, wherein the at least one access command comprises a first write command and
a plurality of first read commands, the first write command comprises a write string, and

wherein the write string instructs the memory storage apparatus to execute an operation corresponding to the write string,
wherein the step of determining whether the at least one access command conforms to the predetermined pattern comprises:
determining whether the first read commands conform to a predetermined read pattern;
determining whether the write string indicated by the first write command conforms to one of a plurality of predetermined
command patterns if the first read commands conform to the predetermined read pattern; and

identifying the at least one access command as conforming to the predetermined pattern if the write string indicated by the
first write command conforms to one of the predetermined command patterns.

US Pat. No. 9,136,875

DECODING METHOD, MEMORY STORAGE DEVICE AND REWRITABLE NON-VOLATILE MEMORY MODULE

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module, the decoding method comprising:
reading a plurality of bits from the rewritable non-volatile memory module according to a first reading voltage;
performing a parity check of a low density parity check algorithm on the bits to obtain a plurality of syndromes, wherein
each of the bits corresponds to at least one of the syndromes;

determining whether the bits have at least one first error according to the syndromes;
if the bits have the at least one first error, obtaining a syndrome weight of each of the bits according to the syndromes
corresponding to each of the bits, wherein the syndrome weights comprises a first syndrome weight of a first bit among the
bits and a second syndrome weight of a second bit among the bits, wherein the first syndrome weight is different from the
second syndrome weight;

obtaining a first initial value of each of the bits according to the syndrome weight of each of the bits; and
performing a first iteration decoding of the low density parity check algorithm on the bits according to the first initial
values.

US Pat. No. 9,304,907

DATA MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical erasing units and a plurality of logical units for mapping to at least a part of the plurality
of physical erasing units, and each of the physical erasing units has a plurality of physical programming units, wherein each
of the physical programming units at least stores an error checking and correcting frame, the data management method comprising:
receiving first data;
identifying a first physical programming unit among the plurality of physical programming units;
identifying a first address of the first physical programming unit;
if the first data is incompressible and the first address of the first physical programming unit is meeting a requirement
of start address, storing the first data starting from the first address; and

if the first data is incompressible and the first address of the first physical programming unit is not meeting the requirement
of start address, storing padding data starting from the first address, and storing the first data starting from a following
address, wherein the following address is meeting the requirement of start address.

US Pat. No. 9,286,986

DATA WRITING METHOD, AND MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data writing method for writing data into a memory cell of a rewritable non-volatile memory module of a memory storage
apparatus to prevent an error bit caused by an over-writing, the data writing method comprising:
detecting an operating temperature of the memory storage apparatus;
determining whether the operating temperature of the memory storage apparatus is larger than a predetermined temperature;
and

adjusting at least one predetermined operation parameter corresponding to the rewritable non-volatile memory module to generate
at least one adjusted operation parameter corresponding to the rewritable non-volatile memory module and writing the data
into the memory cell based on the at least one adjusted operation parameter if the operating temperature of the memory storage
apparatus is larger than the predetermined temperature,

wherein the at least one adjusted operation parameter is configured to adjust a number of a plurality of electrons to be injected
to the memory cell corresponding to the data.

US Pat. No. 9,257,204

READ VOLTAGE SETTING METHOD, AND CONTROL CIRCUIT, AND MEMORY STORAGE APPARATUS USING THE SAME

PHISON ELECTRONICS CORP.,...

7. A read voltage setting method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
includes a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each of the memory cells electrically
connected to one of the word lines and one of the bit lines, each of the memory cells is configured to store a plurality of
bit data, each of the plurality of bit data is identified as a first state or a second state based on a voltage, the read
voltage setting method comprising:
programming data into a plurality of memory cells connected to a first word line among the word lines;
adjusting a first default read voltage corresponding to the word line to obtain a plurality of first test read voltages;
respectively applying the first test read voltages to the first word line to read a plurality of first page data;
obtaining an error bit number corresponding to each of the plurality of first page data according to the data and the plurality
of first page data;

obtaining a first optimized read voltage corresponding to the first word line from the first test read voltages according
to a minimum error bit number among the error bit numbers corresponding to the plurality of first page data;

calculating a difference value between the first optimized read voltage and the first default read voltage as a first read
voltage adjustment value corresponding to the first word line; and

recording the first read voltage adjustment value corresponding to the first word line in a retry table.

US Pat. No. 9,324,435

DATA TRANSMITTING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data transmitting method for a memory storage apparatus having a rewritable non-volatile memory module, and the data
transmitting method comprising:
(a) initially setting a first threshold and a first accumulated value;
(b) updating the first threshold by using the first threshold plus the first accumulated value at intervals of a first predetermined
time;

(c) receiving a writing data;
(d) detecting a temperature of the memory storage apparatus;
(e) determining whether the temperature of the memory storage apparatus is greater than or equal to a temperature threshold,
wherein step (f) is executed if the temperature of the memory storage apparatus is not greater than or equal to the temperature
threshold, and step (g) is executed if the temperature of the memory storage apparatus is greater than or equal to the temperature
threshold;

(f) writing the writing data into the rewritable non-volatile memory module;
(g) determining whether a size of the writing data is greater than or equal to the first threshold, wherein step (h) is executed
if the size of the writing data is not greater than or equal to the first threshold, and step (i) is executed if the size
of the writing data is greater than or equal to the first threshold;

(h) writing the writing data into the rewritable non-volatile memory module, and updating the first threshold by using the
first threshold minus the size of the writing data; and

(i) not writing the writing data into the rewritable non-volatile memory module, and re-executing the step (g) after the first
predetermined time.

US Pat. No. 9,141,530

DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data writing method for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory
module comprises a plurality of physical erasing units, each of the physical erasing units comprises a plurality of physical
programming unit groups, each of the physical programming unit groups comprises a plurality of physical programming units,
the physical programming units of each of the programming unit groups comprise a lower physical programming unit and a upper
physical programming unit, wherein a programming speed of the lower physical programming units is faster than a programming
speed of the upper physical programming units, and a plurality of logical addresses is mapped to a plurality of first physical
erasing units of the physical erasing units, the data writing method comprising:
receiving a first write command, which instructs writing data to at least one first logical address of the logical addresses,
wherein the at least one first logical address is mapped to a second physical erasing unit in the first physical erasing units;

determining whether the second physical erasing unit is in a sequential writing state which represents that the physical programming
units over a predetermined ratio in the second physical erasing unit have been programmed sequentially within a predetermined
time; and

writing the data into a third physical erasing unit of the physical erasing units in a first programming mode if the second
physical erasing unit is in the sequential writing state, wherein the first programming mode represents that the upper programming
units are non-programmable.

US Pat. No. 9,349,475

TIME ESTIMATING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A time estimating method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of memory cells, and the time estimating method comprises:
writing first data into a plurality of first memory cells of the memory cells;
reading the first memory cells according to a reading voltage, so as to determine whether each of the first memory cells belongs
to a first state or a second state; and

calculating a first quantity of the first memory cells belonging to the first state, and obtaining first time information
of the rewritable non-volatile memory module according to the first quantity.

US Pat. No. 9,257,187

DATA STORING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data storing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has
a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each of the memory cells electrically
connects with one of the word lines and one of the bit lines, each of the memory cells stores a plurality of bit data, and
each of the bit data may, according to at least a voltage, be identified as a first state or a second state, the data storing
method comprises:
programming data into a plurality of memory cells connecting to a first word line among the word lines, wherein a first predetermined
reading voltage is initially configured for the first word line;

adjusting the first predetermined reading voltage to obtain a first available reading voltage for the first word line and
applying the first available reading voltage to the first word line to read first page data, wherein the first page data may
be corrected by an error checking and correcting circuit correctly; and

when a first difference value between the first available reading voltage and the first predetermined reading voltage is larger
than a first predetermined threshold value, programming the first page data into a plurality of memory cells connecting to
a second word line among the word lines, wherein the second word line is different from the first word line.

US Pat. No. 9,128,624

FLASH MEMORY STORAGE SYSTEM FOR SIMULATING REWRITABLE DISC DEVICE, FLASH MEMORY CONTROLLER, COMPUTER SYSTEM, AND METHOD THEREOF

PHISON ELECTRONICS CORP.,...

1. A flash memory storage system, comprising:
a flash memory chip, having a plurality of physical blocks;
a connector, configured to couple to a host system; and
a controller, coupled to the flash memory chip and the connector and configured to configure a plurality of logical blocks
and map the logical blocks to a portion of the physical blocks,

wherein the controller is further configured to identify at least one rewritable disc command from the host system and to
write data from the host system into the physical blocks mapped to at least a portion of the logical blocks according to the
at least one rewritable disc command,

wherein the controller is further configured to establish at least one management information of a rewritable disc device,
wherein the at least one management information of the rewritable disc device comprises a written capacity parameter, and
the written capacity parameter records a written capacity of the at least a portion of the logical blocks, wherein the written
capacity parameter is updated according to a capacity of the data after the data is written,

wherein the written capacity parameter is also updated according to a size of a close section without the data being written,
wherein the controller is further configured to obtain a next writable address according to the written capacity parameter,
and to write the data from the host system into the physical blocks starting from the physical block mapped to the logical
block corresponding to the next writable address.

US Pat. No. 9,058,863

REFERENCE FREQUENCY SETTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A reference frequency setting method of a rewritable non-volatile memory storage apparatus, wherein the rewritable non-volatile
memory storage apparatus comprises a rewritable non-volatile memory module, a storage unit, and an oscillator circuit module,
and the oscillator circuit module comprises a register circuit, the rewritable non-volatile memory storage apparatus does
not comprise a crystal oscillator, and the reference frequency setting method comprises:
reading a setting code from the rewritable non-volatile memory module or the storage unit by a first signal transmission path,
and storing the setting code into the register circuit, wherein the setting code comprises a first setting information;

detecting whether a data having a first frequency is inputted;
if the data having the first frequency is not inputted, reading the setting code stored in the register circuit, such that
the oscillator circuit module generates a first reference frequency based on the first setting information of the setting
code;

if the data having the first frequency is inputted, updating the setting code stored in the register circuit by a second signal
transmission path, wherein the updated setting code comprises a second setting information; and

if the data having the first frequency is inputted, reading the updated setting code stored in the register circuit, such
that the oscillator circuit module generates a second reference frequency based on the second setting information.

US Pat. No. 9,310,869

MEMORY STORAGE DEVICE, MEMORY CONTROL CIRCUIT UNIT AND POWER SUPPLY METHOD

PHISON ELECTRONICS CORP.,...

10. A memory control circuit unit configured to control a rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module comprises a plurality of physical erasing units, and the memory control circuit unit comprises:
a host interface circuit configured to couple to a host system;
a memory management circuit;
a memory interface circuit configured to couple to the rewritable non-volatile memory module; and
a power supply module coupled to the host interface circuit, the memory management circuit and the memory interface circuit,
wherein the power supply module is configured to provide a first power voltage to a power input terminal of the host interface
circuit,

the power supply module is further configured to provide a second power voltage to a power input terminal of the memory management
circuit, and

the power supply module is further configured to provide a third power voltage to a power input terminal of the memory interface
circuit,

wherein a reference voltage terminal of the memory interface circuit is coupled to the power input terminal of the memory
management circuit, and voltage values of the first power voltage, the second power voltage and the third power voltage are
different from one another.

US Pat. No. 9,237,005

CLOCK DATA RECOVERY CIRCUIT MODULE AND METHOD FOR GENERATING DATA RECOVERY CLOCK

PHISON ELECTRONICS CORP.,...

1. A crystal-less clock data recovery circuit module, comprising:
a clock data recovery circuit, configured to output a data recovery stream and a data recovery clock;
a frequency comparison circuit, coupled to the clock data recovery circuit, wherein the frequency comparison circuit is configured
to compare a frequency difference between the data recovery clock and a clock signal to adjust a frequency of the clock signal
based on a comparison result; and

a signal detection circuit, coupled to the frequency comparison circuit and configured to receive and detect a first signal,
wherein the signal detection circuit determines whether to enable the frequency comparison circuit according to a detection
result,

wherein the clock data recovery circuit comprises:
a frequency generation circuit, coupled to the frequency comparison circuit and configured to generate the clock signal and
output a control signal according to the comparison result; and

a clock generation circuit, coupled to the frequency generation circuit and configured to generate the data recovery clock
with reference to the clock signal,

wherein the frequency generation circuit comprises:
a reference clock generation circuit, configured to generate and output a reference clock; and
a phase-locked loop circuit, coupled to the frequency comparison circuit, wherein the phase-locked loop circuit is controlled
by the control signal and configured to generate the clock signal according to the control signal and the reference clock.

US Pat. No. 9,201,785

DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method for writing data into a rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module includes at least one memory die, the memory die includes a plurality of physical erasing units, wherein each
of the physical erasing units includes a plurality of physical programming units, the data writing method comprising:
receiving a first write command and first data corresponding to the first write command and temporarily storing the first
data into a buffer memory, wherein the first data includes a plurality of sub data streams,

transmitting the sub data streams from the buffer memory to the rewritable non-volatile memory module to write the sub data
streams into at least one first physical erasing unit among the physical erasing units;

generating parity information based on at least a portion of the sub data streams;
storing the parity information into the buffer memory; and
deleting the first data from the buffer memory while temporarily keeping the parity information in the buffer memory after
transmitting the sub data streams from the buffer memory to the rewritable non-volatile memory module to write the sub data
streams into the at least one first physical erasing unit among the physical erasing units.

US Pat. No. 9,448,868

DATA STORING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

9. The data storing method as recited in claim 8, further comprising:
if the bit error count of the at least one of the one or more predetermined areas of the first physical programming unit is
more than the threshold bit error count, programming dummy data into the first physical programming unit.

US Pat. No. 9,312,013

CONFIGURATION METHOD OF ERASE OPERATION, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A configuration method of erase operation for a rewritable non-volatile memory module comprising a plurality of physical
units, the configuration method of erase operation comprising:
determining whether a first use state of a first physical unit of the physical units conforms to a first default state;
adjusting a first erase operation corresponding to the first physical unit from using a first mode to a second mode if the
first use state conforms to the first default state, wherein the first mode and the second mode are different; and

maintaining the first erase operation in using the first mode if the first use state does not conform to the first default
state.

US Pat. No. 9,304,900

DATA READING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data reading method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of physical erasing units, the data reading method comprising:
configuring a plurality of logical addresses to be mapped to a part of the physical erasing units;
receiving a plurality of first read commands from a host system, wherein the first read commands instruct to read a plurality
of first logical addresses among the logical addresses;

executing the first read commands;
rearranging the first logical addresses as a plurality of rearranged first logical addresses in an ascending or a descending
order and determining whether the first logical addresses are successive according to the rearranged first logical addresses;
and

if the first logical addresses are successive, pre-reading data belonging to a first logical range among he logical addresses
from the physical erasing units into a buffer memory.

US Pat. No. 9,299,859

CAPACITOR STRUCTURE APPLIED TO INTEGRATED CIRCUIT

PHISON ELECTRONICS CORP.,...

1. A capacitor structure applied to an integrated circuit, the capacitor structure comprising:
a metal-oxide semiconductor capacitor having a first terminal and a second terminal; and
two metal capacitors comprising a first metal capacitor and a second metal capacitor, wherein the first metal capacitor does
not comprise a finger-like structure, the second metal capacitor comprises the finger-like structure, and the two metal capacitors
are formed above the metal-oxide semiconductor capacitor and respectively coupled between the first terminal and the second
terminal,

wherein a first level of metal electrode of the first metal capacitor and a first level of metal electrode of the second metal
capacitor are located in a same first metal layer,

wherein a second level of metal electrode of the first metal capacitor and a second level of metal electrode of the second
metal capacitor are located in a same second metal layer, wherein the second metal layer is located above the first metal
layer.

US Pat. No. 9,245,636

NAND FLASH MEMORY UNIT, OPERATING METHOD AND READING METHOD

PHISON ELECTRONICS CORP.,...

1. A NAND flash memory unit comprising:
a plurality of gate layers, wherein a first dielectric layer is comprised between two adjacent gate layers among the gate
layers;

a tunnel layer, penetrating the gate layers;
a charge trapping layer, penetrating the gate layers and disposed between the tunnel layer and the gate layers;
a conductor layer, penetrating the gate layers; and
a second dielectric layer, penetrating the gate layers, wherein the second dielectric layer is disposed between the conductor
layer and the tunnel layer.

US Pat. No. 9,058,296

DATA PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data processing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical programming units, each of the physical programming units comprises a data bit area comprising
a plurality of physical addresses and a redundant bit area configured to record a plurality of flags, and each of the physical
addresses corresponds to one of the plurality of flags, the data processing method comprising:
configuring, by a memory control circuit, a plurality of logical addresses and mapping the logical addresses to parts of the
physical programming units;

receiving from a host system, by a memory control circuit, a reading command of reading a first logical address of the logical
addresses, wherein the first logical address is mapped to a first physical programming unit of the physical programming units;

performing, by a memory control circuit, a first reading process, wherein the first reading process comprises:
reading first data stored in the physical addresses of the first physical programming unit;
determining whether a first flag of the flags corresponding to the physical addresses of the first physical programming unit
is in a first status or in a second status;

if the first flag is in the first status, performing a decryption operation on a part of the first data stored in the physical
address corresponding to the first flag according to a first key to obtain first decrypted data, and transmitting the first
decrypted data to the host system; and

if the first flag is in the second status, performing the decryption operation on specific-format data according to the first
key to obtain second decrypted data, and transmitting the second decrypted data to the host system.

US Pat. No. 9,471,421

DATA ACCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data accessing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical erasing units, wherein each of the physical erasing units comprises a plurality of physical
programming units, and the data accessing method comprises:
determining whether a first physical programming unit configured to store first data among the physical programming units
belongs to a first type physical programming unit or a second type physical programming unit;

if the first physical programming unit belongs to the first type physical programming unit, generating a first verification
code corresponding to the first data and a second verification code for being combined with the first verification code, and
writing the first data and the first verification code into the first physical programming unit; and

combining the second verification code and the first verification code to decode the first data if the first data is decoded
unsuccessfully by using the first verification code.

US Pat. No. 9,280,737

SYSTEM IN PACKAGE STRUCTURE, ELECTROPLATING MODULE THEREOF AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A system in package (SIP) structure, comprising:
a first layout layer, comprising:
a first pad, close to a first side of the first layout layer, and configured to couple to a ground voltage; and
a wire, one terminal of the wire being coupled to the first pad, and another terminal of the wire being coupled to an opening
of the SIP structure, wherein the opening is located at a second side of the first layout layer opposite to the first side,
and the opening is configured to couple to an external voltage;

a second layout layer, disposed opposite to the first layout layer; and
a rewritable non-volatile memory module, disposed on the first layout layer or the second layout layer.

US Pat. No. 9,136,661

STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A storage device, comprising:
a storage module, having a substrate, a first terminal set and a second terminal set, wherein the first and the second terminal
sets are disposed on opposite surfaces of the substrate; and

a sheath member, having an opening and a third terminal set, wherein a portion of the third terminal set is exposed out of
the sheath member, at least a portion of the storage module is sheathed in the sheath member such that the first terminal
set is exposed out of the sheath member through the opening, the second terminal set is electrically connected to the third
terminal set, and the first terminal set exposed out of the sheath member and the portion of the third terminal set exposed
out of the sheath member form a first connection interface.

US Pat. No. 9,424,206

COMMAND EXECUTING METHOD, CONNECTOR AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A command executing method for a memory storage device, comprising:
receiving commands and tags respectively corresponding to the commands from a host system, and temporarily storing the commands
in a command queue;

transmitting the tags to the host system and executing the commands;
in response to completion of executing the commands, keeping the tags corresponding to the commands by holding a configuration
message for releasing the tags from corresponding to the commands being transmitted to the host system;

determining whether an operating status of the memory storage device meets a predetermined condition while holding the configuration
message; and

transmitting, if the operating status meets the predetermined condition, the configuration message to the host system to release
the tags from corresponding to the commands, wherein one of the tags is re-corresponded to another command to be executed
after the tags are released from corresponding to the commands.

US Pat. No. 9,383,929

DATA STORING METHOD AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data storing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has
a plurality of physical erase units, each of the physical erase units has a plurality of physical program units, and the physical
erase units are grouped into at least a system area, the data storing method comprising:
writing system data into a first physical erase unit in the system area;
determining whether the first physical erase unit contains a dancing bit; and
when the first physical erase unit contains the dancing bit, selecting a second physical erase unit among the physical erase
units, and writing the system data into the second physical erase unit.

US Pat. No. 9,229,798

ERROR HANDLING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. An error handling method for a memory controlling circuit unit, wherein a plurality of channels are coupled between the
memory controlling circuit unit and a rewritable nonvolatile memory module, the error handling method comprising:
obtaining a finished event corresponding to a first channel among the channels;
determining whether the finished event is a failed event;
if the finished event is the failed event, stopping an operation of the first channel and performing a first update operation
on a counting value corresponding to the first channel;

if the finished event is not the failed event, keeping the counting value corresponding to the first channel unchanged; and
processing the finished event, wherein the step of processing the finished event comprises:
if the finished event is the failed event, performing a second update operation on the counting value corresponding to the
first channel and performing an error handling procedure; and

if the counting value matches a threshold criterion, recovering the operation of the first channel.

US Pat. No. 9,128,709

DIVIDING A POWER INPUT AND DIRECTLY PROVIDING DIVIDED POWER TO AN OUTPUT TERMINAL IN A POWER CONTROL CIRCUIT

PHISON ELECTRONICS CORP.,...

19. A power control circuit, comprising:
a first power supply channel, for receiving a first power input and determining whether to provide the first power input to
data processing control unit according to a first control signal;

a second power supply channel, for receiving a second power input and determining whether to provide the second power input
to the data processing control unit according to a second control signal;

a voltage limiting unit, coupled between the first power supply channel and the second power supply channel for limiting a
reverse voltage fed back to the second power supply channel from the first power supply channel to smaller than a specific
value or limiting the reverse voltage fed back to the first power supply channel from the second power supply channel to smaller
than the specific value; and

a voltage dividing unit, coupled to the first power input and configured for dividing a voltage of the first power input and
directly provide to the divided first power input to the output terminal of the power control unit via a voltage dividing
node.

US Pat. No. 9,362,951

DECODING METHOD, DECODING CIRCUIT, MEMORY STORAGE DEVICE AND CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for low density parity code, and for a rewritable non-volatile memory module, wherein the rewritable
non-volatile memory module comprises a plurality of first memory cells, and the decoding method comprises:
reading a data bit of each of the first memory cells;
performing a parity check procedure on the data bits to generate a plurality of checks;
in an iterative decoding of the low density parity code, obtaining reliability message of each of the data bits according
to the checks, and deciding an index of an error bit from the data bits according to the reliability messages, wherein the
index of the error bit comprises at least one of a first index of a first error bit and a second index of a second error bit,
wherein the first error bit corresponding to the first index is different from the second error bit corresponding to the second
index in an arrangement of the data bits;

determining whether the index of the error bit and the checks comply with a parity criteria; and
if the index of the error bit and the checks comply with the parity criteria, stopping the iterative decoding, and correcting
the data bit according to the index of the error bit, wherein the first index is used to correct the first error bit, and
the second index is used to correct the second error bit.

US Pat. No. 9,280,460

DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and the
data writing method comprising:
associating the physical erasing units with a data area, a backup area or a spare area;
configuring a plurality of first logical units and a plurality of second logical units for being accessed by a host system,
wherein the first logical units are mapped to physical erasing units associated with the data area, and second logical units
are mapped to the physical erasing units associated with the backup area;

setting a value obtained by summing a minimum threshold and a predetermined number as a garbage collecting threshold, wherein
the minimum threshold is the number of physical erasing units required for a data merging operation, and the predetermined
number is the number of physical erasing units reserved dedicating to write backup data;

receiving a first write command from the host system, wherein the first write command instructs to write first data into at
least one logical unit among the second logical units; and

getting at least one first physical erasing unit from among the physical erasing units of the spare area, writing the first
data into the at least one first physical erasing unit, associating the at least one first physical erasing unit with the
backup area, and adjusting the garbage collecting threshold according to a number of the at least one first physical erasing
unit and the minimum threshold,

wherein the adjusted garbage collecting threshold is obtained by subtracting the number of the physical erasing units associated
with the backup area among the physical erasing units from the value obtained by summing the minimum threshold and the predetermined
number, and the number of the physical erasing units associated with the backup area among the physical erasing units is not
greater than the predetermined number.

US Pat. No. 9,146,861

MEMORY ADDRESS MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A memory address management method for a rewritable non-volatile memory module, the rewritable non-volatile memory module
comprising a plurality of physical erasing units, each of the physical erasing units comprising a plurality of lower physical
programming units and a plurality of upper physical programming units, the lower and upper physical programming units being
programmed in a programming sequence, a plurality of logical addresses being mapped to parts of the physical erasing units,
the logical addresses constituting a plurality of logical programming units mapped to the lower and upper physical programming
units of each of the parts of the physical erasing units, the logical programming units being divided into a plurality of
lower logical programming units and a plurality of upper logical programming units, the memory address management method comprising:
obtaining memory information of the rewritable non-volatile memory module, wherein the memory information comprises the programming
sequence; and

formatting the logical addresses according to the memory information to establish a file system, such that the file system
comprises a plurality of allocation units, wherein a first allocation unit of the allocation units comprises a first lower
logical programming unit of the lower logical programming units and a first upper logical programming unit of the upper logical
programming units, the first allocation unit starts with the first lower logical programming unit and ends with the first
upper logical programming unit, and an initial logical address of a data region in the file system belongs to one of the lower
logical programming units; and

wherein the upper physical programming unit and lower physical programming unit are on the same word line.

US Pat. No. 9,395,768

FLASH DRIVE

PHISON ELECTRONICS CORP.,...

1. A flash drive, comprising:
a housing being flexible, and an inner space being formed by the housing;
a storage module, movably disposed in the inner space; and
at least one elastic member, disposed in the inner space and between the storage module and the housing, the housing being
adapted to be deformed by a force to compress the inner space, so as to provide a pushing force to the storage module for
moving towards a first direction and deform the elastic member,

wherein the storage module comprises a storage element and a connector electrically connected to each other, the inner space
has a channel connected through to an external environment, the storage element moves between a first position and a second
position in the channel, the storage element and the connector are hidden in the inner space when the storage element is located
at the first position, and the connector moves out from the inner space when the storage element is located at the second
position, and

wherein the storage element has a first positioning portion, the housing further has a second positioning portion and a third
positioning portion, the second positioning portion and the third positioning portion are formed on an inner wall of the housing,
the second positioning portion and the third positioning portion are located on a moving path of the first positioning portion,
the first positioning portion and the second positioning portion are latched to each other when the storage element is located
at the first position, and the first positioning portion and the third positioning portion are latched to each other when
the storage element is located at the second position.

US Pat. No. 9,390,764

STORAGE APPARATUS AND PRODUCTION METHOD THEREOF

PHISON ELECTRONICS CORP.,...

1. A storage apparatus, comprising:
a storage element, having a body, a first pad set, and a second pad set, wherein the first pad set and the second pad set
are exposed out of the body and located at opposite ends of the body; and

a fitting member, having a first terminal set and a second terminal set electrically connected to each other, and the storage
element being detachably assembled to the fitting member,

wherein the first terminal set and the first pad set are electrically connected to each other, the second terminal set is
located between the first pad set and the second pad set, and the second terminal set and the second pad set form a connecting
interface used to electrically connect the storage apparatus with an external apparatus,

wherein the fitting member is a U-shape structure, the fitting member comprises a connection part and a carrying part at opposite
sides of the U-shaped structure, the body is located between the connection part and the carrying part so that the storage
element is disposed in the U-shaped structure, and the first terminal set and the second terminal set are formed in the connection
part and connected with each other.

US Pat. No. 9,317,418

NON-VOLATILE MEMORY STORAGE APPARATUS, MEMORY CONTROLLER AND DATA STORING METHOD

PHISON ELECTRONICS CORP.,...

1. A data storing method for a non-volatile memory module, the data storing method comprising:
determining whether a suspend mode signal, a warm reset signal or a hot-reset signal is received by a memory controller from
a host system; and

writing data temporarily stored in a buffer memory into the non-volatile memory module by the memory controller after receiving
the suspend mode signal, the warm reset signal or the hot-reset signal from the host system,

wherein the non-volatile memory module includes a plurality of physical blocks and the physical block is grouped into at least
a data area and a spare area,

wherein the step of writing the data temporarily stored in the buffer memory into the non-volatile memory module by the memory
controller comprises:

getting a physical block from the spare area and writing the data temporarily stored in the buffer memory into the gotten
physical block by the memory controller.

US Pat. No. 9,298,610

DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has
a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming units,
the data writing method comprising:
selecting a physical erasing unit from the plurality of physical erasing units of the rewritable non-volatile memory module
as a first active physical erasing unit;

selecting another physical erasing unit from the plurality of physical erasing units of the rewritable non-volatile memory
module as a second active physical erasing unit;

grouping a plurality of logical units configured on the rewritable non-volatile memory module into a first area and at least
one second area;

receiving a write command indicating storing first data into a first logical unit among the logical units from a host system
and determining whether the first logical unit belongs to the first area or the second area;

if the first logical unit belongs to the first area, programming the first data into the first active physical erasing unit;
if the first logical unit belongs to the second area, programming the first data into the second active physical erasing unit;
if a write command indicating storing second data into a second logical unit among the logical units is received from the
host system and the second logical unit belongs to the second area, programming the second data into the second active physical
erasing unit; and

if a write command indicating storing third data into a third logical unit among the logical units is received from the host
system and the third logical unit belongs to the second area, programming the third data into the second active physical erasing
unit.

US Pat. No. 9,467,314

SIGNAL MODULATION METHOD, ADAPTIVE EQUALIZER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A signal modulation method for an adaptive equalizer, comprising:
receiving a first signal;
performing a first modulation on the first signal based on a first power mode to generate a second signal having a first eye-width;
performing a second modulation on the first signal based on a second power mode to generate the second signal having a second
eye-width, wherein a power consumption of performing the second modulation based on the second power mode is less than a power
consumption of performing the first modulation based on the first power mode;

determining whether the first eye-width and the second eye-width meet a first condition;
if the first eye-width and the second eye-width meets the first condition, performing a third modulation on the first signal
based on the first power mode to generate the second signal having a third eye-width; and

if the first eye-width and the second eye-width does not meet the first condition, performing the third modulation on the
first signal based on the second power mode to generate the second signal having the third eye-width.

US Pat. No. 9,465,584

METHOD FOR GENERATING RANDOM NUMBER, MEMORY STORAGE DEVICE AND CONTROL CIRCUIT

PHISON ELECTRONICS CORP.,...

1. A method for generating a random number for a rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module comprises a plurality of memory cells, and the method for generating the random number comprises:
storing data received from a host system into the memory cells;
reading at least one of the memory cells repeatedly according to a first read voltage to obtain a plurality of sensing currents;
and

generating at least one random number according to the sensing currents.

US Pat. No. 9,450,488

CONTROL CIRCUIT FOR MAINTAINING OUTPUT SIGNAL OF SWITCHING REGULATOR IN A SLEEP MODE AND METHOD FOR REGULATING ELECTRICAL SIGNAL

PHISON ELECTRONICS CORP.,...

1. A control circuit for a switching regulator, comprising:
the switching regulator, regulating an output electrical signal according to a clock signal, a reference voltage and a feedback
voltage;

a clock control unit, coupled to the switching regulator, wherein the clock control unit comprises:
an oscillator, providing an oscillation signal;
a pulse blanking modulator, coupled to the oscillator and configured to receive a sleep signal indicating to enter a sleep
mode of the switching regulator and generate a control signal that blanks at least a portion of the oscillation signal in
response to the sleep signal, wherein the clock control unit provides the control signal in order to maintain the output electrical
signal in the sleep mode of the switching regulator within a predetermined range; and

a logic operator, coupled to the oscillator and the pulse blanking modulator and configured to receive the oscillation signal
from the oscillator and the control signal from the pulse blanking modulator,

wherein the logic operator is further configured to generate the clock signal transmitted to the switching regulator according
to the oscillation signal and the control signal,

wherein a clock frequency of the oscillation signal is maintained at a first clock frequency in the sleep mode,
wherein a clock frequency of the clock signal is changed from the first clock frequency to a second clock frequency in response
to the control signal in the sleep mode,

wherein the first clock frequency is different from the second clock frequency.

US Pat. No. 9,312,011

DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data writing method for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory
module comprises a plurality of physical erasing units, the physical erasing units are at least grouped into a data area and
a spare area, and the data writing method comprises:
allocating a plurality of logical units, wherein at least one first logical unit of the logical units is mapped to at least
one first physical erasing unit of the physical erasing units in the data area, at least one second logical unit of the logical
units is mapped to at least one second physical erasing unit of the physical erasing units in the data area, the at least
one first physical erasing unit stores first data and is filled with the first data, and the at least one second physical
erasing unit stores second data and is not filled with the second data;

selecting at least one third physical erasing unit of the physical erasing units from the spare area and determining whether
a remaining space in the at least one second physical erasing unit is smaller than a threshold;

if the remaining space in the at least one second physical erasing unit is not smaller than the threshold, issuing a first
writing command sequence, wherein the first writing command sequence indicates to write the first data into the at least one
third physical erasing unit and indicates to write the second data into the at least one second physical erasing unit; and

if the remaining space in the at least one second physical erasing unit is smaller than the threshold, selecting at least
one fourth physical erasing unit of the physical erasing units from the spare area and issuing a second writing command sequence,
wherein the second writing command sequence indicates to write the first data into the at least one third physical erasing
unit and indicates to write the second data into the at least one second physical erasing unit and the at least one fourth
physical erasing unit.

US Pat. No. 9,311,045

ELASTIC BUFFER MODULE AND ELASTIC BUFFERING METHOD FOR TRANSMISSION INTERFACE

PHISON ELECTRONICS CORP.,...

1. An elastic buffer module, comprising:
a memory unit, disposed between a transmitting side and a receiving side, wherein a data sequence is written to the memory
unit and the data sequence is received from the transmitting side, stored in the memory unit and outputted by the memory unit
in a single read or write process;

a write control module, coupled to the memory unit, disposed at the transmitting side, and configured to remove at least a
part of auxiliary data from the data sequence, and writing the data sequence that has the auxiliary data removed into the
memory unit in the signal read or write process; and

a read control module, coupled to the memory unit and disposed at the receiving side, configured to read the data sequence
from the memory unit according to a First-In-First-Out rule, and add auxiliary data to the data sequence in the signal read
or write process.

US Pat. No. 9,213,629

BLOCK MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STOARGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A block management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
has a plurality of physical blocks, the block management method comprising:
logically grouping the physical blocks into at least a data area, a spare area and a replacement area, wherein the physical
blocks of the data area includes at least one bad physical block;

configuring a plurality of logical blocks for mapping to the physical blocks of the data area, wherein each of the logical
blocks independently maps to one of the physical blocks of the data area; and

respectively marking at least one logical block mapped to the at least one bad physical block as a bad logical address, wherein
a mapping between the at least one logical block and the at least one bad physical block is fixed and not be changed.

US Pat. No. 9,177,656

DATA WRITING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data writing method, for a rewritable non-volatile memory module which comprises a plurality of physical erasing units
each comprising a plurality of physical programming units, the data writing method comprising:
configuring a plurality of logical addresses, wherein the logical addresses constitute a plurality of logical programming
units and the logical programming units constitute a plurality of logical erasing units;

grouping the logical erasing units into a first region and a second region;
receiving a write command from a host system, wherein the write command instructs to write first data to at least one first
logical address of the logical addresses and the at least one first logical address belongs to a first logical erasing unit
of the logical erasing units;

determining whether the first logical erasing unit belongs to the first region or the second region;
executing a first writing procedure if the first logical erasing unit belongs to the first region, wherein the first writing
procedure comprises:

selecting a spare physical programming unit from the physical programming units; and
writing the first data to the spare physical programming unit, wherein the spare physical programming unit belongs to a first
physical erasing unit of the physical erasing units and the first physical erasing unit further stores data belonging to a
second logical erasing unit of the logical erasing units, and the second logical erasing unit is different from the first
logical erasing unit,

executing a second writing procedure if the first logical erasing unit belongs to the second region, wherein the second writing
procedure comprises:

selecting a second physical erasing unit from the physical erasing units; and
writing the first data to the second physical erasing unit, wherein all valid data in the second physical erasing unit belongs
to the first logical erasing unit.

US Pat. No. 9,507,702

METHOD OF PERFORMING WRITE ACCESS BY DISTRIBUTING CONTROL RIGHTS TO THREADS, MEMORY CONTROLLER AND FLASH MEMORY STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A program management method of a flash memory, adapted to a flash memory storage device comprising a flash memory controller
and a flash memory chip, wherein at least a first thread and a second thread are to be implemented within the flash memory
storage device, the method comprising:
defining a predetermined program unit by the flash memory controller;
receiving a first write command by the flash memory controller, wherein the first write command is corresponding to a first
program data, wherein a quantity of the first program data is bigger than a quantity of the predetermined program unit, wherein
the predetermined program unit includes at least one physical page;

distributing a control right of the flash memory chip to the first thread when the first write command is determined to be
executed by the first thread by the flash memory controller;

controlling, by the flash memory controller, the first thread to release the control right of the flash memory chip each time
in response to a completion of programming data into the predetermined program unit by the first thread;

determining, by the flash memory controller, whether the second thread requests the control right of the flash memory chip
in response to the releasing of the control right of the flash memory by the first thread; and

distributing the control right of the flash memory chip to the first thread if the second thread does not request the control
right of the flash memory chip by the flash memory controller.

US Pat. No. 9,318,155

CLOCK ADJUSTING CIRCUIT, MEMORY STORAGE DEVICE, AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A clock adjusting circuit, disposed on a die, wherein the die has a plurality of layers, the clock adjusting circuit comprising:
a detection circuit, configured to detect a signal characteristic difference between an input signal and an output signal
to generate a first signal;

a control voltage generating circuit, coupled to the detection circuit, and configured to generate a control voltage according
to the first signal;

a voltage-controlled oscillator (VCO), coupled to the control voltage generating circuit, and comprising a inductor and a
capacitor, wherein the VCO is configured to receive the control voltage and oscillate according to an impedance characteristic
of the inductor and the capacitor to generate the output signal, wherein the inductor is disposed on a pad layer among the
layers; and

a filter, coupled between the control voltage generating circuit and the VCO, wherein the filter comprises a filter capacitor,
the filter capacitor is disposed on a first layer among the layers, the first layer is different from the pad layer, and when
viewed from a direction perpendicular to the pad layer, the filter capacitor and the inductor at least partially overlap each
other.

US Pat. No. 9,213,597

MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF

PHISON ELECTRONICS CORP.,...

1. A method for programming data, adapted to a memory storage device coupled to a host system, wherein the memory storage
device comprises an error checking and correcting (ECC) circuit and a rewritable non-volatile memory chip, and the rewritable
non-volatile memory chip comprises a plurality of physical pages, wherein the rewritable non-volatile memory chip comprises
a data area, a system area and a spare area, wherein a physical block storing user data is regarded as logically belonging
to the data area, wherein a physical block logically belonging to the spare area is used for substituting the physical block
logically belonging to the data area, wherein a physical block logically belonging to the system area is used for storing
system data for managing the physical block logically belonging to the data area or the spare area, the method for programming
data comprising:
determining whether write data to be written into the rewritable non-volatile memory chip belongs to a specific type;
generating at least one first type ECC code with a first length by the ECC circuit according to the write data when the write
data belongs to the specific type; and

generating at least one second type ECC code with a second length by the ECC circuit according to the write data when the
write data does not belong to the specific type, wherein the first length is longer than the second length,

wherein the step of determining whether the write data belongs to the specific type comprises: determining the write data
belongs to the specific type if the write data is not from the host system, the write data is data other than user data, or
the write data is to be written into the system area of the rewritable non-volatile memory chip.

US Pat. No. 9,081,662

MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF

PHISON ELECTRONICS CORP.,...

1. A method for programming data, adapted to a memory storage device comprising a buffer memory and a rewritable non-volatile
memory chip, wherein the rewritable non-volatile memory chip comprises a buffer unit and a plurality of physical blocks, the
method for programming data comprising:
temporarily storing first data received from a host system into the buffer memory;
generating a writing complete message for replying to the host system in response to the first data stored in the buffer memory
is transmitted to the buffer unit by using a first data transmitting command;

programming the first data in the buffer unit to a first physical block of the physical blocks;
determining whether the first data in the buffer unit is failed to be programmed to the first physical block;
if a data program failure is detected, programming the first data maintained in the buffer unit to a second physical block
of the physical blocks by using a second data transmitting command, wherein the first data transmitting command is different
to the second data transmitting command, and the second data transmitting command does not clear the first data in the buffer
unit;

changing the rewritable non-volatile memory chip to be in a busy state in response to that the first data in the buffer memory
is transmitted to the buffer unit;

temporarily storing a second data received from the host system to the buffer memory while the rewritable non-volatile memory
chip is in the busy state, and waiting for the rewritable non-volatile memory chip to leave the busy state; and

transmitting the second data in the buffer memory to the buffer unit by using the first data transmitting command in response
to the rewritable non-volatile memory chip leaving the busy state.

US Pat. No. 9,454,182

FLASH DRIVE

PHISON ELECTRONICS CORP.,...

1. A flash drive, suitable for being electrically connected to an electronic device, comprising:
a storage module, being a plate and having a main surface, a first connector and a second connector, wherein the first connector
standing on the main surface along an axis is electrically connected to the storage module and is configured to be electrically
connected to the electronic device along the axis, and the axis is not parallel to the main surface, wherein the second connector
is disposed on the storage module and electrically connected to the storage module; and

a first housing, having a first opening, wherein the first housing comprises a first member and a second member which are
assembled together, the storage module is located between the first member and the second member, the first member has the
first opening, the second connector is formed by a plurality of terminals, and an orthogonal projection of the second connector
on the second member is located in the external of an orthogonal projection of the first member on the second member, such
that the terminals are exposed from the first housing.

US Pat. No. 9,473,473

DATA ACCESSING METHOD AND SYSTEM AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data accessing method for a memory storage apparatus having a rewritable non-volatile memory module, the rewritable non-volatile
memory module comprises a plurality of physical erasing units, and the physical erasing units are logically grouped into a
data area, a spare area, a system area, and a replacement area, wherein a plurality of logical addresses are mapped to the
physical erasing units of the data area, and grouping relations of the physical erasing units grouped to the data area, the
spare area, the system area, and the replacement area change dynamically, the data accessing method comprising:
performing a near field communication (NFC) between the memory storage apparatus and a first electronic apparatus;
receiving a first password from the first electronic apparatus by the memory storage apparatus through the NFC;
recording the first password in a memory unit of the memory storage apparatus;
within a predetermined time after the first password is received from the first electronic apparatus by the memory unit of
the memory storage apparatus through the NFC, connecting a connection interface unit of the memory storage apparatus to a
connection port of a second electronic apparatus,

within the predetermined time after the first password is received from the first electronic apparatus by the memory unit
of the memory storage apparatus through the NFC, if the connection interface unit of the memory storage apparatus is not connected
to the connection port of the second electronic apparatus, deleting the first password recorded in the memory unit; and

if the first password recorded in the memory unit is identical to a second password stored in the memory storage apparatus,
allowing the second electronic apparatus to access the memory storage apparatus by the memory storage apparatus.

US Pat. No. 9,418,731

MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

9. A memory storage device, comprising:
a connection interface unit, configured to couple to a host system;
a rewritable non-volatile memory module comprising a plurality of memory cells; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to obtain a first threshold voltage distribution of the memory cells,
wherein the memory control circuit unit is further configured to group the first threshold voltage distribution of the memory
cells to a plurality of first threshold voltage groups,

wherein the memory control circuit unit is further configured to obtain a second threshold voltage distribution of the memory
cells,

wherein the memory control circuit unit is further configured to group the second threshold voltage distribution of the memory
cells to a plurality of second threshold voltage groups, wherein a terminal threshold voltage of the first threshold voltage
groups is lower than a terminal threshold voltage of the second threshold voltage groups,

wherein the memory control circuit unit is further configured to allocate a first memory cell among the memory cells to a
first virtual block if a first threshold voltage pair of the first memory cell belongs to a first group of the first threshold
voltage groups and a first group of the second threshold voltage groups, such that the first memory cell is operated under
an M-level cell mode,

wherein the memory control circuit unit is further configured to allocate a second memory cell among the memory cells to a
second virtual block if a second threshold voltage pair of the second memory cell belongs to a second group of the first threshold
voltage groups and a second group of the second threshold voltage groups, such that the second memory cell is operated under
an N-level cell mode,

wherein a terminal threshold voltage of the second group of the first threshold voltage groups is lower than a terminal threshold
voltage of the first group of the first threshold voltage groups,

wherein a terminal threshold voltage of the second group of the second threshold voltage groups is higher than a terminal
threshold voltage of the first group of the second threshold voltage groups,

wherein M and N are both positive integers and larger than 1, and N is larger than M.

US Pat. No. 9,361,024

MEMORY CELL PROGRAMMING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory cell programming method, for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory
module has a plurality of physical erasing units, and each of the physical erasing units has a plurality of physical programming
units, the memory cell programming method comprising:
applying a first programming parameter set to write a first kind of data to one of the physical programming units; and
applying a second programming parameter set to write a second kind of data to one of the physical programming units,
wherein at least part of parameters of the first programming parameter set differ from the second programming parameter set,
and the number of bits of data of a memory cell of the one of the physical programming units written with the first kind of
data by applying the first programming parameter set is the same as the number of bits of data of a memory cell of the one
of the physical programming units written with the second kind of data by applying the second programming parameter set.

US Pat. No. 9,460,004

MEMORY ERASING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory erasing method for a rewritable non-volatile memory module of a memory storage apparatus, wherein the rewritable
non-volatile memory module has a plurality of physical blocks, the memory erasing method comprising:
logically grouping the physical blocks into at least a data area and a spare area, wherein each of the physical blocks of
the spare area is not mapped to a logical address; and

during every power on of the memory storage apparatus, configuring an erase mark corresponding to each of the physical blocks
of the spare area and initially setting each of the erase marks to an unerased state, wherein after initially setting each
of the erase marks to the unerased state, the memory storage apparatus is entered to a standby state to receive and process
commands from the host system.

US Pat. No. 9,257,777

FLASH DRIVE

PHISON ELECTRONICS CORP.,...

1. A flash drive, comprising:
a storage module, having a carrier, a first connecting interface and a second connecting interface, wherein the carrier has
a groove, the first connecting interface and the second connecting interface are disposed backward from each other at opposite
sides of the carrier along a first axis; and

a rotating member, having a driving portion connected to the groove and rotating on a rotation axis, such that the driving
portion is slid in the groove, and the carrier is moved along the first axis, wherein a traveling path of the first connecting
interface along the first axis is different from a traveling path of the second connecting interface along the first axis.

US Pat. No. 9,430,325

METHOD FOR PROGRAMMING DATA, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A method for programming data, for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module comprises a plurality of physical erasing units, and each of the physical erasing units comprises a plurality
of physical programming units, the method comprising:
determining a bit error rate (BER) assessing value of a first physical erasing unit among the physical erasing units according
to at least one of erasing count information, writing count information, reading count information, data storage time information
and temperature information of the first physical erasing unit;

receiving a writing command which instructs to write data into at least one of a plurality of logical units, wherein the at
least one of the logical units is mapped to a first physical programming unit among the physical programming units, and the
first physical programming unit belongs to the first physical erasing unit;

determining whether the first physical erasing unit belongs to a first type physical erasing unit or a second type physical
erasing unit according to the determined BER assessing value;

if the first physical erasing unit belongs to the first type physical erasing unit, programming the data and a parity code
corresponding to the data into the first physical programming unit according to a first code rate; and

if the first physical erasing unit belongs to the second type physical erasing unit, programming the data and the parity code
corresponding to the data into the first physical programming unit according to a second code rate, wherein the first code
rate is higher than the second code rate, the step of programming the data and the parity code according to the second code
rate comprises:

determining whether a data length of the data is over a data length of N basic management units, wherein N is a positive integer,
and a data length of N+1 basic management units is equal to a capacity size of the first physical programming unit;

if the data length of the data is not over the data length of the N basic management units, programming the data and the parity
code corresponding to the data into the first physical programming unit according to the second code rate; and

if the data length of the data is over the data length of the N basic management units, programming a first portion of the
data and a first portion of the parity code into the first physical programming unit and programming a second portion of the
data and a second portion of the parity code into a second physical programming unit among the physical programming units
according to the second code rate.

US Pat. No. 9,274,706

DATA MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

23. A memory storage apparatus, comprising:
a connection interface unit configured to couple to a host system;
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical
erasing units, and each of the physical erasing units comprises a plurality of physical programming units; and

a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module, wherein
the memory control circuit unit is configured to configure a plurality of logical units for mapping to at least a part of
the physical erasing units,

wherein the memory control circuit unit is further configured to divide each of the physical programming units into a data
bits area and a spare bits area,

wherein the memory control circuit unit is configured to receive first data, wherein the first data is compressible data,
wherein the memory control circuit unit is further configured to compress the first data into first compressed data, and the
memory control circuit unit generates first data compression information corresponding to the first data, wherein information
indicating whether the first data is compressed and a compression rate corresponding to the first data are integrated into
the first data compression information by the memory control circuit unit,

wherein the memory control circuit unit is configured to divide a first data bits area of a first physical programming unit
among the physical programming units into a first user data area and a first management information area,

wherein the memory control circuit unit is further configured to program the first compressed data into the first user data
area, program first data management information corresponding to the first data into the first management information area,
and program the first data compression information into the first spare bits area of the first physical programming unit.

US Pat. No. 9,389,998

MEMORY FORMATTING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory formatting method for a memory storage apparatus, wherein the memory storage apparatus has a rewritable non-volatile
memory module, and the rewritable non-volatile memory module has a plurality of physical blocks, the memory formatting method
comprising:
configuring a plurality of logical block addresses for mapping to a portion of the physical blocks;
generating a first file system data and a second file system data according to a size of the logical block addresses at initial
partition of the logical block addresses;

storing the first file system data into at least one first physical block among the physical blocks, wherein the at least
one first physical block is mapped to at least one first logical block address among the logical block addresses, wherein
the first file system data is updated if data is written to the logical block addresses;

selecting at least one second physical block among the physical blocks;
storing the second file system data into the at least one second physical block;
determining whether a format command is received from a host system; and
when the format command is received from the host system, re-mapping the at least one first logical block address to the at
least one second physical block,

wherein before the step of re-mapping the at least one first logical block address to the at least one second physical block,
the second file system data is not updated if data is written to the logical block addresses, and

wherein after the step of remapping the at least one first logical block address to the at least one second physical block,
the second file system data is updated if data is written to the logical block addresses.

US Pat. No. 9,236,148

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
having a plurality of physical erasing units, the memory management method comprising:
recording an erasing count of each of the physical erasing units;
grouping the physical erasing units at least into a spare area and a data area;
determining whether a use count of the rewritable non-volatile memory module is greater than a use count threshold;
if the use count of the rewritable non-volatile memory module is not greater than the use count threshold, sorting each of
the physical erasing units in the spare area in an ascending manner according to the erasing count of each of the physical
erasing units in the spare area to form a plurality of sorted physical erasing units;

if the use count of the rewritable non-volatile memory module is greater than the use count threshold, sorting each of the
physical erasing units in the spare area in the ascending manner according to the number of maximum bit errors of the physical
erasing units in the spare area to form the sorted physical erasing units; and

selecting a first physical erasing unit from the spare area to write data according to the sorted physical erasing units,
wherein the first physical erasing unit is a foremost physical erasing unit of the sorted physical erasing units.

US Pat. No. 9,367,390

MEMORY CONTROLLING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A memory controlling method for a rewritable non-volatile memory module, comprising:
receiving a first command from a host system;
if the first command is a read command, providing a first clock signal to the rewritable non-volatile memory module, and reading
a first data in the rewritable non-volatile memory module operated in a frequency of the first clock signal according to the
first clock signal; and

if the first command is a write command, providing a second clock signal to the rewritable non-volatile memory module, and
writing a second data into the rewritable non-volatile memory module operated at a frequency of the second clock signal according
to the second clock signal, wherein the frequency of the second clock signal is different from the frequency of the first
clock signal.

US Pat. No. 9,281,631

CONNECTOR AND STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A connector, suitable for a storage device having a storage module, the connector comprising:
a body;
a plurality of terminals, disposed in the body, wherein a first end of each terminal protrudes from the body and is electrically
connected to the storage module; and

a first housing, covering the body, wherein the first housing has a first indentation and a shielding portion, the first end
of each terminal is located at the first indentation, and the shielding portion shields the first indentation, and the first
end of each terminal is located between the shielding portion and the storage module.

US Pat. No. 9,223,688

DATA STORING METHOD AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data storing method for a memory storage device having a rewritable non-volatile memory module, the rewritable non-volatile
memory module has a plurality of physical erase units, each of the physical erase units has a plurality of physical program
units, and a plurality of logical addresses is configured to map to a part of the physical erase units, the data storing method
comprising:
selecting a first logical address among the logical addresses;
selecting a first physical erase unit among the physical erase units;
moving valid data belonging to the first logical address from a plurality of physical erase units mapped to the first logical
address into the first physical erase unit;

determining whether the first physical erase unit contains a dancing bit; and
when the first physical erase unit contains the dancing bit, executing an erasing operation on the first physical erase unit.

US Pat. No. 9,081,659

CONTROLLING METHOD FOR CONNECTOR, CONNECTOR AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A controlling method for connector, wherein the connector comprises a squelch detector, the controlling method comprising:
receiving a first signal stream under a condition that the squelch detector is turned-off;
determining whether the first signal stream comprises a burst signal under a first operating frequency;
if the first signal stream comprises the burst signal, turning on the squelch detector and determining whether a second signal
stream is a waking signal by the squelch detector under a second operating frequency, wherein the second signal stream is
received after receiving the first signal stream and the second operating frequency is greater than the first operating frequency;
and

if the second signal stream is the waking signal, changing an operating state of the connector to an active state.

US Pat. No. 9,122,421

CONNECTING PART OF STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A connecting part of a storage device, comprising:
a body having a first end and a second end opposite to each other;
a plurality of connecting terminals disposed at the first end and the second end respectively; and
a grounding member assembled to the body, at least a part of the grounding member extending from one of the first end and
the second end to another one of the first end and the second end, and the connecting part of the storage device being grounded
by contacting the grounding member to a connector of an external device when the connecting part of the storage device is
connected to the connector of the external device,

wherein the grounding member has a socketing portion and at least one extending portion, the socketing portion is socketed
at the first end or the second end of the body to cover the connecting terminals disposed at the first end or the second end,
the socketing portion is extended from the socketing portion towards the second end or the first end of the body, and the
grounding member is grounded by contacting the socketing portion to the connector of the external device,

wherein the grounding member further comprises a protruding portion disposed on the extending portion, and the protruding
portion leans against a second grounding interface of the storage device such that the storage device and the grounding member
are grounded with each other.

US Pat. No. 9,083,134

UNIVERSAL SERIES BUS CONNECTOR AND MANUFACTURING METHOD THEREOF

PHISON ELECTRONICS CORP.,...

1. A universal series bus connector, wherein the universal series bus connector has a first end and a second end, comprising:
a base;
a first terminal set, at least comprising a pair of first differential signal terminals and a pair of second differential
signal terminals respectively disposed on the base, wherein, from the first end to the second end, terminals of the pair of
first differential signal terminals are adjacent to each other and terminals of the pair of second differential signal terminals
are adjacent to each other; and

a second terminal set disposed on the base, wherein two of terminals of the second terminal set are located respectively at
two opposite sides of the pair of first differential signal terminals, and another two of the terminals of the second terminal
set are located respectively at two opposite sides of the pair of second differential signal terminals.

US Pat. No. 9,349,473

DATA SAMPLING CIRCUIT MODULE, DATA SAMPLING METHOD AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data sampling circuit module, comprising:
a sensing circuit, configured to receive a differential signal and generate a sensing voltage pair according to the differential
signal, wherein the sensing voltage pair comprises a first sensing voltage and a second sensing voltage, a first voltage value
of the first sensing voltage is related to a first differential signal of the differential signal, and a second voltage value
of the second sensing voltage is related to a second differential signal of the differential signal, wherein a first phase
of the first differential signal and a second phase of the second differential signal are opposite; and

a sampling circuit, coupled to the sensing circuit, wherein the sampling circuit is configured to receive the sensing voltage
pair and output a sampling data stream according to a clock of the differential signal and a voltage relative relationship
of the sensing voltage pair.

US Pat. No. 9,235,534

DATA PROTECTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data protecting method, for protecting a sub-directory and at least one pre-stored file in the sub-directory stored into
a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical
blocks and a plurality of logical block addresses are configured to map to a portion of the physical blocks, and the logical
block addresses are formatted to be a partition having a file allocation table area, a root directory area and a file area,
the data protecting method comprises:
receiving a write command from a host system, wherein the write command indicates a write address;
determining whether the write address is an address storing a file description block of the sub-directory;
determining whether a property data in data streams corresponding to the write command is the same as a corresponding content
recorded in the file description block of the sub-directory when the write address is the address storing the file description
block of the sub-directory; and

transmitting a write failure signal to the host system when the property data in the data streams corresponding to the write
command is not the same as the corresponding content recorded in the file description block of the sub-directory,

wherein the property data comprises at least one of a name of the sub-directory, a read-only property of the sub-directory,
a hidden property of the sub-directory, a system file property of the sub-directory and a directory property of the sub-directory.

US Pat. No. 9,268,634

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of memory cells, the decoding method comprising:
reading a plurality of first memory cells of the memory cells according to at least one first reading voltage to obtain at
least one first verifying bit of each of the first memory cells;

executing a first decoding procedure comprising a probability decoding algorithm according to the at least one first verifying
bits of the first memory cells to obtain a plurality of first decoded bits, and determining whether a decoding is successful
by using the first decoded bits; and

if the decoding is failed, reading the first memory cells according to at least one second reading voltage to obtain at least
one second verifying bit of each of the first memory cells, and executing the first decoding procedure according to the at
least one second verifying bits of the first memory cells to obtain a plurality of second decoded bits,

wherein the at least one second reading voltage is different from the at least one first reading voltage, and the number of
the at least one second reading voltage is equal to the number of the at least one first reading voltage,

wherein the first decoding procedure is an iterative decoding of a hard bit mode.

US Pat. No. 9,123,418

NAND FLASH MEMORY UNIT AND NAND FLASH MEMORY ARRAY

PHISON ELECTRONICS CORP.,...

5. A NAND flash memory unit, comprising:
a string of memory cells connected in series;
two source/drain (S/D) regions coupled to two terminals of the string of memory cells;
at least one select transistor coupled between a terminal of the string and one of the two S/D regions, for selecting the
string of memory cells; and

at least one erase transistor coupled between the at least one select transistor and the one of the two S/D regions,
wherein when the NAND flash memory unit is being programmed or read, a positive voltage is applied to all the erase gates
in a selected block.

US Pat. No. 9,098,395

LOGICAL BLOCK MANAGEMENT METHOD FOR A FLASH MEMORY AND CONTROL CIRCUIT STORAGE SYSTEM USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A logical block management method, for managing a plurality of logical blocks of a flash memory storage device, wherein
the plurality of logical blocks are mapped to a plurality of physical blocks in the flash memory storage device, the logical
block management method comprising:
providing a flash memory controller;
grouping the logical blocks into a plurality of logical zones, wherein the logical zones comprising a first logical zone,
a second logical zone and a third logical zone;

recording mapping relations between the logical blocks and the logical zones, wherein each of the logical blocks maps to one
of the logical zones;

counting a use count value for each of the logical blocks, wherein the use count value for each of the logical blocks is the
number of times the corresponding logical block has been written to, wherein when a host system executes a write command to
one of the logical blocks, the use count value of the corresponding logical block is increased, wherein the use count values
of the logical blocks in the first logical zone is greater than the use count values of the logical blocks in the second logical
zone, and the use count values of the logical blocks in the second logical zone is greater than the use count values of the
logical blocks in the third logical zone;

adjusting the mapping relations between the logical blocks and the logical zones by using the flash memory controller according
to the use count values, wherein the mapping relations between the logical blocks and the logical zones is adjusted by remapping
one of the logical blocks mapped to the third logical zone among the logical zones to the second logical zone among the logical
zones and remapping another logical block mapped to the second logical zone to the third logical zone in response to remapping
the one of the logical blocks mapped to the third logical zone to the second logical zone, wherein the count value of the
one of the logical blocks mapped to the third logical zone is greater than the count values of the logical blocks mapped to
the first logical zone and the second logical zone; and

adjusting the use count values by using the flash memory controller after the step of adjusting the mapping relations between
the logical blocks and the logical zone, wherein the use count values are divided by a predetermined value,

wherein, when the host system is to access a first logical block among the logical blocks, the memory management unit loads
a first logical block-physical block mapping table from a flash memory chip according to the first logical zone that the first
logical block to be accessed belongs to, and performs a data accessing according to the first logical block- physical block
mapping table,

wherein, after the first logical zone is accessed, when a second logical block mapped to the second logical zone among the
logical zones is to be accessed, the memory management unit stores the first logical block-physical block mapping table back
to the flash memory chip, and loads a second logical block-physical block mapping table according to the second logical zone.

US Pat. No. 9,812,194

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method, for a rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method
comprising:
obtaining usage state information of a plurality of first memory cells among the memory cells;
reading a plurality of second memory cells among the memory cells by using a first read voltage level to obtain at least one
first bit and reading the second memory cells by using a second read voltage level to obtain at least one second bit according
to the usage state information, wherein the at least one first bit corresponds to a storage state of a first part of memory
cells among the second memory cells, the at least one second bit corresponds to a storage state of a second part of memory
cells among the second memory cells, and the first read voltage level is different from the second read voltage level; and

decoding a plurality of third bits comprising the at least one first bit and the at least one second bit.

US Pat. No. 9,507,658

DATA READING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data reading method for a rewritable non-volatile memory module, and the data reading method comprising:
setting a multi trigger queue;
receiving a first read command from a host system;
setting a plurality of first read events in the multi trigger queue according to the first read command, wherein the first
read events comprise one general read event and at least one cache read event, wherein data to be read corresponding to the
general read event and data to be read corresponding to the at least one cache read event belong to continuous data, the data
to be read corresponding to the general read event is requested by the first read command, and the data to be read corresponding
to the at least one cache read event is not requested by the first read command;

sending at least one first read command sequence according to at least one of the first read events and receiving first data
from the rewritable non-volatile memory module in response to the at least one first read command sequence;

executing a decoding for the first data; and
if the decoding for the first data fails, resetting the multi trigger queue, and sending at least one second read command
sequence according to at least one second read event in the reset multi trigger queue, wherein the at least one second read
event comprises at least one first cache read event in the at least one cache read event.

US Pat. No. 9,059,789

SIGNAL PROCESSING METHOD, CONNECTOR, AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A signal processing method for a connector, wherein the connector does not comprise a crystal oscillator, the signal processing
method comprising:
receiving a first signal stream from a host system;
tracking a transmission frequency of the first signal stream, and obtaining a frequency shift quantity of the first signal
stream relative to the transmission frequency;

determining whether a spread spectrum operation is performed on the first signal stream according to the frequency shift quantity
to generate a determination result; and

generating a second signal stream according to the determination result and the transmission frequency,
wherein the step of tracking the transmission frequency of the first signal stream comprises:
detecting an average frequency of the first signal stream,
determining whether the average frequency is within a variation range during a first time interval; and
setting the average frequency to be the transmission frequency if the average frequency is within the variation range during
the first time interval.

US Pat. No. 9,947,417

MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A memory management method for a rewritable non-volatile memory module comprising a plurality of memory cells, the method comprising:programming data to the memory cells;
determining whether a storage state of the data conforms with a first condition or a second condition based on a default bias range and a threshold voltage distribution of the memory cells storing the data, wherein the first condition corresponds to that a programming operation for the memory cells is finished, and the second condition corresponds to that the programming operation for the memory cells is terminated before the programming operation is finished;
performing a first operation if the storage state of the data conforms with the first condition; and
performing a second operation if the storage state of the data conforms with the second condition,
wherein the first operation is different from the second operation.

US Pat. No. 9,563,498

METHOD FOR PREVENTING READ-DISTURB ERRORS, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A method of preventing read-disturb errors for a rewritable non-volatile memory module comprising a plurality of physical
erasing units, the method comprising:
counting up an operation numerical value to update the operation numerical value from a first value to a second value when
receiving an operation command from a host system, wherein a first physical erasing unit among the physical erasing units
is selected to execute the operation command, and the second value is greater than the first value;

selecting a second physical erasing unit storing data among the physical erasing units other than the first physical erasing
unit and reading the data from the second physical erasing unit when the second value the operation numerical value is not
smaller than an operation numerical threshold, wherein a value of the operation numerical threshold is a positive integer
greater than 0, and the first value is smaller than the operation numerical threshold;

determining whether a data error occurs at the second physical erasing unit according to the data read from the second physical
erasing unit; and

selecting a third physical erasing unit among the physical erasing units, correcting the data read from the second physical
erasing unit to generate corrected data and writing the corrected data into the third physical erasing unit if the data error
occurs at the second physical erasing unit.

US Pat. No. 9,122,583

MEMORY CONTROLLER AND MEMORY STORAGE DEVICE AND DATA WRITING METHOD

PHISON ELECTRONICS CORP.,...

1. A data writing method for a memory storage device having a rewritable non-volatile memory module, wherein the rewritable
non-volatile memory module has a plurality of physical unit unions, each of the plurality of physical unit unions has a plurality
of physical unit sets, each of the plurality of physical unit sets at least has an upper physical unit and a lower physical
unit, and a speed of writing data into the plurality of lower physical units is faster than a speed of writing data into the
plurality of upper physical units, the data writing method comprising:
partitioning the plurality of physical unit unions into at least a storage area, wherein the storage area has a data area
and a spare area;

configuring a plurality of logical units for mapping the plurality of physical unit unions of the data area, wherein each
of the logical units has a plurality of logical pages;

receiving first update data from a host system, wherein the first update data is to be written into at least one logical page
of a first logical unit among the plurality of logical units;

getting multiple physical unit unions from the physical unit unions of the spare area and independently serving the gotten
physical unit unions as a plurality of buffer physical unit unions corresponding to the first logical unit, wherein the plurality
of buffer physical unit unions are assigned to only write data belonging to the first logical unit and not being shared;

using only a portion of each of the plurality of buffer physical unit unions corresponding to the first logical unit to write
the first update data, wherein a writing speed corresponding to the written portion is faster than a writing speed corresponding
to another portion of each of the plurality of buffer physical unit unions; and

performing a copy procedure to move the first update data from the plurality of buffer physical unit unions corresponding
to the first logical unit to the storage area.

US Pat. No. 9,436,547

DATA STORING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data storing method for a rewritable non-volatile memory module comprising a plurality of physical erasing units, wherein
each of the physical erasing units comprising a plurality of physical programming units and each of the physical programming
units comprises a data bit area and a redundancy bit area, the data storing method comprising:
generating a parity according to first data;
programming the first data into a first physical programming unit among the physical programming units; and
programming the parity into at least one second physical programming unit among the physical programming units, wherein the
at least one second physical programming unit is arranged after the first physical programming unit,

wherein the step of programming the first data into the first physical programming unit among the physical programming units
comprises: programming at least one mark into the redundancy bit area of the first physical programming unit, wherein the
at least one mark indicates that the parity is programmed into the at least one second physical programming unit.

US Pat. No. 9,223,648

MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROCESSING DATA THEREOF

PHISON ELECTRONICS CORP.,...

1. A method for processing data for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
has a plurality of physical programming units, and each of the physical programming units comprises a data bit area and an
error-correction code bit area, the method comprising:
receiving a first data stream;
performing an error-correction encoding procedure on the first data stream to generate an original error checking and correcting
(ECC) code corresponding to the first data stream, wherein the original ECC code is utilized for error-correction of data
corresponding to the first data stream;

rearranging the original ECC code into a second ECC code according to a second rearrangement rule, wherein the original ECC
code is different from the second ECC code, a bit number of the original ECC code is equal to the bit number of the second
ECC code; and

respectively writing the first data stream and the second ECC code into one of the data bit areas and one of the error-correction
code bit areas in the physical programming units.

US Pat. No. 9,176,865

DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of physical erasing units, each of the physical erasing units comprises a plurality of physical programing units,
and the physical erasing units are grouped into at least a data area, the data writing method comprising:
configuring a plurality of logical addresses to map to the physical erasing units in the data area; grouping at least one
physical erasing unit among the physical erasing units besides the physical erasing units in the data area into a first buffer
area;

and grouping at least one physical erasing unit among the physical erasing units besides the physical erasing units in the
data area into a second buffer area, wherein the at least one physical erasing unit of the first buffer area is different
from the at least one physical erasing unit of the second buffer area;

receiving a first write command, wherein the first write command instructs to write a first data to a first logical address
among the logical addresses;

determining whether a quantity of the first data is smaller than a predetermined value;
if the quantity of the first data is smaller than the predetermined value, writing the first data into the at least one physical
erasing unit of the first buffer area or the at least one physical erasing unit of the second buffer area; and if the first
data is written into the at least one second physical erasing unit of the second buffer area, obtaining at least one second
logical address mapped to at least one first physical programing unit in the at least one first physical erasing unit of the
first buffer area, and copying merging valid data belonging to the at least one second logical address into a third physical
erasing unit among the physical erasing units, wherein the number of the at least one second logical address is smaller than
a merging threshold number and the third physical erasing unit is different from the at least one physical erasing unit of
the first buffer area and the at least one physical erasing unit of the second buffer area.

US Pat. No. 10,116,335

DATA PROCESSING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data processing method for encoding data stored in a rewritable non-volatile memory module, and the data processing method comprising:receiving first write data;
performing, by a first stage encoding circuit, a first stage encoding operation of a low-density parity-check (LDPC) code on the first write data so as to generate first transition data;
performing, by a second stage encoding circuit, a second stage encoding operation of the LDPC code on the first transition data so as to generate a first error correcting code (ECC), wherein the first ECC and the first write data is stored into the rewritable non-volatile memory module;
receiving second write data;
synchronously performing, by the first stage encoding circuit, the first stage encoding operation of the LDPC code on the second write data during a time period when the second stage encoding operation of the LDPC code on the first transition data is performed by the second stage encoding circuit; and
controlling a transmission path between the first stage encoding circuit and the second stage encoding circuit by a multiplexer,
wherein the first stage encoding operation is an encoding operation related to a first part of a parity check matrix, and the second stage encoding operation is an encoding operation related to a second part of the parity check matrix.

US Pat. No. 9,424,177

CLOCK SWITCHING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A clock switching method for a memory storage apparatus, wherein the memory storage apparatus includes a memory controller
and a rewritable non-volatile memory module, the memory controller and the rewritable non-volatile memory module are operated
based on a clock, the clock switching method comprising:
setting a value of the clock as a first operation frequency when an operation mode of the memory storage apparatus is switched
to a first state;

determining whether a first time of accessing continuously the rewritable non-volatile memory module is larger than a first
setting value while the operation mode of the memory storage apparatus is in the first state;

re-setting the value of the clock as a second operation frequency to switch the operation mode of the memory storage apparatus
to a second state if the first time is larger than the first setting value;

re-setting the value of the clock as the first operation frequency to switch the operation mode of the memory storage apparatus
to a third state from the second state;

determining whether a second time of accessing continuously the rewritable non-volatile memory module is larger than a third
setting value while the operation mode of the memory storage apparatus is in the third state; and

re-setting the value of the clock as the second operation frequency to switch the operation mode of the memory storage apparatus
to the second state if the second continuous accessing time is larger than the third setting value,

wherein the first operation frequency is larger than the second operation frequency.

US Pat. No. 9,257,157

MEMORY STORAGE DEVICE, MEMORY CONTROLLER, AND TEMPERATURE MANAGEMENT METHOD

PHISON ELECTRONICS CORP.,...

1. A temperature management method suitable for a memory storage device having a rewritable non-volatile memory module and
a memory controller used for controlling the rewritable non-volatile memory module, wherein the memory controller has a buffer
memory comprising a DRAM, and the rewritable non-volatile memory module comprises a plurality of rewritable non-volatile memory
dies, the temperature management method comprising:
detecting and determining whether a hot-spot temperature of the rewritable non-volatile memory module is higher than a predetermined
temperature; and

when affirmative, making the memory controller execute a cooling process, so as to reduce the hot-spot temperature of the
rewritable non-volatile memory module,

wherein the cooling process comprises at least one of:
lowering a total number of the rewritable non-volatile memory dies being simultaneously accessed, wherein at least one of
the rewritable non-volatile memory dies being accessed remains being accessed after the total number of the rewritable non-volatile
memory dies being simultaneously accessed is lowered; and

lowering a total number of the rewritable non-volatile memory dies that are simultaneously busy, wherein at least one of the
rewritable non-volatile memory dies that are busy remains busy after the total number of the rewritable non-volatile memory
dies that are simultaneously busy is lowered.

US Pat. No. 9,208,021

DATA WRITING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLER

PHISON ELECTRONICS CORP.,...

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
at least one memory chip, each of the at least one memory chip comprises a plurality of physical erasing units, each of the
physical erasing units comprises a plurality of physical programming units, and the physical programming units of each of
the physical erasing units comprise a plurality of fast physical programming units and a plurality of slow physical programming
units, wherein a write speed of the fast physical programming units is faster than a write speed of the slow physical programming
units, the data writing method comprising:
writing a first data only into at least one of the fast physical programming units;
generating a first error correction code according to the first data, wherein the first error correction code is configured
for correcting a part of bits in a single one of the fast physical programming units into which at least a part of the first
data is written;

generating a second error correction code according to the first data, wherein the second error correction code is configured
for correcting the fast physical programming unit into which at least a part of the first data is written, and a number of
bits correctable to the second error correction code is greater than a number of bits correctable to the first error correction
code;

writing the first error correction code and the second error correction code into at least one of the physical erasing units;
writing a second data only into at least one of the slow physical programming units;
generating a third error correction code according to the second data, wherein the third error correction code is configured
for correcting a part of bits in a single one of the slow physical programming units into which at least a part of the second
data is written;

generating a fourth error correction code according to the second data, wherein the fourth error correction code is configured
for correcting at least one of the slow physical programming units into which the second data is written, and a number of
bits correctable to the fourth error correction code is greater than a number of bits correctable to the third error correction
code; and

writing the third error correction code and the fourth error correction code into at least one of the physical erasing units.

US Pat. No. 9,192,063

FLASH DRIVE AND OPERATING METHOD THEREOF

PHISON ELECTRONICS CORP.,...

1. A flash drive, comprising:
a storage element, having a first connector and a second connector;
a housing, movably covering a part of the storage element; and
an integrating member, pivoted to the storage element and adapted to move relatively to the housing in a first path or a second
path, wherein when the integrating member moves relatively to the housing along the first path, the first connector is accordingly
exposed from or hidden in the housing, and when the integrating member moves relatively to the housing along the second path
and drives the storage element to move relatively to the integrating member, the second connector is accordingly exposed from
or hidden in the integrating member.

US Pat. No. 9,122,611

METHOD FOR GIVING READ COMMANDS AND READING DATA, AND CONTROLLER AND STORAGE SYSTEM USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A method for giving a read command to a flash memory chip having a first buffer region, a second buffer region and a storage
region, the method comprising:
receiving a host command from a host system by a flash memory controller having a buffer memory, wherein the host command
is a host read command and the host command comprises a first logic address, wherein the first logic address maps to a first
physical address of the storage region;

giving a general read command and a first cache read command to the flash memory chip by the flash memory controller according
to the host command so as to sequentially read a first data starting from the first physical address, wherein the first data
is moved from the storage region to the second buffer region, moved from the second buffer region to the first buffer region
and transferred from the first buffer region to the buffer memory, wherein in response to moving the first data from the storage
region to the second buffer region, the flash memory chip is in a busy state, and in response to moving the first data from
the second buffer region to the first buffer region, the flash memory chip is changed to be in a ready state, wherein a second
data is moved from the storage region to the second buffer region during the first data is transferred from the first buffer
region to the buffer memory and after the first data is transferred from the first buffer region to the buffer memory, the
second data is moved from the second buffer region to the first buffer region, wherein the second data is not requested by
the host command and a logic address corresponding to the second data follows the first logic address;

giving a second cache read command to the flash memory chip by the flash memory controller to read a third data, wherein the
third data is moved from the storage region to the second buffer region during the second data is transferred from the first
buffer region to the buffer memory and after the second data is transferred from the first buffer region to the buffer memory,
the third data is moved from the second buffer region to the first buffer region;

receiving a next host command from the host system, wherein the next host command comprises a second logic address;
determining whether the next host command is the host read command and whether the next host command follows the host command;
when the next host command is the host read command and the next host command follows the host command, transmitting the second
data from the buffer memory to the host system; and

when the next host command is the host read command and the next host command does not follow the host command, giving a first
reset command to the flash memory chip and giving the general read command and a third cache read command to the flash memory
chip by the flash memory controller to sequentially read a fourth data, from the flash memory chip, corresponding to the next
host command from a physical address mapping a fourth logic address.

US Pat. No. 9,058,256

DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method for writing data into a rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module includes a plurality of physical erasing units, each of the physical erasing units includes a plurality of physical
programming units, the physical erasing units are grouped into at least a data area and a spare area, the physical erasing
units of the spare area are used for substituting the physical erasing units of the data area to write data, a plurality of
logical units are configured for mapping to the physical erasing units of the data area, and each of the logical units includes
a plurality of logical pages, the data writing method comprising:
selecting at least one physical erasing unit from the physical erasing units of the spare area as a global random area, wherein
the global random area is used for temporarily storing data belonging to a plurality of updated logical pages, and the updated
logical pages belong to a plurality of updated logical units among the logical units;

building a global random area searching table to record a plurality of updated information corresponding to the updated logical
pages in the global random area;

receiving a write command and an updated data corresponding to the write command, wherein the updated data belongs to a first
logical page and the first logical page belongs to a first logical unit among the logical units;

recording a data dispersedness degree corresponding to the global random area;
determining whether the data dispersedness degree corresponding to the global random area is smaller than a data dispersedness
degree threshold; and

if the data dispersedness degree corresponding to the global random area is smaller than the data dispersedness degree threshold,
writing the updated data into the global random area and recording updated information corresponding to the first logical
page in the global random area searching table.

US Pat. No. 9,659,618

MEMORY INTERFACE, MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND CLOCK GENERATION METHOD

PHISON ELECTRONICS CORP.,...

1. A memory interface for connecting a memory controller to a volatile memory, comprising:
a sampling circuit configured to couple to the memory controller; and
a clock generation circuit coupled to the sampling circuit, the memory controller and the volatile memory,
wherein the clock generation circuit is configured to receive a first data strobe signal and a second data strobe signal from
the volatile memory, wherein the first data strobe signal and the second data strobe signal are differential signals corresponding
to each other,

wherein the clock generation circuit is further configured to generate a clock signal in response to the first data strobe
signal and the second data strobe signal if a relative relation between a first voltage value of the first data strobe signal
and a reference voltage value of a reference voltage signal conforms to a default condition,

wherein the sampling circuit is configured to sample a data signal from the volatile memory based on a raising edge and a
falling edge of the clock signal.

US Pat. No. 9,652,330

METHOD FOR DATA MANAGEMENT AND MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A method for data management, for a memory control circuit unit configured to control a rewritable non-volatile memory
module, the method comprising:
configuring a non-volatile random access memory (NVRAM) and a volatile random access memory (VRAM);
storing first data in the NVRAM, wherein the first data comprises writing data from a host system and specific data read from
the rewritable non-volatile memory module;

storing second data read from the rewritable non-volatile memory module in the VRAM;
when a memory storage device is re-powered on after a power failure, writing the first data into the rewritable non-volatile
memory module from the NVRAM; and

maintaining continuously the writing data stored in the NVRAM when at least a portion of the writing data is stored in a first
lower physical programming unit of the rewritable non-volatile memory module and data is not yet written to a first upper
physical programming unit of the rewritable non-volatile memory module corresponding to the first lower physical programming
unit,

wherein the step of storing the second data read from the rewritable non-volatile memory module in the VRAM comprises:
performing a garbage collection procedure on the rewritable non-volatile memory module to obtain a recycled data from a plurality
of physical erasing units of the rewritable non-volatile memory module; and

storing the recycled data in the VRAM, not in the NVRAM.

US Pat. No. 9,501,397

DATA WRITING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method, for writing data into a plurality of physical blocks, the data writing method comprising:
grouping the physical blocks into a plurality of physical units, wherein each of the physical units has a plurality of physical
pages, and each of the physical pages has a data bit area and a redundancy bit area;

grouping the physical units into at least a data area and a free area;
configuring a plurality of logical units to map to the physical units in the data area;
getting a physical unit among the physical units of the free area;
writing at least one data belonging to at least one logical unit among the logical units into a first physical page of the
gotten physical unit; and

after executing a data merging procedure to move the at least one data from the gotten physical unit into another physical
unit mapped to the at least one logical unit, writing an end mark into the redundancy bit area of a second physical page subsequent
to the first physical page in the gotten physical unit.

US Pat. No. 9,496,041

MEMORY PROGRAMMING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A memory programming method for a rewritable non-volatile memory module having a plurality of memory cells, the memory
programming method comprising:
performing a first programming process on the memory cells according to first write data and obtaining a first programming
result of the first programming process;

grouping the memory cells into a plurality of programming groups according to the first programming result;
performing a second programming process on the memory cells according to the first write data, wherein the second programming
process comprises:

programming a first programming group among the programming groups by using a first program voltage; and
programming a second programming group among the programming groups by using a second program voltage, wherein the first program
voltage and the second program voltage are different; and

after the first write data is programmed, performing the second programming process on the memory cells according to a second
write data without performing the first programming process according to the second write data.

US Pat. No. 9,442,834

DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory comprises
a first memory unit and a second memory unit, the first memory unit comprises a plurality of first physical erasing units,
and the second memory unit comprises a plurality of second physical erasing units, the data management method comprising:
grouping the plurality of the first physical erasing units into at least a data area and a spare area, and grouping the plurality
of the second physical erasing units into at least a data backup area and a command recording area;

configuring a plurality of logical addresses to map to the plurality of the first physical erasing units associated with the
data area;

receiving a write command, wherein the write command instructs to write a first data to at least one first logical address
of the plurality of the logical addresses;

writing the first data to one of the plurality of the first physical erasing units associated with the spare area of the first
memory unit and writing the first data to one of the plurality of the second physical erasing units associated with the data
backup area of the second memory unit in response to the write command;

recording at least a portion of the write command in one of the plurality of the second physical erasing units associated
with the command recording area; and

executing a data merging procedure on a valid data in the plurality of the first physical erasing units related to the first
data and the first data,

wherein a valid data in the plurality of the second physical erasing units related to the first data does not carry out the
data merging procedure with the first data.

US Pat. No. 9,348,693

DATA ACCESSING METHOD FOR FLASH MEMORY MODULE

PHISON ELECTRONICS CORP.,...

1. A data accessing method, suitable for a flash memory module, and the data accessing method comprising:
performing an error correction encoding for a data packet to be stored in the flash memory module to generate a sequence data
code containing the data packet and a corresponding error correction code of the data packet, wherein the data packet comprises
user data and system data, and the system data comprises logical to physical mapping relationship of the user data;

converting the sequence data code into a non-sequence data code based on an inverting operation for the user data, the system
data and the corresponding error correction code, wherein the user data, the system data, and the corresponding error correction
code are inverted in the non-sequence data code; and

storing the non-sequence data code to a page of the flash memory module.

US Pat. No. 9,235,501

MEMORY STORAGE DEVICE, MEMORY CONTROLLER THEREOF, AND METHOD FOR PROGRAMMING DATA THEREOF

PHISON ELECTRONICS CORP.,...

1. A data programming method for a memory storage device having a rewritable non-volatile memory chip, wherein the rewritable
non-volatile memory chip comprises a plurality of rewritable non-volatile memory modules, and each of the rewritable non-volatile
memory modules includes a plurality of physical blocks, and the data programming method comprising:
configuring a plurality of logical blocks for mapping to a portion of the physical blocks in the rewritable non-volatile memory
modules;

receiving a first write command from a host system, wherein a first logical address corresponding to the first write command
belongs to a first logical page;

in response to the first write command, determining whether one of the rewritable non-volatile memory modules has stored specific
data belonging to said first logical page, and if one of the rewritable non-volatile memory modules has not stored the specific
data belonging to said first logical page, serving the one of the rewritable non-volatile memory modules as one of at least
one first suitable memory module;

writing a first writing data corresponding to the first write command into a first physical block among the physical blocks
located in the at least one first suitable memory module if the at least one first suitable memory module is existent;

after the first write command is received, receiving a second write command from the host system, wherein a second logical
address corresponding to the second write command also belongs to said first logical page;

in response to the second write command, determining whether one of the rewritable non-volatile memory modules has stored
the specific data belonging to said first logical page, and if one of the rewritable non-volatile memory modules has not stored
the specific data belonging to said first logical page, serving the one of the rewritable non-volatile memory modules as one
of at least one second suitable memory module; and

writing a second writing data corresponding to the second write command into a second physical block among the physical blocks
located in the at least one second suitable memory module if the at least one second suitable memory module is existent,

wherein the at least one first suitable memory module is different from the at least one second suitable memory module.

US Pat. No. 9,583,217

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the decoding
method comprising:
reading the memory cells according to at least one hard decision voltage to obtain at least one hard bit, wherein the at least
one hard bit comprises a first hard bit:

performing a parity checking procedure for the at least one hard bit to obtain a plurality of syndromes, wherein each of the
at least one hard bit is corresponding to at least one of the syndromes;

determining whether the at least one hard bit has at least one error according to the syndromes;
if the at least one hard bit has the at least one error, updating the at least one hard bit according to channel information
of the at least one hard bit and syndrome weight information corresponding to the at least one hard bit, wherein the step
of updating the at least one hard bit according to the channel information of the at least one hard bit and the syndrome weight
information corresponding to the at least one hard bit comprises:

determining whether first syndrome weight information corresponding to the first hard bit among the syndrome weight information
matches a weight condition:

if the first syndrome weight information matches the weight condition, determining whether the channel information of the
first hard bit matches a channel condition;

if the channel information of the first hard bit matches the channel condition, updating the first hard bit; and
if the channel information of the first hard bit does not match the channel condition, not updating the first hard bit; and
if the at least one hard bit does not have the at least one error, outputting the at least one hard bit.

US Pat. No. 9,530,509

DATA PROGRAMMING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A data programming method, for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical erasing units, wherein a first physical erasing unit among the physical erasing units comprises
a plurality of lower physical programming units and a plurality of upper physical programming units corresponding to the lower
physical programming units, the data programming method comprising:
receiving first data and programming the first data into a first lower physical programming unit among the lower physical
programming units;

receiving second data;
performing a first data obtaining operation corresponding to the first lower physical programming unit to obtain third data,
wherein the first data obtaining operation comprises reading the first lower physical programming unit by using a second read
voltage, wherein a voltage value of the second read voltage is different from a default voltage value of a default read voltage
corresponding to the first lower physical programming unit; and

programming the second data into a first upper physical programming unit among the upper physical programming units according
to the third data.

US Pat. No. 9,479,183

MEMORY STORAGE DEVICE HAVING CLOCK AND DATA RECOVERY CIRCUIT

PHISON ELECTRONICS CORP.,...

1. A memory storage device, comprising:
a connection interface unit, configured to couple to a host system;
a rewritable non-volatile memory module comprising a plurality of physical erasing units; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the connection interface unit comprises a clock and data recovery circuit module,
wherein the clock and data recovery circuit module comprises a data frequency detection circuit and a clock control circuit,
wherein the data frequency detection circuit comprises:
a sampling circuit module, comprising a plurality of sampling circuits and configured to sample a data signal according to
a plurality of reference clocks and output a sampling result;

a first logic circuit module, coupled to the sampling circuits and configured to perform a first logic operation according
to the sampling result and output a first logic result;

a delay circuit module, coupled to the first logic circuit module and configured to delay the first logic result and output
the delayed first logic result;

a second logic circuit module, coupled to the delay circuit module and configured to perform a second logic operation according
to the first logic result and the delayed first logic result and output a second logic result; and

a frequency adjustment circuit, coupled to the second logic circuit module and configured to output a first frequency adjustment
signal according to the second logic result,

wherein the clock control circuit is coupled to the data frequency detection circuit and configured to perform a phase lock
according to the first frequency adjustment signal and a frequency of the data signal.

US Pat. No. 9,460,043

FLASH DRIVE WITH TRANSFORMING MECHANISM

PHISON ELECTRONICS CORP.,...

1. A flash drive with transforming mechanism, comprising:
a storage module having a storage unit and a first interface electrically connected to each other;
a switching module having a second interface and a third interface, wherein the second interface and the third interface are
in different types but are electrically connected to each other, and the first interface corresponds to the second interface;
and

a transforming mechanism located at a first position or a second position relative to the storage module, the switching module
being located in the transforming mechanism, and the switching module being structurally connected to the storage module via
the transforming mechanism, wherein

when the transforming mechanism is located at the first position, the first interface and the second interface are electrically
connected to each other, such that the storage module is configured to electrically connect to a host through the third interface,
and

when the transforming mechanism is located at the second position, the first interface of the storage module is configured
to physically connect to the host, and the third interface is accommodated in the transforming mechanism.

US Pat. No. 9,430,327

DATA ACCESS METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data access method for a rewritable non-volatile memory module, the rewritable non-volatile memory module comprising
a plurality of physical erasing units, and each of the physical erasing units comprising a plurality of physical programming
units, the data accessing method comprising:
filling dummy data to first data to generate second data, generating an error checking and correcting code corresponding to
the second data, generating an error checking and correcting code frame according to the second data and the error checking
and correcting code, writing the error checking and correcting code frame into a first physical programming unit among the
physical programming units, and mapping a logical address to the first physical programming unit;

receiving a read command, wherein the read command instructs to read data from the logical address;
reading the error checking and correcting code frame from the first physical programming unit to obtain a reading data stream,
wherein the reading data stream comprises third data and the error checking and correcting code;

adjusting the third data according to a pattern of the dummy data to generate fourth data when the third data cannot be corrected
by using the error checking and correcting code to obtain corrected data;

using the error checking and correcting code to correct the fourth data to obtain the corrected data, wherein the corrected
data is identical to the second data;

removing the dummy data from the corrected data to obtain fifth data.

US Pat. No. 9,342,404

DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of first memory cells, and the decoding method comprises:
reading the first memory cells according to a first read voltage to obtain a plurality of first verification bits;
performing a first hard bit mode decoding procedure according to the first verification bits, and determining whether the
first hard bit mode decoding procedure generates a first valid codeword by a first correcting circuit;

if the first valid codeword is generated by the first hard bit mode decoding procedure, outputting the first valid codeword;
if the first valid codeword is not generated by the first hard bit mode decoding procedure, performing a second hard bit mode
decoding procedure according to the first verification bits, and determining whether the second hard bit mode decoding procedure
generates a second valid codeword by a second correcting circuit, wherein a precision of the first correcting circuit is less
than a precision of the second correcting circuit;

if the second valid codeword is generated by the second hard bit mode decoding procedure, outputting the second valid codeword.

US Pat. No. 9,268,688

DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data management method, for managing data written into a rewritable non-volatile memory module by a host system, wherein
the rewritable non-volatile memory module includes a plurality of physical units, and each of the physical units includes
a plurality of physical pages, the data management method comprises:
receiving at least two pieces of update data corresponding to different logical access addresses among a plurality of logical
access addresses from the host system, wherein the at least two pieces of update data are corresponding to different logical
pages among a plurality of logical pages;

getting a physical unit from the physical units; and
writing the at least two pieces of update data into an identical physical page of the gotten physical unit,
wherein a size of each of the two pieces of update data is not greater than 4 kilobytes.

US Pat. No. 9,141,476

METHOD OF STORING SYSTEM DATA, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A method of storing system data for a memory storage apparatus, wherein the memory storage apparatus comprises a rewritable
non-volatile memory module, the rewritable non-volatile memory module comprises a plurality of physical erase units, each
of the physical erase units comprises a plurality of physical program units, the method comprising:
writing updated system data into at least one first physical program unit among the physical program units of a first physical
erase unit among the physical erase units; and

writing dummy data into at least one second physical program unit among the physical program units of the first physical erase
unit,

wherein the first physical erase unit is a system physical erase unit and one of the physical program units of the first physical
erase unit records a mark of a system physical erase unit.

US Pat. No. 9,519,436

MEMORY ERASING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory erasing method for a rewritable non-volatile memory module of a memory storage apparatus, wherein the rewritable
non-volatile memory module has a plurality of physical blocks, the memory erasing method comprising:
logically grouping the physical blocks into at least a data area and a spare area;
establishing a link list according to the physical blocks of the spare area, and storing the link list into the rewritable
non-volatile memory module, wherein the physical blocks of the spare area are recorded in the link list according to an arrangement
order; and

during every power on of the memory storage apparatus, selecting a plurality of third physical blocks among the physical blocks
in the spare area according to the link list and a predetermined number, and respectively executing an erase command on the
third physical blocks, wherein the third physical blocks are arranged at a beginning of the link list, and the number of the
third physical blocks is the predetermined number.

US Pat. No. 9,449,660

SAMPLING CIRCUIT MODULE, MEMORY CONTROL CIRCUIT UNIT, AND METHOD FOR SAMPLING DATA

PHISON ELECTRONICS CORP.,...

1. A sampling circuit module, comprising:
a delay-locked loop, comprising:
a control circuit, configured to receive a reference clock signal to output a first control signal; and
a delay circuit, coupled to the control circuit and comprising:
a state machine circuit, configured to receive the first control signal and output a second control signal and/or a third
control signal in response to the first control signal;

a first delay line circuit, coupled to the state machine circuit and configured to receive the reference clock signal and
the second control signal to output a first delay clock signal;

a second delay line circuit, coupled to the state machine circuit and configured to receive the reference clock signal and
the third control signal to output a second delay clock signal; and

a delay signal output circuit, coupled to the first delay line circuit, the second delay line circuit and the state machine
circuit and configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock
signal; and

a sampling circuit, coupled to the delay-locked loop and configured to receive the third delay clock signal and sample a data
signal according to the third delay clock signal to obtain sampled data,

wherein a first delay stage of the first delay line circuit is changed from a first stage to a second stage when the first
delay line circuit is in an idle state and the third delay clock signal is outputted,

wherein a second delay stage of the second delay line circuit is changed from a third stage to a fourth stage when the second
delay line circuit is in the idle state and the third delay clock signal is outputted.

US Pat. No. 9,425,569

STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A storage device, comprising:
a base being an electrical conductor; and
a storage unit comprising a first connecting interface and a second connecting interface, and the base being electrically
connected to the first connecting interface or the second connecting interface, wherein the storage unit further comprises
at least one memory chip, and the first connecting interface and the second connecting interface are structurally disposed
on the base respectively.

US Pat. No. 9,311,231

CONNECTING INTERFACE UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A connecting interface unit without a crystal oscillator, comprising:
a frequency detector configured to receive an input signal from a host system, and to detect a frequency difference between
the input signal and a first reference signal to generate a first frequency signal;

a phase detector configured to receive the input signal from the host system, and to detect a phase difference between the
input signal and the first reference signal to generate a first phase signal;

at least one filter configured to filter the first frequency signal to generate a second frequency signal, and to filter the
first phase signal to generate a second phase signal;

an oscillator coupled to the at least one filter, the frequency detector and the phase detector, and configured to oscillate
according to the second frequency signal and the second phase signal to generate the first reference signal, wherein the first
reference signal is for generating a clock signal;

a first sampling circuit coupled to the oscillator and configured to generate an input data signal according to the first
reference signal;

a transmitter circuit, not receiving a reference clock from a crystal oscillator, coupled to the oscillator and configured
to modulate an output data signal according to the clock signal to generate an output signal, and to transmit the output signal
to the host system; and

a storage unit coupled to the at least one filter and the oscillator, and configured to store an oscillation information of
the second frequency signal or the second phase signal if an amplitude of the input signal conforms to a threshold condition,

wherein the storage unit is configured to provide the oscillation information to the oscillator if the amplitude of the input
signal does not conform to the threshold condition, and the oscillator is configured to oscillate according to the oscillation
information to generate the first reference signal.

US Pat. No. 9,274,891

DECODING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of memory cells, and the decoding method comprises:
reading at least one of the memory cells according to a first read voltage to obtain at least one first verification bit;
executing a hard bit mode decoding procedure according to the at least one first verification bit, and determining whether
a first valid codeword is generated by the hard bit mode decoding procedure;

if the first valid codeword is not generated by the hard bit mode decoding procedure, obtaining storage information of the
at least one of the memory cells;

deciding a voltage number according to the storage information;
reading the at least one of the memory cells according to a plurality of second read voltages matching the voltage number
to obtain a plurality of second verification bits; and

executing a first soft bit mode decoding procedure according to the second verification bits.

US Pat. No. 9,268,554

CONTROLLING METHOD, MEMORY CONTROLLER, AND DATA TRANSMISSION SYSTEM

PHISON ELECTRONICS CORP.,...

1. A controlling method for a rewritable non-volatile memory module, comprising:
receiving a first command from a host system;
determining whether the first command is a configuration command according to a first command code of the first command;
when the first command is determined as the configuration command, analyzing a plurality of first action information in the
configuration command, analyzing a first execution sequence corresponding to the first action information, and executing the
first action information according to the first execution sequence, wherein each of the first action information is configured
to request the rewritable non-volatile memory module to execute a predetermined action; and

when the first command is determined not as the configuration command, executing the first command.

US Pat. No. 9,117,832

SEMICONDUCTOR DEVICE WITH PHYSICAL MANIPULATION DETECTOR AND CORRECTOR

PHISON ELECTRONICS CORP.,...

1. A semiconductor device, comprising:
a first semiconductor substrate;
a first dielectric layer with a first thickness, formed on a first surface of the first semiconductor substrate;
a first floating gate, formed on the first dielectric layer;
a first source diffusion region and a first drain diffusion region, respectively formed at two sides of the first floating
gate on the first surface of the first semiconductor substrate;

a first control gate diffusion region, formed separately from the first source diffusion region and the first drain diffusion
region, on a surface of the first semiconductor substrate, wherein the first source diffusion region, the first drain diffusion
region, the first floating gate, and the first control gate diffusion region form as a part of a first transistor;

a second semiconductor substrate;
a second dielectric layer with a second thickness, formed on a second surface of the second semiconductor substrate, wherein
the second thickness is larger than the first thickness of the first dielectric layer;

a second floating gate, formed on the second dielectric layer;
a second source diffusion region and a second drain diffusion region, respectively formed at two sides of the second floating
gate on the second surface of the second semiconductor substrate;

a second control gate diffusion region, formed separately from the second source diffusion region and the second drain diffusion
region, on a surface of the second semiconductor substrate, wherein the second source diffusion region, the second drain diffusion
region, the second floating gate, and the second control gate diffusion region form as a part of a second transistor; and

a common word line, electrically connected to the first control gate diffusion region and the second control gate diffusion
region.

US Pat. No. 9,086,954

DATA STORING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data storing method, for a memory storage apparatus including a flash memory module, the flash memory module has a plurality
of physical erase unit and each of the physical erase unit has a plurality of physical program unit, the data storing method
comprising:
detecting an operating temperature of the memory storage apparatus through a thermal sensor;
determining whether the operating temperature of the memory storage apparatus is larger than a predetermined temperature;
using a first data storing mode to program the flash memory module if the operating temperature of the memory storage apparatus
is not larger than the predetermined temperature;

using a second data storing mode to program the flash memory module if the operating temperature of the memory storage apparatus
is larger than the predetermined temperature,

wherein the first data storing mode is different from the second data storing mode;
writing first data into a first physical program unit among the physical program units of the physical erase units;
reading the first data from the first physical program unit and correcting the read first data; and
identifying an amount of error bits occurring in the first data read from the first physical program unit,
wherein the step of using the second data storing mode to program the flash memory module comprises:
determining whether the amount of the error bits occurring in the first data read from the first physical program unit is
larger than a second number and smaller than a first number;

if the amount of the error bits occurring in the first data read from the first physical program unit is larger than the second
number and smaller than the first number, writing the corrected first data into a second physical program unit among the physical
program units of the physical erase units and re-map a logical address mapped to the first physical program unit to the second
physical program unit, and

wherein the step of using the first data storing mode to program the flash memory module comprises:
determining whether the amount of the error bits occurring in the first data read from the first physical program unit is
larger than the first number; and

if the amount of the error bits occurring in the first data read from the first physical program unit is larger than the first
number, writing the corrected first data into a third physical program unit among the physical program units of the physical
erase units and re-map a logical address mapped to the first physical program unit to the third physical program unit,

wherein the second number is smaller than the first number.

US Pat. No. 9,720,609

DATA PROTECTING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data protecting method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of word lines, and memory cells on the same word line constitute at least one physical page, the data
protecting method comprising:
assigning a plurality of physical pages into a plurality of encoding groups, wherein the step of assigning the physical pages
into the encoding groups comprises: grouping a first physical page among the physical pages to a first encoding group among
the encoding groups, and grouping a second physical page among the physical pages to a second encoding group among the encoding
groups, wherein the first physical page is composed of memory cells connected to a first word line among the word lines, the
second physical page is composed of memory cells connected to a second word line among the word lines, and the first word
line is adjacent to the second word line;

storing user data and a parity code corresponding to the user data in each of the physical pages;
respectively encoding the user data in the physical pages of the encoding groups to generate a plurality of group parity codes
respectively corresponding to the encoding groups; and

if the user data stored in the first physical page fails to be corrected according to the parity code stored in the first
physical page, correcting the user data stored in the first physical page by using the group parity code corresponding to
the first encoding group.

US Pat. No. 9,721,669

DATA PROTECTION METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data protection method, for a memory storage apparatus comprising a rewritable non-volatile memory module having a plurality
of physical erasing units, the data protection method comprising:
obtaining a current system time from a host system as a boot time if the memory storage apparatus is powered on, wherein a
basic input/output system of the host system loads and executes instruction programs in an expansion ROM of the memory storage
apparatus for transmitting the current system time to the memory storage apparatus;

obtaining a shutdown time corresponding to the memory storage apparatus;
calculating an off time from the shutdown time to the boot time; and
performing a refresh operation on physical erasing units if the off time is longer than an off time threshold.

US Pat. No. 9,612,630

FLASH DRIVE

PHISON ELECTRONICS CORP.,...

1. A flash drive, comprising:
a housing;
a carrier, movably disposed inside the housing along a first axis, wherein the carrier has an elastic arm, and the elastic
arm is deformable along a second axis; and

a storage module, assembled to the carrier and moving together with the carrier in relative to the housing so that a connector
of the storage module is moved outside the housing or hidden inside the housing, wherein the elastic arm has a contour protruded
along a direction away from the storage module when not receiving force,

wherein the housing has a pair of engaging slots disposed along the first axis and located on a first sidewall of the housing
to correspond to the elastic arm, the pair of engaging slots is located on an edge of the first opening,

wherein the housing further comprises a rib disposed on the first sidewall and located on the edge of the first opening, wherein
the rib is connected between the pair of engaging slots, and

wherein the rib extends along the first axis, and a thickness of the rib along the second axis gradually increases along the
first axis towards the second opening.

US Pat. No. 9,607,704

DATA READING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data reading method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of memory cells, and the data reading method comprising:
receiving a read command from a host system, wherein the read command instructs to read data from a plurality of first memory
cells among the memory cells;

sending a first read command sequence to obtain a first data string from the first memory cells;
performing a decoding procedure on the first data string to generate a decoded first data string;
if there is no error bit in the decoded first data string, using the decoded first data string as a corrected data to be sent
to the host system in response to the read command; and

if there is an error bit in the decoded first data string, sending a second read command sequence to obtain a second data
string from the first memory cells, performing a logical operation on the decoded first data string and the second data string
to obtain an adjusting data string, adjusting the decoded first data string according to the adjusting data string to obtain
an adjusted first data string, and using a data string obtained after re-performing the decoding procedure on the adjusted
first data string as the decoded first data string,

wherein the step of adjusting the decoded first data string according to the adjusting data string to obtain the adjusted
first data string comprises:

identifying a plurality of unrecognized data in the decoded first data string and a plurality of unrecognized data addresses
corresponding to the unrecognized data; and

performing an exclusive or operation on the unrecognized data in the decoded first data string by using data corresponding
to the unrecognized data in the adjusting data string to adjust the decoded first data string to obtain the adjusted first
data string.

US Pat. No. 9,467,175

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a parity check code, comprising:
reading a codeword belonging to the parity check code from a rewritable non-volatile memory module, wherein the codeword comprises
a plurality of first message bits and a plurality of first parity bits, and the parity check code corresponds to a parity
check matrix and a generation matrix;

performing an encoding procedure of the parity check code on the first message bits to generate a plurality of second parity
bits; and

generating a plurality of syndromes corresponding to the codeword according to the first parity bits and the second parity
bits, wherein the syndromes are used to determine whether the codeword is a valid codeword,

wherein the parity check matrix comprises a message part matrix and a parity part matrix, and the step of generating the syndromes
corresponding to the codeword according to the first parity bits and the second parity bits comprises:

adding a vector (P1) generated by the first parity bits to a vector (P2) generated by the second parity bits to generate a first vector; and

multiplying the parity part matrix by the first vector to generate the syndromes (S) corresponding to the codeword,
wherein the step of performing the encoding procedure of the parity check code on the first message bits to generate the second
parity bits comprises: multiplying a vector (M1) generated by the first message bits by the generation matrix to generate the second parity bits, so that a result generated
by multiplying the parity check matrix by a vector (M1 P2) constituted by the first message bits and the second parity bits is a zero vector.

US Pat. No. 9,369,283

METHOD FOR ENTERING PASSWORD AND PORTABLE ELECTRONIC DEVICE AND UNLOCKING METHOD AND DATA AUTHENTICATING METHOD

PHISON ELECTRONICS CORP.,...

1. A method of entering password, for a portable electronic device, wherein the portable electronic device has a touch screen,
the method of entering password comprising:
displaying an interface for entering somatosensory password;
measuring an angle variation of the portable electronic device;
recording the measured angle variation of the portable electronic device if the measured angle variation exceeds a predetermined
threshold and updating a count value corresponding to a total number of the recorded angle variation of the portable electronic
device on at least one dimension;

generating a somatosensory signal data set according to the recorded angle variation of the portable electronic device and
the updated count value;

generating a user password data according to the somatosensory signal data set;
encrypting the user password data according to an encryption algorithm to generate an encrypted user password data;
transmitting the encrypted user password data to an authentication unit, wherein the authentication unit decrypts the encrypted
user password data according a decryption algorithm to obtain the user password data, and verifies a user identification of
the portable electronic device according to the user password data obtained;

wherein the steps of updating the count value and generating the somatosensory signal data set comprises:
updating a count value corresponding to a total number of the recorded angle variation of the portable electronic device on
each of the at least one dimension; and

generating the somatosensory signal data set according to the recorded angle variation of the portable electronic device on
each of the at least one dimension and the updated count value corresponding to the total number of the recorded angle variation
of the portable electronic device on each of the at least one dimension.

US Pat. No. 9,336,081

DATA WRITING AND READING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME FOR IMPROVING RELIABILITY OF DATA ACCESS

PHISON ELECTRONICS CORP.,...

1. A data writing method for writing data into a rewritable non-volatile memory module, the data writing method comprising:
compressing the data to generate a first data;
determining whether a length of the first data is smaller than a predetermined length;
when the length of the first data is not smaller than the predetermined length, outputting the first data as a compressed
data;

when the length of the first data is not smaller than the predetermined length, padding the first data by using at least one
padding bit to generated a second data, and outputting the second data as the compressed data, wherein a length of the second
data is equal to the predetermined length;

inputting the compressed data without a predetermined padding data into an error checking and correcting circuit to generate
an error checking and correcting (ECC) code corresponding to the compressed data;

generating an ECC frame according to the compressed data, the ECC code corresponding to the compressed data, and the predetermined
padding data; and

writing the ECC frame into the rewritable non-volatile memory module.

US Pat. No. 9,268,687

DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method for a rewritable non-volatile memory module having a plurality of physical erasing units, and the
data writing method comprising:
grouping the physical erasing units into at least a data area and a spare area;
configuring a plurality of logical units for mapping to the physical erasing units of the data area; and
dynamically reserving a predetermined number of physical erasing units dedicating to write sequential data,
wherein the step of dynamically reserving the predetermined number of physical erasing units dedicating to write the sequential
data comprises:

receiving a write command from a host system, wherein the write command instructs to write first data into at least one first
logical unit among the logical units;

selecting at least one first physical erasing unit from among the physical erasing units of the spare area, writing the first
data into the at least one first physical erasing unit, associating the at least one first physical erasing unit with the
data area,

if a value obtained by subtracting a number of the at least one physical erasing unit from a garbage collection threshold
value before adjustment is greater than a minimum threshold value, the garbage collection threshold value after adjustment
is set to the value obtained by subtracting the number of the at least one physical erasing unit from the garbage collection
threshold value before adjustment,

if the value obtained by subtracting the number of the at least one physical erasing unit from the garbage collection threshold
value before adjustment is not greater than the minimum threshold value, the garbage collection threshold value after adjustment
is set the minimum threshold value.

US Pat. No. 9,146,805

DATA PROTECTING METHOD, MEMORY STORAGE DEVICE, AND MEMORY CONTROLLER

PHISON ELECTRONICS CORP.,...

1. A data protecting method for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory
module comprises a plurality of word lines, a plurality of bit lines, and a plurality of memory cells, each of the memory
cells is located on one of the word lines and one of the bit lines, and the memory cells form a plurality of physical erasing
units, the data protecting method comprising:
storing data into a plurality of first memory cells of the memory cells, wherein the first memory cells are located on a plurality
of first word lines of the word lines and a plurality of first bit lines of the bit lines; and

generating, by an error checking and correcting circuit, a first error correcting code by using first data of the data stored
in the first memory cells,

wherein the first data is only stored in one memory cell of each of the first bit lines among the first memory cells.

US Pat. No. 9,122,498

FIRMWARE CODE LOADING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A firmware code loading method for loading a firmware code from a rewritable non-volatile memory module of a memory storage
apparatus, wherein the firmware code operates a memory storage apparatus and at least having a plurality of segments, the
rewritable non-volatile memory module at least has a first memory part and a second memory part, and the firmware code loading
method comprising:
obtaining a storage address for storing a first portion firmware code copy corresponding to a first portion of the plurality
of segments in the first memory part;

obtaining a storage address for storing a second portion firmware code copy corresponding to a second portion of the plurality
of segments in the second memory part; and

using a parallel mode or a interleave mode to load the first portion firmware code copy and the second portion firmware code
copy respectively from the first memory part and the second memory part into a buffer memory.

US Pat. No. 9,123,578

NON-VOLATILE MEMORY DEVICE

PHISON ELECTRONICS CORP.,...

1. A non-volatile memory device, comprising:
a well, disposed in a substrate;
a plurality of word lines, arranged in an array, disposed on the substrate and extending in a first direction;
a plurality of inter-poly dielectric films respectively between the substrate and the plurality of word lines;
a plurality of floating gates, respectively disposed between the well and the plurality of inter-poly dielectric films;
a plurality of tunnel oxide films, respectively disposed between the well and the plurality of floating gates; and
a plurality of first bit lines and a plurality of second bit lines, arranged periodically, disposed over the plurality of
word lines, and extending in a second direction,

wherein a first distance from the first bit lines to the substrate is smaller than a second distance from the second bit lines
to the substrate.

US Pat. No. 9,875,027

DATA TRANSMITTING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A data transmitting method for a memory storage device having a rewritable non-volatile memory module, comprising:
detecting a temperature of the memory storage device;
determining whether the temperature of the memory storage device is greater than a temperature threshold;
writing first data into the rewritable non-volatile memory module within a first delay time according to a delay count corresponding
to a unit temperature if the temperature is greater than the temperature threshold.

US Pat. No. 9,685,221

MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE DEVICE AND REFERENCE VOLTAGE GENERATION METHOD

PHISON ELECTRONICS CORP.,...

1. A memory control circuit unit, configured to control a volatile memory, the memory control circuit unit comprising:
a processor core;
a memory controller, coupled to the processor core; and
a memory interface, coupled to the memory controller and the volatile memory,
wherein the memory interface comprises:
a first connection interface, configured to couple to the memory controller;
a second connection interface, configured to couple to the volatile memory; and
a reference voltage generator, coupled to the first connection interface and the second connection interface,
wherein the reference voltage generator is configured to detect the first impedance characteristic of the memory controller
via the first connection interface, detect the second impedance characteristic of the volatile memory via the second connection
interface and generate the internal reference voltage according to the detection result,

wherein a voltage value of the internal reference voltage is positively correlated to a voltage value of a supply voltage
of the memory controller, and the internal reference voltage is for resolving a data signal received by the memory interface.

US Pat. No. 9,639,419

READ VOLTAGE LEVEL ESTIMATING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A read voltage level estimating method for a rewritable non-volatile memory module, the read voltage level estimating method
comprising:
reading a first region of the rewritable non-volatile memory module according to a first read voltage level to obtain a first
encoding unit, wherein the first encoding unit belongs to a block code;

performing a first decoding procedure on the first encoding unit and recording first decoding information;
reading the first region according to a second read voltage level to obtain a second encoding unit, wherein the second encoding
unit belongs to the block code;

performing a second decoding procedure on the second encoding unit and recording second decoding information; and
estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information.

US Pat. No. 9,582,224

MEMORY CONTROL CIRCUIT UNIT, MEMORY STORAGE APPARATUS AND DATA ACCESSING METHOD

PHISON ELECTRONICS CORP.,...

1. A memory control circuit unit, comprising:
a host interface configured to couple to a host system;
a memory interface configured to couple to a rewritable non-volatile memory module, wherein the rewritable non-volatile memory
module has a plurality of physical programming units;

a plurality of data randomizer circuits, wherein each of the data randomizer circuits is configured to disarrange input data
to output a corresponding disarranged data and each of the data randomizer circuits has an index number;

a data selection circuit; and
a memory management circuit coupled to the host interface, the memory interface, the data randomizer circuits and the data
selection circuit,

wherein the memory management circuit is configured to receive a first data stream from the host system, and input the first
data stream into the data randomizer circuits,

wherein the data randomizer circuits are configured to disarrange the first data to respectively output a plurality of second
data,

wherein the data selection circuit is configured to select one of the second data streams as a third data stream according
to contents of the second data streams,

wherein the memory management circuit is further configured to issue a command for the rewritable non-volatile memory module
to write the third data stream into a first physical programming unit among the physical programming units,

wherein each of the second data streams comprises a plurality of data bits, and each of the data bits is a first value or
a second value,

wherein in the operation of selecting the one of the second data streams as the third data stream according to the contents
of the second data streams,

the data selection circuit sequentially groups consecutive identical data bits in the second data streams into one string,
wherein each of the second data stream is divided into a plurality of the strings and each of the data bits in the corresponding
string is identical,

wherein the data selection circuit calculates a corresponding first count of each of the second data streams, wherein the
corresponding first counts are respectively amounts of a plurality of first strings among the strings of the second data streams,
and a length of each of the first strings is 1 and each of the data bits of the first strings is the first value,

wherein the corresponding first count of the one of the second data streams is not less than the corresponding first count
of each of the other second data streams among the second data streams.

US Pat. No. 9,543,983

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method, for a rewritable non-volatile memory module comprising a plurality of memory cells, the decoding method
comprising:
sending a read command sequence for reading the plurality of memory cells so as to obtain a plurality of first bits;
determining whether the first bits have at least one first error;
if the first bits have the at least one first error, executing a first iteration decoding procedure on the first bits so as
to obtain a plurality of second bits, and recording first bit flipping information of the first iteration decoding procedure;

determining whether the second bits have at least one second error;
if the second bits have the at least one second error, executing a second iteration decoding procedure on the second bits
according to the first bit flipping information so as to obtain a plurality of third bits;

if the second bits do not have the at least one second error, outputting the second bits;
recording second bit flipping information of the second iteration decoding procedure according to the first bit flipping information;
determining whether the third bits have at least one third error;
if the third bits have the at least one third error, executing a third iteration decoding procedure on the third bits according
to the second bit flipping information so as to obtain a plurality of fourth bits; and

if the third bits do not have the at least one third error, outputting the third bits,
wherein the second bit flipping information indicates a specific bit among the third bits having a bit value different from
an original bit value of said specific bit among the first bits.

US Pat. No. 9,514,040

MEMORY STORAGE DEVICE AND MEMORY CONTROLLER AND ACCESS METHOD THEREOF

PHISON ELECTRONICS CORP.,...

1. A method of accessing a memory storage device, wherein the memory storage device has a rewritable non-volatile memory chip,
and the rewritable non-volatile memory chip has a plurality of physical blocks, the method comprising:
configuring a plurality of logical blocks to be mapped to a part of the physical blocks;
dividing the logical blocks into at least a first partition and a second partition, wherein the first partition records an
auto-execute file;

determining whether a trigger signal is existent, wherein the trigger signal is generated through interaction between a portable
object and the memory storage device;

in response to determining that the trigger signal is existent, sending a media ready message to a host system to allow the
host system to automatically run the auto-execute file and receive a first password;

determining whether to provide the logical blocks in the second partition to the host system according to the first password
received from the host system; and

in response to determining that the trigger signal is not existent and receiving a media check command from the host system,
not providing the logical blocks in the second partition to the host system and sending a media not ready message to the host
system,

wherein the step of sending the media ready message to the host system comprises:
controlling the memory storage device to simulate a power off and reconnection behavior;
simulating a compact disc (CD) partition by using the first partition; and
sending, the media ready message to the host system when the media check command is received from the host system.

US Pat. No. 9,514,819

PROGRAMMING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A programming method for a rewritable non-volatile memory module comprising a plurality of physical erasing units, and
the programming method comprising:
receiving at least one first write command;
determining whether a current state of the rewritable non-volatile memory module matches at least one first condition;
selecting a first physical erasing unit from the physical erasing units and sending a first skipping write command sequence
according to the at least one first write command after it is determined that the current state of the rewritable non-volatile
memory module matches the at least one first condition, wherein the first skipping write command sequence instructs to execute
a first skipping programming process,

wherein the first skipping programming process comprises:
programming a first word line among a plurality of word lines of the first physical erasing unit according to first data corresponding
to the at least one first write command; and

after the first word line is programmed, skipping at least one second word line adjacent to the first word line among the
word lines of the first physical erasing unit, and programming a third word line not adjacent to the first word line among
the word lines of the first physical erasing unit according to the first data; and

sending a normal write command sequence if the current state of the rewritable non-volatile memory module does not match the
at least one first condition, wherein the normal write command sequence instructs to execute a normal programming process,

wherein the normal programming process comprises:
programming the first word line according to the first data; and
after the first word line is programmed, programming the at least one second word line according to the first data.

US Pat. No. 9,396,804

MEMORY PROGRAMMING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

10. A memory control circuit unit, configured to access a rewritable non-volatile memory module, and the memory control circuit
unit comprising:
a host interface, configured to couple to a host system;
a memory interface, configured to couple to the rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module comprises a physical erasing unit, the physical erasing unit comprises a plurality of word line layers and a
plurality of bit line sets, the bit line sets are arranged along a first direction and separated from one another, each of
the bit line sets comprises a plurality of bit lines, the bit lines of each bit line sets are extended along a second direction,
arranged along a third direction and separated from one another, the word line layers are stacked along the second direction
and the word line layers are separated from one another, a memory cell is provided at intersection of each of the word line
layers and each of the bit lines of each of the bit line sets, at least one physical programming unit is constituted by the
memory cells at intersection of one of the bit line sets and one of the word line layers; and

a memory management circuit, coupled to the host interface and the memory interface,
wherein the memory management circuit is configured to issue a first command sequence, so as to program a first data stream
into at least one first physical programming unit of the physical erasing unit, wherein the at least one first physical programming
unit is constituted by the memory cells at intersection of at least one first bit line set among the bit line sets and a first
word line layer among the word line layers,

wherein after programming the first data stream into the at least one first physical programming unit, the memory management
circuit is further configured to issue a second command sequence, so as to program another data stream into at least one another
physical programming unit of the physical erasing unit, wherein the at least one another physical programming unit is constituted
by the memory cells at intersection of the at least one first bit line set among the bit line sets and another word line layer
among the word line layers.

US Pat. No. 9,274,943

STORAGE UNIT MANAGEMENT METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A storage unit management method, configured to manage a plurality of physical units in a rewritable non-volatile memory
module, wherein the physical units are at least grouped into a data area and a spare area, the storage unit management method
comprising:
configuring a plurality of logical units for mapping to a part of the physical units;
determining whether the rewritable non-volatile memory module contains cold data;
performing a first wear-leveling procedure on the physical units when it is determined that the rewritable non-volatile memory
module does not contain any cold data; and

performing a second wear-leveling procedure on the physical units when it is determined that the rewritable non-volatile memory
module contains the cold data,

wherein the first wear-leveling procedure is to perform a physical unit exchange between the data area and the spare area
every time a first time interval occurs, and the second wear-leveling procedure is to perform the physical unit exchange between
the data area and the spare area every time a second time interval occurs,

wherein when the physical unit exchange is performed between the data area and the spare area every time the second time interval
occurs, a physical unit with the highest erase count is selected from all of the physical units belonging to the spare area
for exchanging with the physical unit with the lowest erase count in the data area,

wherein the physical units are at least grouped into a data area and a spare area, and the step of determining whether the
rewritable non-volatile memory module contains the cold data comprises:

recording a first memory erase count when the physical unit exchange is performed between the data area and the spare area,
wherein the first memory erase count is a memory erase count of the rewritable non-volatile memory module at the time of a
specific physical unit belonging to the spare area is exchanged to the data area;

updating the memory erase count of the rewritable non-volatile memory module as the rewritable non-volatile memory module
is in use;

obtaining the memory erase count of the rewritable non-volatile memory module at the time of the specific physical unit is
again associated to the spare area to serve as a second memory erase count;

comparing a difference between the first memory erase count and the second memory erase count with a predetermined value;
determining that the rewritable non-volatile memory module does not contain the cold data when the difference is smaller than
or equal to the predetermined value; and

determining that the rewritable non-volatile memory module contains the cold data when the difference is greater than the
predetermined value.

US Pat. No. 9,063,888

PROGRAM CODE LOADING AND ACCESSING METHOD, MEMORY CONTROLLER, AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A program code loading method for loading a program code from a rewritable non-volatile memory module, wherein the program
code comprises a plurality of data segments, the rewritable non-volatile memory module has at least one first physical block
and at least one second physical block, the first physical block stores a first program code copy corresponding to the program
code, the second physical block stores a second program code copy corresponding to the program code, and the first program
code copy and the second program code copy respectively have a plurality of data segments identical to the data segments of
the program code, the program code loading method comprising:
sequentially loading a first data segment of the first program code copy;
determining whether the first data segment of the first program code copy contains at least one uncorrectable error bit; and
when the first data segment of the first program code copy contains at least one uncorrectable error bit, loading a first
data segment of the second program code copy; and

after loading the first data segment of the second program code copy, sequentially loading a second data segment of the first
program code copy,

wherein a part of the first program code copy and a part of the second program code copy are loaded.

US Pat. No. 9,778,880

MEMORY CONTROL CIRCUIT UNIT, DATA TRANSMITTING METHOD AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A memory control circuit unit for controlling a memory storage device, the memory control circuit unit comprising:
a host interface, coupled to a first host system;
a memory interface, coupled to a rewritable non-volatile memory module;
a memory management circuit, coupled to the host interface and the memory interface; and
a pulse pattern detecting circuit, coupled to the host interface and the memory management circuit,
wherein the memory storage device comprises a reset pin coupled to the memory control circuit unit and the pulse pattern detecting
circuit, so as to receive a first pulse signal from a second host system,

wherein the pulse pattern detecting circuit is configured to determine whether a first serial pulse pattern of the first pulse
signal is conformed to a first predetermined serial pulse pattern,

wherein if the first serial pulse pattern is conformed to the first predetermined pulse pattern, the memory management circuit
is further configured to disable a reset function of the memory storage device.

US Pat. No. 9,715,429

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

9. A memory storage device, comprising:
a connection interface unit, configured to couple to a host system;
a rewritable non-volatile memory module, comprising a plurality of memory cells; and
a memory control circuit unit, coupled to the connection interface unit and the rewritable non-volatile memory module,
wherein the memory control circuit unit is configured to transmit a first read command sequence which instructs reading first
data from a plurality of first memory cells among the plurality of memory cells based on a first read voltage level,

wherein the memory control circuit unit is further configured to perform a first decoding operation on the first data,
wherein the memory control circuit unit is further configured to estimate a channel status of the rewritable non-volatile
memory module and obtaining a second read voltage level according to the channel status if the first decoding operation fails,
wherein the second read voltage level is different from the first read voltage level, and the second read voltage level is
different from an optimal read voltage level,

wherein the memory control circuit unit is further configured to transmit a second read command sequence which instructs reading
second data from the plurality of first memory cells based on the second read voltage level,

wherein the memory control circuit unit is further configured to perform a second decoding operation on the second data.

US Pat. No. 9,619,380

DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory storage apparatus, comprising:
a connecting interface unit configured to couple to a host system;
a rewritable non-volatile memory module;
a memory control circuit unit coupled to the connecting interface unit and the rewritable non-volatile memory module, wherein
the memory control circuit unit includes a first buffer memory and the first buffer memory includes a first data buffer area;
and

a second buffer memory coupled to the first buffer memory, wherein the second buffer memory includes a second data buffer
area and a transmission bandwidth of the second buffer memory is smaller than a transmission bandwidth of the first buffer
memory,

wherein the memory control circuit unit is configured to receive a write command, a start logical address corresponding to
the write command and first data corresponding to the write command,

wherein the memory control circuit unit is further configured to determine whether the first data is a successive big data,
if the first data is the successive big data, the memory control circuit unit temporarily stores the first data into the first
data buffer area and writes the first data from the first data buffer area into the rewritable non-volatile memory module,

if the first data is not the successive big data, the memory control circuit unit temporarily stores the first data into the
second data buffer area without storing the first data into the first data buffer area.

US Pat. No. 9,613,705

METHOD FOR MANAGING PROGRAMMING MODE OF REWRITABLE NON-VOLATILE MEMORY MODULE, AND MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data programming method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical units, wherein the physical units comprise a plurality of first physical units and a plurality
of second physical units, wherein the data programming method comprises:
configuring, initially, the first physical units to be programmed based on a first programming mode and the second physical
units to be programmed based on a second programming mode;

receiving first data from a host system;
determining whether a used capacity of the first physical units reaches a preset capacity;
determining whether at least second data stored in the first physical units matches a preset condition if the used capacity
of the first physical units reaches the preset capacity, wherein the second data is valid data belonging to at least one first
logical unit; and

selecting at least one physical unit from the second physical units and programming the selected physical unit based on the
first programming mode to store at least one part of the first data if the second data matches the preset condition.

US Pat. No. 9,613,707

DATA PROGRAMMING METHOD FOR AVOIDING UNAVAILABILITY OF REWRITABLE NON-VOLATILE MEMORY MODULE DUE TO HIGHER ERASE COUNT OF PART OF PHYSICAL ERASING UNITS, AND MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data programming method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical erasing units, the data programming method comprising:
dividing the physical erasing units into a plurality of first type physical erasing units and a plurality of second type physical
erasing units, wherein a programming mode of the first type physical erasing units is a first programming mode, and a programming
mode of the second type physical erasing units is a second programming mode;

setting the first type physical erasing units as a current writing area and recording a current writing data amount;
calculating a first data amount threshold according to a first writable data amount of the first type physical erasing units
and a change ratio;

receiving first data;
determining whether the current writing data amount is less than the first data amount threshold;
if the current writing data amount is less than the first data amount threshold, programming the first data into at least
one physical erasing unit of the first type physical erasing units using the first programming mode and updating the current
writing data amount according to a data amount of the first data; and

if the current writing data amount is not less than the first data amount threshold, setting the second type physical erasing
units as the current writing area, resetting the current writing data amount, programming the first data into at least one
physical erasing unit of the second type physical erasing units using the second programming mode and updating the current
writing data amount according to the data amount of the first data.

US Pat. No. 9,224,492

MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. An memory management method for a rewritable non-volatile memory module comprising a plurality of memory cells, and the
memory management method comprising:
obtaining a threshold voltage distribution of the memory cells, wherein the threshold voltage distribution comprises a plurality
of states, and each of the states represents a storage status;

determining whether a width of a gap window between two neighboring states among the states is less than a threshold value;
and

if the width of the gap window is less than the threshold value, eliminating one of the two neighboring states.

US Pat. No. 9,213,631

DATA PROCESSING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE DEVICE USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data processing method for a re-writable non-volatile memory module having a plurality of physical programming units,
wherein each of the plurality of physical programming units has a data bit area and a redundancy bit area, the data bit area
has a plurality of physical access addresses, a plurality of logical programming units is configured to map to at least a
portion of the plurality of physical programming units, and each of the plurality of logical programming units has a plurality
of logical access addresses, the data processing method comprising:
receiving a first write data stream, wherein the first write data stream associates with a first logical access address among
the plurality of logical access addresses, and the first logical access address associates with a first logical programming
unit among the plurality of logical programming units;

selecting a first physical programming unit from the plurality of physical programming units;
determining whether the first write data stream associates with a pattern;
if the first write data stream does not associate with the pattern, setting identification information corresponding to the
first logical access address as a default value, programming the first write data stream into the first logical access address
among the plurality of logical access addresses in the data bit area of the first physical programming unit and storing the
identification information corresponding to the first logical access address in a predetermined area;

if the first write data stream associates with the pattern, setting the identification information corresponding to the first
logical access address as an identification value corresponding to the pattern, and storing the identification information
corresponding to the first logical access address in the predetermined area, wherein the first write data stream is not programmed
into the first physical programming unit; and

mapping the first logical programming unit to the first physical programming unit,
wherein a step of storing the identification information corresponding to the first logical access address to the predetermined
area comprises:

programming the identification information corresponding to the first logical access address into the redundancy bit area
of the first physical access address.

US Pat. No. 9,155,189

MULTI-LAYER PRINTED CIRCUIT BOARD STRUCTURE, CONNECTOR MODULE AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A multi-layer printed circuit board (MLPCB) structure, suitable for being connected with a connector, wherein the connector
comprises at least one connection terminal, the MLPCB structure comprising:
a first layout layer, comprising:
a shielding element, configured to provide a grounding voltage; and
at least one pad, coupled to the at least one connection terminal; and
a second layout layer, disposed corresponding to the first layout layer and comprising at least one wire,
wherein one end of each wire is coupled to one of the at least one pad,
wherein a projection plane of the shielding element projected on the second layout layer covers a predefined proportion of
the at least one wire.

US Pat. No. 9,838,389

INTEGRATED CIRCUIT, CODE GENERATING METHOD, AND DATA EXCHANGE METHOD

PHISON ELECTRONICS CORP.,...

1. An integrated circuit, comprising:
at least one first input/output end;
at least one current path, connected with the first input/output end;
at least one control end, disposed above the at least one current path, configured to apply a plurality of control end voltages
on the at least one current path;

at least one second input/output end, connected with the current path; and
at least one sense-amplifier, connected with the at least one second input/output end, configured to sense the electric current
from the at least one second input/output end and identify the threshold voltage according to one of the control end voltages
and the electric current;

wherein at least one current adjusting element is disposed in the at least one current path to adjust an electrical current.

US Pat. No. 9,817,573

SMART CARD MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A smart card management method configured to a flash memory storage device having a flash memory module and a smart card,
the smart card management method comprising:
receiving a first setting command corresponding to a temporary file from a host system, wherein the temporary file is associated
with the smart card, the first setting command comprises a plurality of first setting messages, and one of the first setting
messages comprises first setting command verification information and first location identification information, wherein the
first setting command verification information is configured to verify whether the first setting command is configured to
set the temporary file, and the first location identification information is configured to find a logical unit corresponding
to the one of the first setting messages, wherein the first location identification information comprises ordinal position
identification information configured to indicate an ordinal position of the one of the first setting messages in the first
setting messages;

obtaining the first setting command verification information from the first setting command and determining whether the first
setting command verification information conforms to a default setting command verification information;

obtaining logical units corresponding the first setting messages, and recording a first logic range belonging to the temporary
file in a look-up table according to the logical units corresponding to the first setting messages if the first setting command
verification information conforms to a default setting command verification information;

receiving an operating command from the host system;
determining whether logical units accessed by the operation command are within the first logic range recorded in the look-up
table; and

performing a data accessing operation of the smart card according the operating command if the logical units accessed by the
operation command are within the first logic range.

US Pat. No. 9,773,565

MEMORY RETRY-READ METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A memory retry-read method for a rewritable non-volatile memory module comprising a plurality of word lines, the memory
retry-read method comprising:
setting a first sequence of a plurality of retry-read parameter groups based on a plurality of first weights of the retry-read
parameter groups, wherein each of the retry-read parameter groups corresponds to one of the first weights;

reading first data from a first physical programming unit on a first word line of the word lines based on a first read voltage;
choosing a first adjustment retry-read parameter group from the retry-read parameter groups based on the first sequence if
the first data are unable to be corrected by a first corresponding error checking and correcting code;

retrying reading first new data from the first physical programming unit based on the first adjustment retry-read parameter
group;

determining that the first adjustment retry-read parameter group is a first available retry-read parameter group if the first
new data are able to be corrected by the first corresponding error checking and correcting code; and

adjusting the first weight of the first available retry-read parameter group.

US Pat. No. 9,733,832

BUFFER MEMORY ACCESSING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A buffer memory accessing method, suitable for a buffer memory of a flash memory storage device, wherein the flash memory
storage device comprises a rewritable non-volatile memory module, wherein the buffer memory has a plurality of write buffer
units, the buffer memory accessing method comprising:
receiving a write data from a host system;
determining whether a number of used write buffer units of the write buffer units is not smaller than a predefined value;
temporarily storing the write data to one of the write buffer units that is not being used and transmitting a confirmation
message corresponding to the write data to the host system if the number of the used write buffer units of the write buffer
units is smaller than the predefined value; and

temporarily storing the write data to one of the write buffer units that is not being used and transmitting the confirmation
message corresponding to the write data to the host system after a predefined time interval if the number of the used write
buffer units of the write buffer units is not smaller than the predefined value.

US Pat. No. 9,652,378

WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A writing method for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
comprises a plurality of physical blocks, each of the physical blocks comprises the same number of a plurality of physical
pages, and the physical blocks are at least grouped into a storage area, wherein each of the physical block is the minimum
unit for erasing, and the data storing method comprises:
configuring a plurality of logical addresses to map to a part of the physical pages in the storage area, wherein at least
one of the physical pages stores at least one valid data, wherein a plurality of spare physical blocks among the physical
blocks in the storage area are not mapped to the logical addresses;

transmitting a first write command to the rewritable non-volatile memory module, for writing a first data having a first data
length to at least one first physical page of a first spare physical block among the spare physical blocks;

receiving a status signal transmitted by the rewritable non-volatile memory module;
selecting a second spare physical block from the spare physical blocks and copying the at least one valid data having a second
data length to at least one second physical page of the second spare physical block, after transmitting the first write command
and before receiving the status signal, wherein the second spare physical block is different from the first spare physical
block; and

deciding the second data length according to the first data length, a volume of all the logical addresses and a volume of
all the spare physical blocks in the storage area,

wherein the second data length is not less than the first data length.

US Pat. No. 9,665,481

WEAR LEVELING METHOD BASED ON TIMESTAMPS AND ERASE COUNTS, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A wear leveling method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of physical erasing units, the wear leveling method comprising:
recording a timestamp for each of the physical erasing units storing valid data according to a programming sequence of physical
erasing units storing valid data among the physical erasing units;

recording an erase count for each of the physical erasing units;
selecting a first physical erasing unit from the physical erasing units storing valid data according to the timestamps of
the physical erasing units;

getting a second physical erasing unit from the physical erasing units not storing valid data according to the erase count
of each of the physical erasing units; and

writing the valid data in the first physical erasing unit into the second physical erasing unit and marking the first physical
erasing unit as a physical erasing unit not storing valid data.

US Pat. No. 9,431,132

DATA MANAGING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data managing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises
a plurality of physical erasing units and a plurality of logic units for mapping to at least a part of the physical erasing
units, the data managing method comprising:
receiving a first reading command from a host system, wherein the first reading command indicates to read data from a first
logic unit among the logic units, and the first logic unit is mapped to a first physical erasing unit among the physical erasing
units;

reading a first data stream from the first physical erasing unit, wherein the first data stream comprises first user data,
a first error detecting code and a first error correcting code;

using the first error detecting code, the first error correcting code and the first user data to perform a first decoding
procedure, wherein the first decoding procedure comprises:

performing an error correcting code syndrome calculation on the first data stream to generate a first syndrome corresponding
to the first data stream;

performing a cyclic redundancy check calculation on the first user data to generate a second error detecting code corresponding
to the first user data;

generating a first error locator polynomial corresponding to the first data stream according to the first syndrome and calculating
a first error bit number of the first data stream;

obtaining the first error bit location corresponding to the first user data according to the first syndrome, the first error
locator polynomial and an error location searching rule;

performing the cyclic redundancy check calculation on the first error bit location to generate a third error detecting code
corresponding to the first error bit location;

performing an XOR logic operation on the third error detecting code and the second error detecting code to generate a fourth
error detecting code;

determining whether the fourth error detecting code is equal to the first error detecting code; and
stopping the first decoding procedure if the fourth error detecting code is equal to the first error detecting code, and correcting
the first user data to obtain the corrected user data by using the first error bit location checking whether the first data
stream is correctable, and transmitting the corrected user data to the host system, and identifying the first user data to
be successfully decoded; and

outputting an error message to the host system if the fourth error detecting code is not equal to the first error detecting
code; and

transmitting corrected user data obtained by successfully decoding the first user data to the host system in response to the
first reading command if the first user data is successfully decoded.

US Pat. No. 9,378,130

DATA WRITING METHOD, AND MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data writing method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has
a plurality of physical blocks, each of the physical blocks has a plurality of physical page sets sequentially arranged, each
of the physical page sets has a lower physical page and an upper physical page, a speed of writing data into the lower physical
pages is faster than a speed of writing data into the upper physical pages, and the data writing method comprises:
partitioning the physical blocks into at least a data area and a spare area;
configuring a plurality of logical blocks according to the physical blocks belonging to the data area, wherein each of the
logical blocks has a plurality of logical pages;

receiving a first write command, wherein the first write command instructs to write first updated data into a first logical
block among the logical blocks, wherein a size of the first updated data is no less than a size of each of the physical blocks,
and the updated data is a continuous data;

selecting a plurality of physical blocks from the physical blocks of the spare area as a plurality of spare physical blocks
of a spare physical block set corresponding to the first logical block;

writing the first updated data only into the lower physical pages of the spare physical blocks of the spare physical block
set in response to the first write command;

receiving a second write command, wherein the second write command instructs to write second updated data into the first logical
block among the logical blocks;

writing the second updated data only into the lower physical pages of the spare physical blocks of the spare physical block
set in response to the second write command, and at least one part of the first updated data become invalid data; and

after the second updated data is written into the lower physical pages of the spare physical blocks of the spare physical
block set, moving valid data of all the logical pages of the first logical block from the spare physical blocks of the spare
physical block set to a first physical block among the physical blocks of the data area, wherein the valid data of all the
logical pages of the first logical block are sequentially written into the lower physical page and the upper physical page
of each of the physical page sets of the first physical block, and the lower physical page and the upper physical page of
each of the physical page sets of the first physical block are programmed together.

US Pat. No. 9,213,636

DATA ACCESSING METHOD FOR FLASH MEMORY STORAGE DEVICE HAVING DATA PERTURBATION MODULE, AND STORAGE SYSTEM AND CONTROLLER USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data accessing method, for a flash memory storage device having a data perturbation module, wherein a flash memory of
the flash memory storage device has a plurality of blocks, the data accessing method comprising:
receiving a read command from a host, wherein the read command indicates reading data from a logical block and the logical
block has not been written with data after a card activation process; and

transmitting a predetermined data to the host in response to the read command, wherein the predetermine data is obtained by
decoding encoded data stored in the flash memory through the data perturbation module.

US Pat. No. 9,152,348

DATA TRANSMITTING METHOD, MEMORY CONTROLLER AND DATA TRANSMITTING SYSTEM

PHISON ELECTRONICS CORP.,...

1. A data transmitting method for a memory controller, wherein the memory controller is configured to couple to a host system,
and the host system is configured to execute a plurality of threads so as to transmit a plurality of commands to the memory
controller via at least one human interface device (HID) interface, each of the commands corresponds to one of the threads,
a plurality of packets are transmitted between the memory controller and the host system, the packets comply with a HID class,
and each of the packets at least comprises a command series column and a data column, the data transmitting method comprises:
receiving at least one command packet among the packets by the memory controller from the host system, wherein the command
series column of the at least one command packet records a first command among the commands, and the data column of the at
least one command packet records a content of the first command;

executing an operation corresponding to the first command by the memory controller according to the content of the first command
so as to generate responding data, wherein the responding data is divided into at least one responding data packet among the
packets;

transmitting a responding packet among the packets by the memory controller to the host system, wherein the command series
column of the responding packet records the first command;

transmitting he at least one responding data packet by the memory controller to the host system, wherein the command series
column of the at least one responding data packet records the first command;

determining if one of the at least one responding data packet is lost according to the responding packet by the host system,
wherein the loss of the at least one responding data packet occurs during the at least one responding data packet being transmitted;

if the host system determines that a first responding data packet among the at least one responding data packet is lost, transmitting
a retransmitting packet among the packets by the host system to the memory controller so as to request the memory controller
to retransmit the first responding data packet, wherein the command series column of the retransmitting packet records the
first command; and

retransmitting the first responding data packet by the memory controller to the host system so as to response to the retransmitting
packet.

US Pat. No. 10,001,928

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A memory management method for a memory storage device, wherein the memory storage device comprises a rewritable non-volatile memory module and a buffer memory, and the buffer memory at least comprises a first buffer area and a second buffer area, and the memory management method comprises:loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and
loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity,
wherein the first data quantity is less than the second data quantity.

US Pat. No. 9,965,400

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A memory management method for a rewritable non-volatile memory module, and the memory management method comprising:using a first management mode to manage the rewritable non-volatile memory module after the rewritable non-volatile memory module is powered on; and
using a second management mode to manage the rewritable non-volatile memory module if a shut down command is received from a host system,
wherein the second management mode is different from the first management mode and the second management mode executes at least one mandatory processing procedure in background,
wherein, after the shut down command is received from the host system, one or more write commands are received from the host system, and user data corresponding to the one or more write commands are written into the rewritable non-volatile memory module, and after the user data is written, system data corresponding to the written user data in a memory is written into the rewritable non-volatile memory module.

US Pat. No. 9,886,071

MEMORY STORAGE DEVICE AND POWER MANAGEMENT METHOD THEREOF

PHISON ELECTRONICS CORP.,...

1. A memory storage device comprising:
a rewritable non-volatile memory module;
a first connection interface unit configured to connect to a host device, wherein the first connection interface unit having
a first power pin and a channel configuration pin;

a second connection interface unit having a second power pin;
a power management circuit configured to receive a first power supply voltage from the host device via the first power pin
of the first connection interface unit, and supply an operation voltage to the memory control circuit unit and the rewritable
non-volatile memory module; and

a memory control circuit unit, coupled to the power management circuit, the rewritable non-volatile memory, the first connection
interface unit and the second connection interface unit,

if an external power supply device is electrically connected with the second connection interface unit, the power management
circuit receives a second power supply voltage from the external power supply device via the second power pin of the second
connection interface unit, and supplies the output voltage to the memory control circuit unit and the rewritable non-volatile
memory module, wherein the second power supply voltage is supplied to the host device via the first power pin of the first
connection interface unit;

if the external power supply device is electrically disconnected with the second connection interface unit, the power management
circuit receives a third power supply voltage via the channel configuration pin of the first connection interface unit, and
supplies the output voltage to the memory control circuit unit and the rewritable non-volatile memory module;

during receiving the third power supply voltage via the channel configuration pin of the first connection interface unit,
if the first power supply voltage is detected on the first power pin of the first connection interface unit, the power management
circuit receives the first power supply voltage via the first power pin of the first connection interface unit, and supplies
the output voltage to the memory control circuit unit and the rewritable non-volatile memory module.

US Pat. No. 9,858,366

SIMULATOR AND SIMULATING METHOD FOR FLASH MEMORY BACKGROUND

PHISON ELECTRONICS CORP.,...

1. A simulating method for a flash memory, applicable to a simulator, wherein the simulator comprises a flash memory interface
coupled to a memory controller, a detector coupled to the flash memory interface, a processor coupled to the detector and
a non-flash memory interface coupled to the processor and a data processing unit, the simulating method comprising:
setting, by the data processing unit, a predetermined response condition;
providing, by the detector, a plurality of command sets, wherein each of the command sets comprises multiple commands and
corresponds to a memory type;

receiving, by the flash memory interface, a first command from the memory controller;
if the first command matches one of the multiple commands, identifying, by the detector, a second command in the command sets
according to the first command;

receiving, by the data processing unit, the second command transmitted from the processor through the non-flash memory interface
after the detector identifies the second command,

determining, by the data processing unit, whether the second command matches the predetermined response condition;
obtaining, by the processor, a first signal, which is transmitted from the data processing unit through the non-flash memory
interface, corresponding to the second command according to the predetermined response condition; and

transmitting, by the processor, the first signal to the memory controller.

US Pat. No. 9,830,077

DATA WRITING METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method, for a rewritable non-volatile memory module having a plurality of physical erasing units, each of
the physical erasing units having a plurality of physical programming units, and the data writing method comprising:
at least grouping the physical erasing units into a temporary area and a storage area, wherein the physical erasing units
of the temporary area are operated in a single-page mode for writing data and the physical erasing units of the storage area
are operated in a multi-page mode for writing data;

selecting a first physical erasing unit from among the physical erasing units of the temporary area, copying a plurality of
valid data in the first physical erasing unit to a second physical erasing unit among the physical erasing units of the temporary
area, and performing an erasing operation on the first physical erasing unit;

selecting a third physical erasing unit from among the physical erasing units of the temporary area, copying a plurality of
valid data in the third physical erasing unit to a fourth physical erasing unit among the physical erasing units of the storage
area, and performing the erasing operation on the third physical erasing unit;

selecting a seventh physical erasing unit from among the physical erasing units of the storage area, copying a plurality of
valid data in the seventh physical erasing unit to an eighth physical erasing unit among the physical erasing units of the
temporary area, performing the erasing operation on the seventh physical erasing unit, and copying, in response to the erasing
operation being completed on the seventh physical erasing unit, the valid data previously belonging to the seventh physical
erasing unit and currently being stored in the eighth physical erasing unit to a ninth physical erasing unit among the physical
erasing units of the storage area.

US Pat. No. 9,760,456

MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A memory management method, for controlling a rewritable non-volatile memory module, the memory management method comprising:
detecting a replacement physical unit number of the rewritable non-volatile memory module, wherein the replacement physical
unit number is related to a number of at least one replacement physical unit in the rewritable non-volatile memory module,
wherein each of the at least one replacement physical unit is configured to replace a bad physical unit in the rewritable
non-volatile memory module;

adjusting an available capacity of the rewritable non-volatile memory module from a first available capacity to a second available
capacity if the replacement physical unit number of the rewritable non-volatile memory module meets a default condition;

providing second capacity information with respect to the second available capacity of the rewritable non-volatile memory
module to a host system;

receiving a second operation instruction; and
transmitting a format operation instruction sequence to instruct to format the rewritable non-volatile memory module according
to the second operation instruction,

wherein the formatted rewritable non-volatile memory module has the second available capacity,
wherein the available capacity is a total capacity of a plurality of available physical units in the rewritable non-volatile
memory module, wherein each of the available physical units does not belong to the at least one replacement physical unit.

US Pat. No. 9,710,374

DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

9. A memory storage device comprising:
a connector, configured to couple to a host system;
a rewritable non-volatile memory module, comprising a first memory unit and a second memory unit, wherein the first memory
unit comprises a plurality of first physical erasing units, and the second memory unit comprises a plurality of second physical
erasing units; and

a memory controller, coupled to the connector and the rewritable non-volatile memory module, wherein the memory controller
is configured to configure a plurality of logical addresses and map the logical addresses to a part of the first physical
erasing units of the first memory unit and a part of the second physical erasing units of the second memory unit,

wherein the memory controller is further configured to receive a writing command from a host system, wherein the writing command
instructs to write first data into a first logical address among the logical addresses,

wherein the memory controller is further configured to select a third physical erasing unit from the first physical erasing
units of the first memory unit or the second physical erasing units of the second memory unit,

wherein the memory controller is configured to determine whether the third physical erasing unit belongs to the first memory
unit,

if the third physical erasing unit belongs to the first memory unit, the memory controller is further configured to erase
a second physical erasing unit among the second physical erasing units of the second memory unit while writing the first data
into the third physical erasing unit determined to be belonging to the first memory unit,

if the third physical erasing unit does not belong to the first memory unit, the memory controller is further configured to
erase a first physical erasing unit among the first physical erasing units of the first memory unit while writing the first
data into the third physical erasing unit,

wherein the memory controller is further configured to at least group the first physical erasing units of the first memory
unit and the second physical erasing units of the second memory unit into a data area and a spare area, wherein the part of
the first physical erasing units and the part of the second physical erasing units belong to the data area, and

wherein the memory controller is further configured to configure a first erasing area and a second erasing area, wherein the
third physical erasing unit belongs to the spare area, the erased first physical erasing unit among the first physical erasing
units of the first memory unit belongs to the first erasing area, and the erased second physical erasing unit among the second
physical erasing units of the second memory unit belongs to the second erasing area,

wherein, when a reading, writing, or erasing operation is performed on the first memory, another reading, writing or erasing
operation is simultaneously performed on the second memory unit.

US Pat. No. 9,665,480

MEMORY MANAGEMENT METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A memory management method, for managing a rewritable non-volatile memory module having a plurality of physical erasing
units, and the memory management method comprising:
grouping a plurality of non-spare physical erasing units in the physical erasing units into at least one first physical erasing
unit and at least one second physical erasing unit according to a data quantity of valid data stored in each non-spare physical
erasing unit, wherein the data quantity of the valid data stored in the at least one first physical erasing unit is more than
the data quantity of the valid data stored in the at least one second physical erasing unit, and a data updating frequency
of each of the at least one first physical erasing unit is lower than the data updating frequency of each of the at least
one second physical erasing unit;

selecting at least one third physical erasing unit from the at least one first physical erasing unit, wherein the at least
one third physical erasing unit stores a quantity of valid data less than a preset value; and

selecting at least one fourth physical erasing unit from at least one spare physical erasing unit in the physical erasing
units, and copying valid data stored in each of the at least one third physical erasing unit to the at least one fourth physical
erasing unit.

US Pat. No. 9,601,887

SWITCHING MODULE AND ELECTRONIC DEVICE

PHISON ELECTRONICS CORP.,...

1. An electronic device, comprising:
a switching module having a first interface assembly and a second interface assembly electrically connected to each other;
and

a storage unit having a third interface assembly, wherein the second interface assembly and the third interface assembly are
corresponding to each other so that the third interface assembly is butt-jointed to the second interface assembly and then
electrically connected to the first interface assembly, wherein the storage unit is a system integration package (SIP) and
the third interface assembly is an universal serial bus plug,

wherein at least one terminal of the first interface assembly correspondingly connects to at least one terminal of the second
interface assembly to integrally form a terminal pin, and a pair of the at least one terminals connected to each other of
the first interface assembly and the second interface assembly are opposite ends of the terminal pin,

wherein the switching module comprises:
a body having a first end and a second end opposite to each other, the first interface assembly being disposed at the first
end and the second interface assembly being disposed at the second end;

a first housing having a first portion and a second portion, the first portion having a pair of lateral openings opposite
to each other and accommodating the body, the first interface assembly, the second interface assembly, and the entire storage
unit, wherein the third interface assembly of the storage unit is configured to electrically connect the second interface
assembly through one of the pair of lateral openings and the second portion is packaged at one of the pair of lateral openings,
and a host is configured to electrically connect the first interface assembly through another one of the pair of lateral openings,
the third interface assembly is propped against between the second interface assembly and a bottom side of the first portion,
such that the switching module and the SIP storage unit are integrated into one single unit, and there is no metal housing
surrounded the second interface and located between the first housing and the third interface assembly when the third interface
is butt-jointed to the second interface assembly.

US Pat. No. 9,552,287

DATA MANAGEMENT METHOD, MEMORY CONTROLLER AND EMBEDDED MEMORY STORAGE APPARATUS USING THE SAME

PHISON ELECTRONICS CORP.,...

1. A data management method for an embedded memory storage apparatus, wherein the embedded memory storage apparatus has a
plurality of physical blocks and each of the physical blocks has a plurality of fast physical pages and a plurality of slow
physical pages, the management method comprising:
initially marking a status of a state indication unit as an initial status;
executing a burning step of a high temperature process, where the burning step is configured to use only at least one of the
fast physical pages of the embedded memory storage apparatus to store predetermined data;

marking the status of the state indication unit as a first status;
reading the predetermined data, wherein the predetermined data is stored only in at least one of the fast physical pages;
detecting a status of the state indication unit; and
re-storing the predetermined data by executing a plurality of write commands from a host system in batches into at least one
of the fast physical pages and at least one of the slow physical pages after the high temperature process if the status of
the state indication unit state is detected as the first status.

US Pat. No. 9,529,666

DECODING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A decoding method for a rewritable non-volatile memory module comprising a plurality of first memory cells, the decoding
method comprising:
sending a first read command sequence, wherein the first read command sequence is configured to read the first memory cells
according to a first reading voltage, so as to obtain a plurality of first verification bits;

executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword
is generated by the first decoding procedure;

if the first valid codeword is not generated by the first decoding procedure, sending a second read command sequence, wherein
the second read command sequence is configured to read each of the first memory cells a plurality of times at different voltage
levels, so as to obtain a plurality of second verification bits corresponding to each of the first memory cells without performing
an error correction procedure on the second verification bits;

classifying a threshold voltage of each of the first memory cells into one of a plurality of different voltage intervals according
to the second verification bits not being decoded;

calculating a total number of the first memory cells included in each of the voltage intervals;
obtaining a first channel reliability message according to the total number; and
executing a second decoding procedure according to the second verification bits and the first channel reliability message.

US Pat. No. 9,437,309

OPERATING METHOD OF NAND FLASH MEMORY UNIT

PHISON ELECTRONICS CORP.,...

1. An operating method of a NAND flash memory unit, wherein the NAND flash memory unit comprises a plurality of gate layers,
a conductive structure, and a charge trapping layer, wherein the conductive structure and the charge trapping layer penetrate
the gate layers, wherein the charge trapping layer is disposed between the conductive structure and the gate layers, and wherein
the operating method comprises:
applying an electric potential difference between a first end of the conductive structure and a second end of the conductive
structure so as to generate a current in the conductive structure to heat up the charge trapping layer.

US Pat. No. 9,966,467

INTEGRATED CIRCUIT AND CODE GENERATING METHOD

PHISON ELECTRONICS CORP.,...

1. An integrated circuit, comprising:at least one first input/output end;
at least one current path, connected with the first input/output end;
at least one control end, disposed above the at least one current path, configured to apply a plurality of control end voltages on the at least one current path; and
at least one second input/output end, connected with the current path;
at least one sense-amplifier, connected with the at least one second input/output end, configured to sense a plurality of threshold voltages corresponding to the at least one control end; and
a processing circuit, configured to categorize each of the threshold voltages into a plurality of states,
wherein, the width and the thickness of the current path are defined according to the de Broglie length (DBL), and the length of the current path is longer than the width and the thickness of the current path,
wherein the width and the thickness of the current path are no higher than 10 nm.

US Pat. No. 9,836,121

EYE-WIDTH DETECTOR, MEMORY STORAGE DEVICE AND EYE-WIDTH DETECTION METHOD OF DATA SIGNAL

PHISON ELECTRONICS CORP.,...

1. An eye-width detector, comprising:
a phase interpolator, configured to receive a first clock signal and a phase control signal and output a second clock signal;
a calibration circuit, coupled to the phase interpolator,
wherein the calibration circuit is configured to receive the first clock signal and the second clock signal and output a first
control signal;

an eye-width detection circuit, coupled to the phase interpolator and the calibration circuit,
wherein the eye-width detection circuit is configured to receive a data signal, the first clock signal and the second clock
signal and generate a first sampling value and a second sampling value,

wherein the eye-width detection circuit is further configured to output a second control signal if the first sampling value
and the second sampling value do not match a first condition,

wherein the eye-width detection circuit is further configured to output eye-width information of the data signal if the first
sampling value and the second sampling value match the first condition; and

a multiplexer, coupled to the phase interpolator, the calibration circuit and the eye-width detection circuit,
wherein the multiplexer is configured to receive the first control signal and the second control signal and output the phase
control signal in response to a selection signal.

US Pat. No. 9,823,844

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT, AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory management method configured for a rewritable non-volatile memory module, wherein the rewritable non-volatile
memory module comprises a plurality of physical erasing units, wherein each of the physical erasing units of the physical
erasing units has a plurality of physical programming units, and the memory management method comprises:
receiving a write command and a first data and a first instruction information corresponding to the write command, wherein
the write command is configured to instruct writing the first data into a first logical unit, wherein the first logical unit
has a plurality of logical sub-units, wherein the first instruction information is configured to instruct writing the first
data into at least one first logical sub-unit among the logical sub-units of the first logical unit;

executing a load-align operation corresponding to the first data to the first data according to the first instruction information;
writing an aligned first data obtained through the load-align operation into a first physical programming unit if a predetermined
event does not occur during the load-align operation; and

stopping the load-align operation and storing the first data and the first instruction information corresponding to the write
command into a first physical erasing unit among the physical erasing units if the predetermined event occurs during the load-align
operation, wherein the first instruction information is stored as a first valid bits information corresponding to the first
data in the first physical erasing unit.

US Pat. No. 9,772,937

DATA PROCESSING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A method of data processing, for a memory storage apparatus having a rewritable non-volatile memory module and a smartcard
chip, wherein the rewritable non-volatile memory module comprises a plurality of physical erase units, and each of the physical
erase units comprises a plurality of physical program units, the method comprising:
receiving a write command from a host system, wherein a write data stream corresponding to the write command comprises a plurality
of sub-data streams, and each of the sub-data stream is attached with a data index mark by an application installed in the
host system, wherein the write data stream corresponds to an original data stream to be transmitted to the memory storage
apparatus by the application, and a first rule is pre-agreed by the memory storage apparatus with the application, wherein
the first rule comprises a predetermined function, an initial parameter selecting manner and a parameter adjusting manner,
and the application selects an initial parameter according to the initial parameter selecting manner, substitutes the initial
parameter into the predetermined function so as to obtain the data index mark attached to a first sub-data stream in the original
data stream, and the application further selects initial parameters corresponding to each of the other sub-data streams of
the plurality of sub-data streams according to the parameter adjusting manner, the data index mark of the first sub-data stream
and a sequence of the sub-data streams in the original data stream, and determines the corresponding data index mark individually
attached to each of the other sub-data streams of the plurality of sub-data streams by substituting the initial parameters
of each of corresponding other sub-data streams into the predetermined function, wherein the parameter adjusting manner is
associated with incrementing regularity or decrementing regularity between the initial parameters of each of the other sub-data
streams of the plurality of sub-data streams of the original data stream;

reordering a sequence of the sub-data streams to comply with a sequence of the original data stream according to the first
rule pre-agreed with the application and the data index mark of each of the sub-data streams; and

transmitting the reordered sub-data streams to the smartcard chip.

US Pat. No. 9,710,193

METHOD OF DETECTING MEMORY MODULES, MEMORY CONTROL CIRCUIT UNIT AND STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A method of detecting a rewritable non-volatile memory module by a memory control circuit unit through a memory interface,
the method comprising:
(a) by the memory control circuit unit, setting an output voltage of a write protect pin of a control bus of the memory interface
as a first logic level for the rewritable non-volatile memory module, giving a read status command through the control bus
to the rewritable non-volatile memory module, and receiving a first status message through a data bus of the memory interface
from the rewritable non-volatile memory module in response to the read status command, wherein the control bus and the data
bus are buses independent from each other;

(b) by the memory control circuit unit, determining whether a bit data representing a logic status of the write protect pin
in the first status message conforms to a status corresponding to the first logic level;

(c) by the memory control circuit unit, setting an output voltage of the write protect pin of the control bus as a second
logic level, giving the read status command through the control bus, and receiving a second status message through the data
bus;

(d) by the memory control circuit unit, determining whether the bit data representing the logic status of the write protect
pin in the second status message conforms to a status corresponding to the second logic level; and

(e) if the bit data representing the logic status of the write protect pin in the first status message conforms to the status
corresponding to the first logic level and the bit data representing the logic status of the write protect pin in the second
status message conforms to the status corresponding to the second logic level, identifying that the rewritable non-volatile
memory module has physically connected to the memory interface by the memory control circuit unit.

US Pat. No. 9,690,490

METHOD FOR WRITING DATA, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT

PHISON ELECTRONICS CORP.,...

1. A method for writing data, adapted to a memory control circuit unit, the method comprising:
receiving a write command and first data corresponding to the write command;
obtaining initial data transmission information of the first data according to compression information of the first data,
wherein the initial data transmission information of the first data comprises information with respect to whether the first
data is sequential; and

determining whether the initial data transmission information conforms to a predetermined condition according to whether the
first data is the sequential data;

if the initial data transmission information conforms to the predetermined condition, compressing the first data to second
data and writing the second data into a rewritable non-violate memory module; and

if the initial data transmission information does not conform to the predetermined condition, writing the first data into
the rewritable non-violate memory module,

wherein the compression information of the first data further comprises information with respect to a data stream transmission
rate of the second data, and the data stream transmission rate of the second data is a rate at which the second data is being
transmitted to the rewritable non-volatile memory module through the memory interface,

wherein the step of determining whether the initial data transmission information conforms to the predetermined condition
according to whether the first data is the sequential data further comprising:

determining that the initial data transmission information conforms to the predetermined condition according to a threshold
of the predetermined condition comprising at least one of a compression ratio condition, a compression speed condition, a
decompression transmission speed condition, a decompression speed condition and a decompression transmission speed condition;

if the first data is the sequential data, setting the threshold of the predetermined condition to be a first threshold; and
if the first data is not the sequential data, setting the threshold of the predetermined condition to be a second threshold,
wherein the first threshold is higher than the second threshold.

US Pat. No. 9,639,475

BUFFER MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A buffer memory management method for a buffer memory of a memory storage device having a rewritable non-volatile memory
module, and the buffer memory management method comprising:
allocating a mapping table zone in the buffer memory;
dividing the mapping table zone into a first zone and a second zone, wherein each of the first zone and the second zone has
a plurality of continuous buffer units;

loading a plurality of logical address-physical address mapping tables from the rewritable non-volatile memory module into
the first zone and the second zone, wherein each of the logical address-physical address mapping tables is temporarily stored
into one of the buffer units in the first zone or one of the buffer units in the second zone;

receiving a first write command from a host system, wherein the first write command instructs writing first data into a first
logical address, and a first logical address-physical address mapping table to which the first logical address belongs is
already temporarily stored into a first buffer unit among the buffer units in the second zone;

updating the first logical address-physical address mapping table, and moving the updated first logical address-physical address
mapping table into a second buffer unit among the buffer units in the first zone;

after moving the updated first logical address-physical address mapping table into the second buffer unit among the buffer
units in the first zone, marking the second buffer unit as a dirty status; and

if all the buffer units in the first zone are marked as the dirty status, restoring the logical address-physical address mapping
tables temporarily stored in all the buffer units in the first zone back to the rewritable non-volatile memory module.

US Pat. No. 9,600,363

DATA ACCESSING METHOD, MEMORY CONTROLLING CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data accessing method for a memory storage apparatus, wherein the memory storage apparatus has a rewritable non-volatile
memory module, the rewritable non-volatile memory module has a plurality of physical erasing units, and each of the physical
erasing units has a plurality of physical programming units, the data accessing method comprising:
receiving a first data stream, generating a first check code corresponding to the first data stream by using a first check
code circuit, and generating a first data set according to the first data stream and the first check code corresponding to
the first data stream;

obtaining the first data stream and the first check code corresponding to the first data stream from the first data set by
using a second check code circuit and checking the first data stream by using the first check code corresponding to the first
data stream;

generating a second check code according to information corresponding to the checked first data stream by using a third check
code circuit;

generating an error checking and correcting code by using an error checking and correcting circuit;
generating a data frame according to the checked first data stream, the second check code, and the error checking and correcting
code; and

writing the data frame to a first physical programming unit of the physical programming units,
wherein the first check code circuit is different from the third check code circuit.

US Pat. No. 9,146,691

METHOD FOR MANAGING COMMANDS IN COMMAND QUEUE, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A method for managing a plurality of commands received from a host system, the method comprising:
configuring a command queue register, a first indicator, and a second indicator, wherein the command queue register comprises
a plurality of command transient units, and each of the command transient units has a command index pointing to a command
storage address;

configuring a command index register, wherein the command index register comprises a start index, an end index, and an outstanding
command index;

receiving at least one first command from the host system;
storing the at least one first command in the command queue register according to a plurality of first indication bits in
the first indicator and updating the first indication bits according to a current storage status of the command queue register
to generate a plurality of updated first indication bits;

generating a plurality of updated second indication bits according to the updated first indication bits in the first indicator
and a plurality of second indication bits in the second indicator;

obtaining the number of the at least one first command and at least one first command index among the command indices according
to the updated second indication bits, wherein the at least one first command index corresponding to at least one command
transient unit storing the at least one first command in the command queue register;

adding the at least one first command index into the command index register and updating the end index according to the number
of the at least one first command; and

executing the commands corresponding to a plurality of un-executed command indices recorded in the command index register,
wherein the commands are stored in corresponding command transient units among the command transient units of the command
queue register.

US Pat. No. 9,983,805

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module has a plurality of physical erasing units, each physical erasing unit among the physical erasing units has a plurality of physical programming units, the memory management method comprising:recording a valid data count of each physical erasing unit among the physical erasing units;
identifying a plurality of first physical erasing units among the physical erasing units, wherein the valid data count of each first physical erasing unit among the first physical erasing units is between a first predetermined value and a second predetermined value; and
selecting a second physical erasing unit from the first physical erasing units if a number of the first physical erasing units meets a predetermined condition, copying a plurality of valid data in the second physical erasing unit to a third physical erasing unit among the physical erasing units, and performing an erasing operation for the second physical erasing unit.

US Pat. No. 9,946,661

COMMAND EXECUTING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A command executing method for a memory storage apparatus, the command executing method comprising:grouping a plurality of logical addresses corresponding to the memory storage apparatus into a plurality of logical address groups;
assigning a plurality of keys to the logical address groups respectively, wherein each of the keys is assigned to one logical address group among the logical address groups;
receiving a write command and write data corresponding to the write command from a host system and temporarily storing the write data into a buffer memory, wherein the write data includes a plurality of sector data, the write command indicates writing the plurality of sector data into a plurality of target logical addresses among the logical addresses and the target logical addresses belong to at least two different logical address groups among the logical address groups; and
executing the write command, enabling a direct memory access of the buffer memory once to transfer the write data from the buffer memory to a rewritable non-volatile memory module of the memory storage apparatus, determining and loading the keys corresponding to the at least two different logical address groups, and during the direct memory access:
identifying each of the target logical addresses storing each of the plurality of sector data in the transferred write data and one of the at least two different logical address groups that each of the target logical addresses belong to, and
encrypting the plurality of sector data in the transferred write data by an encryption/decryption circuit with the keys corresponding to the at least two different logical address groups of the target logical addresses in during the direct memory access of transferring the write data from the buffer memory to the rewritable non-volatile memory module.

US Pat. No. 9,880,742

VALID DATA MERGING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A valid data merging method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module
has a plurality of physical erasing units, each of the physical erasing units has a plurality of physical programming units,
a plurality of logical address-physical address mapping tables are stored in the rewritable non-volatile memory module to
record mapping information between a plurality of logical addresses and the physical programming units, the valid data merging
method comprising:
selecting a first physical erasing unit from the physical erasing units;
loading at least one first logical address-physical address mapping table among the logical address-physical address mapping
tables from the rewritable non-volatile memory module according to a physical address-logical address mapping table which
is not one of the plurality of logical address-physical address mapping tables;

updating the at least one first logical address-physical address mapping table according to the physical address-logical address
mapping table;

identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table
and the at least one first logical address-physical address mapping table;

storing the at least one first logical address-physical address mapping table back to the rewritable non-volatile memory module;
copying the identified valid data from the first physical erasing unit to a second physical erasing unit among the physical
erasing units; and

performing an erasing operation to the first physical erasing unit.

US Pat. No. 9,772,797

BUFFER MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A buffer memory management method for a buffer memory of a memory storage device having a rewritable non-volatile memory
module, the buffer memory management method comprising:
allocating a first zone and a second zone in the buffer memory, wherein the first zone and the second zone respectively has
a plurality of continuous buffer units, and at least a portion of the buffer units in the first zone and the second zone are
stored with a plurality of logical address-physical address tables;

performing a restore operation on the buffer units in the first zone to restore the logical address-physical address mapping
tables stored in the first zone to the rewritable non-volatile memory module;

receiving a first write command from a host system, wherein the first write command instructs writing first data into a first
logical address and a first logical address-physical address mapping table to which the first logical address belongs is temporarily
stored in a first buffer unit among the buffer units in the first zone;

writing the first data into the rewritable non-volatile memory module, copying the first logical address-physical address
mapping table of the first zone to a second buffer unit among the buffer units in the second zone; and

updating the first logical address-physical address mapping table temporarily stored in the second buffer unit in the second
zone.

US Pat. No. 9,703,698

DATA WRITING METHOD, MEMORY CONTROLLER AND MEMORY STORAGE APPARATUS

PHISON ELECTRONICS CORP.,...

1. A data writing method, for writing data into a physical erasing unit comprising a plurality of memory cells, a plurality
of word lines, and a plurality of bit lines, wherein each of the memory cells electrically connected to one of the word lines
and one of the bit lines, the memory cells constitute a plurality of physical programming units comprising a plurality of
lower physical programming units and a plurality of upper physical programming units, and a speed of writing data into the
lower physical programming units is higher than a speed of writing data into the upper physical programming units, the data
writing method comprising:
dividing the data into a plurality of information frames in a unit of one physical programming unit, wherein the number of
the information frames is smaller than the number of the physical programming units of the physical erasing unit; and

executing a first programming operation or a second programming operation to program the information frames into the memory
cells connected to at least one first word line,

wherein the first programming operation programs the information frames into the memory cells connected to the at least one
first word line by filling the lower physical programming units with the information frames and then writing the rest of the
information frames to the upper physical programming units,

wherein the second programming operation programs the information frames into the lower and upper physical programming units
of the memory cells connected to the at least one first word line sequentially and then programs an auxiliary pattern into
the memory cells connected to at least one second word line, wherein the auxiliary pattern is invalid data,

wherein, in the second programming operation, the at least one second word line is adjacent to the at least one first word
line, the at least one first word line is not adjacent to a third word line, and a storage state of the memory cells on the
third word line is an erasing state.

US Pat. No. 10,310,739

MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE

PHISON ELECTRONICS CORP.,...

1. A memory management method for a rewritable non-volatile memory module having a plurality of physical erasing units, the memory management method comprising:receiving a write command from a host system;
obtaining a valid data parameter based on a valid data amount of valid data stored in at least a part of the physical erasing units;
obtaining a first threshold value and a second threshold value based on the valid data parameter;
obtaining a first determination parameter based on a number of a plurality of first physical erasing units among the physical erasing units, wherein the first physical erasing units are programmed for storing data by using a single-page programming mode, and each memory cell of a physical erasing unit programmed by using the single-page programming mode stores one data bit;
performing a garbage collection operation if the first determination parameter is greater than the first threshold value;
obtaining a second determination parameter based on a number of a plurality of second physical erasing units among the physical erasing units, wherein the second physical erasing units are not to be stored data; and
if the second determination parameter is less than the second threshold value, programming data corresponding to the write command into a third physical erasing unit among the second physical erasing units by using a multi-page programming mode, wherein each memory cell of a physical erasing unit programmed by using the multi-page programming mode stores a plurality of data bits.