US Pat. No. 10,204,890

SUBSTRATE FOR SYSTEM IN PACKAGE (SIP) DEVICES

Octavo Systems LLC, Aust...

1. A package, comprising:a substrate containing one or more conductive layers, wherein said one or more conductive layers are connected to one or more device wire bond pads on a surface of said substrate using at least one via of a plurality of vias,
wherein said substrate comprises a plurality of configuration pads on said surface of said substrate arranged in at least one array and connected to said one or more conductive layers with one or more vias of said plurality of vias;
a plurality of circuits with external connectors assembled on said surface of said substrate using said one or more device wire bond pads;
wherein at least one device wire bond pad of said one or more device wire bond pads is electrically connected to at least one of said plurality of configuration pads through said one or more conductive layers of said substrate; and
one or more bond wires interconnecting portions of said plurality of circuits using two or more of said configuration pads,
wherein said plurality of circuits, said substrate, and said bond wires are contained within the package.

US Pat. No. 10,470,294

REDUCTION OF PASSIVE COMPONENTS IN SYSTEM-IN-PACKAGE DEVICES

OCTAVO SYSTEMS LLC, Aust...

1. A method for designing a System-in-Package (SiP), comprising:selecting a plurality of active components for use in an SiP design;
determining the number of and capacitance values for a first type of capacitors from an associated data sheet for each of said plurality of active components, wherein said data sheet includes information identifying the recommended number of capacitors and capacitive values to be used with each active component of said plurality of active components for normal operating conditions;
determining the number of and capacitance values for a second type of capacitors from said associated data sheet; and
arranging and operatively interconnecting said plurality of active components for said SiP design on a SiP substrate and operatively interconnecting said first and second types of capacitors on said SiP substrate to said plurality of active components,wherein the arranged number of said first type of capacitors included in said SiP design is less than the number of capacitors of said first type determined from said associated data sheet for each active component of said plurality of active components.

US Pat. No. 10,714,430

EMI SHIELD FOR MOLDED PACKAGES

OCTAVO SYSTEMS LLC, Suga...

1. A packaged integrated circuit device encapsulated using liquid encapsulant during packaging, the packaged integrated circuit device comprising:a substrate;
a radiation-generating component disposed on the substrate; and
an electromagnetic radiation blocking element comprising (i) one or more openings and (ii) a flap disposed over at least one of said one or more openings, wherein
the electromagnetic radiation blocking element is mounted over the radiation-generating component, and
a space between the electromagnetic radiation blocking element and the radiation-generating component is filled with the liquid encapsulant during the packaging,
wherein the radiation-generating component is connected to one or more components disposed on the substrate via at least one of said one or more openings.

US Pat. No. 11,032,910

SYSTEM-IN-PACKAGE DEVICE BALL MAP AND LAYOUT OPTIMIZATION

OCTAVO SYSTEMS LLC, Suga...

1. A system, comprising:a System-in-Package (SiP) including a SiP substrate, a plurality of SiP electronic components within the SiP, a plurality of internal electrical connections for connecting between said plurality of SiP electronic components, and an array of connectors formed on a bottom surface of said SiP substrate;
a printed circuit board (PCB), wherein said PCB comprises a top layer, a ground layer, and a power layer, wherein said top layer comprises a plurality of escape traces on a top surface of said PCB, and wherein said SiP is mounted on said top surface of said PCB; and
a plurality of electronic components mounted on said top surface of said PCB,
wherein at least one of said plurality of electronic components is electrically connected to at least one of said plurality of escape traces, and
wherein at least one of said plurality of SiP electronic components is electrically connected to at least one of said plurality of escape traces using said array of connectors.

US Pat. No. 10,867,979

CIRCUIT MOUNTING STRUCTURE AND LEAD FRAME FOR SYSTEM IN PACKAGE (SIP) DEVICES

OCTAVO SYSTEMS LLC, Suga...

1. A circuit mounting structure, the circuit mounting structure comprising:a plurality of mounting pads for devices;
a plurality of leads; and
one or more interconnection rails having a part disposed between at least one of said plurality of mounting pads and at least one of said plurality of leads, wherein
said one or more interconnection rails are electrically isolated from said plurality of mounting pads and said plurality of leads.