US Pat. No. 9,210,400

METHOD AND IMAGE PROCESSING DEVICE FOR ADJUSTING STEREO IMAGE

Novatek Microelectronics ...

1. An adjusting method for adjusting a stereo image on an image processing device, the adjusting method comprising:
obtaining a disparity map between a first image and a second image, wherein a viewing angle of the first image is different
from a viewing angle of the second image, and the disparity map comprises a plurality of disparity values;

dividing the disparity map into a plurality of layers according to the disparity values, wherein the layers correspond to
a plurality of first layers of the first image and a plurality of second layers of the second image;

generating a first difference according to a displacement of a pixel of an ith first layer of the first layers in an x direction and a displacement of a pixel of an ith second layer of the second layers in the x direction, and generating a first cost according to the first difference, wherein
i is a positive integer;

generating a second cost according to a difference between the displacement of the pixel of the ith first layer in the x direction and a displacement of a pixel of a jth first layer of the first layers in the x direction, and a difference between the displacement of the pixel of the ith second layer in the x direction and a displacement of a pixel of a jth second layer of the second layers in the x direction, wherein j is a positive integer different from i;

executing an optimization algorithm at least according to the first cost and the second cost to obtain the displacement of
the pixel of the ith first layer in the x direction and the displacement of the pixel of the ith second layer in the x direction; and

adjusting a position of the pixel of the ith first layer according to the displacement of the pixel of the ith first layer in the x direction and adjusting a position of the pixel of the ith second layer according to the displacement of the pixel of the ith second layer in the x direction.

US Pat. No. 9,396,695

SOURCE DRIVER AND METHOD FOR DRIVING DISPLAY DEVICE

Novatek Microelectronics ...

1. A source driver for driving a display device, comprising: a first drive channel circuit, configured for receiving a first
pixel data and a first reference voltage group, for driving the display device; a voltage controller, configured for receiving
a voltage command during a line data transmitting period, a horizontal blanking period or a vertical blanking period for generating
a first reference voltage configuration data, wherein the voltage controller updates the first reference voltage configuration
data during a specific period according to the voltage command; and a first programmable voltage buffer unit, coupled to the
voltage controller and the first drive channel circuit, configured for receiving the first reference voltage configuration
data, for applying the first reference voltage group to the first drive channel circuit, wherein the voltage controller further
generates a second reference voltage configuration data according to the voltage command, the source driver further comprises:
a second drive channel circuit, configured for receiving a second pixel data and a second reference voltage group, for driving
the display device; and a second programmable voltage buffer unit, coupled to the voltage controller and the second drive
channel circuit, configured for receiving the second reference voltage configuration data, for applying the second reference
voltage group to the second drive channel circuit.

US Pat. No. 9,472,156

METHOD AND APPARATUS FOR DRIVING A DISPLAY DEVICE

NOVATEK Microelectronics ...

1. A gamma voltage generator of a display driving device, comprising:
a first reference voltage generator;
a switch coupled to the first reference voltage generator;
a plurality of resistors connected in serial and coupled to the switch; and
a modulation resistor coupled between the first reference voltage generator and the switch;
wherein the switch is connected between the first reference voltage generator and an input terminal of the plurality of resistors.

US Pat. No. 9,389,738

TOUCHING APPARATUS AND TOUCHING DETECTING METHOD THEREOF

Novatek Microelectronics ...

1. A touching detecting method for a touch panel having a plurality of touching rows and a plurality of touching columns,
the method comprises:
performing a mutual-capacitor touching detection and a self-capacitor touching detection alternatingly to the touch panel
for obtaining a mutual-capacitor detection result and a self-capacitor detection result, respectively;

obtaining position information of at least one touch point on the touch panel by performing an operation based on the mutual-capacitor
detection result and the self-capacitor detection result;

determining whether none of absolute values of the plurality of mutual-capacitor capacitance variations included in the mutual-capacitor
detection result falls within an invalid detecting range after the step of performing the mutual-capacitor touching detection
is completed;

performing the mutual-capacitor touching detection continuously merely when none of the absolute values of the plurality of
mutual-capacitor capacitance variations falls within the invalid detecting range; and

performing the self-capacitor touching detection merely when at least one of the absolute values of the plurality of mutual-capacitor
capacitance variations falls within the invalid detecting range.

US Pat. No. 9,384,704

LIQUID CRYSTAL DISPLAY AND GATE DRIVER THEREOF

NOVATEK MICROELECTRONICS ...

1. A gate driver, comprising:
a first output unit;
a second output unit;
a first counter for counting a clock to control the first output unit to output a plurality of odd gate driving signals according
to a first start signal and a polarity signal;

a second counter for counting the clock to control the second output unit to output a plurality of even gate driving signals
according to a second start signal and the polarity signal; and

a multiplex unit for selectively outputting the polarity signal to the first counter or the second counter.

US Pat. No. 9,356,584

LEVEL SHIFTER

NOVATEK Microelectronics ...

1. A level shifter, for high-speed level shifting, comprising:
a first P-channel transistor, comprising a gate, a drain and a source, the gate coupled to the drain, the source coupled to
a system voltage;

a second P-channel transistor, comprising a gate, a drain and a source, the gate coupled to the gate of the first P-channel
transistor, the source coupled to the system voltage;

a first N-channel transistor, comprising a gate, a drain and a source, the drain directly connected to the drain of the first
P-channel transistor, the source coupled to a ground level;

a second N-channel transistor, comprising a gate, a drain and a source, the drain directly connected to the drain of the second
P-channel transistor, the source coupled to a ground level; and

a first switch, coupled between the ground level and the sources of the first N-channel transistor and the second N-channel
transistor;

wherein the first N-channel transistor and the second N-channel transistor are low threshold voltage transistor or native
transistors.

US Pat. No. 9,325,054

POWER SUPPLY CIRCUIT FOR ANTENNA, ANTENNA CONTROL SYSTEM, AND DIGITAL COMMUNICATION DEVICE

Novatek Microelectronics ...

1. A power supply circuit, adapted to supply electric power to an antenna, the power supply circuit comprising:
a power management circuit, coupled between a power input terminal and a power output terminal; and
a pin, coupled to the power management circuit, wherein
in a first mode, wherein the pin receives a mode control signal and provides the mode control signal to the power management
circuit such that the power management circuit determines to deliver or not deliver electric power of a power source from
the power input terminal to the power output terminal according to the mode control signal, and

in a second mode, the pin stops receiving the mode control signal and provides a detection signal indicating whether an overload
occurs.

US Pat. No. 9,343,029

GATE DRIVING CIRCUIT AND RELATED LCD DEVICE CAPABLE OF SEPARATING TIME FOR EACH CHANNEL TO TURN ON THIN FILM TRANSISTOR

NOVATEK Microelectronics ...

1. A gate driving circuit for a liquid crystal display (LCD) device, the LCD device comprising a plurality of channels, the
gate driving circuit comprising:
a shift register module, for generating a plurality of scan signals corresponding to the plurality of channels according to
a start signal and a clock signal;

a plurality of logic circuits, each corresponding to a channel of the plurality of channels, for outputting a driving signal
to the channel according to a scan signal of the plurality of scan signals and a shutdown indication signal and outputting
the shutdown indication signal; and

a plurality of shaping and delay units, each of at least one of which is coupled between two of the logic circuits of the
plurality of logic circuits corresponding to two neighboring ones of the channels, for shaping and delaying the shutdown indication
signal outputted by one of the two logic circuits and providing the shaped and delayed shutdown indication signal to the other
one of the two logic circuits, wherein when the shaping and delay unit performs the shaping and delaying, the shaping and
delay unit does not refer to any signal related to a magnitude of the driving signal output by the one of the two logic circuits.

US Pat. No. 9,311,870

DRIVING APPARATUS AND DISPLAY PANEL

Novatek Microelectronics ...

1. A display panel, comprising:
M*2N pixels, arranged as an M*2N matrix, wherein M and N are positive integers;
N data driving units;
2M scan lines, each of the scan lines being electrically coupled to N pixels in the same row; and
2N data lines, each of the data lines being electrically coupled to pixels arranged in a plurality of odd rows of a column
adjacent to one side of the each of the data lines and a plurality of even rows of another column adjacent to another side
of the each of the data lines, wherein only one column of pixels are located between adjacent data lines, and the pixels arranged
in the same column are alternately electrically coupled to opposite data lines of the adjacent data lines, wherein each of
the data driving units is electrically coupled to two of the data lines that are not adjacent to each other.

US Pat. No. 9,239,369

METHOD AND SYSTEM FOR SELECTING BASE STATIONS TO POSITION MOBILE DEVICE

NOVATEK Microelectronics ...

1. A method for selecting a plurality of base stations to position a mobile device comprising:
forming y base station combinations from n base stations taken r base stations at a time, where y=Crn, and taking the y base station combinations as a plurality of base station sets, each base station set corresponding to a
respective distance matrix comprising a plurality of vectors each between the mobile device and a respective one of base stations
in the base station set;

utilizing a first artificial neural network (ANN) unit to select a predefined number of base station sets from the plurality
of base station sets according to a plurality of distance matrixes corresponding to the plurality of base station sets; and

utilizing a second ANN unit to position the mobile device according to the predefined number of base station sets.

US Pat. No. 9,143,272

SERIAL INTERFACE PACKET INFORMATION DETECTION AND CONTROL METHOD AND RECEIVER THEREOF

NOVATEK Microelectronics ...

1. A serial interface packet information detection and control method for a Mobile Industry Processor Interface (MIPI), the
serial interface packet information detection and control method comprising:
receiving and decoding a packet;
generating a control signal according to a packet information of a header of the packet; and
disabling a function register according to the control signal.

US Pat. No. 9,078,301

OUTPUT STAGE CIRCUIT FOR GATE DRIVING CIRCUIT IN LCD

NOVATEK Microelectronics ...

1. An output stage circuit for a gate driving circuit in a liquid crystal display (LCD), the output stage circuit comprising:
a charge unit, coupled to a gate line of the gate driving circuit for charging the gate line with a first supply voltage;
a first discharge unit, coupled to the gate line of the gate driving circuit for discharging the gate line from the first
supply voltage to a specific voltage between the first supply voltage and a second supply voltage;

a second discharge unit, coupled to the gate line of the gate driving circuit for discharging the gate line from the specific
voltage to the second supply voltage; and

a control circuit for controlling the charge unit, the first and the second discharge units according to a timing controller
of the LCD.

US Pat. No. 9,468,064

LIGHT-EMITTING DIODE DRIVING CIRCUIT AND LIGHT-EMITTING APPARATUS THEREOF

Novatek Microelectronics ...

1. A light-emitting diode (LED) driving circuit, for driving an LED string, comprising:
a voltage providing unit, receiving a voltage setting signal and an input voltage to provide an emission driving voltage to
a first terminal of the LED string;

a voltage setting unit, coupled to the voltage providing unit and receiving an emission feedback signal to provide the voltage
setting signal;

a current feedback unit, coupled to the voltage setting unit to provide the emission feedback signal, coupled to a second
terminal of the LED string and sequentially receiving a plurality of current setting voltages to sequentially set a driving
current flowing through the LED string according to the current setting voltages; and

a current dithering unit, receiving a backlight control signal to sequentially provide the current setting voltages, wherein
the current dithering unit comprises:

a dither control unit, receiving the backlight control signal and having a plurality of current setting values corresponding
to a plurality of backlight brightness values and comparing a set brightness value of the backlight control signal with the
backlight brightness values, so as to determine to continuously output one of the current setting values within a backlight
setting period, or alternately output two of the current setting values within the backlight setting period; and

a digital-to-analog converter, coupled to the dither control unit to convert the current setting values into the current setting
voltages to provide the current setting voltages.

US Pat. No. 9,311,844

SOURCE DRIVER AND METHOD TO REDUCE PEAK CURRENT THEREIN

Novatek Microelectronics ...

1. A source driver, comprising:
a level shifter;
a latch circuit, latching at least one current bit-data, wherein the latch circuit selects and outputs the at least one current
bit-data to an input terminal of the level shifter to replace at least one previous bit-data when the at least one current
bit-data is not a complement of the at least one previous bit-data, and the latch circuit selects and outputs the at least
one previous bit-data to the input terminal of the level shifter when the at least one current bit-data is the complement
of the at least one previous bit-data; and

a digital-to-analog converter (DAC) circuit, coupled to an output terminal of the level shifter, wherein the DAC circuit outputs
a voltage corresponding to output data of the level shifter when the at least one current bit-data is not a complement of
the at least one previous bit-data, and the DAC circuit outputs a voltage corresponding to the at least one current bit-data
when the at least one current bit-data is the complement of the at least one previous bit-data.

US Pat. No. 9,349,346

DISPLAY APPARATUS AND METHOD AND COLOR TEMPERATURE COMPENSATION APPARATUS THEREOF

Novatek Microelectronics ...

1. A color temperature compensation apparatus comprising:
a compensation table, recording a relationship between a plurality of compensation values and each of a plurality of gray-levels,
wherein the relationship is established based on a plurality of color temperature compensation curves; and

a controller coupled to the compensation table, generating a plurality of compensation values by referring to the compensation
table according to a gray-level of each of a plurality of image data and a reference color temperature, and calculating each
of a plurality of compensated image data according to the compensation values,

wherein, the color temperature compensation curves respectively correspond to a plurality of color temperatures.

US Pat. No. 9,298,655

BUS DETECTION AND CONTROL METHOD AND BUS DETECTION AND CONTROL DEVICE AND MOBILE INDUSTRY PROCESSOR INTERFACE SYSTEM THEREOF

NOVATEK Microelectronics ...

19. A mobile industry processor interface (MIPI) system, comprising:
a slave;
a mobile industry processor interface bus;
a host, coupled to the slave with the mobile industry processor interface bus; and
a bus detection and control device, comprising:
a bus controller, for detecting statuses of the mobile industry processor interface bus and the host, to output a control
signal; and

a multiplexer, comprising a first input terminal receiving a predefined signal corresponding to an initial state and a second
input terminal receiving a transmission signal outputted to the mobile industry processor interface bus by the host, for outputting
one of the predefined signal corresponding to the initial state and the transmission signal outputted to the mobile industry
processor interface bus by the host as a reception signal of the slave according to the control signal.

US Pat. No. 9,279,831

PROBE CARD AND FABRICATING METHOD THEREOF

NOVATEK Microelectronics ...

1. A probe card, comprising:
a circuit board, wherein a slot is formed on the circuit board; and
an integrated circuit (IC) test interface, comprising:
a reinforcement plate, disposed on the slot of the circuit board;
a first probe assembly, disposed on a terminal of the circuit board and a terminal of the reinforcement plate, and
a second probe assembly, disposed on another terminal of the circuit board and another terminal of the reinforcement plate,
wherein

the first probe assembly and the second probe assembly are separated to allow being independently assembled to or disassembled
from the circuit board, and

each of the first probe assembly and the second probe assembly, comprising:
a probe base, disposed on the circuit board;
a plurality of needles, which are cantilever needles; and
a covering layer, for covering the plurality of needles, and fixed on a surface of the probe base.

US Pat. No. 9,218,651

IMAGE PROCESSING METHOD FOR DYNAMICALLY ADJUSTING LUMINANCE AND CONTRAST OF IMAGE

NOVATEK (SHANGHAI) CO., L...

1. An image processing method for adjusting the luminance and contrast of input image data including a plurality of first
pixel values, comprising:
generating luminance image data including a plurality of second pixel values from the input image data with using local spatial
luminance statistics on the first pixel values included in the input image data;

from a preset mapping curve group comprising a plurality of smooth mapping curves, selecting a corresponding smooth mapping
curve for each of the second pixel values based on a difference between a respective first pixel value and a generated second
pixel value corresponding to said respective first pixel value; and

generating adjusted image data including a plurality of adjusted pixel values by adjusting the plurality of second pixel values
included in the luminance image data using the selected smooth mapping curve so that a dynamic range of each of the adjusted
pixel values included in the adjusted image data is gradually decreased or increased.

US Pat. No. 9,058,791

IMAGE PROCESSING DEVICE

NOVATEK MICROELECTRONICS ...

1. An image processing device, comprising:
an image processing circuit, for receiving a full-resolution 3D input image and outputting a current half-resolution 3D image;
a first up-sampler selectively coupled to the image processing circuit for up-sampling the current half-resolution 3D image
to obtain a current full-resolution 3D image;

an over-driving circuit coupled to the first up-sampler for outputting a first full-resolution 3D output image;
a down-sampler selectively coupled to the over-driving circuit for down-sampling the first full-resolution 3D output image
to obtain a previous half-resolution 3D image and input the previous half-resolution 3D image to a memory; and

a second up-sampler selectively coupled to the memory for up-sampling the previous half-resolution 3D image to obtain a previous
full-resolution 3D image;

wherein, the over-driving circuit is further coupled to the second up-sampler for outputting a second full-resolution 3D output
image according to the current and the previous full-resolution 3D images.

US Pat. No. 9,325,309

GATE DRIVING CIRCUIT AND DRIVING METHOD THEREOF

Novatek Microelectronics ...

18. A driving method of a gate driving circuit, comprising:
generating a plurality of first control signals and a plurality of second control signals according to a gate driver start
pulse; and

determining a plurality of first gate channels of a first gate channel set to share a first level shifter in time-division
according to the first control signals and the second control signals, so as to generate a plurality of gate driving signals.

US Pat. No. 9,241,148

DISPARITY CALCULATING METHOD AND STEREO MATCHING DEVICE THEREOF

NOVATEK Microelectronics ...

1. A disparity calculating method for a stereo-matching device, used for calculating a plurality of disparities between a
plurality of pixels of a first image-block and of a second image-block in a current frame, the disparity calculating method
comprising:
generating an energy matrix according to the first image-block and the second image-block, wherein the energy matrix comprises
a plurality of energies of a plurality of pixels corresponding to a plurality of disparity candidates;

setting the energy corresponding to a starting pixel of the plurality of pixels and a specified disparity candidate of the
plurality of disparity candidates as a first predetermined value and setting the energies corresponding to the starting pixel
and remaining disparity candidates of the plurality of disparity candidates as a second predetermined value, wherein the second
predetermined value is greater than the first predetermined value;

generating a path matrix according to the energy matrix; and
determining the plurality of disparities of the plurality of pixels sequentially from an ending pixel of the plurality of
pixels, wherein the disparity of the ending pixel is set as a third predetermined value.

US Pat. No. 9,491,724

DATA TRANSMISSION SYSTEM AND METHOD WITH FEEDBACK REGARDING A DECODING CONDITION

NOVATEK Microelectronics ...

1. A data transmission system utilized in a Mobile Industry Processor Interface (MIPI) comprising:
a master device comprising:
a control module for generating, according to a feedback signal, a control signal according to which a transmission mode is
thereby determined; and

a packet encoding module coupled to the control module for encoding an original packet to be a transmission packet according
to the original packet and the control signal, and processing a transmission operation under the determined transmission mode;
and

a slave device, for generating the feedback signal, comprising:
a packet decoding module for decoding the transmission packet to be the original packet or a related display device signal
corresponding to the original packet; and

a feedback module coupled to the packet decoding module, for generating a synchronizing signal when a decoding condition of
the packet decoding module indicates that the transmission packet is correctly received or decoded, and for not generating
the synchronizing signal when the decoding condition indicates that the transmission packet is not correctly received or decoded;

wherein the feedback signal indicates whether the synchronizing signal is generated.

US Pat. No. 9,368,570

INTEGRATED CIRCUIT OF DRIVING DEVICE WITH DIFFERENT OPERATING VOLTAGES

NOVATEK Microelectronics ...

1. An integrated circuit for a driving device, the integrate circuit comprising:
a substrate comprising a high-voltage area and a low-voltage area;
a plurality of first trenches, formed in the high-voltage area;
a plurality of first isolations, formed in the plurality of first trenches of the high-voltage area;
a plurality of second trenches, formed in the low-voltage area; and
a plurality of second isolations, formed in the plurality of second trenches of the low-voltage area;
wherein a depth difference exists between each of the plurality of first trenches and each of the plurality of second trenches;
wherein each of the plurality of first isolations is a first height higher than a surface of the substrate, each of the plurality
of second isolations is a second height higher than the surface of the substrate, and the first height and the second height
are different.

US Pat. No. 9,335,842

TOUCH PANEL AND DISPLAY APPARATUS

Novatek Microelectronics ...

1. A touch panel, comprising:
a substrate;
a plurality of first sensing lines, disposed on the substrate in parallel with a first direction;
a plurality of second sensing lines, disposed on the substrate in parallel with a second direction, wherein the first sensing
lines intersect the second sensing lines to define a plurality of meshes; and

a plurality of insulation pads, disposed only at where the first sensing lines intersect the second sensing lines to insulate
the first sensing lines from the second sensing lines,

wherein a plurality of first extending portions are extended from the first sensing lines towards the meshes, and a plurality
of second extending portion are extended from the second sensing lines towards the meshes, wherein the first extending portions
and the second extending portions are distributed next to each other in the meshes.

US Pat. No. 9,236,360

IC CHIP PACKAGE AND CHIP-ON-GLASS STRUCTURE USING THE SAME

NOVATEK MICROELECTRONICS ...

1. An IC chip package, comprising:
an IC chip having a circuit surface; and
a plurality of copper (Cu) bumps whose bottom surfaces directly contact the circuit surface, wherein a surface roughness of
the Cu bumps is in a range of 0.05 ?m to 2 ?m.

US Pat. No. 9,230,495

SELF-DETECTION CHARGE SHARING MODULE

NOVATEK Microelectronics ...

1. A self-detection charge sharing module, for a liquid crystal display device, comprising:
at least one detecting unit, for detecting a plurality of input voltages of a plurality of operational amplifiers driving
a plurality of data lines and a plurality of output voltages of the plurality of data lines, to generate a plurality of detecting
results; and

at least one charge sharing unit, for conducting connection between at least one corresponding first data line and at least
one corresponding second data line among the plurality of data line when the plurality of detecting results indicate at least
one first input voltage and at least one second input voltage among the plurality of input voltage have opposite voltage variation
directions and vary toward each other;

wherein the at least one first input voltage and the at least one second input voltage maintain respective polarities.

US Pat. No. 9,395,728

CHARGE PUMP DEVICE AND DRIVING CAPABILITY ADJUSTMENT METHOD THEREOF

NOVATEK Microelectronics ...

1. A driving capability adjustment method, for a charge pump device, comprising:
setting a driving capability for driving the charge pump device according to whether an output voltage of the charge pump
device reaches a target voltage in a startup period; and

performing following procedure during an operation period after the startup period:
(i)setting the driving capability according to whether the output voltage does not maintain at the target voltage;
if the output voltage does not maintain at the target voltage, after the driving capability is set in step (i), then performing
step (ii): setting the driving capability according to whether the output voltage reaches the target voltage; and

if the output voltage reaches the target voltage, after the driving capability is set in step (ii), restart the procedure
to perform step (i);

wherein the step (i) comprises:
setting the driving capability as a specific driving capability if the output voltage does not maintain at the target voltage;
wherein the step (ii) comprises:
decreasing the driving capability to be lower than the specific driving capability after utilizing the specific capability
to drive the output voltage to reach the target voltage;

wherein a magnitude of the decreased driving capability is determined according to the number of previous times the output
voltage has not maintained at the target voltage.

US Pat. No. 9,392,180

PARTIAL LENS SHADING COMPENSATION METHOD

NOVATEK MICROELECTRONICS ...

1. A partial lens shading compensation method, comprising:
dividing, from the inside towards the outside of an image area, the image area into a plurality of partial areas, the partial
areas being centered on an optical center of the image area, the partial areas including a first partial area, a second partial
area, and a third partial area;

determining, when a target pixel is identified as being located in the first partial area, a first compensation gain according
to the position of the target pixel with reference to the optical center;

determining, when the target pixel is identified as being located in the second partial area, a second compensation gain according
to the position of the target pixel with reference to the optical center;

determining, when the target pixel is identified as being located in the third partial area, a third compensation gain according
to the position of the target pixel with reference to the optical center;

determining a fourth compensation gain according to the position of the target pixel with reference to the optical center;
and

determining a mixed compensation value according to the sum of the first compensation gain, the second compensation gain,
the third compensation gain, and the fourth compensation gain, so as to compensate the target pixel;

wherein within the first partial area, an absolute value of the first compensation gain monotonically varies or oscillates
toward the border of the first partial area at which it becomes zero.

US Pat. No. 9,467,734

STORING METHOD AND PROCESSING DEVICE THEREOF

NOVATEK Microelectronics ...

1. A storing method, for storing data in a storage device of a video recording system, the storing method comprising:
sequentially storing at least one first media content into at least one first fragment of the storage device, and storing
corresponding at least one first metadata into a first metadata writing storage window of the storage device, wherein the
at least one first fragment is outside of a first metadata reserving storage window and the first metadata writing storage
window of the storage device; and

when the storage device reaches a storage limit and at least one second media content and corresponding at least one second
metadata are intended continuously to be stored in the storage device, converting the first metadata writing storage window
into a second metadata reserving storage window to reserve the at least one first metadata, and sequentially overwriting at
least one second fragment of the storage device with the at least one second media content and storing the corresponding at
least one second metadata into a second metadata writing storage window of the storage device, wherein the at least one second
fragment is outside of the second metadata reserving storage window and the second metadata writing storage window;

wherein the first metadata writing storage window follows the first metadata reserving storage window, and the second metadata
writing storage window follows the second metadata reserving storage window.

US Pat. No. 9,449,568

LIQUID CRYSTAL DISPLAY MONITOR AND SOURCE DRIVER AND CONTROL METHOD THEREOF

NOVATEK Microelectronics ...

1. A liquid crystal display (LCD) monitor, comprising:
an LCD panel, for displaying a frame;
a timing controller, for generating a polarity control signal and a latch signal; and
a driving circuit, comprising a plurality of source drivers, a first reference voltage and a second reference voltage;
wherein each source driver of the plurality source drivers comprises:
a comparison circuit, for comparing a common electrode voltage with the first reference voltage and the second reference voltage,
to generate a comparison result;

an enabling circuit, coupled to the comparison circuit, for generating an enabling signal according to the comparison result,
a source driving signal and a reset signal;

a horizontal dot inversion control circuit, coupled to the enabling circuit, for generating a horizontal dot inversion control
signal according to the enabling signal; and

a polarity control circuit, coupled to the enabling circuit, for generating a polarity inversion control signal and the reset
signal according to the enabling signal, the polarity control signal and the latch signal;

wherein the driving circuit is configured to switch between a plurality of inversion driving methods according to a value
of the common electrode voltage, and a driving method is selected from the plurality of inversion driving methods when the
horizontal dot inversion control signal and the polarity inversion control signal are supplied to control the LCD panel according
to the comparison result;

wherein the first reference voltage is higher than the second reference voltage.

US Pat. No. 9,118,286

DC OFFSET CANCELLATION CIRCUIT

Novatek Microelectronics ...

1. A direct current (DC) offset cancellation circuit, comprising:
a first operational amplifier, comprising a first input transconductance stage, a second input transconductance stage and
an output stage, wherein an input terminal of the first input transconductance stage receives an input signal of the first
operational amplifier through a first input terminal of the first operational amplifier, and an output terminal of the output
stage outputs an output signal of the first operational amplifier through an output terminal of the first operational amplifier;
and

a feedback gain circuit, wherein an input terminal of the feedback gain circuit is coupled to the output terminal of the first
operational amplifier, and an output terminal of the feedback gain circuit is coupled to an input terminal of the second input
transconductance stage through a second input terminal of the first operational amplifier.

US Pat. No. 9,467,108

OPERATIONAL AMPLIFIER CIRCUIT AND METHOD FOR ENHANCING DRIVING CAPACITY THEREOF

Novatek Microelectronics ...

1. An operational amplifier circuit, comprising:
a pre-stage operational amplifier having a first input terminal and a second input terminal;
an output stage circuit having an output terminal coupled to the second input terminal of the pre-stage operational amplifier;
an output switch having an input terminal coupled to the output terminal of the output stage circuit and an output terminal;
and

an output stage operational amplifier having a detection circuit coupled to the input terminal and the output terminal of
the output switch.

US Pat. No. 9,112,453

OPERATIONAL AMPLIFIER CIRCUIT

Novatek Microelectronics ...

1. An operational amplifier circuit, comprising:
a main circuit, having an output terminal;
a compensation capacitor, having a first end connected to an internal node of the main circuit, and a second end connected
to the output terminal of the main circuit;

a power circuit, providing a current or a voltage as predetermined; and
a set of switches, connecting the power circuit to the compensation capacitor,
wherein when the main circuit is not in an output state, the set of switches is switched to allow the power circuit to provide
the current or the voltage to the compensation capacitor, and the compensation capacitor is not sensing a voltage at the output
terminal from the main circuit,

wherein when the main circuit is in the output state, the set of switches is switched to disconnect the power circuit from
the compensation capacitor and allow the main circuit to return to an output circuit state and operate normally.

US Pat. No. 9,653,031

MULTI-TYPE COMMON VOLTAGE DRIVING METHOD, COMMON VOLTAGE CONTROL APPARATUS, AND DISPLAY DRIVING CIRCUIT

NOVATEK MICROELECTRONICS ...

1. A multi-type common voltage driving method, adapted to drive a display, the multi-type driving method comprising:
providing a common voltage to a common electrode of the display for a sequence of common voltage switching time units to define
a reference voltage of the display,

wherein each of the common voltage switching time units has a plurality of different types of common voltage pattern periods,
and a time length of each of the common voltage pattern periods comprises at least one frame, wherein the display displays
at least one image during the at least one frame,

wherein in each of the common voltage pattern periods, the common voltage comprises either alternating current (AC) voltage
swings or direct current (DC) voltage level, wherein the common voltage is switched from one of the AC voltage swings and
the DC voltage level to another one of the AC voltage swings and the DC voltage level,

wherein during the different types of the common voltage pattern periods, the provided common voltage has different AC voltage
swings or different DC voltage levels, and

wherein in each of the common voltage switching time units, the different types of the common voltage pattern periods comprise:
a plurality of DC-type common voltage pattern periods, during which the provided common voltage has different DC voltage levels.

US Pat. No. 9,311,863

DIMMING METHOD AND DIMMING DEVICE FOR BACKLIGHT MODULE

Novatek Microelectronics ...

1. A dimming method for a backlight module, comprising:
according to a plurality of light distribution information of a plurality of light sources of the backlight module which are
corresponding to each of different positions of the display panel, respectively obtaining a plurality of light contribution
ratios of the light sources corresponding to the different positions of the display panel; and

according to the light contribution ratios corresponding to the different positions, respectively determining a needed intensity
of each of the light sources,

wherein, the step of determining the needed intensity of each of the light sources comprises:
(i) for each of the different positions of the display panel and while satisfying a target brightness value of the position,
respectively obtaining possible needed intensities of at least two selected light sources according to the light contribution
ratio obtained at the position; and

(ii) for each of the light sources, determining the needed intensity of the light source according to the possible needed
intensities of the light source respectively obtained for the different positions.

US Pat. No. 9,282,303

AUTOMATIC COLOR CORRECTION METHOD AND COLOR CORRECTION MODULE THEREOF

NOVATEK Microelectronics ...

1. An auto-color-correction method for an image capturing device, the auto-color-correction method comprises:
calculating a plurality color temperatures of a plurality of pixels in an image;
calculating a number of pixels of the plurality of pixels located in a first color temperature range as a first number and
a number of pixels of the plurality of pixels located in a second color temperature range as a second number;

generating a color temperature weight according to a relation between the first number and the second number; and
generating at least one correction parameter for image compensation according to the color temperature weight, at least one
first parameter corresponding to the first color temperature range and at least one second parameter corresponding to the
second color temperature range;

wherein the first color temperature range and the second colot temperature range are different.

US Pat. No. 9,240,157

TIMING CONTROLLER, SOURCE DRIVING DEVICE, PANEL DRIVING DEVICE, DISPLAY DEVICE AND DRIVING METHOD FOR REDUCING POWER CONSUMPTION THROUGH REDUCING STANDBY DURATIONS

NOVATEK Microelectronics ...

1. A source driving device comprising:
a plurality of source drivers, connected in series, comprising:
one or more cascade source drivers, comprising one or more first-type cascade source drivers, each first-type cascade source
driver, at different times from other first-type cascade source drivers, activated from power-off to power-up to enter a standby
state by a pulse signal generated by a previous source driver respectively, and triggered by a frame signal to receive corresponding
frame data from the frame signal after the activation;

wherein each of the source drivers other than the last source driver, after complete of receiving the corresponding frame
data, generates a pulse signal to activate the next source driver.

US Pat. No. 9,049,336

AUTO-DETECT METHOD FOR DETECTING IMAGE FORMAT AND PLAYBACK METHOD APPLYING THE SAME

NOVATEK MICROELECTRONICS ...

1. An auto-detect method for detecting a single-frame image format, comprising:
dividing a single-frame image into a plurality of macro-blocks;
dividing each of the macro-blocks into a plurality of sub-blocks;
generating a meta-block in each of the sub-blocks;
calculating a pixel luminance sum characteristic value for each of the meta-blocks;
calculating a first confidence of a left half and a right half of the single-frame image according to the pixel luminance
sum characteristic values;

calculating a second confidence of an upper half and a lower half of the single-frame image according to the pixel luminance
sum characteristic values; and

determining a format of the single-frame image according to the pixel luminance sum characteristic values, and the first confidence
and the second confidence of the single-frame image.

US Pat. No. 9,369,645

IMAGE SENSING APPARATUS AND BLACK LEVEL CONTROLLING METHOD THEREOF

Novatek Microelectronics ...

1. A black level controlling method of an image sensing apparatus at least having a pixel array which includes a plurality
of optical black pixels and a plurality of active pixels, and the black level controlling method comprising:
providing a conversion relationship between analog gain values and offset values;
converting an analog gain value into an analog offset value by using the conversion relationship between analog gain values
and offset values;

deciding whether to adjust the analog offset value according to a first optical black data corresponding to a first part of
the optical black pixels; and

calculating a digital data offset value according to a data corresponding a second part of the optical black pixels,
wherein deciding whether to adjust the analog offset value comprises:
a. determining whether the first optical black data is within a predetermined range and whether the analog offset value is
zero; and

b. adjusting the analog offset value when the first optical black data is not within the predetermined range or the analog
offset value is zero, obtaining optical black data corresponding to another part of the optical black pixels according to
the adjusted analog offset value to be used as the first optical black data, and repeating the step a again.

US Pat. No. 9,305,504

DISPLAY DEVICE AND LIQUID CRYSTAL DISPLAY PANEL HAVING A PLURALITY OF COMMON ELECTRODES

Novatek Microelectronics ...

1. A liquid crystal display panel, comprising:
a plurality of first common electrodes;
a plurality of second common electrodes, wherein the second common electrodes and the first common electrodes are electrically
independent from each other; and

a plurality of pixels, wherein a plurality of first pixels of the pixels are coupled to the first common electrodes, each
of the first pixels is coupled to a corresponding one of the first common electrodes, a plurality of second pixels of the
pixels are coupled to the second common electrodes, and each of the second pixels is coupled to a corresponding one of the
second common electrodes,

wherein the first common electrode of a pixel located on a ith data line and a jth scan line is directly coupled to the first
common electrode of a pixel located on a (i+1)th data line and a (j+1)th scan line through a first wire, and the first common
electrode of the pixel located on the (i+1)th data line and the (j+1)th scan line is directly coupled to the first common
electrode of a pixel located on the ith data line and a (j+2)th scan line through a second wire, wherein the first wire is
distinct from the second wire, and i and j are positive integers.

US Pat. No. 9,215,170

METHOD OF TRANSPORTING DATA WITH EMBEDDED CLOCK

Novatek Microelectronics ...

5. A method for driving a display device, comprising:
receiving a packet of coded data which has a header and an image data;
determining a coding information of the header to acquire a decoded data, wherein the coding information indicates whether
a part of bits of the image data are inverted or not; and

outputting the decoded data to drive the display device.

US Pat. No. 9,189,110

SENSING AND DRIVING APPARATUS, TOUCH SENSING SYSTEM, AND SENSING AND DRIVING METHOD

Novatek Microelectronics ...

1. A sensing and driving apparatus suitable for a sensing interface, the sensing and driving apparatus comprising:
a driving module, outputting a first reference signal and a second reference signal which have different polarities with each
other, and respectively transmitting the first reference signal and the second reference signal to a first driving line and
a second driving line of the sensing interface so as to accordingly generate a first sensing signal during a first period,
wherein the first driving line and the second driving line are extended along the same direction of the sensing interface;
and

a sensing unit, receiving the first sensing signal and detecting a change of the first sensing signal so as to generate a
sensing result accordingly,

wherein the first driving line receiving the first reference signal and the second driving line receiving the second reference
signal are two adjacent driving lines of the sensing interface extended along the same direction of the sensing interface.

US Pat. No. 9,076,374

DISPLAY DEVICE AND DRIVING METHOD APPLICABLE THERETO

NOVATEK MICROELECTRONICS ...

1. A driving method applicable to a display device including a plurality of display driving circuits, including:
synchronously receiving a start pulse and generating a synchronous timing signal by the display driving circuits;
delivering a first signal from a previous display driving circuit to a rear display driving circuit, so that the rear display
driving circuit accordingly detects and stores a signal reception delay denoting a delay between the synchronous timing signal
and the first signal received by the rear display driving circuit;

temporarily stopping receiving a system clock signal and temporarily stopping generating the synchronous timing signal by
the rear display driving circuit after storing the signal reception delay in the rear display driving circuit; and

delivering a second signal from the previous display driving circuit to the rear display driving circuit to wake up the rear
display driving circuit for preparing to receive a display data; wherein,

the rear display driving circuit receives the first signal from the previous display driving circuit;
the rear display driving circuit accordingly detects and stores the signal reception delay according to the received first
signal and the synchronous timing signal;

after the rear display driving circuit temporarily stops receiving the system clock signal and temporarily stops generating
the synchronous timing signal, the rear display driving circuit resumes receiving the system clock signal if the rear display
driving circuit receives the second signal;

the rear display driving circuit re-generates the synchronous timing signal according to the signal reception delay if the
rear display driving circuit receives a third signal from the previous display driving circuit; and

the rear display driving circuit receives a fourth signal from the previous display driving circuit for preparing to receive
the display data.

US Pat. No. 9,397,764

CARRIER FREQUENCY OFFSET CALIBRATION METHOD AND SYSTEM

Novatek Microelectronics ...

1. A carrier frequency offset calibration method, adapted to a carrier frequency offset calibration system to calibrate ca
ier frequency offsets of a transmission signal comprising a primary carrier and a secondary carrier, the method comprising:
analyzing a frequency of the transmission signal according to a known primary carrier frequency, a known secondary carrier
frequency, a primary feedback signal and a secondary feedback signal to obtain a primary carrier offset value and a secondary
carrier offset value, wherein the analyzing step comprises:

calibrating the frequency of the transmission signal according to the known primary carrier frequency, the known secondary
carrier frequency, the primary feedback signal and the secondary feedback signal to obtain a primary baseband signal and a
secondary baseband signal;

calculating carrier power levels of the primary baseband signal and the secondary baseband signal; and
calculating the primary carrier offset value of the primary baseband signal and the secondary carrier offset value of the
secondary baseband signal; and

determining whether to adjust the primary feedback signal and the secondary feedback signal according to a relationship between
the primary carrier offset value and the secondary carrier offset value, wherein the determining step comprises:

if an absolute value of the primary carrier offset value or an absolute value of the secondary carrier offset value is not
less than a frequency offset threshold, and if a sum of the primary carrier offset value and the known primary carrier frequency
is substantially equal to a sum of the secondary carrier offset value and the known secondary carrier frequency, adjusting
the primary feedback signal and the secondary feedback signal as the secondary carrier offset value.

US Pat. No. 9,077,505

MIPI SIGNAL RECEIVING APPARATUS AND METHOD

Novatek Microelectronics ...

1. A signal receiving apparatus, adapted to receiving a mobile industry processor interface (MIPI) signal, comprising:
a signal receiver, receiving a clock signal and receiving an original input data stream according to the clock signal to obtain
an input data stream;

a selector, having a first and a second output terminals, coupled to the signal receiver, and selecting to transmit the input
data stream to the first output terminal or the second output terminal according to a decoding error signal;

a decoding apparatus, coupled to the first output terminal of the selector and performing a decoding operation on the input
data stream received by the first output terminal of the selector so as to generate the decoding error signal; and

a byte boundary searcher, coupled to the second output terminal of the selector and performing a boundary searching operation
on the input data stream received by the second output terminal of the selector to generate byte tuning information,

wherein, the signal receiver adjusts the clock signal according to the byte tuning information to adjust the correspondingly
received input data stream, the byte boundary searcher generates the byte tuning information by comparing the input data stream
with byte data of each of a plurality of byte boundaries, and the byte data of the byte boundaries is formed by performing
byte shifts of different shift amounts on a byte data of a correct byte boundary.

US Pat. No. 9,229,519

SERIAL INTERFACE TRANSMITTING METHOD AND PERIPHERAL DEVICE CHIP

NOVATEK Microelectronics ...

1. A serial interface transmitting method utilized in a serial interface for connecting between a master controller and a
peripheral device, the serial interface transmitting method comprising:
receiving a saving power signal from the master controller, a peripheral clock source and a serial interface clock source
for generating a clock source selection result;

switching an operational mode of the peripheral device according to the clock source selection result; and
transmitting a datum to a peripheral device register or a serial interface register according to the saving power signal and
the operational mode;

wherein the datum is transmitted between the master controller, the serial interface and the peripheral device, and the master
controller further comprises a master controller clock source to synchronize with the peripheral clock source, and the peripheral
device and the master controller exchange the datum while synchronizing.

US Pat. No. 9,756,306

ARTIFACT REDUCTION METHOD AND APPARATUS AND IMAGE PROCESSING METHOD AND APPARATUS

Novatek Microelectronics ...

1. An artifact reduction method, comprising:
scaling down a resolution of each of at least one previous original image frame from a first resolution to a second resolution
to obtain at least one previous low-resolution image frame and storing the at least one previous low-resolution image frame
in a buffer unit;

scaling down a resolution of a current original image frame from the first resolution to the second resolution to obtain a
current low-resolution image frame, wherein the current original image frame and the current low-resolution image frame comprise
a first plurality of pixels and a second plurality of pixels, respectively;

performing an artifact detection to the current low-resolution image frame to obtain a plurality of low-resolution weights
in accordance with a relation of the current low-resolution image frame and the at least one previous low-resolution image
frame retrieved from the buffer unit, wherein the low-resolution weights are respectively corresponding to the second plurality
of pixels in the current low-resolution image frame, and the step of performing the artifact detection to the current low-resolution
image frame to obtain the low-resolution weights comprises:

for each pixel in the second plurality of pixels of the current low-resolution image frame, respectively executing following
steps:

(i) comparing a color or brightness value of a pixel in the current low-resolution image frame with a color or brightness
value of the pixel in the at least one previous low-resolution image frame; and

(ii) if the comparison result satisfies a predetermined condition, adjusting a color or brightness weight corresponding to
the pixel in the low-resolution weights of the at least one previous low-resolution image frame to generate the color or brightness
weight corresponding to the pixel in the low-resolution weights of the current low-resolution image frame;

scaling up a number of the low-resolution weights to generate a plurality of high-resolution weights, wherein the high-resolution
weights are respectively corresponding to the first plurality of pixels in the current original image frame; and

performing a temporal noise reduction to the current original image frame by using the high-resolution weights for reducing
artifact of the current original image frame and obtaining an adjusted image frame, wherein the step of performing the temporal
noise reduction to the current original image frame comprises:

for each pixel in the first plurality of pixels of the current original image frame, respectively executing following steps:
calculating a color or brightness value of a pixel in an adjusted image frame based on a color or brightness value of the
pixel in the current original image frame, a color or brightness value of the pixel in a previous adjusted image frame, and
a color or brightness weight corresponding to the pixel in the high-resolution weights.

US Pat. No. 9,245,857

CHIP PACKAGE

Novatek Microelectronics ...

1. A chip package structure, comprising:
a package body, comprising:
a core circuit;
an electrostatic discharge protection circuit;
a first connection terminal electrically connected to the core circuit;
a second connection terminal electrically connected to the electrostatic discharge protection circuit;
a third connection terminal; and
a first interconnection structure electrically connected to the electrostatic discharge protection circuit, the second connection
terminal and the third connection terminal;

a first lead electrically connecting the second connection terminal and an external circuit; and
a second lead electrically connecting the first connection terminal and the third connection terminal,
wherein the second lead and the first lead are separate.

US Pat. No. 9,214,487

IMAGE SENSOR HAVING LIGHT DISTRIBUTING ELEMENT

Novatek Microelectronics ...

1. An image sensor, comprising:
a plurality of sensing pixels;
a plurality of micro-lenses disposed on the sensing pixels; and
a plurality of first light distributing elements disposed between the sensing pixels and the micro-lenses, and each of the
first light distributing elements including:

a first refractive index pattern; and
a second refractive index pattern surrounding the first refractive index pattern, and a refractive index of the first refractive
index pattern being larger than a refractive index of the second refractive index pattern, wherein the first refractive index
pattern has a first surface facing one of the micro-lenses, the second refractive index pattern covers the first surface of
the first refractive index pattern, the micro-lens corresponding to the first light distributing element has an optic axis,
and a straight line direction extending from one of the sensing pixels towards the micro-lens is parallel with the optic axis,
wherein the first refractive index pattern, the second refractive index pattern and the micro-lens are sequentially arranged
along the straight line direction.

US Pat. No. 9,608,632

RESISTANCE CALIBRATION METHOD AND RELATED CALIBRATION SYSTEM

NOVATEK Microelectronics ...

1. A resistance calibration method for a first resistor of a first module, the resistance calibration method comprising:
performing resistance calibration on a calibration unit of a second module, wherein the first module is connected to the second
module via a pad coupled to the first resistor, and the calibration unit is coupled to the pad;

obtaining a resistance value of the calibration unit after the resistance calibration; and
calibrating a resistance value of the first resistor according to the resistance value of the calibration unit.

US Pat. No. 9,231,620

ITERATIVE DECODING DEVICE AND RELATED DECODING METHOD FOR IRREGULAR LOW-DENSITY PARITY-CHECK CODE CAPABLE OF IMPROVING ERROR CORRECTION PERFORMANCE

NOVATEK Microelectronics ...

1. An iterative decoding device comprising:
a decoder for receiving a set of soft information, iteratively decoding the soft information and updating the set of soft
information accordingly to generate a set of updated soft information;

a dual-mode determination unit coupled to the decoder for generating a determination result, which indicates that a scaling
operation is needed to be performed or not, according to a threshold value and the set of updated soft information, wherein
the threshold value is set to a first threshold value or a second value based on a comparison result of comparing a scaling
counter value, which indicates the number of times that the scaling operation is performed, and a predetermined value; and

a dual-mode scaling unit coupled to the dual-mode determination unit and the decoder for generating the scaling counter value
and performing the scaling operation that is to scale the set of updated soft information according to the determination result,
so as to generate a set of scaled soft information acting as an input of the decoder for next iteration.

US Pat. No. 9,201,483

IMAGE PROCESSING UNIT, IMAGE PROCESSING APPARATUS AND IMAGE DISPLAY SYSTEM

Novatek Microelectronics ...

1. An image processing unit, comprising:
an always on circuit block, configured to receive a first bias voltage from a power supply unit, wherein the first bias voltage
serves as an operating voltage for the always on circuit block; and

a non-always on circuit block, comprising a microcontroller of the image processing unit, wherein when the non-always on circuit
block operates under a first operation mode, the non-always on circuit block receives a second bias voltage from the power
supply unit served as an operating voltage for the non-always on circuit block, so as to perform an image processing operation
on an image input signal, and when the non-always on circuit block operates under a second operation mode, the non-always
on circuit block stops receiving the second bias voltage from the power supply unit, so as to stop the image processing operation,
and at least the microcontroller of the non-always on circuit block is powered down;

wherein the always on circuit block controls the power supply unit to start supplying the second bias voltage to the non-always
on circuit block according a second event trigger signal, such that the non-always on circuit block enters the first operation
mode from the second operation mode; and

wherein one of the always on circuit block and the non-always on circuit block controls the power supply unit to stop supplying
the second bias voltage to the non-always on circuit block according a first event trigger signal, such that the non-always
on circuit block enters the second operation mode from the first operation mode.

US Pat. No. 9,494,961

FEEDBACK DEVICE AND METHOD FOR CONSTANT CURRENT DRIVER

NOVATEK Microelectronics ...

1. A feedback device for a constant current driver, controlling a power supply module in the constant current driver to generate
an output voltage, wherein the constant current driver drives an electrical load with an output current, the feedback device
comprising:
a feedback control module, for receiving a load driven voltage related to the electrical load and generating a control voltage
accordingly, wherein the load driven voltage is a load voltage or generated from the load voltage; and

a feedback output unit, coupled between the feedback control module and the power supply module, for generating a feedback
current via an equivalent resistor of the feedback output unit according to a voltage difference between the control voltage
and a feedback voltage of the power supply module;

wherein the power supply module controls a magnitude of the output voltage according to the feedback current, allowing the
constant current driver to drive the electrical load with the output current.

US Pat. No. 9,318,061

METHOD AND DEVICE FOR MAPPING INPUT GRAYSCALES INTO OUTPUT LUMINANCE

NOVATEK Microelectronics ...

1. A method for mapping an input grayscale into an output luminance comprising:
selecting a first reference grayscale, a first reference luminance, a second reference grayscale and a second reference luminance
according to an input grayscale;

generating a middle reference grayscale and a middle luminance by computing first and second equations of:
X_MID=(X1+X2)/2; and

Y_MID=(Y1+Y2)/2±?,
wherein ? denotes an offset, X1 denotes the first reference grayscale, X2 denotes the second reference grayscale, Y1 denotes the first reference luminance, Y2 denotes the second reference luminance, X_MID denotes the middle reference grayscale, and the Y_MID denotes the middle luminance;
replacing a value of the first or second reference grayscale by a value of the middle reference grayscale, and replacing a
value of the first or second reference luminance by a value of the middle luminance according to the middle reference grayscale
and the input grayscale; and

generating an output luminance by computing a third equation of:
Y=Y1+(Y2?Y1)/(X2?X1)*(X?X1), wherein Y denotes the output luminance.

US Pat. No. 9,172,390

DRIVING VOLTAGE GENERATOR AND DIGITAL TO ANALOG CONVERTER

Novatek Microelectronics ...

1. A digital to analog converter, comprising:
a voltage selector, receiving N first voltages among a plurality of input voltages of an analog format, and the voltage selector
receiving a plurality of selecting signals of a digital format, wherein the voltage selector selects at most one of the first
voltages for providing to an output terminal according to the selecting signals;

M voltage transmitting switches, terminals of the voltage transmitting switches respectively receiving M second voltages different
from the first voltages among the input voltages, and other terminals of the voltage transmitting switches being commonly
coupled to the output terminal, wherein the voltage transmitting switches are respectively turned on or turned off according
to M transmitting enable signals; and

a selecting signal decoder, coupled to the voltage transmitting switches, and generating the transmitting enable signals according
to the selecting signals,

wherein M and N are positive integers.

US Pat. No. 9,397,650

GATE DRIVING APPARATUS

Novatek Microelectronics ...

1. A gate driving apparatus, comprising:
a first gate driving chip, the first gate driving chip comprises a input pin and a first current output pin, the first gate
driving chip receives a reference electrical signal through the input pin and generates a reference current according to the
reference electrical signal, the first current output pin outputs the reference current; and

N second gate driving chips, the second gate driving chips are coupled with each other in series, each of the second gate
driving chips comprises a current input pin and a second current output pin, an input current is received through the current
input pin and an output current is generated by mirroring the input current and outputted by the second current output pin,
the current input pin of the first chip of the second gate driving chips is coupled to the first current output pin of the
first gate driving chip to receive the reference current, N is a positive integer,

wherein, the first gate driving chip and the second gate driving chips further respectively generate at least one first output
signal and at least N second output signals to drive a display panel according to the reference current, wherein the first
gate driving chip comprises:

a reference electrical signal generator, coupled to the input pin and configured to generate the reference electrical signal;
and

a selector, coupled between a coupling path of the reference electrical signal generator and the input pin, though the selector,
the first gate driving chip selectively receives the reference electrical signal generated from outside of the first gate
driving chip or the reference electrical signal generated by the reference signal generator according to a selection signal.

US Pat. No. 9,373,291

METHOD AND DEVICE FOR MAPPING INPUT GRAYSCALES INTO OUTPUT LUMINANCE

NOVATEK Microelectronics ...

1. A method for mapping an input grayscale into an output luminance comprising:
selecting a reference grayscale and a curvature according to an input grayscale; and
generating an output luminance according to the reference grayscale, the curvature, and the input grayscale, wherein the output
luminance is generated by computing an equation of: Y=A*(X2)?A*(X?)*X, wherein Y denotes the output luminance, A denotes the curvature, X denotes the input grayscale, and X? denotes
the reference grayscale.

US Pat. No. 9,165,350

IMAGE SHARPENING METHOD AND IMAGE PROCESSING DEVICE

Novatek Microelectronics ...

1. An image sharpening method adapted to an image processing device, comprising:
obtaining a plurality of pixels in an image;
calculating a first weight of a high pass filter and a second weight of a first filter according to the pixels, wherein the
first filter is a convolution of the high pass filter and a low pass filter;

generating a sharpening filter according to the high pass filter, the first weight, the first filter and the second weight;
and

executing a sharpening operation on the pixels according to the sharpening filter.

US Pat. No. 9,093,896

MULTI-POWER DOMAIN OPERATIONAL AMPLIFIER AND VOLTAGE GENERATOR USING THE SAME

NOVATEK MICROELECTRONICS ...

1. A voltage generator, comprising:
a cascade resistor having a first feedback terminal and a second feedback terminal;
a first regulator, which is configured to output a first output voltage and comprises a multi-power domain operational amplifier,
which has a negative feedback configuration, operates in a first power domain and a second power domain different from the
first power domain, and has an inverting input terminal receiving a first reference voltage, and a noninverting input terminal
coupled to the first feedback terminal; and

a second regulator, which is configured to output a second output voltage, and comprises a single power domain operational
amplifier operating in a third power domain and having the negative feedback configuration, wherein the single power domain
operational amplifier has an inverting input terminal receiving a second reference voltage and a noninverting input terminal
coupled to the second feedback terminal.

US Pat. No. 9,208,740

GATE DRIVER AND DISPLAY DEVICE USING THE SAME

NOVATEK Microelectronics ...

1. A gate driver; comprising:
a logic circuit, for generating a plurality of buffer input signals and a modulation signal;
a plurality of buffers, each receiving one of the plurality of buffer input signals and generating a gate driving signal according
to the one of the plurality of buffer input signals, wherein the buffers are commonly coupled between a first voltage source
node and a second voltage source; and

a switch module, coupled to all of the buffers via the first voltage source node and coupled to a first voltage source, for
determining whether the first voltage source is electrically connected to the first voltage source node according to the modulation
signal;

wherein during a modulation period, the modulation signal causes the switch module to be cut-off and causes the first voltage
source node to be connected to only the plurality of buffers and the plurality of buffer input signals are configured to short
all or some of a plurality of output terminals, so as to modulate at least one of the gate driving signals;

wherein during the modulation period, the plurality of buffer input signals are at a first input level, and when each of the
plurality of buffers receives the buffer input signal at the first input level, the output terminal of the buffer is connected
to the first voltage source node and cut-off from the second voltage source.

US Pat. No. 9,063,596

MULTI-TOUCH POSITIONING METHOD

NOVATEK Microelectronics ...

1. A multi-touch positioning method for a touch control device, the touch control device comprising a plurality of sensing
channels, each of the plurality of sensing channels being interlaced by a first sensing electrode and a second sensing electrode,
the multi-touch positioning method comprising:
retrieving a first touch sensing value and a second touch sensing value respectively corresponding to the first sensing electrode
and the second sensing electrode of each of the sensing channels;

adding the first touch sensing value and the second touch sensing value to generate a sensing sum value corresponding to each
sensing channel;

determining a touch sensing channel having a local maximum value according to the plurality of sensing sum values of the plurality
of sensing channels, so as to define a touch point on the touch sensing channel;

utilizing a center of gravity method to calculate a first coordinate of the touch point according to the sensing sum value
and a horizontal coordinate corresponding to the touch sensing channel and its neighboring sensing channels;

accumulating the first touch sensing values corresponding to the touch sensing channel and two of its neighboring sensing
channels, respectively, to generate a third accumulation result, and accumulating the second touch sensing values corresponding
to the touch sensing channel and two of its neighboring sensing channels, respectively, to generate a fourth accumulation
result;

comparing the third accumulation result and the fourth accumulation result, so as to set a local reference value according
to the greater of the third accumulation result and the fourth accumulation result;

accumulating the sensing sum values corresponding to the touch sensing channel and two of its neighboring sensing channels,
so as to generate a second accumulation result;

dividing the local reference value by the second accumulation result, so as to generate a second dividing result; and
multiplying the second accumulation result by an interpolation constant to generate a multiplying result, so as to define
the multiplying result as a second coordinate of the touch point.

US Pat. No. 9,142,169

DIGITAL TO ANALOG CONVERTER AND SOURCE DRIVER CHIP THEREOF

NOVATEK Microelectronics ...

1. A digital to analog converter (DAC), for a source driver chip of a liquid crystal display (LCD) device, the digital to
analog converter comprising:
an output terminal, for outputting an output voltage;
a plurality of receiving terminals, for receiving a plurality of Gamma voltages; and
a plurality of transmission paths, comprising a plurality of first-type transistors coupled between the plurality of receiving
terminals and the output terminal, respectively, for outputting one of the plurality of Gamma voltages as the output voltage
according to a digital select signal;

wherein a first transmission path corresponding to a first receiving terminal receiving a first Gamma voltage closest to a
middle voltage among the plurality of Gamma voltages has lower on-resistance than other transmission paths among the plurality
of transmission paths;

wherein the first Gamma voltage results in the first-type transistor of the first transmission path having a smaller source-to-gate
voltage.

US Pat. No. 9,489,166

DATA TRANSMISSION METHOD AND DISPLAY DRIVING SYSTEM

NOVATEK MICROELECTRONICS ...

1. A data transmission method applied in a display having a host controller and n display drivers, wherein n is a natural
number greater than 1, the data transmission method comprising:
providing a communication link under Mobile Industry Processor Interface (MIPI) standards between the host controller and
the n display drivers;

determining n virtual channel values Vc1, Vc2, . . . , and Vcn corresponding to the respective n display drivers;

receiving a control command via the communication link under MIPI standards from the host controller, wherein the control
command comprises a virtual channel parameter;

an ith display driver among the n display drivers operating according to the control command when the virtual channel parameter of
the control command indicates an ith virtual channel value Vci among the n virtual channel values, where i is a natural number smaller than or equal to n;

the remaining n?1 display drivers among the n display drivers discarding the control command when the virtual channel parameter
of the control command indicates the ith virtual channel value Vci;

wherein the respective virtual channel values corresponding to the n display drivers are assigned by means of a hardware pin
configuration, a register programming of the display drivers, or a multi-time programming (MTP) of the display drivers;

determining a virtual broadcasting value;
configuring an xth display driver of the n display drivers to provide a synchronization signal when the virtual channel parameter of the control
command indicates the virtual broadcasting value, where x is a natural number smaller than or equal to n;

configuring the remaining n?1 of the n display drivers in an output disable state in response to the synchronization signal;
and

feeding a response back to the host via the communication link under MIPI standards by the xth display driver in a bus turnaround period.

US Pat. No. 9,472,146

DISPLAY DEVICE AND DRIVING MODULE THEREOF

NOVATEK Microelectronics ...

1. A display device comprising a plurality of sub-pixel groups, wherein each of sub-pixel groups comprising
a first sub-pixel located at a first column;
a second sub-pixel located at a second column adjacent to the first column;
a third sub-pixel located at a third column adjacent to the second column;
a fourth sub-pixel located at a fourth column adjacent to the third column; and
a fifth sub-pixel located at the third column and the fourth column;
wherein a height of the first sub-pixel equals a height of the second sub-pixel;
wherein the height of the first sub-pixel is greater than heights of the third sub-pixel, the fourth sub-pixel and the fifth
sub-pixel;

wherein the height of the first sub-pixel is different from or equal to a sum of the heights of the fifth sub-pixel and the
third sub-pixel or a sum of the heights of the fifth sub-pixel and the fourth sub-pixel;

wherein the height of the fifth sub-pixel is different from or equal to the heights of the third sub-pixel and the fourth
sub-pixel.

US Pat. No. 9,142,181

DISPLAY DRIVER AND DISPLAY DIVING METHOD

NOVATEK Microelectronics ...

1. A display driver, comprising:
a first predetermined voltage level providing apparatus, for providing a first predetermined voltage level group comprising
at least one first predetermined voltage level;

a first image data providing apparatus, for outputting a first image data to an output terminal of the first image data providing
apparatus; and

a detection controlling circuit, for receiving and determining when the output terminal of the first image data providing
apparatus is pre-charged to the first predetermined voltage level according to a relationship between an absolute value of
a voltage level of the first image data and an absolute value of the first predetermined voltage level.

US Pat. No. 9,501,984

DRIVING DEVICE AND DRIVING DEVICE CONTROL METHOD THEREOF

NOVATEK Microelectronics ...

1. A driving device, comprising:
a driving module, for generating a plurality of driving signals according to a plurality of next channel data and adjusting
coupling relationships of the plurality of driving signals according to a charge sharing control signal; and

a timing control module, for generating the plurality of next channel data and selecting one of a plurality of charge sharing
control commands as the charge sharing control signal, delaying the plurality of next channel data at least one line period
to acquire a plurality of current channel data, and sequentially comparing the plurality of next channel data and the plurality
of current channel data for determining whether the plurality of next channel data and the plurality of current channel data
satisfy one of a plurality of charge sharing conditions, to select one of the plurality of charge sharing control commands
as the charge sharing control signal.

US Pat. No. 9,270,112

DRIVING CIRCUIT

Novatek Microelectronics ...

1. A driving circuit, comprising:
a second electrostatic current limiting resistor, wherein the second electrostatic current limiting resistor is coupled to
first ends of a plurality of first electrostatic current limiting resistors;

the first electrostatic current limiting resistors, wherein one of the first ends of the first electrostatic current limiting
resistors is commonly coupled to the second electrostatic current limiting resistor so as to receive a reference voltage;
and

a plurality of digital-to-analog converter (DAC) units, wherein the DAC units are respectively coupled to second ends of the
first electrostatic current limiting resistors in a one-on-one manner so as to respectively receive the reference voltage
through the first electrostatic current limiting resistors,

wherein the second electrostatic current limiting resistor has a resistance value smaller than the resistance value of the
first electrostatic current limiting resistors.

US Pat. No. 9,258,498

IMAGE SENSOR

NOVATEK Microelectronics ...

1. An image sensor, comprising:
a pixel unit, comprising:
an image pixel array, comprising a plurality of image pixels, arranged in a plurality of image pixel rows and a plurality
of image pixel columns;

a first reference pixel array, comprising a plurality of first reference pixels, arranged in one or more first reference pixel
rows and a plurality of first reference pixel columns; and

a bias circuit, coupled to the image pixel array, the first reference pixel array, and a pixel readout circuit, wherein the
bias circuit generates a plurality of column sensing signals in a plurality of nodes coupled to the plurality of image pixel
columns according to a bias voltage, generates a plurality of first reference signals in the plurality of nodes coupled to
the plurality of first reference pixel columns according to the bias voltage, and converts the plurality of first reference
signals to a first average reference voltage signal; and

the pixel readout circuit, coupled to the bias circuit of the pixel unit for generating a plurality of reset values and a
plurality of sampling values according to the plurality of column sensing signals and the first average reference voltage
signal;

wherein the plurality of image pixel rows comprises a plurality of first image pixel rows, a total number of the plurality
of first image pixel rows is M1, and a total number of the first reference pixel rows is N1, where M1>N1.

US Pat. No. 9,196,209

CHARGE RECYCLING CIRCUIT

NOVATEK Microelectronics ...

1. A charge recycling circuit for charging a driving circuit using charges which are discharged from the driving circuit,
comprising:
a first node, a second node, and a third node;
a first switch including:
a first end coupled to a first unit gain buffer of the driving circuit; and
a second end;
a second switch including:
a first end coupled to a second unit gain buffer of the driving circuit; and
a second end;
a third switch including:
a first end coupled to the first end of the first switch; and
a second end coupled to the third node;
a fourth switch including:
a first end coupled to the first end of the second switch; and
a second end coupled to the third node;
a fifth switch including:
a first end coupled to the second end of the first switch; and
a second end coupled to the second node;
a sixth switch including:
a first end coupled to the second end of the second switch; and
a second end coupled to the second node;
a seventh switch including:
a first end coupled to the second node; and
a second end coupled to the third node;
a first capacitor including:
a first end coupled to the second end of the first switch; and
a second end coupled to the third node; and
a second capacitor including:
a first end coupled to the second end of the second switch; and
a second end coupled to the third node.

US Pat. No. 9,817,525

TOUCH PANEL

Novatek Microelectronics ...

1. A touch panel, comprising:
a plurality of touch pads arranged in an array, the touch pads are arranged in N columns and M rows, the touch pad in the
ith column and in the jth row is connected to the touch pad in the (i?1)th column and in the (j?1)th row and the touch pad in the (i+1)th column and in the (j+1)th row in a first direction,

or the touch pad in the ith column and in the jth row is connected to the touch pad in the (i+1)th column and in the (j?1)th row and the touch pad in the (i?1)th column and in the (j+1)th row in a second direction, N and M are positive integers, and i and j are positive integers greater than 1 and respectively
smaller than (N?1) and (M?1),

wherein at least a first touch pad and a second touchpad in a boundary column are not adjacent to an end-most touchpad of
the touchpads in the boundary column, wherein the boundary column is one of the first and last columns and the first and second
touch pads are connected by a first conductor line and a second conductor line respectively so as to share a first signal
transmission channel, and there is at least a third touch pad which is not connected by any of the first and second conductor
lines and disposed on the boundary column and between the first and second touch pads, wherein the third touch pad is further
connected to a third conductor line which is extended cross the second conductor line.

US Pat. No. 9,389,623

VOLTAGE CONVERTING DEVICE AND ELECTRONIC SYSTEM THEREOF

NOVATEK Microelectronics ...

1. A voltage converting device comprising:
a differential current generating module comprising:
a first transistor comprising a gate coupled to a feedback voltage, a source coupled to a first node, and a drain coupled
to a first output end, for generating a first differential current according to the feedback voltage, wherein the feedback
voltage is a product of a converting voltage and a ratio;

a second transistor comprising a gate coupled to the feedback voltage, a source coupled to a second note, and a drain coupled
to a second output end, for generating a second differential current according to the feedback voltage;

a first resistor coupled between the first node and the second node; and
a second resistor coupled between the second node and a first supply voltage; and
a voltage converting module coupled to the differential current generating module, a second supply voltage and a third supply
voltage for generating the converting voltage according to the first differential current, the second differential current,
the second supply voltage and the third supply voltage.

US Pat. No. 9,373,293

DISPLAY PANEL AND DISPLAY APPARATUS

Novatek Microelectronics ...

1. A display apparatus comprising:
a source driver providing a plurality of pixel voltages, wherein the pixel voltages respectively correspond to either a maximum
gray-level voltage or a minimum gray-level voltage, and the maximum gray-level voltage and the minimum gray-level voltage
correspond to a same gray-level value and have different polarities; and

a display panel comprising:
a plurality of data lines coupled to the source driver to receive the pixel voltages;
a plurality of pixel switches, each of the pixel switches being respectively coupled to a corresponding data line of the data
lines to transmit a corresponding pixel voltage of the pixel voltages;

a plurality of pixel capacitors, each of the pixel capacitors being respectively coupled between a corresponding pixel switch
of the pixel switches and a common voltage to receive the corresponding pixel voltage; and

a plurality of gray-level switches, each of the gray-level switches being respectively coupled to a corresponding pixel capacitor
of the pixel capacitors in parallel, each of the gray-level switches respectively receiving a gray-level control signal, the
gray-level switches regulating voltage drops across the pixel capacitors coupled to the gray-level switches in parallel according
to the corresponding gray-level control signals, wherein,

when the source driver drives the display panel by a frame inversion, the pixel voltage applied to all the pixels is the maximum
gray-level voltage during a first frame period and is the minimum gray-level voltage during a second frame period, adjacent
to the first frame period;

when the source driver drives the display panel by a column inversion, the pixel voltage applied to all the pixels in a first
column is the maximum gray-level voltage and the pixel voltage applied to all the pixels in a second column, adjacent to the
first column, is the minimum gray-level voltage.

US Pat. No. 9,183,801

SOURCE DRIVER APPARATUS AND DRIVING METHOD OF DISPLAY PANEL

Novatek Microelectronics ...

1. A source driver apparatus configured to drive a display panel, the source driver apparatus comprising:
a data operation circuit configured to receive pixel data and perform a polarity determination operation on the pixel data
to determine a polarity distribution information of a plurality of pixels on the display panel; and

a pixel driving circuit coupled to the data operation circuit and configured to adaptively and dynamically adjust a polarity
distribution of the pixels on the display panel, to drive the display panel according to the pixel data and the polarity distribution
information,

wherein the display panel comprises a plurality of pixel lines, the data operation circuit sequentially performs the polarity
determination operation on the pixel data of at least one part pixels of each of the pixel lines to determine the polarity
distribution information of the at least one part pixels of the display panel,

wherein after the data operation circuit sequentially performs the polarity determination operation on the pixel data of the
at least one part pixels of each of the pixel lines, the data operation circuit determines whether the pixel data of the entire
pixels of each of pixel lines have been completely received.

US Pat. No. 9,401,127

IMAGE PROCESSING METHOD AND ANTI-SATURATION METHOD FOR IMAGE DATA AND IMAGE PROCESSING DEVICE

Novatek Microelectronics ...

1. An anti-saturation method for image data, adapted to an image processing device to perform an image processing, comprising:
analyzing, by a global gain generator, one of a plurality of image frames to obtain an original conversion relationship curve
of the image frame, and the original conversion relationship curve representing a gain processing of a plurality of grayscale
values of the image frame commonly according to an original gain value, wherein the original gain value is greater than 1;

obtaining a default conversion relationship curve by a conversion relationship generator coupled to the global gain generator,
wherein the default conversion relationship curve is commonly used for performing an anti-saturation processing on image data
of the image frames;

combining, by the conversion relationship generator, the default conversion relationship curve and the original conversion
relationship curve to perform the anti-saturation processing on the image frame, so as to obtain an adjusted conversion relationship
curve; and

performing a gain processing on the image data of the image frame according to the adjusted conversion relationship curve
by a conversion circuit coupled to the conversion relationship generator.

US Pat. No. 9,363,069

CLOCK GENERATING DEVICE AND RELATED SYNCHRONIZATION METHOD

NOVATEK Microelectronics ...

1. A clock generating device, comprising:
a clock generating unit, for counting a synchronization period of a synchronization signal, generating a first interrupt signal
according to the synchronization signal, generating a pulse-width modulation signal according a control signal, counting a
phase difference between the synchronization signal and the pulse-width modulation signal, and generating a second interrupt
signal according to the pulse-width modulation signal; and

a computing unit, for acquiring the synchronization period according to the first interrupt signal, acquiring the phase difference
according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation
period of the pulse-width modulation signal and the phase difference.

US Pat. No. 9,288,095

SIGNAL RECEIVING SYSTEM, BAND DETECTION METHOD FOR MULTI-CARRIER SIGNAL AND DEMODULATING APPARATUS THEREOF

Novatek Microelectronics ...

1. A band detection method for a multi-carrier signal, wherein each carrier has a plurality of symbols corresponding to a
plurality of time, the method comprising:
defining a scan area range according to a full band range of the carriers;
obtaining a reference symbol corresponding to each of the symbols of each of the carriers in the scan area range according
to a time offset value and a frequency offset value;

performing an operation according to the symbols of each of the carriers and the respectively corresponding reference symbols
to generate calibration information corresponding to a carrier frequency of each of the carriers; and

tuning the full band range of the carriers according to the calibration information corresponding to the carriers,
wherein the time offset value and the frequency offset value are set according to pilot signals of the carriers.

US Pat. No. 9,142,194

TRANSMISSION METHOD FOR DISPLAY DEVICE

NOVATEK Microelectronics ...

1. A transmission method for a display device, the display device comprises a one-to-many timing controller and a plurality
of source drivers, the transmission method comprising:
determining whether the plurality of source drivers being operated indifferent operational modes are switched on or off according
to a command signal, to receive a display information of the one-to-many timing controller;

wherein the display information comprises at least a first control triggering signal, a first control signal, a first display
information triggering signal, a first display signal, a second display information triggering signal and a second display
signal, and the command signal is an internal setting signal or an external setting signal.

US Pat. No. 9,128,536

FREQUENCY SYNTHESIZER AND FREQUENCY SYNTHESIZING METHOD FOR CONVERTING FREQUENCY'S SPURIOUS TONES INTO NOISE

NOVATEK MICROELECTRONICS ...

1. A frequency synthesizer, comprising:
an accumulating unit, comprising:
a fractional part accumulator for performing an accumulation operation based on a fractional part value to output a carry
sequence, which comprises a plurality of carry bits;

a register unit for writing the carry bits according to a first random address sequence, and reading the carry bits according
to a second random address sequence whose order is different from that of the first random address sequence; and

an integer accumulator for performing an accumulation operation based on an integer value and the read carry bits to continuously
output a count value; and

a clock generator for outputting a clock signal according to the count value.

US Pat. No. 9,420,306

ESTIMATING METHOD OF PREDICTED MOTION VECTOR

NOVATEK Microelectronics ...

1. An estimation method of a predicted motion vector for an image block having one or more pixels, the estimation method comprising:
calculating a pixel difference value corresponding to a current frame and a reference frame which is generated based on at
least one frame preceding to the current frame, for each pixel of the image block;

determining a pixel difference area corresponding to the current frame and the reference frame according to the pixel difference
values corresponding to the plurality of pixels; and

determining a predicted motion vector of the image block according to the pixel difference area corresponding to the current
frame and the reference frame, wherein the step of determining the predicted motion vector of the image block comprises:

determining at least one of a horizontal component and a vertical component of the predicted motion vector, according to at
least one of a horizontal length and a vertical length of the pixel difference area.

US Pat. No. 9,240,151

SOURCE DRIVER AND METHOD FOR DETERMINING POLARITY OF PIXEL VOLTAGE THEREOF

Novatek Microelectronics ...

1. A source driver, comprising:
a data register unit configured to receive an image data signal and provide a plurality of display data;
a plurality of data channels coupled to the data register unit and configured to receive the display data and provide a plurality
of pixel voltages according to the display data, the data channels being grouped into a plurality of data groups and each
data group corresponding to at least two of the data channels; and

a plurality of polarity determining units coupled to the data channels, each of the polarity determining units being configured
to:

determine preset charging directions of pixel voltages provided by the coupled data channels of a corresponding one of the
data groups, according to the received display data of the coupled data channels and the previous display data corresponding
to the received display data;

determine whether to invert polarities of a part of the pixel voltages provided by the coupled data channels of the corresponding
data group, according to the preset charging directions of the pixel voltages of the corresponding data group; and

determine whether to enable a charge sharing function according to the preset charging directions of the pixel voltages of
the corresponding data groups.

US Pat. No. 9,213,484

METHOD FOR DETECTING SINGLE-FINGER ROTATE GESTURE AND THE GESTURE DETECTING CIRCUIT THEREOF

NOVATEK MICROELECTRONICS ...

1. A method for detecting a single-finger rotation gesture, wherein the method comprises:
dividing a touch panel into at least three area segments separated by straight lines extending outwardly from a center point
and setting a plurality of data codes respectively corresponding to each area segment among the at least three area segments,
wherein each of the at least three area segments is permanently fixed to a particular area of the touch panel;

detecting which one of the at least three area segments is touched;
controlling a register to sequentially record the data codes respectively corresponding to the touched area segments within
a predetermined time;

comparing to judge whether temporary data buffered in the register is the same as predetermined default data when the predetermined
time is reached; and

outputting a rotation gesture signal if the temporary data is the same as the default data.

US Pat. No. 9,208,711

APPARATUS AND METHOD FOR DRIVING DISPLAY

NOVATEK MICROELECTRONICS ...

1. An apparatus for driving a display, comprising:
a shift register for generating a plurality of latch signals according to a sync signal;
a first latch unit for latching a data signal in response to the latch signals to obtain a plurality of first data corresponding
to a plurality of channels;

a second latch unit coupled to the first latch unit and for latching the first data corresponding to the channels as a plurality
of second data in response to a latch data signal;

a data comparison unit connected to the first latch unit and the second latch unit, for receiving the first data from the
first latch unit and receiving the second data from the second latch unit and comparing the first data with the second data
corresponding to the same channels to output a plurality of third data corresponding to the channels; and

a level select unit for selecting a plurality of voltage levels corresponding to the channels, according to the third data;
wherein when a difference between a first voltage level of the first data and a second voltage level of the second data exceeds
a default value, a third voltage level of the third data lies between the first voltage level and the second voltage level;

wherein when the first voltage level of the first data is different from the second voltage level of the second data and the
difference between the first voltage level of the first data and the second voltage level of the second data does not exceed
the default value, the third voltage level of the third data is equal to the first voltage level.

US Pat. No. 9,142,168

METHOD AND APPARATUS FOR DRIVING A DISPLAY DEVICE

NOVATEK Microelectronics ...

1. A driving device of a display device, the driving device comprising:
a gamma voltage generator, for generating a gamma voltage according to a control signal to a source driver of the display
device; and

a logic unit, for generating the control signal to the gamma voltage generator according to a difference among contrast ratios
of a plurality of frames to be displayed, to adjust the gamma voltage, so as to reduce power consumption of the display device.

US Pat. No. 9,141,236

LAYOUT STRUCTURE OF CAPACITIVE TOUCH PANEL

Novatek Microelectronics ...

1. A layout structure of a capacitive touch panel, comprising:
a plurality of electrical paths, configured on a substrate; and
a plurality of first touch units, respectively comprising at least one first receiving electrode and at least one first driving
electrode, wherein all of receiving electrodes in the capacitive touch panel are respectively connected to a controller through
different electrical paths, the first driving electrodes are electrically connected to each other, the first touch units are
arranged in an m*n array, and both m and n are positive integers greater than or equal to two;

wherein in one of the first touch units, a number of the at least one first receiving electrode is one and is disposed at
a central portion of the first touch unit, the number of the at least one first driving electrode is greater than one and
is disposed around the at least one first receiving electrode, and all of driving electrodes disposed around the at least
one first receiving electrode are directly electrically connected to each other.

US Pat. No. 9,166,535

CIRCUIT OF OPERATIONAL AMPLIFIER

Novatek Microelectronics ...

1. A circuit of an operational amplifier, comprising:
an operational main circuit;
a plurality of current sources configured to connect the operational main circuit to a high voltage source or a ground voltage
source; and

at least one clamp circuit connected between the operational main circuit and at least one of the current sources,
wherein a transistor device connected to the at least one clamp circuit has a bias endurance level, and the bias endurance
level of the transistor device is lower than a preset bias endurance level of the operational main circuit.

US Pat. No. 9,153,191

POWER MANAGEMENT CIRCUIT AND GATE PULSE MODULATION CIRCUIT THEREOF CAPABLE OF INCREASING POWER CONVERSION EFFICIENCY

NOVATEK Microelectronics ...

1. A power management circuit for a liquid crystal display device, comprising:
one or more power generating circuits, for receiving one or more input voltages and generating one or more output voltages,
respectively;

a gate pulse modulation circuit, coupled between a gate high-level voltage source and a discharging control terminal, for
generating a gate control signal; and

a discharging controller, coupled to the discharging control terminal, for providing a discharging path for the gate pulse
modulation circuit, wherein

one of the gate pulse modulation circuit and the discharging controller is further coupled to a power supply such that the
gate pulse modulation circuit discharges to the power supply to recycle discharges to the power supply for reutilization during
a gate discharging period, and

the power supply is one of the one or more input voltages and the one or more output voltages and is not a ground level.

US Pat. No. 9,148,594

FIXED PATTERN NOISE REMOVAL METHOD

NOVATEK Microelectronics ...

1. A fixed pattern noise (FPN) removal method for an image sensor, comprising:
calculating each compensation value corresponding to each pixel column according to a plurality of compensation pixel values
of the each pixel column; and

sampling a plurality of active pixel values in an active pixel area and compensating the plurality of active pixel values
according to the each compensation value of the each pixel column, to generate a plurality of compensated active pixel values;

wherein a plurality of active pixels sense light to generate the plurality of active pixel values;
wherein the step of calculating each compensation value corresponding to each pixel column according to the plurality of compensation
pixel values of the each pixel column comprises:

setting a specific operational gain; and
sampling and calculating a difference between each primary color pixel column average of pixels of each primary color in the
each pixel column in an optical black area and each primary color pixel average of pixels of the each primary color in the
optical black area under the specific operational gain and an initial state, and saving the difference to a memory;

wherein all pixels in the optical black area do not sense light.

US Pat. No. 9,123,275

METHOD FOR DISPLAYING ERROR RATES OF DATA CHANNELS OF DISPLAY

Novatek Microelectronics ...

1. A method for displaying error rates of data channels of a display, comprising:
repeatedly transmitting a test signal in a specific format to a first and a second source drivers of the display via a first
and a second data channels of the display during a test period by a timing controller of the display, wherein the test signal
in the specific format is a series of bits;

receiving the test signal respectively from the first and the second data channels, and determining whether the received test
signal is in the specific format or not by the first and the second source drivers;

counting a first number and a second number of times, respectively by the first source driver and the second source driver,
that the first source driver and the second source driver determine that the received test signal is not in the specific format
during the testing period;

controlling displaying of a first area of a panel of the display according to the counted first number of times by the first
source driver; and

controlling displaying of a second area of the panel according to the counted second number of times by the second source
driver.

US Pat. No. 9,119,249

LED DEVICE, LED DRIVING CIRCUIT AND METHOD

NOVATEK MICROELECTRONICS ...

1. A light-emitting diode (LED) driving circuit, comprising:
an LED control circuit for shifting an input pulse width modulation (PWM) signal in a higher frequency direction in a frequency
domain to generate an output PWM signal having a duty cycle substantially the same as a duty cycle of the input PWM signal,
the LED control circuit comprising:

a duty cycle detecting circuit for detecting the duty cycle of the input PWM signal, wherein the duty cycle detecting circuit
is configured to filter the input PWM signal to obtain an analog signal, and convert the analog signal into a digital signal
indicating the duty cycle of the input PWM signal; and

a pulse generating circuit for generating the output PWM signal according to the duty cycle of the input PWM signal; and
a power stage circuit for outputting an LED driving current according to the output PWM signal.

US Pat. No. 9,118,903

DEVICE AND METHOD FOR 2D TO 3D CONVERSION

NOVATEK MICROELECTRONICS ...

6. A 2D to 3D conversion method, comprising:
receiving 2D image data by a 2D to 3D conversion device;
displaying a preview frame and assigning a predetermined window by the 2D to 3D conversion device in response to a user selection
on the preview frame, wherein the predetermined window demarcates an image range of the 2D image data;

generating a depth map by the 2D to 3D conversion device according to the 2D image data and the predetermined window, wherein
the depth map comprises depth data of the 2D image data; and

converting the 2D image data into 3D image data by the 2D to 3D conversion device according to the depth data of the depth
map and the predetermined window.

US Pat. No. 9,098,915

IMAGE PROCESSING APPARATUS FOR REGIONAL IMAGE ENHANCEMENT AND IMAGE PROCESSING METHOD USING THE SAME

NOVATEK MICROELECTRONICS ...

1. An image processing apparatus, for adjusting a luminance of a target pixel of an image, the target pixel comprising original
pixel data and corresponding to a mask value, the image processing apparatus comprising:
a luminance detection unit, for generating an original luminance value according to the original pixel data;
a luminance compensation unit, for adjusting the original luminance value according to a non-linear function to generate a
compensated luminance value; and

a mapping unit, for generating adjusted pixel data according to the compensated luminance value;
wherein the non-linear function at least comprises a first monomial function, which has a base part associated with an inverse
value of the original luminance value and an exponent part associated with the mask value, and the luminance detection unit,
the luminance compensation unit and the mapping unit are implemented by hardware.

US Pat. No. 9,059,673

AMPLIFIER CIRCUIT AND OPERATION METHOD THEREOF

Novatek Microelectronics ...

1. An amplifier circuit, comprising:
a first transistor, having a first terminal, a second terminal and a first control terminal, wherein the first control terminal
receives an input signal;

a first load, coupled between a first voltage and a first node;
a first signal isolation element, coupled between the first node and the first terminal of the first transistor;
a first current source, coupled between the second terminal of the first transistor and a second voltage;
a second transistor, having a third terminal, a fourth terminal and a second control terminal, wherein the second control
terminal receives the input signal, and the fourth terminal is coupled to the second terminal of the first transistor;

a second load, coupled between the first voltage and a second node;
a second signal isolation element, coupled between the second node and the third terminal of the second transistor;
a third transistor, having a fifth terminal, a sixth terminal and a third control terminal, wherein the third control terminal
is coupled to the first node, and the fifth terminal is coupled to a third node;

a third load, coupled between the first voltage and the third node;
a third signal isolation element, coupled between the third node and the first terminal of the first transistor;
a second current source, coupled between the sixth terminal of the third transistor and the second voltage;
a fourth transistor, having a seventh terminal, an eighth terminal and a fourth control terminal, wherein the forth control
terminal is coupled to the second node, the seventh terminal is coupled to a fourth node, and the eighth terminal is coupled
to the sixth terminal of the third transistor;

a fourth load, coupled between the first voltage and the fourth node;
a fourth signal isolation element, coupled between the fourth node and the third terminal of the second transistor;
a first switch, coupled between the third control terminal of the third transistor and the second voltage; and
a second switch, coupled between the fourth control terminal of the fourth transistor and the second voltage.

US Pat. No. 9,786,234

DRIVING MODULE HAVING LOW CHARGING/DISCHARGING POWER CONSUMPTION AND DRIVING DEVICE THEREOF

NOVATEK Microelectronics ...

1. A driving module for a driving device of a display system, comprising:
a control unit, for generating a control signal according to a polarity signal indicating whether the driving device performs
a polarity inversion;

a first driving unit, coupled to the control unit, a first voltage source and a second voltage source, for generating a positive
output voltage at a first output end according to a first display voltage and charging the first output end via the second
voltage source according to the control signal; and

a second driving unit, coupled to the control unit, the second voltage source and a third voltage source, for generating a
negative output voltage at a second output end according to a second display voltage and discharging the second output end
via the second voltage source according to the control signal.

US Pat. No. 9,471,075

COMPENSATION MODULE AND VOLTAGE REGULATOR

NOVATEK Microelectronics ...

1. A compensation module for a voltage regulation device comprising a gain stage, an output stage and a miller compensation
module, the compensation module comprising:
a low-output-impedance non-inverting amplifier unit coupled to a gain output of the gain stage and an output-stage input of
the output stage; and

a high-frequency gain unit, coupled between a power end of the voltage regulation device and the low-output-impedance non-inverting
amplifier unit for outputting an high-frequency noise suppression signal to the low-output-impedance non-inverting amplifier
unit according to a high-frequency noise of the power end, to decrease high-frequency noise of the output stage via the low-output-impedance
non-inverting amplifier unit.

US Pat. No. 9,208,544

IMAGE PROCESSING APPARATUS AND IMAGE FINE-TUNING METHOD THEREOF

Novatek Microelectronics ...

1. An image processing apparatus, comprising:
a high-pass filter performing filtering on an input image to generate a filtered image;
a block comparator receiving the input image and a first image and performing a comparing operation between blocks of the
input image and the first image to generate a block comparison result;

an image data reconstructor coupled to the high-pass filter and the block comparator and the image data reconstructor generating
image reconstruction data based on the block comparison result and the filtered image, comprises:

a block extractor coupled to the block comparator and extracting a portion of the block comparison result to generate an information
block; and

a calculating unit coupled to the block extractor and finding a plurality of pixels in the filtered image that correspond
to a plurality of vectors in the information block according to the plurality of vectors, wherein the calculating unit performs
an addition operation on values of the plurality of pixels and calculates an average value according to a result of the addition
operation, wherein the image reconstruction data is generated based on the average value; and

a calculator coupled to the image data reconstructor and the calculator performing an operation on the image reconstruction
data and the input image to generate an output image,

wherein the first image is generated according to the input image.

US Pat. No. 9,196,210

DRIVING MODULE AND DRIVING METHOD FOR AVOIDING CHARGING INEQUALITY

NOVATEK Microelectronics ...

1. A driving module for a liquid crystal display (LCD) device, each pixel of the LCD device comprising a plurality of subpixels
corresponding to a data line, the driving module comprising:
a data line signal processing unit, for generating a plurality of data driving signals;
a scan line signal processing unit, for generating a plurality of gate driving signals; and
a control unit, for controlling the data line signal processing unit and the scan line signal processing unit to charge the
plurality of subpixels within a pixel of the LCD device corresponding to the data line with different charging orders in different
frames via signal control;

wherein the plurality of subpixels within the pixel are charged during a first frame and a second frame, and the plurality
of subpixels within the pixel are not charged in a same sequence during the first frame as the plurality of subpixels within
the pixel are charged during the second frame, and the first frame and the second frame are consecutive frames;

wherein the control unit is further utilized for controlling the data line signal processing unit and the scan line signal
processing unit, to charge the plurality of subpixels within the pixel corresponding to the data line with reverse charging
orders in two adjacent frames, and the plurality of subpixels within the pixel comprises a red (R) subpixel, a green (G) subpixel
and a blue (B) subpixel, each set of RGB subpixels of the plurality of subpixels within the pixel is charged with the reverse
charging orders in the two adjacent frames and is charged with only one of the reverse charging orders in each frame, and
the reverse charging orders are one of RGB/BGR reverse ordering, GRB/BRG reverse ordering and RBG/GBR reverse ordering;

wherein the two reverse charging orders comprise a first forward charging order corresponding to scanning the each set of
RGB subpixels within the pixel in only a left to right direction in the entire first frame, and a second reverse charging
order corresponding to scanning the each set of RGB subpixels within the pixel in only a right to left direction in the entire
second frame.

US Pat. No. 9,118,287

ADAPTIVE AMPLIFICATION CIRCUIT

NOVATEK Microelectronics ...

1. An adaptive amplification circuit, comprising:
an operational amplifier, comprising a variable bias current source for providing a variable bias current for the operational
amplifier;

an equivalent circuit of the operational amplifier, receiving an input voltage and generating an output voltage according
to the input voltage, the equivalent circuit comprising:

a first voltage-to-current circuit for transforming the input voltage to a first current; and
a simulation capacitor coupled between the first voltage-to-current circuit and a reference voltage terminal for generating
the output voltage; and

a bias control unit for generating a bias control signal to the variable bias current source according to the output voltage
so as to adjust the variable bias current.

US Pat. No. 9,443,487

DISPLAY DRIVING APPARATUS AND DRIVING METHOD THEREOF

Novatek Microelectronics ...

1. A display apparatus, comprising:
a display panel having a plurality of pixels arranged in an array, the pixels are divided into a plurality of first display
regions and a plurality of second display regions, wherein each of the first display regions and each of the second display
regions interlace each other and include a plurality of pixel columns, and any adjacent two of the pixel columns for each
of the first display regions and each of the second display regions are different in driving polarity; and

a display driver coupled to the display panel, providing a plurality of driving signals so that driving polarities of one
of the second display regions are opposite to driving polarities of one of the first display region being a left side neighboring
to the one of the second display regions, and are same with driving polarities of one of the first display region being a
right side neighboring to the one of the second display regions,

wherein the pixel columns for each of the first display regions and each of the second display regions are at least three
columns.

US Pat. No. 9,436,023

OPERATIONAL AMPLIFIER

NOVATEK Microelectronics ...

1. An operational amplifier, comprising:
a first metal-oxide-semiconductor field effect transistor (MOSFET), comprising a first drain, a first gate and a first source;
a second MOSFET, comprising a second drain, a second gate and a second source, the second source coupled to the first source
of the first MOSFET; and

a bias source, coupled between a first specific voltage level and the first source of the first MOSFET and the second source
of the second MOSFET;

wherein the first MOSFET and the second MOSFET are depletion-type;
wherein a first body of the first MOSFET and a second body of the second MOSFET are coupled to a second specific voltage level,
and the second specific voltage level is equal to the first specific voltage level or between the first specific voltage level
and a voltage level of the first source of the first MOSFET and the second source of the second MOSFET;

wherein the first MOSFET and the second MOSFET are N-channel MOSFETs, and the first specific voltage level is a ground voltage
level.

US Pat. No. 9,406,106

IMAGE PROCESSING CIRCUIT AND METHOD FOR REMOVING RINGING ARTIFACTS THEREOF

Novatek Microelectronics ...

1. A ringing artifact removing method, adapted to program a processor of an image processing circuit, the ringing artifact
removing method comprising:
receiving grayscale values corresponding to a plurality of display data of an input frame;
calculating a regulating reference value corresponding to each of the display data according to the display data and the display
data at adjacent display positions, comprising:

calculating an edge value and a ring reference value corresponding to each of the display data according to the grayscale
value corresponding to the display data and the grayscale values corresponding to the display data at adjacent display positions,
wherein the input frame is a scaled frame of an original frame and a scaling rate of the input frame relative to the original
frame is taken into account when calculating the edge value and calculating the ring reference value; and

calculating the regulating reference value corresponding to each of the display data according to the edge value and the ring
reference value; and

regulating the grayscale values corresponding to the display data according to the regulating reference values respectively
corresponding to the display data to output grayscale values corresponding to a plurality of regulated display data,

wherein the edge value corresponding to each of the display data is calculated by using following formula,

wherein x is a factor corresponding to the display data, e(x) is the edge value corresponding to the display data, pr is a grayscale value corresponding to the display data pr?1 is a grayscale values corresponding to an adjacent display data, and k is the scaling rate of the input flame relative to
the original frame.

US Pat. No. 9,349,158

IMAGE INTERPOLATION METHOD AND IMAGE INTERPOLATION SYSTEM

NOVATEK Microelectronics ...

1. An image interpolation method, for performing an interpolation on a source image to obtain a destination image, comprising:
performing a domain transformation on a plurality of pixels of the source image, for generating a plurality of first coefficients
and a plurality of second coefficients corresponding to the plurality of pixels;

analyzing and calculating a data correlation degree in at least one direction of each first coefficient according to a plurality
of pixel locations of the plurality of pixels, respectively, for generating a plurality of direction results corresponding
to the plurality of first coefficients;

performing a first interpolation process on the plurality of first coefficients according to the plurality of directional
results, for generating a plurality of first destination coefficients;

performing a second interpolation process on the plurality of first second coefficients, for generating a plurality of second
destination coefficients; and

performing an inverse domain transformation on the plurality of first destination coefficients and the plurality of second
destination coefficients, for generating the plurality of destination pixels of the destination image.

US Pat. No. 9,299,309

INTEGRATED SOURCE DRIVER AND LIQUID CRYSTAL DISPLAY DEVICE USING THE SAME

NOVATEK Microelectronics ...

1. An integrated source driver for a liquid crystal display device, comprising:
a reference voltage generating circuit, for providing a plurality of adjustable voltage ranges within a supply voltage and
a ground level; and

a reference voltage selecting circuit, comprising a plurality of digital to analog converters (DACs), for selecting and generating
a plurality of internal reference voltages from the plurality of adjustable voltage ranges according to a control signal,
respectively;

wherein the plurality of adjustable voltage ranges decrease progressively;
wherein the reference voltage generating circuit receives at least one first external reference voltage;
wherein a plurality of second voltage buffers buffer the at least one first external reference voltage.

US Pat. No. 9,208,739

METHOD AND DEVICE OF GATE DRIVING IN LIQUID CRYSTAL DISPLAY

NOVATEK Microelectronics ...

1. A gate driver for controlling a display apparatus, the gate driver comprising:
a logic circuit, for generating a plurality of switch signals, a breaking signal and a plurality of sharing signals;
a plurality of gate buffers, coupled to the logic circuit, each comprising a first end coupled to the logic circuit, a second
end coupled to a first voltage source, a third end coupled to a second voltage source, and a fourth end, and utilized for
determining to provide a first voltage or a second voltage according to one of the plurality of switch signals to generate
a gate driving signal; and

a charge recycle module, coupled between the plurality of gate buffers and a reference voltage source, for sharing charges
with a plurality of loads according to the plurality of sharing signals;

wherein the charge recycle module comprises:
an adjustment capacitor, comprising a first end coupled to the reference voltage source, and a second end; and
a plurality of switches, each directly connected between the second end and the fourth end of one of the plurality of gate
buffers, for connecting the adjustment capacitor and the gate buffer during a forward edge and a backward edge of a square
wave of the gate driving signal corresponding to the gate buffer according to one of the plurality of sharing signals.

US Pat. No. 9,148,141

LAYOUT STRUCTURE OF CAPACITIVE TOUCH PANEL AND MANUFACTURING METHOD THEREOF

Novatek Microelectronics ...

1. A manufacturing method of a capacitive touch panel, comprising:
providing a substrate;
disposing a conductive layer on the substrate, wherein the conductive layer comprises a plurality of first touch units and
a plurality of second touch units, and the first touch units are electrically connected with each other through a plurality
of connecting sections so as to form a plurality of first touch series extended along a first direction;

disposing an insulation layer on the conductive layer; and
disposing a plurality of electric bridges on the conductive layer after the second touch units of the conductive layer have
been formed, wherein each of the electric bridges comprises a compensation portion, a first crossover portion, and a second
crossover portion, the compensation portions are respectively disposed on the connecting sections, the first crossover portions
and the second crossover portions are disposed on the insulation layer, and the second touch units are electrically connected
with each other through the first crossover portions and the second crossover portions so as to form a plurality of second
touch series extended along a second direction.

US Pat. No. 9,048,249

INTEGRATED CIRCUIT CHIP WITH HIGH SPEED INPUT AND OUTPUT PINS DIRECTLY COUPLED TO COMMON NODE

Novatek Microelectronics ...

1. An integrated circuit (IC) chip, comprising:
a first high-speed signal input pin, disposed on a package of the IC chip;
a first common node, disposed in the IC chip, and directly and electrically coupled to the first high-speed signal input pin;
a first high-speed signal output pin, disposed on the package, and directly and electrically coupled to the first common node;
and

a core circuit, disposed in the IC chip, wherein a first high-speed signal input terminal of the core circuit is directly
and electrically coupled to the first common node.

US Pat. No. 9,812,049

DISPLAY DEVICE AND DRIVING MODULE THEREOF

NOVATEK Microelectronics ...

1. A display device, comprising a plurality of sub-pixel groups having the same sub-pixel pattern, wherein the plurality sub-pixel
groups comprise a first sub-pixel group, at least one second sub-pixel group located at the same columns as the first sub-pixel
group and at least one third sub-pixel group located at the same rows as the first sub-pixel group, and the first sub-pixel
group comprises:
a first sub-pixel, locating at a first column, a first row and a second row next to the first row;
a second sub-pixel, locating at a second column next to the first column, a third column next to the second column, and the
first row;

a third sub-pixel, locating at the second column, the third column and the second row;
a fourth sub-pixel, locating at a fourth column next to the third column, the first row and the second row;
a fifth sub-pixel, locating at a fifth column next to the fourth column, the first row and the second row;
a six sub-pixel, locating at a sixth column next to the fifth column, the first row and the second row; and
a seventh sub-pixel, locating at a seventh column next to the sixth column, the first row and the second row.

US Pat. No. 9,537,489

LEVEL SHIFTER WITH DYNAMIC BIAS TECHNIQUE UNDER OVERSTRESS VOLTAGE

NOVATEK Microelectronics ...

1. A level shifter, for converting a first voltage range to a second voltage range, comprising:
a latch circuit, for outputting the second voltage range;
a stack device, coupled to the latch circuit, comprising a stack transistor for sustaining the second voltage range of the
latch circuit; and

a dynamic bias circuit, coupled to the stack device, for outputting a pulse signal to turn on the stack transistor to toggle
the latch circuit;

wherein the pulse signal has an extremely short width to prevent overstress occurring in the level shifter.

US Pat. No. 9,514,666

IMAGE DISPLAY SYSTEM AND DISPLAY DRIVING MODULE

Novatek Microelectronics ...

1. A display driving module, comprising:
a driving circuit portion, controlled by a system circuit block and comprising one or more driving channels configured to
drive a display panel; and

a non-driving circuit portion configured to connect the system circuit block, the driving circuit portion and the display
panel,

wherein one or more first electrostatic discharge (ESD) protection devices are disposed in the driving circuit portion, and
provide at least one discharge path for the one or more driving channels,

wherein one or more second ESD protection devices are disposed in at least one of the driving circuit portion, the non-driving
circuit portion, the system circuit block and the display panel, and cooperate with the one or more first ESD protection devices
to provide the at least one discharge path.

US Pat. No. 9,084,368

SINGLE FPC BOARD FOR CONNECTING MULTIPLE MODULES AND TOUCH SENSITIVE DISPLAY MODULE USING THE SAME

NOVATEK MICROELECTRONICS ...

1. A single FPC board for connecting multiple modules, comprising:
a thin film having a first module connecting portion, a second module connecting portion and a third module connecting portion,
wherein each of the first module connecting portion, the second module connecting portion and the third module connecting
portion is located on a first side or a second side of the thin film, and the first side is opposite to the second side, wherein
the first to the third module connecting portions are a display panel connecting portion, a touch panel connecting portion
and a motherboard connecting portion, respectively;

at least one first line disposed between the first module connecting portion and the second module connecting portion; and
at least one second line disposed between the first module connecting portion and the third module connecting portion,
wherein the first module connecting portion is located on the first side of the thin film, and the first module connecting
portion is divided into a first signal connecting portion and a second signal connecting portion, which are electrically connected
to the at least one first line and the at least one second line respectively,

wherein the second module connecting portion and the third module connecting portion are located on the second side of the
thin film, the second module connecting portion is electrically connected to the first signal connecting portion through the
at least one first line, and the third module connecting portion is electrically connected to the second signal connecting
portion through the at least one second line, and

wherein the thin film further has a slot extended inward into the thin film from the second side of the thin film to separate
the second module connecting portion and the third module connecting portion.

US Pat. No. 9,069,409

COORDINATE ALGORITHM OF TOUCH PANEL

Novatek Microelectronics ...

1. A coordinate algorithm of a touch panel, wherein the touch panel comprises a plurality of first-direction sensing lines
and a plurality of second-direction sensing lines, the coordinate algorithm comprising:
obtaining a first edge coordinate and a second edge coordinate;
defining a first coordinate compensation parameter and a second coordinate compensation parameter; and
wherein the step of defining the first coordinate compensation parameter comprises defining the first coordinate compensation
parameter according to the number of the first-direction sensing lines;

wherein the step of defining the second coordinate compensation parameter comprises defining the second coordinate compensation
parameter according to the number of the second-direction sensing lines;

taking the first edge coordinate as a first base coordinate, and adjusting the first base coordinate according to the first
coordinate compensation parameter to obtain a first interpolation coordinate when a first edge of the touch panel is touched;
and

taking the second edge coordinate as a second base coordinate, and adjusting the second base coordinate according to the second
coordinate compensator parameter to obtain a second interpolation coordinate when the first edge or a second edge of the touch
panel is touched,

wherein the touch panel further comprises a first dummy line and a second dummy line, the first dummy line and the second
dummy line are physical sensing lines and arranged on an edge region of the touch panel, the first dummy line and the second
dummy line respectively comprise a first part and a second part, and the coordinate algorithm further comprises:

scaling the first interpolation coordinate according to an area difference between the touched first-direction sensing line
and the first part of the first dummy line or the first part of the second dummy line; and

scaling the second interpolation coordinate according to an area difference between the touched second-direction sensing line
and the second part of the first dummy line or the second part of the second dummy line.

US Pat. No. 9,627,337

INTEGRATED CIRCUIT DEVICE

Novatek Microelectronics ...

1. An integrated circuit device, comprising:
a semiconductor substrate;
a first bonding pad structure, disposed on a surface of the semiconductor substrate and exposed outside of the semiconductor
substrate;

a second bonding pad structure, disposed on the surface of the semiconductor substrate and exposed outside of the semiconductor
substrate; and

an internal bonding wire, wherein the first bonding pad structure is electrically coupled to the second bonding pad structure
via the internal bonding wire.

US Pat. No. 9,152,157

FAST RESPONSE CURRENT SOURCE

Novatek Microelectronics ...

1. A fast response current source, comprising:
a constant current generating block, coupled to a first feedback terminal, for providing a first constant current to flow
through the first feedback terminal;

a first feedback capacitor, coupled between an output terminal and the first feedback terminal, for coupling a voltage variation
of the output terminal to the first feedback terminal when a voltage of the output terminal has one of a rising variation
and a falling variation;

a first current buffer, coupled to the first feedback terminal, for generating a first buffering current to flow through the
first feedback terminal, and changing a current value of the first buffering current in response to a corresponding current
variation of the first feedback terminal when the voltage at the output terminal has the falling variation; and

a first output current generating block, coupled to the first current buffer, for generating a first output current to flow
through the output terminal, and changing a current value of the first output current in response to a corresponding variation
of the first buffering current, wherein when the voltage at the output terminal has the falling variation, the first buffering
current is increased, and the first output current is increased according to the increasing of the first buffering current.

US Pat. No. 9,800,265

DATA SERIALIZATION CIRCUIT

Novatek Microelectronics ...

1. A data serialization circuit, comprising:
a delay circuit comprising a plurality of delay stages, receiving an input clock signal and generating a plurality of delayed
clock signals, the delay stages comprising a first delay stage and a second delayed stage prior to the first delay stage,
and the delayed clock signals comprising a first delayed clock signal generated by the first delay stage and a second delayed
clock signal generated by the second delay stage;

a data serializer, coupled to the delay circuit, receiving parallel data and a final stage delayed clock signal of the delayed
clock signals, and converting the parallel data into serial data according to the final stage delayed clock signal; and

a first data sampler and a second data sampler, coupled in series, and coupled to the delay circuit and the data serializer,
wherein, the first data sampler samples the serial data according to the first delayed clock signal to generate a first output
serial data, and the second data sampler samples the first output serial data according to the second delayed clock signal
to generate a second output serial data.

US Pat. No. 9,787,995

SOURCE DRIVER, DRIVING CIRCUIT AND DISPLAY APPARATUS

Novatek Microelectronics ...

1. A source driver, comprising:
a decompressor, receiving a compressed image data and performing a decompression on the compressed image data in order to
provide a restored image data, wherein the restored image data comprises a plurality of display data;

a plurality of data latch units, configured to latch the display data and sequentially provide the display data; and
a digital-to-analog converter, configured to sequentially receive the display data in order to convert the display data from
a digital format into an analog format, so as to sequentially generate a plurality of analog output signals,

wherein the data latch units comprise a first latch unit, a second latch unit and a third latch unit, and the display data
of each of the lines among the display data is temporarily stored into one of the first latch unit and the third latch unit
or temporarily stored into both of the first latch unit and the third latch unit after dividing the display data and then
provided to the second latch unit by at least one the first latch unit and the third latch unit.

US Pat. No. 9,698,789

INTEGRATED CIRCUIT

Novatek Microelectronics ...

1. An integrated circuit, comprising:
a pad, configured to transmit a communication signal;
a core circuit, having a communication terminal coupled to the pad, and a power terminal coupled to a system voltage rail;
and

a control circuit, comprising:
an impedance matching component, having a first terminal coupled to the pad;
a first switch, having a first terminal coupled to the system voltage rail, and a second terminal coupled to a second terminal
of the impedance matching component;

a second switch, having a first terminal coupled to a control terminal of the first switch, and a second terminal coupled
to the second terminal of the impedance matching component, and

a third switch, having a first terminal receiving a control signal, and a second terminal coupled to the control terminal
of the first switch,

wherein the third switch is turned off when the second switch is turned on, and the second switch is turned off when the third
switch is turned on.

US Pat. No. 9,531,336

OPERATIONAL AMPLIFIER AND DRIVING CIRCUIT

Novatek Microelectronics ...

1. An operational amplifier, comprising:
an input stage circuit, providing at least one driving voltage according to an input voltage;
an output stage circuit, coupled to the input stage circuit, and having at least one input terminal and an output terminal,
wherein the at least one input terminal receives the at least one driving voltage, and the output terminal provides an output
voltage according to the at least one driving voltage, and the output terminal is coupled to an inverted input terminal of
the input stage circuit; and

a constant-gm circuit, comprising:
a constant-gm switch circuit, coupled to the input stage circuit, and controlling an operation of the constant-gm circuit;
at least one current mirror circuit, coupled to the constant-gm switch circuit; and
a current mirror switch circuit, coupled between the constant-gm switch circuit and the at least one current mirror circuit,
wherein the constant-gm switch circuit allows the at least one current mirror circuit to operate during a transition period
when the at least one driving voltage is transited according to the at least one driving voltage received by the output stage
circuit, so as to provide a compensation current for the input stage circuit,

wherein when the at least one driving voltage is in a non-transition period, the current mirror switch circuit turns off the
at least one current mirror circuit.

US Pat. No. 9,412,323

POWER SAVING METHOD AND RELATED WAVEFORM-SHAPING CIRCUIT

NOVATEK Microelectronics ...

7. A liquid crystal display (LCD) comprising:
a plurality of scan-line groups, wherein each of the scan-line groups comprises a plurality of scan lines, and the scan-line
groups comprises a first scan-line group and a second scan-line group;

a plurality of waveform-shaping circuits for individually performing a waveform-shaping function on each of the scan-line
groups at different time points, wherein each of the waveform-shaping circuits is coupled to one of the scan-line groups,
and the waveform-shaping circuits comprise a first waveform-shaping circuit corresponding to the first scan-line group and
a second waveform-shaping circuit corresponding to the second scan-line group, each of the waveform-shaping circuits comprising:

a waveform-shaping unit for performing the waveform-shaping function; and
a control logic unit coupled to the waveform-shaping unit, for controlling the waveform-shaping unit to perform the waveform-shaping
function,

wherein the control logic unit of the first waveform-shaping circuit controls the waveform-shaping unit of the first waveform-shaping
circuit to disable the waveform-shaping function on the first scan-line group according to a second timing control signal
received by the control logic unit of the first waveform-shaping circuit, the control logic unit of the second waveform-shaping
circuit controls the waveform-shaping unit of the second waveform-shaping circuit to enable the waveform-shaping function
on the second scan-line group according to a first timing control signal received by the control logic unit of the second
waveform-shaping circuit, and the second timing control signal according to which the waveform-shaping function of the first
scan-line group is disabled is transmitted from the first waveform-shaping circuit to the second waveform-shaping circuit
to serve as the first timing control signal according to which the waveform-shaping function of the second scan-line group
is enabled.

US Pat. No. 9,349,332

NON-OVERLAP DATA TRANSMISSION METHOD FOR LIQUID CRYSTAL DISPLAY AND RELATED TRANSMISSION CIRCUIT

NOVATEK Microelectronics ...

1. A non-overlap data transmission method for a liquid crystal display (LCD) comprising:
obtaining an entire frame image data;
dividing the entire frame image data into a plurality of image data segments and individually sending the image data segments
to a plurality of display processing units at the same time, wherein each of the image data segments is sent to one of the
display processing units and image data of each image data segment does not overlap with image data of the other image data
segments; and

mutually sending image data of the image data segments through the display processing units;
wherein the step of mutually sending the image data of the image data segments through the display processing units comprises:
a first display processing unit of the display processing units sending image data of a first image data segment to a second
display processing unit of the display processing units; and

the second display processing unit of the display processing units sending image data of a second image data segment to the
first display processing unit of the display processing unit.

US Pat. No. 9,299,310

LOAD DRIVING APPARATUS AND DRIVING METHOD THEREOF

Novatek Microelectronics ...

1. A load driving apparatus, comprising:
a first driving unit, disposed at a first driving channel, wherein during a channel output period, the first driving unit
outputs a first driving signal to drive one of a first load and a second load;

a second driving unit, disposed at a second driving channel, wherein during the channel output period, the second driving
unit outputs a second driving signal to drive another one of the first load and the second load; and

a circuit switch module, coupled between the first driving channel and the second driving channel, and comprising a plurality
of signal transmitting paths, wherein during a data loading period and a charge sharing period, the circuit switch module
turns on all the signal transmitting paths to achieve a charge sharing effect between the first load and the second load during
the charge sharing period, wherein the circuit switch module comprises:

a first switch, disposed at a first signal transmitting path, wherein a first terminal of the first switch is coupled to the
first driving unit, and a second terminal of the first switch is coupled to the first load;

a second switch, disposed at a second signal transmitting path, wherein a first terminal of the second switch is coupled to
the second driving unit, and a second terminal of the second switch is coupled to the second load;

a third switch, disposed at a third signal transmitting path, wherein a first terminal of the third switch is coupled to the
first driving unit, and a second terminal of the third switch is coupled to the second load;

a fourth switch, disposed at a fourth signal transmitting path, wherein a first terminal of the fourth switch is coupled to
the second driving unit, and a second terminal of the fourth switch is coupled to the first load; and

a fifth switch, having a first terminal and a second terminal, wherein the first terminal of the fifth switch of the first
driving channel is coupled to the first terminals of the first switch and the third switch, the second terminal of the fifth
switch of the first driving channel is coupled to the first driving unit, the first terminal of the fifth switch of the second
driving channel is coupled to the first terminals of the second switch and the fourth switch, and the second terminal of the
fifth switch of the second driving channel is coupled to the second driving unit,

wherein during the data loading period and the charge sharing period, the first switch, the second switch, the third switch,
and the fourth switch are all turned on,

wherein during the data loading period and the charge sharing period, the fifth switches are turned off, such that the first
driving unit and the second driving unit are disconnected from the circuit switch module, and during the channel output period,
the fifth switches are turned on.

US Pat. No. 9,250,801

UNLOCKING METHOD, PORTABLE ELECTRONIC DEVICE AND TOUCH-SENSITIVE DEVICE

Novatek Microelectronics ...

1. An unlocking method for a portable electronic device, wherein the portable electronic device has a touch-sensitive display,
and a user interface is displayed on the touch-sensitive display, the unlocking method comprising:
when the user interface is in a first user interface locking state, respectively displaying at least one unlocking image on
at least one point of the touch-sensitive display;

sensing a touch signal of the touch-sensitive display; and
when at least one click respectively corresponding to the at least one point is detected on the touch-sensitive display, switching
the user interface to a user interface unlocking state;

when the user interface is in a second user interface locking state, respectively displaying at least one another unlocking
image on at least one another point of the touch-sensitive display; and

when at least one click respectively corresponding to the at least one another point is detected on the touch-sensitive display,
switching the user interface to the user interface unlocking state,

wherein a number of the at least one point is different from a number of the at least one another point.

US Pat. No. 9,213,349

BANDGAP REFERENCE CIRCUIT AND SELF-REFERENCED REGULATOR

NOVATEK Microelectronics ...

1. A bandgap reference circuit, comprising:
a dual-output self-referenced regulator, comprising:
a self-biased operational transconductance amplifier, for utilizing an area difference between bipolar junction transistors
of an input pair to generate a first positive temperature coefficient current to bias the input pair, and generating a positive
temperature coefficient control voltage and a negative temperature coefficient control voltage; and

a feedback voltage amplifier, for amplifying the negative temperature coefficient control voltage, and outputting a reference
voltage to the input pair for feedback, to generate a first negative temperature coefficient current; and

a reference generation circuit, for generating a summation voltage or a summation current according to the positive temperature
coefficient control voltage and the negative temperature coefficient control voltage.

US Pat. No. 9,154,759

APPARATUS AND METHOD FOR WHITE BALANCE COMPENSATION OF PIXEL DATA

NOVATEK MICROELECTRONICS ...

1. An image processing apparatus, comprising:
a sample unit for sampling a pixel to obtain a pixel voltage;
an amplifier for amplifying the pixel voltage according to an analog gain;
an analog to digital converter for converting the amplified pixel voltage into digital pixel data, the digital pixel data
including a plurality of first sub-pixel data which are corresponding to different colors; and

a white balance unit for obtaining a plurality of second sub-pixel data from white balance compensating the first sub-pixel
data, the first sub-pixel data being white balance compensated respectively according to the analog gain and a plurality of
white balance gains which correspond to different sub-pixels;

wherein the white balance unit provides a plurality of third sub-pixel data according to the first sub-pixel data and the
white balance gains, and determines, according to the analog gain and a full well level of the pixel, whether to clamp the
third sub-pixel data so as to provide the second sub-pixel data.

US Pat. No. 9,106,189

OPERATIONAL AMPLIFIER CIRCUIT AND METHOD FOR ENHANCING DRIVING CAPACITY THEREOF

Novatek Microelectronics ...

1. An operational amplifier circuit configured for driving a load, the operational amplifier circuit comprising:
an output stage module comprising an output stage operational amplifier and an output stage circuit, and the output stage
operational amplifier comprising a detection circuit, a first current mirror module and a second current mirror module, wherein
the detection circuit is configured to detect a current output voltage and a previous output voltage and enhance a charge
capacity or a discharge capacity of the output stage circuit for the load based on a detection result; and

a pre-stage operational amplifier comprising four output terminals, wherein two of the four output terminals are coupled to
the first current minor module, and the other two of the four output terminals are coupled to the second current minor module.

US Pat. No. 9,093,895

MULTI-POWER DOMAIN OPERATIONAL AMPLIFIER AND VOLTAGE GENERATOR USING THE SAME

NOVATEK MICROELECTRONICS ...

1. A multi-power domain operational amplifier, comprising:
an input stage circuit configured to transform a set of input voltages into a set of input currents in a first power domain;
a power domain transforming circuit configured to transform the set of input currents into a set of output currents in a second
power domain different from the first power domain; and

an active load configured to generate an output voltage according to the set of output currents,
wherein a common mode range of the output voltage is shifted as compared with a common mode range of the set of input voltages;
and

wherein the power domain transforming circuit comprises cascading current buffers each involving a different power domain.

US Pat. No. 9,842,528

DRIVING DEVICE

Novatek Microelectronics ...

1. A driving device, comprising:
a first code mapping circuit, converting a first input code in input data into a first intermediate code according to a first
code-to-code mapping relation;

a first source driving channel, coupled to the first code mapping circuit, and the first source driving channel receiving
the first intermediate code and converting the first intermediate code into a first analog voltage according to a first code-to-voltage
mapping relation;

a second code mapping circuit, converting a second input code in the input data into a second intermediate code according
to a second code-to-code mapping relation which is different from the first code-to-code mapping relation; and

a second source driving channel, coupled to the second code mapping circuit, and the second source driving channel receiving
the second intermediate code and converting the second intermediate code into a second analog voltage according to a second
code-to-voltage mapping relation which is different from the first code-to-voltage mapping relation.

US Pat. No. 9,812,054

DISPLAY DRIVER AND DISPLAY APPARATUS USING SUB-PIXEL RENDERING METHOD

Novatek Microelectronics ...

1. A display driver, configured to drive a display panel, wherein the display panel is configured to display an image frame
in a first display mode or a second display mode, and the display driver comprises:
a first display driving channel, driving the display panel to display the image frame by using a sub-pixel rendering method
in the first display mode; and

a second display driving channel, driving the display panel to display the image frame by using the sub-pixel rendering method
in the second display mode,

wherein the display panel comprises a sub-pixel repeating unit, the sub-pixel repeating unit is repeatedly arranged to form
the display panel, the sub-pixel repeating unit comprises a plurality of pixel units, and each of the pixel units comprises
one to two sub-pixels,

wherein in the second display mode, the second display driving channel drives the sub-pixels on the display panel to display
corresponding grayscales by using a plurality of gamma voltages, and a voltage value of at least one gamma voltage among the
gamma voltages is determined according to at least one ratio relationship, wherein the at least one ratio relationship is
determined according to at least one of quantity ratios occupied by at least one of the sub-pixels in the sub-pixel repeating
unit.

US Pat. No. 9,639,203

TOUCH CONTROL DETECTION SYSTEM, DELTA-SIGMA MODULATOR AND MODULATING METHOD THEREOF

Novatek Microelectronics ...

1. A delta-sigma modulator, comprising:
a quantizer, generating a modulating result signal;
N integrating circuits, coupled in series, a first stage integrating circuit receiving an input signal, an output end of a
Nth stage integrating circuit coupled to an input end of the quantizer, each of the integrating circuits receiving a plurality
of gain parameters, and N being a positive integer,

wherein, the quantizer quantizes a signal on the output end of the Nth stage integrating circuit according to an error signal for generating a modulating result signal, a center frequency of a
noise transfer function of the delta-sigma modulator is adjusted according to the gain parameters for generating the modulating
result signal, and the gain parameters are determined according to a frequency of the input signal; and

a gain parameter generator, receiving the input signal and generating all of the gain parameters according to the frequency
of the input signal,

wherein each of the integrating circuits comprises:
a first buffer, adjusting a signal according to a first gain parameter for generating a first buffer signal;
a first calculation circuit, executing an arithmetic calculation on the first buffer signal, a second buffer signal and a
third buffer signal for generating a first calculation result signal;

a first integrator, receiving the first calculation result signal for performing an integration, so as to generate a first
integration result signal;

a second buffer, adjusting the modulating result signal according to a second gain parameter for generating the second buffer
signal;

a third buffer, adjusting a second integration result signal according to a third gain parameter for generating the third
buffer signal;

a fourth buffer, adjusting the first integration result signal according to a fourth gain parameter for generating a fourth
buffer signal;

a fifth buffer, adjusting the first integration result signal according to a fifth gain parameter for generating a fifth buffer
signal;

a second calculation circuit, executing an arithmetic calculation on the fourth buffer signal and the fifth buffer signal
for generating a second calculation result signal; and

a second integrator, integrating the second calculation result signal to generate the second integration result signal,
wherein the second integration result signal is provided to the next stage integrating circuit or the quantizer.

US Pat. No. 9,536,482

DISPLAY DEVICE AND DRIVING MODULE THEREOF

NOVATEK Microelectronics ...

1. A display device comprising a plurality of sub-pixel groups,
wherein each of the sub-pixel groups comprises:
a first sub-pixel, located at a first column;
a second sub-pixel, located at a second column adjacent to the first column;
a third sub-pixel, located at a third column adjacent to the second column;
a fourth sub-pixel, located at a fourth column adjacent to the third column; and
a fifth sub-pixel, located at the fourth column;
wherein the row of the second sub-pixel overlaps the row of the first sub-pixel;
wherein the row of the third sub-pixel overlaps the row of the first sub-pixel;
wherein the row of at least one of the fourth sub-pixel and the fifth sub-pixel overlaps the row of the first sub-pixel;
wherein a sum of the heights of the fourth sub-pixel and the fifth sub-pixel is smaller than or equal to the height of the
first sub-pixel.

US Pat. No. 9,515,699

DUAL MODE SERIAL TRANSMISSION APPARATUS AND METHOD FOR SWITCHING MODE THEREOF

Novatek Microelectronics ...

1. A dual mode serial transmission apparatus, comprising:
a first current source;
a first inverting circuit, coupled to the first current source, and receiving a mode selecting signal or a first data transmission
signal;

a second inverting circuit, coupled to the first current source, and receiving the mode selecting signal or a second data
transmission signal;

a second current source; and
a differential pair, having a first and a second load terminals respectively coupled to the first inverting circuit and the
second inverting circuit, a common terminal being coupled to the second current source, and a first and second differential
input terminals receiving the mode selecting signal or respectively receiving the first and second data transmission signals,

wherein when the first and second inverting circuits respectively receive the first and second data transmission signals,
the differential pair receives the mode selecting signal, and when the first and second inverting circuits receive the mode
selecting signal, the differential pair receives the first and second data transmission signals.

US Pat. No. 9,494,959

CURRENT SOURCE FOR VOLTAGE REGULATOR AND VOLTAGE REGULATOR THEREOF

NOVATEK Microelectronics ...

1. A current source for quickly adjusting a first output current comprises:
a constant current generation module, coupled to a control node, for generating a predefined current flowing through the control
node in order to determine a voltage of the control node;

a capacitor, coupled to an output terminal of the current source;
a current variation detection module, coupled between the control node and the capacitor, for generating a variation on the
voltage of the control node via the capacitor when the output terminal of the current source receives an instant current variation;
and

a trans-conductance amplifier, coupled between the control node and the output terminal, for changing a magnitude of the first
output current of the output terminal when the variation on the voltage of the control node is generated;

wherein the output terminal of the current source is coupled to a buffer, in order to control the buffer to output a second
output current.

US Pat. No. 9,471,190

TOUCH PANEL MODULE

Novatek Microelectronics ...

1. A touch panel module, comprising a touch panel area and a non-touch panel area, and the touch panel module comprising:
a touch panel, comprising a plurality of sensing units configured to sense a touch gesture, each of the sensing units comprising
a plurality of first sensing electrodes and a plurality of second sensing electrodes, an electrode area of the first sensing
electrodes increasing along a direction, and an electrode area of the second sensing electrodes decreasing along the direction,
wherein the touch panel is located in the touch panel area, and the touch panel comprises an active area and a non-active
area,

wherein the touch gesture touches the touch panel module to generate a touch area, a ratio of an area of the first sensing
electrodes touched by the touch gesture and the touch area increases along the direction, and the ratio is greater than a
first threshold when the touch gesture moves from the non-active area towards the non-touch panel area along the direction.

US Pat. No. 9,153,188

DRIVING APPARATUS OF DISPLAY WITH PRE-CHARGE MECHANISM

Novatek Microelectronics ...

1. A driving apparatus of a display, comprising:
a digital-to-analog converting (DAC) circuit, for receiving a display data with a digital format, and generating a gray level
voltage according to the display data;

an output buffer circuit, coupled to the DAC circuit, and having an output terminal to output an output signal, the output
buffer circuit receiving the gray level voltage and the output signal and comparing the gray level voltage and the output
signal to generate a comparison result; and

a pre-charge circuit, coupled to the output buffer circuit, and generating a pre-charge output signal to the output terminal
of the output buffer circuit according to a pre-charge enable signal wherein the output buffer circuit does not provide the
comparison result to the pre-charge circuit.

US Pat. No. 10,074,298

IMAGE PROCESSING METHOD AND DISPLAY DEVICE

Novatek Microelectronics ...

1. An image processing method, adapted to a display panel with a display area, the method comprising:analyzing a plurality of original images to be displayed on a plurality of sub-areas in the display area, and determining whether the original image corresponding to each of the sub-areas is still;
when the original image in a current sub-area is determined as still, recording a time length of the original image being still, wherein the current sub-area is one of the sub-areas;
determining processing levels corresponding to a plurality of image processing schemes based on the time length; and
reducing overall or partial luminance (luma) of the original image in the current sub-area by the image processing schemes with the determined processing levels, and displaying a corresponding luma-reduced image on the current sub-area.

US Pat. No. 9,814,133

TOUCH PANEL MODULE AND ELECTROSTATIC DISCHARGING METHOD

Novatek Microelectronics ...

1. A touch panel module, comprising:
a touch panel, comprising one or more conductive electrodes and one or more dummy electrodes, wherein the one or more conductive
electrodes comprise at least one of one or more driving electrodes and one or more sensing electrodes, and the one or more
dummy electrodes are configured to fill areas between the one or more conductive electrodes or areas outside the one or more
conductive electrodes; and

an electrostatic discharge protection circuit, electrically connected to at least one dummy electrode of the one or more dummy
electrodes, and configured to provide an electrostatic discharging path to the at least one dummy electrode,

wherein the electrostatic discharge protection circuit discharges accumulated electrostatic charges of the at least one dummy
electrode through the electrostatic discharging path at all times, or

the electrostatic discharge protection circuit discharges the accumulated electrostatic charges of the at least one dummy
electrode through the electrostatic discharging path when a potential difference between two ends of the electrostatic discharge
protection circuit is greater than a voltage threshold.

US Pat. No. 9,530,377

DISCHARGING CONTROL METHOD, RELATED DRIVING METHOD AND DRIVING DEVICE

NOVATEK Microelectronics ...

1. A discharging control method, for a display system, which comprises a panel with a plurality of pixels and a gate driving
module wherein the gate driving module generates a plurality of gate driving signals according to a gate-high voltage and
a gate-low voltage and the plurality of gate driving signals is switched between the gate-high voltage and the gate-low voltage
in a normal operation period, wherein the display system is drove by a power, for switching the conducting statuses of a plurality
of transistor switches coupled to the plurality of pixels, the discharging control method comprising:
switching the plurality of gate driving signals to the gate-low voltage in a power-off period, wherein the power is turned
off; and

generating at least one raising voltage at a receiving path of the gate-low voltage or a plurality of output paths of the
plurality of gate driving signals, for raising the voltage levels of the plurality of gate driving signals and conducting
the plurality of transistor switches.

US Pat. No. 9,530,231

METHOD FOR GENERATING MASKING IMAGE USING GENERAL POLYGONAL MASK

NOVATEK Microelectronics ...

1. A method for generating a masking image using a general polygonal mask, comprising:
receiving a pixel of a raw image and a polygon vertices array corresponding to a polygonal mask;
determining whether the pixel is inside the polygonal mask;
labeling the pixel to be a masked pixel if the pixel is inside the polygonal mask, or labeling the pixel to be a visible pixel
if the pixel is outside the polygonal mask; and

outputting the masked pixel or the visible pixel to generate the masking image;
wherein determining whether the pixel is inside the polygonal mask comprises:
setting two consecutive vertices of the polygon vertices array to be a start point and a terminal point according to an indication,
wherein the indication is one of numbers from zero to a number of edges of the polygonal mask;

checking if the pixel is bounded by the start and terminal points in a first dimension;
determining if the pixel is at a left side of a first vector according to a cross product and a direction of the first vector
if the pixel is bounded by the start and terminal points in the first dimension;

increasing a count by one if the pixel is at the left side of the first vector;
checking whether relative locations between the pixel and all the edges of the polygonal mask are determined; and
checking if the count is odd to determine whether the pixel is inside the polygonal mask if the relative locations between
the pixel and all the edges of the polygonal mask are checked.

US Pat. No. 9,437,671

POWER AND SIGNAL EXTENDER AND RELATED CIRCUIT BOARD

NOVATEK Microelectronics ...

1. A power and signal extender, on a circuit board, for preventing a power or a signal on the circuit board from influencing
an integrity of a ground plane on the circuit board, the power and signal extender comprising:
a first pin, coupled to a first transmission wire of the circuit board, for receiving the power or the signal from the first
transmission wire; and

a second pin, coupled to a second transmission wire of the circuit board, for outputting the power or the signal to the second
transmission wire;

wherein the circuit board is a double sided board, which comprises:
a first layer, for deploying the first transmission wire and the second transmission wire for transmitting the power or the
signal; and

a second layer, for deploying the ground plane;
wherein the power and signal extender is coupled to the first layer, so that the power or the signal passes through the power
and signal extender rather than passing through the second layer.

US Pat. No. 9,401,114

IMAGE DISPLAY APPARATUS, DISPLAY CONTROL APPARATUS THEREOF, AND SCALER CHIP IMAGE

Novatek Microelectronics ...

1. A display control apparatus, adapted for an image display apparatus, wherein the image display apparatus has a plurality
of display regions, the display regions are respectively corresponding to a plurality of backlight modules, the luminance
of the backlight modules are controlled by the display control apparatus, the display control apparatus comprising:
a backlight control unit, receiving a first image data to generate a plurality of local backlight control signals so as to
control the luminance of the plurality of backlight modules, respectively,

wherein the backlight control unit divides the first image data into a plurality of local image data respectively corresponding
to the plurality of display regions, and the backlight control unit further generates one of the plurality of local backlight
control signals according to a corresponding one of the local image data; and

an image adjusting unit, receiving a plurality of local backlight duty signals respectively corresponding to the plurality
of backlight modules from the backlight control unit, and converts the first image data to a second image data for driving
a display panel according to the plurality of local backlight duty signals,

wherein, the image adjusting unit respectively converts, for each one of a plurality of positions, a first pixel value of
the position in the first image data to be a second pixel value of the position in the second image data according to at least
two of the plurality of local backlight duty signals corresponding to at least two of display regions.

US Pat. No. 9,111,344

IMAGE PROCESSING METHOD AND IMAGE PROCESSING DEVICE THEREOF FOR IMAGE ALIGNMENT

NOVATEK Microelectronics ...

1. An image processing method for image alignment, comprising:
sequentially receiving a plurality of images;
generating at least one threshold corresponding to each image according to a plurality of intensities of each image of the
plurality of images;

converting each image according to the thresholds of each image, for generating a plurality of binary images;
acquiring a plurality of characteristic pixels of each binary image according to the plurality of binary images; and
aligning the plurality of images according to the plurality of characteristic pixels of each binary image.

US Pat. No. 9,048,243

CHIP PACKAGE

Novatek Microelectronics ...

1. A chip package structure, comprising:
a package body, comprising:
a first core circuit comprising at least one first connection terminal thereon;
an electrostatic discharge protection circuit comprising at least one second connection terminal thereon;
at least one third connection terminal; and
at least one interconnection structure electrically connected to the second connection terminal and the third connection terminal;
a first lead configured on the package body and electrically connected to the second connection terminal and an external circuit;
and

a second lead configured on the package body and electrically connecting the first connection terminal and the third connection
terminal,

wherein the second lead and the first lead are separate.

US Pat. No. 9,727,120

DATA COMPRESSION SYSTEM FOR LIQUID CRYSTAL DISPLAY AND RELATED POWER SAVING METHOD

NOVATEK Microelectronics ...

1. A data compression system for a display comprising:
a host, for outputting image data in a first data format or a second data format according to an operation mode of the display,
wherein the image data in the first data format has fewer bit numbers than the image data in the second data format; and

a drive circuit, comprising:
a bypass path, for transmitting the image data according to the operation mode;
a compression unit, coupled to the host, for receiving the image data and performing a compression procedure on the image
data to generate a compression data according to the operation mode;

a storage unit, coupled to the compression unit, for storing the compression data and the image data;
a de-compression unit, coupled to the storage unit, for receiving the compression data and performing a de-compression procedure
on the compression data to recover the image data according to the operation mode; and

a display unit, for displaying the image data;
wherein when the operation mode is a particular mode, the host outputs the image data in the first data format and the bypass
path transmits the image data in the first data format to the storage unit so as to bypass the compression unit and the de-compression
unit, and when the operation mode is a general mode, the host outputs the image data in the second data format and the bypass
path does not transmit the image data.

US Pat. No. 9,697,780

LCD DEVICE WITH IMAGE DITHERING FUNCTION AND RELATED METHOD OF IMAGE DITHERING

NOVATEK MICROELECTRONICS ...

1. A liquid crystal display (LCD), comprising:
a data source, for generating N-bit pixel data, N being a positive integer;
a digital gamma correction unit, coupled to the data source, for performing digital gamma correction on the pixel data to
generate (N+M)-bit digital gamma correction pixel data whose mantissa is the lowest K bits of the (N+M) bits, K and M being
positive integers;

an image-dithering unit, coupled to the digital gamma correction unit, for performing image-dithering on the digital gamma
correction pixel data to generate a plurality of (N+M?K)-bit dithering compensation pixel data in consecutive frames wherein
in generating the (N+M?K)-bit dithering compensation pixel data in the consecutive frames, the K-bit mantissa is removed from
the (N+M)-bit digital gamma correction pixel data and added to the (N+M?K)-bit dithering compensation pixel data of at least
one frame of the consecutive frames for compensating the plurality of (N+M?K)-bit dithering compensation pixel data of the
consecutive frames; and

a converter, coupled to the image-dithering unit, for converting the dithering compensation pixel data into an output image,
wherein a bit number of the converter is lower than a bit number of the digital gamma correction unit.

US Pat. No. 9,613,409

IMAGE CONVERTING METHOD AND RELATED IMAGE CONVERTING MODULE

NOVATEK Microelectronics ...

1. An image converting method for a display device, comprising:
calculating, by a computing module of the display device, a plurality of segment averages of pixel values in a plurality segments
of an input image of a low dynamic range of luminance;

acquiring, by the computing module of the display device, the maximum among the plurality of segment averages as a first threshold;
calculating, by the computing module of the display device, a plurality of local averages of pixel values in adjacent segments
of the input image;

acquiring, by the computing module of the display device, the maximum among the plurality of local averages as a second threshold;
counting, by the computing module of the display device, the number of pixel values exceeding the first threshold in the plurality
of segments as a plurality of first pixel counts and counting the number of pixel values exceeding the second threshold in
the plurality of segments as a plurality of second pixel counts;

generating, by the computing module of the display device, a specular map and a confidence according to the plurality of first
pixel counts and the plurality of second pixel counts;

mapping, by the computing module of the display device, the input image according to the specular map, to generate an intermediate
image of a high dynamic range of luminance;

blending, by the computing module of the display device, the input image and the intermediate image according to the confidence,
to generate an output image, wherein the ratio between the input image and the intermediate image is determined by the confidence,
and

displaying, by the display device, the output image.

US Pat. No. 9,569,989

PANEL DRIVER IC AND COOLING METHOD THEREOF

Novatek Microelectronics ...

1. A panel driver integrated circuit (IC), comprising:
a data encoder receiving an original data and selectively performing an encoding operation, wherein the encoding operation
changes the original data to serve as an output data of the data encoder according to a data mapping table;

a level shifter having an input terminal coupled to the data encoder to receive the output data;
a digital-to-analog converter (DAC) having a data input terminal coupled to an output terminal of the level shifter;
a rearrangement circuit having a plurality of output terminals coupled to a plurality of reference voltage input terminals
of the DAC to provide a plurality of reference voltages, wherein the rearrangement circuit rearranges an order of the reference
voltages according to the encoding operation of the data encoder; and

an output buffer having an input terminal coupled to an output terminal of the DAC.

US Pat. No. 9,197,464

RECEPTION CIRCUIT

NOVATEK Microelectronics ...

1. A reception circuit, capable of enhancing accuracy of signal reception, comprising:
a variable termination resistance unit, coupled to at least one channel, for utilizing at least one termination resistance
corresponding to the at least one channel to perform impedance matching;

a receiver, coupled to the at least one channel, for receiving a calibration signal to generate a digital calibration signal;
and

a data determination control unit, for comparing the digital calibration signal with a predefined data, to adjust the at least
one termination resistance.

US Pat. No. 9,753,578

TOUCH SENSING METHOD CAPABLE OF DYNAMICALLY ADJUSTING TOUGH THRESHOLD VALUE

Novatek Microelectronics ...

1. A touch sensing method, adapted to a touch panel, and the touch sensing method comprising:
receiving a plurality of sensing values of a plurality of sensing points to calculate a plurality of sensing difference values
according to the sensing values;

determining a touch threshold value from at least two different touch threshold values after receiving a first sensing difference
value each time, which are time-independent parameters, according to a comparison result, wherein the comparison result is
generated by comparing the first sensing difference value with a predetermined value, and the first sensing difference value
is determined from the sensing difference values; and

comparing the sensing difference values with the touch threshold value, and determining which one in the sensing points is
touched according to a second comparison result, and

increasing the touch threshold value when a maximum sensing difference value of the sensing difference values is greater than
the predetermined value,

and decreasing the touch threshold value when a maximum sensing difference value of the sensing difference values is smaller
than the predetermined value.

US Pat. No. 9,626,925

SOURCE DRIVER APPARATUS HAVING A DELAY CONTROL CIRCUIT AND OPERATING METHOD THEREOF

Novatek Microelectronics ...

1. A source driver apparatus for driving a plurality of source lines of a display panel, the display panel further comprising
a gate driver apparatus, the source driver apparatus comprising:
a plurality of driving channels, configured to output a plurality of source driving signals; and
a delay control circuit, configured to control the driving channels to change delay times of the source driving signals within
a period, such that the delay times of the source driving signals correspond to distances from the source lines to the gate
driver apparatus,

wherein a first detection terminal and a second detection terminal of the delay control circuit are respectively coupled to
a first position and a second position on a dummy gate line of the display panel to detect a timing of a gate driving signal
at the first position and the second position, and the delay control circuit determines the delay times of the source driving
signals according to the timing of the gate driving signal at the first position and the second position.

US Pat. No. 9,570,990

KNEE VOLTAGE DETECTOR

NOVATEK Microelectronics ...

1. A knee voltage detector, for a flyback converter, comprising:
a delay unit, for delaying an auxiliary related voltage of an auxiliary winding of the flyback converter for a specific period,
to generate a delay signal;

a subtracting unit, for generating a subtracting signal according to the auxiliary related voltage and the delay signal;
a comparing unit, for generating a sampling signal when the subtracting signal indicates that a voltage difference between
the auxiliary related voltage and the delay signal is greater than a threshold value; and

a sample and hold unit, for sampling the delay signal to generate a knee voltage according to the sampling signal when the
voltage difference between the auxiliary related voltage and the delay signal is greater than the threshold value.

US Pat. No. 9,542,872

DATA DRIVER FOR ELECTROPHORETIC DISPLAY

NOVATEK MICROELECTRONICS ...

1. A data driver for an electrophoretic display (EPD), comprising a plurality of driver sub-circuits, each of the driver sub-circuits
driving a pixel column of the EPD in a driving period via a driver end; wherein each of the driver sub-circuits comprises:
an output node;
a first latch and a second latch, for respectively storing updated latch image data and current latch image data in response
to original image data, the second latch further providing the current latch image data to the output node, the updated latch
image data and the current latch image data each selectively corresponding individually to one of a positive reference level,
a negative reference level and a ground reference level;

a multiplexer, coupled to a first capacitor, a second capacitor, the output node and the driver end; and
a comparator, dividing the driving period into a first period, a second period and a third period, wherein when the updated
latch image data and the current latch image data selectively correspond to different levels, the comparator controls the
multiplexer to selectively couple one of the first and second capacitors to the driver end in the first period to recycle
charges at the pixel column into the coupled one of the first and second capacitors, and to selectively couple said one of
the first and second capacitors to the driver end in the second period to pre-charge or pre-discharge the pixel column with
the recycled charges in the coupled one of the first and second capacitors,

wherein when the current latch image data correspond to the positive reference level, and the updated and current latch image
data correspond to different levels, the comparator controls the multiplexer to couple the first capacitor to the driver end
in the first period to recycle positive charges at the pixel column to the first capacitor.

US Pat. No. 9,537,487

DATA CONTROL CIRCUIT

Novatek Microelectronics ...

1. A data control circuit comprising:
an output stage circuit outputting a data signal, wherein the output stage circuit comprises a first n-type transistor and
a first p-type transistor, a source terminal of the first n-type transistor being coupled to a ground voltage, a gate terminal
of the first n-type transistor being coupled to an input terminal of the output stage circuit, a gate terminal of the first
p-type transistor being coupled to the gate terminal of the first n-type transistor, a drain terminal of the first p-type
transistor being coupled to an output terminal of the output stage circuit, a source terminal of the first p-type transistor
being coupled to a system voltage;

a switch circuit, an input terminal of the switch circuit being coupled to an output terminal of the output stage circuit,
an output terminal of the switch circuit being coupled to a post-stage circuit, wherein the switch circuit determines whether
to transmit the data signal of the output stage circuit to the post-stage circuit according to a control signal; and

an impedance module configured in the output stage circuit for reducing noise flowing from the switch circuit to the output
stage circuit, wherein when the impedance module is formed by a transistor, the transistor has a first terminal coupled to
a drain terminal of the first n-type transistor, a second terminal coupled to the output terminal of the output stage circuit,
and a gate terminal coupled to a fixed voltage turning on the transistor.

US Pat. No. 9,459,647

BANDGAP REFERENCE CIRCUIT AND BANDGAP REFERENCE CURRENT SOURCE WITH TWO OPERATIONAL AMPLIFIERS FOR GENERATING ZERO TEMPERATURE CORRELATED CURRENT

NOVATEK Microelectronics ...

1. A bandgap reference circuit with reduced layout area and reduced power consumption, comprising:
a first bipolar junction transistor, comprising a first terminal and a second terminal coupled to a ground;
a first resistor, for generating a proportional to absolute temperature current;
a second bipolar junction transistor, comprising a first terminal coupled to the first resistor, and a second terminal and
a third terminal coupled to the ground;

a second resistor, having a resistance at a specific ratio to a resistance of the first resistor, for generating a complementary
to absolute temperature current;

a first operational amplifier, comprising a first input terminal coupled to a third terminal of the first bipolar junction
transistor, and a second input terminal coupled to the first resistor;

a second operational amplifier, comprising a first input terminal coupled to the third terminal of the first bipolar junction
transistor, and a second input terminal coupled to the second resistor; and

a zero temperature correlated current generator, for summing the proportional to absolute temperature current and the complementary
to absolute temperature current to generate a zero temperature correlated current;

wherein each of the first operational amplifier and the second operational amplifier does not comprise an input pair of N-type
metal oxide semiconductor transistors and comprises an input pair of P-type metal oxide semiconductor transistors and a folded
cascode structure for adapting a wide range of a system voltage, and the input pair of P-type metal oxide semiconductor transistors
receives input voltages from outside of the each of the first operational amplifier and the second operational amplifier;

wherein the power consumption of the first bipolar junction transistor and the second bipolar junction transistor is reduced
by applying the input pair of P-type metal oxide semiconductor transistors and the folded cascode structure.

US Pat. No. 9,323,782

MATCHING SEARCH METHOD AND SYSTEM

NOVATEK Microelectronics ...

1. A matching search method for a stereo matching system, the matching search method comprising:
generating a plurality of offset image blocks by shifting a first image block by a plurality of offset values, wherein the
first image block is a part of a first image captured at a right view or a left view to an object and each of the offset image
blocks comprises a partial of the first image block and predetermined image data;

comparing each of the offset image blocks to a second image block, which is a part of a second image captured at the other
side of view to the object with respect to the first image, so as to determine, from the offset image blocks, a first offset
image block which is the most similar to the second image block;

obtaining a global offset of the first image block relative to the second image block, wherein the global offset is the offset
of the most similar first offset image block relative to the second image block;

performing a matching search for the first offset image block relative to the second image block to generate a matching search
result; and

obtaining disparity information according to the matching search result and the global offset.

US Pat. No. 9,229,677

CONTROL SYSTEM WITH SERIAL INTERFACE

Novatek Microelectronics ...

1. A control system with a serial interface, comprising:
a non-transitory programmable database, wherein a data is written into the non-transitory programmable database through a
programming method;

a first driver, directly coupled to the non-transitory programmable database via the serial interface;
at least one second driver, coupled with the first driver; wherein the first driver and the second driver are LCD drivers;
and

a controller, directly coupled with the non-transitory programmable database and the first driver via the serial interface,
wherein the controller captures the data from the non-transitory programmable database through the serial interface and adjusts
parameters of the first driver and the at least one second driver according to the data, wherein the non-transitory programmable
database has a first pin and a second pin, and the first driver has a third pin and a fourth pin, wherein the first pin is
coupled with the third pin via the serial interface, and the second pin is coupled with the fourth pin via the serial interface,
wherein the controller is coupled with the first pin of the non-transitory programmable database via the serial interface
and coupled with the second pin of the non-transitory programmable database via the serial interface, and the controller controls
the second driver through the first driver.

US Pat. No. 9,792,843

LOAD DRIVING APPARATUS AND GRAYSCALE VOLTAGE GENERATING CIRCUIT

NOVATEK MICROELECTRONICS ...

1. A grayscale voltage generating circuit, comprising:
a plurality of gamma resistor strings, generating a plurality of grayscale voltages according to a plurality of driving signals;
and

a plurality of the load driving apparatus, configured to receive different gamma voltages, and generate the plurality of driving
signals according to the different gamma voltages,

wherein the plurality of load driving apparatus output the plurality of driving signals to one of the gamma resistor strings
according to a selection signal, such that the one of the gamma resistor strings generates the grayscale voltages,

wherein the plurality of load driving apparatus respectively comprising:
an output stage module, comprising a plurality of output stages, and each of the output stages comprises a plurality of transistors,
wherein each of the output stages is coupled to a corresponding one of the loads through the plurality of transistors;

a load driving module, configured to provide the plurality of driving signals; and
an output stage selection module, coupled between gates of the transistors of the output stage module and the load driving
module, wherein the load driving module outputs the plurality driving signals to the output stage selection module, and the
output stage selection module selects one of the output stages according to the selection signal, such that the load driving
module drives the load coupled to the selected output stage through the selected output stage,

wherein the output stage selection module respectively bypasses the plurality of driving signals to the gates of the transistors
of the selected output stage, and does not bypass any of driving signals to the un-selected output stages.

US Pat. No. 9,787,937

DISPLAY APPARATUS FOR VIDEO WALL AND OPERATION METHOD THEREOF

Novatek Microelectronics ...

1. A display apparatus, comprising:
a video input connector, configured to receive a video frame signal of a video source;
a video output connector;
a display panel;
a memory circuit, configured to store extended display identification data (EDID), wherein resolution information of the EDID
affects a resolution of the video frame signal of the video source; and

a video processing circuit, coupled to the video input connector, the video output connector, the memory circuit and the display
panel, and configured to adaptively change the resolution information of the EDID in the memory circuit based on a video wall
configuration parameter,

wherein the video processing circuit resets the resolution information of the EDID in the memory circuit as a default resolution
adapted to the display panel when the video processing circuit determines that the display apparatus is not a first display
apparatus of a video wall based on the video wall configuration parameter, wherein a video wall resolution adapted to the
video wall is greater than the default resolution.

US Pat. No. 9,749,004

TRANSCEIVER AND OPERATION METHOD THEREOF

Novatek Microelectronics ...

1. A transceiver, comprising:
a transmitter, configured to receive an output reference signal to provide an output signal to a signal channel; and
a receiver, coupled to the signal channel to receive a receiving reference signal, so as to provide a receiving signal, wherein
the receiver comprises:

a comparator unit, configured to compare a first signal and a second signal to obtain the receiving signal; and
a signal adjusting unit, coupled between the output reference signal, the receiving reference signal, and the comparator unit
to adjust a voltage level of at least one of the output reference signal and the receiving reference signal, thereby obtaining
the first signal and the second signal, wherein the first signal is the output reference signal or the output reference signal
with an adjusted voltage level, and the second signal is the receiving reference signal or the receiving reference signal
with an adjusted voltage level.

US Pat. No. 9,400,310

ELECTRONIC DEVICE WITH CHIP-ON-FILM PACKAGE

Novatek Microelectronics ...

1. An electronic device with chip-on-film package, comprising:
a flexible substrate at least comprising a non-cutting-out area and a cutting-out area;
a core circuit unit disposed in the non-cutting-out area;
multiple switching elements comprising a first switching element and a second switching element, wherein a first terminal
of the first switching element is electrically connected to a first output terminal of the core circuit unit, and a first
terminal of the second switching element is electrically connected to a second output terminal of the core circuit unit;

multiple output pads disposed in the non-cutting-out area, wherein the multiple output pads comprise a first output pad and
a second output pad, the first output pad is electrically connected to a second terminal of the first switching element, the
first output pad is electrically connected to the first output terminal of the core circuit unit through the first switching
element when the first switching element is turned on, the second output pad is electrically connected to a second terminal
of the second switching element, and the second output pad is electrically connected to the second output terminal of the
core circuit unit through the second switching element when the second switching element is turned on; and

a common test pad disposed in the cutting-out area, wherein the common test pad is electrically connected to the output pads,
the common test pad is electrically connected to the first output terminal of the core circuit unit through the first output
pad and the first switching element when the first switching element is turned on, and the common test pad is electrically
connected to the second output terminal of the core circuit unit through the second output pad and the second switching element
when the second switching element is turned on;

wherein, in a test stage, the switching elements are sequentially turned on in different time such that one of multiple output
signals of the core circuit unit is transmitted to the common test pad.

US Pat. No. 9,299,285

TIMING SCRAMBLING METHOD AND TIMING CONTROL CIRCUIT THEREOF

NOVATEK Microelectronics ...

1. A timing scrambling method, for a timing control device corresponding to a plurality of source driving devices, the timing
scrambling method comprising:
selecting a first timing scrambling signal of a first scrambling generating unit among a plurality of scrambling generating
units in a first period of a clock signal as a scrambling input signal;

selecting a second timing scrambling signal of a second scrambling generating unit among the plurality of scrambling generating
units in a second period of the clock signal as the scrambling input signal, wherein the second period is subsequent to the
first period; and

generating scrambling data for the plurality of source driving devices according to the scrambling input signal and source
driving data of the corresponding source driving device.

US Pat. No. 9,800,800

VIDEO TRANSMISSION SYSTEM

NOVATEK MICROELECTRONICS ...

1. A video transmission system, comprising:
a multi-drop bus, comprising at least one first transmission line and at least one second transmission line;
a timing controller;
a first source driving chip, coupled to the timing controller via the at least one first transmission line of the multi-drop
bus and comprising:

a first source driving circuit,
and
a first terminal circuit embedded in the first source driving chip and coupled to the multi-drop bus and the first source
driving circuit for providing a first terminal resistor with a first adjustable resistance that is set in response to a first
setting command output by the timing controller during a first setting period, wherein the first setting period is before
a first transfer period during which the timing controller transfers first video data to the first source driving circuit;
and

a second source driving chip, coupled to the timing controller via the at least one second transmission line of the multi-drop
bus and comprising:

a second source driving circuit; and
a second terminal circuit embedded in the second source driving chip and coupled to the multi-drop bus and the second source
driving circuit for providing a second terminal resistor with a second adjustable resistance that is set in response to a
second setting command output by the timing controller during a second setting period, the second setting period being before
a second transfer period during which the timing controller transfers second video data to the second source driving circuit,
wherein the first adjustable resistance and the second adjustable resistance are set for impedance matching with the at least
one first transmission line and the at least one second transmission line.

US Pat. No. 9,787,952

COLOR FILTER ARRAY AND MANUFACTURING METHOD THEREOF

NOVATEK Microelectronics ...

1. A color filter array for an image sensing device, the color filter array comprising:
a plurality of pixels, for generating a plurality of pixel data of an image; and
a control unit, for controlling the plurality of pixels;
wherein each of the plurality of pixels is divided into a plurality of sub-pixels corresponding to the same color;
wherein each of the plurality of pixels accumulates pixel value of at least one of the plurality of sub-pixels in each of
the plurality of pixels as the pixel data outputted by each of the plurality of pixels;

wherein the plurality of sub-pixels in a first pixel of the plurality of pixel is corresponding to a first pixel color, and
at least one of the plurality of sub-pixels in the first pixel is altered to be corresponding to a second pixel color;

wherein the first color is different from the second pixel color.

US Pat. No. 9,772,756

DISPLAY DRIVER AND METHOD FOR ADJUSTING COLOR TEMPERATURE OF IMAGE

Novatek Microelectronics ...

1. A display driver, configured to drive a display panel to display an image, and comprising:
an interpolation operation circuit, configured to receive two gamma reference curves, and perform an interpolation operation
on the two gamma reference curves to generate a plurality of gamma curves;

a gamma circuit, electrically connected to the interpolation operation circuit, and configured to select one of the generated
gamma curves based on a user selection signal, and drive the display panel to display the image based on the selected gamma
curve, so as to adjust a color temperature of the image based on the user selection signal, wherein color temperatures of
the generated gamma curves are distinct, and the generated gamma curves have the same gamma value; and

a selector circuit, electrically connected to the interpolation operation circuit, and configured to select at least one gamma
reference curve from a plurality of preset gamma curves for the two gamma reference curves based on a gamma selection signal,
and output the at least one gamma reference curve selected by the selector circuit to the interpolation operation circuit,

wherein the preset gamma curves comprise two gamma curves, and a color temperature of one of the two gamma curves is greater
than a color temperature of another one of the two gamma curves, wherein the selector circuit selects the two gamma curves
for the two gamma reference curves based on the gamma selection signal.

US Pat. No. 9,691,355

METHOD OF READING DATA, METHOD OF TRANSMITTING DATA AND MOBILE DEVICE THEREOF

NOVATEK Microelectronics ...

1. A method of reading data for a display drive integrated circuit (IC) of a panel of a mobile device, comprising:
receiving a plurality of write formats and a plurality of image packets, wherein each of the write formats is associated with
one of the image packets, and each of the image packets corresponds to one display line of a plurality of display lines of
the panel, wherein a processor of the mobile device uses a command mode to transmit the write format and the at least one
image packet to the display drive IC, wherein each of at least one of the write formats indicates respective information for
the display line corresponding to the image packet associated with the write format; and

generating a synchronization signal according to the respective information indicated by the write format for displaying at
least one of the display lines of the panel.

US Pat. No. 9,608,022

COLOR FILTER ARRAY AND IMAGE RECEIVING METHOD THEREOF

NOVATEK Microelectronics ...

1. A color filter array, for an image sensing device, the color filter array comprising a plurality of filter patterns, wherein
each filter pattern comprises:
at least one first filter, corresponding to a first wavelength range of a first color;
at least one second filter, corresponding to a second wavelength range of a second color;
at least one third filter, corresponding to a third wavelength range of a third color;
at least one fourth filter, corresponding to a first infrared wavelength range, wherein the first infrared wavelength range
is an intersection of the first wavelength range and the second wavelength range; and

at least one fifth filter, corresponding to a second infrared wavelength range, wherein the second infrared wavelength range
is an intersection of the first wavelength range and the third wavelength range;

wherein the at least one second filter comprises the second filter located at a first row and a first column and the second
filter located at a second row adjacent to the first row and the first column; the at least one fourth filter comprises the
fourth filter located at the first row and a second column adjacent to the first column; the at least one fifth filter comprises
the fifth filter located at the second row and the second column; the at least one third filter comprises the third filter
located at the first row and a third column adjacent to the second column; and the at least one first filter comprises the
first filter located at the second row and the third column.

US Pat. No. 9,543,285

DISPLAY PANEL

Novatek Microelectronics ...

1. A display panel, comprising:
a plurality of sub-pixel groups, arranged repeatedly to form a pixel array, each of the sub-pixel groups comprising a plurality
of first pixel units, a plurality of second pixel units and a plurality of third pixel units, wherein each of the first pixel
units comprises a first color sub-pixel and a second color sub-pixel, each of the second pixel units comprises the second
color sub-pixel and a third color sub-pixel, and each of the third pixel units comprises the first color sub-pixel and the
third color sub-pixel, and the first color sub-pixel, the second color sub-pixel and the third color sub-pixel are sub-pixels
having three different colors,

wherein at least a part of the first pixel units are arranged along a first direction, at least a part of the second pixel
units are arranged along the first direction, and the first direction is tilted relative to a column direction of the pixel
array.

US Pat. No. 9,411,354

DEVICE AND MODULE OF TRIGGERING AND GENERATING TEMPERATURE COEFFICIENT CURRENT

NOVATEK Microelectronics ...

1. A device of triggering and generating temperature coefficient current, for generating a temperature coefficient current,
the device comprising:
a positive temperature coefficient current generating unit, for generating a first positive temperature coefficient current;
a negative temperature coefficient current generating unit, for generating a first negative temperature coefficient current;
and

a triggering unit, for triggering to generate the temperature coefficient current according to a triggering temperature and
a current difference between the first positive temperature coefficient current and the first negative temperature coefficient
current;

wherein the triggering unit triggers to generate the temperature coefficient current having a negative temperature coefficient
when an environment temperature is less than the triggering temperature;

wherein the positive temperature coefficient current generating unit comprises a first transistor of a first current mirror,
and the first transistor comprises a gate, a drain and a source, wherein the gate is coupled to a gate of a second transistor
of the first current mirror, for generating the first positive temperature coefficient current according to a second positive
temperature coefficient current outputted by the second transistor;

wherein the negative temperature coefficient current generating unit comprises:
a third transistor, belonging to a second current mirror, comprising a gate, a drain and a source, the gate coupled to a gate
of a fourth transistor of the second current mirror, for generating a third negative temperature coefficient current according
to a second negative temperature coefficient current outputted by the fourth transistor; and

a third current mirror, comprising:
a fifth transistor, comprising a gate, a drain and a source, the gate coupled to the drain, the drain coupled to the drain
of the third transistor, for receiving the third negative temperature coefficient current at the drain; and

a sixth transistor, comprising a gate, a drain and a source, the gate coupled to the fifth transistor of the gate, the drain
coupled to the first transistor of the drain, for draining the first negative temperature coefficient current at the drain
according to the third negative temperature coefficient current received by the fifth transistor.

US Pat. No. 9,177,507

INTENSITY COMPENSATION METHOD AND DISPLAY CONTROL DEVICE AND IMAGE DISPLAY DEVICE APPLYING THE SAME

Novatek (Shanghai) Co., L...

1. An intensity compensation method for a display control device of an image display device, comprising:
obtaining a plurality of backlight duty cycles, or a plurality of backlight intensities, of a plurality of backlight sources
according to a plurality of image intensities for an image data;

obtaining a plurality of compensation gains for a plurality of pixels with respect to the image data, according to a plurality
of respective actual backlight intensities, wherein each respective actual backlight intensity is corresponding to one of
the pixels of the image data and is determined based on:

at least two of the backlight duty cycles, which are respectively corresponding to a first backlight source and a second backlight
source at least, of the backlight sources, and

a plurality of backlight intensities corresponding to the pixels, which are measured when the first and the second backlight
sources are respectively turned on with corresponding backlight duty cycles; and

compensating a plurality of first image intensities corresponding to the plurality of pixels of the image data according to
the plurality of compensation gains, to obtain a plurality of second image intensities.

US Pat. No. 9,588,880

ADAPTIVE ADDRESS TRANSLATION METHOD FOR HIGH BANDWIDTH AND LOW IR CONCURRENTLY AND MEMORY CONTROLLER USING THE SAME

NOVATEK MICROELECTRONICS ...

1. An adaptive memory address translation method, comprising:
receiving a plurality of request instructions, wherein a memory address corresponding to each of the request instructions
comprises a bank address;

analyzing the memory addresses corresponding to the request instructions to obtain a translation frequency of each bit in
the memory addresses, wherein the translation frequency of each bit represents how frequent the bit changes value in the memory
addresses;

determining a linear translation formula according to the obtained translation frequency of bits in the memory addresses;
performing a first translation of the memory addresses corresponding to the request instructions according to the linear translation
formula, such that the number of identical bank addresses between two adjacent request instructions is fewer than that before
the first translation; and

utilizing a numerical translation mechanism to perform a second translation of the memory addresses corresponding to the request
instructions, such that the memory addresses corresponding to the any two adjacent request instructions have fewer different
bits than those before the second translation.

US Pat. No. 10,121,777

SILICON CONTROLLED RECTIFIER

Novatek Microelectronics ...

1. A silicon controlled rectifier comprising:a semiconductor substrate comprising silicon of a first conductivity type;
first and second semiconductor wells formed in the semiconductor substrate, and respectively comprising silicon of a second conductivity type and silicon of the first conductivity type;
first and second semiconductor regions respectively formed in the first and the second semiconductor wells in spaced apart relation, and respectively comprising silicon of the first conductivity type and silicon of the second conductivity type;
third and fourth semiconductor regions respectively formed in the first and the second semiconductor wells, and respectively comprising silicon of the second conductivity type and silicon of the first conductivity type, wherein the third semiconductor region directly contacts with the fourth semiconductor region;
a silicide layer formed on the third and the fourth semiconductor regions, wherein the silicide layer extends from the third semiconductor region to the fourth semiconductor region;
a first insulating region formed in the first semiconductor well and located between the first and the third semiconductor regions; and
a second insulating region formed in the second semiconductor well and located between the second and the fourth semiconductor regions,
wherein the first insulating region and the second insulating region directly contact with two sides of the silicide layer.

US Pat. No. 9,773,147

FINGERPRINT ENROLLMENT METHOD AND APPARATUS USING THE SAME

Novatek Microelectronics ...

1. A fingerprint enrollment method adapted for a fingerprint enrollment apparatus comprising a processing unit, the fingerprint
enrollment method comprises:
capturing a first fingerprint image and a second fingerprint image by a fingerprint sensor;
extracting, by the processing unit, a minutiae feature and a pore feature of the first fingerprint image to obtain a first
template;

extracting, by the processing unit, a minutiae feature and a pore feature of the second fingerprint image to obtain a second
template;

calculating, by the processing unit, a minutiae matching score between the minutiae feature of the first template and the
minutiae feature of the second template;

stitching, by the processing unit, the first template and the second template by utilizing a matching relation between the
minutiae feature of the first template and the minutiae feature of the second template when the minutiae matching score is
greater than a first threshold; and

stitching, by the processing unit, the first template and the second template by utilizing a matching relation between the
pore features of the first template and the pore features of the second template and utilizing the matching relation between
the minutiae feature of the first template and the minutiae feature of the second template when the minutiae matching score
is between the first threshold and a second threshold, wherein the second threshold is less than the first threshold.

US Pat. No. 9,659,222

VEHICLE EVENT DATA RECORDER AND OPERATION METHOD THEREOF

Novatek Microelectronics ...

1. A vehicle event data recorder, comprising:
a photography module, configured to capture a scene and output an original video frame;
a first image-processing circuit, coupled to the photography module to directly receive the original video frame from the
photography module, configured to capture the original video frame at a first view angle to generate a first video frame,
and recording the first video frame into a database; and

a second image-processing circuit, coupled to the photography module to directly receive the original video frame from the
photography module, configured to capture the original video frame at a second view angle to generate a second video frame,
and recording the second video frame into the database, wherein the second view angle of the second video frame is different
from the first view angle of the first video frame,

wherein the first image-processing circuit and the second image-processing circuit simultaneously receive the original image
data.

US Pat. No. 10,055,049

TOUCH SENSOR SYSTEM AND MULTIPLEXER THEREOF

NOVATEK Microelectronics ...

1. A touch sensor system, comprising:a touch panel, comprising a plurality of touch sensing areas;
at least one multiplexer, coupled to the plurality of touch sensing areas through a plurality of connecting wire groups on the touch panel, wherein each of the connecting wire groups comprises a plurality of connecting wires; and
a touch controller, coupled to the at least one multiplexer, for controlling touch driving and sensing on the touch panel, the touch controller comprising a plurality of pins connected to the at least one multiplexer via a plurality of touch control wires and a plurality of touch sensing wires, wherein each of the plurality of pins is connected to one of the plurality of touch control wires or one of the plurality of touch sensing wires;
wherein each of the plurality of touch sensing wires transmits driving signals from the touch controller to a corresponding multiplexer among the at least one multiplexer to perform driving on one of the plurality of touch sensing areas, and transmits sensing signals from the touch sensing area to the touch controller;
wherein the touch controller controls the at least one multiplexer to perform touch driving and sensing on the plurality of touch sensing areas in a specific order by triggering the plurality of touch control wires in an order;
wherein each of the at least one multiplexer comprises a plurality of switch groups each coupled between one of the touch sensing wires and one of the connecting wire groups, and each of the switch groups comprises a plurality of switches respectively controlled by a same plurality of control signals transmitted through the touch control wires.

US Pat. No. 9,697,806

SELF-REFRESH CONTROL METHOD, SINK DEVICE THEREOF AND DISPLAY SYSTEM THEREOF

NOVATEK Microelectronics ...

1. A sink device for a display system, comprising:
a selecting module, for selecting one of a video data signal and a self-refresh frame to a display device of the display system;
a receiving module, for receiving the video data signal from a video source of the display system, outputting the video data
signal to the selecting module and generating a writing timing sequence signal according to the video data signal;

a storage module, for storing a frame of the video data signal as the self-refresh frame and outputting the self-refresh frame
to the selecting module according to a reading control signal;

a displaying timing generating module, for generating a reading timing sequence signal corresponding to the reading control
signal and adjusting the reading timing sequence signal according to a blanking indicating signal and a line conflict signal;
and

a self-refreshing module, for generating the writing control signal and the reading control signal according to the writing
timing sequence signal and the reading timing sequence signal, adjusting the reading timing sequence signal according to the
writing timing sequence signal and the reading timing sequence signal via the blanking indicating signal and the line conflict
signal.

US Pat. No. 9,799,284

DRIVING DEVICE HAVING LOW CHARGING/DISCHARGING POWER CONSUMPTION

NOVATEK Microelectronics ...

1. A driving device, comprising:
a first driving circuit, coupled to a first voltage source and a second voltage source having a voltage level lower than the
first voltage source, for driving a positive output voltage to a first output end according to a first display voltage and
charging the first output end with the second voltage source according to a control signal indicating whether the driving
device performs a polarity inversion; and

a second driving circuit, coupled to the second voltage source and a third voltage source having a voltage level lower than
the second voltage source, for driving a negative output voltage to a second output end according to a second display voltage
and discharging the second output end with the second voltage source according to the control signal.

US Pat. No. 9,544,506

IMAGE PROCESSING METHOD FOR IMAGE CAPTURING DEVICE

NOVATEK Microelectronics ...

1. An image processing method, comprising:
acquiring a first image during a first exposure time, and a second image during a second exposure time, wherein the first
exposure time is smaller than the second exposure time;

acquiring the image region with the luminance greater than a first threshold in the second image as a first over-exposure
region;

acquiring the image region located at corresponding positions of the first over-exposure region and in the first image as
a second over-exposure region;

comparing the second over-exposure region of the first image and the first over-exposure region of the second image, for acquiring
a first moving-object region;

excluding the first moving-object region from the second over-exposure region, to generate a third over-exposure region;
acquiring the image region located at corresponding positions of the third over-exposure region and in the second image as
a fourth over-exposure region; and

combining the third over-exposure region of the first image and the fourth over-exposure region of the second image.

US Pat. No. 9,659,539

GATE DRIVER CIRCUIT, DISPLAY APPARATUS HAVING THE SAME, AND GATE DRIVING METHOD

Novatek Microelectronics ...

1. A gate driver circuit for driving a display panel, comprising:
M groups of gate channels, M being an integer greater than 1, wherein each of the M groups of gate channels comprises:
a control circuit receiving a power supply voltage from a power supply circuit and generating a modulated supply voltage;
and

an output buffer connected to the control circuit, the output buffer powered by the modulated supply voltage and receiving
an input signal, so as to output a gate signal to a gate line of the display panel, wherein a driving pulse of the gate signal
is shaped during a charge period according to the modulated supply voltage, and the shape of the driving pulse of the gate
signal is maintained at a preset level during a pre-charge period, wherein the length of the pre-charge period is adjusted
according to the number of scan lines.