US Pat. No. 9,245,826

ANCHOR VIAS FOR IMPROVED BACKSIDE METAL ADHESION TO SEMICONDUCTOR SUBSTRATE

Newport Fab, LLC, Newpor...

1. A structure comprising:
at least one anchor via disposed in at least one corner of a semiconductor substrate;
a metal filler within said at least one anchor via, said metal filler having a protruding portion extending from a backside
of said semiconductor substrate;

a backside metal layer on a bottom surface of said semiconductor substrate, said backside metal layer being bonded to said
protruding portion of said metal filler of said at least one anchor via;

wherein said metal filler within said at least one anchor via does not provide ground connection to one or more active devices
in said semiconductor substrate.

US Pat. No. 9,136,157

DEEP N WELLS IN TRIPLE WELL STRUCTURES

Newport Fab, LLC, Newpor...

1. A structure in a semiconductor die comprising:
a P substrate;
an epitaxial layer situated above said P substrate;
at least one P substrate contact situated in said epitaxial layer, said at least one P substrate contact allowing a bias voltage
to be applied to said P substrate;

a deep N well situated in said P substrate, said deep N well being situated at a depth below a top surface of said P substrate
such that a portion of said P substrate is situated between said deep N well and said epitaxial layer;

a lateral isolation N well situated in said P substrate and said epitaxial layer, said lateral isolation N well being a lightly
doped N type region extending from a top surface of said epitaxial layer to said deep N well;

an isolated P well situated over said deep N well, said isolated P well being laterally surrounded by said lateral isolation
N well, said isolated P well extending completely through said epitaxial layer;

said isolated P well being electrically isolated from said P substrate by said deep N well and said lateral isolation N well.

US Pat. No. 9,343,353

SOI STRUCTURE FOR SIGNAL ISOLATION AND LINEARITY

Newport Fab, LLC, Newpor...

1. A method for improving electrical signal isolation between adjacent devices situated in a top semiconductor layer, said
method comprising:
etching a first portion of a trench through said top semiconductor layer and a base oxide layer below said top semiconductor
layer to an interface between said base oxide layer and a handle wafer, said first portion of said trench having a width between
substantially parallel sidewalls;

etching a second portion of said trench from said interface into said handle wafer below said base oxide layer, said second
portion of said trench having sloped sidewalls situated within said handle wafer;

applying an implant to said sloped sidewalls so as to amorphize said sloped sidewalls of said second portion of said trench
to form an amorphized region;

wherein a depth of said second portion of said trench between said interface and a bottom of said trench is greater than said
width of said first portion of said trench, such that a signal path length between two of said adjacent devices along said
amorphized region is at least twice said depth of said second portion.

US Pat. No. 9,190,994

RF SWITCH BRANCH HAVING IMPROVED LINEARITY

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) switch branch having a reduced nonlinearity, said RF switch branch comprising:
a primary transistor;
a first transistor having power terminals electrically connected between a drain node and a body node of said primary transistor;
a second transistor having power terminals electrically connected between said body node and a source node of said primary
transistor;

wherein one of said power terminals of said first transistor and one of said power terminals of said second transistor are
coupled to ground through a body resistor of said primary transistor;

wherein a ratio between a body node-to-ground impedance of said primary transistor and either a drain-to-body impedance of
said primary transistor or a source-to-body impedance of said primary transistor increases without increasing said body node-to-ground
impedance when said primary transistor is ON.

US Pat. No. 9,105,681

METHOD FOR FORMING DEEP SILICON VIA FOR GROUNDING OF CIRCUITS AND DEVICES, EMITTER BALLASTING AND ISOLATION

Newport Fab, LLC, Newpor...

1. A method of fabricating a deep silicon via in a semiconductor die, said method comprising:
forming a deep silicon via opening through at least one pre-metal dielectric layer of said semiconductor die;
extending said deep silicon via opening through at least one epitaxial layer of said semiconductor die, and partially into
a conductive substrate of said semiconductor die;

forming a conductive plug in said deep silicon via opening;
wherein said at least one epitaxial layer and said conductive substrate have a same conductivity type.

US Pat. No. 9,064,886

HETEROJUNCTION BIPOLAR TRANSISTOR HAVING A GERMANIUM EXTRINSIC BASE UTILIZING A SACRIFICIAL EMITTER POST

Newport Fab, LLC, Newpor...

1. A method for fabricating a heterojunction bipolar transistor (“HBT”) comprising:
forming a germanium layer over a SiGe layer, said SiGe layer including an intrinsic base;
forming an emitter sacrificial post and a raised germanium extrinsic base by etching away portions of said germanium layer,
said emitter sacrificial post in direct contact with said SiGe layer;

depositing a conformal dielectric layer over said raised germanium extrinsic base;
removing said emitter sacrificial post;
forming an emitter over said intrinsic base within an emitter opening defined by said removing said emitter sacrificial post.

US Pat. No. 9,984,269

FINGERPRINT SENSOR WITH DIRECT RECORDING TO NON-VOLATILE MEMORY

Tower Semiconductor Ltd.,...

1. A sensor including:a semiconductor substrate;
a metallization layer formed over the substrate, and
a plurality of pixels disposed in an array, each said pixel comprising:
an electrically isolated non-volatile memory structure including a metal via structure extending through the metallization layer, a polycrystalline silicon gate structure connected to a first end of the metal via structure and located between the substrate and the metallization layer, and a fixed electrode connected to an opposing second end of the metal via structure;
a first non-volatile memory (NVM) cell including a first drain region and a first source region formed in the semiconductor substrate, wherein the polycrystalline silicon gate structure is operably disposed over a first channel region separating the first source region and the first drain region such that current flow between the first source region and the first drain region is controlled by a charge stored on the electrically isolated non-volatile memory structure; and
a normally-open MEMS switch disposed on the metallization layer and including a movable electrode disposed on an actuating member such that the movable electrode contacts the fixed electrode only when the MEMS switch is subjected to a predetermined actuating force; and
a read/write control circuit configured to generate a stored charge on said electrically isolated non-volatile memory structure of every pixel of the plurality of pixels during an initialization operating phase of said sensor.

US Pat. No. 9,458,011

SCALABLE SELF-SUPPORTED MEMS STRUCTURE AND RELATED METHOD

Newport Fab, LLC, Newpor...

7. A method of forming a self-supported MEMS structure, said method comprising:
forming a polymer layer over a MEMS plate over a substrate;
forming a trench over said MEMS plate;
forming an oxide liner in said trench on sidewalls of said trench;
depositing a metallic filler in said trench to form a via;
removing said polymer layer such that said via and said MEMS plate form said self-supported MEMS structure.

US Pat. No. 9,436,092

SEMICONDUCTOR FABRICATION UTILIZING GRATING AND TRIM MASKS

Newport Fab, LLC, Newpor...

1. A method for fabricating a semiconductor device, said method comprising:
exposing a photoresist layer disposed on a semiconductor wafer utilizing a grating mask having a plurality of grating lines
to produce exposed lines and unexposed lines in said photoresist layer;

exposing said photoresist layer utilizing a trim mask having a chrome line in a blocking portion situated over a selected
one of said unexposed lines, wherein said trim mask includes at least two recesses having different depths adjacent to said
chrome line, and wherein said chrome line is aligned with respective sidewalls of said at least two recesses.

US Pat. No. 9,377,350

LIGHT SENSOR WITH CHEMICALLY RESISTANT AND ROBUST REFLECTOR STACK

Newport Fab, LLC, Newpor...

1. A light sensor comprising:
a reflector stack over a substrate, said reflector stack having an adhesion layer, a patterned reflector layer over said adhesion
layer, and a smoothing layer over said patterned reflector layer;

a conformal passivation layer covering said reflector stack;
an absorbing layer above said reflector stack and separated from said reflector stack.

US Pat. No. 9,362,160

SOI STRUCTURE AND METHOD FOR UTILIZING TRENCHES FOR SIGNAL ISOLATION AND LINEARITY

Newport Fab, LLC, Newpor...

1. A structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of
said structure, said structure comprising:
a first portion of a trench extending through said top semiconductor layer and through a base oxide layer below said top semiconductor
layer;

a handle wafer situated below said base oxide layer;
a second portion of said trench extending from an interface between said base oxide layer and said handle wafer into said
handle wafer and having sloped sidewalls, wherein a depth of said second portion of said trench from said interface to a bottom
of said trench is greater than that of said first portion of said trench from a top surface of said top semiconductor layer
to said interface, wherein said first portion of said trench has a substantially constant width that is greater than a width
of said second portion at said bottom of said trench;

wherein said sloped sidewalls are amorphized, thereby reducing carrier mobility in said handle wafer to improve electrical
signal isolation between said adjacent devices situated in said top semiconductor layer.

US Pat. No. 9,147,609

THROUGH SILICON VIA STRUCTURE, METHOD OF FORMATION, AND INTEGRATION IN SEMICONDUCTOR SUBSTRATE

Newport Fab, LLC, Newpor...

1. A semiconductor substrate having a plurality of devices, said semiconductor substrate comprising:
a plurality of through silicon vias disposed in said substrate extending from a top surface of said substrate to a bottom
surface of said substrate;

a conductive filler disposed within each of said plurality of through silicon vias, each of said plurality of through silicon
vias having a hollow center to reduce thermal stress in said semiconductor substrate, said hollow center being entirely surrounded
by said conductive filler to provide space for said conductive filler to expand inward;

wherein each of said plurality of through silicon vias has a pinched off region at a bottom portion to prevent contamination
during processing of said semiconductor substrate, and wherein said hollow center is tapered in said pinched off region.

US Pat. No. 9,209,264

HETEROJUNCTION BIPOLAR TRANSISTOR HAVING A GERMANIUM RAISED EXTRINSIC BASE

Newport Fab, LLC, Newpor...

1. A heterojunction bipolar transistor (“HBT”) comprising:
an intrinsic base in a SiGe layer;
a raised germanium extrinsic base over said SiGe layer, a portion of said raised germanium extrinsic base being situated on
a mounded portion of said SiGe layer;

a base contact situated over and contacting said raised germanium extrinsic base;
an emitter situated over said intrinsic base;
a collector situated under said intrinsic base;
said raised germanium extrinsic base having a reduced parasitic base-collector capacitance;
wherein said mounded portion of said SiGe layer is laterally adjacent to said intrinsic base in said SiGe layer.

US Pat. No. 9,481,568

INTEGRATION OF ACTIVE DEVICES WITH PASSIVE COMPONENTS AND MEMS DEVICES

Newport Fab, LLC, Newpor...

1. An integrated semiconductor structure comprising:
an active device having a device top electrode connected to a conductive jumper by a device-side via/interconnect metal stack
that includes a first plurality of interconnect metals and vias that are alternately stacked;

a passive component comprising a microelectromechanical systems (MEMS) device having a component bottom plate connected to
said conductive jumper by a component-side via/interconnect metal stack that includes a second plurality of interconnect metals
and vias that are alternately stacked,

said component bottom plate being situated at an intermediate metal level higher than said device top electrode, and said
conductive jumper being situated at a connecting metal level higher than said component bottom plate.

US Pat. No. 9,346,669

ROBUST MEMS STRUCTURE WITH VIA CAP AND RELATED METHOD

Newport Fab, LLC, Newpor...

10. A method of forming a self-supported MEMS structure, said method comprising:
forming a polymer layer over a MEMS plate over a substrate;
forming a via collar along sidewalls of a first portion of a trench over said polymer layer;
forming a second portion of said trench within said polymer layer;
forming an oxide liner in said trench lining sidewalls of said via collar and sidewalls of said second portion of said trench;
depositing a metallic filler in said trench to form a via;
forming a metal cap layer over said via collar and said metallic filler;
removing a portion of said metal cap layer to form a via cap;
removing said polymer layer such that said via is supported only on a bottom thereof by said substrate.

US Pat. No. 10,095,909

HYBRID MEMS-FLOATING GATE DEVICE

Tower Semiconductor Ltd.,...

1. An integrated circuit (IC) including a metallization layer formed over a semiconductor substrate, the IC including at least one hybrid Micro-Electro-Mechanical-System-Floating-Gate (MEMS-FG) device comprising:a memory cell including a first source region and a first drain region formed in the semiconductor substrate, and a first gate structure formed between the semiconductor substrate and the metallization layer and disposed over a first channel region separating the first source region and the first drain region;
a MEMS switch disposed on the metallization layer and including a movable electrode and at least one fixed electrode, the MEMS switch being configured such that said movable electrode is disposed away from the fixed electrode in the absence of an actuating force, and such that the movable electrode abuts the fixed electrode when the MEMS switch is subjected to said actuating force; and
a metal structure fixedly connected between the gate structure and the fixed electrode, said metal structure extending through the metallization layer,
wherein the gate structure, the metal structure and the fixed electrode collectively form an electrically isolated structure.

US Pat. No. 9,725,306

MEMS DEVICE WITH SEALED CAVITY AND METHOD FOR FABRICATING SAME

Newport Fab, LLC, Newpor...

1. A MEMS device comprising:
a top MEMS plate and a bottom MEMS plate;
a lower chamber between said bottom MEMS plate and said top MEMS plate, and an upper chamber between said top MEMS plate and
a sealing layer;

said top MEMS plate having at least one segment that is narrower than said bottom MEMS plate, thereby causing said lower and
upper chambers to have a similar pressure;

wherein said top MEMS plate is a first metal segment of a lower metal layer configured for interlayer connection, and said
top MEMS plate is electrically coupled to a first metal segment of an upper metal layer through conductive vias;

wherein said bottom MEMS plate is electrically coupled to a second metal segment of said lower metal layer, and to a second
metal segment of said upper metal layer.

US Pat. No. 10,177,044

BULK CMOS RF SWITCH WITH REDUCED PARASITIC CAPACITANCE

Newport Fab, LLC, Newpor...

1. A method for fabricating a bulk CMOS RF switch in an active switch area of a base structure, the method comprising:forming an epitaxial silicon layer over a semiconductor substrate such that a Deep N-well is at least partially formed in a first epitaxial region of said epitaxial layer adjacent to an interface between the epitaxial silicon layer and said substrate, said epitaxial silicon layer having a resistivity in the range of 0.5 to 2 ohm-cm, and said Deep N-well having a second nominal N-type doping concentration in the range of 1×1016 to 1×1018 atoms per cubic centimeter;
forming a P-well by implanting a first P-type dopant into a second epitaxial region of the epitaxial silicon layer, the second epitaxial region being located above a first epitaxial layer portion of the first epitaxial region and the first P-type dopant being implanted through an upper epitaxial surface of the epitaxial silicon layer such that the P-well extends from the upper epitaxial surface to a first upper boundary region of the first epitaxial layer portion;
disposing a mask over the entire active switch area during a first N-type implant such that a third epitaxial region of the epitaxial silicon layer, which is located above a second epitaxial layer portion of the first epitaxial region, maintains said first nominal N-type doping concentration;
performing a second N-type implant during which spaced-apart first and second contact diffusions are formed in the P-Well, and a third contact diffusion is formed in the third epitaxial region, said third contact diffusion being formed such that said third contact diffusion is separated from a second upper boundary region of the second epitaxial layer portion by a body region comprising said intrinsic epitaxial material; and
forming backend metallization structures over including metal via structures connected to the first, second and third contact diffusions while the body region comprises said intrinsic epitaxial material.

US Pat. No. 9,272,901

MEMS DEVICE WITH SEALED CAVITY AND RELEASE CHAMBER AND RELATED DOUBLE RELEASE METHOD

Newport Fab, LLC, Newpor...

1. A MEMS device comprising:
a top MEMS plate and a bottom MEMS plate;
a lower chamber between said bottom MEMS plate and said top MEMS plate, and an upper chamber between said top MEMS plate and
a first sealing layer;

a release chamber between said top MEMS plate and a second sealing layer, said release chamber allowing gaseous content of
said upper chamber to be released.

US Pat. No. 9,412,758

SEMICONDUCTOR ON INSULATOR (SOI) STRUCTURE WITH MORE PREDICTABLE JUNCTION CAPACITANCE AND METHOD FOR FABRICATION

Newport Fab, LLC, Newpor...

1. A semiconductor on insulator (SOI) structure comprising:
a buried oxide layer over a bulk semiconductor layer;
a device layer on said buried oxide layer, wherein said device layer comprises a substantially un-doped semiconductor at an
interface between said device layer and said buried oxide layer;

at least one transistor fabricated in said device layer, wherein a source/drain junction of said at least one transistor does
not contact said buried oxide layer, thereby forming a source/drain junction capacitance, and wherein a thickness of said
device layer is configured such that said source/drain junction capacitance behaves substantially similarly to a source/drain
junction capacitance of a semiconductor structure fabricated on a bulk silicon wafer;

at least one trench extending through said device layer and contacting a top surface of said buried oxide layer, thereby electrically
isolating said at least one transistor;

wherein a high resistivity of said bulk semiconductor layer facilitates formation of at least one thick depletion region that
extends from a bottom surface of said buried oxide layer into said bulk semiconductor layer, such that a thickness of said
at least one thick depletion region is based on said high resistivity.

US Pat. No. 10,177,045

BULK CMOS RF SWITCH WITH REDUCED PARASITIC CAPACITANCE

Newport Fab, LLC, Newpor...

1. An integrated circuit comprising:a base structure including an epitaxial layer formed on an upper surface of a semiconductor substrate, and
at least one bulk CMOS RF switch formed in an active switch area of the base structure, said at least one bulk CMOS RF switch including:
a Deep N-Well including a first N-type dopant at least partially disposed in a first epitaxial region of the epitaxial layer, said Deep N-well having a nominal concentration of said N-type dopant in the range of 1×1016 to 1×1018 atoms per cubic centimeter;
a transistor element including:
a P-Well including a first P-type dopant disposed in a second epitaxial region such that said P-Well is entirely located over a first epitaxial layer portion of the first epitaxial region,
spaced-apart N-type source and drain contact diffusions formed by a second N-type dopant disposed in the P-Well adjacent to the upper epitaxial surface such that a channel region is formed by a portion of the P-Well located between the source and drain contact diffusions, and
a gate structure located over the channel region; and
an N-Tap element comprising a body region formed by a third epitaxial region of said epitaxial layer that is at least partially located over a second epitaxial layer portion of the first epitaxial region, said N-Tap element also including a third N-type contact diffusion formed by said second N-type dopant and disposed in the third epitaxial region adjacent to the upper epitaxial surface, wherein the body region comprises intrinsic epitaxial material having a resistivity in the range of 0.5 to 2ohm-cm, and wherein said N-Tap element is configured such that said third N-type contact diffusion is separated from a second upper boundary region of the second epitaxial layer portion by said intrinsic epitaxial material forming said body region.

US Pat. No. 10,062,644

COPPER INTERCONNECT FOR IMPROVING RADIO FREQUENCY (RF) SILICON-ON-INSULATOR (SOI) SWITCH FIELD EFFECT TRANSISTOR (FET) STACKS

Newport Fab, LLC, Newpor...

1. A method of fabricating a radio frequency (RF) switch comprising:fabricating a plurality of silicon-on-insulator (SOI) CMOS transistors;
forming a pre-metal dielectric layer formed over the plurality of SOI CMOS transistors;
forming a plurality of contacts that extend through the pre-metal dielectric layer and provide electrical connections to the plurality of SOI CMOS transistors;
forming a first metal layer comprising a plurality of metal traces over the pre-metal dielectric structure, wherein the first metal layer has a first metal composition;
forming a plurality of additional metal layers over the first metal layer, wherein the plurality of additional metal layers having a second metal composition, different than the first metal composition;
fabricating the plurality of SOI CMOS transistors and the additional metal layers in accordance with a first process node having a first minimum line width; and
fabricating the first metal layer in accordance with a second process node having a second minimum line width, which is less than the first minimum line width.

US Pat. No. 9,673,081

ISOLATED THROUGH SILICON VIA AND ISOLATED DEEP SILICON VIA HAVING TOTAL OR PARTIAL ISOLATION

Newport Fab, LLC, Newpor...

1. A method for improving electrical signal isolation in a semiconductor substrate, said method comprising:
fabricating a deep trench having sidewalls into said semiconductor substrate having a first conductivity type and a high resistivity,
wherein said deep trench has an aspect ratio greater than or approximately equal to 18:1;

forming a non-dielectric partial isolation region having a second conductivity type along an upper portion of said sidewalls
of said deep trench;

wherein said non-dielectric partial isolation region extends deeper into said semiconductor substrate than a collector of
a bipolar device disposed in said semiconductor substrate so as to increase radio frequency isolation and reduce occurrence
of DC voltage breakdown in said semiconductor substrate due to an electric field between said collector and said deep trench.

US Pat. No. 9,917,104

HYBRID MOS-PCM CMOS SOI SWITCH

Tower Semiconductor Ltd.,...

1. An integrated circuit (IC) switch configured to control signals transmitted along a signal path, the switch comprising:
a plurality of Metal-Oxide-Silicon (MOS) transistors coupled in series in the signal path; and
a plurality of switching elements connected in parallel and disposed in the signal path, wherein each said switching element
comprises a Phase Change Material (PCM) structure,

wherein said plurality of MOS transistors comprises a first MOS transistor fabricated on a first Silicon-On-Insulator (SOI)
island and a second MOS transistor fabricated on a second Silicon-On-Insulator (SOI) island, said first and second SOI islands
being separated by an intervening isolation region, and

wherein the plurality of switching elements are fabricated on a dielectric layer portion disposed over the intervening isolation
region and are connected in parallel between a drain terminal of the first MOS transistor and a source terminal of the second
MOS transistor.

US Pat. No. 9,620,617

STRUCTURE AND METHOD FOR REDUCING SUBSTRATE PARASITICS IN SEMICONDUCTOR ON INSULATOR TECHNOLOGY

Newport Fab, LLC, Newpor...

1. A structure comprising:
a buried oxide layer over a bulk semiconductor layer;
a device layer over said buried oxide layer;
a compensation implant region near an interface of said buried oxide layer and said bulk semiconductor layer;
wherein said compensation implant region is configured to substantially eliminate a parasitic conduction layer near said buried
oxide layer;

a deep trench extending through said device layer and said buried oxide layer, wherein said deep trench is filled with a dielectric
material; and

a damaged implant region in said bulk semiconductor layer under said deep trench, wherein said damaged implant region is separated
from said compensation implant region in said bulk semiconductor layer.

US Pat. No. 9,608,079

SEMICONDUCTOR DEVICE HAVING REDUCED DRAIN-TO-SOURCE CAPACITANCE

Newport Fab, LLC, Newpor...

1. A semiconductor device comprising:
a source region in a semiconductor die;
a drain region in said semiconductor die;
a source finger electrode located over the source region, wherein said source finger electrode comprises at least one isolated
segment and a main segment having a first portion and a second portion that is narrower than said first portion, wherein the
at least one isolated segment and the main segment of the source finger electrode are physically separated segments of a first
metal layer; and

a plurality of source contacts that electrically couple the at least one isolated segment and the main segment of the source
finger electrode to the source region.

US Pat. No. 10,014,366

TAPERED POLYSILICON GATE LAYOUT FOR POWER HANDLING IMPROVEMENT FOR RADIO FREQUENCY (RF) SWITCH APPLICATIONS

Newport Fab, LLC, Newpor...

1. A semiconductor structure comprising:an active semiconductor region located on a buried dielectric layer, wherein the active semiconductor region includes a plurality of source/drain regions separated by a plurality of channel regions; and
a polysilicon gate structure located over the active semiconductor region, wherein the polysilicon gate structure includes:
a plurality of polysilicon gate fingers, wherein each of the plurality of polysilicon gate fingers extends over a portion of a corresponding one of the plurality of channel regions;
a polysilicon base region that joins the plurality of polysilicon gate fingers; and
a plurality of triangular polysilicon extension regions each located along and continuous with a corresponding one of the plurality of polysilicon gate fingers, wherein each of the triangular polysilicon extension regions extends over a portion of one of the plurality of channel regions, wherein the plurality of channel regions have first lengths under the polysilicon gate fingers, and wherein the plurality of channel regions have second lengths where the triangular polysilicon extension regions are continuous with the polysilicon gate fingers, wherein the second lengths are greater than the first lengths.

US Pat. No. 9,941,353

STRUCTURE AND METHOD FOR MITIGATING SUBSTRATE PARASITICS IN BULK HIGH RESISTIVITY SUBSTRATE TECHNOLOGY

Newport Fab, LLC, Newpor...

1. A structure comprising:a field isolation region in a high resistivity substrate;
a compensation implant region under said field isolation region in said high resistivity substrate;
a damaged region below said compensation implant region;
wherein said compensation implant region is configured to substantially eliminate a parasitic p-n junction under said field isolation region, wherein said parasitic p-n junction is formed between trapped charges in said field isolation region and said high resistivity substrate, said high resistivity substrate having a resistivity of about 1000 ohms-cm or greater.

US Pat. No. 9,755,063

RF SOI SWITCHES INCLUDING LOW DIELECTRIC CONSTANT FEATURES BETWEEN METAL LINE STRUCTURES

Newport Fab, LLC, Newpor...

1. A method for fabricating a radio frequency (RF) silicon-on-insulator (SOI) switch on an SOI substrate such that said RF
SOI switch includes first and second elongated spaced-apart source/drain regions separated by an elongated channel region,
an elongated polycrystalline silicon (polysilicon) gate structure disposed over the channel region, at least two dielectric
layers comprising one or more dielectric materials having a first dielectric constant disposed on an upper surface of the
substrate, and a plurality of metal contact/via structures disposed in said at least two dielectric layers, the method comprising:
forming a low dielectric constant (low-k) feature over said substrate in an associated interstitial region;
forming a dielectric layer of said two or more dielectric layers including depositing one or more dielectric materials having
a first dielectric constant into first and second reserved regions disposed on opposite sides of said interstitial region;
and

forming a plurality of periodically spaced metal structures that extend through said dielectric layer only in said first and
second reserved regions such that each of said plurality of periodically spaced metal structures is entirely surrounded by
said one or more dielectric materials forming said dielectric layer.

US Pat. No. 9,754,814

INTEGRATED PASSIVE DEVICE HAVING IMPROVED LINEARITY AND ISOLATION

Newport Fab, LLC, Newpor...

1. A structure for improved electrical signal isolation between radio frequency (RF) integrated passive devices (IPDs), said
structure comprising:
a non-recrystallized amorphized region in a semiconductor substrate that does not include an active device, such that said
non-recrystallized amorphized region is not subject to high annealing temperatures associated with active device region doping;

said non-recrystallized amorphized region having a substantially uniform thickness;
a dielectric layer formed over said non-recrystallized amorphized region;
said RF IPDs formed over said dielectric layer;
a plurality of charge carrier traps at an interface between said non-recrystallized amorphized region and said dielectric
layer, wherein a Fermi potential at a top surface of said substrate is pinned by said plurality of charge carrier traps such
that depletion of said substrate of carriers will not be modulated by signals applied to said RF IPDs.

US Pat. No. 9,640,528

LOW-COST COMPLEMENTARY BICMOS INTEGRATION SCHEME

Newport Fab, LLC, Newpor...

1. A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device comprising:
a CMOS device in a CMOS region of a substrate;
a first well in said CMOS region;
an NPN bipolar device in a bipolar region of said substrate;
a second well in said bipolar region;
a sub-collector of said NPN bipolar device reaching a top surface of said substrate, said sub-collector surrounding a selectively
implanted collector;

said second well being a collector sinker, said collector sinker being laterally adjacent and electrically connected to said
sub-collector of said NPN bipolar device in a laterally overlapping region;

wherein said first well in said CMOS region and said collector sinker in said bipolar region form a p-n junction to provide
electrical isolation between said CMOS device and said NPN bipolar device;

said collector sinker being electrically connected to a collector contact;
said sub-collector not extending vertically below said collector sinker.

US Pat. No. 10,068,997

SIGE HETEROJUNCTION BIPOLAR TRANSISTOR WITH CRYSTALLINE RAISED BASE ON GERMANIUM ETCH STOP LAYER

Newport Fab, LLC, Newpor...

1. A method for fabricating a heterojunction bipolar transistor (HBT) comprising:sequentially forming a silicon-germanium (SiGe) layer, a substantially pure germanium (Ge) layer over the SiGe layer, and a silicon (Si) layer on the substantially pure Ge layer, wherein forming said substantially pure Ge layer comprises forming said Ge layer with a Ge concentration greater than 95%;
utilizing a dry etching process to form an emitter window by removing a portion of the Si layer using an underlying portion of the substantially pure Ge layer as an etch stop;
utilizing a wet etch process to remove said underlying portion of the substantially pure Ge layer, thereby exposing a contact portion of the SiGe layer in the emitter window; and
forming a polycrystalline silicon emitter structure that is at least partially disposed inside the emitter window such that a lower portion of the polycrystalline silicon emitter structure abuts the contact portion of the SiGe layer.

US Pat. No. 10,044,331

HIGH POWER RF SWITCHES USING MULTIPLE OPTIMIZED TRANSISTORS

Newport Fab, LLC, Newpor...

1. A switch comprising:a plurality of field effect transistors connected in series between a first node and a second node, wherein the plurality of field effect transistors include:
a first transistor having a first body region having a first conductivity type, and a first set of lightly doped drain (LDD) regions having a second conductivity type, opposite the first conductivity type; and
a second transistor having a second body region having the first conductivity type, and a second set of LDD regions having the second conductivity type, wherein the first set of LDD regions has a dopant concentration lower than a dopant concentration of the second set of LDD regions, and wherein the first body region has a dopant concentration greater than a dopant concentration of the second body region, whereby the first transistor has a higher breakdown voltage than the second transistor.

US Pat. No. 9,887,123

STRUCTURE HAVING ISOLATED DEEP SUBSTRATE VIAS WITH DECREASED PITCH AND INCREASED ASPECT RATIO AND RELATED METHOD

Newport Fab, LLC, Newpor...

1. A structure comprising:
a device layer over a buried oxide layer;
a deep trench extending entirely through said device layer and partially through said buried oxide layer;
a dielectric filler located in said deep trench;
a plurality of via holes, each extending entirely through said dielectric filler and only partially through said buried oxide
layer;

conductive fillers located in said via holes, wherein said conductive fillers form isolated deep substrate vias that extend
entirely through said dielectric filler and only partially through said buried oxide layer.

US Pat. No. 10,062,636

INTEGRATION OF THERMALLY CONDUCTIVE BUT ELECTRICALLY ISOLATING LAYERS WITH SEMICONDUCTOR DEVICES

Newport Fab, LLC, Newpor...

1. A semiconductor structure comprising:a semiconductor wafer having at least one semiconductor device integrated in a device layer;
a thermally conductive but electrically isolating layer on a back side of said semiconductor wafer;
a front side glass on a front side of said semiconductor wafer;
wherein said thermally conductive but electrically isolating layer is conformal and substantially coextensive with said device layer, and configured to dissipate heat from said at least one semiconductor device integrated in said semiconductor wafer;
wherein said thermally conductive but electrically isolating layer has a coefficient of thermal expansion (CTE) that is closely matched with said device layer.

US Pat. No. 9,984,888

METHOD OF FABRICATING A SEMICONDUCTOR WAFER INCLUDING A THROUGH SUBSTRATE VIA (TSV) AND A STEPPED SUPPORT RING ON A BACK SIDE OF THE WAFER

Newport Fab, LLC, Newpor...

1. A method comprising:forming at least one through substrate via (TSV) in said semiconductor wafer;
coarse grinding a back side of said semiconductor wafer to form an outer ring of a stepped support ring;
fine grinding said back side of said semiconductor wafer to form an inner ring of said stepped support ring, wherein said fine grinding exposes said at least one TSV and forms a usable back side region of said semiconductor wafer; and
forming a back side metal on said usable back side region of said semiconductor wafer without performing any polish action on said usable back side region of said semiconductor wafer.

US Pat. No. 9,751,753

INTEGRATION OF ACTIVE DEVICES WITH PASSIVE COMPONENTS AND MEMS DEVICES

Newport Fab, LLC, Newpor...

1. A method of manufacturing an integrated semiconductor structure, the method comprising:
forming an active device in a semiconductor substrate, the active device having a device top electrode;
forming a first portion of a device-side via/interconnect metal stack, wherein the first portion of the device side via/interconnect
metal stack is coupled to the device top electrode;

forming a first portion of a passive component;
forming a component-side via/interconnect metal stack, wherein the component-side via/interconnect metal stack is coupled
to the first portion of said passive component;

forming a second portion of said device-side via/interconnect metal stack, wherein the second portion of the device side via/interconnect
metal stack is coupled to the first portion of the device side via/interconnect metal stack; and then

forming a conductive jumper to connect said component-side via/interconnect metal stack to said second portion of said device-side
via/interconnect metal stack.

US Pat. No. 9,673,191

EFFICIENT FABRICATION OF BICMOS DEVICES

Newport Fab, LLC, Newpor...

1. A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device comprising:
a CMOS device in a CMOS region;
a PNP bipolar device in a bipolar region;
a spacer clear region defined by an opening in a common spacer layer over said CMOS region and said bipolar region, wherein
a sub-collector, a selectively implanted collector, and a base of said PNP bipolar device are formed in said spacer clear
region, wherein a width of said sub-collector of said PNP bipolar device is substantially defined by said opening;

a collector sinker directly adjoining said spacer clear region and electrically connected to said sub-collector of said PNP
bipolar device.

US Pat. No. 9,634,089

SELECTIVE AMORPHIZATION FOR SIGNAL ISOLATION AND LINEARITY

Newport Fab, LLC, Newpor...

1. A method for improving electrical signal isolation between adjacent devices situated in a top semiconductor layer, said
method comprising:
fabricating a gate and a protection mask on said top semiconductor layer, said top semiconductor layer situated over a base
oxide layer, and said base oxide layer situated over a handle wafer;

applying an inert implant through said top semiconductor layer and said base oxide layer, and into a top surface of said handle
wafer, while protecting a region of said top semiconductor layer situated under and substantially aligned with said gate so
as to amorphize said top surface of said handle wafer, thereby reducing carrier mobility in said handle wafer to improve electrical
signal isolation between said adjacent devices situated in said top semiconductor layer;

wherein said inert implant is applied to an entire top surface of said top semiconductor layer except said region situated
under and substantially aligned with said gate, and produces damaged regions within said top semiconductor layer.

US Pat. No. 9,577,035

ISOLATED THROUGH SILICON VIAS IN RF TECHNOLOGIES

Newport Fab, LLC, Newpor...

11. A structure for providing electrical isolation in a semiconductor substrate, said structure comprising:
a deep trench isolation loop having a first depth disposed in said semiconductor substrate, said deep trench isolation loop
extending through a shallow trench insulation region and terminating in said semiconductor substrate below a bottom surface
of said shallow trench insulation;

a semiconductor device within a perimeter of another deep trench isolation loop having said first depth disposed in said semiconductor
substrate, a width of said deep trench isolation loop being substantially equal to a width of said another deep trench isolation
loop;

a dielectric material disposed in said deep trench isolation loop;
one or more through silicon vias (TSVs), having a second depth, disposed in said semiconductor substrate and within a perimeter
of said deep trench isolation loop.

US Pat. No. 10,062,712

METHOD TO FABRICATE BOTH FD-SOI AND PD-SOI DEVICES WITHIN A SINGLE INTEGRATED CIRCUIT

Newport Fab, LLC, Newpor...

1. A method comprising:forming a first mask over a first region of a silicon layer having a first thickness;
oxidizing a second region of the silicon layer that is exposed through the first mask, thereby forming an oxide layer that reduces the thickness of the silicon layer in the second region to a second thickness, less than the first thickness;
removing the first mask;
removing the oxide layer;
fabricating a partially-depleted silicon-on-insulator (PD-SOI) transistor in the first region of the silicon layer;
fabricating a fully-depleted silicon-on-insulator (FD-SOI) transistor in the second region of the silicon layer; and
forming shallow trench isolation (STI) regions between the PD-SOI transistor and the FD-SOI transistor by:
forming a second mask over portions of the first and second regions of the silicon layer, wherein the second mask exposes locations where shallow trench isolation (STI) regions are to be formed;
removing portions of the silicon layer exposed through the second mask, thereby forming trenches that define a first silicon-on-insulator (SOI) region in the first region of the silicon layer and a second SOI region in the second region of the silicon layer;
depositing a dielectric material over the second mask and into the trenches;
planarizing the dielectric material to expose the second mask over both the first and second regions of the silicon layer;
etching upper portions of the dielectric material through the exposed second mask; and then removing the second mask.

US Pat. No. 9,997,396

DEEP TRENCH ISOLATION STRUCTURE AND METHOD FOR IMPROVED PRODUCT YIELD

Newport Fab, LLC, Newpor...

1. A semiconductor structure comprising:a deep trench adjacent to field oxide regions in a semiconductor substrate;
an electrically conductive metallic filler material in said deep trench;
a high density plasma (HDP) oxide layer, free of thermal oxide, in said deep trench and situated directly over said electrically conductive metallic filler material, wherein said HDP oxide layer does not reach a bottom of said deep trench, interfaces with said electrically conductive metallic filler adjacent to at least one of said field oxide regions, and has a substantially co-planar top surface with said semiconductor substrate and at least one of said field oxide regions, thereby preventing nodules in said deep trench;
wherein a semiconductor device is surrounded and enclosed by said electrically conductive metallic filler and said HDP oxide layer.

US Pat. No. 9,700,869

CONTINUOUSLY PRODUCING DIGITAL MICRO-SCALE PATTERNS ON A THIN POLYMER FILM

Newport Fab, LLC, Newpor...

1. A method for continuously producing a plurality of micro-scale patterned structures, the method comprising:
disposing a liquid film on a first surface;
moving the first surface such that the liquid film passes through a gap region defined between the first surface and an opposing
second surface;

generating an electric field in the gap region such that the liquid film undergoes electrohydrodynamic (EHD) patterning deformation
during passage through the gap region, whereby portions of the liquid film form a plurality of patterned liquid features having
a micro-scale patterned shape; and

solidifying the plurality of patterned liquid features such that each of the plurality of patterned liquid features forms
an associated solid micro-scale patterned structure having said micro-scale patterned shape.

US Pat. No. 10,192,805

THERMALLY CONDUCTIVE AND ELECTRICALLY ISOLATING LAYERS IN SEMICONDUCTOR STRUCTURES

Newport Fab, LLC, Newpor...

1. A semiconductor structure comprising:a semiconductor wafer having at least one semiconductor device integrated in a first device layer;
a thermally conductive but electrically isolating layer on a front side of said semiconductor wafer, said thermally conductive but electrically isolating layer between said first device layer and a second device layer;
at least one passive device situated on said thermally conductive but electrically isolating layer and in said second device layer;
wherein said thermally conductive but electrically isolating layer is configured to dissipate heat from said at least one semiconductor device integrated in said first device layer.

US Pat. No. 10,325,907

SUBSTRATE ISOLATION FOR LOW-LOSS RADIO FREQUENCY (RF) CIRCUITS

Newport Fab, LLC dba Jazz...

1. A semiconductor structure comprising:a semiconductor substrate; and
an isolation region formed on the semiconductor substrate, wherein the isolation region includes:
one or more shallow trench isolation (STI) regions;
one or more semiconductor regions that extend through the STI regions within the isolation region; and
a grid of deep trench isolation (DTI) regions that extend through the STI regions and into the semiconductor substrate.

US Pat. No. 10,290,630

BICMOS INTEGRATION WITH REDUCED MASKING STEPS

Newport Fab, LLC, Newpor...

1. A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device comprising:a CMOS device in a CMOS region;
a PNP bipolar device in a bipolar region;
an NPN bipolar device in said bipolar region and forming a p-n junction with said CMOS device, said NPN bipolar device having an extrinsic base being self-aligned with an emitter of said NPN bipolar device;
wherein said extrinsic base of said NPN bipolar device and an emitter of said PNP bipolar device share a P type dopant;
wherein said NPN bipolar device includes a CMOS N well having a first dopant concentration;
wherein said NPN bipolar device includes a sub-collector having a second dopant concentration, wherein said CMOS N well is a collector sinker for said NPN bipolar device;
wherein said first dopant concentration of said CMOS N well is greater than said second dopant concentration of said sub-collector;
wherein said sub-collector and said CMOS N well are laterally adjacent, have substantially the same depth with a partially overlapped region, and have bottom surfaces directly contacting a substrate, such that said sub-collector and said CMOS N well form a direct electrical path for external connection;
wherein said sub-collector is a singly doped region between said extrinsic base and said substrate.

US Pat. No. 10,290,631

LINEARITY AND LATERAL ISOLATION IN A BICMOS PROCESS THROUGH COUNTER-DOPING OF EPITAXIAL SILICON REGION

Newport Fab, LLC, Newpor...

1. A method comprising:growing an epitaxial layer over a semiconductor substrate, wherein the semiconductor substrate has a first conductivity type and the epitaxial layer has a second conductivity type, opposite the first conductivity type;
forming a mask over the epitaxial layer, wherein the mask covers a first region of the epitaxial layer and exposes a second region of the epitaxial layer;
implanting a dopant having the first conductivity type through the mask into the second region of the epitaxial layer, whereby the second region of the epitaxial layer becomes counter-doped to the first conductivity type;
forming one or more shallow trench isolation regions in the counter-doped second region of the epitaxial layer, wherein portions of the counter-doped second region of the epitaxial layer are exposed through the one or more shallow trench isolation regions; and
forming one or more deep trench isolation regions that extend through the one or more shallow trench isolation regions and the counter-doped second region of the epitaxial layer, wherein the one or more shallow trench isolation regions, the one or more deep trench isolation regions and the counter-doped second region of the epitaxial layer form an isolation region.

US Pat. No. 10,319,716

SUBSTRATE ISOLATION FOR LOW-LOSS RADIO FREQUENCY (RF) CIRCUITS

Newport Fab, LLC, Newpor...

1. A method comprising:forming one or more shallow trench isolation (STI) regions in a first semiconductor region located over a semiconductor substrate, wherein dummy active regions of the first semiconductor region extend through the one or more shallow trench isolation regions to an upper surface of the first semiconductor region, wherein no devices are formed in the dummy active regions; and
forming a grid of deep trench isolation (DTI) regions in the first semiconductor region, wherein the grid of DTI regions extends entirely through the first semiconductor region, wherein the grid of DTI regions includes a pattern that exhibits only T-shaped or Y-shaped intersections.

US Pat. No. 10,297,591

BICMOS INTEGRATION USING A SHARED SIGE LAYER

Newport Fab, LLC, Newpor...

1. A bipolar complementary-metal-oxide-semiconductor (BiCMOS) device comprising:a CMOS device in a CMOS region;
a PNP bipolar device in a bipolar region;
an NPN bipolar device in said bipolar region;
a silicon-germanium (SiGe) layer over a base of said PNP bipolar device and a selectively implanted collector of said NPN bipolar device;
wherein a first portion of said SiGe layer forms a base of said NPN bipolar device, and a second portion of said SiGe layer forms an emitter of said PNP bipolar device;
wherein said NPN bipolar device includes a collector sinker laterally adjacent said selectively implanted collector, and said collector sinker forms a p-n junction with said CMOS device;
wherein said NPN bipolar device includes a CMOS N well having a first dopant concentration;
wherein said NPN bipolar device includes a sub-collector having a second dopant concentration, wherein said CMOS N well is said collector sinker for said NPN bipolar device;
wherein said first dopant concentration of said CMOS N well is greater than said second dopant concentration of said sub-collector;
wherein said sub-collector and said CMOS N well are laterally adjacent, have substantially the same depth with a partially overlapped region, and have bottom surfaces directly contacting a substrate, such that said sub-collector and said CMOS N well form a direct electrical path for external connection;
wherein said sub-collector is a singly doped region between said base and said substrate.

US Pat. No. 10,347,625

LINEARITY AND LATERAL ISOLATION IN A BICMOS PROCESS THROUGH COUNTER-DOPING OF EPITAXIAL SILICON REGION

Newport Fab, LLC, Newpor...

1. A semiconductor structure comprising:a semiconductor substrate having a first conductivity type;
an epitaxial region formed over the semiconductor substrate, wherein the epitaxial region has a second conductivity type, opposite the first conductivity type, and wherein the epitaxial region forms a collector region of a heterojunction bipolar transistor; and
an isolation region formed on the semiconductor substrate, wherein the isolation region includes:
one or more shallow trench isolation regions;
one or more deep trench isolation regions; and
one or more lightly doped regions of the first conductivity type, each having a sheet resistance of at least about 50 K?/square.

US Pat. No. 10,325,833

BENT POLYSILICON GATE STRUCTURE FOR SMALL FOOTPRINT RADIO FREQUENCY (RF) SWITCH

Newport Fab, LLC, Newpor...

16. A silicon on insulator (SOI) transistor structure comprising:an active semiconductor region located on a buried dielectric layer, wherein the active semiconductor region includes a plurality of source/drain regions having a first conductivity type separated by channel/body regions having a second conductivity type; and
a plurality of polysilicon gate fingers, each extending over a corresponding one of the channel/body regions, and each including a first rectangular portion, a second rectangular portion and a connecting portion that joins the first and second rectangular portions, wherein the first rectangular portions extend in parallel with a first axis and are separated by a first spacing, and wherein the second rectangular portions extend in parallel with the first axis and are separated by a second spacing, greater than the first spacing, and wherein each connecting portion introduces an offset between the corresponding first and second rectangular portions along a second axis, wherein the offset results in the source/drain regions having a plurality of different lengths along the second axis.

US Pat. No. 10,469,121

NON-LINEAR SHUNT CIRCUIT FOR THIRD ORDER HARMONIC REDUCTION IN RF SWITCHES

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) circuit comprising:a main signal line coupled between a transmitter/receiver circuit and an antenna;
a RF switch including a series branch operably connected to the main signal line and configured to be operably controlled by a switch control signal such that the series branch selectively passes an RF signal transmitted on the main signal line between the transmitter/receiver circuit and the antenna in accordance with the switch control signal; and
a non-linear shunt circuit coupled between the main signal line and a ground potential, the non-linear shunt circuit including at least one harmonic cancellation element configured to cancel third harmonics of the RF signal that are generated by the RF switch,
wherein the non-linear shunt circuit further comprises at least one protection circuit connected in series with the harmonic cancellation element, said at least one protection circuit being configured to generate an impedance that is independent of a frequency of the RF signal,
wherein said harmonic cancellation element comprises a first and second field effect transistors connected in a back-to-back configuration, and
wherein said at least one protection circuit comprises:
a first capacitor coupled in series with said harmonic cancellation element between said main signal line and said ground potential;
a first resistor connected between said main signal line and a first gate terminal of said first field effect transistor; and
a second resistor connected between said main signal line and a second gate terminal of said second field effect transistor.

US Pat. No. 10,469,035

AMPLIFIER USING PARALLEL HIGH-SPEED AND LOW-SPEED TRANSISTORS

Newport Fab, LLC, Newpor...

1. An amplifier circuit for generating an amplified output signal on an output node in response to an unamplified input signal received at an input node, the amplifier circuit comprising:a first transistor having a first control terminal coupled to the input node and a first output terminal coupled to the output node, the first transistor being operably configured to have a first cutoff frequency; and
a second transistor having a second control terminal coupled to the input node and a second output terminal coupled to the output node, the second transistor being operably configured to have a second cutoff frequency,
wherein the first and second transistors are configured such that the first cutoff frequency is at least 1.5 times greater than the second cutoff frequency,
wherein the output node is coupled to a first voltage source by way of a resistive element,
wherein the first transistor comprises a first npn bipolar junction transistor (BJT) having a first p-doped base region connected to the input node, a first n-doped collector region connected to the output node, and a first n-doped emitter region coupled to a second voltage source, and
wherein the second transistor comprises a second npn BJT having a second base region connected to the input node, a second n-doped collector region connected to the output node, and a second n-doped emitter region coupled to the second voltage source.

US Pat. No. 10,461,253

HIGH RELIABILITY RF SWITCH BASED ON PHASE-CHANGE MATERIAL

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) switch comprising:a heating element;
a thermally resistive material adjacent to first and second sides of said heating element;
a heat valve under said heating element;
a heat spreader under said heat valve and over a substrate;
a nugget comprising a thermally conductive and electrically insulating material situated on top of said heating element;
a phase-change material having an active segment situated approximately over said nugget and passive segments situated approximately under input/output contacts of said RF switch.

US Pat. No. 10,454,027

PHASE-CHANGE MATERIAL (PCM) RADIO FREQUENCY (RF) SWITCHES WITH STRESSOR LAYERS AND CONTACT ADHESION LAYERS

Newport Fab, LLC, Newpor...

1. A radio frequency (RF) switch comprising:a stressed phase-change material (PCM) and a heating element underlying an active segment of said stressed PCM and extending outward and transverse to said stressed PCM;
passive segments of said stressed PCM situated under contacts of said RF switch;
at least one transition layer situated over said stressed PCM;
an encapsulation layer situated over said at least one transition layer and on first and second sides of said stressed PCM;
a stressor layer situated over said encapsulation layer and said stressed PCM.

US Pat. No. 9,458,011

SCALABLE SELF-SUPPORTED MEMS STRUCTURE AND RELATED METHOD

Newport Fab, LLC, Newpor...

7. A method of forming a self-supported MEMS structure, said method comprising:
forming a polymer layer over a MEMS plate over a substrate;
forming a trench over said MEMS plate;
forming an oxide liner in said trench on sidewalls of said trench;
depositing a metallic filler in said trench to form a via;
removing said polymer layer such that said via and said MEMS plate form said self-supported MEMS structure.