US Pat. No. 9,588,170

SYSTEMS AND METHODS FOR TEST CIRCUITRY FOR INSULATED-GATE BIPOLAR TRANSISTORS

NXP USA, INC., Austin, T...

1. A saturation edge detection circuit for testing a saturation level in an insulated gate bipolar transistor (“IGBT”), the
circuit comprising:
a first input operable to receive an on signal;
a second input coupled to an IGBT driver circuit; and
an output coupled to a control electrode of the IGBT, the output operable to indicate a change in a state of a saturation
voltage associated with the IGBT during operation of the IGBT;

a first latch having a first input coupled to a supply voltage and a second input coupled to an output of a comparator, the
comparator being part of the IGBT driver circuit;

a second latch having a first input coupled to an output of the first latch, and a second input operable to receive a delayed
on signal.

US Pat. No. 9,544,019

SYSTEMS AND METHODS FOR RIPPLE COMMUNICATION DECODING

NXP USA, Inc., Austin, T...

1. A ripple control receiver, comprising:
a ripple signal extractor configured to receive a power signal having a superimposed ripple signal and extract the ripple
signal from the power signal, wherein the ripple signal extractor comprises

a band-pass filter having an input and an output, the band-pass filter configured to receive the power signal having the superimposed
ripple communication signal, and

a signal-squaring element having an input and an output, the signal-squaring element input coupled to the band-pass filter
output, the signal-squaring element output coupled to a fast low-pass filter and a slow low-pass filter;

the fast low-pass filter configured to receive the extracted ripple signal and generate a first filtered ripple signal;
the slow low-pass filter configured to receive the extracted ripple signal and generate a second filtered ripple signal;
an accumulator configured to accumulate a difference between the first filtered ripple signal and the second filtered ripple
signal and generate an accumulated value in response to the accumulated difference; and

decoding logic configured to receive the accumulated value and decode ripple control data from the accumulated value.

US Pat. No. 9,538,659

SOLDER WETTABLE FLANGES AND DEVICES AND SYSTEMS INCORPORATING SOLDER WETTABLE FLANGES

NXP USA, INC., Austin, T...

1. A solder wettable flange comprising:
a flange body formed from a conductive material and having a bottom surface, a top surface, sidewalls extending between the
top surface and the bottom surface, and one or more depressions extending into the body from the bottom surface, wherein each
depression is defined by a depression surface, the bottom surface is solder wettable, and the sidewalls are non-solder wettable
due to a feature selected from oxidation of the sidewalls, and the sidewalls being at least partially formed from a non-solder
wettable material.

US Pat. No. 9,536,869

ELECTROSTATIC DISCHARGE PROTECTION APPARATUS AND METHOD THEREFOR

NXP USA, Inc., Austin, T...

1. An electrostatic discharge protection apparatus, comprising:
a stack arrangement having:
a first electrostatic discharge protection element comprising a first terminal, and a second terminal; and
a second electrostatic discharge element comprising a first terminal, and a second terminal, the first electrostatic discharge
protection element serially coupled to the second electrostatic discharge protection element, wherein the first electrostatic
discharge protection element includes a transistor having a collector terminal, an emitter terminal, and a base terminal connected
to the emitter terminal; the stack arrangement to provide a bias potential between the first and second electrostatic discharge
protection elements based on a breakdown voltage of the first and second electrostatic discharge protection elements;

the stack arrangement further comprises a clamp arrangement including a first voltage clamp serially coupled to a second voltage
clamp, the clamp arrangement to provide a further bias potential across the first and second electrostatic discharge protection
elements responsive to a breakdown voltage of each of the first and second voltage clamps, wherein a potential at the node
between the first and second electrostatic discharge protection elements is substantially equal to a potential at a node between
the first and second voltage clamps; and

the second electrostatic discharge protection element is further inhibited from responding to a parasitic event at potentials
below the further bias potential in response to the breakdown voltage of the first and second electrostatic discharge protection
elements being higher than the breakdown voltage of the first and second voltage clamps.

US Pat. No. 9,543,015

MEMORY ARRAY AND COUPLED TCAM ARCHITECTURE FOR IMPROVED ACCESS TIME DURING SEARCH OPERATION

NXP USA, Inc., Austin, T...

1. A memory device comprising:
a first ternary content addressable memory (TCAM);
a second TCAM;
a memory array coupled to the first and second TCAMs;
a first priority logic coupled between the first TCAM and the memory array;
a second priority logic coupled between the second TCAM and the memory array; and
a look-ahead signal generated by the first priority logic and provided to the second priority logic, wherein match lines from
the first and second TCAMs are coupled to respective word lines in the memory array, and

wherein a pitch of match lines for the first and second TCAMs is approximately twice a pitch of word lines in the memory array.

US Pat. No. 9,543,067

MAGNETIC PRE-CONDITIONING OF MAGNETIC SENSORS

NXP USA, INC., Austin, T...

1. A method executable by a handler apparatus to process a fabricated sensor device that comprises a magnetic sensing element
and a flux guide aligned to direct magnetic flux toward the magnetic sensing element, the method comprising:
passing the fabricated sensor device through an externally applied magnetic field applied by an external magnetic field source
that is outside of the fabricated sensor device by the handler apparatus, the externally applied magnetic field having a component
aligned along a long axis of the flux guide, the component of the externally applied magnetic field having a magnitude along
the long axis of the flux guide sufficient to place the flux guide of the fabricated sensor device into a known magnetic state;

prior to passing the fabricated sensor device through the externally applied magnetic field, the handler apparatus aligning
the fabricated sensor device to the externally applied magnetic field so that the long axis of the flux guide is aligned to
the component of the externally applied magnetic field while the fabricated sensor device passes through the externally applied
magnetic field to thereby magnetically pre-condition the fabricated sensor device prior to testing and operation of the fabricated
sensor device; and

after passing the fabricated sensor device through the externally applied magnetic field, the handler apparatus providing
the fabricated and pre-conditioned sensor device for subsequent testing and operation of the fabricated sensor device.

US Pat. No. 9,542,334

MEMORY MANAGEMENT UNIT TAG MEMORY WITH CAM EVALUATE SIGNAL

NXP USA, INC., Austin, T...

1. A method for generating a speculative miss signal from base and offset operands without requiring addition of the base
and offset operands comprising:
receiving a base operand and offset operand, wherein each operand comprises a first plurality of address bits comprising tag
bits and index bits;

pairing each address bit from the base operand with a corresponding address bit from the offset operand, thereby forming a
plurality of index bit pairs and a plurality of tag bit pairs;

applying the plurality of index bit pairs and the plurality of tag bit pairs to an indexed content-addressable memory (CAM)
array to generate two speculative miss signals from two speculatively indexed rows by using a two stage dynamic comparator
to generate a speculative odd miss signal and a speculative even miss signal, respectively, in response to a delayed evaluate
signal that is delayed with respect to a control word line signal applied to the two speculatively indexed rows; and

selecting one of the speculative odd miss signal and speculative even miss signal for output based on a sum value computed
by adding at least the least significant index bit of the base operand with the least significant index bit of the offset
operand.

US Pat. No. 9,553,548

LOW DROP OUT VOLTAGE REGULATOR AND METHOD THEREFOR

NXP USA, INC., Austin, T...

1. A circuit comprising:
a first stage amplifier having a first input coupled to receive a reference voltage, a second input, a first output, and a
second output;

a second stage amplifier having a first input coupled to the first output of the first stage amplifier, a second input coupled
to the second output of the first stage amplifier, and an output;

a feed-forward amplifier having a first input coupled to receive the reference voltage, a second input, and an output coupled
to the output of the second stage amplifier;

a transistor having a control terminal coupled to the output of the second stage amplifier and to the output of the feed-forward
amplifier, a first current terminal coupled to an output voltage terminal and a second current terminal coupled to a first
voltage supply;

a first resistive element having a first terminal coupled to the output voltage terminal and a second terminal coupled to
the second input of the first stage amplifier and to the second input of the feed-forward amplifier; and

a second resistive element having a first terminal coupled to the second terminal of the first resistive element and a second
terminal coupled to a second voltage supply.

US Pat. No. 9,606,802

PROCESSOR SYSTEM WITH PREDICATE REGISTER, COMPUTER SYSTEM, METHOD FOR MANAGING PREDICATES AND COMPUTER PROGRAM PRODUCT

NXP USA, INC., Austin, T...

18. A method, comprising:
executing, by a processing unit of a processor system, a predicate swap instruction of a predetermined instruction set to
perform:

swapping, by the processing unit, predicate data at a first predicate data location of a first plurality of predicate data
locations of a predicate register with data at a corresponding general purpose data location of a first set of M sets of general
purpose register locations of a second plurality of general purpose data locations based on a first portion of the predicate
swap instruction identifying the first predicate data location and a second portion of the predicate swap instruction identifying
the first set of the M sets; and

swapping, by the processing unit, predicate data at a second predicate data location of the first plurality of predicate data
locations with data at a corresponding general purpose data location of a second set of the M sets based on a third portion
of the predicate swap instruction identifying the second predicate data location and a fourth portion of the predicate swap
instruction identifying the second set of the M sets.

US Pat. No. 9,531,328

AMPLIFIERS WITH A SHORT PHASE PATH, PACKAGED RF DEVICES FOR USE THEREIN, AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A packaged radio frequency (RF) amplifier device comprising:
an input lead;
an output lead;
a first transistor that includes a control terminal and first and second current carrying terminals, wherein the control terminal
is coupled to the input lead, the first current carrying terminal is coupled to a voltage reference, and the first transistor
is characterized by a first drain-source capacitance; and

an inverse class-F circuit coupled between the second current carrying terminal and the output lead and configured to harmonically
terminate the RF amplifier device, wherein the inverse class-F circuit includes

a first shunt circuit coupled between a first cold point node and the voltage reference, wherein the first cold point node
corresponds to a second harmonic frequency cold point for the RF amplifier device, and wherein the first cold point node is
located on a signal path between the second current carrying terminal and the output lead, and the first shunt circuit adds
a shunt negative susceptance to the inverse class-F circuit at a fundamental frequency of the RF amplifier device, and

a second shunt circuit coupled between the first cold point node and the voltage reference, wherein the second shunt circuit
is resonant at the second harmonic frequency.

US Pat. No. 9,521,636

SYNCHRONIZATION CIRCUITRY, COMMON PUBLIC RADIO INTERFACE ENABLE DEVICE, AND A METHOD OF SYNCHRONIZING A SYNCHRONIZED CLOCK SIGNAL OF A SECOND TRANSCEIVER TO A CLOCK OF A FIRST TRANSCEIVER

NXP USA, INC., Austin, T...

1. A controller device for a data interface between a slave sub-system and a master sub-system in a chain of at least two
sub-systems in a mobile communication base station system, each of the sub-systems comprising at least one slave sub-system
and at least one master sub-system for controlling the time of the slave sub-system, the at least one master sub-systems comprising
a synchronization master sub-system controlling a time synchronization of the chain to an external clock external to the chain,
the controller device comprising:
a slave transceiver, for receiving a received signal representing binary data from a master sub-system, the binary data having
a bit duration controlled by a clock cycle of a transmit clock of the master sub-system, and the transmitting data to the
master sub-system, the transceiver being connected with a clock input to a controllable phase locked loop, PLL, for clocking
the transceiver with the transmit clock; and

a synchronization device for synchronizing the transmit clock of the slave transceiver to a clock of a master transceiver
of the master sub-system based on the received signal received from the master sub-system, the synchronization circuitry comprising:

a clock input port for receiving an external clock signal from an external clock generator;
a received signal input port for receiving the received signal from the master transceiver;
said PLL, for generating the transmit clock, the PLL comprising a PLL output for outputting the transmit clock, a first phase
input coupled to the clock input port and a second phase input coupled to the PLL output via a negative feedback loop for
providing a negative feedback signal; and

a frequency and phase tracking loop coupling the received signal input and the second phase input, for providing a selection
signal which controls a phase and/or frequency of the negative feedback signal to counter phase and or frequency error between
the external clock signal and the received signal,

wherein the frequency and phase tracking loop comprises:
a clock recovery circuit for generating a receiver clock signal on basis of the transmit clock signal and the received signal,
a phase detector circuit for generating a phase error signal, the phase detector circuit receiving the negative feedback signal
and the receiver clock signal of which the frequency is divided by a first factor, the phase error signal indicating a phase
difference between the negative feedback signal and the divided receiver clock signal,

a selection signal generator for generating the selection signal on basis of the phase error signal, to select the selected
clock signal, wherein the selection signal generator comprises an integrator and counter circuit for generating the selection
signal.

US Pat. No. 9,524,256

REQUEST CONTROLLER, PROCESSING UNIT, ARRANGEMENT, METHOD FOR CONTROLLING REQUESTS AND COMPUTER PROGRAM PRODUCT

NXP USA, INC., Austin, T...

1. An interrupt request controller to control an interrupt request of at least one processing unit, said interrupt request
requesting to switch a context of said processing unit or to switch said processing unit from a current operation to another
operation, said interrupt request controller comprising:
a controller input to receive the interrupt request;
a request processing unit connected to said controller input, the request processing unit to decide whether to grant said
received interrupt request based on at least one decision criterion;

a controller output connected to said request processing unit, the controller output to provide information about at least
one granted request;

wherein said request processing unit includes:
a control logic unit including:
a state input to receive information about a current state in a logic flow of an application executing in said processing
unit; and

a request input to receive information about the received interrupt request;
said control logic unit arranged to determine whether said received interrupt occurs too often, to determine whether said
received interrupt request belongs to said current state of the logic flow of the application, to grant said received interrupt
request in response to said received interrupt request belonging to said current state of the application and to reject said
received interrupt request in response to the received interrupt request not belonging to said current state of the logic
flow of the application;

said control logic unit further including a control logic output to provide a request grant signal in response to said received
interrupt request being granted.

US Pat. No. 9,527,731

METHODOLOGY AND SYSTEM FOR WAFER-LEVEL TESTING OF MEMS PRESSURE SENSORS

NXP USA, Inc., Austin, T...

1. A method for testing a plurality of pressure sensors on a device wafer, wherein said pressure sensors are located on a
first side of a substrate portion of said device wafer, each of said pressure sensors includes a cavity, a port extends through
said substrate portion from a second side of said substrate portion to said first side into said cavity, and said method comprises:
placing a diaphragm of one of said pressure sensors on said device wafer in proximity to a nozzle of a test system;
positioning a seal element surrounding an outlet of said nozzle in contact with said second side of said substrate portion
surrounding said port;

applying mechanical force to said seal element to form a pressure seal between said second side of said substrate portion
and said seal element;

applying a pneumatic pressure stimulus to said diaphragm via said outlet of said nozzle, wherein said pneumatic pressure stimulus
is imposed on said diaphragm via said port and said cavity associated with said one of said pressure sensors; and

measuring a cavity pressure within said cavity in response to said applying said pneumatic pressure stimulus.

US Pat. No. 9,529,374

LOW DROP-OUT VOLTAGE REGULATOR AND A METHOD OF PROVIDING A REGULATED VOLTAGE

NXP USA, Inc., Austin, T...

1. A low drop-out voltage regulator for providing a regulated voltage, the low drop-out voltage regulator comprises
a supply voltage terminal for receiving a supply voltage;
a regulated voltage terminal for providing the regulated voltage;
a regulated voltage driver for providing the regulated voltage to the regulated voltage terminal in response to a control
voltage;

a feedback-loop circuit for generating the control voltage on basis of a feedback voltage such that the regulated voltage
driver provides the regulated voltage wherein, in the feedback-loop circuit, a first feedback voltage is generated which relates
to the value of the regulated voltage on basis of a first ratio between the first feedback voltage and the regulated voltage;

a pull-up circuit for pulling the regulated voltage up to the supply voltage when a difference between the supply voltage
and the control voltage is smaller than a predefined voltage difference, wherein

the pull-up circuit is configured to provide a pull-up signal to the feedback-loop circuit when the regulated voltage is pulled
up to the supply voltage, and

the feedback-loop circuit is configured to generate a second feedback voltage instead of the first feedback voltage when it
receives the pull-up signal the second feedback voltage is generated on basis of a second ratio between the second feedback
voltage and the regulated voltage, the second ratio is different from the first ratio and the second ratio is for preventing
oscillations in the low drop-out voltage regulator.

US Pat. No. 9,565,137

CUT-THROUGH FORWARDING MODULE AND A METHOD OF RECEIVING AND TRANSMITTING DATA FRAMES IN A CUT-THROUGH FORWARDING MODE

NXP USA, Inc., Austin, T...

1. A cut-through forwarding module comprising:
a receiver unit being configured to receive data frames and to partition data packets of the data frames into data blocks,
a transmitter unit being configured to transmit data frames based on received data packets,
a pre-loading unit being configured to store a first data block of a first received data frame and to pre-load the stored
first data block into the transmitter unit before a subsequent data frame is being received by the receiver unit,

a processing unit being configured to control a transfer of the first data block of the first received data frame to the pre-loading
unit and to control use of the pre-loaded first data block as a first data block of subsequent data frame to be transmitted
by the transmitter unit, the subsequent data frame is to be transmitted after a transmission of a first transmitted data frame
being based on the first received data frame.

US Pat. No. 9,552,279

DATA BUS NETWORK INTERFACE MODULE AND METHOD THEREFOR

NXP USA, INC., Austin, T...

1. A microcontroller device comprising:
a host processing module;
a debug module; and
a data bus network interface module for enabling reception and transmission of application messages to/from a remote network
node via a data bus network, the data bus network interface module being arranged to:

receive a data bus message from the remote network node via the data bus network, read a non-data field of the data bus message,
and make data content of the data bus message available to the debug module if the non-data field comprises a value defined
for debug use; and

receive data from the debug module for transmission over the data bus network and, upon receipt of said data from the debug
module, to generate a second data bus message containing the received data and comprising a second non-data field value defined
for debug use.

US Pat. No. 9,552,893

SAMPLE-AND-HOLD CIRCUIT AND CAPACITIVE SENSING DEVICE THAT INCLUDES THE SAMPLE-AND-HOLD CIRCUIT

NXP USA, Inc., Austin, T...

1. A sample-and-hold circuit comprising:
an input;
one or more dedicated capacitive elements;
one or more parasitic capacitive elements connected to said one or more dedicated capacitive elements;
an output;
a group of switches; and
a control unit, wherein
said control unit is arranged to control said switches so as to interconnect said input, said one or more dedicated capacitive
elements, and said output in a cyclic manner in accordance with a sample-and-hold cycle, and

the sample-and-hold cycle comprises, in chronological order,
an observation phase in which said one or more dedicated capacitive elements are disconnected from said output and connected
to said input so as to adapt an electrical charge of said dedicated capacitive elements to an input voltage applied at said
input,

a read-out phase in which said one or more dedicated capacitive elements are disconnected from said input and connected to
said output so as to provide an output voltage in dependence on said electrical charge,

a sleep phase in which said one or more dedicated capacitive elements are disconnected from both said input and said output,
said sleep phase involving a forward charge transfer between said one or more dedicated capacitive elements and said one or
more parasitic capacitive elements, and

a restoration phase in which said one or more dedicated capacitive elements are disconnected from said input and connected
to said output so as to cause a reverse charge transfer between said one or more dedicated capacitive elements and said one
or more parasitic capacitive elements, said reverse charge transfer canceling said forward charge transfer at least partly.

US Pat. No. 9,553,446

SHARED ESD CIRCUITRY

NXP USA, INC., Austin, T...

1. An integrated circuit comprising:
an ESD clamp circuit;
a first bus coupled to a first current electrode of the ESD clamp circuit;
a first diode coupled between the first bus and the first current electrode;
a second bus coupled to the first current electrode of the ESD clamp circuit;
a second diode coupled between the second bus and the first current electrode;
a first plurality of terminals, each terminal of the first plurality coupled to the first bus;
a second plurality of terminals, each terminal of the second plurality coupled to the second bus; and
a trigger circuit including a first input coupled to a first node to sense an ESD event occurring on at least one terminal
of the first plurality of terminals, a second input coupled to a second node to sense an ESD event occurring on at least one
terminal of the second plurality of terminals, and an output coupled to a control electrode of the ESD clamp circuit for making
the ESD clamp circuit conductive in response to a sensed ESD event on at least one terminal of the first plurality of terminals
to discharge current from the sensed ESD event on the first bus through the first diode and for making the ESD clamp circuit
conductive in response to a sensed ESD event on at least one terminal of the second plurality of terminals to discharge current
from the sensed ESD event on the second bus through the second diode.

US Pat. No. 9,531,373

GATE DRIVE CIRCUIT AND A METHOD FOR SETTING UP A GATE DRIVE CIRCUIT

NXP USA, Inc., Austin, T...

1. A gate drive circuit for a power transistor, the gate drive circuit comprising:
a first switch,
a first capacitor, a first terminal of the first capacitor being electrically coupled to the first switch, the first switch
being electrically coupled between the first terminal and a voltage supply of the power transistor, a second terminal of the
first capacitor being electrically coupled to the reference potential,

a first voltage limiter in parallel with the first capacitor for limiting a voltage across the first capacitor to a first
predetermined voltage,

a second capacitor,
a pre-charging circuit arranged between the first terminal of the first capacitor and a first terminal of the second capacitor,
a third capacitor, a first terminal of the third capacitor being electrically coupled to a second terminal of the second capacitor,
a second terminal of the third capacitor being electrically coupled to a gate terminal of the power transistor,

a second switch arranged between the first terminal of the first capacitor and the second terminal of the second capacitor,
a third switch arranged between the first terminal of the third capacitor and the reference potential,
a fourth switch arranged between the second terminal of the third capacitor and the reference potential,during a setup of the gate drive circuit after applying the voltage supply:
the gate drive circuit being configured to arrange the first switch in an on state to electrically couple the supply voltage
to the first terminal for charging the first capacitor to obtain the first predetermined voltage across the first capacitor,
the gate drive circuit being further configured to configure the pre-charging circuit to pre-charge the second capacitor to
obtain a second predetermined voltage across the second capacitor and the gate drive circuit being further configured to pre-charge
the third capacitor to obtain a third predetermined voltage across the third capacitor, the gate drive circuit being configured
to be powered by the voltage across the first capacitor.

US Pat. No. 9,531,167

DEVICE AND METHOD FOR CONNECTING AN RF GENERATOR TO A COAXIAL CONDUCTOR

NXP USA, INC., Austin, T...

1. A device, comprising:
a substrate;
a radio frequency generator on the substrate, the radio frequency generator being configured to receive an input signal and
output a radio frequency signal at an output contact pad;

a coaxial conductor coupled to a first surface of the substrate, the coaxial conductor including a conductive core and a conductive
shield around the conductive core and being configured to transmit the radio frequency signal to a radiation device; and

a cap coupled to the substrate and extending from a second surface of the substrate opposite the first surface, the cap including
an outer wall and a center post, the outer wall being electrically connected to the conductive shield of the coaxial conductor
and the center post being electrically connected to the conductive core of the coaxial conductor; and

wherein the output contact pad is electrically connected to the conductive core.

US Pat. No. 9,554,240

MULTIPLE CONNECTION MANAGEMENT FOR BLUETOOTH LOW ENERGY DEVICES

NXP USA, Inc., Austin, T...

1. A method to manage connections to a Bluetooth device, comprising:
performing a power-on reset (PoR) for a Bluetooth (BT) device having a volatile memory and a non-volatile memory (NVM), the
NVM storing device identification information (DII) data and persistent BT data associated with a plurality of bonded BT peer
devices; and

prior to an active connection being formed with one of the bonded BT peer devices,
accessing the DII data within the NVM; and
storing the DII data in the volatile memory;
wherein the persistent BT data is not stored in the volatile memory prior to an active connection being formed with one of
the bonded BT peer devices.

US Pat. No. 9,553,184

EDGE TERMINATION FOR TRENCH GATE FET

NXP USA, INC., Austin, T...

1. A semiconductor device comprising:
a semiconductor layer disposed at a substrate of the semiconductor device, the semiconductor layer having a first conductivity
type;

a plurality of active cells disposed at the semiconductor layer, each active cell comprising:
a trench extending into the semiconductor layer from a surface of the semiconductor layer;
a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the active cell and at a first depth
below the surface such that the entirety of the body region is separated from the surface by a directly interposing region
of the semiconductor layer, the body region of the active cell having a second conductivity type different than the first
conductivity type; and

a first body contact region extending from the body region of the active cell to the surface of the semiconductor layer, and
a termination cell disposed at the semiconductor layer adjacent to an edge of the plurality of active cells, the termination
cell comprising:

a trench extending into the semiconductor layer from the surface of the semiconductor layer;
a body region disposed in the semiconductor layer adjacent to a sidewall of the trench of the termination cell and at a second
depth less than the first depth, the body region of the termination cell having the second conductivity type; and

a second body contact region extending from the body region of the termination cell to the surface of the semiconductor layer;
and

wherein the body region of the termination cell extends from the second depth to a third depth at its lowermost depth, and
the body regions of the active cells extend from the first depth to a fourth depth at their lowermost depths, the fourth depth
greater than the third depth.

US Pat. No. 9,528,881

STRESS ISOLATED DETECTOR ELEMENT AND MICROBOLOMETER DETECTOR INCORPORATING SAME

NXP USA, Inc., Austin, T...

1. A detector element for a microbolometer detector comprising:
a platform structure spaced apart from a substrate, said platform structure having a central region and a peripheral region
surrounding said central region, said peripheral region being circumscribed by a first edge, a second edge, a third edge,
and a fourth edge, said first and third edges opposing one another, said second and fourth edges opposing one another;

a first contact located at said peripheral region of said platform structure proximate said first edge;
a second contact located at said peripheral region proximate said third edge;
a beam structure extending across said central region between said first and second contacts; and
at least one sensor located at said peripheral region proximate at least one of said second and fourth edges.

US Pat. No. 9,525,570

CURRENT SENSING CIRCUITRY AND INTEGRATED CIRCUIT AND METHOD FOR SENSING A CURRENT

NXP USA, Inc., Austin, T...

1. Current sensing circuitry for sensing a current through a load, the current sensing circuitry comprising:
an adaptive-resistance sensor component operably coupled in series with the load; and
control logic for controlling a resistance of the adaptive-resistance sensor component, wherein the control logic is arranged
to:

receive a voltage signal across the adaptive-resistance sensor component,
compare the received voltage signal to a determined reference value; and
in response to the comparison, control the resistance of the adaptive-resistance sensor component, such that the voltage signal
across the adaptive-resistance sensor component substantially tracks the determined reference value, wherein the control logic
comprises:

an up-down counter, having as an output a control signal arranged to control the resistance of the adaptive-resistance sensor
component, wherein the current sensing circuitry further comprises current regulation circuitry arranged to receive the control
signal output by the up-down counter, and the up-down counter further being arranged to count in a first direction if the
received voltage signal is greater than the determined reference value; and count in a second direction opposite to the first
direction if the received voltage signal is less than the determined reference value; and

comparator logic arranged to compare the received voltage signal to the determined reference value and to provide an indication
to the up-down counter as to whether the received voltage signal is less than or greater than the determined reference value,
wherein the comparator logic comprises:

a synchronous comparator arranged to perform the comparison of the received voltage signal to the determined reference value
and to provide an indication to the up-down counter as to whether the received voltage signal is less than or greater than
the determined reference value on one of a positive edge or a negative edge of a clock signal; and

the up-down counter is further arranged to count up or count down, depending on the received indication on the other of the
positive edge or negative edge of the clock signal.

US Pat. No. 9,602,314

COMMUNICATIONS RECEIVER EQUALIZER

NXP USA, Inc., Austin, T...

1. A delay cell comprising:
a transconductance stage configured to convert a differential input voltage signal to a differential output current signal,
wherein the transconductance stage comprises:

a differential pair of first and second transistors coupled in a source degeneration configuration;
a negative resistance network coupled in parallel with a tunable resistor network; and
shunt inductive circuitry coupled in parallel with the negative resistance network.

US Pat. No. 9,563,590

DEVICES WITH ARBITRATED INTERFACE BUSSES, AND METHODS OF THEIR OPERATION

NXP USA, INC., Austin, T...

1. A device, comprising:
data storage including one or more registers configured to store data;
a plurality of external interfaces, each of the plurality of external interfaces configured to receive substantially simultaneously
during a first communication interval a data access request for access to the one or more registers, the data access requests
comprising one of a read request to the one or more registers and a write request to the one or more registers;

an arbitrator communicatively coupled to each of the plurality of external interfaces; and
an interface bus communicatively coupled between the arbitrator and the one or more registers,
wherein the arbitrator is configured to arbitrate control of the interface bus between the plurality of external interfaces
during a first single processing interval subsequent to the first communication interval to complete each write request and
retrieve data for each read request during the first single processing interval, and

wherein the plurality of external interfaces are configured to substantially simultaneously transmit the retrieved data for
each read request during a second communication interval subsequent to the first single processing interval.

US Pat. No. 9,543,454

DIODES WITH MULTIPLE JUNCTIONS

NXP USA, Inc., Austin, T...

1. A diode comprising:
a semiconductor substrate having a surface;
a first contact region disposed at the surface of the semiconductor substrate and having a first conductivity type;
a second contact region disposed at the surface of the semiconductor substrate, laterally spaced from the first contact region,
and having a second conductivity type,

a buried region disposed in the semiconductor substrate, the buried region vertically adjacent to the first contact region,
the buried region having the second conductivity type, and electrically connected with the second contact region;

an isolation region disposed at the surface of the semiconductor substrate between the first contact region and the second
contact region; and

a separation region disposed at the surface of the semiconductor substrate between the first contact region and the isolation
region, the separation region formed from a portion of first well region disposed in the semiconductor substrate that extends
to the surface.

US Pat. No. 9,749,161

FIXED-POINT CONJUGATE GRADIENT DIGITAL PRE-DISTORTION (DPD) ADAPTATION

NXP USA, Inc., Austin, T...

1. A method for predistorting an input signal, comprising:
receiving, at an input of a digital predistortion actuator, a first input signal comprising a plurality of input signal samples
to be transmitted over a non-linear electronic device;

applying, at the digital predistortion actuator, a memory polynomial comprising a first set of pre-equalizing filtering coefficients
to generate a first pre-distorted input signal which is provided to the non-linear electronic device to produce an output
signal;

computing, at a digital predistortion adapter, a second set of pre-equalizing filtering coefficients with an iterative fixed-point
conjugate gradient method by:

generating an initialized set of conjugate gradient parameters based on N received digital samples of the first pre-distorted
input signal and N received digital samples captured from the output signal by defining an initial solution u=u_init for the
second set of pre-equalizing filtering coefficients and initializing an initial output value b=average(z(0)·A·y(0)), an initial
search direction value v=b?A·u, an initial residual value r=v, and an initial residual magnitude value ?=v?·v, where z(0)
is a first output signal value, A is a covariance matrix, and y(0) is a first pre-distorted input signal value,

computing one or more scalar conjugate gradient parameters having a dynamic range that is suitable for fixed-point arithmetic,
and

processing the initialized set of conjugate gradient parameters and the one or more scalar conjugate gradient parameters to
update selected conjugate gradient parameters, thereby generating the second set of pre-equalizing filtering coefficients;
and

updating the first set of pre-equalizing filtering coefficients with the second set of pre-equalizing filtering coefficients
to adaptively modify the memory polynomial applied at the digital predistortion actuator to generate a second pre-distorted
input signal which is provided to the non-linear electronic device to produce the output signal.

US Pat. No. 9,596,669

METHOD AND APPARATUS FOR TRANSMITTING DATA

NXP USA, INC., Austin, T...

1. A method for transmitting data across an interface, the method comprising:
determining a first default symbol interval boundary;
transmitting a first burst of data across the interface at a time based upon the first default symbol interval boundary;
receiving a unit interval timing signal;
receiving a symbol interval value;
dividing the unit interval timing signal by the received symbol value to generate a symbol interval timing signal;
determining a second default symbol interval boundary;
transmitting a second burst of data across the interface, wherein the start of the second burst of data is aligned with the
second default symbol interval boundary based on a start of the symbol interval timing signal in the second default symbol
interval boundary;

determining a third default symbol interval boundary, the time between the first and second default symbol interval boundaries
being the same as the time between the second and third default interval boundaries;

determining an offset based on a unit interval of a fixed amount of time;
applying the offset to the third default symbol interval boundary at a start of a burst of data; and
transmitting a third burst of data across the interface, wherein the start of the third burst of data is aligned with the
offset and not aligned with the third default symbol interval boundary.

US Pat. No. 9,543,942

METHOD AND APPARATUS FOR CONTROLLING AN IGBT DEVICE

NXP USA, Inc., Austin, T...

1. A control module for controlling at least one insulated gate bipolar transistor, IGBT, device; the control module comprising
at least one output arranged to be operably coupled to at least one IGBT driver module for the at least one IGBT device;
the control module is arranged to receive a first IGBT control signal indicating a required operating state of the at least
one IGBT device and at least one further IGBT control signal;

wherein the control module is further arranged to, upon the first IGBT control signal indicating a required change in operating
state of the at least one IGBT device:

control the at least one IGBT driver module to change an operating state of the at least one IGBT device by applying a first
logical state modulation at the output thereof; and

apply at least one further modulation to the logical state at the output thereof in accordance with the at least one further
IGBT control signal within a time period from the first logical state transition, the time period being less than a state
change reaction period ?t for the at least one IGBT device.

US Pat. No. 9,536,614

COMMON SOURCE ARCHITECTURE FOR SPLIT GATE MEMORY

NXP USA, Inc., Austin, T...

1. A memory system, comprising:
a plurality of split gate non-volatile memory (NVM) cells, wherein:
each split gate NVM cell has a control gate and a source,
the plurality of split gate NVM cells are arranged into a plurality of program sectors,
each program sector of the plurality of sectors includes a subset of split gate NVM cells of the plurality of split gate NVM
cells, and

each program sector has the control gates of its subset of split gate NVM cells physically shorted together; and
a program/erase circuit configured to
erase a first erase sector that comprises the plurality of program sectors by applying an erase voltage to the control gates
of each of the split gate NVM cells of the first erase sector, which includes each subset of split gate NVM cells of the plurality
of program sectors; and

program a selected program sector of the plurality of program sectors by simultaneously:
applying a programming signal to the control gates of the split gate NVM cells of the selected program sector,
applying a non-programming signal to the control gates of the split gate NVM cells of program sectors of the plurality of
program sectors that are not selected for programming, and

applying a source voltage to the sources of each of the split gate NVM cells of the first erase sector.

US Pat. No. 9,588,530

VOLTAGE REGULATOR CIRCUIT AND METHOD THEREFOR

NXP USA, Inc., Austin, T...

1. A voltage regulator circuit arranged to receive a voltage supply signal, and to output a regulated voltage signal; the
voltage regulator circuit comprising:
a switched mode power supply component selectively configurable to perform regulation of the voltage supply signal;
a linear voltage regulator component selectively configurable to perform regulation of the voltage supply signal, the linear
voltage regulator comprising a switching device, and a diode coupled between a bulk connection of the switching device and
an input of the voltage regulator;

a controller component arranged to receive an indication of a voltage level of the voltage supply signal, to configure the
bulk connection of the switching device, and to selectively configure the linear voltage regulator component to perform regulation
of the voltage supply signal during a quiescent operating mode of the voltage regulator circuit, if the indicated voltage
level of the voltage supply signal is greater than the threshold voltage level, wherein while the quiescent operating mode
the linear voltage regulator component to maintain an particular output voltage level without a load current being driven
by the linear voltage regulator component,

the diode to cause a current flow from an output of the voltage regulator circuit to the input of the voltage regulator circuit
through the bulk connection of the switching device to be resisted, if the indicated voltage level of the voltage supply signal
is less than a threshold voltage level.

US Pat. No. 9,564,861

BROADBAND RADIO FREQUENCY POWER AMPLIFIERS, AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A packaged amplifier device having a bandwidth defined by a range of frequencies between a low cutoff frequency and an
upper cutoff frequency, the amplifier device comprising:
an input lead configured to receive an input radio frequency (RF) signal;
an output lead configured to produce an amplified RF signal;
a transistor having a gate, a first current conducting terminal coupled to the output lead, and a second current conducting
terminal coupled to a reference node; and

an input impedance matching circuit including an integrated passive device, a first node, a second node, and a reference node,
and having a first inductance having a first terminal coupled to the input lead and a second terminal coupled to the first
node, a filter output coupled to the gate of the transistor, and a plurality of passive components that form a multiple pole
filter, wherein a first pole of the filter is positioned at a first frequency within the bandwidth, and a second pole of the
filter is positioned at a second frequency outside the bandwidth, and the input impedance matching circuit is configured to
filter the input RF signal to produce a filtered RF signal at the filter output, and wherein the integrated passive device
includes

a first integrated capacitance having a first terminal coupled to the first node, and a second terminal coupled to the reference
node,

a second inductance having a first terminal coupled to the first node, and a second terminal coupled to a second node, and
a second integrated capacitance having a first terminal coupled to the second node, and a second terminal coupled to the reference
node, wherein the first and second inductance and the first and second capacitance define the first pole of the filter, and
the second inductance and the second capacitance define the second pole of the filter, and wherein the second node is coupled
to the gate of the transistor.

US Pat. No. 9,540,227

INHIBITING PROPAGATION OF SURFACE CRACKS IN A MEMS DEVICE

NXP USA, Inc., Austin, T...

1. A microelectromechanical systems (MEMS) device comprising:
a structural layer having a surface, said surface including a first surface region and a second surface region adjacent to
said first surface region, said first surface region lying in a first plane that is offset from a second plane of said second
surface region, said second plane being substantially parallel to said first plane, and said surface including a longitudinal
joint between said first and second surface regions; and

at least one trench formed in said surface of said structural layer extending across said longitudinal joint.

US Pat. No. 9,542,351

MEMORY CONTROLLER, COMPUTING DEVICE WITH A MEMORY CONTROLLER, AND METHOD FOR CALIBRATING DATA TRANSFER OF A MEMORY SYSTEM

NXP USA, INC., Austin, T...

1. A memory controller, comprising:
a connection interface connected or connectable to a memory, the memory controller being arranged to read data from the memory
via the connection interface;

a clock unit arranged to provide a data transfer clock signal having a first frequency, wherein the data transfer clock signal
is provided to the memory via the connection interface, the data transfer clock signal being arranged for clocking a data
transfer from the memory to the memory controller via the connection interface;

an oversampling circuit arranged to sample a calibration data pattern read by the memory controller via the connection interface
at a second frequency to provide an oversampled calibration data pattern, the second frequency being larger than the first
frequency, and wherein the calibration data pattern includes a predetermined sequence of bits;

wherein the memory controller is arranged to determine a timing shift of a data transfer from the memory to the memory controller
based on the oversampled calibration data pattern.

US Pat. No. 9,550,664

REDUCING MEMS STICTION BY INCREASING SURFACE ROUGHNESS

NXP USA, INC., Austin, T...

1. A method for manufacturing a microelectromechanical systems (MEMS) device, the method comprising:
forming an insulating layer over a substrate;
depositing a first polysilicon layer on the insulating layer by reacting a silicon-containing gas, gaseous hydrochloric acid,
and hydrogen for a first duration of time at a first temperature, wherein, during the deposition, the gaseous hydrochloric
acid is at least 15% of a total flow of the gaseous hydrochloric acid and the silicon-containing gas;

etching the first polysilicon layer using gaseous hydrochloric acid and hydrogen for a second duration of time at a second
temperature;

depositing a second polysilicon layer over the etched first polysilicon layer by reacting the silicon-containing gas and hydrogen
for a third duration of time at a third temperature; and

patterning the second polysilicon layer and the first polysilicon layer to form a travel stop region of the MEMS device.

US Pat. No. 9,529,745

SYSTEM ON CHIP AND METHOD OF OPERATING A SYSTEM ON CHIP

NXP USA, INC., Austin, T...

1. A system on chip, SoC, comprising two or more data sources, a memory unit, a memory control unit, and a processing unit,
wherein each of the data sources is capable of providing a data stream,
wherein the memory control unit is arranged to maintain, for each of the data streams, a buffer in the memory unit and to
route the respective data stream to the processing unit via the respective buffer,

wherein each of the thus maintained buffers has buffer characteristics which are variable and which comprise at least the
amount of free memory of the respective buffer and a data accumulation rate of the respective buffer,

wherein the memory control unit is arranged to allocate and de-allocate memory regions to and from each of said buffers in
dependence of the data accumulation rate of the respective buffer, thereby allowing for re-allocation of memory of the memory
unit among the buffers, and

wherein the buffer characteristics of each buffer include a hypothetical fill time T and wherein the memory control unit is
arranged to associate, with each of the buffers, an allocation threshold T_ALLOC and to allocate a memory region in the memory
unit to the respective buffer in response to detecting that the hypothetical fill time T is less than the allocation threshold
T_ALLOC.

US Pat. No. 9,601,985

SEGMENTED DRIVER FOR A TRANSISTOR DEVICE

NXP USA, Inc., Austin, T...

1. A segmented driver, comprising:
at least one drive pin and a sense pin;
a driver circuit that is configured to activate a selected drive level between said at least one drive pin and a reference
node;

a comparator that is configured to compare a voltage of said sense pin with a threshold voltage and to provide a threshold
indication when said voltage of said sense pin reaches said threshold voltage; and

a controller that is configured to command said driver circuit to activate a first drive level in response to an off indication,
and to command said driver circuit to switch from said first drive level to a second drive level that is lower than said first
drive level in response to said threshold indication.

US Pat. No. 9,542,238

SYSTEMS AND METHODS FOR DIRECT MEMORY ACCESS COHERENCY AMONG MULTIPLE PROCESSING CORES

NXP USA, Inc., Austin, T...

1. In a multi-core system configured to execute a plurality of tasks and having a semaphore engine and a direct memory access
(DMA) engine, a method comprises:
selecting, by a task scheduler of a first core, a first task for execution by the first core, wherein executing the first
task comprises allocating an entry in a workspace memory of the first core, and requesting a semaphore lock of a first semaphore
identified by a first semaphore identifier;

in response to the semaphore lock request, the task scheduler of the first core switching the first task to an inactive state
and selecting a next task for execution by the first core;

in response to the semaphore lock request, the semaphore engine, acquiring the semaphore lock of the first semaphore for the
first task;

in response to acquiring the semaphore lock of the first semaphore for the first task, the semaphore engine providing a data
transfer request to the DMA engine;

in response to the data transfer request, transferring, by the DMA engine, data associated with the locked first semaphore
to the entry of the workspace memory of the first core;

after the transferring the data, the task scheduler switching the first task from the inactive state to a ready for scheduling
state so that the first task can be selected for execution by the task scheduler;

when there is no other task waiting to acquire lock of the first semaphore, the DMA engine transferring modified data from
the entry of the workspace memory of the first core to external memory; and

when there is at least one other task waiting to acquire lock of the first semaphore, the method further comprises:
selecting, by the semaphore engine, a task of the at least one other task to acquire lock of the first semaphore; and
transferring, by the DMA engine, the modified data from the entry of the workspace memory of the first core to an entry of
a workspace allocated by the selected task of the at least one other task.

US Pat. No. 9,542,263

ELECTRONIC DEVICE HAVING A RUNTIME INTEGRITY CHECKER

NXP USA, INC., Austin, T...

1. Electronic device having a runtime integrity checker for monitoring contents of storage locations in an address range,
the runtime integrity checker comprising:
a location selector for selecting the storage locations by generating addresses within the address range for locations to
be checked,

an interface unit coupled to the location selector for receiving the addresses for accessing the locations to be checked via
a bus interface,

a processor coupled to the interface unit for retrieving the contents from the locations to be checked, and
a mask unit for processing a mask coupled to the location selector for defining the locations to be checked based on bits
in the mask, wherein the locations to be checked consists of data that is not expected to change during runtime of the electronic
device, and wherein locations that are not checked consists of data that is expected to change during runtime of the electronic
device.

US Pat. No. 9,541,521

ENHANCED SENSITIVITY ION SENSING DEVICES

NXP USA, Inc., Austin, T...

1. An ion sensitive semiconductor device comprising:
a substrate comprising a surface;
a semiconductor device layer, formed within the surface of the substrate, and comprising a conductivity modulated region,
a first doped region disposed laterally adjacent to the conductivity modulated region, and a second doped region disposed
laterally adjacent to the conductivity modulated region;

a gate stack formed on the surface of the substrate and over a first surface of the conductivity modulated region;
a buried dielectric layer formed within the substrate and adjacent to a second surface of the conductivity modulated region,
wherein the second surface is opposite to the first surface;

a conductive well region formed within the substrate beneath and adjacent to the buried dielectric layer, wherein the conductive
well region is electrically isolated from the remainder of the substrate;

multiple conductive structures overlying the surface of the substrate, wherein the multiple conductive structures comprise
a first conductor formed in first metal layer electrically coupled to the conductive well region by a first conductive via,
and

an ion-sensitive sense plate structure electrically coupled to the first conductor and configured to sense a concentration
of a target ion or molecule in a fluid adjacent to a portion of the ion-sensitive sense plate structure.

US Pat. No. 9,543,379

SEMICONDUCTOR DEVICE WITH PERIPHERAL BREAKDOWN PROTECTION

NXP USA, Inc., Austin, T...

1. A device comprising:
a semiconductor substrate;
source and drain regions disposed in the semiconductor substrate and having a first conductivity type;
a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is
disposed;

a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers
drift during operation upon application of a bias voltage between the source and drain regions;

a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift
region; and

a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity
type;

wherein the breakdown protection region comprises an electrically floating well disposed between the device isolation region
and the body region;

wherein the breakdown protection region has a width at a surface of the semiconductor substrate in a lateral direction that
establishes a spacing between the body region and the device isolation region, the width falling in a range from 1.0 microns
to 2.0 microns so that the breakdown protection region improves a breakdown voltage level of the device by preventing charge
inversion from occurring in the body region along the device isolation region; and

wherein the first conductivity type is p-type and the second conductivity type is n-type.

US Pat. No. 9,756,592

ANTENNA DELAY BUFFERING IN TELECOMMUNICATION RECEIVERS

NXP USA, INC., Austin, T...

1. A telecommunication receiver for receiving, from multiple antennas, related data having different delays, the receiver
comprising:
an input buffer for buffering the data for each antenna separately as buffered input data, wherein the input buffer is arranged
for buffering per antenna the amount of data which corresponds with twice an amount of data that can be submitted to a Fourier
transform unit for selecting relevant data,

the Fourier transform unit for selecting, from the buffered input data, relevant input data and Fourier transforming the relevant
input data into transformed data for each antenna separately as soon as the relevant input data are available, and

an output buffer for buffering the transformed data for each antenna separately as buffered output data until a predetermined
amount of transformed data from all antennas is buffered.

US Pat. No. 9,552,890

ANTIFUSE WITH BYPASS DIODE AND METHOD THEREOF

NXP USA, Inc., Austin, T...

1. A semiconductor device comprising:
an antifuse having a first node and a second node;
a first diode having a first diode anode and a first diode cathode, the first diode cathode coupled to the first node of the
antifuse, and the first diode anode coupled to the second node of the antifuse such that the first diode and the antifuse
are in a parallel combination; and

a second diode coupled in series with the parallel combination, where the second diode is coupled oppositely biased compared
to the first diode, and where the first diode has a first area, and the second diode has a second area, and wherein the second
area is at least twice as large as the first area.

US Pat. No. 9,543,420

PROTECTION DEVICE AND RELATED FABRICATION METHODS

NXP USA, Inc., Austin, T...

1. A semiconductor device comprising:
a first region of semiconductor material having a first conductivity type and a first dopant concentration;
a base well region within the first region, the base well region having the first conductivity type and a second dopant concentration
greater than the first dopant concentration of the first region;

a base contact region within the base well region, the base contact region having the first conductivity type and a third
dopant concentration greater than the first dopant concentration;

an emitter region of semiconductor material within the base well region, the emitter region having a second conductivity type
opposite the first conductivity type; and

a collector region of semiconductor material having the second conductivity type, wherein:
at least a portion of the first region resides between the emitter region and the collector region;
a depth of the collector region is greater than a depth of the emitter region;
a depth of a second portion of the first region underlying the emitter region is greater than or equal to the depth of the
collector region;

at least a portion of the base well region resides between the emitter region and the collector region; and
the depth of the collector region is greater than a depth of the base well region.

US Pat. No. 9,588,531

VOLTAGE REGULATOR WITH EXTENDED MINIMUM TO MAXIMUM LOAD CURRENT RATIO

NXP USA, Inc., Austin, T...

1. A low-dropout (LDO) voltage regulator disposed within a semiconductor package, the LDO voltage regulator comprising:
an inner loop; and
an outer loop coupled to the inner loop, wherein:
the inner loop is configured to control a load response of the LDO voltage regulator and to reduce at least one of: a printed
circuit board (PCB) effect on the outer loop, a packaging effect on the outer loop, or a parasitic effect on the outer loop,
wherein the inner loop comprises an operational transconductance amplifier (OTA) circuit having a load current dependent DC
gain, and wherein the OTA circuit comprises:

an OTA;
a tracking pole diode coupled to the OTA, wherein the tracking pole diode is configured to compensate gain variations due
to load changes at the output of the OTA circuit; and

a filter array coupled in parallel with the tracking pole diode, wherein the filter array is configured to maintain a consistent
frequency response under influence of the at least one of the PCB, packaging, or parasitic effect, and wherein the tracking
pole diode has: (a) its source terminal coupled to a first terminal of the filter array, and (b) its gate terminal coupled
to its drain terminal and to a second terminal of the filter array;

the outer loop is configured to control a voltage at an output of the LDO voltage regulator;
the output of the LDO voltage regulator is coupled to an integrated circuit within the semiconductor package; and
the PCB, package, and parasitic effects comprise inductive or resistive effects caused by elements disposed outside of the
semiconductor package.

US Pat. No. 9,575,758

METHOD FOR SETTING BREAKPOINTS, AND AN INTEGRATED CIRCUIT AND DEBUG TOOL THEREFOR

NXP USA, INC., Austin, T...

1. A method for setting one or more breakpoints within executable program code of an embedded device, the method comprising:
copying at least one area of non-volatile memory (NVM) of the embedded device, comprising at least one instruction at which
a breakpoint is to be set, into at least one area of overlay memory to be memory-mapped by mapping hardware of the embedded
device to cover the at least one area of NVM;

replacing within the at least one area of overlay memory the at least one instruction at which a breakpoint is to be set with
a breakpoint operation code to be executed by at least one processor core of the embedded device; and

enabling the mapping hardware of the embedded device to map the at least one area of NVM, comprising the at least one instruction
at which a breakpoint is to be set, to the at least one area of overlay memory during execution of the program code within
the embedded device by the at least one processor core.

US Pat. No. 9,553,187

SEMICONDUCTOR DEVICE AND RELATED FABRICATION METHODS

NXP USA, Inc., Austin, T...

1. A semiconductor device structure comprising:
a body well region of semiconductor material having a first conductivity type;
a drift region of semiconductor material having a second conductivity type;
a source region of semiconductor material having the second conductivity type, a channel portion of the body well region residing
laterally between the source region and a first portion of the drift region, the first portion being adjacent to the channel
portion; and

a gate structure overlying at least the channel portion of the body well region and the first portion of the drift region,
wherein

a second portion of the gate structure overlying the channel portion proximate the source region has the second conductivity
type,

a throttling portion of the gate structure overlies the first portion of the drift region and at least a portion of the channel
portion,

a doping of the throttling portion is different from the second portion of the gate structure, and
a width of an area of the throttling portion that overlaps the channel portion is less than a width of the gate structure.

US Pat. No. 9,563,494

SYSTEMS AND METHODS FOR MANAGING TASK WATCHDOG STATUS REGISTER ENTRIES

NXP USA, Inc., Austin, T...

1. A data processing system comprising:
one or more processors each configured to execute a plurality of tasks;
one or more watchdog status registers each comprising a plurality of bits, wherein
each watchdog status register is associated with one of the one or more processors, and
each bit of the plurality of bits of one watchdog status register is associated with one task of the plurality of tasks of
one processor that is associated with the one watchdog status register;

a centralized watchdog task configured to
determine whether every bit of the plurality of bits of a respective watchdog status register stores a first state value,
and

write a trigger data pattern to the respective watchdog status register, in response to a determination that every bit of
the plurality of bits of the respective watchdog status register stores the first state value, wherein

the trigger data pattern comprises the first state value for each of the plurality of bits of the respective watchdog status
register; and

one or more hardware logic circuits each associated with a particular processor that is associated with a particular watchdog
status register, each hardware logic circuit configured to

identify a set of active tasks of the particular processor that are presently in an active task state, in response to a detection
that the trigger data pattern is written to the particular watchdog status register.

US Pat. No. 9,553,371

RADAR MODULE

NXP USA, INC., Austin, T...

1. A device comprising:
a radar module comprising a connector to interface with an external receptacle, the radar module to receive a millimeter radio
frequency (RF) signal that includes a desired frequency range reflected from an object, the radar module including:

a printed circuit board (PCB) having a first major surface and a second major surface, the first major surface overlying and
coplanar to the second major surface;

a parabolic structure comprising a reflective surface to reflect the received millimeter RF signal;
an electromagnetic (EM) absorber between the PCB and the reflective surface, the EM absorber including an opening aligned
with an antenna structure, the EM absorber being a graded absorber to absorb a frequency range of the received millimeter
RF signal received from undesirable directions.

US Pat. No. 9,572,199

MULTIMODE RAKE RECEIVER, CELLULAR BASE STATION AND CELLULAR COMMUNICATION DEVICE

NXP USA, INC., Austin, T...

1. A multimode rake receiver, comprising
a common antenna interface, arranged to at least receive in a first mode a first CDMA radio channel carrying information encoded
according to a first baseband modulation standard and to receive in a second mode a second CDMA radio channel carrying information
encoded according to a second baseband modulation standard;

a common signal processing path, at least arranged to process in said first mode said first CDMA radio channel and in said
second mode said second CDMA radio channel, wherein said common signal path comprises:

a common descrambling and de-spreading unit; and
a common hybrid code generating unit arranged to provide to said common descrambling and de-spreading unit chip codes applicable
in said first mode to said first CDMA radio channel and in said second mode to said second CDMA radio channel; and

a control unit to communicate with the common descrambling and de-spreading unit, and with the common hybrid code generating
unit, the control unit to provide a first control signal to the common descrambling and de-spreading unit and to the common
hybrid code generating unit, the first control signal to cause the common descrambling and de-spreading unit and the common
hybrid code generating unit to be in the first mode, and to provide a second control signal to the common descrambling and
de-spreading unit and to the common hybrid code generating unit, the second control signal to cause the common descrambling
and de-spreading unit and the common hybrid code generating unit to be in the second mode, the common descrambling and de-spreading
unit to operate in only one of the first mode or the second mode at any given point of time depending on whether the first
control signal or the second control signal is received.

US Pat. No. 9,559,077

DIE ATTACHMENT FOR PACKAGED SEMICONDUCTOR DEVICE

NXP USA, Inc., Austin, T...

1. A method for forming a packaged semiconductor device, comprising:
attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate, wherein
no bond pads are located on the first major surface, wherein a top surface of each protrusion has a die attach material, wherein
the die attach material directly contacts the first major surface and the top surface of each protrusion, and wherein the
attaching results in a space under exposed portions of the first major surface of the semiconductor die between the plurality
of protrusions;

forming interconnects between bond pads located on a second major surface of the semiconductor die and the package substrate
subsequent to the attaching, wherein the second major surface is opposite the first major surface;

filling the space with underfill material subsequent to the forming the interconnects; and
forming an encapsulant material over the semiconductor die and the interconnects subsequent to the filling the space.

US Pat. No. 9,606,567

METHOD AND APPARATUS FOR PROVIDING ELECTRICAL ISOLATION

NXP USA, Inc., Austin, T...

1. A high voltage device, the high voltage device comprising:
a high-voltage transistor having a first current terminal to be coupled to a high-voltage supply, a second current terminal
to be coupled to a high voltage load, and a control terminal;

a driver module coupled to the control terminal of the high voltage transistor device;
an isolation circuit configured to provide electrical isolation to the driver module from a received control signal having
a control voltage, the isolation circuit comprising:

a boost circuit, wherein the boost circuit is configured to receive the control signal at a control input and output a boosted
control signal having a boosted control signal voltage, wherein the boosted control signal voltage is at least five times
the control signal voltage;

a first capacitive isolation component formed in a printed circuit board with multiple layers, wherein the first capacitive
isolation component comprises:

a first shielding dielectric layer;
a first conductive element layer having a first electrically conductive element;
an intermediate dielectric layer;
a second conductive element layer having a second electrically conductive element;
a second shielding dielectric layer
wherein
the first electrically conductive element and the second electrically conductive element are electrically isolated with respect
to one another by the intermediate dielectric layer and positioned relative to each other to provide a capacitive coupling
between the first electrically conductive element and the second electrically conductive element,

the first conductive element layer abuts the first shielding dielectric layer, and the second shielding dielectric layer abuts
the second conductive element layer;

the first electrically conductive element of the first capacitive isolation component is coupled to the boost circuit to receive
the boosted control signal from the boost circuit,

the second electrically conductive element of the first capacitive isolation component is operably coupled to a first input
of the driver module to provide the boosted control signal to the driver module over the capacitive coupling, and

the driver module drives the control terminal of the high voltage transistor device according to the boosted control signal
to drive the high voltage transistor device to provide a high voltage to the high voltage load, the high voltage an order
of magnitude greater than the boosted control signal voltage.

US Pat. No. 9,621,115

AMPLIFIER DEVICES WITH IN-PACKAGE TRANSMISSION LINE COMBINER

NXP USA, INC., Austin, T...

1. An amplifier comprising:
a device package including an output lead and at least one input lead, the device package encasing:
a first amplifier with a first transistor including a first transistor output;
a second amplifier with a second transistor including a second transistor output; and
a combiner coupled to the first transistor output and the second transistor output, the combiner including a transmission
line having a length configured to provide at least a portion of an impedance inverter between the first transistor output
and the second transistor output, wherein the impedance inverter is configured to compensate for a first transistor parasitic
capacitance and a second transistor parasitic capacitance, and wherein the impedance inverter further includes a first set
of bond wires and a second set of bond wires.

US Pat. No. 9,601,354

SEMICONDUCTOR MANUFACTURING FOR FORMING BOND PADS AND SEAL RINGS

NXP USA, Inc., Austin, T...

1. A method for making integrated circuits using a semiconductor substrate, the method comprising:
etching a first pad opening to a first depth into a plurality of build-up layers including interlayer dielectric layers and
metal layers that are over the semiconductor substrate;

depositing a conductive layer over the plurality of build-up layers, including over the first pad opening and along sidewalls
of the first pad opening; and

etching the conductive layer to leave a remaining portion of the conductive layer over the first pad opening, along the sidewalls
of the first pad opening, and extending over a portion of a top surface of the plurality of build-up layers to form a first
bond pad within the first pad opening;

wherein the first depth is located at a transition layer of the plurality of build-up layers and the transition layer comprises
an isolation dielectric layer, an interconnect structure is exposed in a first sidewall of the first pad opening, and the
conductive layer is conformal deposited over the first pad opening, including over the isolation dielectric layer within the
first pad opening and along the sidewalls of the first pad opening, to form a connection with the interconnect structure.

US Pat. No. 9,628,027

MULTI-PATH DEVICES WITH MUTUAL INDUCTANCE COMPENSATION NETWORKS AND METHODS THEREOF

NXP USA, INC., Austin, T...

1. An apparatus comprising:
a first output lead;
a second output lead;
a multi-path device, the multi-path device having a first amplifier with a first output, and a second amplifier with a second
output;

a first set of multiple parallel bonding wires coupling the first output of the first amplifier with the first output lead;
a second set of multiple parallel bonding wires coupling the second output of the second amplifier with the second output
lead, wherein the second set of bonding wires has a first mutual inductance with the first set of bonding wires;

a first compensation network coupled in series with the first set of multiple parallel bonding wires between the first output
and the first output lead; and

a second compensation network coupled in series with the second set of multiple parallel bonding wires between the second
output and the second output lead, the second compensation network configured to have a second mutual inductance with the
first compensation network, the second mutual inductance configured to at least partially cancel effects of the first mutual
inductance.

US Pat. No. 9,620,854

ELECTRONIC HIGH FREQUENCY DEVICE AND MANUFACTURING METHOD

NXP USA, Inc., Austin, T...

1. An electronic device comprising:
a wiring board having one or more layers;
an integrated circuit arranged on the wiring board;
an antenna;
and a signal path,
wherein the integrated circuit is arranged to generate a high frequency signal and to feed it to the signal path, the signal
path is arranged to convey the high frequency signal to the antenna and the antenna is arranged to emit the high frequency
signal into an environment of the electronic device;

wherein the signal path comprises a wave guide that traverses one or more of said layers, and wherein the waveguide has at
least one of: a longitudinal axis which is perpendicular to said layers or a cylindrical inner space.

US Pat. No. 9,609,693

HEATING SYSTEM AND METHOD OF TESTING A SEMICONDUCTOR DEVICE USING A HEATING SYSTEM

NXP USA, Inc., Austin, T...

1. A method comprising:
providing a semiconductor device;
providing a heating system configured to generate heat and bring heat to the semiconductor device, wherein the heating system
includes a thermal contact area and a conductive heating unit, the conductive heating unit having a first heating resistor;

placing the semiconductor device in thermal contact with the thermal contact area of the conduction heating unit as a semiconductor
device under test;

placing the semiconductor device under test into a convection heating chamber;
operating the first heating resistor of the conduction heating unit to provide a part of the heat generated by the first heating
resistor to the semiconductor device under test via a thermally conductive and electrically insulating connection between
the first heating resistor and the thermal contact area;

operating the convection heating chamber to provide a user-defined heat-controlled convection to the semiconductor device
under test while the semiconductor device under test is in thermal contact with the conduction heating unit and the first
heating resistor of the conduction heating unit is operated to provide the part of the heat generated by the first heating
resistor to the semiconductor device under test via the thermally conductive and electrically insulating connection between
the first heating resistor and the thermal contact; and

operating the semiconductor device under test with electrical operating conditions to conduct a performance test while operating
the first heating resistor of the conduction heating unit to provide the part of the heat.

US Pat. No. 9,595,954

METHOD AND CIRCUIT FOR RECHARGING A BOOTSTRAP CAPACITOR USING A TRANSFER CAPACITOR

NXP USA, INC., Austin, T...

1. A circuit comprising:
a high side driver for driving a high side transistor to couple a load output to a supply voltage;
a bootstrap capacitor coupled to a bootstrap input of the high side driver;
a transfer capacitor coupled to the bootstrap capacitor to charge the bootstrap capacitor, the transfer capacitor having a
first transfer capacitor terminal and a second transfer capacitor terminal, the second transfer capacitor terminal directly
connected to a low side power input of a low side driver;

a first resistor coupled to the first transfer capacitor terminal, the transfer capacitor configured to be charged from a
voltage source through the first resistor, wherein the first resistor is configured to effectively decoupled the transfer
capacitor from the voltage source during a voltage transient event; and

a second resistor through which the transfer capacitor is configured to charge the boot capacitor.

US Pat. No. 9,606,879

MULTI-PARTITION NETWORKING DEVICE AND METHOD THEREFOR

NXP USA, INC., Austin, T...

1. A multi-partition networking device comprising at least one primary partition running on a first set of hardware resources
and at least one secondary partition running on at least one further set of hardware resources; wherein the multi-partition
networking device is arranged to:
operate in a first operating state, whereby the first set of hardware resources are in an active state and the primary partition
is arranged to process network traffic and the at least one further set of hardware resources are in a standby state;

transition to a second operating state upon detection of a suspicious condition within the primary partition, whereby the
at least one further set of hardware resources are transitioned from a standby state to an active state;

transition to a third operating state upon detection of a failure condition within the primary partition, whereby processing
of network traffic is transferred to the secondary partition; and

the multi-partition networking device further comprising;
a management module, the management module arranged to detect the occurrence of at least one suspicious condition within the
primary partition, and to cause the multi-partition networking device to transition to the second operating state upon detection
of the at least one suspicious condition within the primary partition; and

a network sub-module arranged to:
detect when an occupancy level for at least one buffer pool for received network traffic exceeds a threshold; and
output to the management module a buffer pool threshold exceeded indication, upon detection of an occupancy level for the
at least one buffer pool exceeding the threshold.

US Pat. No. 9,599,587

METHODS AND APPARATUS FOR AN ISFET

NXP USA, INC., Austin, T...

1. A method of forming a CMOS ISFET, comprising:
providing a substrate;
forming a floating gate structure over the substrate, wherein the floating gate structure includes a metal plate configured
to sense an ion concentration of a fluid adjacent to the metal plate; and

forming a control gate structure communicatively coupled to the floating gate structure, such that the control gate structure
is configured to receive a bias voltage and effect transfer of charge selectively between the floating gate structure and
the control gate structure;

wherein the at least one control gate structure includes a control gate electrode coupled to the substrate via a conductive
interconnect, and a capacitor structure formed by the substrate, the floating gate structure, and an oxide layer provided
therebetween.

US Pat. No. 9,589,928

COMBINED QFN AND QFP SEMICONDUCTOR PACKAGE

NXP USA, INC., Austin, T...

1. A semiconductor package, comprising:
a die pad having an upper surface and a lower surface;
an integrated circuit attached on the upper surface of the die pad;
a plurality of first package type leads surrounding the die pad, wherein each of the plurality of first package type leads
is electrically connected to the integrated circuit with first bond wires;

a plurality of second package type leads that surround the first package type leads, wherein the second package type leads
have proximal ends that are positioned above the plurality of first package type leads, wherein the proximal ends of the second
package type leads are electrically connected to the integrated circuit with second bond wires, and wherein the second package
type leads are of a different lead type than the first package type leads; and

a mold cap that at least partially covers the die pad, the integrated circuit, the plurality of first and second package type
leads, and the first and second bond wires;

a pre-molded portion for positioning the first package type leads and supporting the second package type leads over the first
package type leads, wherein the pre-molded portion includes a structure located between leads of the plurality of first package
type leads and leads of the plurality of second package type leads in a direction orthogonal to the upper surface of the die
pad, wherein the structure is formed separately from the mold cap.

US Pat. No. 9,569,641

DATA PROCESSING SYSTEM WITH TEMPERATURE MONITORING FOR SECURITY

NXP USA, INC., Austin, T...

1. A processing system comprising:
a processor; and
a temperature security module coupled to provide a temperature tamper signal to the processor, wherein the temperature security
module includes:

a shelf mode trim value;
an operating mode trim value; and
a programmable temperature trim value,
wherein one of a group consisting of: the programmable temperature trim value, the shelf mode trim value, and the operating
mode trim value, is used based on a deployment mode of the processing system to set a temperature monitor trim value, wherein
the temperature security module is configured to use one of the programmable trim value or the shelf mode trim value to set
the temperature monitor trim value during a first deployment mode in which a battery power supply is provided to the temperature
security module, operating power is not provided to the processing system, and a shelf mode indicator indicates shelf mode,

wherein the temperature security module further includes
a temperature monitor configured to provide the temperature tamper signal when a detected temperature of the processing system
is not within a temperature range indicated by the selected one of the programmable temperature trim value, the shelf mode
trim value, and the operating mode trim value.

US Pat. No. 9,614,074

PARTIAL, SELF-BIASED ISOLATION IN SEMICONDUCTOR DEVICES

NXP USA, INC., Austin, T...

1. A device comprising:
a semiconductor substrate;
a buried doped isolation layer disposed in the semiconductor substrate to isolate the device;
a body region disposed in the semiconductor substrate and to which a voltage is applied during operation and in which a channel
is formed during operation; and

a depletion region disposed in the semiconductor substrate and having a conductivity type in common with the buried doped
isolation layer and the body region, the depletion region reaching a depth in the semiconductor substrate to be in contact
with the buried doped isolation layer;

wherein the depletion region establishes an electrical link between the buried doped isolation layer and the body region such
that the buried doped isolation layer is biased at a voltage level lower than the voltage applied to the body region.

US Pat. No. 9,590,097

SEMICONDUCTOR DEVICES AND RELATED FABRICATION METHODS

NXP USA, INC., Austin, T...

1. A method of fabricating a semiconductor device on a semiconductor substrate, the method comprising:
forming a body region of semiconductor material having a first conductivity type within the semiconductor substrate;
forming a junction isolation region of semiconductor material having a second conductivity type opposite the first conductivity
type within the semiconductor substrate, the junction isolation region residing laterally between the body region and a second
region of semiconductor material having the first conductivity type;

forming a first drift region of semiconductor material having the second conductivity type within the second region;
forming a source region of semiconductor material having the second conductivity type within the body region; and
forming a drain region of semiconductor material having the second conductivity type within the second region, wherein the
first drift region resides laterally between the drain region and the junction isolation region to provide a conductive path
between the drain region and the junction isolation region.

US Pat. No. 9,584,104

SEMICONDUCTOR DEVICE AND METHOD OF OPERATING A SEMICONDUCTOR DEVICE

NXP USA, Inc., Austin, T...

1. A semiconductor device, comprising a substrate and an electronic circuit formed at least partly on or in the substrate;
wherein
the electronic circuit comprises a first voltage provider node, a second voltage provider node, and an intermediary node,
wherein the intermediary node is connected to the first voltage provider node by a first network having a first resistance
and to the second voltage provider node by a second network having a second resistance, the resistance between the intermediary
node and the first voltage provider node being the first resistance and the resistance between the intermediary node and the
second voltage provider node being the second resistance;

the substrate is susceptible to conducting a substrate current, which is a variable spurious electrical current and the semiconductor
device further comprises a substrate current sensor connected to the substrate and arranged to sense the substrate current;

the first network is arranged to reduce the first resistance in response to the substrate current sensor signaling an increase
of the substrate current and to increase the first resistance in response to the substrate current sensor signaling a decrease
of the substrate; and

the second network is arranged to reduce the second resistance in response to the substrate current sensor signaling an increase
of the substrate current and to increase the second resistance in response to the substrate current sensor signaling a decrease
of the substrate.

US Pat. No. 9,588,808

MULTI-CORE SYSTEM PERFORMING PACKET PROCESSING WITH CONTEXT SWITCHING

NXP USA, INC., Austin, T...

1. A method comprising:
processing packet data in form of tasks in a multi-core system;
executing a context switch instruction for a first task in a first processing core;
accessing first context information for the first task in the first processing core by a task manager externally coupled to
the first processing core in response to the execution of the context switch instruction;

providing the first context information from the task manager to a context storage buffer in a second processing core during
execution of a second task in the second processing core;

storing the first context information in a next register of the second processing core from the context storage buffer of
the second processing core during execution of the second task in the second processing core, wherein the next register stores
context information of a next task to be executed in the second processing core;

migrating, by the task manager, execution of the first task from the first processing core to the second processing core during
execution of the second task in the second processing core;

transferring second context information of the second task from a current register of the second processing core to a previous
register of the second processing core during a context switch from the second task to the first task in the second processing
core; and

transferring the first context information for the first task from the next register to the current register during the context
switch from the second task to the first task in the second processing core.

US Pat. No. 9,826,630

FAN-OUT WAFER LEVEL PACKAGES HAVING PREFORMED EMBEDDED GROUND PLANE CONNECTIONS AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A method for fabricating Fan-Out Wafer Level Packages (FO-WLPs), comprising:
bonding a plurality of preformed connections to a ground plane array, the ground plane array comprising a plurality of ground
plane structures interconnected by a plurality of spars;

after bonding the plurality of preformed connections to the ground plane array, placing the plurality of preformed connections
and the ground plane array on a temporary substrate;

after placing the plurality of preformed connections and the ground plane array on the temporary substrate, forming a molded
panel over the temporary substrate and around the ground plane array and the plurality of preformed connections to yield an
Embedded Ground Plane (EGP) array and a plurality of preformed EGP connections, respectively;

after forming the molded panel, removing material from a backside of the molded panel to thin the molded panel and expose
the plurality of preformed EGP connections;

after removing material from the backside of the molded panel, removing the temporary substrate to expose a frontside of the
molded panel;

after removing the temporary substrate, producing one or more Redistribution Layers (RDLs) over the frontside of the molded
panel; and

after producing the one or more RDLs over the frontside of the molded panel, singulating the molded panel and severing the
ground plane array through the plurality of spars to yield a plurality of FO-WLPs, each of the plurality of FO-WLPs including
a molded package body containing a singulated EGP separated from the EGP array and one or more of the preformed EGP connections.

US Pat. No. 9,742,469

POSITIONING GUIDANCE FOR INCREASING RELIABILITY OF NEAR-FIELD COMMUNICATIONS

NXP USA, INC., Austin, T...

1. A method of operating a near field communication (NFC)-enabled device, comprising:
transmitting from a plurality of antennas of a first NFC-enabled device, a plurality of commands;
receiving, at the plurality of antennas, a plurality of responses to the corresponding plurality of commands;
measuring a response delay time of the responses received at the plurality of antennas;
recording the response delay time such that the response delay time is associated with the antenna of the plurality of antennas
from which the respective command was transmitted; and

determining the distance of the plurality of antennas from the source of the response based on the response delay time associated
with the plurality of antennas;

wherein the response delay time is the amount of time between the command sent and the reception of a first response edge.

US Pat. No. 10,045,366

SCHEDULER FOR LAYER MAPPED CODE WORDS

NXP USA, INC., Austin, T...

9. A radio base station that manages first and second radio cells including first and second user devices, respectively, wherein the radio base station schedules first and second code words corresponding to the first and second user devices, respectively, wherein the first code word includes a first identifier and a first code word number and the second code word includes a second identifier and a second code word number, the radio base station comprising:a command processor that receives first and second code block commands of the first and second code words, respectively, and outputs the first and second identifiers;
a layer mapper that receives a plurality of code block commands and a plurality of control commands of the first code word, and a plurality code block commands and a plurality control commands of the second code word, and outputs the first and second code word numbers, wherein the layer mapper outputs the first code word number when a plurality of code block commands and a plurality of control commands of the first code word are received, processed, and stored in a mapped data storage, and outputs the second code word number when a plurality of code block commands and a plurality of control commands of the second code word are received, processed, and stored in the mapped data storage;
a header memory that receives and stores a header of the first code word and a header of the second code word, wherein the header of the first code word includes the first code word number and the first identifier, and the header of the second code word includes the second code word number and the second identifier; and
a scheduler connected to the command processor, the layer mapper, and the header memory, for scheduling the first and second code words, wherein the scheduler includes:
a buffer memory that receives and stores the first and second identifiers from the command processor;
a de-multiplexer that receives the first and second code word numbers from the layer mapper, and the first and second identifiers from the header memory, and outputs the first code word number based on the first identifier and the second code word number based on the second identifier;
a set of completion queues including first and second completion queues corresponding to the first and second identifiers, respectively, connected to the de-multiplexer for receiving and storing the first and second code word numbers, wherein the first completion queue stores the first code word number, and the second completion queue stores the second code word number;
a sequence controller connected to the buffer memory for receiving the first and second identifiers, wherein the sequence controller generates first and second select signals corresponding to the first and second identifiers, respectively; and
a multiplexer connected to the sequence controller for receiving the first and second select signals, and to the set of completion queues for receiving the first and second code word numbers, wherein the multiplexer outputs one of the first and second code word numbers based on the first and second select signals, and wherein the scheduler schedules the first and second code words based on the one of the first and second identifiers.

US Pat. No. 9,614,369

ESD PROTECTION DEVICE

NXP USA, Inc., Austin, T...

1. A device comprising an electrostatic discharge protection clamp having an anode and a cathode each of which are adapted
to limit a voltage appearing across protected terminals of an integrated circuit to which the electrostatic discharge protection
clamp is coupled, comprising:
an active semiconductor region overlying a substrate comprising
a first P-well,
a second P-well,
a third P-well,
a first N-well between the second and third P-wells and between the first and third P-wells,
a second N-well between the first and second P-wells,
a first P-type contact region at the first P-well electrically connected to an anode/cathode terminal of the electrostatic
discharge protection clamp,

a first N-type contact region at the first P-well electrically connected to the anode/cathode terminal,
a second P-type contact region at the third P-well electrically connected to a cathode/anode of the electrostatic discharge
protection clamp,

a second N-type contact region at the third P-well electrically connected to the cathode/anode and between the first N-well
and the second P-type contact.

US Pat. No. 9,612,881

METHOD, APPARATUS, AND SYSTEM FOR UNAMBIGUOUS PARAMETER SAMPLING IN A HETEROGENEOUS MULTI-CORE OR MULTI-THREADED PROCESSOR ENVIRONMENT

NXP USA, Inc., Austin, T...

1. A method comprising:
masking one or more thread requests;
executing at least one of a command routine or a command thread for a command in response to both ascertaining that a ceasing
of all bus activity for the one or more masked thread requests has occurred, and additionally ascertaining that a completion
of all routines being processed for the one or more masked thread requests has occurred, wherein

the command routine or the command thread reads a plurality of parameters using thread atomicity with deterministic synchronization,
and

the plurality of parameters comprises one or more of a counter and a state indicator.

US Pat. No. 9,583,665

PIN DIODE WITH NANOCLUSTERS

NXP USA, Inc., Austin, T...

1. A diode for detecting the presence of radiation comprising:
a P region;
an N region;
an intrinsic region located between the P region and the N region;
a layer of nanoclusters located adjacent to the intrinsic region, wherein the nanoclusters are doped with a material that
generates alpha particles upon interactions with neutrons.

US Pat. No. 9,589,637

STORAGE ELEMENT WITH STORAGE AND CLOCK TREE MONITORING CIRCUIT AND METHODS THEREFOR

NXP USA, Inc., Austin, T...

1. A storage element with monitoring circuit, comprising:
a data input interface providing data;
a data output interface;
a clock signal input interface providing a clock;
a storage fault indicator interface;
a monitored state information storage element having a clock input terminal coupled to the clock signal input interface, a
data input terminal coupled to the data input interface and a data output terminal;

a previous state information storage element having a clock input terminal coupled to the clock signal input interface, and
a data input terminal coupled to the data output terminal of the monitored state information storage element, the previous
state information storage element being configured to record the previous state of the monitored state information storage
element;

a state change indication unit having a clock input terminal coupled to the clock signal input interface, the state change
indication unit being configured to generate a state change indicator indicative of whether the monitored state information
storage element shall have performed a state change by observing the data at the data input interface and the data at the
output terminal of the monitored state information storage element; and

a state change confirmation unit coupled to the state change indication unit, the state change confirmation unit being configured
to generate a storage fault indicator by observing the data at the output terminal of the monitored state information storage
element and the data at the output of the previous state information storage element and checking whether the result of this
observation is in line with the state change indicator.

US Pat. No. 9,589,909

RADIO FREQUENCY AND ELECTROMAGNETIC INTERFERENCE SHIELDING IN WAFER LEVEL PACKAGING USING REDISTRIBUTION LAYERS

NXP USA, INC., Austin, T...

1. A semiconductor device package having interconnect layers, the semiconductor device package comprising:
a semiconductor device die comprising one or more bond pads on an active face of the semiconductor device die;
a first set of conductors formed in the interconnect layers, and coupled to an input/output bond pad that is a member of the
one or more bond pads, wherein the first set of conductors is configured to transport a signal on a path to or from an end
point of the first set of conductors to or from the input/output bond pad;

a second set of conductors formed in the interconnect layers, and coupled to a ground voltage, wherein
the second set of conductors is configured to electromagnetically isolate the first set of conductors along the path, and
the semiconductor device package is a fan-out wafer level package.

US Pat. No. 9,614,046

SEMICONDUCTOR DEVICES WITH A THERMALLY CONDUCTIVE LAYER

NXP USA, INC., Austin, T...

1. A semiconductor device comprising:
a semiconductor substrate that includes a host substrate, a channel, an upper surface, and a lower surface;
an active area proximate the upper surface of the semiconductor substrate;
a substrate opening in the semiconductor substrate wherein a bottom of the substrate opening is defined by a recessed surface
of the semiconductor substrate;

a thermally conductive layer disposed over the semiconductor substrate and over the channel that contacts the recessed surface
of the semiconductor substrate and extends between the recessed surface of the semiconductor substrate and a portion of the
semiconductor substrate within the active area, the thermally conductive layer comprising a substantially electrically insulating
layer within the active area;

a through wafer via within the semiconductor substrate that includes a sidewall that extends from the lower surface of the
semiconductor substrate to the recessed surface; and

a high thermal conductivity backside layer in contact with the sidewall of the through wafer via.

US Pat. No. 9,590,506

MULTIPLE MODE POWER REGULATOR

NXP USA, Inc., Austin, T...

1. A power regulator having a first operational mode and a second operational mode, the power regulator comprising:
an output terminal configured to provide a regulated voltage;
a first control unit configured to control the power regulator in the first operational mode;
a second control unit configured to control the power regulator in the second operational mode; and
a detection unit connected to the output terminal, the detection unit configured to detect, at start-up, whether or not an
external inductor is connected to the output terminal, wherein the detection unit is further connected to the first control
unit to activate the first operation mode when an external inductor is detected, and to the second control unit to activate
the second operation mode when no external inductor is detected, wherein

the detection unit is further configured to detect in which of first and second distinct inductance ranges an inductance of
the detected inductor lies so as to provide inductance dependent control in the first operation mode.

US Pat. No. 9,986,646

PACKAGED ELECTRONIC DEVICES WITH TOP TERMINATIONS, AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A device comprising:a substrate having a substrate top surface;
a transistor of an amplifier circuit, the transistor coupled to the substrate top surface and having a transistor top surface, wherein the transistor includes a first die pad exposed at the transistor top surface;
an encapsulation having an encapsulation top surface over at least a portion of the substrate top surface and the transistor top surface, wherein the encapsulation includes an opening extending from the encapsulation top surface to the first die pad of the transistor;
a first conductive termination structure within the opening in the encapsulation, wherein the first conductive termination structure is a solid conductive structure that is directly physically coupled to the first die pad, the first conductive termination structure extends from the first die pad to the encapsulation top surface, and an entirety of the first conductive structure from the first die pad to the encapsulation top surface is formed from a bulk conductive material; and
a second circuit that forms a portion of the amplifier circuit, wherein the second circuit is physically coupled to the encapsulation top surface and electrically coupled to the transistor through the first conductive termination structure.

US Pat. No. 9,731,697

HOMOGENEITY DETECTION CIRCUIT, A VALVE DRIVING SYSTEM AND A METHOD OF HOMOGENEITY DETECTION IN A VALVE DRIVING SYSTEM

NXP USA, Inc., Austin, T...

1. A homogeneity detection circuit for detecting an incorrect operation of components of a valve driving system, the homogeneity
detection circuit comprising:
a first input for receiving a first signal being related to a voltage or a current of a first driving signal for driving a
first valve;

a second input for receiving a second signal being related to a voltage or a current of a second driving signal for driving
a second valve;

a comparison circuit for comparing the first signal with the second signal and for generating a warning signal if predetermined
differences are detected between the first driving signal and the second driving signal, wherein the comparison circuit is
configured to use only the first signal when the first valve receives the first driving signal in a test mode and to use only
the second signal when the second valve receives the second driving signal in the test mode; and

a third input for receiving, from a controller, a control signal indicating when the first valve and/or the second valve receive
respective driving signals in the test mode.

US Pat. No. 9,652,413

SIGNAL PROCESSING SYSTEM AND INTEGRATED CIRCUIT COMPRISING A PREFETCH MODULE AND METHOD THEREFOR

NXP USA, Inc., Austin, T...

1. A processing system comprising:
a memory;
a master device to issue a request to access information at the memory, the request including an access address;
a programmable control register to define a first range of memory addresses and first parameters that define whether prefetching
is enabled for accesses to addresses within the first range of memory addresses, a second range of memory addresses and second
parameters that define whether prefetching is enabled for accesses to addresses within the second range of memory addresses,
and default settings that define whether prefetching is enabled for accesses to addresses that are not within the first or
the second range of memory addresses; and

a prefetch module to determine whether prefetching of information relative to the access address is enabled based on the first
parameters in response to determining that the access address is included in the first range of memory addresses, to determine
whether prefetching of information relative to the access address is enabled based on the second parameters in response to
determining that the access address is included in the second range of memory addresses, and to determine whether prefetching
of information relative to the access address is enabled based on the default settings in response to determining that the
access address is not included within the first range of memory addresses or within the second range of memory addresses.

US Pat. No. 9,584,175

RADIO FREQUENCY TRANSCEIVER LOOPBACK TESTING

NXP USA, INC., Austin, T...

1. An integrated circuit comprising:
a receiver portion comprising:
a first receiver input to receive a radio frequency (RF) signal;
a second receiver input to receive an output signal from a phase locked loop; and
a mixer coupled to the first receiver input and to the second receiver input;
a transmitter portion to transmit an RF signal at a transmitter output of the transmitter portion and to receive a modulated
PLL signal at a transmitter input of the transmitter portion;

the phase locked loop (PLL) shared between the receiver portion and the transmitter portion, the PLL during normal operation
being used by the transmitter portion during a transmit mode and being used by the receiver portion during a receive mode,
and the PLL providing at an output the modulated PLL signal based on a transmitter modulation signal; and

wherein, during a test mode, the transmitter output and the first receiver input are coupled together in a loopback configuration,
and the modulated PLL signal is provided to both the first receiver input and to the second receiver input.

US Pat. No. 9,942,858

METHOD FOR LINK ADAPTATION AND POWER AMPLIFIER VOLTAGE CONTROL AND SYSTEM THEREFOR

NXP USA, Inc., Austin, T...

1. A method comprising:determining a quality indicator designating a quality of packet reception at a wireless local area network transceiver;
estimating a distance from the transceiver to a media access point transmitter in communication with the transceiver based on the quality indicator; and
determining a supply voltage provided to a radio frequency power amplifier at the transceiver, wherein
if the distance is less than a first threshold distance, selecting a first supply voltage;
if the distance is greater than the first threshold distance and less than a second threshold distance, selecting a second supply voltage greater than the first supply voltage; and
if the distance is greater than the second threshold distance, selecting a third supply voltage less than the second supply voltage.

US Pat. No. 9,570,387

THREE-DIMENSIONAL INTEGRATED CIRCUIT SYSTEMS IN A PACKAGE AND METHODS THEREFOR

NXP USA, Inc., Austin, T...

1. A method for making a packaged semiconductor device, comprising:
dispensing adhesive into a the first cavity of the substrate having a first major surface and a second major surface, wherein
the first cavity extends into the substrate from the second major surface; and

placing a first component having a thickness less than a thickness of the substrate into the first cavity such that the adhesive
physically contacts a first major surface of the first component and at least partially fills a gap between sidewalls of the
first component and sidewalls of the first cavity, wherein, after placing the first component, a second major surface of the
first component is coplanar with the second major surface of the substrate immediately after the first component is placed
in the first cavity.

US Pat. No. 9,652,572

METHOD AND APPARATUS FOR PERFORMING LOGIC SYNTHESIS

NXP USA, Inc., Austin, T...

1. A method of designing at least a part of an integrated circuit, IC, design, the method comprising:
identifying a first and at least one further module within the IC design that are mutually exclusive;
selecting at least one register within the first identified module and at least one register within the at least one further
identified module to be shared;

merging the first and at least one further mutually exclusive modules such that a register is shared between the first and
at least one further mutually exclusive modules for the registers selected to be shared;

generating, by a signal processing module arranged to perform logic synthesis, a merged gate level netlist for the first and
at least one further mutually exclusive modules; and

outputting a merged gate level netlist to a subsequent design phase.

US Pat. No. 9,654,310

ANALOG DELAY CELL AND TAPPED DELAY LINE COMPRISING THE ANALOG DELAY CELL

NXP USA, INC., Austin, T...

1. An analog delay cell comprising:
a transconductance stage comprising:
a first current source having a first terminal coupled to receive a first power supply voltage, and a second terminal;
a first transistor having a first current electrode coupled to the second terminal of the first current source, a control
electrode for receiving a first input signal, and a second current electrode;

a second current source having a first terminal coupled to receive the first power supply voltage, and a second terminal;
a second transistor having a first current electrode coupled to the second terminal of the second current source, a control
electrode for receiving a second input signal, and a second current electrode coupled to the second current electrode of the
first transistor;

a variable capacitor having a first terminal coupled to the first current electrode of the first transistor, a second terminal
coupled to the first current electrode of the second transistor, and a control terminal for receiving a control signal; and

a first current sink having a first terminal coupled to the second current electrodes of the first and second transistors,
and a second terminal coupled to receive a second power supply voltage, wherein the first current sink provides negative-source
degeneration; and

a transimpedance stage comprising:
a first inverter having an input terminal coupled to the first current electrode of the first transistor, an output terminal
for providing a first output signal, a first power supply terminal and a second power supply terminal;

a second inverter having an input terminal coupled to the first current electrode of the second transistor, and an output
terminal for providing a second output signal, a first power supply terminal and a second power supply terminal;

a first inductor having a first terminal coupled to the input terminal of the first inverter, and a second terminal coupled
to the output terminal of the first inverter;

a second inductor having first terminal coupled to the input terminal of the second inverter, and a second terminal coupled
to the output terminal of the second inverter; and

a second current sink having a first terminal coupled to the second power supply terminals of the first and second inverters,
and second terminal coupled to receive the second power supply voltage.

US Pat. No. 9,685,405

FUSE/RESISTOR UTILIZING INTERCONNECT AND VIAS AND METHOD OF MAKING

NXP USA, INC., Austin, T...

1. A method of making a semiconductor structure comprising forming a fuse/resistor structure over a functional layer that
includes a substrate, the method of forming the fuse/resistor structure comprising:
forming a first metal layer bounded by a first insulating layer at a junction;
forming an insulating layer over the first metal layer;
forming a via having a bottom surface over the junction, wherein
said forming the via comprises forming a first opening partially through the insulating layer, forming a second opening surrounding
the first opening partially through the insulating layer and extending the first opening to the junction, depositing a barrier
layer in the first and second openings, and depositing a metal on the barrier layer in the first opening, and

more of the bottom surface of the via is in contact with the first insulating layer than is in contact with the first metal
layer; and

forming a second metal layer over and in contact with a top area of the via.

US Pat. No. 9,653,164

METHOD FOR INTEGRATING NON-VOLATILE MEMORY CELLS WITH STATIC RANDOM ACCESS MEMORY CELLS AND LOGIC TRANSISTORS

NXP USA, INC., Austin, T...

1. A method of making a semiconductor device, the method comprising:
depositing a first polysilicon layer in a non-volatile memory (NVM) region and a logic region of a substrate;
depositing a first anti-reflective coating (ARC) layer over the first polysilicon layer;
patterning the first ARC layer and the first polysilicon layer to form a first gate in the NVM region while the first ARC
layer and the first polysilicon layer remains in the logic region;

forming a memory cell including the first gate in the NVM region while the first ARC layer and first polysilicon layer remains
in the logic region;

removing the first ARC layer and the first layer of polysilicon in the logic region;
implanting source/drain extension regions of the memory cell before depositing a logic gate polysilicon layer in the NVM region
and the logic region;

patterning the logic gate polysilicon layer to form a second gate in the logic region while the logic gate polysilicon layer
is removed from the NVM region; and

concurrently implanting source/drain regions of the memory cell and the second gate.

US Pat. No. 9,788,314

BASE TRANSCEIVER STATION FOR REDUCING CONGESTION IN COMMUNCATION NETWORK

NXP USA, INC., Austin, T...

1. A base transceiver station, comprising:
an antenna interface system that receives first and second uplink real-time (RT) data;
an uplink random-access memory (RAM) connected to the antenna interface system, wherein the antenna interface system stores
the first and second uplink RT data in the uplink RAM;

a first direct memory access (DMA) controller connected to the uplink RAM;
a cache memory connected to the first DMA controller, wherein the first DMA controller fetches the first uplink RT data from
the uplink RAM and stores the first uplink RT data in the cache memory;

a set of processors including a first processor connected to the cache memory, wherein the first processor fetches the first
uplink RT data from the cache memory for baseband decoding, and a second processor connected to the first DMA controller,
wherein the first DMA controller fetches the second uplink RT data from the uplink RAM and provides the second uplink RT data
to the second processor for baseband decoding;

a second DMA controller connected to at least one processor of the set of processors and the cache memory; and
a downlink RAM connected to the second DMA controller and the antenna interface system,
wherein the second DMA controller fetches downlink RT data from at least one of the cache memory and the at least one processor
and stores the downlink RT data in the downlink RAM,

wherein the antenna interface system fetches the downlink RT data from the downlink RAM and transmits the downlink RT data,
and

wherein the first and second uplink RT data are stored in the uplink RAM as in-phase and quadrature-phase components, and
the downlink RT data is stored in the downlink RAM as in-phase and quadrature-phase components.

US Pat. No. 9,607,911

OPTICAL PROGRAMMING OF ELECTRONIC DEVICES ON A WAFER

NXP USA, Inc., Austin, T...

1. A system for programming integrated circuit (IC) dies formed on a wafer comprising:
an optical transmitter configured to output a digital program as an optical signal;
an optical sensor formed with said IC dies of said wafer, said optical sensor being configured to receive said optical signal
from said optical transmitter;

a processor formed on said wafer and in communication with said optical sensor, said processor being adapted to convert said
optical signal to said digital program; and

a memory element associated with one of said IC dies on said wafer, said memory element being adapted to store said digital
program, wherein said one of said IC dies includes a built-in self-test (BIST) mechanism to determine a functionality of said
one of said IC dies, said processor is configured to communicate with said BIST mechanism, said processor is further configured
to execute said digital program and receive a test result indicative of said functionality of said one of said IC dies, and
wherein execution of said digital program initiates operation of said BIST mechanism and receipt of said test result from
said BIST mechanism.

US Pat. No. 9,607,953

SEMICONDUCTOR PACKAGE WITH ISOLATION WALL

NXP USA, Inc., Austin, T...

1. A semiconductor device package comprising:
a substrate;
a first circuit on said substrate, said first circuit comprising a first plurality of electrical components;
a second circuit on said substrate, said second circuit comprising a second plurality of electrical components;
an isolation wall located between said first circuit and said second circuit, said isolation wall extending perpendicularly
from a surface of said substrate above a height of said first plurality of components and said second plurality of components,
said isolation wall having an upper edge, said upper edge having a notched profile of indentations extending toward said surface
of said substrate; and

encapsulation material covering said surface of said substrate and said first and second circuits.

US Pat. No. 9,590,548

METHOD AND APPARATUS FOR REGULATING AN OUTPUT VOLTAGE OF AN ALTERNATOR

NXP USA, Inc., Austin, T...

1. A method of regulating an output voltage of an alternator, the method comprising, within an alternator regulator module:
measuring a first voltage across a first external contact of the alternator regulator module operably coupled to a first output
contact of the alternator and a second external contact of the alternator regulator module operably coupled to a second output
contact of the alternator during an ON state of an excitation cycle for the alternator;

measuring a second voltage across the first external contact of the alternator regulator module and the second external contact
of the alternator regulator module during an OFF state of an excitation cycle for the alternator;

deriving an average voltage value of the first and second voltage measurements; and
deriving an offset value based at least partly on the derived average voltage value,
wherein the method further comprises:
measuring an instantaneous voltage across the first external contact of the alternator regulator module and the second external
contact of the alternator regulator module; and

configuring a control signal for regulating the output voltage of the alternator based at least partly on the instantaneous
voltage measurement and the derived offset value.

US Pat. No. 9,641,464

FIFO BUFFER SYSTEM PROVIDING SAME CLOCK CYCLE RESPONSE TO POP COMMANDS

NXP USA, Inc., Austin, T...

1. A first-in first-out (FIFO) buffer system comprising:
a first storage partition comprising a single-port memory bank having an input to receive a clock signal, the first storage
partition associated with a first subset of memory addresses, the first storage partition further comprises a first prefetch
buffer having an input to receive the clock signal;

a second storage partition comprising a single-port memory bank having an input to receive the clock signal, the second storage
partition associated with a second subset of memory addresses; and

FIFO control logic coupled to the first and second storage partitions and having an input to receive the clock signal, in
response to a read access for data being received by the FIFO control logic during a clock cycle of the clock signal, the
FIFO control logic to access and output the data from the first storage partition in a same clock cycle of the clock signal
in which the read access for the data is received and while a write access to the first storage partition is received in the
same clock cycle of the clock signal, to determine the first prefetch buffer contains valid data in response to a prefetch
of first data completing before the same clock cycle, and to determine the first prefetch buffer does not contain valid data
in response to the prefetch of the first data not completing before the same clock cycle, to access and output the data from
the first storage partition by accessing and outputting data from the first prefetch buffer in response to determining the
first prefetch buffer is storing valid data and by accessing and outputting data available at an output of the single-port
memory bank of the first storage partition in response to determining the first prefetch buffer is not storing valid data.

US Pat. No. 9,606,064

METHOD OF DETECTING IRREGULAR CURRENT FLOW IN AN INTEGRATED CIRCUIT DEVICE AND APPARATUS THEREFOR

NXP USA, INC., Austin, T...

1. A method of detecting irregular high current flow within an integrated circuit (IC) device, the method comprising:
obtaining infrared (IR) emission information for the IC device;
identifying at least one functional component of a plurality of functional components within one or more functional modules
of the IC device, the at least one identified functional component comprising a high current flow, based on the obtained IR
emission information;

obtaining IR emission information for a plurality of reference components, wherein each of the plurality of reference components
comprising different IR emission spectral properties, the different IR emission spectral properties corresponding to IR emission
spectral properties of different ones of the plurality of functional components, wherein the plurality of reference components
formed within a reference module of the IC device, and wherein each of the plurality of reference components having individually
configured bias conditions that correspond to bias conditions of a different one of the plurality of functional components;
and

determining whether the high current flow of the at least one functional component comprises an irregular high current flow
based on a comparison of respective IR emission information for the at least one functional component and a corresponding
one of the plurality of reference components.

US Pat. No. 9,607,918

FAN-OUT WAFER LEVEL PACKAGES CONTAINING EMBEDDED GROUND PLANE INTERCONNECT STRUCTURES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A Fan-Out Wafer Level Package (FO-WLP), comprising:
a molded package body;
a first microelectronic device embedded in the molded package body and having a backside contact;
an Embedded Ground Plane (EGP) further embedded in the molded package body; and
a backside EGP interconnect structure embedded in the molded package body and bonded to the backside contact such that the
first microelectronic device is electrically coupled to the EGP through the backside EGP interconnect structure;

a second microelectronic device embedded in the molded package body and electrically coupled to the EGP through the backside
EGP interconnect structure;

wherein the second microelectronic device has a height less than the first microelectronic device; and
wherein the backside EGP interconnect structure comprises one or more stepped features compensating for the difference in
height between the first and second microelectronic devices.

US Pat. No. 9,601,638

GAN-ON-SI SWITCH DEVICES

NXP USA, INC., Austin, T...

1. A method of forming a low leakage current switching device, comprising:
forming one or more elevated mesa islands in a gallium nitride substrate layer, each elevated mesa island having mesa sidewalls
and an elevated surface of the gallium nitride substrate layer that is vertically and laterally displaced from a upper facing
surface of the gallium nitride substrate layer;

forming one or more ohmic alloy source/drain contact layers on the elevated surface of the one or more elevated mesa islands;
then

forming an implant mask to protect an interior portion of each elevated surface of the elevated mesa island while leaving
uncovered the mesa sidewalls and a peripheral region around each elevated surface of the elevated mesa island; and

forming an isolation region for each elevated mesa island by using the implant mask to implant ions into an upper portion
of the mesa sidewalls and the peripheral region uncovered by the implant mask layer, thereby forming the isolation region
to extend into a portion of the elevated mesa island.

US Pat. No. 9,599,672

INTEGRATED CIRCUIT WITH SCAN CHAIN HAVING DUAL-EDGE TRIGGERED SCANNABLE FLIP FLOPS AND METHOD OF OPERATING THEREOF

NXP USA, Inc., Austin, T...

1. An integrated circuit comprising:
a scan chain having a first plurality of dual edge flip flops and a second plurality of dual edge flip flops, wherein each
dual edge flip flop of the first and second pluralities of dual edge flip flops includes a data input, a scan input, a clock
input, and data output, the scan chain to receive a test pattern at the scan input that is synchronous with a test clock during
a shift phase of scan testing;

a clock divider circuit coupled to receive the test clock and configured to divide the test clock to provide a divided test
clock having a lower frequency than the test clock;

clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to receive
a system clock, a control input coupled to receive a scan enable signal, and an output coupled to provide one of the divided
test clock and the system clock as a clock signal to the clock input of the scan chain based on the scan enable signal, wherein
the divided test clock is provided to the clock input of the scan chain during the shift phase of scan testing; and

second clock selection circuitry having a first input coupled to receive the divided test clock, a second input coupled to
receive a second system dock, a control input coupled to receive the scan enable signal, and an output configured to provide
the divided test clock as a second clock signal to the clock input of each dual edge flip flop of the second plurality of
dual edge flip flops when the scan enable signal has the first value, and to provide the second system clock as the clock
signal to the clock input of each dual edge flip flop of the second plurality of dual edge flip flops when the scan enable
signal has the second value wherein the second system clock is 90 degrees out of phase with the system clock.

US Pat. No. 9,601,479

PROTECTION CIRCUIT, CIRCUIT EMPLOYING SAME, AND ASSOCIATED METHOD OF OPERATION

NXP USA, Inc., Austin, T...

1. A circuit comprising:
a first input terminal;
a first circuit portion having a second input terminal, wherein the first circuit portion includes an input buffer that includes
the second input terminal and an output terminal; and

a second circuit portion that includes:
a transistor device having first, second, and third ports, wherein the first port is electrically coupled to the first input
terminal, and wherein the second port is electrically coupled to the second input terminal;

a diode-type device having an anode and a cathode, wherein the diode-type device is electrically coupled between the third
port and either a power source or a power input terminal of the integrated circuit; and

an additional circuit and a capacitor coupled in series between the third port and the second port, wherein an output terminal
of the additional circuit is coupled to the capacitor, and wherein the additional circuit includes either a buffer circuit
or a driver circuit,

wherein one or both of (a) the output terminal is short-circuited to an output pin of the circuit and configured for supplying
at least one output signal to another device external to the circuit, or (b) the output terminal is coupled to a third circuit
portion included within the integrated circuit.

US Pat. No. 9,595,329

NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM) WITH BACKUP CONTROL

NXP USA, INC., Austin, T...

1. A memory system, comprising;
a first plurality of non-volatile random access memory (NVRAM) cells, wherein each NVRAM cell has a volatile portion coupled
to a corresponding non-volatile portion;

a non-volatile indicator circuit that provides information as to whether the first plurality of NVRAM cells has the most recent
data written into NVRAM cells in the non-volatile portions; and

a memory controller coupled to the first plurality of NVRAM cells and the non-volatile indicator circuit;
wherein, in response to a power up of the memory system, the memory controller directs the first plurality of NVRAM cells
to load data present in each of the non-volatile portions into the corresponding volatile portions if the non-volatile indicator
circuit indicates that the most recent data had been written into the non-volatile portion of all of the first plurality NVRAM
cells of the block.

US Pat. No. 9,559,178

NON-VOLATILE MEMORY (NVM) CELL AND DEVICE STRUCTURE INTEGRATION

NXP USA, Inc., Austin, T...

1. A semiconductor device comprising:
a substrate having a capacitor region with a first doped well and a memory region with a second doped well;
a dielectric layer over the substrate in the capacitor region and the memory region;
a select gate layer over the dielectric layer in the capacitor region and the memory region;
a select gate over the memory region and a plurality of lines of electrodes over the capacitor region from the select gate
layer;

a charge storage layer over the capacitor region and the memory region including over the select gate and the plurality of
lines of electrodes;

a control gate layer over the charge storage layer over the capacitor region and over the memory region; and
conductive vias electrically connecting the plurality of conductive lines to the first doped well, wherein:
the control gate layer is patterned to form a control gate of a memory cell over the memory region and a first electrode of
a capacitor over the capacitor region

the plurality of lines of electrodes are connected to the first doped well in the capacitor region to form a second electrode
of the capacitor.

US Pat. No. 9,992,758

SEARCH METHOD AND APPARATUS FOR A COMMUNICATION SYSTEM

NXP USA, Inc., Austin, T...

1. A method for searching of base stations in a mobile communication system, the method comprising:detecting at least one slot boundary at a first stage of detecting, wherein said detecting the at least one slot boundary comprises:
correlating an input signal with a primary synchronization channel code and detecting at least one correlation peak,
determining a first threshold based on a histogram of bins of correlation values of said correlating the input signal with the primary synchronization channel code, wherein a bin above an average of all correlation values and that has zero or a minimum of delays of correlation values is used to set the first threshold, and
selecting the possible base station slot boundaries corresponding to delays of correlation values above the first threshold;
detecting at least one frame boundary, at a second stage of detecting, in accordance with a frame delay and a scrambling code group, wherein said detecting the at least one frame boundary comprises:
correlating a slot aligned input signal aligned to the detected slot boundary with secondary synchronization channel (SSCH) codes for combining the SSCH codes into code words,
correlating multiple SSCH sequences at multiple possible frame delays for identifying frame boundaries and identifying a code group by the respective SSCH sequence,
for each of said delays of correlation values above the first threshold,
aligning the input signal to the corresponding slot boundary,
computing an average correlation value based on all correlations with said SSCH sequences, and
setting a second threshold based on the average correlation value; and
detecting a scrambling code in a third stage of detecting, wherein said detecting the scrambling code comprises:
correlating a frame aligned input signal aligned to the frame boundary with the codes in the code group as identified at the second stage, and
processing any delay and codeword of the scrambling code that have a correlation value above the second threshold for computing the correlation with the codes in the detected group so as to detect multiple base stations.

US Pat. No. 9,594,623

SYSTEM ON CHIP AND METHOD OF UPDATING PROGRAM CODE ON A SYSTEM ON CHIP

NXP USA, INC., Austin, T...

1. A system on chip (SoC), comprising:
multiple functional units;
a memory unit comprising a program region and a log region;
a processing unit for executing program code and arranged to perform an update operation in response to an update request
received or generated by the processing unit, wherein the update operation comprises appending an update enabling record to
a sequence of update records in the log region, writing new program code to the program region, and appending an update completion
record to the sequence of update records in the log region;

a memory control unit connected between the memory unit and the processing unit, for controlling access to the memory unit;
and

a fault collection unit arranged to assert a fault flag in response to a fault occurring in the SoC, wherein the multiple
functional units are connected to the fault collection unit, each one of the multiple functional units configured to signal
a fault of the respective functional unit to the fault collection unit;

wherein the memory control unit is further connected to the fault collection unit and arranged to disable write access to
the log region in response to the fault flag being asserted.

US Pat. No. 9,586,812

DEVICE WITH VERTICALLY INTEGRATED SENSORS AND METHOD OF FABRICATION

NXP USA, Inc., Austin, T...

1. A method of producing a sensor device comprising:
forming a device structure having a first wafer layer, a second wafer layer, and a signal routing layer interposed between
said first and second wafer layers;

forming a first active transducer element of a first sensor in said first wafer layer;
forming a trench extending through said second wafer layer and extending through a portion of said signal routing layer, said
trench surrounding a region of said second wafer layer, and said trench electrically isolating said region of said second
wafer layer surrounded by said trench from a remainder of said second wafer layer;

forming a second active transducer element of a second sensor in said region of said second wafer layer to produce said sensor
device that includes both of said first and second sensors each being capable of sensing a different physical stimulus; and

attaching a third wafer layer with said first wafer layer, said attaching operation producing a cavity in which said first
active transducer element is located.

US Pat. No. 9,588,157

INTEGRATED CIRCUIT, CURRENT SENSE CIRCUIT FOR A PULSE WIDTH MODULATION DRIVER AND METHOD THEREFOR

NXP USA, Inc., Austin, T...

1. A current sensing circuit for a pulse width modulation driver, the current sensing circuit comprising:
a first PWM control circuit comprising:
a first switching device arranged to receive a PWM signal from the PWM driver whose current is to be sensed; and
a second switching device whose supply current is arranged to track the sensed current of the PWM driver;
a first analog-to-digital converter operably coupled to the first switching device and second switching device, wherein the
first ADC comprises:

a first digital-to-analog converter arranged to provide a current sense to the second switching device that tracks the current
passing through the PWM driver;

a first comparator arranged to receive and compare an output current from the first DAC and an output current from the first
switching device; and

a first successive approximation register arranged to receive an output from the comparator and provide:
a first output to the first ADC; and
a second output that provides a representation of the sensed current.

US Pat. No. 9,558,373

3D GRAPHICS SYSTEM USING ENCRYPTED TEXTURE TILES

NXP USA, Inc., Austin, T...

1. A 3D graphics system comprising:
a key storage configured to store encryption keys,
an input for receiving a texture comprising tiles of texture data and for receiving texture tile status data,
a texture storage configured to store the tiles of texture data,
a texture tile encryption status storage configured to store the texture tile status data indicating whether an associated
one of the tiles of texture data is encrypted or not and if encrypted which one of the encryption keys has been used,

a first decryption unit coupled to the texture storage, to the first tile encryption status storage and to the key storage
and configured to decrypt encrypted tiles of texture data in accordance with the associated ones of the encryption keys and
to output decrypted tiles of texture data,

a render unit coupled to the first decryption unit configured to render the decrypted tiles of texture data into rendered
tiles,

an encryption unit coupled to the render unit, to a frame buffer and to a buffer tile encryption status storage configured
to receive at least one of the rendered tiles as input, to encrypt the at least one of the rendered tiles, and to store the
encrypted rendered tiles in the frame buffer and to store an associated buffer tile status data in the buffer tile encryption
status storage, the buffer tile status data indicates whether an associated one of the rendered tiles is encrypted or not,
and if encrypted which one of the encryption keys has been used,

a second decryption unit coupled to the frame buffer, the buffer tile encryption status memory and the key storage configured
to receive encrypted rendered tiles as input, to decrypt the encrypted rendered tiles, and to output decrypted rendered tiles,

an output for supplying the decrypted rendered tiles and if present the rendered tiles not encrypted, to a display controller.

US Pat. No. 10,143,084

PLATED OPENING WITH VENT PATH

NXP USA, INC., Austin, T...

1. A method of forming a plated opening in a workpiece comprising:forming a first opening in a first major surface of workpiece, wherein the forming the first opening includes removing non-conductive material of the workpiece to form a sidewall of the non-conductive material;
plating the sidewall with a conductive material to form a sidewall plating;
after the plating, forming a vent opening, wherein the forming the vent opening includes removing a portion of the non-conductive material at the sidewall, wherein at least a first portion of the sidewall plating remains after the forming the vent opening, wherein the forming the vent opening includes forming a second sidewall of the non-conductive material that is not covered by the sidewall plating.

US Pat. No. 9,628,057

SPREAD-SPECTRUM CLOCK GENERATION CIRCUIT, INTEGRATED CIRCUIT AND APPARATUS THEREFOR

NXP USA, Inc., Austin, T...

1. A spread-spectrum clock generation circuit comprising:
at least one comparison element;
a shunt charge storage device operably coupled to the at least one comparison element and arranged to limit a voltage applied
thereto;

at least one charge storage device arranged to couple an output of the at least one comparison element to an input of the
at least one comparison element and arranged to set a first oscillation frequency of the spread-spectrum clock generation
circuit; and

a switched charge storage arrangement additionally arranged to couple an output of the at least one comparison element to
an input of the at least one comparison element and arranged to set a second oscillation frequency of the spread-spectrum
clock generation circuit.

US Pat. No. 9,618,556

MEMS DEVICE POSITIONING APPARATUS, TEST SYSTEM, AND TEST METHOD

NXP USA, Inc., Austin, T...

1. A method of testing a microelectromechanical systems (MEMS) device comprising:
loading said MEMS device into a fixture of a positioning apparatus, said positioning apparatus including a support structure,
a positioning structure, a first shaft spanning between said support structure and said positioning structure, and a second
shaft in physical communication with said positioning structure, said fixture being retained on said second shaft;

installing said positioning structure and said fixture into a test chamber;
placing said fixture into a first position;
obtaining a first output signal from said MEMS device in said first position;
orienting said fixture into a second position by rotating at least one of said first and second shafts, wherein said orienting
operation rotates said fixture about at least one of first and second orthogonal axes;

obtaining a second output signal from said MEMS device in said second position; and
determining a functionality of said MEMS device utilizing said first and second output signals.

US Pat. No. 9,619,405

DEVICE HAVING MEMORY ACCESS PROTECTION

NXP USA, INC., Austin, T...

1. A system, comprising:
a system bus connectable to a target memory and to a source of indirect memory access requests, the indirect memory access
requests comprising control data indicative of a memory access control register to be written to provide access to the target
memory and requested address data indicative of at least one memory address of the target memory to be accessed, and

a protection unit for controlling access to the target memory, comprising:
a data storage for containing protection data defining access rights of source units to access specified address ranges of
the target memory,

a system bus interface arranged to interface to at least one source unit via the system bus and a memory bus interface arranged
to interface to the target memory via a memory bus,

a control monitor to monitor the system bus for detecting a respective indirect memory access request issued by a respective
source unit, and

an indirect address monitor arranged to, upon said detecting, compare requested address data of the respective indirect memory
access request to respective specified address ranges and subsequently grant the indirect memory access as requested by the
respective indirect memory access request in accordance with respective access rights of the respective source unit.

US Pat. No. 9,621,483

ETHERCAT PACKET FORWARDING WITH DISTRIBUTED CLOCKING

NXP USA, INC., Austin, T...

1. A packet forwarding system, the system comprising:
a plurality of slave devices, each slave device comprising
a processing port and a forward port coupled to ports of a master device in a redundant ring topology,
an internal clock configured to provide a current time, and
a slave memory storing a processing timestamp variable, a forwarding timestamp variable, a temporary timestamp variable and
a copy-direct bit, wherein the system is configured to

generate a header of a frame datagram for each slave that comprises a circulating bit indicating whether the redundant ring
topology is interrupted,

when the frame datagram is received at the forward port of a slave device and the copy-direct bit is set, the current time
is copied to the forwarding time stamp variable and the copy-direct bit is reset,

when the frame datagram is received at the forward port of the slave device and the copy-direct bit is not set, the current
time is copied to the temporary time stamp variable,

when the frame datagram is received at the processing port of the slave device, the current time is copied to the processing
time stamp variable and if the circulating bit indicates that the redundant ring topology is not interrupted, the copy-direct
bit is set, and if the circulating bit indicates that the redundant ring topology is net interrupted, the temporary timestamp
variable is copied to the forwarding timestamp variable.

US Pat. No. 9,620,002

METHOD AND APPARATUS FOR SELECTING AT LEAST ONE DEVICE TO BE WIRELESSLY CONTROLLED

NXP USA, INC., Austin, T...

1. A method for selecting at least one device to be controlled by a radio frequency (RF) controller device, the method comprising:
determining a first link quality value for a first device associated with a first group of a plurality of groups, each group
of the plurality of groups having one or more controllable devices;

determining a second link quality value for a second device associated with a second group of the plurality of groups;
calculating a first proximity factor for the first group based at least partly on the determined first link quality value;
calculating a second proximity factor for the second group based at least partly on the determined second link quality value;
comparing the first and second proximity factors;
based on the comparing, selecting the first group to be controlled by the RF controller device over the second group in response
to the first group having a more favourable proximity factor than the second group; and

subsequent to selecting the first group, selecting a different group of the plurality of groups in response to the different
group having a proximity factor that is more favourable by more than a threshold amount than the proximity factor of the currently
selected first group.

US Pat. No. 9,601,614

COMPOSITE SEMICONDUCTOR DEVICE WITH DIFFERENT CHANNEL WIDTHS

NXP USA, INC., Austin, T...

1. A device comprising:
a semiconductor substrate;
a first constituent transistor comprising a first plurality of transistor structures in the semiconductor substrate connected
in parallel with one another; and

a second constituent transistor comprising a second plurality of transistor structures in the semiconductor substrate connected
in parallel with one another;

wherein the first and second constituent transistors are disposed laterally adjacent to one another and connected in parallel
with one another;

wherein each transistor structure of the first and second pluralities of transistor structures comprises a plurality of source
regions and a plurality of body contact regions disposed in an alternating arrangement with the plurality of source regions
along a lateral dimension of the device; and

wherein each transistor structure of the first plurality of transistor structures has a lower resistance in a saturation region
of operation than each transistor structure of the second plurality of transistor structures due to a layout difference in
the alternating arrangement between the first and second pluralities of transistor structures.

US Pat. No. 9,595,505

THERMALLY-ENHANCED THREE DIMENSIONAL SYSTEM-IN-PACKAGES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A three dimensional (3D) System-in-Package (SiP) comprising:
a heat-dissipating structure having a first principal surface and a second principal surface opposite the first principal
surface;

a first microelectronic device having a backside disposed adjacent and thermally coupled to the first principal surface of
the heat-dissipating structure;
a second microelectronic device having a backside disposed adjacent and thermally coupled to the second principal surface
of the heat-dissipating structure;
a first substrate to which the first microelectronic device is mounted;
a second substrate to which the second microelectronic device is mounted;
a thermally-conductive base piece to which the second substrate is mounted, the thermally-conductive base piece assuming the
form of a metal plate placed in contact with the second substrate; and

metal clip extending from an outer edge portion of the heat-dissipating structure to the thermally-conductive base piece.

US Pat. No. 9,589,927

PACKAGED RF AMPLIFIER DEVICES WITH GROUNDED ISOLATION STRUCTURES AND METHODS OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A packaged radio frequency (RF) amplifier device comprising:
a device substrate having a top substrate surface;
a transistor die, wherein the transistor die includes a top die surface, a bottom die surface coupled to the top substrate
surface, a semiconductor substrate, first and second transistors formed in the semiconductor substrate, a conductive structure
at the top die surface and positioned between the first and second transistors, and a low resistance path that extends vertically
through the semiconductor substrate between the conductive structure and the bottom die surface, wherein the first transistor
forms a portion of a first signal path through the device, and the second transistor forms a portion of a second signal path
through the device; and

an isolation structure coupled to the conductive structure and extending into an area above the top die surface between the
first and second transistors, wherein the isolation structure reduces inductive coupling between the first and second signal
paths.

US Pat. No. 9,839,028

CARRIER AGGREGATION CONTROLLER AND METHOD

NXP USA, Inc., Austin, T...

1. A carrier aggregation controller for providing an aggregated baseband signal from a plurality of baseband signals, each
baseband signal of the plurality of baseband signals being associated with a respective central frequency of a plurality of
central frequencies, the aggregated baseband signal comprising the plurality of baseband signals each centered at the respective
central frequency of the plurality of central frequencies, the controller comprising
an accumulating memory;
a selector configured to add at least
a first list of frequency domain samples obtained for a first baseband signal to first consecutive locations in the accumulating
memory and

a second list of frequency domain samples obtained for a second baseband signal to second consecutive locations in the accumulating
memory; and

a time domain transformer configured to apply at least an inverse discrete Fourier transform to the frequency domain samples
accumulated in the accumulating memory, thereby obtaining the aggregated baseband signal;

wherein the first consecutive locations are centered at a first preset location associated with the first baseband signal,
and the second consecutive locations are centered at a second preset location associated with the second baseband signal.

US Pat. No. 9,741,449

SAMPLE AND HOLD CIRCUIT

NXP USA, Inc., Austin, T...

1. An apparatus, comprising:
a sample and hold circuit including a first capacitor and a second capacitor and configured and arranged to
in a first mode
sample a voltage difference between an input node of the sample and hold circuit and a first reference voltage using the first
capacitor; and

provide a voltage stored by the second capacitor, and referenced to a second reference voltage, to a first output node of
the sample and hold circuit; and

in a second mode
sample a voltage difference between the input node and the first reference voltage using the second capacitor; and
provide a voltage stored by the first capacitor, and referenced to the second reference voltage, to a second output node of
the sample and hold circuit; and

wherein the sample and hold circuit includes a set of components including capacitors and transistors, each component being
subject to failure in response to a voltage difference between at least a pair of terminals of the component exceeding the
tolerance voltage of the component and the voltage difference between the input node and the second reference voltage is greater
than the tolerance voltage of the components.

US Pat. No. 9,689,919

METHOD AND APPARATUS FOR TESTING MEMORY

NXP USA, INC., Austin, T...

9. A system, comprising:
a memory for storing data;
a memory built-in self-test (MBIST) wrapper circuit coupled to the memory for testing operation of the memory, wherein the
MBIST wrapper circuit provides retention data to the memory for storage in the memory;

a scan chain of flip-flops having an input and an output, wherein the scan chain receives scan data via the input and stores
the scan data in the flip-flops;

combinational logic coupled to the memory, wherein the flip-flops of the scan chain comprise a part of the combinational logic;
and

a power management control (PMC) unit for controlling an operating voltage of the combinational logic,
wherein the PMC unit initiates a low-power mode in which the operating voltage of the combinational logic is reduced for a
predetermined period of time, and

the MBIST wrapper circuit reads the retention data from the memory and determines retention of data by the memory based on
the read retention data.

US Pat. No. 9,658,664

ELECTRONIC DEVICE HAVING A PIN FOR SETTING ITS MODE OF OPERATION AND METHOD TO SET A MODE OF OPERATION FOR AN ELECTRONIC DEVICE HAVING A PIN

NXP USA, Inc., Austin, T...

1. An electronic device having a pin for setting its mode of operation, the electronic device comprising:
a push-pull stage including a first transistor having a first current electrode coupled to the pin and a second current electrode
coupled to a first reference voltage and a second transistor having a first current electrode coupled to the pin and a second
current electrode coupled to a second reference voltage, the push-pull stage configured to adjust a voltage provided at the
pin;

a first current mirror including a third transistor, a control electrode of the third transistor coupled to a control electrode
of the first transistor, the first current mirror to clone a current conducted at the first transistor; and

a second current mirror including a fourth transistor, a control electrode of the fourth transistor coupled to a control electrode
of the second transistor, the second current mirror to clone a current conducted at the second transistor,

wherein the pin is connected to a first terminal of a resistor,
wherein the electronic device is arranged to detect a location of the resistor, the location identifying connectivity of a
second terminal of the resistor,

wherein the electronic device is arranged to detect a size of the resistor based on a current provided by the first current
mirror and a current provided by the second current mirror,

wherein the electronic device is arranged to determine a first setting based on the location of the resistor, and
wherein the electronic device is arranged to determine a second setting based on the size of the resistor.

US Pat. No. 9,652,106

TOUCH-SCREEN INTERFACE CIRCUIT

NXP USA, Inc., Austin, T...

1. A touch-screen interface circuit, configured to operate in at least a first, a second and a third mode, comprising:
a first resistive x-plate having
at least a first x-terminal connected in said first mode to a voltage supply and
a second x-terminal connected in said first mode to a circuit ground;
a voltage regulator circuit comprising
a floating reference voltage source connected in said first mode to said second x-terminal, and to a first input of
a touch-screen reference buffer circuit having a second input connected in said first mode to said first x-terminal; said
voltage regulator circuit arranged to control in said first mode a connection between said voltage supply and said first x-terminal;
and

a second resistive y-plate having at least a first y-terminal and being arranged to apply a local wiper contact to said first
x-plate, said wiper contact having an x-position, a y-position and a pressure.

US Pat. No. 9,653,410

TRANSISTOR WITH SHIELD STRUCTURE, PACKAGED DEVICE, AND METHOD OF MANUFACTURE

NXP USA, Inc., Austin, T...

1. A transistor comprising:
a semiconductor substrate having a first terminal and a second terminal; and
an interconnect structure on an upper surface of said semiconductor substrate, said interconnect structure being formed of
multiple layers of dielectric material and electrically conductive material, wherein said interconnect structure comprises:

a pillar formed from said electrically conductive material, said pillar being in electrical contact said first terminal, said
pillar extending through said dielectric material;

a tap interconnect formed from said electrically conductive material, said tap interconnect being in electrical contact with
said second terminal, said tap interconnect extending through said dielectric material; and

a shield structure formed from said electrically conductive material, said shield structure extending through said dielectric
material toward said semiconductor substrate, said shield structure being positioned between said pillar and said tap interconnect
wherein said tap interconnect forms a portion of an input to said second terminal, said pillar forms a portion of an output
from said first terminal, and said shield structure is configured to block an electric field between said tap interconnect
and said pillar.

US Pat. No. 9,685,816

POWER RECEIVER FOR WIRELESS CHARGING SYSTEM

NXP USA,INC., Austin, TX...

1. A power receiver for a wireless power transmission system, the power receiver comprising:
input circuitry that converts power transmitted wirelessly from a power transmitter into an input signal; and
a regulator, connected to the input circuitry, that regulates the input signal to generate a regulated output signal based
on a current reference signal and a voltage reference signal, wherein:

the output signal is applied to a load; and
the regulator controls at least one of the current reference signal and the voltage reference signal to control power loss
within the power receiver;

the regulator (i) senses output voltage level and output current level of the output signal, (ii) generates the regulated
output signal based on the sensed output voltage level and the sensed output current level, and (iii) adjusts the current
reference signal to control the power loss within the receiver;

the regulator comprises:
a power transistor having a control node, an input node that receives the input signal, and an output node that provides the
output signal; and

control circuitry that controls a voltage level at the control node of the power transistor based on the voltage reference
signal, the sensed output voltage level, the current reference signal, and the sensed output current level;

the control circuitry comprises:
voltage-based control circuitry that controls the voltage level at the control node of the power transistor based on a comparison
of the voltage reference signal and the sensed output voltage; and

current-based control circuitry that controls the voltage level at the control node of the power transistor based on a comparison
of the current reference signal and the sensed output current level;

the voltage-based control circuitry comprises:
a differential amplifier connected to receive the voltage reference signal and the sensed output voltage level; and
a first control transistor having a control node connected to an output of the differential amplifier, and an output node
connected to the control node of the power transistor; and

the current-based control circuitry comprises:
a first operational amplifier (opamp) connected to receive the current reference signal and the sensed output current level;
and

a second control transistor having a control node connected to an output of the first opamp, and an output node connected
to the control node of the power transistor.

US Pat. No. 9,666,710

SEMICONDUCTOR DEVICES WITH VERTICAL FIELD FLOATING RINGS AND METHODS OF FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A semiconductor device comprising:
a semiconductor substrate having a first conductivity type, a first surface, and an opposed second surface;
a gate structure supported by the first surface of the semiconductor substrate;
a first current carrying region disposed in the semiconductor substrate at the first surface, wherein the first current carrying
region is laterally separated from the gate structure;

a drift region of a second conductivity type disposed in the semiconductor substrate at the first surface, wherein the second
conductivity type is opposite the first conductivity type, and the drift region extends laterally from the first current carrying
region to the gate structure; and

a first buried region of the second conductivity type disposed in the semiconductor substrate below the first current carrying
region, wherein the first buried region is vertically aligned with the first current carrying region, the first buried region
does not extend into any portion of the semiconductor substrate directly underlying the gate structure, and a first portion
of the semiconductor substrate with the first conductivity type is present between the first buried region and the first current
carrying region.

US Pat. No. 9,608,623

SYSTEM AND METHOD FOR MONITORING VOLTAGE ACROSS ISOLATION BARRIER

NXP USA, Inc., Austin, T...

1. An isolation system comprising:
a first low voltage (LV) circuit portion including a first control logic portion;
a first high voltage (HV) circuit portion including a second control logic portion and an analog-to-digital converter portion;
one or more coupling channels coupling the first LV and HV circuit portions by way of a galvanic barrier; and
a first transistor device having a first terminal coupled at least indirectly to a first connection having a first voltage
level and a second terminal coupled at least indirectly to a second connection having a second voltage level related to the
first voltage level,

wherein the second terminal is coupled at least indirectly to a first port of the analog-to-digital converter portion,
wherein the first control logic portion governs provision of an output signal from an output terminal of the isolation system
for receipt by another device, the output signal being generated based at least indirectly upon the second voltage level and
being indicative of the first voltage level, and

wherein, due to the galvanic barrier, the output signal can be provided for receipt by the other device in a manner that avoids
exposure of the other device to an undesirably high current or power level associated with the first HV circuit portion or
the first transistor device.

US Pat. No. 9,595,509

STACKED MICROELECTRONIC PACKAGE ASSEMBLIES AND METHODS FOR THE FABRICATION THEREOF

NXP USA, INC., Austin, T...

1. A stacked microelectronic package assembly, comprising:
a base package layer, comprising:
a first microelectronic package having a first backside contact;
a second microelectronic package positioned laterally adjacent the first microelectronic package and having a second backside
contact;

a substrate to which the first and second microelectronic packages are mounted in a laterally-spaced relationship such that
neighboring sidewalls of the first and second microelectronic packages define an unfilled air gap between the first and second
microelectronic packages; and

a stacked bridge device stacked onto the base package layer opposite the substrate, the stacked bridge device extending from
the first microelectronic package to the second microelectronic package to span the unfilled air gap, the stacked bridge device
having first and second terminals soldered to first and second backside contacts, respectively.

US Pat. No. 9,594,860

ANALOG MIXED SIGNAL MODEL EQUIVALENCE CHECKING

NXP USA, INC., Austin, T...

1. A method comprising:
solving, by one or more processors included in an equivalence checking system, a difference function that is based upon a
first digital section included in a first mixed signal model and a second digital section included in a second mixed signal
model, the solving resulting in a digital equivalence result;

determining whether the first mixed signal model is equivalent to the second mixed signal model based upon the digital equivalence
result and an analog equivalence verification between a first analog section included in the first mixed signal model and
a second analog section included in the second mixed signal model; and

generating, by at least one of the one or more processors, an equivalence notification based upon the determination.

US Pat. No. 9,582,320

COMPUTER SYSTEMS AND METHODS WITH RESOURCE TRANSFER HINT INSTRUCTION

NXP USA, Inc., Austin, T...

16. A method of inserting a hint instruction into a plurality of instructions executable by a processor corresponding to a
task, comprising:
identifying a resource transfer instruction within the plurality of instructions, wherein execution of the resource transfer
instructions causes a transfer from a current resource to a new resource;

identifying a window of instructions preceding the resource transfer instruction whose predicted execution time is within
an amount of time required to perform a load of task context information for a context switch; and

combining a hint instruction with the window of instructions, wherein the hint instruction, upon execution by the processor,
provides an indication that the resource transfer instruction will be executed subsequent to the hint instruction.

US Pat. No. 9,584,046

GATE DRIVE CIRCUIT AND A METHOD FOR CONTROLLING A POWER TRANSISTOR

NXP USA, Inc., Austin, T...

14. A power inverter comprising:
a first capacitor, a first terminal of the first capacitor-being electrically coupled to a gate terminal of a power transistor,
a first switch being arranged between a second terminal of the first capacitor and a first predetermined voltage,
a measurement circuit for measuring a differential voltage across the first capacitor,
a reference source for generating a reference voltage,
a gate drive circuit being configured to pre-charge the first capacitor to obtain a second predetermined voltage across the
first capacitor, the gate drive circuit being further configured to arrange the first switch in an on state for turning on
the power transistor to electrically couple the first predetermined voltage to the second terminal of the first capacitor
being pre-charged at the second predetermined voltage, the measurement circuit being configured to arrange the first switch
in an off state when the differential voltage across the first capacitor has changed with respect to the second predetermined
voltage by the reference voltage,

the power inverter further comprising a further power transistor, a gate terminal of the further power transistor electrically
coupled to a further gate drive circuit, an emitter or source terminal of the further power transistor being electrically
coupled to the collector terminal of the power transistor and a collector or drain terminal of the further power transistor
being electrically coupled to a supply voltage.

US Pat. No. 9,584,354

RADIO SIGNAL DECODING AND DECODER

NXP USA, INC., Austin, T...

1. A radio signal decoder comprising:
a receiver configured to receive a digitized radio signal, the radio signal having modulated subcarrier frequencies encoding
digital information, wherein the modulated subcarrier frequencies include a first set of subcarrier frequencies with a first
subcarrier spacing and a second set of subcarrier frequencies with a second subcarrier spacing, the second subcarrier spacing
different from the first subcarrier spacing;

a first transformer configured with the first subcarrier spacing and configured to transform the digitized radio signal from
a time domain into a frequency domain, the first transformer producing a first transformed signal having a value for each
frequency in the first set of subcarrier frequencies;

a first decoder configured to reconstruct digital information from output of the first transformer;
an inverse transformer configured to:
receive as input at least a part of the output of the first transformer representing a frequency range overlapping the second
set of subcarrier frequencies, and

transform the input from the frequency domain back to the time domain;
a second transformer configured with the second subcarrier spacing and configured to transform the output of the inverse transformer
from the time domain to a frequency domain, the second transformer producing a second transformed signal having a value for
each frequency in the second set;

a second decoder reconstructing digital information from output of the second transformer.

US Pat. No. 9,583,603

ESD PROTECTION WITH INTEGRATED LDMOS TRIGGERING JUNCTION

NXP USA, INC., Austin, T...

1. An electronic apparatus comprising an electrostatic discharge (ESD) protection device, the ESD protection device comprising:
a semiconductor substrate;
a base region in the semiconductor substrate and having a first conductivity type;
an emitter region in the base region and having a second conductivity type;
a collector region in the semiconductor substrate, spaced from the base region, and having the second conductivity type;
a breakdown trigger region doped to effectively have the second conductivity type, and disposed laterally between the base
region and the collector region to define a junction across which breakdown occurs to trigger the ESD protection device to
shunt ESD discharge current; and

a gate structure supported by the semiconductor substrate over the breakdown trigger region and electrically tied via an interconnect
to the base region and the emitter region;

wherein the lateral width of the breakdown trigger region is configured to establish a voltage level at which the breakdown
occurs.

US Pat. No. 9,575,118

SEMICONDUCTOR DEVICE COMPRISING AN OUTPUT DRIVER CIRCUITRY, A PACKAGED SEMICONDUCTOR DEVICE AND ASSOCIATED METHODS

NXP USA, Inc., Austin, T...

1. A semiconductor device for use in a package comprising an output pin and a reference pin, the semiconductor device comprising
a plurality of output pads bondable to the output pin, a plurality of reference pads bondable to the reference pin, and an
output driver circuitry having a control terminal for receiving a control signal and arranged to drive the plurality of output
pads relative to the plurality of reference pads in dependence on the control signal,
the output driver circuitry comprising a plurality of driver sections and a selection circuitry,
each driver section having a driver control terminal for receiving a section control signal, a section reference terminal
and a section output terminal, the section reference terminal connected to a single reference pad from the plurality of reference
pads, the section output terminal connected to a single output pad from the plurality of output pads, the driver section being
arranged to drive the single output pad relative to the single reference pad in dependence on the section control signal,

the plurality of reference pads being connected in a one-to-one relationship to the plurality of driver sections,
the plurality of output pads being connected in a one-to-one relationship to the plurality of driver sections,
the selection circuitry having at least one selection input terminal for receiving at least one selection signal, a selection
control terminal connected to the control terminal for receiving the control signal, a plurality of selection output terminals,
each selection output terminal of the plurality of selection output terminals being connected to a respective section control
terminal of a respective driver section of the plurality of driver sections and arranged to provide respective section control
signals to each of the section control terminals of the plurality of driver sections in dependence on the at least one selection
signal and the control signal.

US Pat. No. 9,576,471

RADIO FREQUENCY REMOTE CONTROLLER DEVICE, INTEGRATED CIRCUIT AND METHOD FOR SELECTING AT LEAST ONE DEVICE TO BE CONTROLLED

NXP USA, INC., Austin, T...

1. A radio frequency (RF) remote controller device comprising:
radio frequency (RF) circuitry operably coupled to an antenna arrangement and arranged to transmit and receive RF signals
to and from a plurality of controllable devices;

a memory element for storing a list of device types for which directivity is, or is not, required; and
signal processing logic operably coupled to the RF circuitry and to a user interface;
wherein:
the antenna arrangement is arranged to comprise a directivity characteristic; and
the signal processing logic upon receipt of a command input from the user interface, is arranged to:
determine at least one link quality value that is at least partly dependent upon the directivity characteristic for at least
one controllable device of the plurality of controllable devices; and

select the at least one controllable device for remote controlling based on the determined at least one link quality value
and a determination that the at least one controllable device is of a type of certain predefined types according to the list
of device types.

US Pat. No. 9,575,024

DECODER FOR DETERMINING A SUBSTANCE OR MATERIAL STRUCTURE OF A DETECTED OBJECT BASED ON SIGNALS OF A CAPACITIVE SENSOR AND METHOD FOR DETERMINING A SUBSTANCE OR MATERIAL STRUCTURE OF A DETECTED OBJECT BASED ON SIGNALS OF A CAPACITI

NXP USA, INC., Austin, T...

1. A decoder unit for determining a material of a detected object based on a signal from a capacitive sensor, the decoder
unit comprising:
a distribution determination device that determines a detected distribution relation based on the signal;
a comparison device that compares the detected distribution relation with a first predetermined distribution relation of a
plurality of predetermined distribution relations and with a second predetermined distribution relation of the plurality of
predetermined distribution relations, the first predetermined distribution relation being associated with a first material
and the second predetermined distribution relation being associated with a second material; and

an output device that indicates the presence of the first material and indicates a first detected object as accidentally contacting
the capacitive sensor when the detected distribution relation matches the first predetermined distribution relation, and that
indicates the presence of the second material and indicates a second detected object as intentionally contacting the capacitive
sensor when the detected distribution relation matches the second predetermined distribution relation.

US Pat. No. 9,570,548

DEEP TRENCH ISOLATION STRUCTURES AND SYSTEMS AND METHODS INCLUDING THE SAME

NXP USA, INC., Austin, T...

1. A semiconductor device, comprising:
a semiconductor body of a first conductivity type, the semiconductor body having a body dopant concentration and a body surface;
a device region extending into the semiconductor body from the body surface; and
a deep trench isolation structure configured to electrically isolate the device region from other device regions that extend
within the semiconductor body, the deep trench isolation structure comprising

(i) an isolation trench extending into the semiconductor body from the body surface and extending around the device region,
(ii) a dielectric material extending within the isolation trench,
(iii) a first semiconducting region of the first conductivity type having a first dopant concentration, wherein the device
region separates the first semiconducting region from the body surface, and

(iv) a second semiconducting region of the first conductivity type having a second dopant concentration and separating the
device region from the first semiconducting region,

wherein the first dopant concentration is greater than the body dopant concentration, and further wherein the first dopant
concentration is greater than the second dopant concentration.

US Pat. No. 9,562,825

SHOCK SENSOR WITH LATCH MECHANISM AND METHOD OF SHOCK DETECTION

NXP USA, Inc., Austin, T...

11. A micromechanical shock sensor comprising:
a proof mass coupled to a surface of a substrate and configured for planar movement relative to said substrate when said proof
mass is subjected to a force of at least a threshold magnitude;

a projection element extending laterally from said proof mass, said projection element including a first strike surface and
a first latch surface opposing said first strike surface;

a latch mechanism having a latch spring attached to said surface and a latch tip extending from a movable end of said latch
spring, said latch tip including a second strike surface and a second latch surface opposing said second strike surface, said
second strike surface facing said first strike surface prior to movement of said proof mass; and

a retention anchor attached to said surface and located proximate said latch tip, wherein movement of said proof mass in response
to said force causes said latch tip to become retained between said projection element and said retention anchor to place
said shock sensor in a latched state, and said second latch surface abuts said first latch surface when said shock sensor
is in said latched state, wherein said second latch surface comprises an indent region and said first latch surface resides
in said indent region when said shock sensor is in said latched state.

US Pat. No. 10,031,825

ELECTRONIC DEVICE HAVING MULTIPLEXED INPUT/OUTPUT TERMINALS

NXP USA, Inc., Austin, T...

1. An electronic device, the device comprising:at least one terminal arrangement to interface internal signals in the electronic device to external signals of other electronic devices via a terminal,
the terminal arrangement comprising the terminal, a terminal driver and a terminal control circuit,
the terminal control circuit including a storage unit to store pad multiplexor configuration data, a pad multiplexor, and a terminal checker including a first section coupled between a storage unit and a pad multiplexor and a second section coupled between the pad multiplexor and pads of the electronic device, the terminal control circuit configured to receive a terminal configuration, the terminal configuration defining properties of the terminal driver,
the terminal driver being coupled to the terminal control circuit configured to set an actual configuration of the terminal driver according to the terminal configuration, and the electronic device, the terminal checker configured to
compare the actual configuration to at least one check configuration, wherein the comparison between the actual configuration and the check configuration includes: the terminal checker to compare control signals being routed to a pad multiplexor to control signals defined in the check configuration, and to compare electrical properties of pads of the terminal arrangement to electrical properties of the pads defined in the check configuration, the check configuration defining a configuration of the terminal driver that is either allowed or not allowed,
and when the configuration of the terminal driver is a not allowed configuration, set the actual configuration to a default configuration.

US Pat. No. 9,787,079

OVER-CURRENT PROTECTION DEVICE

NXP USA, INC., Austin, T...

1. An over-current protection circuit comprising:
a supply current input;
a supply current output;
a current supply switch comprising
a first switch terminal coupled to the supply current input,
a second switch terminal coupled to the supply current output,
a third switch terminal coupled to a gate driver, and
a high electron mobility transistor (HEMT) comprising a first current electrode coupled to the first switch terminal, a second
current electrode coupled to the second switch terminal, and a control electrode coupled to the third switch terminal, wherein

the current supply switch provides an on-state, in which the current supply switch provides a conductive connection between
the first switch terminal and the second switch terminal, and an off-state, in which the current supply switch interrupts
the conductive connection between the first switch terminal and the second switch terminal wherein the HEMT is a normally-on
transistor;

a sense transistor comprising a first current electrode coupled to the first switch terminal, a second current electrode,
and a control electrode coupled to the third switch terminal; and

a switch control device including:
an operational amplifier having a first input terminal coupled to the second current electrode of the sense transistor, a
second input terminal coupled to the second switch terminal, and an output terminal:

a comparator transistor having a first current electrode coupled to the in put terminal of the operational amplifier, a second
current electrode, and a control electrode coupled to the output terminal of the operational amplifier; and

a comparator having an input terminal coupled to the second current electrode of the comparator transistor, and an output
terminal coupled to the gate driver;

the switch control device arranged to control the current supply switch of an over-current protection device based on level
of a supply current provided to the over-current protection circuit, and to control the current supply switch into the off-state
if the supply current is larger than a limit current, and wherein the over-current protection circuit provides an instant
reaction to the supply current being larger than the limit current based on the HEMT being the normally-on transistor; and

the over-current protection circuit is configured to receive the supply current via the supply current input and to provide
the supply current via the supply current output if the current supply switch is in the on-state.

US Pat. No. 9,748,964

MULTI-CHANNEL ANALOG TO DIGITAL CONVERTER

NXP USA, Inc., Austin, T...

1. A multi-channel analog to digital converter (ADC) comprising:
a first multiplying digital to analog converter (MDAC) comprising:
a first switched capacitor circuit path coupled between a first input node and an input node of a first gain element,
a second switched capacitor circuit path coupled between a second input node and the input node of the first gain element;
a second MDAC comprising:
a third switched capacitor circuit path coupled between a third input node and an input node of a second gain element,
a fourth switched capacitor circuit path coupled between a fourth input node and the input node of the second gain element;
a third MDAC comprising:
a fifth switched capacitor circuit path coupled between a fifth input node and an input node of a third gain element,
a sixth switched capacitor circuit path coupled between the fifth input node and the input node of the third gain element,
a seventh switched capacitor circuit path coupled between a sixth input node and the input node of the third gain element,
a eighth switched capacitor circuit path coupled between the sixth input node and the input node of the third gain element;
wherein the fifth input node is coupled to an output node of the first gain element, and the sixth input node is coupled to
an output node of the second gain element.

US Pat. No. 9,735,614

SUPPLY-SWITCHING SYSTEM

NXP USA, INC., Austin, T...

1. A supply-selection circuit for selecting a higher of a first voltage generated by a main supply and a second voltage generated
by a battery, comprising:
a first transistor having a drain terminal connected to body and gate terminals thereof, and a source terminal connected to
the main supply for receiving the first voltage, wherein the drain terminal thereof outputs the first voltage when the first
voltage is higher than the second voltage;

a second transistor having a drain terminal connected to body and gate terminals thereof, and a source terminal connected
to the main supply for receiving the first voltage; and

a third transistor having a drain terminal connected to the drain terminal of the first transistor, a body terminal connected
to the drain terminal thereof, a gate terminal connected to the body terminal of the second transistor, and a source terminal
connected to the battery for receiving the second voltage, wherein the drain terminal thereof outputs the second voltage when
the second voltage is higher than the first voltage.

US Pat. No. 9,659,622

SENSE AMPLIFIER

NXP USA, INC., Austin, T...

1. Non-volatile memory (NVM) circuitry comprising:
a non-volatile (NV) element coupled to a first current electrode of a force path transistor and to a first current electrode
of a sense path transistor, wherein a second current electrode of the force path transistor is coupled to a first force node
and a second current electrode of the sense path transistor is coupled to a first sense node;

a reference cell coupled to a first current electrode of a reference force path transistor and to a first current electrode
of a reference sense path transistor, wherein a second current electrode of the reference force path transistor is coupled
a second force node and a second current electrode of the reference sense path transistor is coupled to a second sense node;

a first capacitive element having a first electrode and having a second electrode coupled to a first input of an amplifier
stage; and

a second capacitive element having a first electrode and having a second electrode coupled to a second input of the amplifier
stage,

wherein the NVM circuitry is configured to, during a first phase of a sensing operation, couple the first sense node to the
first electrode of the first capacitive element and couple the second sense node to the first electrode of the second capacitive
element, and during a second phase of the sensing operation, couple the first sense node to the first electrode of the second
capacitive element and couple the second sense node to the first electrode of the first capacitive element.

US Pat. No. 9,666,671

SEMICONDUCTOR DEVICE WITH COMPOSITE DRIFT REGION AND RELATED FABRICATION METHOD

NXP USA, Inc., Austin, T...

1. A device comprising:
a semiconductor substrate having a surface;
a gate structure supported by the semiconductor substrate at the surface;
a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed proximate the
gate structure;

source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed
on the body region;

an isolation region disposed in the semiconductor substrate between the body region and the drain region; and
a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers
from the source region drift to reach the drain region after passing through the channel;

wherein the composite drift region comprises a first, channel-side section adjacent the channel, a second, drain-side section
adjacent the drain region, and a third section disposed between the first and second sections;

wherein the first and second sections have a dopant concentration level that decreases by an order of magnitude or more between
upper and lower boundaries of the first and second sections;

wherein the first and second sections have a lower dopant concentration level than the third section at a first depth, relative
to the surface of the semiconductor substrate, deeper than a lower boundary of the isolation region; and

wherein the first and second sections have a higher dopant concentration level than the third section at a second depth, relative
to the surface of the semiconductor substrate, shallower than the lower boundary of the isolation region.

US Pat. No. 9,628,005

DEVICE FOR DETERMINING A POSITION OF A ROTOR OF AN ELECTRIC MOTOR

NXP USA, INC., Austin, T...

1. A device for determining a rotor position in a polyphase electric motor having stator coils comprising three phases, the
device comprising:
a power control unit configured to apply drive voltages on each of the three phases, wherein the drive voltages comprise drive
pulses alternating between a zero voltage and a supply voltage according to a pulse width modulation scheme so as to generate
sinusoidal phase currents in each of the phases for synchronously driving the motor;

a measurement unit arranged for measuring a voltage value on a respective phase by
determining a zero-crossing interval where the respective phase current is around zero,
disconnecting the respective phase from the respective drive voltage during the zero-crossing interval,
determining at least one measurement interval in the zero-crossing interval where the drive voltage of a first other phase
is the supply voltage and the drive voltage of a second other phase is the zero voltage, and

measuring the voltage value during the measurement interval;
a position unit configured to determine the rotor position based on the voltage value,
wherein the measurement unit is arranged for initiating the zero-crossing interval based on detecting the respective phase
current being below a predetermined threshold.

US Pat. No. 9,626,279

DEBUG METHOD AND DEVICE FOR PROVIDING INDEXED TRACE MESSAGES

NXP USA, INC., Austin, T...

1. A method comprising:
determining if a branch of a conditional branch instruction has been taken; and
in response to the branch having not been taken, clearing a first flag of an instruction flow history flag buffer (IFFB),
otherwise

in response to the branch having been taken, setting the first flag, and generating a trace address message comprising a destination
address of the branch and an index identifying a location of the first flag of the IFFB.

US Pat. No. 9,620,604

STRUCTURES FOR SPLIT GATE MEMORY CELL SCALING WITH MERGED CONTROL GATES

NXP USA, INC., Austin, T...

1. A memory device having a first memory cell and a second memory cell in and over a substrate, comprising:
a first active region in the substrate including a first portion and a second portion;
a first doped region in the first active region, the first doped region between and abutting the first portion and the second
portion of the first active region, and a top surface of the first active region is substantially coplanar with a top surface
of the first doped region;

a control gate over the first doped region and extending past the first doped region over the first portion of the first active
region on a first side of the first doped region and extending past the first doped region over the second portion of the
first active region on a second side of the first doped region, wherein the first side is opposite the second side;

a charge storage layer between the control gate and the first active region, and extending past the first doped region over
the first portion of the first active region on the first side of the first doped region and extending past the first doped
region over the second portion of the first active region on the second side of the first doped region;

a first select gate over the first active region on the first side of the first doped region and adjacent to the control gate,
the first select gate spaced apart from the first doped region by the first portion of the first active region; and

a second select gate over the first active region on the second side of the first doped region and adjacent to the control
gate, the second select gate spaced apart from the first doped region by the second portion of the first active region.

US Pat. No. 9,618,952

CURRENT GENERATOR CIRCUIT AND METHOD OF CALIBRATION THEREOF

NXP USA, Inc., Austin, T...

1. A current generator circuit comprising:
at least one current generation component arranged to generate an output current of the current generator circuit;
at least one absolute current calibration component arranged to enable calibration of an absolute current value of the output
current; and

at least one temperature coefficient calibration component arranged to enable calibration of a temperature coefficient characteristic
of the output current, the at least one temperature coefficient calibration component being further arranged to be in a passive
state at a reference temperature.

US Pat. No. 9,618,988

METHOD AND APPARATUS FOR MANAGING A THERMAL BUDGET OF AT LEAST A PART OF A PROCESSING SYSTEM

NXP USA, INC., Austin, T...

1. A method of managing a thermal budget for at least a part of a processing system, the method comprising:
in response to detecting, by a processing core of the processing system, a use case event;
scaling, by the processing core, thermal curve data, stored at a storage location of a memory of the processing system, based
on a current use case scenario and one or more current environment parameters for the at least part of the processing system;

determining, by the processing core, a thermal budget violation time window for the current use case scenario of the at least
part of the processing system based on the scaled thermal curve data; and

managing the thermal budget for the at least part of the processing system based on the determined thermal budget violation
time window.

US Pat. No. 9,614,041

MULTI-GATE SEMICONDUCTOR DEVICES WITH IMPROVED HOT-CARRIER INJECTION IMMUNITY

NXP USA, Inc., Austin, T...

1. A semiconductor device comprising:
a substrate having a first dopant type;
a first gate electrode formed over the substrate;
a second gate electrode formed over the substrate and spatially separated from the first gate electrode;
a first region of a second dopant type formed in the substrate between and partially underlying the first and second gate
electrodes, the first region having a first dopant concentration;

a first pocket of the first dopant type formed in the first region, the pocket being spaced apart from the first and second
gate electrodes and having a second dopant concentration;

a source region formed in the semiconductor substrate on an opposing side of the first gate electrode from the first region,
the source region having the second dopant type; and

a drain region formed in the semiconductor substrate on an opposing side of the second gate electrode from the first region,
the drain region having the second dopant type; and

a second pocket of the first dopant type formed in the drain region, the second pocket being adjacent to and spaced apart
from the second electrode, the second pocket having a third dopant concentration.

US Pat. No. 9,590,058

METHODS AND STRUCTURES FOR A SPLIT GATE MEMORY CELL STRUCTURE

NXP USA, INC., Austin, T...

1. A method for forming a split gate memory cell structure using a semiconductor substrate, the method comprising:
forming a gate stack over the semiconductor substrate, wherein the gate stack has a conductive portion with a top surface
and a dielectric portion having a bottom surface on the top surface of the conductive portion, the gate stack having a first
sidewall along a side of the conductive portion and a side of the dielectric portion;

forming a charge storage layer over the substrate including over the gate stack and along the first sidewall;
forming a conductive layer over the charge storage layer;
etching the conductive layer to leave a first conductive spacer along the first sidewall, wherein a top of the first conductive
spacer is above the top surface of the conductive portion and below the top of the dielectric portion;

forming a first sidewall spacer from a lower surface of the first conductive spacer to a first height below the top of the
first conductive spacer and a second sidewall spacer along the first sidewall between the top of the first conductive spacer
and the top surface of the dielectric portion wherein a portion of the second sidewall spacer is directly above the conductive
spacer; and

siliciding the first conductive spacer between the first sidewall spacer and the second sidewall spacer.

US Pat. No. 9,589,908

METHODS TO IMPROVE BGA PACKAGE ISOLATION IN RADIO FREQUENCY AND MILLIMETER WAVE PRODUCTS

NXP USA, INC., Austin, T...

1. An electronic device comprising:
a substrate comprising a first plurality of conductive interconnect paths extending between first and second opposed surfaces
of the substrate;

an integrated circuit die affixed to the first surface of the substrate for electrical connection to the plurality of conductive
interconnect paths; and

an array of conductors affixed to the second surface of the substrate for electrical connection to the plurality of conductive
interconnect paths, said array comprising a signal feed conductor and an array of shielding conductors surrounding the signal
feed conductor.

US Pat. No. 9,589,967

FAST PROGRAMMING ANTIFUSE AND METHOD OF MANUFACTURE

NXP USA, INC., Austin, T...

1. An antifuse element comprising:
a substrate material;
an isolation trench formed in the substrate material, the isolation trench having a first side and a second side opposite
the first side;

an electrode positioned above the substrate material and having at least a portion proximate to the first side of the isolation
trench; and

an insulating layer disposed between the electrode and the substrate material such that voltage of a threshold applied between
the electrode and the substrate material causes a rupture in the insulating layer and creates a current path from the electrode
through the insulating layer and under the isolation trench to the substrate material proximate the second side of the isolation
trench;

a first contact electrically coupled to the electrode and a second contact electrically coupled to the substrate material
proximate the second side of the isolation trench, and wherein the current path is created between the first contact and the
second contact.

US Pat. No. 9,590,757

EQUALIZER FOR JOINT-EQUALIZATION

NXP USA, INC., Austin, T...

1. An equalizer for equalizing a composite signal originating from a given number L of simultaneous data streams, hereinafter
layers, able to be received over a communication channel, on a given number M of antennas, at one or more radio units, in
a wireless communication system, the equalizer comprising:
a processing unit such as a processor; and,
a memory unit operably coupled to the processing unit;
wherein the processing unit is arranged to produce an estimate data representing a transmitted signal vector x of size L, associated with an estimation of a transmitted signal received at the one or more radio units, based on:
a received signal data representing a received signal vector Y of size N×1, associated with the received composite signal;
a channel response estimate data representing a channel estimation matrix H of size N×L, associated with a channel response estimation of the communication channel;
a layer covariance data representing a layer covariance matrix C of size L×L, associated with the layers able to be received
over the communication channel; and,

a noise covariance data representing a noise covariance matrix S of size N×N, associated with a noise level present at the
antennas;

wherein, when the composite signal is received on a given number N of antennas, where M is greater than N, the processing
unit is arranged to:

increase the dimension associated with the given number N of antennas, to the given number M of antennas, at one or more similar
positions with respect to Y, H and S?1, thereby producing Y_inc, H_inc and S?_inc, respectively, wherein S?1 denotes the inverse matrix of S;

add padding elements to Y_inc, H_inc and S?1_inc, at the one or more similar positions, thereby producing Y_pad, H_pad and S?1_pad, respectively; and,

produce the estimate data representing the transmitted signal vector x based on Y_pad, H_pad, C and _pad.

US Pat. No. 9,582,397

METHOD AND SYSTEM FOR OBTAINING RUN-TIME INFORMATION ASSOCIATED WITH EXECUTING AN EXECUTABLE

NXP USA, INC., Austin, T...

9. A method of generating run-time information while executing an executable, the method comprising:
receiving an object file while executing the executable;
retrieving embedded debugging information entries (DIE) from object file;
formatting the embedded DIE to have a predetermined format;
retrieving external DIE from an external memory, wherein the one or more external DIE relates to an array of registers;
formatting the external DIE to have the predetermined format;
storing the embedded DIE and the external DIE in a DIE collection in a debugging information consumer;
obtaining the run-time information from at least one or more registers, one or more variables, one or more functions, one
or more memory locations, for executing the executable, and letting the debugging information consumer retrieve run-time values
and format the run-time values according to the external debugging information entries in the debugging information entries
collection; and

presenting a visualization of the run-time values as formatted according to the external debugging information entries.

US Pat. No. 9,584,118

SUBSTRATE BIAS CIRCUIT AND METHOD FOR BIASING A SUBSTRATE

NXP USA, INC., Austin, T...

1. A substrate bias circuit comprising:
a first voltage source;
a plurality of transistors, each transistor in the plurality of transistors having a substrate terminal;
a second voltage source coupled to the substrate terminal of a first transistor in the plurality of transistors, the second
voltage source comprising a voltage regulator; and

a first diode having an anode terminal connection to the first voltage source and a cathode terminal connection to the second
voltage source.

US Pat. No. 9,573,799

MEMS DEVICE HAVING VARIABLE GAP WIDTH AND METHOD OF MANUFACTURE

NXP USA, Inc., Austin, T...

1. A microelectromechanical systems (MEMS) device comprising:
a base structure including a substrate having a first dielectric layer formed thereon, a first structural layer formed on
said first dielectric layer, and a second dielectric layer formed over said first structural layer, wherein an exposed region
of a top surface of said substrate is exposed from each of said first dielectric layer, said first structural layer, and said
second dielectric layer; and

a proof mass suspended above said base structure to yield a first gap between said proof mass and said exposed region of said
top surface of said substrate and a second gap between said proof mass and said first structural layer, a first width of said
first gap being greater than a second width of said second gap.

US Pat. No. 9,570,440

SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH AN ACTIVE DEVICE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF

NXP USA, Inc., Austin, T...

1. A method for forming a semiconductor device, the method comprising the steps of:
forming a buried layer below a top substrate surface of a semiconductor substrate having a first conductivity type, wherein
the buried layer has a second conductivity type that is different from the first conductivity type;

forming a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity
type, and an isolation structure is formed by the sinker region and the buried layer;

forming an active device in a portion of the semiconductor substrate contained by the isolation structure, wherein the active
device includes a body region of the second conductivity type and a source region of the first conductivity type formed in
the body region, and wherein the body region and the isolation structure are separated by a portion of the semiconductor substrate
having the first conductivity type; and

forming a diode circuit between the isolation structure and the body region.

US Pat. No. 9,559,097

SEMICONDUCTOR DEVICE WITH NON-ISOLATED POWER TRANSISTOR WITH INTEGRATED DIODE PROTECTION

NXP USA, Inc., Austin, T...

1. A method of fabricating a non-isolated transistor, the method comprising:
forming a device separating region of the transistor in a semiconductor substrate, the substrate having a first conductivity
type, the device separating region having a second conductivity type and defining an active area of the transistor, the second
conductivity type being different from the first conductivity type; the device separating regions extending in a vertical
orientation in the substrate but not across the active area in a lateral orientation to isolate the active area;

forming a body region of the transistor in the active area, the body region having the first conductivity type; and
forming source and drain regions of the transistor in the active area, the source region being situated on the body region,
the source and drain regions having the second conductivity type;

wherein a spacing is defined between the device separating region and the body region to establish a first breakdown voltage
lower than a second breakdown voltage in a conduction path between the source and drain regions.

US Pat. No. 9,690,897

EFFICIENT EXTRACTION FOR COLORLESS MULTI PATTERNING

NXP USA, INC., Austin, T...

1. A computer-implemented method comprising:
identifying, at a computing system, metal features in a metal layer of an integrated circuit design;
generating, at the computing system, a graph based on spacing relationships between the metal features;
predicting, at the computing system, which metal features are to be formed by a same mask in a multiple patterning lithography
process using the graph; and

generating, at the computing system, analysis data for the integrated circuit design based on the prediction of which metal
features are to be formed by the same mask.

US Pat. No. 9,651,618

ELECTRONIC DEVICE AND METHOD FOR STATE RETENTION

NXP USA, Inc., Austin, T...

1. An electronic device comprising:
a set of two or more scan chains; and
a buffer chain, wherein:
each of the scan chains has an input end and an output end, which are opposite ends of the respective scan chain, and each
of the scan chains comprises a sequence of stateful elements connected in series between the input end and the output end,
and each of the scan chains is arranged to hold a string having a length identical to a length of the respective scan chain,

the electronic device is arranged to shift the strings of the scan chains in parallel from the scan chains into a memory unit
via the respective output ends in a store operation and back from the memory unit into the respective scan chains via the
respective input ends in a restore operation, wherein the store operation and the restore operation each comprise at least
N0 elementary downstream shift operations,

the set of scan chains includes a long chain, a short chain and a detour chain, wherein the long chain has a length N0, the short chain has a length N1, where N1 is shorter than N0, and

the buffer chain has a length of K=N0?N1, and has an input end and an output end, which are opposite ends of the buffer chain, with the output end of the short chain
coupled to the input end of the buffer chain, the buffer chain is provided at least partly by the detour chain, the buffer
chain comprises the input end of the detour chain and the input end of the buffer chain is the input end of the detour chain,
wherein the electronic device further comprises a branch from the detour chain coupling the output end of the buffer chain
to the memory unit.

US Pat. No. 9,628,119

ADAPTIVE HIGH-ORDER NONLINEAR FUNCTION APPROXIMATION USING TIME-DOMAIN VOLTERRA SERIES TO PROVIDE FLEXIBLE HIGH PERFORMANCE DIGITAL PRE-DISTORTION

NXP USA, INC., Austin, T...

1. A method for predistorting an input signal to compensate for non-linearities caused to the input signal in producing an
output signal, the method comprising:
providing an input for receiving a first input signal as a plurality of signal samples, to be transmitted over a non-linear
element;

providing at least one digital predistortion block comprising a plurality of IQ predistorter cells coupled to the input, each
IQ predistorter cell comprising a lookup table (LUT) for generating an LUT output to form a plurality of LUTs, wherein the
at least one digital predistortion block is configured to apply interpolation between LUT entries for the plurality of LUTs
and generate an output signal from each of the plurality of IQ predistorter cells by adaptively modifying the first input
signal using interpolated LUT entries;

providing a combiner to combine the output signal from the plurality of IQ predistorter cells to generate the output signal
for transmission to the non-linear element;

providing a digital predistortion adaptation block coupled to the at least one digital predistortion block and configured
to apply adaptation values to each of the plurality of LUTs based on a predistortion performance of the at least one digital
predistortion block; and

providing at least one error calculation block coupled to the digital predistortion adaptation block and configured to apply
predistortion error values to the digital predistortion adaptation block, wherein providing at least one error calculation
block configured to apply adaptation values to the digital predistortion adaptation block comprises providing at least one
error calculation block configured to apply adaptation values to the plurality of LUT entries per IQ predistorter cell using
a plurality of lines of extrapolation.

US Pat. No. 9,626,170

METHOD AND COMPUTER PROGRAM PRODUCT FOR DISASSEMBLING A MIXED MACHINE CODE

NXP USA, INC., Austin, T...

1. A method for disassembling a mixed machine code, wherein the machine code is provided as a sequence of code items, the
sequence of code items comprises one or more instructions and one or more data items; and the method comprises:
storing the sequence of code items in accordance with a corresponding sequence of addresses;
executing the machine code, thereby generating an execution trace; and
partitioning the sequence of addresses into instruction address blocks and data address blocks on the basis of control data,
the control data comprising at least the execution trace.

US Pat. No. 9,620,951

OVERCURRENT PROTECTION DEVICE AND METHOD OF OPERATING A POWER SWITCH

NXP USA, Inc., Austin, T...

1. An overcurrent protection device, comprising:
a maximum-allowed-current unit configured to determine a maximum allowed current in real-time, wherein said maximum allowed
current is determined based on a selected one of a plurality of maximum allowed current profiles stored in a memory, and wherein
the selected maximum allowed current profile is based on an instantaneous level of a supply voltage, and said supply voltage
is a voltage across the overcurrent protection device and a load to be powered; and

a power switch connectable with a switch input to a voltage supply and with a switch output to said load, and configured to
provide power to said load, wherein said power switch has a conductive state and a nonconductive state, and the power switch
is arranged to assume the nonconductive state in response to an indication that a current through the power switch is exceeding
the maximum allowed current; and

a turn-on detector to communicate with the power switch, the turn-on detector to detect a turn-on event for the power switch
in response to a first edge of a pulse width modulation control signal, to trigger a first edge of a turn-on detection signal
in response to the first edge of the pulse width modulation control signal, and to trigger a second edge in the turn-on detection
signal in response to a second edge of the pulse width modulation control signal with a particular amount of delay from the
first edge of the pulse width modulation control signal being detected.

US Pat. No. 9,613,673

SENSE AMPLIFIER

NXP USA, INC., Austin, T...

1. Non-volatile memory (NVM) circuitry comprising:
a non-volatile (NV) element coupled to a first current electrode of a force path transistor and to a first current electrode
of a sense path transistor, wherein a second current electrode of the force path transistor is coupled to a first force node
and a second current electrode of the sense path transistor is coupled to a first sense node;

a reference cell coupled to a first current electrode of a reference force path transistor and to a first current electrode
of a reference sense path transistor, wherein a second current electrode of the reference force path transistor is coupled
a second force node and a second current electrode of the reference sense path transistor is coupled to a second sense node;

a first capacitive element having a first electrode and having a second electrode coupled to a first input of an amplifier
stage; and

a second capacitive element having a first electrode and having a second electrode coupled to a second input of the amplifier
stage,

wherein the NVM circuitry is configured to, during a first phase of a sensing operation, couple the first sense node to the
first electrode of the first capacitive element and couple the second sense node to the first electrode of the second capacitive
element, and during a second phase of the sensing operation, couple the first sense node to the first electrode of the second
capacitive element and couple the second sense node to the first electrode of the first capacitive element.

US Pat. No. 9,612,254

MICROELECTROMECHANICAL SYSTEMS DEVICES WITH IMPROVED LATERAL SENSITIVITY

NXP USA, Inc., Austin, T...

1. A microelectromechanical systems (MEMS) device comprising:
a substrate;
a first anchored structure fixedly coupled to the substrate;
a second anchored structure fixedly coupled to the substrate; and
a movable structure resiliently coupled to the substrate, the movable structure having an opening formed therethrough and
being positioned such that the first anchored structure is at least partially within the opening and such that the second
anchored structure is at least partially within the opening, and wherein the movable structure is in a capacitor-forming relationship
with the first anchored structure and the second anchored structure, wherein the movable structure comprises a first movable
structure finger extending only partially across the opening and a second movable structure finger extending only partially
across the opening, and wherein the first movable structure finger is positioned to move away from the first anchored structure
to decrease capacitance between the movable structure and the first anchored structure when the movable structure moves in
a first direction, and wherein the second movable structure finger is positioned to move closer to the second anchored structure
to increase capacitance between the movable structure and the second anchored structure when the movable structure moves in
the first direction, and wherein the movable structure comprises a first portion and a second portion, the second portion
being on a side of the opening opposite the first portion, and wherein the first movable structure finger extends from the
first portion, into the opening, and towards the second portion, and wherein the first anchored structure comprises a first
anchored structure finger in a capacitor-forming relationship with the first movable structure finger, and wherein the first
anchored structure finger extends from the first anchored structure towards the first portion of the movable structure, and
wherein the movable structure further comprises a third portion and a fourth portion, the fourth portion being on a side of
the opening opposite the third portion, and wherein the first anchored structure further comprises a second anchored structure
finger in a capacitor-forming relationship with the third portion of the movable structure.

US Pat. No. 9,607,981

SEMICONDUCTOR DEVICE AND DRIVER CIRCUIT WITH SOURCE AND ISOLATION STRUCTURE INTERCONNECTED THROUGH A DIODE CIRCUIT, AND METHOD OF MANUFACTURE THEREOF

NXP USA, INC., Austin, T...

1. A method for forming a semiconductor device, the method comprising the steps of:
forming a buried layer below a top substrate surface of a semiconductor substrate having a first conductivity type, wherein
the buried layer has a second conductivity type that is different from the first conductivity type;

forming a sinker region between the top substrate surface and the buried layer, wherein the sinker region has the second conductivity
type, and an isolation structure is formed by the sinker region and the buried layer;

forming an active device in a portion of the semiconductor substrate contained by the isolation structure, includes
a body region of the second conductivity type extending from the top substrate surface to a first depth,
a source region of the first conductivity type formed in the body region,
a drift region of the first conductivity type within a central portion of the active area, and
a drain region of the first conductivity type formed in the drift region; and
forming a diode circuit connected between the isolation structure and the source region.

US Pat. No. 9,589,860

ELECTRONIC DEVICES WITH SEMICONDUCTOR DIE COUPLED TO A THERMALLY CONDUCTIVE SUBSTRATE

NXP USA, INC., Austin, T...

1. An electronic device comprising:
a thermally conductive substrate;
a work piece that includes
a semiconductor die having a plurality of major surfaces including an upper surface and a lower surface, and
a sintered metallic layer applied to the lower surface of the semiconductor die; and
a thermally conductive flow layer between a lower surface of the sintered metallic layer and the thermally conductive substrate,
wherein the thermally conductive flow layer couples the work piece to the thermally conductive substrate.

US Pat. No. 9,582,281

DATA PROCESSING WITH VARIABLE OPERAND SIZE

NXP USA, INC., Austin, T...

1. A method of data processing comprising:
storing a first set of register size codes for a bank of registers obtained from a register and operand size register (ROSR);
executing a single instruction for writing a second set of register size codes for the bank of registers into the ROSR;
executing a first instruction to determine a result based on a first operand and a second operand, wherein the first operand
identifies a first register of the bank of registers, wherein a first size of the first register of the bank of registers
for the executing the first instruction is determined from a first register size code of the second set of register size codes
stored in the ROSR;

executing a second instruction to determine a result based on a third operand and a fourth operand, wherein the third operand
identifies the first register of the bank of registers, wherein the first size of the first register of the bank of registers
for the executing the second instruction is determined from the first register size code of the second set of register size
codes stored in the ROSR;

executing a third instruction to determine a result based on a fifth operand and a sixth operand, wherein the fifth operand
identifies a second register of the bank of registers, wherein a second size of the second register of the bank of registers
for the executing the third instruction is determined from a second register size code of the second set of register size
codes stored in the ROSR; and

executing a second single instruction for restoring the first set of register size codes for the bank of registers to the
ROSR.

US Pat. No. 9,576,661

SYSTEMS AND METHODS FOR SRAM WITH BACKUP NON-VOLATILE MEMORY THAT INCLUDES MTJ RESISTIVE ELEMENTS

NXP USA, Inc., Austin, T...

1. A memory device, comprising:
an SRAM cell that stores a logic state;
a first MTJ having a first terminal and a second terminal coupled to a storing node;
a second MTJ having a first terminal and a second terminal, wherein the first terminal of the second MTJ is coupled to the
storing node, and

wherein the first and second MTJs are characterized as being programmed to a first resistance state by flowing current from
the first terminal to the second terminal and to a second resistance state, different from the first resistance state, by
flowing current from the second terminal to the first terminal;

a storing circuit coupled to the storing node, the SRAM cell, and a non-volatile word line, wherein the storing circuit couples
the logic state of the SRAM cell to the storing node during a store mode, wherein the storing circuit comprises:

a first P channel transistor having a control electrode coupled to a complementary non-volatile word line;
a second P channel transistor having a control electrode coupled to the SRAM cell;
a first N channel transistor having a control electrode coupled to the non-volatile word line; and
a second N channel transistor having a control electrode coupled to the SRAM cell;
wherein:
the first and second P channel transistors are coupled in series between a positive power supply terminal and the storing
node; and

the first and second N channel transistors are coupled in series between a negative power supply terminal and the storing
node;

wherein, during the store mode, the logic state of the SRAM cell is stored in the first and second MTJs by applying a storing
voltage between the first terminal of the first MTJ and the second terminal of the second MTJ of a first polarity during a
first time period of a store operation and a second polarity during a second time period of the store operation.

US Pat. No. 9,558,800

NON-VOLATILE RANDOM ACCESS MEMORY (NVRAM)

NXP USA, Inc., Austin, T...

1. A non-volatile memory device comprising:
an array of non-volatile memory cells, wherein a memory cell in the array of non-volatile memory cells includes:
a first resistive element including a first terminal and a second terminal;
a second resistive element including a first terminal and a second terminal; and
a select transistor including a gate electrode coupled to a word line, a first current electrode coupled to the first terminal
of the first resistive element and the first terminal of the second resistive element, and a second current electrode coupled
to a bit line, wherein the second terminal of the first resistive element is coupled to a first source line, and the second
terminal of the second resistive element is coupled to a second source line;

a first segmentation transistor including a first current electrode coupled to the first source line, a second current electrode
coupled to a global source line, and a control electrode coupled to a first local source line enable signal, wherein the first
segmentation transistor couples the first source line to the global source line when the first local source line enable signal
is set to place the first segmentation transistor in a conductive mode.

US Pat. No. 9,559,198

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE THEREFOR

NXP USA, Inc., Austin, T...

1. A bi-directional trench field effect power transistor, comprising:
a substrate with a substrate top surface;
a layer stack extending over the substrate top surface, a first vertical trench and a second vertical trench being present
in the layer stack, each of said first and second vertical trenches extending in a vertical direction from a top layer of
the layer stack towards the substrate;

a first current terminal and a second current terminal, the first current terminal being situated in said vertical direction
below the second current terminal and the second current terminal being situated on or above the top layer; and

an electrical path which can be selectively enabled or disabled to allow current to flow in a first direction or a second
direction, opposite to the first direction, between the first current terminal and the second current terminal, the electrical
path comprising:

a body extending laterally between the first and second vertical trenches and vertically between said first current terminal
and said second current terminal;

a first drift region extending, in said vertical direction, between the body and the first current terminal;
a second drift region extending, in said vertical direction, between the body and the second current terminal;
wherein the first vertical trench and the second vertical trench have the same of option (a) and/or (b);
option (a) being:
the first and second vertical trenches extend, in said vertical direction, from said top layer beyond an upper boundary of
the first drift region, and in a lateral direction parallel to the substrate top-surface electrically isolate, and define,
the first drift region;

option (b) being: each of said first and second vertical trenches comprising:
a gate electrode in an first part of the vertical trench, the gate electrode being electrically coupled to the body, for forming,
when a suitable voltage is applied to the gate, a vertical channel in the body through which a current can flow from the first
drift region to the second drift region or vice versa;

a lower shield plate, the shield plate being situated in a lower part of the trench, the lower part being closer to the substrate
than the first part, for generating an accumulation layer in the first drift region when the lower shield plate is biased
with respect to the first current terminal in a first polarity and locally reducing the electrical field density when the
lower shield plate is biased with respect to the first current terminal in a second polarity; and

a body-side vertical sidewall, and another vertical sidewall facing the body-side vertical sidewall, of which at least the
body-side vertical sidewall is covered with a dielectric which separates the gate electrode and the shield plate from the
body-side vertical sidewall, the dielectric being thicker in the first part than in the lower part.

US Pat. No. 9,974,174

PACKAGE TO BOARD INTERCONNECT STRUCTURE WITH BUILT-IN REFERENCE PLANE STRUCTURE

NXP USA, Inc., Austin, T...

1. An interconnect structure comprising:a reference plane structure having a first major surface and a second major surface opposite the first major surface, the reference plane structure including a plurality of through holes from the first major surface to the second major surface;
a plurality of conductive columns, each conductive column positioned within a through hole;
a plurality of isolation structures, each isolation structure fills an annular region within the through hole between each conductive column and surrounding portion of the reference plane structure; and
a solder mask over at least a portion of the first major surface of the reference plane structure, wherein
the solder mask comprises a first plurality of openings, each of the first plurality of openings aligned to a top surface of each conductive column to define first electrical contact areas for the conductive columns, and
the solder mask further comprises a second plurality of openings, each of the second plurality of openings positioned over a portion of the first major surface of the reference plane structure to define second electrical contact areas for the reference plane structure.

US Pat. No. 9,720,051

SENSOR PACKAGE INCLUDING A MAGNETIC FIELD SENSOR AND A CONTINUOUS COIL STRUCTURE FOR ENABLING Z-AXIS SELF-TEST CAPABILITY

NXP USA, Inc., Austin, T...

1. A sensor package comprising:
a magnetic field sensor, said magnetic field sensor comprising in-plane sense elements located in a plane of said magnetic
field sensor and configured to detect a magnetic field oriented perpendicular to said plane, wherein all of said in-plane
sense elements are located within an area of said magnetic field sensor;

a continuous coil structure surrounding said area occupied by said in-plane sense elements such that an entirety of said continuous
coil structure is laterally displaced outside of said area;

circuitry coupled to said continuous coil structure, said circuitry being configured to provide an electric current to said
continuous coil structure to apply a self-test magnetic field to be sensed by said in-plane sense elements, wherein a vector
component of said self-test magnetic field is oriented approximately perpendicular to said plane of said magnetic field sensor;
and

at least one flux guide configured to direct said vector component of said self-test magnetic field into said plane.

US Pat. No. 9,692,387

BALUN TRANSFORMER

NXP USA, INC., Austin, T...

1. A balun for transforming signals between an unbalanced impedance and a balanced impedance, comprising:
a stack of at least an electrically conductive plate, and a dielectric layer having a first side and a second side opposite
to the first side;

a first electrically conductive line comprising a first end and a second end, arranged on the dielectric layer at the first
side of the dielectric layer;

a second electrically conductive line comprising a third end and a fourth end, arranged on the dielectric layer at the second
side of the dielectric layer such that the first electrically conductive line substantially overlaps the second electrically
conductive line; and

a micro strip line comprising a fifth end electrically coupled to the third end and a sixth end electrically coupled to the
electrically conductive plate; wherein

the electrically conductive plate is arranged on the dielectric layer at the second side,
the first end is electrically coupled to the balanced impedance, the second end is electrically coupled to the electrically
conductive plate, the third end is electrically coupled to the balanced impedance, the fourth end to the unbalanced terminal,
and

the electrically conductive plate is hollowed in at least a region corresponding to a portion of an overlap area of the first
electrically conductive line and second electrically conductive line.

US Pat. No. 9,654,000

BUCK CONVERTER AND METHOD OF OPERATING A BUCK CONVERTER

NXP USA, Inc., Austin, T...

1. A buck converter having an output node and a ground node, wherein a load is connected or connectable between the output
node and the ground node and the buck converter is arranged to drive an output current I_out through the output node, thereby
generating an output voltage V_out in the output node; the buck converter comprises:
a current control unit arranged to control the output current I_out in dependence on a control voltage V_ctl provided at a
control node; and

a voltage control unit arranged to provide the control voltage V_ctl and comprising:
an integrator unit arranged to control the control voltage V_ctl in dependence on a time integral of a difference between
the output voltage V_out and a reference voltage V_ref;

at least one of an overshoot detector arranged to detect an overshoot of the output voltage V_out, and an undershoot detector
arranged to detect an undershoot of the output voltage V_out; and

a current source connected to the control node and arranged to pull a current of amplitude I_pull from the control node in
response to the overshoot detector detecting an overshoot of the output voltage V_out, or arranged to push a current of amplitude
I_push to the control node in response to the undershoot detector detecting an undershoot of the output voltage V_out, or
both, wherein

I_pull=C_int*(V_out?V_gnd)/L/? and/or

I_push=?C_int*(V_in?V_out)/L/?
wherein ? is a voltage-to-current ratio of a switcher unit of the current control unit, V_in is a supply voltage, V_gnd is
a ground voltage, L is an internal inductance of the current control unit, and C_int is an internal capacitance of the integrator
unit.

US Pat. No. 9,652,430

CONFIGURABLE SERIAL AND PULSE WIDTH MODULATION INTERFACE

NXP USA, Inc., Austin, T...

1. A reconfigurable register device, comprising:
an arrangement of storage elements,
wherein the storage elements are arranged sequentially in a chain structure,
wherein each of the storage elements is configured for storing a state of a binary signal;
a combinatorial logic circuitry connectable to the arrangement of storage elements, wherein the combinatorial logic circuitry
is configured to enable the arrangement of storage elements to form a binary synchronous counter;

a bypass logic circuitry connectable to the arrangement of storage elements, wherein the bypass logic circuitry is configured
to enable the arrangement of storage elements to form a serial shift register; and

a switching circuitry having a mode signal input terminal for receiving a mode signal indicative of at least one of a counter
mode and a shift register mode, wherein the switching circuitry is configured to selectively connect the arrangement of storage
elements to the combinatorial logic circuitry if the mode signal indicates the counter mode, and to selectively connect the
arrangement of storage elements to the bypass logic circuitry if the mode signal indicates the shift register mode;

a buffer comprising a number of storage cells corresponding to the number of storage elements in the arrangement, wherein
each of the storage cells is configured for storing a state of a binary signal, the buffer is connected to the arrangement
of storage elements and is configured to store the state of each storage element of the arrangement in a respective storage
cell of the buffer; and

a control logic circuitry configured to load of the states of the storage elements into the respective storage cells.

US Pat. No. 9,652,577

INTEGRATED CIRCUIT DESIGN USING PRE-MARKED CIRCUIT ELEMENT OBJECT LIBRARY

NXP USA, Inc., Austin, T...

1. A method of utilizing a pre-marked circuit element object library to create an integrated circuit, the method comprising:
inserting a first circuit element object into a schematic design, wherein the first circuit element object comprises a plurality
of first terminals, and wherein each of the first terminals has one of a plurality of first pre-assigned voltage values;

connecting each of the first terminals to one or more second terminals, wherein each of the one or more second terminals correspond
to one or more second circuit element objects;

generating a layout design from the schematic design in response to determining that the first pre-assigned voltage value
of each of the first terminals matches a second pre-assigned voltage value of the one or more second terminals to which it
is connected;

determining whether the layout design passes or fails at least one of the one or more verification tests;
replacing the first circuit element object with a third circuit element object in the layout design, in responses to a determination
that the layout design fails the at least one of the one or more verification tests, wherein the third circuit element object
comprises at least one of a plurality of third pre-assigned voltage values that is different than at least one of the plurality
of first pre-assigned voltage values;

generating mask layer data in response to a determination that the layout design passes the one or more verification tests,
wherein the mask layer data is configured to generate a plurality of masks for construction of an integrated circuit corresponding
to the schematic design.

US Pat. No. 9,641,274

SNR ESTIMATION FOR SOUNDING SIGNALS

NXP USA, INC., Austin, T...

8. A method of estimating a Signal to Noise Ratio, SNR, of a first sounding signal associated with a first user, the first
sounding signal being transmitted along with a second sounding signal associated with a second user, over a wide channel of
a wireless communication system, the first and second sounding signals being code-division multiplexed in the frequency domain
based on a phase rotated version of a known code exhibiting constant-amplitude zero autocorrelation, CAZAC, property, the
method comprising:
receiving at a plurality of antennas and converting the first and second sounding transmission signals into first and second
frequency-domain sounding signals, respectively;

performing a complex multiplication, in the frequency domain, between the first and second frequency-domain sounding signals
and a complex conjugate of the known CAZAC code, thereby generating first and second phase rotated frequency-domain sounding
signals, respectively;

transforming the first and second phase rotated frequency-domain sounding signals from the frequency domain to the time domain,
thereby generating first and second cyclically shifted time-domain sounding signals;

estimating a power delay profile of the wide channel based on the first and second cyclically shifted time-domain sounding
signals, thereby generating a power delay profile estimate comprising first and second energy regions associated with first
and second propagation delays occurring in the wide channel, respectively;

producing a matrix representation of correlation between the first and second frequency-domain sounding signals received at
the plurality of antennas, thereby generating a noise and interference covariance matrix;

determining a noise power level of the wide channel based on the noise and interference covariance matrix;
determining a first received power level by integrating samples associated with the first energy region; and,
determining the SNR of the first sounding signal by dividing the first received power level by the noise power level.

US Pat. No. 9,626,280

DEBUG METHOD AND DEVICE FOR HANDLING EXCEPTIONS AND INTERRUPTS

NXP USA, INC., Austin, T...

1. A method comprising:
in response to an occurrence of an exception/interrupt, executing an exception/interrupt handler;
determining if a predicted return address of a Return From Exception Or Interrupt (RFEOI) instruction of the exception/interrupt
handler results in a match or a mismatch with an actual return address of the RFEOI instruction; and

generating a first trace address message identifying the actual return address in response to determining the mismatch, otherwise,
not generating the trace address message identifying the actual return address in response to determining match.