US Pat. No. 9,167,638

LED CONTROLLER CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An LED controller circuit, wherein the controller circuit is for controlling an inductive power converter which includes
a transistor for conducting an inductor current, and the inductor is driven by a drive voltage (VIN) received from a dimmer
circuit, wherein the controller circuit comprises:
a feedback arrangement for controlling the transistor in response to upper and lower thresholds of the inductor current; and
a processor for determining, based on an analysis or signal processing of the on-time of the transistor, dimmer characteristics,
including at least the dimmer type being leading edge or trailing edge and the on state and off states of the ac dimmed voltage
signal.

US Pat. No. 9,443,773

IC AND IC MANUFACTURING METHOD

NXP B.V., Eindhoven (NL)...

1. A method of manufacturing a vertical bipolar transistor in a CMOS process, comprising:
forming a collector by:
implanting an impurity of a first type into a substrate to form n-wells in the substrate and separated from one another at
a predefined spacing; and

connecting, after implanting the n-wells, the n-wells by laterally diffusing the impurity of the first type from each of said
n-wells into a portion of the substrate between the n-wells;

forming a halo implant using an impurity of a second type and a shallow implant using an impurity of the first type, said
halo implant enveloping the shallow implant in the substrate and being located over the laterally-diffused impurities of the
collector, said halo implant vertically separating the shallow implant from the laterally-diffused impurities of the collector;

forming, laterally spaced from the halo implant, a further implant using an impurity of the second type for providing a conductive
connection through a MOSFET channel and to the halo implant, wherein the MOSFET channel is formed in one of the n-wells; and

providing respective conductive connections to the further implant, the shallow implant and the collector allowing at least
a portion of each of the shallow implant, the halo implant and the collector to be respectively operable as an emitter, base
and collector of the vertical bipolar transistor.

US Pat. No. 9,438,429

METHOD FOR AUTHENTICATION AND ELECTRONIC DEVICE FOR PERFORMING THE AUTHENTICATION

NXP B.V., Eindhoven (NL)...

1. An authentication method for a secure data transmission, the method comprising:
performing, in a processor, a first authentication protocol by using a first cipher, and
performing, in the processor, a second authentication protocol by using a second cipher, wherein the second authentication
protocol replaces a handshake protocol.

US Pat. No. 9,426,842

DISTRIBUTED RADIO SYSTEM

NXP B.V., Eindhoven (NL)...

1. A distributed radio system comprising:
a plurality of distributed receivers not sharing a same oscillator, each receiver being adapted to receive a same radio signal
and to transmit respective digital signals;

a digital communication channel coupled to the plurality of receivers and adapted to receive the digital signals and to transmit
the digital signals;

a base-band unit coupled to the communication channel and adapted to combine and process the digital signals;wherein the baseband processing is split in such a way that further processing and combining of partly demodulated signals
may be done in another unit while maintaining the diversity gain and the signal and a control data are exchanged over the
digital communication channel; and
the digital signals comprising information available in each receiver of the plurality of receivers for exploiting a diversity
gain of the same radio signal.

US Pat. No. 9,198,255

VOLTAGE TO CURRENT ARCHITECTURE TO IMPROVE PWM PERFORMANCE OF OUTPUT DRIVERS

NXP B.V., Eindhoven (NL)...

1. A method comprising:
providing a controlled current path including a load configured and arranged to draw current from the controlled current path;
controlling current through the load in the controlled current path, in response to first and second aspects of a modulating
voltage signal, by causing a transistor circuit, including a transistor, to switch between

a current-conducting mode in which the controlled current is drawn through a first current branch,
a current-blocking mode in which the controlled current through the first current branch is blocked; and
wherein switching the transistor between the current-conducting mode and the current-blocking mode subjects junctions of the
transistor to voltage stresses due to current in the controlled current path spiking towards a breakdown threshold of the
transistor;

in response to the first aspect of the modulating voltage signal and in the current-conducting mode, using the transistor
circuit to direct current in the controlled current path through the first current branch; and

in response to the second aspect of the modulating voltage signal and in the current-blocking mode, diverting the current
in the controlled current path from the first current branch to a second current branch sufficiently fast to suppress current
spikes in the controlled current path and the junctions from reaching the breakdown threshold of the transistor and thereby
avoiding junction breakdown.

US Pat. No. 9,245,804

USING A DOUBLE-CUT FOR MECHANICAL PROTECTION OF A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP)

NXP B.V., Eindhoven (NL)...

1. A method for assembling a wafer level chip scale processed (WLCSP) wafer, the wafer having a front-side surface and a back-side
surface, a plurality of device die having electrical contacts on the front-side surface, the method comprising:
mounting the wafer onto a grinding foil;
back-grinding, to a thickness, the back-side surface the wafer;
mounting the wafer onto a sawing foil onto a first-side surface;
sawing through second-side surface, the second-side surface opposite the first chosen-side surface, to a depth of the back-ground
thickness of the wafer, in areas corresponding to saw lanes of the plurality of device die;

stretching the sawing foil so as to space apart device die;
on the front-side surface of the wafer, re-mounting the wafer onto molding foil and removing the sawing foil;
enveloping the device die in molding compound on the back-side surfaces and vertical faces of the spaced-apart device die,
the molding compound of a thickness on the back-side surface and another thickness on the vertical faces;

removing the molding foil;
re-mounting the molded WLCSP wafer on its back-side surface, onto a sawing foil; and
sawing the molded WLCSP wafer on the front-side surface in saw lanes of the plurality of device die so as to separate the
molded wafer into individual device die having protective molding thereon.

US Pat. No. 9,257,374

THIN SHRINK OUTLINE PACKAGE (TSOP)

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a device die;
a package structure defining a rectangular boundary and having a top surface and an opposite bottom surface, the device die
mounted to the top surface on a die attach pad enclosed by the rectangular boundary;

a first plurality of terminal I/O leads extending from one side of the rectangular boundary, the first plurality of terminal
I/O leads electrically connected to the device die by wire bonds;

a second plurality of terminal I/O leads extending from another opposite side of the rectangular boundary, the second plurality
of terminal I/O leads electrically connected to the device die by wire bonds;

wherein the terminal I/O leads have a pitch of about 0.65 mm and have a length about 0.5 mm from the rectangular boundary.

US Pat. No. 9,070,001

SAFE INITIALIZATION PROCEDURE FOR A COMMUNICATION SYSTEM

NXP B.V., Eindhoven (NL)...

1. A transponder for communicating with a reader device, the transponder comprising:
a processing unit adapted for generating an identifier during an initialization phase of a communication session with the
reader device, the identifier comprising a first part, which is a random number, and a second part, which is identical to
at least a portion of a previous identifier used during a previous communication session preceding the present communication
session with the reader device, wherein the at least a portion of the previous identifier used during a previous communication
session preceding the present communication session is a random number generated for the previous communication session;

a transmission unit adapted for transmitting the identifier to the reader device;
wherein the processing unit is adapted for generating the identifier with an order of the first part and the second part which
order is modified, particularly is alternated, between subsequent communication sessions.

US Pat. No. 9,219,412

BUCK CONVERTER WITH REVERSE CURRENT PROTECTION, AND A PHOTOVOLTAIC SYSTEM

NXP B.V., Eindhoven (NL)...

1. A buck converter having an input and an output and comprising:
a high-side switch, a low-side switch, a protection switch and a shutter switch, each having a respective control terminal
and respective first and second main terminals;

the first low-side main terminal being connected to a ground, the second low-side main terminal and the first high-side main
terminal being connected to a converter node,

the second high-side main terminal being connected to the second protection main terminal and the first protection main terminal
being connected to an input node such that the high-side switch and the protection switch are in anti-series,

the first shutter main terminal being connected to the protection control terminal,
the shutter control terminal being electrically coupled to the input node, and
the second main shutter terminal being directly connected to the output;
wherein either;
(a) the protection switch is a NMOS transistor and the shutter control terminal is electrically directly coupled to the input
node; or

(b) the protection switch is a PMOS transistor and the shutter control terminal is electrically coupled to the input node
by a floating supply for providing an offset voltage from a voltage at the input node.

US Pat. No. 9,154,881

DIGITAL AUDIO PROCESSING SYSTEM AND METHOD

NXP B.V., Eindhoven (NL)...

1. An audio processing system, comprising:
combining means for combining left and right channels of an audio data stream to derive sum and difference signals;
a time domain to frequency domain converter for converting the sum and difference signals to the frequency domain;
a first processing unit for deriving a frequency domain noise signal based at least partly on the frequency domain difference
signal;

a second processing unit for processing the frequency domain sum signal using the noise signal thereby to reduce noise artifacts
in the sum signal; and

a frequency domain to time domain converter for converting at least the processed frequency domain sum signal to the time
domain.

US Pat. No. 9,171,837

CASCODE CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A cascode transistor circuit comprising:
a first, depletion mode transistor having its drain for connection to a high power line;
a second, silicon MOSFET with its drain connected to the source of the first transistor and its source for connection to a
low power line;

a substrate on which the first and second transistors are mounted, which has a conductive track providing the connection between
the source of the first transistor and the drain of the second transistor; and

wherein the first, depletion mode, transistor comprises a high electron mobility transistor or a junction gate field effect
transistor.

US Pat. No. 9,170,297

SECURE LOW PIN COUNT SCAN

NXP B.V., Eindhoven (NL)...

1. A contactless smartcard integrated circuit comprising:
a digital module;
a first pin for inputting a clock signal, the first pin being electrically coupled to the digital module;
a second pin for both inputting a test scan sequence and outputting scan data, the second pin being electrically coupled to
the digital module; and

a test control logic for controlling both input to the second pin and output from the second pin,
wherein the digital module comprises a scan chain compactor configured to create a single scan chain,
wherein the scan chain compactor is electrically coupled to a first input of a comparative logic and an output of the comparative
logic is electrically coupled to a signature generator,

wherein a second input of the comparative logic is electrically coupled to an input buffer, the input buffer being electrically
coupled to the second pin such that mask data may be provided to the second input of the comparative logic from the second
pin.

US Pat. No. 9,203,745

ROUTING TABLE UPDATING

NXP B.V., Eindhoven (NL)...

1. A method of transmitting routing information within a network, the method comprising:
in response to a change in preferred route from one node to another node within the network, providing a message comprising
a digital word in which at least each node in the mesh network other than the one node and the another node is represented
by a single binary bit, where the single binary bit associated with each node is set to one value if the node is in the preferred
route, and the other value if the node is not in the preferred route;

wherein the preferred route is the route with the lowest hop count, the lowest hop count determined by the number of bits
in the digital word set to the value indicating that a node is in the preferred route; and

wherein the method further comprises receiving a first message from a node which neighbors said one node informing said one
node of a shorter route if the route provided by said one node is longer than the preferred route in a routing table of the
node which neighbors said one node.

US Pat. No. 9,220,159

ELECTRONIC BALLAST

NXP B.V., Eindhoven (NL)...

1. An electronic ballast for lighting applications, the electronic ballast comprising:
a first charge pump having an input capacitor charged with a supply current drawn from a power source by application of a
charging voltage to the input capacitor, a magnitude of the supply current being proportional to a magnitude of the charging
voltage; and

a voltage booster for generating a boost voltage, which is used to augment the charging voltage, thereby increasing the current
drawn from the power source, wherein the voltage booster comprises a secondary winding of a transformer configured to generate
the boost voltage, wherein a primary winding of the transformer is energised by a source of alternating voltage generated
within the electronic ballast, wherein the secondary winding is coupled to an anode of a diode via a second capacitor, and
wherein a cathode of the diode is connected to the input capacitor.

US Pat. No. 9,082,241

WIRELESS COMMUNICATIONS CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a portable motion-sensing circuit configured and arranged to be carried by a user and to indicate that motion is sensed in
response to detecting whether the user has been moving for a predetermined period of time; and

a communication circuit communicatively coupled to the motion-sensing circuit and configured and arranged to operate in an
active mode and an inactive mode in which the communication circuit is consuming less power relative to power consumed by
the communication circuit in the active mode, and in which wireless access authentication communications with the communication
circuit are respectively permitted and inhibited in the active and inactive modes, wherein the communication circuit is configured
and arranged to operate in the active mode in response to a spectral characteristic of the motion being sensed at the motion-sensing
circuit and a type of motion indicated by the spectral characteristic, and to use the low-frequency communication circuit
to detect a polling signal from a remote base station, and

identify the remote base station based upon the polling signal.

US Pat. No. 9,241,237

DEVICE WITH AN EEPROM HAVING BOTH A NEAR FIELD COMMUNICATION INTERFACE AND A SECOND INTERFACE

NXP B.V., Eindhoven (NL)...

1. A lock/security peripheral device comprising:
a passive near field communication (NFC) interface;
a data interface;
a memory, wherein the memory is dual interfaced such that the passive NFC interface and the data interface can both be used
by the memory to transmit data;

an NFC antenna, connected to the passive NFC interface, that is configured to communicate NFC signals with a first external
device; and

a logic controller in data communication with the data interface, wherein the passive NFC interface and the data interface
automatically share both a single memory and necessary authentication data.

US Pat. No. 9,048,681

WIRELESS POWER AND DATA APPARATUS, SYSTEM AND METHOD

NXP B.V., Eindhoven (NL)...

1. For use in wirelessly charging portable devices and in both powering and authenticating remote operator-carried transponders
for activating an automotive circuit, an apparatus comprising:
a portable device including circuitry configured to be wirelessly charged;
a first circuit-based module including signal transmission circuitry and configured an arranged to
operate in a first mode to generate and transmit a first signal to wirelessly charge a portable device, wherein the first
circuit-based module is configured to communicate and exchange data with the portable device while in the first mode and while
wirelessly charging the portable device by energy sourced from the first signal, and

in response to detecting the presence of a remote transponder, operate in a second mode to generate and transmit a second
signal to power and communicate authentication data with the remote transponder; and

a second circuit-based module including logic circuitry and configured and arranged to authenticate the transponder by accessing
and processing stored authentication data with authentication data carried in signals received from the remote transponder
via the first module, and generate an output for activating the automotive circuit based upon the authentication.

US Pat. No. 9,473,932

LOCAL TRUSTED SERVICE MANAGER

NXP B.V., Eindhoven (NL)...

1. A method for managing a secure element which is embedded into a host unit, the method comprising:
transmitting a request for a management script from the host unit to a program element of the secure element;
at the program element, generating a management script in accordance with the request and encrypting the generated management
script;

transmitting the encrypted management script from the program element to the host unit;
transmitting the encrypted management script from the host unit to a secure domain of the secure element; and
at the secure domain, decrypting and executing the management script, wherein the request comprises a parameter value which
is to be used to generate the management script, the host unit is a mobile communication unit, and the parameter value is
an International Mobile Equipment Identity of the mobile communication unit.

US Pat. No. 9,545,041

I/O DEVICE, METHOD FOR PROVIDING ESD PROTECTION FOR AN I/O DEVICE AND ESD PROTECTION DEVICE FOR AN I/O DEVICE

NXP B.V., Eindhoven (NL)...

1. A method for providing electrostatic discharge (ESD) protection for an Input/Output (I/O) device, the method comprising:
activating a switch device to turn off the I/O device during an ESD event, wherein the switch device is directly connected
to a trigger device configured to generate an ESD trigger signal during the ESD event and is not directly connected to an
ESD power clamp, and wherein the trigger device and the ESD power clamp are connected to different voltage lines; and

deactivating the switch device to turn on the I/O device in the absence of an ESD event.

US Pat. No. 9,300,353

START OF FRAME DELIMITER IN A COMMUNICATION PACKET

NXP B.V., Eindhoven (NL)...

1. A transmitter for communicating, the transmitter comprising:
a memory;
a processor in communication with the memory, the processor configured to: determine a spreading code with low sidelobe levels
in its autocorrelation sequence to be used; create a Start of Frame Delimiter (SOFD) for a packet including the spreading
code and a cyclic prefix, wherein the cyclic prefix is a limited fraction of a SOFD sequence and less than half of a length
of the spreading code, and transmit the packet with the SOFD.

US Pat. No. 9,432,779

HEARING AID ANTENNA

NXP B.V., Eindhoven (NL)...

1. An antenna in a hearing aid, the antenna comprising:
a solid three-dimensional dielectric support body;
an electrically conductive first plate on a first surface of the support body;
an electrically conductive second plate on a second surface of the support body, wherein the first surface and the second
surface are arranged on opposing ends of the support body;

an electrically conductive filament arranged on and/or in the support body configured to reactively couple the first plate
with the second plate, comprising first sections and second sections, wherein the second sections are perpendicular to the
first sections.

US Pat. No. 9,385,703

CIRCUIT AND METHOD FOR BODY BIASING

NXP B.V., Eindhoven (NL)...

1. An apparatus, comprising:
a first transistor having a source, a drain, a gate, and a body, the first transistor configured and arranged to provide a
data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control
signal provided to the gate, the first transistor being subject to attenuation of the data signal due to body effects,

wherein the first transistor is an n-type transistor subject to variation in on-resistance between the source and drain for
different voltages of the data signal due to body effects

a body bias circuit configured and arranged to bias the body of the first transistor based on a voltage of the data signal
and to reduce attenuation of the data signal by the first transistor;

wherein the body bias circuit is configured and arranged to bias the body of the first transistor toward a lesser of a source
voltage of the source and a drain voltage of the drain, thereby reducing variation in the on-resistance exhibited by the first
transistor;

wherein the body bias circuit includes:
a second transistor configured and arranged to connect the body of the first transistor to the drain of the first transistor
in response to the drain voltage being less than the source voltage;

a third transistor configured and arranged to connect the body of the first transistor to the source of the first transistor
in response to the drain voltage being greater than the source voltage; and

a resistor configured to mitigate parasitic effects in the first transistor by providing a discharge path between the body
of the first transistor and ground.

US Pat. No. 9,451,669

CMOS ADJUSTABLE OVER VOLTAGE ESD AND SURGE PROTECTION FOR LED APPLICATION

NXP B.V., Eindhoven (NL)...

1. A light emitting diode protection circuit, comprising:
a plurality of diodes connected in series;
a first input connected to a first diode of the plurality of diodes;
a second input connected to a junction between two of the plurality of diodes, wherein shorting the first input to the second
input reduces a breakdown voltage of the plurality of diodes;

an output;
a first resistor connected between the plurality of diodes and the output;
a transistor with a gate connected to a junction between the first resistor and the plurality of diodes and a source connected
to the output;

a second resistor connected between the first input and a drain of the transistor; and
a silicon controlled rectifier (SCR) with an anode connected to the first input, a base connected to the drain of the transistor,
and a cathode connected to the output.

US Pat. No. 9,054,773

APPARATUS COMPRISING A BROADCAST RECEIVER CIRCUIT AND PROVIDED WITH AN ANTENNA

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising
a broadcast receiver circuit,
an embedded antenna configured and arranged for receiving broadcast signals in a broadcast band of interest, the embedded
antenna being less than one tenth of the wavelength corresponding to a center frequency of the broadcast band of interest
and for presenting a primarily reactive impedance, and

a tuning circuit coupled between the antenna and the broadcast receiver circuit, which tuning circuit includes a filter circuit
coupled to ground, wherein the filter circuit includes primarily reactive impedance of the embedded antenna and the tuning
circuit is configured and arranged to have a first resonance at a first frequency below a lower cutoff frequency for the broadcast
band of interest, and a second resonance at a second frequency above an upper cutoff frequency of the broadcast band and wherein
the tuning circuit comprises an amplifier with an output to the receiver circuit and with an input to the filter circuit,
and wherein the tuning circuit is configured to provide a carrier to noise ratio (CNR) which is substantially flat across
the broadcast band.

US Pat. No. 9,369,124

POWER-ON-RESET CIRCUIT WITH LOW POWER CONSUMPTION

NXP B.V., Eindhoven (NL)...

1. For use with circuitry that is reset by a power-on reset signal that is provided in response to power being provided, a
circuit comprising:
a detector that includes a portion that is configured to draw current from a supply voltage, the detector configured to
detect that the supply voltage has exceeded a trip-point voltage level,
disable, in response to detecting that the supply voltage exceeds the trip point voltage level, current draw from the portion
of the detector, and

enable, in response to an enable signal, current draw from the portion of the detector;
a pulse generator configured to generate a reset signal in response to the supply voltage transitioning from a voltage below
the trip point voltage level to above the trip point voltage level; and

a monitor configured to detect that the supply voltage has dropped and to provide, in response to detecting the supply voltage
has dropped, the enable signal to the detector to enable current draw from the portion of the detector.

US Pat. No. 9,204,246

RADIO FREQUENCY-COMMUNICATION DEVICE AND METHOD FOR OPERATING THE SAME

NXP B.V., Eindhoven (NL)...

1. A Near Field Communication device comprising a data transmitter and a data receiver,
wherein the data transmitter comprises a load modulator adapted to receive a radio frequency (RF) carrier signal emitted by
another Near Field Communication device and to modulate the RF carrier signal using the load modulator in accordance with
data to be sent, and

wherein the data receiver comprises a RF carrier signal generator adapted to emit a radio frequency carrier signal and a load
demodulator connected to an emission path of the radio frequency carrier signal, wherein the load demodulator demodulates
the radio frequency carrier signal when the radio frequency carrier signal has been load modulated by another Near Field Communication
device.

US Pat. No. 9,287,998

BROADCAST DEVICE FOR BROADCASTING PAYLOAD DATA, NETWORK DEVICE FOR RECEIVING BROADCASTED PAYLOAD DATA AND METHOD FOR INITIATING BROADCASTING PAYLOAD DATA

NXP B.V., Eindhoven (NL)...

1. A method for preparing broadcasting payload data, the method comprising:
wirelessly transmitting a message from a broadcast device, the message containing configuration information of the broadcasting,
wherein the message is receivable at a network device,
wherein the configuration information includes a transmission frame structure, is extractable at the network device and includes
data that is used by the network device and causes the network device to be configured for receiving at least a part of the
broadcast payload data based on the configuration information and in the transmission frame structure,

wherein the configuration information comprises information indicative of a start time at which the broadcasting starts, the
start time being at a time after the message has been transmitted, and

establishing a communication between the network device and a second network device according to the transmission frame structure,
wherein the configuration information is used for configuring the network device by causing the network device to act based
on a previous wireless communication with the second network device, the previous wireless communication having been performed
according to a previous transmission frame structure different from the transmission frame structure.

US Pat. No. 9,280,692

METHOD AND RFID READER FOR EVALUATING A DATA STREAM SIGNAL IN RESPECT OF DATA AND/OR COLLISION

NXP B.V., Eindhoven (NL)...

1. A method for evaluating by a radio frequency identification reader a data stream signal in respect of data and/or collision,
comprising comparing the data stream signal with at least one threshold level using the radio frequency identification reader,
and evaluating the results of the comparison using the radio frequency identification reader, wherein the at least one threshold
level is adapted such that an adaptation speed of the at least one threshold level is adapted in dependence of an actual sample
amplitude of the data stream signal, wherein the adaptation speed is a function of a variance of the at least one threshold
level, a relative distance of the at least one threshold level to the actual sample amplitude of the data stream signal that
is represented by
and an on/off variable that is used to activate or deactivate an adaptation of the at least one threshold level, wherein S
represents the actual sample amplitude of the data stream signal, and wherein L represents a threshold level.

US Pat. No. 9,298,238

CMOS POWER BACKUP SWITCHING CIRCUIT AND METHOD FOR OPERATING A CMOS POWER BACKUP SWITCHING CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A Complementary Metal Oxide Semiconductor (CMOS) power switching circuit comprising:
a voltage selection circuit configured to output the highest output voltage between an output voltage of a primary power supply
and an output voltage of a backup power supply; and

a control circuit configured to connect a load circuit to either the primary power supply or the backup power supply by comparing
the output voltage of the primary power supply with a power supply switchover level that is different from the output voltage
of the backup power supply and is set as a function of the highest output voltage, wherein the backup power supply serves
as a voltage reference to set the power supply switchover level only when the output voltage of the primary power supply is
lower than the output voltage of the backup power supply, wherein the control circuit comprises:

a voltage divider configured to scale the output voltage of the primary power supply to generate a scaled output voltage;
a voltage sensor circuit configured to set a threshold voltage below the output voltage of the backup power supply as a function
of the highest output voltage, to compare the scaled output voltage with the threshold voltage, and to output a digital signal
indicative of the magnitude of the scaled output voltage relative to the threshold voltage, wherein the voltage sensor circuit
is further configured to set the threshold voltage as the function of the output voltage of the backup power supply only when
the output voltage of the primary power supply is lower than the output voltage of the backup power supply;

a power transfer switch configured to connect the load circuit to either the primary power supply or the backup power supply;
and

a switch control circuit configured to control the switching of the power transfer switch between the primary power supply
and the backup power supply based on the digital signal.

US Pat. No. 9,306,498

CURRENT DRIVEN FLOATING DRIVER CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A circuit for generating a modulated signal, comprising:
a constant current source;
a first switch coupled to the constant current source;
a second switch coupled to the first switch and a ground, wherein the first switch and the second switch are coupled to a
third switch, the third switch is coupled to a first integrated circuit pad, wherein the first integrated circuit pad is defined
to be used for coupling the third switch to a resonance circuit and

a fourth switch coupled to the ground and a fifth switch.

US Pat. No. 9,262,711

NFC TAG, COMMUNICATION METHOD AND SYSTEM

NXP B.V., Eindhoven (NL)...

1. Near field communication tag, comprising:
a first tag interface for wireless near field communication with a first device;
a second tag interface for wired communication with a second device;
a field detection section for detecting a near field for the wireless near field communication;
a pin connectable to the second device, wherein an output signal is determined based on a result of the detecting of a near
field and the output signal is provided to the pin; and

an electronic storage storing pin configuration information specifying the output signal.

US Pat. No. 9,222,989

MANUFACTURING METHODS FOR A SENSOR PACKAGE INCLUDING A LEAD FRAME

NXP B.V., Eindhoven (NL)...

1. A method for manufacturing a sensor package comprising;
bending a lead frame so as to achieve a first portion extending in a direction along a first longitudinal axis and having
a die pad, and a second portion extending in a direction inclined to the longitudinal axis, which second portion has a first
side facing away from the first portion and a second side opposing to the first side;

mounting an application specific integrated circuit onto the die pad, and mounting a magneto resistive sensor and a ferrite
to the second portion;

wherein the lead frame is formed as a plurality of fingers in the transit from the first portion to the second portion, at
least a part of the fingers are electrically isolated from the die pad and at least one finger being electrically connected
to the die pad, which fingers are connected to a tie bar for positioning purposes before mounting, which tie bar is removed
after mounting one out of a group consisting of the magneto resistive sensor and the ferrite to the fingers thus fixing the
position of the fingers relative to each other;

electrically connecting the magneto resistive sensor to the application specific integrated circuit via the fingers of the
lead frame that are electrically isolated from the die pad, wherein electrically connecting is carried out as coupling the
magneto resistive sensor to the fingers with wire bonds that are attached to the fingers at a side remote from the application
specified integrated circuit; and

moulding in a single moulding step a body covering the second portion of the lead frame, the magneto resistive sensor, the
ferrite, the die pad, the application specific integrated circuit and an electrical connection between the sensor and the
application specific integrated circuit, so as to achieve a one-piece moulding body.

US Pat. No. 9,264,034

CIRCUIT AND METHOD FOR BODY BIASING

NXP B.V., Eindhoven (NL)...

1. An apparatus, comprising:
a first transistor having a source, a drain, a gate, and a body, the first transistor configured and arranged to provide a
data signal from a first one of the source or the drain to the other one of the source or the drain in response to a control
signal provided to the gate, the first transistor being subject to attenuation of the data signal due to body effects; and

a body bias circuit configured and arranged to bias the body of the first transistor based on a voltage of the data signal
and to reduce attenuation of the data signal by the first transistor, wherein the body bias circuit includes:

a second transistor having a source, a drain, and a gate and wherein the source and drain are connected between the body of
the first transistor and the first one of the source or the drain of the first transistor;

a third transistor having a source, a drain, and a gate and wherein the source and drain are connected between the body of
the first transistor and the other one of the source or drain of the first transistor;

the apparatus further including:
a first switch connected between the second transistor and the first one of the source or the drain of the first transistor;
a second switch connected between the third transistor and the other one of the source or the drain of the first transistor;
wherein the gate of the second transistor is connected between the second switch and the third transistor and the gate of
the third transistor is connected between the first switch and the second transistor.

US Pat. No. 9,226,143

CONTROLLING APPLICATION ACCESS TO MOBILE DEVICE FUNCTIONS

NXP B.V., Eindhoven (NL)...

1. A method of controlling application access to predetermined functions of a mobile device, the method comprising:
generating, with a Trusted Service Manager (TSM) a set of keys, wherein each key is unique and corresponds to only one of
the predetermined functions;

receiving, in the TSM, an application from an application provider together with information identifying a set of needed functions;
generating, in the TSM, a signed application by digitally signing the received application with each of the keys that respectively
corresponds to one of the needed functions identified by the received information; and

transmitting information identifying the needed functions and the signed application and a set of access rules from the TSM
to a Secure Element of the mobile device;

wherein the method is performed by one or more hardware processors.

US Pat. No. 9,091,741

PROPORTIONAL-INTEGRAL-DERIVATIVE (PID) ANALOG CONTROLLER AND A METHOD FOR TESTING A PID ANALOG CONTROLLER OF A DC/DC CONVERTER

NXP B.V., Eindhoven (NL)...

1. A method for testing a Proportional-Integral-Derivative (PID) analog controller of a Direct Current (DC)/DC converter,
the method comprising:
setting an analog regulation loop, which is formed by an operational transconductance amplifier (OTA) of the PID analog controller
and a feedback network of the PID analog controller, to a stable condition and testing a DC parameter of the PID analog controller
using a tester; and

setting the analog regulation loop to an unstable condition and testing an Alternate Current (AC) parameter of the PID analog
controller using the tester.

US Pat. No. 9,288,107

METHOD AND SYSTEM FOR CONTROLLING OPERATIONS IN A MOBILE COMMUNICATION DEVICE THAT IS ENABLED FOR NEAR FIELD COMMUNICATION (NFC)

NXP B.V., Eindhoven (NL)...

1. A method for controlling operations in a mobile communication device that is enabled for near field communication (NFC),
the method comprising:
starting an NFC service in the mobile communication device;
starting an initialization process of a secure element (SE) of the mobile communication device in response to starting the
NFC service;

once the initialization process of the SE has begun, monitoring an SE-specific session ID for an indication of the status
of the initialization process of the SE;

if the SE-specific session ID indicates that the initialization process is not complete, continuing to monitor the SE-generated
session ID; and

if the SE-specific session ID indicates that the initialization process is complete, notifying the NFC service that the initialization
process of the SE is complete and command the terminal host to release suspended commands/interrupts.

US Pat. No. 9,154,098

AMPLIFIER CIRCUIT AND AMPLIFICATION METHOD

NXP B.V., Eindhoven (NL)...

1. An amplifier circuit comprising:
a digital to analogue converter;
an amplifier for amplifying the analogue signal, and having a feedback impedance, an output from the amplifier for connection
to an output load,

wherein the circuit further comprises:
a voltage sensor for sensing the output voltage and generating a binary output which indicates whether the output is above
or below a threshold;

a variable gain feedback system for generating a feedback signal for combination with a digital input, thereby to provide
offset cancellation; and

a controller for controlling the variable gain, wherein the controller is adapted to reduce the gain over time between at
least two non-zero values to provide offset cancellation during an initial period of time of operation of the amplifier circuit.

US Pat. No. 9,368,958

SENSOR CONTROLLED TRANSISTOR PROTECTION

NXP B.V., Eindhoven (NL)...

1. A circuit for protecting a transistor, comprising:
a temperature sensing device coupled to the transistor, the temperature sensing device includes a sense diode that is biased
with a pre-selected constant current;

a tunable clamping circuit connected between transistor terminals through a diode, wherein the tunable clamping circuit is
configured to provide an adjustable clamping voltage; and

a temperature controller coupled to the temperature sensing device and the tunable clamping circuit, the temperature controller
is configured to trigger a change in a clamping voltage of the tunable clamping circuit based on a feedback from the temperature
sensing device.

US Pat. No. 9,281,239

BIOCOMPATIBLE ELECTRODES AND METHODS OF MANUFACTURING BIOCOMPATIBLE ELECTRODES

NXP B.V., Eindhoven (NL)...

1. A method of manufacturing a biocompatible electrode on a semiconductor device having a dielectric layer above at least
one metallisation layer, the method comprising:
etching a via in the dielectric layer and therein exposing the metallisation layer with via sidewalls extending from the metallisation
layer;

depositing filling metal in the via;
etching back the filling metal using a non-electropolishing chemical mechanical polishing tool to remove the metal from and
expose a top surface of the dielectric layer via chemical mechanical polishing and to leave the metal in the via level with
the top surface of the dielectric layer;

after etching back the filling metal and exposing the top surface and without moving the semiconductor device between chambers
of a single etching apparatus comprising the non-electropolishinq chemical mechanical polishing tool, carrying out a further
etch to etch back the filling metal in the via to form a recess in the filling metal within the via, by supplying a constant
flow of hydrogen peroxide from the chemical mechanical polishing tool into the recess and using the hydrogen peroxide to both
wet etch the filling metal and remove portions of the filling metal dissolved during the etch from the recess, the recess
in the filling metal having recess sidewalls inset from the via sidewalls;

depositing an electrode metal over the top surface of the dielectric layer and in the recess in the via; and
etching back the electrode metal using chemical mechanical polishing to remove the electrode metal from the surface of the
dielectric layer and to leave the electrode metal in the via to form the biocompatible electrode, and depositing a biocompatible-dielectric
layer over the electrode metal and covering the top surface of the dielectric layer.

US Pat. No. 9,263,955

SWITCHED MODE CONVERTER AND METHODS OF CONTROLLING SWITCHED MODE CONVERTERS

NXP B.V., Eindhoven (NL)...

1. A method of controlling a switched mode converter comprising a switch and for providing power to device having a load,
comprising:
in response to the load exceeding a first threshold, operating in a first mode, being a continuous conduction mode (CCM);
in response to the load exceeding a second threshold and not exceeding the first threshold, operating in second mode, being
a boundary conduction mode (BCM) without valley skipping wherein the switching frequency increases with decreasing load;

in response to the load exceeding a third threshold and not exceeding the second threshold, operating in a third mode, being
a BCM with valley skipping, wherein the switching frequency depends on the load and the number of valleys skipped and is between
a fixed upper and a lower switching frequency limit; and

in response to the load not exceeding the third threshold, operating in a fourth mode, being a BCM with valley skipping, wherein
the switching frequency depends on at least the load, and is between an upper and a lower switching frequency limit wherein
the upper switching frequency limit decreases with decreasing load.

US Pat. No. 9,258,643

SYSTEM FOR BLENDING SIGNALS

NXP B.V., Eindhoven (NL)...

1. A time modification system comprising:
a delay module for receiving an input signal comprising a series of digital samples at an input sample rate, the delay module
providing a delayed output signal;

a duration modification module for receiving the input signal or a delayed version thereof, and providing a modified output
signal, wherein the duration modification module is configured to extend or compress the input signal using an audio buffer;
and

a first switch for selecting either the delayed output signal or the modified output signal based on a target delay.

US Pat. No. 9,281,872

NEAR-FIELD COMMUNICATION AUTHENTICATION

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a wireless communication circuit configured and arranged to send and receive over-the-air communications using a first protocol;
a near-field communication circuit configured and arranged to send and receive near-field communications using a second protocol
that is different than the first protocol, and to receive power via received near-field communications;

a first circuit configured and arranged to communicate with remote transceivers via the wireless communication circuit;
a second circuit configured and arranged to communicate via the near-field communication circuit with local near-field communication
devices, and to receive power via the near-field communication circuit; and

a third circuit connected to and operable in response to inputs received via the first circuit and the near-field communication
circuit, and to operate using power received via the near-field communication circuit, the third circuit being configured
and arranged to

operate in an update mode in which identification (ID) data received via the near-field communication circuit and the second
circuit is stored;

operate in a read mode in which access to the stored ID data is facilitated via the near-field communication and second circuits;
and

in response to a read-only command, operate a read-only mode in which access to the stored ID data is restricted to read-only
access, and in the read-only mode provide read-only access to the stored ID data via the second circuit and the near-field
communication circuit using the power received from the near-field communication circuit, and provide the read-only access
to the stored ID data via the first circuit and the wireless communication circuit.

US Pat. No. 9,263,335

DISCRETE SEMICONDUCTOR DEVICE PACKAGE AND MANUFACTURING METHOD

NXP B.V., Eindhoven (NL)...

5. A method of manufacturing a discrete semiconductor package, comprising:
providing a wafer comprising a plurality of discrete semiconductor devices, each of said discrete semiconductor devices having
a first surface and a second surface opposite said first surface carrying a contact;

forming respective conductive bodies on each of said contacts;
covering at least the surface of the wafer carrying the conductive bodies with an encapsulating material;
singulating the discrete semiconductor devices; and
providing a capping member over at least the conductive body of each of the discrete semiconductor devices;
partially singulating the discrete semiconductor devices prior to said covering step, thereby exposing the sides of each discrete
semiconductor device that connect the first surface to the second surface; and

wherein said covering step further comprises covering said sides with the encapsulating material.

US Pat. No. 9,231,201

ELECTRIC DEVICE WITH A LAYER OF CONDUCTIVE MATERIAL CONTACTED BY NANOWIRES

NXP B.V., Eindhoven (NL)...

1. An electric device comprising:
a layer of an electrically conductive material, and
a set of nanowires (NW) electrically connected to the layer of the electrically conductive material for conducting an electric
current via the nanowires (NW) to the layer of the electrically conductive material, each nanowire (NW) electrically contacting
the layer of the electrically conductive material in a respective contact surface, all contact surfaces having substantially
the same surface area;

wherein at least one of the nanowires (NW) and the layer of electrically conductive material is electrically connected to
a selection device, wherein the selection device is a diode and the selection device is provided with a gate.

US Pat. No. 9,219,475

POWER ARBITRATION METHOD AND APPARATUS HAVING A CONTROL LOGIC CIRCUIT FOR ASSESSING AND SELECTING POWER SUPPLIES

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a first power circuit for providing a regulated voltage to and for powering an integrated circuit (IC) having an operating
voltage level;

a second power circuit configured and arranged for providing power to and for powering the IC;
a control logic circuit that includes:
a compare circuit that is configured and arranged for assessing, based on the regulated voltage and a first threshold voltage
level, the first threshold voltage being indicative of the operating voltage level, whether the second power circuit is to
provide power to the IC as an alternative to the first power circuit providing power to the IC, and in response thereto, for
providing an arbitration-control signal, and

an over-rule circuit that is configured and arranged for assessing, based on a comparison between the regulated voltage and
a second threshold voltage level that is lower than the first threshold, and in response to the assessment, for disabling
the compare circuit; and

a power-signal switching circuit, responsive to the control logic circuit and connected to receive power from each of the
first and the second power circuits for providing power to the powered integrated circuit, configured and arranged for enabling,
in response to the arbitration-control signal, power to be provided to the powered integrated circuit from a selected one
of the first power circuit and the second power circuit.

US Pat. No. 9,190,970

AMPLIFIER CIRCUIT

NXP B.V., Eindhoven (NL)...

1. An integrated power amplifier circuit comprising:
first and second amplifiers fabricated on one or more dies, the one or more dies being mounted on a support structure;
a first set of one or more connection elements connected to the first amplifier and passing above a portion of the support
structure; and

a second set of one or more connection elements connected to the second amplifier and passing above a portion of the support
structure,

wherein the support structure comprises at least one void, at least a portion of the at least one void being positioned directly
underneath at least one of the first and second sets of one or more connection elements; and

wherein the support structure comprises a flange, and wherein the at least one void is formed in the flange.

US Pat. No. 9,270,341

WIRELESS POWER AND DATA CONNECTOR

NXP B.V., Eindhoven (NL)...

1. A base-unit for non-galvanic coupling to a contactless-unit, the base-unit comprising:
an antenna coupled to an RF power source,
at least one data-link,
an authentication controller coupled to the at least one data-link, and
a data interface for coupling at least one of a data source and data sink to the base unit, the data interface being coupled
to the at least one data-link wherein

the base-unit is operable to
transmit and/or receive payload data via the data interface,
wirelessly transmit RF power from the RF power source to a contactless-unit in physical proximity to the base-unit,
transmit and/or receive authentication data via the at least one data-link to authenticate a non-galvanic connection to a
contactless-unit only when the contactless-unit is in physical proximity to the base-unit, and

transmit and/or receive payload data via the at least one data link following the authentication of the non-galvanic connection
to a contactless unit; and

wherein the authentication controller further comprises a watchdog timer and wherein the base-unit is operable to periodically
re-authenticate a non galvanic connection to a contactless-unit, the re-authentication period being determined by the watchdog
timer, and to disable further payload data transmission and/or reception if the re-authentication of the non-galvanic connection
fails.

US Pat. No. 9,270,343

WIRELESS CHARGING RECOGNIZING RECEIVER MOVEMENT OVER CHARGING PAD WITH NFC ANTENNA ARRAY

NXP B.V., Eindhoven (NL)...

1. A method for charging a receiver capable of creating an NFC field comprising:
providing a pad having a plurality of charging coils arranged in an array and a plurality of NFC antennas arranged in an array;
placing said receiver upon said pad;
causing said receiver to create an NFC field;
measuring said NFC field strength at two or more NFC antennas in said pad;
comparing said NFC field strengths at said two or more NFC antennas to determine at least one NFC antenna with greater field
strength;

selecting one or more charging coils associated with said at least one NFC antenna according to a predetermined rule; and
activating said one or more charging coils to charge said receiver by maintaining a charge to the receiver by assessing movement
of the receiver on the pad and re-selecting one or more charging coils.

US Pat. No. 9,263,954

SWITCHED MODE POWER SUPPLY

NXP B.V., Eindhoven (NL)...

1. A switched mode power supply comprising:
an input for connection to a rectified mains supply,
a transformer having a primary winding on a mains side and a secondary winding on a dc output side;
a switching element for controlling current flow in the primary winding of the transformer;
a sense resistor in series with the switching element;
a feedback control system for controlling the switching element dependent on a sense voltage, which is dependent on the sense
resistor,

wherein the feedback control system is part of an integrated circuit, and the transformer is outside the integrated circuit,
and

wherein the integrated circuit further comprises a detection arrangement for converting a rate of change of the sense voltage
into a constant current using a capacitor and converting the constant current into a constant voltage level using a resistor,
thereby deriving a voltage signal representing the mains voltage, wherein the feedback control system comprises a first comparator
and a second comparator, wherein the first comparator and the second comparator are for comparing the sense voltage with respective
reference voltages to generate two comparator outputs, wherein the first comparator is for comparing the sense voltage with
a first reference voltage to generate a first comparator output signal and inputting the first comparator output signal into
a reset input of a first set-reset latch to control the first set-reset latch, wherein a second set-reset latch is provided
which receives the two comparator outputs generated by the first and second comparators and which generates a sample signal
for a sample and hold circuit.

US Pat. No. 9,263,299

EXPOSED DIE CLIP BOND POWER PACKAGE

NXP B.V., Eindhoven (NL)...

7. A method for packaging an integrated circuit (IC) device from a semiconductor wafer substrate, the wafer substrate having
a top-side surface with a plurality active device die defined thereon, and an under-side surface, the method comprising:
backgrinding the under-side surface of the wafer substrate to a prescribed thickness;
applying a solderable conductive surface to the under-side surface of the wafer substrate;
separating out the plurality active device die from the semiconductor wafer substrate, each of the active device die having
bond pads, the bond pads providing electrical connection to circuit elements in the active device die;

mounting the plurality of active device die, into predetermined positions, onto a temporary carrier;
dispensing a solder paste onto the bond pads on the plurality active device die;
attaching individual lead frame portions to the temporary carrier and bond pads, wherein upper individual lead frame portions
contact the solder paste present on the bond pads and lower individual lead frame portions contact the temporary carrier;
and

reflowing the solder so that a connection is made between the upper lead frame portions and the bond pads of the plurality
of active device die.

US Pat. No. 9,298,955

PROXIMITY ASSURANCE FOR SHORT-RANGE COMMUNICATION CHANNELS

NXP B.V., Eindhoven (NL)...

1. A method for proximity assurance for a short range communication connection between a first device having a first accelerometer
and a second device having a second accelerometer comprising:
establishing the short range communication connection between the first and the second device to allow data exchange;
creating a bump by bringing the first device and the second device into physical contact and recording the bump in the first
and second accelerometer to generate a first and a second accelerometer history of the bump;

generating a first value using the first accelerometer history and a second value using the second accelerometer history;
exchanging the values between the first device and the second device using the short range communication channel;
exchanging the accelerometer histories between the first device and the second device;
verifying by the second device whether the first value agrees with the first accelerometer history and verifying by the first
device whether the second value agrees with the second accelerometer history; and

determining if the first accelerometer history matches the second accelerometer history in order to verify physical proximity.

US Pat. No. 9,271,355

SWITCHING POWER SUPPLY CONTROLLER

NXP B.V., Eindhoven (NL)...

1. A switching power supply controller, the switching power supply controller configured to generate a switch signal for controlling
a switch to convert an input signal from a phase cut dimmer into a driving signal for a solid state lighting element, wherein
the switching power supply controller is configured to;
determine a conduction period of the input signal from the phase cut dimmer within a half cycle period of the input signal;
determine a burst period within said conduction period comprising a period of time less than said conduction period;
generate a switch signal comprising a plurality of switching cycles over the burst period, the switch signal comprising a
first subset of switching cycles and a second subset of switching cycles, wherein the switching power supply controller is
configured to control the switching cycles of the second subset such that the average energy transferred per switching cycle
to the driving signal is less than the average energy transferred per switching cycle to the driving signal for the switching
cycles of the first subset.

US Pat. No. 9,269,617

VIA NETWORK STRUCTURES AND METHOD THEREFOR

NXP B.V., Eindhoven (NL)...

1. A method for manufacturing an integrated circuit device providing a surface over a structural aspect of the integrated
circuit device, the method comprising:
in a first insulating material, forming a first via network layer that includes a first plurality of metal via strips that
extend about parallel to the surface and in different directions to facilitate structural support of the bond pad contact
over the via strip and that each contact and extend between a bond pad contact and a first metal layer;

forming, in a second insulating material, a second via network layer that includes a second plurality of metal via strips
that extend about parallel to the surface and in different directions to facilitate structural support of the bond pad and
that each contact and extend between the first metal layer and a second metal layer,

wherein the via strips of the first via network are made from a first type of metal and the via strips of the second via network
are made from a second type of metal that has a lower yield strength than the first type of metal.

US Pat. No. 9,257,985

SYNCHRONIZED LOGIC CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A synchronised logic circuit comprising:
an input module;
an output module;
a decision logic module connected between the input and output modules and configured to provide a next output state to the
output module dependent on a current input state provided from the input and output modules;

a clock module connected to the input and output modules and configured to provide a clock signal for synchronising operation
of the input and output modules; and

an input detection module connected to the input module and configured to provide an enable signal to the clock module on
detection of a change in an input provided to the input module,

wherein the clock module is configured to provide a clock signal to the input and output modules on receiving the enable signal
from the input detection circuit.

US Pat. No. 9,246,550

NFC DEVICE FOR CONTACTLESS COMMUNICATION

NXP B.V., Eindhoven (NL)...

1. A Near Field Communication (NFC) device for contactless communication comprising:
a transmitter being adapted to generate an electromagnetic carrier signal and to modulate the carrier signal according to
transmitting data; and

an antenna having an inductor, which antenna is connected to and driven by the transmitter with the modulated carrier signal,
wherein connection points of the antenna are further connected to inputs of switches, the outputs of the switches being switchable
between ground potential and inputs of a rectifier, the outputs of the rectifier being fed to power supply rails of the NFC
device.

US Pat. No. 9,223,736

DEVICES AND METHODS FOR AN ENHANCED DRIVER MODE FOR A SHARED BUS

NXP B.V., Eindhoven (NL)...

1. A device comprising:
a transmission circuit configured and arranged to transmit data in accordance with a signal bus protocol that uses passive
bias to set a signal bus to a recessive value in the absence of an actively-driven signal value and including

a first driver circuit configured and arranged to actively drive the signal bus to a dominant value that is different from
and higher than the recessive value, and

a second driver circuit configured and arranged to actively drive the signal bus to and through the recessive value to another
value that is below the recessive value; and

a control circuit configured and arranged to
disable the second driver circuit in response to the device operating in a first data transmission mode, and
enable the second driver circuit in response to the device entering a second transmission mode.

US Pat. No. 9,190,237

ELECTRODE COATING FOR ELECTRON EMISSION DEVICES WITHIN CAVITIES

NXP B.V., Eindhoven (NL)...

1. A method for forming a field emission diode for an electrostatic discharge device, the method comprising:
forming a first electrode, a sacrificial layer, and a second electrode, wherein the sacrificial layer separates the first
and second electrode;

forming a cavity between the first and second electrode by removing the sacrificial layer, wherein the cavity separates the
first and second electrodes; and

depositing an electron emission material on a surface of at least one of the first and second electrodes through at least
one access hole after formation of the first and second electrodes, wherein the access hole is located remotely from a location
of electron emission on the first or second electrodes;

plugging the access hole after depositing the electron emission material and forming a vacuum or low gas pressure in the cavity,
wherein the cavity is hermetically sealed.

US Pat. No. 9,390,295

DEVICE WITH CAPACITIVE SECURITY SHIELD

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising a capacitive security shield, the capacitive security shield comprising:
a set of randomly distributed dielectric or conducting particles formed within a dielectric layer;
a plurality of electrodes formed in a layer over which the set of particles are formed; and
a non-volatile memory storing a sequence of configuration patterns;
a controller circuit coupled to the non-volatile memory and configured and arranged to
retrieve the sequence of configuration patterns from the memory, one at a time, each configuration pattern indicative of a
respective subset of the plurality of electrodes; and

for each retrieved configuration pattern, reconfiguring the plurality of electrodes for measuring a capacitance characteristic
via the respective subset of electrodes indicated in the configuration pattern; and

wherein for a first one of the configuration patterns the reconfiguring by the controller circuit configures the electrodes
as at least two sets, wherein a first set is used to measure a capacitance characteristic, and a second set is configured
as a non-measurement set, wherein for a second one of the configuration patterns, the reconfiguring by the controller circuit
reconfigures the electrodes into a third set and a fourth set that are different than the first and second sets, and the third
set is used to measure a reconfigured capacitance characteristic.

US Pat. No. 9,355,276

PROCESSING SYSTEM

NXP B.V., Eindhoven (NL)...

1. A processing system comprising:
a processing unit;
memory adapted to store firmware code and application code for execution by the processor; and
a memory access control unit adapted to control access of the processing unit to firmware code and application code stored
in the memory,

wherein the memory access control unit is adapted to transition between a normal mode in which access to firmware code is
disabled when access to application code is enabled, and a secure mode in which access to application code is disabled when
the application code calls to the firmware code through a single entry point address when the single entry point address matches
an address stored in a register of the memory access control unit; and

wherein the memory access control unit is adapted to transition between the normal mode and the secure mode when the application
code calls a function; and

wherein the single entry point address corresponds to a dispatcher function to which the application code passes at least
one parameter to define at least one function of the firmware code to be executed.

US Pat. No. 9,304,175

MAGNETORESISTIVE SENSOR DEVICE AND METHOD OF FABRICATING SUCH MAGNETORESISTIVE SENSOR DEVICE

NXP B.V., Eindhoven (NL)...

1. A method of fabricating a magnetoresistive sensor device, the method comprising:
forming at least one silicon wafer having a first side and a second side, wherein the first side is opposite to the second
side;

forming either an AMR sensing element or a multilayer GMR sensing element, said formed sensing element being arranged above
the first side of the formed silicon wafer; and

forming at least one magnetic layer underneath the second side of the formed silicon wafer and the formed sensing element,
said magnetic layer providing at least one bias magnetic field.

US Pat. No. 9,269,690

PACKAGED SEMICONDUCTOR DEVICE WITH INTERIOR POLYGONAL PADS

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a semiconductor chip having conductive pads;
a package structure defining a rectangular boundary and having a bottom surface and comprising;
only two interior polygonal pads exposed at the bottom surface of the package structure, each of the interior polygonal pads
being physically and electrically separated from each other at the bottom surface of the package structure and located on
a centerline of the bottom surface of the package structure; and

only four edge polygonal pads exposed at the bottom surface of the package structure, each of the edge polygonal pads being
located at an edge of the rectangular boundary, the edge polygonal pads including one edge polygonal pad in the vicinity of
each corner of the rectangular boundary;

wherein each of the interior polygonal pads has a first side that is parallel to a facing side of the edge polygonal pad that
is nearest to the first side and a second side that is parallel to a facing side of the edge polygonal pad that is nearest
to the second side, wherein the first side and the second side of each of the interior polygonal pads are not parallel to
the rectangular boundary of the package structure; and

wherein the interior polygonal pads are configured such that a line running between at least one vertex of each of the interior
polygonal pads is parallel to an edge of the rectangular boundary of the package structure;

wherein each of the interior polygonal pads and the edge polygonal pads is electrically connected to a different one of the
conductive pads of the semiconductor chip.

US Pat. No. 9,203,237

PROTECTION CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A circuit comprising:
a thyristor-based circuit having anode and cathode end regions separated by two base regions;
a first resistor connected between one of the base regions and one of an internal circuit terminal and a reference terminal;
and

a diode-based circuit connected in series with the thyristor-based circuit, the diode-based circuit and the thyristor-based
circuit being connected between the internal circuit terminal and the reference terminal, the diode-based circuit being configured
and arranged with the thyristor-based circuit to

operate in a first mode at which a voltage between the internal circuit and reference teiminals is below a first voltage level
at which the thyristor-based circuit breaks down,

transition between the first mode and a second mode in response to a voltage spike by applying the spike voltage across the
base regions and therein transitioning the thyristor-based circuit into a forward-biased mode, and

operate in the second mode in which the voltage between the internal circuit and reference terminals exceeds the first voltage
level, in which the thyristor-based circuit operates in the forward-biased mode and the diode operates in a breakdown mode
to conduct current between the internal circuit terminal and reference terminal, the second mode having a holding voltage
that is based upon a sum of a breakdown voltage of the diode-based circuit and a holding voltage for maintaining the thyristor-based
circuit in the forward-biased mode, wherein the current passed between the internal circuit terminal and reference circuit
terminal in each of the first and second modes and the transition therebetween being limited to current passed through a p-n
junction between the base regions.

US Pat. No. 9,147,732

GROUP 13 NITRIDE SEMICONDUCTOR DEVICE AND METHOD OF ITS MANUFACTURE

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a substrate;
at least one semiconducting layer comprising a nitride of a group 13 element on said substrate; and
an ohmic contact on the at least one semiconducting layer, said ohmic contact comprising a silicon-comprising portion on the
at least one semiconducting layer and a metal portion adjacent to and extending over said silicon-comprising portion, the
metal portion comprising titanium and a further metal, wherein the ohmic contact does not contain gold, wherein the metal
portion comprises a titanium layer, a layer of the further metal over the titanium layer, and a capping layer made of a material
containing titanium for protecting the layer of the further metal, wherein the silicon-comprising portion comprises a first
silicon-comprising portion and a second silicon-comprising portion laterally separated from the first silicon-comprising portion,
wherein a part of the metal portion extends between the first silicon-comprising portion and the second silicon-comprising
portion, and wherein the metal portion completely envelopes the first silicon-comprising portion and the second silicon-comprising
portion.

US Pat. No. 9,092,608

RANDOM-ID FUNCTION FOR SMARTCARDS

NXP B.V., Eindhoven (NL)...

1. A method for dynamically changing a random card identification code associated with a smartcard in a system having a card
reader system interacting with the smartcard comprising:
providing a current random card identification code associated with the smartcard from the smartcard to the card reader system
at the beginning of an interaction between the smartcard and the card reader system;

verifying whether the current random card identification code is valid in the card reader system; and
providing a new random card identification code from the card reader system to the smartcard if the current random card identification
code is valid;

wherein the smartcard comprises a state machine that operates to replace the current random card identification code with
the new random card identification code in a non-secure memory of the smartcard when the new random card identification code
is provided to the smartcard;

wherein the current random card identification code and the new random card identification code are card identification codes
that are used in an anti-collision process to distinguish between multiple smartcards and the current and new random card
identification codes are used to encrypt contents of a secure memory of the smartcard.

US Pat. No. 9,292,795

INTERPRETATION ENGINE USING THREE PREDICATE VALUES AND CONTENT ADDRESSABLE MEMORY

NXP B.V., Eindhoven (NL)...

1. An interoperable device comprising interpretation engine and a memory, the interpretation engine comprising hardwired logic
and configured to receive data and to determine a function to be executed in response to the received data and in accordance
with a knowledge base that comprises one or more relationships that are structured in triplets, wherein each triplet comprises
a subject, a predicate and an object, and wherein the interpretation engine is configured to recognize only a predetermined,
fixed plurality of predicate values;
wherein the predetermined plurality of predicate values is three values, wherein each predicate can only take a value from
the set:

a predicate that indicates that the subject belongs to a class denoted by the object;
a predicate that indicates that the subject comprises or possesses the object;
a predicate that indicates that the subject takes a literal value denoted by the object;
wherein the determination of a function to be executed is performed by the hardwired logic;
wherein the function is a function of the interoperable device or a communication function with another interoperable device;
wherein the memory is content addressable memory that comprises the knowledge base and the memory is categorized according
to values of predicates of relationships in the knowledge base.

US Pat. No. 9,128,500

SWITCHING CIRCUITS WITH VOLTAGE VALLEY DETECTION

NXP B.V., Eindhoven (NL)...

1. A switching circuit comprising:
a switching transistor adapted to control operation of the switching circuit according to a control signal applied to a control
terminal of the switching transistor, wherein the switching transistor is a MOSFET and the control terminal comprises the
gate of the MOSFET;

a regulating circuit connected to the gate of the switching transistor and having a high-side transistor and a low-side transistor
and adapted to generate the control signal; and

a valley detecting circuit adapted to sense a voltage at the control terminal when the switching transistor is in an OFF state
and to generate a drive signal according to the sensed voltage,

wherein the regulating circuit is adapted to generate the control signal based on the generated drive signal;
wherein the valley detecting circuit includes a comparator having a first input connected to the control terminal of the switching
transistor and a second input connected to a reference voltage and wherein the valley detecting circuit is adapted to generate
the drive signal based on a comparison of the sensed voltage at the first input of the comparator with the reference voltage
at the second input of the comparator when the switching transistor is in the OFF state;

wherein the reference voltage is a value within the range of about ?0.5 volts to about 0.5 volts; and
wherein the valley detecting circuit comprises a resistor connected in series with the low side transistor of the regulating
circuit and a diode connected in parallel with the resistor.

US Pat. No. 9,119,274

RESONANT CONVERTER CONTROL

NXP B.V., Eindhoven (NL)...

1. A method of controlling a power output of a resonant power converter comprising first and second switches connected in
series between a pair of supply voltage lines, a resonant circuit connected to a node between the first and second switches
and to an output connectable to an output electrical load, the resonant circuit comprising an inductor and a capacitor, the
method comprising:
closing the first switch to start a first conduction interval;
setting a first voltage level;
setting a first time period; and
opening the first switch to end the first conduction interval when a voltage across the capacitor crosses the first voltage
level and when a time period from closing the first switch exceeds the first time period.

US Pat. No. 9,065,487

WIDEBAND SOFTWARE-DEFINED RF RECEIVER

NXP B.V., Eindhoven (NL)...

1. An RF receiver comprising
an analog-to-digital converter for converting an analog intermediate frequency band signal to a digital intermediate frequency
band signal, wherein the analog intermediate frequency band signal has a plurality of narrow frequency bands of interest each
of which contains a particular signal of interest,

a plurality of decimation units coupled in cascade for generating a decimated signal, corresponding to the particular signal
of interest in one of the plurality of narrow frequency bands, based on the digital intermediate frequency band signal,

a signal processing unit for processing the decimated signal, and
a bypass path for feeding a bypass signal to the signal processing unit, the bypass signal being either the digital intermediate
frequency band signal or an output signal from one of the decimation units which is not the last one of the cascade coupled
decimation units,

wherein the signal processing unit is adapted to, by processing the bypass signal in parallel with the decimated signal of
the last one of the cascade coupled decimation units, detect critical reception conditions in the particular signal of interest
in one of the plurality of narrow frequency bands caused by information indicated by the bypass signal from at least one other
of the plurality of narrow frequency bands of interest based on the bypass signal and to adapt the processing of the decimated
signal in accordance with detected critical reception conditions.

US Pat. No. 9,743,468

CONTROLLER

NXP B.V., Eindhoven (NL)...

1. A controller for a switched mode power supply, SMPS, comprising:
a switch toggling unit configured to toggle a power switch with a fixed primary stroke duration within each switching cycle
in which the power switch is closed, the switch toggling unit having a first switching mode and a second switching mode, wherein
the first switching mode is a continuous conduction mode or a boundary conduction mode and the second switching mode is a
discontinuous conduction mode; and

a switch mode selector configured to determine the current in an inductor of the SMPS based on a measurement of a voltage
across a sense resistor having a first terminal that is directly connected to the inductor of the SMPS and to ground and a
second terminal that is connected to the power switch and to set the switching mode of the switch toggling unit in accordance
with a peak current in the inductor of the SMPS,

wherein the switch mode selector is configured to:
set the switching mode of the switch toggling unit as the first switching mode when the peak current in the inductor of the
SMPS is greater than a first threshold; and

set the switching mode of the switch toggling unit as the second switching mode when the peak current in the inductor of the
SMPS is less than a second threshold, wherein the first threshold is the same as the second threshold.

US Pat. No. 9,154,126

HIGH VOLTAGE OUTPUT DRIVER

NXP B.V., Eindhoven (NL)...

1. A push-pull output driver circuit comprising:
a high-side driver circuit including two transistors connected between a power source and an output node, the transistors
connected to one another in anti-series and responsive to a first control signal;

a low-side driver circuit including two transistors connected between the output node and ground, the transistors connected
to one another in anti-series and responsive to a second control signal;

for the high-side driver circuit, a diode connected between the source and drain of one of the transistors, and another diode
connected between the source and drain of the other one of the transistors, the respective diodes being configured and arranged
to prevent current flow between the power source and output node in opposite directions;

for the low-side driver circuit, a diode connected between the source and drain of one of the transistors, and another diode
connected between the source and drain of the other one of the transistors, the respective diodes being configured and arranged
to prevent current flow between the output node and ground in opposite directions; and

wherein the high-side and low-side driver circuits respond to the first and second control signals for push-pull driving of
the output node, wherein the high-side driver circuit further includes a charge pump configured to apply a voltage to short
the gates and the connected source/drain active regions of the high-side driver circuit transistors.

US Pat. No. 9,362,898

RF POWER DETECTOR AND DETECTION METHOD

NXP B.V., Eindhoven (NL)...

1. An RF detector circuit, comprising:
an envelope detector having an output capacitor on which an envelope detection signal is provided;
a reference storage capacitor for storing a reference voltage;
a differential amplifier having a first input coupled to the output capacitor and a second input coupled to the reference
storage capacitor;

a reset circuit;
a charging circuit for charging the reference storage capacitor at a first rate; and
a discharge circuit for discharging the reference storage capacitor at a second, different, rate; and a controller, for controlling
the sequence of charging and discharging the reference storage capacitor to store an amplifier offset voltage on the reference
storage capacitor based on toggling of the amplifier output during the charging or discharging operation which has the slower
rate.

US Pat. No. 9,356,457

WIRELESS CHARGING USING PASSIVE NFC TAG AND MULTIPLE ANTENNA OF DIFFERING SHAPES

NXP B.V., Eindhoven (NL)...

1. A method of charging a rechargeable battery of a receiver by a charging pad, said receiver having NFC functionality and
being capable of being charged according to a predetermined battery charging standard, said method comprising:
receiving, via Near Field Communication (NFC), information from said receiver at a passive NFC tag of said charging pad about
said predetermined battery charging standard; and

in response to receiving said information at the passive NFC tag of the charging pad, causing said charging pad to charge
the rechargeable battery of said receiver according to said predetermined battery charging standard;

wherein said charging pad has at least two charging coils, one of the at least two charging coils being configured to facilitate
charging of a rechargeable battery according to a first battery charging standard and a different one of the at least two
charging coils being configured to facilitate charging of a rechargeable battery according to a second battery charging standard,
wherein the first battery charging standard is different from the second battery charging standard; and

wherein causing said charging pad to charge the rechargeable battery of said receiver according to said predetermined battery
charging standard comprises choosing at least one of said at least two charging coils for charging the rechargeable battery
of the receiver according to said predetermined battery charging standard.

US Pat. No. 9,466,599

STATIC CURRENT IN IO FOR ULTRA-LOW POWER APPLICATIONS

NXP B.V., Eindhoven (NL)...

1. An input/output (IO) circuit comprising:
an IO driver circuit;
an electrostatic discharge (ESD) protection semiconductor switch with a first input configured to receive an ESD, a second
input connected to an ESD rail, and a switch control input;

an ESD trigger circuit connected to the switch control input, wherein the ESD trigger circuit is configured to produce a trigger
signal to close the ESD protection semiconductor switch when an ESD detection circuit detects the ESD;

a bias circuit configured to provide a back bias signal to an isolated well of the ESD protection semiconductor switch when
the IO driver circuit is in normal operation; and

an output semiconductor switch connected between the ESD trigger circuit and the switch control input, wherein the output
semiconductor switch is configured to isolate the ESD trigger circuit from the back bias signal the ESD protection semiconductor
switch is an NMOS device and the back bias signal is negative relative to a ground, and the output semiconductor switch is
configured to isolate the ESD trigger circuit from the negative back bias signal.

US Pat. No. 9,755,679

LOAD DEPENDENT RECEIVER CONFIGURATION

NXP B.V., Eindhoven (NL)...

1. A communication device, comprising:
a receiver, wherein the receiver includes an analog RF receiver frontend, an analog-to-digital converter (ADC) coupled to
the analog RF receiver frontend, and a digital signal processing unit coupled to the ADC;

a transmitter comprising an analog RF transmitter frontend;
a sensor to measure antenna detuning, wherein the sensor is configured to monitor at least one of a voltage and a current
in a signal path coupled to an antenna and matching network;

a memory;
a plurality of receiver configurations stored in the memory, wherein each of the plurality of receiver configurations include
parameter-value pairs; and

a control unit, coupled to the sensor and the receiver, to select a receiver configuration from the plurality of receiver
configurations based on an output of the sensor, wherein the control unit is configured to configure the receiver by altering
values of receiver control parameters according to the parameter-value pairs.

US Pat. No. 9,331,678

LOCAL OSCILLATOR SIGNAL GENERATION

NXP B.V., Eindhoven (NL)...

1. A local oscillator signal generation circuit for a frequency divider circuit comprising:
a delay device adapted to delay a data signal according to a control signal;
a data flip-flop having the delayed data signal provided to its data input terminal and a reference clocking signal provided
to its clock input terminal; and

a control circuit adapted to generate first and second partially overlapping pulse windows from the delayed data signal and
to generate the control signal based on the first and second partially overlapping pulse windows and the reference clocking
signal,

wherein the control signal is provided to the delay device to control the amount by which the data signal is delayed so that
the data signal is stable when it is sampled by the data flip-flop, and wherein a local oscillator signal is derived from
the output of the data flip-flop.

US Pat. No. 9,723,678

METHODS OF CONTROLLING RGBW LAMPS, RGBW LAMPS AND CONTROLLER THEREFOR

NXP B.V., Eindhoven (NL)...

1. A method of controlling a lamp comprising first, second and third colour LEDs and a white LED,
the method comprising:
characterising the variation of chromaticity and luminosity of each of the LEDs as a function of temperature over an operating
temperature range;

defining each of a virtual first, virtual second and virtual third LED, such that the chromaticity of each virtual LED is
achieved by combining component light from the first, second and third LEDs for all temperatures within the operating range;

defining a virtual white LED, such that the chromaticity of the virtual white LED is achieved by combining light from the
white LED with light from a two of the first, second and third LEDs, for all temperatures within the operating range;

receiving data representative of a requested setting R, G, B of each of three primary colours, thereby defining a requested
chromaticity and a requested luminance;

determining an operating temperature of each LED;
determining a virtual white control setting corresponding to a maximum fraction of a total luminance at the requested chromaticity
which is provided by the virtual white LED;

determining a control setting for each of the respective first, second and third virtual LEDs, in dependence on the difference
between the requested setting of the respective primary colour and the control setting of the virtual white LED;

controlling each of the first, second and third LED with a respective output control setting which is a sum of the respective
first LED, second LED or third LED component light of the virtual white, virtual first, virtual second and virtual third LED
control settings at the operating temperature;

and controlling the white LED with an output control setting which is the white LED component of the virtual white LED.

US Pat. No. 9,268,351

CASCODE SEMICONDUCTOR DEVICE FOR POWER FACTOR CORRECTION

NXP B.V., Eindhoven (NL)...

1. A semiconductor device, comprising first and second field effect transistors arranged in a cascode configuration:
wherein the first field effect transistor is a depletion mode transistor having a leakage current in operation;
wherein the second field effect transistor comprises an inherent drain to source resistance and additional drain to source
resistance arranged in parallel to the first drain to source resistance, the second additional drain to source resistance
arranged such that in operation current through the additional resistance matches the leakage current of the first field effect
transistor; and

whereby a gate of the first field effect transistor is connected to the drain of the second field effect transistor; and
wherein the second additional drain to source resistance is a resistive divider, and comprises at least two resistances connected
as a voltage divider having a common node, wherein the common node of the voltage divider is connected to the gate of a third
field effect transistor.

US Pat. No. 9,961,739

CONTROLLER FOR A LAMP

NXP B.V., Eindhoven (NL)...

1. A controller for a lamp, comprisingan input terminal configured to receive
a requested-colour-signal representative of a requested-colour-value to be provided by the lamp; and
one or more temperature-values associated with the lamp;
an output terminal configured to provide a lamp-control-signal to the lamp;
a full-colour-module configured to provide a full-colour-lamp-control-signal for the output terminal;
a stabilization-module configured to provide a stabilized-lamp-control-signal for the output terminal; and
a mode controller configured to compare the requested-colour-value with a threshold value, and
if the requested-colour-value satisfies the threshold value, then instruct the stabilization-module to provide the stabilized-lamp-control-signal to the output terminal;
if the requested-colour-value does not satisfy the threshold value, then instruct the full-colour-module to provide the full-colour-lamp-control-signal to the output terminal;
wherein the stabilization-module is configured to
generate stabilized-colour-values based on the temperature-values; and
provide the stabilized-lamp-control-signal based on the requested-colour-value and the stabilized-colour-values; and
wherein the full-colour-module is configured to
provide the full-colour-lamp-control-signal based on the requested-colour-value.

US Pat. No. 9,237,619

DIMMABLE LED LIGHTING CIRCUITS, CONTROLLERS THEREFOR AND A METHOD OF CONTROLLING A DIMMABLE LED LIGHTING CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A controller, for a dimmable LED lighting circuit comprising an arrangement of at least one LED of a first type connected
in series with at least one LED of a second type, the controller comprising a control circuit, a bypass circuit and a further
bypass circuit and being operable for controlling a current,
the current being separable into a first part and a second part, and being further separable into a further first part and
a further second part,

wherein the controller is configured to direct the first part through the at least one LED of the second type and direct the
second part through the bypass circuit,

wherein the controller is configured to direct the further first part through the at least one LED of the first type and direct
the further second part through the further bypass circuit, and

wherein the control circuit is configured to adjust, in dependence on an indication of a dimming level of the LED lighting
circuit, a current ratio which is at least one of (a) the ratio between the first part and the second part, and (b) the ratio
between the further first part and the further second part.

US Pat. No. 9,201,720

FLEXRAY NETWORK RUNTIME ERROR DETECTION AND CONTAINMENT

NXP B.V., Eindhoven (NL)...

11. A FlexRay network guardian comprising:
a resetting leading coldstart node (RLCN) detector configured to detect a RLCN failure;
a deaf coldstart node (DCN) detector configured to detect a DCN failure;
a babbling idiot (BI) detector configured to detect a BI failure;
a FlexRay network decoder connected to the RLCN detector, DCN detector, and BI detector;
a protocol operation control device connected to the FlexRay network decoder, RLCN detector, DCN detector, and BI detector;
a macrotick generation device connected to the protocol operation control device, RLCN detector, DCN detector, and BI detector;
a clock synchronization processing device connected to the protocol operation control device, macrotick generation device,
RLCN detector, DCN detector, and BI detector;

a frame and symbol processing device connected to the protocol operation control device,
clock synchronization processing device, FlexRay network decoder, RLCN detector, DCN detector, and BI detector;
a media access control device connected to the protocol operation control device, macrotick generation device, frame and symbol
processing device, RLCN detector, DCN detector, and BI detector,

wherein the RLCN detector, DCN detector, and BI detector receive signals regarding the status of the FlexRay network from
the media access control device, the macrotick generation device, the frame and symbol processing device, the clock synchronizing
processing device, FlexRay network decoder, and the protocol operation control device,

wherein the RLCN detector, DCN detector, and BI detector are configured to send an indication of a failure to a containment
module.

US Pat. No. 9,066,226

INITIALIZATION OF EMBEDDED SECURE ELEMENTS

NXP B.V., Eindhoven (NL)...

1. A method for initializing a secure element for use with a host unit, the method comprising:
storing a set of initial keys and a master key in a memory of the secure element;
receiving an identifier of the host unit associated with the secure element;
generating a modified set of keys based on the initial set of keys, the master key, and the identifier of the host unit;
storing the modified set of keys in the memory of the secure element; and
deleting the set of initial keys from the memory of the secure element.

US Pat. No. 9,349,645

APPARATUS, DEVICE AND METHOD FOR WAFER DICING

NXP B.V., Eindhoven (NL)...

1. An apparatus for wafer dicing, comprising:
a wafer holding device having a first temperature, the wafer holding device configured to hold a wafer that includes multiple
dies;

a die separation bar moveably coupled to the wafer holding device such that a portion of the wafer can be bent over the die
separation bar to fracture an attachment material and to create a set of separated dies; and

a cooling device coupled to the apparatus and having a second temperature which enables the die separation bar to fracture
the attachment material in response to movement of the die separation bar with respect to the wafer holding device.

US Pat. No. 9,569,386

METHOD AND SYSTEM FOR SINGLE-LINE INTER-INTEGRATED CIRCUIT (I2C) BUS

NXP B.V., Eindhoven (NL)...

1. An inter-integrated circuit (I2C) compatible device comprising:
a serial data line (SDA) interface for connection to an SDA line of a bus;
a single-line I2C module configured to:
transmit a sync word from the SDA interface over the SDA line of the bus, wherein the sync word is a SYNC BYTE+Not Acknowledge
(NACK) bit; and

following transmission of the sync word, transmit I2C data from the SDA interface over the SDA line of the bus such that digital
data is communicated over the bus via a single line, wherein the next byte that is transmitted from the SDA interface over
the SDA line of the bus following the sync word is a 7 bit slave address plus a data direction bit formatted according to
the I2C specification, wherein the data direction bit indicates either a write operation or a read operation.

US Pat. No. 9,473,110

ANTENNA RESONANCE FREQUENCY CONTROL USING AN ACTIVE RECTIFIER OR A DRIVER STAGE

NXP B.V., Eindhoven (NL)...

1. An antenna control circuit comprising:
an H-bridge circuit including three half-bridge circuits; and
a controller configured to control the H-bridge circuit;
wherein a first half-bridge circuit and a second half-bridge circuit of the three half-bridge circuits are configured to electrically
connect across a resonant antenna with a first resonant frequency and a second resonant frequency;

wherein a third half-bridge circuit is configured to electrically connect to a first capacitance connected to the resonant
antenna, wherein the controller is configured to control the third half-bridge circuit to switch the connection of the first
capacitance to the resonant antenna to a first position that changes the resonant frequency of the resonant antenna to the
first resonant frequency;

wherein the resonant antenna comprises a second capacitance and an inductor coil, wherein the second capacitance is in parallel
with the inductor coil.

US Pat. No. 9,375,711

SENSOR AND A METHOD OF ASSEMBLING A SENSOR

NXP B.V., Eindhoven (NL)...

13. An apparatus comprising:
a micro-fluidic structure having sidewalls that define a fluidic channel;
a bio-sensor configured and arranged with the micro-fluidic structure to form a cavity in which the fluid flows via the fluidic
channel, the bio-sensor including

a nanoelectrode, and
a bio-receptor coupled to the nanoelectrode and interfacing with the fluidic channel, the bio-receptor being configured and
arranged to chemically interact with target biologically-active molecules in the fluidic channel, and to impart an impedance
characteristic to the nanoelectrode that is based upon the chemical interaction with the target molecules;

an electrical contact electrically connected to the nanoelectrode and isolated from contact with the fluid in the fluidic
channel; and

a clamp including a spring component and configured and arranged to, in response to pressing of the micro-fluidic structure
to the bio-sensor, clamp the micro-fluidic structure to the bio-sensor and to, via the clamping and spring force applied via
the spring component, form the cavity and a liquid-tight seal that confines the fluid within the cavity.

US Pat. No. 9,159,224

WIRELESS POWER AND DATA APPARATUS, SYSTEM AND METHOD

NXP B.V., Eindhoven (NL)...

1. For use with wireless communications involving a resonant circuit having a resonant frequency susceptible to detuning,
an apparatus comprising:
a remote transponder circuit;
a transceiver circuit configured and arranged to
transmit radio frequency (RF) power to the remote transponder circuit, and
wirelessly communicate with the remote transponder circuit via first and second different carrier frequencies, using the resonant
circuit and the RF power, the first and second carrier frequencies being respectively set sufficiently proximate to the resonant
frequency such that signals communicated based on the resonant frequency can be acquired by demodulating based on the resonant
frequency; and

a frequency-selection circuit coupled to the transceiver circuit and configured and arranged to set the carrier frequency
to one of the first and second carrier frequencies based upon a signal sent from the transponder circuit, wherein the frequency-selection
circuit is configured and arranged to set the carrier frequency to one of the first and second carrier frequencies based upon
a determination of whether the signal sent from the transponder circuit passes or fails an error condition corresponding to
a threshold level at which the communicated signals can be acquired via the demodulating.

US Pat. No. 9,900,950

ADJUSTED PULSE WIDTH MODULATION (PWM) CURVE CALCULATIONS FOR IMPROVED ACCURACY

NXP B.V., Eindhoven (NL)...

1. An LED (light emitting diode) controller connectable to a string of LEDs, the LED controller comprising:
a light intensity calculator configured to calculate a sequential set of light intensity values, wherein the set of light
intensity values correspond to points on a desired light output curve; and

processing logic configured to:
initialize a scaling parameter of the light intensity calculator with a present scaling value, wherein the present scaling
value indicates a first number of steps over which the desired light output curve extends,

dynamically receive a subsequent scaling value at a change time after the light intensity calculator has begun calculation
of the set of light intensity values according to the present scaling value, wherein the subsequent scaling value indicates
a second number of steps over which the desired light output curve extends, and

change the scaling parameter of the light intensity calculator to the subsequent scaling value before the light intensity
calculator has completed calculation of the set of light intensity values, wherein

the light intensity calculator is configured to calculate a next light intensity value immediately after the change time according
to the subsequent scaling value, and

a difference between the next light intensity value and a previous light intensity value calculated immediately before the
change time is within a flicker threshold.

US Pat. No. 9,509,306

TAMPER RESISTANT IC

NXP B.V., Eindhoven (NL)...

1. A method for manufacturing an integrated circuit comprising implementing a physical unclonable function at least partially
in a passivation layer of said integrated circuit comprising:
(a) providing a basic structure which comprises a pad for external connections, internal connections and PUF detector connections;
(b) covering the basic structure, except the PUF detector connections, with photoresist layer;
(c) randomly distributing conducting particles over the entire resulting surface;
(d) removing the photoresist layer such that only the particles which are substantially above the PUF detector connections
remain on the surface;

(e) depositing the passivation layer on all elements except the pad for the external connections.

US Pat. No. 9,355,056

COMMUNICATION APPARATUS WITH SLEW RATE FEEDBACK

NXP B.V., Eindhoven (NL)...

1. An apparatus for communicating in a network including a master circuit and a plurality of slave circuits on bus that is
controlled by the master circuit corresponding to master and slave data communication, the apparatus comprising:
a feedback circuit configured and arranged to provide a feedback signal indicative of a slew rate and bit time of signals
communicated in the network between the master and slave circuits on the bus; and

a data-transmission circuit responsive to an input signal and a feedback signal received from the feedback circuit, the data-transmission
circuit configured and arranged to

communicate data over the bus using control provided by the master circuit, and
transmit data on the bus by generating output signals via a waveform corresponding to the input signal, and controlling the
waveform based upon the slew rate and bit time on the bus and indicated via the feedback signal,

wherein the data-transmission circuit is configured and arranged to control the waveform based upon deviations in the slew
rate and bit time indicated via the feedback signal.

US Pat. No. 10,021,744

DUAL OUTPUT POWER CONVERTER AND METHOD FOR OPERATING A DUAL OUTPUT POWER CONVERTER

NXP B.V., Eindhoven (NL)...

1. A power converter comprising:a dual output resonant converter including a first output, a second output, a common mode control input, and a differential mode control input,
wherein a voltage/current at the first output and a voltage/current at the second output are controlled in response to a common mode control signal received at the common mode control input and a differential mode control signal received at the differential mode control input; and
a dual output controller including a first error signal input, a second error signal input, a common mode control output, and a differential mode control output,
wherein the dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to a first error signal received at the first error signal input and a second error signal received at the second error signal input,
wherein the first error signal is a function of the voltage/current at the first output and the second error signal is a function of the voltage/current at the second output, and
wherein the common mode control signal is output from the common mode control output and the differential mode control signal is output from the differential mode control output;
wherein (VcapH+VcapL)/2 of the dual output resonant converter is a function of the common mode control signal and Vbus/2?(VcapH?VcapL)/2 of the dual output resonant converter is a function of the differential mode control signal; and
wherein VcapH is a voltage at a specific node in a resonant tank of the dual output resonant converter when a high side switch of the dual output resonant converter is on and VcapL is a voltage at a specific node in the resonant tank of the dual output resonant converter when a low side switch of the dual output resonant converter is on.

US Pat. No. 9,203,016

MANUFACTURING MAGNETIC SENSOR ELEMENTS MONOLITHICALLY INTEGRATED AT A SEMICONDUCTOR CHIP COMPRISING AN INTEGRATED CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A method for manufacturing a magnetic sensor module having magnetic sensor elements monolithically integrated at a semiconductor
chip which comprises an integrated circuit, the method comprising
providing a composite semiconductor arrangement comprising (i) the semiconductor chip, (ii) contact elements for the integrated
circuit, which are formed on the semiconductor chip, and (iii) a dielectric layer formed over the semiconductor chip and over
the contact elements,

forming a magnetic sensor layer by providing the material for the magnetic sensor elements monolithically over the dielectric
layer,

exposing the contact elements by removing a part of the dielectric layer which part is located above the contact elements,
and

forming an electric conductive protection layer over either the formed magnetic sensor layer or the exposed contact elements
in order to prevent negative interactions between (i) the step of forming the magnetic sensor elements resulting from the
magnetic sensor layer and (ii) the step of exposing the contacting elements.

US Pat. No. 9,360,913

METHOD OF PROVIDING A CLOCK FREQUENCY FOR A PROCESSOR

NXP B.V., Eindhoven (NL)...

1. A method of providing a clock frequency to a processor, said method comprising:
determining an actual load of said processor;
determining a control value, the control value relating to a desired first frequency, from the deviation of said actual load
to a preset target processor load

providing at least one reference signal;
using a second signal as input for a noise shaper, said second signal relating to said control value;
generating a first signal having said first frequency by combining the output signal of said noise shaper with one of the
at least one reference signals; and

using said first frequency as clock frequency for said processor.

US Pat. No. 9,276,535

TRANSCONDUCTANCE AMPLIFIER

NXP B.V., Eindhoven (NL)...

1. A transconductance amplifier, comprising:
An input amplifier stage;
an output amplifier stage; and
a replica output stage which generates a feedback current which is a scaled replica of the output current of the amplifier,
wherein the feedback current is provided to the amplifier input; and wherein the input amplifier stage comprises a first inverter
and a second inverter in series, the second inverter providing a drive signal, and the amplifier output stage and replica
output stage are driven in parallel each by the drive signal.

US Pat. No. 9,129,671

SEMICONDUCTOR DEVICE IDENTIFIER GENERATION METHOD AND SEMICONDUCTOR DEVICE

NXP B.V., Eindhoven (NL)...

1. A method of generating an identifier from a semiconductor device comprising a volatile memory having a plurality of memory
cells, the method comprising:
(a) causing the memory cells to assume a first plurality of pseudo-random bit values inherent to variations in the microstructure
of the memory cells;

(b) retrieving, by a processor circuit, the pseudo-random bit values from at least a subset of the plurality of memory cells;
(c) causing the memory cells to assume at least a second plurality of pseudo-random bit values inherent to variations in the
microstructure of the memory cells; and

(d) generating the identifier by averaging at least some of the first plurality pseudo-random bit values and the at least
second plurality of pseudo-random bit values.

US Pat. No. 9,112,415

CONTROL OF A HALF RESONANT CONVERTER FOR AVOIDING CAPACITIVE MODE

NXP B.V., Eindhoven (NL)...

14. A method for controlling an energy converter having a switching frequency and a switching phase, a first switch, a second
switch, a half-bridge node therebetween, and an oscillator, the method comprising
opening the first switch whilst the second switch is open,
monitoring a parameter indicative of a state of the energy converter, including monitoring the polarity of a current in the
resonant circuit,
and both
(a) delaying closing the second switch;
(b) retarding the switching phase by interrupting oscillation of the oscillator in response to the parameter exhibiting a
first characteristic when the first switch is opened wherein the first characteristic is an undesired polarity of the current
in the resonant circuit;

closing the second switch in response to the parameter exhibiting a second characteristic within a third predetermined period
which starts immediately after the first switch is opened, wherein the second characteristic is an opposite polarity of the
current in the resonant circuit; and

increasing the switching frequency in response to the parameter exhibiting the first characteristic throughout a second predetermined
period which starts immediately after the first switch is opened.

US Pat. No. 9,466,688

SEMICONDUCTOR DEVICE WITH MULTILAYER CONTACT AND METHOD OF MANUFACTURING THE SAME

NXP B.V., Austin, TX (US...

1. A method of constructing a bipolar transistor semiconductor device, comprising:
forming a first substrate layer including a collector region of a first conductivity type;
forming a second substrate layer over and on the first substrate layer including a base region of a second conductivity type
in an active area of the second substrate layer;

embedding an emitter region of the first conductivity type in a top surface of the base region;
depositing a metal emitter contact over and on the emitter region;
depositing a metal base contact over and on the base region;
forming an isolation layer over and on the second substrate layer, wherein the isolation layer separates the metal emitter
contact and the metal base contact;

forming a passivation layer over and on the metal base contact and over and on the metal emitter contact region and over and
on the isolation layer; and

depositing a metal emitter contact extension over and on the metal emitter contact region, wherein the metal emitter contact
extension extends through an opening in the passivation layer above the metal emitter contact, a bottom surface of the metal
emitter contact extension in contact with an upper surface of the metal emitter contact is oriented in a first plane, and
the metal emitter contact includes a step extending above the first plane.

US Pat. No. 9,185,417

VIDEO DECODING SWITCHABLE BETWEEN TWO MODES

NXP B.V., Eindhoven (NL)...

1. A video decoder apparatus configured to decode a motion-compensated transform-coded video stream, wherein the video decoder
apparatus comprises:
a first video decoder configured to decode the video stream at a first resolution, wherein a motion-compensation step of the
decoding is performed in an image-domain; and

a second video decoder configured to decode the video stream at a second resolution, wherein the motion-compensation step
is performed in a transform-domain after removal of high frequency data samples; and

a switch configured to switch the video decoder apparatus between the first video decoder and the second video decoder while
decoding the video stream.

US Pat. No. 9,105,687

METHOD FOR REDUCING DEFECTS IN SHALLOW TRENCH ISOLATION

NXP B.V., Eindhoven (NL)...

1. A method of manufacturing a semiconductor device, the method comprising:
forming a trench that includes a needle defect;
depositing a high density plasma oxide and a liner oxide over the trench including the needle defect;
removing the part of the high density oxide and the liner oxide over the needle defect by applying an oxide etch; and
after the step of applying the oxide etch, etching back the needle defect by applying a silicon etch.

US Pat. No. 9,485,609

PULSE FREQUENCY CONTROL FOR WIRELESS COMMUNICATIONS AND RANGING

NXP B.V., Eindhoven (NL)...

7. A method for providing a security function that relies upon distance bounding between a pair of devices, the method comprising:
generating, using a clock circuit, a clock signal having a base frequency that is within an expected frequency range;
selecting, using a frequency adjustment circuit and based upon a frequency offset value, a particular frequency adjustment
value from a plurality of frequency adjustment values;

providing an adjusted clock signal having a frequency corresponding to the base frequency as modified by the particular frequency
adjustment value, the particular frequency adjustment value being sufficiently large to result in the adjusted clock signal
being outside of the expected frequency range;

receiving, at a wireless communication circuit, wireless communication signals;
identifying, from the wireless communication signals, a set of received wireless communication pulses that have a pulse repetition
frequency that corresponds to the adjusted clock signal; and

applying, using a processing circuit, a distance ranging protocol to the identified set of received wireless communication
pulses to verify the identified set of received wireless communication pulses as part of a cryptographic authentication process.

US Pat. No. 9,318,913

METHOD OF CONTROLLING A POWER TRANSFER SYSTEM AND POWER TRANSFER SYSTEM

NXP B.V., Eindhoven (NL)...

1. A method of controlling a power transfer system for wireless charging of a battery power source of a portable device by
a power transfer device comprising:
initiating the data communication link between said power transfer device and said portable device,
requesting said portable device to transmit identification information via said data communication link to said power transfer
device,

detecting whether said identification information of said portable device is received by said power device or not,
setting a charging power to be transferred to said portable device, said charging power not exceeding a first predetermined
value when said identification information is not received by said power transfer device, and

establishing a power transfer link by said power transfer device to transfer said charging power to said portable device.

US Pat. No. 9,304,152

CURRENT MONITORING CIRCUITS AND METHODS

NXP B.V., Eindhoven (NL)...

1. A current monitoring circuit, comprising:
a main transistor arrangement for connection in series with a load;
a set of measurement branches in parallel with the main transistor arrangement, each measurement branch comprising a series
resistor and switch for controlling the connection of the branch into circuit;

a gate controller for controlling the switching of the main transistor arrangement and branch switches; and
a sense amplifier for measuring a current through the load based on the current flowing through the main transistor arrangement
or a branch.

US Pat. No. 9,974,132

CIRCUITS, CONTROLLERS AND METHODS FOR CONTROLLING LED STRINGS OR CIRCUITS

NXP B.V., Eindhoven (NL)...

1. A controller for controlling a string of N LEDs connected in series and each having a current bypass switch in parallel therewith and configured to be supplied from a current source connected in series with the string of LEDs and being supplied by a supply voltage, the controller comprising:a respective bypass switch controller for each current bypass switch and configured to control the current bypass switch such that the respective LED has an on-period and an off-period, according to a common duty cycle;
a phase control unit configured to set a respective timing of each of the current bypass switches such that the fraction of LEDs not bypassed corresponds to the common duty cycle; and
a duty cycle adjustor configured to adjust the common duty cycle, in dependence on the supply voltage, and further configured to provide a duty cycle reference signal indicative of the common duty cycle to each respective bypass switch controller, wherein the duty cycle adjustor comprises a comparator configured to compare a voltage across the current source with a headroom voltage, and wherein the duty cycle adjustor is configured to: (a) periodically increase the duty cycle reference signal, (b) compare the voltage across the current source with the headroom voltage, and (c) decrease the duty cycle reference signal in response to the voltage across the current source being less than the headroom voltage.

US Pat. No. 9,622,303

CURRENT MIRROR AND CONSTANT-CURRENT LED DRIVER SYSTEM FOR CONSTANT-CURRENT LED DRIVER IC DEVICE

NXP B.V., Eindhoven (NL)...

1. A current mirror for a constant-current light-emitting diode (LED) driver system, the current mirror comprising:
at least one current mirror cell, wherein each of the at least one current mirror cell comprises:
a plurality of semiconductor circuits configured to generate an output current based on a reference current; and
a control module configured to alternately and continuously charge the semiconductor circuits in response to a plurality of
non-overlapping clock signals;

wherein the semiconductor circuits include first and second semiconductor circuits, which are connected to a voltage rail,
to a reference current signal path from which the reference current is received, and to a current output signal path to which
the output current is output;

wherein the control module comprises a first control circuit and a second control circuit,
wherein the first control circuit comprises a first set of switches connected to a gate terminal of the first semiconductor
circuit, connected to the reference current signal path, and connected to the current output signal path, and

wherein the second control circuit comprises a second set of switches connected to a gate terminal of the second semiconductor
circuit, connected to the reference current signal path, and connected to the current output signal path.

US Pat. No. 9,506,969

NOISE SENSOR

NXP B.V., Eindhoven (NL)...

1. A common mode noise sensor with a single amplification path comprising:
first and second terminals for receiving respective first and second signals from a power supply;
an amplifier stage connected to the first and second terminals and having an output; and
a resistor network connected to the amplifier stage, the resistor network arranged such that the output of the amplifier stage
is configured to provide an output signal in which a differential mode noise in the first and second signals is suppressed
in preference to a common mode noise in the first and second signals; and

wherein the resistor network comprises a first resistor, a second resistor, a third resistor and a fourth resistor,
the first resistor connected in series with a filter capacitor between the first terminal and an inverting input,
the second resistor connected between the output and the inverting input,
the third resistor is connected between a non-inverting input and earth, and
the fourth resistor in connected between the non-inverting input and the second terminal.

US Pat. No. 9,338,817

REDUCTION OF DATA CORRUPTION IN WIRELESS SYSTEMS

NXP B.V., Eindhoven (NL)...

1. A method for managing a wireless Universal Serial Bus (USB) connection between a host device and a client device, the wireless
connection suitable for carrying data traffic between the host device and the client device according to a wireless USB specification,
the method comprising:
measuring, at the client device, the client device's remaining power supply capacity;
sending a low power notification from the client device to the host device when the remaining power supply capacity drops
below a first threshold power supply capacity, wherein the low power notification comprises a wireless USB Device Notification
(DN);

receiving the low power notification at the host device; and
closing the wireless USB connection between the client device and the host device to further data traffic in response to the
received low power notification;

wherein closing the wireless USB connection comprises sending a USB disconnect information element (IE) from the host device
to the client device.

US Pat. No. 9,077,571

ADAPTIVE EQUALIZER AND/OR ANTENNA TUNING

NXP B.V., Eindhoven (NL)...

1. A device for wirelessly communicating using an antenna, the device comprising:
a transmission circuit configured and arranged to transmit a first wireless signal using magnetic coupling between the antenna
and a remote device, the coupling occurring over a wireless medium;

a receiver circuit configured and arranged to receive a second wireless signal that is from the antenna and that represents
the first wireless signal as modified by the coupling occurring over the wireless medium;

an error circuit configured and arranged to generate an error signal by comparing the first wireless signal to the second
wireless signal; and

an equalizer circuit configured and arranged to pre-code the first wireless signal with coding that compensates for inter-symbol
interference by compensating for the error signal.

US Pat. No. 9,323,540

TASK EXECUTION DETERMINISM IMPROVEMENT FOR AN EVENT-DRIVEN PROCESSOR

NXP B.V., Eindhoven (NL)...

11. An event-driven processor comprising:
an instruction store configured to store an instruction set, wherein the instruction set comprises computer executable instructions
to implement a heartbeat timer within the event-driven processor; and

an operation code interpreter to configure the heartbeat timer and to handle an event based on the heartbeat timer, wherein
the operation code interpreter is configured to specify a first heartbeat period for the event-driven processor and to specify
a second heartbeat period for the event-driven processor after the first heartbeat period expires, wherein the second heartbeat
period is longer than the first heartbeat period, and wherein the second heartbeat period is twice the first heartbeat period.

US Pat. No. 9,318,428

CHIP HAVING TWO GROUPS OF CHIP CONTACTS

NXP B.V., Eindhoven (NL)...

1. A chip comprising:
a substrate,
an integrated circuit provided on the substrate,
a passivating layer that protects the integrated circuit and which is provided with through-holes,
a plurality of chip contacts formed by pads, which chip contacts are accessible from outside the chip through said through-holes
and connected to the integrated circuit, wherein at least some of the pads are connected to a corresponding bump of a particular
material extending through the passivating layer and configured and arranged to provide an external contact via an upper surface
of the corresponding bump when the chip is connected to an external package or chip,

additional chip contacts formed by additional bumps of, or including, the particular material resulting from a bumping process
used to apply the corresponding bumps, the corresponding bumps and the additional bumps being exposed and respectively configured
and arranged to couple the chip contacts to an external circuit, and

for each additional chip contact, connecting conductors formed by elongated connecting bumps of, or including, the particular
material on the passivating layer and electrically connecting the additional chip contact to one of the corresponding bumps,
and wherein the height of one of the corresponding bumps is greater than the height of one of the elongated connecting bumps
and the height of one of the additional bumps to which the one of the corresponding bumps is respectively connected, wherein
the heights are defined as a distance of the particular material above a plane in which an upper surface of the passivating
layer lies,

the particular material over the passivating layer consisting of a single material having a height defined by a thickness
of the particular material extending uninterrupted between a lower surface of the particular material in direct contact with
the passivating layer, and an upper surface of the particular material.

US Pat. No. 9,219,419

SWITCHED MODE POWER SUPPLIES

NXP B.V., Eindhoven (NL)...

1. A switched-mode power supply comprising:
a transformer with a first winding and a second winding;
a transmitter configured to:
detect a detectable variable (Vout) at the first winding,
generate a transformer relayed signal in accordance with the detectable variable (Vout), and
provide the transformer relayed signal to the first winding; and
a receiver configured to:
receive the transformer relayed signal from the second winding, and
control a controllable variable at the second winding in response to the transformer relayed signal,
wherein the transformer relayed signal is a symbol stream comprising a plurality of symbols.

US Pat. No. 9,202,588

1T COMPACT ROM CELL WITH DUAL BIT STORAGE FOR HIGH SPEED AND LOW VOLTAGE

NXP B.V., Eindhoven (NL)...

1. A ROM memory device, comprising:
a plurality of rows and columns of memory cells, each memory cell including a bit line pair and a transistor to store two
bits of data therein; and

a virtual ground line disposed between adjacent pairs of bit line pairs, wherein the bit line pair and virtual ground line
are configured to read data stored in the memory cells.

US Pat. No. 9,184,469

BATTERY

NXP B.V., Eindhoven (NL)...

1. A battery arrangement, comprising:
a carrier foil having a top major surface and a bottom major surface opposite the top major surface, wherein the top major
surface faces up when the bottom major surface faces down, with solid state batteries spaced along the carrier foil and mounted
on the opposite major surfaces of the carrier foil in pairs, with the solid state batteries of each pair mounted at the same
position along the length of the carrier foil but on the opposite major surfaces of the carrier foil,

wherein the carrier foil is folded to define a stack of solid state batteries in a meander pattern with battery pairs that
are adjacent each other along the carrier foil arranged back to back in the stack;

wherein the solid state batteries are electrically connected in series or parallel or a combination thereof by conductive
tracks on the carrier foil or by connection wires.

US Pat. No. 9,081,251

DISPLAY DEVICE

NXP B.V., Eindhoven (NL)...

1. A display device comprising:
a substrate having a plurality of apertures therein, the substrate having a first effective dielectric constant;
a dielectric material disposed within at least some of the apertures, the dielectric material having an adjustable second
effective dielectric constant;

an array of pixels, each pixel comprising an array of corresponding said apertures in the substrate, each aperture of the
array having a maximum opening dimension less than a wavelength of light at least one frequency;

a phase change material on top of the substrate configured and arranged to vary the second effective dielectric constant,
thereby to vary light transmission characteristics of the array of pixels between transmission of the at least one frequency
in the visible spectrum and transmission of substantially no frequency in the visible spectrum, wherein as a result of the
varying, the array of pixels transmit the at least one frequency in the visible spectrum through the apertures via surface
plasmon oscillation when the first effective dielectric constant is substantially same as the second effective dielectric
constant, and the array of pixels reflect the at least one frequency in the visible spectrum by perturbing surface plasmon
oscillation in the apertures when the first effective dielectric constant is substantially different from the second effective
dielectric constant.

US Pat. No. 9,071,160

POWER-DEPENDENT MAINS UNDER-VOLTAGE PROTECTION

NXP B.V., Eindhoven (NL)...

1. A method of controlling a mains-connected switched mode power supply comprising:
determining a signal indicative of a power drawn by the switched mode power supply, wherein the signal indicative of the power
drawn by the switched mode power supply is a control signal that is an input to an operational amplifier of the switched mode
power converter, which is connected to three current mirrors that are connected in series, and controls a timing of a switch
connected to a primary winding of a transformer of the switched mode power converter that is connected to the three current
mirrors through an auxiliary primary winding;

determining a signal indicative of a mains voltage;
determining whether a brown-out condition is met, in dependence on both the signal indicative of a power drawn and the signal
indicative of the mains voltage; and

in response to detecting a brown-out condition, disabling the switched mode power supply,
wherein the determining whether a brown-out condition is met comprises comparing a threshold signal with a difference between
a scaled version of the control signal and a scaled version of the signal indicative of the mains voltage,

and the brown-out condition is met if the difference does not exceed the threshold signal.

US Pat. No. 9,504,108

LOW-NOISE CURRENT REGULATION CIRCUITS

NXP B.V., Eindhoven (NL)...

11. A method, comprising:
generating a first clock signal with a frequency spectrum having a first frequency range;
generating a second clock signal by spreading frequency spectrum of the first clock signal to have a second frequency range
that is wider than the first frequency range;

providing a regulated voltage at a supply node as a function of the second clock signal; and
regulating current in a circuit path, from the supply node and passing through a load circuit, as a function of the first
clock signal.

US Pat. No. 9,450,755

TRANSPONDER, READER AND METHODS FOR OPERATING THE SAME

NXP B.V., Eindhoven (NL)...

1. Method for operating a transponder, the method comprising:
receiving transmitted reader data by the transponder, the reader data comprising a representation of x a representation of
sqrt[b]/x, redundant information associated with x, and redundant information associated with sqrt[b]/x, wherein x is an element
of a binary Galois field and b is a constant;

determining, by the transponder, whether x is a first coordinate of a point on an elliptic curve defined by the elliptic curve
equation y2+xy=x3+ax2+b by determining (if Trace(x)==Trace(a) and if Trace (?b/x)==0;

calculating a product from the redundant information associated with x and the redundant information associated with sqrt[b]/x;
and

determining if redundant information in the calculated product is known by the transponder;
wherein the elliptic curve is defined over the Galois field such that x and y are elements of the Galois field,
wherein y is a second coordinate of the point on the elliptic curve.

US Pat. No. 9,391,187

SEMICONDUCTOR HETEROJUNCTION DEVICE

NXP B.V., Eindhoven (NL)...

1. A heterojunction semiconductor device comprising:
a substrate;
a multilayer structure disposed on the substrate, the multilayer structure comprising:
a first layer comprising a first semiconductor disposed on top of the substrate;
a second layer comprising a second semiconductor disposed on top of the first layer to define an interface between the first
layer and the second layer, wherein the second semiconductor is different from the first semiconductor such that a Two-Dimensional
Electron Gas (2DEG) forms adjacent to the interface;

a first terminal electrically coupled to a first area of the interface between the first layer and second layer;
a second terminal electrically coupled to a second area of the interface between the first layer and second layer, and
an electrically conducting channel comprising at least one metallic conducting channel in contact with the first layer, wherein
the electrically conducting channel connects the second terminal and a region of the first layer such that electric charge
can flow between the second terminal and the first layer.

US Pat. No. 9,357,322

LOUDSPEAKER POLARITY DETECTOR

NXP B.V., Eindhoven (NL)...

1. A method comprising the steps of:
determining a plurality of impedance values of a loudspeaker, each of the impedance values corresponding to a different input
signal or input signal portions provided to the loudspeaker; and

determining the polarity of the loudspeaker based on the impedance values.

US Pat. No. 9,336,823

PLAYING AUDIO IN TRICK-MODES

NXP B.V., Eindhoven (NL)...

1. A method of playing a digital audio signal at a speed different from that at which it was recorded, the method comprising:
playing a first segment of the digital audio signal;
skipping to a second segment of the digital audio signal that is not contiguous with the first segment; and
playing the second segment,
wherein at least one of the first and second segments is played at a rate different from the rate at which the at least one
of the first and second segments was recorded, and wherein the rate is sample rate.

US Pat. No. 9,332,347

CONTROL OF A LOUDSPEAKER OUTPUT

NXP B.V., Eindhoven (NL)...

1. A method of controlling an output of a loudspeaker, comprising:
Measuring a coil voltage and a coil current over time;
Deriving an admittance function using the coil voltage and the coil current overtime;
Calculating an input-voltage-to-excursion transfer function over time from the admittance function, a blocked electrical impedance
and a force factor;

Using the input-voltage-to-excursion transfer function over time to predict a coil excursion; and
Using the coil excursion to control audio processing of the loudspeaker.

US Pat. No. 9,329,622

CYCLE STEALING WHEN A PROCESS OR ENVIRONMENTAL VARIATION IS DETECTED AND A PROCESSING INSTRUCTION IS USING A CRITICAL PATH

NXP B.V., Eindhoven (NL)...

1. A clock control circuit for controlling a clock signal used by a processing system which receives processing instructions,
comprising:
a sensor arrangement for sensing process or environmental variations and determining therefrom whether or not cycle stealing
may be required;

a detector arrangement for determining if a processing instruction uses a critical path in the processing system; and
a clock control unit for implementing cycle stealing when it is determined by the sensor arrangement that cycle stealing may
be required and when it is determined by the detector arrangement that the processing instruction uses a critical path.

US Pat. No. 9,305,537

SIGNAL PROCESSING APPARATUS CONCEALING IMPULSE NOISE BY AUTOREGRESSIVE MODELING

NXP B.V., Eindhoven (NL)...

1. A signal processing apparatus comprising:
a noise detector configured to:
receive a stream of information representative of a stream of audio signal samples;
detect samples in the received stream of information that are distorted by impulse noise in order to generate a noise detection
signal, wherein the noise detection signal also identifies preceding and succeeding samples that are undistorted; and

a processor configured to:
receive a stream of information representative of the stream of audio signal samples;
receive the noise detection signal from the noise detector;
determine, based on preceding and/or succeeding undistorted samples in the received stream of audio signal samples, auto-regressive
model parameters;

apply the auto-regressive model parameters to the preceding undistorted samples to determine forward linear predicted values
of the distorted samples;

apply the auto-regressive model parameters to the succeeding undistorted samples to determine backward linear predicted values
of the distorted samples;

combine the forward and backward linear predicted values by means of a window function to determine composite predicted values
of the distorted samples;

replace the distorted samples in the received stream of information with the composite predicted values to provide a reconstructed
stream of audio signal samples; and

determine the stability of the auto-regressive model parameters, and if the stability is determined to be below a predetermined
threshold value then replace the estimated auto-regressive model parameters with previously determined stable auto-regressive
model parameters for further processing.

US Pat. No. 9,252,673

CONTROLLER

NXP B.V., Eindhoven (NL)...

1. A controller for a switched mode power supply, SMPS, comprising:
a first terminal for receiving a controller input voltage;
a second terminal for coupling to ground;
a selectably engagable load;
a load selector configured to:
engage the selectably engagable load between the first and second terminals in order to draw a selectably engagable load current,
and

disengage the selectably engagable load from the first and second terminals in accordance with a comparison between a disengagement
threshold and the controller input voltage or a controller input current at the first terminal.

US Pat. No. 9,174,648

SYSTEM FOR USING SHORT TEXT MESSAGING FOR REMOTE DIAGNOSTIC

NXP B.V., Eindhoven (NL)...

1. A system configured to be incorporated in a vehicle, the system comprising:
a communication system including a text messaging communication hardware to receive a message via a text messaging service,
wherein the message text includes a command and a source identifier; and

a microcontroller, coupled to the communication system and a machine control system, to execute the command through the machine
control system, wherein the machine control system is configured to control components of the vehicle and the microcontroller
is configured to determine if, based on the source identifier included in the message, a configuration allows execution of
the received command and to return a response to the communication system.

US Pat. No. 9,161,123

CONTROL OF A MICROPHONE

NXP B.V., Eindhoven (NL)...

1. A microphone circuit comprising:
a microphone;
an analog to digital converter at the output of the microphone;
a clip detection circuit configured to detect when the analog to digital converter output has reached a threshold;
a variable attenuator coupled to the microphone;
a control circuit configured to control the variable attenuator based on output of the clip detection circuit; and
an overrule circuit configured to overrule the control circuit.

US Pat. No. 9,129,991

VERTICAL MOSFET TRANSISTOR WITH A VERTICAL CAPACITOR REGION

NXP B.V., Eindhoven (NL)...

1. A method of manufacturing an integrated circuit die, the method comprising:
providing a semiconductor substrate;
forming a first semiconducting layer of a first conductivity type on a first side of the semiconductor substrate;
forming a vertical MOSFET by:
forming a second semiconducting layer of a second conductivity type on a second side of the semiconductor substrate such that
the first and second semiconducting layers are separated by the substrate;

forming a gate trench in the second semiconducting layer, lining said gate trench with a dielectric layer and filling the
lined gate trench with a gate electrode material; and

forming a semiconducting region of a first conductivity type in the second semiconducting layer adjacent to said gate trench;
forming a plurality of trenches through said second semiconducting layer, a first one of said trenches delimiting said vertical
MOSFET;

filling the first one of said trenches with an electrically insulating material;
lining at least one further one of said trenches with an electrically insulating material and filling said lined further one
of said trenches with a conductive material, thereby defining a vertical capacitor having the first semiconducting layer as
a first plate and the conductive material as a second plate, wherein the region of the first conductivity type in the second
semiconducting layer adjacent the gate trench is a source of the vertical MOSFET and the first semiconducting region is a
drain of the vertical MOSFET; and

electrically isolating the second plate of the vertical capacitor from the source.

US Pat. No. 9,065,439

CLOCK BUFFER

NXP B.V., Eindhoven (NL)...

1. A tuneable buffer circuit for use in a clock tree, comprising:
a voltage sensor for sensing a supply voltage;
a set of at least two buffers coupled in parallel, each buffer having a grounding circuit for implementing a selectable grounding
function;

a bypass switch connected in parallel with the at least two buffers;
a switching arrangement for switching between different modes of operation in dependence on the sensed supply voltage, wherein
in a normal mode one buffer in the at least two buffers is connected into the tuneable buffer circuit;
in a first low voltage mode the at least two buffers are connected into the tuneable buffer circuit in parallel without a
grounding function;

in a second low voltage mode the at least two buffers connected into the tuneable buffer circuit in parallel with grounding
function; and

in a bypass mode the at least two buffers are bypassed by the bypass switch.

US Pat. No. 9,413,407

CONVERSION SYSTEM

NXP B.V., Eindhoven (NL)...

1. A radiofrequency (RF) apparatus comprising:
an RF signal input or output;a mixing module comprising a first plurality of Intermediate Frequency (IF) amplifiers, wherein at least one IF amplifier
is coupled to the RF signal input or output via a first switch and a first plurality of input or output signals to or from
the first plurality of IF amplifiers are not in quadrature;
a multi-phase local oscillator signal generator configured to provide a reconfigurable switching signal phase to said first
switch; and

a vector conversion module configured to transmit or receive the first plurality of input or output signals and receive or
provide a second plurality of input or output IF signals to or from a weighted sum of the first plurality of IF amplifier
input or output signals,

wherein at least one of the second plurality of the input or output IF signals is different from the first plurality of the
IF amplifier input or output signals; and

wherein the vector conversion module further comprises: a summing amplifier for at least one of the second plurality of input
or output IF signals, the summing amplifier connected to at least one of the IF amplifiers via a weighted resistor network.

US Pat. No. 9,357,316

TIME DIVISION MULTIPLEXED ACCESS METHOD OF OPERATING A NEAR FIELD COMMUNICATION SYSTEM AND A NEAR FIELD COMMUNICATION SYSTEM OPERATING THE SAME

NXP B.V., Eindhoven (NL)...

1. A method of operating a near-field communication system comprising a first transmitter, a second transmitter and a binaural
hearing aid system comprising a left receiver and a right receiver, according to a time division multiplexed access arrangement
wherein a time division multiplexed access frame comprises at least a first synchronous channel slot, wherein a distance between
each of the first transmitter and the second transmitter and an opposite receiver is greater than a distance between the left
receiver and the right receiver, the method comprising:
transmitting a left signal from the first transmitter during the first synchronous channel slot,
transmitting a right signal from the second transmitter during the first synchronous channel slot,
receiving the left signal by the left receiver, and
receiving the right signal by the right receiver,
wherein the time division multiplexed access frame further comprises a random channel slot for concurrent transmission from
the first and second transmitters, the method further comprising transmitting a control signal from one of the first and second
transmitters during the random channel slot.

US Pat. No. 9,325,927

METHOD OF OPERATING A MULTI-STREAM RECEPTION SCHEME

NXP B.V., Eindhoven (NL)...

1. A method of operating a multi-stream reception scheme involving at least two streams comprising at least two receivers
having respective voltage controlled oscillators (VCOs), the method comprising:
selecting one of the at least two streams;
monitoring a change in local oscillator frequency in the selected stream;
if a frequency distance between the local oscillator frequencies of the at least two streams is below a value likely to cause
one of pulling and coupling between the VCOs of the at least two receivers, resetting a frequency planning of the monitored
stream to maximize the frequency distance of the VCO of the monitored stream with the VCOs of unselected streams using both
a fractional-N PLL and an integer-N PLL; and

supplying a reference frequency simultaneously to both the fractional-N PLL and the integer-N PLL.

US Pat. No. 9,305,455

SWITCH MODULE AND LIGHTING CONTROL SYSTEM COMPRISING THE SWITCH MODULE

NXP B.V., Eindhoven (NL)...

16. A method of controlling a lamp unit from mutually separated switch modules in a lighting control system, wherein the lamp
unit responds selectively to messages from the switch modules when the messages comprise ID information matching with ID information
stored in the lamp unit, the method comprising
detecting user control operation of sensors in the switch modules;
transmitting messages from the switch modules in response to user control operation of sensors in the switch modules;
setting the ID information value in memories of the switch module and/or the further switch module;
using the ID information values from the memories of the switch module and/or the further switch module in the messages to
the lamp unit;

determining, in at least one of the switch modules, from at least one of the messages from a further one of the switch modules,
whether a first time point of the user control operation in said further one of the switch modules is separated from a second
time point of user control operation in said at least one of the switch modules by a time interval with a duration that is
less than a predetermined threshold;

determining matching ID information based on the ID information value of the switch module and the ID information value of
the further switch module, wherein the ID information value of the further switch module is received by the switch module
in a message from the further switch module; and

providing for matching ID information values in the switch module and/or the further switch module when said duration lies
below the predetermined threshold, the matching ID information values being used in the messages to the lamp unit to identify
and control operation of the lamp unit by the switch module and/or the further switch module.

US Pat. No. 9,225,323

SIGNAL CROSSING DETECTION

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a first crossing detection circuit configured and arranged to detect a signal crossing of an electrical signal when a first
time cycle is active, the signal crossing pertaining to a fixed value that the signal crosses;

a second crossing detection circuit configured and arranged to detect the signal crossing of the electrical signal when a
second time cycle is active, the first time cycle being different than the second time cycle;

a reset circuit configured and arranged to reset the first crossing detection circuit while the second time cycle is active,
and to reset the second crossing detection circuit while the first time cycle is active; and

the first and second crossing detection circuits being configured and arranged to provide a signal crossing detection output
in response to the signal crossing pertaining to the fixed value during any of the first and second time cycles.

US Pat. No. 9,213,627

NON-VOLATILE MEMORY WITH BLOCK ERASABLE LOCATIONS

NXP B.V., Eindhoven (NL)...

1. A memory apparatus, the apparatus comprising:
a non-volatile main memory circuit that comprises a plurality of physical blocks of memory locations, the main memory supporting
erasing of at least a physical block at a time; and

a mapping control circuit configured and arranged to maintain pointing information for use to identify respective ones of
the physical blocks that are assigned to respective functions, to define a subset of the physical blocks and to store successive
versions of the pointing information in a first and second one of the physical blocks from the subset, the mapping control
circuit being configured and arranged to

erase the first one of the blocks, after storing a first version of the pointing information in a second one of the blocks,
the first version being not less recent than any of the pointing information in the first one of the blocks, and

recover the pointing information at least on start up of the main memory by testing which physical block of the defined subset
contains a most recent version of the pointing information by searching in the subset for a partly filled block that has only
partly been written, and

in response to finding a partly filled block, using a last written version of the pointing information from that partly filled
block, and

in response to finding no partly filled block, using a last written version of the pointing information from a full block.

US Pat. No. 9,196,537

PROTECTION OF A WAFER-LEVEL CHIP SCALE PACKAGE (WLCSP)

NXP B.V., Eindhoven (NL)...

1. A method for assembling a wafer level chip scale processed (WLCSP) wafer, the wafer having a front-side surface and a back-side
surface, a plurality of device die having electrical contacts on the front-side surface, the method comprising:
back-grinding, to a thickness, the back-side surface the wafer;
applying a protective layer of a thickness onto the back-side surface of the wafer;
mounting the WLCSP wafer onto a sawing foil onto the back-side surface having the protective layer;
sawing the WLCSP wafer in saw lanes of the plurality of device die on the front-side surface, the sawing occurring with a
blade of a first kerf and to a first depth of the back-ground wafer thickness;

again sawing the WLCSP along the saw lanes of the plurality of device die, the sawing occurring with a blade of a second kerf,
the second kerf narrower than the first kerf, and sawing to a depth of the thickness of the protective layer;

separating the plurality of device die into individual device die;
wherein each individual device die has a protective layer on the back-side, the protective layer having a stand-off distance
from a vertical edge of the individual device die.

US Pat. No. 9,116,533

CASCODED SEMICONDUCTOR DEVICES WITH GATE BIAS CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A cascode transistor circuit comprising:
a first, depletion mode transistor having its drain connected to a high power line;
a switching device connected between the source of the first transistor and a low power line, the switching device comprising
a diode function for enabling reverse current flow in the first transistor; and

a gate bias circuit connected between the gate of the first transistor and the low power line, the gate bias circuit being
adapted to compensate the forward voltage of the diode function of the switching device such that a forward voltage of the
gate of the first transistor is increased for reverse current flows, wherein the gate bias circuit comprises first and second
diodes connected in parallel and in opposing directions with the cathode of the first diode connected directly to the anode
of the second diode and the cathode of the second diode connected directly to the anode of the first diode;

wherein the first transistor and the gate bias circuit are formed as part of an integrated circuit.

US Pat. No. 9,100,001

POWER-SWITCH TEST APPARATUS AND METHOD

NXP B.V., Eindhoven (NL)...

1. A power-switch apparatus comprising:
a plurality of power-switching circuits coupled between a voltage supply and a switched voltage output;
a test control circuit coupled to each of the power-switching circuits and configured and arranged to operate at least one
of the power-switching circuits in an on condition for providing the switched voltage output, in response to a test signal
received at the at least one of the power-switching circuits, while operating at least another one of the respective power-switching
circuits in an off condition;

a current emulation circuit coupled to the switched voltage output and configured and arranged to emulate an expected current
draw for the respective power-switching circuits under at least one load condition; and

an output circuit coupled to receive the switched voltage output and configured and arranged to
compare a value of the switched voltage output to a reference value, and
in response to the comparison, provide a test output indicative of an operational characteristic of the power-switching circuits
operated in the on condition.

US Pat. No. 9,078,318

SWITCHED MODE POWER CONVERTER AND METHOD OF OPERATING THE SAME

NXP B.V., Eindhoven (NL)...

1. A switched mode power converter providing an output current for LED applications, the switched mode power converter comprising:
an inductor,
wherein the inductor is subjected to a current decreasing from a maximum value to zero, and immediately thereafter, the inductor
is subjected to the current increasing from zero to the maximum value;

a switch, is configured such that,
wherein the switch is forced to be open in response to a first change in a converter control signal, which first change is
indicative of an absence of a requirement for every one of a plurality of LED loads, thereby providing an interruption; and

wherein the switch is no longer forced to be open in response to a second change in the converter control signal, which second
change is indicative of a recommencement of a requirement for one of any one and a plurality of the plurality of LED loads,
thereby ending the interruption.

US Pat. No. 9,070,003

METHOD FOR HANDLING COLLISION IN AN IDENTIFICATION SYSTEM

NXP B.V., Eindhoven (NL)...

1. A method for handling collision in an identification system the method comprising the following steps:
a reader device transmits an initialization command to a first transponder and to a second transponder;
upon receiving the initialization command, the first transponder and the second transponder enter into a muted state, and
in the muted state the first transponder and the second transponder do not respond to commands from the reader device;

in a first start time slot randomly determined by the first transponder, the first transponder enters into an un-muted state
from the muted state and the first transponder remains in the un-muted state until the reader device sends a mute command
to the first transponder;

in a second start time slot randomly determined by the second transponder, the second transponder enters into an un-muted
state from the muted state and the second transponder remains in the un-muted state until the reader device sends a mute command
to the second transponder;

wherein, when the first start time slot and the second time slot occur at the same randomly determined time slot, then:
when a transponder has a weaker signal modulation than another transponder, then the transponder with the weaker signal modulation
re-enters into a muted state until a third start time slot randomly determined by the transponder corresponding to the weaker
signal modulation; and

when the signal modulation of the first transponder and the second transponder have substantially the same strength, then
the first transponder and the second transponder re-enter into a muted state until a start time slot randomly determined by
the corresponding transponder.

US Pat. No. 9,967,946

OVERSHOOT PROTECTION CIRCUIT FOR LED LIGHTING

NXP B.V., San Jose, CA (...

1. An article of manufacture comprising overshoot-protection circuitry for an LED (light-emitting diode) controller, the overshoot-protection circuitry comprising:a switch-drain node configured to be connected to a drain of a switch in the LED controller that controls at least one LED;
a switch-gate node configured to be connected to a gate of the switch in the LED controller that controls the at least one LED; and
inter-node circuitry connected between the switch-drain and switch-gate nodes and configured to limit a magnitude of a drain-to-source voltage of the switch.

US Pat. No. 9,723,669

LED LIGHTING SYSTEM AND CONTROLLER, A METHOD OF CONTROLLING A PLURALITY OF LEDS, AND A COMPUTER PROGRAM THEREFOR

NXP B.V., Eindhoven (NL)...

1. An LED lighting system comprising:
a heatsink;
a plurality of strings of LEDs each string comprising one or more LEDs each having a junction and being mounted on the heatsink,
and

a controller comprising a memory unit and a processor and being configured to supply a respective current to each of the strings
of LEDs;

wherein the processor comprises: a first temperature estimation subunit configured to generate a first estimate, being an
estimate of the junction temperature of the LEDs of a one of the strings of LEDs; a heatsink temperature estimation subunit
configured to estimate a temperature of the heatsink from the first estimate; and a second temperature estimation subunit
configured to provide a second estimate, being an estimate of a junction temperature of LEDs of a second string of LEDs, from
the estimated temperature of the heatsink.

US Pat. No. 9,500,681

FET RF POWER DETECTOR

NXP B.V., Eindhoven (NL)...

1. A FET RF signal detector circuit comprising:
a first unbalanced differential transistor pair circuit;
a second unbalanced differential transistor pair circuit;
a current mirror output circuit for generating a sensor current and an output current derived from currents flowing in the
differential transistor pair circuits;

wherein the first unbalanced differential transistor pair circuit comprises two branches, each with a respective tail, and
a first variable resistor between the branch tails, wherein the first unbalanced differential transistor pair circuit connects
to a first current source tail arrangement; and

wherein the second unbalanced differential transistor pair circuit comprises two branches, each with a respective tail, and
a second variable resistor between the branch tails, wherein the second unbalanced differential transistor pair circuit connects
to a second current source tail arrangement; and

wherein the sensor current is subtracted from current output from an additional current source through a resistor.

US Pat. No. 9,448,300

SIGNAL-BASED DATA COMPRESSION

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a radar transceiver configured and arranged to transmit radar signals and to receive reflections of the transmitted radar
signals over a communication channel;

a data compression circuit configured and arranged to
determine a compression factor based on distance characteristics of the channel and a velocity of an object that causes the
received reflections, and

compress data representing the radar signals as a function of the determined compression factor; and
a data generator circuit configured and arranged to generate an output signal including the compressed data.

US Pat. No. 9,435,842

CIRCUIT AND METHOD FOR DETECTION OF IC CONNECTION FAILURE

NXP B.V., Eindhoven (NL)...

1. A testing circuit for testing an IC connection between an RF chip and external circuitry, the testing circuit comprising:
a current source for injecting a DC current towards the connection to be tested; an on-chip ESD protection circuit which provides
a path between one side of the connection to be tested and a fixed voltage line; a shunt path coupled to the other side of
the connection to be tested; and a testing unit, wherein the testing unit is adapted to determine if the current source current
flows through the ESD protection circuit and thereby determine whether the connection to be tested presents a short circuit
for DC, wherein the ESD protection circuit is between one side of the connection to be tested and a constant voltage line,
and the shunt path is between the other side of the connection to be tested and a second connection, wherein the current source
output is coupled to the second connection.

US Pat. No. 9,412,544

SYSTEM AND METHOD FOR DRIVING A RELAY CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A circuit, comprising:
a relay circuit;
a first driver circuit, the first driver circuit includes a first switch coupled to the relay circuit and a second switch
coupled to a battery supply for the relay circuit; and

a second driver circuit coupled to the relay circuit,
wherein the circuit is configured such that the first driver circuit drives the relay circuit if a voltage of the battery
supply for the relay circuit is lower than a preselected voltage threshold and the second driver circuit drives the relay
circuit if the voltage of the battery supply is higher than the preselected voltage threshold, wherein the first driver circuit
is an active clamping driver circuit, wherein the second driver circuit is a free-wheel diode driver circuit, wherein the
active clamping driver circuit comprises a driver transistor, a first diode, and a second diode, wherein the cathode of the
first diode is connected to a first switch, the anode of the first diode is connected to the anode of the second diode, and
the cathode of the second diode is connected to the gate of the driver transistor, wherein the free-wheel diode driver circuit
comprises the driver transistor and a third diode, and wherein the anode of the third diode is connected to the driver transistor
and the cathode of the third diode is connected to a second switch.

US Pat. No. 9,413,342

RESISTIVE DIVIDER CIRCUIT FOR A DIFFERENTIAL SIGNAL COMMUNICATIONS RECEIVER

NXP B.V., Eindhoven (NL)...

1. A resistive divider circuit for differential signaling, the resistive divider circuit comprising:
a first branch; and
a second branch;
wherein each branch comprises:
an input;
a first resistive component comprised of a number of unit resistors;
a second resistive component comprised of a number of unit resistors; and
an output connected between the first resistive component and the second resistive component, the output forming a differential
mode output;

wherein the number of unit resistors of the first resistive component is equal to the number of unit resistors of the second
resistive component; and

wherein a lowpass filter is connected to the resistive divider circuit at a point on the resistive divider circuit where the
highest impedance exists.

US Pat. No. 9,406,374

MITIGATING LEAKAGE IN MEMORY CIRCUITS

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a memory circuit including a plurality of rows of memory cells, each memory cell in a corresponding row having pass transistors
connected to a shared word-line;

a word-line driver circuit configured and arranged to:
enable pass transistors of a first set of memory cells of the memory circuit by applying a first voltage to word-lines of
the first set of memory cells;

disable pass transistors of a second set of memory cells of the memory circuit by applying a second voltage to word-lines
of the second set of memory cells; and

mitigate leakage of pass transistors of a third set of memory cells of the memory circuit by applying a third voltage to word-lines
of the third set of memory cells, wherein the third voltage is between the first and second voltages.

US Pat. No. 9,397,569

CURRENT CONTROL CIRCUIT WITH IN PARALLEL TRANSISTOR MODULES

NXP B.V., Eindhoven (NL)...

1. A current control circuit, comprising:
a first terminal;
a second terminal;
a plurality of transistor modules in parallel with each other between the first terminal and the second terminal, each transistor
module comprising:

a main transistor having a main drain, a main source and a main gate, wherein the main source and the main drain define a
main source-drain path, the main drain is coupled to the first terminal, the main source is coupled to the second terminal
and the main gate is coupled to a local control terminal;

a sense transistor having a sense drain, a sense source and a sense gate, wherein the sense source and the sense drain define
a sense source-drain path, the sense drain is coupled to the first terminal, the sense gate is coupled to the local control
terminal, and the sense source is configured to provide a local feedback signal;

a local controller configured to:
receive the local feedback signal and a main control signal; and
provide a local control signal to the local control terminal in accordance with the local feedback signal and the main control
signal in order to control the current through the main source-drain path and the sense source-drain path.

US Pat. No. 9,379,884

SYMBOL CLOCK RECOVERY CIRCUIT

NXP B.V., Eindhoven (NL)...

1. A symbol clock recovery circuit comprising:
an Analogue to Digital Converter (ADC) comprising an ADC input terminal, an ADC output terminal and an ADC clock terminal,
wherein the ADC input terminal is configured to receive a baseband signal, wherein the baseband signal is representative of
one or more symbols, and wherein the ADC output terminal is configured to provide an ADC output signal;

a controllable inverter comprising an inverter input terminal, an inverter output terminal and an inverter control terminal,
wherein the inverter input terminal is configured to receive a carrier frequency signal, the inverter output terminal is configured
to provide a configurable clock signal to the ADC clock terminal; and wherein the configurable clock signal is selectively
inverted with respect to the received carrier frequency signal in accordance with a first feedback signal received at the
inverter control signal;

a timing detector comprising a timing detector input terminal, a timing detector output terminal, a first timing detector
feedback terminal, wherein:

the timing detector input terminal is configured to receive the ADC output signal from the ADC output terminal;
the timing detector output terminal is configured to provide a digital output signal; and
the first timing detector feedback terminal is configured to provide the first feedback signal to the inverter control terminal;
wherein the timing detector is configured to determine an error signal associated with the received ADC output signal, and
set the first feedback signal in accordance with the error signal;

wherein the controllable inverter is configured to set a timing of a rising edge of the configurable clock signal at a resolution
of half carrier frequency.

US Pat. No. 9,379,430

MULTIBAND ANTENNA

NXP B.V., Eindhoven (NL)...

1. A multiband antenna comprising:
a substrate having a first surface and a second surface, wherein the second surface is on an opposite side of the substrate
relative to the first surface;

a first conductive plate on the first surface of the substrate;
a second conductive plate on the second surface of the substrate, wherein the second conductive plate at least partially overlaps
the first conductive plate in a plane of the substrate;

a ground plane, wherein the substrate is connected to the ground plane and is substantially perpendicular to the ground plane;
a single feeding port that provides a direct electrical connection to each of the first conductive plate and the second conductive
plate, wherein the first conductive plate is configured to transmit or receive signals in a first frequency band and the second
conductive plate is configured to transmit or receive signals in a second frequency band.

US Pat. No. 9,331,028

ELECTRIC FIELD GAP DEVICE AND MANUFACTURING METHOD

NXP B.V., Eindhoven (NL)...

1. A method of forming an electric field gap structure, comprising:
providing a silicon substrate;
etching cathode channels into the substrate, the cathode channels being defined in part by sidewall surfaces;
lining the top surface of the substrate and the sidewall surfaces of the cathode channels with a lining dielectric layer,
wherein the lining dielectric layer leaves the cathode channels open;

after the lining, forming shielding regions on the sidewall surfaces of the cathode channels but leaving an unshielded portion
at the top of the cathode channels, wherein the shielding regions leave the cathode channels open;

oxidising the substrate at the unshielded portion of the cathode channels so that oxidation occurs at the top of the cathode
channels such that an amount of original silicon of the silicon substrate between tops of adjacent cathode channels is narrowed
to form pointed non-oxidised substrate regions between the cathode channels;

etching away the layers at and above the pointed substrate regions;
providing a cathode contact over each pointed substrate region;
forming a sacrificial layer over the cathode contacts;
providing an anode metal layer over the sacrificial layer;
etching the sacrificial layer to form a cavity between the cathode contacts and the anode metal layer.

US Pat. No. 9,171,810

ELECTRONIC DEVICE INCORPORATING A RANDOMIZED INTERCONNECTION LAYER HAVING A RANDOMIZED CONDUCTION PATTERN

NXP B.V., Eindhoven (NL)...

1. An electronic device, comprising:
a randomized interconnection layer having a randomized conductive pattern formed by etching of a heterogeneous layer; and
a sensing circuit, electrically coupled to the randomized interconnection layer to detect the randomized conductive pattern.

US Pat. No. 9,153,529

PRE-SOLDERED LEADLESS PACKAGE

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a patterned conductive layer defining contact pads for being connected to terminals of a semiconductor chip ;
the semiconductor chip comprising the terminals at a first side and an adhesive layer at a second side opposite to the first
side, wherein the semiconductor chip is mounted with the adhesive layer on a patterned conductive layer such that the semiconductor
chip part of each respective contact pad leaving part thereof uncovered by the chip for wire bonding;

wire bonds connecting respective terminals of the semiconductor chip and the respective contact pad at the first side thereof;
a molding compound covering the semiconductor chip, the wire bonds and the contact pads, wherein the molding compound is also
located on the second side of the semiconductor device, separating contact regions that are located directly on a backside
of the contact pads;

solder bumps that are provided directly on the backside of that contact pads, and wherein the semiconductor device is configured
such that the solder bumps have a side contact surface, wherein the side contact surface is co-planar with the molding compound
at a cut line just along the solder bumps; and wherein each of the solder bumps extend from the cut line to the contact regions
directly under the respective a terminals.

US Pat. No. 9,048,116

SEMICONDUCTOR DEVICE HAVING ISOLATION TRENCHES

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a plurality of transistors formed at an active area of semiconductor substrate, the transistors each comprising a source layer,
a drain layer and a gate;

an isolation trench formed around the active area and having an insulator liner; and
a further isolation trench formed in a drift region and filled with the insulator liner and an electrode material, wherein
a transistor gate is electrically connected to a top of the further isolation trench, and the transistor drain is capacitively
connected to a bottom of the further isolation trench.

US Pat. No. 9,503,260

SECURITY TOKEN AND SERVICE ACCESS SYSTEM

NXP B.V., Eindhoven (NL)...

1. A security token configured to facilitate access to a remote computing service via a mobile device external to said security
token, said security token comprising:
a Near Field Communication (NFC) interface;
a smart card integrated circuit; and
a smart card applet stored in and executable by said smart card integrated circuit, wherein the smart card applet is configured
to support a cryptographic challenge-response protocol executable by the mobile device, wherein a plurality of credentials
for the cryptographic challenge-response protocol are maintained inside a single security token.

US Pat. No. 9,503,023

CLASS-D AMPLIFIER

NXP B.V., Eindhoven (NL)...

1. A class-D amplifier apparatus, comprising:
an amplifier circuit, having a set of input terminals, a set of output terminals, a quiescent circuit configuration, and an
active circuit configuration;

an amplifier control device, coupled to the amplifier circuit;
wherein the amplifier control device is configured to place the amplifier circuit in the quiescent circuit configuration before
measuring a voltage between the set of output terminals;

wherein the amplifier control device is configured to add the output terminals voltage from the set of input terminals before
placing the amplifier circuit in the active circuit configuration.

US Pat. No. 9,385,670

DUAL BRIDGE AMPLIFIER CONFIGURATION

NXP B.V., Eindhoven (NL)...

1. An amplifier comprising:
a first bridge amplifier section having two differential amplifiers with a first load connected between their outputs;
a second bridge amplifier section having two differential amplifiers with a second load connected between their outputs;
a mode switch between a first output of one differential amplifier of the first bridge amplifier section and a second output
of one differential amplifier of the second bridge amplifier section;

a control circuit, coupled to the mode switch, and configured to control the mode switch based on a set of input signals to
the first and second bridge amplifier sections;

a clip detection circuit configured to detect clipping in the first or second outputs; and
a delay circuit, coupled to the clip detection circuit and the control circuit, and configured to provide a delay period in
response to the detected clipping, wherein the control circuit is configured to inhibit closing of the mode switch during
the delay period.

US Pat. No. 9,380,033

IMPLEMENTING USE-DEPENDENT SECURITY SETTINGS IN A SINGLE WHITE-BOX IMPLEMENTATION

NXP B.V., Eindhoven (NL)...

1. A non-transitory machine-readable storage medium encoded with instructions for execution by a cryptographic system for
enforcing security settings, the non-transitory machine-readable storage medium comprising:
instructions for receiving, by the cryptographic system, a first input message associated with a first security setting of
a plurality of security settings;

instructions for performing, by the cryptographic system, a keyed cryptographic operation mapping the first input message
into a first output message, wherein the keyed cryptographic operation produces a correct output message when the cryptographic
system is authorized for the first security setting,

wherein each of the plurality of security settings has an associated set of input messages wherein the sets of input messages
do not overlap,

wherein an input message space includes all potential input messages to the keyed cryptographic operation and the plurality
of input message groups includes all of the input messages in the input message space.

US Pat. No. 9,331,866

NETWORK COMMUNICATIONS APPARATUS, SYSTEM, AND METHOD

NXP B.V., Eindhoven (NL)...

1. An apparatus operable as a terminal for use in a master-slave network having a master communication circuit and having
a plurality of slave communication circuits respectively operable as serially-connected communication circuits, the apparatus
comprising:
a switching circuit configured and arranged to operate in a communication mode, in which the switch communicates information
carried by data signals between a first data port and a second data port, and operate in an addressing mode, in which the
switching circuit receives a first information signal having a voltage level that represents a cascade of slave circuits of
the plurality of slave circuits in series between the master communication circuit and the first data port, and sends a second
information signal on the second data port, the second information signal being generated by applying a voltage potential
between the first and second data ports thereby modifying the voltage level of the first information signal;

an address generation circuit configured and arranged to generate an address for the apparatus based on a voltage difference
between a voltage level on the first data port in the communication mode and the voltage level of the first information; and
a circuit configured and arranged to communicate by using a protocol in which the address identifies the apparatus irrespective
of other slave communication circuits in the network in communications with the first data port.

US Pat. No. 9,329,853

METHOD AND SERVICE PROVIDER FOR MANAGING EXPIRED OR CONSUMED APPLICATIONS BEING STORED IN MOBILE COMMUNICATION DEVICES

NXP B.V., Eindhoven (NL)...

1. A service provider in a system for providing contactless services to a mobile communication device of a customer, the service
provider comprising:
a database configured to store a plurality of applications;
a transmitter configured to receive a retrieval request from the mobile communication device for a particular application,
retrieve the requested application from the database, format the requested application according to a format chosen by the
customer, and send the formatted application to the mobile communication device, wherein the mobile communication device is
configured as a Near Field Communication (NFC) mobile phone;

a first interface configured to communicate with a Trusted Service Manager via a computer network; and
a second interface configured to communicate with the mobile communication device via wireless services.

US Pat. No. 9,192,006

ELECTRONIC DEVICE FOR DRIVING LIGHT EMITTING DIODES

NXP B.V., Eindhoven (NL)...

1. A method for driving one or more light emitting diodes, the method comprising the steps of:
switching a switch-mode power converter to produce an output voltage across the one or more light emitting diodes;
sensing a current provided by the switch-mode power converter;
providing a variable input signal to generate a reference voltage, that varies as a function of the output voltage; and
controlling the step of switching, in response to a comparison of the sensed current and the reference voltage; and
generating the reference voltage in response to a variable input signal, wherein the variable input signal allows for control
of current through the one or more light emitting diodes substantially independent from the output voltage.

US Pat. No. 9,166,484

RESONANT CONVERTER

NXP B.V., Eindhoven (NL)...

1. A resonant converter having a primary side for receiving a DC voltage from an input power supply and a secondary side for
providing a DC output voltage, the resonant converter comprising:
a first converter switch;
a second converter switch coupled in series with the first converter switch, wherein the first and second converter switches
are provided across the input power supply;

a switching transformer with a primary side winding and a secondary side winding, wherein the primary side winding is coupled
in parallel with the second converter switch, the switching transformer configured to transfer energy from the primary side
winding to the secondary side winding of the switching transformer;

a resonant tank associated with the primary side winding of the switching transformer;
a signalling transformer with a primary side winding and a secondary side winding, wherein the secondary side winding of the
signalling transformer is connected to the secondary side winding of the switching transformer and configured to transfer
a signal from the secondary side winding of the signalling transformer to the primary side winding of the signalling transformer;
and

a primary side controller configured to control the first and second converter switches in response to the signal received
at the primary side winding of the signalling transformer,

wherein the switching transformer has a first secondary side winding and a second secondary side winding and the signalling
transformer has a first secondary side winding and a second secondary side winding,

wherein a first terminal of the first secondary side winding of the switching transformer is coupled to a first terminal of
the second secondary side winding of the switching transformer and to ground, a second terminal of the first secondary side
winding of the switching transformer is coupled to a first terminal of the first secondary side winding of the signalling
transformer, a second terminal of the second secondary side winding of the switching transformer is coupled to a first terminal
of the second secondary side winding of the signalling transformer.

US Pat. No. 9,142,625

FIELD PLATE ASSISTED RESISTANCE REDUCTION IN A SEMICONDUCTOR DEVICE

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a substrate;
a source region, a drain region, and a drain extension region formed in the substrate; and
an insulation layer adjacent to the drain extension region, wherein a gate layer and a field plate are formed within the insulation
layer, the field plate includes a polysilicon layer, a via, and a metal layer, wherein the field plate is located adjacent
to the drain extension region and is electrically insulated from the gate layer and the source region such that a voltage
can be applied to the field plate independent from voltages applied to the gate layer and the source region, wherein the field
plate includes a polysilicon layer enclosed in the insulation layer, a metal layer exposed at the surface of the insulation
layer, and a via connecting the polysilicon layer and the metal layer and enclosed in the insulation layer.

US Pat. No. 9,123,185

PASSENGER TRANSPORTING SYSTEM AND METHOD FOR OBTAINING TICKETS IN SUCH A SYSTEM

NXP B.V., Eindhoven (NL)...

1. A system for obtaining tickets for journeys in a passenger transportation system which comprises stations for entering
and/or leaving one or more transport vehicles of the passenger transportation system for journeys between the stations, the
system comprising:
at least one contactlessly readable data carrier device configured to store a ticket information item which uniquely identifies
a respective station or a respective transport vehicle in which the at least one contactlessly readable data carrier device
is located; and

a mobile reader device carried by a passenger configured to:
read the at least one contactlessly readable data carrier device via nearfield communication;
store the ticket information item from reading the at least one contactlessly readable data carrier device; and
calculate, exclusively in the mobile reader device using an algorithm and tariff information stored in the mobile reader device,
an overall fare for a route traveled by the passenger from the ticket information item and one or more additional ticket information
items collected by the mobile reader device for a plurality of journeys over a plurality of days, wherein the overall fare
for the journeys is calculated only after the plurality of days by:

determining a sum of individual fares using the ticket information item and the one or more additional ticket information
items;

determining whether the passenger has traveled a certain number of journeys in a month and the sum of the individual fares
exceeds the price of a monthly pass;

based on a determination that the passenger has traveled a certain number of journeys in the month and the sum of the individual
fares exceeds the price of the monthly pass, calculating the overall fare as the price of the monthly pass; and

based on a determination that the passenger has not traveled the certain number of journeys in the month or the sum of the
individual fares does not exceed the price of the monthly pass, calculating the overall fare as the sum of the individual
fares.

US Pat. No. 9,112,486

ASYMMETRIC PROPAGATION DELAYS IN LEVEL SHIFTERS AND RELATED CIRCUITS

NXP B.V., EIndhoven (NL)...

1. An apparatus useful for processing communications between different signaling voltage levels by creating true and complement
signals from at least one input signal, whereby the true and complement signals are each subject to different timing delays
for respective signal transitions, the true and complement signals being level shifted to a new signaling voltage level and
one of the true and complement signals being inverted relative to the input signal, the apparatus comprising:
logic circuitry configured and arranged to
determine, relative to a particular signal state and using binary logic gates that each receive the true and complement signals
as inputs, which of the true and complement signals is subject to a smaller timing delay, and

to generate, in response to the determination, a selection signal that identifies the one of the true and complement signals
determined as being subject to the smaller timing delay; and

signal selection control circuitry configured and arranged to provide, in response to the selection signal, the one of the
true and complement signals determined as being subject to the smaller timing delay as an output signal.

US Pat. No. 9,111,523

DEVICE FOR AND A METHOD OF PROCESSING A SIGNAL

NXP B.V., Eindhoven (NL)...

1. A system for processing a signal having a known interference, comprising:
a processing unit having an input terminal, a first output terminal and a second output terminal, wherein the processing unit
is configured to receive the signal at the input terminal, supply the signal to the first output terminal, after a specific
delay, generate a reduction signal based on the signal received at the input terminal, and supply the reduction signal to
the second output terminal;

a first reproduction unit coupled to the first output terminal, wherein the first reproduction unit is configured to generate
the known interference as a reference signal; and

a second reproduction unit coupled to the second output terminal, wherein the second reproduction unit is configured to generate
a sound representative of the reduction signal, wherein the reduction signal and the specific delay are configured for reducing
the known interference at a location of the second reproduction unit, wherein the second reproduction unit is part of a headset
and comprises a built-in inner microphone in each earpiece.

US Pat. No. 9,106,314

CONCURRENT MULTIBAND TRANSCEIVER

NXP B.V., Eindhoven (NL)...

1. An RF front-end adapted to perform either in a receiving mode or in a transmitting mode and adapted to receive or transmit
signals located in at least two separated frequency bands, respectively comprising an input and an output and further comprising
an input and an output;
an input matching circuit comprising a first input coupled to the input;
an output matching circuit coupled to the output;
the input matching circuit being coupled to the output matching circuit via respective first amplifier and second amplifier;
a phase shifter coupled either to the input of the RF front-end in a transmitting mode, or to the output of the RF front-end
in a receiving mode;

wherein the phase shifter provides at its output an odd multiple of 180° phase shift of a signal situated in a first frequency
band applied to its input and

wherein the phase shifter provides at its output an even multiple of 180° phase shift of a signal situated in a second frequency
band applied to its input.

US Pat. No. 9,071,236

METHOD AND SYSTEM FOR CONTROLLING A CHARGE PUMP

NXP B.V., Eindhoven (NL)...

1. A method for controlling a charge pump, the method comprising:
monitoring a power-on status of the charge pump;
calculating a duty cycle of the charge pump within a time period based on the power-on status of the charge pump; and
adjusting at least one of a clock frequency setting and a capacitance setting of the charge pump based on the duty cycle of
the charge pump.

US Pat. No. 9,503,897

SECURE WIRELESS COMMUNICATION APPARATUS

NXP B.V., Eindhoven (NL)...

1. An apparatus comprising:
a wireless communication circuit configured and arranged to send and receive wireless communications;
a first circuit having a timer and configured and arranged to start the timer in response to user input data, and to generate
session initiation commands in response to at least one of a status of the timer and a power-based event; and

a second circuit having a memory circuit and configured and arranged with
a session identification (ID) circuit configured and arranged to generate and store a session ID in response to each session
initiation command, each session ID being different than other session IDs generated by the session ID circuit in response
to the session initiation commands, and

a communication circuit configured and arranged to
assess validity of the user input data and, in response to the user input data being determined to be valid, access the session
ID stored by the session ID circuit, and store the accessed session ID in the memory circuit, and

initiate data communication via the wireless communication circuit for wireless communication to a remote device,
access a current version of the session ID stored by the session ID circuit during the data communication and comparing the
current version of the session ID with the session ID stored in the memory circuit, and continuing the communication of the
data to the wireless communication circuit in response to the current version of the session ID matching the session ID stored
in the memory circuit.

US Pat. No. 9,338,145

SECURITY PATCH WITHOUT CHANGING THE KEY

NXP B.V., Eindhoven (NL)...

1. A method of patching a cryptographic implementation without changing a key in a cryptographic system, comprising:
sending a message from a first message set to the cryptographic implementation, wherein the first message uses a first portion
of the cryptographic implementation;

deciding to patch the cryptographic implementation;
sending a second message from a second message set to the cryptographic implementation after deciding to patch the cryptographic
implementation, wherein the second message uses a second portion of the cryptographic implementation that is not used for
any messages in the first message set.

US Pat. No. 9,331,067

BIGFET ESD PROTECTION THAT IS ROBUST AGAINST THE FIRST PEAK OF A SYSTEM-LEVEL PULSE

NXP B.V., Eindhoven (NL)...

1. An electrostatic discharge (ESD) protection device, the ESD protection device comprising: a bigFET configured to conduct
an ESD pulse during an ESD event, the bigFET comprising: a backgate terminal; a source terminal; a current distributor connected
to the backgate terminal and the source terminal and configured to homogeneously activate a parasitic bipolar junction transistor
of the bigFET in response to a current that is generated during a first current peak of the ESD pulse; and a trigger device
including a capacitor and configured to drive the bigFET for at least a part of time during the ESD pulse.

US Pat. No. 9,319,780

SMART PASSIVE SPEAKER DRIVE

NXP B.V., Eindhoven (NL)...

1. A circuit embodied in a mobile device, comprising:
a headphone audio driver;
a loudspeaker audio driver; and
a switch coupled to outputs of the headphone audio driver and the loudspeaker audio driver, wherein the switch is configured
to connect, based on a user configuration stored in the mobile device, the output of the loudspeaker audio driver to an external
speaker when the external speaker is connected to the mobile device, wherein the switch is configured to connect the output
of the headphone audio driver to an external headphone when the external headphone is connected to the mobile device.

US Pat. No. 9,190,350

SEMICONDUCTOR DEVICE LEADFRAME

NXP B.V., Eindhoven (NL)...

1. A lead frame for a semiconductor device manufactured by film assisted moulding, the lead frame comprising:
a connection lead, the connection lead comprising
a connection portion for electrical connection to a semiconductor die, having a bond wire portion,
wherein an edge of said connection portion comprises
a recessed portion
wherein the recessed portion is arranged to seal against a film assisted moulding film during moulding of the semiconductor
device;

further comprising a mould compound; and
wherein the seal between the recessed portion and the film is configured to block the mould compound from contacting the bond
wire portion.

US Pat. No. 9,064,847

HETEROJUNCTION SEMICONDUCTOR DEVICE WITH CONDUCTIVE BARRIER PORTION AND MANUFACTURING METHOD

NXP B.V., Eindhoven (NL)...

1. A semiconductor device comprising:
a group 13 nitride heterojunction comprising a first layer having a first bandgap and a second layer having a second bandgap,
wherein the first layer is located between a substrate and the second layer;

a first capping layer over the second layer; and
a Schottky electrode and a first further electrode each conductively coupled to a different area of the heterojunction with
the first capping layer between the heterojunction and the Schottky electrode and the first further electrode, said Schottky
electrode comprising a central region and an edge region, a conductive barrier portion located underneath said edge region
only of the Schottky electrode for locally increasing the Schottky barrier of the Schottky electrode, wherein the conductive
barrier portion comprises a second capping layer and wherein underneath the central region of the Schottky electrode is free
of the second capping layer and wherein the first capping layer is separated from the second capping layer by an etch stop
layer.

US Pat. No. 9,048,861

ANALOGUE TO DIGITAL CONVERTER

NXP B.V., Eindhoven (NL)...

1. An analogue to digital converter comprising:
an input terminal configured to receive an analogue input signal;
an output terminal configured to provide an output digital signal;
a main summer having a summing input, a subtracting input and a summing output, wherein the summing input is connected to
the input terminal;

an analogue filter having a filter input and a filter output, wherein the filter input is connected to the summing output;
a quantizer having a quantizer input and a quantizer output, wherein the quantizer input is connected to the filter output;
a digital integrator having a digital integrator input and a digital integrator output, wherein the digital integrator output
is configured to provide a multi-bit output signal, the digital integrator input is connected to the quantizer output, and
the digital integrator output is connected to the output terminal;

a main feedback digital to analogue converter having a main feedback converter input and a main feedback converter output,
wherein the main feedback converter input is connected to the digital integrator output, and the main feedback converter output
is connected to the subtracting input of the main summer; and

an intermediate feedback digital to analogue converter having an intermediate feedback converter input and an intermediate
feedback converter output, wherein the intermediate feedback converter input is connected to the quantizer output.

US Pat. No. 10,021,766

CONTROLLER FOR A HORTICULTURAL LIGHTING SYSTEM

NXP B.V., Eindhoven (NL)...

1. A controller for a horticultural lighting system comprising:a receiver configured to receive a set of lighting parameters; and
one or more output terminals configured to provide lighting control signaling to an LED array,
wherein the lighting control signaling is configured to set one or more operating parameters of the LED array in accordance with the received set of lighting parameters;
wherein the controller is configured to receive or determine a junction temperature representative of a junction temperature of one or more LEDs in the LED array,
wherein the controller is configured to also set one or more operating parameters of the LED array in accordance with the junction temperature; and
wherein the controller is configured to command a driver to drive a forward bias current through an LED in the LED array, the current comprising a measurement current (Ilow) portion comprising a non-zero measurement current;
further comprising,
a sampler configured to sample a forward bias voltage drop (Vf), and determine the forward bias voltage drop (Vf) at the measurement current (Ilow); and
a calculator configured to calculate the junction temperature of the LED from the determined forward bias voltage drop; and
wherein the controller is configured to set the one or more operating parameters of the LED array in accordance with the calculated junction temperature of the LED.

US Pat. No. 9,331,634

FREQUENCY DOWN-CONVERSION

NXP B.V., Eindhoven (NL)...

1. An apparatus, comprising:
a first mixer configured and arranged to down-convert a radio frequency (RF) signal to produce a first intermediate frequency
(IF) signal having a first number (M) of phase components;

a second mixer configured and arranged to down-convert the first IF signal to produce a second IF signal having a second number
(N) of phase components; and

a plurality of summing circuits, each configured and arranged to combine various ones of phase components of the second IF
signal to produce a respective phase component of a third IF signal, the third IF signal having a third number (O) of phase
components, wherein N>M and N?O, wherein the first mixer is configured and arranged to subtract a frequency of a first local
oscillator (LO) signal from a frequency of the RF signal to produce a frequency of the first IF signal and the second mixer
is configured and arranged to subtract a frequency of a second LO signal from a frequency of the first IF signal to produce
a frequency of the second IF signal, the second LO signal has a frequency that is less than a frequency of the first LO signal,
wherein the ratio of the frequency of the first LO signal to the frequency of the second LO signal is equal to N/(M*2).