US Pat. No. 9,245,129

SYSTEM AND METHOD FOR PROTECTING DATA BY RETURNING A PROTECT SIGNAL WITH THE DATA

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving, by a system from a client operating in an unprotected state, a request to read data from memory;
in response to the request, determining, by the system, that the data is stored in a protected portion of the memory;
in response to determining that the data is stored in the protected portion of the memory, returning, by the system to the
client, the data and a protect signal for use in protecting the data, wherein the protect signal changes the unprotected state
of the client to a protected state;

preventing, by the system, the client from writing to an unprotected portion of the memory, while the client is operating
in the protected state.

US Pat. No. 9,262,348

MEMORY BANDWIDTH REALLOCATION FOR ISOCHRONOUS TRAFFIC

NVIDIA Corporation, Sant...

1. A computer implemented method for dynamically resizing a buffer configured to store data associated with isochronous data
requests, the method comprising:
determining, based on an amount of outstanding non-isochronous data requests, that the buffer configured to store data associated
with isochronous data requests should be resized;

determining a new size of the buffer based on the amount of outstanding non-isochronous data requests and a ratio of a memory
clock to a clock running the buffer; and

resizing the buffer according to the new size.

US Pat. No. 9,256,514

DEBUGGING AND PERFOMANCE ANALYSIS OF APPLICATIONS

NVIDIA CORPORATION, Sant...

1. A non-transitory computer-readable medium having stored thereon computer-executable instructions that, responsive to execution
by a computer system, cause said computer system to perform operations comprising:
recording function calls between a graphics application and a graphics application programming interface (API) while operating
on a frame of interest;

maintaining a reference count for an object created by said graphics API, wherein said reference count is incremented each
time said object is referenced and decremented each time a reference to said object is removed;

manipulating said reference count such that said graphics API behaves as if there is at least one remaining reference for
said object and does not delete said object when said reference count for said object reaches zero so that said object remains
intentionally available when said frame of interest is subsequently replayed;

recording a beginning state of said graphics API;
determining a difference between said beginning state and an ending state of said graphics API;
generating a list of graphics API calls that return said ending state to said beginning state; and
after said manipulating, replaying said frame of interest including repeating said function calls and using said object during
said replaying.

US Pat. No. 9,240,691

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR REMEDYING A CHARGING ERROR

NVIDIA Corporation, Sant...

1. A method, comprising:
detecting, at a module that includes a microcontroller, a voltage of a battery connected to a battery charger, wherein the
voltage is below a minimum threshold voltage at which the battery charger detects the battery; and

sending, by the module, at least one pulse of current to the battery to increase the voltage of the battery above the minimum
threshold voltage, wherein the battery charger, once the voltage is above the minimum threshold voltage, detects the battery
and begins to charge the battery,

wherein the at least one pulse of current is sent from a general purpose input/output (GPIO) port of the microcontroller,
and

wherein the GPIO port is coupled to a gate of a p-channel field effect transistor (FET) and a first end of a first resistor,
a second end of the first resistor is connected to a source of the p-channel FET, and a drain of the p-channel FET is connected
to a diode.

US Pat. No. 9,274,792

COMPILER-CONTROLLED REGION SCHEDULING FOR SIMD EXECUTION OF THREADS

NVIDIA Corporation, Sant...

1. A method for scheduling threads to execute different regions of a program, the method comprising:
analyzing a control flow graph that is based on program code and comprises a plurality of regions, wherein each region represents
a different portion of the program code, is assigned an execution priority, and has a thread frontier that includes one or
more thread frontier regions, each thread frontier region being one of the plurality of regions in the control flow graph;

inserting one or more update predicate mask variable instructions at the end of a first region included in the plurality of
regions based on the control flow graph and the program code; and

inserting one or more conditional branch instructions at the end of the first region that are arranged to reflect execution
priority of the one or more thread frontier regions in the thread frontier of the first region.

US Pat. No. 9,244,810

DEBUGGER GRAPHICAL USER INTERFACE SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT

NVIDIA Corporation, Sant...

1. A computer program product embodied on a non-transitory computer readable medium for a graphical user interface (GUI) of
a debugger, the computer program product including code adapted to be executed by a computer to perform a method comprising:
invoking, by a system, a debugger in a first mode that is a browsing only mode not associated with a signal dump;
during operation of the debugger in the first mode:
identifying, by the system, one of a source database and a hardware database,
determining, by the system, constructs using the one of the source database and the hardware database,
displaying, by the system, in a first portion of a GUI of the debugger a list of the constructs determined from the one of
the source database and the hardware database, and

displaying, by the system, in a second portion of the GUI of the debugger source code corresponding to the constructs;
invoking, by the system, the debugger in a second mode that is a waveform mode associated with the signal dump;
during operation of the debugger in the second mode:
identifying, by the system, the hardware database,
determining, by the system, the constructs using the hardware database,
displaying, by the system, in the first portion of the GUI of the debugger a list of the constructs determined using the hardware
database,

displaying, by the system, in the second portion of the GUI of the debugger the source code corresponding to the constructs,
enabling, by the system, an option within the GUI allowing a user to toggle from displaying in the second portion of the GUI
of the debugger the source code corresponding to the constructs to displaying in the second portion of the GUI of the debugger
waveforms corresponding to the constructs,

receiving, through the option by the system from the user, a request to toggle from displaying in the second portion of the
GUI of the debugger the source code corresponding to the constructs to displaying in the second portion of the GUI of the
debugger waveforms corresponding to the constructs,

identifying, by the system, the signal dump;
determining, by the system, waveforms corresponding to the constructs, using the signal dump, and
in response to receiving the request, displaying, by the system, in the second portion of the GUI of the debugger the waveforms
corresponding to the constructs.

US Pat. No. 9,245,595

SYSTEM AND METHOD FOR PERFORMING SRAM ACCESS ASSISTS USING VSS BOOST

NVIDIA Corporation, Sant...

1. A method comprising:
receiving a memory access request at a storage cell array comprising two or more storage cell subarrays, each storage cell
subarray including at least one row of storage cells, wherein the memory access request specifies a read operation or a write
operation and a voltage boost is applied during both read and write operations; and

applying, during the memory access, the voltage boost to a first negative supply rail of a first storage cell subarray of
the two or more storage cell subarrays, wherein a boosted voltage of the first negative supply rail of the first storage cell
subarray is lower than a voltage of a second negative supply rail of a second storage cell subarray of the two or more storage
cell subarrays.

US Pat. No. 9,245,601

HIGH-DENSITY LATCH ARRAYS

NVIDIA Corporation, Sant...

1. A device comprising:
an array of cells arranged into columns and rows, wherein each cell comprises a latch cell that includes a transmission gate,
a pair of inverters, and an output buffer,

wherein each row of latch cells is connected to at least one common node for addressing the row of latch cells, and
wherein each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal,
wherein the pair of inverters comprises an inverter having an input coupled to an output of a tri-state inverter, and wherein
an input of the tri-state inverter is coupled to an output of the inverter.

US Pat. No. 9,256,623

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR SCHEDULING TASKS ASSOCIATED WITH CONTINUATION THREAD BLOCKS

NVIDIA Corporation, Sant...

1. A method comprising:
generating a first task metadata data structure in a memory;
generating a second task metadata data structure in the memory, wherein the second task metadata data structure is related
to the first task metadata data structure;

executing a first task corresponding to the first task metadata data structure in a processor, wherein at least one instruction
in the first task causes one or more child tasks to be executed by the processor;

generating state information representing a continuation task related to the first task and storing the state information
in the second task metadata data structure;

executing the continuation task in the processor after the one or more child tasks have finished execution; and
indicating that the first task has logically finished execution when the continuation task has finished execution,
wherein the continuation task comprises one or more instructions that are dependent on at least one intermediate value produced
by the one or more child tasks.

US Pat. No. 9,239,795

EFFICIENT CACHE MANAGEMENT IN A TILED ARCHITECTURE

NVIDIA Corporation, Sant...

1. A subsystem configured to cache data in a tile-based architecture, comprising:
a fetch controller configured to issue requests for portions of data; and
a cache unit coupled to the fetch controller and configured to:
receive a request for a first portion of data corresponding to a first subregion associated with a screen tile from the fetch
controller,

determine that the first portion of data is not resident in the cache unit,
acquire the first portion of data from a memory unit,
identify, based on a cache policy, a first cache line in the cache unit that stores a second portion of data corresponding
to a second subregion associated with the screen tile, wherein the cache policy indicates that one or more portions of data
corresponding to the second subregion should be evicted before one or more portions of data corresponding to other subregions
associated with the screen tile are evicted,

evict the second portion of data from the first cache line, and
after evicting, store the first portion of data in the first cache line.

US Pat. No. 9,250,683

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ALLOWING A HEAD TO ENTER A REDUCED POWER MODE

NVIDIA Corporation, Sant...

1. An apparatus, comprising:
a first processor having a head;
a second processor having a head; and
a link coupled between the head of the first processor and the head of the second processor for communicating first data therebetween;
wherein the apparatus is operable such that the head of the second processor is capable of entering a head reduced power mode
corresponding to the second processor, while at least a portion of the head of the first processor is configured in a reduced
power mode and while one or more other portions of the head of the first processor is not configured in the reduced power
mode.

US Pat. No. 9,245,363

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT IMPLEMENTING AN ALGORITHM FOR PERFORMING THIN VOXELIZATION OF A THREE-DIMENSIONAL MODEL

NVIDIA Corporation, Sant...

1. A method comprising:
receiving a surface at a processing engine;
mapping, by the processing engine, the surface onto a plurality of volumetric picture elements (voxels) by:
projecting the surface onto a two dimensional plane associated with a major dimension of a normal to the surface,
selecting a subset of voxels in the plurality of voxels based on the projection of the surface,
dividing the subset of voxels into one or more columns of voxels, and
for each column of voxels, tagging each voxel in the column of voxels associated with a crosshair shape that intersects any
point on the surface; and

generating, by the processing engine, a value for each voxel in the plurality of voxels that is tagged,
wherein a voxel intersects with the surface when the surface intersects the crosshair shape associated with the voxel, and
wherein the processing engine is at least one of a software engine executed by a processor or a hardware engine included in
the processor.

US Pat. No. 9,250,931

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CALCULATING SETTINGS FOR A DEVICE, UTILIZING ONE OR MORE CONSTRAINTS

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying a plurality of parameters associated with a device, including descriptions of hardware and software installed
within the device;

creating a directed acyclic graph (DAG) including a plurality of nodes, where each of the nodes represents a unique variation
of the plurality of parameters associated with the device and where at least one node of the DAG is directly pointed to by
two or more additional nodes of the DAG,

determining, for each of the plurality of nodes, a speed associated with the node, where the speed is determined based on
the parameters represented by the node, and

directing the plurality of nodes within the DAG based on the speed associated with each node; and
calculating one or more settings for the device, utilizing the plurality of nodes included within the DAG.

US Pat. No. 9,251,557

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR RECOVERING FROM A MEMORY UNDERFLOW CONDITION ASSOCIATED WITH GENERATING VIDEO SIGNALS

NVIDIA Corporation, Sant...

1. A method comprising:
determining that a first counter is greater than a second counter, wherein the first counter represents a number of pixels
that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested
from a memory for the current frame;

incrementing an address corresponding to a memory fetch request by an offset; and
issuing the memory fetch request to a memory,
wherein the offset is equal to the difference between the first counter and the second counter plus a threshold value.

US Pat. No. 9,454,806

EFFICIENT APPROXIMATE-NEAREST-NEIGHBOR (ANN) SEARCH FOR HIGH-QUALITY COLLABORATIVE FILTERING

NVIDIA CORPORATION, Sant...

1. A computer implemented method of performing an approximate-nearest-neighbor search, said method comprising:
splitting an image into a plurality of tiles;
for each of said plurality of tiles, perform the following in parallel on a processor:
dividing image patches into a plurality of clusters, wherein each cluster comprises similar images patches, and wherein said
dividing continues recursively until a size of a cluster is below a threshold value;

performing a nearest-neighbor query within each of said plurality of clusters; and
performing collaborative filtering in parallel for each image patch, wherein said collaborative filtering aggregates and processes
nearest neighbor image patches from a same cluster containing a respective image patch to form an output image.

US Pat. No. 9,071,244

GROUND REFERENCED SINGLE-ENDED SIGNALING

NVIDIA Corporation, Sant...

1. A transmitter circuit, comprising:
a precharge with flying capacitor sub-circuit that includes a first flying capacitor configured to be precharged to a ground
supply voltage during a positive phase of a clock and a second flying capacitor configured to be precharged to the ground
supply voltage during a negative phase of the clock; and

a discharge and multiplexor sub-circuit that is configured to:
couple the first flying capacitor to a single-ended signaling line during the negative phase of the clock to drive the single-ended
signaling line based on a first data signal; and

couple the second flying capacitor to the single-ended signaling line during the positive phase of the clock to drive the
single-ended signaling line based on a second data signal.

US Pat. No. 9,147,447

GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT

NVIDIA Corporation, Sant...

1. A system, comprising:
a first processing unit configured to include a first ground-referenced single-ended signaling (GRS) interface circuit, wherein
the first GRS interface circuit is configured to include a unidirectional transmitter circuit and a bidirectional transceiver
circuit;

a memory subsystem configured to include a second GRS interface circuit; and
a package configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface,
wherein the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along
one trace of the one or more electrical traces, and

wherein the bidirectional transceiver circuit is configured to transmit write data via GRS signals coupled to the one or more
electrical traces by serializing data from an on-chip write bus to generate corresponding GRS signals for transmission via
the one or more electrical traces.

US Pat. No. 9,355,492

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR UTILIZING A WAVEFRONT PATH TRACER

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying, by a processor, a set of light transport paths associated with a scene;
performing, by the processor, parallel path tracing, utilizing a wavefront path tracer that uses a structure of arrays (SOA)
memory layout, wherein performing the parallel path tracing further comprises regenerating one or more new light transport
paths, utilizing one or more queues associated with one or more chunks.

US Pat. No. 9,384,001

CUSTOM CHAINING STUBS FOR INSTRUCTION CODE TRANSLATION

NVIDIA CORPORATION, Sant...

1. A method of executing instruction code in a processing system comprising a microprocessor comprising a hardware decoder,
the method comprising:
translating instruction code in a form non-native to the microprocessor into a translated instruction set native to the microprocessor
using a translator, wherein the translated instruction set comprises a branch instruction with a target address external to
the translation;

connecting the branch instruction to a chaining stub operable to selectively allow additional instruction code at the target
address to be directly received and decoded in a hardware decoder, wherein the hardware decoder is operable to decode instruction
code for execution in the microprocessor;

executing the translated instruction set until the chaining stub is reached; and
decoding and executing the additional instruction code at the target address using the hardware decoder.

US Pat. No. 9,256,914

GRAPHIC CARD FOR COLLABORATIVE COMPUTING THROUGH WIRELESS TECHNOLOGIES

NVIDIA Corporation, Sant...

1. A graphics card for collaborative computing through wireless technologies, the card comprising:
a Graphics Processing Unit (GPU) for data computing;
a wireless controller for wirelessly receiving data from other graphic cards or sending data to the other graphics cards,
and communicating with the GPU by bus; and

a master card circuit that is directly coupled to the GPU and configured to:
determine the GPU has encountered a heavy computing load;
send a help request to the other graphics cards through the wireless controller;
receive a rejection of the help request from a slave card circuit within a first other graphics card of the other graphics
cards;

wirelessly send data to be processed to a second graphic card if the second graphic card accepts the help request; and
wirelessly receive a processing result from the second graphic card.

US Pat. No. 9,274,701

METHOD AND SYSTEM FOR A CREASED PAPER EFFECT ON PAGE LIMITS

NVIDIA CORPORATION, Sant...

1. In a touchscreen viewing device, a method for implementing a crease effect, comprising:
receiving a swipe input related to an image displayed on a touch screen of a viewing device; and
upon determination that the swipe input will generate an item end effect, causing a crease effect to appear on the image in
response to the swipe input, wherein the swipe input comprises an access request beyond an end of data of a file associated
with the image; and

subsequent to the end of the swipe input, undoing the crease effect on the image to return the image to an original effect.

US Pat. No. 9,264,265

SYSTEM AND METHOD OF GENERATING WHITE NOISE FOR USE IN GRAPHICS AND IMAGE PROCESSING

NVIDIA CORPORATION, Sant...

1. A method comprising:
receiving a plurality of samples of one or more hash inputs selected from the group consisting of a primitive coordinate,
and a texel address; and

generating a plurality of white noise samples from a one-way cryptographic hashing said hash input, wherein each sample of
the hash input is evaluated independent and in parallel to each generate one or more white noise samples.

US Pat. No. 9,268,528

SYSTEM AND METHOD FOR DYNAMICALLY REDUCING POWER CONSUMPTION OF FLOATING-POINT LOGIC

NVIDIA Corporation, Sant...

1. A method, comprising:
computing a first number of trailing zeros in a first significand associated with a floating-point format input operand;
computing a second number of trailing zeros in a second significand;
summing the first number of trailing zeros with the second number of trailing zeros to produce a trailing zero sum;
receiving a disable control signal that is based on a characteristic of the floating-point format input operand and the trailing
zero sum;

disabling a portion of a logic circuit based on the disable control signal; and
processing the first significand and the second significand by the logic circuit to generate an output.

US Pat. No. 9,269,183

COMBINED CLIPLESS TIME AND LENS BOUNDS FOR IMPROVED SAMPLE TEST EFFICIENCY IN IMAGE RENDERING

NVIDIA CORPORATION, Sant...

1. A method for reducing the number of sample points tested for rendering a screen space region of an image, the method comprising:
(i) constructing, by a processor, a bilinear approximation per primitive for a screen space region which is to be rendered,
wherein a primitive comprises a plurality of vertices, wherein each vertex is expressed as a function of lens position, projection
direction, and time, and
wherein the screen space region includes a plurality of sample points;
(ii) evaluating the bilinear approximation to estimate coverage of a predefined primitive against one or more sample points
in the screen space region; and

(iii) excluding from testing at least one sample point in the screen space region which is not covered by the predefined primitive,
wherein the bilinear approximation function identifies a region which is uncovered with respect to the predefined primitive.

US Pat. No. 9,239,697

DISPLAY MULTIPLIER PROVIDING INDEPENDENT PIXEL RESOLUTIONS

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving first image data for a first display device;
receiving second image data for a second display device, wherein the second display device has fewer scan lines than the first
display device;

computing a scan line ratio multiplier value as a height in scan lines of a frame including the first image data and the second
image data divided by a height in scan lines of the second display device;

duplicating a scan line of the second image data a number of times based on the scan line ratio multiplier value; and
generating a display multiplier output stream that includes a first scan line of the first image data, the scan line of the
second image data, a second scan line of the first image data, and the duplicated scan line of the second image data.

US Pat. No. 9,071,233

LOW POWER MASTER-SLAVE FLIP-FLOP

NVIDIA Corporation, Sant...

1. A flip-flop circuit comprising:
a clocked pull-up component comprising:
a first clock gated pull-up transistor, coupled to a supply voltage, and
a second clock gated pull-up transistor, coupled to the supply voltage;
a master latch component configured to propagate a true level of an embedded logic function of a data input bundle to a master
true storage node, and a complement of the level of the embedded logic function of the data input bundle to a master complement
storage node when a clock signal is at a first level; and to hold a first value of the master true storage node and hold a
second value of the master complement storage node constant when a clock signal is at a second level; comprising:

a complement pull-up logic cone configured to generate the complement level of the embedded logic function of the data input
bundle, coupled between the first clock gated pull-up transistor and the master complement storage node, and a true pull-up
logic cone configured to generate the true level of the embedded logic function of the data input bundle, coupled between
the second clock gated pull-up transistor and the master true storage node; and

a slave latch component having a slave true storage node and a slave complement storage node, with the slave true storage
node communicatively coupled to the master true storage node when the clock signal is at the second level, so that a value
of the slave true storage node is set equal to the value of the master true storage node, and decoupled when the clock signal
is at the first level, so that the slave true storage node retains a previous value, and with the slave complement storage
node communicatively coupled to the master complement storage node when the clock signal is at the second level, so that a
value of the slave complement storage node is set equal to the value of the master complement storage node, and decoupled
when the clock signal is at the first level, so that the slave complement storage node retains a previous value; comprising:

a transistor gated by the slave true storage node, coupled between the first clock gated pull-up transistor and the slave
complement storage node, and

a transistor gated by the slave complement storage node, coupled between the second clock gated pull-up transistor and the
slave true storage node.

US Pat. No. 9,274,985

APPROACH FOR ALLOCATING VIRTUAL BANK MANAGERS WITHIN A DYNAMIC RANDOM ACCESS MEMORY (DRAM) CONTROLLER TO PHYSICAL BANKS WITHIN A DRAM

NVIDIA Corporation, Sant...

1. A computer-implemented method for allocating virtual bank managers within a dynamic random access memory (DRAM) controller,
the method comprising:
receiving a first memory access request directed to a DRAM comprising a plurality of physical banks;
identifying a first physical bank within the plurality of physical banks that is associated with the first memory access request;
determining whether a first virtual bank manager included in a plurality of virtual bank managers that reside within the DRAM
controller is available for allocation to the first physical bank;

if the first virtual bank manager is available, then:
allocating the first virtual bank manager to the first physical bank; and
associating the first virtual bank manager with the first memory access request; or
if the first virtual bank manager is not available, then:
waiting until the first virtual bank manager is available for allocation;
allocating the first virtual bank manager to the first physical bank; and
associating the first virtual bank manager with the first memory access request.

US Pat. No. 9,258,633

REAR COVER OF FLAT PANEL ELECTRONIC DEVICE AND FLAT PANEL ELECTRONIC DEVICE HAVING THE REAR COVER

NVIDIA Corporation, Sant...

1. A rear cover of a flat panel electronic device comprising:
an outer surface of the rear cover is provided with a recess;
a supporting leg, the supporting leg pivotably connected in the recess through a pivot means enabling the supporting leg to
pivot between a retracting position and an unfolding position, the supporting leg configured to be contained in the recess
when in the retracted position, and making an angle with the rear cover when being in the unfolding position;

a speaker disposed in the supporting leg;
sound holes are disposed at a position on a side wall of the supporting leg corresponding to the speaker;
a through-hole formed at a position of the rear cover corresponding to the pivot means; and
an electric wire of the speaker passing through the through-hole to extend into the rear cover.

US Pat. No. 9,251,551

BINDLESS MEMORY ACCESS IN DIRECT 3D

NVIDIA Corporation, Sant...

1. A computer-implemented method for accessing data objects stored in a memory that is accessible by a graphics processing
unit (GPU), the method comprising:
creating a data object in the memory based on a command received from an application program;
transmitting a first handle associated with the data object to the application program such that data associated with different
graphics commands can be accessed by the GPU, wherein the first handle includes a memory address that provides access to only
a particular portion of the data object;

receiving a first graphics command as well as the first handle from the application program, wherein the first graphics command
includes a draw command or a compute grid launch;

transmitting the first graphics command and the first handle to the GPU for processing; and
configuring a shader program associated with the GPU to perform a bindless memory access directed to the data object via the
first handle based on the first graphics command;

wherein the shader program is configured to intermix bound memory accesses directed to the data object with the bindless memory
access.

US Pat. No. 9,247,179

REVERSE VIDEO PLAYBACK IN A DATA PROCESSING DEVICE

NVIDIA Corporation, Sant...

1. A method comprising:
initiating, through an interface of a data processing device, reverse playback of a video file stored in a memory of the data
processing device;

causing, through at least one of a set of instructions associated with a processor of the data processing device communicatively
coupled to the memory and an operating system executing on the data processing device, the processor to read frames corresponding
to the video file in a reverse chronological order within a desired timeframe following the initiation of the reverse playback,
wherein a timestamp is associated with each one of the frames;

decoding, through the processor, each frame corresponding to the reverse chronological order for rendering thereof on the
data processing device; and

determining a frame rate for the rendering based to maintain a time interval between the timestamps associated with the decoded
frames equal to the time interval between the timestamps associated with the frames during a forward playback of the video
file.

US Pat. No. 9,272,664

NAKED EYE 3D VIDEO SYSTEM FOR BACKING A VEHICLE AND VEHICLE INCLUDING THE SYSTEM

NVIDIA Corporation, Sant...

1. A naked eye 3D video system for backing a vehicle, including:
two cameras for being installed on a rear of the vehicle and configured to capture images of a scene behind the vehicle respectively;
a processor configured to divide the images captured by the two cameras into image strips in equidistance respectively, and
integrate alternatively the divided image strips together into integrated images by interleaving;

a display device for being installed on an instrument panel of the vehicle and configured to display the integrated images
in a form of three dimensions for a driver to watch with naked eyes; and

a position detector configured to detect a distance between a nearest obstacle behind the vehicle and the vehicle on the basis
of the captured images;

wherein the position detector is configured to perform edge detection of the captured images based on a Sobel operator to
determine a nearest edge in the captured images, identify a nearest obstacle that belongs to the nearest edge, and calculate
a distance between the nearest obstacle and the vehicle based on installation positions and an angle between the cameras.

US Pat. No. 9,262,328

USING CACHE HIT INFORMATION TO MANAGE PREFETCHES

NVIDIA CORPORATION, Sant...

1. A system comprising:
a plurality of caches comprising first cache and a second cache, the second cache having greater latency than the first cache;
and

a prefetcher configured to monitor addresses included in access requests to the second cache, detect a pattern to the access
requests, and determine a prefetch distance based on the pattern, the prefetcher further configured to prefetch cache lines
to the second cache that are selected according to the prefetch distance and receive feedback from the second cache, the feedback
indicating whether an access request issued in response to a cache miss in the first cache results in a cache hit in the second
cache, the prefetch distance also determined according to the feedback.

US Pat. No. 9,262,174

DYNAMIC BANK MODE ADDRESSING FOR MEMORY ACCESS

NVIDIA Corporation, Sant...

1. A method for accessing a multi-bank memory, the method comprising:
receiving a first memory access instruction included in a plurality of memory access instructions, wherein a bank mode is
concurrently specified for each memory access instruction in the plurality of memory access instructions, and the first memory
access instruction specifies an individual memory address;

receiving a bank mode that defines a per-bank bit-width for the first memory access instruction, wherein the bank mode specifies
a first memory address-to-bank mapping when the bank mode is a first value and a second memory address-to-bank mapping when
the bank mode is a second value;

dynamically mapping the individual memory address based on the bank mode to produce a mapped individual memory address; and
transmitting a read request or a write request to the multi-bank memory to execute the first memory access instruction.

US Pat. No. 9,251,870

GROUND-REFERENCED SINGLE-ENDED MEMORY INTERCONNECT

NVIDIA Corporation, Sant...

1. A system, comprising:
a first processing unit comprising a first ground-referenced single-ended signaling (GRS) interface circuit;
a first cache memory comprising a second GRS interface circuit; and
a multi-chip module (MCM) package configured to include a ground network and one or more electrical traces that couple the
first GRS interface circuit to the second GRS interface circuit,

wherein the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along
one trace of the one or more electrical traces by discharging a capacitor between the one trace and the ground network, and
current associated with transmitting the pulse is locally balanced between the one trace and the ground network.

US Pat. No. 9,269,182

SYSTEM AND METHOD FOR IDENTIFYING ENTRY POINTS OF A HIERARCHICAL STRUCTURE

NVIDIA Corporation, Sant...

1. A method for identifying a plurality of entry points of a hierarchical structure having a plurality of nodes, the method
comprising:
selecting a first node of a hierarchical structure;
determining the plurality of entry points by performing an entry point search operation at the first node; and
for each entry point in the plurality of entry points, initiating a hierarchical tree operation at the entry point,
wherein the entry point search operation is performed by a processor and comprises the steps of:
performing a node test for the first node;
determining whether the first node is identified as an entry point based on the node test;
if the first node is not identified as an entry point, then inserting any child nodes included in the first node into a node
traversal list, or

if the first node is identified as an entry point, then inserting the first node into an entry point list; and
if the node traversal list is not empty, then selecting a next node from the node traversal list and performing the entry
point search operation at the next node, and

wherein the node test identifies the first node as an entry point when:
a bounding volume associated with a plurality of rays intersects the first node; and
the first node includes a primitive.

US Pat. No. 9,083,577

SAMPLER CIRCUIT FOR A DECISION FEEDBACK EQUALIZER AND METHOD OF USE THEREOF

Nvidia Corporation, Sant...

1. A sampler for sampling an input signal state, comprising:
a first sampler portion including a series-coupled first master regeneration latch and first slave latch;
a second sampler portion including a series-coupled second master regeneration latch and second slave latch; and
a first feedback circuit coupled to a first node between said first master regeneration latch and said first slave latch and
operable to provide a feedback signal to said second master regeneration latch to cause a bias charge to be built up therefor,
wherein said bias charge is generated during a track mode of said sampler and subsequent latching occurs in a regeneration
mode of said sampler.

US Pat. No. 9,563,432

DYNAMIC CONFIGURATION OF PROCESSING PIPELINE BASED ON DETERMINED TYPE OF FETCHED INSTRUCTION

Nvidia Corporation, Sant...

1. A micro-processing system, comprising:
a memory/storage subsystem configured to store instruction code comprising non-native instruction set architecture (ISA) code
and native ISA code in a common address space;

a processing pipeline comprising:
fetch logic configured to fetch portions of the instruction code from the common address space, the fetch logic comprising
address translation logic;

instruction type determining logic configured to determine, at runtime, which of the portions of fetched instruction code
are non-native ISA code;

decode logic downstream of the fetch logic and operable for decoding non-native ISA code into native ISA code;
an arbitration stage downstream of the decode logic; and
execution logic downstream of the decode logic;
wherein the micro-processing system uses a first configuration of the processing pipeline to process portions of the fetched
instruction code that are non-native ISA code in response to determining that those portions are non-native ISA code, wherein
otherwise the micro-processing system uses a second configuration of the processing pipeline to process the portions of the
fetched instruction code that are native ISA code;

wherein the first configuration comprises: the fetch logic including the address translation logic; the decode logic; the
arbitration stage; and the execution logic; and

wherein the second configuration comprises: the fetch logic but the address translation logic is bypassed; the arbitration
stage; and the execution logic, wherein the decode logic is bypassed in the second configuration;

wherein the arbitration stage is operable for merging native ISA code output from the decode logic and native ISA code output
from the fetch logic for execution by the execution logic.

US Pat. No. 9,263,000

LEVERAGING COMPRESSION FOR DISPLAY BUFFER BLIT IN A GRAPHICS SYSTEM HAVING AN INTEGRATED GRAPHICS PROCESSING UNIT AND A DISCRETE GRAPHICS PROCESSING UNIT

NVIDIA Corporation, Sant...

1. A method of operating a multi-graphics processor system with a limited bus bandwidth, comprising:
rendering a frame utilizing a discrete graphics processing unit (dGPU) that includes a video encoder and a graphics processing
core, wherein the frame is stored in a local memory associated with the dGPU;

compressing the frame via the video encoder; and
copying, via an intra-system bus, the compressed frame from the local memory to a frame buffer included in a system memory
associated with a processor that includes a central processing unit (CPU), an integrated graphics processing unit (iGPU),
a display controller, and a video decoder,

wherein the video decoder decompresses the compressed frame and stores the decompressed frame in the frame buffer, and
wherein the video encoder utilizes an industry standard compression protocol to compress the frames, the industry standard
compression protocol being compatible with the video decoder.

US Pat. No. 9,274,743

DEDICATED VOICE/AUDIO PROCESSING THROUGH A GRAPHICS PROCESSING UNIT (GPU) OF A DATA PROCESSING DEVICE

NVIDIA Corporation, Sant...

1. A method comprising:
receiving input audio data by a Graphics Processing Unit (GPU) of a data processing device from a Central Processing Unit
(CPU) of the data processing device;

implementing by the GPU a voice/audio processing engine stored in a memory of the GPU in the data processing device, the voice/audio
processing engine including a plurality of processing algorithms;

decoding, by the voice/audio processing engine of the GPU, the input audio data into a text or machine-readable format;
performing, by the voice/audio processing engine of the GPU, a contextual interpretation of the decoded input audio data,
utilizing a content database stored in the memory of the GPU containing word meanings, contextual information, and search
results;

processing, by another processing engine of the GPU separate from the voice/audio processing engine, display data associated
with the input audio data; and

combining results of the contextual interpretation of the decoded input audio data with the processed display data.

US Pat. No. 9,301,395

VOLTAGE NOISE REDUCTION THROUGH CO-LAYOUTS OF MULTILAYER CERAMIC CAPACITORS AND SOLID ELECTROLYTIC POLYMER CAPACITORS

NVIDIA Corporation, Sant...

1. A surface mounted layout to reduce voltage noise on a printed circuit board, comprising:
a first co-layout of multilayer ceramic capacitors mounted on a first corner of a rectangular footprint of a bottom side of
the printed circuit board;

a second co-layout of multilayer ceramic capacitors mounted on a second corner of the rectangular footprint of the bottom
side of the printed circuit board diagonal to the first corner; and

a first solid electrolytic polymer capacitor and a second solid electrolytic polymer capacitor mounted on the remaining corners,
respectively, of the rectangular footprint of the bottom side of the printed circuit board,

wherein the rectangular footprint of the printed circuit board is a footprint of a high-speed processing unit mounted on the
printed circuit board, and

wherein the high-speed processing unit is mounted on a top side of the printed circuit board opposite the bottom side comprising
the first co-layout of multilayer ceramic capacitors and the second co-layout of multilayer ceramic capacitors, and

wherein a set of leads of at least one of the first co-layout of multilayer ceramic capacitors, the first solid electrolytic
polymer capacitor, the second co-layout of multilayer ceramic capacitors, and the second solid electrolytic polymer capacitor
is coupled to at least one of a voltage supply pin and a ground pin of a voltage supply of the high-speed processing unit
through a via.

US Pat. No. 9,146,949

DATA STRUCTURES AND STATE TRACKING FOR NETWORK PROTOCOL PROCESSING

NVIDIA CORPORATION, Sant...

1. A method of forming hashing table chains, comprising:
obtaining a first connection hash value, the first connection hash value pointing to a first slot in the hashing table;
obtaining a second connection hash value, the second connection hash value pointing to the first slot in the hashing table;
assigning the second connection hash value to a second slot in the hashing table;
pointing the first slot toward the second slot;
obtaining a third connection hash value, the third connection hash value pointing to the second slot in the hashing table;
moving contents of the second slot to a third slot in the hashing table; and
assigning the third connection hash value to the second slot in the hashing table.

US Pat. No. 9,092,658

AUTOMATIC DETECTION OF STEREOSCOPIC CONTENT IN VIDEO/IMAGE DATA

NVIDIA Corporation, Sant...

1. A method comprising:
calculating, utilizing a processor, a correlation between two portions of an image created by dividing the image utilizing
a vertical reference edge, including determining for each of a plurality of rows of the image an offset between the two portions
of the image, and calculating an average offset for the image by averaging the plurality of offsets for the plurality of rows;
and

determining whether the image is stereoscopic by calculating a sample variance of the plurality of offsets, and determining
that the image is stereoscopic if the sample variance is below a predetermined threshold value.

US Pat. No. 9,286,114

SYSTEM AND METHOD FOR LAUNCHING DATA PARALLEL AND TASK PARALLEL APPLICATION THREADS AND GRAPHICS PROCESSING UNIT INCORPORATING THE SAME

NVIDIA CORPORATION, Sant...

1. A system for launching data parallel and task parallel application threads, comprising:
a global thread launcher operable to retrieve a launch request from a queue and track buffer resources associated with said
launch request and allocate output buffers therefor, said global thread launcher included in a processor of said system and
said queue and output buffers included in a memory of said system, wherein said global thread launcher is further configured
to track any interlocks associated with said launch request;

a queue manager associated with said global thread launcher and operable to store a new launch request in said queue; and
a local thread launcher, separate from said global thread launcher and included in a streaming multiprocessor of said system
and operable to receive said launch request from said global thread launcher, set a program counter and resource pointers
of pipelines of the streaming multiprocessor and receive reports from pipelines thereof as threads complete execution.

US Pat. No. 9,215,528

FLAT PANEL ELECTRONIC DEVICE AND AUDIO PLAYING APPARATUS THEREOF

NVIDIA CORPORATION, Sant...

1. An audio playing apparatus for a flat panel electronic device, comprising:
an audio generator operable to generate a left channel audio and a right channel audio;
a sensor operable to detect a placed state of the flat panel electronic device, the placed state including a portrait state
and a landscape state;

a plurality of speakers configured such that at least one pair of speakers of the plurality of speakers is symmetrically disposed
at a left side and a right side of the flat panel electronic device with respect to a user, irrespective of the placed state
that the flat panel electronic device is placed; and

a controller operable to receive a detecting signal from the sensor and control, based on the detecting signal and a playing
mode of the audio playing apparatus, the plurality of speakers such that the at least one pair of speakers plays the left
channel audio and the right channel audio correspondingly according to the placed state of the flat panel electronic device;

wherein the audio playing apparatus has a power saving mode, and the controller is operable to control only one pair of speakers
of the plurality of speakers to play the left channel audio and the right channel audio correspondingly under the power saving
mode.

US Pat. No. 9,331,869

INPUT/OUTPUT REQUEST PACKET HANDLING TECHNIQUES BY A DEVICE SPECIFIC KERNEL MODE DRIVER

NVIDIA CORPORATION, Sant...

1. One or more non-transitory computing device readable media having computing device executable instructions which when executed
perform a method comprising:
receiving, by a device specific kernel mode driver, a dispatch table including a pluralityy of input/output manager function
pointers;

sending, by the device specific kernel mode driver to an operating system kernel mode driver, the dispatch table including
the plurality of input/output manager function pointers;

receiving, by the device specific kernel mode driver, a dispatch table including the plurality of input/output manager function
pointers and a plurality of operating system function pointers;

storing, by the device specific kernel mode driver, the dispatch table including the plurality of input/output manager function
pointers and the plurality of operating system function pointers;

creating, by the device specific kernel mode driver, a dispatch table including the plurality of input/output manager function
pointers and the plurality of operating system functions wherein one or more of the operating system function pointers are
replaced by one or more device specific kernel mode driver function pointers;

sending, by the device specific kernel mode driver to an input/output manager, the dispatch table including, the plurality
of input/output manager function pointers and the plurality of operating system functions wherein one or more of the operating
system function pointers are replaced by one or more device specific kernel mode driver function pointers;

receiving, by a device specific kernel mode driver, a input/output request packet from the input/output manager based on the
dispatch table including the plurality of input/output manager function pointers and the plurality of operating system functions
wherein one or more of the operating system function pointers are replaced by one or more device specific kernel mode driver
function pointers from the device specific kernel mode driver to the input/output manager;

determining, by the device specific kernel mode driver, if the input/output request packet is to receive a given handling;
dispatching, by the device specific kernel mode driver using an operating system function pointer in the dispatch table stored
by the device specific kernel mode driver, the input/output request packet to a device specific dispatch input/output request
packet handler if the input/output request packet is to receive the given handling; and

redirecting, by the device specific kernel mode driver using an operating system function pointer in the dispatch table stored
by the device specific kernel mode driver, the input/output request packet to an operating system dispatch input/output request
packet handler if the input/output request packet is not to receive the given handling.

US Pat. No. 9,281,054

TECHNIQUE FOR OPTIMIZING STATIC RANDOM-ACCESS MEMORY PASSIVE POWER CONSUMPTION

NVIDIA Corporation, Sant...

1. A computer-implemented method for performing a memory access operation with a memory module, the method comprising:
identifying a row of bit cells residing within the memory module;
determining that the memory access operation involves a subset of bit cells within the row of bit cells, wherein each bit
cell in the subset of bit cells is indexed with a numerical value having a first parity;

pre-charging the subset of bit cells via a wordline coupled to the subset of bit cells without pre-charging bit cells within
the row of bit cells indexed with a numerical value having a second parity; and

performing the memory access operation with the subset of bit cells.

US Pat. No. 9,262,797

MULTI-SAMPLE SURFACE PROCESSING USING ONE SAMPLE

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving multi-sample pixel data;
determining an encoding state associated with the multi-sample pixel data, wherein a first encoding state indicates that a
single sample represents all samples of a multi-sample pixel, a second encoding state indicates that the single sample represents
one sample of the multi-sample pixel, and a third encoding state indicates that the single sample represents a plurality of
samples of the multi-sample pixel, wherein a number of samples in the plurality of samples is less than a total number of
samples of the multi-sample pixel;

providing data for the single sample to a processing unit;
providing the encoding state to the processing unit;
processing the single sample of the multi-sample pixel by the processing unit to generate processed data for the single sample,
wherein a sample mask is associated with the multi-sample pixel that indicates which samples of the multi-sample pixel are
represented by the processed multi-sample pixel data;

determining whether a second single sample is stored in a buffer for a tile that includes the multi-sample pixel and at least
one additional multi-sample pixel;

determining that the second single sample corresponds to the single sample; and
merging the sample mask with a stored sample mask associated with the second single sample.

US Pat. No. 9,367,946

COMPUTING SYSTEM AND METHOD FOR REPRESENTING VOLUMETRIC DATA FOR A SCENE

NVIDIA CORPORATION, Sant...

1. A computing system, comprising:
a memory configured to store a three-dimensional (3D) clipmap data structure having at least one clip level and at least one
mip level, wherein said 3D clipmap data structure comprises a mipmap data structure having a plurality of levels that span
a scene and compose said at least one clip level and said at least one mip level, said plurality of levels respectively associated
with a plurality of memory pages and said at least one clip level maps less than all of said plurality of memory pages; and

a processor configured to generate voxelized data for a scene and cause said voxelized data to be stored in said 3D clipmap
data structure.

US Pat. No. 9,171,115

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TRANSLATING A COMMON HARDWARE DATABASE INTO A LOGIC CODE MODEL

NVIDIA Corporation, Sant...

1. A computer program product embodied on a non-transitory computer readable medium, comprising:
code for receiving a graph-based common representation of a hardware design stored in a hardware model database, the graph-based
common representation including a plurality of hardware module nodes;

code for generating logic code for each hardware module node of the graph-based common representation of the hardware design;
code for generating flow control code for each hardware module node of the graph-based common representation of the hardware
design; and

code for storing a logic code model of the hardware design that includes the generated logic code and the generated flow control
code, wherein a first hardware module node is either a fanout node or a fanin node, wherein the fanout node corresponds to
a multicast construct or a separate construct and the fanin node corresponds to a merge construct or a select construct, wherein
the hardware design is used to manufacture an integrated circuit.

US Pat. No. 9,490,847

ERROR DETECTION AND CORRECTION FOR EXTERNAL DRAM

NVIDIA Corporation, Sant...

1. A method for accessing a memory unit, the method comprising:
receiving a first data access request associated with a first data sector included in a page within the memory unit, a second
data access request associated with a second data sector included in the page, and an error correction code (ECC) access request
associated with an ECC sector corresponding to the first data sector and the second data sector;

accessing the first data sector to process the first data access request;
accessing the second data sector to process the second data access request; and
accessing the ECC sector only once when performing an operation on ECC data stored in the ECC sector, wherein the ECC data
corresponds to data associated with the first data access request and data associated with the second data access request.

US Pat. No. 9,269,179

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GENERATING PRIMITIVE SPECIFIC ATTRIBUTES

NVIDIA Corporation, Sant...

1. A method, comprising:
generating, by a vertex shader, per-vertex attributes for a first provoking vertex associated with a first primitive,
wherein the first provoking vertex determines constant primary and secondary colors associated with the first primitive when
flat shading is enabled;

generating, by a geometry shader, one or more primitive-specific attributes in association with the first primitive;
determining that a portion of a graphics processor is operating in a fast geometry shader mode;
determining that the first provoking vertex associated with the first primitive is also associated with a second primitive;
invalidating the association between the first provoking vertex and the second primitive such that the first provoking vertex
is unique to the first primitive; and

creating a new instance of the first provoking vertex to produce a second provoking vertex that is associated only with the
second primitive, wherein the second provoking vertex determines constant primary and secondary colors associated with the
second primitive when flat shading is enabled.

US Pat. No. 9,165,399

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INPUTTING MODIFIED COVERAGE DATA INTO A PIXEL SHADER

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving coverage data at a depth/stencil test module, wherein the coverage data includes two-dimensional (2D) raster coverage
data output by a rasterization module that indicates which subsamples within a multi-sampled pattern are covered by a primitive;

modifying the coverage data by the depth/stencil test module to generate modified coverage data, wherein the coverage data
is modified by modifying values in the coverage data for any subsamples that fail a depth/stencil test;

inputting the modified coverage data into a pixel shader; and
performing one or more actions at the pixel shader, utilizing the modified coverage data,
wherein the rasterization module, the depth/stencil test module, and the pixel shader are included in a rendering pipeline
implemented by a graphics processing unit.

US Pat. No. 9,118,932

ADAPTIVE FILTERING MECHANISM TO REMOVE ENCODING ARTIFACTS IN VIDEO DATA

NVIDIA Corporation, Sant...

1. A method comprising:
determining, through at least one of a processor of a data processing device communicatively coupled to a memory and a hardware
engine, edge pixels and flat pixels of a video frame of a video sequence during one of decoding thereof and post-processing
associated with the decoding based on a predetermined threshold, the edge pixels being associated with at least one edge of
the video frame around which there is a change in intensity level above a threshold value thereof and the flat pixels being
associated with at least one area of the video frame around which the change in the intensity level is below the threshold
value;

quantifying, through the at least one of the processor and the hardware engine, spatial correlation of pixels of the video
frame around the at least one edge to estimate a strength of ringing artifacts therein, persistence of the ringing artifacts
within the video frame and temporal persistence thereof across the video frame and another video frame of the video sequence
based on the determined edge pixels and the flat pixels and a raw output of the decoding;

adaptively and spatially filtering, through an edge preserving filter implemented through at least one of: executing instructions
on the processor and the hardware engine, the pixels around the at least one edge of the video frame based on metadata associated
with the video sequence, the estimated strength of the ringing artifacts, the persistence of the ringing artifacts within
the video frame and the temporal persistence of the ringing artifacts across the video frame and the another video frame;

adaptively and temporally filtering, through the at least one of the processor and the hardware engine, the video frame to
mitigate artifacts resulting from a cumulative effect of compression during encoding of the video sequence; and

blending, through the at least one of the processor and the hardware engine, an output of the adaptive spatial filtering and
the adaptive temporal filtering to generate an output with suppressed ringing artifacts, spatial and temporal persistence
thereof and artifacts resulting from the cumulative effect of compression therein.

US Pat. No. 9,117,284

ASYNCHRONOUS COMPUTE INTEGRATED INTO LARGE-SCALE DATA RENDERING USING DEDICATED, SEPARATE COMPUTING AND RENDERING CLUSTERS

NVIDIA CORPORATION, Sant...

1. An asynchronous computing and rendering system, comprising:
a data storage unit that provides storage for processing a large-scale data set organized in accordance to data subregions;
a computing cluster containing a parallel plurality of asynchronous computing machines that provide compute results based
on the data subregions;

a rendering cluster containing a parallel multiplicity of asynchronous rendering machines, each separate from each of the
parallel plurality of asynchronous computing machines of the computing cluster, coupled to the asynchronous computing machines,
wherein each rendering machine renders a subset of the data subregions;

wherein a proxy geometry is employed in providing compute and rendering results of selected data subregions and each rendering
machine calculates an intersection of the proxy geometry with data subregions it has to process; and

a data interpretation platform coupled to the asynchronous rendering machines that provides user interaction and rendered
viewing capabilities for the large-scale data set.

US Pat. No. 9,086,838

SYNCHRONOUS MEDIA DISPLAY THROUGH AUTOMATIC HARDWARE PROFILES ACROSS MULTIPLE DISPLAY UNITS

NVIDIA Corporation, Sant...

10. A system comprising:
a plurality of display units; and
a data processing device communicatively coupled to the plurality of display units, the data processing device configured
to:

automatically identify hardware profile data associated with a plurality of display units;
create a set of synchronization settings when the hardware profile data does not match a set of settings in a hardware profile
lookup table; and

automatically apply the set of synchronization settings to simultaneously display a sequence of graphics signals across the
plurality of display units.

US Pat. No. 9,268,601

API FOR LAUNCHING WORK ON A PROCESSOR

NVIDIA Corporation, Sant...

1. A computer-implemented method for launching work on a processor, the method comprising:
initializing, via an application programming interface (API), a first state object that is assigned to a first workload and
resides within a memory region accessible to a program executing on the processor;

populating the first state object with data that indicates a first number of cooperative thread arrays (CTAs) that are responsible
for processing the first workload that is generated by the program, wherein the first number is greater than or equal to two;

generating the first number of CTAs in order to process the first workload on the processor according to the data within the
first state object;

launching, via the API, the first number of CTAs for a queue-based launcher using data elements stored in a queue buffer;
and

invalidating, via the API, an instruction cache associated with the first data object prior to launching the first number
of CTAs;

wherein a structure of the first state object is dynamic.

US Pat. No. 9,286,659

MULTI-SAMPLE SURFACE PROCESSING USING SAMPLE SUBSETS

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving multi-sample pixel data read from a memory storing multi-sample pixel data;
analyzing the multi-sample pixel data, by an analysis unit that is coupled between the memory and a processing unit, to identify
subsets of samples of a multi-sample pixel that have equal data, such that data for one sample in a subset represents multi-sample
pixel data for all samples in the subset;

generating an encoding state that indicates which samples of the multi-sample pixel are included in each one of the subsets;
providing the encoding state and only data for a first sample that is included in a first subset to the processing unit;
determining, by the processing unit, that the encoding state indicates that the first sample does not represent all of the
samples of the multi-sample pixel; and

requesting multi-sample pixel data for one or more additional samples of the multi-sample pixel.

US Pat. No. 9,274,859

MULTI PROCESSOR AND MULTI THREAD SAFE MESSAGE QUEUE WITH HARDWARE ASSISTANCE

NVIDIA CORPORATION, Sant...

1. A method of updating a message queue, said method comprising:
storing, in a message queue, a first message token associated with a first message, wherein said message queue is coupled
to a first processor and a second processor;

determining if there is sufficient space in said message queue for a second message token associated with a second message;
if it is determined that sufficient space exists in said message queue for said second message token, updating said message
queue by initiating a writing of said second message token into said message queue; and

if it is determined that sufficient space does not exist in said message queue for said second message token, responsive to
the determination that sufficient space does not exist in said message queue preparing to put a software component into a
wait condition by copying a program counter into a temporary space, disabling interrupts and setting a program counter to
a full handler sub-method wherein a hardware component disables said interrupts and a software component later enables said
interrupts.

US Pat. No. 9,246,481

SYSTEM AND METHOD FOR A DYNAMIC VOLTAGE CONTROLLED OSCILLATOR

NVIDIA Corporation, Sant...

1. A method, comprising:
transmitting a first signal to a memory delay structure included in a digital voltage controlled oscillator (DVCO), wherein
the memory delay structure comprises an array of memory cells configured to model signal propagation through other instances
of arrays of memory cells included in a particular clock domain;

selecting a row of memory cells within the array of memory cells;
sensing a plurality of column signals associated with the selected row of memory cells; and
generating a memory delay signature signal based on the plurality of column signals, wherein the memory delay signature signal
is configured to indicate a longest propagation delay through the selected row of memory cells.

US Pat. No. 9,077,329

LATCH CIRCUIT WITH A BRIDGING DEVICE

NVIDIA Corporation, Sant...

1. A latch circuit, comprising:
a storage sub-circuit including two cross-coupled inverters and configured to capture a level of an input signal when a clock
signal transitions from a first level to a second level and hold the captured level of the input signal to generate an output
signal that equals the captured level of the input signal while the clock signal is at the second level, wherein the inverters
each have a supply terminal coupled to ground;

a bridging transistor coupled between the supply terminals and configured to connect the supply terminals to each other and
to the ground when the bridging transistor is turned on; and

a propagation sub-circuit configured to receive the input signal and propagate the input signal to generate the output signal
so that the input signal is passed through to the output signal while the clock signal is at the first level, wherein at least
one pull-up transistor activates the propagation sub-circuit when the clock signal is at the first level and deactivates the
propagation sub-circuit when the clock signal is at the second level.

US Pat. No. 9,281,817

POWER CONSERVATION USING GRAY-CODED ADDRESS SEQUENCING

NVIDIA CORPORATION, Sant...

1. An integrated circuit comprising:
sequential logic operable to store and output a plurality of data, wherein a respective location of each of said plurality
of data in said sequential logic is assigned a respective address represented by a plurality of digits;

sequence generation logic operable to generate an address sequence that comprises a sequence of addresses of said plurality
of data in said sequential logic; and

a multiplexer structure comprising a plurality of levels of multiplexers arranged in a hierarchical order, each level comprising
one or more multiplexers, wherein said multiplexer structure is coupled with an output of said sequential logic and is further
operable to control an output sequence of said plurality of data from said sequential logic in accordance with said address
sequence,

wherein said address sequence is generated based on reducing an aggregate number of transistor switching activities across
said multiplexer structure during outputting said plurality of data from said sequential logic.

US Pat. No. 9,275,491

GPU WORK CREATION AND STATELESS GRAPHICS IN OPENGL

NVIDIA Corporation, Sant...

1. A computer-implemented method for generating work to be processed by a graphics pipeline residing within a graphics processor,
the method comprising:
receiving an indication that a first graphics workload is to be submitted to a command queue associated with the graphics
processor;

allocating, via a first shader thread, a first portion of shader accessible memory for one or more units of state information
that are related to processing the first graphics workload;

populating, via the first shader thread, the first portion of memory with the one or more units of state information;
sorting the first graphics workload and a second graphics workload in an order of execution based on the one or more units
of state information and on state information related to processing the second graphics workload; and

transmitting to the command queue of the graphics processor the one or more units of state information stored within the first
portion of memory and the state information related to processing the second graphics workload, wherein the first graphics
workload and the second graphics workload are processed within the graphics pipeline in the order of execution.

US Pat. No. 9,255,967

SYSTEM AND METHOD FOR MEASURING AN INTEGRATED CIRCUIT AGE

NVIDIA Corporation, Sant...

1. An apparatus, comprising:
a first clock generator for generating a first clock signal;
a second clock generator for generating a second clock signal;
a phase detector in communication with the first clock generator and the second clock generator, the phase detector operable
for receiving the first clock signal from the first clock generator and the second clock signal from the second clock generator,
and outputting a phase difference signal; and

a circuit in communication with the phase detector and the first clock generator, the circuit operable for receiving the first
clock signal from the first clock generator and the phase difference signal from the phase detector, the circuit further operable
for synchronizing the phase difference signal from the phase detector with the first clock signal from the first clock generator;

wherein the phase difference signal is capable of being used as a measure of an integrated circuit age.

US Pat. No. 9,218,691

SYSTEM AND METHOD FOR ENABLING SCENE PROGRAM FUNCTIONALITY

NVIDIA CORPORATION, Sant...

1. A computer-implemented method for rendering a graphics scene, the method comprising:
receiving a call from an application program to execute one or more instances of a first scene program, wherein each instance
of the first scene program is associated with a sequence of graphics commands;

identifying a machine code version of the first scene program and a corresponding high-level version of the first scene program;
determining, based on state information associated with the high-level version of the first scene program, that two or more
instances of the machine code version of the first scene program can be executed in parallel; and

in response, launching two or more threads for parallel execution of the two or more instances of the machine code version
of the first scene program.

US Pat. No. 9,263,106

EFFICIENT COMMAND MAPPING SCHEME FOR SHORT DATA BURST LENGTH MEMORY DEVICES

NVIDIA CORPORATION, Sant...

1. A method of memory controller operation, the method comprising:
receiving a plurality of commands for a memory device from a command bus, the memory device clocked by a clock, wherein at
least one command of the plurality of commands comprises a first command and a second command received within a single clock
cycle of said clock, wherein the memory device executes no more than one data access command each clock cycle;

executing the first command during a first clock cycle;
executing the second command during a second subsequent clock cycle, wherein the second command is a data access command;
and

communicating results of the executed data access command to the memory controller via a data bus, wherein the command bus
comprises bit lines for receiving a column command and a row-activate command at the memory device, and wherein the second
command utilizes at least one bit line of the bit lines for receiving a row-activate command.

US Pat. No. 9,286,256

SHARING DATA CROSSBAR FOR READS AND WRITES IN A DATA CACHE

NVIDIA Corporation, Sant...

1. A method for processing a plurality of data requests received from a client entity within a computing device, the method
comprising:
determining an instruction type and an address associated with each data request included in the plurality of data requests,
wherein the instruction type comprises a local, shared, or global instruction type, and the plurality of data requests are
directed towards a memory unit that includes a plurality of memory banks;

identifying a subset of the plurality of data requests to process together, the subset of data requests comprising at least
two data requests for different memory banks of the memory unit, each of the at least two data requests comprising either
a shared instruction type or global instruction type;

processing, by a single arbiter, the subset of data requests within a same single clock cycle of a clock to which arbiter
operations are synchronized; and

scheduling a cache crossbar unit either to transmit data associated with at least one data request included in the subset
of data requests to the memory unit at a second clock cycle or to transmit data associated with the at least one data request
retrieved from the memory unit at the second clock cycle.

US Pat. No. 9,262,837

PCIE CLOCK RATE STEPPING FOR GRAPHICS AND PLATFORM PROCESSORS

NVIDIA Corporation, Sant...

1. A method of modifying a data rate used in communications between a first processor and a second processor via a bus, the
method comprising:
sending, from the first processor, a first handshake signal to the second processor via the bus;
receiving, by the second processor, the first handshake signal from the first processor via the bus;
sending, from the second processor, a second handshake signal to the first processor via the bus;
receiving, by the first processor, the second handshake signal from the second processor via the bus;
determining, by the first processor, based on the received second handshake signal, that the second processor is capable of
transmitting data via the bus at a first modified data rate;

determining, by the second processor, based on the received first handshake signal, that the first processor is capable of
transmitting data via the bus at a second modified data rate;

instructing, by the first processor, the second processor to change a data rate at which the second processor transmits data
via the bus to the first modified data rate;

instructing, by the second processor, the first processor to change a data rate at which the first processor transmits data
via the bus to the second modified data rate;

changing, by the first processor, based on the received instruction from the second processor, the data rate at which the
first processor transmits data via the bus to the second modified data rate; and

changing, by the second processor, based on the received instruction from the first processor, the data rate at which the
second processor transmits data via the bus to the first modified data rate.

US Pat. No. 9,204,422

SCHEDULING MODIFICATION FOR EXPECTED PUBLIC WARNING SYSTEM MESSAGE

NVIDIA CORPORATION, Sant...

1. A modem for use at a terminal, the modem comprising:
a wireless interface arranged to connect to a communications network;
a memory configured to store a priority scheme, the modem configured to handle data received from the communications network
according to the priority scheme while in an operating mode; and

a processor configured to:
receive a message from the communications network via the wireless interface whilst in the operating mode;
assess the message on receipt to determine that one or more public warning message is to be broadcast to the modem from the
communication network in a second later time period; and

based on said determination, modify operation of the modem in the second later time period to ensure said one or more public
warning message is received and acted on by the modem by increasing a priority level associated with the communication channel
used to broadcast data for the one or more time slots of the second later time period to a priority level higher than a priority
level associated with a paging channel (PCH), wherein the priority level defines a priority given to the respective communication
channels for reception of data.

US Pat. No. 9,292,908

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR ENHANCING AN IMAGE UTILIZING A HYPER-CLARITY TRANSFORM

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying an image;
enhancing the identified image utilizing a compositor and a pyramid data structure including a plurality of levels as input
into the compositor, where each of the plurality of levels of the pyramid data structure includes an instance of the identified
image having a unique resolution, an upsampled instance of the identified image, and a resampled instance of the identified
image; and

returning the enhanced image.

US Pat. No. 9,086,933

SYSTEM AND METHOD FOR LAUNCHING CALLABLE FUNCTIONS

NVIDIA CORPORATION, Sant...

1. A driver for launching a callable function, wherein the driver:
recognizes at load time of a program that a first function within the program is a callable function;
generates a second function which:
receives arguments,
translates the arguments from a calling convention for launching a function into a calling convention for calling a callable
function, and

calls the first function using the translated arguments;
receives a procedure call representing a launch of the first function and, in response, launches the second function, wherein
information identifying a collection of data points is received in the procedure call;

launches a plurality of threads, each thread executing the second function for a subset of the data points; and
in response to the procedure call and prior to launching the second function:
allocates metadata for the first function, wherein the metadata include resource requirements of the first function or locations
of resources needed for execution; and

configures the launch of the second function using the metadata.

US Pat. No. 9,411,595

MULTI-THREADED TRANSACTIONAL MEMORY COHERENCE

NVIDIA CORPORATION, Sant...

1. A multi-threaded microprocessor with a transactional memory system, comprising:
a data cache backed by a shared memory resource, the data cache including a plurality of cache locations; and
a cache controller operatively coupled with the data cache and which maintains and controls, for each of the cache locations,
(i) a global state for the cache location specifying coherency of the cache location relative to the shared memory resource
and to a cache location in another data cache backed by the shared memory resource, and

(ii) thread state information associated with a plurality of threads that interact with the cache location, the thread state
information being specified separately from and in addition to the global state, where the cache controller uses the thread
state information to individually control whether each thread can read from and write to the cache location, and to control
whether uncommitted transactions of threads relating to the cache location are to be rolled back.

US Pat. No. 9,292,265

METHOD FOR CONVERGENCE ANALYSIS BASED ON THREAD VARIANCE ANALYSIS

NVIDIA Corporation, Sant...

1. A computer-implemented method for characterizing a thread program, the method comprising:
marking each basic block associated with the thread program as being convergent, wherein each basic block includes a plurality
of instructions and starts with a label instruction and is terminated by a control transfer instruction;

marking a set of instructions associated with each basic block as being invariant;
initializing a work list that includes instructions that are known to be variant relative to the set of instructions;
selecting a first instruction from the work list;
marking the first instruction as variant;
adding successor instructions to the work list based on the first instruction; and
propagating a divergence attribute to identify associated basic blocks as divergent, and to identify instructions within the
associated basic blocks as variant.

US Pat. No. 9,286,119

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR MANAGEMENT OF DEPENDENCY BETWEEN TASKS

NVIDIA Corporation, Sant...

1. A method comprising:
generating a first task data structure for a first task in a memory;
generating a second task data structure in the memory, wherein the second task data structure is a placeholder for a second
task that is dependent on the first task;

storing a pointer to the second task data structure in a first output dependence field of the first task data structure;
setting a reference counter field of the second task data structure to an initial value that indicates a number of dependencies
associated with the second task; and

launching the second task when the reference counter field stores a particular value,
wherein each task data structure comprises a reference counter field, one or more output dependence fields, and a task meta
data (TMD) pointer field, and

wherein the initial value of the reference counter field of the second task data structure is set to prevent the second task
from being launched until the second task is generated in the memory and the TMD pointer field of the second task data structure
is initialized to null to indicate that the second task has not been generated at the time of initialization.

US Pat. No. 9,471,456

INTERLEAVED INSTRUCTION DEBUGGER

NVIDIA CORPORATION, Sant...

1. A method comprising:
monitoring concurrent execution of a plurality of programs each comprising a corresponding plurality of instructions executing
interleaved with other instructions of said corresponding plurality of instructions and other instructions of said plurality
of programs, wherein each of said plurality of instructions comprises at least one operation operating on a plurality of threads;

from a superset of instructions comprising instructions from said plurality of programs executing concurrently, organizing
a first plurality of instructions corresponding to a first program of said plurality of programs based on a first execution
order of said first plurality of instructions, and based on a second execution order of operations of a corresponding instruction
in said first plurality of instructions, and based on a third execution order of threads of a corresponding operation in said
corresponding instruction, wherein an instruction of said first program comprises one or more operations such that each operation
is executed on two or more threads;

generating a result set representing said first plurality of instructions organized based on said first, second, and third
execution orders, wherein said result set comprises data resulting from execution of said first plurality of instructions
such that first data is associated with a corresponding operation of a corresponding instruction in said result set; and

displaying said result set.

US Pat. No. 9,293,380

SYSTEM AND METHOD FOR SELECTING A DERATING FACTOR TO BALANCE USE OF COMPONENTS HAVING DISPARATE ELECTRICAL CHARACTERISTICS

Nvidia Corporation, Sant...

1. A test system for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics
in a wafer fabrication process, comprising:
structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies
over integrated circuit (IC) samples fabricated under different process conditions; and

derating factor selection circuitry coupled to said structural at-speed ATE and configured to employ results of said structural
at-speed tests to identify performance deterioration in said samples, said performance deterioration indicating said derating
factor to be employed in a subsequent wafer fabrication process, wherein said derating factor is applied to a ratio of high-voltage
threshold (HVT) transistors to standard-voltage threshold (SVT) transistors.

US Pat. No. 9,235,392

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPROVED POWER EFFICIENCY DURING PROGRAM CODE EXECUTION

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying, by a processor, input code including ordered programming statements within memory;
generating, by the processor, an initial graph representation of arithmetic operations specified by the ordered programming
statements, wherein the initial graph representation includes nodes corresponding to the arithmetic operations and edges corresponding
to data flow between the nodes;

annotating, by the processor, at least a first portion of the edges of the initial graph representation with predefined attributes
describing requirements related to the corresponding data flow to produce, by the processor, a partially annotated graph representation;

applying, by the processor, a set of propagation rules to each node within the partially annotated graph representation to
update attributes of at least a second portion of the edges of the partially annotated graph representation describing requirements
related to the corresponding data flow and to produce, by the processor, a fully annotated graph representation;

for each edge within the fully annotated graph representation, selecting, by the processor, numerical types for the edge based
on the attributes of the edge describing the requirements related to the corresponding data flow to produce a transformed
graph representation; and

generating, by the processor, output code based on the transformed graph representation.

US Pat. No. 9,711,099

TECHNIQUES FOR AVOIDING AND REMEDYING DC BIAS BUILDUP ON A FLAT PANEL VARIABLE REFRESH RATE DISPLAY

NVIDIA CORPORATION, Sant...

1. A method for driving a display panel having a variable refresh rate, said method comprising:
receiving a current input frame from an image source;
determining a number of re-scanned frames to insert between said current input frame and a subsequent input frame, wherein
said re-scanned frames repeat said input frame, and wherein said determining depends on a minimum refresh interval (MRI) of
said display panel;

calculating respective intervals at which to insert said re-scanned frames between said current input frame and said subsequent
input frame;

determining if a charge accumulation in pixels of said display panel has crossed over a predetermined threshold value; and
responsive to a determination that said charge accumulation has crossed over a predetermined threshold value, performing a
counter-measure to remediate said charge accumulation.

US Pat. No. 9,256,316

POWER GATING A DISPLAY OF A DATA PROCESSING DEVICE DURING CLONING THEREOF ACROSS AN EXTERNAL DISPLAY WHILE RETAINING TOUCH-SENSIBILITY THEREOF

NVIDIA Corporation, Sant...

1. A method comprising:
detecting, through a processor communicatively coupled to a memory, coupling of an external display to a data processing device
including an internal display that includes a display driver circuit configured to modify power levels of a backlight based
on a control signal transmitted from the processor to the display driver circuit;

cloning, through the processor, display data of the internal display on the external display following the detection of the
coupling;

triggering, through a software driver component, the processor to turn off the backlight by transmitting a signal to the display
driver circuit following the cloning; and

maintaining, through the software driver component, a touchscreen capability of the data processing device even when the backlight
of the internal display is turned off,

wherein the touchscreen capability is provided through a touch sensor associated with the internal display, and
wherein the touchscreen capability is maintained based on a control signal. transmitted from the processor to a touch sensor
driver circuit associated with the touch sensor.

US Pat. No. 9,117,392

DIRECT INTERFACING OF AN EXTERNAL GRAPHICS CARD TO A DATA PROCESSING DEVICE AT A MOTHERBOARD-LEVEL

NVIDIA Corporation, Sant...

1. A method comprising:
providing a plurality of Input/Output (I/O) interfaces at a periphery of a motherboard of a data processing device;
providing traces between a processor of the data processing device and the plurality of I/O interfaces across a surface of
the motherboard, the traces providing conductive pathways between circuits of the processor and the plurality of I/O interfaces;

exposing a first I/O interface of the plurality of I/O interfaces using a first port protruding through an external cosmetic
surface of the data processing device when the data processing device is assembled, where the motherboard is located inside
of the external cosmetic surface of the data processing device, and where the first port receives a connector of an external
graphics card located outside of the external cosmetic surface area of the data processing device to enable direct data transfer
between the external graphics card and the data processing device through the exposed first I/O interface by way of the first
port to enhance a processing capability of the data processing device; and

exposing a second I/O interface of the plurality of I/O interfaces using a second port protruding through the external cosmetic
surface of the data processing device to power the external graphics card by the data processing device.

US Pat. No. 9,198,123

COMMUNICATION SYSTEM AND METHOD

Nvidia Corporation, Sant...

1. A modem for use at a terminal, the modem comprising:
first interface apparatus comprising a first wireless transceiver arranged to connect to a wireless cellular network;
second interface apparatus arranged to connect to the terminal; and
processing apparatus arranged to transmit a first request message to a part of the wireless cellular network to request establishment
of a channel to access a further, packet-based network via the first interface apparatus, wherein the first request message
requests said channel as being of a type that supports both a first and second version of a packet protocol;

wherein the processing apparatus is further arranged to receive a first response message via the first interface apparatus,
the first response message indicating rejection of the first request,

wherein the processing apparatus is further arranged, upon detecting that a field in the first response message defines a
reason other than said part of the wireless cellular network does not support first and second versions of the packet protocol
on a single channel, to default to transmit a default request message to said part of the wireless cellular network to request
establishment of a channel to access the further, packet-based network via the first interface apparatus, wherein the default
request message requests said channel as being of a type that supports the first version of the packet protocol.

US Pat. No. 9,176,736

SYSTEM AND METHOD FOR PERFORMING PREDICATED SELECTION OF AN OUTPUT REGISTER

NVIDIA Corporation, Sant...

1. A method comprising:
receiving an instruction having an opcode associated with a first predicate condition and a second predicate condition;
executing the instruction to generate a result;
determining whether the first predicate condition is true;
if the first predicate condition is true, then storing the result of the instruction in a first output register, or
if the first predicate condition is false, then storing the result of the instruction in a second output register; and
determining whether the second predicate condition is true; and
if the second predicate condition is true, then applying a first input argument to the opcode, or
if the second predicate condition is false, then applying a second input argument to the opcode.

US Pat. No. 9,106,401

DETERMINISTIC SYNCHRONIZATION FOR TRANSMITTING SIGNALS BETWEEN DIFFERENT CLOCK DOMAINS

NVIDIA CORPORATION, Sant...

1. A method for transmitting a first signal between a first clock domain and a second clock domain, the method comprising:
determining a relative phase difference between a source clock of the first clock domain and a destination clock of the second
clock domain, wherein the destination clock is not derived from the source clock, and wherein the relative phase difference
is measured for different combinations of delay configurations of the source clock and the destination clock;

configuring a delay element based on the relative phase difference to generate a phase-shifted source clock and a phase-shifted
destination clock; and

transmitting the first signal between the first clock domain and the second clock domain using the phase-shifted source clock
and the phase-shifted destination clock.

US Pat. No. 9,094,095

SUPPORT OF PLURAL BANDWIDTHS IN A TELECOMMUNICATIONS SYSTEM

NVIDIA CORPORATION, Sant...

1. A method for supporting communication between a base station and a plurality of user equipment sharing a plurality of timeslots
in a communication frame and operable over a plurality of bandwidths, the method comprising:
allocating a user equipment at least a first one of a plurality of timeslots in a communication frame, each of the first one
of the plurality of timeslots using a first bandwidth of the plurality of bandwidths and allocating the user equipment at
least a second one of the plurality of timeslots in the communication frame, each of the second one of the plurality of timeslots
using a second bandwidth of the plurality of bandwidths, said first bandwidth different from said second bandwidth.

US Pat. No. 9,070,213

TILE BASED PRECISION RASTERIZATION IN A GRAPHICS PIPELINE

NVIDIA CORPORATION, Sant...

1. In a raster stage of a graphics processor, a method for tile based precision rasterization comprising:
receiving a graphics primitive for screen rasterization in a raster stage of a graphics processor;
rasterizing the graphics primitive at a first level precision to generate a plurality of tiles of pixels using large integer
operands of edge equations used to define said graphics primitive, wherein the rasterizing the graphics primitive comprises
searching a grid of tiles to identify said plurality of tiles; and

rasterizing the tiles at a second level precision to generate covered pixels, wherein the first level precision is higher
than the second level precision, and wherein said second level of precision is based on a number of pixels in each of said
plurality of tiles, wherein each of the plurality of tiles is divided into at least two portions and wherein the at least
two portions are rasterized at a third level precision to address a plurality of pixels comprising each portion and wherein
integer values for addressing the plurality of tiles at the first level precision are larger than integer values for addressing
a plurality of pixels at the second level precision; and

outputting the covered pixels for rendering operations in a subsequent stage of the graphics processor.

US Pat. No. 9,299,312

METHOD AND APPARATUS FOR GENERATING IMAGES USING A COLOR FIELD SEQUENTIAL DISPLAY

NVIDIA Corporation, Sant...

1. A method for displaying auto-stereoscopic image information, the method comprising:
obtaining a line of pixel intensity data that includes a first perspective having a left image and a right image, wherein
each of the left image and the right image includes color channel information for only a first color of a plurality of colors
associated with an auto-stereoscopic image, wherein the line of pixel intensity data is processed based on a pixel clock operating
at a first frequency;

driving the pixel intensity data to a color field sequential display;
receiving at least one line of vertical blanking data that is processed based on the pixel clock operating at a second frequency,
the first and second frequencies being different frequencies; and

updating a backlight state corresponding to a backlight color associated with a backlight coupled to the color field sequential
display, wherein the backlight color corresponds to the first color.

US Pat. No. 9,207,277

SYSTEM AND METHOD FOR GENERATING A YIELD FORECAST BASED ON WAFER ACCEPTANCE TESTS

NVIDIA CORPORATION, Sant...

8. A method for generating a yield forecast for a wafer batch based on an wafer acceptance test (WAT) of a plurality of semiconductor
devices forming a plurality of integrated circuits (ICs) in said wafer batch, comprising:
measuring saturation currents of said plurality of semiconductor devices;
calculating weighted standard deviation of said saturation currents with respect to target NMOS and PMOS saturation currents;
measuring speed performances of said plurality of ICs and generating a speed performance model;
measuring power performances of said plurality of ICs and generating a power performance model;
projecting distributions among said plurality of ICs of speed performances and variations from said power performance model;
and

integrating one of said distributions about a target performance profile to generate said yield forecast.

US Pat. No. 9,324,174

MULTI-CHIP RENDERING WITH STATE CONTROL

NVIDIA Corporation, Sant...

1. A method of rendering a graphical image comprising:
with a central processing unit, providing commands to processors including a first and a second processor:
providing a first device mask command instructing the first processor to execute one or more first commands following the
first device mask command, and further instructing the second processor to not execute the one or more first commands following
the first device mask command;

providing the one or more first commands to the processors, the one or more first commands comprising a command instructing
the processors to turn geometry pulling off;

providing the second device mask command instructing the second processor to execute one or more second commands following
the second device mask command, and further instructing the first processor to not execute the one or more second commands
following the second device mask command;

providing the one or more second commands to the processors, the one or more second commands including a command instructing
the processors to turn geometry pulling on;

providing the third device mask command instructing the first processor to execute one or more third commands following the
third device mask command and further instructing the second processor to execute the one or more third commands following
the third device mask command; and

providing the one or more third commands to the processors, the one or more third commands comprising a rendering command,
wherein the first processor executes the one or more first commands after the first device mask command and before the second
device mask command, then ignores the one or more second commands after the second device mask command and before the third
device mask command, and

wherein the second processor ignores the one or more first commands after the first device mask command and before the second
device mask command, then executes the one or more second commands after the second device mask command and before the third
device mask command.

US Pat. No. 9,222,981

GLOBAL LOW POWER CAPTURE SCHEME FOR CORES

NVIDIA CORPORATION, Sant...

1. A method for testing an integrated circuit, said method comprising:
programming a respective duration of a first time window for each of a plurality of modules on the integrated circuit;
counting a number of pulses of a first clock signal during the first time window for each of the plurality of modules; and
staggering capture pulses to the plurality of modules by generating pulses of a second clock signal for each of the plurality
of modules during a respective second time window, wherein a number of pulses generated is based on a respective number of
first clock signal pulses counted for each of the plurality of modules.

US Pat. No. 9,086,707

SYSTEM AND METHOD FOR MODULATING A DUTY CYCLE OF A SWITCHING MODE POWER SUPPLY

NVIDIA Corporation, Sant...

12. A system to digitally control a switching mode power supply, comprising:
a switching mode power supply configured to deliver at least one of a steady-state output voltage and a steady-state output
current;

a high-speed processing unit that is coupled to the switching mode power supply and comprises:
a power management unit configured to:
calculate a base duty cycle based on at least one of an output voltage of the high-speed processing unit, an output current
of the high-speed processing unit, an input voltage of the high-speed processing unit, and a set of parameters of the switching
mode power supply coupled to the high-speed processing unit is used as a variable in such calculations,

calculate a dynamic offset duty cycle by applying a transfer function to a sampled feedback voltage signal, and
add the base duty cycle to the dynamic offset duty cycle to obtain a duty cycle of the switching mode power supply;
a voltage sensor, embedded in the high-speed processing unit, to sense a plurality of on-die analog feedback voltages of the
high-speed processing unit; and

an analog to digital converter to convert the plurality of on-die analog feedback voltages to a plurality of digital voltage
signals, and wherein the power management unit is configured to continuously sample the plurality of digital voltage signals
to obtain the sampled feedback voltage signal; and

a pulse-width modulator coupled between the switching mode power supply and the high-speed processing unit to modulate the
duty cycle of the switching mode power supply.

US Pat. No. 9,286,247

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING SETTINGS FOR A DEVICE BY UTILIZING A DIRECTED ACYCLIC GRAPH CONTAINING A PLURALITY OF DIRECTED NODES EACH WITH AN ASSOCIATED SPEED AND IMAGE QUALITY

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying a plurality of parameters associated with a device, including descriptions of hardware and software installed
within the device;

creating a directed acyclic graph (DAG) including a plurality of nodes, where each of the nodes represents a unique variation
of the plurality of parameters associated with the device;

determining, for each of the plurality of nodes, a speed associated with the node, where the speed is determined based on
the parameters represented by the node;

directing the plurality of nodes within the DAG based on the speed associated with each node; and
determining one or more settings associated with the device, based on the plurality of nodes within the DAG, including:
identifying a node in the DAG that corresponds to the identified plurality of parameters associated with the device,
determining a first subset of nodes in the DAG including nodes that are known to be slower than or equal in speed to the identified
node,

determining, from the first subset of nodes, a second subset of nodes including nodes for which a monotonic set of presets
have been determined,

identifying a final node from the second subset of nodes that has a determined monotonic set of presets having the highest
output image quality within the second subset of nodes, and

utilizing the determined monotonic set of presets of the identified final node as the one or more settings associated with
the device.

US Pat. No. 9,230,678

INTEGRATED CIRCUIT HAVING AN ENHANCED FUSELESS FUSE STRUCTURE, A METHOD OF MANUFACTURING THE SAME AND A DATA STRUCTURE FOR USE WITH THE FUSELESS FUSE STRUCTURE

Nvidia Corporation, Sant...

1. An integrated circuit having fuses for configuring circuitry thereof, said integrated circuit comprising:
a fuse wrapper configured to decode fuseless fuse data for controlling said fuses;
JTAG registers configured to store fuse register values in designated blocks, wherein said fuse register values and said designated
blocks are determined from said fuseless fuse data; and

options registers configurable by software to store fuse override data for modifying said fuse register values.

US Pat. No. 9,087,469

METHODS AND SYSTEMS FOR AUTOMATICALLY SWITCHING MONITOR SCENE MODES

NVIDIA Corporation, Sant...

11. The method of claim 1, wherein the located scene mode in the profile table includes all activated hardware modules inside of the GPU that are in
the list.

US Pat. No. 9,088,289

SYSTEM AND METHOD FOR INCREASING A VOLTAGE RANGE ASSOCIATED WITH A VOLTAGE CONTROLLED OSCILLATOR

NVIDIA Corporation, Sant...

1. An apparatus, comprising:
a voltage-to-current converter that includes an operational amplifier having a first input connected to a control voltage
and an output connected to a gate of a first transistor;

a current controlled oscillator in communication with the voltage-to-current converter; and
at least one circuit component in communication with the voltage-to-current converter, wherein the at least one circuit component
includes a second transistor having a gate connected to the control voltage.

US Pat. No. 9,367,889

SYSTEM AND METHOD FOR PROPAGATING SCENE INFORMATION TO RENDERERS IN A MULTI-USER, MULTI-SCENE ENVIRONMENT

NVIDIA CORPORATION, Sant...

1. A system for propagating scene information to a renderer, comprising:
an update request receiver operable to receive update requests from said renderer and determine a point from which said renderer
is to be updated, wherein said update requests include requests for changes made to said scene information while said renderer
was inactive; and

an update propagator associated with said update request receiver and operable to employ a graph containing scene information
to construct a change list in response to said update request and transmit said change list toward said renderer, said system
and renderer implemented on a cloud server.

US Pat. No. 9,311,733

EFFICIENT ROUND POINT RASTERIZATION

NVIDIA Corporation, Sant...

1. A method for rasterizing a round point primitive within a tile space, the method comprising:
generating an inclusion boundary based on a size and a location for the round point primitive;
generating a candidate tile region based on the inclusion boundary;
generating a rejection boundary based on a rotation of the inclusion boundary;
generating a set of rasterization tiles based on the candidate tile region and the rejection boundary; and
rasterizing the set of rasterization tiles.

US Pat. No. 9,060,355

MESSAGE HANDLING

NVIDIA CORPORATION, Sant...

1. A method of handling messages at a user equipment received from a communications network during a procedure, the method
implemented at the user equipment comprising:
receiving a first message from the communications network whilst the user equipment is in a first operating state;
processing the first message and entering a second operating state in response to receiving the first message;
receiving a second message from the communications network whilst the user equipment is in the second operating state;
detecting that the second message is a duplicate of the first message; and
checking for an indication that the second message is a potential duplicate of the first message, the indication based on
re-establishment of a signaling radio bearer; wherein:

if said indication is not present, the method comprising transmitting a failure notification to the communications network;
and

if said indication is present, the method comprising discarding the second message and not transmitting a failure notification
to the communications network to prevent failure of said procedure.

US Pat. No. 9,384,583

NETWORK DISTRIBUTED PHYSICS COMPUTATIONS

NVIDIA Corporation, Sant...

1. A method for performing physics computations, the method comprising:
receiving a physics function request and data associated with the physics function request from a rendering computer via a
network;

identifying a physics function associated with the physics function request;
operating a local graphics processing unit (GPU) to perform the identified physics function, thereby generating physics result
data for a first frame, wherein, concurrently with generating physics result data for the first frame, the rendering computer
renders a second frame; and

transmitting the physics result data to the rendering computer via the network.

US Pat. No. 9,286,647

PIXEL SHADER BYPASS FOR LOW POWER GRAPHICS RENDERING

NVIDIA Corporation, Sant...

1. A computer-implemented method for drawing graphical objects within a graphics processing pipeline, the method comprising:
determining that a bypass mode for a first primitive is a no-bypass mode;
rasterizing the first primitive to generate a first set of rasterization results;
generating a first set of colors for the first set of rasterization results via a pixel shader unit;
rasterizing a second primitive to generate a second set of rasterization results;
generating a second set of colors for the second set of rasterization results without the pixel shader unit performing any
processing operations on the second set of rasterization results; and

transmitting the first set of pixel colors and the second set of pixel colors to a raster operations (ROP) unit for further
processing.

US Pat. No. 9,241,146

INTERLEAVED APPROACH TO DEPTH-IMAGE-BASED RENDERING OF STEREOSCOPIC IMAGES

NVIDIA Corporation, Sant...

1. A method for generating stereoscopic images, the method comprising:
receiving a first image frame associated with a first eye;
receiving a first depth frame associated with the first eye;
reprojecting the first image frame based on the first depth frame to create a second image frame associated with a second
eye;

identifying a first pixel in the second image frame that remains unwritten as a result of reprojecting the first image frame;
and

determining a value for the first pixel based on a corresponding pixel in a prior image frame associated with the second eye,
wherein the prior image frame is not reconstructed based on depth information.

US Pat. No. 9,223,409

PORTABLE FUNCTION-EXPANDING DEVICE FOR ELECTRONIC DEVICE

NVIDIA Corporation, Sant...

1. A portable function-expanding device for an electronic device, comprising:
a housing with a plurality of accommodating slots provided on an upper surface thereof for accommodating electronic devices
respectively, wherein a function-expanding interface is provided in each of the accommodating slots for being connected with
a function interface of the electronic device accommodated therein; and

a function means located in the housing and connected with at least one function-expanding interface to fulfill the function-expanding
of the corresponding electronic device,

wherein the function-expanding interface provided in at least one accommodating slot of the housing comprises a video input
interface for being connected with a video output interface of the corresponding electronic device; and

the function means comprises a projecting means, which includes:
a light source;
an electro-optical converting module connected with the video input interface for converting light from the light source into
a light signal corresponding to an electronic signal from the video input interface; and

a portable light amplifier connected with the electro-optical converting module for receiving, amplifying and outputting the
light signal.

US Pat. No. 9,390,042

SYSTEM AND METHOD FOR SENDING ARBITRARY PACKET TYPES ACROSS A DATA CONNECTOR

NVIDIA Corporation, Sant...

1. A computer-implemented method for transmitting packets from a first hardware unit to a second hardware unit across a data
connector, the method comprising:
receiving a first signal that corresponds to a first packet type;
reading a first packet specification from a software register, wherein the first packet specification defines the first packet
type;

generating a packet according to the first packet type based on the first packet specification; and
causing the packet to be transmitted from the first hardware unit to the second hardware unit across the data connector.

US Pat. No. 9,355,483

VARIABLE FRAGMENT SHADING WITH SURFACE RECASTING

NVIDIA Corporation, Sant...

1. A method, comprising:
generating shaded samples that are covered by a primitive fragment at a first shading rate using a first sampling mode;
storing the shaded samples in a target buffer that is associated with the first sampling mode and the first shading rate,
wherein the target buffer represents a first pixel resolution;

receiving a second primitive fragment;
decreasing the first shading rate to produce a second shading rate;
determining a second sampling mode;
recasting the target buffer to represent a second pixel resolution based on the second sampling mode, wherein the second pixel
resolution is lower than the first pixel resolution;

generating additional shaded samples that are covered by the second primitive fragment at the second shading using the second
sampling mode; and

storing the additional shaded samples in the target buffer.

US Pat. No. 9,298,868

HIERARCHICAL PUSHDOWN OF CELLS AND NETS TO ANY LOGICAL DEPTH

NVIDIA Corporation, Sant...

1. A computer-implemented method for automatically generating pushdown structures when designing integrated circuits using
an integrated circuit design tool, the method comprising:
receiving a first set of circuit structures associated with an integrated circuit;
receiving partition boundary information associated with the integrated circuit;
performing a logical pushdown of the first set of circuit structures into a second set of circuit structures associated with
the integrated circuit, wherein each circuit structure in the first set that is logically pushed down into the second set
overlaps at least one circuit structure in the second set, and wherein the logical pushdown amends a logical description of
each circuit structure in the second set;

performing a physical pushdown of the first set of circuit structures into the the second set of circuit structures based
one or more partition boundaries; and

storing a data set corresponding to the second set of circuit structures, wherein the data set includes at least one logical
pushdown structure and at least one physical pushdown structure corresponding to the at least one logical pushdown structure.

US Pat. No. 9,256,265

METHOD AND SYSTEM FOR ARTIFICIALLY AND DYNAMICALLY LIMITING THE FRAMERATE OF A GRAPHICS PROCESSING UNIT

NVIDIA CORPORATION, Sant...

1. A method for limiting the frame rate of a graphics processing unit, the method comprising:
in a computer system comprising an integrated graphics processing unit (GPU) and a discrete GPU,
generating a timestamp in response to a rendering being completed for a current frame of a plurality of frames;
comparing the timestamp for the current rendered frame to a timestamp of a previous frame in the plurality of frames corresponding
to a most recent power source query to determine if a duration of elapsed time between the respective timestamps exceeds a
timing threshold value;

querying a current power source of the computer system to determine if the current power source has changed since the most
recent power source query when the timestamp of the previous frame exceeds the timing threshold value;

in the event the current power source has changed since the most recent power source query, determining if the computer system
is being powered by a first power source of a plurality of power sources;

in the event the power source comprises the first power source of the plurality of power sources, determining if the discrete
GPU is currently in operation; and

automatically limiting a frame rate of the discrete GPU if the frame rate is above a frame rate threshold value in response
to a determination that the discrete GPU is currently in operation.

US Pat. No. 9,224,449

VARIABLE DYNAMIC MEMORY REFRESH

NVIDIA Corporation, Sant...

1. A method, comprising:
refreshing a first region of a memory at a first refresh rate;
characterizing the first region to measure data retention characteristics of the first region by:
copying data from the first region of the memory to a storage resource,
writing a pattern to the first region of the memory,
waiting for a retention time period, and
reading the first region to obtain read data; and
refreshing a second region of the memory at a second refresh rate that is different than the first refresh rate.

US Pat. No. 9,420,657

FLAT PANEL ELECTRONIC DEVICE AND CURRENT CONTROL SYSTEM THEREOF

NVIDIA CORPORATION, Sant...

1. A current control system of a flat panel electronic device, the current control system comprising:
a detecting module operable to detect a current in a main circuit of the flat panel electronic device; and
a control mechanism operable to reduce a brightness level of a backlight unit of the flat panel electronic device when the
current in the main circuit is larger than or equal to a threshold, wherein the current in the main circuit is reduced to
be less than the threshold, wherein the threshold comprises a first threshold signal and a second threshold signal, wherein
the first threshold signal is smaller than the second threshold signal, wherein the control mechanism is operable to control
the backlight unit to reduce to a first brightness level when the current in the main circuit is larger than or equal to the
first threshold signal.

US Pat. No. 9,275,377

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DETERMINING A MONOTONIC SET OF PRESETS

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving at a server from a personal computer separate from the server a plurality of parameters associated with a display
of the personal computer; and

determining, by the server, a monotonic set of presets associated with the personal computer, based on the plurality of parameters,
including:

determining by the server a minimum image quality and associated preset that is provided by the personal computer by adjusting
each of the plurality of parameters to their minimum level,

determining by the server a maximum image quality and associated preset that is provided by the personal computer by incrementally
adjusting the plurality of parameters of the personal computer, utilizing a predetermined algorithm,

calculating by the server a plurality of ascending image quality levels and associated presets from the minimum image quality
to the maximum image quality, and

identifying the monotonic set of presets as the presets associated with the minimum image quality, maximum image quality,
and plurality of ascending image quality levels; and

returning the determined monotonic set of presets to the personal computer from the server.

US Pat. No. 9,250,692

POWER-EFFICIENT PERSONALIZATION OF A COMPUTING ENVIRONMENT OF A DATA PROCESSING DEVICE WITH RESPECT TO A USER THEREOF

NVIDIA Corporation, Sant...

1. A method comprising:
providing, in a data processing device comprising a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), a
capability to interface a microprocessor with the GPU;

communicatively interfacing a sensor with the microprocessor;
obtaining data related to an operating environment external to the data processing device through the sensor;
determining, through the microprocessor, personalization required of a computing environment of the data processing device
with respect to a user thereof based on the data related to the operating environment external to the data processing device;
and

utilizing the GPU solely to effect the personalization required of the computing environment of the data processing device
with respect to the user determined through the microprocessor to reduce power consumption through the data processing device.

US Pat. No. 9,245,371

GLOBAL STORES AND ATOMIC OPERATIONS

NVIDIA Corporation, Sant...

1. A computer-implemented method for accessing data objects stored within a buffer memory, the method comprising:
receiving a stream of one or more shading program commands via a graphics driver that executes within a central processing
unit;

executing, within a shader engine, at least one of the one or more shading program commands to generate processed data;
determining from the stream of one or more shading program commands an address generated by the graphics driver and included
in the at least one of the one or more shading program commands, wherein the address is associated with a first data object
stored within the buffer memory; and

storing, from within the shader engine, the processed data in the first data object stored within the buffer memory,
wherein the first data object has been bound to a context of an application program by the graphics driver to provide the
shader engine with access to the first data object, and the application program is associated with the stream of one or more
shading program commands.

US Pat. No. 9,153,211

METHOD AND SYSTEM FOR TRACKING ACCESSES TO VIRTUAL ADDRESSES IN GRAPHICS CONTEXTS

NVIDIA CORPORATION, Sant...

1. A computer-implemented method for tracking accesses to virtual addresses, the method comprising:
Initializing a virtual access bit buffer that includes a plurality of virtual access bits by clearing each virtual access
bit in the plurality of virtual access bits, wherein the virtual access bit buffer includes a different virtual access bit
for each virtual page residing within a virtual memory space allocated for a graphics context;

receiving a virtual address from a client conveying a memory access request associated with the graphics context;
matching a virtual page associated with the virtual address with a page table entry;
deriving a physical address from a physical page contained in the page table entry;
determining that virtual access tracking is enabled; and
setting a virtual access bit located in the virtual access bit buffer, wherein the virtual access bit corresponds to the virtual
page.

US Pat. No. 9,201,434

MULTIPHASE CURRENT-PARKING SWITCHING REGULATOR

NVIDIA Corporation, Sant...

14. A multi-phase electric power conversion device, comprising:
at least two regulator phases; and a multi-phase control unit configured to: obtain a target current;
compute a number of the regulator phases needed to provide the target current to a load based on an efficiency characteristic
of the regulator phases; and configure the regulator phases to provide the target current to the load, wherein

a first regulator phase of the regulator phases is configured to couple a first current source to the load to provide a first
portion of the target current, and

a second regulator phase couples the load to a second current source when an output voltage level at the load is less than
a minimum voltage level and decoupled the load from the second current source when the output voltage level at the load is
greater than a maximum voltage level.

US Pat. No. 9,115,721

TURBOFAN AND GRAPHICS CARD WITH THE TURBOFAN

NVIDIA Corporation, Sant...

1. A turbofan, comprising:
a turbofan assembly which admits air in an axial direction and dispenses air in a radial direction;
an inlet fan assembly disposed at an inlet of the turbofan assembly and disposed coaxially with the turbofan assembly; and
a driving means for driving the turbofan assembly and the inlet fan assembly to rotate,
wherein the turbofan assembly comprises a first annular support and first vanes disposed on the first annular support, the
first vanes extend along the axial direction of the turbofan, and the first annular support forms a space in the interior
thereof,

wherein vanes of the inlet fan assembly extend along the radial direction of the turbofan,
wherein the inlet fan assembly is disposed in the space and located at one side of the first annular support in proximity
to the inlet,

wherein a diameter of the inlet fan assembly matches with an inner diameter of the first annular support.

US Pat. No. 9,105,250

COVERAGE COMPACTION

NVIDIA CORPORATION, Sant...

1. A method for compressing graphics data, the method comprising:
at a graphics processor comprising integrated circuits and coupled to a display device, sorting a plurality of coverage masks
into an order of descending number of samples covered by the plurality of coverage masks; and

at the graphics processor, identifying a first coverage mask, wherein the first coverage mask comprises a greatest number
of covered samples; and

at the graphics processor, compacting additional coverage masks of the plurality of coverage masks in the order of descending
number of samples covered, wherein the compacting additional coverage masks comprises removing samples from a coverage mask
that are covered by any other compacted coverage mask.

US Pat. No. 9,094,676

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR APPLYING A SETTING BASED ON A DETERMINED PHASE OF A FRAME

NVIDIA Corporation, Sant...

1. A method, comprising:
determining that a display device is operating in a three-dimensional mode, wherein the display device includes a first overdrive
table associated with a first phase and a second overdrive table associated with a second phase;

determining a phase of a current frame by comparing a polarity of the current frame to a polarity of a previous frame; and
if the phase of the current frame is the first phase, then driving one or more cells of the display device based on a first
setting in the first overdrive table, or

if the phase of the current frame is the second phase, then driving the one or more cells of the display device based on a
second setting in the second overdrive table.

US Pat. No. 9,092,573

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR TESTING DEVICE PARAMETERS

NVIDIA Corporation, Sant...

1. A method, comprising:
determining a plurality of device parameters, utilizing a directed acyclic graph (DAG), wherein the plurality of parameters
includes descriptions of hardware or software installed within a device; and

testing the determined plurality of device parameters.

US Pat. No. 9,489,201

PARTITIONED REGISTER FILE

NVIDIA Corporation, Sant...

1. A system comprising:
a processing unit;
a register file coupled to the processing unit, the register file comprising at least a first memory structure and a second
memory structure, the first memory structure having a lower access energy than the second memory structure;

wherein the processing unit is configured to address the register file using a single logical namespace for both the first
memory structure and the second memory structure; and

a compiler that is configured to, at compile time:
determine a frequency of access for each value of a plurality of values in code for execution by the processing unit;
allocate a first portion of the plurality of values associated with a low frequency of access to a first portion of register
addresses in the single logical namespace for the register file; and

allocate a second portion of the plurality of values associated with a high frequency of access to a second portion of register
addresses in the single logical namespace for the register file; and

a digital logic circuit that is configured to map each register address in the first portion of register addresses in the
single logical namespace to the first memory structure and map each register address in the second portion of register addresses
in the logical namespace to the second memory structure.

US Pat. No. 9,292,414

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR DEBUGGING GRAPHICS PROGRAMS LOCALLY UTILIZING A SYSTEM WITH A SINGLE GPU

NVIDIA Corporation, Sant...

1. A method comprising:
storing an initial state of an application programming interface (API) context in a memory, wherein the initial state of the
API context corresponds to the start of a frame;

intercepting a stream of API commands associated with the frame, wherein the stream of API commands are generated by a graphics
application;

storing the intercepted stream of API commands;
transmitting the intercepted stream of API commands to a software layer that implements the API to render the frame;
initiating a replay loop to re-render the frame, including restoring a current API context to match the initial state of the
API context and transmitting the stored stream of API commands to the software layer;

during the replay loop, performing instruction stepping between breakpoints including in response to a breakpoint encountered
during the transmitting of the stored stream of API commands to the software layer;

(a) determining whether the breakpoint has already been encountered,
(b) when it is determined that the breakpoint has already been encountered,
(1) continuing the transmitting of the stored stream of API commands to the software layer until a next breakpoint is encountered
and then repeating (a), and

(c) when it is determined that the breakpoint has not already been encountered,
(1) storing a graphics processing unit (GPU) context in the memory,
(2) after storing the GPU context in the memory, continuing the transmitting of the stored stream of API commands to the software
layer until the next breakpoint is encountered and then repeating (a).

US Pat. No. 9,135,675

MULTIPLE GRAPHICS PROCESSING UNIT DISPLAY SYNCHRONIZATION SYSTEM AND METHOD

NVIDIA CORPORATION, Sant...

1. A graphics processing system comprising: a hardware component for transmitting display component information; a component
for adjusting transmission timing of display component information from a first stream of display signals and a second stream
of display signals within a synchronization tolerance, wherein said adjusting includes an adjustment to a duration of a timing
factor included in a transmission signal of said display component information; wherein a first pixel source provides said
first stream of display signals and a second pixel source provides said second stream of display signals, and wherein said
transmission timing adjustment comprises: a simulation of a generator locking (genlock) function that is performed independently
in relation to a genlock hardware component; and at least one of: sliding a timing alignment of said first pixel source to
match a timing alignment of said second pixel source; or sliding said timing alignment of said second pixel source to match
said timing alignment of said first pixel source; and a component for switching between said first stream of display signals
and said second stream of display signals upon said performance of said transmission timing adjustment; and wherein upon said
switching, an independent timing of said first pixel source and said second pixel source is restored.

US Pat. No. 9,110,809

REDUCING MEMORY TRAFFIC IN DRAM ECC MODE

NVIDIA CORPORATION, Sant...

1. A method for managing memory traffic, comprising:
causing first data to be written to a data cache memory, wherein a first write request comprises a partial write and writes
the first data to a first portion of the data cache memory;

tracking the number of partial writes in the data cache memory;
issuing a fill request for one or more partial writes in the data cache memory if the number of partial writes in the data
cache memory is greater than a predetermined first threshold.

US Pat. No. 9,087,161

ASYMMETRICAL SCALING MULTIPLE GPU GRAPHICS SYSTEM FOR IMPLEMENTING COOPERATIVE GRAPHICS INSTRUCTION EXECUTION

NVIDIA CORPORATION, Sant...

1. A multiple GPU (graphics processor unit) graphics system comprising:
a plurality of GPUs configured to execute graphics instructions from a computer system, wherein each GPU of the plurality
of GPUs comprises a plurality of graphics rendering pipelines;

a serial bus connector coupled to at least one GPU of the plurality of GPUs, wherein the serial bus connector is configured
to removeably couple the at least one GPU to the computing system, wherein the serial bus is operable to hot-plug the at least
one GPU to the computer system and enable the at least one GPU to communicate with the computer system through a serial bus;

a GPU output multiplexer; and
a controller unit coupled to the GPUs and the output multiplexer, wherein the controller unit is configured to control the
GPUs and the output multiplexer such that the GPUs cooperatively execute the graphics instructions from the computer system,
and wherein the GPUs have asymmetric graphics rendering capabilities, and wherein the controller unit is operable to allocate
a first workload to a first GPU of the plurality of GPUs and operable to allocate a second workload to a second GPU of the
plurality of GPUs, wherein the first workload is larger than the second workload, wherein the GPU output multiplexer is operable
to multiplex output from the GPUs having asymmetric graphics rendering capabilities.

US Pat. No. 9,442,755

SYSTEM AND METHOD FOR HARDWARE SCHEDULING OF INDEXED BARRIERS

NVIDIA Corporation, Sant...

1. A method comprising:
initiating execution of a plurality of threads to process instructions of a program that includes a barrier instruction;
for each thread in the plurality of threads, pausing execution of instructions when the thread reaches the barrier instruction;
determining that the barrier instruction may be scheduled for execution when either a maximum duration of time has transpired
or a minimum number of participating threads that is less than a number of threads that participate in the barrier instruction
have reached the barrier instruction;

associating a first sub-group of the threads in the plurality of threads with a first sub-barrier index;
associating a second sub-group of the threads in the plurality of threads with a second sub-barrier index; and
executing threads in the first sub-group serially and executing threads in the second sub-group serially, wherein at least
one thread in the first sub-group is executed in parallel with at least one thread in the second sub-group.

US Pat. No. 9,390,663

LIQUID CRYSTAL DISPLAY OVERDRIVE INTERPOLATION CIRCUIT AND METHOD

Nvidia Corporation, Sant...

1. A liquid crystal display overdrive interpolation circuit, comprising:
a diagonal interpolator operable to perform a diagonal interpolation along a diagonal direction in a lookup table based on
TO and FROM gray levels; and

a further interpolator coupled to said diagonal interpolator and operable to perform a further interpolation based on a result
of said diagonal interpolation and said FROM gray level.

US Pat. No. 9,329,988

PARALLEL DYNAMIC MEMORY ALLOCATION USING A NESTED HIERARCHICAL HEAP

NVIDIA Corporation, Sant...

1. A method of allocating memory from a nested hierarchical heap, the method comprising:
receiving a memory allocation request specifying an amount of memory;
identifying a heap level based on the amount of memory and a block size of a plurality of heap levels of the nested hierarchical
heap, wherein each of the plurality of heap levels of the nested hierarchical heap is associated with a different block collection
state;

computing a number of blocks needed to satisfy the memory allocation request;
determining that the number of blocks is available at the heap level by reading the block collection state associated with
the heap level, wherein each bit included in the block collection state is associated with a different block of the heap level
and indicates whether the block is available; and

allocating the number of blocks using an atomic operation.

US Pat. No. 9,293,109

TECHNIQUE FOR STORING SHARED VERTICES

NVIDIA Corporation, Sant...

1. A computer-implemented method for populating a plurality of global buffers, the method comprising:
receiving from a first processing unit data indicating a number of entries within a first local index buffer generated by
the first processing unit, wherein the first processing unit is included in a plurality of processing units; and

transmitting to the first processing unit a first base address within a global index buffer that reflects a first location
within the global index buffer where the entries within the first local index buffer should be written, wherein the first
base address within the first global index buffer is based on a number of entries within the global index buffer already allocated
to at least one other processing unit included in the plurality of processing units.

US Pat. No. 9,208,755

LOW POWER APPLICATION EXECUTION ON A DATA PROCESSING DEVICE HAVING LOW GRAPHICS ENGINE UTILIZATION

NVIDIA Corporation, Sant...

1. A method, comprising:
determining, through test instructions executing on a processor of a data processing device, utilization of a graphics engine
of the processor by an application executing on the data processing device based on initiation thereof through a driver associated
with at least one of the processor and an operating system executing on the data processing device;

detecting, through the test instructions executing on the processor, an idle state of at least one non-graphics engine of
the processor;

transitioning, through the processor, a frame buffer associated therewith into a self-refresh mode of low power utilization
thereof following determination of utilization of the graphics engine below a threshold and detection of the idle state of
the at least one non-graphics engine;

copying data related to the execution of the application to a memory of the data processing device in conjunction with the
transitioning of the frame buffer into the self-refresh mode;

clock-gating the at least one non-graphics engine following the transitioning of the frame buffer into the self-refresh mode
and copying the data related to the execution of the application to the memory to reduce a power consumption of the data processing
device; and

enabling the graphics engine to utilize the copied data in the memory for continued execution of the application on the data
processing device;

wherein when the utilization of the graphics engine exceeds the threshold, the method further comprises:
transitioning, through the processor, the frame buffer back into an active mode thereof; and
copying the data from the memory back into the frame buffer following the transitioning of the frame buffer back into the
active mode.

US Pat. No. 9,384,410

METHOD AND SYSTEM FOR IMAGE COMPRESSION WHILE ENCODING AT LEAST ONE EXTRA BIT

NVIDIA CORPORATION, Sant...

1. A method for encoding at least one extra bit in an image compression and decompression system, comprising:
accessing an input image;
compressing the input image into a compressed image using an encoder system, wherein said encoding system implements an algorithm
for encoding the input image in addition to at least one extra bit, wherein the at least one extra bit is based on a bit ordering
of a plurality values associated with the input image;

communicatively transferring the compressed image to a decoding system; and
decompressing the compressed image into a resulting uncompressed image that is unaltered from said input image, wherein the
algorithm for encoding enables the recovery of the at least one extra bit.

US Pat. No. 9,307,213

ROBUST SELECTION AND WEIGHTING FOR GRAY PATCH AUTOMATIC WHITE BALANCING

NVIDIA CORPORATION, Sant...

1. A method for calculating a white balance for an image capture device, the method comprising:
receiving a set of image data comprising a plurality of pixels;
calculating a position in a color space for each of the plurality of pixels, the color space comprising a plot of common lights;
determining a plurality of distances between the positions of the pixels in the color space and the plot of common lights;
sorting the plurality of pixels into a plurality of sample populations based on the distances;
selecting a first sample population from the plurality of sample populations by calculating an estimate of a probability density
as a function of distance from the plot of common lights for the plurality of sample populations;

averaging the distances in the first sample population to determine an initial gray point estimate; and
refining the initial gray point estimate into a final gray point estimate.

US Pat. No. 9,300,933

PREDICTIVE ENHANCEMENT OF A PORTION OF VIDEO DATA RENDERED ON A DISPLAY UNIT ASSOCIATED WITH A DATA PROCESSING DEVICE

NVIDIA Corporation, Sant...

1. A method comprising:
detecting a battery mode of operation of a data processing device;
in response to detecting the battery mode of operation of the data processing device:
(a) predicting, through a processor of the data processing device communicatively coupled to a memory, a portion of a video
frame on which a user of the data processing device is likely to focus on during rendering thereof on a display unit associated
with the data processing device, the video frame being part of decoded video data; and

(b) rendering, through the processor, the portion of the video frame on the display unit at an enhanced level compared to
other portions thereof following the prediction of the portion of the video frame;

wherein the portion of the video frame is predicted through at least one of:
the processor analyzing motion vectors associated with the video frame and determining from the analyzing that the portion
includes activity above a threshold, and

the processor analyzing audio content associated with the video frame.

US Pat. No. 9,300,261

METHOD AND APPARATUS FOR EFFICIENT LOAD BIASING

NVIDIA CORPORATION, Sant...

1. A circuit for driving a plurality of loads, said circuit comprising:
a first signal amplifier operable to supply a first content signal to a first terminal of a first load of said plurality of
loads;

a second signal amplifier operable to supply a second content signal to a second terminal of a second load of said plurality
of loads, wherein said first and second signal amplifiers are configured to operate using a first voltage difference provided
by a first power supply; and

a bias amplifier operable to bias a third terminal of said first load and a fourth terminal of said second load with a bias
signal of a bias voltage level, wherein said bias amplifier is configured to bias using a second voltage difference provided
by a second power supply that is less than said first voltage difference, wherein said second voltage difference is close
to said bias voltage level, wherein said second power supply includes at least one grounded terminal.

US Pat. No. 9,292,269

CONTROL FLOW OPTIMIZATION FOR EFFICIENT PROGRAM CODE EXECUTION ON A PROCESSOR

NVIDIA Corporation, Sant...

1. A method comprising:
identifying, based on execution of instructions through a processor communicatively coupled to a memory, a divergent region
of interest (DRI) within a control flow graph, the control flow graph being a data structure abstracting control flow behavior
of executable program code, the DRI being a region within the control flow graph not comprising a post-dominator node associated
therewith, and the DRI, when optimized, providing for reduced runtime of the executable program code compared to the DRI unoptimized;

introducing, through the execution of the instructions, a decision node in the control flow graph such that the decision node
post-dominates an entry point of the DRI and is dominated by the entry point;

redirecting, through the execution of the instructions, a regular control flow path within the control flow graph from another
node previously coupled to the DRI to the decision node;

redirecting, through the execution of the instructions, a runaway path from the another node to the decision node, the runaway
path being a control flow path that previously diverged away from the DRI instead of being coupled thereto;

marking, through the execution of the instructions, the runaway path to differentiate the runaway path from the regular control
flow path following the redirection of the regular control flow path and the runaway path to the decision node by:

implementing, through the execution of the instructions, a temporary assignment node in the runaway path;
injecting an appropriate assignment number within the temporary assignment node; and
utilizing the assignment number to differentiate between the runaway path and the regular control flow path; and
directing, through the execution of the instructions, control flow from the decision node to an originally intended destination
of each of the regular control flow path and the runaway path based on the marking to provide for program thread synchronization
and optimization within the DRI.

US Pat. No. 9,142,040

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PROCESSING GRAPHICS DATA ASSOCIATED WITH SHADING

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving a first fragment;
shading the first fragment; and
while the first fragment is being shaded:
receiving a second fragment,
determining whether at least one aspect of the second fragment conflicts with the first fragment,
if it is determined that the at least one aspect of the second fragment does not conflict with the first fragment, shading
the second fragment,

if it is determined that the at least one aspect of the second fragment conflicts with the first fragment:
storing information associated with the second fragment,
receiving a third fragment, and
shading the third fragment, if it is determined that at least one aspect of the third fragment does not conflict with the
first fragment,

wherein the shading of the third fragment is performed in association with a first warp that is associated with the shading
of the first fragment, only if coordinates associated with the third fragment fail to conflict with coordinates associated
with the first fragment.

US Pat. No. 9,118,992

PORTED ENCLOSURE AND AUTOMATED EQUALIZATION OF FREQUENCY RESPONSE IN A MICRO-SPEAKER AUDIO SYSTEM

NVIDIA Corporation, Sant...

1. A ported enclosure configured to house a micro-speaker, comprising:
an enclosure comprising a port, wherein the enclosure is tuned to a first resonance frequency that is different from a second
resonance frequency associated with the micro-speaker;

wherein the micro-speaker has a Qts that exceeds 0.5.

US Pat. No. 9,081,681

METHOD AND SYSTEM FOR IMPLEMENTING COMPRESSED NORMAL MAPS

NVIDIA CORPORATION, Sant...

1. A method for compressing normal maps in a computer system, comprising:
accessing a map of input normals, said map of input normals comprising a plurality of normal vectors on a surface of an image;
defining a memory block having a first portion and a second portion;
storing a table of indices in the first portion of the memory block; and
storing a table of normals in the second portion of the memory block, the normals in the second portion of the memory block
comprising a subset of normals out of a set of unit normals of a quantized unit sphere,

wherein the indices of the first portion of the memory block reference the normals of the second portion of the memory block,
wherein the quantized unit sphere is quantized into points and the subset of normals is derived from a subset of the points
selected to represent the map of input normals,

further wherein the subset of the normals stored in the second portion of the memory block is selected by applying a compression
algorithm to the set of unit normals of the quantized unit sphere according to a pre-defined metric for manipulating an average
value corresponding to the unit normals.

US Pat. No. 9,495,951

REAL TIME AUDIO ECHO AND BACKGROUND NOISE REDUCTION FOR A MOBILE DEVICE

Nvidia Corporation, Sant...

1. An audio enhancement system for a mobile device, comprising:
a display unit configured to exhibit a microphone signal waveform of a microphone of a mobile device having a speaker, a speaker
input waveform that is applied to the speaker, and an echo cancelling waveform of an output of an acoustic echo canceller,
wherein the microphone signal is subject to audio interference from acoustic echo feedback from the speaker and audio background
noise associated with the mobile device; and

an interference reduction unit coupled to the microphone signal and configured to provide a reduction in the audio interference,
wherein a reduced audio interference is indicated by the echo cancelling waveform in real time, wherein the interference reduction
unit includes the acoustic echo canceller coupled to an audio background noise suppressor to provide the reduced audio interference.

US Pat. No. 9,392,158

METHOD AND SYSTEM FOR INTELLIGENT DYNAMIC AUTOFOCUS SEARCH

NVIDIA CORPORATION, Sant...

1. A method of autofocusing of a camera lens, comprising:
determining an initial lens position dataset using a confidence score;
relating said initial lens position dataset to an initial sharpness score dataset to locate a focus position;
comparing a predicted sharpness score to an actual sharpness score to validate said focus position by determining a difference
between said predicted sharpness score and said actual sharpness score to determine if said difference is within a first predetermined
threshold range, wherein if said difference is within said first predetermined threshold range, said focus position is validated;

adding said actual sharpness score to said initial sharpness score dataset responsive to said difference being outside a first
predetermined threshold range; and

adjusting said camera lens to said validated focus position.

US Pat. No. 9,389,622

VOLTAGE OPTIMIZATION CIRCUIT AND MANAGING VOLTAGE MARGINS OF AN INTEGRATED CIRCUIT

Nvidia Corporation, Sant...

1. A voltage margin controller located in a voltage domain and comprising:
monitoring branches including circuit function indicators configured to indicate whether circuitry in said voltage domain
could operate at corresponding candidate reduced voltage levels; and

a voltage margin adjuster coupled to said monitoring branches and configured to develop a voltage margin adjustment for a
voltage regulator of said voltage domain based upon an operating number of said circuit function indicators, wherein said
operating number is a number of consecutive passing function indicators directly below an operating voltage provided by said
voltage regulator for said voltage domain.

US Pat. No. 9,329,984

METHODS AND SYSTEMS FOR MONITORING AND LOGGING SOFTWARE AND HARDWARE FAILURES

Nvidia Corporation, Sant...

1. A method for monitoring and logging errors over a communication network, comprising:
detecting an event caused by an error;
generating a log of the event in response to the detection;
generating a first message prompting if a user consents to allowing a third party provider track the error;
transmitting the log to the third party provider over the communication network if the user consents to allowing the third
party provider track the error; and

deleting the log if the user declines to allow the third party provider to track the error.

US Pat. No. 9,292,295

VOLTAGE DROOP REDUCTION BY DELAYED BACK-PROPAGATION OF PIPELINE READY SIGNAL

NVIDIA Corporation, Sant...

1. A method for generating flow-control signals, comprising:
generating, by a first pipeline stage, a delayed ready signal based on a downstream ready signal that is received from a second
pipeline stage and a throttle disable signal;

generating, by the first pipeline stage, a downstream valid signal based on an upstream valid signal and the delayed ready
signal; and,

generating, by the first pipeline stage, an upstream ready signal based on the delayed ready signal and the downstream valid
signal;

wherein generating the delayed ready signal comprises:
generating an internal ready signal by performing a logic OR operation between the downstream ready signal and a logical inverse
of the downstream valid signal,

generating a delayed internal ready signal based on the internal ready signal and a time delay, and
performing a logical OR operation between the delayed internal ready signal and the throttle disable signal to generate the
delayed ready signal.

US Pat. No. 9,134,979

CONVERGENCE ANALYSIS IN MULTITHREADED PROGRAMS

NVIDIA Corporation, Sant...

1. A computer-implemented method for characterizing a thread program, the method comprising:
selecting a basic block within a control flow graph corresponding to the thread program, wherein the control flow graph includes
one or more block nodes corresponding to basic blocks within the thread program;

generating a Petri net representation of the control flow graph that includes an indicator subnet corresponding to the selected
basic block;

enumerating a state space graph from the Petri net representation, wherein the state space graph includes a plurality of state
nodes corresponding to a state enumeration of the Petri net representation; and

determining whether the basic block is convergent based on the state space graph.

US Pat. No. 9,069,684

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR INVALIDATNG CACHE LINES

NVIDIA Corporation, Sant...

1. A method, comprising:
invalidating one or more cache lines that hold data from within a region of a memory address space,
wherein invalidating the one or more cache lines includes:
identifying a region register that corresponds to the region of the memory address space, and
comparing a phase field of a cache line within the cache to a phase field of the identified region register.

US Pat. No. 9,069,706

CONFIDENTIAL INFORMATION PROTECTION SYSTEM AND METHOD

NVIDIA CORPORATION, Sant...

1. A confidential information protection method comprising:
setting a permission sticky bit flag in a non-transient computer readable storage media to a default state upon system set
up;

adjusting said permission sticky bit flag access permission indication in accordance with an application instruction at system
reset;

protecting said permission sticky bit flag from adjustment in violation of said access permission indication, wherein if said
access permission indication is set to prohibit access said permission sticky bit flag can not be altered again until another
system set up or reset.

US Pat. No. 9,396,515

RENDERING USING MULTIPLE RENDER TARGET SAMPLE MASKS

NVIDIA CORPORATION, Sant...

1. A method for updating samples included in render targets, the method comprising:
receiving a first render target included in a plurality of render targets related to a first surface;
receiving a second render target included in the plurality of render targets related to the first surface;
mapping the first render target and the second render target to the same physical address space;
receiving first pixel data related to a first pixel included in the first surface;
computing a first color value based on the first pixel data;
creating a first composite mask based on a first coverage mask and a first render target sample mask, wherein the first coverage
mask is associated with the first surface, and the first render target sample mask is associated with the first render target;
and

updating a first sample included in the first render target and associated with the first pixel based on the first color value
and the first composite mask;

wherein a second sample included in the second render target stores second pixel data related to a second pixel included in
the first surface.

US Pat. No. 9,386,326

VIDEO DECODING ERROR CONCEALMENT TECHNIQUES

NVIDIA CORPORATION, Sant...

1. A method comprising:
determining an error during decoding video data;
determining a recovery point within a current frame when an error is determined;
determining a number of macroblocks to be concealed; and
concealing the determined number of macroblocks from the determined recovery point, including:
loading macroblock data into a plurality of buffers;
determining if a top neighbor macroblock and a left neighbor macroblock of a current macroblock are valid to use for concealing
the current macroblock having an error; and

concealing the current macroblock having the error based upon the available neighbor macroblocks using the data in the plurality
of buffers, wherein;

the current macroblock does not have a valid top neighbor macroblock or valid left neighbor macroblock if the current macroblock
is the first macroblock of the frame;

the current macroblock having an error is concealed with a predetermined value when the current macroblock does not have a
valid top neighbor macroblock or valid left neighbor macroblock;

the current macroblock has a valid left neighbor macroblock if the current macroblock is in the first row of the frame and
is not the first macroblock in the first row;

the current macroblock has a valid too neighbor macroblock and a valid left neighbor macroblock if the current macroblock
is not in the first row of the frame and is not the first macroblock in the row;

the current macroblock having an error is concealed using data in the top neighbor macroblock, if the current macroblock has
a valid top neighbor macroblock and not a valid left neighbor macroblock, by replicating data in a row buffer storing pixel
values from the top neighbor macroblock to fill each row of the current macroblock;

the current macroblock having an error is concealed using data in the left neighbor macroblock, if the current macroblock
has a valid left neighbor macroblock and not a valid top neighbor macroblock, by replicating data in a column buffer storing
pixel values from the right neighbor macroblock to fill each column of the current macroblock;

the current macroblock having an error is concealed using an average of a column buffer storing pixel values from the right
neighbor macroblock to fill each pixel of the current macroblock if the current macroblock has a valid left neighbor macroblock
and a valid top neighbor macroblock;

the current macroblock having an error is concealed by replicating data in a row buffer storing pixel values from the top
neighbor macroblock to fill each row of the current macroblock if the current macroblock has a valid left neighbor macroblock
and a valid top neighbor macroblock; and

the current macroblock having an error is concealed by replicating data in a column buffer storing pixel values from the left
neighbor macroblock to fill each column of the current macroblock if the current macroblock has a valid left neighbor macroblock
and a valid top neighbor macroblock.

US Pat. No. 9,304,775

DISPATCHING OF INSTRUCTIONS FOR EXECUTION BY HETEROGENEOUS PROCESSING ENGINES

NVIDIA Corporation, Sant...

1. A method for dispatching program instructions for execution in a SIMD (single-instruction multiple-data) architecture with
heterogeneous processing engines of different types, the method comprising:
loading first dispatch slots with first program instructions that are highest priority program instructions, wherein each
of the first program instructions is executable by only a specific type of the heterogeneous processing engines;

loading second dispatch slots with second program instructions that can be executed by any type of the heterogeneous processing
engines, wherein each of the second dispatch slots corresponds to a different first dispatch slot; and

for each of the first program instructions that are loaded into first dispatch slots:
determining that an execution conflict exists between the first instruction and other first program instructions, and
for each of the other first program instructions:
loading the first program instruction into the corresponding second dispatch slot and loading the second program instruction
in the corresponding second slot into the corresponding first dispatch slot.

US Pat. No. 9,293,119

METHOD AND APPARATUS FOR OPTIMIZING DISPLAY UPDATES ON AN INTERACTIVE DISPLAY DEVICE

NVIDIA CORPORATION, Sant...

1. A method for displaying input in a touch-sensitive display panel, the method comprising:
placing a display panel of a mobile computing device in a low power refresh mode;
rendering a display update in response to detecting a sensor input received in the display panel;
transmitting the display update to the display panel;
buffering the display update in a frame buffer comprised in the mobile computing device; and
interrupting a current refresh period of a timing controller of the display panel by rescanning a current frame displayed
in the display panel to include the display update from the frame buffer.

US Pat. No. 9,274,979

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR OPTIMIZING DATA ENCRYPTION AND DECRYPTION BY IMPLEMENTING ASYMMETRIC AES-CBC CHANNELS

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying, by a hardware processor of a system, data to be written to hardware memory of the system;
encrypting, by the hardware processor, the data utilizing a first number of a plurality of AES-CBC channels of the system,
to form encrypted data;

storing, by the hardware processor, the encrypted data in the hardware memory;
determining, by the hardware processor of the system, that the encrypted data is to be read from the hardware memory;
determining, by the hardware processor, a second number of the plurality of AES-CBC channels of the system to utilize to decrypt
the encrypted data, wherein the second number is different than the first number and achieves a determined performance target;

while reading the encrypted data from the hardware memory, decrypting the encrypted data utilizing the determined second number
of the plurality of AES-CBC channels to achieve the determined performance target;

wherein the performance target is a speed for the decrypting that is determined as a function of a speed of the encrypting,
such that the second number of the plurality of AES-CBC channels of the system to utilize to decrypt the encrypted data is
determined as that which achieves the determined speed for the decrypting;

wherein the speed determined for the decrypting is determined by multiplying a predefined integer by the speed of the encrypting,
the predefined integer being greater than one.

US Pat. No. 9,202,139

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR GENERATING A SUBSET OF A LOW DISCREPANCY SEQUENCE

NVIDIA Corporation, Sant...

1. A method, comprising:
identifying, by a hardware processor of a system, an image to be displayed by the system;
sampling, by the hardware processor, an image plane of the image to be displayed, where the sampling results in a low discrepancy
sequence associated with the image;

determining, by the hardware processor, a threshold value;
selecting, by the hardware processor, a single dimension of the low discrepancy sequence;
for each element included within the low discrepancy sequence, comparing, by the hardware processor, the selected single dimension
to the determined threshold value;

generating by the hardware processor a subset of the low discrepancy sequence, based on the comparing; and
determining, by the hardware processor, a plurality of light transport path segments associated with the image to be displayed,
utilizing the subset of the low discrepancy sequence.

US Pat. No. 9,159,367

AUTOMATIC PLAYBACK OF ONE OR MORE EXCERPT(S) OF A VIDEO SEQUENCE ON A DATA PROCESSING DEVICE

NVIDIA Corporation, Sant...

1. A method comprising:
initiating, through an interface of a data processing device, generation of at least one excerpt of a video sequence associated
with a video file stored in a memory of the data processing device;

automatically reading, through a processor of the data processing device communicatively coupled to the memory, video frames
of the video file corresponding to the at least one excerpt and reference video frames thereof in accordance with the initiation
through the interface; and

decoding, through the processor, the video frames of the video file corresponding to the at least one excerpt and the reference
video frames thereof following the automatic reading for rendering thereof on the data processing device, wherein the decoding
of the video frames and the reference video frames further comprises:

decoding, through the processor, each key frame of the video sequence, at least one video frame around the each key frame
of the video sequence temporally closest thereto and at least one reference video frame of the at least one video frame around
the each key frame;

decoding, through the processor, at least one another set of a decoded key frame, at least one video frame around the decoded
key frame and at least one reference video frame thereof;

skipping decoding other video frames of the video sequence; and
compositing, through the processor, the decoded each key frame, the at least one video frame around the each key frame and
the at least one reference video frame thereof with the at least one another set of the decoded key frame, the at least one
video frame around the decoded key frame and the at least one reference video frame thereof to generate highlights of the
video sequence as the at least one excerpt.

US Pat. No. 9,129,443

CACHE-EFFICIENT PROCESSOR AND METHOD OF RENDERING INDIRECT ILLUMINATION USING INTERLEAVING AND SUB-IMAGE BLUR

NVIDIA CORPORATION, Sant...

1. A processor configured to render an indirect illumination image, comprising:
a buffer restructurer configured to organize a reflective shadow map (RSM), rendered with respect to a reference view, into
a plurality of unique sub-RSMs, each having sub-RSM pixels;

an indirect illumination computer configured to employ interleaved sampling on said plurality of unique sub-RSMs to generate
a plurality of indirect illumination sub-images; and

a filter operable to smooth accumulated light values of said indirect illumination sub-images for subsequent interleaving
into said indirect illumination image, wherein said organizing said RSM into said plurality of unique sub-RSMs comprises assigning
each pixel of said RSM to a single sub-RSM so that each sub-RSM has a same resolution and number of said sub-RSM pixels as
all other sub-RSMs.

US Pat. No. 9,112,588

WI-FI TRANSCEIVER HAVING DUAL-BAND VIRTUAL CONCURRENT CONNECTION MODE AND METHOD OF OPERATION THEREOF

NVIDIA CORPORATION, Sant...

1. A transceiver, comprising:
first transmit and receive intermediate frequency (IF) strips;
second transmit and receive IF strips;
first and second local oscillators (LOs);
switches operable to multiplex clock signals from the first and second local oscillators to cause said transceiver to operate
in a selectable one of:

a unified, multiple-input, multiple-output (MIMO) mode in which said first and second transmit and receive IF strips are driven
to transmit and receive in a first band, and

a concurrent multiple-band connection mode in which said first transmit and receive IF strips are driven in said first band
and said second transmit and receive IF strips are concurrently driven in a second band; and

digital baseband circuitry coupled to said first and second transmit and receive IF strips and including a media access controller
(MAC) operable as a MIMO processor in said concurrent multiple-band connection mode.

US Pat. No. 9,093,135

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING A STORAGE ARRAY

NVIDIA Corporation, Sant...

1. A storage array, comprising:
a plurality of sub-arrays configured to provide a register for each thread of a plurality of threads, each sub-array configured
to store one bit of the register for each thread, and each sub-array comprising:

storage cells configured in an array of rows and columns, wherein each storage cell is associated with a different thread
of the plurality of threads and stores one bit of data;

a read multiplexer coupled to the storage cells and configured to output a global read bit line selected from local read bit
lines output by the storage cells;

read drivers, each read driver coupled between a read bit line precharge and one of the columns; and
write drivers, each write driver coupled between a global write bit line and one of the columns, and configured to write the
global write bit line to the storage cells for each thread of the plurality of threads.

US Pat. No. 9,087,473

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR CHANGING A DISPLAY REFRESH RATE IN AN ACTIVE PERIOD

NVIDIA Corporation, Sant...

1. A method, comprising:
receiving a request to change a display refresh rate;
determining whether a display is operating in the active period; and
in response to the request, conditionally changing the display refresh rate based on the determination by updating at least
one display timing register during an active period in which pixels are being written to a display device, wherein the changing
of the display refresh rate is delayed when it is determined that the display is not operating in the active period.

US Pat. No. 9,053,041

SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR PERFORMING GRAPH COLORING

NVIDIA Corporation, Sant...

1. A computer-implemented method, comprising:
identifying a graph with a plurality of vertices;
categorizing the plurality of vertices by:
assigning a random number to each vertex in the graph; and
comparing the assigned random number of each vertex to the assigned random numbers of each of the neighbors of the vertex,
and determining whether the assigned random number of a single vertex is greater than each of the assigned random numbers
of each of the neighbors of the single vertex and at the same time determining whether the assigned random number of a single
vertex is less than each of the assigned random numbers of each of the neighbors of the single vertex, wherein all vertices
in the graph that have an assigned random number greater than the assigned random numbers of each of their neighbors are added
to a first independent set, and all vertices in the graph that have an assigned random number less than the assigned random
numbers of each of their neighbors are added to a second independent set separate from the first independent set, wherein
the categorizing of the plurality of vertices is optimized.

US Pat. No. 9,430,242

THROTTLING INSTRUCTION ISSUE RATE BASED ON UPDATED MOVING AVERAGE TO AVOID SURGES IN DI/DT

NVIDIA Corporation, Sant...

1. A computer-implemented method for throttling an instruction issue rate of a processor, the method comprising:
receiving a plurality of instructions to be issued to one or more execution units within the processor;
dispatching a subset of instructions included in the plurality of instructions to the one or more execution units within a
first number of clock cycles during a current scheduling period, wherein the instruction issue rate during the current scheduling
period is defined by a number of clock cycles for which at least one instruction is dispatched, and wherein the instruction
issue rate during the current scheduling period is less than or equal to a throttling rate for the current scheduling period;

updating a moving average based on the instruction issue rate during the current scheduling period; and
updating a throttling rate for a next scheduling period based on the moving average.

US Pat. No. 9,412,042

INTERACTION WITH AND DISPLAY OF PHOTOGRAPHIC IMAGES IN AN IMAGE STACK

NVIDIA CORPORATION, Sant...

1. A non-transitory computer-readable storage medium having computer-executable instructions that, when executed, perform
a method comprising:
displaying, in a first display instance, a first image selected from a plurality of images stored in a memory, the plurality
of images comprising images of a scene, the plurality of images captured sequentially during a time interval at a plurality
of different values for a first attribute;

receiving information that identifies a portion of the first image comprising a first location of interest within the first
image;

identifying and selecting a second image of the plurality of images that includes a region within the second image that corresponds
to the first location of interest and that is rated highest, with respect to the first attribute, relative to other regions
in the plurality of images that also correspond to the first location of interest, wherein the second image has a first value
for the first attribute, wherein the plurality of images further comprises images of the scene captured over a plurality of
different values for a second attribute at each value of the first attribute, wherein the region is also rated highest with
respect to the second attribute relative to other regions in a subset of images of the plurality of images, the subset of
images also having the first value for the first attribute; and

displaying, in a second display instance, the second image.

US Pat. No. 9,292,065

SYSTEM AND METHOD FOR PROVIDING LOW-VOLTAGE, SELF-POWERED VOLTAGE MULTI-SENSING FEEDBACK

NVIDIA Corporation, Sant...

11. A system comprising:
a power management integrated circuit (PMIC) configured to generate a supply voltage; and
an analog multiplexor coupled to the supply voltage, the analog multiplexor including:
an n-to-1 multiplexor comprising a number of transmission gates coupled to a corresponding number of input signals, and
a bypass switch configured to short the supply voltage to an output of the analog multiplexor when the supply voltage is below
a threshold voltage,

wherein the analog multiplexor includes a plurality of p-type metal oxide semiconductor (PMOS) transistors, each PMOS transistor
having an n-type well biased by the supply voltage.

US Pat. No. 9,210,437

HARDWARE MULTI-STREAM MULTI-STANDARD VIDEO DECODER DEVICE

NVIDIA CORPORATION, Sant...

1. A hardware multi-stream multi-standard video decoder device comprising:
a command parser for accessing a plurality of video streams, for identifying a video encoding standard used for encoding video
streams of said plurality of video streams, and for interleaving portions of said plurality of video streams;

a plurality of hardware decoding blocks for performing operations associated with decoding said plurality of video streams,
wherein different subsets of said plurality of hardware decoding blocks are for decoding video streams encoded using different
video encoding standards, such that interleaved video streams are decoded by said command parser selectively activating and/or
deactivating subsets of said plurality of hardware decoding blocks upon receipt of a video stream of said plurality of video
streams during an initial stage for use in decoding said plurality of video streams responsive to said identified video encoding
standard; and

a plurality of register sets for storing parameters associated with said plurality of video streams, wherein each register
set of said plurality of register sets is associated with a respective video stream of said plurality of video streams, wherein
said plurality of video streams are concurrently decoded using said plurality of register sets, wherein said command parser
is operable to deactivate one or more hardware decoding blocks that were previously activated based on the one or more hardware
decoding blocks not being involved in decoding a portion of said plurality of video streams, and wherein said command parser
is operable to deactivate hardware decoding blocks within a stage of a multiple stage macroblock level pipeline if no data
of said plurality of video streams is received at said stage, and wherein the hardware multi-stream multi-standard video decoder
device further comprises a hardware post-processing block for post-processing a decoded video stream, wherein said command
parser is further configured to deactivate one or more of said plurality of hardware decoding blocks if a video stream of
the plurality of video streams received at said command parser is a decoded video stream such that said hardware post-processing
block performs said post-processing operation on said decoded video stream.

US Pat. No. 9,170,836

SYSTEM AND METHOD FOR RE-FACTORIZING A SQUARE MATRIX INTO LOWER AND UPPER TRIANGULAR MATRICES ON A PARALLEL PROCESSOR

NVIDIA CORPORATION, Sant...

1. A system for re-factorizing a square input matrix on a parallel processor, comprising:
a matrix generator operable to generate an intermediate matrix by embedding a permuted form of said input matrix in a zeroed-out
sparsity pattern of a combination of lower and upper triangular matrices resulting from an LU factorization of a previous
matrix having a same sparsity pattern, reordering to minimize fill-in and pivoting strategy as said input matrix; and

a re-factorizer associated with said matrix generator and operable to use parallel threads to apply an incomplete-LU factorization
with zero fill-in on said intermediate matrix.

US Pat. No. 9,153,539

GROUND-REFERENCED SINGLE-ENDED SIGNALING CONNECTED GRAPHICS PROCESSING UNIT MULTI-CHIP MODULE

NVIDIA Corporation, Sant...

1. A system, comprising:
a first processor chip configured to include a first single-ended signaling interface circuit;
a graphics processing cluster (GPC) chip that includes a multi-threaded processor core configured to execute graphics shader
programs and a second single-ended interface circuit;

a multi-chip module (MCM) package configured to include the first processor chip, the GPC chip, and an interconnect circuit,
wherein the interconnect circuit comprises a first interconnect chip and a second interconnect chip that is coupled to the
first interconnect chip and configured to transmit an access request from a second processor chip to the first interconnect
chip;

a first set of electrical traces fabricated within the MCM package and configured to couple the first single-ended signaling
interface circuit to the interconnect circuit;

a second set of electrical traces fabricated within the MCM package and configured to couple the second single-ended signaling
interface circuit to the interconnect circuit;

a memory controller chip that is configured to perform read-modify-write operations to a frame buffer memory and includes
a third single-ended signaling interface circuit, wherein the first interconnect chip is configured to transmit the access
request to the memory controller chip and the memory controller chip is configured to reply to the access request; and

a third set of electrical traces fabricated within the MCM package and configured to couple the third single-ended signaling
interface circuit to the interconnect circuit.

US Pat. No. 9,098,272

POWER MANAGEMENT USING AUTOMATIC LOAD/UNLOAD DETECTION OF DAC

NVIDIA CORPORATION, Sant...

1. An automatic load detection system comprising:
a display controller generating a control signal;
a selector operable to select pixel data or a first reference signal, wherein said selection is responsive to said control
signal, and wherein said selector is coupled to said display controller, wherein said first reference signal is operable for
load detection, wherein said control signal is raster information for a pixel being processed, wherein said raster information
provides coordinates of said pixel and wherein said first reference signal is selected when said control signal corresponds
to an non-displayed portion of a digital video frame;

a digital to analog converter (DAC) operable to receive a selection by said selector and outputs an output signal, wherein
said DAC is coupled to said selector, and wherein said output signal has a first detectable value when said first reference
signal is selected and a load is coupled to said DAC, and wherein said output signal has a second detectable value when said
first reference signal is selected and said load is uncoupled from said DAC; and

a comparator operable to compare said output signal to a second reference signal and outputting a comparison signal, wherein
said comparator is coupled to said DAC, and wherein said comparison signal has a third value when said output signal has said
first detectable value, and wherein said comparison signal has a fourth value when said output signal has said second detectable
value, and wherein said fourth value indicates that said load is uncoupled from said DAC.

US Pat. No. 9,058,677

SYSTEM AND METHOD FOR REDUCING THE COMPLEXITY OF PERFORMING BROAD-PHASE COLLISION DETECTION ON GPUS

NVIDIA CORPORATION, Sant...

1. A method for performing a collision detection analysis for a plurality of graphics objects, the method comprising:
initializing a cell identifier (ID) array that includes memory space for entries corresponding to a first bounding sphere
associated with a first graphics object and entries corresponding to a second bounding sphere associated with a second graphics
object;

generating an unsorted cell ID array that includes one or more entries corresponding to the first bounding sphere and one
or more entries corresponding to the second bounding sphere, wherein each entry in the unsorted cell ID array includes a cell
ID number and an object ID;

generating a sorted cell ID array based on the cell ID number associated with each entry in the unsorted cell ID array;
generating a collision cell list based on the sorted cell ID array;
setting a cell type to a first cell type; and
traversing the collision cell list with a plurality of threads to perform a narrow phase collision detection analysis on each
collision cell included in the collision cell list having only the first cell type.

US Pat. No. 9,507,638

COMPUTE WORK DISTRIBUTION REFERENCE COUNTERS

NVIDIA Corporation, Sant...

1. A method of allocating and releasing architectural resources in a multi-threaded system, the method comprising:
allocating the architectural resources to a first thread array including a first plurality of threads to execute a parent
processing task;

determining, by one or more threads included in the first plurality of threads and during execution of the parent processing
task, whether a release of the architectural resources is to be overridden when a first thread included in the first plurality
of threads has exited based on the existence of a child processing task generated from the parent processing task and associated
with at least one thread included in the first plurality of threads;

releasing the architectural resources when the first thread has exited and no thread included in the first plurality of threads
has determined that the release of the architectural resources is to be overridden; and

retaining the architectural resources when the first thread has exited and at least one of the one or more threads included
in the first plurality of threads has determined that the release of the architectural resources is to be overridden.

US Pat. No. 9,355,041

FRAME BUFFER ACCESS TRACKING VIA A SLIDING WINDOW IN A UNIFIED VIRTUAL MEMORY SYSTEM

NVIDIA Corporation, Sant...

1. A memory subsystem implemented in a processor, the memory subsystem comprising:
a memory management unit that includes a sliding window tracker configured to:
detect a first access operation associated with a first memory page group included within a sliding window;
set a first reference bit included in a reference vector and corresponding to the first memory page group to an active value,
wherein an inactive value of a second reference bit in the reference vector and corresponding to a second memory page group
also included in the sliding window indicates that the second memory page group has not been accessed; and

in response to the active value of the first reference bit and the inactive value of the second reference bit, cause the selection
of a memory page in the second memory page group to migrate from a second memory to a first memory.

US Pat. No. 9,081,535

AUTOMATIC TOPOLOGY CONFIGURATION THROUGH AUTOMATIC HARDWARE PROFILES ACROSS MULTIPLE DISPLAY UNITS

NVIDIA Corporation, Sant...

10. A system comprising:
a plurality of display units; and
a data processing device communicatively coupled to the plurality of display units, the data processing device configured
to:

automatically identify hardware profile data associated with the plurality of display units,
create a set of topology settings when the hardware profile data does not match a set of settings in a hardware profile lookup
table, and

automatically apply the set of topology settings to simultaneously display a sequence of graphics signals across the plurality
of display units.

US Pat. No. 9,497,631

AUTHENTICATION COMMANDS

Nvidia Corporation, Sant...

1. A modem for use at a terminal for accessing first and second communication networks, the modem comprising:
a device interface for connecting to a subscriber identity device, the subscriber identification device comprising:
computer storage storing first and second subscriber identity applications, and first and second pieces of user authentication
data, separate from one another, for effecting independent first and second user authentication procedures for the first and
second applications respectively; and

a processing unit operable to execute the first application to provide access to the first network when the first authentication
procedure has been completed, and to execute the second application to provide access to the second network when the second
authentication procedure has been completed;

wherein the modem further comprises:
a host interface for connecting to a host processor of the terminal; and
an actuation component configured responsive to an authentication command received via the host interface and having an attribute
identifying at least one of the first and second pieces of user authentication data to actuate the processing unit of the
subscriber identification device to perform an authentication task in relation to the identified user authentication data,
wherein the authentication command has a parameter identifying one of the first and second pieces of user authentication data
and has a preamble which does not identify either of the first and second pieces of user authentication data.

US Pat. No. 9,367,487

MITIGATING MAIN CROSSBAR LOAD USING DEDICATED CONNECTIONS FOR CERTAIN TRAFFIC TYPES

NVIDIA Corporation, Sant...

1. A parallel processing unit, comprising:
one or more general processing clusters (GPCs) for processing data;
a main crossbar unit configured to route data between the one or more GPCs and/or between the one or more GPCs and one or
more memory partition units;

a control crossbar unit including at least one type of dedicated connection and configured to route control information generated
by one or more control information generators within the parallel processing unit and one or more destination components within
the parallel processing unit; and

the one or more memory partition units, each memory partition unit including frame buffer logic that couples the memory partition
unit to an external memory unit and an intermediary cache unit for temporarily storing data being processed by the one or
more GPCs or data being transmitted to or from the external memory unit.

US Pat. No. 9,355,710

HYBRID APPROACH TO WRITE ASSIST FOR MEMORY ARRAY

NVIDIA CORPORATION, Sant...

1. A hybrid write-assist memory system, comprising:
an array voltage supply;
a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply
voltage coupled to the array voltage supply;

a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply
voltage during a write operation, wherein the voltage reduction of the separable cell supply voltage is provided through a
charge sharing connection with an upper metal capacitance and an upper metal coupling capacitance during an initial portion
of the write operation; and

a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently
with the voltage reduction of the separable cell supply voltage during the write operation.

US Pat. No. 9,183,607

SCOREBOARD CACHE COHERENCE IN A GRAPHICS PIPELINE

NVIDIA CORPORATION, Sant...

1. In a graphics pipeline of a graphics processor, a method for latency buffered scoreboarding, comprising:
receiving a graphics primitive for rasterization in a raster stage of a graphics processor;
rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive;
storing an ID to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted
to a subsequent stage of the graphics processor, wherein the ID is generated by a raster unit;

buffering fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage;
comparing the ID and the fragment data from the buffering;
accounting for a completion of parameter evaluation, by using a scoreboard clear packet, for each of the plurality of pixels
when the ID and the fragment data match and as the fragment data is written to a memory, wherein the scoreboard clear packet
comprises information that identifies in-flight fragments that have just been launched, and wherein the scoreboard clear packet
is an ID generated by the raster unit.

US Pat. No. 9,123,128

GRAPHICS PROCESSING UNIT EMPLOYING A STANDARD PROCESSING UNIT AND A METHOD OF CONSTRUCTING A GRAPHICS PROCESSING UNIT

Nvidia Corporation, Sant...

1. A graphics pipeline, comprising:
accelerators;
an input output interface coupled to each of said accelerators; and
a general processing unit coupled to said input output interface and configured to emulate a programmable function unit of
said graphics pipeline, said general processing unit configured to issue vector instructions via said input output interface
to vector data paths for said programmable function unit;

wherein said accelerators include said vector data paths that are external to said general processing unit.

US Pat. No. 9,389,617

PULSED CURRENT SENSING

NVIDIA Corporation, Sant...

1. A method, comprising:
configuring a current source to generate a current by alternately enabling a first switching mechanism to couple the current
source to an electric power source while disabling a second switching mechanism to decouple the current source from a current
sink and then disabling the first switching mechanism to decouple the current source from the electric power source while
enabling the second switching mechanism to couple the current source to the current sink;

generating a pulsed sense enable signal; and
sampling a sense voltage across a resistive sense mechanism according to the pulsed sense enable signal while the current
source is coupled to the electric power source, wherein the sense voltage represents a measurement of the current.

US Pat. No. 9,335,964

GRAPHICS SERVER FOR REMOTELY RENDERING A COMPOSITE IMAGE AND METHOD OF USE THEREOF

Nvidia Corporation, Sant...

1. A graphics server for remotely rendering a composite image, comprising:
a graphics renderer configured to render updates for a plurality of graphics windows within said composite image;
a display processing unit (DPU) configured to identify changed portions of said composite image, scale said changed portions
to respective coordinate systems of said plurality of graphic windows and provide said changed portions to an encoder for
encoding and subsequent transmission.

US Pat. No. 9,310,872

PROCESSOR FREQUENCY MAINLY DEPENDING ON A TARGET FRAME RATE WHILE PROCESSING A GRAPHICS APPLICATION

NVIDIA CORPORATION, Sant...

1. A variable frequency processor, comprising:
a processing core operable at a clock frequency to undertake a processing of a graphics application; and
a clock frequency controller coupled to said processing core and operable to adjust said clock frequency based on a current
frame rate of said processing, a target frame rate for said processing, a current load of said variable frequency processor,
and a target load for said variable frequency processor, said clock frequency controller configured to:

make a preliminary decision to scale down said clock frequency if said current load of said variable frequency processor is
below said target load;

make a preliminary decision to scale up said clock frequency if said current load of said variable frequency processor is
above said target load;

increase said clock frequency if said current frame rate is below said target frame rate irrespective of said preliminary
decision;

decrease said clock frequency if said current frame rate exceeds said target frame rate and said preliminary decision is to
scale down said clock frequency; and

maintain said clock frequency if said current frame rate exceeds said target frame rate and said preliminary decision is to
scale up said clock frequency.

US Pat. No. 9,292,904

VIDEO IMAGE PROCESSING WITH PARALLEL PROCESSING

NVIDIA CORPORATION, Sant...

1. A digital video signal processing system comprising:
memory;
a main processor;
a processing pipeline coupled to said main processor and said memory, wherein said processing pipeline comprises a plurality
of processing segments coupled to said a memory, wherein a respective processing segment comprises:

a stage controller configured to issue an instruction for performing a processing task on a digital video signal; and
a processing unit coupled to said stage controller and configured to perform said processing task on said digital video signal
responsive to said instruction,

wherein said stage controller is configured to perform one or more other operations in parallel with said processing unit
performing said processing task,

wherein said one or more other operations are completed at said stage controller before said processing task is completed
at said processing unit, and

wherein said processing unit is configured to send an indication to said stage controller, wherein said indication is indicative
of a completion of said processing task.

US Pat. No. 9,113,162

DYNAMIC PACKET SIZE CONTROL FOR MPEG-4 DATA PARTITION MODE

NVIDIA CORPORATION, Sant...

1. A system for performing dynamic AC prediction, said system comprising:
a processor;
a memory coupled to said processor a display coupled to said processor;
a graphics controller coupled to said processor and comprising a component for performing dynamic AC prediction, said component
comprising:

a DC prediction component coupled to said decision logic and for performing DC prediction for a current macroblock using DC
coefficients associated with at least one adjacent macroblock;

an AC prediction component for performing AC prediction for said current macroblock using AC coefficients associated with
said at least one adjacent macroblock; and

a decision logic coupled to said AC prediction component, said decision logic for determining whether an overflow condition
is to occur in a current data packet if said current macroblock is encoded in said current data packet, said decision logic
further for, if no overflow condition is to occur, maintaining said AC prediction in an enabled state and designating said
current macroblock for encoding in said current data packet wherein said graphics controller further comprises a video encoder,
said video encoder comprising a buffer, a variable-length coder, and said component; wherein said decision logic is further
operable to, before determining whether said overflow condition is to occur, determine a macroblock type of said current macroblock,
wherein said decision logic is further operable to, if said current macroblock comprises an inter block, supply said AC coefficients
and said DC coefficients to said variable-length coder for encoding said current macroblock in said current data packet, wherein
said decision logic is further operable to, if said current macroblock comprises an intra block, determine an AC prediction
mode status associated with said AC prediction, wherein said decision logic is further operable to, if said AC prediction
is disabled, supply said AC coefficients and DC predict coefficients to said variable-length coder for encoding said current
macroblock in said current data packet, and wherein said decision logic is further operable to, if said AC prediction is enabled,
supply AC predict coefficients and said DC predict coefficients to said variable-length coder for encoding said current macroblock
in said current data packet.

US Pat. No. 9,099,050

METHOD AND APPARATUS FOR DYNAMICALLY MODIFYING THE GRAPHICS CAPABILITIES OF A MOBILE DEVICE

NVIDIA Corporation, Sant...

1. A method for dynamically modifying the graphics capabilities of a mobile device, the method comprises:
abstracting the handling of a first graphics subsystem and a second graphics subsystem associated with the mobile device,
so that the first graphics subsystem and the second graphics subsystem appear as a third graphics subsystem to an operating
system for the mobile device;

detecting a configuration change event corresponding to the second graphics subsystem;
masking the configuration change event to induce the generation of a reset event; and
modifying the graphics capabilities of the mobile device to match the highest graphics capabilities between the first graphics
subsystem and the second graphics subsystem that are accessible to the mobile device.