1. A frequency synthesizer, comprising:a PLL circuit that includes a voltage control oscillator, a variable frequency divider, a phase comparator, and a loop filter, the variable frequency divider dividing a frequency signal output from the voltage control oscillator, the phase comparator extracting a phase difference between a phase of the divided frequency signal and a phase of a reference frequency signal, the loop filter supplying the voltage control oscillator with a control voltage corresponding to the phase difference;
a DDS configured to operate based on a clock signal to generate the reference frequency signal having a reference frequency, the reference frequency corresponding to a value obtained by dividing a set value of an output frequency of the frequency signal by a dividing number, the frequency signal being output from the voltage control oscillator, the dividing number being set in the variable frequency divider;
a clock signal supply unit configured to supply the clock signal to the DDS from a plurality of preliminarily prepared clock frequencies, the clock signal corresponding to a selected clock frequency;
a storage unit storing the clock frequency, the reference frequency, and a minimum dividing number in association with one another, the reference frequency is preliminarily obtained such that a frequency of a spurious component does not exist in a predetermined frequency range and the dividing number of the variable frequency divider is minimum, the spurious component being included in a used frequency band of the DDS while the DDS is operated with the clock signal having the clock frequency selected from the plurality of the clock frequencies so as to generate the reference frequency signal having the reference frequency from the DDS, and
a setting unit configured to select a combination of the clock frequency, the reference frequency, and the minimum dividing number corresponding to the set value of the output frequency so as to set the clock signal supply unit, the DDS, and the variable frequency divider, wherein
the storage unit stores the frequency of the spurious component generated due to the clock frequencies different from one another in association with the clock signal having the clock frequency where an absolute value of a difference between an upper/lower limit value of the frequency range and the frequency of an adjacent spurious component closest to the frequency range becomes maximum, the reference frequency, and the minimum dividing number while the frequency signal with the reference frequency associated with the minimum dividing number is generated by the DDS, and when the clock signal supply unit is prepared for supplying the clock signals such that the frequency of the spurious component does not exist within the predetermined frequency range and the clock frequencies are different from one another.